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#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { x = 0; char c = getchar(), f = 0; for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) f = 1; for (; c >= 0 && c <= 9 ; c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); if (f) x = -x; } const int P = 1e9 + 7; int n, D, dp[3005][3005], s[3005][3005], res; struct edge { int to, nxt; } e[3005]; int et, head[3005], iv[3005]; inline int ksm(int x, int q = P - 2) { int r = 1; for (; q; q >>= 1, x = 1ll * x * x % P) if (q & 1) r = 1ll * r * x % P; return r; } inline void adde(int x, int y) { e[++et] = (edge){y, head[x]}, head[x] = et; } inline void dfs(int x) { for (int i = 1; i <= n + 1; i++) dp[x][i] = 1; for (int i = head[x]; i; i = e[i].nxt) { dfs(e[i].to); for (int j = 1; j <= n + 1; j++) dp[x][j] = 1ll * dp[x][j] * s[e[i].to][j] % P; } for (int i = 1; i <= n + 1; i++) s[x][i] = (s[x][i - 1] + dp[x][i]) % P; } inline int inv(int x) { return x < 0 ? P - iv[-x] : iv[x]; } int main() { read(n), read(D); for (int i = 2, f; i <= n; i++) read(f), adde(f, i); iv[1] = 1; for (int i = 2; i <= n + 1; i++) iv[i] = 1ll * iv[P % i] * (P - P / i) % P; dfs(1); for (int i = 1, w = 1; i <= n + 1; (res += 1ll * w * s[1][i] % P) %= P, w = 1, i++) for (int j = 1; j <= n + 1; j++) if (i ^ j) w = 1ll * w * (D - j) % P * inv(i - j) % P; return printf( %d n , (res + P) % P), 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long in, temp = 0, t = 0; int casos; cin >> casos; for (int i = 0; i < casos; i++) { cin >> in; temp = in * (in + 1) / 2; for (long long i = 0;; i++) { if ((1 << i) > in) { break; } else { long long j = 1 << i; t = t + j; } } temp = temp - 2 * t; cout << temp << endl; t = 0; temp = 0; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int tmp = 0; tmp < t; tmp++) { unsigned long long int n, k; cin >> n >> k; if (k >= n) { cout << 1 << n ; continue; } bool fl = false; for (int i = 2; i * i <= n; i++) { if (n % i == 0 && n / i <= k) { cout << i << n ; fl = true; break; } } if (!fl) { for (int i = int(sqrt(n)); i >= 2; i--) { if (n % i == 0 && i <= k) { cout << n / i << n ; fl = true; break; } } } if (!fl) { cout << n << n ; } } }
|
`timescale 1ns / 1ps
module ControlUnit(
input [5:0] op,
input clk,
input rst,
input zero,
input sign,
output wire [2:0] state,
output ExtSel,
// PC
output [1:0] PCSrc,
output PCWre,
// ALU
output ALUSrcA,
output ALUSrcB,
output reg [2:0] ALUOp,
// Instruction Memory
output InsMemRW,
output IRWre,
// Data Memory
output mRD,
output mWR,
output DBDataSrc,
// Register File
output RegWre,
output WrRegDSrc,
output [1:0] RegDst
);
MultiState ms(
.clk(clk),
.rst(rst),
.op(op),
.state(state)
);
assign PCWre = (op != 6'B111111 && state == 3'B000 ? 1 : 0);
assign ALUSrcA = (op == 6'B011000 ? 1 : 0);
assign ALUSrcB = (op == 6'B000010 || op == 6'B010010 || op == 6'B100111
|| op == 6'B110000 || op == 6'B110001 ? 1 : 0);
assign DBDataSrc = (op == 6'B110001 ? 1 : 0);
assign RegWre = (op == 6'B110100 || op == 6'B110110 || op == 6'B111000
|| op == 6'B110000 || op == 6'B111001 || op == 6'B111111 || (state != 3'B011 && op != 6'B111010) ? 0 : 1);
assign WrRegDSrc = (op != 6'B111010 ? 1 : 0);
assign InsMemRW = 1;
assign mRD = (op == 6'B110001 && state == 3'B100 ? 1 : 0);
assign mWR = (op == 6'B110000 && state == 3'B100 ? 1 : 0);
assign IRWre = (state == 3'B000 ? 1 : 0);
assign ExtSel = (op != 6'B010010 && op != 6'B100111 ? 1 : 0);
assign PCSrc = (op == 6'B111000 || op == 6'B111010 ? 2'B11 :
(op == 6'B111001 ? 2'B10 :
((op == 6'B110100 && zero == 1) || (op == 6'B110110 && (sign == 1 && zero == 0)) ? 2'B01 :
2'B00)));
assign RegDst = (op == 6'B111010 ? 2'B00 :
(op == 6'B000010 || op == 6'B010010 || op == 6'B100111 || op == 6'B110001 ? 2'B01 : 2'B10));
always@(op or zero or sign) begin
case (op)
// add
6'B000000: ALUOp = 3'B000;
// sub
6'B000001: ALUOp = 3'B001;
// addi
6'B000010: ALUOp = 3'B000;
// or
6'B010000: ALUOp = 3'B101;
// and
6'B010001: ALUOp = 3'B110;
// ori
6'B010010: ALUOp = 3'B101;
// sll
6'B011000: ALUOp = 3'B100;
// slt
6'B100110: ALUOp = 3'B011;
// sltiu
6'B100111: ALUOp = 3'B010;
// sw
6'B110000: ALUOp = 3'B000;
// lw
6'B110001: ALUOp = 3'B000;
// beq
6'B110100: ALUOp = 3'B001;
// bltz
6'B110110: ALUOp = 3'B001;
// j
6'B111000: ALUOp = 3'Bzzz;
// jr
6'B111001: ALUOp = 3'Bzzz;
// jal
6'B111010: ALUOp = 3'Bzzz;
// halt
6'B111111: ALUOp = 3'Bzzz;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, s, x1, x2, v1, v2, w, d, ans; int main() { cin >> s >> x1 >> x2 >> v1 >> v2 >> w >> d; ans = abs(x1 - x2) * v2; if (d == 1) { if (w < x2) { if (x1 < x2) { if (x1 >= w) ans = min(ans, (x2 - w) * v1); else ans = min(ans, (2 * s + x2 - w) * v1); } else ans = min(ans, (2 * s - x2 - w) * v1); } else { if (x1 > x2) ans = min(ans, (2 * s - x2 - w) * v1); else ans = min(ans, (2 * s + x2 - w) * v1); } } else { if (w < x2) { if (x1 > x2) ans = min(ans, (2 * s - x2 + w) * v1); else ans = min(ans, (x2 + w) * v1); } else { if (x1 < x2) ans = min(ans, (x2 + w) * v1); else { if (x1 <= w) ans = min(ans, (w - x2) * v1); else ans = min(ans, (2 * s + w - x2) * v1); } } } printf( %d n , ans); return 0; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:47:33 03/21/2011
// Design Name:
// Module Name: memorias
// Project Name:
// Target Device_ns:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rom (
input wire clk,
input wire ce,
input wire [12:0] a,
input wire we,
input wire [7:0] din,
output reg [7:0] dout
);
reg [7:0] mem[0:8191];
integer i;
initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
$readmemh ("ace.hex", mem, 0);
end
always @(posedge clk) begin
dout <= mem[a];
if (we == 1'b1 && ce == 1'b1)
mem[a] <= din;
end
endmodule
module ram1k (
input wire clk,
input wire ce,
input wire [9:0] a,
input wire [7:0] din,
output reg [7:0] dout,
input wire we
);
reg [7:0] mem[0:1023];
always @(posedge clk) begin
dout <= mem[a];
if (we == 1'b1 && ce == 1'b1)
mem[a] <= din;
end
endmodule
module ram1k_dualport(
input wire clk,
input wire ce,
input wire [9:0] a1,
input wire [9:0] a2,
input wire [7:0] din,
output reg [7:0] dout1,
output reg [7:0] dout2,
input wire we
);
reg [7:0] mem[0:1023];
always @(posedge clk) begin
dout2 <= mem[a2];
dout1 <= mem[a1];
if (we == 1'b1 && ce == 1'b1)
mem[a1] <= din;
end
endmodule
module ram16k (
input wire clk,
input wire ce,
input wire [13:0] a,
input wire [7:0] din,
output reg [7:0] dout,
input wire we
);
reg [7:0] mem[0:16383];
always @(posedge clk) begin
dout <= mem[a];
if (we == 1'b1 && ce == 1'b1)
mem[a] <= din;
end
endmodule
module ram32k (
input wire clk,
input wire ce,
input wire [14:0] a,
input wire [7:0] din,
output reg [7:0] dout,
input wire we
);
reg [7:0] mem[0:32767];
always @(posedge clk) begin
dout <= mem[a];
if (we == 1'b1 && ce == 1'b1)
mem[a] <= din;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void checkmax(T &t, T x) { if (x > t) t = x; } template <class T> void checkmin(T &t, T x) { if (x < t) t = x; } template <class T> void _checkmax(T &t, T x) { if (t == -1 || x > t) t = x; } template <class T> void _checkmin(T &t, T x) { if (t == -1 || x < t) t = x; } int main() { int n, num, flag; double dou, sum, sub; while (cin >> n) { sum = num = flag = 0; for (int i = 0; i < (2 * n); ++i) { scanf( %lf , &dou); sub = ceil(dou) - dou; sum += sub; if (sub < 10e-4 && sub > -10e-4) num++; } sum -= n - num; if (num == 0) printf( %.3lf n , fabs(sum)); else { for (int i = 0; i < (num); ++i) { if (fabs(sum) > fabs(sum - 1)) sum = sum - 1; else { printf( %.3lf n , fabs(sum)); flag = 1; break; } } if (!flag) printf( %.3lf n , fabs(sum)); } } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:23:35 04/24/2015
// Design Name: ADD
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_add.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ADD
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_add;
// Inputs
reg [15:0] a;
reg [15:0] b;
// Outputs
wire [15:0] sum;
wire overflow;
wire carry;
// Instantiate the Unit Under Test (UUT)
ADD uut (
.a(a),
.b(b),
.sum(sum),
.overflow(overflow),
.carry(carry)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
//#100;
check_fa(16'h0002, 16'h0004, 16'h0006, 0, 0);
check_fa(16'h4000, 16'h4000, 16'h8000, 1, 0);
check_fa(16'hc000, 16'h4000, 16'h0000, 0, 1);
check_fa(16'h8000, 16'h8000, 16'h0000, 1, 1);
end
task check_fa;
input [15:0] i_a;
input [15:0] i_b;
input [15:0] exp_s;
input exp_v;
input exp_c;
begin
a = i_a; b = i_b;
#1;
if ((sum !== exp_s) || (carry !== exp_c) || (overflow !== exp_v)) begin
$display("Error @%dns S=%b, eS=%b | C=%b, eC=%b | V=%b, eV=%b", $time, sum, exp_s, carry, exp_c, overflow, exp_v);
end
$display ("======================");
end
endtask
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:57:36 02/22/2015
// Design Name: decodeFSM
// Module Name: C:/Users/ChrisP/Documents/RL02Controller/RL02Controller/decodeFSM_tb.v
// Project Name: RL02Controller
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: decodeFSM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decodeFSM_tb;
// Inputs
reg clk;
reg rst;
reg sectorPulse;
reg currentRealBit;
reg currentRealBitValid;
// Outputs
wire [15:0] bitOut;
wire bitOutReady;
wire headerOut;
wire headerOutStrobe;
wire [2:0] decode_state;
wire [5:0] sectorNum;
wire sectorNumReady;
wire headNum;
wire headNumReady;
wire [8:0] cylNum;
wire cylNumReady;
wire crcInvalid;
wire SPI_FIFOAcceptingData;
reg readBack;
// Instantiate the Unit Under Test (UUT)
decodeFSM uut (
.clk(clk),
.rst(rst),
.currentRealBit(currentRealBit),
.currentRealBitValid(currentRealBitValid),
.sectorPulse(sectorPulse),
.wordOut(bitOut),
.wordOutReady(bitOutReady),
.headerOut(headerOut),
.headerOutStrobe(headerOutStrobe),
.decode_state(decode_state),
.prog_empty(SPI_FIFOAcceptingData)
);
headerDecode HDR (
.clk(clk),
.rst(rst),
.headerBitIn(headerOut),
.headerBitInStrobe(headerOutStrobe),
.decode_state(decode_state),
.sectorNum(sectorNum),
.sectorNumReady(sectorNumReady),
.headNum(headNum),
.headNumReady(headNumReady),
.cylNum(cylNum),
.cylNumReady(cylNumReady),
.crcInvalid(crcInvalid)
);
initial begin
// Initialize Inputs
clk = 0;
currentRealBit = 0;
currentRealBitValid = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 1;
sectorPulse = 1;
toggle_clk;
rst = 0;
zero;
sectorPulse = 0;
repeat (46) begin //Preamble
zero;
end
one; //Sync Bit
zero;//Sector
zero;
one;
zero;
zero;
one;
zero;//head
zero;//Cyninder
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
repeat (16) begin
zero;//Reserved word
end
zero;//CRC-16 of previous 2 words
one;
zero;
one;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
one;
one;
one;
one;
//postamble
repeat (16) begin
zero;
end
one; //random glitch (to be expected between post and pre-ambles
//data preamble
repeat (46) begin
zero;
end
one;//sync
readBack = 1;
repeat (100) begin
toggle_clk;
end
readBack = 0;
//data;
repeat (1024) begin
one;
zero;
end
repeat (16) begin //Data CRC
one; //TODO figure out what CRC is required (although the FPGA shouldn't care at all)
end
//postamble
repeat (16) begin
zero;
end
one;//Random glitches from previous records (as observed on disk, should be ignored)
zero;
zero;
one;
one;
one;
one;
one;
zero;
sectorPulse = 1;
repeat (24) begin//Let the sector pulse sit for a while
toggle_clk;
end;
repeat (10) begin //There are some drive utilized things that fly by during the sector pulse
one;
zero;
end
sectorPulse = 0;
repeat (46) begin //Preamble
zero;
end
one; //Sync Bit
zero;
zero;
end
task one;
begin
currentRealBit = 1;
currentRealBitValid = 1;
#10 clk = ~clk;
#10 clk = ~clk;
currentRealBitValid = 0;
toggle_clk;
end
endtask
task zero;
begin
currentRealBit = 0;
currentRealBitValid = 1;
#10 clk = ~clk;
#10 clk = ~clk;
currentRealBitValid = 0;
toggle_clk;
end
endtask
task toggle_clk;
begin
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
end
endtask
endmodule
|
// MBT 5-1-2017
//
// fast version of the gateway reset sequence
//
// this version assumes that all channels work
// and is just for gatelevel simulation.
//
`include "bsg_defines.v"
module bsg_source_sync_channel_control_master_master
#(parameter `BSG_INV_PARAM( link_channels_p )
, parameter `BSG_INV_PARAM(tests_p )
, parameter `BSG_INV_PARAM(prepare_cycles_p ) // ignored
, parameter `BSG_INV_PARAM(timeout_cycles_p )) // ignored
(input clk_i // from io_master_clk_i
, input reset_i // from im_reset_i
// we should begin the calibration stuff
, input start_i
// from masters, signals that that channel thinks it is done with the test
, input [tests_p+1-1:0][link_channels_p-1:0] test_scoreboard_i
, output [$clog2(tests_p+1)-1:0] test_index_r_o
// simultaneously a reset signal and a signal to the masters
, output prepare_o
, output done_o // we are done with all of this calibration stuff.
);
logic done_r, done_n;
logic [$clog2(tests_p+1)-1:0] test_index_n, test_index_r;
assign test_index_r_o = test_index_r;
logic started_r;
always_ff @(posedge clk_i)
if (reset_i)
started_r <= 0;
else
started_r <= started_r | start_i;
// we assert reset on states that end in 0
assign prepare_o = ~(test_index_r[0]) & started_r & ~done_r;
always_ff @(posedge clk_i)
begin
if (reset_i)
test_index_r <= 0;
else
test_index_r <= test_index_n;
end
assign done_o = done_r;
always @(posedge clk_i)
if (reset_i)
done_r <= 0;
else
done_r <= done_n;
always_comb
begin
done_n = done_r;
if (&test_scoreboard_i[tests_p])
done_n = 1'b1;
end
// move to the next test if everybody is happy
always_comb
begin
test_index_n = test_index_r;
if (!done_r & started_r & (&test_scoreboard_i[test_index_r]))
test_index_n = test_index_r+1;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_source_sync_channel_control_master_master)
|
module ARM_CU_ALU_TestBench3;
parameter sim_time = 750*2; // Num of Cycles * 2
reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;
//module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, output MEMADD, MFA,READ_WRITE,WORD_BYTE);
ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);
initial fork
Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
#1 Reset = 0;
join
always@(posedge MFA)begin
case(MEMADD)
8'h00:begin
#1 MEMDAT = 32'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h01:begin
#1 MEMDAT = 32'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h02:begin
#1 MEMDAT = 32'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h03:begin
#1 MEMDAT = 32'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h04:begin
#1 MEMDAT = 32'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h05:begin
#1 MEMDAT = 32'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h06:begin
#1 MEMDAT = 32'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h07:begin
#1 MEMDAT = 32'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h08:begin
#1 MEMDAT = 32'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h09:begin
#1 MEMDAT = 32'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h0A:begin
#1 MEMDAT = 32'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h0B:begin
#1 MEMDAT = 32'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
default:begin
#1 MEMDAT = 32'h00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
endcase
end
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench3.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench3);
$display(" Test Results" );
$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end
endmodule
//iverilog ARM_ALU.v ARM_CU_ALU.v BarrelShifter.v Buffer32_32.v controlunit4.v Decoder4x16.v Multiplexer2x1_32b.v Register.v Register2.v RegisterFile.v Register2Buff.v ARM_CU_ALU_TestBench3.v
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
module testbench;
parameter NO_OF_MSGS=128, MSG_WIDTH=4, B=3, PATTERN_WIDTH=74, SIGN_DEPTH=128,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),DATA_WIDTH=MSG_WIDTH*NO_OF_MSGS,
NOS_SHIFTER=2*NO_OF_MSGS, POINTER_WIDTH=$clog2(NOS_SHIFTER), NOS_KEY=4, NOS_CMPS=SIGN_DEPTH/NOS_KEY,NOS_STGS=$clog2(SIGN_DEPTH/NOS_KEY),SFT_DEL_WDH=$clog2(NOS_STGS+NOS_KEY+2),MAX_PAT_SZ=78;
localparam clk_prd = 2, nos_inputs=80;
reg clk;
reg reset;
reg datInReady;
reg [DATA_WIDTH-1:0] DataIn;
wire getDATA;
wire [NOS_STGS:1] fullCompare;
wire [POINTER_WIDTH-1:0] shift_pnt;
wire [6:0]dout;
reg [DATA_WIDTH-1:0] ram [nos_inputs-1:0];
integer i=0;
Wu_Manber_shiftPE #(NO_OF_MSGS,MSG_WIDTH,B,PATTERN_WIDTH, SIGN_DEPTH,SHIFT_WIDTH,DATA_WIDTH,NOS_SHIFTER,POINTER_WIDTH,NOS_KEY,NOS_CMPS,NOS_STGS,SFT_DEL_WDH,MAX_PAT_SZ)
uut (.clk(clk),
.reset(reset),
.datInReady(datInReady),
.DataIn(DataIn),
.getDATA(getDATA),
.fullCompare(fullCompare),
.shift_pnt(shift_pnt),
.dout(dout)
);
initial begin
$readmemh("/home/ashikpoojari/Desktop/xilinx_codes/codes100/input.txt", ram); // memory_list is memory file
end
initial begin
clk <= 1'b1;
reset <= 1'b0;
datInReady <= 1'b0;
#(2*clk_prd) reset <= 1'b1;
#(4*clk_prd) reset <= 1'b0;
#(5*clk_prd) datInReady <= 1'b1;
#(1*clk_prd) datInReady <= 1'b0;
end
always
#(clk_prd/2) clk <= ~clk;
always@(getDATA)begin
if(getDATA)begin
DataIn=ram[i];
i=i+1;
end
end
endmodule
|
# include <bits/stdc++.h> # define sz(x) (int)x.size() # define f first # define s second using namespace std; using ll = long long; void solve() { int n, a, b; cin >> n >> a >> b; int x, y; cin >> x >> y; int c = n - max(a, b) + abs(a - b) / 2; int d = min(a, b) + abs(a - b) / 2; if (d >= x && c >= y) cout << YES n ; else cout << NO n ; } int main(){ ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) solve(); }
|
#include <bits/stdc++.h> int main() { int tcase; for (scanf( %d , &tcase); tcase--;) { long long l, r; scanf( %lld%lld , &l, &r); if (l == r) { printf( %lld n , r); continue; } int p = 63 - __builtin_clzll(l ^ r); long long temp = 0; for (int i = 63; i > p; --i) if (l >> i & 1) temp |= 1LL << i; long long a = (1LL << p) - 1, b = (1LL << (p + 1)) - 1; a |= temp, b |= temp; if (l <= b && b <= r) a = b; printf( %lld n , a); } return 0; }
|
#include <bits/stdc++.h> int main() { char str[5010]; memset(str, 0, sizeof(str)); scanf( %s , str); int n; n = strlen(str); int res = 0; for (int i = 0; i < n; i++) { int l = 0, sum = 0; for (int j = i; j < n; j++) { if (str[j] == ( ) l++; else if (str[j] == ) ) l--; else l--, sum++; if (!l) res++; if (l < 0 && sum > 0) { l += 2; sum--; } else if (l < 0 && sum <= 0) { break; } } } printf( %d n , res); }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e12; const int maxn = 2e5 + 30; int n; long long dp[maxn][2], val[maxn], h[maxn], ans; vector<int> G[maxn]; void Min(long long &x, long long y) { if (x > y) x = y; } void dfs(int u, int fa) { for (auto v : G[u]) { if (v == fa) continue; dfs(v, u); } long long s = 0; vector<long long> r, sum; r.clear(); for (auto v : G[u]) { if (v == fa) continue; s += dp[v][0]; r.push_back(dp[v][1] - dp[v][0]); } sort(r.begin(), r.end()); int m = r.size(); sum.resize(m + 1); sum[0] = 0; for (int i = 0; i < m; i++) sum[i + 1] = sum[i] + r[i]; if (!fa) { dp[u][0] = inf; for (int i = 0; i <= m; i++) Min(dp[u][0], s + sum[i] + val[u] * abs((m - i) - i)); } else { dp[u][0] = inf; dp[u][1] = inf; for (int i = 0; i <= m; i++) { Min(dp[u][0], s + sum[i] + val[u] * abs((m - i) - (i + 1))); Min(dp[u][1], s + sum[i] + val[u] * abs((m - i + 1) - i)); } if (h[u] < h[fa]) dp[u][0] = inf; if (h[u] > h[fa]) dp[u][1] = inf; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld , &val[i]); for (int i = 1; i <= n; i++) scanf( %lld , &h[i]); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); ans += val[u] + val[v]; } dfs(1, 0); cout << (ans + dp[1][0]) / 2 << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS_DIFF_OUT_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS_DIFF_OUT_INTERMDISABLE (O, OB, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, TM, TS);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
inout IO;
inout IOB;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
input TM;
input TS;
// define constants
localparam MODULE_NAME = "IOBUFDS_DIFF_OUT_INTERMDISABLE";
wire t1, t2,out_val,out_b_val;
wire T_OR_IBUFDISABLE_1;
wire T_OR_IBUFDISABLE_2;
reg DQS_BIAS_BINARY = 1'b0;
tri0 GTS = glbl.GTS;
or O1 (t1, GTS, TM);
bufif0 B1 (IO, I, t1);
or O2 (t2, GTS, TS);
notif0 N2 (IOB, I, t2);
reg O_int, OB_int;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IOBUFDS_DIFF_OUT_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
#1 $finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2")) begin
$display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
#1 $finish;
end
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
assign out_b_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
assign out_b_val = 1'bx;
end
default : begin
assign out_val = 1'b0;
assign out_b_val = 1'b0;
end
endcase
endgenerate
always @(IO or IOB or DQS_BIAS_BINARY) begin
if (IO == 1'b1 && IOB == 1'b0) begin
O_int <= IO;
OB_int <= ~IO;
end
else if (IO == 1'b0 && IOB == 1'b1) begin
O_int <= IO;
OB_int <= ~IO;
end
else if ((IO === 1'bz || IO == 1'b0) && (IOB === 1'bz || IOB == 1'b1)) begin
if (DQS_BIAS_BINARY == 1'b1) begin
O_int <= 1'b0;
OB_int <= 1'b1;
end else begin
O_int <= 1'bx;
OB_int <= 1'bx;
end
end
else begin
O_int <= 1'bx;
OB_int <= 1'bx;
end
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE_1 = ~TM || IBUFDISABLE;
assign T_OR_IBUFDISABLE_2 = ~TS || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE_1 == 1'b1) ? out_val : (T_OR_IBUFDISABLE_1 == 1'b0) ? O_int : 1'bx;
assign OB = (T_OR_IBUFDISABLE_2 == 1'b1) ? out_b_val : (T_OR_IBUFDISABLE_2 == 1'b0) ? OB_int : 1'bx;
end
"FALSE" : begin
assign O = O_int;
assign OB = OB_int;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => OB) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => OB) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => IOB) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => OB) = (0:0:0, 0:0:0);
(INTERMDISABLE => IO) = (0:0:0, 0:0:0);
(INTERMDISABLE => IOB) = (0:0:0, 0:0:0);
(TM => O) = (0:0:0, 0:0:0);
(TM => OB) = (0:0:0, 0:0:0);
(TM => IO) = (0:0:0, 0:0:0);
(TM => IOB) = (0:0:0, 0:0:0);
(TS => O) = (0:0:0, 0:0:0);
(TS => OB) = (0:0:0, 0:0:0);
(TS => IO) = (0:0:0, 0:0:0);
(TS => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
#include <bits/stdc++.h> const long long int MOD = 1e9 + 7; const long long int INF = 1011111111; const long long int LLINF = 1000111000111000111LL; const long double EPS = 1e-10; const long double PI = 3.14159265358979323; using namespace std; long long int power(int x, int n) { if (n == 0) return 1; else if (n % 2 == 0) return power((x * x), n / 2); else return x * power((x * x), (n - 1) / 2); } long long int dp[5005][5005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, m, i, j, k; cin >> n >> k; vector<long long int> v(n); for (i = 0; i < n; i++) cin >> v[i]; sort(v.begin(), v.end()); vector<pair<pair<long long int, long long int>, long long int> > check; vector<long long int>::iterator it; for (i = 0; i < n; i++) { long long int idx; it = upper_bound(v.begin(), v.end(), v[i] + 5); if (it == v.end()) idx = n - 1; else { idx = it - v.begin(); idx--; } check.push_back({{i, idx}, idx - i + 1}); } long long int ans = 0; for (i = 0; i < n; i++) { for (j = 0; j <= k; j++) { dp[i + 1][j] = max(dp[i + 1][j], dp[i][j]); if (j + 1 <= k) dp[i + check[i].second][j + 1] = max(dp[i + check[i].second][j + 1], dp[i][j] + check[i].second); } } cout << dp[n][k]; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* Testbench for the non-synthesizable behavioral model for the
* instruction memory
*/
// Import the modules that will be tested for in this testbench
`include "instrmem.v"
// IMPORTANT: To run this, try: ncverilog -f instrmem.f +gui
module tb_instrmem ();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the instruction memory
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// instr output signals
wire [0:31] instruction;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// enb;
reg enable;
// instr_addr
reg [0:127] instruction_address;
reg [0:31] counter;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 6'd32;
parameter size_of_input2 = 4'd8;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
// always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 10ns <==> 100 MHz clock
*/
// #5 clock = 0;
// #5 clock = 1;
// end
// ============================================================
/**
* Instantiate an instance of instr_mem() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "im"
*/
instr_mem im (
// instance_name(signal name),
// Signal name can be the same as the instance name
instruction_address,instruction,enable);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
instruction_address=32'd10;
enable=1'd0;
counter=32'd0;
#30
instruction_address=32'd0;
enable=1'd1;
//counter=32'd0;
#30
instruction_address=32'd1;
enable=1'd1;
#30
instruction_address=32'd2;
enable=1'd1;
#30
instruction_address=32'd3;
enable=1'd1;
/*
instruction_address=8'd200;
reset=1'b0;
*/
// Try reading the instruction memory without being reset
for(count=0;count<=size_of_input2;count=count+1)
begin
#10
// Randomly set the instruction address to a value
instruction_address=counter;
// Reset the instruction memory
enable=1'b1;
counter=counter+3'd1;
end
// Reset the instruction memory
#10
instruction_address=8'd180;
enable=1'b0;
// Read the instruction memory after being reset
for(count=0;count<=size_of_input;count=count+1)
begin
#10
// Randomly set the instruction address to a value
instruction_address=counter;
// Reset the instruction memory
enable=1'b1;
counter=counter+3'd1;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
// bsg_mesosync_link is the designed IO in bsg group that devides
// the core's clock to a slower clock for IO based on the configuration
// it receives. For each input data line it can choose between the clock
// edge and which cycle in the divided clock to take the sameple, based on
// the bit_cfg_i configuration.
//
// It has four phases to be calibrated. After reset, it would send out a
// known pattern so the other side (master) can bit-allign its input. Next
// it would send all possible transitions of data using two counters to make
// sure the output channel is reliable.
//
// To find out the proper values for bit configuration, it has a logic
// analzers which would sample input singal on both positive and negative
// edges of the clock. Master chooses a line at a time and sends known
// patterns to it and read the logic analyzer's data to find out the delays
// of each line and find the proper line configurations. Finally, a loopback
// mode is enabled and it sends out the input data to its output for final check.
//
// There is no handshake protocol on the pins side, but from channel to core
// there is valid-and-ready handshake protocol. It must be connected to a
// valid-and-credit protocol based module on the connected chip. It uses
// a FIFO and credit counter to convert from valid-only to valid-and-credit
// and to valid-and-ready in next step.
//
// It includes 3 main modules, bsg_mesosync_input must be close to input pins,
// bsg_mesosync_output must be close to output pins and bsg_mesosync_loopback
// must be close and next to bsg_mesosync_output. Connection between input
// and output module and input and loopback module are distance safe, using
// bsg_fifo_relay. Moreover, connection between core and loopback module is
// distance safe as well.
//
// Most important feature of this IO is least latency.
`include "bsg_defines.v"
`ifndef DEFINITIONS_V
`include "definitions.v"
`endif
module bsg_mesosync_link
#( parameter `BSG_INV_PARAM(ch1_width_p ) //3
, parameter `BSG_INV_PARAM(ch2_width_p ) //3
, parameter `BSG_INV_PARAM(LA_els_p ) //64
, parameter `BSG_INV_PARAM(cfg_tag_base_id_p ) //10
, parameter `BSG_INV_PARAM(loopback_els_p ) //16
, parameter `BSG_INV_PARAM(credit_initial_p ) //8
, parameter `BSG_INV_PARAM(credit_max_val_p ) //12
, parameter `BSG_INV_PARAM(decimation_p ) //4
, parameter width_lp = ch1_width_p + ch2_width_p
)
( input clk
, input reset
, input config_s config_i
// Signals with their acknowledge
, input [width_lp-1:0] pins_i
, output logic [width_lp-1:0] pins_o
// connection to core, 2 bits are used for handshake
, input [width_lp-3:0] data_i
, input v_i
, output logic ready_o
, output v_o
, output [width_lp-3:0] data_o
, input ready_i
);
// internal singals
logic channel_reset;
logic loopback_en;
logic ready, valid;
logic [width_lp-1:0] from_meso_input;
logic [width_lp-1:0] to_meso_output;
logic logic_analyzer_data, ready_to_LA, LA_valid;
// relay nodes
config_s relay_out;
relay_node input_relay_1(.config_i(config_i),
.config_o(relay_out));
// Mesosynchronous channel
bsg_mesosync_input
#( .ch1_width_p(ch1_width_p)
, .ch2_width_p(ch2_width_p)
, .LA_els_p(LA_els_p)
, .cfg_tag_base_id_p(cfg_tag_base_id_p)
) mesosync_input
( .clk(clk)
, .reset(reset)
, .config_i(relay_out)
// Sinals with their acknowledge
, .pins_i(pins_i)
, .data_o(from_meso_input)
, .valid_o(valid)
// Logic analyzer signals for mesosync_output module
, .LA_data_o(logic_analyzer_data)
, .LA_valid_o(LA_valid)
, .ready_to_LA_i(ready_to_LA)
);
bsg_mesosync_output
#( .width_p(width_lp)
, .cfg_tag_base_id_p(cfg_tag_base_id_p)
) mesosync_output
( .clk(clk)
, .reset(reset)
, .config_i(relay_out)
// Sinals with their acknowledge
, .data_i(to_meso_output)
, .ready_o(ready)
, .pins_o(pins_o)
// Logic analyzer signals for mesosync_input module
, .LA_data_i(logic_analyzer_data)
, .LA_valid_i(LA_valid)
, .ready_to_LA_o(ready_to_LA)
// loopback signals
, .loopback_en_o(loopback_en)
, .channel_reset_o(channel_reset)
);
// loop back module with mode and line_ready inputs, and valid-and-credit
// protocol on both directions to meso-channel , and valid-and-ready protocol
// on both directions to core
bsg_mesosync_core #( .width_p(width_lp-2)
, .els_p(loopback_els_p)
, .credit_initial_p(credit_initial_p)
, .credit_max_val_p(credit_max_val_p)
, .decimation_p(decimation_p)
) mesosync_core
( .clk_i(clk)
, .reset_i(channel_reset)
, .loopback_en_i(loopback_en)
, .line_ready_i(ready)
// Connection to mesosync_link
, .meso_data_i(from_meso_input[width_lp-1:2])
, .meso_v_i(valid & from_meso_input[0])
, .meso_token_o(to_meso_output[1])
, .meso_v_o(to_meso_output[0])
, .meso_data_o(to_meso_output[width_lp-1:2])
, .meso_token_i(valid & from_meso_input[1])
// connection to core
, .data_i(data_i)
, .v_i(v_i)
, .ready_o(ready_o)
, .v_o(v_o)
, .data_o(data_o)
, .ready_i(ready_i)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_mesosync_link)
|
#include <bits/stdc++.h> using namespace std; int n, k; int fr[200002]; int arr[200002]; bool check(int cati) { int qq = 0; for (int i = 1; i <= 200000; ++i) qq += fr[i] / cati; if (qq >= k) return 1; return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> k; for (int i = 1; i <= n; ++i) cin >> arr[i], fr[arr[i]]++; int b = 1; int e = n; int ans = 1; while (b <= e) { int mid = (b + e) / 2; if (check(mid)) ans = mid, b = mid + 1; else e = mid - 1; } int qa = 0; for (int i = 1; i <= 200000; ++i) { if (qa == k) return 0; while (fr[i] >= ans && qa < k) cout << i << , ++qa, fr[i] -= ans; } return 0; }
|
//wb_tx1_ddr3.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_tx1_ddr3
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2016/06/21
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
module wb_tx1_ddr3 (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
localparam ADDR_0 = 32'h00000000;
localparam ADDR_1 = 32'h00000001;
localparam ADDR_2 = 32'h00000002;
//Local Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_0: begin
//writing something to address 0
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_1: begin
//writing something to address 1
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_2: begin
//writing something to address 3
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
ADDR_0: begin
//reading something from address 0
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_0);
o_wbs_dat <= ADDR_0;
end
ADDR_1: begin
//reading something from address 1
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_1);
o_wbs_dat <= ADDR_1;
end
ADDR_2: begin
//reading soething from address 2
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_2);
o_wbs_dat <= ADDR_2;
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:11:59 11/11/2015
// Design Name:
// Module Name: LEDWorm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LEDWorm (clk1, clk2, clk3, SSLED, LEDSEL, inClk, buttonA, buttonB, reset);
input inClk, buttonA, buttonB, reset;
output clk1, clk2, clk3;
output [3:0] LEDSEL;
output [6:0] SSLED;
reg [2:0] clockSelect;
wire rotClk, I1, I2, I3;
clockGen_50MHz_to_3Hz prescale_1 (clk1, inClk); // clk1 --> 3Hz
clockGen_divBy2 prescale_2 (clk2, clk1); // clk2 --> 3Hz / 2 = 1.5Hz
clockGen_divBy4 prescale_3 (clk3, clk1); // clk3 --> 3Hz / 4 = 0.75Hz
LEDRotator L1 (SSLED, LEDSEL, rotClk, reset); // Keeps rotating SSLED @rotClk
// Clock Selection Logic
and sel_1 (I1, clk1, clockSelect[2]);
and sel_2 (I2, clk2, clockSelect[1]);
and sel_3 (I3, clk3, clockSelect[0]);
or sel_4 (rotClk, I1, I2, I3);
// Input Signal Handling Logic
always @(posedge buttonA or posedge buttonB or posedge reset) begin
if (reset) begin
clockSelect = 3'b100; // Choose 3Hz Clock on Reset
end else
if (buttonA) begin
// Shift clockwise in set {clk1, clk2, clk3}
case (clockSelect)
3'b100: clockSelect = 3'b010; // clk1 --> clk2
3'b010: clockSelect = 3'b001; // clk2 --> clk3
3'b001: clockSelect = 3'b100; // clk3 --> clk1
default: clockSelect = 3'b100; // Any arbitrary selection goes to a valid selection
endcase
end
else begin
// Shift counter-clockwise in set {clk1, clk2, clk3}
case (clockSelect)
3'b100: clockSelect = 3'b001; // clk1 --> clk3
3'b001: clockSelect = 3'b010; // clk3 --> clk2
3'b010: clockSelect = 3'b100; // clk2 --> clk1
default: clockSelect = 3'b100; // Any arbitrary selection goes to a valid selection
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:05:56 10/30/2014
// Design Name:
// Module Name: RegistroLoad
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RegistroCargaInterfaz #(parameter Width = 32)
(CLK,Reset,ResetStart,InDatoMemoria,Write,Address,
Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,
Coeff06,Coeff07,Coeff08,Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,
Coeff19,Offset,InDato,Start);
genvar i;
input CLK,Write,Reset,ResetStart;
input signed [Width-1:0] InDatoMemoria;
input [8:0] Address;
wire [21:0] EnableRegister ;
output Start;
wire EnableStart;
wire [Width-1:0] OutRegisterStart;
output signed [Width-1:0] Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,
Coeff06,Coeff07,Coeff08,Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,
Coeff19,Offset,InDato;
wire signed [Width-1:0] Aux [21:0]; //*********************
DecoEscrituraRegistros DecoEscrituraRegistro (
.Address(Address), //*****************
.Write(Write), //*****************
.EnableStart(EnableStart), //*********************
.EnableRegister(EnableRegister) //*****************
);
generate
for (i=0; i<21; i=i+1) begin: MemoriaToRegistros
Registro #(.Width(Width)) RegistroCoeffcientes (
.CLK(CLK), //*********************
.reset(Reset), //*********************
.Enable(EnableRegister[i]), //*********************
.Entrada(InDatoMemoria), //*********************
.Salida(Aux[i]) //*********************
);
end
endgenerate
Registro #(.Width(Width)) RegistroEntrada ( // Solo cuando se hace un master reset los coeficientes se borrar
.CLK(CLK), //*********************
.reset(ResetStart), //*********************
.Enable(EnableRegister[21]), //*********************
.Entrada(InDatoMemoria), //*********************
.Salida(Aux[21]) //*********************
);
Registro #(.Width(Width)) RegistroStart (
.CLK(CLK), //*********************
.reset(ResetStart), //*********************
.Enable(EnableStart), //*********************
.Entrada(InDatoMemoria), //*********************
.Salida(OutRegisterStart) //*********************
);
assign Start = OutRegisterStart[00] | OutRegisterStart[01] | OutRegisterStart[02] |
OutRegisterStart[03] | OutRegisterStart[04] | OutRegisterStart[05] | OutRegisterStart[06] |
OutRegisterStart[07] | OutRegisterStart[08] | OutRegisterStart[09] | OutRegisterStart[10] |
OutRegisterStart[11] | OutRegisterStart[12] | OutRegisterStart[13] | OutRegisterStart[14] |
OutRegisterStart[15] | OutRegisterStart[16] | OutRegisterStart[17] | OutRegisterStart[18] |
OutRegisterStart[19] | OutRegisterStart[20] | OutRegisterStart[21] | OutRegisterStart[22] |
OutRegisterStart[23] | OutRegisterStart[24] | OutRegisterStart[25] | OutRegisterStart[26] |
OutRegisterStart[27] | OutRegisterStart[28] | OutRegisterStart[29] | OutRegisterStart[30] |
OutRegisterStart[31];
assign Coeff00 = Aux[0];
assign Coeff01 = Aux[1];
assign Coeff02 = Aux[2];
assign Coeff03 = Aux[3];
assign Coeff04 = Aux[4];
assign Coeff05 = Aux[5];
assign Coeff06 = Aux[6];
assign Coeff07 = Aux[7];
assign Coeff08 = Aux[8];
assign Coeff09 = Aux[9];
assign Coeff10 = Aux[10];
assign Coeff11 = Aux[11];
assign Coeff12 = Aux[12];
assign Coeff13 = Aux[13];
assign Coeff14 = Aux[14];
assign Coeff15 = Aux[15];
assign Coeff16 = Aux[16];
assign Coeff17 = Aux[17];
assign Coeff18 = Aux[18];
assign Coeff19 = Aux[19];
assign Offset = Aux[20];
assign InDato = Aux[21];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << ? << 1 << << 3 << endl; int ac; cin >> ac; cout << ? << 1 << << 2 << endl; int ab; cin >> ab; cout << ? << 2 << << 3 << endl; int bc; cin >> bc; int amc = ab - bc; int a2 = ac + amc; int a = a2 / 2; int b = ab - a; int c = bc - b; vector<int> res = {a, b, c}; for (int i = 0; i < n - 3; i++) { cout << ? << 1 << << i + 4 << endl; int tmp; cin >> tmp; res.push_back(tmp - a); } cout << ! ; for (int val : res) cout << val << ; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int n; cin >> n; int a[n]; for (int j = 1; j <= n; j++) { a[j] = pow(2, j); } int f = 0, s = 0; for (int j = 1; j <= n; j++) { if (j < n / 2 || j == n) f += a[j]; else { s += a[j]; } } cout << f - s << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, mod = 1000000007; char t[2042]; long long dp[2042][2042], suff[2042][2042]; int solve() { dp[n][0] = 1; for (int cInd = n - 1; cInd >= 0; cInd--) { dp[cInd][0] = 1; for (int kLeft = 0; kLeft <= k; kLeft++) { bool f = 0; for (int d = 0; cInd + d + 1 <= n; d++) { if (kLeft - (n - (cInd + d)) * (d + 1) >= 0) { dp[cInd][kLeft] += (1LL * dp[cInd + d + 1][kLeft - (n - (cInd + d)) * (d + 1)] * ( z - t[d + cInd])) % mod; } else { f = 1; break; } } if (f) { for (int d = n - cInd - 1; 1; d--) { if (kLeft - (n - (cInd + d)) * (d + 1) >= 0) { dp[cInd][kLeft] += (1LL * dp[cInd + d + 1][kLeft - (n - (cInd + d)) * (d + 1)] * ( z - t[d + cInd])) % mod; } else { f = 1; break; } } } dp[cInd][kLeft] += (suff[cInd + 1][kLeft] + dp[cInd + 1][kLeft] * (t[cInd] - a )) % mod; dp[cInd][kLeft] %= mod; suff[cInd][kLeft] += (1LL * dp[cInd + 1][kLeft] * (t[cInd] - a ) + suff[cInd + 1][kLeft]) % mod; } } return dp[0][k]; } int main() { cin >> n >> k; cin >> t; cout << solve() << n ; return 0; }
|
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Basic test for functions that work with unbounded vectors as return
// and param types.
module vhdl_unbounded_func_test();
vhdl_unbounded_func dut();
initial begin
#1; // wait for signal assignment
if(dut.test_out1 != 'b1010100110) begin
$display("FAILED 1");
$finish;
end
if(dut.test_out2 != 'b010110) begin
$display("FAILED 2");
$finish;
end
if(dut.neg_test_out1 != ~dut.test_out1) begin
$display("FAILED 3");
$finish;
end
if(dut.neg_test_out2 != ~dut.test_out2) begin
$display("FAILED 4");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6; const long long int inf = 1e18; vector<long long int> v, arr; void pf() {} long long int sqrtfun(long long int num) { long long int lo = 0, hi = (long long int)2e9, mid; if (num == 1) return num; while (lo + 1 < hi) { mid = lo + hi >> 1LL; if (mid * mid == num) return mid; else if (mid * mid > num) hi = mid; else lo = mid; } return (mid * mid > num) ? mid - 1 : mid; } long long int get(long long int r) { int ans = upper_bound(arr.begin(), arr.end(), r) - arr.begin(); return ans + sqrtfun(r) - 1; } void solve() { for (long long int i = 2; i <= N; i++) { for (long long int j = i * i * i; j <= inf; j *= i) { long long int x = sqrtfun(j); if (x * x != j) v.push_back(j); if (inf / i < j) break; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int t, l, r, ans = 0; cin >> t; solve(); sort(v.begin(), v.end()); for (auto i : v) { if (arr.empty()) arr.push_back(i); else if (arr.back() != i) arr.push_back(i); } while (t--) { cin >> r; cout << r - get(r) - 1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, x, y; char a[100005]; int main(void) { scanf( %d%d%d , &n, &x, &y); for (int i = 1; i <= n; i++) { cin >> a[i]; } if (a[x] == a[y]) puts( 0 ); else puts( 1 ); }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 8; int a[N], fa[N][20]; vector<int> E[N]; long long res; void dfs(int x, int f) { fa[x][0] = f; long long temp = a[f]; for (int i = 1; i < 20; i++) { fa[x][i] = fa[fa[x][i - 1]][i - 1]; temp = min(temp, (i + 1ll) * a[fa[x][i]]); } if (f != x) res += temp + a[x]; for (int &e : E[x]) if (e != f) dfs(e, x); } int main() { ios::sync_with_stdio(false); int n, rt = 0; a[0] = INT_MAX; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i], rt = a[rt] < a[i] ? rt : i; for (int i = 1, u, v; i < n; i++) cin >> u >> v, E[u].push_back(v), E[v].push_back(u); dfs(rt, rt); cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; long long POW(long long a, long long b, long long MMM = MOD) { long long ret = 1; for (; b; b >>= 1, a = (a * a) % MMM) if (b & 1) ret = (ret * a) % MMM; return ret; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { if (a == 0 || b == 0) return a + b; return a * (b / gcd(a, b)); } int dx[] = {0, 1, 0, -1}, dy[] = {1, 0, -1, 0}; int ddx[] = {0, 0, 1, 1, 1, -1, -1, -1}, ddy[] = {1, -1, 1, 0, -1, 1, 0, -1}; tuple<int, int, int, int> query[100000]; int ans[100000]; map<int, vector<tuple<int, int, int> > > M; int cc; void upd(int i, vector<int>& tree, int k) { int n = tree.size(); while (i < n) { tree[i] += k; i += (i & -i); } } int sum(int i, vector<int>& tree) { int c = 0; while (i > 0) { c += tree[i]; i -= (i & -i); } return c; } int main() { int n; scanf( %d , &n); for (int(i) = (0); (i) <= (n - 1); (i) += (1)) { int x, y, z; scanf( %d%d%d , &x, &y, &z); if (x == 3) M[z].push_back(tuple<int, int, int>(x, y, cc++)); else M[z].push_back(tuple<int, int, int>(x, y, -1)); } for (auto it = M.begin(); it != M.end(); it++) { vector<tuple<int, int, int> > v = it->second; int N = v.size(); vector<int> vv; for (int(i) = (0); (i) <= (N - 1); (i) += (1)) vv.push_back(get<1>(v[i])); sort(vv.begin(), vv.end()); vv.resize(unique(vv.begin(), vv.end()) - vv.begin()); for (int(i) = (0); (i) <= (N - 1); (i) += (1)) get<1>(v[i]) = lower_bound(vv.begin(), vv.end(), get<1>(v[i])) - vv.begin(); vector<int> tree(N + 5, 0); for (int(i) = (0); (i) <= (N - 1); (i) += (1)) { int x, y, z; tie(x, y, z) = v[i]; if (x == 1) upd(y + 1, tree, 1); else if (x == 2) upd(y + 1, tree, -1); else ans[z] = sum(y + 1, tree); } } for (int(i) = (0); (i) <= (cc - 1); (i) += (1)) printf( %d n , ans[i]); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i = 2, c = 0, v = 1; cin >> n; int x = 5; while (n - x > 0) { n = n - x; x = x * 2; v = v * 2; } while (n - v >= 1) { n = n - v; c++; } if (c + 1 == 1) { cout << Sheldon ; } if (c + 1 == 2) { cout << Leonard ; } if (c + 1 == 3) { cout << Penny ; } if (c + 1 == 4) { cout << Rajesh ; } if (c + 1 == 5) { cout << Howard ; } }
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(time(0)); const double eps = 1e-10; const long long inf = 0x3f3f3f3f3f3f3f3fLL; const long long N = 2e5 + 5; const long long MOD = 1e9 + 7; long long pw(long long b, long long p) { long long res = 1; while (p > 0) { if (p & 1) res = res * b % MOD; b = b * b % MOD; p >>= 1; } return res; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; vector<long long> h(n); long long sum = 0; for (long long i = 0; i < n; i++) { cin >> h[i]; sum += h[i]; } sum -= (n * (n - 1)) / 2; long long rem = sum % n; long long cnt = sum / n; for (long long i = 0; i < n; i++) { cout << i + cnt + (rem >= i + 1) << ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A221OI_BEHAVIORAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_BEHAVIORAL_V
|
`include "../src/include/FIFO2MM_adv.v"
`include "../src/s2mm_adv.v"
`include "s2mm_test_fifo_generator_0_0.v"
`include "s2mm_test.v"
`timescale 1ns / 1ps
/// 2. first line output : if f0 valid
/// 3. sof for reset
module test();
parameter integer C_PIXEL_WIDTH = 8;
parameter integer C_IMG_WBITS = 12;
parameter integer C_IMG_HBITS = 12;
parameter integer C_DATACOUNT_BITS = 10;
// User parameters ends
// Parameters of Axi Master Bus Interface M_AXI
parameter integer C_M_AXI_BURST_LEN = 16;
parameter integer C_M_AXI_ADDR_WIDTH = 32;
parameter integer C_M_AXI_DATA_WIDTH = 64;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr;
wire [7 : 0] m_axi_awlen;
wire [2 : 0] m_axi_awsize;
wire [1 : 0] m_axi_awburst;
wire m_axi_awlock;
wire [3 : 0] m_axi_awcache;
wire [2 : 0] m_axi_awprot;
wire [3 : 0] m_axi_awqos;
wire m_axi_awvalid;
reg m_axi_awready = 1;
wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_wdata;
wire [C_M_AXI_DATA_WIDTH/8-1 : 0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
reg m_axi_wready = 1;
reg [1 : 0] m_axi_bresp;
reg m_axi_bvalid;
wire m_axi_bready;
wire[31:0] S_AXIS_tdata;
wire S_AXIS_tlast;
wire S_AXIS_tready;
wire S_AXIS_tuser;
reg S_AXIS_tvalid;
reg[11:0] height = 240;
reg[11:0] width = 320;
wire[C_M_AXI_ADDR_WIDTH-1:0] addr;
assign addr = 32'h3FF80000;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] stride;
assign stride = 256;
reg clk;
reg resetn;
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
s2mm_test uut(
.M_AXI_awaddr(m_axi_awaddr),
.M_AXI_awlen(m_axi_awlen),
.M_AXI_awsize(m_axi_awsize),
.M_AXI_awburst(m_axi_awburst),
.M_AXI_awlock(m_axi_awlock),
.M_AXI_awcache(m_axi_awcache),
.M_AXI_awprot(m_axi_awprot),
.M_AXI_awqos(m_axi_awqos),
.M_AXI_awvalid(m_axi_awvalid),
.M_AXI_awready(m_axi_awready),
.M_AXI_wdata(m_axi_wdata),
.M_AXI_wstrb(m_axi_wstrb),
.M_AXI_wlast(m_axi_wlast),
.M_AXI_wvalid(m_axi_wvalid),
.M_AXI_wready(m_axi_wready),
.M_AXI_bresp(m_axi_bresp),
.M_AXI_bvalid(m_axi_bvalid),
.M_AXI_bready(m_axi_bready),
.S_AXIS_tdata(S_AXIS_tdata),
.S_AXIS_tlast(S_AXIS_tlast),
.S_AXIS_tready(S_AXIS_tready),
.S_AXIS_tuser(S_AXIS_tuser),
.S_AXIS_tvalid(S_AXIS_tvalid),
.MBUF_W_addr(addr),
.clk(clk),
.IMG_SIZE_height(height),
.IMG_SIZE_width(width),
.IMG_SIZE_stride(stride),
.resetn(resetn),
.soft_resetn(1'b1)
);
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
reg[11:0] col;
reg[11:0] row;
wire final_data;
assign final_data = (col == 0 && row == 0);
assign S_AXIS_tuser = (col == width-1 && row == height-1);
assign S_AXIS_tlast = (col == 0);
assign S_AXIS_tdata = ((row << 16) | col);
reg randominput;
always @(posedge clk) begin
if (resetn == 1'b0)
randominput <= 1'b0;
else
randominput <= (RANDOMINPUT ? {$random}%2 : 1);
if (resetn == 1'b0) begin
col <= width-1;
row <= height -1;
end
else if (S_AXIS_tvalid && S_AXIS_tready) begin
if (col != 0) begin
col <= col - 1;
row <= row;
end
else if (row != 0) begin
col <= width - 1;
row <= row - 1;
end
else begin
col <= width-1;
row <= height-1;
end
end
else begin
col <= col;
row <= row;
end
if (resetn == 1'b0)
S_AXIS_tvalid <= 1'b0;
else
S_AXIS_tvalid <= randominput;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool one(string s); bool two(string s); void c(string s); void c2(string s); int main() { string str; int i; cin >> str; if (one(str)) { c(str); } else if (two(str)) { c2(str); } else { cout << str << endl; } return 0; } bool one(string s) { int i; int len = s.length(); for (i = 0; i < len; i++) { if (i == 0) { if (isupper(s[i])) { return false; } } else { if (!isupper(s[i])) return false; } } return true; } bool two(string s) { int i; int len = s.length(); for (i = 0; i < len; i++) { if (!isupper(s[i])) return false; } return true; } void c(string s) { int i; int len = s.length(); s[0] = toupper(s[0]); for (i = 1; i < len; i++) { s[i] = tolower(s[i]); } cout << s << endl; } void c2(string s) { int i; int len = s.length(); for (i = 0; i < len; i++) { s[i] = tolower(s[i]); } cout << s << endl; }
|
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Simple branch predictor implementation
We assume flag to be "true" if instruction is bf and it jumps backwords
or if instruction is bnf and it jumps forward.
Copyright (C) 2013 Stefan Kristiansson <>
******************************************************************************/
`include "mor1kx-defines.v"
module mor1kx_branch_predictor_simple
(
// Signals belonging to the stage where the branch is predicted.
input op_bf_i, // branch if flag
input op_bnf_i, // branch if not flag
input [9:0] immjbr_upper_i, // branch offset
output predicted_flag_o //result of predictor
);
// Static branch prediction - backward branches are predicted as taken,
// forward branches as not taken.
assign predicted_flag_o = op_bf_i & immjbr_upper_i[9] |
op_bnf_i & !immjbr_upper_i[9];
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module soc_system_video_vga_controller_0 (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:40:17 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_stub.v
// Design : zynq_design_1_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module zynq_design_1_auto_pc_1(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
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#include <bits/stdc++.h> using namespace std; map<int, int> times; const int INF = 0x3fffffff; struct Node { int l, r; int v; Node() { l = -1, r = -1; } Node(int _l, int _r) { l = _l, r = _r; } } node[120000]; int fa[120000]; int n, v, ls, rs, root; int ans; int Findroot(int t) { if (fa[t] != t) return Findroot(fa[t]); return t; } void dfs(int mi, int ma, int now) { if (node[now].v <= mi || node[now].v >= ma) { if (times[node[now].v] != -1) { ans++; times[node[now].v]++; } } else { ans -= times[node[now].v]; times[node[now].v] = -1; } if (node[now].l ^ (~0)) dfs(mi, min(ma, node[now].v), node[now].l); if (node[now].r ^ (~0)) dfs(max(mi, node[now].v), ma, node[now].r); return; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= n; i++) { scanf( %d%d%d , &v, &ls, &rs); if (ls ^ (~0)) fa[ls] = i; if (rs ^ (~0)) fa[rs] = i; node[i].l = ls; node[i].r = rs; node[i].v = v; } root = Findroot(1); dfs(-INF, INF, root); printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; vector<int> isbandyk(int a, vector<int> prad) { vector<int> rez; vector<int> ats(prad.size(), -1); int pas = 0; for (int i = 0; i < prad.size(); i++) { if (prad[i] <= a - 1) { rez.push_back(prad[i]); pas = i; ats[i] = 1; } } for (int i = pas + 1; i < prad.size(); i++) { if (prad[i] == a) { rez.push_back(prad[i]); ats[i] = 1; } } for (int i = 0; i < prad.size(); i++) { if (prad[i] > a) { rez.push_back(prad[i]); ats[i] = 2; } else if (prad[i] == a && i < pas) { rez.push_back(prad[i]); ats[i] = 2; } } sort(prad.begin(), prad.end()); if (prad == rez) { return ats; } else { vector<int> c; return c; } return ats; } int main(int argc, const char* argv[]) { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> eil; for (int i = 0; i < n; i++) { char a; cin >> a; int b = a - 0 ; eil.push_back(b); } bool taip = false; for (int i = 0; i < 10; i++) { vector<int> b = isbandyk(i, eil); if (b.size() != 0) { for (int i = 0; i < b.size(); i++) cout << b[i]; taip = true; break; } } if (!taip) cout << - ; cout << n ; } return 0; }
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`timescale 1ns / 1ps
// Modified by: Adam Michael, CM1884
// Mohammad Almisbaa, CM2060
// Date: November 5, 2015
// Summary: This is just a square wave generator.
//File: CRTClockTemplate.v
//Generate 25MHz VGA clock from a SystemClock
//SystemClockFreq and CRTClockFreq are input parameters in MHz
//ECE333 Fall 2015
//Term Project on Pong game on VGA
//this is a template to be completed by students
module CRTClock(SystemClockFreq, CRTClockFreq, PixelClock, Reset, Clock);
parameter SystemClockSize=10;
input [SystemClockSize-1:0] SystemClockFreq;
input [SystemClockSize-1:0] CRTClockFreq;
output PixelClock;
input Reset;
input Clock;
reg [SystemClockSize-1:0] counter;
wire [SystemClockSize-1:0] MaxCounter;
assign MaxCounter = (SystemClockFreq / CRTClockFreq) - 1;
assign PixelClock = counter > (MaxCounter >> 1);
always @ (posedge Clock or posedge Reset)
if (Reset) counter <= 0;
else begin
if (counter == MaxCounter) counter <= 0;
else counter <= counter + 1'd1;
end
endmodule
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#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int n; cin >> n; if (n % 2 == 0) return cout << NO , 0; long long int arr[2 * n + 1]; long long int a = 1, b = n + 1; for (long long int i = 1; i < 2 * n + 1; i += 2) { if (a % 2) { arr[a++] = i; arr[b++] = i + 1; } else { arr[b++] = i; arr[a++] = i + 1; } } cout << YES n ; for (long long int i = 1; i < 2 * n + 1; i++) cout << arr[i] << ; }
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#include <bits/stdc++.h> using namespace std; int N, M, A, B; int main() { scanf( %d%d%d%d , &N, &M, &A, &B); int rA = (A - 1) / M + 1, cA = A - (rA - 1) * M; int rB = (B - 1) / M + 1, cB = B - (rB - 1) * M; if (B == N) cB = M; if (rA == rB) { puts( 1 ); exit(0); } if (rA + 1 == rB) { if (cA == 1 && cB == M) puts( 1 ); else puts( 2 ); exit(0); } int fA = (cA == 1); int fB = (cB == M); if (fA + fB) { printf( %d n , 3 - fA - fB); exit(0); } if (cB + 1 == cA) puts( 2 ); else puts( 3 ); return 0; }
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//////////////////////////////////////////////////////////////////
// //
// Memory Access - Instantiates the memory access stage //
// sub-modules of the Amber 25 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Instantiates the Data Cache //
// Also contains a little bit of logic to decode memory //
// accesses to decide if they are cached or not //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2011 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a25_mem
(
input i_clk,
input i_fetch_stall, // Fetch stage asserting stall
input i_exec_stall, // Execute stage asserting stall
output o_mem_stall, // Mem stage asserting stall
input [31:0] i_daddress,
input i_daddress_valid,
input [31:0] i_daddress_nxt, // un-registered version of address to the cache rams
input [31:0] i_write_data,
input i_write_enable,
input i_exclusive, // high for read part of swap access
input [3:0] i_byte_enable,
input [8:0] i_exec_load_rd, // The destination register for a load instruction
input i_cache_enable, // cache enable
input i_cache_flush, // cache flush
input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
output [31:0] o_mem_read_data,
output o_mem_read_data_valid,
output [10:0] o_mem_load_rd, // The destination register for a load instruction
// Wishbone accesses
output o_wb_cached_req, // Cached Request
output o_wb_uncached_req, // Unached Request
output o_wb_write, // Read=0, Write=1
output [15:0] o_wb_byte_enable, // byte eable
output [127:0] o_wb_write_data,
output [31:0] o_wb_address, // wb bus
input [127:0] i_wb_uncached_rdata, // wb bus
input [127:0] i_wb_cached_rdata, // wb bus
input i_wb_cached_ready, // wishbone access complete and read data valid
input i_wb_uncached_ready // wishbone access complete and read data valid
);
`include "memory_configuration.v"
wire [31:0] cache_read_data;
wire address_cachable;
wire sel_cache_p;
wire sel_cache;
wire cached_wb_req;
wire uncached_data_access;
wire uncached_data_access_p;
wire cache_stall;
wire uncached_wb_wait;
reg uncached_wb_req_r = 'd0;
reg uncached_wb_stop_r = 'd0;
reg cached_wb_stop_r = 'd0;
wire daddress_valid_p; // pulse
reg [31:0] mem_read_data_r = 'd0;
reg mem_read_data_valid_r = 'd0;
reg [10:0] mem_load_rd_r = 'd0;
wire [10:0] mem_load_rd_c;
wire [31:0] mem_read_data_c;
wire mem_read_data_valid_c;
reg mem_stall_r = 'd0;
wire use_mem_reg;
reg fetch_only_stall_r = 'd0;
wire fetch_only_stall;
wire void_output;
wire wb_stop;
reg daddress_valid_stop_r = 'd0;
wire [31:0] wb_rdata32;
// ======================================
// Memory Decode
// ======================================
assign address_cachable = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]];
assign sel_cache_p = daddress_valid_p && address_cachable && i_cache_enable && !i_exclusive;
assign sel_cache = i_daddress_valid && address_cachable && i_cache_enable && !i_exclusive;
assign uncached_data_access = i_daddress_valid && !sel_cache && !cache_stall;
assign uncached_data_access_p = daddress_valid_p && !sel_cache;
assign use_mem_reg = wb_stop && !mem_stall_r;
assign o_mem_read_data = use_mem_reg ? mem_read_data_r : mem_read_data_c;
assign o_mem_load_rd = use_mem_reg ? mem_load_rd_r : mem_load_rd_c;
assign o_mem_read_data_valid = !void_output && (use_mem_reg ? mem_read_data_valid_r : mem_read_data_valid_c);
// Return read data either from the wishbone bus or the cache
assign wb_rdata32 = i_daddress[3:2] == 2'd0 ? i_wb_uncached_rdata[ 31: 0] :
i_daddress[3:2] == 2'd1 ? i_wb_uncached_rdata[ 63:32] :
i_daddress[3:2] == 2'd2 ? i_wb_uncached_rdata[ 95:64] :
i_wb_uncached_rdata[127:96] ;
assign mem_read_data_c = sel_cache ? cache_read_data :
uncached_data_access ? wb_rdata32 :
32'h76543210 ;
assign mem_load_rd_c = {i_daddress[1:0], i_exec_load_rd};
assign mem_read_data_valid_c = i_daddress_valid && !i_write_enable && !o_mem_stall;
assign o_mem_stall = uncached_wb_wait || cache_stall;
// Request wishbone access
assign o_wb_byte_enable = i_daddress[3:2] == 2'd0 ? {12'd0, i_byte_enable } :
i_daddress[3:2] == 2'd1 ? { 8'd0, i_byte_enable, 4'd0} :
i_daddress[3:2] == 2'd2 ? { 4'd0, i_byte_enable, 8'd0} :
{ i_byte_enable, 12'd0} ;
assign o_wb_write = i_write_enable;
assign o_wb_address = {i_daddress[31:2], 2'd0};
assign o_wb_write_data = {4{i_write_data}};
assign o_wb_cached_req = !cached_wb_stop_r && cached_wb_req;
assign o_wb_uncached_req = !uncached_wb_stop_r && uncached_data_access_p;
assign uncached_wb_wait = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
always @( posedge i_clk )
begin
uncached_wb_req_r <= (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
end
assign fetch_only_stall = i_fetch_stall && !o_mem_stall;
always @( posedge i_clk )
fetch_only_stall_r <= fetch_only_stall;
assign void_output = (fetch_only_stall_r && fetch_only_stall) || (fetch_only_stall_r && mem_read_data_valid_r);
// pulse this signal
assign daddress_valid_p = i_daddress_valid && !daddress_valid_stop_r;
always @( posedge i_clk )
begin
uncached_wb_stop_r <= (uncached_wb_stop_r || (uncached_data_access_p&&!cache_stall)) && (i_fetch_stall || o_mem_stall);
cached_wb_stop_r <= (cached_wb_stop_r || cached_wb_req) && (i_fetch_stall || o_mem_stall);
daddress_valid_stop_r <= (daddress_valid_stop_r || daddress_valid_p) && (i_fetch_stall || o_mem_stall);
// hold this until the mem access completes
mem_stall_r <= o_mem_stall;
end
assign wb_stop = uncached_wb_stop_r || cached_wb_stop_r;
always @( posedge i_clk )
if ( !wb_stop || o_mem_stall )
begin
mem_read_data_r <= mem_read_data_c;
mem_load_rd_r <= mem_load_rd_c;
mem_read_data_valid_r <= mem_read_data_valid_c;
end
// ======================================
// L1 Data Cache
// ======================================
a25_dcache u_dcache (
.i_clk ( i_clk ),
.i_fetch_stall ( i_fetch_stall ),
.i_exec_stall ( i_exec_stall ),
.o_stall ( cache_stall ),
.i_request ( sel_cache_p ),
.i_exclusive ( i_exclusive ),
.i_write_data ( i_write_data ),
.i_write_enable ( i_write_enable ),
.i_address ( i_daddress ),
.i_address_nxt ( i_daddress_nxt ),
.i_byte_enable ( i_byte_enable ),
.i_cache_enable ( i_cache_enable ),
.i_cache_flush ( i_cache_flush ),
.o_read_data ( cache_read_data ),
.o_wb_cached_req ( cached_wb_req ),
.i_wb_cached_rdata ( i_wb_cached_rdata ),
.i_wb_cached_ready ( i_wb_cached_ready )
);
endmodule
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#include <bits/stdc++.h> using namespace std; int n, a[300000 + 10], ans = 2e9; vector<int> lj[300000 + 10]; multiset<int> s; int main() { int i; scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d , &a[i]), s.insert(a[i]); for (i = 1; i < n; ++i) { int u, v; scanf( %d%d , &u, &v); lj[u].push_back(v); lj[v].push_back(u); } for (i = 1; i <= n; ++i) { int da = a[i]; s.erase(s.find(a[i])); for (int j : lj[i]) da = max(da, a[j] + 1), s.erase(s.find(a[j])); if (!s.empty()) da = max(da, *s.rbegin() + 2); s.insert(a[i]); for (int j : lj[i]) s.insert(a[j]); ans = min(da, ans); } printf( %d , ans); }
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, i, t; cin >> t; while (t--) { cin >> n; if (n % 2 == 0) cout << n / 2 << n ; else cout << (n / 2) + 1 << n ; } }
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#include <bits/stdc++.h> using namespace std; int main() { string a = , b = ; int n, m; cin >> n >> m; for (int i = 0; i < 2220; i++) { if (i % 2 == 0) { a += 5 ; b += 4 ; } else { a += 4 ; b += 5 ; } } a += 5 ; b += 5 ; cout << a << endl; cout << b << endl; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using pii = pair<int, int>; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int tests; cin >> tests; for (int test = 0; test < tests; ++test) { int n; cin >> n; vector<ll> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; ll x, y; int fx, fy; cin >> x >> fx >> y >> fy; ll req; cin >> req; int lo = 1, hi = n + 1; for (int i = 0; i < n; ++i) a[i] /= 100; sort(a.begin(), a.end()); reverse(a.begin(), a.end()); while (lo < hi) { int mid = (lo + hi) / 2; vector<ll> c(mid); for (int i = 0; i < mid; ++i) { if (i % fx == fx - 1) c[i] += x; if (i % fy == fy - 1) c[i] += y; } sort(c.begin(), c.end()); reverse(c.begin(), c.end()); ll sum = 0; for (int i = 0; i < mid; ++i) sum += a[i] * c[i]; if (sum >= req) hi = mid; else lo = mid + 1; } if (lo == n + 1) lo = -1; cout << lo << n ; } }
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#include <bits/stdc++.h> using namespace std; int c1, c2, c3, c4, n, m; int rs1, rs2, rs3, rs4, rs; int a, b; int main() { ios_base::sync_with_stdio(0); ; cin.tie(0); ; cin >> c1 >> c2 >> c3 >> c4; cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> a; rs1 += min(a * c1, c2); } rs2 = min(rs1, c3); for (int i = 1; i <= m; i++) { cin >> b; rs3 += min(b * c1, c2); } rs4 = min(rs3, c3); cout << min(rs2 + rs4, c4); return 0; }
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#include <bits/stdc++.h> using namespace std; static inline void WRITE(int a) { printf( %d n , a); } static inline void WRITE2(int a, int b) { printf( %d %d n , a, b); } const int S9 = 1000000007, S6 = 1000007, S5 = 100007, S4 = 10007, S3 = 1007, S2 = 107; const double E2 = 0.01, E4 = 0.0001, E6 = 0.000001, E8 = 0.00000001; int tab[4][2]; int check() { bool czy = false; int ob = 0, at = 1; if (tab[ob][0] > tab[2][1] && tab[at][1] > tab[3][0]) if (tab[ob][0] > tab[3][1] && tab[at][1] > tab[2][0]) return 1; if ((tab[ob][0] < tab[2][1] && tab[at][1] < tab[3][0]) || (tab[ob][0] < tab[3][1] && tab[at][1] < tab[2][0])) czy = true; ob = 1; at = 0; if (tab[ob][0] > tab[2][1] && tab[at][1] > tab[3][0]) if (tab[ob][0] > tab[3][1] && tab[at][1] > tab[2][0]) return 1; if (((tab[ob][0] < tab[2][1] && tab[at][1] < tab[3][0]) || (tab[ob][0] < tab[3][1] && tab[at][1] < tab[2][0])) && czy) return 2; return 0; } int main() { for (int i = 0; i < 4; i++) scanf( %d%d , &tab[i][0], &tab[i][1]); int x = check(); if (x == 0) puts( Draw ); else printf( Team %d n , x); return 0; }
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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 22:04:40 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb,
web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]" */;
input clka;
input rsta;
input ena;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
endmodule
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#include <bits/stdc++.h> const int inf = (1ll << 30) - 1; const int maxn = (int)1e5 + 10; using namespace std; int dp[150][(1 << 16) + 100]; int c[111]; int r[111]; int b[111]; char temp[111]; int cntR[(1 << 16) + 10]; int cntB[(1 << 16) + 10]; int n; void solve() { memset(dp, -1, sizeof dp); queue<pair<pair<int, int>, int> > pq; scanf( %d , &n); int xx = 0; for (int i = 0; i < n; i++) { scanf( %s%d%d , temp, &r[i], &b[i]); c[i] = temp[0] == R ? 1 : 0; xx += c[i]; } if (xx * 2 > n) { for (int i = 0; i < n; i++) { c[i] ^= 1; swap(r[i], b[i]); } } for (int i = 0; i < (1 << n); i++) { for (int j = 0; j < n; j++) { if (i & (1 << j)) { if (c[j]) cntR[i]++; else cntB[i]++; } } } dp[0][0] = 0; pq.push(make_pair(make_pair(0, 0), 0)); while (pq.size() > 0) { int x = pq.front().first.first; int y = pq.front().first.second; int mask = pq.front().second; pq.pop(); if (dp[x][mask] < y) continue; for (int i = 0; i < n; i++) { if (mask & (1 << i)) continue; int nmask = mask | (1 << i); int X = x, Y = y; if (r[i] >= cntR[mask]) { X += cntR[mask]; } else X += r[i]; if (b[i] >= cntB[mask]) { Y += cntB[mask]; } else Y += b[i]; if (dp[X][nmask] == -1 || dp[X][nmask] < Y) { dp[X][nmask] = Y; pq.push(make_pair(make_pair(X, Y), nmask)); } } } int sumA = 0, sumB = 0; for (int i = 0; i < n; i++) { sumA += r[i]; sumB += b[i]; } int ans = inf; for (int i = 0; i < 144; i++) { if (dp[i][(1 << n) - 1] == -1) continue; ans = min(ans, max(sumA - i, sumB - dp[i][(1 << n) - 1])); } printf( %d n , ans + n); } int main() { int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const long double radian = 180 / acos(-1); int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long x, mini = LLONG_MAX, p; cin >> x; x %= 360; if (x < 0) x = 360 + x; for (int i = 0; i < 4; i++) { if (min(x, 360 - x) < mini) { mini = min(x, 360 - x); p = i; } x = (x + 270) % 360; } cout << p; return 0; }
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// file: Clock48MHZ_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module Clock48MHZ_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 3;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
Clock48MHZ clknetwork
(// Clock in ports
.CLK_100 (CLK_IN1),
// Clock out ports
.CLK_48 (clk_int[1]),
.CLK_OUT1 (clk_int[2]),
.CLK_OUT2 (clk_int[3]),
// Status and control signals
.LOCKED (LOCKED));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
ODDR clkout_oddr
(.Q (CLK_OUT[clk_out_pins]),
.C (clk[clk_out_pins]),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; const int INF = (1 << 30) - 1; const long double EPS = 1e-9; const long double PI = fabs(atan2(0.0, -1.0)); const int MAXV = 80010; int n; vector<int> g[MAXV]; void load() { scanf( %d , &n); for (int i = 0, u, v; i < n - 1; i++) { scanf( %d%d , &u, &v); --u, --v; g[u].push_back(v); g[v].push_back(u); } } int sz[MAXV]; unsigned long long pths[MAXV]; unsigned long long dp[MAXV]; unsigned long long bad = 0; void dfs(int v, int p) { sz[v] = 1; for (int i = 0; i < (int)g[v].size(); i++) { int to = g[v][i]; if (to == p) continue; dfs(to, v); sz[v] += sz[to]; } pths[v] = 0; for (int i = 0; i < (int)g[v].size(); i++) { int to = g[v][i]; if (to == p) continue; pths[v] += sz[to] * 1ULL * (sz[v] - sz[to] - 1); } assert(pths[v] % 2 == 0); pths[v] /= 2; pths[v] += sz[v] - 1; dp[v] = 0; for (int i = 0; i < (int)g[v].size(); i++) { int to = g[v][i]; if (to == p) continue; dp[v] += dp[to]; } bad += dp[v]; dp[v] += pths[v] * 1ULL * sz[v]; for (int i = 0; i < (int)g[v].size(); i++) { int to = g[v][i]; if (to == p) continue; bad += dp[to] * 1ULL * (sz[v] - sz[to] - 1); } } void solve() { dfs(0, -1); unsigned long long res = 0; unsigned long long all = 0; for (int i = 0; i < n; i++) all += pths[i]; for (int i = 0; i < n; i++) res += pths[i] * (all - pths[i]); cout << res - 2 * bad << n ; } int main() { load(); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; double eps = 1e-7; int n, m, A, B, a[6010]; int cmp(double x) { if (x > eps) return 1; if (x < -eps) return -1; return 0; } struct line { double k, b; line(double _k, double _b) { k = _k, b = _b; } line(double __x) { k = 2, b = -2 * __x; } friend line operator+(const line& u, const line& v) { return line(u.k + v.k, u.b + v.b); } void operator+=(const line& v) { k += v.k, b += v.b; } void shift(double x) { b -= k * x; } double f(double x) { return k * x + b; } double rt() { return -b / k; } }; vector<line> v; vector<double> u; void SHIFT() { int tur = -1; for (int i = 0; i < v.size(); i++) if (cmp(v[i].f(u[i + 1])) != -1 && cmp(v[i].f(u[i])) != 1) tur = i; if (tur == -1) { if (cmp(v[0].f(u[0])) == 1) tur = -1; if (cmp(v.back().f(u.back())) == -1) tur = v.size(); } for (int i = 0; i < v.size(); i++) { double x = v[i].rt(); if (tur == -1 && i == 0) { x = u[0], tur++; u[i] += A, u[i + 1] += B; v.insert(v.begin() + i, line(0, 0)); u.insert(u.begin() + i + 1, x + B); v[i + 1].shift(B); i += 1; continue; } if (tur == v.size() && i == v.size() - 1) { x = u.back(), tur--; u[i] += A, u[i + 1] += B; u.insert(u.begin() + i, x + A); v.insert(v.begin() + i, line(0, 0)); v[i].shift(A); i += 1; continue; } if (i < tur) u[i] += A, v[i].shift(A); else if (i > tur) u[i + 1] += B, v[i].shift(B); else { u[i] += A, u[i + 1] += B; u.insert(u.begin() + i + 1, x + A); u.insert(u.begin() + i + 2, x + B); v.insert(v.begin() + i + 1, line(0, 0)); v.insert(v.begin() + i + 2, v[i]); v[i].shift(A); v[i + 2].shift(B); i += 2; } } int i = 0; while (i < u.size() && cmp(u[u.size() - i - 1] - m) == 1) i++; u[u.size() - i] = m; u.erase(u.end() - i + 1, u.end()), v.erase(v.end() - i + 1, v.end()); } void ADD(line p) { for (auto& i : v) i += p; } double pos() { if (cmp(v[0].f(u[0])) == 1) return u[0]; if (cmp(v.back().f(u.back())) == -1) return u.back(); for (int i = 0; i < v.size(); i++) if (cmp(v[i].f(u[i + 1])) != -1 && cmp(v[i].f(u[i])) != 1) return v[i].rt(); for (int i = 1; i + 1 < u.size(); i++) if (cmp(v[i - 1].f(u[i])) == -1 && cmp(v[i].f(u[i])) == 1) return u[i]; } double b[6010], res; int main() { scanf( %d%d%d%d , &n, &m, &A, &B); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); v.emplace_back(a[1]); u.push_back(1), u.push_back(m); for (int i = 2; i <= n; i++) b[i - 1] = pos(), SHIFT(), ADD(line(a[i])); b[n] = pos(); for (int i = n; i >= 2; i--) { if (cmp(max(b[i] - B, 1.0) - b[i - 1]) == 1) b[i - 1] = max(b[i] - B, 1.0); else if (cmp(b[i - 1] - max(b[i] - A, 1.0)) == 1) b[i - 1] = max(b[i] - A, 1.0); } for (int i = 1; i <= n; i++) printf( %lf , b[i]), res += (b[i] - a[i]) * (b[i] - a[i]); puts( ); printf( %lf n , res); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { pair<int, int> u, v; int n, ans = 0; long long a, b, c, p, q; scanf( %d%d%d%d , &u.first, &u.second, &v.first, &v.second); scanf( %d , &n); while (n--) { scanf( %lld%lld%lld , &a, &b, &c); p = a * u.first + b * u.second + c; q = a * v.first + b * v.second + c; if ((p > 0 && q < 0) || (p < 0 && q > 0)) ++ans; } printf( %d n , ans); }
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#include <bits/stdc++.h> using namespace std; string a; int main() { int t; cin >> t; while (t--) { int n; cin >> n; cin >> a; for (int i = 0; i < a.length(); i += 2) cout << a[i]; cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; void task(); int main() { srand(time(0)); ios_base::sync_with_stdio(0); task(); return 0; } vector<int> prefix_function(string s) { int n = s.length(); vector<int> p(n, 0); for (int i = 1; i < n; ++i) { int j = p[i - 1]; while (j > 0 && s[i] != s[j]) j = p[j - 1]; if (s[i] == s[j]) p[i] = j + 1; } return p; } string s[3]; void task() { cin >> s[0] >> s[1] >> s[2]; sort(s, s + 3); int ans = 1e9 + 10; do { string ss = s[0]; { vector<int> p = prefix_function(s[1] + ! + s[0]); int mx = 0; for (int i = s[1].length(); i < ((int)((p).size())); ++i) mx = max(mx, p[i]); if (p.back() != ((int)((s[1]).size())) && mx != ((int)((s[1]).size()))) ss += s[1].substr(p.back(), ((int)((s[1]).size())) - p.back()); } { vector<int> p = prefix_function(s[2] + ! + ss); int mx = 0; for (int i = s[2].length(); i < ((int)((p).size())); ++i) mx = max(mx, p[i]); if (p.back() != ((int)((s[2]).size())) && mx != ((int)((s[2]).size()))) ss += s[2].substr(p.back(), ((int)((s[2]).size())) - p.back()); ans = min(ans, ((int)((ss).size()))); } } while (next_permutation(s, s + 3)); cout << ans; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m, h; cin >> n >> m >> h; vector<int> ms(m), ns(n); vector<vector<int> > ok(n, vector<int>(m)); for (int i = 0; i < m; i++) { cin >> ms[i]; } for (int i = 0; i < n; i++) { cin >> ns[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> ok[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (ok[i][j] == 0) { cout << 0 << ; } else { cout << min(ms[j], ns[i]) << ; } } cout << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLRTP_PP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_PP_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; const long long maxn = 1e6 + 00; const long long inf = 1e9 + 800; long long a[maxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, r, sum = 0; ; cin >> n >> r; for (long long i = 0; i < (1 << n); i++) { cin >> a[i]; sum += a[i]; } cout << fixed << setprecision(10); for (long long i = 0; i < r; i++) { cout << (long double)sum / (1 << n) << endl; long long p, v; cin >> p >> v; sum -= a[p]; a[p] = v; sum += a[p]; } cout << (long double)sum / (1 << n) << endl; }
|
#include <bits/stdc++.h> using namespace std; #define ll long long int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; int n, k; while (t--) { char a[3] = { a , b , c }; cin >> n >> k; int temp = k; while(k--) { cout<<a[0]; } int i = 1; n = n - temp; //cout << n; while(n--) { if(i == 3){ i = 0; } cout<<a[i]; i++; } cout << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O21BA_FUNCTIONAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_FUNCTIONAL_PP_V
|
/***********************************************************************************************************************
* Copyright (C) 2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
TODO
*/
module UART(txd, rxd);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P9" *) //not yet used
input wire rxd;
(* LOC = "P7" *)
output reg txd = 0;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Clocking
//The 2 MHz RC oscillator
wire clk_250khz_cnt; //dedicated output to hard IP only
wire clk_250khz; //general fabric output
GP_RCOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OSC_FREQ("2M"),
.HARDIP_DIV(8),
.FABRIC_DIV(1)
) rcosc (
.PWRDN(1'b0),
.CLKOUT_HARDIP(clk_250khz_cnt),
.CLKOUT_FABRIC(clk_250khz)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Baud rate generator
localparam UART_BAUD = 9600;
localparam CLOCK_FREQ = 250000;
localparam UART_BDIV = CLOCK_FREQ / UART_BAUD;
localparam UART_BMAX = UART_BDIV - 1;
reg[7:0] baud_count = UART_BMAX;
wire baud_edge = (baud_count == 0);
reg sending = 0;
always @(posedge clk_250khz_cnt) begin
baud_count <= baud_count - 1'h1;
if(baud_edge)
baud_count <= UART_BMAX;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit counter
localparam MESSAGE_MAX = 14'h3fff;
reg[13:0] message_count = MESSAGE_MAX;
wire message_edge = (message_count == 0);
always @(posedge clk_250khz_cnt) begin
message_count <= message_count - 1'h1;
if(message_edge)
message_count <= MESSAGE_MAX;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Pattern generator for the actual message we're sending
//Start bit is in LSB since that's what we output during reset.
//High 6 bits of PGEN ignored, then bit-reversed payload
//We need an extra stop bit so we don't glitch for one clock when the counter wraps
//(before we know the byte is over).
wire txd_raw;
GP_PGEN #(
.PATTERN_LEN(5'd11),
.PATTERN_DATA({6'h0, 8'h82, 1'h1, 1'h1})
) tx_pgen (
.nRST(!message_edge),
.CLK(baud_edge),
.OUT(txd_raw)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Timer so we know how long the actual message lasts
localparam BYTE_MAX = 8'd10;
//Can't infer GP_COUNTx_ADV yet, so instantiate
wire byte_done;
GP_COUNT8_ADV #(
.CLKIN_DIVIDE(1),
.COUNT_TO(BYTE_MAX),
.RESET_MODE("LEVEL"),
.RESET_VALUE("COUNT_TO")
) byte_count (
.CLK(clk_250khz_cnt),
.RST(!sending),
.UP(1'b0),
.KEEP(!baud_edge),
.OUT(byte_done),
.POUT()
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Send logic
reg send_pending = 0;
always @(posedge clk_250khz) begin
if(message_edge) begin
send_pending <= 1;
end
if(send_pending && baud_edge) begin
send_pending <= 0;
sending <= 1;
end
if(byte_done) begin
sending <= 0;
end
end
always @(*) begin
if(!sending || byte_done)
txd <= 1;
else
txd <= txd_raw;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.size(); int l[n]; for (int i = 0; i < n; ++i) { l[i] = n; } for (int i = 0; i < n; ++i) { for (int j = 1; j <= min(n - i - 1, i); ++j) { if (s[i - j] == s[i] && s[i] == s[i + j]) { l[i - j] = min(l[i - j], i + j); break; } } } set<pair<int, int> > h; for (int i = 0; i < n; ++i) { h.insert({l[i], i}); } long long sum = 0; for (int i = 0; i < n; ++i) { sum += n - ((*h.begin()).first); h.erase({l[i], i}); } cout << sum; return 0; }
|
// This pass performs an optimisation that decomposes wide arithmetic
// comparisons into LUT-size chunks (as guided by the `LUT_WIDTH
// macro) connected to a single lookahead-carry-unit $lcu cell,
// which is typically mapped to dedicated (and fast) FPGA
// carry-chains.
(* techmap_celltype = "$lt $le $gt $ge" *)
module _80_lcu_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
generate
if (_TECHMAP_CELLTYPE_ == "" || `LUT_WIDTH < 2)
wire _TECHMAP_FAIL_ = 1;
else if (_TECHMAP_CELLTYPE_ == "$lt") begin
// Transform $lt into $gt by swapping A and B
$gt #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
end
else if (_TECHMAP_CELLTYPE_ == "$le") begin
// Transform $le into $ge by swapping A and B
$ge #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
end
else begin
// Perform sign extension on A and B
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
(* force_downto *)
wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
(* force_downto *)
wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
// For $ge operation, start with the assumption that A and B are
// equal (propagating this equality if A and B turn out to be so)
localparam CI = _TECHMAP_CELLTYPE_ == "$ge";
$__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI))
_TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y));
end
endgenerate
endmodule
module $__CMP2LCU (A, B, P, G, Y);
parameter AB_WIDTH = 0;
parameter AB_SIGNED = 0;
parameter LCU_WIDTH = 1;
parameter BUDGET = 0;
parameter CI = 0;
(* force_downto *)
input [AB_WIDTH-1:0] A; // A from original $gt/$ge
(* force_downto *)
input [AB_WIDTH-1:0] B; // B from original $gt/$ge
(* force_downto *)
input [LCU_WIDTH-1:0] P; // P of $lcu
(* force_downto *)
input [LCU_WIDTH-1:0] G; // G of $lcu
output Y;
parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0;
generate
if (AB_WIDTH == 0) begin
(* force_downto *)
wire [LCU_WIDTH-1:0] CO;
$lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO));
assign Y = CO[LCU_WIDTH-1];
end
else begin
localparam COST =
_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
? 0
: (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]
? 1
: 2);
if (BUDGET < COST)
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI))
_TECHMAP_REPLACE_ (.A(A), .B(B), .P({P, 1'b1}), .G({G, 1'b0}), .Y(Y));
else begin
wire PP, GG;
// Bit-wise equality (xnor) of A and B
assign PP = A[AB_WIDTH-1] ^~ B[AB_WIDTH-1];
if (AB_SIGNED)
assign GG = ~A[AB_WIDTH-1] & B[AB_WIDTH-1];
else if (_TECHMAP_CONSTMSK_P_[LCU_WIDTH-1]) // First compare for LUT if P (and G) is constant
assign GG = A[AB_WIDTH-1] & ~B[AB_WIDTH-1];
else
// Priority "encoder" that checks A[i] == 1'b1 && B[i] == 1'b0
// from MSB down, deferring to less significant bits if the
// MSBs are equal
assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]);
(* force_downto *)
wire [LCU_WIDTH-1:0] P_, G_;
if (LCU_WIDTH == 1) begin
// Propagate only if all pairs are equal
// (inconclusive evidence to say A >= B)
assign P_ = P[0] & PP;
// Generate if any comparisons call for it
assign G_ = G[0] | GG;
end
else begin
// Propagate only if all pairs are equal
// (inconclusive evidence to say A >= B)
assign P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
// Generate if any comparisons call for it
assign G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
end
if (AB_WIDTH == 1)
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
_TECHMAP_REPLACE_ (.A(), .B(), .P(P_), .G(G_), .Y(Y));
else
$__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI))
_TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y));
end
end
endgenerate
endmodule
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: mor1kx processor Wishbone bus bridge
For now, very simple, not registering, assumes 32-bit data, addressing
Copyright (C) 2012 Authors
Author(s): Julius Baxter <>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_bus_if_wb32
#(
parameter BUS_IF_TYPE = "CLASSIC",
parameter BURST_LENGTH = 8
)
(
input clk,
input rst,
output cpu_err_o,
output cpu_ack_o,
output [31:0] cpu_dat_o,
input [31:0] cpu_adr_i,
input [31:0] cpu_dat_i,
input cpu_req_i,
input [3:0] cpu_bsel_i,
input cpu_we_i,
input cpu_burst_i,
output [31:0] wbm_adr_o,
output wbm_stb_o,
output wbm_cyc_o,
output [3:0] wbm_sel_o,
output wbm_we_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
output [31:0] wbm_dat_o,
input wbm_err_i,
input wbm_ack_i,
input [31:0] wbm_dat_i,
input wbm_rty_i
);
localparam BADDR_WITH = (BURST_LENGTH==4) ? 2 :
(BURST_LENGTH==8) ? 3 :
(BURST_LENGTH==16)? 4 : 30;
initial
$display("%m: Wishbone bus IF is %s",BUS_IF_TYPE);
generate
/* verilator lint_off WIDTH */
if (BUS_IF_TYPE=="B3_READ_BURSTING") begin : b3_read_bursting
/* verilator lint_on WIDTH */
// Burst until the incoming address is not what it should be
wire finish_burst;
reg finish_burst_r;
reg bursting;
reg [31:2] burst_address;
reg [BADDR_WITH-1:0] burst_wrap_start;
wire [BADDR_WITH-1:0] burst_wrap_finish;
wire address_differs;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
bursting <= 0;
else if (wbm_err_i)
bursting <= 0;
else if (bursting & finish_burst & wbm_ack_i)
bursting <= 0;
else if (cpu_req_i & !bursting & !cpu_we_i)
bursting <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
begin
burst_address <= 0;
burst_wrap_start <= 0;
end
else if (cpu_req_i & !bursting)
begin
burst_address <= cpu_adr_i[31:2];
burst_wrap_start <= cpu_adr_i[BADDR_WITH+2-1:2];
end
else if (wbm_ack_i)
burst_address[BADDR_WITH+2-1:2] <= burst_address[BADDR_WITH+2-1:2]
+ 1;
assign address_differs = (burst_address!=cpu_adr_i[31:2]);
assign burst_wrap_finish = burst_wrap_start - 1;
assign finish_burst = (bursting & (
(BURST_LENGTH!=0 &&
burst_address[BADDR_WITH+2-1:2]==(burst_wrap_finish))
| address_differs
| !cpu_req_i
)
)
;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
finish_burst_r <= 0;
else if (wbm_ack_i)
finish_burst_r <= finish_burst;
else
finish_burst_r <= 0;
assign wbm_adr_o = bursting ? {burst_address,2'b00} : cpu_adr_i;
assign wbm_stb_o = bursting & !finish_burst_r;
assign wbm_cyc_o = bursting & !finish_burst_r;
assign wbm_sel_o = cpu_bsel_i;
assign wbm_we_o = cpu_we_i;
assign wbm_cti_o = bursting ? (finish_burst ? 3'b111 : 3'b010) :
3'b000;
assign wbm_bte_o = BURST_LENGTH==4 ? 2'b01 :
BURST_LENGTH==8 ? 2'b10 :
BURST_LENGTH==16 ? 2'b11 :
2'b00; // Linear burst
assign wbm_dat_o = cpu_dat_i;
assign cpu_err_o = wbm_err_i;
assign cpu_ack_o = (wbm_ack_i) &
!(bursting & address_differs) & cpu_req_i;
assign cpu_dat_o = wbm_err_i ? 0 : wbm_dat_i;
/* verilator lint_off WIDTH */
end else if (BUS_IF_TYPE=="B3_REGISTERED_FEEDBACK") begin : b3_registered_feedback
/* verilator lint_on WIDTH */
assign wbm_adr_o = cpu_adr_i;
assign wbm_stb_o = cpu_req_i;
assign wbm_cyc_o = cpu_req_i;
assign wbm_sel_o = cpu_bsel_i;
assign wbm_we_o = cpu_we_i;
assign wbm_cti_o = cpu_burst_i ? 3'b010 : 3'b111;
assign wbm_bte_o = BURST_LENGTH==4 ? 2'b01 :
BURST_LENGTH==8 ? 2'b10 :
BURST_LENGTH==16 ? 2'b11 :
2'b00; // Linear burst
assign wbm_dat_o = cpu_dat_i;
assign cpu_err_o = wbm_err_i;
assign cpu_ack_o = wbm_ack_i;
assign cpu_dat_o = wbm_dat_i;
end else begin : classic // CLASSIC only
// Only classic, single cycle accesses
// A register to force de-assertion of access request signals after
// each ack
reg cycle_end;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
cycle_end <= 1;
else
cycle_end <= wbm_ack_i | wbm_err_i;
assign cpu_err_o = wbm_err_i;
assign cpu_ack_o = wbm_ack_i;
assign cpu_dat_o = wbm_dat_i;
assign wbm_adr_o = cpu_adr_i;
assign wbm_stb_o = cpu_req_i & !cycle_end;
assign wbm_cyc_o = cpu_req_i;
assign wbm_sel_o = cpu_bsel_i;
assign wbm_we_o = cpu_we_i;
assign wbm_cti_o = 0;
assign wbm_bte_o = 0;
assign wbm_dat_o = cpu_dat_i;
end // else: !if(BUS_IF_TYPE=="READ_B3_BURSTING")
endgenerate
endmodule // mor1kx_bus_if_wb
|
#include <bits/stdc++.h> using namespace std; int a, b, h, n, i; long long x, ans; pair<pair<int, int>, int> p[100005]; map<long long, long long> f; void update(int index, long long value) { while (index < 1e9) { f[index] = max(f[index], value); index += (-index & index); } } long long read(int index) { long long ans = 0; while (index > 0) { ans = max(ans, f[index]); index -= (-index & index); } return ans; } int main() { scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d%d%d , &p[i].first.second, &p[i].first.first, &p[i].second); sort(p, p + n); reverse(p, p + n); for (i = 0; i < n; i++) { x = read(p[i].first.first) + p[i].second; update(p[i].first.second + 1, x); ans = max(ans, x); } printf( %lld , ans); }
|
#include <bits/stdc++.h> using namespace std; int n; struct SegTree { int L, R, P, DELTA; struct node { int d; bool zero; } v[212345 * 4]; inline void set_zero(int x) { v[x].zero = 1; v[x].d = 0; } inline void fix(int x, int d) { v[x].zero = 0; v[x].d += d; } inline void rep(int x) { if (v[x].zero) { set_zero(x * 2); set_zero(x * 2 + 1); v[x].zero = 0; } else { fix(x * 2, v[x].d); fix(x * 2 + 1, v[x].d); v[x].d = 0; } } void update(int x, int l, int r) { if (l > R || r < L) return; if (L <= l && r <= R) { if (l < r) rep(x); else v[x].zero = 0; v[x].d += DELTA; return; } int m = (l + r) / 2; rep(x); update(x * 2, l, m); update(x * 2 + 1, m + 1, r); } void gao_zero(int x, int l, int r) { if (l > R || r < L) return; if (L <= l && r <= R) { set_zero(x); return; } int m = (l + r) / 2; rep(x); gao_zero(x * 2, l, m); gao_zero(x * 2 + 1, m + 1, r); } int add(int x, int y) { if (~y) return x + y; return -1; } int query(int x, int l, int r) { if (v[x].zero) return -1; if (l == r) return v[x].d; int m = (l + r) / 2; if (P <= m) return add(v[x].d, query(x * 2, l, m)); else return add(v[x].d, query(x * 2 + 1, m + 1, r)); } void up(int l, int r, int d) { L = l, R = r, DELTA = d; update(1, 1, n); } void zero(int l, int r) { L = l, R = r; gao_zero(1, 1, n); } int qr(int p) { P = p; return query(1, 1, n); } } tree; int x[212345], len[212345]; vector<pair<int, int> > qu[212345]; int ans[212345], nxt[212345]; int L[212345], D[212345], id[212345], top = 0; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d%d , x + i, len + i); int q; scanf( %d , &q); for (int i = 0; i < int(q); i++) { int u, v; scanf( %d%d , &u, &v); qu[u].push_back(make_pair(v, i)); } nxt[n] = -1; for (int i = n - 1; i >= 1; --i) { int j = i + 1; while (~j && x[j] + len[j] <= x[i] + len[i]) j = nxt[j]; nxt[i] = j; } for (int i = n; i >= 1; --i) { if (nxt[i] == -1) { } else { while (top > 0 && id[top] < nxt[i]) { tree.up(L[top], n, -D[top]); --top; } if (x[i] + len[i] >= x[nxt[i]]) { } else { tree.up(nxt[i], n, x[nxt[i]] - x[i] - len[i]); ++top; L[top] = nxt[i]; D[top] = x[nxt[i]] - x[i] - len[i]; id[top] = i; } } for (auto x : qu[i]) ans[x.second] = tree.qr(x.first); } for (int i = 0; i < int(q); i++) printf( %d n , ~ans[i] ? ans[i] : 0); }
|
#include <bits/stdc++.h> #pragma GCC optimize( inline ) int rd() { register int k = 0; char c = getchar(); while (c > 9 || c < 0 ) c = getchar(); while (c >= 0 && c <= 9 ) k = k * 10 + c - 48, c = getchar(); return k; } const int N = 100001; struct Q { int o, t, l, r; } q[N]; struct C { int x, v; } c[N]; int n, m, p, l = 1, r, qn, cn, a[N], bl[N], ans[N], T, b[N << 1], B, v[N << 1], sv[N], s; bool cmp(register const Q& x, register const Q& y) { return bl[x.l] != bl[y.l] ? x.l < y.l : (bl[x.r] == bl[y.r] ? x.t < y.t : x.r < y.r); } void Ins(register int p) { --sv[v[p]], ++sv[++v[p]]; } void Del(register int p) { --sv[v[p]], ++sv[--v[p]]; } void Set(register int t, register int i) { if (q[i].l <= c[t].x && c[t].x <= q[i].r) Del(a[c[t].x]), Ins(c[t].v); std::swap(a[c[t].x], c[t].v); } int main() { B = n = rd(), m = rd(), p = pow(n, 0.66); for (register int i = 1; i <= n; ++i) b[i] = a[i] = rd(), bl[i] = i / p; for (register int i = 1; i <= m; ++i) { if (rd() == 1) ++qn, q[qn] = {qn, cn, rd(), rd()}; else c[++cn] = {rd(), b[++B] = rd()}; } std::sort(b + 1, b + B + 1), B = std::unique(b + 1, b + B + 1) - b - 1, std::sort(q + 1, q + qn + 1, cmp); for (register int i = 1; i <= n; ++i) a[i] = std::lower_bound(b + 1, b + B + 1, a[i]) - b; for (register int i = 1; i <= cn; ++i) c[i].v = std::lower_bound(b + 1, b + B + 1, c[i].v) - b; for (register int i = 1; i <= qn; ++i) { while (l > q[i].l) Ins(a[--l]); while (r < q[i].r) Ins(a[++r]); while (l < q[i].l) Del(a[l++]); while (r > q[i].r) Del(a[r--]); while (T < q[i].t) Set(++T, i); while (T > q[i].t) Set(T--, i); for (s = 1; sv[s] > 0; ++s) ; ans[q[i].o] = s; } for (register int i = 1; i <= qn; ++i) printf( %d n , ans[i]); return 0; }
|
Require Import AutoSep.
(** * The simplest function *)
Definition diverger := bmodule "diverger" {{
bfunction "diverger"() [SPEC reserving 0
PRE[_] [| True |]
POST[_] [| False |] ]
Diverge
end
}}.
(* Eval compute in compile diverger. *)
Theorem divergerOk : moduleOk diverger.
vcgen; sep_auto.
Qed.
(* Print Assumptions divergerOk. *)
(** * A function with a private local variable *)
Definition seven := bmodule "seven" {{
bfunction "seven"("x") [SPEC reserving 1
PRE[_] [| True |]
POST[R] [| R = $7 |] ]
"x" <- 7;;
Return "x"
end
}}.
Theorem sevenOk : moduleOk seven.
vcgen; sep_auto.
Qed.
(** * A function with both parameters and private local variables *)
Definition triple := bmodule "triple" {{
bfunction "triple"("x", "y") [SPEC("x") reserving 1
PRE[V] [| True |]
POST[R] [| R = $3 ^* V "x" |] ]
"y" <- "x" + "x";;
"y" <- "y" + "x";;
Return "y"
end
}}.
Theorem tripleOk : moduleOk triple.
vcgen; (sep_auto; words).
Qed.
(** * Immediate return *)
Definition immedS : spec := SPEC reserving 0
PRE[_] [| True |]
POST[_] [| True |].
Definition immed := bmodule "immed" {{
bfunction "immed"() [immedS]
Return 0
end
}}.
(* Eval compute in compile immed. *)
Theorem immedOk : moduleOk immed.
vcgen; sep_auto.
Qed.
(* Print Assumptions immedOk. *)
Definition immedTest := bimport [[ "immed"!"immed" @ [immedS] ]]
bmodule "main" {{
bfunction "main"() [SPEC reserving 1
PRE[_] [| True |]
POST[_] [| True |] ]
Call "immed"!"immed"()
[PRE[_] [| True |]
POST[_] [| True|] ];;
Return 0
end
}}.
(* Eval compute in compile immedTest. *)
Theorem immedTestOk : moduleOk immedTest.
vcgen; (sep_auto; words).
Qed.
(* Print Assumptions immedTestOk. *)
Definition immedProg := link immed immedTest.
(* Eval compute in compile immedProg. *)
Theorem immedProgOk : moduleOk immedProg.
link immedOk immedTestOk.
Qed.
(* Print Assumptions immedProgOk. *)
(** Let's also test with a version that reserves more stack space than needed. *)
Definition immedTestBig := bimport [[ "immed"!"immed" @ [immedS] ]]
bmodule "main" {{
bfunction "main"() [SPEC reserving 5
PRE[_] [| True |]
POST[_] [| True |] ]
Call "immed"!"immed"()
[PRE[_] [| True |]
POST[_] [| True|] ];;
Return 0
end
}}.
(* Eval compute in compile immedTest. *)
Theorem immedTestBigOk : moduleOk immedTestBig.
vcgen; (sep_auto; words).
Qed.
(** * Incrementer *)
Definition incS : spec := SPEC("x") reserving 0
PRE[V] [| True |]
POST[R] [| R = V "x" ^+ $1 |].
Definition inc := bmodule "inc" {{
bfunction "inc"("x") [incS]
Return "x" + 1
end
}}.
(* Eval compute in compile inc. *)
Theorem incOk : moduleOk inc.
vcgen; sep_auto.
Qed.
Definition incTest := bimport [[ "inc"!"inc" @ [incS] ]]
bmodule "main" {{
bfunction "main"("y") [SPEC reserving 3
PRE[_] [| True |]
POST[R] [| R = $10 |] ]
"y" <-- Call "inc"!"inc"(7)
[PRE[_, R] Emp
POST[R'] [| R' = R ^+ $2 |] ];;
"y" <- "y" + 2;;
Return "y"
end
}}.
Theorem incTestOk : moduleOk incTest.
vcgen; (sep_auto; words).
Qed.
(** * Always-0, in a convoluted way *)
Definition always0S : spec := SPEC("x") reserving 0
PRE[_] [| True |]
POST[R] [| R = $0 |].
Definition always0 := bmodule "always0" {{
bfunction "always0"("x") [always0S]
If ("x" = 0) {
Skip
} else {
"x" <- 0
};;
Return "x"
end
}}.
(* Eval compute in compile always0. *)
Theorem always0Ok : moduleOk always0.
vcgen; sep_auto.
Qed.
|
#include <bits/stdc++.h> using namespace std; bool b[150000] = {0}; bool dfs(int n, vector<set<int>>& v) { b[n] = 1; for (auto itr = v[n].begin(); itr != v[n].end(); itr++) { if (!b[*itr]) if (v[n] != v[*itr]) return 0; if (!b[*itr]) dfs(*itr, v); } return 1; } int main() { int n, m; cin >> n >> m; vector<set<int>> v(n); for (int i = 0; i < n; i++) v[i].insert(i); for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; v[a].insert(b); v[b].insert(a); } bool r = 1; for (int i = 0; i < n && r; i++) { if (!b[i]) { if (!dfs(i, v)) r = 0; } } cout << (r ? YES : NO ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O22A_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o22a (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void past_code(); void file() {} long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } long long todic(string z) { long long sum = 0; long long j = 1; for (long long i = 0; i < z.length(); i++) { sum += (z[i] - 0 ) * j; j *= 2; } return sum; } string tobin(long long a) { string x; while (a != 0) { x += to_string(a % 2); a /= 2; } return x; } bool isPrime(long long n) { if (n <= 1) return false; for (long long i = 2; i <= sqrt(n); i++) if (n % i == 0) return false; return true; } string towlo(string x) { string h; for (long long i = 0; i < x.length(); i++) { h += tolower(x[i]); } return h; } bool comp(pair<long long, long long> a, pair<long long, long long> b) { return a.second > b.second; } inline void read(int &x) { x = 0; char c = getchar(); int f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = 10 * x + c - 0 ; c = getchar(); } x *= f; } long long fact(long long o) { if (o == 0) return 1; return o * fact(o - 1); } long long sumd(long long x) { long long sum = 0; while (x != 0) { sum += x % 10; x /= 10; } return sum; } bool com(pair<long long, long long> a, pair<long long, long long> b) { return a.second > b.second; } bool vis[505][505]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string x; cin >> x; int k; cin >> k; map<string, int> m; string h[] = { January , February , March , April , May , June , July , August , September , October , November , December }; m[ January ] = 0; m[ June ] = 5; m[ November ] = 10; m[ February ] = 1; m[ July ] = 6; m[ December ] = 11; m[ March ] = 2; m[ August ] = 7; m[ April ] = 3; m[ September ] = 8; m[ May ] = 4; m[ October ] = 9; cout << h[(k + m[x]) % 12] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long in() { int32_t x; scanf( %d , &x); return x; } const long long maxn = 1e5 + 10; const long long mod = 1e9 + 7; const long long inf = 1e9 + 10; vector<long long> g[maxn]; long long deg[maxn]; long long a[maxn]; bool mark[maxn]; long long rem; vector<long long> path, V; inline void dfs(long long node) { mark[node] = true; rem--; path.push_back(node); for (auto u : g[node]) { if (mark[u]) { cout << 0 << endl; exit(0); } dfs(u); } } long long dp[maxn]; int32_t main() { long long n = in(), q = in(), t = in(); rem = n; for (long long i = 0; i < n; i++) a[i] = in(); for (long long i = 0; i < q; i++) { long long from = in() - 1, to = in() - 1; g[from].push_back(to); deg[to]++; } V.push_back(0); dp[0] = 1; for (long long i = 0; i < n; i++) { if (!mark[i] && !deg[i]) { path.clear(); dfs(i); long long prefsum = 0; for (auto v : path) { prefsum += a[v]; V.push_back(prefsum); if (v - path.back()) t -= prefsum; } } } if (rem) return cout << 0 << endl, 0; if (t < 0) return cout << 0 << endl, 0; for (long long i = 1; i < V.size(); i++) { for (long long pre = 0; pre + V[i] < maxn; pre++) (dp[pre + V[i]] += dp[pre]) %= mod; } cout << dp[t] << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 200005; long long n, m, u, v, k; long long flag; long long a[N]; long long x, y, z; long long aa, bb, cc, dd; long long ans[100005]; long long sum; void init() {} long long gcd(long long x, long long y) { if (!y) return x; return gcd(y, x % y); } struct node { long long x, id; bool operator<(const node t) const { return x < t.x; } }; long long getn(long long x, long long y, long long z) { long long n; cout << ? << x << << y << << z << endl; cin >> n; return n; } void solve() { init(); cin >> n; sum = 0; for (long long i = 1; i <= n; i++) { a[i] = 0; } for (long long i = 0; i < n / 3; i++) { ans[i] = getn(i * 3 + 1, i * 3 + 2, i * 3 + 3); if (!ans[i]) { u = i; } else { v = i; } } aa = getn(u * 3 + 1, u * 3 + 2, v * 3 + 1); bb = getn(u * 3 + 1, u * 3 + 2, v * 3 + 2); cc = getn(v * 3 + 1, v * 3 + 2, u * 3 + 1); dd = getn(v * 3 + 1, v * 3 + 2, u * 3 + 2); if (aa + bb == 0) { x = u * 3 + 1; } else { x = u * 3 + 3; } a[x] = 0; if (cc + dd == 2) { y = v * 3 + 1; } else { y = v * 3 + 3; } a[y] = 1; for (long long i = 0; i < n / 3; i++) { if (ans[i]) { aa = getn(i * 3 + 1, i * 3 + 2, x); bb = getn(i * 3 + 2, i * 3 + 3, x); if (aa + bb == 0) { a[i * 3 + 1] = 1; a[i * 3 + 2] = 0; a[i * 3 + 3] = 1; } else if (aa + bb == 2) { a[i * 3 + 1] = 1; a[i * 3 + 2] = 1; a[i * 3 + 3] = 1; } else if (aa == 1) { a[i * 3 + 1] = 1; a[i * 3 + 2] = 1; a[i * 3 + 3] = 0; } else { a[i * 3 + 1] = 0; a[i * 3 + 2] = 1; a[i * 3 + 3] = 1; } } else { aa = getn(i * 3 + 1, i * 3 + 2, y); bb = getn(i * 3 + 2, i * 3 + 3, y); if (aa + bb == 0) { a[i * 3 + 1] = 0; a[i * 3 + 2] = 0; a[i * 3 + 3] = 0; } else if (aa + bb == 2) { a[i * 3 + 1] = 0; a[i * 3 + 2] = 1; a[i * 3 + 3] = 0; } else if (aa == 1) { a[i * 3 + 1] = 1; a[i * 3 + 2] = 0; a[i * 3 + 3] = 0; } else { a[i * 3 + 1] = 0; a[i * 3 + 2] = 0; a[i * 3 + 3] = 1; } } } for (long long i = 1; i <= n; i++) { if (a[i] == 0) sum++; } cout << ! << sum << ; for (long long i = 1; i <= n; i++) { if (a[i] == 0) cout << i << ; } cout << endl; } signed main() { long long t = 1; cin >> t; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); long k; scanf( %ld , &k); int d; scanf( %d , &d); long arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } if (d == 1) { cout << 1 << endl; } else { set<long> con; unordered_map<long, int> cnt; for (int i = 0; i < d; i++) { con.insert(arr[i]); cnt[arr[i]]++; } long ans = con.size(); long final = con.size(); if (final == 1) { cout << 1 << endl; } else { for (int i = 0; i < n - d; i++) { cnt[arr[i]]--; if (cnt[arr[i]] == 0) { ans--; } cnt[arr[i + d]]++; if (cnt[arr[i + d]] == 1) { ans++; } final = min(final, ans); } cout << final << endl; } } } }
|
#include <bits/stdc++.h> using namespace std; void incr(long long &st, long long &en, long long &k, long long val) { en++; if (val <= k) { k++; } } void decr(long long &st, long long &en, long long &k, long long val) { long long sz = en - st + 1; if (val < k) { k -= val; sz = sz - val; } else { sz = val; } st = 1; en = sz + st - 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, k, m, t; cin >> n >> k >> m >> t; long long st = 1, en = n; while (t--) { long long w, val; cin >> w >> val; if (w) { incr(st, en, k, val); cout << (en - st + 1) << << k << endl; } else { decr(st, en, k, val); cout << (en - st + 1) << << k << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long int n; cin >> n; long long int ar[n + 1]; for (long long int i = 0; i < n; i++) cin >> ar[i]; sort(ar, ar + n, greater<long long int>()); vector<long long int> v, ans; for (long long int i = 0; i < n; i++) { v.push_back(ar[i]); } ans.push_back(v[0]); for (long long int i = 1; i < v.size(); i++) { long long int p = v[i]; while (p >= 0) { if (find(ans.begin(), ans.end(), p) != ans.end()) { p--; } else { ans.push_back(p); break; } } } long long int cnt = 0; for (long long int i = 0; i < ans.size(); i++) cnt += ans[i]; cout << cnt << endl; }
|
#include <bits/stdc++.h> using namespace std; char str[210], in[10]; int cnt[10], r[10]; int main() { scanf( %s %s , in, str); int l = strlen(in); for (int i = 0; i < l; i++) { if (in[i] == 9 ) cnt[6]++; else if (in[i] == 5 ) cnt[2]++; else cnt[in[i] - 0 ]++; } l = strlen(str); for (int i = 0; i < l; i++) { if (str[i] == 9 ) r[6]++; else if (str[i] == 5 ) r[2]++; else r[str[i] - 0 ]++; } int ans = 0x7fffffff; for (int i = 0; i <= 9; i++) { if (cnt[i] == 0) continue; ans = min(ans, r[i] / cnt[i]); } cout << ans << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [6:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [1:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 6
audio_start_r, // 5
data_start_r, // 4
volume_start_r, // 3
audio_ctrl_r, // 2:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b001};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[1:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__OR2_PP_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_SYMBOL_V
`define SKY130_FD_SC_HS__NAND3_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_SYMBOL_V
|
`timescale 1ns / 1ps
module virtual_master(
/*
- This is just done for simultion purposes, the module implements a task that sends data over the I2C bus
*/
output reg SDA,
output reg SCL,
output reg dbg=0
);
reg [7:0] dataSent = 8'bz0zzz0zz, addressSent=8'bzzz0000z; //DATA BB, ADD E1
integer i=0;
task sendData;
input [7:0] addressSent,dataSent;
begin
#5;
SDA=1;SCL=1;
#1;
SDA=0;
#1;
SCL=0;
//SDA=dataSent[0];#1;
for(i=7;i>=0;i--) begin
SCL=0;SDA=addressSent[i];#1;SCL=1;#1;
end
SDA=1'bz;
SCL=0;
#1;
SCL=1;#1;
for(i=7;i>=0;i--) begin
SCL=0;SDA=dataSent[i];#1;SCL=1;#1;
end
SCL=0;#1;SCL=1;#1;SCL=0;#1;
SDA=0;#1;SCL=1;#2;SDA=1'bz;
#10;
end
endtask
endmodule
module TB ();
//Signals, and internal registers are declared here
pullup(SDA);
pullup(SCK);
reg CLK_IN=0;
wire PWM_OUT_1,PWM_OUT_2,PWM_OUT_3;
parameter [7:0] dev1 = 8'bzzz0000z,dev2 = 8'bzzzz000z, dev3 = 8'bz0z0000z;
//Devices instantiation here
//-----------I2CPWM slaves-----------------------
//this is dev1
I2C_PWM_INTERFACE #(8'hE1,6,1) uut_1(
.SDA(SDA),
.SCK(SCK),
.CLK_IN(CLK_IN),
.PWM_OUT(PWM_OUT_1)
);
//this is dev2
I2C_PWM_INTERFACE #(8'hF1,6,1) uut_2(
.SDA(SDA),
.SCK(SCK),
.CLK_IN(CLK_IN),
.PWM_OUT(PWM_OUT_2)
);
//this is dev3
I2C_PWM_INTERFACE #(8'hA1,6,1) uut_3(
.SDA(SDA),
.SCK(SCK),
.CLK_IN(CLK_IN),
.PWM_OUT(PWM_OUT_3)
);
//-----------------------------------------------
//Master starting the i2c communication
virtual_master master(.SDA(SDA),.SCL(SCK));
initial begin
$dumpfile("testing.dump");
$dumpvars;
master.sendData(dev1,8'b0zzzzzzz); //Set dev1 duty cycle to 127
master.sendData(dev2,8'b00zz00z0); //Set dev2 duty cycle to 50
master.sendData(dev3,8'bzz00z000); //Set dev3 duty cycle to 200
end
always begin
CLK_IN=~CLK_IN;
#1;
if($time==500us)$finish();
end
endmodule // TB
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3000; vector<int> E[MAXN]; long long dp[MAXN][MAXN]; int P[MAXN][MAXN]; int T[MAXN][MAXN]; int n; bool cmp(int a, int b) { return dp[a] > dp[b]; } void dfs(int x, int p, int r) { P[r][x] = p; int d = 1; for (int i = 0; i < E[x].size(); ++i) { int v = E[x][i]; if (v != p) { dfs(v, x, r); d += T[r][v]; } } T[r][x] = d; } long long dp_get(int u, int v) { if (u == v || dp[u][v] != 0) return dp[u][v]; long long d = max(dp_get(u, P[u][v]), dp_get(v, P[v][u])) + T[u][v] * 1LL * T[v][u]; dp[u][v] = d; dp[v][u] = d; return d; } void solve() { scanf( %d , &n); for (int i = 1; i < n; ++i) { int x, y; scanf( %d%d , &x, &y); --x, --y; E[x].push_back(y); E[y].push_back(x); } for (int i = 0; i < n; ++i) dfs(i, -1, i); long long bestres = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < i; ++j) bestres = max(bestres, dp_get(i, j)); printf( %I64d n , bestres); } int main() { solve(); return 0; }
|
`timescale 1ns / 1ps
`define BUS_REQUESTED 1'b1
`define BUS_NOT_REQUESTED 1'b0
`define BUS_GRANTED 1'b1
`define BUS_NOT_GRANTED 1'b0
module arbiter(
grant1, grant2,
request_p1, request_p2, enable, reset, clk
);
// outputs from the module
output reg grant1;
output reg grant2;
// inputs to the module
input request_p1; // request coming from P1
input request_p2; // request coming from P2
input enable;
input reset;
input clk;
// reg [1:0]choose_bit2;
// reg [1:0]choose_bit1;
always @(reset) begin
if (reset) begin
// choose_bit1 = 2'b00;
// choose_bit2= 2'b00;
end
end
always @*
begin
if(enable)
begin
// $display("request_p1:%d, request_p2:%d",request_p1, request_p2);
case ({request_p1,request_p2})
2'b11: begin
grant1 = `BUS_GRANTED;
grant2 = `BUS_NOT_GRANTED;
end
2'b01: begin
grant1 = `BUS_NOT_GRANTED;
grant2 = `BUS_GRANTED;
end
2'b10: begin
grant1 = `BUS_GRANTED;
grant2 = `BUS_NOT_GRANTED;
end
default: begin
grant1 = `BUS_GRANTED;
grant2 = `BUS_NOT_GRANTED;
end
endcase
// if (request_p1 == `BUS_REQUESTED && request_p2 == `BUS_REQUESTED)
// begin
// grant1 = `BUS_GRANTED;
// grant2 = `BUS_NOT_GRANTED;
// end else
// begin
// if (request_p1 == `BUS_REQUESTED && request_p2 == `BUS_NOT_REQUESTED)
// begin
// grant1 = `BUS_GRANTED;
// grant2 = `BUS_NOT_GRANTED;
// end else
// begin
// if (request_p1 == `BUS_NOT_REQUESTED && request_p2 == `BUS_REQUESTED)
// begin
// grant1 = `BUS_NOT_GRANTED;
// grant2 = `BUS_GRANTED;
// end
// end
// end
// $display("grant1:%d, grant2:%d",grant1, grant2);
end
// $display("enableArbiter:%d",enable);
end
// always @(posedge clk) begin
// if (request_p1 == `BUS_REQUESTED && request_p2 == `BUS_REQUESTED) begin
// if (choose_bit1 == 2'b00 || choose_bit1 == 2'b01) begin
// // selected_tag = tag_p1;
// grant1 = `BUS_GRANTED;
// grant2 = `BUS_NOT_GRANTED;
// choose_bit1 = choose_bit1 + 1'b1;
// if (choose_bit2 == 2'b01) begin
// choose_bit2 = 2'b00;
// end else begin end
// end else begin
// // selected_tag = tag_p2;
// grant1 = `BUS_NOT_GRANTED;
// grant2 = `BUS_GRANTED;
// choose_bit1 = choose_bit1 + 1'b1;
// if (choose_bit2 == 2'b01) begin
// choose_bit2 = 2'b00;
// end else begin end
// end
// end else if (request_p1 == `BUS_REQUESTED && request_p2 == `BUS_NOT_REQUESTED) begin
// if (choose_bit2 == 2'b00) begin
// choose_bit1 = 2'b00;
// choose_bit2 = 2'b01;
// end else begin
// choose_bit2 = 2'b00;
// end
// // selected_tag = tag_p1;
// grant1 = `BUS_GRANTED;
// grant2 = `BUS_NOT_GRANTED;
// choose_bit1 = choose_bit1 + 1'b1;
// end else if (request_p1 == `BUS_NOT_REQUESTED && request_p2 == `BUS_REQUESTED) begin
// if (choose_bit2 == 1) begin
// choose_bit1 = 2'b00;
// choose_bit2 = 2'b01;
// end else begin
// choose_bit2 = 2'b00;
// end
// // selected_tag = tag_p2;
// grant1 = `BUS_NOT_GRANTED;
// grant2 = `BUS_GRANTED;
// choose_bit1 = choose_bit1 + 1'b1;
// end else begin end
// end
endmodule
|
/* wb_intercon_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module wb_intercon_tb;
vlog_tb_utils vlog_tb_utils0();
vlog_tap_generator #("wb_intercon.tap", 3) vtg();
wb_mux_tb #(.AUTORUN (0)) wb_mux_tb();
wb_arbiter_tb #(.AUTORUN (0)) wb_arb_tb();
wb_cdc_tb #(.AUTORUN (0)) wb_cdc_tb();
initial begin
wb_mux_tb.run;
vtg.ok("wb_mux: All tests passed!");
wb_arb_tb.run;
vtg.ok("wb_arbiter: All tests passed!");
wb_cdc_tb.run;
vtg.ok("wb_cdc: All tests passed!");
#3 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int N = 0, p = 0, q = 0; int k = 0; cin >> N; for (int i = 0; i < N; i++) { cin >> p >> q; if (q - p >= 2) k++; } cout << k; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10, mod = 1e9 + 7, INF = 0x3f3f3f3f; int main() { int n, a, x, b, y; cin >> n >> a >> x >> b >> y; while (a != x && b != y) { a++; if (a > n) a = 1; b--; if (b < 1) b = n; if (a == b) { printf( YES ); return 0; } } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int suspect[100000]; int justify[100000]; bool killer[100000]; pair<int, int> a[100000]; int main() { int n, m; scanf( %d%d , &n, &m); int cnt = 0; for (int i = 0; i < n; i++) { killer[i] = false; char x; int k; scanf( %d , &k); if (k < 0) { x = - ; k *= -1; } else x = + ; k--; if (x == + ) { suspect[k]++; a[i].second = 1; } else { a[i].second = 0; justify[k]++; cnt++; } a[i].first = k; } int cntkiller = 0; for (int i = 0; i < n; i++) if (suspect[i] + cnt - justify[i] == m) { killer[i] = true; cntkiller++; } for (int i = 0; i < n; i++) { if (a[i].second == 1 && killer[a[i].first] && cntkiller == 1) printf( Truth n ); else if (a[i].second == 0 && killer[a[i].first] && cntkiller == 1) printf( Lie n ); else if (a[i].second == 1 && killer[a[i].first]) printf( Not defined n ); else if (a[i].second == 1 && !killer[a[i].first]) printf( Lie n ); else if (a[i].second == 0 && !killer[a[i].first]) printf( Truth n ); else printf( Not defined n ); } }
|
#include <bits/stdc++.h> using namespace std; int a[1000100], g[1000100]; int main() { for (int i = 1; i < 20; i++) { int msk = (1 << i) - 1; for (int j = (1 << i - 1); j < (1 << i); j++) { g[j] = (1 << i - 1) | g[j ^ msk]; } } int n, x; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } for (int i = 19; i >= 0; i--) { vector<int> v, piv; for (int j = 0; j < n; j++) { if (a[j] >= (1 << i)) continue; int x = a[j]; for (int k = 0; k < v.size(); k++) { if (x & (piv[k] & -piv[k])) x ^= piv[k]; } if (x > 0) { v.push_back(a[j]); piv.push_back(x); } } if (v.size() == i) { printf( %d n , i); for (int j = 0; j < (1 << i); j++) { int x = 0; for (int k = 0; k < i; k++) { if (g[j] & (1 << k)) x ^= v[k]; } printf( %d , x); } puts( ); break; } } return 0; }
|
module testbench();
localparam width_p = 8;
logic [width_p-1:0] li;
logic [`BSG_SAFE_CLOG2(width_p)-1:0] addr_lo;
logic v_lo;
bsg_priority_encode #(
.width_p(8)
,.lo_to_hi_p(1)
) pe (
.i(li)
,.addr_o(addr_lo)
,.v_o(v_lo)
);
initial begin
li = 8'b0;
#(10);
assert(v_lo == 1'b0);
assert(addr_lo == 8'b0);
li = 8'b1;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'b0);
li = 8'b11;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'b0);
li = 8'b10;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'b1);
li = 8'b100;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd2);
li = 8'b1000;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd3);
li = 8'b1000_0000;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd7);
li = 8'b1010_0000;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd5);
li = 8'b1011_0000;
#(10);
assert(v_lo == 1'b1);
assert(addr_lo == 8'd4);
end
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module fifo_2clock_cascade
#(parameter WIDTH=32, SIZE=9)
(input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o,
output [15:0] space, output [15:0] short_space,
input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i,
output [15:0] occupied, output [15:0] short_occupied,
input arst);
wire [WIDTH-1:0] data_int1, data_int2;
wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
wire [SIZE-1:0] level_wclk, level_rclk;
wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied;
wire [15:0] l_space, l_occupied;
fifo_short #(.WIDTH(WIDTH)) shortfifo
(.clk(wclk), .reset(arst), .clear(0),
.datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
.dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
.space(s1_space), .occupied(s1_occupied) );
fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
(.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
.rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
.arst(arst) );
fifo_short #(.WIDTH(WIDTH)) shortfifo2
(.clk(rclk), .reset(arst), .clear(0),
.datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
.dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
.space(s2_space), .occupied(s2_occupied));
// Be conservative -- Only advertise space from input side of fifo, occupied from output side
assign space = {11'b0,s1_space} + l_space;
assign occupied = {11'b0,s2_occupied} + l_occupied;
// For the fifo_extram, we only want to know the immediately adjacent space
assign short_space = {11'b0,s1_space};
assign short_occupied = {11'b0,s2_occupied};
endmodule // fifo_2clock_cascade
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_TB_V
`define SKY130_FD_SC_HVL__DLXTP_TB_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dlxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__dlxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_TB_V
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#include <bits/stdc++.h> using namespace std; int Solution() { int n; cin >> n; string s; cin >> s; int cnt = 0; for (int i = 0; i < n; ++i) cnt += (s[i] == H ); s += s; int ans = 0x7fffffff; for (int i = 0; i < n; ++i) { int dif = 0; for (int j = 0; j < cnt; ++j) if (s[i + j] != H ) ++dif; if (dif < ans) ans = dif; } cout << ans << endl; return 0; } int main() { Solution(); return 0; }
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