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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v; for (int i = 1; i * i <= n; i++) { if (n % i == 0) { v.push_back(i); if (i != n / i) { v.push_back(n / i); } } } sort(v.begin(), v.end()); int ans = 0; for (int i = v.size() - 1; i > -1; i--) { int p = v[i]; int q = 0; while (p % 2 == 0) { q++; p /= 2; } int r = pow(2, q + 1) + 0.5; r--; if (p == r) { ans = v[i]; break; } } cout << ans << endl; }
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// megafunction wizard: %LPM_MUX%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: counter_bus_mux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module counter_bus_mux (
data0x,
data1x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
// Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL "data0x[3..0]"
// Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL "data1x[3..0]"
// Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
// Retrieval info: CONNECT: @data 0 0 4 0 data0x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 4 data1x 0 0 4 0
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
// Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
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#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; else { return (gcd(b, (a % b))); } } int main() { int t; long long n; scanf( %d , &t); for (int i = 1; i <= t; i++) { cin >> n; long long a = (long long)4LL * n; long long b = (long long)(n + 1LL); long long res = gcd(a, b); res = (long long)(a) / res; cout << (res + 1) << endl; } return 0; }
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#include <bits/stdc++.h> const int inf = 1e5 + 10; const long long mod = 998244353; const int LARGEST = 0x3f3f3f3f; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int dx[] = {0, 1, 1, 1, 0, -1, -1, -1}; int dy[] = {1, 1, 0, -1, -1, -1, 0, 1}; int bx[] = {0, 1, 0, -1}; int by[] = {-1, 0, 1, 0}; using namespace std; int a[inf], stmin[inf][20], stmax[inf][20]; pair<int, int> q[inf]; int dp[inf]; int n, s, len, head, tail; int ask(int x, int y) { int tlen = log(y - x + 1) / log(2); int p = max(stmax[x][tlen], stmax[y - (1 << tlen) + 1][tlen]); int q = min(stmin[x][tlen], stmin[y - (1 << tlen) + 1][tlen]); return p - q; } int main() { ios::sync_with_stdio(0); cin >> n >> s >> len; for (int i = 1; i <= n; i++) { cin >> a[i]; stmax[i][0] = stmin[i][0] = a[i]; } for (int j = 1; j < 20; j++) for (int i = 1; i <= n; i++) if (i + (1 << (j - 1)) <= n) { stmax[i][j] = max(stmax[i][j - 1], stmax[i + (1 << (j - 1))][j - 1]); stmin[i][j] = min(stmin[i][j - 1], stmin[i + (1 << (j - 1))][j - 1]); } if (len > n || ask(1, len) > s) { cout << -1 << endl; return 0; } for (int i = 1; i <= n; i++) dp[i] = LARGEST; dp[0] = 0; dp[len] = 1; head = tail = 1; q[tail++] = make_pair(dp[0], 0); for (int i = len + 1; i <= n; i++) { int l = 1, r = i - len + 1, ans = -1; while (l < r) { int mid = (l + r) >> 1; if (ask(mid, i) <= s) r = ans = mid; else l = mid + 1; } if ((ask(l, i) <= s) && ans == -1) ans = l; else if (ans != -1 && (ask(l, i) <= s)) ans = min(ans, l); while (head < tail && q[tail - 1].first >= dp[i - len]) tail--; q[tail++] = make_pair(dp[i - len], i - len); if (ans != -1) { while (head < tail && q[head].second < ans - 1) head++; if (head < tail) dp[i] = min(dp[i], q[head].first + 1); } } if (dp[n] != LARGEST) cout << dp[n] << endl; else cout << -1 << endl; }
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//////////////////////////////////////////////////////////////////////
//// ////
//// eth_random.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
//
`include "timescale.v"
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;
wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg [9:0] RandomLatched;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
x[9:0] <= 0;
else
x[9:0] <= {x[8:0], Feedback};
end
assign Feedback = ~(x[2] ^ x[9]);
assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RandomLatched <= 10'h000;
else
begin
if(StateJam & StateJam_q)
RandomLatched <= Random;
end
end
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
endmodule
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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const int N = (int)1e6 + 7, mod = 1000000007, M = 2e9, lvl = 21; char s[N]; int n, c[10], x[4] = {1, 6, 8, 9}; vector<int> base, a; void push(int x) { a.push_back(x / 100); x %= 100; a.push_back(x / 10); x %= 10; a.push_back(x); } bool div7() { if (a.size() <= 4) { int ret = a.back(); a.pop_back(); if (a.empty()) return ret % 7 == 0; ret += a.back() * 10; a.pop_back(); if (a.empty()) return ret % 7 == 0; ret += a.back() * 100; a.pop_back(); if (a.empty()) return ret % 7 == 0; ret += a.back() * 1000; a.pop_back(); if (a.empty()) return ret % 7 == 0; } int t = a.back() * 2, bg; a.pop_back(); bg = a.back(); a.pop_back(); bg += a.back() * 10; a.pop_back(); bg += a.back() * 100; a.pop_back(); push(bg - t); return div7(); } void print() { for (int i : base) printf( %d , i); for (int i = 0; i < 4; i++) printf( %d , x[i]); while (c[0]--) printf( 0 ); exit(0); } int main() { scanf( %s , s); n = strlen(s); for (int i = 0; i < n; i++) c[s[i] - 0 ]++; c[1]--; c[6]--; c[8]--; c[9]--; for (int i = 1; i <= 9; i++) { while (c[i]--) base.push_back(i); } do { a.clear(); for (int i : base) a.push_back(i); for (int i = 0; i < 4; i++) a.push_back(x[i]); if (div7()) print(); n++; } while (next_permutation(x, x + 4)); puts( 0 ); return 0; }
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#include <bits/stdc++.h> using namespace std; using namespace std; int m, h, t, n, i, j, k; int a[200000], q[200000]; long long sum[200000], ans; long long pas[200000]; long long get(int i, int j) { return sum[j] - sum[i] + a[i]; } int main() { cin >> n; for (i = 0; i < n; i++) cin >> a[i]; cin >> m; for (i = 0; i < m; i++) cin >> q[i]; sort(a, a + n); sum[0] = a[0]; for (i = 1; i < n; i++) { sum[i] = sum[i - 1]; sum[i] += a[i]; } for (i = 1; i <= 100000; i++) { ans = 0; long long num = 0; long long freespace = i; for (j = n - 2; j >= 0;) { if (freespace > n * 10) freespace = n * 10; num++; long long l = j - freespace + 1; if (l < 0) l = 0; ans += num * get(l, j); j = j - freespace; freespace = freespace * i; } pas[i] = ans; } for (i = 0; i < m; i++) cout << pas[q[i]] << ; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1000 * 1000 * 1000 + 7LL; const double EXP = 1e-6; const int MAX = 100001; int main() { int n, k; while (cin >> n >> k) { int a[10001]; for (int i = 1; i <= n; i++) a[i] = 1; a[n] = 0; while (k--) { for (int i = 1; i <= n; i++) { if (a[i] + a[i] > n - i) { int p = n - i - a[i]; int o = n - p; a[i] += a[o]; cout << o << ; } else if (a[i] == n - i) cout << n << ; else { a[i] += a[i]; cout << i << ; } } cout << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_1_V
`define SKY130_FD_SC_LS__DLYMETAL6S4S_1_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s4s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlymetal6s4s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlymetal6s4s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlymetal6s4s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlymetal6s4s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlymetal6s4s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S4S_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_TB_V
`define SKY130_FD_SC_LS__DLXTP_TB_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ls__dlxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_TB_V
|
`timescale 1ns / 1ns
module computer;
// Inputs
reg clk50;
reg rst;
reg RxD;
// Outputs
wire sram_sramEnable_o;
wire sram_writeEnable_o;
wire sram_readEnable_o;
wire [19:0] sram_addr_o;
wire flash_flashByte_o;
wire flash_flashVpen_o;
wire flash_flashRP_o;
wire flash_flashSTS_o;
wire flash_flashEnable_o;
wire flash_flashCE1_o;
wire flash_flashCE2_o;
wire flash_readEnable_o;
wire flash_writeEnable_o;
wire [22:0] flash_addr_o;
wire TxD;
// Bidirs
wire [31:0] sram_data_io;
wire [15:0] flash_data_io;
// Instantiate the Unit Under Test (UUT)
cpu Lx (
.clk50(clk50),
.rst(rst),
.sram_sramEnable_o(sram_sramEnable_o),
.sram_writeEnable_o(sram_writeEnable_o),
.sram_readEnable_o(sram_readEnable_o),
.sram_addr_o(sram_addr_o),
.sram_data_io(sram_data_io),
.flash_flashByte_o(flash_flashByte_o),
.flash_flashVpen_o(flash_flashVpen_o),
.flash_flashRP_o(flash_flashRP_o),
.flash_flashSTS_o(flash_flashSTS_o),
.flash_flashEnable_o(flash_flashEnable_o),
.flash_flashCE1_o(flash_flashCE1_o),
.flash_flashCE2_o(flash_flashCE2_o),
.flash_readEnable_o(flash_readEnable_o),
.flash_writeEnable_o(flash_writeEnable_o),
.flash_addr_o(flash_addr_o),
.flash_data_io(flash_data_io),
.RxD(RxD),
.TxD(TxD)
);
sram SRAM (
.addr_i(sram_addr_o),
.en_i(sram_sramEnable_o),
.oe_i(sram_readEnable_o),
.we_i(sram_writeEnable_o),
.data_io(sram_data_io)
);
initial begin
// Initialize Inputs
clk50 = 0;
rst = 0;
RxD = 1;
// Wait 100 ns for global reset to finish
#100 rst = 1;
// Add stimulus here
end
initial begin
forever #1 clk50 = ~clk50;
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int N, K; cin >> N >> K; using arr2 = array<int, 2>; vector<arr2> binTrie; const int w = 30; binTrie.push_back({-1, -1}); vector<int> sz(1, 0); auto add = [&](int x) { int v = 0; for (int i = w - 1; i >= 0; --i) { int b = (x >> i) & 1; ++sz[v]; if (binTrie[v][b] >= 0) { v = binTrie[v][b]; continue; } int v_ = binTrie.size(); binTrie[v][b] = v_; binTrie.push_back({-1, -1}); sz.push_back(0); v = v_; } ++sz[v]; }; auto xor_lower_bound_size = [&](int x, int k) { int v = 0, ret = 0; for (int i = w - 1; i >= 0; --i) { int b = ((x ^ k) >> i) & 1; int t = (k >> i) & 1; if ((!t) and binTrie[v][b ^ 1] >= 0) ret += sz[binTrie[v][b ^ 1]]; if (binTrie[v][b] < 0) { v = -1; break; } v = binTrie[v][b]; } if (v >= 0) ret += sz[v]; return ret; }; vector<int> A(N + 1); for (int i = 0; i < N; ++i) { cin >> A[i + 1]; A[i + 1] ^= A[i]; } long long ans = 0; for (int i = 0; i <= N; ++i) { ans += xor_lower_bound_size(A[i], K); add(A[i]); } cout << ans << endl; }
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#include <bits/stdc++.h> long long dx[8] = {0, 1, 0, -1, 1, 1, -1, -1}; long long dy[8] = {1, 0, -1, 0, -1, 1, 1, -1}; using namespace std; class pa3 { public: long long x; long long y, z; pa3(long long x = 0, long long y = 0, long long z = 0) : x(x), y(y), z(z) {} bool operator<(const pa3 &p) const { if (x != p.x) return x < p.x; if (y != p.y) return y < p.y; return z < p.z; } bool operator>(const pa3 &p) const { if (x != p.x) return x > p.x; if (y != p.y) return y > p.y; return z > p.z; } bool operator==(const pa3 &p) const { return x == p.x && y == p.y && z == p.z; } bool operator!=(const pa3 &p) const { return !(x == p.x && y == p.y && z == p.z); } }; class pa4 { public: long long x; long long y, z, w; pa4(long long x = 0, long long y = 0, long long z = 0, long long w = 0) : x(x), y(y), z(z), w(w) {} bool operator<(const pa4 &p) const { if (x != p.x) return x < p.x; if (y != p.y) return y < p.y; if (z != p.z) return z < p.z; return w < p.w; } bool operator>(const pa4 &p) const { if (x != p.x) return x > p.x; if (y != p.y) return y > p.y; if (z != p.z) return z > p.z; return w > p.w; } bool operator==(const pa4 &p) const { return x == p.x && y == p.y && z == p.z && w == p.w; } }; class pa2 { public: long long x, y; pa2(long long x = 0, long long y = 0) : x(x), y(y) {} pa2 operator+(pa2 p) { return pa2(x + p.x, y + p.y); } pa2 operator-(pa2 p) { return pa2(x - p.x, y - p.y); } bool operator<(const pa2 &p) const { return y != p.y ? y < p.y : x < p.x; } bool operator>(const pa2 &p) const { return x != p.x ? x < p.x : y < p.y; } bool operator==(const pa2 &p) const { return abs(x - p.x) == 0 && abs(y - p.y) == 0; } bool operator!=(const pa2 &p) const { return !(abs(x - p.x) == 0 && abs(y - p.y) == 0); } }; string itos(long long i) { ostringstream s; s << i; return s.str(); } long long gcd(long long v, long long b) { if (v > b) return gcd(b, v); if (v == b) return b; if (b % v == 0) return v; return gcd(v, b % v); } long long mod; long long extgcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return a; } long long d = extgcd(b, a % b, y, x); y -= a / b * x; return d; } pair<long long, long long> operator+(const pair<long long, long long> &l, const pair<long long, long long> &r) { return {l.first + r.first, l.second + r.second}; } pair<long long, long long> operator-(const pair<long long, long long> &l, const pair<long long, long long> &r) { return {l.first - r.first, l.second - r.second}; } long long pr[1000010]; long long inv[1000010]; long long beki(long long wa, long long rr, long long warukazu) { if (rr == 0) return 1 % warukazu; if (rr == 1) return wa % warukazu; wa %= warukazu; if (rr % 2 == 1) return ((long long)beki(wa, rr - 1, warukazu) * (long long)wa) % warukazu; long long zx = beki(wa, rr / 2, warukazu); return (zx * zx) % warukazu; } long long comb(long long nn, long long rr) { if (rr < 0 || rr > nn || nn < 0) return 0; long long r = pr[nn] * inv[rr]; r %= mod; r *= inv[nn - rr]; r %= mod; return r; } void gya(long long ert) { pr[0] = 1; for (long long i = 1; i <= ert; i++) { pr[i] = (pr[i - 1] * i) % mod; } inv[ert] = beki(pr[ert], mod - 2, mod); for (long long i = ert - 1; i >= 0; i--) { inv[i] = inv[i + 1] * (i + 1) % mod; } } long long sita[1010]; long long oya[1010]; vector<long long> G[1010], H1[1010], H2[1010]; long long dfs1(long long r, long long p) { oya[r] = p; sita[r] = 1; for (auto v : G[r]) if (v != p) { sita[r] += dfs1(v, r); } return sita[r]; } long long dep[1011]; void dfs2(long long r, long long p, long long d = 1) { oya[r] = p; dep[r] = d; for (auto v : G[r]) if (v != p) { dfs2(v, r, d + 1); H1[r].push_back(v); } } void dfs3(long long r, long long p, long long d = 1) { oya[r] = p; dep[r] = d; for (auto v : G[r]) if (v != p) { dfs3(v, r, d + 1); H2[r].push_back(v); } } long long dp[1010][1010]; long long mae[1010][1011]; long long wei[1010]; signed main() { cin.tie(0); ios::sync_with_stdio(false); long long n; cin >> n; for (long long i = 0; i < n - 1; i++) { long long y, yy; cin >> y >> yy; G[y].push_back(yy); G[yy].push_back(y); } if (n == 1) { return 0; } if (n == 2) { cout << 1 2 1 << endl; return 0; } dfs1(1, 1); long long root = -1; for (long long i = 2; i <= n; i++) { long long wa = n - 1; bool ok = true; for (auto v : G[i]) if (v != oya[i]) { if (!(sita[v] <= n / 2)) ok = 0; wa -= sita[v]; } if (!ok) continue; if (wa <= n / 2) root = i; } if (root == -1) root = 1; dfs1(root, root); vector<pair<long long, long long> > ve; for (auto v : G[root]) ve.push_back({v, sita[v]}); long long m = ve.size(); dp[0][0] = 1; mae[0][0] = -1; for (long long i = 0; i < m; i++) { for (long long j = 0; j <= n; j++) if (dp[i][j]) { dp[i + 1][j] = 1; mae[i + 1][j] = mae[i][j]; dp[i + 1][j + ve[i].second] = 1; mae[i + 1][j + ve[i].second] = i; } } vector<long long> V1, V2; for (long long j = n / 2; j >= 0; j--) if (dp[m][j]) { long long imaval = j; long long imaind = m; while (1) { V1.push_back(ve[mae[imaind][imaval]].first); long long ee = imaval; imaval -= ve[mae[imaind][imaval]].second; imaind = mae[imaind][ee]; if (mae[imaind][imaval] == -1) break; } break; } for (auto v : ve) { bool bo = 0; for (auto w : V1) if (v.first == w) { bo = 1; break; } if (!bo) V2.push_back(v.first); } for (auto v : V1) dfs2(v, root), H1[root].push_back(v); for (auto v : V2) dfs3(v, root), H2[root].push_back(v); long long h1 = 0, h2 = 0; for (long long i = 1; i <= n; i++) h1 += H1[i].size(); for (long long i = 1; i <= n; i++) h2 += H2[i].size(); assert(h1 + h2 == n - 1); ve.clear(); for (long long i = 1; i <= n; i++) for (auto v : H1[i]) ve.push_back({dep[v], v}); sort(ve.begin(), ve.end()); for (long long i = 0; i < ve.size(); i++) { wei[ve[i].second] = (i + 1) * (h2 + 1); } ve.clear(); for (long long i = 1; i <= n; i++) for (auto v : H2[i]) ve.push_back({dep[v], v}); sort(ve.begin(), ve.end()); for (long long i = 0; i < ve.size(); i++) { wei[ve[i].second] = i + 1; } for (long long i = 1; i <= n; i++) if (i != root) { cout << i << << oya[i] << << wei[i] - wei[oya[i]] << endl; } for (long long i = 1; i <= n; i++) if (i != root) { } return 0; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input [2:0] vol_select,
input [8:0] dac_address_ext,
input play,
input reset,
input palmode,
output sdout,
output mclk_out,
output lrck_out,
output sclk_out,
output DAC_STATUS
);
reg[8:0] dac_address_r;
reg[8:0] dac_address_r_sync;
wire[8:0] dac_address = dac_address_r_sync;
wire[31:0] dac_data;
assign DAC_STATUS = dac_address_r[8];
reg[10:0] vol_reg;
reg[10:0] vol_target_reg;
reg[1:0] vol_latch_reg;
reg vol_valid;
reg[2:0] sysclk_sreg;
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
`ifdef MK2
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
`endif
`ifdef MK3
dac_buf snes_dac_buf (
.clock(clkin),
.wren(~we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [10 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(dac_address), // Bus [8 : 0]
.q(dac_data)); // Bus [31 : 0]
`endif
reg [10:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;
reg [15:0] smpshift;
wire mclk = cnt[2]; // mclk = clk/8
wire lrck = cnt[8]; // lrck = mclk/64
wire sclk = cnt[3]; // sclk = lrck*32
reg [2:0] mclk_sreg;
reg [2:0] lrck_sreg;
reg [1:0] sclk_sreg;
assign mclk_out = ~mclk_sreg[2];
assign lrck_out = lrck_sreg[2];
assign sclk_out = sclk_sreg[1];
wire lrck_rising = ({lrck_sreg[0],lrck} == 2'b01);
wire lrck_falling = ({lrck_sreg[0],lrck} == 2'b10);
wire sclk_rising = ({sclk_sreg[0],sclk} == 2'b01);
wire sclk_falling = ({sclk_sreg[0],sclk} == 2'b10);
wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
reg sdout_reg;
assign sdout = sdout_reg;
reg play_r;
initial begin
cnt = 9'h100;
smpcnt = 16'b0;
lrck_sreg = 2'b00;
sclk_sreg = 2'b00;
mclk_sreg = 2'b00;
dac_address_r = 9'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 9'h000;
vol_target_reg = 9'h000;
samples <= 2'b00;
end
/*
21477272.727272... / 37500 * 1232 = 44100 * 16
21281370 / 709379 * 23520 = 44100 * 16
*/
reg [19:0] phaseacc = 0;
wire [14:0] phasemul = (palmode ? 23520 : 1232);
wire [19:0] phasediv = (palmode ? 709379 : 37500);
reg [3:0] subcount = 0;
reg int_strobe = 0, comb_strobe = 0;
always @(posedge clkin) begin
int_strobe <= 0;
comb_strobe <= 0;
if(reset) begin
dac_address_r <= dac_address_ext;
phaseacc <= 0;
subcount <= 0;
end else if(sysclk_rising) begin
if(phaseacc >= phasediv) begin
phaseacc <= phaseacc - phasediv + phasemul;
subcount <= subcount + 1;
int_strobe <= 1;
if (subcount == 0) begin
comb_strobe <= 1;
dac_address_r <= dac_address_r + play_r;
end
end else begin
phaseacc <= phaseacc + phasemul;
end
end
end
parameter ST0_IDLE = 10'b1000000000;
parameter ST1_COMB1 = 10'b0000000001;
parameter ST2_COMB2 = 10'b0000000010;
parameter ST3_COMB3 = 10'b0000000100;
parameter ST4_INT1 = 10'b0000010000;
parameter ST5_INT2 = 10'b0000100000;
parameter ST6_INT3 = 10'b0001000000;
reg [63:0] ci[2:0], co[2:0], io[2:0];
reg [9:0] cicstate = 10'h200;
wire [63:0] bufi = {{16{dac_data[31]}}, dac_data[31:16], {16{dac_data[15]}}, dac_data[15:0]};
always @(posedge clkin) begin
if(reset) begin
cicstate <= ST0_IDLE;
{ci[2], ci[1], ci[0]} <= 192'h0;
{co[2], co[1], co[0]} <= 192'h0;
{io[2], io[1], io[0]} <= 192'h0;
end else if(int_strobe) begin
if(comb_strobe) cicstate <= ST1_COMB1;
else cicstate <= ST4_INT1;
end else begin
case(cicstate)
/****** COMB STAGES ******/
ST1_COMB1: begin
cicstate <= ST2_COMB2;
ci[0] <= bufi;
co[0][63:32] <= bufi[63:32] - ci[0][63:32];
co[0][31:0] <= bufi[31:0] - ci[0][31:0];
end
ST2_COMB2: begin
cicstate <= ST3_COMB3;
ci[1] <= co[0];
co[1][63:32] <= co[0][63:32] - ci[1][63:32];
co[1][31:0] <= co[0][31:0] - ci[1][31:0];
end
ST3_COMB3: begin
cicstate <= ST4_INT1;
ci[2] <= co[1];
co[2][63:32] <= co[1][63:32] - ci[2][63:32];
co[2][31:0] <= co[1][31:0] - ci[2][31:0];
end
/****** INTEGRATOR STAGES ******/
ST4_INT1: begin
io[0][63:32] <= co[2][63:32] + io[0][63:32];
io[0][31:0] <= co[2][31:0] + io[0][31:0];
cicstate <= ST5_INT2;
end
ST5_INT2: begin
io[1][63:32] <= io[0][63:32] + io[1][63:32];
io[1][31:0] <= io[0][31:0] + io[1][31:0];
cicstate <= ST6_INT3;
end
ST6_INT3: begin
io[2][63:32] <= io[1][63:32] + io[2][63:32];
io[2][31:0] <= io[1][31:0] + io[2][31:0];
cicstate <= ST0_IDLE;
end
default: begin
cicstate <= ST0_IDLE;
end
endcase
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
mclk_sreg <= {mclk_sreg[1:0], mclk};
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
end
wire [9:0] vol_orig = volume + volume[7];
wire [9:0] vol_3db = volume + volume[7:1] + volume[7];
wire [9:0] vol_6db = {1'b0, volume, volume[7]} + volume[7];
wire [9:0] vol_9db = {1'b0, volume, 1'b0} + volume + volume[7:6];
wire [9:0] vol_12db = {volume, volume[7:6]};
reg [9:0] vol_scaled;
always @* begin
case(vol_select)
3'b000: vol_scaled = vol_orig;
3'b001: vol_scaled = vol_3db;
3'b010: vol_scaled = vol_6db;
3'b011: vol_scaled = vol_9db;
3'b100: vol_scaled = vol_12db;
default: vol_scaled = vol_orig;
endcase
end
always @(posedge clkin) begin
vol_target_reg <= vol_scaled;
end
always @(posedge clkin) begin
if (lrck_rising) begin
dac_address_r_sync <= dac_address_r;
end
end
// ramp volume only on sample boundaries
always @(posedge clkin) begin
if (lrck_rising) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
wire signed [15:0] dac_data_ch = lrck ? io[2][59:44] : io[2][27:12];
wire signed [25:0] vol_sample;
wire signed [15:0] vol_sample_sat;
assign vol_sample = dac_data_ch * $signed({1'b0, vol_reg});
assign vol_sample_sat = ((vol_sample[25:23] == 3'b000 || vol_sample[25:23] == 3'b111) ? vol_sample[23:8]
: vol_sample[25] ? 16'sh8000
: 16'sh7fff);
always @(posedge clkin) begin
if (sclk_falling) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
if (lrck_rising | lrck_falling) begin
smpshift <= vol_sample_sat;
end else begin
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
endmodule
|
#include <bits/stdc++.h> const int maxn = 2e3 + 5; using namespace std; int arr[maxn]; int dp[maxn][maxn]; int check(int x, int lef, int rig) { return (lef <= x && x <= rig ? 1 : 0); } int main() { int n, h, l, r; scanf( %d %d %d %d , &n, &h, &l, &r); for (int i = 1; i <= n; i++) { scanf( %d , &arr[i]); } memset((dp), (-1), sizeof(dp)); dp[0][0] = 0; for (int i = 1; i <= n; i++) { for (int j = 0; j < h; j++) { if (dp[i - 1][j] != -1) { dp[i][(j + arr[i]) % h] = max(dp[i - 1][j] + check((j + arr[i]) % h, l, r), dp[i][(j + arr[i]) % h]); dp[i][(j + arr[i] - 1) % h] = max(dp[i - 1][j] + check((j + arr[i] - 1) % h, l, r), dp[i][(j + arr[i] - 1) % h]); } } } int ans = -1; for (int i = 0; i < h; i++) { ans = max(ans, dp[n][i]); } printf( %d n , ans); return 0; }
|
/* Semi Dual Port (SDP) memory have the following configurations:
* Memory Config RAM(BIT) Port Mode Memory Depth Data Depth
* ----------------|---------| ----------|--------------|------------|
* B-SRAM_16K_SD1 16K 16Kx1 16,384 1
* B-SRAM_8K_SD2 16K 8Kx2 8,192 2
* B-SRAM_4K_SD4 16K 4Kx2 4,096 4
*/
module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 16;
parameter CFG_ENABLE_A = 1;
parameter [16383:0] INIT = 16384'hx;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input [CFG_ENABLE_A-1:0] A1EN;
input [CFG_ABITS-1:0] B1ADDR;
output [CFG_DBITS-1:0] B1DATA;
input B1EN;
wire [31-CFG_DBITS:0] open;
generate if (CFG_DBITS == 1) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(1),
.BIT_WIDTH_1(1),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
.WREB(1'b0), .CEB(B1EN),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS == 2) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(2),
.BIT_WIDTH_1(2),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
.WREB(1'b0), .CEB(B1EN),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS <= 4) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(4),
.BIT_WIDTH_1(4),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(A1EN), .OCE(1'b0),
.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS <= 8) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(8),
.BIT_WIDTH_1(8),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
.WREB(1'b0), .CEB(B1EN),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS <= 16) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(16),
.BIT_WIDTH_1(16),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(|A1EN), .OCE(1'b0),
.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, A1EN}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS <= 32) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(32),
.BIT_WIDTH_1(32),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(|A1EN), .OCE(1'b0),
.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI(A1DATA),
.DO(B1DATA),
.ADA({A1ADDR, {(10-CFG_ABITS){1'b0}}, A1EN}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else begin
wire TECHMAP_FAIL = 1'b1;
end endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; int ar[305][305]; vector<pair<int, int> > poss[90005]; int dp[305][305]; vector<int> col[305]; int vis[305]; int n, m, p; void pr() {} void solve() { memset(dp, 127, sizeof(dp)); ; scanf( %d %d %d , &n, &m, &p); for (int i = 0; i < (int)(n); i++) { for (int j = 0; j < (int)(m); j++) { scanf( %d , &ar[i][j]); poss[ar[i][j]].push_back(make_pair(i, j)); if (ar[i][j] == 1) { dp[i][j] = i + j; } } } for (int val = 2; val <= p; val++) { memset(vis, 0, sizeof(vis)); ; for (int i = 0; i < (int)(m); i++) { col[i].clear(); } for (int i = 0; i < poss[val].size(); i++) { pair<int, int> a = poss[val][i]; col[a.second].push_back(a.first); } for (int i = 0; i < poss[val - 1].size(); i++) { pair<int, int> a = poss[val - 1][i]; vis[a.first] = 1; } for (int i = 0; i < n; i++) { if (!vis[i]) continue; int best = 1e9; for (int j = 0; j < m; j++) { best++; if (ar[i][j] == val - 1) best = min(best, dp[i][j]); for (int k = 0; k < col[j].size(); k++) { dp[col[j][k]][j] = min(dp[col[j][k]][j], best + abs(col[j][k] - i)); } } best = 1e9; for (int j = m; j >= 0; j--) { best++; if (ar[i][j] == val - 1) best = min(best, dp[i][j]); for (int k = 0; k < col[j].size(); k++) { dp[col[j][k]][j] = min(dp[col[j][k]][j], best + abs(col[j][k] - i)); } } } } printf( %d , dp[poss[p][0].first][poss[p][0].second]); } int main() { int TC = 1; for (int ZZ = 1; ZZ <= TC; ZZ++) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_SYMBOL_V
`define SKY130_FD_SC_LP__CLKINV_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void qmax(int &x, int y) { if (x < y) x = y; } void qmin(int &x, int y) { if (x > y) x = y; } inline long long read() { char s; long long k = 0, base = 1; while ((s = getchar()) != - && s != EOF && !(isdigit(s))) ; if (s == EOF) exit(0); if (s == - ) base = -1, s = getchar(); while (isdigit(s)) { k = k * 10 + (s ^ 0 ); s = getchar(); } return k * base; } inline void write(int x) { static char cnt, num[15]; cnt = 0; if (!x) { printf( 0 ); return; } for (; x; x /= 10) num[++cnt] = x % 10; for (; cnt; putchar(num[cnt--] + 48)) ; } const int maxn = 1e5 + 100; int a[maxn]; int n, l, r, l1, r1, la, ra; int q(int x) { printf( ? %d n , x); fflush(stdout); int y; scanf( %d , &y); return y; } void ret(int x) { printf( ! %d n , x); fflush(stdout); exit(0); } int main() { n = read(); if ((n / 2) % 2 == 1) { ret(-1); return 0; } memset(a, 0x3f3f3f3f, sizeof(a)); l = 1, r = n / 2; la = q(l); ra = q(n / 2 + l); if (la == ra) { ret(l); return 0; } int mdl, mdr, mda, mdb; while (l <= r) { mdl = (l + r) / 2; mdr = mdl + n / 2; mda = q(mdl); mdb = q(mdr); if (mda == mdb) { ret(mdl); return 0; } if ((la < ra) ^ (mda < mdb)) r = mdl - 1; else l = mdl + 1; } ret(-1); return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long n; long long len[1000005]; long long pai[1000005]; string s; long long find(long long x) { if (pai[x] == x) return x; return pai[x] = find(pai[x]); } void merge(long long a, long long b) { long long paiA = find(a), paiB = find(b); pai[paiB] = paiA; } int32_t main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(0); cin >> n >> s; long long p = 0, b = 0; pai[0] = 0; for (long long i = 1; i <= n; i++) { pai[i] = i; if (s[i - 1] == 1 ) { p++; b = 0; } else if (s[i - 1] == 0 ) { b++; p = 0; } else { p++, b++; } len[i - 1] = max(p, b); } for (long long i = 1; i <= n; i++) { long long res = 0, pos = 0; while (pos < n) { pos += i - 1; while (pos < n and len[pos] < i) { merge(pos + 1, pos); pos = find(pos); } if (pos >= n) break; pos++; res++; } cout << res << ; } cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int const MAX = 2005; int mp[MAX][MAX]; int main() { int n; bool flag = true; scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &mp[i][j]); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (mp[i][i] || mp[i][j] != mp[j][i] || (i != j && !mp[i][j])) { printf( NO n ); return 0; } } } for (int i = 1; i <= n; i++) { int u = 1; for (int j = 1; j <= n; j++) { if (i == j) continue; if (mp[i][j] < mp[i][u]) u = j; } for (int j = 1; j <= n; j++) { if (i == j) continue; if (abs(mp[i][j] - mp[j][u]) != mp[i][u]) { printf( NO n ); return 0; } } } printf( YES n ); }
|
#include <bits/stdc++.h> using namespace std; int main() { int W, H, n; scanf( %d%d%d , &W, &H, &n); multiset<int> w, h; w.insert(-W); h.insert(-H); set<int> wa, ha; wa.insert(0); wa.insert(W); ha.insert(0); ha.insert(H); for (int i = 0; i < n; i++) { char t; int x; scanf( n%c%d , &t, &x); if (t == H ) { auto r = ha.lower_bound(x); auto l = r; l--; h.erase(h.find((*l) - (*r))); ha.insert(x); h.insert((*l) - x); h.insert(x - (*r)); } else if (t == V ) { auto r = wa.lower_bound(x); auto l = r; l--; w.erase(w.find((*l) - (*r))); wa.insert(x); w.insert((*l) - x); w.insert(x - (*r)); } printf( %lld n , 1ll * (*h.begin()) * (*w.begin())); } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, x, y, z, f[1000000], k, ans = 0, a, b, c, t; vector<long long> v; map<long long, long long> m; int main() { cin >> n >> a >> b >> c >> t; for (int i = 0; i < n; i++) cin >> f[i]; sort(f, f + n); for (int i = 0; i < n; i++) { x = a; k = (t - f[i]) * c; k -= (t - f[i]) * b; k += a; x = max(x, k); ans += x; } cout << ans; return 0; }
|
//
// PCI Parity Generator.
//
// PCI Target generates PAR in the data phase of a read cycle.
// The 1's sum on AD, CBE and PAR is even.
//
// Date Version Author Description
// 2005-05-13 R00A00 PAU First alfa revision (eng)
//
// Copyright (C) 2005 Peio Azkarate,
//
// This source file is free software; you can redistribute it |
// and/or modify it under the terms of the GNU Lesser General |
// Public License as published by the Free Software Foundation; |
// either version 2.1 of the License, or (at your option) any |
// later version. |
module pcipargen_new (clk_i, pcidatout_i, cbe_i, parOE_i, par_o);
input clk_i;
input [31:0] pcidatout_i;
input [3:0] cbe_i;
input parOE_i;
output par_o;
wire [31:0] d;
wire pardat;
wire parcbe;
wire par;
wire par_s;
assign d = pcidatout_i;
assign pardat = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^
d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^
d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^
d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
assign parcbe = cbe_i[0] ^ cbe_i[1] ^ cbe_i[2] ^ cbe_i[3];
assign par = pardat ^ parcbe;
// PAR
assign par_o = ( parOE_i == 1 ) ? par_s : 1'bZ;
endmodule
/*
component sync
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component sync2
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
begin
u1: sync2 port map (
clk => clk_i,
d => par,
q => par_s
);
end rtl;
*/
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#include <bits/stdc++.h> using namespace std; void init_code() { ios_base::sync_with_stdio(false); cin.tie(NULL); } int main() { init_code(); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> arr(n + 1, 0); map<int, int> mp; for (int i = 1; i <= n; ++i) { cin >> arr[i]; mp[arr[i]] += 1; } int res = 0, shifts = 0; for (int i = 1; i <= n; ++i) { if (arr[i] > i + shifts) { int diff = arr[i] - i - shifts; res += diff; shifts += diff; } } cout << res << n ; } return 0; }
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#include <bits/stdc++.h> int a[1010], b[1010]; int n, k, inf = 0x0f0f0f0f; int test(int cur) { int i, ans = 0; if (cur <= 0) return inf; for (i = 0; i < n; i++) { if (a[i] != cur) ans++; cur += k; } return ans; } int main() { int i, j, cur; while (~scanf( %d%d , &n, &k)) { for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < n; i++) b[i] = test(a[i] - i * k); for (i = 1, j = 0; i < n; i++) if (b[i] < b[j]) j = i; printf( %d n , b[j]); cur = a[j] - k * j; for (i = 0; i < n; i++) { if (a[i] != cur) { if (a[i] < cur) printf( + %d %d n , i + 1, cur - a[i]); else printf( - %d %d n , i + 1, a[i] - cur); } cur += k; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
/**
* udp_dff$NR_pp$PKG$sN: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$NR_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int k = 0; string a, b, c; cin >> a >> b >> c; for (int i = 0; i < a.size(); i++) { if (a[i] == c[i] || b[i] == c[i]) k++; else { k = -1; break; } } if (k == a.size()) cout << YES << endl; else cout << NO << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 100000 + 77, L = 17; int n, q, tim = 1, root = 1; int b[N], d[N], Par[N][L], St[N], En[N]; long long S[N << 2], lz[N << 2]; inline void Shift(int l, int r, int id) { long long x = lz[id]; lz[id] = 0; S[id] += (r - l) * x; if (r - l > 1) lz[id << 1] += x, lz[id << 1 ^ 1] += x; } void Add(int ql, int qr, int x, int l = 1, int r = n + 1, int id = 1) { Shift(l, r, id); if (qr <= l || r <= ql) return; if (ql <= l && r <= qr) { lz[id] += x; Shift(l, r, id); return; } int mid = ((l + r) >> 1); Add(ql, qr, x, l, mid, id << 1); Add(ql, qr, x, mid, r, id << 1 ^ 1); S[id] = S[id << 1] + S[id << 1 ^ 1]; } long long Get(int ql, int qr, int l = 1, int r = n + 1, int id = 1) { Shift(l, r, id); if (qr <= l || r <= ql) return 0; if (ql <= l && r <= qr) return S[id]; int mid = ((l + r) >> 1); return Get(ql, qr, l, mid, id << 1) + Get(ql, qr, mid, r, id << 1 ^ 1); } vector<int> a[N]; void dfs(int v = 1) { St[v] = tim++; for (int i = 1; i < L; ++i) Par[v][i] = Par[Par[v][i - 1]][i - 1]; for (int u : a[v]) { if (u == Par[v][0]) continue; Par[u][0] = v; d[u] = d[v] + 1; dfs(u); } En[v] = tim; } inline bool isPar(int v, int u) { return St[v] <= St[u] && En[u] <= En[v]; } inline int GetPar(int v, int k) { for (int i = 0; i < L; ++i) if (k & (1 << i)) v = Par[v][i]; return v; } inline int GetLca(int v, int u) { if (d[v] < d[u]) swap(v, u); v = GetPar(v, d[v] - d[u]); if (v == u) return v; for (int i = L - 1; i >= 0; --i) if (Par[v][i] != Par[u][i]) v = Par[v][i], u = Par[u][i]; return Par[v][0]; } inline int GetLca(int r, int v, int u) { int t = GetLca(v, u); if (isPar(r, t)) return t; if (isPar(r, u) || isPar(r, v)) return r; if (!isPar(t, r)) return t; int x = GetLca(r, v); int y = GetLca(r, u); return (d[x] > d[y] ? x : y); } inline void Update(int r, int v, int u, int x) { int t = GetLca(r, v, u); if ((!isPar(t, r))) { Add(St[t], En[t], x); return; } Add(1, n + 1, x); if (r == t) return; int p = GetPar(r, d[r] - d[t] - 1); Add(St[p], En[p], -x); } inline long long GetSum(int r, int v) { if (!isPar(v, r)) return Get(St[v], En[v]); long long res = Get(1, n + 1); if (r == v) return res; int p = GetPar(r, d[r] - d[v] - 1); res -= Get(St[p], En[p]); return res; } int main() { scanf( %d %d , &n, &q); for (int i = 1; i <= n; ++i) scanf( %d , b + i); for (int v, u, i = 1; i < n; ++i) scanf( %d %d , &v, &u), a[v].push_back(u), a[u].push_back(v); d[1] = 1; dfs(); for (int i = 1; i <= n; ++i) Add(St[i], St[i] + 1, b[i]); while (q--) { int tp, v, u, x; scanf( %d %d , &tp, &v); if (tp == 1) { root = v; } else if (tp == 2) { scanf( %d %d , &u, &x); Update(root, v, u, x); } else { printf( %lld n , GetSum(root, v)); } } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const double PI = 3.14159265359; int oneCt = 0, n; class File { public: string name; int type; bool isNum; int numVal; File(string _name, int _type) : name(_name), type(_type), isNum(true) { int sz = name.size(); string s = name; numVal = 0; if (s[0] == 0 ) { isNum = false; } else { for (int i = sz - 1, mult = 1; i >= 0; i--, mult *= 10) { if (s[i] >= 0 && s[i] <= 9 ) { numVal += mult * (s[i] - 0 ); } else { isNum = false; } } } } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; vector<bool> avail(n + 1, true); vector<File> files; for (int i = 0; i < n; i++) { int x; string s; cin >> s >> x; oneCt += x; File f(s, x); files.push_back(f); } vector<File> ob, zb; for (auto f : files) { if (f.isNum) { int nv = f.numVal; if (nv <= n) avail[nv] = false; if (nv > oneCt && f.type) ob.push_back(f); else if (!f.type && (nv <= oneCt || nv > n)) { zb.push_back(f); } } else if (f.type) ob.push_back(f); else zb.push_back(f); } vector<string> operations; queue<File> qob, qob2, qzb, qzb2; for (auto f : ob) { if (f.isNum && f.numVal > oneCt && f.numVal <= n) { qob.push(f); } else { qob2.push(f); } } while (qob2.size()) { qob.push(qob2.front()); qob2.pop(); } for (auto f : zb) { if (f.isNum && f.numVal <= oneCt) { qzb.push(f); } else { qzb2.push(f); } } while (qzb2.size()) { qzb.push(qzb2.front()); qzb2.pop(); } stack<int> oneAvail, zeroAvail; for (int i = 1; i <= n; i++) { if (i <= oneCt && avail[i]) oneAvail.push(i); else if (i > oneCt && avail[i]) zeroAvail.push(i); } while (qob.size() || qzb.size()) { if (qob.size() && oneAvail.size()) { auto f = qob.front(); if (f.isNum && f.numVal <= n) { zeroAvail.push(f.numVal); } string s = move ; s += f.name; s += ; s += to_string(oneAvail.top()); operations.push_back(s); qob.pop(); oneAvail.pop(); } else if (qzb.size() && zeroAvail.size()) { auto f = qzb.front(); if (f.isNum && f.numVal <= oneCt) { oneAvail.push(f.numVal); } string s = move ; s += f.name; s += ; s += to_string(zeroAvail.top()); operations.push_back(s); qzb.pop(); zeroAvail.pop(); } else { auto f = qob.front(); if (f.isNum && f.numVal <= n) { zeroAvail.push(f.numVal); } string s = move ; s += f.name; s += aaaaaa ; operations.push_back(s); f.name = aaaaaa ; f.isNum = false; qob.pop(); qob.push(f); } } cout << operations.size() << endl; for (string s : operations) { cout << s << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long mul(long long a, long long b, long long p = 1000000007) { return ((a % p) * (b % p)) % p; } long long add(long long a, long long b, long long p = 1000000007) { return (a % p + b % p) % p; } void input(long long a[], long long sz) { for (long long i = 0; i < sz; i++) cin >> a[i]; } void print(long long a[], long long sz) { for (long long i = 0; i < sz; i++) { if (i == sz - 1) cout << a[i] << n ; else cout << a[i] << ; } } long long maxr(long long a[], long long sz) { long long ma; for (long long i = 0; i < sz; i++) { if (i == 0) ma = a[i]; else if (a[i] > ma) ma = a[i]; } return ma; } long long minr(long long a[], long long sz) { long long mi; for (long long i = 0; i < sz; i++) { if (i == 0) mi = a[i]; else if (a[i] < mi) mi = a[i]; } return mi; } long long isprm(long long n) { if (n <= 1) return 0; if (n <= 3) return 1; if (n % 2 == 0 || n % 3 == 0) return 0; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return 0; return 1; } long long power(long long x, long long y, long long p = 1000000007) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long modInverse(long long n, long long p = 1000000007) { return power(n, p - 2, p); } long long ncrMod(long long n, long long r, long long p = 1000000007) { if (r == 0) return 1; long long fac[n + 1]; fac[0] = 1; for (long long i = 1; i <= n; i++) fac[i] = fac[i - 1] * i % p; return (fac[n] * modInverse(fac[r], p) % p * modInverse(fac[n - r], p) % p) % p; } struct comp { bool operator()(const pair<long long, long long> &a, const pair<long long, long long> &b) const { if (a.first == b.first) { return (a.second > b.second); } return (a.first < b.first); } }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t; cin >> t; while (t--) { long long n, q; cin >> n >> q; long long a[n + 5]; input(a, n); if (n == 1) { cout << a[0] << n ; for (long long i = 0; i < q; i++) { long long l, r; cin >> l >> r; cout << a[0] << n ; } continue; } map<long long, long long> mp; long long ans = 0; long long k = 0; for (long long i = 0; i < n; i++) { if (k % 2 == 0) { if ((i - 1) >= 0 && (i + 1) < n && a[i] > a[i - 1] && a[i] > a[i + 1]) { ans += a[i]; mp[i] = 1; k++; } else if ((i - 1) < 0 && a[i] > a[i + 1]) { ans += a[i]; mp[i] = 1; k++; } else if ((i + 1) >= n && a[i] > a[i - 1]) { ans += a[i]; mp[i] = 1; k++; } } else { if ((i - 1) >= 0 && (i + 1) < n && a[i] < a[i - 1] && a[i] < a[i + 1]) { ans -= a[i]; mp[i] = -1; k++; } } } if (k % 2 == 0) { auto it = mp.end(); it--; long long i = (*it).first; ans += a[i]; mp.erase(it); } cout << ans << n ; for (long long i = 0; i < q; i++) { long long l, r; cin >> l >> r; l--; r--; long long x = max(l - 1, (long long)0); long long y = min(l + 1, n - 1); for (long long i = x; i < y + 1; i++) { if (mp[i] == 1) ans -= a[i]; else if (mp[i] == -1) ans += a[i]; else mp.erase(i); } x = max(r - 1, y + 1); y = min(r + 1, n - 1); for (long long i = x; i < y + 1; i++) { if (mp[i] == 1) ans -= a[i]; else if (mp[i] == -1) ans += a[i]; else mp.erase(i); } long long t = a[l]; a[l] = a[r]; a[r] = t; x = max(l - 1, (long long)0); y = min(l + 1, n - 1); long long h; auto it = mp.lower_bound(x); if (it == mp.end()) { it--; h = (*it).second; if (h == 1) h = -1; else h = 1; } else { h = (*it).second; } for (long long i = x; i < y + 1; i++) { if (h == 1) { if ((i - 1) >= 0 && (i + 1) < n && a[i] > a[i - 1] && a[i] > a[i + 1]) { ans += a[i]; mp[i] = 1; h = -1; } else if ((i - 1) < 0 && a[i] > a[i + 1]) { ans += a[i]; mp[i] = 1; h = -1; } else if ((i + 1) >= n && a[i] > a[i - 1]) { ans += a[i]; mp[i] = 1; h = -1; } else mp.erase(i); } else { if ((i - 1) >= 0 && (i + 1) < n && a[i] < a[i - 1] && a[i] < a[i + 1]) { ans -= a[i]; mp[i] = -1; h = 1; } else mp.erase(i); } } x = max(r - 1, y + 1); y = min(r + 1, n - 1); auto it2 = mp.lower_bound(x); if (it2 == mp.begin()) { h = 1; } else { it2--; h = (*it2).second; if (h == 1) h = -1; else h = 1; } for (long long i = x; i < y + 1; i++) { if (h == 1) { if ((i - 1) >= 0 && (i + 1) < n && a[i] > a[i - 1] && a[i] > a[i + 1]) { ans += a[i]; mp[i] = 1; h = -1; } else if ((i - 1) < 0 && a[i] > a[i + 1]) { ans += a[i]; mp[i] = 1; h = -1; } else if ((i + 1) >= n && a[i] > a[i - 1]) { ans += a[i]; mp[i] = 1; h = -1; } else mp.erase(i); } else { if ((i - 1) >= 0 && (i + 1) < n && a[i] < a[i - 1] && a[i] < a[i + 1]) { ans -= a[i]; mp[i] = -1; h = 1; } else mp.erase(i); } } if (mp.size() % 2 == 0 && mp.size() > 0) { auto it = mp.end(); it--; long long i = (*it).first; ans += a[i]; mp.erase(it); } cout << ans << n ; } } return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// ======================================================================
module sub
(
input clk,
input fastclk,
input reset_l
);
// Example counter/flop
reg [31:0] count_f;
always_ff @ (posedge fastclk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_f <= 32'h0;
// End of automatics
end
else begin
count_f <= count_f + 1;
end
end
// Another example flop
reg [31:0] count_c;
always_ff @ (posedge clk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_c <= 32'h0;
// End of automatics
end
else begin
count_c <= count_c + 1;
if (count_c >= 3) begin
$display("[%0t] fastclk is %0d times faster than clk\n",
$time, count_f/count_c);
// This write is a magic value the Makefile uses to make sure the
// test completes successfully.
$write("*-* All Finished *-*\n");
$finish;
end
end
end
// An example assertion
always_ff @ (posedge clk) begin
AssertionExample: assert(!reset_l || count_c<100);
end
// And example coverage analysis
cover property (@(posedge clk) count_c==3);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; struct node { double x, y; } po[1010]; double dis(node a, node b) { return sqrt((a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y)); } node mark; double cha(node a, node b, node c) { return (b.x - a.x) * (c.y - a.y) - (c.x - a.x) * (b.y - a.y); } double get(node a, node b, node c) { return abs(cha(a, b, c)) / dis(a, b) / 2.0; } int main() { int n; cin >> n; double ans = 1e9; for (int i = (0); i < (n); ++i) cin >> po[i].x >> po[i].y; for (int i = (0); i < (n); ++i) { ans = min(ans, get(po[(i - 1 + n) % n], po[(i + 1) % n], po[i])); } cout << fixed << setprecision(10) << ans << n ; }
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//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_charToTransmitter (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (a == 0) { return b; } else { return gcd(b % a, a); } } long long int lcm(long long int a, long long int b) { return a * b / gcd(a, b); } int f(char c) { return (int)c - 48; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int t; cin >> t; while (t--) { long long int n, x; cin >> n >> x; long long int a[1005]; long long int sum = 0; long long int count = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; sum += (a[i] - x); if (a[i] == x) { count++; } } if (count == n) { cout << 0 << endl; } else if (count > 0) { cout << 1 << endl; } else if (sum == 0) { cout << 1 << endl; } else { cout << 2 << endl; } } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_misc_chunk5.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_misc_chunk5(clk ,sel_bypass ,spare_misc_pad ,
spare_misc_paddata ,obsel ,io_tdo_en ,ckd ,vref ,vddo ,io_tdo ,
rst_val_up ,io_tdi ,mode_ctl ,rst_val_dn ,io_trst_l ,bsi ,io_tck ,
clock_dr ,tck ,shift_dr ,trst_l ,hiz_l ,tdi ,update_dr ,rst_io_l ,
por_l ,tdo ,se ,si ,reset_l ,so ,bso ,spare_misc_padoe ,
spare_misc_pad_to_core );
output [2:1] spare_misc_pad_to_core ;
input [2:1] spare_misc_paddata ;
input [5:4] obsel ;
input [2:1] spare_misc_padoe ;
inout [2:1] spare_misc_pad ;
output io_tdi ;
output io_trst_l ;
output io_tck ;
output so ;
output bso ;
input clk ;
input sel_bypass ;
input io_tdo_en ;
input ckd ;
input vref ;
input vddo ;
input io_tdo ;
input rst_val_up ;
input mode_ctl ;
input rst_val_dn ;
input bsi ;
input clock_dr ;
input shift_dr ;
input hiz_l ;
input update_dr ;
input rst_io_l ;
input por_l ;
input se ;
input si ;
input reset_l ;
inout tck ;
inout trst_l ;
inout tdi ;
inout tdo ;
supply0 vss ;
wire bscan_spare1_spare2 ;
wire net133 ;
wire bscan_spare2_spare1 ;
wire net084 ;
bw_io_cmos2_pad tdo_pad (
.oe (io_tdo_en ),
.vddo (vddo ),
.data (io_tdo ),
.to_core (net133 ),
.pad (tdo ),
.por_l (por_l ) );
bw_u1_ckbuf_40x Iclkbuf_5 (
.clk (net084 ),
.rclk (clk ) );
bw_io_hstl_pad spare_misc_pad_2_pad (
.obsel ({obsel } ),
.so (so ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net084 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_spare2_spare1 ),
.bsr_si (bsi ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (bscan_spare1_spare2 ),
.oe (spare_misc_padoe[2] ),
.data (spare_misc_paddata[2] ),
.se (se ),
.to_core (spare_misc_pad_to_core[2] ),
.por_l (por_l ),
.pad (spare_misc_pad[2] ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_hstl_pad spare_misc_pad_1_pad (
.obsel ({obsel } ),
.so (bscan_spare1_spare2 ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net084 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bso ),
.bsr_si (bscan_spare2_spare1 ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (si ),
.oe (spare_misc_padoe[1] ),
.data (spare_misc_paddata[1] ),
.se (se ),
.to_core (spare_misc_pad_to_core[1] ),
.por_l (por_l ),
.pad (spare_misc_pad[1] ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_cmos2_pad_dn tck_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_tck ),
.pad (tck ),
.por_l (por_l ) );
bw_io_cmos2_pad_up tdi_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_tdi ),
.pad (tdi ),
.por_l (por_l ) );
bw_io_cmos2_pad_up trst_l_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_trst_l ),
.pad (trst_l ),
.por_l (por_l ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, x, y, aa; scanf( %I64d %I64d , &x, &y); if (y > x) { printf( -1 n ); return 0; } a = x / y; if ((x % y) && (a % 2)) a++; if (!(a % 2)) aa = a - 1; else aa = a; double cc = (double)(x - aa * y); double c = cc / (double)a; double res = y + c; printf( %0.11lf n , res); return 0; }
|
module sin_lut (input [5:0] lookup, output [7:0] value);
assign value = (lookup == 6'd0) ? 128 :
(lookup == 6'd1) ? 140 :
(lookup == 6'd2) ? 152 :
(lookup == 6'd3) ? 165 :
(lookup == 6'd4) ? 176 :
(lookup == 6'd5) ? 188 :
(lookup == 6'd6) ? 198 :
(lookup == 6'd7) ? 208 :
(lookup == 6'd8) ? 218 :
(lookup == 6'd9) ? 226 :
(lookup == 6'd10) ? 234 :
(lookup == 6'd11) ? 240 :
(lookup == 6'd12) ? 245 :
(lookup == 6'd13) ? 250 :
(lookup == 6'd14) ? 253 :
(lookup == 6'd15) ? 254 :
(lookup == 6'd16) ? 255 :
(lookup == 6'd17) ? 254 :
(lookup == 6'd18) ? 253 :
(lookup == 6'd19) ? 250 :
(lookup == 6'd20) ? 245 :
(lookup == 6'd21) ? 240 :
(lookup == 6'd22) ? 234 :
(lookup == 6'd23) ? 226 :
(lookup == 6'd24) ? 218 :
(lookup == 6'd25) ? 208 :
(lookup == 6'd26) ? 198 :
(lookup == 6'd27) ? 188 :
(lookup == 6'd28) ? 176 :
(lookup == 6'd29) ? 165 :
(lookup == 6'd30) ? 152 :
(lookup == 6'd31) ? 140 :
(lookup == 6'd32) ? 128 :
(lookup == 6'd33) ? 115 :
(lookup == 6'd34) ? 103 :
(lookup == 6'd35) ? 90 :
(lookup == 6'd36) ? 79 :
(lookup == 6'd37) ? 67 :
(lookup == 6'd38) ? 57 :
(lookup == 6'd39) ? 47 :
(lookup == 6'd40) ? 37 :
(lookup == 6'd41) ? 29 :
(lookup == 6'd42) ? 21 :
(lookup == 6'd43) ? 15 :
(lookup == 6'd44) ? 10 :
(lookup == 6'd45) ? 5 :
(lookup == 6'd46) ? 2 :
(lookup == 6'd47) ? 1 :
(lookup == 6'd48) ? 0 :
(lookup == 6'd49) ? 1 :
(lookup == 6'd50) ? 2 :
(lookup == 6'd51) ? 5 :
(lookup == 6'd52) ? 10 :
(lookup == 6'd53) ? 15 :
(lookup == 6'd54) ? 21 :
(lookup == 6'd55) ? 29 :
(lookup == 6'd56) ? 37 :
(lookup == 6'd57) ? 47 :
(lookup == 6'd58) ? 57 :
(lookup == 6'd59) ? 67 :
(lookup == 6'd60) ? 79 :
(lookup == 6'd61) ? 90 :
(lookup == 6'd62) ? 103 :
(lookup == 6'd63) ? 115 :
/*lookup undefined*/ 0 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 10; const int inf = 1e9; struct node { int s, ind; } f[maxn]; int sum[maxn]; int cmp(node a, node b) { if (a.s == b.s) return a.ind < b.ind; return a.s < b.s; } int main() { int i, n, c, re = 0, value; scanf( %d%d , &n, &c); for (i = 1; i <= n; i++) { scanf( %d , &f[i].s); f[i].ind = i; sum[i] = sum[i - 1] + (f[i].s == c); } sort(f + 1, f + n + 1, cmp); for (i = 1; i <= n; i++) { if (f[i].s == c) continue; if (f[i].s != f[i - 1].s) { value = 1; re = max(re, value); continue; } value -= (sum[f[i].ind - 1] - sum[f[i - 1].ind]); if (value < 0) value = 0; value++; re = max(re, value); } printf( %d , re + sum[n]); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const int MAXN = 5 * 1e5 + 1, MODM = 1e9 + 7; int n; vector<int> g[MAXN]; int sz[MAXN]; int pr[MAXN]; int ans[MAXN]; int m1, m2; int now; int root = -1; void dfs(int v, int p = -1) { sz[v] = 1; pr[v] = p; for (auto to : g[v]) { if (to != p) { dfs(to, v); sz[v] += sz[to]; } } } void dfs2(int v, int p = -1) { int k = m1; if (sz[now] == m1) k = m2; ans[v] |= (n - sz[v] - k <= (n / 2)); ans[v] |= (n - sz[now] <= (n / 2)); for (auto it : g[v]) if (it != p) dfs2(it, v); } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } dfs(1); for (int v = 1; v <= n; v++) { int cnt = 0; for (auto to : g[v]) if (to != pr[v]) cnt += (sz[to] <= (n / 2)); if (v != 1) cnt += (n - sz[v] <= (n / 2)); ans[v] = (cnt == g[v].size()); if (ans[v]) root = v; } if (root == -1) { for (int i = 0; i < n; i++) cout << 0 << ; return 0; } fill(sz, sz + MAXN, 0); dfs(root); for (auto it : g[root]) { if (sz[it] > m1) { m2 = m1; m1 = sz[it]; } else m2 = max(m2, sz[it]); } for (auto it : g[root]) { now = it; dfs2(it, root); } for (int i = 0; i < n; i++) cout << ans[i + 1] << ; return 0; }
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module antiDroopIIR (
input clk,
input trig,
input signed [12:0] din,
input signed [6:0] tapWeight,
input accClr_en,
input oflowClr,
output reg oflowDetect = 1'd0,
output reg signed [15:0] dout = 16'sd0);
parameter IIR_scale = 15; // define the scaling factor for the IIR multiplier, eg for 0.002 (din = 63, IIR_scale = 15).
//`define ADDPIPEREG
reg signed [12:0] din_del = 13'sd0;
`ifdef ADDPIPEREG reg signed [12:0] din_del_b = 13'sd0;
`endif
reg signed [47:0] tap = 48'sd0;
reg signed [19:0] multreg = 20'sd0;
(* equivalent_register_removal = "no" *) reg trig_a = 1'b0, trig_b = 1'b0;
wire trig_edge = trig_a & ~trig_b;
//reg trig_edge = 1'b0;
reg signed [6:0] tapWeight_a = 7'sd0, tapWeight_b = 7'sd0;
always @(posedge clk) begin
//trig_edge <= trig_a & ~trig_b;
tapWeight_a <= tapWeight;
tapWeight_b <= tapWeight_a;
trig_a <= trig;
trig_b <= trig_a;
din_del <= din;
`ifdef ADDPIPEREG
din_del_b <= din_del;
multreg <= din_del*tapWeight_b;
dout <= {din_del_b, 3'b000} + tap[IIR_scale+12:IIR_scale-3];
`else
multreg <= din*tapWeight_b;
dout <= {din_del, 3'b000} + tap[IIR_scale+12:IIR_scale-3];
`endif
if (trig_edge && accClr_en) tap <= 48'd0;
else tap <= multreg + tap;
//tap <= din*tapWeight + tap;
if (oflowDetect && oflowClr) oflowDetect <= 1'b0;
//else if ((~& tap[47:IIR_scale+12]) || (& ~tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if ((~& tap[47:IIR_scale+12]) || (& tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
else if (^ tap[IIR_scale+13:IIR_scale+12]) oflowDetect <= 1'b1;
else oflowDetect <= oflowDetect;
end
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_SYMBOL_V
`define SKY130_FD_SC_LS__XNOR3_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; const int maxn = 1005; int in[maxn]; int t1, t2; struct edge { int v, w; }; vector<edge> g[maxn]; void dfs(int u, int fa) { if (in[u] == 1) { if (!t1) t1 = u; t2 = u; } for (edge e : g[u]) { if (e.v == fa) continue; dfs(e.v, u); } } struct Ans { int a, b, c; }; vector<Ans> ans; void add(int a, int b, int c) { if (a == b || !c) return; ans.push_back({a, b, c}); } int main() { int n; cin >> n; for (int i = 1; i < n; ++i) { int u, v, w; cin >> u >> v >> w; in[u]++, in[v]++; g[u].push_back({v, w}); g[v].push_back({u, w}); } for (int i = 1; i <= n; ++i) if (in[i] == 2) { cout << NO << endl; return 0; } cout << YES << endl; for (int u = 1; u <= n; ++u) { for (edge e : g[u]) { int v = e.v, w = e.w; if (v < u) continue; int a1, a2, b1, b2; t1 = t2 = 0; dfs(u, v); a1 = t1, a2 = t2; t1 = t2 = 0; dfs(v, u); b1 = t1, b2 = t2; add(a1, b1, w / 2); add(a2, b2, w / 2); add(a1, a2, -w / 2); add(b1, b2, -w / 2); } } cout << ans.size() << endl; for (auto p : ans) cout << p.a << << p.b << << p.c << endl; }
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#include <bits/stdc++.h> using namespace std; int i, j, k, n, m, p; int a[33], c[100010][33]; int fac[100010], inv[100010]; int l, r, L, R, len, Ans; inline int Pow(int x, int y) { int Ans = 1; for (; y; y >>= 1, x = 1ll * x * x % p) if (y & 1) Ans = 1ll * Ans * x % p; return Ans; } inline void Init() { int t = p; for (int i = 2; i * i <= t; i++) if (!(t % i)) { a[++m] = i; t /= i; while (!(t % i)) t /= i; } if (t > 1) a[++m] = t; int phi = p; for (int i = 1; i <= m; i++) phi = phi / a[i] * (a[i] - 1); fac[0] = inv[0] = 1; for (int i = 1; i < 100010; i++) { int x = i; for (int j = 1; j <= m; j++) { c[i][j] = c[i - 1][j]; while (!(x % a[j])) x /= a[j], c[i][j]++; } fac[i] = 1ll * fac[i - 1] * x % p; inv[i] = Pow(fac[i], phi - 1); } } inline int Calc(int x, int y) { if (x < y || y < 0) return 0; if (!y) return 1; int Ans = 1ll * fac[x] * inv[y] % p * inv[x - y] % p; for (int i = 1; i <= m; i++) Ans = 1ll * Ans * Pow(a[i], c[x][i] - c[y][i] - c[x - y][i]) % p; return Ans; } int main() { scanf( %d%d%d%d , &n, &p, &l, &r); Init(); for (i = 0; i <= n; i++) len = n - i, Ans = (Ans + 1ll * (Calc(len, (len - l >> 1)) - Calc(len, (min(r, len) + len >> 1) + 1)) * Calc(n, i)) % p; if (Ans < 0) Ans += p; cout << Ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0), cin.tie(0); int arr[4]; for (int i = 0; i < (int)4; i++) cin >> arr[i]; sort(arr, arr + 4); bool ok = 0; for (int mask = 0; mask < (1 << 4); mask++) { int sum1 = 0; int sum2 = 0; for (int bit = 0; bit < 4; bit++) { if (mask & (1 << bit)) { sum1 += arr[bit]; } else { sum2 += arr[bit]; } } if (sum1 == sum2) { ok = 1; break; } } if (ok) cout << YES << n ; else cout << NO << n ; return 0; }
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#include <bits/stdc++.h> const int N = 1e3 + 10, O = 27; int cnt, n, m; bool v[O], ok[O], cur[O]; std::vector<int> empty, full; std::string s, temp; int main() { scanf( %d , &n); std::cin >> s; for (int i = 0; i < n; i++) { if (s[i] != * ) { v[s[i] - a ] = true; full.push_back(i); } else { empty.push_back(i); } } for (int i = 0; i < 26; i++) ok[i] = !v[i]; scanf( %d , &m); for (int i = 0; i < m; i++) { static bool acc; acc = true; std::cin >> temp; for (int j : full) if (s[j] != temp[j]) { acc = false; break; } if (!acc) continue; for (int j : empty) if (v[temp[j] - a ]) { acc = false; break; } if (!acc) continue; memset(cur, 0, sizeof cur); for (int j : empty) cur[temp[j] - a ] = true; for (int j = 0; j < 26; j++) if (!cur[j]) ok[j] = false; } for (int i = 0; i < 26; i++) if (ok[i]) cnt++; printf( %d n , cnt); return 0; }
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#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > Dates; int n, x, y, ans, cur; int main() { std::ios_base::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y; Dates.push_back(make_pair(x, y)); } sort(Dates.begin(), Dates.end()); for (int i = 0; i < Dates.size(); i++) { if (Dates[i].second > cur) cur = Dates[i].second; else if (Dates[i].second < cur) { ans++; } } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; int mark[2000010 * 2]; int tree[2000010 * 4]; bool emerged[2000010 * 2]; void insert(int l, int r, int i, int ind, int num) { tree[ind] += num; if (l == r) return; int mid = (l + r) / 2; if (i <= mid) insert(l, mid, i, ind * 2, num); if (i > mid) insert(mid + 1, r, i, ind * 2 + 1, num); } int find(int l, int r, int y, int ind) { if (l == r) return l; int mid = (l + r) / 2; if (tree[ind * 2] >= y) { return find(l, mid, y, ind * 2); } else { return find(mid + 1, r, y - tree[ind * 2], ind * 2 + 1); } } int main() { memset(tree, 0, sizeof(tree)); memset(emerged, 0, sizeof(emerged)); memset(mark, 0, sizeof(mark)); int n, m; scanf( %d%d , &n, &m); for (int i = n + 1; i <= 2 * n; ++i) insert(1, 2 * n, i, 1, 1); int x, y; for (int i = 0; i < m; i++) { scanf( %d%d , &x, &y); int place = find(1, 2 * n, y, 1); if (((mark[place] > 0) || emerged[x]) && (mark[place] != x)) { cout << -1 << endl; return 0; } insert(1, 2 * n, place, 1, -1); insert(1, 2 * n, n - i, 1, 1); mark[n - i] = mark[place] = x; emerged[x] = true; } int j = 1; for (int i = n + 1; i <= 2 * n; i++) { int tmp; if (mark[i] > 0) tmp = mark[i]; else { while (emerged[j]) j++; tmp = j; j++; } printf( %d , tmp); } printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n][3]; for (int i = 0; i < n; i++) { for (int j = 0; j < 3; j++) { cin >> a[i][j]; } } int c = 1; for (int i = 0; i < 3; i++) { int sum = 0; for (int j = 0; j < n; j++) { sum += a[j][i]; } if (sum != 0) { c = 0; cout << NO ; break; } } if (c) { cout << YES ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int MAXN = 1e5 + 10; const int MAXK = 5 + 1; long long sumv[MAXK][MAXN << 2], setv[MAXN << 2]; long long prefix[MAXK][MAXN], C[MAXK][MAXK]; void Pushdown(int o, int lft, int rht) { if (setv[o] != -1) { setv[(o << 1)] = setv[(o << 1 | 1)] = setv[o]; int mid = lft + rht >> 1; for (int k = 0; k < MAXK; ++k) { sumv[k][(o << 1)] = setv[(o << 1)] * (prefix[k][mid] - prefix[k][lft - 1] + mod) % mod; sumv[k][(o << 1 | 1)] = setv[(o << 1 | 1)] * (prefix[k][rht] - prefix[k][mid] + mod) % mod; } setv[o] = -1; } } void Pushup(int o) { for (int k = 0; k < MAXK; ++k) sumv[k][o] = sumv[k][(o << 1)] + sumv[k][(o << 1 | 1)]; } void Build(int o, int lft, int rht) { if (lft == rht) { scanf( %lld , setv + o); sumv[0][o] = setv[o] % mod; for (int k = 1; k < MAXK; ++k) sumv[k][o] = sumv[k - 1][o] * lft % mod; } else { int mid = lft + rht >> 1; Build((o << 1), lft, mid); Build((o << 1 | 1), mid + 1, rht); Pushup(o); } } int ul, ur, uv; void Update(int o, int lft, int rht) { if (ul <= lft and rht <= ur) { setv[o] = uv; for (int k = 0; k < MAXK; ++k) sumv[k][o] = setv[o] * (prefix[k][rht] - prefix[k][lft - 1] + mod) % mod; } else { Pushdown(o, lft, rht); int mid = lft + rht >> 1; if (ul <= mid) Update((o << 1), lft, mid); if (ur > mid) Update((o << 1 | 1), mid + 1, rht); Pushup(o); } } int ql, qr, qk; long long Query(int o, int lft, int rht) { if (ql <= lft and rht <= qr) return sumv[qk][o]; Pushdown(o, lft, rht); int mid = lft + rht >> 1; long long ans = 0; if (ql <= mid) ans += Query((o << 1), lft, mid); if (qr > mid) ans += Query((o << 1 | 1), mid + 1, rht); return ans % mod; } void work() { for (int i = 0; i < MAXK; ++i) { C[i][0] = C[i][i] = 1; for (int j = 1; j < i; ++j) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % mod; } for (int i = 1; i < MAXN; ++i) { long long u = 1; for (int k = 0; k < MAXK; ++k) { prefix[k][i] = (prefix[k][i - 1] + u) % mod; u = u * i % mod; } } int N, Q, K; char cmd[20]; long long ans, ret; scanf( %d%d , &N, &Q); memset(setv, -1, sizeof setv); Build(1, 1, N); while (Q--) { scanf( %s , cmd); switch (cmd[0]) { case ? : scanf( %d%d%d , &ql, &qr, &K); ans = 0; ret = 1; for (qk = K; qk >= 0; --qk, ret = ret * (1 - ql) % mod) ans += Query(1, 1, N) * (ret) % mod * C[K][qk] % mod; printf( %lld n , (ans % mod + mod) % mod); break; case = : scanf( %d%d%d , &ul, &ur, &uv); Update(1, 1, N); break; } } } int main() { work(); return 0; }
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#include <bits/stdc++.h> using namespace std; int n; long long L[500005]; char ch[500005]; class segtree { public: long long seg[(1 << 19) * 2]; long long lazy[(1 << 19) * 2]; void lazy_evaluate(int k) { if (k * 2 + 2 >= (1 << 19) * 2) return; lazy[k * 2 + 2] += lazy[k]; lazy[k * 2 + 1] += lazy[k]; seg[k * 2 + 2] += lazy[k]; seg[k * 2 + 1] += lazy[k]; lazy[k] = 0; } long long update(int beg, int end, int idx, int lb, int ub, long long num) { if (ub < beg || end < lb) { return seg[idx]; } if (beg <= lb && ub <= end) { lazy[idx] += num; seg[idx] += num; return seg[idx]; } if (lazy[idx]) { lazy_evaluate(idx); } return seg[idx] = min(update(beg, end, idx * 2 + 1, lb, (lb + ub) / 2, num), update(beg, end, idx * 2 + 2, (lb + ub) / 2 + 1, ub, num)); } long long query(int beg, int end, int idx, int lb, int ub) { if (ub < beg || end < lb) { return 1500000000000000000LL; } if (beg <= lb && ub <= end) { return seg[idx]; } if (lazy[idx]) { lazy_evaluate(idx); } return min(query(beg, end, idx * 2 + 1, lb, (lb + ub) / 2), query(beg, end, idx * 2 + 2, (lb + ub) / 2 + 1, ub)); } } kaede; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld , &L[i]); scanf( %s , &ch); long long cur = 0; long long ans = 0; bool ok = 0; for (int i = 0; i < n; i++) { if (ch[i] == L ) ans += L[i]; else if (ch[i] == W ) ans += L[i] * 3LL; else ans += L[i] * 5LL; } vector<long long> vec; int lasw, lasg; for (int i = 0; i < n; i++) { if (ch[i] == G ) { cur += L[i]; kaede.update(i, i, 0, 0, (1 << 19) - 1, cur); vec.push_back(L[i]); lasg = i; continue; } if (ch[i] == W ) { cur += L[i]; lasw = i; ok = 1; kaede.update(i, i, 0, 0, (1 << 19) - 1, cur); vec.push_back(L[i]); continue; } if (ch[i] == L ) { if (cur >= L[i]) { cur -= L[i]; kaede.update(i, i, 0, 0, (1 << 19) - 1, cur); vec.push_back(L[i]); continue; } else { long long need = L[i] - cur; if (ok) { ans += 3LL * need; vec[lasw] += need; } else { ans += 5LL * need; vec[lasg] += need; } cur = 0; vec.push_back(L[i]); kaede.update(i, i, 0, 0, (1 << 19) - 1, cur); continue; } } } for (int i = n - 1; i >= 0; i--) { if (ch[i] == L ) continue; if (ch[i] == W ) continue; long long mn = kaede.query(i, n - 1, 0, 0, (1 << 19) - 1); if (2LL * vec[i] <= mn) { kaede.update(i, n - 1, 0, 0, (1 << 19) - 1, -2LL * vec[i]); ans -= 4LL * vec[i]; } else { kaede.update(i, n - 1, 0, 0, (1 << 19) - 1, -mn); ans -= 2LL * mn; } } for (int i = n - 1; i >= 0; i--) { if (ch[i] == L ) continue; if (ch[i] == G ) continue; long long mn = kaede.query(i, n - 1, 0, 0, (1 << 19) - 1); if (2LL * vec[i] <= mn) { kaede.update(i, n - 1, 0, 0, (1 << 19) - 1, -2LL * vec[i]); ans -= 2LL * vec[i]; } else { kaede.update(i, n - 1, 0, 0, (1 << 19) - 1, -mn); ans -= 1LL * mn; } } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; template <typename T> bool chkmin(T &first, T second) { return second < first ? first = second, 1 : 0; } template <typename T> bool chkmax(T &first, T second) { return first < second ? first = second, 1 : 0; } template <typename T> void readint(T &first) { first = 0; int f = 1; char c; for (c = getchar(); !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) first = first * 10 + (c - 0 ); first *= f; } const int MOD = 1000000007, INV3 = (MOD + 1) / 3; inline int dmy(int first) { return first >= MOD ? first - MOD : first; } inline void inc(int &first, int second) { first = dmy(first + second); } int qmi(int first, int second) { int ans = 1; for (; second; second >>= 1, first = 1ll * first * first % MOD) if (second & 1) ans = 1ll * ans * first % MOD; return ans; } const int MAXN = 6005; int n; int cnt[4][4]; int main() { readint(n); for (int i = 1, first, second; i <= n; ++i) readint(first), readint(second), ++cnt[first & 3][second & 3]; long long res = 0; for (int i = 0; i <= 3; ++i) for (int j = 0; j <= 3; ++j) res += 1ll * cnt[i][j] * (cnt[i][j] - 1) / 2 * (n - cnt[i][j]) + 1ll * cnt[i][j] * (cnt[i][j] - 1) * (cnt[i][j] - 2) / 6; cout << res << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; const long long inf = 1e18; int bcg[maxn]; struct Edge { int u, v, nxt; long long w; } edge[maxn * 2], edge1[maxn * 2]; vector<Edge> vec[maxn]; struct Node { long long p; int v; friend bool operator<(Node a, Node b) { return a.p > b.p; } Node() {} Node(long long x, int y) { p = x, v = y; } }; int head[maxn], head1[maxn]; long long deep[maxn]; int depth[maxn]; int bian[maxn * 2]; long long dis[50][maxn]; int lca[maxn][25]; int vis[maxn]; int cnt, cnt1, tot; int n, m; int findd(int x) { return bcg[x] == x ? bcg[x] : bcg[x] = findd(bcg[x]); } bool cmp(Edge a, Edge b) { return a.w < b.w; } void add_e1(int x, int y, long long w) { ++cnt1; edge1[cnt1].u = x; edge1[cnt1].v = y; edge1[cnt1].w = w; edge1[cnt1].nxt = head1[x]; head1[x] = cnt1; } void add_e(int x, int y, long long w) { ++cnt; edge[cnt].u = x; edge[cnt].v = y; edge[cnt].w = w; edge[cnt].nxt = head[x]; head[x] = cnt; } int merges(int x, int y) { int xx = findd(x); int yy = findd(y); if (xx != yy) { bcg[xx] = yy; return 1; } return 0; } void init() { cnt = cnt1 = 0; tot = 0; memset(deep, 0, sizeof(deep)); memset(head, 0, sizeof(head)); memset(head1, 0, sizeof(head1)); } void dfs(int x, int ff) { lca[x][0] = ff; for (int i = 1; i <= 20; i++) lca[x][i] = lca[lca[x][i - 1]][i - 1]; for (int i = head[x]; i; i = edge[i].nxt) { int v = edge[i].v; if (v == ff) continue; deep[v] = deep[x] + edge[i].w; depth[v] = depth[x] + 1; dfs(v, x); } } int LCA(int x, int y) { if (depth[x] < depth[y]) swap(x, y); int ff = depth[x] - depth[y]; for (int i = 20; i >= 0; i--) { if (ff & (1 << i)) x = lca[x][i]; } if (x == y) return y; for (int i = 20; i >= 0; i--) { if (lca[x][i] != lca[y][i]) x = lca[x][i], y = lca[y][i]; } return lca[y][0]; } priority_queue<Node> que; void dij(int id, int x) { for (int i = 0; i <= n + 4; i++) { dis[id][i] = inf; vis[i] = 0; } dis[id][x] = 0; while (!que.empty()) que.pop(); que.push(Node(0, x)); while (!que.empty()) { Node vv = que.top(); que.pop(); if (vis[vv.v] || vv.p > dis[id][vv.v]) continue; vis[vv.v] = 1; for (int i = 0; i < (int)vec[vv.v].size(); i++) { Edge k = vec[vv.v][i]; int sw = k.v; if (vis[sw]) continue; if (dis[id][sw] > dis[id][vv.v] + k.w) { dis[id][sw] = dis[id][vv.v] + k.w; que.push(Node(dis[id][sw], sw)); } } } } int main() { scanf( %d%d , &n, &m); int u, v; long long w; init(); for (int i = 1; i <= m; i++) { scanf( %d%d%lld , &u, &v, &w); add_e1(u, v, w); vec[u].push_back((Edge){u, v, 0, w}); vec[v].push_back((Edge){v, u, 0, w}); } sort(edge1 + 1, edge1 + cnt1 + 1, cmp); for (int i = 1; i <= n + 4; i++) bcg[i] = i; for (int i = 1; i <= cnt1; i++) { int x = edge1[i].u, y = edge1[i].v; if (merges(x, y)) { add_e(x, y, edge1[i].w); add_e(y, x, edge1[i].w); } else { bian[++tot] = x; bian[++tot] = y; } } depth[1] = 0; deep[1] = 0; dfs(1, 0); sort(bian + 1, bian + 1 + tot); int sz = unique(bian + 1, bian + 1 + tot) - (bian + 1); for (int i = 1; i <= sz; i++) { dij(i, bian[i]); } int q; scanf( %d , &q); int x, y; while (q--) { scanf( %d%d , &x, &y); long long ans = inf; int pq = LCA(x, y); ans = deep[x] + deep[y] - 2 * deep[pq]; for (int i = 1; i <= sz; i++) { ans = min(ans, dis[i][x] + dis[i][y]); } cout << ans << n ; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 18 23:18:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.v
// Design : system_xlconstant_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_0(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[0:0]" */;
output [0:0]dout;
endmodule
|
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
module d (
cos_z0,
sin_z0,
done,
z0,
start,
clock,
reset
);
// Sine and cosine computer.
//
// This module computes the sine and cosine of an input angle. The
// floating point numbers are represented as integers by scaling them
// up with a factor corresponding to the number of bits after the point.
//
// Ports:
// -----
// cos_z0: cosine of the input angle
// sin_z0: sine of the input angle
// done: output flag indicated completion of the computation
// z0: input angle
// start: input that starts the computation on a posedge
// clock: clock input
// reset: reset input
output signed [19:0] cos_z0;
reg signed [19:0] cos_z0;
output signed [19:0] sin_z0;
reg signed [19:0] sin_z0;
output done;
reg done;
input signed [19:0] z0;
input start;
input clock;
input reset;
(* gentb_constant = 1'b0 *)
wire reset;
always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR
reg [5-1:0] i;
reg [1-1:0] state;
reg signed [20-1:0] dz;
reg signed [20-1:0] dx;
reg signed [20-1:0] dy;
reg signed [20-1:0] y;
reg signed [20-1:0] x;
reg signed [20-1:0] z;
if (reset) begin
state = 1'b0;
cos_z0 <= 1;
sin_z0 <= 0;
done <= 1'b0;
x = 0;
y = 0;
z = 0;
i = 0;
end
else begin
case (state)
1'b0: begin
if (start) begin
x = 159188;
y = 0;
z = z0;
i = 0;
done <= 1'b0;
state = 1'b1;
end
end
1'b1: begin
dx = $signed(y >>> $signed({1'b0, i}));
dy = $signed(x >>> $signed({1'b0, i}));
case (i)
0: dz = 205887;
1: dz = 121542;
2: dz = 64220;
3: dz = 32599;
4: dz = 16363;
5: dz = 8189;
6: dz = 4096;
7: dz = 2048;
8: dz = 1024;
9: dz = 512;
10: dz = 256;
11: dz = 128;
12: dz = 64;
13: dz = 32;
14: dz = 16;
15: dz = 8;
16: dz = 4;
17: dz = 2;
default: dz = 1;
endcase
if ((z >= 0)) begin
x = x - dx;
y = y + dy;
z = z - dz;
end
else begin
x = x + dx;
y = y - dy;
z = z + dz;
end
if ((i == (19 - 1))) begin
cos_z0 <= x;
sin_z0 <= y;
state = 1'b0;
done <= 1'b1;
end
else begin
i = i + 1;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int INF = INT_MAX; const int NINF = INT_MIN; int n, q, l, r, curr; vector<int> vec, tv, Count; void Solve() { cin >> n >> q; vec = tv = vector<int>(n, 0); for (int i = 0; i <= n - 1; i++) cin >> vec[i]; for (int i = 0; i <= q - 1; i++) { cin >> l >> r; l--; r; tv[l]++; if (r < n) tv[r]--; } curr = 0; for (int i = 0; i <= n - 1; i++) { curr += tv[i]; if (curr > 0) Count.push_back(curr); } sort(Count.rbegin(), Count.rend()); sort(vec.rbegin(), vec.rend()); long long int ans = 0ll; int i = 0; for (auto v : Count) { ans += ((v * 1ll) * (vec[i] * 1ll)); i++; } cout << ans << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); Solve(); return 0; }
|
#include <bits/stdc++.h> const int kM = 4e4 + 5; const int kN = 55; int M, n, m, k; long long T[kM << 3], tag[kM << 3], a[kN][kM], pre[kM], s[kM], f[kN][kM]; void Update(int cur) { T[cur] = std::max(T[cur << 1], T[cur << 1 | 1]); } void PushTag(int cur) { T[cur << 1] += tag[cur]; T[cur << 1 | 1] += tag[cur]; tag[cur << 1] += tag[cur]; tag[cur << 1 | 1] += tag[cur]; tag[cur] = 0; } void Build(int cur, int l, int r) { if (l < r) { int mid = (l + r) >> 1; Build(cur << 1, l, mid); Build(cur << 1 | 1, mid + 1, r); Update(cur); } else T[cur] = s[l]; } void Modify(int cur, int l, int r, int ql, int qr, long long v) { if (l > qr || r < ql) return; if (ql <= l && r <= qr) T[cur] += v, tag[cur] += v; else { int mid = (l + r) >> 1; PushTag(cur); if (ql <= mid) Modify(cur << 1, l, mid, ql, qr, v); if (qr > mid) Modify(cur << 1 | 1, mid + 1, r, ql, qr, v); Update(cur); } } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) scanf( %d , &a[i][j]); for (int i = 1; i <= m + k; ++i) pre[i] = pre[i - 1] + a[1][i]; for (int i = 1; i <= m; ++i) f[1][i] = pre[i + k - 1] - pre[i - 1]; for (int i = 2; i <= n; ++i) { for (int j = 1; j <= m + k; ++j) pre[j] = pre[j - 1] + a[i][j]; for (int j = 1; j <= m; ++j) s[j] = pre[j + k - 1] - pre[std::max(k, j - 1)] + f[i - 1][j]; memset(tag, 0, sizeof(tag)); Build(1, 1, m); for (int j = 1; j <= m; ++j) { f[i][j] = T[1] + pre[j + k - 1] - pre[j - 1]; Modify(1, 1, m, j - k + 1, j, a[i][j]); Modify(1, 1, m, j + 1, j + k, -a[i][j + k]); } } long long ans = 0; for (int i = 1; i <= m; ++i) ans = std::max(ans, f[n][i]); printf( %lld , ans); return 0; }
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// integrates sound features: tapeout, beeper and covox
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module sound(
input wire clk,
input wire [7:0] din,
input wire beeper_wr,
input wire covox_wr,
input wire beeper_mux, // output either tape_out or beeper
output wire sound_bit
);
reg [6:0] ctr;
reg [7:0] val;
reg mx_beep_n_covox;
reg beep_bit;
reg beep_bit_old;
wire covox_bit;
always @(posedge clk)
begin
/* if( beeper_wr ) */
if( beeper_wr && (beep_bit!=beep_bit_old) )
mx_beep_n_covox <= 1'b1;
else if( covox_wr )
mx_beep_n_covox <= 1'b0;
end
always @(posedge clk) if( beeper_wr ) beep_bit_old <= beep_bit;
always @(posedge clk)
if( beeper_wr )
beep_bit <= beeper_mux ? din[3] /*tapeout*/ : din[4] /*beeper*/;
always @(posedge clk)
if( covox_wr )
val <= din;
always @(negedge clk)
ctr <= ctr + 6'd1;
assign covox_bit = ( {ctr,clk} < val );
bothedge trigger
(
.clk( clk ),
.d( mx_beep_n_covox ? beep_bit : covox_bit ),
.q( sound_bit )
);
endmodule
// both-edge trigger emulator
module bothedge(
input wire clk,
input wire d,
output wire q
);
reg trgp, trgn;
assign q = trgp ^ trgn;
always @(posedge clk)
if( d!=q )
trgp <= ~trgp;
always @(negedge clk)
if( d!=q )
trgn <= ~trgn;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int nodes_size; long long int edge_size; class edge { public: long long int node; long long int cost; edge(long long int i, long long int j) { node = i; cost = j; } }; class graph { public: long long int node; vector<edge> edges; long long int parent; long long int cost; vector<long long int> children; } nodes[1005]; long long int visited[1005]; class point { public: long long int x; long long int y; point() {} point(long long int i, long long int j) { x = i; y = j; } }; void fill_array(long long int ar[], long long int value, long long int size) { for (long long int i = 0; i < size; i++) ar[i] = value; } void print_ll_vector(vector<long long int> v) { for (long long int i = 0; i < v.size(); i++) cout << v[i] << ; cout << endl; } void input_graph(bool is_undirected, bool is_cost) { cin >> nodes_size; edge_size = nodes_size - 1; for (long long int i = 0; i < edge_size; i++) { long long int a, b, c; cin >> a >> b; if (is_cost) { cin >> c; nodes[a].edges.push_back(edge(b, c)); if (is_undirected) nodes[b].edges.push_back(edge(a, c)); } else { nodes[a].edges.push_back(edge(b, 1)); if (is_undirected) nodes[b].edges.push_back(edge(a, 1)); } } } vector<pair<long long int, long long int> > destroyed_edges; long long int ctr = 0, c; vector<long long int> ans; void dfs(long long int node, long long int parent) { visited[node] = 1; for (long long int i = 0; i < nodes[node].edges.size(); i++) { if (nodes[node].edges[i].node != parent) { if (visited[nodes[node].edges[i].node]) { if (node > nodes[node].edges[i].node) { if (c > 0 || ctr == 1) { destroyed_edges.push_back( make_pair(node, nodes[node].edges[i].node)); c++; } else { c++; ans.push_back(node); ans.push_back(nodes[node].edges[i].node); } } } else dfs(nodes[node].edges[i].node, node); } } } vector<long long int> new_edges; int main() { input_graph(true, false); fill_array(visited, 0, nodes_size + 1); for (long long int i = 1; i <= nodes_size; i++) { if (!visited[i]) { c = 0; ctr++; dfs(i, -1); if (c == 0 && i != 1) new_edges.push_back(i); } } cout << (ans.size() / 2) + new_edges.size() << endl; for (long long int i = 0; i < ans.size();) { cout << ans[i] << << ans[i + 1] << << ans[i] << << 1 << endl; i = i + 2; } for (long long int i = 0; i < new_edges.size(); i++) cout << destroyed_edges[i].first << << destroyed_edges[i].second << << destroyed_edges[i].first << << new_edges[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long pow = 1; long long L, R; cin >> L >> R; while (pow * 10 <= R) pow *= 10; if (L < pow) { if (R < pow * 5) cout << R * (pow * 10 - 1 - R) << endl; else cout << pow * 5 * (pow * 5 - 1) << endl; } else { if (R >= pow * 5 && L <= pow * 5) cout << pow * 5 * (pow * 5 - 1) << endl; else cout << max(R * (pow * 10 - 1 - R), L * (pow * 10 - 1 - L)) << endl; } return 0; }
|
module module0(clk_, rst_, bar, foo);
input clk_;
input rst_;
input [1:0] bar;
output [1:0] foo;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1;
parameter poser_width_out = 0+1-0+1;
parameter poser_grid_width = 2;
parameter poser_grid_depth = 1;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 2'b11 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar };
wire [poser_width_out-1:0] poser_outputs;
assign { foo } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const int MOD = 1000000007; signed main() { cin.tie(0), cout.tie(0); ios::sync_with_stdio(0); int n, k; cin >> n >> k; int a, b, c, d; cin >> a >> b >> c >> d; if (k < n + 1 || n <= 4) cout << -1 << n , exit(0); else { cout << a << << c << ; for (int i = 1; i <= n; i++) if (i != a && i != b && i != c && i != d) cout << i << ; cout << d << << b << n ; cout << c << << a << ; for (int i = 1; i <= n; i++) if (i != a && i != b && i != c && i != d) cout << i << ; cout << b << << d << n ; } return 0; }
|
/*********************************************************************
* SYNOPSYS CONFIDENTIAL *
* *
* This is an unpublished, proprietary work of Synopsys, Inc., and *
* is fully protected under copyright and trade secret laws. You may *
* not view, use, disclose, copy, or distribute this file or any *
* information contained herein except pursuant to a valid written *
* license from Synopsys. *
*********************************************************************/
// Generate Partial Products for 32 x 32 Multiplier using Radix 4 Booth
// Recoding (8 Bit Signed Operands) & Partial Product Generation
//
module GenPP_32Bits(PP15,PP14,PP13,PP12,PP11,PP10,PP9,PP8,
PP7,PP6,PP5,PP4,PP3,PP2,PP1,PP0,iso_X,iso_Y,iso_in);
`define nBits 32
output [`nBits:0] PP15; // Partial Product 15
output [`nBits:0] PP14; // Partial Product 14
output [`nBits:0] PP13; // Partial Product 13
output [`nBits:0] PP12; // Partial Product 12
output [`nBits:0] PP11; // Partial Product 11
output [`nBits:0] PP10; // Partial Product 10
output [`nBits:0] PP9; // Partial Product 9
output [`nBits:0] PP8; // Partial Product 8
output [`nBits:0] PP7; // Partial Product 7
output [`nBits:0] PP6; // Partial Product 6
output [`nBits:0] PP5; // Partial Product 5
output [`nBits:0] PP4; // Partial Product 4
output [`nBits:0] PP3; // Partial Product 3
output [`nBits:0] PP2; // Partial Product 2
output [`nBits:0] PP1; // Partial Product 1
output [`nBits:0] PP0; // Partial Product 0
input [`nBits-1:0] iso_X; // Mulitiplicand, X
input [`nBits-1:0] iso_Y; // Mulitiplier, Y
input iso_in;
wire iso_in_N;
wire [`nBits-1:0] X;
wire [`nBits-1:0] Y;
// Booth recoding requires dividing the multiplier into overlapping segments
// which are 3 bits in lenth. The segments are defined using the rules below:
//
// Multiplier Y = Yn-1 Yn-2 .... Y2 Y1 Y0 , where n = Mulitplier width
//
// Signed Multiplier (2's complement form):
//
// Seg 0 = Y1, Y0, 0
// Seg j = Yi+1, Yi, Yi-1 For j = 1 to (n/2)-1, i=2*j
// Seg n/2 = Yn-1, Yn-1, Yn-2 --> For Odd n
// Seg n/2 = Yn-1, Yn-2, Yn-3 --> For Even n
//
// Unsigned Multiplier:
//
// Seg 0 = Y1, Y0, 0
// Seg j = Yi+1, Yi, Yi-1 For j = 1 to (n/2)-1, i=2*j
// Seg n/2 = 0, Yn-1, Yn-2 --> For Odd n
// Seg n/2 = Yn-1, Yn-2, Yn-3 --> For Even n
// Seg (n/2)+1 = 0, 0, Yn-1 --> For Even n
//
wire [2:0] Seg15 = Y[31:29]; // Segment 15
wire [2:0] Seg14 = Y[29:27]; // Segment 14
wire [2:0] Seg13 = Y[27:25]; // Segment 13
wire [2:0] Seg12 = Y[25:23]; // Segment 12
wire [2:0] Seg11 = Y[23:21]; // Segment 11
wire [2:0] Seg10 = Y[21:19]; // Segment 10
wire [2:0] Seg9 = Y[19:17]; // Segment 9
wire [2:0] Seg8 = Y[17:15]; // Segment 8
wire [2:0] Seg7 = Y[15:13]; // Segment 7
wire [2:0] Seg6 = Y[13:11]; // Segment 6
wire [2:0] Seg5 = Y[11:9]; // Segment 5
wire [2:0] Seg4 = Y[9:7]; // Segment 4
wire [2:0] Seg3 = Y[7:5]; // Segment 3
wire [2:0] Seg2 = Y[5:3]; // Segment 2
wire [2:0] Seg1 = Y[3:1]; // Segment 1
wire [2:0] Seg0 = {Y[1:0], 1'b0}; // Segment 0
assign X = iso_X;
assign Y = iso_Y;
assign PP15[`nBits:0] = BoothDecode(Seg15[2:0],X[`nBits-1:0]);
assign PP14[`nBits:0] = BoothDecode(Seg14[2:0],X[`nBits-1:0]);
assign PP13[`nBits:0] = BoothDecode(Seg13[2:0],X[`nBits-1:0]);
assign PP12[`nBits:0] = BoothDecode(Seg12[2:0],X[`nBits-1:0]);
assign PP11[`nBits:0] = BoothDecode(Seg11[2:0],X[`nBits-1:0]);
assign PP10[`nBits:0] = BoothDecode(Seg10[2:0],X[`nBits-1:0]);
assign PP9[`nBits:0] = BoothDecode(Seg9[2:0],X[`nBits-1:0]);
assign PP8[`nBits:0] = BoothDecode(Seg8[2:0],X[`nBits-1:0]);
assign PP7[`nBits:0] = BoothDecode(Seg7[2:0],X[`nBits-1:0]);
assign PP6[`nBits:0] = BoothDecode(Seg6[2:0],X[`nBits-1:0]);
assign PP5[`nBits:0] = BoothDecode(Seg5[2:0],X[`nBits-1:0]);
assign PP4[`nBits:0] = BoothDecode(Seg4[2:0],X[`nBits-1:0]);
assign PP3[`nBits:0] = BoothDecode(Seg3[2:0],X[`nBits-1:0]);
assign PP2[`nBits:0] = BoothDecode(Seg2[2:0],X[`nBits-1:0]);
assign PP1[`nBits:0] = BoothDecode(Seg1[2:0],X[`nBits-1:0]);
assign PP0[`nBits:0] = BoothDecode(Seg0[2:0],X[`nBits-1:0]);
// FUNCTION: BoothDecode - Use Booth Encoding to generate partial products.
//
// Yi+1| Yi |Yi-1| Description |Action
// ----+----+----+--------------------------------------------------+--------
// 0 | 0 | 0 |Add Zero (No String) | +0
// 0 | 0 | 1 |Add Multiplicand (End of String) | +X
// 0 | 1 | 0 |Add Multiplicand (String of one) | +X
// 0 | 1 | 1 |Add Twice the Multiplicand (End of String) | +2X
// 1 | 0 | 0 |Substract Twice the Multiplicand (Start of string)| -2X
// 1 | 0 | 1 |Substract the Multiplicand (-2X +X) | -X
// 1 | 1 | 0 |Substract the Multiplicand (Start of string) | -X
// 1 | 1 | 1 |Substract Zero (Center of String) | -0
//
function [`nBits:0] BoothDecode;
input [2:0] Segment;
input [`nBits:0] X;
case ( Segment[2:0] )
3'b000 : BoothDecode = 33'h000000000; // + Zero
3'b001,
3'b010 : BoothDecode = { X[`nBits-1], X[`nBits-1:0] } ; // +X
3'b011 : BoothDecode = { X[`nBits-1:0], 1'b0 } ; // +2X
3'b100 : BoothDecode = { ~X[`nBits-1:0], 1'b1 } ; // -2X
3'b101,
3'b110 : BoothDecode = { ~X[`nBits-1], ~X[`nBits-1:0] } ;// -X
3'b111 : BoothDecode = 33'h1FFFFFFFF; // - Zero
endcase
endfunction
endmodule
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#include <bits/stdc++.h> using namespace std; template <class T> bool uin(T &a, T b) { if (a > b) { a = b; return true; } return false; } template <class T> bool uax(T &a, T b) { if (a < b) { a = b; return true; } return false; } int main() { ios::sync_with_stdio(false); cout.precision(10); cout << fixed; int N, X, Y; cin >> N >> X >> Y; for (int i = 0; i < (int)(N); ++i) { int A; cin >> A; long long l = 0, r = 1e18; while (r - l > 1) { long long m = (l + r) / 2; long long hits = m / X + m / Y; if (hits >= A) r = m; else l = m; } if (r % Y == 0 && r % X == 0) cout << Both n ; else if (r % X) cout << Vanya n ; else if (r % Y) cout << Vova n ; } return 0; }
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/* Title: traffic_fsm.v
* Author: Sergiy Kolodyazhnyy <>
* Date: April 20, 2017
* Purpose: Implementation of traffic control system as Moore FSM
* Developed on: Ubuntu 16.04 LTS , Quartus Prime Lite 16.1
* Tested on: DE1-SoC , Cyclone V , 5CSEMA5F31
* TODO: implement the pedestrian timer in cross_go and main_go states
*/
module traffic_fsm(hex_pins,main_lights,cross_lights,sensors,clk);
input clk; // Cyclone's 50MHz clock
/*
* left main - sensors[0]
* left cross - sensors[1]
* traffic cross - sensors[2]
* walk main - sensors[3]
* walk cross - sensors[4]
*/
input [4:0] sensors;
// order of the lights:
// red,yellow,green,yellow_arrow,green_arrow
output reg [4:0] main_lights;
output reg [4:0] cross_lights;
output [6:0] hex_pins;
reg [3:0] state;
// constants for idiomatic state definitions
parameter main_go=0,cross_go=1,
main_wait=2,cross_wait=3,
main_arrow_go=4,cross_arrow_go=5,
main_arrow_wait=6,cross_arrow_wait=7,
all_stop=8;
reg [3:0] sleep;
wire [3:0] current_count; // counter output
/* These registers help keeping track of which states have
* been visited during transitions between a specific "go"
* state and "all_stop" state.
*/
reg cross_tracker,cross_arrow_tracker,main_arrow_tracker;
//module timer(counter,duration,clk);
timer tm0(current_count,sleep,clk);
//module seven_seg_decoder(led_out,bin_in);
seven_seg_decoder ssd(hex_pins,current_count);
// ensure we start out with main street traffic
initial
begin
state <= main_go;
sleep <= 6;
end
// output logic
always @(posedge clk)
begin
case(state)
main_go:
begin
main_lights <= 5'b00100;
cross_lights <= 5'b10000;
end
cross_go:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b00100;
end
main_wait:
begin
main_lights <= 5'b01000;
cross_lights <= 5'b10000;
end
cross_wait:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b01000;
end
main_arrow_go:
begin
main_lights <= 5'b00001;
cross_lights <= 5'b10000;
end
cross_arrow_go:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b00001;
end
main_arrow_wait:
begin
main_lights <= 5'b00010;
cross_lights <= 5'b10000;
end
cross_arrow_wait:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b00010;
end
all_stop:
begin
main_lights <= 5'b10000;
cross_lights <= 5'b10000;
end
endcase
end
/*
* This portion handles state transitions and propagates
* new value to the timer that keeps FSM in specific states
*
*/
always @(posedge clk)
begin
if(state == main_go && (sensors[0]|sensors[1]|sensors[2]|sensors[4]))
begin
if( current_count == 4'b0001 )
sleep = 4;
if( current_count == 4'b0000 )
state = main_wait;
end
else if(state == main_wait || state == cross_wait ||
state == main_arrow_wait || state == cross_arrow_wait)
begin
if( current_count == 4'b0001 )
sleep = 3;
if( current_count == 4'b000)
state = all_stop;
end
else if(state == cross_go)
begin
if( current_count == 4'b0001 )
begin
cross_tracker = 1'b1;
sleep = 3;
if (sensors[1])
cross_arrow_tracker = 1'b1;
if (sensors[0])
main_arrow_tracker = 1'b1;
end
if( current_count == 4'b0000 )
state = cross_wait;
end
else if(state == cross_arrow_go)
begin
if( current_count == 4'b0001 )
begin
sleep = 3;
cross_arrow_tracker = 1'b0;
end
if( current_count == 4'b0000 )
state = cross_arrow_wait;
end
else if(state == main_arrow_go)
begin
if( current_count == 4'b0001 )
begin
sleep = 3;
main_arrow_tracker = 1'b0;
end
if( current_count == 4'b0000 )
state = main_arrow_wait;
end
else if(state == all_stop)
begin
// we've come from main_go state, and there's cross traffic waiting
if ( current_count == 4'b0001 && ~cross_tracker )
sleep = 6;
if ( current_count == 4'b0000 && ~cross_tracker )
state = cross_go;
// we've let cross traffic go, but somebody is waiting for an arrow
if ( cross_tracker && (cross_arrow_tracker|main_arrow_tracker) )
begin
if ( current_count == 4'b0001 )
sleep = 4;
if ( current_count == 4'b0000 )
if ( cross_arrow_tracker )
state = cross_arrow_go;
else
state = main_arrow_go;
end
// we've let cross traffic go, but nobody is waiting for an arrow
else if ( cross_tracker && (~cross_arrow_tracker && ~main_arrow_tracker) )
begin
if ( current_count == 4'b0001 )
sleep = 6;
if ( current_count == 4'b0000 )
begin
cross_tracker = 1'b0;
state = main_go;
end
end
end
end // End of transition logic
endmodule
/* This module returns countdown value from initial value
* "duration" to 0. The module uses Cyclone's 50MHz clock
* which ticks at 50 million times each second, thus counter
* is decremented each second
*/
module timer(counter,duration,clk);
input clk;
input [3:0] duration;
output reg [3:0] counter;
reg [25:0] ticker;
parameter tick_count = 49999999;
initial
begin
ticker <= tick_count;
counter <= duration;
end
always @(posedge clk)
begin
// checking counter status is most important
// hence it's top most statement
if ( counter == 0)
begin
ticker <= tick_count;
counter <= duration;
end
ticker <= ticker - 1;
if ( ticker == 0 )
counter <= counter - 1;
end
endmodule
/* This module is technically boilerplate code
* that is reused from Lab 3. Uses data flow modeling.
*/
module seven_seg_decoder(led_out,bin_in);
output [6:0] led_out;
input [3:0] bin_in;
wire [3:0] bin_in_inv;
assign bin_in_inv = ~bin_in;
/* A => bin_in[3]
* B => bin_in[2]
* C => bin_in[1]
* D => bin_in[0]
*/
//led_out[6] = A’B’C’ + A’BCD + ABC’D’
assign led_out[6] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1]) |
(bin_in_inv[3] & bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]);
//led_out[5] = A’B’D + A’B’C + A’CD +ABC’D
assign led_out[5] = (bin_in_inv[3] & bin_in_inv[2] & bin_in[0]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
//led_out[4] = A’D + B’C’D + A’BC’
assign led_out[4] = (bin_in_inv[3] & bin_in[0]) |
(bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1]);
//led_out[3] = B’C’D + BCD + A’BC’D’ + AB’CD’
assign led_out[3] = (bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in[2] & bin_in[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
//led_out[2] = ABD’ + ABC + A’B’CD’
assign led_out[2] = (bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in[3] & bin_in[2] & bin_in[1]) |
(bin_in_inv[3] & bin_in_inv[2] & bin_in[1] & bin_in_inv[0]);
//led_out[1] = BCD’ + ACD + ABD’ + A’BC’D
assign led_out[1] = (bin_in[2] & bin_in[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
//led_out[0] = A’B’C’D + A’BC’D’ + AB’CD + ABC’D
assign led_out[0] = (bin_in_inv[3] & bin_in_inv[2] & bin_in_inv[1] & bin_in[0]) |
(bin_in_inv[3] & bin_in[2] & bin_in_inv[1] & bin_in_inv[0]) |
(bin_in[3] & bin_in_inv[2] & bin_in[1] & bin_in[0]) |
(bin_in[3] & bin_in[2] & bin_in_inv[1] & bin_in[0]);
endmodule
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#include <bits/stdc++.h> using namespace std; template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; string sep; for (const auto &x : v) os << sep << x, sep = , ; return os << } ; } template <typename T, size_t size> ostream &operator<<(ostream &os, const array<T, size> &arr) { os << { ; string sep; for (const auto &x : arr) os << sep << x, sep = , ; return os << } ; } template <typename A, typename B> ostream &operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << << H; dbg_out(T...); } auto random_address = [] { char *p = new char; delete p; return (uint64_t)p; }; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count() * (random_address() | 1)); template <typename T> void output_vector(const vector<T> &v, bool add_one = false, int start = -1, int end = -1) { if (start < 0) start = 0; if (end < 0) end = int(v.size()); for (int i = start; i < end; i++) cout << v[i] + (add_one ? 1 : 0) << (i < end - 1 ? : n ); } const int ATTEMPTS = 50; int N, M; vector<vector<int>> adj; vector<int> tour_index; vector<array<int, 2>> low_link; vector<bool> in_stack; int tour; vector<int> tour_list; array<int, 2> combine(array<int, 2> x, int y) { array<int, 3> a = {x[0], x[1], y}; sort(a.begin(), a.end()); return {a[0], a[1]}; } array<int, 2> combine(array<int, 2> x, array<int, 2> y) { array<int, 4> a = {x[0], x[1], y[0], y[1]}; sort(a.begin(), a.end()); return {a[0], a[1]}; } bool interesting_dfs(int node) { tour_index[node] = tour++; tour_list.push_back(node); low_link[node] = {tour_index[node], tour_index[node]}; in_stack[node] = true; for (int neighbor : adj[node]) if (tour_index[neighbor] < 0) { if (!interesting_dfs(neighbor)) return false; low_link[node] = combine(low_link[node], low_link[neighbor]); } else if (in_stack[neighbor]) { low_link[node] = combine(low_link[node], tour_index[neighbor]); } else { return false; } in_stack[node] = false; return true; } vector<int> save_interesting; bool check_interesting(int node) { if (save_interesting[node] >= 0) return save_interesting[node]; tour_index.assign(N, -1); low_link.resize(N); in_stack.assign(N, false); tour = 0; tour_list.clear(); return (save_interesting[node] = interesting_dfs(node)); } void run_case() { cin >> N >> M; adj.assign(N, {}); for (int i = 0; i < M; i++) { int u, v; cin >> u >> v; u--; v--; adj[u].push_back(v); } save_interesting.assign(N, -1); int root = -1; for (int iter = 0; iter < ATTEMPTS; iter++) { root = int(rng() % N); if (check_interesting(root)) break; root = -1; } if (root < 0) { cout << -1 << n ; return; } vector<bool> bad(N, false); for (int x : tour_list) if (low_link[x][0] < tour_index[x] && low_link[x][1] < tour_index[x]) { bad[x] = true; } else { assert(low_link[x][1] == tour_index[x]); int above = tour_list[low_link[x][0]]; bad[x] = bad[above]; } vector<int> interesting; for (int i = 0; i < N; i++) if (!bad[i]) interesting.push_back(i); if (5 * int(interesting.size()) < N) cout << -1 << n ; else output_vector(interesting, true); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int tests; cin >> tests; while (tests-- > 0) run_case(); }
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#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; long long a[N]; long long dp[N][20]; int main() { int n, m, k; cin >> n >> m >> k; a[0] = 0; for (int i = 1; i <= m; i++) dp[0][i] = -1e10; long long ans = 0; for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); for (int j = 1; j <= m; j++) { if (j == 1) dp[i][j] = max(a[i] - k, dp[i - 1][m] + a[i] - k); else dp[i][j] = dp[i - 1][j - 1] + a[i]; ans = max(ans, dp[i][j]); } } printf( %I64d n , ans); return 0; }
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#include <bits/stdc++.h> #include <string> using namespace std; bool susp() { int n; cin >> n; string days; cin >> days; for (int i = 0; i < n - 1; i++) { for (int j = i + 1; j < n; j++) { if (days[j] == days[i] && days[j - 1] != days[i]) return false; } } return true; } int main() { int t; cin >> t; bool cases[t]; for (int i = 0; i < t; i++) { cases[i] = susp(); } for (bool b : cases) { if (b) cout << YES << endl; else cout << NO << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5, inf = 1e9 + 7; long long n, k, i, j; long long A[N], l[N], r[N], len[N]; set<pair<long long, long long> > st; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long i, j, a, b, ans = 0, cur; cin >> n; for (i = 1; i < n + 1; i++) cin >> A[i]; i = 1; while (i <= n) { j = i; while (j <= n && A[j] == A[i]) j++; r[i] = j; l[j] = i; len[i] = j - i; st.insert(pair<long long, long long>(i - j, i)); i = j; } while (!st.empty()) { cur = st.begin()->second; st.erase(st.begin()); ans++; len[cur] = 0; a = l[cur]; b = r[cur]; if (st.empty()) break; if (A[a] == A[b] && a > 0 && b <= n) { st.erase(pair<long long, long long>(-len[a], a)); st.erase(pair<long long, long long>(-len[b], b)); r[a] = r[b]; l[r[a]] = a; len[a] += len[b]; len[b] = 0; st.insert(pair<long long, long long>(-len[a], a)); } else { r[a] = b; l[b] = a; } } cout << ans; }
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#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const int dir[8][2] = {{0, 1}, {1, 0}, {0, -1}, {-1, 0}, {1, 1}, {1, -1}, {-1, -1}, {-1, 1}}; const int mod = 1e9 + 7, gakki = 5 + 2 + 1 + 19880611 + 1e9; const int MAXN = 1e6 + 5, MAXM = 1e6 + 5; const int MAXQ = 100010, INF = 1e9; inline void read(int &v) { v = 0; char c = 0; int p = 1; while (c < 0 || c > 9 ) { if (c == - ) { p = -1; } c = getchar(); } while (c >= 0 && c <= 9 ) { v = (v << 3) + (v << 1) + c - 0 ; c = getchar(); } v *= p; } int n, m; int len; int anser = INT_MAX; int num[55]; void dfs(int x, int where, int sum) { for (int i = x + 1; i <= len; i++) { if (num[i] >= num[x] + 2) { if (where == m - 1) { anser = min(anser, sum + num[i]); return; } dfs(i, where + 1, sum + num[i]); break; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; string ch; cin >> ch; len = ch.size(); for (int i = 0; i < len; i++) { num[i + 1] = (ch[i] - a ) + 1; } sort(num + 1, num + 1 + len); num[len + 1] = INT_MAX; if (m == 1) { cout << num[1] << endl; return 0; } for (int i = 1; i <= len - m + 1; i++) { dfs(i, 1, num[i]); } if (anser == INT_MAX) { cout << -1 << endl; } else { cout << anser << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1100; const int M = 256; const int K = 26; const int INF = 2000000000; const double eps = 1e-12; int k, m, n, d[K], a[N]; char s[N]; bool ok; int F(); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; k = 1; for (int i = 0; i < 26; i++) d[i] = k, k <<= 1; for (int i = 0; i < n; i++) { cin >> s; m = 0; for (int j = 0; s[j]; j++) m = m | d[s[j] - a ]; a[i] = m; } sort(a, a + n); m = 1; for (int i = 1; i < n; i++) if (a[i] != a[i - 1]) m++; cout << m; return 0; } int F() { return 0; }
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// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 22233 $
// $Date: 2010-10-09 13:26:19 +0000 (Sat, 09 Oct 2010) $
`ifdef BSV_NO_MAIN_V
`else
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_TIMESCALE
`timescale `BSV_TIMESCALE
`endif
module main();
reg CLK;
// reg CLK_GATE;
reg RST_N;
reg [31:0] cycle;
reg do_vcd;
reg do_fsdb;
reg do_fst;
reg do_cycles;
`TOP top(.CLK(CLK), /* .CLK_GATE(CLK_GATE), */ .RST_N(RST_N));
// For Sce-Mi linkage, insert code here
`ifdef BSV_SCEMI_LINK
`include `BSV_SCEMI_LINK
`endif
`ifdef BSV_DUMP_LEVEL
`else
`define BSV_DUMP_LEVEL 0
`endif
`ifdef BSV_DUMP_TOP
`else
`define BSV_DUMP_TOP main
`endif
initial begin
// CLK_GATE = 1'b1;
// CLK = 1'b0; // This line will cause a neg edge of clk at t=0!
// RST_N = 1'b0; // This needs #0, to allow always blocks to wait
cycle = 0;
do_vcd = $test$plusargs("bscvcd") ;
do_fst = $test$plusargs("bscfst") ;
do_fsdb = $test$plusargs("bscfsdb") ;
do_cycles = $test$plusargs("bsccycle") ;
`ifdef BSC_FSDB
if (do_fsdb) begin
$fsdbDumpfile("dump.fsdb");
$fsdbDumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
end
`else
// if (do_fst && ! do_vcd) begin
// $dumpfile("|vcd2fst -F -f dump.fst -");
// $dumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
// end
if (do_vcd) begin
$dumpfile("dump.vcd");
$dumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
end
`endif
#0
RST_N = 1'b0;
#1;
CLK = 1'b1;
// $display("reset");
#1;
RST_N = 1'b1;
// $display("reset done");
// #200010;
// $finish;
end
`ifndef NO_CLOCK // for cosim
always
begin
#1
if (do_cycles)
$display("cycle %0d", cycle) ;
cycle = cycle + 1 ;
#4;
CLK = 1'b0 ;
#5;
CLK = 1'b1 ;
end // always begin
`endif // `ifndef NO_CLOCK
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; void run() { long long n; cin >> n; long long p[n]; for (long long i = 0; i < n; i++) cin >> p[i]; for (long long i = 0; i < n; i++) { if (p[i] == 0) p[i] = -1; if (p[i] != -1) p[i] %= 2; } long long ones = 0, zeros = 0; for (long long i = 1; i <= n; i++) { if (i % 2) ones++; else zeros++; } for (long long i = 0; i < n; i++) { if (p[i] == 0) zeros--; else if (p[i] == 1) ones--; } long long dp[n][zeros + 1][ones + 1][2]; for (long long i = 0; i < n; i++) { for (long long j = 0; j < zeros + 1; j++) { for (long long k = 0; k < ones + 1; k++) { for (long long l = 0; l < 2; l++) dp[i][j][k][l] = 1e9; } } } if (p[0] != -1) dp[0][0][0][p[0]] = 0; else { dp[0][1][0][0] = 0; dp[0][0][1][1] = 0; } for (long long i = 1; i < n; i++) { for (long long j = 0; j < zeros + 1; j++) { for (long long k = 0; k < ones + 1; k++) { if (p[i] == -1) { if (j + 1 <= zeros) dp[i][j + 1][k][0] = min(dp[i - 1][j][k][0], dp[i - 1][j][k][1] + 1); if (k + 1 <= ones) dp[i][j][k + 1][1] = min(dp[i - 1][j][k][1], dp[i - 1][j][k][0] + 1); } else dp[i][j][k][p[i]] = min(dp[i - 1][j][k][p[i]], dp[i - 1][j][k][1 - p[i]] + 1); } } } cout << min(dp[n - 1][zeros][ones][0], dp[n - 1][zeros][ones][1]); } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; run(); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2008 by Wilson Snyder.
module t (clk);
input clk;
integer cyc; initial cyc=1;
integer sum;
integer cpre;
always @ (posedge clk) begin
if (cyc!=0) begin
cpre = cyc;
cyc <= cyc + 1;
if (cyc==1) begin
if (mlog2(32'd0) != 32'd0) $stop;
if (mlog2(32'd1) != 32'd0) $stop;
if (mlog2(32'd3) != 32'd2) $stop;
sum <= 32'd0;
end
else if (cyc<90) begin
// (cyc) so if we trash the variable things will get upset.
sum <= mlog2(cyc) + sum * 32'd42;
if (cpre != cyc) $stop;
end
else if (cyc==90) begin
if (sum !== 32'h0f12bb51) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function integer mlog2;
input [31:0] value;
integer i;
begin
if(value < 32'd1) begin
mlog2 = 0;
end
else begin
value = value - 32'd1;
mlog2 = 0;
for(i=0;i<32;i=i+1) begin
if(value > 32'd0) begin
mlog2 = mlog2 + 1;
end
value = value >> 1;
end
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; bitset<2005> a[2005]; int pos[2005]; int ans[2005]; bool gause(int n, int m) { int d = 1; for (int i = 1; i <= n; i++) { if (!a[d][i]) { for (int j = d + 1; j <= m; j++) if (a[j][i]) { swap(a[d], a[j]); break; } } if (!a[d][i]) continue; pos[d] = i; for (int j = 1; j <= m; j++) if (j != d && a[j][i]) a[j] ^= a[d]; d++; } for (int i = d; i <= m; i++) if (a[i][n + 1]) return 0; for (int i = 1; i < d; i++) ans[pos[i]] = a[i][n + 1]; return 1; } bool num[1005][4]; int id[128], cur[1005]; const char *val = .RYB ; int main() { id[ W ] = 0; id[ R ] = 1; id[ Y ] = 2; id[ B ] = 3; int n, m; scanf( %d%d , &n, &m); int sz = 0; for (int i = 1; i <= n; i++) num[i][0] = num[i][3] = 1; for (int i = 1; i <= m; i++) { char str[5]; int k; scanf( %s%d , str, &k); for (int j = 1; j <= k; j++) scanf( %d , &cur[j]); if (str[0] == m ) { scanf( %s , str); int v = id[str[0]]; ++sz; for (int j = 1; j <= k; j++) { int x = cur[j]; if (num[x][0]) a[sz].flip(2 * x - 1); if (num[x][1]) a[sz].flip(2 * x); } if (v & 1) a[sz].flip(2 * n + 1); ++sz; for (int j = 1; j <= k; j++) { int x = cur[j]; if (num[x][2]) a[sz].flip(2 * x - 1); if (num[x][3]) a[sz].flip(2 * x); } if ((v >> 1) & 1) a[sz].flip(2 * n + 1); } else if (str[0] == R && str[1] == Y ) { for (int j = 1; j <= k; j++) { int x = cur[j]; swap(num[x][0], num[x][2]); swap(num[x][1], num[x][3]); } } else if (str[0] == R && str[1] == B ) { for (int j = 1; j <= k; j++) { int x = cur[j]; num[x][2] ^= num[x][0]; num[x][3] ^= num[x][1]; } } else { for (int j = 1; j <= k; j++) { int x = cur[j]; num[x][0] ^= num[x][2]; num[x][1] ^= num[x][3]; } } } if (!gause(2 * n, sz)) { puts( NO ); return 0; } puts( YES ); for (int i = 1; i <= n; i++) { int s = (ans[2 * i - 1] ^ (ans[2 * i] << 1)); putchar(val[s]); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n1, n2, n3, n4; long long ans; unordered_map<char, int> m; string s; while (cin >> n1 >> n2 >> n3 >> n4) { ans = 0; m[ 1 ] = n1; m[ 2 ] = n2; m[ 3 ] = n3; m[ 4 ] = n4; cin >> s; for (int i = 0; i < s.size(); i++) { ans += m[s[i]]; } cout << ans << endl; } return 0; }
|
module wb_upsizer_tb
(input wb_clk_i,
input wb_rst_i,
output done);
localparam aw = 32;
localparam MEMORY_SIZE_WORDS = 2**10;
localparam DW_IN = 32;
localparam SCALE = 2;
localparam DW_OUT = DW_IN * SCALE;
wire [aw-1:0] wbm_m2s_adr;
wire [DW_IN-1:0] wbm_m2s_dat;
wire [DW_IN/8-1:0] wbm_m2s_sel;
wire wbm_m2s_we ;
wire wbm_m2s_cyc;
wire wbm_m2s_stb;
wire [2:0] wbm_m2s_cti;
wire [1:0] wbm_m2s_bte;
wire [DW_IN-1:0] wbm_s2m_dat;
wire wbm_s2m_ack;
wire wbm_s2m_err;
wire wbm_s2m_rty;
wire [aw-1:0] wbs_m2s_adr;
wire [DW_OUT-1:0] wbs_m2s_dat;
wire [DW_OUT/8-1:0] wbs_m2s_sel;
wire wbs_m2s_we ;
wire wbs_m2s_cyc;
wire wbs_m2s_stb;
wire [2:0] wbs_m2s_cti;
wire [1:0] wbs_m2s_bte;
wire [DW_OUT-1:0] wbs_s2m_dat;
wire wbs_s2m_ack;
wire wbs_s2m_err;
wire wbs_s2m_rty;
wire [31:0] slave_writes;
wire [31:0] slave_reads;
wb_bfm_transactor
#(.MEM_HIGH(MEMORY_SIZE_WORDS-1),
.MEM_LOW (0),
.VERBOSE (0))
wb_bfm_transactor0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wbm_m2s_adr),
.wb_dat_o (wbm_m2s_dat),
.wb_sel_o (wbm_m2s_sel),
.wb_we_o (wbm_m2s_we ),
.wb_cyc_o (wbm_m2s_cyc),
.wb_stb_o (wbm_m2s_stb),
.wb_cti_o (wbm_m2s_cti),
.wb_bte_o (wbm_m2s_bte),
.wb_dat_i (wbm_s2m_dat),
.wb_ack_i (wbm_s2m_ack),
.wb_err_i (wbm_s2m_err),
.wb_rty_i (wbm_s2m_rty),
//Test Control
.done(done));
integer idx;
always @(done) begin
if(done === 1) begin
$display("Average wait times");
$display("Master : %f", ack_delay/num_transactions);
$display("%0d : All tests passed!", $time);
end
end
wb_upsizer
#(.DW_IN (DW_IN),
.SCALE (SCALE))
dut
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
// Master Interface
.wbs_adr_i (wbm_m2s_adr),
.wbs_dat_i (wbm_m2s_dat),
.wbs_sel_i (wbm_m2s_sel),
.wbs_we_i (wbm_m2s_we ),
.wbs_cyc_i (wbm_m2s_cyc),
.wbs_stb_i (wbm_m2s_stb),
.wbs_cti_i (wbm_m2s_cti),
.wbs_bte_i (wbm_m2s_bte),
.wbs_dat_o (wbm_s2m_dat),
.wbs_ack_o (wbm_s2m_ack),
.wbs_err_o (wbm_s2m_err),
.wbs_rty_o (wbm_s2m_rty),
// Wishbone Slave interface
.wbm_adr_o (wbs_m2s_adr),
.wbm_dat_o (wbs_m2s_dat),
.wbm_sel_o (wbs_m2s_sel),
.wbm_we_o (wbs_m2s_we),
.wbm_cyc_o (wbs_m2s_cyc),
.wbm_stb_o (wbs_m2s_stb),
.wbm_cti_o (wbs_m2s_cti),
.wbm_bte_o (wbs_m2s_bte),
.wbm_dat_i (wbs_s2m_dat),
.wbm_ack_i (wbs_s2m_ack),
.wbm_err_i (wbs_s2m_err),
.wbm_rty_i (wbs_s2m_rty));
assign slave_writes = mem.writes;
assign slave_reads = mem.reads;
time start_time;
time ack_delay;
integer num_transactions;
initial begin
ack_delay = 0;
num_transactions = 0;
while(1) begin
@(posedge wbm_m2s_cyc);
start_time = $time;
@(posedge wbm_s2m_ack);
ack_delay = ack_delay + $time-start_time;
num_transactions = num_transactions+1;
end
end
wb_bfm_memory #(.DEBUG (0),
.dw (DW_OUT),
.mem_size_bytes(MEMORY_SIZE_WORDS*(DW_IN/8)))
mem
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (wbs_m2s_cti),
.wb_bte_i (wbs_m2s_bte),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (wbs_s2m_err),
.wb_rty_o (wbs_s2m_rty));
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pcie_pipe_misc.v
// Version : 1.3
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_3_pcie_pipe_misc #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter TCQ = 1; // clock to out delay model
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PG_N_TB_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PG_N_TB_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 RESET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 RESET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 RESET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 RESET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; long long n, k; int main() { cin >> n >> k; long long falta = (n % k); long long ans = n + (k - falta); cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using ll = long long; const int MN = 1e5 + 100; const int MP = 1e4 + 100; const int MOD = 1e9 + 7; ll pw(ll b, int p) { ll r = 1LL; for (; p; p >>= 1, b = b * b % MOD) if (p & 1) r = r * b % MOD; return r; } int N, K; int p[MP], q[MN]; int t[MN], l[MN], T[MN]; void pcpp(void) { for (int i = 2; i <= N; ++i) { if (!q[i]) t[i] = i - 1, p[l[i] = ++p[0]] = i; for (int j = 1, k; j <= p[0] && (k = i * p[j]) <= N; ++j) { assert(!q[k]), q[k] = 1, l[k] = j; if (l[i] == j) { t[k] = t[i] * p[j]; break; } t[k] = t[i] * (p[j] - 1); } } } ll v[MN], f, z[MN]; int main(void) { scanf( %d%d , &N, &K); pcpp(); z[0] = 1LL, z[1] = pw(K, MOD - 2); for (int i = 1; i < N; ++i) z[i + 1] = z[i] * z[1] % MOD; for (int i = 0; i <= N; ++i) T[i + 1] = (t[i] + T[i]) % MOD; for (int i = 1; i < N; ++i) v[i] = N - i - 1; for (int g = 1; g < N; ++g) { int k = (N + g - 1) / g; v[g] += T[k + 1]; if (k * g > N) v[k * g - N] -= t[k]; } for (int i = 1; i < N; ++i) f += v[i] * z[N - i] % MOD; printf( %lld n , f % MOD); return 0; }
|
// Testbench for ltcminer_icarus.v
`timescale 1ns/1ps
`ifdef SIM // Avoids wrong top selected if included in ISE/PlanAhead sources
module test_ltcminer ();
reg clk = 1'b0;
reg [31:0] cycle = 32'd0;
initial begin
clk = 0;
while(1)
begin
#5 clk = 1; #5 clk = 0;
end
end
always @ (posedge clk)
begin
cycle <= cycle + 32'd1;
end
// Running with default zero's for the data1..3 regs.
// tx_hash=553a4b69b43913a61b42013ce210f713eaa7332e48cda1bdf3b93b10161d0876 at 187,990 nS and
// final_hash (if SIM is defined) at 188,000 nS with golden_nonce_match flag NOT set since it is
// not a diff=32 share. To test golden_nonce, just tweak the target eg 31'hffffffff will match everything
// With serial input(at comm_clk_frequency=1_000_000), we get rx_done at t=70,220nS, however there is already a
// PBKDF2_SHA256_80_128 loaded in Xbuf (for nonce=00000001). The first final_hash at 188,000 nS is corrupted as
// the input data has changed from all 0's. The Xbuf starts salsa rom at t=188,000 but the nonce is incorrectly
// taken from the newly loaded data so once salsa in complete it also generates a corrupt final_hash at ~362,000 nS.
// Nonce is incremented then the newly loaded data starts PBKDF2_SHA256_80_128, so we must supply a nonce 1 less
// than the expected golden_nonce. The correct PBKDF2_SHA256_80_128 is ready at ~ 197,000 nS. We get final_hash for
// the corrupted work at ~362,000 nS then our required golden_nonce is at 536,180 nS.
// This is only really a problem for simulation. With live hashing we just lose 2 nonces every time getwork is
// loaded, which isn't a big deal.
wire RxD;
wire TxD;
wire extminer_rxd = 0;
wire extminer_txd;
wire [3:0] dip = 0;
wire [3:0] led;
wire TMP_SCL=1, TMP_SDA=1, TMP_ALERT=1;
parameter comm_clk_frequency = 1_000_000; // Speeds up serial loading enormously rx_done is at t=70,220nS
parameter baud_rate = 115_200;
ltcminer_icarus #(.comm_clk_frequency(comm_clk_frequency)) uut
(clk, RxD, TxD, led, extminer_rxd, extminer_txd, dip, TMP_SCL, TMP_SDA, TMP_ALERT);
// Send serial data - 84 bytes, matches on nonce 318f (included in data)
// NB starting nonce is 381e NOT 381f (see note above)
reg [671:0] data = 672'h000007ff0000318e7e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg serial_send = 0;
wire serial_busy;
reg [31:0] data_32 = 0;
reg [31:0] start_cycle = 0;
serial_transmit #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) sertx (.clk(clk), .TxD(RxD), .send(serial_send), .busy(serial_busy), .word(data_32));
// TUNE this according to comm_clk_frequency so we send a single getwork (else it gets overwritten with 0's)
// parameter stop_cycle = 7020; // For comm_clk_frequency=1_000_000
parameter stop_cycle = 0; // Use this to DISABLE sending data
always @ (posedge clk)
begin
serial_send <= 0; // Default
// Send data every time tx goes idle (NB the !serial_send is to prevent serial_send
// going high for two cycles since serial_busy arrives one cycle after serial_send)
if (cycle > 5 && cycle < stop_cycle && !serial_busy && !serial_send)
begin
serial_send <= 1;
data_32 <= data[671:640];
data <= { data[639:0], 32'd0 };
start_cycle <= cycle; // Remember each start cycle (makes debugging easier)
end
end
endmodule
`endif
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#include <bits/stdc++.h> using namespace std; const double EPS = 1e-6; double n, r; bool check(double R) { double x1 = r + R; double y1 = 0; double x2 = cos(2 * acos(-1) / n) * (r + R); double y2 = sin(2 * acos(-1) / n) * (r + R); double len = sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); if (len <= 2 * R) return true; else return false; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> r; double l1 = 0, r1 = 10000; for (int i = 0; i < 500; i++) { double mm = (l1 + r1) / 2.0; if (check(mm)) r1 = mm; else l1 = mm; } cout.fixed; cout.precision(15); cout << l1; return 0; }
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#include <bits/stdc++.h> using namespace std; long long a[200005], dp1[200005], dp2[200005]; int main() { long long n, k, x; int xx; cin >> n >> k >> x; for (int i = 1; i <= n; i++) { scanf( %d , &xx); a[i] = xx; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { if (i != 1) { dp1[i] = dp1[i - 1] | a[i - 1]; } } for (int i = n; i >= 1; i--) { dp2[i] = dp2[i + 1] | a[i + 1]; } long long mx = 0; long long pw = 1; for (int i = 1; i <= k; i++) { pw *= x; } for (int i = n; i >= 1; i--) { mx = max(mx, ((pw * a[i]) | dp1[i] | dp2[i])); } cout << mx; }
|
#include <bits/stdc++.h> bool commonDigits(long a, long b) { bool digits[10] = {0}; bool output(0); while (a > 0) { digits[a % 10] = 1; a /= 10; } while (b > 0) { if (digits[b % 10]) { output = 1; break; }; b /= 10; } return output; } int main() { long n(0); scanf( %ld , &n); long total(0); std::vector<long> divisors; for (long k = 1; k <= sqrt(n); k++) { if (n % k == 0) { divisors.push_back(k); if (n / k > k) { divisors.push_back(n / k); } } } for (long k = 0; k < divisors.size(); k++) { if (commonDigits(n, divisors[k])) { ++total; } } printf( %ld n , total); return 0; }
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#include <bits/stdc++.h> using namespace std; const int Nmax = 1e5 + 5, lg = 16; struct updates { int l, x, y, id; bool operator<(const updates &other) const { if (l != other.l) return l > other.l; return id < other.id; } }; vector<updates> upd; vector<int> v[Nmax]; struct Node { int s, l, r; bool full; Node() { s = l = r = full = 0; } Node(int S, int L, int R, bool Full) { s = S; l = L; r = R; full = Full; } }; int f[Nmax], x, y, w, i, answer[Nmax], n, q; Node combina(Node a, Node b) { if (a.full && b.full) return Node(0, a.l + b.l, a.r + b.r, 1); if (a.full) return Node(b.s, a.l + b.l, b.r, 0); if (b.full) return Node(a.s, a.l, a.r + b.r, 0); return Node(a.s + b.s + f[a.r + b.l], a.l, b.r, 0); } class SegmentTree { Node *a; public: void build(int sz) { a = new Node[4 * sz + 5]; } void update(int node, int st, int dr, int pos) { if (st == dr) { a[node].s = 0; a[node].l = a[node].r = a[node].full = 1; return; } if (pos <= ((st + dr) / 2)) update((node << 1), st, ((st + dr) / 2), pos); else update(((node << 1) + 1), ((st + dr) / 2) + 1, dr, pos); a[node] = combina(a[(node << 1)], a[((node << 1) + 1)]); } Node query(int node, int st, int dr, int Left, int Right) { if (Left <= st && dr <= Right) return a[node]; if (Left <= ((st + dr) / 2) && ((st + dr) / 2) < Right) return combina( query((node << 1), st, ((st + dr) / 2), Left, Right), query(((node << 1) + 1), ((st + dr) / 2) + 1, dr, Left, Right)); if (Left <= ((st + dr) / 2)) return query((node << 1), st, ((st + dr) / 2), Left, Right); else return query(((node << 1) + 1), ((st + dr) / 2) + 1, dr, Left, Right); } } aint[Nmax]; class HeavyPath { int level[Nmax], dad[Nmax], to[Nmax], pos[Nmax], w[Nmax], sz[Nmax], First[Nmax], t[Nmax][lg + 2], nrChains; void dfs(int node) { for (auto i = 1; i <= lg; ++i) t[node][i] = t[t[node][i - 1]][i - 1]; w[node] = 1; for (auto it : v[node]) if (!level[it]) { level[it] = level[node] + 1; dad[it] = t[it][0] = node; dfs(it); w[node] += w[it]; } } void chains(int node) { to[node] = nrChains; pos[node] = ++sz[nrChains]; if (v[node].size() == 1 && node != 1) return; int xson = 0; for (auto it : v[node]) if (it != dad[node] && w[xson] < w[it]) xson = it; chains(xson); for (auto it : v[node]) if (it != dad[node] && it != xson) { First[++nrChains] = it; chains(it); } } Node query(int x, int y) { if (to[x] == to[y]) return aint[to[x]].query(1, 1, sz[to[x]], pos[x], pos[y]); return combina(query(x, dad[First[to[y]]]), aint[to[y]].query(1, 1, sz[to[y]], 1, pos[y])); } public: void prepare() { memset(level, 0, sizeof(level)); level[1] = 1; dad[1] = 0; dfs(1); nrChains = 1; First[1] = 1; memset(sz, 0, sizeof(sz)); chains(1); int i; for (i = 1; i <= nrChains; ++i) aint[i].build(sz[i]); } int get_answer(int x, int y) { int X = x, Y = y; if (level[x] < level[y]) swap(x, y), swap(X, Y); int up = level[x] - level[y] - 1, i; if (up != -1) { for (i = 0; i <= lg; ++i) if (up & (1 << i)) x = t[x][i]; if (dad[x] == y) { auto ans = query(x, X); if (ans.full) return f[ans.l]; return ans.s + f[ans.l] + f[ans.r]; } x = dad[x]; } for (i = lg; i >= 0; --i) if (t[x][i] != t[y][i]) x = t[x][i], y = t[y][i]; auto ans1 = query(x, X), ans2 = query(y, Y); swap(ans2.l, ans2.r); ans1 = combina(ans2, ans1); if (ans1.full) return f[ans1.l]; return ans1.s + f[ans1.l] + f[ans1.r]; } void add_edge(int x, int y) { if (y == dad[x]) swap(x, y); aint[to[y]].update(1, 1, sz[to[y]], pos[y]); } } hp; int main() { cin.sync_with_stdio(false); cin >> n >> q; for (i = 1; i < n; ++i) cin >> f[i]; for (i = 1; i < n; ++i) { cin >> x >> y >> w; v[x].push_back(y); v[y].push_back(x); upd.push_back({w, x, y, 0}); } for (i = 1; i <= q; ++i) { cin >> x >> y >> w; upd.push_back({w, x, y, i}); } sort(upd.begin(), upd.end()); hp.prepare(); for (auto it : upd) { if (!it.id) hp.add_edge(it.x, it.y); else answer[it.id] = hp.get_answer(it.x, it.y); } for (i = 1; i <= q; ++i) cout << answer[i] << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_2_V
`define SKY130_FD_SC_HS__NOR3B_2_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_2 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_2 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_2_V
|
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); } long long dotproduct(vector<long long>& a, vector<long long>& b) { long long sum = 0; for (long long i = 0; i < a.size(); i += 1) { sum += a[i] * b[i]; } return sum; } int main() { fast(); long long px, py, pz; long long x, y, z; cin >> px >> py >> pz >> x >> y >> z; px *= 2; py *= 2; pz *= 2; x *= 2; y *= 2; z *= 2; long long a1, a2, a3, a4, a5, a6; cin >> a1 >> a2 >> a3 >> a4 >> a5 >> a6; long long res = 0; vector<long long> zoxnv = {0, -1, 0}; vector<long long> zox2nv = {0, 1, 0}; vector<long long> xoynv = {0, 0, -1}; vector<long long> xoy2nv = {0, 0, 1}; vector<long long> yoznv = {-1, 0, 0}; vector<long long> yoz2nv = {1, 0, 0}; vector<long long> seezox = {px - (x / 2), py, pz - (z / 2)}; if (dotproduct(seezox, zoxnv) > 0) { res += a1; } vector<long long> seezox2 = {px - (x / 2), py - y, pz - (z / 2)}; if (dotproduct(seezox2, zox2nv) > 0) { res += a2; } vector<long long> seexoy = {px - (x / 2), py - (y / 2), pz}; if (dotproduct(seexoy, xoynv) > 0) { res += a3; } vector<long long> seexoy2 = {px - (x / 2), py - (y / 2), pz - z}; if (dotproduct(seexoy2, xoy2nv) > 0) { res += a4; } vector<long long> seeyoz = {px, py - (y / 2), pz - (z / 2)}; if (dotproduct(seeyoz, yoznv) > 0) { res += a5; } vector<long long> seeyoz2 = {px - x, py - (y / 2), pz - (z / 2)}; if (dotproduct(seeyoz2, yoz2nv) > 0) { res += a6; } cout << res; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_2_V
`define SKY130_FD_SC_HDLL__O221AI_2_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o221ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o221ai_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 7; int n, p[N]; deque<pair<int, int> > deq; bool mrk[N]; vector<int> dor[2]; int dfs(int v, int d) { mrk[v] = 1; if (!mrk[p[v]]) return dfs(p[v], d + 1); return d; } void add(int v, int l) { dor[l].clear(); int pnt = v; do { dor[l].push_back(pnt); pnt = p[pnt]; } while (pnt != v); } void remake(int l) { int go = dor[l].size() / 2 + 1; for (int i = 0; i < dor[l].size(); i++) { p[dor[l][i]] = dor[l][(i + go) % dor[l].size()]; } } void merge() { for (int i = 0; i < dor[0].size(); i++) { p[dor[0][i]] = dor[1][i]; p[dor[1][i]] = dor[0][(1 + i) % dor[0].size()]; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> p[i]; for (int i = 1; i <= n; i++) { if (!mrk[i]) { deq.push_back({dfs(i, 1), i}); } } sort(deq.begin(), deq.end()); while (deq.size()) { if (deq[0].first % 2) { add(deq[0].second, 0); remake(0); deq.pop_front(); continue; } if (deq.size() == 1 || deq[1].first != deq[0].first) { cout << -1; return 0; } add(deq[0].second, 0); add(deq[1].second, 1); merge(); deq.pop_front(); deq.pop_front(); } for (int i = 1; i <= n; i++) cout << p[i] << ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_TB_V
`define SKY130_FD_SC_MS__OR2_TB_V
/**
* or2: 2-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__or2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_TB_V
|
#include <bits/stdc++.h> const int N = 200100; char a[N], b[N]; int cnt[330]; int main() { int la, lb, i; long long ans = 0; scanf( %s%s , a, b); la = strlen(a), lb = strlen(b); for (i = 0; i < lb - la; i++) cnt[b[i]]++; for (i = 0; i < la; i++) { cnt[b[lb - la + i]]++; if (a[i] == 0 ) ans += cnt[ 1 ]; else ans += cnt[ 0 ]; cnt[b[i]]--; } printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> const int T_DATA = 100000; const int N = 100000; int T; int a, b; char mp[N + 10]; int n, m; int l[N + 10], r[N + 10]; int dis[N + 10]; int main() { scanf( %d , &T); while (T--) { scanf( %d %d , &a, &b); scanf( %s , mp + 1); n = strlen(mp + 1); m = 0; for (int i = 1, j; i <= n; i = j + 1) { while (i <= n && mp[i] != 1 ) ++i; if (i > n) break; for (j = i; j < n && mp[j + 1] == 1 ; ++j) ; ++m; l[m] = i, r[m] = j; } if (m == 0) { printf( 0 n ); continue; } if (m == 1) { printf( %d n , a); continue; } for (int i = 1; i <= m - 1; ++i) dis[i] = l[i + 1] - r[i] - 1; std::sort(dis + 1, dis + m); int ans = a * m; for (int ind = 1; ind <= m - 1; ++ind) { if (dis[ind] * b >= a) continue; ans -= a - dis[ind] * b; } printf( %d n , ans); } return 0; }
|
// File: Up_CounterTBV.v
// Generated by MyHDL 0.10
// Date: Tue Aug 14 06:51:20 2018
`timescale 1ns/10ps
module Up_CounterTBV (
);
// myHDL -> Verilog Testbench for `Up_Counter` module
reg clk = 0;
reg rst = 0;
wire Trig;
wire [4:0] count;
reg [4:0] Up_Counter0_0_count_i = 0;
reg Up_Counter0_0_Trig_i = 0;
always @(rst, clk, Trig, count) begin: UP_COUNTERTBV_PRINT_DATA
$write("%h", clk);
$write(" ");
$write("%h", rst);
$write(" ");
$write("%h", Trig);
$write(" ");
$write("%h", count);
$write("\n");
end
always @(posedge clk, negedge rst) begin: UP_COUNTERTBV_UP_COUNTER0_0_LOGIC
if (rst) begin
Up_Counter0_0_count_i <= 0;
Up_Counter0_0_Trig_i <= 0;
end
else if ((((Up_Counter0_0_count_i % 17) == 0) && (Up_Counter0_0_count_i != 0))) begin
Up_Counter0_0_Trig_i <= 1;
Up_Counter0_0_count_i <= 0;
end
else begin
Up_Counter0_0_count_i <= (Up_Counter0_0_count_i + 1);
end
end
assign count = Up_Counter0_0_count_i;
assign Trig = Up_Counter0_0_Trig_i;
initial begin: UP_COUNTERTBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: UP_COUNTERTBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h1a: begin
rst <= 1;
end
(-'h1): begin
rst <= 0;
end
default: begin
// pass
end
endcase
if ((i == 42)) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[1 << 20], w[25][25]; string s[25]; pair<int, int> alph[25][26]; int ma[25][26]; int cost[1 << 20]; vector<pair<int, int> > rco; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> w[i][j]; } fill(cost, cost + (1 << 20), (int)1e9); cost[0] = 0; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { cost[1 << j] = min(cost[1 << j], w[j][i]); alph[i][(s[j][i] - a )].first |= (1 << j); alph[i][(s[j][i] - a )].second += w[j][i]; ma[i][s[j][i] - a ] = max(ma[i][s[j][i] - a ], w[j][i]); } for (int j = 0; j < 26; j++) { alph[i][j].second -= ma[i][j]; cost[alph[i][j].first] = min(cost[alph[i][j].first], alph[i][j].second); } } for (int i = 1; i < (1 << 20); i++) { if (cost[i] != (int)1e9) rco.push_back(make_pair(i, cost[i])); } fill(dp, dp + (1 << n), (int)1e9); dp[0] = 0; for (int i = 0; i < rco.size(); i++) { const int mask = rco[i].first, co = rco[i].second; for (int j = 0; j < (1 << n); j++) { dp[j | mask] = min(dp[j | mask], dp[j] + co); } } cout << dp[(1 << n) - 1]; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:16:49 05/04/2013
// Design Name: mix16bitaddr
// Module Name: D:/Xilinx_ISE_Pro/maju_ASIC_FPGA/assign3/mixAdderq2/testbnc.v
// Project Name: mixAdderq2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mix16bitaddr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbnc;
// Inputs
reg [15:0] A;
reg [15:0] B;
reg Cin;
// Outputs
wire [15:0] Sum;
wire Cout;
// Instantiate the Unit Under Test (UUT)
mix16bitaddr uut (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);
integer i;
initial begin
for(i=0;i<=2**17;i=i+1) //////2^17
begin
{A,B,Cin}=i;
#5 $monitor("A=%d, B=%d, CarryIn=%d, Carryout=%d, Sum=%d",A,B,Cin,Cout,Sum);
end
$stop;end
//initial begin
//#1000;
// $stop;
//end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int ma = INT_MIN; string ans = nah ; while (n--) { string s; int s1, s2, a, b, c, d, e; cin >> s; cin >> s1 >> s2 >> a >> b >> c >> d >> e; int val = 0; val += 100 * s1 + (-50) * s2 + a + b + c + d + e; if (val > ma) { ma = val; ans = s; } } cout << ans; return 0; }
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This latency aware read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post reads until the length register
reaches a value of zero. When all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
*/
// altera message_off 10230
module latency_aware_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire too_many_pending_reads;
reg too_many_pending_reads_d1;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// control logic
assign too_many_pending_reads = (fifo_used + reads_pending) >= (FIFODEPTH - 4);
assign master_read = (length != 0) & (too_many_pending_reads_d1 == 0);
assign increment_address = (length != 0) & (too_many_pending_reads_d1 == 0) & (master_waitrequest == 0);
assign control_done = (reads_pending == 0) & (length == 0); // master done posting reads and all reads have returned
assign control_early_done = (length == 0); // if you need all the pending reads to return then use 'control_done' instead of this signal
always @ (posedge clk)
begin
if (reset == 1)
begin
too_many_pending_reads_d1 <= 0;
end
else
begin
too_many_pending_reads_d1 <= too_many_pending_reads;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + 1;
end
else
begin
reads_pending <= reads_pending; // a read was posted, but another returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // read was not posted but a read returned
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_wr_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 write requests from 4 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
#include <bits/stdc++.h> using namespace std; long long sum[400006] = {0}; long long Min[400006] = {0}; long long Max[400006] = {0}; void solve() { long long n; cin >> n; long long k; cin >> k; vector<long long> v(n); for (long long i = 0; i < n; i++) cin >> v[i]; for (long long i = 0; i <= 2 * k + 3; i++) Min[i] = Max[i] = sum[i] = 0; for (long long i = 0; i < n / 2; i++) { Max[max(v[i], v[n - i - 1])]++; Min[min(v[i], v[n - i - 1])]++; sum[v[i] + v[n - i - 1]]++; } for (long long i = 1; i <= k; i++) { Min[i] += Min[i - 1]; Max[i] += Max[i - 1]; } long long ans = 2000000000000000005; long long c; for (long long i = 2; i <= k + 1; i++) { c = Min[i - 1]; if (c <= n / 2) ans = min(ans, c + 2 * ((n / 2) - c) - sum[i]); } for (long long i = k + 1; i <= 2 * k; i++) { if (i - k - 1 >= 0) c = Max[i - k - 1]; if (c <= n / 2) ans = min(ans, c * 2 + (n / 2 - c) - sum[i]); } cout << ans << n ; } signed main() { ios_base ::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { solve(); } return 0; }
|
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