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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
bit a_finished;
bit b_finished;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [31:0] o;
wire si = 1'b0;
ExampInst i
(// Outputs
.o (o[31:0]),
// Inputs
.i (1'b0)
/*AUTOINST*/);
Prog p (/*AUTOINST*/
// Inputs
.si (si));
always @ (posedge clk) begin
if (!a_finished) $stop;
if (!b_finished) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module InstModule (
output logic [31:0] so,
input si
);
assign so = {32{si}};
endmodule
program Prog (input si);
initial a_finished = 1'b1;
endprogram
module ExampInst (o,i);
output logic [31:0] o;
input i;
InstModule instName
(// Outputs
.so (o[31:0]),
// Inputs
.si (i)
/*AUTOINST*/);
//bind InstModule Prog instProg
// (.si(si));
// Note is based on context of caller
bind InstModule Prog instProg
(/*AUTOBIND*/
.si (si));
endmodule
// Check bind at top level
bind InstModule Prog2 instProg2
(/*AUTOBIND*/
.si (si));
// Check program declared after bind
program Prog2 (input si);
initial b_finished = 1'b1;
endprogram
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_1_V
`define SKY130_FD_SC_HD__DLRBP_1_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_1_V
|
//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for data[7:0] , crc[15:0]=1+x^2+x^15+x^16;
//-----------------------------------------------------------------------------
module crc16(
input [7:0] data_in,
input crc_en,
output [15:0] crc_out,
input rst,
input clk);
reg [15:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
lfsr_c[0] = lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];
lfsr_c[1] = lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];
lfsr_c[2] = lfsr_q[8] ^ lfsr_q[9] ^ data_in[0] ^ data_in[1];
lfsr_c[3] = lfsr_q[9] ^ lfsr_q[10] ^ data_in[1] ^ data_in[2];
lfsr_c[4] = lfsr_q[10] ^ lfsr_q[11] ^ data_in[2] ^ data_in[3];
lfsr_c[5] = lfsr_q[11] ^ lfsr_q[12] ^ data_in[3] ^ data_in[4];
lfsr_c[6] = lfsr_q[12] ^ lfsr_q[13] ^ data_in[4] ^ data_in[5];
lfsr_c[7] = lfsr_q[13] ^ lfsr_q[14] ^ data_in[5] ^ data_in[6];
lfsr_c[8] = lfsr_q[0] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[6] ^ data_in[7];
lfsr_c[9] = lfsr_q[1] ^ lfsr_q[15] ^ data_in[7];
lfsr_c[10] = lfsr_q[2];
lfsr_c[11] = lfsr_q[3];
lfsr_c[12] = lfsr_q[4];
lfsr_c[13] = lfsr_q[5];
lfsr_c[14] = lfsr_q[6];
lfsr_c[15] = lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];
end // always
always @(posedge clk, posedge rst) begin
if(rst) begin
lfsr_q <= {16{1'b1}};
end
else begin
lfsr_q <= crc_en ? lfsr_c : lfsr_q;
end
end // always
endmodule // crc16
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a; for (int i = 0; i < n; i++) { int x; cin >> x; a.push_back(x); } sort(a.begin(), a.end()); int l = 0; int r = n - 1; for (int i = 0; i < n; i++) { if (i % 2) { cout << a[r--] << ; } else { cout << a[l++] << ; } } return 0; }
|
module Decoder#(parameter DATA_BITS = 8, PARITY_BITS = 4)(
DataParity_in_12p, DataParity_valid_12p,reset_b,clk,
Data_out_14p, EDACerr1_14p,EDACerr2_14p);
// declare the local parameters and signals
localparam k = DATA_BITS;
localparam r = PARITY_BITS;
input wire clk, reset_b, DataParity_valid_12p;
input wire [k+r:1] DataParity_in_12p;
output reg EDACerr1_14p;
output reg EDACerr2_14p;
output reg [k:1] Data_out_14p;
//intermediate signals
reg [r-1:1] syndrome; // required for single error correction
reg [k+r:1] data_in,temp_data;
reg [k:1] data_out;
reg dataparity_valid_int;
reg err1, err2; // flags to detect single/ double errors
// sequential elements
always@(posedge clk or negedge reset_b) begin
if(~reset_b) begin
data_in <= 'd0;
dataparity_valid_int <= 'd0;
err1 <= 'd0; err2 <= 'd0;
Data_out_14p <= 'd0;
EDACerr1_14p <= 1'b0;
EDACerr2_14p <= 1'b0;
end
else if(DataParity_valid_12p) begin
data_in <= DataParity_in_12p;
dataparity_valid_int <= DataParity_valid_12p;
if(dataparity_valid_int) begin
Data_out_14p <= data_out;
EDACerr1_14p <= err1;
EDACerr2_14p <= err2;
end
end
end
// combinational logic syndrome generation
integer i,j,a,l;
integer cnt;
reg P;
always @(data_in) begin
if(reset_b) begin // only if reset is de-asserted
// calculate the parity over entire codeword to detect double bit errors
P = ^(data_in);
temp_data = data_in; //temporary data_in storage
for(i=1;i<r;i=i+1) begin
cnt = 1;
a = cnt[i-1] & data_in[1];
for(cnt=2;cnt<(k+r);cnt=cnt+1) begin
a = a ^ (data_in[cnt] & cnt[i-1]);
end
syndrome[i] = a;
end
// check for errors
if(|(syndrome) && P) begin
// which means 1 bit error present
$display("Inside decoder: One bit error was present at %0d bit, and is corrected",syndrome);
temp_data[syndrome] = ~temp_data[syndrome]; // bit corrected
err1 = 1'b1; err2 = 1'b0;
end
else if(|(syndrome) && ~P) begin
// double error present
$display("Inside decoder: Double bit error was present");
err2 = 1'b1; err1 = 1'b0;
end
else if (~(|syndrome) && ~P)begin
// no error present
$display("Inside decoder: No error was found in the data received");
err1 = 1'b0; err2 = 1'b0;
end
// extract data_out from data_in
j = 1; l = 1;
while ( (l<k+r) || (j<=k)) begin
if ( l == ((~l+1)&l)) begin
l = l+1;
end
else begin
data_out[j] = temp_data[l];
j = j+1; l = l+1;
end
end
if(|(err1))
$display("Inside decoder: Data after correction: %h",data_out);
else
$display("Decoder output: Data: %h",data_out);
end
end
endmodule
|
`include "constants.vh"
/*
clear valid when dpen
set valid when wrrfen
*/
`default_nettype none
module rrf(
input wire clk,
input wire reset,
input wire [`RRF_SEL-1:0] rs1_1tag,
input wire [`RRF_SEL-1:0] rs2_1tag,
input wire [`RRF_SEL-1:0] rs1_2tag,
input wire [`RRF_SEL-1:0] rs2_2tag,
input wire [`RRF_SEL-1:0] com1tag,
input wire [`RRF_SEL-1:0] com2tag,
output wire rs1_1valid,
output wire rs2_1valid,
output wire rs1_2valid,
output wire rs2_2valid,
output wire [`DATA_LEN-1:0] rs1_1data,
output wire [`DATA_LEN-1:0] rs2_1data,
output wire [`DATA_LEN-1:0] rs1_2data,
output wire [`DATA_LEN-1:0] rs2_2data,
output wire [`DATA_LEN-1:0] com1data,
output wire [`DATA_LEN-1:0] com2data,
input wire [`RRF_SEL-1:0] wrrfaddr1,
input wire [`RRF_SEL-1:0] wrrfaddr2,
input wire [`RRF_SEL-1:0] wrrfaddr3,
input wire [`RRF_SEL-1:0] wrrfaddr4,
input wire [`RRF_SEL-1:0] wrrfaddr5,
input wire [`DATA_LEN-1:0] wrrfdata1,
input wire [`DATA_LEN-1:0] wrrfdata2,
input wire [`DATA_LEN-1:0] wrrfdata3,
input wire [`DATA_LEN-1:0] wrrfdata4,
input wire [`DATA_LEN-1:0] wrrfdata5,
input wire wrrfen1,
input wire wrrfen2,
input wire wrrfen3,
input wire wrrfen4,
input wire wrrfen5,
input wire [`RRF_SEL-1:0] dpaddr1,
input wire [`RRF_SEL-1:0] dpaddr2,
input wire dpen1,
input wire dpen2
);
reg [`RRF_NUM-1:0] valid;
reg [`DATA_LEN-1:0] datarr [0:`RRF_NUM-1];
assign rs1_1data = datarr[rs1_1tag];
assign rs2_1data = datarr[rs2_1tag];
assign rs1_2data = datarr[rs1_2tag];
assign rs2_2data = datarr[rs2_2tag];
assign com1data = datarr[com1tag];
assign com2data = datarr[com2tag];
assign rs1_1valid = valid[rs1_1tag];
assign rs2_1valid = valid[rs2_1tag];
assign rs1_2valid = valid[rs1_2tag];
assign rs2_2valid = valid[rs2_2tag];
wire [`RRF_NUM-1:0] or_valid =
(~wrrfen1 ? `RRF_NUM'b0 :
(`RRF_NUM'b1 << wrrfaddr1)) |
(~wrrfen2 ? `RRF_NUM'b0 :
(`RRF_NUM'b1 << wrrfaddr2)) |
(~wrrfen3 ? `RRF_NUM'b0 :
(`RRF_NUM'b1 << wrrfaddr3)) |
(~wrrfen4 ? `RRF_NUM'b0 :
(`RRF_NUM'b1 << wrrfaddr4)) |
(~wrrfen5 ? `RRF_NUM'b0 :
(`RRF_NUM'b1 << wrrfaddr5));
wire [`RRF_NUM-1:0] and_valid =
(~dpen1 ? ~(`RRF_NUM'b0) :
~(`RRF_NUM'b1 << dpaddr1)) &
(~dpen2 ? ~(`RRF_NUM'b0) :
~(`RRF_NUM'b1 << dpaddr2));
always @ (posedge clk) begin
if (reset) begin
valid <= 0;
end else begin
valid <= (valid | or_valid) & and_valid;
end
end
always @ (posedge clk) begin
if (~reset) begin
if (wrrfen1)
datarr[wrrfaddr1] <= wrrfdata1;
if (wrrfen2)
datarr[wrrfaddr2] <= wrrfdata2;
if (wrrfen3)
datarr[wrrfaddr3] <= wrrfdata3;
if (wrrfen4)
datarr[wrrfaddr4] <= wrrfdata4;
if (wrrfen5)
datarr[wrrfaddr5] <= wrrfdata5;
end
end
endmodule // rrf
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int b[200100]; int l[200100], r[200100]; int main(){ int T; scanf( %d , &T); int tot = T; int num = 0; while (T--){ num++; int N, K, M; scanf( %d%d%d , &N, &K, &M); for (int i = 1; i <= M; i++) scanf( %d , &b[i]); int ind = 1; int cnt = 0; for (int i = 1; i <= N; i++){ l[i] = 0; if (ind == M+1 || b[ind] != i){ cnt++; } else { ind++; l[i] = cnt; } } if (cnt%(K-1) != 0){ printf( NO n ); continue; } bool work = false; for (int i = 1; i <= N; i++){ if (l[i] >= K/2 && cnt-l[i] >= K/2){ work = true; break; } } if (work) printf( YES n ); else printf( NO n ); } }
|
#include <bits/stdc++.h> using namespace std; int n, m; char arr[55][55]; int dp[55][55][55][55]; int f(int ind, int let, int dig, int sim) { if (ind == n) { if (let && dig && sim) return 0; else return 1e9; } if (dp[ind][let][dig][sim] != -1) return dp[ind][let][dig][sim]; int &ret = dp[ind][let][dig][sim]; ret = 1e9; for (int i = 0; i < m; i++) { if (arr[ind][i] >= a && arr[ind][i] <= z ) ret = min(ret, f(ind + 1, let + 1, dig, sim) + min(i, m - i)); else if (arr[ind][i] >= 0 && arr[ind][i] <= 9 ) ret = min(ret, f(ind + 1, let, dig + 1, sim) + min(i, m - i)); else ret = min(ret, f(ind + 1, let, dig, sim + 1) + min(i, m - i)); } return ret; } int main() { while (scanf( %d %d , &n, &m) == 2) { memset(dp, -1, sizeof dp); for (int i = 0; i < n; i++) scanf( %s , &arr[i]); int ans = f(0, 0, 0, 0); printf( %d n , ans); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
//Date : Tue Mar 8 16:35:05 2016
//Host : lubuntu running 64-bit Ubuntu 15.04
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 15:55:33 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_clk_wiz_1_0 -prefix
// system_clk_wiz_1_0_ system_clk_wiz_1_0_stub.v
// Design : system_clk_wiz_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_clk_wiz_1_0(clk_out1, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */;
output clk_out1;
input clk_in1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long s, x; cin >> s >> x; long long ans = __builtin_popcountll(x); ans = 1LL << ans; if (s == x) ans -= 2; for (int i = 0; i < 60; i++) { if (x & (1LL << i)) s -= 1LL << i; } for (int i = 0; i < 60; i++) { int j = i + 1; if ((s & (1LL << j)) && !(x & (1LL << i))) s -= 1LL << j; } if (s != 0) puts( 0 ); else cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { double h, l; scanf( %lf %lf , &h, &l); printf( %lf n , (l * l - h * h) / (2 * h * 1.0)); return 0; }
|
module testmux();
# (parameter WIDTH = 32)
(
input wire [2:0] /* synopsys enum cur_info */ sel,
input wire [WIDTH-1:0] a,
output reg [WIDTH-1:0] out
);
endmodule
module top_test();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [WIDTH-1:0] boo_out_symbolic; // From testmux_boo of testmux.v
wire [WIDTH-1:0] boo_out_value; // From testmux_boo of testmux.v, ...
wire [WIDTH-1:0] defaultwidth_out_symbolic;// From testmux_defaultwidth of testmux.v
// End of automatics
/*AUTO_LISP(setq verilog-auto-inst-param-value nil)*/
/* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
.a (@_a_symbolic[]),
.out (@_out_symbolic[]),
);
*/
testmux #(.WIDTH( 16 )) testmux_boo
(/*AUTOINST*/
// Outputs
.out (boo_out_symbolic[WIDTH-1:0]), // Templated
// Inputs
.sel (sel[2:0]),
.a (boo_a_symbolic[WIDTH-1:0])); // Templated
testmux testmux_defaultwidth
(/*AUTOINST*/
// Outputs
.out (defaultwidth_out_symbolic[WIDTH-1:0]), // Templated
// Inputs
.sel (sel[2:0]),
.a (defaultwidth_a_symbolic[WIDTH-1:0])); // Templated
//======================================================================
/*AUTO_LISP(setq verilog-auto-inst-param-value t)*/
/* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
.a (@_a_value[]),
.out (@_out_value[]),
);
*/
testmux #(.IGNORE((1)),
.WIDTH( 16 ),
.IGNORE2(2))
testmux_boo
(/*AUTOINST*/
// Outputs
.out (boo_out_value[15:0]), // Templated
// Inputs
.sel (sel[2:0]),
.a (boo_a_value[15:0])); // Templated
//======================================================================
testmux #(.IGNORE((1)),
.WIDTH(WIDTH), // Make sure we don't recurse!
.IGNORE2(2))
testmux_boo
(/*AUTOINST*/
// Outputs
.out (boo_out_value[WIDTH-1:0]), // Templated
// Inputs
.sel (sel[2:0]),
.a (boo_a_value[WIDTH-1:0])); // Templated
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 1e5 + 15; const int maxm = 1e6 + 15; const int mod = 1e9 + 7; struct Edge { int to, next; } edge[maxm]; int head[maxn], dfn[maxn], bccno[maxn], low[maxn]; int ecnt, cnt, bcnt; void add(int u, int v) { edge[ecnt].to = v; edge[ecnt].next = head[u]; head[u] = ecnt++; } void init() { ecnt = 0; memset(dfn, 0, sizeof dfn); memset(head, -1, sizeof head); } stack<int> Stack; void tarjan(int fa, int u) { dfn[u] = low[u] = ++cnt; Stack.push(u); for (int i = head[u]; ~i; i = edge[i].next) { int v = edge[i].to; if (!dfn[v]) { tarjan(u, v); low[u] = min(low[u], low[v]); } else if (v != fa) low[u] = min(low[u], dfn[v]); } if (low[u] == dfn[u]) { int v; bcnt++; do { v = Stack.top(); Stack.pop(); bccno[v] = bcnt; } while (v != u); } } long long quickMod(long long y) { long long res = 1, x = 2; while (y) { if (y & 1) res = res * x % mod; x = x * x % mod; y >>= 1; } return res; } int w[maxn], x[maxn], y[maxn]; namespace hld { int son[maxn], par[maxn], size[maxn], top[maxn]; int tid[maxn], dep[maxn], c[maxn], tot, n; void init(int _n) { n = _n, tot = 0; memset(tid, 0, sizeof tid); memset(c, 0, sizeof c); } void dfs1(int u, int fa, int depth = 0) { par[u] = fa; dep[u] = depth; size[u] = 1; son[u] = 0; int maxx = 0; for (int i = head[u]; ~i; i = edge[i].next) { int v = edge[i].to; if (v == fa) continue; dfs1(v, u, depth + 1); size[u] += size[v]; if (size[v] > maxx) { maxx = size[v]; son[u] = v; } } } int lowbit(int x) { return x & -x; } void Add(int x, int y) { for (; x <= n; x += lowbit(x)) c[x] += y; } void dfs2(int u, int acs) { tid[u] = ++tot, top[u] = acs; if (w[u]) Add(tot, 1); if (!son[u]) return; dfs2(son[u], acs); for (int i = head[u]; ~i; i = edge[i].next) { int v = edge[i].to; if (tid[v]) continue; dfs2(v, v); } } int sum(int x) { int res = 0; for (; x; x -= lowbit(x)) res += c[x]; return res; } int query(int u, int v) { int f1 = top[u], f2 = top[v], res = 0; while (f1 != f2) { if (dep[f1] < dep[f2]) swap(f1, f2), swap(u, v); res += sum(tid[u]) - sum(tid[f1] - 1); u = par[f1], f1 = top[u]; } if (dep[u] > dep[v]) swap(u, v); return res += sum(tid[v]) - sum(tid[u] - 1); } } // namespace hld int main() { int n, m; scanf( %d %d , &n, &m); init(); for (int i = 1; i <= m; i++) { int u, v; scanf( %d %d , &u, &v); add(u, v); add(v, u); x[i] = u, y[i] = v; } for (int i = 1; i <= n; i++) if (!dfn[i]) tarjan(0, i); for (int i = 1; i <= n; i++) w[bccno[i]]++; for (int i = 1; i <= bcnt; i++) w[i] = (w[i] == 1 ? 0 : 1); ecnt = 0; memset(head, -1, sizeof head); for (int i = 1; i <= m; i++) { int u = bccno[x[i]], v = bccno[y[i]]; if (u == v) continue; add(u, v), add(v, u); } int k; scanf( %d , &k); hld::init(n); hld::dfs1(1, 0), hld::dfs2(1, 1); while (k--) { int u, v; scanf( %d %d , &u, &v); long long ans = quickMod(hld::query(bccno[u], bccno[v])); if (ans >= mod) ans -= mod; printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; string to_string(bool b) { return (b ? true : false ); } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } const int mod = 1000000007; void solve() { int n; cin >> n; map<string, int> m; vector<string> v(n); for (int i = 0; i < (n); ++i) cin >> v[i]; for (int i = 0; i < (n); ++i) { for (int j = 1; j <= 8; j++) { for (int k = 0; k + j <= 9; k++) { m[v[i].substr(k, j)]++; } } } vector<string> ans(n); for (int i = 0; i < (n); ++i) { map<string, int> mm; for (int j = 1; j <= 8; j++) { for (int k = 0; k + j <= 9; k++) { mm[v[i].substr(k, j)]++; } } string anss = v[i]; int len = 9; for (auto it = mm.begin(); it != mm.end(); it++) { if (m[it->first] == it->second) { if ((int)(it->first).size() < len) { len = (int)(it->first).size(); anss = it->first; } } } ans[i] = anss; } for (int i = 0; i < (n); ++i) cout << ans[i] << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tt = 1; while (tt--) solve(); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/08 21:20:19
// Design Name:
// Module Name: timing_signal_generator_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timing_signal_generator_tb(
);
parameter CYCLE = 5;
parameter LEN = 4;
parameter TIME = 500;
reg clr_n, on, off;
reg [3:0] power;
wire [(LEN-1):0] T;
timing_signal_generator #(.CYCLE(CYCLE), .LEN(LEN)) DUT (
.clr_n(clr_n),
.on(on),
.off(off),
.power(power),
.T(T));
initial begin
#TIME $stop;
end
initial begin
clr_n = 1;
on = 0; off = 1;
power = 4'b0000;
#10 clr_n = 0;
#10 clr_n = 1;
#10 power = 4'b0001;
end
endmodule
|
// Test bench for the restricted 27x27 bit multiplier. (The
// restriction is that if the most significant bit of opa is set to
// one the three least significant bits of opa must be zero.) This
// enables us to design a 27x27 bit multiplier using only two DSP48E1
// multipliers and one LUT based adder outside the DSP blocks in the
// Xilinx 7-series of FPGAs.
`timescale 1ns / 1ps
module tb_mult_27x27;
parameter LATENCY = 4;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [53:0] res; // From dut of mult_27x27.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg clk; // To dut of mult_27x27.v
reg [26:0] opa; // To dut of mult_27x27.v
reg [26:0] opb; // To dut of mult_27x27.v
// End of automatics
mult_27x27 #(.LATENCY(LATENCY))
dut(/*AUTOINST*/
// Outputs
.res (res[53:0]),
// Inputs
.clk (clk),
.opa (opa[26:0]),
.opb (opb[26:0]));
reg running = 1;
initial while(running) begin
clk = 0;
#10;
clk = 1;
#10;
end
reg [53:0] expected_res;
reg res_is_valid = 0;
always @(posedge clk) begin
expected_res <= repeat(LATENCY-1) @(posedge clk) $unsigned(opa)*$unsigned(opb);
end
integer state = 10; // FIXME: Remove the unused state variable
initial begin
opa = 0;
opb = 0;
expected_res = 0;
repeat(100) @(posedge clk);
repeat(10000) @(posedge clk) begin : FOO
reg [26:0] restricted_opa;
//
if(1 || !state) begin
restricted_opa = {$random,$random} ;
if(restricted_opa[26]) begin
restricted_opa[2:0] = 3'b000;
end
opa <= restricted_opa;
opb <= {$random,$random};
opb <= $random;
state = 10;
end else begin
state = state - 1;
end
if(expected_res !== res) begin
$display("expected_res !== res!");
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$stop;
// Note: We don't check the last few values, but it
// doesn't really matter as they are randomly generated
// anyway.
end
end
running = 0;
#10;
$display("");
$display("*** Multiplier test PASSED ***");
$display("");
end
initial begin
while(1) begin
$display(" opa opb res expected_res res^expected");
repeat(20) begin
@(posedge clk);
$display("%x %x %x %x %x ",opa,opb,res, expected_res, res^expected_res);
end
end
end
endmodule
|
module ledDriver /*#( parameter NUM_LEDS = 60 )*/(input clk, input reset, output reg led, input data, input lastBit, input start, output finish, output read);
//Generate the pulse width modulated output signal
//Running at 20MHz, a High pulse of 8 cycles and 17 low cycles produces a 0,
//16 cycles of high and 9 low a 1.
//Are we doing stuff right now?
reg running = 0;
//Are we waiting for RES?
reg resCounting = 0;
/*
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter LOG_BITS = clog2(NUM_LEDS*24);
reg[LOG_BITS-1:0] bitCnt = 0; */
reg read = 0;
//Count repeatedly counts from 0 to 24.
reg[4:0] count = 0;
always @(posedge clk or posedge reset) begin
if (reset || ~running) begin
count<=0;
end else begin
if (count!=24) begin
count <= count + 1;
end else begin
count <=0;
end
end
end
/*
wire lastBit;
assign lastBit = (bitCnt==(NUM_LEDS*24-1));*/
reg firstbit = 0;
always @(posedge clk or posedge reset) begin
if (reset) begin
running <= 0;
firstbit <= 1;
read <= 0;
end else begin
if (~running & start) begin
running <= 1;
//data <= inData;
//bitCnt<= 0;
firstbit <= 1;
end else if (running) begin
firstbit<=0;
if (lastBit && count==24) begin
running <= 0;
resCounting <= 1;
read <= 0;
end else if (count==0 && ~firstbit) begin
//data <= data << 1;
read <= 1;
//bitCnt <= bitCnt +1;
end else read <= 0;
end else if (resCounting && finish) begin
resCounting <= 0;
end
end
end
/*//The bit being currently output
wire current;
//Is always the highest bit in the shift reg
assign current = data[(NUM_LEDS*24)-1]; */
//Pulse out the data
always @(posedge clk or posedge reset) begin
if (reset || ~running) begin
led <= 0;
end else begin
if (count==0) begin
led <= 1;
end else if ( (count==8 && ~data) || (count==16 && data)) begin
led<=0;
end
end
end
//Counter for res contition
reg [10:0] resCounter=0;
always @(posedge clk or posedge reset) begin
if (reset || ~resCounting) begin
resCounter=0;
end else begin
resCounter <= resCounter+1;
end
end
assign finish = resCounter==11'h7FF;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double Pi = 3.14159265358979323; int main() { ios_base::sync_with_stdio(0); cin.tie(); double x0, y0, v, T, n, x, y, r; vector<tuple<double, double> > c; cin >> x0 >> y0 >> v >> T; T = v * T * 1.0; cin >> n; while (n--) { cin >> x >> y >> r; double angulo, d, adiff; d = sqrt((x - x0) * (x - x0) + (y - y0) * (y - y0)); if (d * d <= r * r || (x == x0 && y == y0)) { cout << 1.000 n ; return 0; } if (r == 0) continue; if (d * d >= ((r + T) * (r + T))) continue; angulo = atan2(y - y0, x - x0); if (angulo < 0) { angulo += 2 * Pi; } if (sqrt(d * d - r * r) <= T) { adiff = asin(r / d); } else { adiff = acos((-r * r + T * T + d * d) / (2 * T * d)); } double x1 = angulo - adiff; if (x1 < 0) x1 = 2 * Pi + x1; c.push_back(make_tuple(x1, 1)); x1 = angulo + adiff; if (x1 > 2 * Pi) x1 -= 2 * Pi; c.push_back(make_tuple(x1, -1)); } sort(c.begin(), c.end()); double s = 0.0; int in = 0, fin = -1; vector<int> sweep(c.size(), 0); while (in != fin && c.size() != 0) { double angulo, con; if (fin == -1 && in == 0) fin = 0; tie(angulo, con) = c[in]; if (con == -1 && s == 0) fin = in; if (con == -1 && s > 0) s--; else if (con == 1) s++; sweep[in] += s; in++; in %= c.size(); } in = -1; for (int i = 0; i < c.size(); i++) { if (sweep[i] == 0) { in = i; in++; in %= c.size(); break; } } if (in == -1 && c.size() != 0) { cout << 1.00 ; return 0; } fin = -1; double sum = 0.0, an = -1; while (c.size() != 0 && in != fin) { if (fin == -1) fin = in; if (sweep[in] == 1 && an == -1) an = get<0>(c[in]); if (sweep[in] == 0) { if (get<0>(c[in]) < an) sum += get<0>(c[in]) - an + 2 * Pi; else sum += get<0>(c[in]) - an; an = -1; } in++; in %= c.size(); } cout << setprecision(20) << (sum / (2 * Pi)) << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_1_V
`define SKY130_FD_SC_HDLL__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_1_V
|
// Copyright (c) 2016 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Bug report test (could not elaborate a function used to specify a range).
module vhdl_elab_range_test;
integer left, right;
vhdl_elab_range dut(left, right);
initial begin
#1;
if(left !== 2) begin
$display("FAILED 1");
$finish();
end
if(right !== 0) begin
$display("FAILED 2");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int times[50] = {0}; int graph[50][50] = {0}; void findMissing(int n, int &temp1, int &temp2) { bool condition = false; for (int i = 0; i < n; i++) { if (times[i] != (n - 1)) { if (condition) temp2 = i; else { temp1 = i; condition = true; } } } } void swap(int &n1, int &n2) { n1 += n2; n2 = n1 - n2; n1 -= n2; } void findOrder(int n, int &temp1, int &temp2) { for (int i = 0; i < n; i++) { bool condition = false; if (i == temp1 || i == temp2) continue; else { if (graph[temp1][i] == 1 && graph[i][temp2] == 1) return; else if (graph[i][temp1] == 1 && graph[temp2][i] == 1) { swap(temp1, temp2); return; } } } } int main() { int n, temp1, temp2; cin >> n; for (int i = 0; i < (((n * (n - 1)) / 2) - 1); i++) { cin >> temp1 >> temp2; times[temp1 - 1]++; times[temp2 - 1]++; graph[temp1 - 1][temp2 - 1] = 1; } findMissing(n, temp1, temp2); findOrder(n, temp1, temp2); cout << temp1 + 1 << << temp2 + 1 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21AI_2_V
`define SKY130_FD_SC_HD__O21AI_2_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ai_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int NMAX = 1e5 + 4; int a[NMAX]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int mn = 1e9 + 4; for (int i = 0; i < n; ++i) { cin >> a[i]; mn = min(mn, a[i]); } vector<int> res; for (int i = 0; i < n; ++i) { if (a[i] == mn) { res.push_back(i); } } int ans = 1e6 + 4; for (int i = 0; i < res.size() - 1; ++i) { ans = min(ans, (res[i + 1] - res[i])); } cout << ans; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:46:39 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_quad_spi_flash_0/system_axi_quad_spi_flash_0_stub.v
// Design : system_axi_quad_spi_flash_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_quad_spi,Vivado 2016.4" *)
module system_axi_quad_spi_flash_0(ext_spi_clk, s_axi_aclk, s_axi_aresetn,
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, io0_i, io0_o, io0_t, io1_i,
io1_o, io1_t, io2_i, io2_o, io2_t, io3_i, io3_o, io3_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t, ip2intc_irpt)
/* synthesis syn_black_box black_box_pad_pin="ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,io2_i,io2_o,io2_t,io3_i,io3_o,io3_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */;
input ext_spi_clk;
input s_axi_aclk;
input s_axi_aresetn;
input [6:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [6:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input io0_i;
output io0_o;
output io0_t;
input io1_i;
output io1_o;
output io1_t;
input io2_i;
output io2_o;
output io2_t;
input io3_i;
output io3_o;
output io3_t;
input sck_i;
output sck_o;
output sck_t;
input [0:0]ss_i;
output [0:0]ss_o;
output ss_t;
output ip2intc_irpt;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PR_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PR_SYMBOL_V
/**
* udp_dff$PR: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PR_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND3_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); mt19937 rnf(2106); const int N = 100005; int n, m, k; vector<int> a[N]; vector<int> v[2]; void dfs0(int x, int p, int z) { v[z].push_back(x); for (int i = 0; i < a[x].size(); ++i) { int h = a[x][i]; if (h == p) continue; dfs0(h, x, (z ^ 1)); } } bool c[N]; int dfs(int x, int p) { c[x] = true; for (int i = 0; i < a[x].size(); ++i) { int h = a[x][i]; if (h == p) continue; if (!c[h]) { int u = dfs(h, x); if (u) return u; } else return x; } return 0; } int p[N]; int d[N]; int f[N]; vector<int> bfs(int s) { memset(c, false, sizeof c); queue<int> q; q.push(s); c[s] = true; int minu = N; int xx, yy; while (!q.empty()) { int x = q.front(); q.pop(); for (int i = 0; i < a[x].size(); ++i) { int h = a[x][i]; if (!c[h]) { c[h] = true; p[h] = x; d[h] = d[x] + 1; if (x != s) f[h] = f[x]; else f[h] = h; q.push(h); } else { if (x != s && h != s) { if (f[h] != f[x]) { if (d[x] + d[h] < minu) { minu = d[x] + d[h]; xx = x; yy = h; } } } } } } vector<int> v; for (int i = xx; i != s; i = p[i]) v.push_back(i); vector<int> v1; for (int i = yy; i != s; i = p[i]) v1.push_back(i); reverse((v1).begin(), (v1).end()); v.push_back(s); for (int i = 0; i < v1.size(); ++i) v.push_back(v1[i]); return v; } void solv() { scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < m; ++i) { int x, y; scanf( %d%d , &x, &y); a[x].push_back(y); a[y].push_back(x); } if (m == n - 1) { dfs0(1, 1, 0); if (v[1].size() > v[0].size()) swap(v[0], v[1]); printf( 1 n ); for (int i = 0; i < k / 2 + k % 2; ++i) printf( %d , v[0][i]); printf( n ); return; } int s = dfs(1, -1); vector<int> v = bfs(s); if (v.size() <= k) { printf( 2 n ); printf( %d n , v.size()); for (int i = 0; i < v.size(); ++i) printf( %d , v[i]); printf( n ); return; } vector<int> vv; for (int i = 0; i < v.size(); i += 2) vv.push_back(v[i]); v = vv; printf( 1 n ); for (int i = 0; i < k / 2 + k % 2; ++i) printf( %d , v[i]); printf( n ); } int main() { solv(); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct segtree { int n; vector<long long> tree; void init(int s) { n = s; tree.resize(4 * s); } long long qry(int i, int j) { return qry(i, j, 1, 0, n - 1); } void upd(int i, long long v) { upd(i, v, 1, 0, n - 1); } long long qry(int i, int j, int x, int nowi, int nowj) { if (i <= nowi && nowj <= j) return tree[x]; if (nowi > j || nowj < i) return 0; int m = (nowi + nowj) / 2; return qry(i, j, 2 * x, nowi, m) + qry(i, j, 2 * x + 1, m + 1, nowj); } void upd(int i, long long v, int x, int nowi, int nowj) { if (nowi == i && nowj == i) { tree[x] = v; return; } if (nowi > i || nowj < i) return; int m = (nowi + nowj) / 2; upd(i, v, 2 * x, nowi, m); upd(i, v, 2 * x + 1, m + 1, nowj); tree[x] = tree[2 * x] + tree[2 * x + 1]; } }; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, ans = 0; cin >> n; n *= 2; vector<int> a(n), p(n + 1, -1), v(n + 1); for (auto &i : a) cin >> i; for (int i = 0; i < n; ++i) { if (p[a[i]] == -1) p[a[i]] = i; v[i] = p[a[i]]; } segtree s; s.init(n); for (int i = n - 1; ~i; --i) { s.upd(v[i], 1); if (v[i]) ans += s.qry(0, v[i] - 1); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; long long n; bool use[100000 + 10], b[100000 + 10]; int a[100000 + 10], Now; int Ans; int L[100000 + 10], R[100000 + 10], CNT = 0; int main() { int Cnt = 0; scanf( %I64d , &n); for (long long i = 3; i <= n; i += 2) { if (b[i]) continue; Now = 1; a[1] = i; for (long long j = 2 * i; j <= n; j += i) { b[j] = false; if (use[j]) continue; a[++Now] = j; } if (Now == 1) continue; if (Now % 2 == 0) { for (int i = 1; i + 1 <= Now; i += 2) { Ans++; L[Ans] = a[i]; use[a[i]] = true; R[Ans] = a[i + 1]; use[a[i + 1]] = true; } } else { Ans++; L[Ans] = a[1]; use[a[1]] = true; R[Ans] = a[3]; use[a[3]] = true; for (int i = 4; i + 1 <= Now; i += 2) { Ans++; L[Ans] = a[i]; use[a[i]] = true; R[Ans] = a[i + 1]; use[a[i + 1]] = true; } } } Now = 0; for (long long j = 2; j <= n; j += 2) { b[j] = false; if (use[j]) continue; a[++Now] = j; } if (Now % 2 == 0) { for (int i = 1; i + 1 <= Now; i += 2) { Ans++; L[Ans] = a[i]; use[a[i]] = true; R[Ans] = a[i + 1]; use[a[i + 1]] = true; } } else { if (Now != 1) { Ans++; L[Ans] = a[1]; use[a[1]] = true; R[Ans] = a[3]; use[a[3]] = true; for (int i = 4; i + 1 <= Now; i += 2) { Ans++; L[Ans] = a[i]; use[a[i]] = true; R[Ans] = a[i + 1]; use[a[i + 1]] = true; } } } printf( %d n , Ans); for (int i = 1; i <= Ans; i++) printf( %d %d n , L[i], R[i]); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:52:55 10/29/2013
// Design Name: Clock_Divider
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/proyecto-final/clock48_test.v
// Project Name: proyecto-final
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Clock_Divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clock48_test;
// Inputs
reg clock;
reg reset;
// Outputs
wire clock_out;
// Instantiate the Unit Under Test (UUT)
Clock_Divider uut (
.clock(clock),
.reset(reset),
.clock_out(clock_out)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:20:39 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Decrementer_0_0/RAT_Decrementer_0_0_stub.v
// Design : RAT_Decrementer_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "Decrementer,Vivado 2016.4" *)
module RAT_Decrementer_0_0(I, O)
/* synthesis syn_black_box black_box_pad_pin="I[7:0],O[7:0]" */;
input [7:0]I;
output [7:0]O;
endmodule
|
`timescale 1ns / 1ps
module uart_rx
#(
parameter DBIT = 8, // Number of data bits to receive
SB_TICK = 16 // Number of ticks for the stop bit. 16 ticks=1 stop bit, 24=1.5 and 32=2.
)
(
input wire clk,
input wire reset,
input wire data_in,
input wire s_tick,
output reg rx_done_tick,
output wire [7:0] data_out
);
// state declaration for the FSMD
localparam [1:0]
idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
// signal declaration
reg [1:0] state_reg, state_next;
reg [3:0] cnt_15_reg, cnt_15_next;
reg [2:0] cnt_8_reg, cnt_8_next;
reg [7:0] shift_out_reg, shift_out_next;
// body
// FSMD state & data registers
always@(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
cnt_15_reg <= 0;
cnt_8_reg <= 0;
shift_out_reg <= 0;
end
else
begin
state_reg <= state_next;
cnt_15_reg <= cnt_15_next;
cnt_8_reg <= cnt_8_next;
shift_out_reg <= shift_out_next;
end
// FSMD next-state logic
always@*
begin
state_next = state_reg ;
cnt_15_next = cnt_15_reg;
cnt_8_next = cnt_8_reg;
shift_out_next = shift_out_reg;
rx_done_tick = 1'b0;
case (state_reg)
idle:
if(~data_in)
begin
state_next = start;
cnt_15_next = 0;
end
start:
if (s_tick)
if(cnt_15_reg==7)
begin
state_next=data;
cnt_15_next=0;
cnt_8_next=0;
end
else
cnt_15_next = cnt_15_reg+1'b1;
data:
if(s_tick)
if(cnt_15_reg==15)
begin
cnt_15_next=0;
shift_out_next = {data_in, shift_out_reg[7:1]};
//shift_out_next<={shift_out_reg[6:0],data_in}; // shift the bits in reverse order
if(cnt_8_reg==(DBIT-1))
state_next=stop;
else
cnt_8_next=cnt_8_reg+1'b1;
end
else
cnt_15_next=cnt_15_reg+1'b1;
stop:
if(s_tick)
if(cnt_15_reg==(SB_TICK-1))
begin
state_next=idle;
rx_done_tick=1'b1;
end
else
cnt_15_next = cnt_15_reg+1'b1;
endcase
end
//output
assign data_out = shift_out_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; double eps(1e-10); int sign(const double& x) { return (x > eps) - (x + eps < 0); } bool equal(const double& x, const double& y) { return x + eps > y && y + eps > x; } struct Point { double x, y, z; Point() {} Point(const double& x, const double& y, const double& z) : x(x), y(y), z(z) {} void print() const { printf( %f%f%f n , x, y, z); } void scan() { scanf( %lf%lf%lf , &x, &y, &z); } double sqrlen() const { return x * x + y * y + z * z; } double len() const { return sqrt(max(0., sqrlen())); } bool operator<(const Point& b) const { if (!equal(x, b.x)) { return x < b.x; } if (!equal(y, b.y)) { return y < b.y; } if (!equal(z, b.z)) { return z < b.z; } return false; } double dirlen() const { return len() * ((*this) < Point(0, 0, 0) ? -1 : 1); } Point operator+(const Point& b) const { return Point(x + b.x, y + b.y, z + b.z); } Point operator-(const Point& b) const { return Point(x - b.x, y - b.y, z - b.z); } double operator%(const Point& b) const { return x * b.x + y * b.y + z * b.z; } Point operator*(const Point& b) const { return Point(y * b.z - z * b.y, z * b.x - x * b.z, x * b.y - y * b.x); } Point zoom(const double& l) const { double lambda(l / len()); return Point(lambda * x, lambda * y, lambda * z); } }; inline Point operator*(const double& x, const Point& a) { return Point(x * a.x, x * a.y, x * a.z); } struct Plane { Point o, norm; }; struct Line { Point s, d; Line(const Point& s, const Point& d) : s(s), d(d) {} }; Point intersection(const Line& a, const Line& b) { double lambda(((b.s - a.s) * b.d).dirlen() / (a.d * b.d).dirlen()); return a.s + lambda * a.d; } vector<pair<Point, pair<int, int>>> evts; void calc(const vector<Point>& points, const vector<Point>& q) { Plane p1, p2; p1.o = points[0]; p2.o = q[0]; p1.norm = (points[0] - points[1]) * (points[2] - points[0]); p2.norm = (q[0] - q[1]) * (q[2] - q[0]); p1.norm = p1.norm.zoom(1); p2.norm = p2.norm.zoom(1); if (sign((p1.norm * p2.norm).len()) == 0) { return; } Point d(p1.norm * p2.norm); Point g(d * p1.norm); d = d.zoom(1); g = g.zoom(1); Line l(p1.o + (p2.o - p1.o) % p2.norm / (g % p2.norm) * g, d); static vector<pair<Point, pair<int, int>>> vec; vec.clear(); for (int i(0); i < (int)points.size(); i++) { Point a(points[i]), b(points[(i + 1) % (int)points.size()]); int da(sign((a - l.s) % g)), db(sign((b - l.s) % g)); if (da == db) { } else { Point crs(intersection(Line(a, b - a), l)); if (da != 0 && db != 0) { evts.push_back(make_pair(crs, make_pair(da, 0))); } else { vec.push_back(make_pair(crs, make_pair(da, db))); } } } for (int i(0); i < (int)vec.size(); i++) { if (vec[i].second.second == 0) { if (vec[i].second.first != vec[(i + 1) % (int)vec.size()].second.second) { evts.push_back( make_pair(vec[i].first, make_pair(vec[i].second.first, 0))); } } } } vector<Point> vec[2]; int main() { for (int d(0); d < 2; d++) { int n; scanf( %d , &n); for (int i(0); i < n; i++) { Point p; p.scan(); vec[d].push_back(p); } } calc(vec[0], vec[1]); for (auto& evt : evts) { evt.second.second = 1; } calc(vec[1], vec[0]); sort(evts.begin(), evts.end()); int ans(0); int cur(0); for (auto evt : evts) { if (evt.second.second == 1) { cur += evt.second.first; } else { if (cur != 0) { ans += evt.second.first; } } } printf( %s n , ans != 0 ? YES : NO ); }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 05:22:49 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_stub.v
// Design : dds_compiler_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, l; int pre[200010], other[200010], last[100010]; int flag[100010]; void connect(int x, int y) { pre[++l] = last[x]; last[x] = l; other[l] = y; } int dfs(int x, int fa) { flag[x] = 1; int cur(0); for (int p = last[x]; p; p = pre[p]) { if (other[p] == fa) continue; if (flag[other[p]] == 2) continue; int edge; if (!flag[other[p]]) edge = dfs(other[p], x); else edge = 0; if (edge) printf( %d %d %d n , x, other[p], edge); else if (cur) printf( %d %d %d n , cur, x, other[p]), cur = 0; else cur = other[p]; } flag[x] = 2; return cur; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); connect(x, y); connect(y, x); } if (m & 1) printf( No solution n n ); else dfs(1, -1); return 0; }
|
`include "common.vh"
`timescale 1ns/10ps
module Reg(input clk, upZ, output signed[31:0] valZ, valX, valY,
input[3:0] idxZ, idxX, idxY, input signed[31:0] nextZ, nextP);
reg[31:0] store[0:14];
integer k;
initial for (k = 0; k < 15; k = k + 1) store[k] = 0;
assign valX = &idxX ? nextP : store[idxX];
assign valY = &idxY ? nextP : store[idxY];
assign valZ = &idxZ ? nextP : store[idxZ];
always @(posedge clk) if (&{upZ,|idxZ,~&idxZ}) store[idxZ] <= nextZ;
endmodule
module Decode(input[31:0] insn, output[3:0] idxZ, idxX, output reg[3:0] idxY,
output reg signed[31:0] valI, output reg[3:0] op,
output[1:0] kind, output storing, loading, deref_rhs, branching);
wire [19:0] tI;
wire [1:0] dd;
assign {kind, dd, idxZ, idxX, tI} = insn;
always @* case (kind)
default: {idxY,op,valI[11:0],valI[31:12]} = { tI,{20{tI[11]}}};
2'b11: {idxY,op,valI[19:0],valI[31:20]} = {8'h0,tI,{12{tI[19]}}};
endcase
assign storing = ^dd;
assign loading = ⅆ
assign deref_rhs = dd[0];
assign branching = &idxZ & ~storing;
endmodule
module Shuf(input[1:0] kind, input signed[31:0] valX, valY, valI,
output reg signed[31:0] valA, valB, valC);
always @* case (kind)
2'b00: {valA,valB,valC} = {valX ,valY,valI};
2'b01: {valA,valB,valC} = {valX ,valI,valY};
2'b10: {valA,valB,valC} = {valI ,valX,valY};
2'b11: {valA,valB,valC} = {32'h0,valX,valI};
endcase
endmodule
module Exec(input clk, en, output reg done, output reg[31:0] valZ,
input[3:0] op, input signed[31:0] valA, valB, valC);
reg signed[31:0] rY, rZ, rA, rB, rC;
reg[3:0] rop;
reg add, act, staged;
always @(posedge clk) begin
{ rop , valZ , rA , rB , rC , done , add , act , staged } <=
{ op , rZ , valA , valB , valC , add , act , staged , en } ;
if (staged) case (rop)
4'h0: rY <= (rA | rB) ; 4'h8: rY <= (rA |~ rB );
4'h1: rY <= (rA & rB) ; 4'h9: rY <= (rA &~ rB );
4'h2: rY <= (rA ^ rB) ; 4'ha: rY <= {rA[19:0],rB[11:0]};
4'h3: rY <= (rA >>> rB) ; 4'hb: rY <= (rA >> rB );
4'h4: rY <= (rA + rB) ; 4'hc: rY <= (rA - rB );
4'h5: rY <= (rA * rB) ; 4'hd: rY <= (rA << rB );
4'h6: rY <= {32{rA == rB}}; 4'he: rY <= {32{rA [rB] }};
4'h7: rY <= {32{rA < rB}}; 4'hf: rY <= {32{rA >= rB }};
endcase
if (act) rZ <= rY + rC;
end
endmodule
module Core(
input clk, reset,
output reg[31:0] adr_o, // address
input [31:0] dat_i, // data in
output [31:0] dat_o, // data out
output wen_o, // write enable
output [ 3:0] sel_o, // select
output stb_o, // strobe
input ack_i, // acknowledge
input err_i, // error
input rty_i, // retry
output cyc_o, // cycle
inout halt
);
localparam[3:0] s0=0, s1=1, s2=2, s3=3, s4=4, s5=5, s6=6, s7=7;
wire deref_rhs, branching, storing, loading, edone;
wire[3:0] idxX, idxY, idxZ, op;
wire signed[31:0] valX, valY, valZ, valI, valA, valB, valC, rhs;
wire[1:0] kind;
reg[31:0] insn, _data;
reg signed[31:0] _irhs, nextP;
reg[3:0] state;
wire signed[31:0] nextI = branching ? nextZ : nextP;
wire signed[31:0] nextZ = deref_rhs ? _data : _irhs;
wire [31:0] _adrD = deref_rhs ? _irhs : valZ;
wire memory = loading | storing;
wire i_strb = state == s5;
wire d_strb = state == s3 && memory;
wire upZ = state == s4 && !storing;
assign sel_o = 4'hf;
assign stb_o = d_strb | i_strb;
assign wen_o = d_strb & storing;
assign dat_o = deref_rhs ? valZ : _irhs;
assign cyc_o = stb_o;
assign halt = err_i | rty_i;
always @(posedge clk)
if (reset) begin
state <= s5;
adr_o <= `RESETVECTOR;
end else case (state)
s0: begin state <= !halt ? s1 : s0; end
s1: begin state <= edone ? s2 : s1; _irhs <= rhs; end
s2: begin state <= memory ? s3 : s4; adr_o <= _adrD; end
s3: begin state <= ack_i ? s4 : s3; _data <= dat_i; end
s4: begin state <= s5 ; adr_o <= nextI; end
s5: begin state <= ack_i ? s6 : s5; nextP <= adr_o + 1; end
s6: begin state <= s0 ; insn <= dat_i; end
s7: begin state <= s5; end
endcase
Decode decode(.insn, .op, .idxZ, .idxX, .idxY, .valI, .deref_rhs,
.kind, .branching, .loading, .storing);
Shuf shuf(.kind, .valX, .valA, .valY, .valB, .valI, .valC);
Exec exec(.clk, .en ( state == s0 ), .done ( edone ),
.op, .valA, .valB, .valC, .valZ ( rhs ));
Reg regs(.clk, .nextP, .idxX, .idxY, .idxZ,
.upZ, .nextZ, .valX, .valY, .valZ);
endmodule
|
// $Id: c_interleave.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// interleave a given number of blocks of bits
// (a0 a1 a2 b0 b1 b2 c0 c1 c2) -> (a0 b0 c0 a1 b1 c1 a2 b2 c2)
//==============================================================================
module c_interleave
(data_in, data_out);
// input data width
parameter width = 8;
// number of blocks in input data
parameter num_blocks = 2;
// width of each block
localparam step = width / num_blocks;
// vector of input data
input [0:width-1] data_in;
// vector of output data
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < step; i = i + 1)
begin:blocks
genvar j;
for(j = 0; j < num_blocks; j = j + 1)
begin:bits
assign data_out[i*num_blocks+j] = data_in[i+j*step];
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; inline long long getint() { long long _x = 0, _tmp = 1; char _tc = getchar(); while ((_tc < 0 || _tc > 9 ) && _tc != - ) _tc = getchar(); if (_tc == - ) _tc = getchar(), _tmp = -1; while (_tc >= 0 && _tc <= 9 ) _x *= 10, _x += (_tc - 0 ), _tc = getchar(); return _x * _tmp; } inline long long add(long long _x, long long _y, long long _mod = 1000000007LL) { _x += _y; return _x >= _mod ? _x - _mod : _x; } inline long long sub(long long _x, long long _y, long long _mod = 1000000007LL) { _x -= _y; return _x < 0 ? _x + _mod : _x; } inline long long mul(long long _x, long long _y, long long _mod = 1000000007LL) { _x *= _y; return _x >= _mod ? _x % _mod : _x; } long long mypow(long long _a, long long _x, long long _mod) { if (_x == 0) return 1LL; long long _ret = mypow(mul(_a, _a, _mod), _x >> 1, _mod); if (_x & 1) _ret = mul(_ret, _a, _mod); return _ret; } void sleep(double sec = 1021) { clock_t s = clock(); while (clock() - s < CLOCKS_PER_SEC * sec) ; } int __ = 1, _cs; int dp[702][10]; int fac[702 + 702], inv[702 + 702]; inline int C(int a, int b) { return mul(fac[a], mul(inv[b], inv[a - b])); } int pp[702], ten[702 + 702]; int sv[702][10][702]; int sv2[702][10][702]; int iten[702 + 702]; int dpw[10][702]; void build() { ten[0] = fac[0] = inv[0] = 1; iten[0] = 1; int inv10 = mypow(10, 1000000007LL - 2, 1000000007LL); for (int i = 1; i < 702 + 702; i++) { fac[i] = mul(fac[i - 1], i); inv[i] = mypow(fac[i], 1000000007LL - 2, 1000000007LL); ten[i] = mul(ten[i - 1], 10); iten[i] = mul(iten[i - 1], inv10); } int inv9 = mypow(9, 1000000007LL - 2, 1000000007LL); for (int i = 1; i < 702; i++) pp[i] = mul(sub(ten[i], 1), inv9); for (int i = 1; i < 10; i++) { dpw[i][0] = 1; for (int j = 1; j < 702; j++) dpw[i][j] = mul(dpw[i][j - 1], i); } for (int k = 0; k < 702; k++) for (int dgt = 1; dgt < 10; dgt++) for (int i = 0; i <= k; i++) { int tmp = 1; tmp = mul(tmp, C(k, i)); tmp = mul(tmp, dpw[dgt][i]); if (9 - dgt > 0) tmp = mul(tmp, dpw[9 - dgt][k - i]); tmp = mul(tmp, ten[k - i]); sv[k][dgt][i] = tmp; if (i) sv[k][dgt][i] = add(sv[k][dgt][i], sv[k][dgt][i - 1]); } for (int k = 1; k < 702; k++) for (int dgt = 1; dgt < 10; dgt++) { if (dgt == 9) { for (int i = 0; i < k; i++) { int j = k - i; if (dgt == 9 and i + j < k) continue; int way = C(k, j); way = mul(way, C(k - j, i)); way = mul(way, dpw[dgt][i]); if (9 - dgt > 0) way = mul(way, dpw[9 - dgt][k - i - j]); way = mul(way, ten[k - i - j]); way = mul(way, pp[j]); dp[k][dgt] = add(dp[k][dgt], mul(way, dgt)); } continue; } for (int j = 1; j <= k; j++) { int way = C(k, j); way = mul(way, sv[k - j][dgt][k - j]); way = mul(way, pp[j]); dp[k][dgt] = add(dp[k][dgt], mul(way, dgt)); } } } char c[702]; int ans, len; void init() { scanf( %s , c); len = strlen(c); } int cnt[10]; void go(int bt, bool bnd) { if (bt == len or not bnd) { int res = len - bt; if (res) { int ps = 0; for (int i = 9; i; i--) { ans = add(ans, mul(dp[res][i], ten[ps])); ps += cnt[i]; } } int ps = 0; for (int i = 0; i < 10; i++) { if (i) { for (int j = 0; j <= res; j++) { int way = sv2[res][i][j]; way = mul(way, ten[len - (ps + j) - cnt[i]]); way = mul(way, pp[cnt[i]]); ans = add(ans, mul(i, way)); } } ps += cnt[i]; } return; } for (int i = 0; i <= c[bt] - 0 ; i++) { if (bt == 0 and i == 0) continue; cnt[i]++; go(bt + 1, i == c[bt] - 0 ); cnt[i]--; } } void solve() { for (int res = 0; res < 702; res++) for (int i = 1; i < 10; i++) { for (int j = 0; j <= res; j++) { int way = C(res, j); way = mul(way, dpw[i][j]); way = mul(way, dpw[10 - i][res - j]); sv2[res][i][j] = way; } } if (len > 1) { for (int i = 1; i < 10; i++) ans = add(ans, dp[len - 1][i]); } go(0, true); cout << ans << endl; } int main() { build(); while (__--) { init(); solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 100; const int MAXM = 15; int N, Q, M; int log2(int v) { int r = 1; while (v >>= 1) r++; return r; } int a[MAXN]; int t[2][MAXN]; struct ST { int v[3 * MAXN][2][MAXM]; int l[3 * MAXN], r[3 * MAXN]; bool lz[3 * MAXN]; int NXT; int sz; void updv(const int& n) { assert(n != -1 and l[n] != -1 and r[n] != -1); for (int i = 0; i <= M; i++) for (int j = 0; j < 2; j++) v[n][j][i] = v[l[n]][j][v[r[n]][j][i]]; } void init(int n, int nl, int nr) { assert(n != -1 and nl < nr); lz[n] = false; l[n] = r[n] = -1; if (nr - nl == 1) { for (int i = 0; i < M; i++) for (int j = 0; j < 2; j++) v[n][j][i] = i + 1; v[n][a[nl]][M] = M, v[n][!a[nl]][M] = 0; } if (nr - nl > 1) { int m = nl + ((nr - nl) >> 1); init(l[n] = NXT++, nl, m); init(r[n] = NXT++, m, nr); updv(n); } } ST() {} ST(const int& s, bool ini) { sz = s; NXT = 0; if (ini) init(NXT++, 0, sz); } void prop(int n, int nl, int nr) { if (!lz[n]) return; for (int i = 0; i <= M; i++) swap(v[n][0][i], v[n][1][i]); if (nr - nl > 1) { lz[l[n]] = !lz[l[n]]; lz[r[n]] = !lz[r[n]]; } lz[n] = false; } void upd(int n, int nl, int nr, int gl, int gr) { if (gl <= nl and gr >= nr) { lz[n] = !lz[n]; prop(n, nl, nr); return; } if (nr - nl > 1) { prop(n, nl, nr); int m = nl + ((nr - nl) >> 1); if (gl < m) upd(l[n], nl, m, gl, gr); else prop(l[n], nl, m); if (gr > m) upd(r[n], m, nr, gl, gr); else prop(r[n], m, nr); updv(n); return; } assert(false); } void upd(int gl, int gr) { upd(0, 0, sz, gl, gr); } int qry(int n, int nl, int nr, int gl, int gr, int c = M) { prop(n, nl, nr); if (gl <= nl and gr >= nr) { return v[n][0][c]; } if (nr - nl > 1) { int m = nl + ((nr - nl) >> 1); if (gr > m) c = qry(r[n], m, nr, gl, gr, c); if (gl < m) c = qry(l[n], nl, m, gl, gr, c); return c; } assert(false); return -1; } int qry(int gl, int gr) { return qry(0, 0, sz, gl, gr); } } st; void q1() { int l, r, v; scanf( %d%d%d , &l, &r, &v); if (v & 1) st.upd(--l, r); } void q2() { int l, r; scanf( %d%d , &l, &r); printf( %d n , (st.qry(--l, r) == 0 ? 2 : 1)); } int main() { scanf( %d%d%d , &N, &M, &Q); for (int i = 0, v; i < N; i++) { scanf( %d , &v); a[i] = v & 1; } st = *(new ST(N, true)); for (int i = 0, type; i < Q; i++) { scanf( %d , &type); if (type == 1) q1(); else if (type == 2) q2(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 400000 + 10; struct Point { long long x, y; Point operator+(const Point &A) { return (Point){x + A.x, y + A.y}; } Point operator-(const Point &A) { return (Point){x - A.x, y - A.y}; } } P[Maxn]; int n, A[Maxn], cnt; long long sum[Maxn]; double CalCJ(Point A, Point B) { return A.x * B.y - A.y * B.x; } bool OnLeft(Point P, Point A, Point B) { return CalCJ(B - A, P - A) > 0; } bool OnRight(Point P, Point A, Point B) { return CalCJ(B - A, P - A) < 0; } void solve() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &A[i]); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + (long long)A[i]; long long ans = 0, tot; for (int i = 1; i <= n; i++) ans += (long long)A[i] * (long long)i; tot = ans; P[++cnt] = (Point){1, sum[0]}; for (int i = 2; i <= n; i++) { Point C = (Point){1ll, (long long)A[i]}; int l = 2, r = cnt + 1; P[cnt + 1] = (Point){n + 1, (0x3f3f3f3f) * 10ll}; while (l < r) { int mid = ((l + r) >> 1); if (!OnRight(C + P[mid - 1], P[mid - 1], P[mid])) l = mid + 1; else r = mid; } l--; long long nans = tot - (long long)A[i] * (long long)i + sum[i - 1] + P[l].x * (long long)A[i] - P[l].y; ans = ((ans) > (nans) ? (ans) : (nans)); Point Q = (Point){(long long)i, sum[i - 1]}; while (cnt > 1 && !OnLeft(Q, P[cnt - 1], P[cnt])) cnt--; P[++cnt] = Q; } P[cnt = 1] = (Point){n, sum[n]}; for (int i = n - 1; i; i--) { Point C = (Point){1ll, (long long)A[i]}; int l = 2, r = cnt + 1; P[cnt + 1] = (Point){0, (-0x3f3f3f3f) * 10ll}; while (l < r) { int mid = ((l + r) >> 1); if (!OnLeft(P[mid - 1] - C, P[mid - 1], P[mid])) l = mid + 1; else r = mid; } l--; long long nans = tot + sum[i] - (long long)A[i] * (long long)i - P[l].y + P[l].x * (long long)A[i]; ans = ((ans) > (nans) ? (ans) : (nans)); Point Q = (Point){(long long)i, sum[i]}; while (cnt > 1 && !OnRight(Q, P[cnt - 1], P[cnt])) cnt--; P[++cnt] = Q; } printf( %I64d n , ans); } int main() { solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_MS__FILL_DIODE_FUNCTIONAL_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fill_diode ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_N_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_N_TB_V
/**
* udp_dff$PE_pp$PG$N: Positive edge triggered enabled D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_pe_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg DATA_EN;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DATA_EN = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DATA_EN = 1'b0;
#60 NOTIFIER = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 DATA_EN = 1'b1;
#160 NOTIFIER = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 DATA_EN = 1'b0;
#260 NOTIFIER = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 NOTIFIER = 1'b1;
#380 DATA_EN = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 NOTIFIER = 1'bx;
#480 DATA_EN = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PE_pp$PG$N dut (.D(D), .DATA_EN(DATA_EN), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; int n; int A[3005][5], dp[3005][3]; int solve(int x, bool a) { int &r = dp[x][a]; if (r != -1) return r; if (x == n) { if (a == 0) { return r = A[x][1]; } else { return r = A[x][2]; } } if (a == 0) { return r = max(solve(x + 1, 0) + A[x][2], solve(x + 1, 1) + A[x][1]); } else { return r = max(solve(x + 1, 1) + A[x][2], solve(x + 1, 0) + A[x][3]); } } int main() { scanf( %d , &n); for (int i = 1; i <= 3; i++) for (int j = 1; j <= n; j++) { scanf( %d , A[j] + i); } memset(dp, -1, sizeof dp); cout << solve(1, 0) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1000000000; struct sTree { int pl, pr; int val, cnt, debt; } tree[4000009]; int treeSize; int NewNode(int LL, int RR) { int cur = ++treeSize; tree[cur].cnt = RR - LL + 1; return cur; } void CalcDebt(int LL, int RR, int cur); void Add(int L, int R, int d, int LL, int RR, int cur) { if (L <= LL && R >= RR) { tree[cur].debt += d; tree[cur].val += d; return; } int M = LL + (RR - LL) / 2; if (!tree[cur].pl) tree[cur].pl = NewNode(LL, M); if (!tree[cur].pr) tree[cur].pr = NewNode(M + 1, RR); CalcDebt(LL, RR, cur); if (L <= M && LL <= R) { Add(L, R, d, LL, M, tree[cur].pl); } if (L <= RR && M + 1 <= R) { Add(L, R, d, M + 1, RR, tree[cur].pr); } if (tree[tree[cur].pl].val < tree[tree[cur].pr].val) { tree[cur].val = tree[tree[cur].pl].val; tree[cur].cnt = tree[tree[cur].pl].cnt; } else if (tree[tree[cur].pl].val > tree[tree[cur].pr].val) { tree[cur].val = tree[tree[cur].pr].val; tree[cur].cnt = tree[tree[cur].pr].cnt; } else { tree[cur].val = tree[tree[cur].pl].val; tree[cur].cnt = tree[tree[cur].pl].cnt + tree[tree[cur].pr].cnt; } } int Get(int cur) { if (tree[cur].val == 0) { return 2 * inf + 1 - tree[cur].cnt; } return 2 * inf + 1; } void CalcDebt(int LL, int RR, int cur) { int M = LL + (RR - LL) / 2; Add(LL, M, tree[cur].debt, LL, M, tree[cur].pl); Add(M + 1, RR, tree[cur].debt, M + 1, RR, tree[cur].pr); tree[cur].debt = 0; } int n; struct event { char type; int p, L, R; } e[200009]; bool operator<(event a, event b) { if (a.p != b.p) return a.p < b.p; return a.type < b.type; } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; x1 += inf, y1 += inf, x2 += inf, y2 += inf; e[2 * i].type = + ; e[2 * i].p = min(x1, x2) - 1; e[2 * i].L = min(y1, y2); e[2 * i].R = max(y1, y2); e[2 * i + 1].type = - ; e[2 * i + 1].p = max(x1, x2); e[2 * i + 1].L = min(y1, y2); e[2 * i + 1].R = max(y1, y2); } sort(e, e + 2 * n); int root = NewNode(0, 2 * inf); long long ans = 0; int prev = -1; for (int i = 0; i < 2 * n; i++) { int j = i; while (j + 1 < 2 * n && e[j + 1].p == e[i].p) j++; ans += 1LL * Get(root) * (e[i].p - prev); for (int k = i; k <= j; k++) { if (e[k].type == + ) { Add(e[k].L, e[k].R, 1, 0, 2 * inf, root); } else { Add(e[k].L, e[k].R, -1, 0, 2 * inf, root); } } i = j; prev = e[i].p; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int Mod = 1e9 + 9; int Pow(int x, int e) { int ret = 1; while (e) { if (e & 1) ret = 1ll * ret * x % Mod; x = 1ll * x * x % Mod; e >>= 1; } return ret; } const int N = 1e5 + 10; char S[N]; int main() { int n, a, b, k; scanf( %d%d%d%d%s , &n, &a, &b, &k, S); int ia = Pow(a, Mod - 2); int coe = Pow(a, n), ans = 0; for (int i = 0; i <= k - 1; i++) { ans = (ans + 1ll * (S[i] == + ? 1 : Mod - 1) * coe) % Mod; coe = 1ll * coe * ia % Mod * b % Mod; } int p = 1ll * Pow(ia, k) * Pow(b, k) % Mod; if (p == 1) ans = 1ll * ans * ((n + 1) / k) % Mod; else ans = 1ll * ans * (Pow(p, (n + 1) / k) - 1) % Mod * Pow(p - 1, Mod - 2) % Mod; printf( %d n , ans); return 0; }
|
module ITU_656_Decoder( // TV Decoder Input
iTD_DATA,
// Position Output
oTV_X,
oTV_Y,
oTV_Cont,
// YUV 4:2:2 Output
oYCbCr,
oDVAL,
// Control Signals
iSwap_CbCr,
iSkip,
iRST_N,
iCLK_27 );
input [7:0] iTD_DATA;
input iSwap_CbCr;
input iSkip;
input iRST_N;
input iCLK_27;
output [15:0] oYCbCr;
output [9:0] oTV_X;
output [9:0] oTV_Y;
output [31:0] oTV_Cont;
output oDVAL;
// For detection
reg [23:0] Window; // Sliding window register
reg [17:0] Cont; // Counter
reg Active_Video;
reg Start;
reg Data_Valid;
reg Pre_Field;
reg Field;
wire SAV;
reg FVAL;
reg [9:0] TV_Y;
reg [31:0] Data_Cont;
// For ITU-R 656 to ITU-R 601
reg [7:0] Cb;
reg [7:0] Cr;
reg [15:0] YCbCr;
assign oTV_X = Cont>>1;
assign oTV_Y = TV_Y;
assign oYCbCr = YCbCr;
assign oDVAL = Data_Valid;
assign SAV = (Window==24'hFF0000)&(iTD_DATA[4]==1'b0);
assign oTV_Cont= Data_Cont;
always@(posedge iCLK_27 or negedge iRST_N)
begin
if(!iRST_N)
begin
// Register initial
Active_Video<= 1'b0;
Start <= 1'b0;
Data_Valid <= 1'b0;
Pre_Field <= 1'b0;
Field <= 1'b0;
Window <= 24'h0;
Cont <= 18'h0;
Cb <= 8'h0;
Cr <= 8'h0;
YCbCr <= 16'h0;
FVAL <= 1'b0;
TV_Y <= 10'h0;
Data_Cont <= 32'h0;
end
else
begin
// Sliding window
Window <= {Window[15:0],iTD_DATA};
// Active data counter
if(SAV)
Cont <= 18'h0;
else if(Cont<1440)
Cont <= Cont+1'b1;
// Check the video data is active?
if(SAV)
Active_Video<= 1'b1;
else if(Cont==1440)
Active_Video<= 1'b0;
// Is frame start?
Pre_Field <= Field;
if({Pre_Field,Field}==2'b10)
Start <= 1'b1;
// Field and frame valid check
if(Window==24'hFF0000)
begin
FVAL <= !iTD_DATA[5];
Field <= iTD_DATA[6];
end
// ITU-R 656 to ITU-R 601
if(iSwap_CbCr)
begin
case(Cont[1:0]) // Swap
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cr};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cb};
endcase
end
else
begin
case(Cont[1:0]) // Normal
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cb};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cr};
endcase
end
// Check data valid
if( Start // Frame Start?
&& FVAL // Frame valid?
&& Active_Video // Active video?
&& Cont[0] // Complete ITU-R 601?
&& !iSkip ) // Is non-skip pixel?
Data_Valid <= 1'b1;
else
Data_Valid <= 1'b0;
// TV decoder line counter for one field
if(FVAL && SAV)
TV_Y<= TV_Y+1;
if(!FVAL)
TV_Y<= 0;
// Data counter for one field
if(!FVAL)
Data_Cont <= 0;
if(Data_Valid)
Data_Cont <= Data_Cont+1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[200000], b[200000]; set<pair<int, int>> se; set<pair<int, int>>::iterator t; int main() { int n, m, d; cin >> n >> m >> d; for (int i = 0; i < n; i++) { cin >> a[i]; se.insert(make_pair(a[i], i)); } int cnt = 0, pos; while (!se.empty()) { pos = se.begin()->second; b[pos] = ++cnt; se.erase(se.begin()); while (1) { t = se.lower_bound({a[pos] + d + 1, 0}); if (t == se.end()) break; pos = t->second; b[pos] = cnt; se.erase(t); } } cout << cnt << n << b[0] << ; for (int i = 1; i < n; i++) cout << b[i] << ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_TB_V
`define SKY130_FD_SC_HD__NOR4_TB_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__nor4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_TB_V
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, k; cin >> n >> k; long long a[n + 2][n + 2], i, j; string s; memset(a, 0, sizeof(a)); for (i = 1; i <= n; i++) { cin >> s; for (j = 1; j <= n; j++) a[i][j] = (s[j - 1] == B ? 1 : 0); } long long left[n + 2][n + 2], right[n + 2][n + 2], top[n + 2][n + 2], bot[n + 2][n + 2]; memset(left, 0, sizeof(left)); memset(right, 0, sizeof(right)); memset(bot, 0, sizeof(bot)); memset(top, 0, sizeof(top)); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) left[i][j] = left[i][j - 1] + a[i][j]; for (j = n; j >= 1; j--) right[i][j] = right[i][j + 1] + a[i][j]; } for (j = 1; j <= n; j++) { for (i = 1; i <= n; i++) top[i][j] = top[i - 1][j] + a[i][j]; for (i = n; i >= 1; i--) bot[i][j] = bot[i + 1][j] + a[i][j]; } long long row[n + 2], col[n + 2]; memset(row, 0, sizeof(row)); memset(col, 0, sizeof(col)); for (i = 1; i <= n; i++) row[i] = row[i - 1] + (right[i][1] == 0); for (j = 1; j <= n; j++) col[j] = col[j - 1] + (bot[1][j] == 0); long long dpcol[n + 2][n + 2]; memset(dpcol, 0, sizeof(dpcol)); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { dpcol[i][j] = (top[i - 1][j] == 0); if (i + k <= n) dpcol[i][j] = dpcol[i][j] && (bot[i + k][j] == 0); } } for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) dpcol[i][j] += dpcol[i][j - 1]; } long long dprow[n + 2][n + 2]; memset(dprow, 0, sizeof(dprow)); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { dprow[i][j] = (left[i][j - 1] == 0); if (j + k <= n) dprow[i][j] = dprow[i][j] && (right[i][j + k] == 0); } } for (j = 1; j <= n; j++) for (i = 1; i <= n; i++) dprow[i][j] += dprow[i - 1][j]; long long ans = 0; for (i = 1; i <= n - k + 1; i++) { for (j = 1; j <= n - k + 1; j++) { long long temp = col[j - 1] + col[n] - col[j + k - 1] + row[i - 1] + row[n] - row[i + k - 1]; temp += (dpcol[i][j + k - 1] - dpcol[i][j - 1]); temp += (dprow[i + k - 1][j] - dprow[i - 1][j]); ans = max(ans, temp); } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 500; const int INF = 1e7 + 500; const int MOD = 1e9 + 7; const int LOG = 18; const double EPS = 1e-9; const double PI = 3.1415926535; vector<pair<int, int> > P; long double L = INF, R = -INF, M1, M2; long double dist(long double x0, long double y0, long double x1, long double y1) { return sqrt((x1 - x0) * (x1 - x0) + (y1 - y0) * (y1 - y0)); } long double f(long double sx) { long double s, h, r = 0; for (auto p : P) { s = dist(sx, 0, p.first, p.second); h = dist(sx, 0, sx, p.second); r = max(r, (s * s) / (2 * h)); } return r; } int main() { int N, xi, yi; bool pl = false, mi = false; cin >> N; for (int i = 0; i < N; i++) { cin >> xi >> yi; P.push_back({xi, yi}); if (yi > 0) pl = true; if (yi < 0) mi = true; if (L > xi) L = xi; if (R < xi) R = xi; } if (pl & mi) { cout << -1 << endl; return 0; } long double rad1, rad2, ans = 1e18; for (int i = 0; i < 500; i++) { M1 = (2 * L + R) / 3; M2 = (L + 2 * R) / 3; rad1 = f(M1); rad2 = f(M2); if (rad1 < rad2) { R = M2; ans = min(ans, rad1); } else { L = M1; ans = min(ans, rad2); } } cout << setprecision(20) << ans << endl; return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_datamux(datain, sel, dataout);
parameter DATA_WIDTH = 8;
parameter SELECT_WIDTH = 1;
parameter NUMBER_OF_CHANNELS = 2;
input [NUMBER_OF_CHANNELS * DATA_WIDTH - 1 : 0] datain;
input [SELECT_WIDTH - 1 : 0] sel;
output [DATA_WIDTH - 1 : 0] dataout;
wire [DATA_WIDTH - 1 : 0] vectorized_data [0 : NUMBER_OF_CHANNELS - 1];
assign dataout = vectorized_data[sel];
genvar c;
generate
for(c = 0 ; c < NUMBER_OF_CHANNELS ; c = c + 1)
begin : channel_iterator
assign vectorized_data[c] = datain[(c + 1) * DATA_WIDTH - 1 : c * DATA_WIDTH];
end
endgenerate
`ifdef ADD_UNIPHY_SIM_SVA
assert property (@datain NUMBER_OF_CHANNELS == 2**SELECT_WIDTH) else
$error("%t, [DATAMUX ASSERT] NUMBER_OF_CHANNELS PARAMETER is incorrect, NUMBER_OF_CHANNELS = %d, 2**SELECT_WIDTH = %d", $time, NUMBER_OF_CHANNELS, 2**SELECT_WIDTH);
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__SEDFXTP_PP_BLACKBOX_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLRBN_BEHAVIORAL_PP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1010; int h[N], e[2 * N], ne[2 * N], w[2 * N], idx; int dist[N][N]; int n, m, k; bool st[N]; pair<int, int> q[N]; void add(int a, int b, int c) { e[idx] = b; ne[idx] = h[a]; w[idx] = c; h[a] = idx++; } priority_queue<pair<int, int>, vector<pair<int, int>>, greater<pair<int, int>>> heap; void dijkstra(int start, int dist[]) { memset(st, 0, sizeof st); dist[start] = 0; heap.push({0, start}); while (heap.size()) { int t = heap.top().second; heap.pop(); if (st[t]) continue; st[t] = 1; for (int i = h[t]; i != -1; i = ne[i]) { int j = e[i]; if (dist[j] > dist[t] + w[i]) { dist[j] = dist[t] + w[i]; heap.push({dist[j], j}); } } } } int main() { ios::sync_with_stdio(false); cin.tie(); cout.tie(0); int T = 1; while (T--) { memset(dist, 0x3f, sizeof dist); memset(h, -1, sizeof h); cin >> n >> m >> k; for (int i = 1; i <= m; i++) { int a, b, c; cin >> a >> b >> c; add(a, b, c), add(b, a, c); } for (int i = 1; i <= k; i++) cin >> q[i].first >> q[i].second; for (int i = 1; i <= n; i++) dijkstra(i, dist[i]); long long ans = 1e18; for (int i = 0; i < idx; i += 2) { int a = e[i], b = e[i ^ 1]; long long now = 0; for (int j = 1; j <= k; j++) { int from = q[j].first, to = q[j].second; now += min(min(dist[from][a] + dist[b][to], dist[from][b] + dist[a][to]), dist[from][to]); } ans = min(ans, now); } cout << ans << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_4_V
`define SKY130_FD_SC_HS__FAH_4_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fah_4 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
sky130_fd_sc_hs__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fah_4 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(NULL); int n, m; cin >> n >> m; vector<char> A(n * 2); for (int i = 0; i < n * 2; i++) cin >> A[i]; vector<vector<pair<int, int> > > table(n * 2, vector<pair<int, int> >(20)); for (int i = 0; i < n * 2; i++) { if (A[i] == X || i == n - 1 || i == n * 2 - 1) table[i][0] = make_pair(-1, -1); else { if (A[i + 1] == . ) table[i][0] = make_pair(i + 1, 1); else { int num = (i < n ? i + n : i - n); if (A[num] == . ) table[i][0] = make_pair(num, 1); else table[i][0] = make_pair(-1, -1); } } } for (int k = 1; k < 20; k++) { for (int i = 0; i < n * 2; i++) { if (table[i][k - 1].first == -1) table[i][k] = make_pair(-1, -1); else { pair<int, int> p = table[i][k - 1]; table[i][k] = make_pair(table[p.first][k - 1].first, p.second + table[p.first][k - 1].second); } } } for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--, b--; if (a % n > b % n) swap(a, b); int k = 19; int res = 0; while (k >= 0) { if (table[a][k].first != -1 && table[a][k].first % n < b % n) { res += table[a][k].second; a = table[a][k].first; } k--; } if (a % n != b % n) { if (A[a + 1] == . ) a = a + 1, res++; else { a = a < n ? a + n : a - n, res++; if (A[a] == X ) { cout << -1 n ; continue; } if (A[a + 1] == . ) a = a + 1, res++; else { cout << -1 n ; continue; } } } if (a == b) cout << res << n ; else { if (A[a < n ? a + n : a - n] == . ) { a = (a < n ? a + n : a - n), res++; if (a == b) cout << res << n ; else cout << -1 n ; } else cout << -1 n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, Q; vector<vector<int>> V; map<pair<int, int>, int> M; int ret[101010]; template <int um> class UF { public: vector<int> par, rank; vector<vector<int>> hist; UF() { par = rank = vector<int>(um, 0); for (int i = 0; i < um; i++) par[i] = i; } void reinit() { int i; for (i = 0; i < (um); i++) rank[i] = 0, par[i] = i; } int operator[](int x) { return (par[x] == x) ? (x) : operator[](par[x]); } void pop() { if (hist.size()) { auto a = hist.back(); hist.pop_back(); par[a[0]] = a[1]; rank[a[0]] = a[2]; par[a[3]] = a[4]; rank[a[3]] = a[5]; } } void operator()(int x, int y) { x = operator[](x); y = operator[](y); hist.push_back({x, par[x], rank[x], y, par[y], rank[y]}); if (x == y) return; if (rank[x] < rank[y]) { par[x] = y; } else if (rank[x] > rank[y]) { par[y] = x; } else { rank[x]++; par[y] = x; } } }; void dfs(int L, int R, UF<201010>& uf, vector<vector<int>> V) { vector<vector<int>> LV, RV; int nums = 0; int M = (L + R) / 2; int con = 0; if (V.empty()) return; for (auto& v : V) { if (v[2] <= L && R <= v[3]) { uf(v[0] * 2, v[1] * 2 + 1); uf(v[0] * 2 + 1, v[1] * 2); if (uf[v[0] * 2] == uf[v[0] * 2 + 1]) con = 1; if (uf[v[1] * 2] == uf[v[1] * 2 + 1]) con = 1; nums += 2; } else { if (v[2] < M) LV.push_back({v[0], v[1], max(L, v[2]), min(M, v[3])}); if (v[3] > M) RV.push_back({v[0], v[1], max(M, v[2]), min(R, v[3])}); } } int i; if (con) { for (int i = L; i < R; i++) ret[i] = 1; } else { dfs(L, M, uf, LV); dfs(M, R, uf, RV); } while (nums--) uf.pop(); } void solve() { int i, j, k, l, r, x, y; string s; cin >> N >> Q; for (i = 0; i < (Q); i++) { cin >> x >> y; x--, y--; if (x > y) swap(x, y); if (M.count({x, y}) == 0) { M[{x, y}] = i; } else { V.push_back({x, y, M[{x, y}], i}); M.erase({x, y}); } } for (auto& r : M) V.push_back({r.first.first, r.first.second, r.second, Q}); UF<201010> uf; dfs(0, Q, uf, V); for (i = 0; i < (Q); i++) { if (ret[i]) cout << NO << endl; else cout << YES << endl; } } int main(int argc, char** argv) { string s; int i; if (argc == 1) ios::sync_with_stdio(false), cin.tie(0); for (i = 0; i < (argc - 1); i++) s += argv[i + 1], s += n ; for (i = 0; i < (s.size()); i++) ungetc(s[s.size() - 1 - i], stdin); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_2_V
`define SKY130_FD_SC_LS__A32O_2_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32o_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NAND3B_FUNCTIONAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_FUNCTIONAL_V
|
// file: clk25_2_X.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______226.965____237.727
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________25____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk25_2_X,clk_wiz_v3_6,{component_name=clk25_2_X,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module clk25_2_X
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET
);
// Input buffering
//------------------------------------
//IBUFG clkin1_buf
// (.O (clkin1),
// .I (CLK_IN1));
assign clkin1 = CLK_IN1;
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
/*
freq M D
161 38.75 6
168 38.75 5.75
167 38.5 5.75
92 39.75 10.75
123 39.5 8
*/
localparam real MULT = 38.75;
localparam real DIV = 6.0;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (MULT),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (40.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_unused),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR3B_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor3b (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_BLACKBOX_V
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module oq_regs_eval_full
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH),
parameter MAX_PKT = 2048/CTRL_WIDTH, // allow for 2K bytes,
parameter MIN_PKT = 60/CTRL_WIDTH + 1,
parameter PKTS_IN_RAM_WIDTH = log2((2**SRAM_ADDR_WIDTH)/MIN_PKT)
)
(
// --- Inputs from dst update ---
input dst_update,
input [NUM_OQ_WIDTH-1:0] dst_oq,
input [PKTS_IN_RAM_WIDTH-1:0] dst_max_pkts_in_q,
input [PKTS_IN_RAM_WIDTH-1:0] dst_num_pkts_in_q,
input dst_num_pkts_in_q_done,
input [SRAM_ADDR_WIDTH-1:0] dst_oq_full_thresh,
input [SRAM_ADDR_WIDTH-1:0] dst_num_words_left,
input dst_num_words_left_done,
// --- Inputs from src update ---
input src_update,
input [NUM_OQ_WIDTH-1:0] src_oq,
input [PKTS_IN_RAM_WIDTH-1:0] src_max_pkts_in_q,
input [PKTS_IN_RAM_WIDTH-1:0] src_num_pkts_in_q,
input src_num_pkts_in_q_done,
input [SRAM_ADDR_WIDTH-1:0] src_oq_full_thresh,
input [SRAM_ADDR_WIDTH-1:0] src_num_words_left,
input src_num_words_left_done,
// --- Clear the flag ---
input initialize,
input [NUM_OQ_WIDTH-1:0] initialize_oq,
output [NUM_OUTPUT_QUEUES-1:0] full,
// --- Misc
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
// ------------- Wires/reg ------------------
reg [NUM_OUTPUT_QUEUES-1:0] full_pkts_in_q;
reg [NUM_OUTPUT_QUEUES-1:0] full_words_left;
wire src_full_pkts_in_q;
reg src_full_pkts_in_q_held;
wire dst_full_pkts_in_q;
wire src_full_words_left;
reg src_full_words_left_held;
wire dst_full_words_left;
reg dst_update_d1;
reg src_update_d1;
reg [PKTS_IN_RAM_WIDTH-1:0] dst_max_pkts_in_q_held;
reg [PKTS_IN_RAM_WIDTH-1:0] src_max_pkts_in_q_held;
reg [PKTS_IN_RAM_WIDTH-1:0] dst_oq_full_thresh_held;
reg [PKTS_IN_RAM_WIDTH-1:0] src_oq_full_thresh_held;
reg [NUM_OQ_WIDTH-1:0] dst_oq_held;
reg [NUM_OQ_WIDTH-1:0] src_oq_held;
reg src_num_pkts_in_q_done_held;
reg src_num_words_left_done_held;
// ------------- Logic ------------------
assign full = full_pkts_in_q | full_words_left;
assign src_full_pkts_in_q = src_num_pkts_in_q >= src_max_pkts_in_q_held &&
src_max_pkts_in_q_held != 0;
assign dst_full_pkts_in_q = dst_num_pkts_in_q >= dst_max_pkts_in_q_held &&
dst_max_pkts_in_q_held != 0;
assign src_full_words_left = src_num_words_left <= src_oq_full_thresh_held ||
src_num_words_left < 2 * MAX_PKT;
assign dst_full_words_left = dst_num_words_left <= dst_oq_full_thresh_held ||
dst_num_words_left < 2 * MAX_PKT;
always @(posedge clk)
begin
dst_update_d1 <= dst_update;
src_update_d1 <= src_update;
if (reset) begin
full_pkts_in_q <= 'h0;
full_words_left <= 'h0;
end
else begin
if (dst_update) begin
dst_oq_held <= dst_oq;
end
if (src_update) begin
src_oq_held <= src_oq;
end
// Latch the maximums the cycle immediately following the update
// notifications. The update notifications are linked to the read
// ports of the appropriate registers so the read value will always
// be returned in the next cycle.
if (dst_update_d1) begin
dst_max_pkts_in_q_held <= dst_max_pkts_in_q;
dst_oq_full_thresh_held <= dst_oq_full_thresh;
end
if (src_update_d1) begin
src_max_pkts_in_q_held <= src_max_pkts_in_q;
src_oq_full_thresh_held <= src_oq_full_thresh;
end
// Update the full status giving preference to stores over removes
// since we don't want to accidentally try adding to a full queue
// Number of packets in queue
if (dst_num_pkts_in_q_done) begin
full_pkts_in_q[dst_oq_held] <= dst_full_pkts_in_q;
src_num_pkts_in_q_done_held <= src_num_pkts_in_q_done;
src_full_pkts_in_q_held <= src_full_pkts_in_q;
end
else if (src_num_pkts_in_q_done) begin
full_pkts_in_q[src_oq_held] <= src_full_pkts_in_q;
end
else if (src_num_pkts_in_q_done_held) begin
full_pkts_in_q[src_oq_held] <= src_full_pkts_in_q_held;
end
else if (initialize) begin
full_pkts_in_q[initialize_oq] <= 1'b0;
end
// Number of words left:
if (dst_num_words_left_done) begin
full_words_left[dst_oq_held] <= dst_full_words_left;
src_num_words_left_done_held <= src_num_words_left_done;
src_full_words_left_held <= src_full_words_left;
end
else if (src_num_words_left_done) begin
full_words_left[src_oq_held] <= src_full_words_left;
end
else if (src_num_words_left_done_held) begin
full_words_left[src_oq_held] <= src_full_words_left_held;
end
else if (initialize) begin
full_words_left[initialize_oq] <= 1'b0;
end
end
end
endmodule // oq_regs_eval_full
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const int MAXN = 30005; int lst[MAXN], N; bool ok(vector<int> &v) { if ((int)v.size() <= 2) return true; for (int i = (int)v.size() - 2; i >= max(1, (int)v.size() - 5); i--) if (v[i + 1] - v[i] != v[1] - v[0]) return false; return true; } bool check(vector<int> &a, vector<int> &b, int n) { if ((int)a.size() < 2) { b.push_back(lst[n]); if (!ok(b)) { b.erase(b.end() - 1); a.push_back(lst[n]); } } else if ((int)b.size() < 2) { a.push_back(lst[n]); if (!ok(a)) { a.erase(a.end() - 1); b.push_back(lst[n]); } } else { a.push_back(lst[n]); if (!ok(a)) { a.erase(a.end() - 1); b.push_back(lst[n]); } } return ok(a) && ok(b); } int main() { cin >> N; for (int i = 0; i < N; i++) cin >> lst[i]; int sz = min(6, N); vector<int> x, y; for (int mask = 0; mask < (1 << sz); mask++) { vector<int> a, b; for (int i = 0; i < sz; i++) { if (mask & (1 << i)) a.push_back(lst[i]); else b.push_back(lst[i]); } if (!ok(a) || !ok(b)) continue; bool k = true; for (int i = sz; i < N; i++) { if (!check(a, b, i)) { k = false; break; } } if (k) { x = a, y = b; break; } } if ((int)x.size() == 0 && (int)y.size() > 0) { x.push_back(y[(int)y.size() - 1]); y.erase(y.end() - 1); } else if ((int)y.size() == 0 && (int)x.size() > 0) { y.push_back(x[(int)x.size() - 1]); x.erase(x.end() - 1); } if ((int)x.size() == 0 && (int)y.size() == 0) { cout << No solution << endl; return 0; } for (int i = 0; i < (int)x.size(); i++) cout << x[i] << ; cout << endl; for (int i = 0; i < (int)y.size(); i++) cout << y[i] << ; cout << endl; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
reg first_req;
wire xzcheck_enable;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if((first_req ^ first_req) == 1'b0) begin
if (req)
first_req <= 1'b1;
end
else begin
first_req <= 1'b0;
end
end
else
first_req <= 1'b0;
end
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_handshake_assert #(
.min_ack_cycle(min_ack_cycle),
.max_ack_cycle(max_ack_cycle),
.req_drop(req_drop),
.deassert_count(deassert_count),
.max_ack_length(max_ack_length))
assert_handshake_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.req(req),
.ack(ack),
.first_req(first_req),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_handshake_assume #(
.min_ack_cycle(min_ack_cycle),
.max_ack_cycle(max_ack_cycle),
.req_drop(req_drop),
.deassert_count(deassert_count),
.max_ack_length(max_ack_length))
assert_handshake_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.req(req),
.ack(ack),
.first_req(first_req),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_handshake_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_handshake_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.req(req),
.ack(ack));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_handshake.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_handshake_assert (clk, reset_n, req, ack, first_req, xzcheck_enable);
parameter min_ack_cycle = 0;
parameter max_ack_cycle = 0;
parameter req_drop = 0;
parameter deassert_count = 0;
parameter max_ack_length = 0;
input clk, reset_n, req, ack, first_req, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_handshake_assume (clk, reset_n, req, ack, first_req, xzcheck_enable);
parameter min_ack_cycle = 0;
parameter max_ack_cycle = 0;
parameter req_drop = 0;
parameter deassert_count = 0;
parameter max_ack_length = 0;
input clk, reset_n, req, ack, first_req, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_handshake_cover (clk, reset_n, req, ack);
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n, req, ack;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m = 0; cin >> n; while (n--) { int x, y; cin >> x >> y; m = max(m, x + y); } cout << m; return 0; }
|
`include "constants.vh"
`include "alu_ops.vh"
//`default_nettype none
module exunit_ldst
(
input wire clk,
input wire reset,
input wire [`DATA_LEN-1:0] ex_src1,
input wire [`DATA_LEN-1:0] ex_src2,
input wire [`ADDR_LEN-1:0] pc,
input wire [`DATA_LEN-1:0] imm,
input wire dstval,
input wire [`SPECTAG_LEN-1:0] spectag,
input wire specbit,
input wire issue,
input wire prmiss,
input wire [`SPECTAG_LEN-1:0] spectagfix,
input wire [`RRF_SEL-1:0] rrftag,
output wire [`DATA_LEN-1:0] result,
output wire rrf_we,
output wire rob_we, //set finish
output wire [`RRF_SEL-1:0] wrrftag,
output wire kill_speculative,
output wire busy_next,
//Signal StoreBuf
output wire stfin,
//Store
output wire memoccupy_ld,
input wire fullsb,
output wire [`DATA_LEN-1:0] storedata,
output wire [`ADDR_LEN-1:0] storeaddr,
//Load
input wire hitsb,
output wire [`ADDR_LEN-1:0] ldaddr,
input wire [`DATA_LEN-1:0] lddatasb,
input wire [`DATA_LEN-1:0] lddatamem
);
reg busy;
wire clearbusy;
wire [`ADDR_LEN-1:0] effaddr;
wire killspec1;
//LATCH
reg dstval_latch;
reg [`RRF_SEL-1:0] rrftag_latch;
reg specbit_latch;
reg [`SPECTAG_LEN-1:0] spectag_latch;
reg [`DATA_LEN-1:0] lddatasb_latch;
reg hitsb_latch;
reg insnvalid_latch;
assign clearbusy = (killspec1 || dstval || (~dstval && ~fullsb)) ? 1'b1 : 1'b0;
assign killspec1 = ((spectag & spectagfix) != 0) && specbit && prmiss;
assign kill_speculative = ((spectag_latch & spectagfix) != 0) && specbit_latch && prmiss;
assign result = hitsb_latch ? lddatasb_latch : lddatamem;
assign rrf_we = dstval_latch & insnvalid_latch;
assign rob_we = insnvalid_latch;
assign wrrftag = rrftag_latch;
assign busy_next = clearbusy ? 1'b0 : busy;
assign stfin = ~killspec1 & busy & ~dstval;
assign memoccupy_ld = ~killspec1 & busy & dstval;
assign storedata = ex_src2;
assign storeaddr = effaddr;
assign ldaddr = effaddr;
assign effaddr = ex_src1 + imm;
always @ (posedge clk) begin
if (reset | killspec1 | ~busy | (~dstval & fullsb)) begin
dstval_latch <= 0;
rrftag_latch <= 0;
specbit_latch <= 0;
spectag_latch <= 0;
lddatasb_latch <= 0;
hitsb_latch <= 0;
insnvalid_latch <= 0;
end else begin
dstval_latch <= dstval;
rrftag_latch <= rrftag;
specbit_latch <= specbit;
spectag_latch <= spectag;
lddatasb_latch <= lddatasb;
hitsb_latch <= hitsb;
insnvalid_latch <= ~killspec1 & ((busy & dstval) |
(busy & ~dstval & ~fullsb));
end
end // always @ (posedge clk)
always @ (posedge clk) begin
if (reset | killspec1) begin
busy <= 0;
end else begin
busy <= issue | busy_next;
end
end
endmodule // exunit_ldst
//`default_nettype none
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; int clean(vector<pair<int, int> > &I) { for (int i = 0; i < (int)I.size(); i++) { swap(I[i].first, I[i].second); I[i].second *= -1; } sort(begin(I), end(I)); for (int i = 0; i < (int)I.size(); i++) { I[i].second *= -1; swap(I[i].first, I[i].second); } vector<pair<int, int> > I_nw; int lastb = -1; for (int i = 0; i < (int)I.size(); i++) { if (lastb < I[i].first) I_nw.push_back(I[i]); lastb = max(lastb, I[i].first); } I = I_nw; return I_nw.size(); } long long pw(long long a, long long e, long long mod) { if (e <= 0) return 1; long long x = pw(a, e / 2, mod); x = (x * x) % mod; if (e % 2) x = (x * a) % mod; return x; } int main() { cin.sync_with_stdio(0); cin.tie(0); cout << fixed << setprecision(10); int K, N[2]; cin >> K >> N[0] >> N[1]; vector<pair<int, int> > I[2]; map<int, int> M; M[0] = M[K] = 0; for (int k = 0; k < 2; k++) { I[k].resize(N[k]); for (int i = 0; i < N[k]; i++) { cin >> I[k][i].first >> I[k][i].second; I[k][i].first--; } N[k] = clean(I[k]); for (int i = 0; i < N[k]; i++) M[I[k][i].first] = M[I[k][i].second] = 0; } int m = 0, last = 0; vector<int> len; vector<long long> cnt; for (auto it = M.begin(); it != M.end(); it++) { it->second = m++; if (it->first != last) len.push_back(it->first - last); last = it->first; } int L = len.size(); cnt.resize(L); for (int i = 0; i < L; i++) cnt[i] = (pw(2, len[i], mod) + mod - 2) % mod; for (int k = 0; k < 2; k++) for (int i = 0; i < N[k]; i++) { I[k][i].first = M[I[k][i].first]; I[k][i].second = M[I[k][i].second]; } vector<long long> ans[3]; for (int k = 0; k < 3; k++) ans[k].resize(L + 1, 0); ans[2][0] = 1; vector<long long> sum_ans[3]; for (int k = 0; k < 3; k++) sum_ans[k].resize(L + 1, 0); int pos[2] = {0, 0}, last_st[2] = {-1, -1}; for (int i = 0; i < L; i++) { for (int k = 0; k < 3; k++) sum_ans[k][i + 1] = (sum_ans[k][i] + ans[k][i]) % mod; ans[2][i + 1] = (ans[0][i] + ans[1][i] + ans[2][i]) * cnt[i] % mod; for (int k = 0; k < 2; k++) { while (pos[1 - k] < N[1 - k] && I[1 - k][pos[1 - k]].second <= i + 1) { last_st[1 - k] = I[1 - k][pos[1 - k]].first; pos[1 - k]++; } ans[k][i + 1] = (sum_ans[2][i + 1] - sum_ans[2][last_st[1 - k] + 1] + sum_ans[1 - k][i + 1] - sum_ans[1 - k][last_st[1 - k] + 1]) % mod; } } long long ansF = (ans[0][L] + ans[1][L] + ans[2][L]) % mod; if (ansF < 0) ansF += mod; cout << ansF << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBN_1_V
`define SKY130_FD_SC_LS__SDFBBN_1_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBN_1_V
|
#include <bits/stdc++.h> using namespace std; struct ter { int cx, cy, dir, pt, rem; ter(){}; ter(int _cx, int _cy, int _dir, int _pt, int _rem) : cx(_cx), cy(_cy), dir(_dir), pt(_pt), rem(_rem){}; }; const int dx[] = {0, 1, 1, 1, 0, -1, -1, -1}; const int dy[] = {1, 1, 0, -1, -1, -1, 0, 1}; ter on; queue<ter> Q; int n, t[32], cx, cy, dir, pt, rem, dir1, dir2, sol, maxx = -3; bool bio[312][312][8][31][6], mp[312][312]; void radi() { while (!Q.empty()) { on = Q.front(); cx = on.cx; cy = on.cy; dir = on.dir; pt = on.pt; rem = on.rem; Q.pop(); if (bio[cx][cy][dir][pt][rem]) continue; bio[cx][cy][dir][pt][rem] = 1; if (mp[cx][cy] == 0) ++sol; mp[cx][cy] = 1; if (rem > 0) { Q.push(ter(cx + dx[dir], cy + dy[dir], dir, pt, rem - 1)); } else { if (pt == n) continue; dir1 = (dir + 1) % 8; dir2 = (dir + 7) % 8; Q.push(ter(cx + dx[dir1], cy + dy[dir1], dir1, pt + 1, t[pt + 1] - 1)); Q.push(ter(cx + dx[dir2], cy + dy[dir2], dir2, pt + 1, t[pt + 1] - 1)); } } } int main() { std::ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; ++i) cin >> t[i]; Q.push(ter(155, 155, 0, 1, t[1] - 1)); radi(); cout << sol << endl; return 0; }
|
module ddr2_ctrl_input(
sys_rst_n,
ddr2_clk,
local_init_done,
local_ready,
local_address,
local_read_req,
local_write_req,
local_wdata,
local_be,
local_size,
local_burstbegin,
um2ddr_wrclk,
um2ddr_wrreq,
um2ddr_data,
um2ddr_ready,
um2ddr_command_wrreq,
um2ddr_command,
rd_ddr2_size,
rd_ddr2_size_wrreq,
read_permit
);
input sys_rst_n;
input ddr2_clk;
input local_ready;
input local_init_done;
output[25:0] local_address;
output local_write_req;
output local_read_req;
output local_burstbegin;
output[31:0] local_wdata;
output[3:0] local_be;
output[3:0] local_size;
input um2ddr_wrclk;
input um2ddr_wrreq;
input [127:0] um2ddr_data;
output um2ddr_ready;
input um2ddr_command_wrreq;
input [33:0] um2ddr_command;
output[6:0] rd_ddr2_size;
output rd_ddr2_size_wrreq;
input read_permit;
/////////////////////////////////////
reg[25:0] local_address;
reg local_write_req;
reg local_read_req;
reg local_burstbegin;
reg[31:0] local_wdata;
reg[3:0] local_be;
reg[3:0] local_size;
wire um2ddr_ready;
reg[6:0] rd_ddr2_size;
reg rd_ddr2_size_wrreq;
reg[95:0] um2ddr_reg;
///////////////////////////////////
reg [6:0] pkt_len;
reg [1:0] shift;
reg [25:0] op_addr;
reg [2:0] state;
///////////////////////////////////
assign um2ddr_ready = ~(um2ddr_afull | um2ddr_command_afull); //changed by mxl from & to |;
///////////////////////////////////
parameter idle_s = 3'h0,
wr_start_s = 3'h1,
wr_mid_fs = 3'h2,
wr_mid_sd = 3'h3,
wr_end_s = 3'h4,
rd_start_s = 3'h5,
rd_s = 3'h6,
wait_s = 3'h7;
always@(posedge ddr2_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)begin
local_write_req <= 1'b0;
local_read_req <= 1'b0;
local_burstbegin <= 1'b0;
rd_ddr2_size_wrreq <= 1'b0;
um2ddr_command_rdreq <= 1'b0;
um2ddr_rdreq <= 1'b0;
um2ddr_reg <= 96'b0;
shift <= 2'b0;
state <= idle_s;
end
else begin
case(state)
idle_s:begin
if(um2ddr_command_empty)begin
local_write_req <= 1'b0;
local_read_req <= 1'b0;
local_burstbegin <= 1'b0;
rd_ddr2_size_wrreq <= 1'b0;
um2ddr_command_rdreq <= 1'b0;
state <= idle_s;
end
else begin
op_addr <= um2ddr_command_rdata[25:0];
pkt_len <= um2ddr_command_rdata[32:26];
um2ddr_command_rdreq <= 1'b1;
local_address <= um2ddr_command_rdata[25:0];
if(um2ddr_command_rdata[33])begin//read ddr2
pkt_len <= um2ddr_command_rdata[32:26]<<2;
state <= rd_start_s;
end
else begin//write ddr2
um2ddr_rdreq <= 1'b1;
//local_wdata <= um2ddr_rdata;
state <= wr_start_s;
end
end
end
wr_start_s:begin
um2ddr_command_rdreq <= 1'b0;
um2ddr_rdreq <= 1'b0;
if(local_ready&local_init_done)begin
local_write_req <= 1'b1;
local_burstbegin <= 1'b1;
local_be <= 4'hf;
local_size <= 4'h4;
pkt_len <= pkt_len - 1'b1;
local_address <= op_addr ;
// um2ddr_rdreq <= 1'b1;
local_wdata <= um2ddr_rdata[127:96];
um2ddr_reg <= um2ddr_rdata[95:0];
state <= wr_mid_fs;
end
else begin
local_write_req <= 1'b0;
state <= wr_start_s;
end
end
wr_mid_fs:
begin
if(local_ready&local_init_done)
begin
local_write_req <= 1'b1;
local_burstbegin <= 1'b0;
um2ddr_rdreq <= 1'b0;
local_be <= 4'hf;
local_wdata <= um2ddr_reg[95:64];
state <= wr_mid_sd;
end
else
begin
//local_write_req <= 1'b0;
local_burstbegin <= 1'b0;
um2ddr_rdreq <= 1'b0;
state <= wr_mid_fs;
end
end
wr_mid_sd:
begin
if(local_ready&local_init_done)
begin
local_write_req <= 1'b1;
um2ddr_rdreq <= 1'b0;
local_be <= 4'hf;
local_wdata <= um2ddr_reg[63:32];
state <= wr_end_s;
end
else
begin
// local_write_req <= 1'b0;
state <= wr_mid_sd;
end
end
wr_end_s:
begin
if(local_ready&local_init_done)
begin
local_write_req <= 1'b1;
um2ddr_rdreq <= 1'b0;
local_be <= 4'hf;
local_wdata <= um2ddr_reg[31:0];
op_addr <= op_addr + 4'h4;
if(pkt_len == 7'h0)
begin
state <= idle_s;
end
else
begin
um2ddr_rdreq <= 1'b1;
state <= wr_start_s;
end
end
else
begin
state <= wr_end_s;
end
end
rd_start_s:begin
um2ddr_command_rdreq <= 1'b0;
if(read_permit==1'b0)begin
state <= rd_start_s;
end
else begin
rd_ddr2_size <= pkt_len;
rd_ddr2_size_wrreq <= 1'b1;
state <= rd_s;
end
end
rd_s:begin
rd_ddr2_size_wrreq <= 1'b0;
if(local_ready&&local_init_done)
begin
local_read_req <= 1'b1;
local_burstbegin <= 1'b1;
local_be <= 4'hf;
local_address <= op_addr;
if(pkt_len > 7'h8)
begin
local_size <= 4'h4;
pkt_len <= pkt_len - 4'h4;
op_addr <= op_addr + 4'h4;
state <= wait_s;
end
else begin
local_size <= pkt_len[3:0];
//op_addr <= op_addr + pkt_len[3:0];
//local_read_req <= 1'b0;
//local_burstbegin <= 1'b0;
state <= idle_s;
end
end
else begin
local_read_req <= 1'b0;
state <= rd_s;
end
end
wait_s:begin
local_read_req <= 1'b0;
state <= rd_s;
end
default:begin
local_write_req <= 1'b0;
local_read_req <= 1'b0;
local_burstbegin <= 1'b0;
rd_ddr2_size_wrreq <= 1'b0;
um2ddr_command_rdreq <= 1'b0;
um2ddr_rdreq <= 1'b0;
state <= idle_s;
end
endcase
end
end
wire [9:0] um2ddr_wrusedw;
reg um2ddr_rdreq;
wire [127:0] um2ddr_rdata;
wire um2ddr_empty;
um2ddr_fifo um2ddr_fifo (
.aclr(!sys_rst_n),
.data(um2ddr_data),
.rdclk(ddr2_clk),
.rdreq(um2ddr_rdreq),
.wrclk(um2ddr_wrclk),
.wrreq(um2ddr_wrreq),
.q(um2ddr_rdata),
.rdempty(um2ddr_empty),
.wrusedw(um2ddr_wrusedw));
wire um2ddr_afull;
assign um2ddr_afull = (um2ddr_wrusedw > 9'd127)?1'b1:1'b0;
wire [7:0] um2ddr_command_wrusedw;
reg um2ddr_command_rdreq;
wire [33:0] um2ddr_command_rdata;
wire um2ddr_command_empty;
um2ddr_command_fifo um2ddr_command_fifo (
.aclr(!sys_rst_n),
.data(um2ddr_command),
.rdclk(ddr2_clk),
.rdreq(um2ddr_command_rdreq),
.wrclk(um2ddr_wrclk),
.wrreq(um2ddr_command_wrreq),
.q(um2ddr_command_rdata),
.rdempty(um2ddr_command_empty),
.wrusedw(um2ddr_command_wrusedw));
wire um2ddr_command_afull;
assign um2ddr_command_afull = (um2ddr_command_wrusedw > 8'hfa)?1'b1:1'b0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:08 04/16/207
// Design Name:
// Module Name: BinaryExponentiation
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BinaryExponentiation( input clk, input [8:0] base, input [7:0] exponent, input reset,
output reg [99:0] result, output reg isDone
);
reg [99:0] nextResult;
reg nextIsDone;
reg [3:0] nextIndex;
reg [3:0] index;
reg nextStart;
reg start;
initial begin
nextResult = 0;
result = 0;
nextIsDone = 0;
isDone = 0;
index = 7;
nextIndex = 7;
nextStart = 0;
start = 0;
end
always @ (posedge clk) begin
result <= nextResult;
isDone <= nextIsDone;
index <= nextIndex;
start <= nextStart;
end
always @ (*) begin
if (result == 0) begin
nextResult = base;
nextIsDone = 0;
end
else begin
if (isDone == 1) begin
if (reset == 1) begin
nextIsDone = 0;
nextResult = 0;
nextIndex = 7;
nextStart = 0;
end
else begin
nextIsDone = 1;
nextResult = result;
nextIndex = index;
nextStart = start;
end
end
else begin
nextIndex = index > 0 ? index - 1 : index;
nextIsDone = 0;
nextStart = start;
if (exponent[index] == 1 & start == 0) begin
nextStart = 1;
nextResult = result;
end
if (start == 1) begin
if (exponent[index] == 0) begin
nextResult = result * result;
end
else begin
nextResult = result * result * base;
end
if (index == 0) begin
nextIsDone = 1;
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string start[1791791]; string fin[1791791]; pair<int, int> diffs[1791791]; int is_in(string a, string b) { string s = a + # + b; int n = (int)s.length(); vector<int> pi(n); for (int i = 1; i < n; ++i) { int j = pi[i - 1]; while (j > 0 && s[i] != s[j]) j = pi[j - 1]; if (s[i] == s[j]) ++j; pi[i] = j; } for (int i = (int)a.length(); i < pi.size(); ++i) { if (pi[i] == a.length()) { return i - 2 * (int)a.length(); } } return -1; } int main() { ios_base::sync_with_stdio(0); int n; cin >> n; for (int i = 0; i < n; ++i) { cin >> start[i]; } for (int i = 0; i < n; ++i) { cin >> fin[i]; } for (int i = 0; i < n; ++i) { int first_diff = -1; for (int ii = 0; ii < start[i].length(); ++ii) { if (start[i][ii] != fin[i][ii]) { first_diff = ii; break; } } int last_diff = -1; for (int ii = 0; ii < start[i].length(); ++ii) { if (start[i][ii] != fin[i][ii]) { last_diff = ii; } } diffs[i] = {first_diff, last_diff}; } int one_with_diff = -1; for (int i = 0; i < n; ++i) { if (diffs[i].first != -1) { one_with_diff = i; break; } } for (int i = 0; i < n; ++i) { if (diffs[i].first != -1 && diffs[one_with_diff].first != -1 && i != one_with_diff) { if (diffs[i].second - diffs[i].first != diffs[one_with_diff].second - diffs[one_with_diff].first) { cout << NO ; return 0; } for (int ii = 0; ii <= diffs[i].second - diffs[i].first; ++ii) { if (start[i][diffs[i].first + ii] != start[one_with_diff][diffs[one_with_diff].first + ii] || fin[i][diffs[i].first + ii] != fin[one_with_diff][diffs[one_with_diff].first + ii]) { cout << NO ; return 0; } } } } int same_pref_len = 0; for (int pref_len = 1;; ++pref_len) { char pref = # ; bool ok = 1; for (int i = 0; i < n; ++i) { if (diffs[i].first != -1) { if (diffs[i].first < pref_len) { ok = 0; break; } if (pref == # ) { pref = start[i][diffs[i].first - pref_len]; } else { if (pref != start[i][diffs[i].first - pref_len]) { ok = 0; break; } } } } if (!ok) { break; } same_pref_len += 1; } int same_suff_len = 0; for (int suff_len = 1;; ++suff_len) { char suff = # ; bool ok = 1; for (int i = 0; i < n; ++i) { if (diffs[i].first != -1) { if (diffs[i].second + suff_len >= start[i].length()) { ok = 0; break; } if (suff == # ) { suff = start[i][diffs[i].second + suff_len]; } else { if (suff != start[i][diffs[i].second + suff_len]) { ok = 0; break; } } } } if (!ok) { break; } same_suff_len += 1; } string from, to; for (int i = 0; i < n; ++i) { if (diffs[i].first != -1) { from = ; for (int j = diffs[i].first - same_pref_len; j <= diffs[i].second + same_suff_len; ++j) { from += start[i][j]; } to = ; for (int j = diffs[i].first - same_pref_len; j <= diffs[i].second + same_suff_len; ++j) { to += fin[i][j]; } break; } } for (int i = 0; i < n; ++i) { if (diffs[i].first == -1) { if (is_in(from, start[i]) != -1) { cout << NO ; return 0; } } else { if (is_in(from, start[i]) != diffs[i].first - same_pref_len) { cout << NO ; return 0; } } } cout << YES << endl; cout << from << endl; cout << to << endl; }
|
#include <bits/stdc++.h> using namespace std; int T, n, s, t; int main() { cin >> T; while (T--) { cin >> n >> s >> t; cout << max(1, max(n - s + 1, n - t + 1)) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; FILE *in = stdin; class node { public: long long sum[5], hnode; node() { sum[0] = sum[1] = sum[2] = sum[3] = sum[4] = hnode = 0; return; } node(int x) { for (int q = 0; q < 5; q++) { sum[q] = 0; } sum[0] = x; hnode = 1; return; } }; node merge(node a, node b) { node c; c.hnode = a.hnode + b.hnode; int left = a.hnode % 5; for (int q = 0; q < 5; q++) { c.sum[q] = a.sum[q] + b.sum[(5 - left + q) % 5]; } return c; } class segment_tree { public: node tree[4 * 100000]; segment_tree() { for (int q = 0; q < 4 * 100000; q++) { tree[q] = node(); } return; } void add(int i, int l, int r, int x, int v, int typ) { if (l == r) { if (typ == 0) { tree[i] = node(v); } else { tree[i] = node(); } return; } int mid = (l + r) >> 1; if (x <= mid) add(i * 2, l, mid, x, v, typ); else add(i * 2 + 1, mid + 1, r, x, v, typ); tree[i] = merge(tree[i * 2], tree[i * 2 + 1]); return; } long long sum() { return tree[1].sum[2]; } }; int N, a[100000][2]; set<int> heap; segment_tree seg; map<int, int> ind; int main() { fscanf(in, %d , &N); for (int q = 0; q < N; q++) { char qq[22]; int x; fscanf(in, %s , qq); if (qq[0] == s ) { a[q][0] = -1; } else { fscanf(in, %d , &x); if (qq[0] == a ) a[q][0] = 0; else a[q][0] = 1; a[q][1] = x; heap.insert(x); } } int cind = 0; for (set<int>::iterator it = heap.begin(); it != heap.end(); it++) { ind[*it] = cind; cind++; } for (int q = 0; q < N; q++) { if (a[q][0] == -1) { printf( %I64d n , seg.sum()); } else { seg.add(1, 0, cind - 1, ind[a[q][1]], a[q][1], a[q][0]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long n; cin >> n; vector<long long> l(n + 5), r(n + 5); for (long long i = 1; i < n + 1; ++i) cin >> l[i]; for (long long i = 1; i < n + 1; ++i) cin >> r[i]; vector<pair<long long, long long> > v; for (long long i = 1; i < n + 1; ++i) v.push_back({l[i] + r[i], i}); sort(v.begin(), v.end()); long long x = n, ans[n + 5]; for (long long i = 0; i < (long long)v.size(); ++i) { ans[v[i].second] = x; while (i + 1 < (long long)v.size() && v[i].first == v[i + 1].first) { ++i; ans[v[i].second] = x; } x--; } for (long long i = 1; i < n + 1; ++i) { long long c1 = 0; for (long long j = 1; j < i; ++j) if (ans[i] < ans[j]) ++c1; long long c2 = 0; for (long long j = i + 1; j < n + 1; ++j) if (ans[j] > ans[i]) ++c2; if (c1 == l[i] && c2 == r[i]) continue; cout << NO n ; return 0; } cout << YES n ; for (long long i = 1; i < n + 1; ++i) cout << ans[i] << ; return 0; }
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : xaw2verilog
// / / Filename : DCM1.v
// /___/ /\ Timestamp : 11/15/2016 13:32:30
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle H:/Firmware/font5_base_new/font5_base/font5-firmware/ipcore_dir/DCM1.xaw -st DCM1.v
//Design Name: DCM1
//Device: xc5vlx50t-3ff1136
//
// Module DCM1
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_ADV_INST = 0.030 UI
// Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.152 ns
`timescale 1ns / 1ps
module DCM1(CLKIN_IN,
RST_IN,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
wire [6:0] GND_BUS_7;
wire [15:0] GND_BUS_16;
assign GND_BIT = 0;
assign GND_BUS_7 = 7'b0000000;
assign GND_BUS_16 = 16'b0000000000000000;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(5), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(25.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DCM_AUTOCALIBRATION("TRUE"), .DCM_PERFORMANCE_MODE("MAX_SPEED"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("HIGH"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"),
.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DADDR(GND_BUS_7[6:0]),
.DCLK(GND_BIT),
.DEN(GND_BIT),
.DI(GND_BUS_16[15:0]),
.DWE(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.DO(),
.DRDY(),
.LOCKED(LOCKED_OUT),
.PSDONE());
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const double eps = 1e-8; const int maxn = 1e6 + 5; const int maxm = 3e4 + 5; const long long mod = 1e9 + 7; const long long inf = 0x3f3f3f3f; const int _inf = -1e9 + 7; inline int scan() { int m = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) m = m * 10 + c - 0 , c = getchar(); return m; } int N, Q, S, M, K; int num[200]; int dp[200][30000]; int main() { cin >> N >> K >> S; for (int i = 1; i <= N; i++) { scanf( %d , num + i); } memset(dp, inf, sizeof dp); dp[0][0] = 0; for (int i = 1; i <= N; i++) { for (int j = i - 1; j >= 0; j--) { for (int k = i * j; k >= 0; k--) { dp[j + 1][k + i - j - 1] = min(dp[j + 1][k + i - j - 1], dp[j][k] + num[i]); } } } int ans = inf; for (int i = 0; i <= min(S, N * N); i++) ans = min(ans, dp[K][i]); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[404040]; inline void solve() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , a + i); int N = 0; for (int i = 1, j = 1; i <= n; i = j) { for (; j <= n && a[i] == a[j]; j++) ; a[++N] = j - i; } int s2 = 0, i2 = 2; for (; i2 <= N && s2 <= a[1]; i2++) s2 += a[i2]; i2--; int sum = a[1] + s2; int s3 = 0, i3 = i2 + 1; for (; i3 <= N && (sum + a[i3]) * 2 <= n; i3++) sum += a[i3], s3 += a[i3]; i3--; if (a[1] < s3) printf( %d %d %d n , a[1], s2, s3); else puts( 0 0 0 ); } int main() { int t; scanf( %d , &t); while (t--) solve(); }
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580wn59.v
//
// Programmable interrupt controller k580wn59 design file of Bashkiria-2M replica.
//
// Warning: Interrupt level shift not supported.
module k580wn59(
input clk, input reset, input addr, input we_n,
input[7:0] idata, output reg[7:0] odata,
output intr, input inta_n, input[7:0] irq);
reg[1:0] state;
reg[7:0] irqmask;
reg[7:0] smask;
reg[7:0] serviced;
reg[2:0] addr0;
reg[7:0] addr1;
reg init;
reg addrfmt;
reg exinta_n;
wire[7:0] r = irq & ~(irqmask | smask);
assign intr = |r;
reg[2:0] x;
always @(*)
casex (r)
8'bxxxxxxx1: x = 3'b000;
8'bxxxxxx10: x = 3'b001;
8'bxxxxx100: x = 3'b010;
8'bxxxx1000: x = 3'b011;
8'bxxx10000: x = 3'b100;
8'bxx100000: x = 3'b101;
8'bx1000000: x = 3'b110;
default: x = 3'b111;
endcase
always @(*)
casex ({inta_n,state})
3'b000: odata = 8'hCD;
3'bx01: odata = addrfmt ? {addr0,x,2'b00} : {addr0[2:1],x,3'b000};
3'bx1x: odata = addr1;
3'b100: odata = addr ? irqmask : irq;
endcase
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 0; init <= 0; irqmask <= 8'hFF; smask <= 8'hFF; serviced <= 0; exinta_n <= 1'b1;
end else begin
exinta_n <= inta_n;
smask <= smask & (irq|serviced);
case (state)
2'b00: begin
if (~we_n) begin
init <= 0;
casex ({addr,idata[4:3]})
3'b000:
case (idata[7:5])
3'b001: serviced <= 0;
3'b011: serviced[idata[2:0]] <= 0;
endcase
3'b01x: begin init <= 1'b1; addr0 <= idata[7:5]; addrfmt <= idata[2]; end
3'b1xx: if (init) addr1 <= idata; else irqmask <= idata;
endcase
end
if (inta_n&~exinta_n) state <= 2'b01;
end
2'b01: begin
if (inta_n&~exinta_n) state <= 2'b10;
end
2'b10: begin
if (inta_n&~exinta_n) begin
state <= 2'b00;
smask[x] <= 1'b1;
serviced[x] <= 1'b1;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); vector<long long int> v; long long int n, i; cin >> n; if (n == 1) { cout << 1; return 0; } for (long long int i = 1; i * i <= n; ++i) { if (n % i == 0) { if (i * i == n) v.push_back(i); else { v.push_back(i); v.push_back(n / i); } } } sort(v.begin(), v.end()); if (v.size() == 2) cout << n; else { long long int flag = 0; if (v.size() == 3) { if (v[1] / v[0] != v[2] / v[1]) { cout << 1; } else cout << v[1]; } else { long long int ans = v[1] / v[0]; for (i = 1; i < v.size() - 1; i++) { if (v[i + 1] != ans * v[i]) { flag = 1; break; } } if (flag == 1) cout << 1; else { cout << v[1]; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; bool f, a[(int)1e6 + 9]; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 1; i < (n == 3 ? 2 : (n >> 1)); i++) { if (n % i == 0) { for (int j = 0; j < i; j++) { if (!a[j]) continue; int k = j + i; f = 1; while (k != j) { if (!a[k]) { f = 0; break; } k = (k + i) % n; } if (f) break; } if (f) break; } } if (f) printf( YES ); else printf( NO ); return 0; }
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : jtag_lm32.v
// Title : JTAG data register for LM32 CPU debug interface
// Version : 6.0.13
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module jtag_lm32 (
input JTCK,
input JTDI,
output JTDO2,
input JSHIFT,
input JUPDATE,
input JRSTN,
input JCE2,
input JTAGREG_ENABLE,
input CONTROL_DATAN,
output REG_UPDATE,
input [7:0] REG_D,
input [2:0] REG_ADDR_D,
output [7:0] REG_Q,
output [2:0] REG_ADDR_Q
);
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire [9:0] tdibus;
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
TYPEA DATA_BIT0 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(JTDI),
.TDO(tdibus[0]),
.DATA_OUT(REG_Q[0]),
.DATA_IN(REG_D[0]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT1 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[0]),
.TDO(tdibus[1]),
.DATA_OUT(REG_Q[1]),
.DATA_IN(REG_D[1]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT2 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[1]),
.TDO(tdibus[2]),
.DATA_OUT(REG_Q[2]),
.DATA_IN(REG_D[2]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT3 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[2]),
.TDO(tdibus[3]),
.DATA_OUT(REG_Q[3]),
.DATA_IN(REG_D[3]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT4 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[3]),
.TDO(tdibus[4]),
.DATA_OUT(REG_Q[4]),
.DATA_IN(REG_D[4]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT5 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[4]),
.TDO(tdibus[5]),
.DATA_OUT(REG_Q[5]),
.DATA_IN(REG_D[5]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT6 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[5]),
.TDO(tdibus[6]),
.DATA_OUT(REG_Q[6]),
.DATA_IN(REG_D[6]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT7 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[6]),
.TDO(tdibus[7]),
.DATA_OUT(REG_Q[7]),
.DATA_IN(REG_D[7]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA ADDR_BIT0 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[7]),
.TDO(tdibus[8]),
.DATA_OUT(REG_ADDR_Q[0]),
.DATA_IN(REG_ADDR_D[0]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA ADDR_BIT1 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[8]),
.TDO(tdibus[9]),
.DATA_OUT(REG_ADDR_Q[1]),
.DATA_IN(REG_ADDR_D[1]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA ADDR_BIT2 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[9]),
.TDO(JTDO2),
.DATA_OUT(REG_ADDR_Q[2]),
.DATA_IN(REG_ADDR_D[2]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
assign clk_enable = JTAGREG_ENABLE & JCE2;
assign captureDr = !JSHIFT & JCE2;
// JCE2 is only active during shift
assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
// bug511
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [7:0] au;
wire [7:0] as;
Test1 test1 (.au);
Test2 test2 (.as);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] result=%x %x\n",$time, au, as);
`endif
if (au != 'h12) $stop;
if (as != 'h02) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module Test1 (output [7:0] au);
wire [7:0] b;
wire signed [3:0] c;
// verilator lint_off WIDTH
assign c=-1; // 'hf
assign b=3; // 'h3
assign au=b+c; // 'h12
// verilator lint_on WIDTH
endmodule
module Test2 (output [7:0] as);
wire signed [7:0] b;
wire signed [3:0] c;
// verilator lint_off WIDTH
assign c=-1; // 'hf
assign b=3; // 'h3
assign as=b+c; // 'h12
// verilator lint_on WIDTH
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module simpleuart (
input clk,
input resetn,
output ser_tx,
input ser_rx,
input [3:0] reg_div_we,
input [31:0] reg_div_di,
output [31:0] reg_div_do,
input reg_dat_we,
input reg_dat_re,
input [31:0] reg_dat_di,
output [31:0] reg_dat_do,
output reg_dat_wait
);
reg [31:0] cfg_divider;
reg [3:0] recv_state;
reg [31:0] recv_divcnt;
reg [7:0] recv_pattern;
reg [7:0] recv_buf_data;
reg recv_buf_valid;
reg [9:0] send_pattern;
reg [3:0] send_bitcnt;
reg [31:0] send_divcnt;
reg send_dummy;
assign reg_div_do = cfg_divider;
assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0;
always @(posedge clk) begin
if (!resetn) begin
cfg_divider <= 1;
end else begin
if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0];
if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8];
if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
end
end
always @(posedge clk) begin
if (!resetn) begin
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
recv_buf_data <= 0;
recv_buf_valid <= 0;
end else begin
recv_divcnt <= recv_divcnt + 1;
if (reg_dat_re)
recv_buf_valid <= 0;
case (recv_state)
0: begin
if (!ser_rx)
recv_state <= 1;
recv_divcnt <= 0;
end
1: begin
if (2*recv_divcnt > cfg_divider) begin
recv_state <= 2;
recv_divcnt <= 0;
end
end
10: begin
if (recv_divcnt > cfg_divider) begin
recv_buf_data <= recv_pattern;
recv_buf_valid <= 1;
recv_state <= 0;
end
end
default: begin
if (recv_divcnt > cfg_divider) begin
recv_pattern <= {ser_rx, recv_pattern[7:1]};
recv_state <= recv_state + 1;
recv_divcnt <= 0;
end
end
endcase
end
end
assign ser_tx = send_pattern[0];
always @(posedge clk) begin
if (reg_div_we)
send_dummy <= 1;
send_divcnt <= send_divcnt + 1;
if (!resetn) begin
send_pattern <= ~0;
send_bitcnt <= 0;
send_divcnt <= 0;
send_dummy <= 1;
end else begin
if (send_dummy && !send_bitcnt) begin
send_pattern <= ~0;
send_bitcnt <= 15;
send_divcnt <= 0;
send_dummy <= 0;
end else
if (reg_dat_we && !send_bitcnt) begin
send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
send_bitcnt <= 10;
send_divcnt <= 0;
end else
if (send_divcnt > cfg_divider && send_bitcnt) begin
send_pattern <= {1'b1, send_pattern[9:1]};
send_bitcnt <= send_bitcnt - 1;
send_divcnt <= 0;
end
end
end
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <>
* updated to include Direct Cache Bus by Charley Picker <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlbrg_datamem #(
parameter depth = 8
) (
input sys_clk,
/* Primary port (read-write) */
input [depth-1:0] a,
input [1:0] we,
input [15:0] di,
output [15:0] dout,
/* Secondary port (read-only) */
input [depth-1:0] a2,
output [15:0] do2
);
reg [7:0] ram0[0:(1 << depth)-1];
reg [7:0] ram1[0:(1 << depth)-1];
wire [7:0] ram0di;
wire [7:0] ram1di;
wire [7:0] ram0do;
wire [7:0] ram1do;
wire [7:0] ram0do2;
wire [7:0] ram1do2;
reg [depth-1:0] a_r;
reg [depth-1:0] a2_r;
always @(posedge sys_clk) begin
a_r <= a;
a2_r <= a2;
end
/*
* Workaround for a strange Xst 11.4 bug with Spartan-6
* We must specify the RAMs in this order, otherwise,
* ram1 "disappears" from the netlist. The typical
* first symptom is a Bitgen DRC failure because of
* dangling I/O pins going to the SDRAM.
* Problem reported to Xilinx.
*/
always @(posedge sys_clk) begin
if(we[1])
ram1[a] <= ram1di;
end
assign ram1do = ram1[a_r];
assign ram1do2 = ram1[a2_r];
always @(posedge sys_clk) begin
if(we[0])
ram0[a] <= ram0di;
end
assign ram0do = ram0[a_r];
assign ram0do2 = ram0[a2_r];
assign ram0di = di[7:0];
assign ram1di = di[15:8];
assign dout = {ram1do, ram0do};
assign do2 = {ram1do2, ram0do2};
endmodule
|
module spiral_0(
i_data,
o_data_36,
o_data_83
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [19:0] i_data;
output signed [19+7:0] o_data_36;
output signed [19+7:0] o_data_83;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire signed [26:0] w1,
w8,
w9,
w64,
w65,
w18,
w83,
w36;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign w1 = i_data;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign w64 = w1 << 6;
assign w65 = w1 + w64;
assign w18 = w9 << 1;
assign w83 = w65 + w18;
assign w36 = w9 << 2;
assign o_data_36=w36;
assign o_data_83=w83;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, maxx; vector<int> v, cnt; map<int, int> ma; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; maxx = min(2, n); v.resize(n + 1); cnt.resize(100001); for (int i = 1; i <= n; i++) { cin >> v[i]; map<int, int>::iterator it; it = ma.find(cnt[v[i]]); if (it != ma.end()) { it->second -= 1; if (it->second == 0) ma.erase(cnt[v[i]]); } cnt[v[i]] += 1; it = ma.find(cnt[v[i]]); if (it == ma.end()) ma.insert(pair<int, int>(cnt[v[i]], 1)); else it->second += 1; int chk = 1; if (ma.size() == 1) { chk = 0; pair<int, int> ff; ff = *ma.begin(); if (ff.first == 1) chk = 1; else if (ff.second == 1) chk = 1; } if (ma.size() > 2) chk = 0; if (ma.size() == 2) { chk = 0; pair<int, int> ff, ss; it = ma.begin(); ff = *it; it++; ss = *it; if ((ff.first == 1 && ff.second == 1) || (ss.first == ff.first + 1 && ss.second == 1)) chk = 1; } if (chk == 1) maxx = max(maxx, i); } cout << maxx; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int arr[1005]; int res[1005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; ++i) cin >> arr[i]; sort(arr, arr + n); int ini = 0, fin = n - 1, idx = 0; while (ini <= fin) { res[idx] = arr[ini++]; res[idx + 1] = arr[fin--]; idx += 2; } for (int i = 0; i < n; ++i) cout << res[i] << ; cout << n ; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_chip_tb
//
// Generated
// by: wig
// on: Tue Apr 18 07:50:26 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_chip_tb.v,v 1.1 2006/04/19 07:33:12 wig Exp $
// $Date: 2006/04/19 07:33:12 $
// $Log: avfb_chip_tb.v,v $
// Revision 1.1 2006/04/19 07:33:12 wig
// Updated/added testcase for 20060404c issue. Needs more work!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.82 2006/04/13 13:31:52 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_chip_tb
//
// No user `defines in this module
module avfb_chip_tb
//
// Generated module avfb_chip_tb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for dut
avfb_chip dut (
);
// End of Generated Instance Port Map for dut
endmodule
//
// End of Generated Module rtl of avfb_chip_tb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transceiver control
*/
module xcvr_ctrl (
input wire reconfig_clk,
input wire reconfig_rst,
input wire pll_locked_in,
output wire [18:0] xcvr_reconfig_address,
output wire xcvr_reconfig_read,
output wire xcvr_reconfig_write,
input wire [7:0] xcvr_reconfig_readdata,
output wire [7:0] xcvr_reconfig_writedata,
input wire xcvr_reconfig_waitrequest
);
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_LOAD_PMA_1 = 4'd1,
STATE_LOAD_PMA_2 = 4'd2,
STATE_INIT_ADAPT_1 = 4'd3,
STATE_INIT_ADAPT_2 = 4'd4,
STATE_INIT_ADAPT_3 = 4'd5,
STATE_INIT_ADAPT_4 = 4'd6,
STATE_CONT_ADAPT_1 = 4'd7,
STATE_CONT_ADAPT_2 = 4'd8,
STATE_CONT_ADAPT_3 = 4'd9,
STATE_CONT_ADAPT_4 = 4'd10,
STATE_DONE = 4'd11;
reg [3:0] state_reg = STATE_IDLE, state_next;
reg [18:0] xcvr_reconfig_address_reg = 19'd0, xcvr_reconfig_address_next;
reg xcvr_reconfig_read_reg = 1'b0, xcvr_reconfig_read_next;
reg xcvr_reconfig_write_reg = 1'b0, xcvr_reconfig_write_next;
reg [7:0] xcvr_reconfig_writedata_reg = 8'd0, xcvr_reconfig_writedata_next;
reg [7:0] read_data_reg = 8'd0, read_data_next;
reg read_data_valid_reg = 1'b0, read_data_valid_next;
reg [15:0] delay_count_reg = 0, delay_count_next;
reg pll_locked_sync_1_reg = 0;
reg pll_locked_sync_2_reg = 0;
reg pll_locked_sync_3_reg = 0;
assign xcvr_reconfig_address = xcvr_reconfig_address_reg;
assign xcvr_reconfig_read = xcvr_reconfig_read_reg;
assign xcvr_reconfig_write = xcvr_reconfig_write_reg;
assign xcvr_reconfig_writedata = xcvr_reconfig_writedata_reg;
always @(posedge reconfig_clk) begin
pll_locked_sync_1_reg <= pll_locked_in;
pll_locked_sync_2_reg <= pll_locked_sync_1_reg;
pll_locked_sync_3_reg <= pll_locked_sync_2_reg;
end
always @* begin
state_next = STATE_IDLE;
xcvr_reconfig_address_next = xcvr_reconfig_address_reg;
xcvr_reconfig_read_next = 1'b0;
xcvr_reconfig_write_next = 1'b0;
xcvr_reconfig_writedata_next = xcvr_reconfig_writedata_reg;
read_data_next = read_data_reg;
read_data_valid_next = read_data_valid_reg;
delay_count_next = delay_count_reg;
if (xcvr_reconfig_read_reg || xcvr_reconfig_write_reg) begin
// operation in progress
if (xcvr_reconfig_waitrequest) begin
// wait state, hold command
xcvr_reconfig_read_next = xcvr_reconfig_read_reg;
xcvr_reconfig_write_next = xcvr_reconfig_write_reg;
end else begin
// release command
xcvr_reconfig_read_next = 1'b0;
xcvr_reconfig_write_next = 1'b0;
if (xcvr_reconfig_read_reg) begin
// latch read data
read_data_next = xcvr_reconfig_readdata;
read_data_valid_next = 1'b1;
end
end
state_next = state_reg;
end else if (delay_count_reg != 0) begin
// stall for delay
delay_count_next = delay_count_reg - 1;
state_next = state_reg;
end else begin
read_data_valid_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// wait for PLL to lock
if (pll_locked_sync_3_reg) begin
delay_count_next = 16'hffff;
state_next = STATE_LOAD_PMA_1;
end else begin
state_next = STATE_IDLE;
end
end
STATE_LOAD_PMA_1: begin
// load PMA config
xcvr_reconfig_address_next = 19'h40143;
xcvr_reconfig_writedata_next = 8'h80;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_LOAD_PMA_2;
end
STATE_LOAD_PMA_2: begin
// check status
if (read_data_valid_reg && read_data_reg[0]) begin
// start initial adaptation
xcvr_reconfig_address_next = 19'h200;
xcvr_reconfig_writedata_next = 8'hD2;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_INIT_ADAPT_1;
end else begin
// read status
xcvr_reconfig_address_next = 19'h40144;
xcvr_reconfig_read_next = 1'b1;
state_next = STATE_LOAD_PMA_2;
end
end
STATE_INIT_ADAPT_1: begin
// start initial adaptation
xcvr_reconfig_address_next = 19'h201;
xcvr_reconfig_writedata_next = 8'h02;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_INIT_ADAPT_2;
end
STATE_INIT_ADAPT_2: begin
// start initial adaptation
xcvr_reconfig_address_next = 19'h202;
xcvr_reconfig_writedata_next = 8'h01;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_INIT_ADAPT_3;
end
STATE_INIT_ADAPT_3: begin
// start initial adaptation
xcvr_reconfig_address_next = 19'h203;
xcvr_reconfig_writedata_next = 8'h96;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_INIT_ADAPT_4;
end
STATE_INIT_ADAPT_4: begin
// check status
if (read_data_valid_reg && read_data_reg == 8'h80) begin
// start continuous adaptation
xcvr_reconfig_address_next = 19'h200;
xcvr_reconfig_writedata_next = 8'hF6;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_CONT_ADAPT_1;
end else begin
// read status
xcvr_reconfig_address_next = 19'h207;
xcvr_reconfig_read_next = 1'b1;
state_next = STATE_INIT_ADAPT_4;
end
end
STATE_CONT_ADAPT_1: begin
// start continuous adaptation
xcvr_reconfig_address_next = 19'h201;
xcvr_reconfig_writedata_next = 8'h01;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_CONT_ADAPT_2;
end
STATE_CONT_ADAPT_2: begin
// start continuous adaptation
xcvr_reconfig_address_next = 19'h202;
xcvr_reconfig_writedata_next = 8'h03;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_CONT_ADAPT_3;
end
STATE_CONT_ADAPT_3: begin
// start continuous adaptation
xcvr_reconfig_address_next = 19'h203;
xcvr_reconfig_writedata_next = 8'h96;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_CONT_ADAPT_4;
end
STATE_CONT_ADAPT_4: begin
// check status
if (read_data_valid_reg && read_data_reg == 8'h80) begin
// done
state_next = STATE_DONE;
end else begin
// read status
xcvr_reconfig_address_next = 19'h207;
xcvr_reconfig_read_next = 1'b1;
state_next = STATE_CONT_ADAPT_4;
end
end
STATE_DONE: begin
// done with operation
state_next = STATE_DONE;
end
endcase
end
if (!pll_locked_sync_3_reg) begin
// go back to idle if PLL is unlocked
state_next = STATE_IDLE;
end
end
always @(posedge reconfig_clk) begin
state_reg <= state_next;
xcvr_reconfig_address_reg <= xcvr_reconfig_address_next;
xcvr_reconfig_read_reg <= xcvr_reconfig_read_next;
xcvr_reconfig_write_reg <= xcvr_reconfig_write_next;
xcvr_reconfig_writedata_reg <= xcvr_reconfig_writedata_next;
read_data_reg <= read_data_next;
read_data_valid_reg <= read_data_valid_next;
delay_count_reg <= delay_count_next;
if (reconfig_rst) begin
state_reg <= STATE_IDLE;
xcvr_reconfig_read_reg <= 1'b0;
xcvr_reconfig_write_reg <= 1'b0;
read_data_valid_reg <= 1'b0;
delay_count_reg <= 0;
end
end
endmodule
`resetall
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: scdata_rep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module scdata_rep(/*AUTOARG*/
// Outputs
sctag_scdata_col_offset_c2_buf, sctag_scdata_fb_hit_c3_buf,
sctag_scdata_fbrd_c3_buf, sctag_scdata_rd_wr_c2_buf,
sctag_scdata_set_c2_buf, sctag_scdata_stdecc_c2_buf,
sctag_scdata_way_sel_c2_buf, sctag_scdata_word_en_c2_buf,
scdata_sctag_decc_c6,
// Inputs
sctag_scdata_col_offset_c2, sctag_scdata_fb_hit_c3,
sctag_scdata_fbrd_c3, sctag_scdata_rd_wr_c2, sctag_scdata_set_c2,
sctag_scdata_stdecc_c2, sctag_scdata_way_sel_c2,
sctag_scdata_word_en_c2, scdata_sctag_decc_c6_ctr
);
input [3:0] sctag_scdata_col_offset_c2;
input sctag_scdata_fb_hit_c3;
input sctag_scdata_fbrd_c3;
input sctag_scdata_rd_wr_c2;
input [9:0] sctag_scdata_set_c2;
input [77:0] sctag_scdata_stdecc_c2;
input [11:0] sctag_scdata_way_sel_c2;
input [15:0] sctag_scdata_word_en_c2;
input [155:0] scdata_sctag_decc_c6_ctr;
output [3:0] sctag_scdata_col_offset_c2_buf;
output sctag_scdata_fb_hit_c3_buf;
output sctag_scdata_fbrd_c3_buf;
output sctag_scdata_rd_wr_c2_buf;
output [9:0] sctag_scdata_set_c2_buf;
output [77:0] sctag_scdata_stdecc_c2_buf;
output [11:0] sctag_scdata_way_sel_c2_buf;
output [15:0] sctag_scdata_word_en_c2_buf;
output [155:0] scdata_sctag_decc_c6;
assign sctag_scdata_col_offset_c2_buf = sctag_scdata_col_offset_c2;
assign sctag_scdata_fb_hit_c3_buf = sctag_scdata_fb_hit_c3;
assign sctag_scdata_fbrd_c3_buf = sctag_scdata_fbrd_c3;
assign sctag_scdata_rd_wr_c2_buf = sctag_scdata_rd_wr_c2;
assign sctag_scdata_set_c2_buf = sctag_scdata_set_c2;
assign sctag_scdata_stdecc_c2_buf = sctag_scdata_stdecc_c2;
assign sctag_scdata_way_sel_c2_buf = sctag_scdata_way_sel_c2;
assign sctag_scdata_word_en_c2_buf = sctag_scdata_word_en_c2;
assign scdata_sctag_decc_c6 = scdata_sctag_decc_c6_ctr;
endmodule // scdata_rep
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update
);
wire w_pcie_legacy_irq_set;
wire w_pcie_msi_irq_set;
wire [2:0] w_pcie_irq_vector;
wire w_pcie_legacy_irq_clear;
wire w_pcie_irq_done;
pcie_irq_gen
pcie_irq_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
nvme_irq_handler
nvme_irq_handler_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the communication channel
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
/*
`include "viterbidec.v"
`include "cencoder.v"
`include "noisegen.v"
`include "xor2.v"
`include "pipe.v"
`include "pipe2.v"
*/
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
// ============================================================
module tb_communication_channel();
/**
* Description of module to model a communication channel
*
* This includes 3 stages in the communications channel
* @stage 1: Data from the transmitter (TX) is encoded.
* @stage 2: Data is "transmitted" across the communication
* channel, and gets corrupted with noise.
* Noise in the communication channel is modeled
* by pseudo-random noise that corrupts some of
* the data bits
* @stage 3: Data is received at the receiver (RX), and is
* subsequently decoded.
*/
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the communication channel
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// ============================================================
// Declare "wire" signals: outputs from the DUT
// Outputs from the communication channel
wire d; // Output data signal
wire [1:0] c; // Encoded data
wire [1:0] cx; // Corrupted encoded data
wire b; // Original data
// -----------------------------------------------------------
// Encoded data output from the convolutional encoder
wire [1:0] r_c;
//wire [255:0] rf;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// ------------------------------------------------------------
// Inputs to the communication channel
//reg [255:0] r; // Original data: 256 stream of bits
reg r[0:255]; // Original data: 256 stream of bits
reg rr;
/**
* Randomly generated number to determine if data bit should
* be corrupted
*/
reg [7:0] e;
reg clock; // Clock input to all flip-flops
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 1st stage of the communication
* channel
*/
// Original data input & input to the convolutional encoder
reg r_b;
// Encoded data output from the convolutional encoder
// reg [1:0] r_c;
/**
* Propagated randomly generated number to determine if data
* bit should be corrupted - propagated value from the input
* to the communications channel
*/
reg [7:0] r_e;
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 2nd stage of the communication
* channel
*/
// Propagated values of the encoded data; also, input to XOR gate
reg [1:0] rr_c;
/**
* Further propagated randomly generated number to determine
* if data bit should be corrupted - propagated value from the
* input to the communications channel
*/
reg [7:0] r_e1;
/**
* Randomly generated error that determines the corruption of
* the data bits
*
* Random number will corrupt the encoded data bits based on
* the XOR operator - invert the bits of the encoded data if
* they are different from the random error bits
*
* Also, input to XOR gate to generated corrupted encoded bits
*/
wire [1:0] r_e2;
/**
* Corrupted encoded data bits - model corruption of data during
* transmission of the data in the communications channel
*/
wire [1:0] r_cx;
// Propagated original data input
reg r_b1;
/** ########################################################
#
# IMPORTANT!!!: MODIFY THE error_level HERE!!!
#
########################################################
***
*
* Error level that will be used to generate noise that will
* be used to corrupt encoded data bits
*
* Randomly generated error bits will be compared with this
* error level
*/
reg [7:0] error_level;
// ------------------------------------------------------------
// Inputs to the 3rd stage of the communication channel
// Further propagated values of the encoded data
reg [1:0] rr_c1;
// Propagated values of the corrupted encoded data
reg [1:0] r_cx1;
// Propagated original data input
reg r_b2;
// Reset signal for the flip-flops and registers
reg rset;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 9'd256;
// ============================================================
// Declare and instantiate modules for the communication channel
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
d,r_cx1,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,r_b,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the noise generator so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "ng"
*/
noise_generator ng (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_e1,r_e2,error_level);
// ------------------------------------------------------------
/**
* Instantiate an instance of the 2-bit 2-input XOR gate so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor22"
*/
xor2_2bit xor22 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c,r_e2,r_cx);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_c"
*/
pipeline_buffer_2bit pipe_c (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c1,c,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_cx"
*/
pipeline_buffer_2bit pipe_cx (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_cx1,cx,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_b"
*/
pipeline_buffer pipe_b (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b2,b,clock,rset);
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
// Period = 10 clock cycles
end
// ============================================================
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clock)
begin
if(rset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=rr;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 2nd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c<=0;
r_e1<=0;
r_b1<=0;
end
else
begin
rr_c<=r_c;
r_e1<=r_e;
r_b1<=r_b;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 3rd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c1<=0;
r_cx1<=0;
r_b2<=0;
end
else
begin
rr_c1<=rr_c;
r_cx1<=r_cx;
r_b2<=r_b1;
end
end
// ------------------------------------------------------------
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
error_level=8'd5;
rset=1;
// @t=20,
#20
rset=0;
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/// $readmemb("testfile.bit",rf);
/**
* IMPORTANT NOTE:
* Start to process inputs from the input file after
* 30 clock cycles
*/
for(count=0;count<size_of_input;count=count+1)
begin
#10
$display("Next");
e=$random;
rr=r[count];
if(rr_c != r_cx)
begin
$display($time,"rr_c NOT EQUAL to r_cx");
end
if(count==150)
begin
rset=1;
end
else if(count==151)
begin
rset=0;
end
end
// Problem with d and error_level
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_PP_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVGND_PP_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_BLACKBOX_V
`define SKY130_FD_SC_LS__A31OI_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31oi (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, k, op; string tes; int main() { cin >> n >> k >> ws >> tes; op = 0; for (int i = 1; i < n; i++) if (tes.substr(0, i) == tes.substr(n - i, i)) op = i; cout << tes; tes = tes.substr(op, tes.length()); for (int i = 1; i < k; i++) cout << tes; cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; using DO = double; using LL = long long; using VI = vector<LL>; const int N = 5e5 + 10; int head[N], nxt[N << 1], to[N << 1]; LL wei[N << 1]; int E; void init(int n) { for (int i = 1; i <= n; i++) { head[i] = -1; } E = 0; } void add(int u, int v, int w) { nxt[E] = head[u]; to[E] = v; wei[E] = w; head[u] = E++; nxt[E] = head[v]; to[E] = u; wei[E] = w; head[v] = E++; } LL dp[N][2]; int n, k; void dfs(int u, int fa = 0) { dp[u][0] = dp[u][1] = 0; VI vec; for (int e = head[u], v; ~e; e = nxt[e]) { v = to[e]; if (v == fa) continue; dfs(v, u); dp[u][0] += dp[v][0]; dp[u][1] += dp[v][0]; if (dp[v][0] < dp[v][1] + wei[e]) { vec.push_back(dp[v][1] + wei[e] - dp[v][0]); } } sort(vec.begin(), vec.end()); reverse(vec.begin(), vec.end()); for (int i = 0; i < min((int)vec.size(), k); i++) { dp[u][0] += vec[i]; } for (int i = 0; i < min((int)vec.size(), k - 1); i++) { dp[u][1] += vec[i]; } } int main() { int T; scanf( %d , &T); while (T--) { scanf( %d %d , &n, &k); init(n); for (int i = 1, u, v, w; i < n; i++) { scanf( %d %d %d , &u, &v, &w); add(u, v, w); } dfs(1); printf( %I64d n , max(dp[1][0], dp[1][1])); } return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void solve() { long long w, h; cin >> w >> h; int l1; cin >> l1; vector<long long> row1(l1); for (int i = 0; i < l1; i++) { cin >> row1[i]; } int l2; cin >> l2; vector<long long> row2(l2); for (int i = 0; i < l2; i++) { cin >> row2[i]; } sort(row1.begin(), row1.end()); sort(row2.begin(), row2.end()); long long gap = max(row1[l1 - 1] - row1[0], row2[l2 - 1] - row2[0]); int h1; cin >> h1; vector<long long> col1(h1); for (int i = 0; i < h1; i++) { cin >> col1[i]; } int h2; cin >> h2; vector<long long> col2(h2); for (int i = 0; i < h2; i++) { cin >> col2[i]; } sort(col1.begin(), col1.end()); sort(col2.begin(), col2.end()); long long gap2 = max(col1[h1 - 1] - col1[0], col2[h2 - 1] - col2[0]); long long area = max(h * gap, w * gap2); cout << area << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int t = 1; cin >> t; while (t--) solve(); return 0; }
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