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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O31AI_FUNCTIONAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const double PI = 2.0 * acos(0.0); const double EPS = 1e-6; int a[455]; int b[455]; vector<int> G[455]; int boss[455]; void init() { for (int i = 1; i < 455; i++) boss[i] = i; } int find_boss(int x) { return boss[x] = (boss[x] == x ? x : find_boss(boss[x])); } bool unite(int x, int y) { int bx = find_boss(x); int by = find_boss(y); if (bx == by) return false; boss[bx] = by; return true; } vector<pair<pair<int, int>, int> > res; int pour(int from, int to, int d) { int flow = min(d, max(a[to] - b[to], 0)); a[to] -= flow; int pos = ((int)(res).size()); for (int i = 0; flow < d && i < ((int)(G[to]).size()); i++) { int v = G[to][i]; if (v == from) continue; flow += pour(to, v, d - flow); } if (from != -1) { int po = min(a[to], flow); if (po > 0) res.insert(res.begin() + pos, make_pair(make_pair(to, from), po)); if (po < flow) res.push_back(make_pair(make_pair(to, from), flow - po)); } return flow; } int main() { int n, v, e; scanf( %d %d %d , &n, &v, &e); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= n; i++) scanf( %d , b + i); init(); while (e--) { int x, y; scanf( %d %d , &x, &y); if (unite(x, y)) { G[x].push_back(y); G[y].push_back(x); } } for (int i = 1; i <= n; i++) if (a[i] < b[i]) a[i] += pour(-1, i, b[i] - a[i]); for (int i = 1; i <= n; i++) if (a[i] != b[i]) return puts( NO ), 0; printf( %d n , ((int)(res).size())); for (__typeof((res).begin()) itr = (res).begin(); itr != (res).end(); itr++) printf( %d %d %d n , itr->first.first, itr->first.second, itr->second); return 0; }
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: RF writeback mux
Choose between ALU and LSU input.
Copyright (C) 2012 Authors
Author(s): Julius Baxter <>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_wb_mux_cappuccino
#(
parameter OPTION_OPERAND_WIDTH = 32
)
(
input clk,
input rst,
input [OPTION_OPERAND_WIDTH-1:0] alu_result_i,
input [OPTION_OPERAND_WIDTH-1:0] lsu_result_i,
input [OPTION_OPERAND_WIDTH-1:0] mul_result_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_i,
output [OPTION_OPERAND_WIDTH-1:0] rf_result_o,
input op_mul_i,
input op_lsu_load_i,
input op_mfspr_i
);
reg [OPTION_OPERAND_WIDTH-1:0] rf_result;
reg wb_op_mul;
assign rf_result_o = wb_op_mul ? mul_result_i : rf_result;
always @(posedge clk)
if (op_mfspr_i)
rf_result <= spr_i;
else if (op_lsu_load_i)
rf_result <= lsu_result_i;
else
rf_result <= alu_result_i;
always @(posedge clk)
wb_op_mul <= op_mul_i;
endmodule // mor1kx_wb_mux_cappuccino
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD1_TB_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD1_TB_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv5sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__clkdlyinv5sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD1_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_FUNCTIONAL_V
`define SKY130_FD_SC_LS__HA_FUNCTIONAL_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__ha (
COUT,
SUM ,
A ,
B
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
// Local signals
wire and0_out_COUT;
wire xor0_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const long long M = 1e9 + 7; const double pi = acos(-1); long long dp[1000006]; int main() { long long n; cin >> n; long long a[n + 1]; memset(dp, 0, sizeof(dp)); dp[0] = 1; for (long long i = 1; i <= n; i++) { cin >> a[i]; vector<long long> v; for (long long j = 1; j * j <= a[i]; j++) { if (a[i] % j == 0) { if (a[i] / j == j) { v.push_back(j); } else { v.push_back(j); v.push_back(a[i] / j); } } } sort(v.begin(), v.end(), greater<long long>()); for (long long j = 0; j < v.size(); j++) { dp[v[j]] += dp[v[j] - 1]; dp[v[j]] %= M; } } long long ans = 0; for (long long i = 1; i <= n; i++) { ans += dp[i]; ans %= M; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int OO = (int)2e9 + 5; const int MOD = (int)1e9 + 7; const long double Pi = 3.141592653589793238; const int N = (int)2e5 + 5; long long qqaGJJ[N], ss[2][N], vRI[2][N], n, uVyh = 0; int main() { cin >> n; for (int i = (int)(1); i <= (int)(n); i++) cin >> qqaGJJ[i]; reverse(qqaGJJ + 1, qqaGJJ + n + 1); for (int i = (int)(1); i <= (int)(n); i++) { if (i == 1) { ss[0][i] = ss[1][0] = 0; vRI[0][i] = vRI[1][i] = 0; } else { for (int k = (int)(0); k <= (int)(1); k++) { ss[k][i] = ss[k][i - 1] + abs(qqaGJJ[i] - qqaGJJ[i - 1]) * (((i + k) % 2) ? 1 : -1); vRI[k][i] = min(vRI[k][i - 1], ss[k][i]); } } } uVyh = ss[1][2]; for (int i = (int)(2); i <= (int)(n); i++) { uVyh = max(uVyh, ss[(i + 1) % 2][i] - vRI[(i + 1) % 2][i - 1]); } cout << uVyh; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; if (n % 2 == 0) { cout << n / 2 << n ; } else { cout << int(n / 2) + 1 << n ; } } }
|
#include <bits/stdc++.h> using namespace std; void DFS(int s); vector<int> v[60]; int d = 0; int c[200]; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i <= 50; i++) v[i].clear(); memset(c, 0, sizeof(c)); for (int i = 1; i <= m; i++) { int u, vv; scanf( %d %d , &u, &vv); v[u].push_back(vv); v[vv].push_back(u); } int mx = 0; for (int i = 1; i <= n; i++) { if (c[i] == 0) { d = 0; DFS(i); mx = mx + d - 1; } } printf( %I64d n , (long long)pow(2, mx)); return 0; } void DFS(int s) { d++; c[s] = 1; int sz = v[s].size(); for (int i = 0; i < sz; i++) { int x = v[s][i]; if (c[x] == 0) { DFS(x); } } }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_det
(
input clk,
input rstn,
input [128:0] data_in,
output [31:0] det_fp
);
wire [31:0] m0_s_fp;
wire [31:0] m1_s_fp;
reg [2:0] sub_pipe;
always @(posedge clk, negedge rstn)
if(!rstn) sub_pipe <= 3'b000;
else sub_pipe <= {sub_pipe[1:0], data_in[128]};
flt_mult u0_flt_mult(clk, rstn, data_in[127:96], data_in[95:64], m0_s_fp);
flt_mult u1_flt_mult(clk, rstn, data_in[63:32], data_in[31:0], m1_s_fp);
flt_add_sub u4_flt_add_sub(clk, sub_pipe[2], m0_s_fp, m1_s_fp, det_fp);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[102]; int main() { int n, i, l, r, j; char name[100009]; cin >> n; scanf( %s , name); l = 0; r = 9; for (i = 0; i < n; i++) { if (name[i] == L ) for (j = 0; j < 10; j++) if (a[j] == 0) { a[j] = 1; break; } if (name[i] == R ) for (j = 9; j >= 0; j--) if (a[j] == 0) { a[j] = 1; break; } if (name[i] >= 0 && name[i] <= 9 ) a[name[i] - 0 ] = 0; } for (i = 0; i < 10; i++) printf( %d , a[i]); cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 1000000007; const int MM = 998244353; const long double PI = acos(-1); const long long INF = 2e18; template <typename T, typename T1> void amax(T &a, T1 b) { if (b > a) a = b; } template <typename T, typename T1> void amin(T &a, T1 b) { if (b < a) a = b; } long long power(long long b, long long e) { if (e == 0) return 1; if (e & 1) return b * power(b * b, e / 2); return power(b * b, e / 2); } long long power(long long b, long long e, long long m) { if (e == 0) return 1; if (e & 1) return b * power(b * b % m, e / 2, m) % m; return power(b * b % m, e / 2, m); } long long modinv(long long a, long long m) { return power(a, m - 2, m); } int TLE_TERROR() { long long n, ans = 0; cin >> n; long long a[n], c[n + 1]; memset(c, 0, sizeof(c)); for (long long i = 0; i < n; i++) { cin >> a[i]; ans ^= a[i]; } for (long long i = 2; i <= n; i++) { long long z = n / i; c[i - 1] += z; z *= i; long long zz = n - z; c[zz]++; } for (long long i = n - 1; i >= 0; i--) c[i] += c[i + 1]; for (long long i = 1; i <= n; i++) { if (c[i] % 2 != 0) ans ^= i; } cout << ans; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int TESTS = 1; while (TESTS--) TLE_TERROR(); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct vt { int p; int a; int b; }; int main() { int n, index; cin >> n; int a[n + 5], b[200005]; for (int i = 1; i < 200005; i++) { b[i] = 0; } int maxd = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; b[a[i]]++; } for (int i = n; i >= 1; i--) { if (maxd < b[a[i]]) { maxd = b[a[i]]; index = i; } } if (maxd == n) cout << 0 ; else if (maxd == 1) { int u = 0; vt x[n + 5]; for (int i = 2; i <= n; i++) { if (a[i] == a[i - 1]) continue; if (a[i] > a[i - 1]) { x[u].p = 2; x[u].a = i; x[u].b = i - 1; u++; a[i] = a[i - 1]; } else if (a[i] < a[i - 1]) { x[u].p = 1; x[u].a = i; x[u].b = i - 1; u++; a[i] = a[i - 1]; } } cout << u << endl; for (int i = 0; i < u; i++) { cout << x[i].p << << x[i].a << << x[i].b << endl; } } else { int u = 0; vt x[n + 5]; for (int i = index - 1; i >= 1; i--) { if (a[i] == a[i + 1]) continue; if (a[i] > a[i + 1]) { x[u].p = 2; x[u].a = i; x[u].b = i + 1; u++; a[i] = a[i + 1]; } else if (a[i] < a[i + 1]) { x[u].p = 1; x[u].a = i; x[u].b = i + 1; u++; a[i] = a[i + 1]; } } for (int i = index + 1; i <= n; i++) { if (a[i] == a[i - 1]) continue; if (a[i] > a[i - 1]) { x[u].p = 2; x[u].a = i; x[u].b = i - 1; u++; a[i] = a[i - 1]; } else if (a[i] < a[i - 1]) { x[u].p = 1; x[u].a = i; x[u].b = i - 1; u++; a[i] = a[i - 1]; } } cout << u << endl; for (int i = 0; i < u; i++) { cout << x[i].p << << x[i].a << << x[i].b << endl; } } }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:02:45 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_clk_wiz_0_0 -prefix
// system_clk_wiz_0_0_ system_clk_wiz_0_0_stub.v
// Design : system_clk_wiz_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_clk_wiz_0_0(clk_out1, resetn, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,resetn,locked,clk_in1" */;
output clk_out1;
input resetn;
output locked;
input clk_in1;
endmodule
|
module sdram_fsm (
input wr_en,
input rd_en,
input [31:0] data,
input [31:0] addr,
output data
// SDRAM control signals
output reg [ 1:0] sdClkE,
output reg sdWeN,
output reg sdCasN,
output reg sdRasN,
output reg sdCsN,
output reg [11:0] sdA,
output reg [ 1:0] sdBa,
output reg [ 3:0] sdDqm,
input [31:0] sdDqIn,
output reg [31:0] sdDqOut,
output reg sdDqOeN
);
parameter IDLE = 0;
parameter PRE_CHARGE = 1;
parameter WAIT_FOR_RP = 2;
parameter AUTO_REFRESH = 3;
parameter LOAD_MODE = 4;
parameter ACTIVE = 5;
parameter RAS_TO_CAS = 6;
parameter READ_INIT = 7;
parameter WRITE_INIT = 8;
parameter CAS_LAT = 9;
parameter READ_DATA = 10;
parameter BURST_TERM = 11;
// controller engine state machine
always @ (posedge sdClk or negedge rstN) begin
if (!rstN) begin
presState <= IDLE;
brstCntr <= 9'd0;
counter <= 4'b0000;
rfshed <= 1'b0;
instrFifoRead <= 1'b0;
//sdClkE <= 2'b11;
sdWeNQ <= 1'b1;
sdCasN <= 1'b1;
sdRasN <= 1'b1;
sdCsN <= 1'b1;
sdA <= 12'd0;
sdBa <= 2'b00;
sdDqm <= 4'b1111;
sdDqOeN <= 1'b1;
accWasWrite <= 1'b0;
writing <= 1'b0;
initialize <= 1'b1;
end
else begin
writing <= 1'b0;
presState <= nextState; // state transition
accWasWrite <= accIsWrite;
rfshed <= 1'b0; // strobes
case (nextState)
IDLE : begin
sdCsN <= 1'b1;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
sdDqm <= 4'b1111;
end
PRE_CHARGE: begin
sdCsN <= 1'b0;
sdRasN <= 1'b0;
sdCasN <= 1'b1;
sdWeNQ <= 1'b0;
sdA[10] <= 1'b1; // all-bank precharge
counter <= {1'b0,rp}; // precharge command period
end
WAIT_FOR_RP: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
sdDqm <= 4'b1111;
sdDqOeN <= 1'b1;
counter <= counter - 1'b1;
end
AUTO_REFRESH: begin
sdCsN <= 1'b0;
sdRasN <= 1'b0;
sdCasN <= 1'b0;
sdWeNQ <= 1'b1;
counter <= rfc; // minimum refresh period
rfshed <= 1'b1;
end
LOAD_MODE: begin
sdCsN <= 1'b0;
sdRasN <= 1'b0;
sdCasN <= 1'b0;
sdWeNQ <= 1'b0;
sdA <= mode0val;
sdBa <= 2'b00;
initialize <= 1'b0;
end
ACTIVE: begin
sdCsN <= 1'b0;
sdRasN <= 1'b0;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
// controlled by : row signal
sdBa <= accAddr[12:11]; // bank
sdA <= accAddr[24:13];
// Note that it is assumed that burst will be all on same row
// rowActive <= accAddr[24:13]; // record active row
counter <= rcd; // active to R/W delay
brstCntr <= 9'd0;
// lastPage <= accAddr[24:11]; // for page hit detection
end
RAS_TO_CAS: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
counter <= counter - 1'b1;
end
READ_INIT: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b0;
sdWeNQ <= 1'b1;
sdDqm <= sdDqm_c;
// Note that it is assumed that burst will be all on same row
// controlled by : col signal
sdBa <= accAddr[12:11]; // bank
sdA[10] <= 1'b0; // auto precharge disabled
sdA[8:0] <= accAddr[10: 2]; // colAddr[8:0]
counter <= {1'b0,cl - 1'b1}; // cas latency
end
WRITE_INIT: begin
writing <= 1'b1;
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b0;
sdWeNQ <= 1'b0;
sdDqm <= sdDqm_c;
// Note that it is assumed that burst will be all on same row
// controlled by : col signal
sdBa <= accAddr[12:11]; // bank
sdA[10] <= 1'b0; // auto precharge disabled
sdA[8:0] <= accAddr[10: 2]; // colAddr[8:0]
sdDqOeN <= 1'b0;
counter <= {1'b0,wr};
end
CAS_LAT: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
counter <= counter - 1'b1;
end
READ_DATA: begin
sdCsN <= 1'b0; // NOP
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
sdDqm <= 4'b0000;
sdA[8:0] <= accAddr[10: 2]; // colAddr[8:0]
brstCntr <= brstCntr + 1'b1;
end
BURST_TERM: begin
sdCsN <= 1'b0;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b0;
sdDqm <= 4'b1111;
end
default: begin
sdCsN <= 1'b1;
sdRasN <= 1'b1;
sdCasN <= 1'b1;
sdWeNQ <= 1'b1;
sdDqm <= 4'b1111;
instrFifoRead <= 1'b0;
end
endcase
end
end
// next state calculation
always @ (*) begin
engRdDataRdy = 1'b0;
case (presState)
IDLE: begin
if(initialize)
nextState = PRECHRG;
else if(wr | rd)
nextState = ACTIVE;
else
nextState = IDLE;
end
PRE_CHARGE: begin
nextState = WAIT_FOR_RP;
end
WAIT_FOR_RP: begin
if (counter != 4'd0) nextState = WAIT_FOR_RP;
else begin
if (initialize)
nextState = AUTO_REFRESH;
else
nextState = IDLE;
end
end
AUTO_REFRESH: begin
if(counter != 4'd0)
nextState = AUTO_REFRESH;
else if(initialize)
nextState = LOAD_MODE;
else
nextState = IDLE;
end
LOAD_MODE: begin
nextState = IDLE;
end
ACTIVE: begin
nextState = RAS_TO_CAS;
end
RAS_TO_CAS: begin
if (counter != 4'd0) nextState = RAS_TO_CAS;
else begin
if (accIsWrite) nextState = WRITE_INIT;
else nextState = READ_INIT;
end
end
READ_INIT: begin
nextState = CAS_LAT;
end
WRITE_INIT: begin
if (accBurstTerm)
nextState = BURST_TERM;
else
nextState = WRITE_DATA;
end
CAS_LAT: begin
if (counter != 4'd0)
nextState = CAS_LAT;
else begin
engRdDataRdy = 1'b1;
nextState = READ_DATA;
end
end
READ_DATA: begin
engRdDataRdy = 1'b1;
if (accBurstTerm)
nextState = BURST_TERM;
else
nextState = READ_DATA;
end
WRITE_DATA: begin
if (accBurstTerm)
nextState = BURST_TERM;
else
nextState = WRITE_DATA;
end
BURST_TERM: begin
engRdDataRdy = 1'b0;
nextState = PRE_CHARGE;
end
default: begin
nextState = IDLE;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
module VGA_ctrl
(
input clk,
input [2:0] d_in,
output [2:0] rgb,
output Hs,
output Vs,
input VGA_en,
// For debug purposes
output[9:0] H_count,
output[9:0] V_count,
output clk_25,
output D_En
);
wire[9:0] H_cnt;
wire[9:0] V_cnt;
wire V_cnt_en;
// reg H_cnt_en = 1;
reg H_sync_next = 0;
reg H_sync_reg = 0;
reg V_sync_next = 0;
reg V_sync_reg = 0;
reg H_DEN_next = 0;
reg H_DEN_reg = 0;
reg V_DEN_next = 0;
reg V_DEN_reg = 0;
reg[9:0] H_disp = 0;
reg[9:0] V_disp = 0;
// Instantiate the module
clock_div clock_div_25 (
.CLKIN_IN(clk),
.CLKDV_OUT(clk_25),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
counter#(.CNT_MAX(800), .DATA_WIDTH(10))
H_counter
(
.clk (clk_25),
.en_in (VGA_en),
.cnt (H_cnt),
.en_out (V_cnt_en)
);
counter#(.CNT_MAX(521), .DATA_WIDTH(10))
V_counter
(
.clk (clk_25),
.en_in (V_cnt_en),
.cnt (V_cnt),
.en_out ()
);
// sync part for H and V sync signals
always @(posedge clk_25) begin
H_sync_reg <= H_sync_next;
V_sync_reg <= V_sync_next;
H_DEN_reg <= H_DEN_next;
V_DEN_reg <= V_DEN_next;
end
// Combinatoric part H sync pulse
always @* begin
if (H_cnt < 95) begin
H_sync_next <= 0;
H_DEN_next <= 0;
end else if ((H_cnt > 142) & (H_cnt < 783)) begin // random values
H_sync_next <= 1;
H_DEN_next <= 1;
end else if (H_cnt == 799) begin
H_sync_next <= 0;
H_DEN_next <= 0;
end else begin
H_sync_next <= 1;
H_DEN_next <= 0;
end
end
// Combinatoric part V sync pulse
always @* begin
if (V_cnt < 2) begin
V_sync_next <= 0;
V_DEN_next <= 0;
end else if ((V_cnt > 30) & (V_cnt < 510)) begin // random values
V_sync_next <= 1;
V_DEN_next <= 1;
end else begin
V_sync_next <= 1;
V_DEN_next <= 0;
end
end
always @* begin
if ((V_DEN_reg) & (H_DEN_reg)) begin
H_disp <= H_cnt - 144;
V_disp <= V_cnt - 31;
end else begin
H_disp <= 0;
V_disp <= 0;
end
end
// Output logic
assign rgb = ((V_DEN_reg) & (H_DEN_reg)) ? d_in : 0;
assign D_En = ((V_DEN_reg) & (H_DEN_reg));
assign Hs = H_sync_reg;
assign Vs = V_sync_reg;
assign H_count = H_disp;
assign V_count = V_disp;
endmodule
|
`timescale 1ns/1ns
//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for data[7:0] , crc[15:0]=1+x^2+x^15+x^16;
//-----------------------------------------------------------------------------
//
// MQ 3/12/2015: minor variable name tweaks, flip bit ordering,
// add testbench, invert output, synchronous reset, etc.
module usb_crc16(
input [7:0] d,
input dv,
output [15:0] crc,
input rst,
input c);
reg [15:0] crc_q, crc_d;
// flip the input and output bit vectors, and invert the output...
wire [7:0] df = { d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7] };
assign crc = { ~crc_q[ 0], ~crc_q[ 1], ~crc_q[ 2], ~crc_q[ 3],
~crc_q[ 4], ~crc_q[ 5], ~crc_q[ 6], ~crc_q[ 7],
~crc_q[ 8], ~crc_q[ 9], ~crc_q[10], ~crc_q[11],
~crc_q[12], ~crc_q[13], ~crc_q[14], ~crc_q[15] };
always @(*) begin
crc_d[0] = crc_q[8] ^ crc_q[9] ^ crc_q[10] ^ crc_q[11] ^ crc_q[12] ^ crc_q[13] ^ crc_q[14] ^ crc_q[15] ^ df[0] ^ df[1] ^ df[2] ^ df[3] ^ df[4] ^ df[5] ^ df[6] ^ df[7];
crc_d[1] = crc_q[9] ^ crc_q[10] ^ crc_q[11] ^ crc_q[12] ^ crc_q[13] ^ crc_q[14] ^ crc_q[15] ^ df[1] ^ df[2] ^ df[3] ^ df[4] ^ df[5] ^ df[6] ^ df[7];
crc_d[2] = crc_q[8] ^ crc_q[9] ^ df[0] ^ df[1];
crc_d[3] = crc_q[9] ^ crc_q[10] ^ df[1] ^ df[2];
crc_d[4] = crc_q[10] ^ crc_q[11] ^ df[2] ^ df[3];
crc_d[5] = crc_q[11] ^ crc_q[12] ^ df[3] ^ df[4];
crc_d[6] = crc_q[12] ^ crc_q[13] ^ df[4] ^ df[5];
crc_d[7] = crc_q[13] ^ crc_q[14] ^ df[5] ^ df[6];
crc_d[8] = crc_q[0] ^ crc_q[14] ^ crc_q[15] ^ df[6] ^ df[7];
crc_d[9] = crc_q[1] ^ crc_q[15] ^ df[7];
crc_d[10] = crc_q[2];
crc_d[11] = crc_q[3];
crc_d[12] = crc_q[4];
crc_d[13] = crc_q[5];
crc_d[14] = crc_q[6];
crc_d[15] = crc_q[7] ^ crc_q[8] ^ crc_q[9] ^ crc_q[10] ^ crc_q[11] ^ crc_q[12] ^ crc_q[13] ^ crc_q[14] ^ crc_q[15] ^ df[0] ^ df[1] ^ df[2] ^ df[3] ^ df[4] ^ df[5] ^ df[6] ^ df[7];
end // always
always @(posedge c) begin
if(rst)
crc_q <= {16{1'b1}};
else
crc_q <= dv ? crc_d : crc_q;
end // always
endmodule // crc
`ifdef TEST_USB_CRC16
module tb();
wire c;
task tick;
begin
wait(c);
wait(~c);
end
endtask
reg [7:0] d;
wire [15:0] crc;
reg dv, rst;
sim_clk #(125) clk_125_r(.clk(c));
usb_crc16 usb_crc16_inst(.*);
initial begin
$dumpfile("crc16.lxt");
$dumpvars();
rst <= 1'b0;
dv <= 1'b0;
#100;
tick();
rst <= 1'b1;
tick();
rst <= 1'b0;
tick();
dv <= 1'b1;
d <= 8'h0;
tick();
d <= 8'h1;
tick();
d <= 8'h2;
tick();
d <= 8'h3;
tick();
dv <= 1'b0;
tick();
tick();
$finish();
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; int a[MAXN], b[MAXN], c[MAXN]; int tb[MAXN]; int d, n; long long x; long long getNextX() { x = (x * 37 + 10007) % 1000000007; return x; } void initAB() { for (int i = 0; i < n; i = i + 1) { a[i] = i + 1; } for (int i = 0; i < n; i = i + 1) { swap(a[i], a[getNextX() % (i + 1)]); } for (int i = 0; i < n; i = i + 1) { if (i < d) b[i] = 1; else b[i] = 0; } for (int i = 0; i < n; i = i + 1) { swap(b[i], b[getNextX() % (i + 1)]); } } struct node { int p, num; bool operator<(const node &t) const { return num > t.num; } }; node nd[MAXN]; int main() { while (cin >> n >> d >> x) { initAB(); int cnt = 10000000; for (int i = 0; i < n; i++) { nd[i].num = a[i]; nd[i].p = i; } sort(nd, nd + n); int l = 0; for (int i = 0; i < n; i++) { if (b[i] == 1) { tb[l++] = i; } } memset(c, -1, sizeof(c)); for (int i = 0; i < n; i++) { int p = nd[i].p; for (int j = 0; j < l && cnt > 0; j++) { if (p + tb[j] < n && c[p + tb[j]] == -1) { c[p + tb[j]] = a[p]; } cnt--; } } for (int i = 0; i < n; i++) { if (c[i] == -1) { c[i] = 0; for (int j = 0; j < l && i - tb[j] >= 0; j++) { c[i] = max(c[i], a[i - tb[j]] * b[tb[j]]); } } printf( %d n , c[i]); } } return 0; }
|
typedef struct packed {
logic [7:0] data;
logic wr_ena;
} mystruct_s;
module submod
(input logic a_port,
input logic [4:0] b_bus,
input mystruct_s single_struct_is_fine,
input mystruct_s [2:0] array_of_struct_is_not,
output logic status);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire status = 1'h0;
// End of automatics
endmodule // submod
module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic status; // From submod0 of submod.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
logic a_port; // To submod0 of submod.v
mystruct_s [2:0] array_of_struct_is_not; // To submod0 of submod.v
logic [4:0] b_bus; // To submod0 of submod.v
mystruct_s single_struct_is_fine; // To submod0 of submod.v
// End of automatics
submod submod0
(/*AUTOINST*/
// Outputs
.status (status),
// Inputs
.a_port (a_port),
.b_bus (b_bus[4:0]),
.single_struct_is_fine (single_struct_is_fine),
.array_of_struct_is_not (array_of_struct_is_not[2:0]));
endmodule // top
// Local Variables:
// verilog-typedef-regexp: "_s$"
// End:
|
`timescale 1ns / 1ps
`include "cache_defines.vh"
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:21:06 03/12/2015
// Design Name: cache
// Module Name: D:/Modelsim Projects/Xilinx/cache_implementation/cacheblock2_tb.v
// Project Name: cache_implementation
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cache
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cacheblock2_tb;
parameter TAG_WIDTH = 4; // width of the tag
parameter DATA_WIDTH = 8; // width of the data
parameter ENTRIES_WIDTH = 16; // # of entries
parameter OPCODE_WIDTH = 2; // width of opcode
parameter LINE_WIDTH = TAG_WIDTH+DATA_WIDTH+OPCODE_WIDTH; // length of the input vector
// Inputs
reg [LINE_WIDTH-1:0]vector_in;
reg clk;
reg enable;
reg [TAG_WIDTH-1:0]tag_count;
reg [DATA_WIDTH-1:0]data_test;
// Outputs
wire [DATA_WIDTH-1:0]data_out;
wire [DATA_WIDTH-1:0]data_out_miss;
wire [TAG_WIDTH-1:0]tag_out_miss;
wire hit_miss_out;
// Instantiate the Unit Under Test (UUT)
cache #(TAG_WIDTH,DATA_WIDTH,ENTRIES_WIDTH) cacheblock2 (
.data_out(data_out),
.data_out_miss(data_out_miss),
.tag_out_miss(tag_out_miss),
.hit_miss_out(hit_miss_out),
.vector_in(vector_in),
.clk(clk),
.enable(enable)
);
initial begin
// Initialize Inputs
// data_in = 0;
clk = 0;
enable = 0;
// Wait 100 ns for global reset to finish
// Fill up cache
tag_count = {TAG_WIDTH{1'b0}};
data_test = {DATA_WIDTH{1'b1}};
repeat(ENTRIES_WIDTH)begin: bench1
#2 vector_in = {`WRITE,tag_count,data_test}; // write to a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 4'b1;
data_test = data_test + 8'b1;
end // end repeat loop
// This loop reads all the data that has been written in the cache previously
tag_count = {TAG_WIDTH{1'b0}};
data_test = {DATA_WIDTH{1'b1}};
repeat(ENTRIES_WIDTH)begin: bench2
#2 vector_in = {`READ,tag_count,data_test}; // read a new tag entry every time
tag_count = tag_count + 1'b1;
data_test = data_test + 1'b1;
end // end repeat loop
#2 vector_in = 14'b10_0110_00010001; // write to a different tag entry
#2 vector_in = 14'b01_0110_00000001; // read the above tag entry
#2 vector_in = 14'b01_0011_00000001; // read the above tag entry
repeat(4)begin: bench3
#2 vector_in = {`READ,1000,data_test}; // read same tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
end // end repeat loop
#2 vector_in = 26'b00_0011_00000001; // flashes entire cache
// reads entire cache to confirm that has been flashed
tag_count = {TAG_WIDTH{1'b0}};
data_test = {DATA_WIDTH{1'b1}};
repeat(ENTRIES_WIDTH)begin: bench4
#2 vector_in = {`READ,tag_count,data_test}; // read a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 1'b1;
data_test = data_test + 1'b1;
end // end repeat loop
// #2 $finish;
end
always begin
#1 clk = ~clk; // Toggle clock every 1 ticks
end
endmodule
|
#include <bits/stdc++.h> inline long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } inline void sub(long long &a, long long b) { a -= b; if (a < 0) a += 1000000007; } inline void add(long long &a, long long b) { a += b; if (a >= 1000000007) a -= 1000000007; } template <typename T> inline T const &MAX(T const &a, T const &b) { return a > b ? a : b; } template <typename T> inline T const &MIN(T const &a, T const &b) { return a < b ? a : b; } inline long long qp(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % 1000000007; a = a * a % 1000000007, b >>= 1; } return ans; } inline long long qp(long long a, long long b, long long c) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % c; a = a * a % c, b >>= 1; } return ans; } using namespace std; const unsigned long long ba = 233; const double eps = 1e-6; const long long INF = 0x3f3f3f3f3f3f3f3f; const int N = 100000 + 10, maxn = 1000000 + 10, inf = 0x3f3f3f3f; long long h[N], a[N]; int cnt, pre[N]; struct sgt { pair<int, int> ma[N << 2]; void update(int pos, pair<int, int> v, int l, int r, int rt) { if (l == r) { ma[rt] = v; return; } int m = (l + r) >> 1; if (pos <= m) update(pos, v, l, m, rt << 1); else update(pos, v, m + 1, r, rt << 1 | 1); ma[rt] = max(ma[rt << 1], ma[rt << 1 | 1]); } pair<int, int> query(int L, int R, int l, int r, int rt) { if (L <= l && r <= R) return ma[rt]; int m = (l + r) >> 1; pair<int, int> ans = make_pair(0, 0); if (L <= m) ans = max(ans, query(L, R, l, m, rt << 1)); if (m < R) ans = max(ans, query(L, R, m + 1, r, rt << 1 | 1)); return ans; } } sg; int main() { int n, d; scanf( %d%d , &n, &d); for (int i = 1; i <= n; i++) { scanf( %lld , &h[i]); a[cnt++] = h[i]; } sort(a, a + cnt); cnt = unique(a, a + cnt) - a; for (int i = 1; i <= n; i++) { pair<int, int> x = make_pair(0, 0), y; int p = upper_bound(a, a + cnt, h[i] - d) - a; p--; if (p >= 0) x = max(x, sg.query(1, p + 1, 1, cnt, 1)); p = lower_bound(a, a + cnt, h[i] + d) - a; if (p < cnt) x = max(x, sg.query(p + 1, cnt, 1, cnt, 1)); p = lower_bound(a, a + cnt, h[i]) - a; y = sg.query(p + 1, p + 1, 1, cnt, 1); if (x.first + 1 > y.first) { sg.update(p + 1, make_pair(x.first + 1, i), 1, cnt, 1); pre[i] = x.second; } } pair<int, int> x = sg.query(1, cnt, 1, cnt, 1); printf( %d n , x.first); stack<int> st; for (int now = x.second; now != 0; now = pre[now]) st.push(now); while (!st.empty()) printf( %d , st.top()), st.pop(); return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; int main() { cin >> s; long long mid; for (long long i = 0; i < s.size(); i++) { if (s[i] == ^ ) { mid = i; break; } } long long sum = 0; for (long long i = 0; i < s.size(); i++) { if (s[i] == = || s[i] == ^ ) continue; long long x = s[i] - 48; sum += x * (i - mid); } if (sum == 0) cout << balance ; else if (sum < 0) cout << left ; else cout << right ; }
|
#include <bits/stdc++.h> using namespace std; int num[300005]; long long dp[300005], ans = -LONG_LONG_MAX; vector<int> G[300005]; int cnt = 0; void dfs(int now, int fa) { for (int k : G[now]) { if (k != fa) { dfs(k, now); dp[now] += max((long long)0, dp[k]); } } ans = max(ans, dp[now]); } void dfs2(int now, int fa) { for (int k : G[now]) { if (k != fa) { dfs2(k, now); dp[now] += max((long long)0, dp[k]); } } if (dp[now] == ans) { dp[now] = 0; cnt++; } } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> num[i]; dp[i] = num[i]; } for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; G[x].push_back(y); G[y].push_back(x); } dfs(1, -1); for (int i = 1; i <= n; i++) dp[i] = num[i]; dfs2(1, -1); cout << cnt * ans << << cnt; }
|
/*****************************************************************************
* *
* Module: Altera_UP_Avalon_Audio *
* Description: *
* This module reads and writes data to the Audio chip on Altera's DE2 *
* Development and Education Board. The audio chip must be in master mode *
* and the digital format must be left justified. *
* *
*****************************************************************************/
module Audio_Controller(
// Inputs
CLOCK_50,
reset,
clear_audio_in_memory,
read_audio_in,
clear_audio_out_memory,
left_channel_audio_out,
right_channel_audio_out,
write_audio_out,
AUD_ADCDAT,
// Bidirectionals
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
// Outputs
left_channel_audio_in,
right_channel_audio_in,
audio_in_available,
audio_out_allowed,
AUD_XCK,
AUD_DACDAT
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
localparam AUDIO_DATA_WIDTH = 32;
localparam BIT_COUNTER_INIT = 5'd31;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
input clear_audio_in_memory;
input read_audio_in;
input clear_audio_out_memory;
//input [AUDIO_DATA_WIDTH:1] left_channel_audio_out;
//input [AUDIO_DATA_WIDTH:1] right_channel_audio_out;
input [31:0] left_channel_audio_out;
input [31:0] right_channel_audio_out;
input write_audio_out;
input AUD_ADCDAT;
// Bidirectionals
inout AUD_BCLK;
inout AUD_ADCLRCK;
inout AUD_DACLRCK;
// Outputs
output reg audio_in_available;
//output [AUDIO_DATA_WIDTH:1] left_channel_audio_in;
//output [AUDIO_DATA_WIDTH:1] right_channel_audio_in;
output [31:0] left_channel_audio_in;
output [31:0] right_channel_audio_in;
output reg audio_out_allowed;
output AUD_XCK;
output AUD_DACDAT;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire bclk_rising_edge;
wire bclk_falling_edge;
wire adc_lrclk_rising_edge;
wire adc_lrclk_falling_edge;
wire dac_lrclk_rising_edge;
wire dac_lrclk_falling_edge;
wire [7:0] left_channel_read_available;
wire [7:0] right_channel_read_available;
wire [7:0] left_channel_write_space;
wire [7:0] right_channel_write_space;
// Internal Registers
reg done_adc_channel_sync;
reg done_dac_channel_sync;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
// Output Registers
always @ (posedge CLOCK_50)
begin
if (reset == 1'b1)
audio_in_available <= 1'b0;
else if ((left_channel_read_available[7] | left_channel_read_available[6])
& (right_channel_read_available[7] | right_channel_read_available[6]))
audio_in_available <= 1'b1;
else
audio_in_available <= 1'b0;
end
always @ (posedge CLOCK_50)
begin
if (reset == 1'b1)
audio_out_allowed <= 1'b0;
else if ((left_channel_write_space[7] | left_channel_write_space[6])
& (right_channel_write_space[7] | right_channel_write_space[6]))
audio_out_allowed <= 1'b1;
else
audio_out_allowed <= 1'b0;
end
// Internal Registers
always @ (posedge CLOCK_50)
begin
if (reset == 1'b1)
done_adc_channel_sync <= 1'b0;
else if (adc_lrclk_rising_edge == 1'b1)
done_adc_channel_sync <= 1'b1;
end
always @ (posedge CLOCK_50)
begin
if (reset == 1'b1)
done_dac_channel_sync <= 1'b0;
else if (dac_lrclk_falling_edge == 1'b1)
done_dac_channel_sync <= 1'b1;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign AUD_BCLK = 1'bZ;
assign AUD_ADCLRCK = 1'bZ;
assign AUD_DACLRCK = 1'bZ;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_Clock_Edge Bit_Clock_Edges (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.test_clk (AUD_BCLK),
// Bidirectionals
// Outputs
.rising_edge (bclk_rising_edge),
.falling_edge (bclk_falling_edge)
);
Altera_UP_Clock_Edge ADC_Left_Right_Clock_Edges (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.test_clk (AUD_ADCLRCK),
// Bidirectionals
// Outputs
.rising_edge (adc_lrclk_rising_edge),
.falling_edge (adc_lrclk_falling_edge)
);
Altera_UP_Clock_Edge DAC_Left_Right_Clock_Edges (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.test_clk (AUD_DACLRCK),
// Bidirectionals
// Outputs
.rising_edge (dac_lrclk_rising_edge),
.falling_edge (dac_lrclk_falling_edge)
);
Altera_UP_Audio_In_Deserializer Audio_In_Deserializer (
// Inputs
.clk (CLOCK_50),
.reset (reset | clear_audio_in_memory),
.bit_clk_rising_edge (bclk_rising_edge),
.bit_clk_falling_edge (bclk_falling_edge),
.left_right_clk_rising_edge (adc_lrclk_rising_edge),
.left_right_clk_falling_edge (adc_lrclk_falling_edge),
.done_channel_sync (done_adc_channel_sync),
.serial_audio_in_data (AUD_ADCDAT),
.read_left_audio_data_en (read_audio_in & audio_in_available),
.read_right_audio_data_en (read_audio_in & audio_in_available),
// Bidirectionals
// Outputs
.left_audio_fifo_read_space (left_channel_read_available),
.right_audio_fifo_read_space (right_channel_read_available),
.left_channel_data (left_channel_audio_in),
.right_channel_data (right_channel_audio_in)
);
defparam
Audio_In_Deserializer.AUDIO_DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_In_Deserializer.BIT_COUNTER_INIT = BIT_COUNTER_INIT;
Altera_UP_Audio_Out_Serializer Audio_Out_Serializer (
// Inputs
.clk (CLOCK_50),
.reset (reset | clear_audio_out_memory),
.bit_clk_rising_edge (bclk_rising_edge),
.bit_clk_falling_edge (bclk_falling_edge),
.left_right_clk_rising_edge (done_dac_channel_sync & dac_lrclk_rising_edge),
.left_right_clk_falling_edge (done_dac_channel_sync & dac_lrclk_falling_edge),
.left_channel_data (left_channel_audio_out),
.left_channel_data_en (write_audio_out & audio_out_allowed),
.right_channel_data (right_channel_audio_out),
.right_channel_data_en (write_audio_out & audio_out_allowed),
// Bidirectionals
// Outputs
.left_channel_fifo_write_space (left_channel_write_space),
.right_channel_fifo_write_space (right_channel_write_space),
.serial_audio_out_data (AUD_DACDAT)
);
defparam
Audio_Out_Serializer.AUDIO_DATA_WIDTH = AUDIO_DATA_WIDTH;
Audio_Clock Audio_Clock (
// Inputs
.inclk0 (CLOCK_50),
.areset (),
// Outputs
.c0 (AUD_XCK),
.locked ()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A2BB2OI_BEHAVIORAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_BEHAVIORAL_PP_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg a; initial a = 1'b1;
reg b_fc; initial b_fc = 1'b0;
reg b_pc; initial b_pc = 1'b0;
reg b_oh; initial b_oh = 1'b0;
reg b_oc; initial b_oc = 1'b0;
wire a_l = ~a;
wire b_oc_l = ~b_oc;
// Note we must ensure that full, parallel, etc, only fire during
// edges (not mid-cycle), and must provide a way to turn them off.
// SystemVerilog provides: $asserton and $assertoff.
// verilator lint_off CASEINCOMPLETE
always @* begin
// Note not all tools support directives on casez's
`ifdef ATTRIBUTES
case ({a,b_fc}) // synopsys full_case
`else
case ({a,b_fc})
`endif
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
priority case ({a,b_fc})
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
end
always @* begin
`ifdef ATTRIBUTES
case (1'b1) // synopsys full_case parallel_case
`else
`ifdef FAILING_FULL
case (1'b1) // synopsys parallel_case
`else
case (1'b1) // synopsys parallel_full
`endif
`endif
a: ;
b_pc: ;
endcase
end
`ifdef NOT_YET_VERILATOR // Unsupported
// ambit synthesis one_hot "a, b_oh"
// cadence one_cold "a_l, b_oc_l"
`endif
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==2) begin
a <= 1'b0;
b_fc <= 1'b1;
b_pc <= 1'b1;
b_oh <= 1'b1;
b_oc <= 1'b1;
end
if (cyc==3) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==4) begin
`ifdef FAILING_FULL
b_fc <= 1'b1;
`endif
`ifdef FAILING_PARALLEL
b_pc <= 1'b1;
`endif
`ifdef FAILING_OH
b_oh <= 1'b1;
`endif
`ifdef FAILING_OC
b_oc <= 1'b1;
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//PS2 mouse controller.
//This module decodes the standard 3 byte packet of an PS/2 compatible 2 or 3 button mouse, or alternatively, if an intellimouse is detected, a 4-byte packet is supported with scrollwheel support.
//The module also automatically handles power-up initailzation of the mouse.
module userio_ps2mouse
(
input clk, // 28MHz clock
input clk7_en,
input reset, //reset
inout ps2mdat, //mouse PS/2 data
inout ps2mclk, //mouse PS/2 clk
input [5:0] mou_emu,
input sof,
output reg [7:0]zcount, // mouse Z counter
output reg [7:0]ycount, //mouse Y counter
output reg [7:0]xcount, //mouse X counter
output reg _mleft, //left mouse button output
output reg _mthird, //third(middle) mouse button output
output reg _mright, //right mouse button output
input test_load, //load test value to mouse counter
input [15:0] test_data //mouse counter test value
);
reg mclkout;
wire mdatout;
reg [ 2-1:0] mdatr;
reg [ 3-1:0] mclkr;
reg [11-1:0] mreceive;
reg [12-1:0] msend;
reg [16-1:0] mtimer;
reg [ 3-1:0] mstate;
reg [ 3-1:0] mnext;
wire mclkneg;
reg mrreset;
wire mrready;
reg msreset;
wire msready;
reg mtreset;
wire mtready;
wire mthalf;
reg [ 3-1:0] mpacket;
reg intellimouse=0;
wire mcmd_done;
reg [ 4-1:0] mcmd_cnt=1;
reg mcmd_inc=0;
reg [12-1:0] mcmd;
// bidirectional open collector IO buffers
assign ps2mclk = (mclkout) ? 1'bz : 1'b0;
assign ps2mdat = (mdatout) ? 1'bz : 1'b0;
// input synchronization of external signals
always @ (posedge clk) begin
if (clk7_en) begin
mdatr[1:0] <= #1 {mdatr[0], ps2mdat};
mclkr[2:0] <= #1 {mclkr[1:0], ps2mclk};
end
end
// detect mouse clock negative edge
assign mclkneg = mclkr[2] & !mclkr[1];
// PS2 mouse input shifter
always @ (posedge clk) begin
if (clk7_en) begin
if (mrreset)
mreceive[10:0] <= #1 11'b11111111111;
else if (mclkneg)
mreceive[10:0] <= #1 {mdatr[1],mreceive[10:1]};
end
end
assign mrready = !mreceive[0];
// PS2 mouse data counter
always @ (posedge clk) begin
if (clk7_en) begin
if (reset)
mcmd_cnt <= #1 4'd0;
else if (mcmd_inc && !mcmd_done)
mcmd_cnt <= #1 mcmd_cnt + 4'd1;
end
end
assign mcmd_done = (mcmd_cnt == 4'd9);
// mouse init commands
always @ (*) begin
case (mcmd_cnt)
// GUARD STOP PARITY DATA START
4'h0 : mcmd = {1'b1, 1'b1, 1'b1, 8'hff, 1'b0}; // reset
4'h1 : mcmd = {1'b1, 1'b1, 1'b1, 8'hf3, 1'b0}; // set sample rate
4'h2 : mcmd = {1'b1, 1'b1, 1'b0, 8'hc8, 1'b0}; // sample rate = 200
4'h3 : mcmd = {1'b1, 1'b1, 1'b1, 8'hf3, 1'b0}; // set sample rate
4'h4 : mcmd = {1'b1, 1'b1, 1'b0, 8'h64, 1'b0}; // sample rate = 100
4'h5 : mcmd = {1'b1, 1'b1, 1'b1, 8'hf3, 1'b0}; // set sample rate
4'h6 : mcmd = {1'b1, 1'b1, 1'b1, 8'h50, 1'b0}; // sample rate = 80
4'h7 : mcmd = {1'b1, 1'b1, 1'b0, 8'hf2, 1'b0}; // read device type
4'h8 : mcmd = {1'b1, 1'b1, 1'b0, 8'hf4, 1'b0}; // enable data reporting
default : mcmd = {1'b1, 1'b1, 1'b0, 8'hf4, 1'b0}; // enable data reporting
endcase
end
// PS2 mouse send shifter
always @ (posedge clk) begin
if (clk7_en) begin
if (msreset)
msend[11:0] <= #1 mcmd;
else if (!msready && mclkneg)
msend[11:0] <= #1 {1'b0,msend[11:1]};
end
end
assign msready = (msend[11:0]==12'b000000000001);
assign mdatout = msend[0];
// PS2 mouse timer
always @(posedge clk) begin
if (clk7_en) begin
if (mtreset)
mtimer[15:0] <= #1 16'h0000;
else
mtimer[15:0] <= #1 mtimer[15:0] + 16'd1;
end
end
assign mtready = (mtimer[15:0]==16'hffff);
assign mthalf = mtimer[11];
// PS2 mouse packet decoding and handling
always @ (posedge clk) begin
if (clk7_en) begin
if (reset) begin
{_mthird,_mright,_mleft} <= #1 3'b111;
xcount[7:0] <= #1 8'h00;
ycount[7:0] <= #1 8'h00;
zcount[7:0] <= #1 8'h00;
end else begin
if (test_load) // test value preload
{ycount[7:2],xcount[7:2]} <= #1 {test_data[15:10],test_data[7:2]};
else if (mpacket == 3'd1) // buttons
{_mthird,_mright,_mleft} <= #1 ~mreceive[3:1];
else if (mpacket == 3'd2) // delta X movement
xcount[7:0] <= #1 xcount[7:0] + mreceive[8:1];
else if (mpacket == 3'd3) // delta Y movement
ycount[7:0] <= #1 ycount[7:0] - mreceive[8:1];
else if (mpacket == 3'd4) // delta Z movement
zcount[7:0] <= #1 zcount[7:0] + {{4{mreceive[4]}}, mreceive[4:1]};
else if (sof) begin
if (mou_emu[3]) ycount <= #1 ycount - 1'b1;
else if (mou_emu[2]) ycount <= #1 ycount + 1'b1;
if (mou_emu[1]) xcount <= #1 xcount - 1'b1;
else if (mou_emu[0]) xcount <= #1 xcount + 1'b1;
end
end
end
end
// PS2 intellimouse flag
always @ (posedge clk) begin
if (clk7_en) begin
if (reset)
intellimouse <= #1 1'b0;
else if ((mpacket==3'd5) && (mreceive[2:1] == 2'b11))
intellimouse <= #1 1'b1;
end
end
// PS2 mouse state machine
always @ (posedge clk) begin
if (clk7_en) begin
if (reset || mtready)
mstate <= #1 0;
else
mstate <= #1 mnext;
end
end
always @ (*) begin
mclkout = 1'b1;
mtreset = 1'b1;
mrreset = 1'b0;
msreset = 1'b0;
mpacket = 3'd0;
mcmd_inc = 1'b0;
case(mstate)
0 : begin
// initialize mouse phase 0, start timer
mtreset=1;
mnext=1;
end
1 : begin
//initialize mouse phase 1, hold clk low and reset send logic
mclkout=0;
mtreset=0;
msreset=1;
if (mthalf) begin
// clk was low long enough, go to next state
mnext=2;
end else begin
mnext=1;
end
end
2 : begin
// initialize mouse phase 2, send command/data to mouse
mrreset=1;
mtreset=0;
if (msready) begin
// command sent
mcmd_inc = 1;
case (mcmd_cnt)
0 : mnext = 4;
1 : mnext = 6;
2 : mnext = 6;
3 : mnext = 6;
4 : mnext = 6;
5 : mnext = 6;
6 : mnext = 6;
7 : mnext = 5;
8 : mnext = 6;
default : mnext = 6;
endcase
end else begin
mnext=2;
end
end
3 : begin
// get first packet byte
mtreset=1;
if (mrready) begin
// we got our first packet byte
mpacket=1;
mrreset=1;
mnext=4;
end else begin
// we are still waiting
mnext=3;
end
end
4 : begin
// get second packet byte
mtreset=1;
if (mrready) begin
// we got our second packet byte
mpacket=2;
mrreset=1;
mnext=5;
end else begin
// we are still waiting
mnext=4;
end
end
5 : begin
// get third packet byte
mtreset=1;
if (mrready) begin
// we got our third packet byte
mpacket=3;
mrreset=1;
mnext = (intellimouse || !mcmd_done) ? 6 : 3;
end else begin
// we are still waiting
mnext=5;
end
end
6 : begin
// get fourth packet byte
mtreset=1;
if (mrready) begin
// we got our fourth packet byte
mpacket = (mcmd_cnt == 8) ? 5 : 4;
mrreset=1;
mnext = !mcmd_done ? 0 : 3;
end else begin
// we are still waiting
mnext=6;
end
end
default : begin
//we should never come here
mclkout=1'bx;
mrreset=1'bx;
mtreset=1'bx;
msreset=1'bx;
mpacket=3'bxxx;
mnext=0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 2e5 + 123; int a[N]; vector<int> g[N]; int n, node, stdist = 0; void dfs(int k, int par, int dist) { if (dist > stdist) { node = k; stdist = dist; } for (auto it : g[k]) { if (it == par) continue; dfs(it, k, dist + (a[k] ^ a[it])); } } signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n - 1; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } node = 1; dfs(node, node, 0); dfs(node, node, 0); cout << (stdist + 1) / 2; return false; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_TB_V
/**
* udp_dff$PS_pp$PG: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_ps_pp_pg.v"
module top();
// Inputs are registered
reg D;
reg SET;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 SET = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 SET = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 SET = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 SET = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PS_pp$PG dut (.D(D), .SET(SET), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_TB_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:45:31 11/23/2014
// Design Name: ssg_display
// Module Name: /home/aneez/workspace/vSevenSegmentDisplay/ssg_display_tb.v
// Project Name: vSevenSegmentDisplay
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ssg_display
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ssg_display_tb;
// Inputs
reg sw;
reg clk;
reg rst;
// Outputs
wire [7:0] sseg_cathode;
wire [3:0] sseg_anode;
// Instantiate the Unit Under Test (UUT)
ssg_display uut (
//.sw(sw),
.clk(clk),
.greset(rst),
.sseg_cathode(sseg_cathode),
.sseg_anode(sseg_anode)
);
initial begin
// Initialize Inputs
sw = 0;
clk = 0;
rst = 1;
#10 rst = 0;
// Wait 100 ns for global reset to finish
#100;
//#1000 $finish;
// Add stimulus here
# rst = 1;
end
always #20 clk = ~clk;
endmodule
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ()
//
// Brief Description:
// Dual-clock FIFO (using Altera dcfifo IP).
//
//------------------------------------------------------------------------------
`ifndef _ZL_FIFO_DC_V_
`define _ZL_FIFO_DC_V_
module zl_fifo_dc #
(
parameter Data_width = 0,
parameter Addr_width = 0
)
(
input clk_in,
input rst_in_n,
input clk_out,
//
input in_req,
output in_ack,
input [Data_width-1:0] in_data,
output in_full,
output in_empty,
output [Addr_width-1:0] in_used,
//
output out_req,
input out_ack,
output [Data_width-1:0] out_data,
output out_full,
output out_empty,
output [Addr_width-1:0] out_used
);
dcfifo #
(
.intended_device_family("Cyclone IV E"),
.lpm_numwords(2**Addr_width),
.lpm_showahead("ON"),
.lpm_type("dcfifo"),
.lpm_width(Data_width),
.lpm_widthu(Addr_width),
.overflow_checking("ON"),
.rdsync_delaypipe(4),
.underflow_checking("ON"),
.use_eab("ON"),
.write_aclr_synch("OFF"),
.wrsync_delaypipe(4)
)
dcfifo_component
(
.rdclk (clk_out),
.wrclk (clk_in),
.wrreq (in_ack),
.aclr (~rst_in_n),
.data (in_data),
.rdreq (out_ack),
.wrfull (in_full),
.q (out_data),
.rdempty (out_empty),
.wrusedw (in_used),
.rdusedw (out_used),
.rdfull (out_full),
.wrempty (in_empty)
);
assign in_ack = in_req && !in_full;
assign out_req = !out_empty;
endmodule // zl_fifo_dc
`endif // _ZL_FIFO_DC_V_
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_UTIL
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_address_range_check (
address,
is_addr_within_valid_range
);
parameter FLASH_ADDR_WIDTH = 23;
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output is_addr_within_valid_range;
assign is_addr_within_valid_range = (address >= MIN_VALID_ADDR) && (address <= MAX_VALID_ADDR);
endmodule
module altera_onchip_flash_address_write_protection_check (
use_sector_addr,
address,
write_protection_mode,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
input use_sector_addr;
input [FLASH_ADDR_WIDTH-1:0] address;
input [4:0] write_protection_mode;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
wire is_sector1_writable;
wire is_sector2_writable;
wire is_sector3_writable;
wire is_sector4_writable;
wire is_sector5_writable;
assign is_sector1_addr = (use_sector_addr) ? (address == 1) : ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = (use_sector_addr) ? (address == 2) : ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = (use_sector_addr) ? (address == 3) : ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = (use_sector_addr) ? (address == 4) : ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = (use_sector_addr) ? (address == 5) : ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_sector1_writable = ~(write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
assign is_sector2_writable = ~(write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
assign is_sector3_writable = ~(write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
assign is_sector4_writable = ~(write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
assign is_sector5_writable = ~(write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_s_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
input [2:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = (address == 1);
assign is_sector2_addr = (address == 2);
assign is_sector3_addr = (address == 3);
assign is_sector4_addr = (address == 4);
assign is_sector5_addr = (address == 5);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_a_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_convert_address (
address,
flash_addr
);
parameter FLASH_ADDR_WIDTH = 23;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE2_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
parameter ADDR_RANGE3_OFFSET = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output [FLASH_ADDR_WIDTH-1:0] flash_addr;
assign flash_addr = (address <= ADDR_RANGE1_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE1_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
(address <= ADDR_RANGE2_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE2_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
(address + ADDR_RANGE3_OFFSET[FLASH_ADDR_WIDTH-1:0]);
endmodule
module altera_onchip_flash_convert_sector (
sector,
flash_sector
);
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
input [2:0] sector;
output [2:0] flash_sector;
assign flash_sector =
(sector == 1) ? SECTOR1_MAP[2:0] :
(sector == 2) ? SECTOR2_MAP[2:0] :
(sector == 3) ? SECTOR3_MAP[2:0] :
(sector == 4) ? SECTOR4_MAP[2:0] :
(sector == 5) ? SECTOR5_MAP[2:0] :
3'd0; // Set to 0 for invalid sector ID
endmodule
module altera_onchip_flash_counter (
clock,
reset,
count
);
input clock;
input reset;
output [4:0] count;
reg [4:0] count_reg;
assign count = count_reg;
initial begin
count_reg = 0;
end
always @ (posedge reset or posedge clock) begin
if (reset) begin
count_reg <= 0;
end
else begin
count_reg <= count_reg + 5'd1;
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
// Alternative is to concatenate sample value and or status for data.
`timescale 1ns/100ps
module axi_ad9652_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status,
// processor control signals
adc_ddr_edgesel,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [15:0] adc_data_in_p;
input [15:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data_a;
output [15:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// processor control signals
input adc_ddr_edgesel;
// delay control signals
input up_clk;
input [16:0] up_dld;
input [84:0] up_dwdata;
output [84:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [15:0] adc_data_p = 'd0;
reg [15:0] adc_data_n = 'd0;
reg [15:0] adc_data_p_d = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or_p_d = 'd0;
reg [15:0] adc_data_a = 'd0;
reg [15:0] adc_data_b = 'd0;
reg adc_or_a = 'd0;
reg adc_or_b = 'd0;
// internal signals
wire [15:0] adc_data_p_s;
wire [15:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
genvar l_inst;
// two data pin modes are supported-
// mux - across clock edges (rising or falling edges),
// mux - within clock edges (lower 7 bits and upper 7 bits)
always @(posedge adc_clk) begin
adc_status <= 1'b1;
adc_data_p <= adc_data_p_s;
adc_data_n <= adc_data_n_s;
adc_data_p_d <= adc_data_p;
adc_or_p <= adc_or_p_s;
adc_or_n <= adc_or_n_s;
adc_or_p_d <= adc_or_p;
end
always @(posedge adc_clk) begin
if (adc_ddr_edgesel == 1'b1) begin
adc_data_a <= adc_data_p_d;
adc_data_b <= adc_data_n;
adc_or_a <= adc_or_p_d;
adc_or_b <= adc_or_n;
end else begin
adc_data_a <= adc_data_n;
adc_data_b <= adc_data_p;
adc_or_a <= adc_or_n;
adc_or_b <= adc_or_p;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 15; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[16]),
.up_dwdata (up_dwdata[84:80]),
.up_drdata (up_drdata[84:80]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_LP_V
`define SKY130_FD_SC_LP__O311AI_LP_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311ai_lp (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311ai_lp (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_LP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string input, temp; bool f1, f2; cin >> n; getline(cin, input); for (int i = 0; i < n; i++) { f1 = false; f2 = false; getline(cin, input); if (input.length() > 4) { temp = input.substr(0, 5); if (temp == miao. ) f2 = true; temp = input.substr(input.length() - 5, 5); if (temp == lala. ) f1 = true; } if (f1 && !f2) cout << Freda s << endl; else if (f2 && !f1) cout << Rainbow s << endl; else cout << OMG>.< I don t know! << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { char ch; int state = 0; while ((ch = cin.get()) != EOF) switch (state) { case 0: if (isdigit(ch)) { cout << ch; state = 1; } if (ch == , ) { cout << ch; state = 2; } if (ch == ) { state = 0; } if (ch == . ) { cout << ch; state = 3; } break; case 1: if (isdigit(ch)) { cout << ch; state = 1; } if (ch == , ) { cout << ch; state = 2; } if (ch == ) { state = 6; } if (ch == . ) { cout << ; cout << ch; state = 3; } break; case 2: if (isdigit(ch)) { cout << ; cout << ch; state = 1; } if (ch == , ) { cout << ; cout << ch; state = 2; } if (ch == ) { state = 2; } if (ch == . ) { cout << ; cout << ch; state = 3; } break; case 3: if (ch == . ) { cout << ch; state = 4; } break; case 4: if (ch == . ) { cout << ch; state = 5; } break; case 5: if (isdigit(ch)) { cout << ch; state = 1; } if (ch == , ) { cout << ch; state = 2; } if (ch == ) { state = 5; } if (ch == . ) { cout << ; cout << ch; state = 3; } break; case 6: if (isdigit(ch)) { cout << ; cout << ch; state = 1; } if (ch == , ) { cout << ch; state = 2; } if (ch == ) { state = 6; } if (ch == . ) { cout << ; cout << ch; state = 3; } break; } exit: return (0); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_2_V
`define SKY130_FD_SC_LP__DLRTP_2_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_2_V
|
#include <bits/stdc++.h> using namespace std; string input() { int n; string sequence; cin >> n >> sequence; return sequence; } int getMaxBalance(const string &sequence) { int balance = 0; int maxBalance = 0; for (char bracket : sequence) { balance += (bracket == [ ) - (bracket == ] ); if (balance > maxBalance) { maxBalance = balance; } } return maxBalance; } int getOpenClosePairs(const string &sequence) { int result = 0; for (int i = 1; i < (int)sequence.size(); ++i) { result += sequence[i - 1] == [ && sequence[i] == ] ; } return result; } vector<string> solve(const string &sequence) { const int maxBalace = getMaxBalance(sequence); const int length = (int)sequence.size() + 3 * getOpenClosePairs(sequence); vector<string> result(2 * maxBalace + 1, string(length, )); int previousHeight = 2 * maxBalace + 1; char previousBracket = ] ; int col = 0; for (char bracket : sequence) { int height; if ( [ == previousBracket && [ == bracket) { height = previousHeight - 2; } else if ( [ == previousBracket && ] == bracket || ] == previousBracket && [ == bracket) { col += 3 * ( [ == previousBracket && ] == bracket); height = previousHeight; } else if ( ] == previousBracket && ] == bracket) { height = previousHeight + 2; } else { assert(false); } int middle = (int)result.size() / 2; int topRow = middle - height / 2; int bottomRow = middle + height / 2; int minusCol = col + ( [ == bracket) - ( ] == bracket); result[topRow][col] = result[bottomRow][col] = + ; result[topRow][minusCol] = result[bottomRow][minusCol] = - ; for (int row = topRow + 1; row < bottomRow; ++row) { result[row][col] = | ; } ++col; previousHeight = height; previousBracket = bracket; } return result; } void output(const vector<string> &picture) { for (const string &row : picture) { cout << row << endl; } } int main() { const string sequece = input(); auto picture = solve(sequece); output(picture); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long f[1 << 10], M = 1000000; long long l, r, k; class Matrix { public: long long a[3][3]; Matrix(int fib = 0) { memset(a, 0, sizeof(a)); if (fib) a[1][2] = a[2][1] = a[2][2] = 1; } Matrix operator*(const Matrix &v) { Matrix ret; for (int i = 1; i <= 2; ++i) for (int j = 1; j <= 2; ++j) for (int k = 1; k <= 2; ++k) ret.a[i][k] = (ret.a[i][k] + a[i][j] * v.a[j][k]) % M; return ret; } void print() { cout << a[1][2] % M << endl; } }; Matrix one(1); long long solve(long long l, long long r, long long v) { l = (l - 1) / v + 1; r = r / v; return r - l + 1; } Matrix fib(long long u) { if (u == 1) return one; Matrix cache = fib(u / 2); cache = cache * cache; if (u % 2) cache = cache * one; return cache; } int main() { cin >> M >> l >> r >> k; long long ans = 1; if (k >= 1000000) { ans = (r - l + 1) / (k - 1) + 2; while (solve(l, r, ans) < k) --ans; } else { for (int i = 1; i + k - 1 <= 1000000; ++i) { long long tl = (l - 1) / i + 1, tr = r / (i + k - 1); if (tl <= tr) ans = max(ans, tr); } } fib(ans).print(); return 0; }
|
/*
* This demonstrates a basic dynamic array
*/
module main;
byte foo[];
int idx;
initial begin
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
$finish;
end
foo = new[10];
if (foo.size() != 10) begin
$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
$finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
$display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
$finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
$display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
$finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
if (foo[idx%10] != (idx%10)) begin
$display("FAILED -- foo[%0d%%10] = %0d", foo[idx%10]);
$finish;
end
end
foo.delete();
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
$finish;
end
$display("PASSED");
end
endmodule // main
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Shift CK/Address/Commands/Controls
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay #
(
parameter TCQ = 100,
parameter tCK = 3636,
parameter DQS_CNT_WIDTH = 3,
parameter N_CTL_LANES = 3,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
// Start only after PO_CIRC_BUF_DELAY decremented
input cmd_delay_start,
// Control lane being shifted using Phaser_Out fine delay taps
output reg [N_CTL_LANES-1:0] ctl_lane_cnt,
// Inc/dec Phaser_Out fine delay line
output reg po_stg2_f_incdec,
output reg po_en_stg2_f,
output reg po_stg2_c_incdec,
output reg po_en_stg2_c,
// Completed delaying CK/Address/Commands/Controls
output po_ck_addr_cmd_delay_done
);
localparam TAP_CNT_LIMIT = 63;
//Calculate the tap resolution of the PHASER based on the clock period
localparam FREQ_REF_DIV = (tCK > 5000 ? 4 :
tCK > 2500 ? 2 : 1);
localparam integer PHASER_TAP_RES = ((tCK/2)/64);
// Determine whether 300 ps or 350 ps delay required
localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300;
// Determine the number of Phaser_Out taps required to delay by 300 ps
// 300 ps is the PCB trace uncertainty between CK and DQS byte groups
// Increment control byte lanes
localparam TAP_CNT = 0;
//localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES;
//Decrement control byte lanes
localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29;
reg delay_dec_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4 /* synthesis syn_maxfan = 10 */;
reg [5:0] delay_cnt_r;
reg [5:0] delaydec_cnt_r;
reg po_cnt_inc;
reg po_cnt_dec;
reg [3:0] wait_cnt_r;
assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4;
always @(posedge clk) begin
if (rst || po_cnt_dec || po_cnt_inc)
wait_cnt_r <= #TCQ 'd8;
else if (cmd_delay_start && (wait_cnt_r > 'd0))
wait_cnt_r <= #TCQ wait_cnt_r - 1;
end
always @(posedge clk) begin
if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0))
po_cnt_inc <= #TCQ 1'b0;
else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_inc <= #TCQ 1'b1;
else
po_cnt_inc <= #TCQ 1'b0;
end
//Tap decrement
always @(posedge clk) begin
if (rst || (delaydec_cnt_r == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
//po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane
//the alignment is started once the
always @(posedge clk) begin
if (rst) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end else begin
if (po_cnt_dec) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b1;
end else begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end
if (po_cnt_inc) begin
po_stg2_c_incdec <= #TCQ 1'b1;
po_en_stg2_c <= #TCQ 1'b1;
end else begin
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end
end
end
// delay counter to count 2 cycles
// Increment coarse taps by 2 for all control byte lanes
// to mitigate late writes
always @(posedge clk) begin
// load delay counter with init value
if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL"))
delay_cnt_r <= #TCQ 'd0;
else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delay_cnt_r <= #TCQ 'd1;
else if (po_cnt_inc && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
// delay counter to count TAP_DEC cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_DEC
if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delaydec_cnt_r <= #TCQ TAP_DEC;
else if (po_cnt_dec && (delaydec_cnt_r > 6'd0))
delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1;
end
//ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle
//This ensures all ctrl byte lanes have had their output phase shifted.
always @(posedge clk) begin
if (rst || ~cmd_delay_start )
ctl_lane_cnt <= #TCQ 6'b0;
else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt;
else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0))
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
end
// All control lanes have decremented to 31 fine taps from 46
always @(posedge clk) begin
if (rst || ~cmd_delay_start) begin
delay_dec_done <= #TCQ 1'b0;
end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) ||
((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin
delay_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_dec_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
endmodule
|
// lint_checking MODLNM OFF
module autoasciienum_onehot (
input clk,
input rst_n,
output ack
);
localparam // synopsys enum state_info
IDLE = 0,
S1 = 1,
S2 = 2,
S3 = 3,
DONE = 4;
reg [4:0] // synopsys enum state_info
cur_state, nxt_state;
always @ (*) begin
nxt_state = 5'h0;
case (1'b1)
cur_state[IDLE] : nxt_state[S1] = 1'b1;
cur_state[S1] : nxt_state[S2] = 1'b1;
cur_state[S2] : nxt_state[S3] = 1'b1;
cur_state[S3] : nxt_state[DONE] = 1'b1;
cur_state[DONE] : nxt_state[DONE] = 1'b1;
endcase
end
always @ (posedge clk or negedge rst_n)
if (rst_n == 1'b0) begin
cur_state <= 'h1;
end
else begin
cur_state <= nxt_state;
end
assign ack = cur_state[DONE];
/*AUTOASCIIENUM("cur_state", "cur_state_ascii")*/
// Beginning of automatic ASCII enum decoding
reg [31:0] cur_state_ascii; // Decode of cur_state
always @(cur_state) begin
case ({cur_state})
(5'b1<<IDLE): cur_state_ascii = "idle";
(5'b1<<S1): cur_state_ascii = "s1 ";
(5'b1<<S2): cur_state_ascii = "s2 ";
(5'b1<<S3): cur_state_ascii = "s3 ";
(5'b1<<DONE): cur_state_ascii = "done";
default: cur_state_ascii = "%Err";
endcase
end
// End of automatics
endmodule
|
module RegisterFileTestBench2;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] in,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
initial fork
//Clk 0
Clk = 0 ; RESET = 1 ; Pcin = 32'bz ; in = 32'bz ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ;
//Clk 1 (Rising Edge)
#1 RESET = 0 ; #1 Pcin = 32'bz ; #1 in = 1 ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0 ; #1 RSLCT[7:4] = 0 ; #1 RSLCT[11:8] = 0 ; #1 RSLCT[15:12] = 0 ; #1 RSLCT[19:16] = 0 ;
//Clk 0 (Falling Edge)
#2 Pcin = 32'bz ; #2 in = 1 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0 ; #2 RSLCT[7:4] = 0 ; #2 RSLCT[11:8] = 0 ; #2 RSLCT[15:12] = 0 ; #2 RSLCT[19:16] = 0 ;
//Clk 1 (Rising Edge)
#3 Pcin = 32'bz ; #3 in = Rn ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0 ; #3 RSLCT[7:4] = 0 ; #3 RSLCT[11:8] = 0 ; #3 RSLCT[15:12] = 1 ; #3 RSLCT[19:16] = 0 ;
//Clk 0 (Falling Edge)
#4 Pcin = 32'bz ; #4 in = Rn ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0 ; #4 RSLCT[7:4] = 0 ; #4 RSLCT[11:8] = 0 ; #4 RSLCT[15:12] = 1 ; #4 RSLCT[19:16] = 0 ;
//Clk 1 (Rising Edge)
#5 Pcin = 32'bz ; #5 in = Rn ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0 ; #5 RSLCT[7:4] = 0 ; #5 RSLCT[11:8] = 0 ; #5 RSLCT[15:12] = 2 ; #5 RSLCT[19:16] = 0 ;
//Clk 0 (Falling Edge)
#6 Pcin = 32'bz ; #6 in = Rn ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0 ; #6 RSLCT[7:4] = 0 ; #6 RSLCT[11:8] = 0 ; #6 RSLCT[15:12] = 2 ; #6 RSLCT[19:16] = 0 ;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("RegisterFileTestBench2.vcd");
$dumpvars(0,RegisterFileTestBench2);
$display(" Test Results" );
$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v RegisterFileTestBench2.v
|
#include <bits/stdc++.h> using namespace std; namespace variables { struct triple { long long first, second, third; }; } // namespace variables using namespace variables; void testt(); namespace andu2006 { void debug(set<long long> _var, string _name = ) { cerr << Debug #set << _name << = [ ; for (auto it : _var) cerr << it << , ; cerr << END] : << size = << _var.size() << n n ; } void light_debug(set<long long> _var, string _name = ) { cerr << Debug #set << _name << = [ ; for (auto it : _var) cerr << it << , ; cerr << END] n n ; } void debug(map<long long, long long> _var, string _name = ) { cerr << Debug #map (size = << _var.size() << ) n ; for (auto it : _var) cerr << _name << [ << it.first << ] = << it.second << n ; } void light_debug(map<long long, long long> _var, string _name = ) { cerr << Debug #map n ; for (auto it : _var) cerr << _name << [ << it.first << ] = << it.second << n ; } void debug(deque<long long> _var, string _name = ) { cerr << Debug #deque << _name << = [ ; for (auto it : _var) cerr << it << , ; cerr << END] : << size = << _var.size() << n n ; } void light_debug(deque<long long> _var, string _name = ) { cerr << Debug #deque << _name << = [ ; for (auto it : _var) cerr << it << , ; cerr << END] n n ; } void debug(vector<long long> _var, string _name = ) { cerr << Debug #vector << _name << = [ ; for (auto it : _var) cerr << it << , ; cerr << END] : << size = << _var.size() << n n ; } void light_debug(vector<long long> _var, string _name = ) { cerr << Debug #vector << _name << = [ ; for (auto it : _var) cerr << it << , ; cerr << END] n n ; } void debug(string _var, string _name = ) { cerr << Debug #string << _name << = ; cerr << << _var << ; cerr << : << size = << _var.size() << n n ; } void light_debug(string _var, string _name = ) { cerr << Debug #string : << _name << = << << _var << << n n ; } void debug(long long _var, string _name = ) { cerr << Debug #int64 : << _name << = << _var << n n ; } void debug(unsigned long long _var, string _name = ) { cerr << Debug #uint64 : << _name << = << _var << n n ; } void debug(unsigned int _var, string _name = ) { cerr << Debug #uint32 : << _name << = << _var << n n ; } void debug(int _var, string _name = ) { cerr << Debug #int32 : << _name << = << _var << n n ; } void debug(char _var, string _name = ) { cerr << Debug #char : << _name << = << _var << n n ; } void debug(bool _var, string _name = ) { cerr << Debug #Boolean : << _name << = << (_var ? 1 True : 0 False ) << n n ; } string emptyString; vector<long long> emptyVector; stack<long long> emptyStack; queue<long long> emptyQueue; void multipleTests() { long long __test_count; cin >> __test_count; while (__test_count--) testt(); } void done() { exit(0); } void fastIO() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } void rseed() { srand(time(NULL)); } void mreset(void* _pointer, unsigned int _size) { memset(_pointer, 0, _size); } template <char compArg> bool compare(long long a, long long b) { if (compArg == < ) return a < b; else if (compArg == > ) return a > b; return false; } template <char compArg1, char compArg2> bool compair(pair<long long, long long> a, pair<long long, long long> b) { return compare<compArg1>(a.first, b.first) || (a.first == b.first && compare<compArg2>(a.second, b.second)); } template <char compArg1, char compArg2> struct objcompair { bool operator()(pair<long long, long long> a, pair<long long, long long> b) { return compare<compArg1>(a.first, b.first) || (a.first == b.first && compare<compArg2>(a.second, b.second)); } }; long long trailingZeroes(long long x) { if (x == 0) return 0; return (x & 1 ? 0 : 1 + trailingZeroes(x / 2)); } long long trailingOnes(long long x) { if (x == 0) return 0; return (x & 1 ? 1 + trailingZeroes(x / 2) : 0); } long long trailingPowerOfTwo(long long x) { return 1ll << trailingZeroes(x); } long long popCount(long long x) { if (x == 0) return x; return 1 + popCount(x & -x); } long long log2(long long x) { if (x == 0) return -1; return 1 + log2(x / 2); } long long getBit(long long x, long long pos) { return (x >> pos) & 1; } long long cutLastOne(long long x) { return x & -x; } long long binPow(long long _num, long long _exponent, long long _mod) { if (_exponent == 0) return 1; long long _half = binPow(_num, _exponent / 2, _mod); return _half * _half % _mod * (_exponent & 1 ? _num : 1) % _mod; } long long modularInverse(long long _x, long long _mod) { return binPow(_x, _mod - 2, _mod); } long long comb(long long _n, long long _k, long long _mod) { long long _ans = 1; for (long long i = _n - _k + 1; i <= _n; i++) _ans = _ans * i % _mod; for (long long i = 2; i <= _k; i++) _ans = _ans * modularInverse(i, _mod) % _mod; return _ans; } const long double PI = acos(-1); const long double rad = 180 / PI; long double degsin(long long __alpha) { return sin(__alpha / rad); } long double degcos(long long __alpha) { return cos(__alpha / rad); } long double degtan(long long __alpha) { return tan(__alpha / rad); } long double degasin(long long _sine) { return asin(_sine) * rad; } long double degacos(long long _cosine) { return acos(_cosine) * rad; } long double degatan(long long _tangent) { return atan(_tangent) * rad; } long long gcd(long long _num1, long long _num2) { if (_num2 == 0) return _num1; return gcd(_num2, _num1 % _num2); } long long lcm(long long _num1, long long _num2) { return _num1 * _num2 / gcd(_num1, _num2); } long long divisors(long long _num) { if (_num == 0) return 0; long long _cnt = 1, _exp; while (_num % 2 == 0) { _cnt++; _num /= 2; } for (long long _divisor = 3; _divisor * _divisor <= _num; _divisor += 2) { _exp = 0; while (_num % _divisor == 0) { _exp++; _num /= _divisor; } _cnt *= (_exp + 1); } if (_num > 1) _cnt *= 2; return _cnt; } long long eulerTotient(long long _num) { if (_num == 0) return 0; long long _cnt = 1, _divisor = 2; while (_num % _divisor == 0) { _cnt *= _divisor; _num /= _divisor; } _cnt /= _divisor; _cnt *= (_divisor - 1); for (long long _divisor = 3; _divisor * _divisor <= _num; _divisor += 2) { if (_num % _divisor == 0) { while (_num % _divisor == 0) { _cnt *= _divisor; _num /= _divisor; } _cnt /= _divisor; _cnt *= (_divisor - 1); } } if (_num > 1) _cnt *= _num - 1; return _cnt; } void sieve(bool* _startpos, bool* _endpos) { long long _maxnum = _endpos - _startpos; for (long long i = 4; i < _maxnum; i += 2) *(_startpos + i) = 1; for (long long i = 3; i * i < _maxnum; i += 2) if (*(_startpos + i) == 0) for (long long j = i * i; j < _maxnum; j += i) *(_startpos + j) = 1; } } // namespace andu2006 void testt() {} set<long long> points; long long pos[100001], fr[100001], p[5001], sizp; int main() { andu2006::fastIO(); long long p1[100], p2[100], n, m; for (long long i = 0; i < 100001; i++) pos[i] = -1; cin >> n >> m; for (long long i = 0; i < n; i++) cin >> p1[i]; for (long long i = 0; i < m; i++) { cin >> p2[i]; pos[p2[i] + 40000] = i; fr[p2[i] + 40000]++; for (long long j = 0; j < n; j++) points.insert(p1[j] + p2[i]); } long long ans = 0; bool b1[61] = {0}, b2[61] = {0}; for (auto it : points) p[sizp++] = it; for (long long i = 0; i < sizp; i++) { for (long long j = i; j < sizp; j++) { for (long long k = 0; k < n; k++) { if (pos[p[i] - p1[k] + 40000] != -1) { b2[pos[p[i] - p1[k] + 40000]] = 1; b1[k] = 1; } if (pos[p[j] - p1[k] + 40000] != -1) { b2[pos[p[j] - p1[k] + 40000]] = 1; b1[k] = 1; } } long long cnt = 0; for (long long i = 0; i < max(n, m); i++) { if (b1[i] == 1) cnt++; if (b2[i] == 1) cnt += fr[p2[i] + 40000]; b1[i] = b2[i] = 0; } ans = max(ans, cnt); } } cout << ans; andu2006::done(); }
|
#include <bits/stdc++.h> using namespace std; long long n, l, r; long long gerar(long long n) { if (n == 0) { return 0; } return 2 * gerar(n / 2) + 1; } long long solve(long long esq, long long dir, long long l, long long r, long long valor) { long long mid = (esq + dir) / 2; long long res = 0; if (valor == 1) { return 1; } if (valor == 0) { return 0; } if (mid >= l && mid <= r) { res += valor % 2ll; } if (mid - 1 >= l) { res += solve(esq, mid - 1, l, r, valor / 2ll); } if (mid + 1 <= r) { res += solve(mid + 1, dir, l, r, valor / 2ll); } return res; } int main() { scanf( %lld %lld %lld , &n, &l, &r); long long qtd = gerar(n); printf( %lld n , solve(1, qtd, l, r, n)); }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[3010], x, y, c[100], d[100], n, l, r, time, count = 0, p, q, i, j; scanf( %d%d%d%d , &p, &q, &l, &r); memset(a, 0, sizeof(a)); while (p--) { scanf( %d%d , &x, &y); for (i = x; i <= y; i++) a[i]++; } for (i = 0; i < q; i++) { scanf( %d%d , &c[i], &d[i]); } for (time = l; time <= r; time++) { for (i = 0; i < q; i++) { int flag = 0; for (j = c[i] + time; j <= d[i] + time; j++) { if (a[j] > 0) { count++; flag++; break; } } if (flag > 0) { break; } } } printf( %d n , count); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long n; long long b[200005]; long long cnt[65]; vector<long long> vec, vec2; int main(void) { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> b[i]; for (int i = 1; i <= n; i++) { long long x = 0; for (long long t = b[i]; t % 2 == 0; t /= 2) x++; cnt[x]++; } long long mn = -1e9, mn_i; for (int i = 0; i < 65; i++) { if (mn < cnt[i]) { mn = cnt[i]; mn_i = i; } } for (int i = 1; i <= n; i++) { if (!(b[i] % (1LL << mn_i) == 0 && b[i] % (1LL << (mn_i + 1)))) vec.push_back(b[i]); } cout << (int)vec.size() << endl; for (int i = 0; i < vec.size(); i++) cout << vec[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int k, n[3], t[3]; while (scanf( %d , &k) == 1) { for (int i = 0; i < 3; i++) scanf( %d , &n[i]); for (int i = 0; i < 3; i++) scanf( %d , &t[i]); deque<int> q[3]; for (int i = 0; i < 3; i++) q[i].clear(); int p = 0; while (k--) { for (int i = 0; i < 3; i++) if (q[i].size() == n[i]) { p = q[i].front() + t[i]; for (int j = 0; j < 3; j++) { while (q[j].size() && q[j].front() + t[j] <= p) q[j].pop_front(); } i = -1; } for (int i = 0; i < 3; i++) q[i].push_back(p); } printf( %d n , p + t[0] + t[1] + t[2]); } return 0; }
|
// dig
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "cog.v" // cog logic and memory (8 instances)
`include "hub.v" // hub logic and memory
module dig
(
input nres, // reset input (active low)
output [7:0] cfg, // configuration output (set by clkset instruction)
input clk_cog, // cog clock input
input clk_pll, // pll simulator clock input (2x cog clock)
input [31:0] pin_in, // pin state inputs
output [31:0] pin_out, // pin state outputs
output [31:0] pin_dir, // pin direction outputs
output [7:0] cog_led // led outputs to show which cogs are active
);
// cnt
reg [31:0] cnt;
always @(posedge clk_cog)
if (nres)
cnt <= cnt + 1'b1;
// bus enable
reg ena_bus;
always @(posedge clk_cog or negedge nres)
if (!nres)
ena_bus <= 1'b0;
else
ena_bus <= !ena_bus;
// bus select
reg [7:0] bus_sel;
always @(posedge clk_cog or negedge nres)
if (!nres)
bus_sel <= 8'b0;
else if (ena_bus)
bus_sel <= {bus_sel[6:0], ~|bus_sel[6:0]};
// cogs
wire [7:0] bus_r;
wire [7:0] bus_e;
wire [7:0] bus_w;
wire [7:0] [1:0] bus_s;
wire [7:0] [15:0] bus_a;
wire [7:0] [31:0] bus_d;
wire [7:0] pll;
wire [7:0] [31:0] outx;
wire [7:0] [31:0] dirx;
genvar i;
generate
for (i=0; i<8; i++)
begin : coggen
cog cog_( .nres (nres),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena_bus (ena_bus),
.ptr_w (ptr_w[i]),
.ptr_d (ptr_d),
.ena (cog_ena[i]),
.bus_sel (bus_sel[i]),
.bus_r (bus_r[i]),
.bus_e (bus_e[i]),
.bus_w (bus_w[i]),
.bus_s (bus_s[i]),
.bus_a (bus_a[i]),
.bus_d (bus_d[i]),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack[i]),
.cnt (cnt),
.pll_in (pll),
.pll_out (pll[i]),
.pin_in (pin_in),
.pin_out (outx[i]),
.pin_dir (dirx[i]) );
end
endgenerate
// hub
wire hub_bus_r = |bus_r;
wire hub_bus_e = |bus_e;
wire hub_bus_w = |bus_w;
wire [1:0] hub_bus_s = bus_s[7] | bus_s[6] | bus_s[5] | bus_s[4] | bus_s[3] | bus_s[2] | bus_s[1] | bus_s[0];
wire [15:0] hub_bus_a = bus_a[7] | bus_a[6] | bus_a[5] | bus_a[4] | bus_a[3] | bus_a[2] | bus_a[1] | bus_a[0];
wire [31:0] hub_bus_d = bus_d[7] | bus_d[6] | bus_d[5] | bus_d[4] | bus_d[3] | bus_d[2] | bus_d[1] | bus_d[0];
wire [31:0] bus_q;
wire bus_c;
wire [7:0] bus_ack;
wire [7:0] cog_ena;
wire [7:0] ptr_w;
wire [27:0] ptr_d;
hub hub_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.nres (nres),
.bus_sel (bus_sel),
.bus_r (hub_bus_r),
.bus_e (hub_bus_e),
.bus_w (hub_bus_w),
.bus_s (hub_bus_s),
.bus_a (hub_bus_a),
.bus_d (hub_bus_d),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack),
.cog_ena (cog_ena),
.ptr_w (ptr_w),
.ptr_d (ptr_d),
.cfg (cfg) );
// pins
assign pin_out = outx[7] | outx[6] | outx[5] | outx[4] | outx[3] | outx[2] | outx[1] | outx[0];
assign pin_dir = dirx[7] | dirx[6] | dirx[5] | dirx[4] | dirx[3] | dirx[2] | dirx[1] | dirx[0];
// cog leds
assign cog_led = cog_ena;
endmodule
|
`begin_keywords "1364-2005"
/*
* Copyright (c) 2005 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* andnot1.v
* This tests types.
*/
module main;
reg a, b, c;
wire d = a & !b; // change from !b to ~b and everything is fine
reg [2:0] tmp;
reg ref;
initial begin
// Do an exaustive scan of the possible values.
for (tmp = 0 ; tmp < 4 ; tmp = tmp + 1) begin
a = tmp[0];
b = tmp[1];
c = a & ~b;
#1 if (c != d) begin
$display("FAILED -- a=%b, b=%b, c=%b, d=%b",
a, b, c, d);
$finish;
end
end // for (tmp = 0 ; tmp < 4 ; tmp = tmp + 1)
$display("PASSED");
end
endmodule // main
`end_keywords
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information of Xilinx, Inc.
// and is protected under U.S. and international copyright and other
// intellectual property laws.
//
// DISCLAIMER
//
// This disclaimer is not a license and does not grant any rights to the
// materials distributed herewith. Except as otherwise provided in a valid
// license issued to you by Xilinx, and to the maximum extent permitted by
// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
// and (2) Xilinx shall not be liable (whether in contract or tort, including
// negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these
// materials, including for any direct, or any indirect, special, incidental,
// or consequential loss or damage (including loss of data, profits, goodwill,
// or any type of loss or damage suffered as a result of any action brought by
// a third party) even if such damage or loss was reasonably foreseeable or
// Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
//
// Xilinx products are not designed or intended to be fail-safe, or for use in
// any application requiring fail-safe performance, such as life-support or
// safety devices or systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any other
// applications that could lead to death, personal injury, or severe property
// or environmental damage (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and liability of any use of
// Xilinx products in Critical Applications, subject only to applicable laws
// and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
// AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : gtpa1_dual_wrapper_top.v
// Description: PCI Express Wrapper for GTPA1_DUAL
//
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
module gtpa1_dual_wrapper_top #(
parameter SIMULATION = 0
)
(
// Clock and reset
input wire sys_rst_n,
input wire sys_clk,
input wire gt_usrclk,
input wire gt_usrclk2x,
output wire gt_refclk_out,
output wire gt_reset_done,
input wire rxreset,
// RX and TX path GTP <-> PCIe
output wire [1:0] rx_char_is_k,
output wire [15:0] rx_data,
output wire rx_enter_elecidle,
output wire [2:0] rx_status,
input wire rx_polarity,
input wire [1:0] tx_char_disp_mode,
input wire [1:0] tx_char_is_k,
input wire tx_rcvr_det,
input wire [15:0] tx_data,
// Status and control path GTP <-> PCIe
output wire phystatus,
output wire gt_rx_valid,
output wire gt_plllkdet_out,
input wire gt_tx_elec_idle,
input wire [1:0] gt_power_down,
// PCIe serial datapath
output wire arp_txp,
output wire arp_txn,
input wire arp_rxp,
input wire arp_rxn
);
wire [1:0] gt_refclk;
assign gt_refclk_out = gt_refclk[0];
GTPA1_DUAL_WRAPPER #
(
// Simulation attributes
.WRAPPER_SIM_GTPRESET_SPEEDUP (1),
.WRAPPER_SIMULATION (SIMULATION)
) GT_i
(
//---------------------- Loopback and Powerdown Ports ----------------------
.TILE0_RXPOWERDOWN0_IN (gt_power_down),
.TILE0_RXPOWERDOWN1_IN (2'b10),
.TILE0_TXPOWERDOWN0_IN (gt_power_down),
.TILE0_TXPOWERDOWN1_IN (2'b10),
//------------------------------- PLL Ports --------------------------------
.TILE0_CLK00_IN (sys_clk),
.TILE0_CLK01_IN (1'b0),
.TILE0_GTPRESET0_IN (!sys_rst_n),
.TILE0_GTPRESET1_IN (1'b1),
.TILE0_PLLLKDET0_OUT (gt_plllkdet_out),
.TILE0_PLLLKDET1_OUT (),
.TILE0_RESETDONE0_OUT (gt_reset_done),
.TILE0_RESETDONE1_OUT (),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.TILE0_RXCHARISK0_OUT ({rx_char_is_k[0], rx_char_is_k[1]}),
.TILE0_RXCHARISK1_OUT (),
.TILE0_RXDISPERR0_OUT (),
.TILE0_RXDISPERR1_OUT (),
.TILE0_RXNOTINTABLE0_OUT (),
.TILE0_RXNOTINTABLE1_OUT (),
//-------------------- Receive Ports - Clock Correction --------------------
.TILE0_RXCLKCORCNT0_OUT (),
.TILE0_RXCLKCORCNT1_OUT (),
//------------- Receive Ports - Comma Detection and Alignment --------------
.TILE0_RXENMCOMMAALIGN0_IN (1'b1),
.TILE0_RXENMCOMMAALIGN1_IN (1'b1),
.TILE0_RXENPCOMMAALIGN0_IN (1'b1),
.TILE0_RXENPCOMMAALIGN1_IN (1'b1),
//----------------- Receive Ports - RX Data Path interface -----------------
.TILE0_RXDATA0_OUT ({rx_data[7:0], rx_data[15:8]}),
.TILE0_RXDATA1_OUT (),
.TILE0_RXRESET0_IN (rxreset),
.TILE0_RXRESET1_IN (1'b1),
.TILE0_RXUSRCLK0_IN (gt_usrclk2x),
.TILE0_RXUSRCLK1_IN (1'b0),
.TILE0_RXUSRCLK20_IN (gt_usrclk),
.TILE0_RXUSRCLK21_IN (1'b0),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.TILE0_GATERXELECIDLE0_IN (1'b0),
.TILE0_GATERXELECIDLE1_IN (1'b0),
.TILE0_IGNORESIGDET0_IN (1'b0),
.TILE0_IGNORESIGDET1_IN (1'b0),
.TILE0_RXELECIDLE0_OUT (rx_enter_elecidle),
.TILE0_RXELECIDLE1_OUT (),
.TILE0_RXN0_IN (arp_rxn),
.TILE0_RXN1_IN (1'b0),
.TILE0_RXP0_IN (arp_rxp),
.TILE0_RXP1_IN (1'b0),
//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
.TILE0_RXSTATUS0_OUT (rx_status),
.TILE0_RXSTATUS1_OUT (),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.TILE0_PHYSTATUS0_OUT (phystatus),
.TILE0_PHYSTATUS1_OUT (),
.TILE0_RXVALID0_OUT (gt_rx_valid),
.TILE0_RXVALID1_OUT (),
//------------------ Receive Ports - RX Polarity Control -------------------
.TILE0_RXPOLARITY0_IN (rx_polarity),
.TILE0_RXPOLARITY1_IN (1'b0),
//-------------------------- TX/RX Datapath Ports --------------------------
.TILE0_GTPCLKOUT0_OUT (gt_refclk),
.TILE0_GTPCLKOUT1_OUT (),
//----------------- Transmit Ports - 8b10b Encoder Control -----------------
.TILE0_TXCHARDISPMODE0_IN ({tx_char_disp_mode[0], tx_char_disp_mode[1]}),
.TILE0_TXCHARDISPMODE1_IN (2'b00),
.TILE0_TXCHARISK0_IN ({tx_char_is_k[0], tx_char_is_k[1]}),
.TILE0_TXCHARISK1_IN (2'b00),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TILE0_TXDATA0_IN ({tx_data[7:0], tx_data[15:8]}),
.TILE0_TXDATA1_IN (16'd0),
.TILE0_TXUSRCLK0_IN (gt_usrclk2x),
.TILE0_TXUSRCLK1_IN (1'b0),
.TILE0_TXUSRCLK20_IN (gt_usrclk),
.TILE0_TXUSRCLK21_IN (1'b0),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.TILE0_TXN0_OUT (arp_txn),
.TILE0_TXN1_OUT (),
.TILE0_TXP0_OUT (arp_txp),
.TILE0_TXP1_OUT (),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TILE0_TXDETECTRX0_IN (tx_rcvr_det),
.TILE0_TXDETECTRX1_IN (1'b0),
.TILE0_TXELECIDLE0_IN (gt_tx_elec_idle),
.TILE0_TXELECIDLE1_IN (1'b0)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int main() { cin >> n; for (int i = 0, c = 2 % n; i < n - 1; i++, c = (c + i + 1) % n) { if (c) cout << c << ; else cout << n << endl; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int mo = 1000000007; inline void gn(long long &x) { int sg = 1; char c; while (((c = getchar()) < 0 || c > 9 ) && c != - ) ; c == - ? (sg = -1, x = 0) : (x = c - 0 ); while ((c = getchar()) >= 0 && c <= 9 ) x = x * 10 + c - 0 ; x *= sg; } inline void gn(int &x) { long long t; gn(t); x = t; } inline void gn(unsigned long long &x) { long long t; gn(t); x = t; } inline void gn(double &x) { double t; scanf( %lf , &t); x = t; } inline void gn(long double &x) { double t; scanf( %lf , &t); x = t; } template <class T1, class T2> inline void gn(T1 &r, T2 &s) { gn(r), gn(s); } template <class T1, class T2, class T3> inline void gn(T1 &r, T2 &s, T3 &t) { gn(r), gn(s), gn(t); } template <class T1, class T2, class T3, class T4> inline void gn(T1 &r, T2 &s, T3 &t, T4 &u) { gn(r), gn(s), gn(t), gn(u); } inline void gs(char *s) { scanf( %s , s); } inline void gc(char &c) { while ((c = getchar()) > 126 || c < 33) ; } inline void pc(char c) { putchar(c); } const int DX[] = {1, 0, -1, 0}, DY[] = {0, 1, 0, -1}; long long powmod(long long a, long long b) { long long res = 1; a %= mo; for (; b; b >>= 1) { if (b & 1) res = res * a % mo; a = a * a % mo; } return res; } long long powmod(long long a, long long b, long long mo) { long long res = 1; a %= mo; for (; b; b >>= 1) { if (b & 1) res = res * a % mo; a = a * a % mo; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } const int N = 5055, M = 111111; int l, m, n, t, C, x, y, prex; vector<int> a[N]; int dis[N][N]; void bfs(int k) { for (int i = (1); i <= (n); ++i) dis[k][i] = inf; dis[k][k] = 0; queue<int> Q; Q.push(k); while (!Q.empty()) { int p = Q.front(); Q.pop(); for (auto i : a[p]) { if (dis[k][i] == inf) { dis[k][i] = dis[k][p] + 1; Q.push(i); } } } } int p[9]; void update() { printf( %d %d %d n , p[0], p[1], p[2]); fflush(stdout); if (p[0] == x || p[1] == x || p[2] == x) exit(0); prex = x; scanf( %d , &x); if (p[0] == x || p[1] == x || p[2] == x) exit(0); } void go(int &x, int y) { for (auto i : a[x]) if (dis[i][y] == dis[x][y] - 1) { x = i; break; } } int main() { scanf( %d%d , &n, &m); for (int i = (1); i <= (m); ++i) scanf( %d%d , &x, &y), a[x].push_back(y), a[y].push_back(x); for (int i = (1); i <= (n); ++i) bfs(i); p[0] = p[1] = p[2] = 1; x = -1; while (1) { update(); int q[9]; int ans = inf; for (int i = (0); i <= (((int)(a[x]).size()) - 1); ++i) for (int j = (0); j <= (((int)(a[x]).size()) - 1); ++j) for (int k = (0); k <= (((int)(a[x]).size()) - 1); ++k) { int res = dis[p[0]][a[x][i]] + dis[p[1]][a[x][j]] + dis[p[2]][a[x][k]]; if (i != j) res -= n; if (j != k) res -= n; if (i != k) res -= n; if (res < ans) ans = res, q[0] = a[x][i], q[1] = a[x][j], q[2] = a[x][k]; } for (int i = (0); i <= (2); ++i) if (dis[p[i]][x] == 1) q[i] = x; for (int i = (0); i <= (2); ++i) go(p[i], q[i]); } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Apod.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Apod (
address,
clock,
q);
input [10:0] address;
input clock;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({64{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "Apod.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=apod",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 64,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "apod"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Apod.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "64"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Apod.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=apod"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_a 0 0 64 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; char str[200005]; int arr[200005]; int cum[200005]; int main() { scanf( %s , &str); int n = strlen(str); int q, idx; scanf( %d , &q); while (q--) { scanf( %d , &idx); int l = idx, r = n - idx + 1; arr[l]++; arr[r + 1]--; } for (int i = 1; i <= n; i++) { cum[i] = cum[i - 1] + arr[i]; } for (int i = 0; i < n; i++) { if (cum[i + 1] % 2 == 0) { printf( %c , str[i]); } else { printf( %c , str[n - i - 1]); } } }
|
module merge_step(X9,Y9,b,X17,Y17,clk);
`define WIDTH 22
input clk;
input [`WIDTH-1:0] X9;
input [`WIDTH-1:0] Y9;
input [7:0] b;
output reg [`WIDTH-1:0] X17;
output reg [`WIDTH-1:0] Y17;
wire [`WIDTH-1:0] tmpX10;
wire [`WIDTH-1:0] tmpX11;
wire [`WIDTH-1:0] tmpX12;
wire [`WIDTH-1:0] tmpX13;
wire [`WIDTH-1:0] tmpX14;
wire [`WIDTH-1:0] tmpX15;
wire [`WIDTH-1:0] tmpX16;
wire [`WIDTH-1:0] tmpX17;
wire [`WIDTH-1:0] tmpY10;
wire [`WIDTH-1:0] tmpY11;
wire [`WIDTH-1:0] tmpY12;
wire [`WIDTH-1:0] tmpY13;
wire [`WIDTH-1:0] tmpY14;
wire [`WIDTH-1:0] tmpY15;
wire [`WIDTH-1:0] tmpY16;
wire [`WIDTH-1:0] tmpY17;
//
//merge Y
merge_loc #(.shift_num(9))
M1 (.A_in(Y9),.b(b[7]),.A_out(tmpY10),.clk(clk));
merge_loc #(.shift_num(10))
M2 (.A_in(Y9),.b(b[6]),.A_out(tmpY11),.clk(clk));
merge_loc #(.shift_num(11))
M3 (.A_in(Y9),.b(b[5]),.A_out(tmpY12),.clk(clk));
merge_loc #(.shift_num(12))
M4 (.A_in(Y9),.b(b[4]),.A_out(tmpY13),.clk(clk));
merge_loc #(.shift_num(13))
M5 (.A_in(Y9),.b(b[3]),.A_out(tmpY14),.clk(clk));
merge_loc #(.shift_num(14))
M6 (.A_in(Y9),.b(b[2]),.A_out(tmpY15),.clk(clk));
merge_loc #(.shift_num(15))
M7 (.A_in(Y9),.b(b[1]),.A_out(tmpY16),.clk(clk));
merge_loc #(.shift_num(16))
M8 (.A_in(Y9),.b(b[0]),.A_out(tmpY17),.clk(clk));
//merge X
merge_loc #(.shift_num(9))
M9 (.A_in(X9),.b(b[7]),.A_out(tmpX10),.clk(clk));
merge_loc #(.shift_num(10))
M10 (.A_in(X9),.b(b[6]),.A_out(tmpX11),.clk(clk));
merge_loc #(.shift_num(11))
M11 (.A_in(X9),.b(b[5]),.A_out(tmpX12),.clk(clk));
merge_loc #(.shift_num(12))
M12 (.A_in(X9),.b(b[4]),.A_out(tmpX13),.clk(clk));
merge_loc #(.shift_num(13))
M13 (.A_in(X9),.b(b[3]),.A_out(tmpX14),.clk(clk));
merge_loc #(.shift_num(14))
M14 (.A_in(X9),.b(b[2]),.A_out(tmpX15),.clk(clk));
merge_loc #(.shift_num(15))
M15 (.A_in(X9),.b(b[1]),.A_out(tmpX16),.clk(clk));
merge_loc #(.shift_num(16))
M16 (.A_in(X9),.b(b[0]),.A_out(tmpX17),.clk(clk));
//sum X17,Y17
always @(*)begin
if(X17>=22'b0111111111111111111111)
X17<=22'b0111111111111111111111;
end
always @(X9 or Y9) begin
X17<=X9-tmpY10-tmpY11-tmpY12-tmpY13-tmpY14-tmpY15-tmpY16-tmpY17;
Y17<=Y9+tmpX10+tmpX11+tmpX12+tmpX13+tmpX14+tmpX15+tmpX16+tmpX17;
// $display("X17=%d,Y17=%d",X17,Y17);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const long long inf = 3e18; long long t, a[maxn], b[maxn], x[maxn]; long long l[maxn], r[maxn]; int n; int main() { scanf( %d%lld , &n, &t); for (int i = 1; i <= n; i++) scanf( %lld , a + i); for (int i = 1; i <= n; i++) scanf( %lld , x + i); for (int i = 1; i <= n; i++) { if (i < n && x[i] > x[i + 1]) { puts( No ); return 0; } l[i] = a[i] + t; r[i] = inf; if (x[i] < i) { puts( No ); return 0; } } int now = 1; for (int i = 1; i < n; i++) { for (now = max(now, i); now < x[i]; now++) { l[now] = max(l[now], a[now + 1] + t); } if (now != n) r[now] = min(r[now], a[now + 1] + t - 1); } for (int i = 1; i <= n; i++) { if (l[i] > r[i]) { puts( No ); return 0; } b[i] = min(r[i], max(b[i - 1] + 1, l[i])); if (b[i] <= b[i - 1] || b[i - 1] + 1 > r[i]) { puts( No ); return 0; } } puts( Yes ); for (int i = 1; i <= n; i++) printf( %lld , b[i]); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 32-Bit Shift Register Look-Up-Table with Carry and Clock Enable
// /___/ /\ Filename : SRLC32E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:04 PST 2004
// \___\/\___\
//
// Revision:
// 03/15/05 - Initial version.
// 01/07/06 - Add LOC parameter (CR 222733)
// 01/18/06 - Add timing path for A1, A2, A3, A4 (CR224341).
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module SRLC32E #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output Q,
output Q31,
input [4:0] A,
input CE,
input CLK,
input D
);
reg [31:0] data;
wire CLK_dly, CE_dly, D_dly;
wire CLK_in, CE_in, D_in;
wire clk_is_inverted;
reg notifier;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
while ((CLK_in !== 1'b0) && (first_time == 1'b1)) #1000;
deassign data;
end
always @(posedge CLK_in)
if (CE_in == 1'b1)
data[31:0] <= {data[30:0], D_in};
assign Q = data[A];
assign Q31 = data[31];
always @(notifier)
data[0] = 1'bx;
`ifndef XIL_TIMING
assign D_dly = D;
assign CLK_dly = CLK;
assign CE_dly = CE;
`endif
assign clk_is_inverted = IS_CLK_INVERTED;
assign CLK_in = clk_is_inverted ^ CLK_dly;
assign D_in = D_dly ;
assign CE_in = CE_dly ;
specify
(A[0] => Q) = (0:0:0, 0:0:0);
(A[1] => Q) = (0:0:0, 0:0:0);
(A[2] => Q) = (0:0:0, 0:0:0);
(A[3] => Q) = (0:0:0, 0:0:0);
(A[4] => Q) = (0:0:0, 0:0:0);
(CLK => Q) = (0:0:0, 0:0:0);
(CLK => Q31) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:38:23 04/26/2015
// Design Name:
// Module Name: register_file
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module register_file(
input clock,
input flush,
input [2:0] read_adr_1,
input [2:0] read_adr_2,
input [15:0] write_data,
input [2:0] write_adr,
input write_en,
output reg [15:0] data_out_1,
output reg [15:0] data_out_2
);
reg [15:0] file [7:0];
integer i;
initial begin
for (i = 0; i < 8 ; i = i + 1) begin
file[i] = 16'h00;
end
data_out_1 = 0;
data_out_2 = 0;
end
always @(negedge clock) begin
if (write_en == 1) begin
file[write_adr] = write_data;
end
end
always @(posedge clock) begin
case (flush)
0: begin
data_out_1 = file[read_adr_1];
data_out_2 = file[read_adr_2];
end
1: begin
data_out_1 = 0;
data_out_2 = 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void reset(int& n, int first) { n = n & ~(1 << first); } bool check(int n, int first) { return (bool)(n & (1 << first)); } set<int> ax, ay; multiset<int> bx, by; set<int>::iterator l, r; int main() { int i, j, k, n, w, h; while (scanf( %d%d%d , &w, &h, &n) == 3) { ax.clear(); ay.clear(); bx.clear(); by.clear(); ax.insert(0); ax.insert(h); ay.insert(0); ay.insert(w); bx.insert(h); by.insert(w); for (i = 0; i < n; i++) { char ch; int v; scanf( %c%c%d , &ch, &ch, &v); if (ch == H ) { r = ax.lower_bound(v); l = --r; r++; bx.erase(bx.find(*r - *l)); ax.insert(v); bx.insert(v - *l); bx.insert(*r - v); } else { r = ay.lower_bound(v); l = --r; r++; by.erase(by.find(*r - *l)); ay.insert(v); by.insert(v - *l); by.insert(*r - v); } long long ans = (long long)(*bx.rbegin()) * (*by.rbegin()); cout << ans << endl; } } }
|
/*
File: earb.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eMesh Arbiter
########################################################################
This block takes three FIFO inputs (write, read request, read response),
arbitrates between the active channels, and forwards the result on to
the transmit channel.
The arbitration order is (fixed, highest to lowest)
1) read responses
2) read requests
3) writes
*/
module earb (/*AUTOARG*/
// Outputs
emwr_rd_en, emrq_rd_en, emrr_rd_en, emm_tx_access, emm_tx_write,
emm_tx_datamode, emm_tx_ctrlmode, emm_tx_dstaddr, emm_tx_srcaddr,
emm_tx_data,
// Inputs
clock, reset, emwr_rd_data, emwr_empty, emrq_rd_data, emrq_empty,
emrr_rd_data, emrr_empty, emm_tx_rd_wait, emm_tx_wr_wait, emtx_ack
);
// TX clock
input clock;
input reset;
// FIFO slave port, writes
input [102:0] emwr_rd_data;
output emwr_rd_en;
input emwr_empty;
// FIFO slave port, read requests
input [102:0] emrq_rd_data;
output emrq_rd_en;
input emrq_empty;
// FIFO slave port, read responses
input [102:0] emrr_rd_data;
output emrr_rd_en;
input emrr_empty;
// eMesh master port, to TX
output emm_tx_access;
output emm_tx_write;
output [1:0] emm_tx_datamode;
output [3:0] emm_tx_ctrlmode;
output [31:0] emm_tx_dstaddr;
output [31:0] emm_tx_srcaddr;
output [31:0] emm_tx_data;
input emm_tx_rd_wait;
input emm_tx_wr_wait;
// Ack from TX protocol module
input emtx_ack;
// Control bits inputs (none)
// output wires
wire emm_tx_access;
wire emm_tx_write;
wire [1:0] emm_tx_datamode;
wire [3:0] emm_tx_ctrlmode;
wire [31:0] emm_tx_dstaddr;
wire [31:0] emm_tx_srcaddr;
wire [31:0] emm_tx_data;
//############
//# Arbitrate & forward
//############
reg ready;
reg [102:0] fifo_data;
// priority-based ready signals
wire rr_ready = ~emrr_empty & ~emm_tx_wr_wait;
wire rq_ready = ~emrq_empty & ~emm_tx_rd_wait & ~rr_ready;
wire wr_ready = ~emwr_empty & ~emm_tx_wr_wait & ~rr_ready & ~rq_ready;
// FIFO read enables, when we're idle or done with the current datum
wire emrr_rd_en = rr_ready & (~ready | emtx_ack);
wire emrq_rd_en = rq_ready & (~ready | emtx_ack);
wire emwr_rd_en = wr_ready & (~ready | emtx_ack);
always @ (posedge clock) begin
if( reset ) begin
ready <= 1'b0;
fifo_data <= 'd0;
end else begin
if( emrr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrr_rd_data;
end else if( emrq_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrq_rd_data;
end else if( emwr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emwr_rd_data;
end else if( emtx_ack ) begin
ready <= 1'b0;
end
end // else: !if( reset )
end // always @ (posedge clock)
//#############################
//# Break-out the emesh signals
//#############################
assign emm_tx_access = ready;
assign emm_tx_write = fifo_data[102];
assign emm_tx_datamode = fifo_data[101:100];
assign emm_tx_ctrlmode = fifo_data[99:96];
assign emm_tx_dstaddr = fifo_data[95:64];
assign emm_tx_srcaddr = fifo_data[63:32];
assign emm_tx_data = fifo_data[31:0];
endmodule // earb
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(time(0)); const long long inf = 0x3f3f3f3f3f3f3f3fLL; const long long N = 35; const long long MOD = 1e9 + 7; long long n, u, r, ans = -inf; long long a[N], b[N], k[N], p[N], dp[N][N]; void go(long long pos, long long lst) { if ((u - pos) % 2 == 0) { long long cur = 0; for (long long i = 1; i <= n; i++) cur += dp[pos][i] * k[i]; ans = max(ans, cur); if (pos == u) return; } if (!lst) { for (long long i = 1; i <= n; i++) dp[pos + 1][i] = dp[pos][i] ^ b[i]; go(pos + 1, 1); } for (long long i = 1; i <= n; i++) dp[pos + 1][i] = dp[pos][p[i]] + r; go(pos + 1, 0); } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> u >> r; for (long long i = 1; i <= n; i++) cin >> a[i], dp[0][i] = a[i]; for (long long i = 1; i <= n; i++) cin >> b[i]; for (long long i = 1; i <= n; i++) cin >> k[i]; for (long long i = 1; i <= n; i++) cin >> p[i]; go(0, 0); cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X, SLEEP_B, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; signed main() { long long n; cin >> n; vector<long long> left; vector<long long> right; long long ok = 0; for (long long i = 0; i < n; i++) { string s; cin >> s; long long l = 0, r = 0; for (auto it : s) { if (it == ( ) { l++; } else if (it == ) && l != 0) { l--; } else { r++; } } if (r == 0 && l != 0) { left.push_back(l); } if (r != 0 && l == 0) { right.push_back(r); } if (r == 0 && l == 0) { ok++; } } sort(left.begin(), left.end()); sort(right.begin(), right.end()); long long r = 0; long long ans = 0; for (long long l = 0; l < left.size(); l++) { long long cur = left[l]; while (r < right.size() && right[r] < cur) { r++; } if (r < right.size() && right[r] == cur) { r++; ans++; } if (r == right.size()) break; } ans += ok / 2; cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, temp; cin >> n; vector<int> num; while (n != 0) { cin >> temp; num.push_back(temp); n--; } sort(num.begin(), num.end()); int smallest = 1; for (int i = 0; i < num.size(); i++) { if (smallest != num[i]) { break; } smallest++; } cout << smallest; return 0; }
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_prbs_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel use LFSR to generate random address, isntructions
// or burst_length.
//Reference:
//Revision History: 1.1 Added condition to zero out the LSB address bits according to
// DWIDTH and FAMILY. 7/9/2009
//
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_cmd_prbs_gen_axi #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // 64,15,20
parameter SEED_WIDTH = 32, // 32,15,4
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input clk_en,
input [SEED_WIDTH-1:0] prbs_seed_i,
output[SEED_WIDTH-1:0] prbs_o // generated address
);
wire[ADDR_WIDTH - 1:0] ZEROS;
reg [SEED_WIDTH - 1:0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
assign ZEROS = 'b0;
//
//**************************************************************
//####################################################################################################################
// #
// #
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
// upper 32 bits are loadable #
// #
//
//
// ........................................................................................
// ^ ^ ^ ^ |
// | ____ | ___ ___ | ___ | ___ ___ ___ |
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
// we need to provide 30 bits addres. SRLC32 has only one bit output.
// address seed will be loaded to upper 32 bits.
//
// parallel load and serial shift out to LFSR during INIT time
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
end else if(clk_en) begin
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= #TCQ lfsr_q[62];
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
lfsr_q[1] <= #TCQ lfsr_q[64];
end
end
always @(lfsr_q[32:1]) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
function integer logb2;
input [31:0] in;
integer i;
begin
i = in;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {prbs_seed_i};
end else if(clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
integer i;
always @(lfsr_q[32:1]) begin
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
end
else begin
for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}};
end
end
end endgenerate
//////////////////////////////////////////////////////////////////////////
//####################################################################################################################
// #
// #
// 15 taps: [15,14]: #
// #
// #
//
//
// .............................................................
// ^ ^ . ^
// | ____ | ___ ___ ___ ___ ___ |
// | | | |---|<- | | | | | |...| | | | |
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
// |___| --- |___| |___| |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
generate
if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
always @(posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
end else if(clk_en) begin
lfsr_q[20] <= #TCQ lfsr_q[19];
lfsr_q[19] <= #TCQ lfsr_q[18];
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
lfsr_q[1] <= #TCQ lfsr_q[20];
end
end
always @ (lfsr_q) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
assign prbs_o = prbs;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; int vis[26], cnt[26], h[26]; set<int> e[26]; vector<string> S[1005]; int mp[26]; bool operator<=(string a, string b) { for (int i = 0; i < min(a.size(), b.size()); i++) { if (a[i] == b[i]) continue; return mp[a[i] - a ] < mp[b[i] - a ]; } return a.size() <= b.size(); } int main() { ios_base::sync_with_stdio(false); string s; int n, k, p; cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> p; for (int i = 1; i <= k; i++) { cin >> s, S[p].push_back(s); for (char c : s) h[c - a ] = 1; } } vector<string> v; for (int i = 0; i < n; i++) for (string s : S[i]) v.push_back(s); for (int i = 1; i < v.size(); i++) { string &s1 = v[i - 1], &s2 = v[i]; for (int i = 0; i < min(s1.size(), s2.size()); i++) { if (s1[i] != s2[i]) { int c1 = s1[i] - a , c2 = s2[i] - a ; if (e[c1].find(c2) == e[c1].end()) e[c1].insert(c2), cnt[c2]++; break; } } } vector<int> q; int m = 0; for (int i = 0; i < 26; i++) m += (h[i]); for (int i = 0; i < 26; i++) if (cnt[i] == 0 and h[i]) q.push_back(i); for (int k = 0; k < q.size(); k++) { int i = q[k]; vis[i] = 1; for (int j : e[i]) { if (vis[j]) continue; cnt[j]--; if (cnt[j] == 0) q.push_back(j); } } bool ok = 1; for (int i = 0; i < q.size(); i++) mp[q[i]] = i; for (int i = 1; i < v.size(); i++) ok &= (v[i - 1] <= v[i]); if (q.size() != m or !ok) cout << IMPOSSIBLE << n , exit(0); for (int i : q) cout << (char)(i + a ); return 0; }
|
/*
* DE0Nano_Button.v
*
* ___ _ _ _ _ ___ _ _ ___
* | __._ _ _| |_ ___ _| |_| |___ _| | . | \ |_ _|
* | _>| ' ' | . / ._/ . / . / ._/ . | | || |
* |___|_|_|_|___\___\___\___\___\___|_|_|_\_||_|
*
*
* Created on : 20/06/2015
* Author : Ernesto Andres Rincon Cruz
* Web : www.embeddedant.org
* Device : EP4CE22F17C6N
* Board : DEO-NANO
*
* Revision History:
* Rev 1.0.0 - (ErnestoARC) First release 20/06/2015.
*/
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE0Nano_Button(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY
);
//=======================================================
// PARAMETER declarations
//=======================================================
parameter LED_SEQUENCE_0 =8'b10000000;
parameter LED_SEQUENCE_1 =8'b01000000;
parameter LED_SEQUENCE_2 =8'b00100000;
parameter LED_SEQUENCE_3 =8'b00010000;
parameter LED_SEQUENCE_4 =8'b00001000;
parameter LED_SEQUENCE_5 =8'b00000100;
parameter LED_SEQUENCE_6 =8'b00000010;
parameter LED_SEQUENCE_7 =8'b00000001;
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg [7:0]LedsState=LED_SEQUENCE_0;
reg [7:0]LedsNextState;
wire Clock_Sequence;
reg SequenceControl=0;
wire Btn1_Signal;
wire Btn2_Signal;
//Frequency Divider Module
ClockDivider #(.Bits_counter (28)) DIVIDER_A
( .P_CLOCK(CLOCK_50),
.P_TIMER_OUT(Clock_Sequence),
.P_COMPARATOR(28'd16000000));
// Debounce circuir for Button1
DeBounce DebBtn1 (
.clk(CLOCK_50),
.n_reset(1'b1),
.button_in(KEY[0]),
.DB_out(Btn1_Signal)
);
// Debounce circuir for Button2
DeBounce DebBtn2 (
.clk(CLOCK_50),
.n_reset(1'b1),
.button_in(KEY[1]),
.DB_out(Btn2_Signal)
);
//=======================================================
// Structural coding
//=======================================================
// Leds Sequence control
always @(*)
begin
case (LedsState)
LED_SEQUENCE_0:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_1;
else
LedsNextState=LED_SEQUENCE_7;
end
LED_SEQUENCE_1:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_2;
else
LedsNextState=LED_SEQUENCE_0;
end
LED_SEQUENCE_2:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_3;
else
LedsNextState=LED_SEQUENCE_1;
end
LED_SEQUENCE_3:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_4;
else
LedsNextState=LED_SEQUENCE_2;
end
LED_SEQUENCE_4:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_5;
else
LedsNextState=LED_SEQUENCE_3;
end
LED_SEQUENCE_5:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_6;
else
LedsNextState=LED_SEQUENCE_4;
end
LED_SEQUENCE_6:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_7;
else
LedsNextState=LED_SEQUENCE_5;
end
LED_SEQUENCE_7:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_0;
else
LedsNextState=LED_SEQUENCE_6;
end
default:
LedsNextState=LED_SEQUENCE_0;
endcase
end
// Led direction control
always @ (posedge CLOCK_50)
begin
if (Btn1_Signal==0)
SequenceControl<=0;
else if (Btn2_Signal==0)
SequenceControl<=1;
else
SequenceControl<=SequenceControl;
end
// Leds sequence registers
always @ (posedge Clock_Sequence)
begin
LedsState<=LedsNextState;
end
//=======================================================
// Connections & assigns
//=======================================================
assign LED = LedsState;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_8_V
`define SKY130_FD_SC_MS__BUF_8_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__buf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__buf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_8_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_FUNCTIONAL_PP_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_FUNCTIONAL_PP_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file DMem.v when simulating
// the core, DMem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module DMem(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [5 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(6),
.C_ADDRB_WIDTH(6),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(64),
.C_READ_DEPTH_B(64),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(64),
.C_WRITE_DEPTH_B(64),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 96; const int MAXN = 1e6 + 5; const int MAXK = 8e6 + 5; const int MOD = 1e9 + 7; const int MAX_ASCII_CODE = 26; const int MAX_NUMBER_OF_NODES = 1e5 + 5; int n, m; int arr[MAXN]; int rea[MAXK]; int foo(int v) { if (v == 0) return -2; if (rea[v] != -1) return rea[v]; if (rea[v] == -2) return -2; int ho = -2; for (int i = (int)0; i < (int)(22); i++) { if ((v & (1 << i)) > 0) { ho = max(foo((v ^ (1 << i))), ho); } } rea[v] = ho; return rea[v]; } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(NULL); cout << fixed << setprecision(11); int t = 1; while (t--) { cin >> n; memset(rea, -1, sizeof(rea)); for (int i = (int)0; i < (int)(n); i++) { cin >> arr[i]; rea[arr[i]] = arr[i]; } int t; int no = (1 << 22) - 1; for (int i = (int)0; i < (int)(n); i++) { t = arr[i]; t = (no ^ arr[i]); cout << max(-1, foo(t)) << ; } cout << n ; } }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:46 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top RAT_slice_1_0_0 -prefix
// RAT_slice_1_0_0_ RAT_slice_12_3_0_sim_netlist.v
// Design : RAT_slice_12_3_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_slice_12_3_0,xlslice,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "xlslice,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_slice_1_0_0
(Din,
Dout);
input [17:0]Din;
output [7:0]Dout;
wire [17:0]Din;
assign Dout[7:0] = Din[7:0];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int maxN = 1000 * 1000 + 50; vector<int> v[maxN]; int cnt; bool mark[maxN]; void dfs(int s) { mark[s] = 1; cnt++; for (int i = 0; i < v[s].size(); i++) if (mark[v[s][i]] == 0) dfs(v[s][i]); } int main() { int n, m, k, sum = 0, com = 0; cin >> n >> m >> k; for (int i = 1; i <= m; i++) { int a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } for (int i = 1; i <= n; i++) if (mark[i] == 0) { com++; cnt = 0; dfs(i); sum += min(k, cnt); } if (k == 1) cout << max(0, com - 2) << endl; else cout << max(0, com - 1 - (sum / 2)) << endl; return 0; }
|
// This module will display the input values on the DE0 GPIO BOARD
// It requires the DE0 CLOCK_50 signal to be connected to it's clock input
// all other inputs can just use whatever data should be displayed.
// The one output, GPIO_0, should be connected to GPIO0_D (all 32 bits are used)
// This module works by selecting 1 of eight rows/7-seg displays at a time
// and multiplexing through the desired output signals.
module GPIO_Board(
clock_50,
R0, R1, R2, R3, R4, R5, R6, R7,
HEX0, HEX0_DP, HEX1, HEX1_DP,
HEX2, HEX2_DP, HEX3, HEX3_DP,
HEX4, HEX4_DP, HEX5, HEX5_DP,
HEX6, HEX6_DP, HEX7, HEX7_DP, GPIO_0);
input [15:0] R0, R1, R2, R3, R4, R5, R6, R7;
input [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
input HEX0_DP, HEX1_DP, HEX2_DP, HEX3_DP, HEX4_DP, HEX5_DP, HEX6_DP, HEX7_DP;
input clock_50;
output [31:0]GPIO_0;
// create a 17 bit counter to manage the timing of displaying the information
// bits 16:14 will be used at the 3 bit row counter / signal multiplexer select
// bits 13:11 will be used to disable the row output right before and right after
// the counter changes. This is to avoid ghosting on the display caused by hardware
// switching delay
reg [16:0]count;
wire [2:0]count3bit;
// 17 bit counter
initial
count <= 17'b0;
always @(posedge clock_50)
count <= count + 1'b1;
// create a logic circuit which will output a 0 when count[13:11] are 000 or 111
// this signal will be ANDed with the row output in order to disable the row output
// when the count3bit is close to changing.
wire row_gate;
// comment out this line and uncomment the next line to see what ghosting looks like
assign row_gate = (count[13:11] == 3'b0 || count[13:11] == 3'b111) ? 1'b0 : 1'b1;
//assign row_gate = 1'b1;
assign count3bit = count[16:14];
// use a 16 bit 8:1 MUX to select between the row input signals (R0 to R7)
wire [15:0] matrix_columns2, matrix_columns;
// output the mux to matrix_columns2 and then flip the order of the bits to display the
// binary value with the LSb on the right
mux_8to1_16bit matrix_mux(matrix_columns2, count3bit, R0, R1, R2, R3, R4, R5, R6, R7);
// flip the bits
assign matrix_columns = {matrix_columns2[0], matrix_columns2[1], matrix_columns2[2], matrix_columns2[3]
, matrix_columns2[4], matrix_columns2[5], matrix_columns2[6], matrix_columns2[7]
, matrix_columns2[8], matrix_columns2[9], matrix_columns2[10], matrix_columns2[11]
, matrix_columns2[12], matrix_columns2[13], matrix_columns2[14], matrix_columns2[15]};
// use a 8-bit 8:1 MUX to select between hex input signals (HEX0 to HEX7)
// concatenate the decimal point input with the 7-segment signal to make a 8-bit signal
wire [7:0] hex_segments;
mux8to1_8bit hex_mux(hex_segments, count3bit,
{HEX0_DP, HEX0}, {HEX1_DP, HEX1},
{HEX2_DP, HEX2}, {HEX3_DP, HEX3},
{HEX4_DP, HEX4}, {HEX5_DP, HEX5},
{HEX6_DP, HEX6}, {HEX7_DP, HEX7},
);
// use a 3-to-8 decoder to select which row to power based on the count3bit value
wire [7:0]rowa;
decoder3to8 row_dec(count3bit, rowa[0], rowa[1], rowa[2], rowa[3], rowa[4], rowa[5], rowa[6], rowa[7]);
// AND the row output of the decoder with the row_gate signal to disable the row output when close
// to switching
wire [7:0]row;
assign row = row_gate ? rowa : 8'b0;
// connect the signals to the GPIO0 output
assign GPIO_0 = {hex_segments, matrix_columns, row};
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_mask_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_mask_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_mask_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_mask_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 10005, M = 105; int n; char s[N]; int p, m; int lim; int dp[2][N][M]; int ch[N][2], tot = 1; int fa[N]; void dfs(int u) { if (!ch[u][0]) return; dfs(ch[u][0]); dfs(ch[u][1]); for (int i = 0; i <= lim; i++) for (int j = 0; i + j <= lim; j++) { dp[0][u][i + j + (p < m)] = max(dp[0][u][i + j + (p < m)], dp[0][ch[u][0]][i] + dp[0][ch[u][1]][j]); dp[0][u][i + j + (p >= m)] = max(dp[0][u][i + j + (p >= m)], dp[0][ch[u][0]][i] - dp[1][ch[u][1]][j]); dp[1][u][i + j + (p < m)] = min(dp[1][u][i + j + (p < m)], dp[1][ch[u][0]][i] + dp[1][ch[u][1]][j]); dp[1][u][i + j + (p >= m)] = min(dp[1][u][i + j + (p >= m)], dp[1][ch[u][0]][i] - dp[0][ch[u][1]][j]); } return; } int main() { scanf( %s , s + 1); scanf( %d%d , &p, &m); n = strlen(s + 1); lim = min(p, m); memset(dp[0], -63, sizeof(dp[0])); memset(dp[1], 63, sizeof(dp[1])); tot = 1; int pre = tot; for (int i = 1; i <= n; i++) { if (s[i] == ( || s[i] == ? ) { ch[pre][ch[pre][0] ? 1 : 0] = ++tot; fa[tot] = pre; pre = tot; } else if (s[i] == ) ) pre = fa[pre]; else dp[0][tot][0] = dp[1][tot][0] = s[i] - 0 , pre = fa[pre]; } dfs(1); printf( %d , dp[0][1][lim]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2B_1_V
`define SKY130_FD_SC_HDLL__AND2B_1_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2B_1_V
|
`timescale 1ns / 1ps
`default_nettype none //To avoid bugs involving implicit nets
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Acknowledgements: Prof. Kyle Gilsdorf (Arizona State)
// - http://www.public.asu.edu/~kyle135/
// -
//
//
// Author: Rushang Vinod Vandana Karia
// - Masters in Computer Science @ Arizona State
// -
// -
// - github.com/RushangKaria
//
//
// Module: System_Control_Unit.v
//
// Description : This module uses a PLL to stabilize all the clocks
// and also generates a global reset
//
// Copyright : Copyright (C) 2014 Rushang Vinod Vandana Karia
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
module System_Control_Unit
(
input wire CLK_I, //Input System Clock
input wire RSTN_I, //Input Reset
input wire [7:0] SW_I,
output wire CLK_O, //Output Stable Clock
output wire TFT_CLK_O, //Output Stable TFT Clock
output wire TFT_CLK_180_O,
output wire [3:0] MSEL_O,
output wire ASYNC_RST //Global Asynchronous Reset
);
///////////////////////////////////////////////////////////////////////
// MODULE SPECIFIC PARAMETER DECLARATIONS
///////////////////////////////////////////////////////////////////////
parameter integer RST_SYNC_NUM = 100;
parameter integer RST_DBNC = 10;
parameter integer RST_SYNC_NUM_LENGTH = $clog2(RST_SYNC_NUM);
parameter VDD = 1'b1;
parameter GROUND = 1'b0;
genvar i;
///////////////////////////////////////////////////////////////////////////////////////
// SIGNALS LOCAL TO MODULE
///////////////////////////////////////////////////////////////////////////////////////
wire Start_Up_Rst;
wire DcmRst;
reg DcmLckd;
wire SysConCLK;
reg [RST_DBNC-1:0] RstDbncQ;
reg [RST_DBNC-1:0] RstDbncTemp;
wire intRst;
reg intfb;
reg intpllout_xs;
reg [7:0] int_sw;
reg [RST_SYNC_NUM-1:0] RstQ;
reg [RST_SYNC_NUM_LENGTH:0] RstD;
wire RstDbnc;
wire int_TFTClk;
///////////////////////////////////////////////////////////////////////////////////////
// SYNTHESIS SPECIFIC INSTRUCTIONS
///////////////////////////////////////////////////////////////////////////////////////
//synthesis attribute KEEP of async_rst is "TRUE"
initial
begin
RstQ[RST_SYNC_NUM-1] = 0;
RstQ[RST_SYNC_NUM-2:0] = {RST_SYNC_NUM-1{1'b1}};
RstD[RST_SYNC_NUM_LENGTH:0] = {1'b1,RST_SYNC_NUM[RST_SYNC_NUM_LENGTH-1:0]};
end
///////////////////////////////////////////////////////////////////////////////////////
// COMPONENT INSTANTIATIONS :: These are required core files for the architecture
// :: These are board specific implementations so may not
// :: work for different architectures
///////////////////////////////////////////////////////////////////////////////////////
IBUFG IBUGF_inst
(
.O (SysConCLK), //Stable clock
.I (CLK_I) //Input unstable clock
);
assign CLK_O = SysConCLK;
dcm_TFT9 DCM_inst //Digital control manager. To generate clock for the TFT @ 9Mhz
(
.CLK_IN1 (SysConCLK), //Clock in
.CLK9 (int_TFTClk), //Clock out @ 9MHz
.CLK9_180 (TFT_CLK_180_O), //Clock out @ 9MHz out of phase with CLK9
.RESET (DcmRst), //Status and Control
.LOCKED (DcmLckd) //Status and Control
);
SRL16 #(
.INIT (16'h000F)
)
SRL16_inst
(
.CLK (SysConCLK), //Input Clock
.Q (Start_Up_Rst), //Data output
.A0 (VDD), //Select this line
.A1 (VDD), //Select this line
.A2 (GROUND), //Do not select this line
.A3 (GROUND), //Do not select this line
.D (GROUND) //SRL data input
);
assign TFT_CLK_O = int_TFTClk; //Assign the TFT clock
//////////////////////////////////////////////////////////
// DEBOUNCE RESET
//////////////////////////////////////////////////////////
always@(RSTN_I)
RstDbncQ[0] = ~RSTN_I;
generate
for(i=1;i<RST_DBNC;i=i+1)
always@(posedge SysConCLK)
RstDbncQ[i] <= RstDbncQ[i-1];
endgenerate
always@(RstDbncQ[0])
RstDbncTemp[0] = RstDbncQ[0];
generate
for(i=1;i<RST_DBNC-1;i=i+1)
always@*
RstDbncTemp[i] <= RstDbncTemp[i-1] & RstDbncQ[i];
endgenerate
assign RstDbnc = RstDbncTemp[RST_DBNC-2] & ~RstDbncQ[RST_DBNC-1];
//////////////////////////////////////////////////////////
// RESET WITH TAKE-OFF AND LANDING
//////////////////////////////////////////////////////////
always@(posedge SysConCLK)
if(RstDbnc || RstQ[RST_SYNC_NUM-1])
RstQ <= {RstQ[RST_SYNC_NUM-2:0],RstQ[RST_SYNC_NUM-1]};
assign DcmRst = ~RstQ[RST_SYNC_NUM-2] || ~RstQ[RST_SYNC_NUM-3] || ~RstQ[RST_SYNC_NUM-4] || Start_Up_Rst;
assign intRst = ~DcmLckd;
always@(posedge SysConCLK)
if(intRst)
RstD <= {1'b1,RST_SYNC_NUM[RST_SYNC_NUM_LENGTH-1:0]};
else if(RstD[RST_SYNC_NUM_LENGTH])
RstD <= RstD - 1;
assign ASYNC_RST = RstQ[RST_SYNC_NUM-1] || RstD[RST_SYNC_NUM_LENGTH];
//////////////////////////////////////////////////////////
// SYNCHRONIZE ASYNC SWITCH INPUTS WITH TFT CLOCK
//////////////////////////////////////////////////////////
InputSyncV #(
.WIDTH (4)
)
sync_sw
(
.CLK_I (int_TFTClk),
.D_I (SW_I[3:0]),
.D_O (MSEL_O)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_2_V
`define SKY130_FD_SC_HS__TAPMET1_2_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog wrapper for tapmet1 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__tapmet1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__tapmet1_2 (
VPWR,
VGND
);
input VPWR;
input VGND;
sky130_fd_sc_hs__tapmet1 base (
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__tapmet1_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__tapmet1 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_2_V
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module shift_right_32(
input[31:0] a, //value to be shifted
output[31:0] out //output
);
//shifts everything right by 1
assign out[0] = a[1];
assign out[1] = a[2];
assign out[2] = a[3];
assign out[3] = a[4];
assign out[4] = a[5];
assign out[5] = a[6];
assign out[6] = a[7];
assign out[7] = a[8];
assign out[8] = a[9];
assign out[9] = a[10];
assign out[10] = a[11];
assign out[11] = a[12];
assign out[12] = a[13];
assign out[13] = a[14];
assign out[14] = a[15];
assign out[15] = a[16];
assign out[16] = a[17];
assign out[17] = a[18];
assign out[18] = a[19];
assign out[19] = a[20];
assign out[20] = a[21];
assign out[21] = a[22];
assign out[22] = a[23];
assign out[23] = a[24];
assign out[24] = a[25];
assign out[25] = a[26];
assign out[26] = a[27];
assign out[27] = a[28];
assign out[28] = a[29];
assign out[29] = a[30];
assign out[30] = a[31];
assign out[31] = a[31];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_TB_V
`define SKY130_FD_SC_MS__FILL_DIODE_TB_V
/**
* fill_diode: Fill diode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fill_diode.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ms__fill_diode dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_TB_V
|
/*
* This module handles duration of note, style of play (i.e. normal, staccato or slurred) and BPM control.
*/
module timing_controller (CLK, BPM, MODE, NOTE, START, EN, DONE);
input CLK; // 100 MHz clock
input [1:0] MODE; // Note style
input [3:0] NOTE; // Note type, e.g. crotchet
input START; // Start flag to enable playback
input [7:0] BPM; // 8-bit BPM value
output reg EN; // Output enable (to control duration)
wire [15:0] DURATION; // Note duration
output reg DONE; // Flag to request the next note
reg [15:0] counter;
parameter
NORMAL = 2'b00,
STACCATO = 2'b01,
SLURRED = 2'b10,
BPM_COMM = 2'b11;
duration_lut dur_lut_blk (NOTE[3:0], DURATION);
BPM_prescaler bpm_pre_blk (CLK, BPM, slowCLK);
initial begin
EN <= 1;
counter <= 0;
DONE <= 0;
end
// Do something so that all the notes start at the beginning of a tone
// Perhaps an output to the top module to draw notes from.
// OR: Just have a slower build up in volume
always @ (posedge slowCLK) begin
if (START) begin
DONE <= 0;
counter <= counter + 1;
case (MODE)
NORMAL : begin if (counter <= DURATION/128*125) EN <= 1; else EN <= 0; end
STACCATO: begin if (counter <= DURATION/128*102) EN <= 1; else EN <= 0; end
SLURRED : begin if (counter <= DURATION) EN <= 1; end
endcase
// Reset counter once duration reached
if (counter == DURATION) begin
counter <= 0;
DONE <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { map<string, int> mp; vector<string> vec; string s; int n, m, v; double k; cin >> n >> m >> k; for (int i = 0; i < n; i++) { cin >> s >> v; if (v >= 100) { mp[s] = k * v + 1e-9; if (mp[s] >= 100) vec.push_back(s); else mp[s] = 0; } } for (int i = 0; i < m; i++) { cin >> s; if (!mp[s]) vec.push_back(s); } sort(vec.begin(), vec.end()); cout << vec.size() << n ; for (int i = 0; i < vec.size(); i++) { cout << vec[i] << << mp[vec[i]] << n ; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: LINEALIZADOR_NORMALIZADOR
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module LINEALIZADOR_NORMALIZADOR(
//INPUTS
input wire CLK,
input wire [31:0] I,
input wire [31:0] V,
input wire RST_LN_FF,
input wire Begin_FSM_I,
input wire Begin_FSM_V,
//OUTPUTS
output wire ACK_I,
output wire ACK_V,
output wire [31:0] RESULT_I,
output wire [31:0] RESULT_V
);
wire ACK_LN;
wire ACK_FF;
wire [31:0] LINEAL;
LINEALIZADOR #(.P(32)) LINEALIZADOR_FLOAT (
.CLK(CLK), //system clock
.T(I), //VALOR DEL ARGUMENTO DEL LOGARITMO QUE SE DESEA CALCULAR
.RST_LN(RST_LN_FF), //system reset
.Begin_FSM_LN(Begin_FSM_I), //INICIAL EL CALCULO
.ACK_LN(ACK_LN), //INDICA QUE EL CALCULO FUE REALIZADO
.O_FX(), //BANDERA DE OVER FLOW X
.O_FY(), //BANDERA DE OVER FLOW Y
.O_FZ(), //BANDERA DE OVER FLOW Z
.U_FX(), //BANDERA DE UNDER FLOW X
.U_FY(), //BANDERA DE UNDER FLOW Y
.U_FZ(), //BANDERA DE UNDER FLOW Z
.RESULT(LINEAL) //RESULTADO FINAL
);
I_NORM_FLOAT_TO_FIXED NORM_I_FLOAT_FIXED(
.CLK(CLK), //system clock
.F(LINEAL), //VALOR BINARIO EN COMA FLOTANTE
.RST_FF(RST_LN_FF), //system reset
.Begin_FSM_FF(ACK_LN), //INICIA LA CONVERSION
.ACK_FF(ACK_I), //INDICA QUE LA CONVERSION FUE REALIZADA
.RESULT(RESULT_I) //RESULTADO FINAL
);
/*V_NORM_FLOAT_TO_FIXED NORM_V_FLOAT_FIXED(
.CLK(CLK), //system clock
.F(V), //VALOR BINARIO EN COMA FLOTANTE
.RST_FF(RST_LN_FF), //system reset
.Begin_FSM_FF(Begin_FSM_V), //INICIA LA CONVERSION
.ACK_FF(ACK_V), //INDICA QUE LA CONVERSION FUE REALIZADA
.RESULT(RESULT_V) //RESULTADO FINAL
);*/
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : xaw2verilog
// / / Filename : DCM_Scope.v
// /___/ /\ Timestamp : 10/02/2020 08:51:22
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle D:/prj/sd2snes/verilog/sd2snes_sdd1/ipcore_dir/DCM_Scope.xaw -st DCM_Scope.v
//Design Name: DCM_Scope
//Device: xc3s400-4pq208
//
// Module DCM_Scope
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_INST = 0.07 UI
// Period Jitter (Peak-to-Peak) for block DCM_INST = 0.75 ns
`timescale 1ns / 1ps
module DCM_Scope(CLKIN_IN,
RST_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(41.667), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("TRUE") )
DCM_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
module testbench;
localparam integer PERIOD = 12000000 / 9600;
// reg clk = 0;
// initial #10 forever #5 clk = ~clk;
reg clk;
always #5 clk = (clk === 1'b0);
reg RX = 1;
wire TX;
wire LED1;
wire LED2;
wire LED3;
wire LED4;
wire LED5;
top uut (
.clk (clk ),
.RX (RX ),
.TX (TX ),
.LED1(LED1),
.LED2(LED2),
.LED3(LED3),
.LED4(LED4),
.LED5(LED5)
);
task send_byte;
input [7:0] c;
integer i;
begin
RX <= 0;
repeat (PERIOD) @(posedge clk);
for (i = 0; i < 8; i = i+1) begin
RX <= c[i];
repeat (PERIOD) @(posedge clk);
end
RX <= 1;
repeat (PERIOD) @(posedge clk);
end
endtask
reg [4095:0] vcdfile;
initial begin
if ($value$plusargs("vcd=%s", vcdfile)) begin
$dumpfile(vcdfile);
$dumpvars(0, testbench);
end
repeat (10 * PERIOD) @(posedge clk);
// turn all LEDs off
send_byte("1");
send_byte("3");
send_byte("5");
// turn all LEDs on
send_byte("1");
send_byte("2");
send_byte("3");
send_byte("4");
send_byte("5");
// turn all LEDs off
send_byte("1");
send_byte("2");
send_byte("3");
send_byte("4");
send_byte("5");
repeat (10 * PERIOD) @(posedge clk);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e3 + 5; int a[maxn][maxn]; int col[maxn]; int deg[maxn]; bool vis[maxn]; int n; void recurse() { int piv = -1; for (int i = 1; i <= n; i++) { if (vis[i]) continue; if (deg[i] % 2 == 1) { piv = i; break; } } if (piv == -1) { for (int i = 1; i <= n; i++) { if (vis[i]) continue; col[i] = 0; } return; } vis[piv] = true; vector<int> adj; for (int i = 1; i <= n; i++) { if (vis[i]) continue; if (a[piv][i] == 1) { a[piv][i] = a[i][piv] = 0; adj.push_back(i); deg[i] -= 1; } } for (auto i : adj) { for (auto j : adj) { if (i == j) continue; if (a[i][j] == 1) { a[i][j] = 0; deg[i] -= 1; } else { a[i][j] = 1; deg[i] += 1; } } } recurse(); int cnt[] = {0, 0}; for (int i : adj) { cnt[col[i]] += 1; } col[piv] = cnt[0] % 2 == 0 ? 0 : 1; } void solve() { int m; cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) a[i][j] = 0; memset(deg, 0, sizeof deg); memset(vis, false, sizeof vis); for (int i = 1; i <= m; i++) { int p, q; cin >> p >> q; a[p][q] = a[q][p] = 1; deg[p] += 1; deg[q] += 1; } recurse(); cout << *max_element(col + 1, col + n + 1) + 1 << endl; for (int i = 1; i <= n; i++) cout << 1 + col[i] << ; cout << endl; } int main() { int t; cin >> t; while (t--) { solve(); } return 0; }
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: data_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:33 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module is used LFSR to generate random data for memory
// data write or memory data read comparison.The first data is
// seeded by the input prbs_seed_i which is connected to memory address.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module data_prbs_gen #
(
parameter TCQ = 100,
parameter EYE_TEST = "FALSE",
parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i"
parameter SEED_WIDTH = 32
)
(
input clk_i,
input clk_en,
input rst_i,
input [31:0] prbs_fseed_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH - 1:0] prbs_seed_i,
output [PRBS_WIDTH - 1:0] prbs_o // generated address
);
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
integer i;
always @ (posedge clk_i)
begin
if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up
// if (rst_i ) //reset it to a known good state to prevent it locks up
begin
lfsr_q <= #TCQ {prbs_seed_i + prbs_fseed_i[31:0] + 32'h55555555};
end
else if (clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
#include <bits/stdc++.h> using namespace std; using lli = long long int; using pii = pair<int, int>; using vi = vector<int>; using vb = vector<bool>; using vvi = vector<vector<int>>; using vlli = vector<long long int>; using vpii = vector<pair<int, int>>; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); lli n, k, a, x[100005], c[100005], money = 0; multiset<lli> unused; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> x[i]; cin >> a; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 1; i <= n; i++) { unused.insert(c[i]); while (!unused.empty() && k < x[i]) { auto temp = unused.begin(); k += a; money += *temp; unused.erase(temp); } if (k < x[i]) return cout << -1, 0; } cout << money; }
|
#include <bits/stdc++.h> using namespace std; int inp[105][105]; int a[105]; int b[105]; int temp[105]; int main() { int n, m; scanf( %d , &n); scanf( %d , &m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &inp[i][j]); for (int i = 0; i < m; i++) b[i] = inp[0][i]; int up = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) up = max(up, inp[i][j]); int prevk = 0; for (int i = 1; i <= n - 1; i++) { map<int, int> mp; for (int j = 0; j < m; j++) { temp[j] = inp[i][j] - b[j]; mp[temp[j]] = 1; } int currk = 0; if (mp.size() == 2) { int f = mp.rbegin()->first; int s = mp.begin()->first; if (max(f, s) >= 0 && min(f, s) <= 0) currk = max(s, f) - min(s, f); else currk = -1; } if (mp.size() > 2 || (currk && prevk && currk != prevk) || (currk != 0 && currk <= up)) { printf( NO n ); return 0; } prevk = max(prevk, currk); a[i] = max(mp.rbegin()->first, mp.begin()->first); } printf( YES n ); if (prevk == 0) prevk = 2e9 + 7; printf( %d n , prevk); for (int i = 0; i < n; i++) printf( %d , (a[i] >= 0) ? a[i] : (a[i] + prevk)); cout << endl; for (int i = 0; i < m; i++) printf( %d , b[i]); cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR3_PP_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; struct SquareMatrix { SquareMatrix(int _n) : n(_n) { data.assign(_n, vector<long long>(_n, 0)); } vector<long long> &operator[](int i) { return data[i]; } const vector<long long> &operator[](int i) const { return data[i]; } SquareMatrix operator*(const SquareMatrix &other) const { assert(n == other.n); SquareMatrix ret(n); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { for (int k = 0; k < n; ++k) { ret[i][j] = (ret[i][j] + data[i][k] * other[k][j]) % mod; } } } return ret; } vector<vector<long long>> data; int n; }; SquareMatrix quickpower(SquareMatrix m, long long p) { int n = m.n; SquareMatrix ret(n); for (int i = 0; i < n; ++i) ret[i][i] = 1; while (p) { if (p & 1) { ret = ret * m; } m = m * m; p >>= 1; } return ret; } int fun(int x) { int res = 0; while (x) { res += x % 2; x /= 2; } return res; } int main() { long long n, k, m; scanf( %lld %lld %lld , &n, &k, &m); long long num = 1 << m; SquareMatrix M(num * (k + 1)); for (int i = 0; i < num * (k + 1); i++) { int x = i % (k + 1); int y = i / (k + 1); int x1 = x; int y1 = (y * 2) % num; int x2 = x + 1; int y2 = (y * 2) % num + 1; M[i][y1 * (k + 1) + x1] += 1; if (x2 <= k) M[i][y2 * (k + 1) + x2] += fun(y) + 1ll; } M = quickpower(M, n); long long ans = 0; for (int i = 0; i < num; i++) ans = (ans + M[0][i * (k + 1) + k]) % mod; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { char c = getchar(); int x = 0, f = 1; for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; return x * f; } const int MAXN = 8e3 + 5; int nxt[MAXN], p[MAXN][MAXN], dp[MAXN]; int N, len; char s[MAXN], S[MAXN]; inline int calc(int x) { int ret = 0; while (x) x /= 10, ret++; return ret; } inline void KMP(int st) { len = N - st + 1; for (int i = 1; i <= len; i++) s[i] = S[st + i - 1]; int j = 0; for (int i = 2; i <= len; i++) { while (j && s[i] != s[j + 1]) j = nxt[j]; if (s[i] == s[j + 1]) j++; nxt[i] = j; } for (int i = 1; i <= len; i++) { int tmp = i - nxt[i]; if (i % tmp) tmp = i; p[st][st + i - 1] = tmp + calc(i / tmp); } } int main() { scanf( %s , S + 1); N = strlen(S + 1); for (int i = 1; i <= N; i++) KMP(i); memset(dp, 0x3f, sizeof(dp)); dp[0] = 0; for (int i = 1; i <= N; i++) for (int j = 0; j < i; j++) dp[i] = min(dp[i], dp[j] + p[j + 1][i]); printf( %d n , dp[N]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__OR2_FUNCTIONAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03:54:36 07/21/2013
// Design Name: dsha_finisher
// Module Name: C:/Dropbox/bc/fpga/test/dsha_finisher.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: dsha_finisher
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module dsha_finisher_test;
// Inputs
reg clk;
reg [255:0] X;
reg [95:0] Y;
reg [31:0] in_nonce;
// Outputs
wire [255:0] hash;
wire [31:0] out_nonce;
// Instantiate the Unit Under Test (UUT)
dsha_finisher uut (
.clk(clk),
.X(X),
.Y(Y),
.in_nonce(in_nonce),
.hash(hash),
.out_nonce(out_nonce)
);
parameter P=10;
always #(P/2) clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
X = 256'h356d66244c73b9f1e1a328b2c6615412a965a72218c5c19eb5c5d4073db86a04;
Y = 96'h1c2ac4af504e86edec9d69b1;
in_nonce = 32'hb2957c02;
uut.chunk1.roundnum = 6'h3e;
uut.chunk2.roundnum = 6'h3e;
#(135*P);
$finish();
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR3_BLACKBOX_V
`define SKY130_FD_SC_MS__XOR3_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, v = 0, p = 0; string s, result = ; cin >> n >> s; v = (n - 11) / 2; p = v; for (int i = 0; i < n; i++) { if (s[i] == 8 ) { if (v > 0) v--; else result += s[i]; } else { if (p > 0) p--; else result += s[i]; } } if (result[0] == 8 ) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 7; const int MOD = 1e9 + 7; int n; int h[MAXN]; int main() { int m, k, ta, tb; scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= m; i++) { scanf( %d , &ta); h[ta] = 1; } int cur = 1; if (!h[cur]) for (int i = 0; i < k; i++) { scanf( %d%d , &ta, &tb); if (ta != cur && tb != cur) continue; if (ta == cur && tb == cur) continue; if (ta != cur) swap(ta, tb); if (h[tb]) { printf( %d n , tb); return 0; } else { cur = tb; } } printf( %d n , cur); return 0; }
|
//
// bsg_tag_client
//
// simple serial on-chip configuration network
//
//
// 8/30/2016
//
// RESET SEMANTICS
//
// * NORMAL USAGE
//
// 0. wire bsg_tag_i.en high
// 1. assert reset on the send side of the module for at least one cycle (via bsg_tag_i)
// 2. clock the send side for one cycle.
// 3. clock the recv side for several cycles (for values to flush through synchronizers)
// 5. after resets are dropped, optionally start updating values on bsg_tag_s bus.
//
//
// * CLOCK GENERATOR NORMAL
//
// 0. follow steps 0-2 in NORMAL USAGE
// 1. pull bsg_tag_i.en low to disconnect bsg_tag
// 2. assert async_reset on clock gen
// 3. deassert async_reset on clock gen (clock starts)
// 4. after a few cycles
// 5. pull bsg_tag_i.en high to attach bsg_tag
//
// * CLOCK GENERATOR FAILSAFE
//
// 0. wire bsg_tag_i.en low
// 1. assert async_reset on clock gen
// 2. deassert async_reset
// 3. go
//
//
// note: operation of bsg_tag_i.en is only valid if there
// are no attempts to transmit data on bsg_tag at the same time
// otherwise it is a CDC violation.
`include "bsg_defines.v"
module bsg_tag_client
import bsg_tag_pkg::bsg_tag_s;
#(parameter `BSG_INV_PARAM(width_p), harden_p=1)
(
input bsg_tag_s bsg_tag_i
, input recv_clk_i
, output recv_new_r_o // optional; notifies of new value
, output [width_p-1:0] recv_data_r_o
);
localparam debug_level_lp = 1;
logic op_r, op_r_r, param_r;
always_ff @(posedge bsg_tag_i.clk)
begin
op_r <= bsg_tag_i.op;
param_r <= bsg_tag_i.param;
op_r_r <= op_r;
end
wire reset_op = ~op_r & param_r;
wire shift_op = op_r;
wire no_op = ~op_r & ~param_r;
// when this is high, tag_data_r is already transmitting data
// this control has another cycle of latency in this clock domain
// before passing into the next, which is important.
wire send_now = op_r_r & no_op;
logic [width_p-1:0] tag_data_r, recv_data_r, tag_data_n, tag_data_shift;
logic tag_toggle_r;
// shift in new state
if (width_p == 1)
begin : sb
assign tag_data_shift = { param_r };
end
else
begin : mb
assign tag_data_shift = { param_r, tag_data_r[width_p-1:1] };
end
bsg_mux2_gatestack #(.width_p(width_p),.harden_p(harden_p)) tag_data_mux
(.i0 (tag_data_r ) // sel=0
,.i1(tag_data_shift ) // sel=1
,.i2({ width_p {shift_op} }) // sel var
,.o (tag_data_n)
);
bsg_dff #(.width_p(width_p), .harden_p(harden_p)) tag_data_reg
(.clk_i(bsg_tag_i.clk)
,.data_i(tag_data_n)
,.data_o(tag_data_r)
);
// synopsys translate_off
if (debug_level_lp > 1)
always @(negedge bsg_tag_i.clk)
begin
if (reset_op & ~(~bsg_tag_i.op & bsg_tag_i.param))
$display("## bsg_tag_client (send) RESET DEASSERTED (%m)");
if (~reset_op & (~bsg_tag_i.op & bsg_tag_i.param))
$display("## bsg_tag_client (send) RESET ASSERTED (%m)");
if (send_now)
$display("## bsg_tag_client (send) SENDING %b (%m)",tag_data_r);
end
// synopsys translate_on
logic recv_toggle_r, recv_toggle_n;
// cross clock boundary
bsg_launch_sync_sync #(.width_p(1)) blss
(.iclk_i (bsg_tag_i.clk)
,.iclk_reset_i(reset_op)
,.iclk_data_i (tag_toggle_r ^ send_now)
,.iclk_data_o (tag_toggle_r) // this is the flop that is reset
,.oclk_i (recv_clk_i )
,.oclk_data_o(recv_toggle_n)
);
// note: bsg_tag_i.en is wired from off-chip and should be
// only toggled when there is no attempt to transmit data
wire recv_new = (recv_toggle_r ^ recv_toggle_n) & bsg_tag_i.en;
// we had to add recv_new_r_r to pipeline the receive logic
// and the fanout to the recv_data_r register at the maximum
// frequency on the chip (i.e. the clock generator)
logic recv_new_r, recv_new_r_r;
always_ff @(posedge recv_clk_i)
begin
recv_toggle_r <= recv_toggle_n;
recv_new_r <= recv_new;
recv_new_r_r <= recv_new_r;
end
bsg_dff_en #(.width_p(width_p),.harden_p(harden_p)) recv
(.clk_i(recv_clk_i)
,.en_i(recv_new_r)
,.data_i(tag_data_r)
,.data_o(recv_data_r)
);
// the recv_en_i signal has to come after the flop
// so this works even when the clock is not working
assign recv_new_r_o = recv_new_r_r & bsg_tag_i.en;
assign recv_data_r_o = recv_data_r;
endmodule
`BSG_ABSTRACT_MODULE(bsg_tag_client)
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