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`timescale 1 ns / 1 ps
module test;
/* verilator lint_off STMTDLY */
reg clk, rst;
reg [15:0] fm_data[0:65535];
reg [10:0] psg_data[0:21000];
reg [15:0] fm_snd=16'd0;
initial begin
$readmemh("data.hex",fm_data);
$readmemh("psg.hex",psg_data);
end
`ifdef FINISH_AT
initial
#((`FINISH_AT)*1000_000) $finish;
`endif
initial begin
rst = 1'b1;
#50;
rst = 1'b0;
//#10000000 $finish;
end
initial begin
clk = 0;
forever clk = #19 ~clk;
end
integer psgce_cnt;
reg psg_zero;
always @(posedge clk)
if( rst ) begin
psgce_cnt <= 0;
psg_zero <= 1'b0;
end else begin
if( psgce_cnt == 15*16 ) begin
psgce_cnt <= 0;
psg_zero <= 1'b1;
end else begin
psgce_cnt <= psgce_cnt+1;
psg_zero<= 1'b0;
end
end
integer psg_cnt;
reg [10:0] psg_snd;
always @(posedge clk)
if( rst ) begin
psg_cnt<=0;
psg_snd <= 11'd0;
end else if( psg_zero ) begin
psg_cnt<=psg_cnt==21000 ? 0 : psg_cnt+1;
psg_snd<=psg_data[psg_cnt];
end
integer zero_cnt;
reg fm_zero;
always @(posedge clk)
if( rst ) begin
zero_cnt <= 0;
fm_zero <= 1'b0;
end else begin
if( zero_cnt==1007 ) begin
zero_cnt<=0;
fm_zero <=1'b1;
end else begin
zero_cnt <= zero_cnt+1;
fm_zero <= 1'b0;
end
end
integer cnt;
always @(posedge clk)
if( rst ) begin
cnt<=0;
fm_snd <= 16'd0;
end else if( fm_zero ) begin
cnt<=cnt+1;
`ifndef NOFM
fm_snd<=fm_data[cnt<<1];
`endif
if(cnt>=30000) $finish;
end
wire signed [15:0] snd;
jt12_genmix u_mix(
.rst ( rst ),
.clk ( clk ),
.fm_snd ( fm_snd ),
.psg_snd ( psg_snd ),
.snd ( snd ) // Mixed sound at clk sample rate
);
initial begin
$dumpfile("test.lxt");
`ifdef DUMP_ALL
$dumpvars(0, test);
`endif
$dumpvars(1, test.u_mix.u_psg2);
$dumpvars(0,test.fm_snd);
$dumpvars(0,test.u_mix.fm2);
$dumpvars(0,test.u_mix.fm3);
$dumpvars(0,test.u_mix.fm4);
$dumpvars(0,test.u_mix.fm5);
$dumpvars(0,test.psg_snd);
$dumpvars(0,test.u_mix.psg1);
$dumpvars(0,test.u_mix.psg2);
$dumpvars(0,test.u_mix.psg3);
$dumpvars(0,test.u_mix.mixed);
$dumpon;
end
endmodule // test
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:59:48 04/01/2015
// Design Name: crc
// Module Name: /home/christopher/Documents/RL02Controller/RL02Controller/crc_tb.v
// Project Name: RL02Controller
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: crc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module crc_tb;
// Inputs
reg [0:0] data_in;
reg crc_en;
reg rst;
reg clk;
// Outputs
wire [15:0] crc_out;
// Instantiate the Unit Under Test (UUT)
crc uut (
.data_in(data_in),
.crc_en(crc_en),
.crc_out(crc_out),
.rst(rst),
.clk(clk)
);
initial begin
// Initialize Inputs
data_in = 0;
crc_en = 0;
rst = 1;
clk = 0;
toggle_clk;
rst = 0;
toggle_clk;
zero;
zero;
one;
one;
zero;
zero;
zero;
one;
zero;
one;
zero;
zero;
zero;
one;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
zero;
toggle_clk;
end
task one;
begin
data_in = 1;
crc_en = 1;
#10 clk = ~clk;
#10 clk = ~clk;
crc_en = 0;
end
endtask
task zero;
begin
data_in = 0;
crc_en = 1;
#10 clk = ~clk;
#10 clk = ~clk;
crc_en = 0;
end
endtask
task toggle_clk;
begin
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { if (a > b) { return a; } else { return b; } } long long min(long long a, long long b) { if (a < b) { return a; } else { return b; } } struct P { double x, y; P() {} P(double x, double y) : x(x), y(y) {} P operator+(const P &a) const { return P(x + a.x, y + a.y); } P operator-(const P &a) const { return P(x - a.x, y - a.y); } double operator^(const P &a) const { return x * a.x + y * a.y; } void in() { scanf( %lf%lf , &x, &y); } void out() { printf( REQUIRED %.7f %.7f n , x, y); } double dist(P a, P b) { return sqrt((a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y)); } double sqdist(P a, P b) { return (a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y); } }; int n, m; int a[300001], b[300001]; int nxt[1000001], dir[1000001], cost[1000001], rev[1000001]; int h; int visit[300001], c[300001]; int edge[300001]; int l[300001], r[300001]; int lb[300001], ty[1000001]; void insert(int u, int v) { nxt[++h] = nxt[u]; nxt[u] = h; dir[h] = v; nxt[++h] = nxt[v]; nxt[v] = h; dir[h] = u; } void insert2(int u, int v, int id) { nxt[++h] = nxt[u]; nxt[u] = h; dir[h] = v; rev[h] = h + 1; ty[h] = id; edge[id] = h; nxt[++h] = nxt[v]; nxt[v] = h; dir[h] = u; rev[h] = h - 1; ty[h] = -1; } void DFS2(int p, int color) { c[p] = color; visit[p] = 1; for (int i = nxt[p]; i > 0; i = nxt[i]) if (visit[dir[i]] == 0) { DFS2(dir[i], 1 - color); } } int s, t; int lvl[300001]; int q[300001]; bool BFS() { for (int i = (1); i <= (2 * n); i++) lvl[i] = -1; lvl[s] = 0; int top = 0, tail = 0; q[top++] = s; while (top > tail) { int u = q[tail++]; for (int po = nxt[u]; po > 0; po = nxt[po]) { if (lvl[dir[po]] == -1 && cost[po] > 0) { lvl[dir[po]] = lvl[u] + 1; q[top++] = dir[po]; } } } return (lvl[t] != -1); } int DFS(int u, int flow) { if (u == t) return flow; int w = flow; for (int po = nxt[u]; po > 0; po = nxt[po]) { if (lvl[dir[po]] == lvl[u] + 1 && cost[po]) { int x = DFS(dir[po], min(w, cost[po])); w -= x; cost[po] -= x; cost[rev[po]] += x; } } if (w == flow) lvl[u] = -3; return flow - w; } int MaxFlow() { int ans = 0; int p; while (BFS()) { while (p = DFS(s, 99999), p) { ans += p; } } return ans; } set<int> S; int main() { scanf( %d%d , &n, &m); for (int i = (1); i <= (n); i++) nxt[i] = -1; h = n; for (int i = (1); i <= (n); i++) scanf( %d , &a[i]); for (int i = (1); i <= (m); i++) { scanf( %d%d , &l[i], &r[i]); insert(l[i], r[i]); } for (int i = (1); i <= (n); i++) visit[i] = 0; for (int i = (1); i <= (n); i++) if (visit[i] == 0) DFS2(i, 1); for (int i = (0); i <= (n + 1); i++) nxt[i] = -1; h = n + 1; for (int i = (1); i <= (n); i++) { if (c[i] == 1) insert2(i, n + 1, i); else insert2(0, i, i); } for (int i = (1); i <= (m); i++) { if (c[l[i]] == 1) insert2(r[i], l[i], 0); else insert2(l[i], r[i], 0); } for (int i = (1); i <= (n); i++) { int base = a[i]; for (int j = (2); j <= (sqrt(base)); j++) { if (base % j == 0) { S.insert(j); while (base % j == 0) base /= j; } } if (base != 1) S.insert(base); } int ans = 0; s = 0; t = n + 1; for (set<int>::iterator it = S.begin(); it != S.end(); ++it) { int w = *it; for (int i = (1); i <= (h); i++) cost[i] = 0; for (int i = (1); i <= (h); i++) if (ty[i] == 0) cost[i] = 999; for (int i = (1); i <= (n); i++) { b[i] = 0; int base = a[i]; while (base % w == 0) { base /= w; b[i]++; } cost[edge[i]] = b[i]; } ans += MaxFlow(); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 3; const int M = 26; char s1[N], s2[N]; int z1[N][M], z2[N][M]; int n; bool check(int l1, int r1, int l2, int r2) { int l, i, t1, t2; for (i = 0; i < M; ++i) { t1 = z1[r1 - 1][i]; if (l1) t1 -= z1[l1 - 1][i]; t2 = z2[r2 - 1][i]; if (l2) t2 -= z2[l2 - 1][i]; if (t1 != t2) return false; } l = r1 - l1; if (l & 1) { for (i = 0; i < l; ++i) if (s1[l1 + i] != s2[l2 + i]) return false; return true; } l >>= 1; if (check(l1, l1 + l, l2, l2 + l) && check(l1 + l, r1, l2 + l, r2)) return true; if (check(l1, l1 + l, l2 + l, r2) && check(l1 + l, r1, l2, l2 + l)) return true; return false; } int main() { if (0) { freopen( input.txt , w , stdout); int n, i; n = 8192; for (i = 0; i < n; ++i) printf( a ); printf( n ); for (i = 0; i < n; ++i) printf( a ); printf( n ); return 0; } int i, j; scanf( %s , s1); scanf( %s , s2); n = strlen(s1); ++z1[0][s1[0] - a ]; ++z2[0][s2[0] - a ]; for (i = 1; i < n; ++i) { for (j = 0; j < M; ++j) z1[i][j] += z1[i - 1][j], z2[i][j] += z2[i - 1][j]; ++z1[i][s1[i] - a ]; ++z2[i][s2[i] - a ]; } printf( %s n , (check(0, n, 0, n)) ? YES : NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)1e5 + 10; int sx[MAXN], sy[MAXN], sz[MAXN]; char s[MAXN]; void solve(int x, int y, int z) { if (x + y + z < 3) { printf( YES n ); return; } int e = (x + y + z) / 3; vector<int> v; v.push_back(x); v.push_back(y); v.push_back(z); sort(v.begin(), v.end()); if ((x + y + z) % 3 == 0) { if (x == e && y == e && z == e) printf( YES n ); else printf( NO n ); return; } else if ((x + y + z) % 3 == 1) { if (v[2] == e + 1 && v[1] == e) printf( YES n ); else printf( NO n ); return; } else { if (v[2] == e + 1 && v[1] == e + 1) printf( YES n ); else printf( NO n ); return; } } int main() { scanf( %s , s); int n = strlen(s); for (int i = 1; i <= n; i++) { sx[i] = sx[i - 1] + (s[i - 1] == x ); sy[i] = sy[i - 1] + (s[i - 1] == y ); sz[i] = sz[i - 1] + (s[i - 1] == z ); } int m; scanf( %d , &m); for (int i = 1; i <= m; i++) { int l, r; scanf( %d%d , &l, &r); int x = sx[r] - sx[l - 1], y = sy[r] - sy[l - 1], z = sz[r] - sz[l - 1]; solve(x, y, z); } return 0; }
|
#include <bits/stdc++.h> using namespace std; char S[111111]; long long cnt1[26], cnt2[26 * 26]; int main() { scanf( %s , S); int len = strlen(S); for (int i = 0; i < len; i++) { for (int j = 0; j < 26; j++) cnt2[26 * j + S[i] - a ] += cnt1[j]; cnt1[S[i] - a ]++; } long long ans = 0; for (int i = 0; i < 26; i++) ans = max(ans, cnt1[i]); for (int i = 0; i < 26 * 26; i++) ans = max(ans, cnt2[i]); printf( %lld , ans); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 6-Bit Look-Up Table
// /___/ /\ Filename : LUT6.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Replace primitive with function; Remove buf.
// 01/07/06 - 222733 - Add LOC Parameter
// 06/04/07 - Add wire declaration to internal signal.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// 09/12/16 - ANSI ports, speed improvements
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`celldefine
module LUT6 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000
)(
output O,
input I0,
input I1,
input I2,
input I3,
input I4,
input I5
);
// define constants
localparam MODULE_NAME = "LUT6";
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "LUT6_dr.v"
`else
reg [63:0] INIT_REG = INIT;
`endif
// begin behavioral model
reg O_out;
assign O = O_out;
function lut_mux8_f;
input [7:0] d;
input [2:0] s;
begin
if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0))
lut_mux8_f = d[s];
else if ( ~(|d) || &d)
lut_mux8_f = d[0];
else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) &&
(d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}]))
lut_mux8_f = d[{1'b0,s[1:0]}];
else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) &&
(d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}]))
lut_mux8_f = d[{s[2],1'b0,s[0]}];
else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) &&
(d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}]))
lut_mux8_f = d[{s[2:1],1'b0}];
else if (((s[0] === 1'b1) || (s[0] === 1'b0)) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}]))
lut_mux8_f = d[{1'b0,1'b0,s[0]}];
else if (((s[1] === 1'b1) || (s[1] === 1'b0)) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) &&
(d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}]))
lut_mux8_f = d[{1'b0,s[1],1'b0}];
else if (((s[2] === 1'b1) || (s[2] === 1'b0)) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) &&
(d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}]))
lut_mux8_f = d[{s[2],1'b0,1'b0}];
else
lut_mux8_f = 1'bx;
end
endfunction
always @(I0 or I1 or I2 or I3 or I4 or I5) begin
if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b1)
O_out = INIT_REG[{I5, I4, I3, I2, I1, I0}];
else if ( ~(|INIT_REG) || &INIT_REG )
O_out = INIT_REG[0];
else
O_out = lut_mux8_f ({lut_mux8_f (INIT_REG[63:56], {I2, I1, I0}),
lut_mux8_f (INIT_REG[55:48], {I2, I1, I0}),
lut_mux8_f (INIT_REG[47:40], {I2, I1, I0}),
lut_mux8_f (INIT_REG[39:32], {I2, I1, I0}),
lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}),
lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}),
lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}),
lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I5, I4, I3});
end
// end behavioral model
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
(I3 => O) = (0:0:0, 0:0:0);
(I4 => O) = (0:0:0, 0:0:0);
(I5 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2014/03/12 13:10:34
// Design Name:
// Module Name: filter_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module filter_tb;
reg clk;
reg resetn;
reg [7:0] din00;
reg [7:0] din01;
reg [7:0] din02;
reg [7:0] din10;
reg [7:0] din11;
reg [7:0] din12;
reg [7:0] din20;
reg [7:0] din21;
reg [7:0] din22;
reg din_valid;
wire [7:0] dout;
wire dout_valid;
filter1 filter_uut
(
.clk(clk),
.resetn(resetn),
.din00(din00),
.din01(din01),
.din02(din02),
.din10(din10),
.din11(din11),
.din12(din12),
.din20(din20),
.din21(din21),
.din22(din22),
.din_valid(din_valid),
.dout(dout),
.dout_valid(dout_valid)
);
reg [7:0] counter1;
reg [7:0] counter2;
parameter clk_period = 10;
initial clk = 1'b0;
always #(clk_period/2) clk = ~clk;
initial begin
resetn = 1'b0;
#100
resetn = 1'b1;
end
always@(posedge clk) begin
if(resetn == 1'b0) begin
counter1 <= 0;
counter2 <= 0;
end
else begin
if(counter1 == counter2) begin
counter1 <= 0;
counter2 <= counter2 + 1;
end
else begin
counter1 <= counter1 + 1;
end
end
end
always@(posedge clk) begin
if(resetn == 1'b0) begin
din_valid <= 1'b0;
din00 <= 0;
din01 <= 0;
din02 <= 0;
din10 <= 0;
din11 <= 0;
din12 <= 0;
din20 <= 0;
din21 <= 0;
din22 <= 0;
end
else begin
if($random%2 == 1 ) begin
din_valid <= 1'b1;
din00 <= {$random%128};
din01 <= {$random%128};
din02 <= {$random%128};
din10 <= {$random%128};
din11 <= {$random%128};
din12 <= {$random%128};
din20 <= {$random%128};
din21 <= {$random%128};
din22 <= {$random%128};
end
else begin
din_valid <= 1'b0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
`define SIMULATION
module mult_32_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg [15:0]in_A;
reg [15:0]in_B;
wire [31:0] pp;
wire done;
mult_32 uut (.clk(clk) , .rst(rst) , .init(start) , .A(in_A) , .B(in_B) , .pp(pp) , .done(done));
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; in_A = 16'h0005; in_B = 16'h0003;//in_A = 16'hFA00; in_B = 16'hFA00; //in_A = 8'hAA; in_B = 8'h24;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
end
end
initial begin: TEST_CASE
$dumpfile("mult_32_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*120) $finish;
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for bug report #942: VHDL function bodies in arch declaration not
// supported
module br942_test();
logic clk, rst, q;
e dut(clk, rst, q);
initial begin
rst = 1;
clk = 0;
#1;
clk = 1;
#1;
rst = 0;
clk = 0;
if(q !== 1'b0) begin
$display("FAILED 1");
$finish();
end
#1;
clk = 1;
#1;
clk = 0;
if(q !== 1'b1) begin
$display("FAILED 2");
$finish();
end
#1;
clk = 1;
#1;
if(q !== 1'b0) begin
$display("FAILED 3");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e6 + 10, M = 20, mo = 1e9 + 7; vector<vector<long long> > f, sum; vector<long long> g; long long a[maxn], c[maxn]; long long n, l, k, K, B, ans, i, j, z, x, y, N, r; int main() { scanf( %lld%lld%lld , &n, &l, &k); g.push_back(0); for (i = 0; i < n; i++) { scanf( %lld , &a[i]); c[i] = a[i]; g.push_back(0); } if (l <= n) { printf( %lld n , l); return 0; } sort(c, c + n); K = min(l / n, k); N = (l / n) % mo; r = l % n; f.push_back(g); sum.push_back(g); for (i = 1; i <= k; i++) { f.push_back(g); sum.push_back(g); } for (i = 0; i < n; i++) { f[1][i] = 1; sum[0][i] = 1; } sum[1][0] = 1; for (i = 1; i < n; i++) sum[1][i] = (f[1][i] + sum[1][i - 1]) % mo; for (i = 2; i <= K; i++) { for (j = 0; j < n; j++) { z = upper_bound(c, c + n, c[j]) - c - 1; f[i][j] = sum[i - 1][z]; } sum[i][0] = f[i][0]; for (j = 1; j < n; j++) sum[i][j] = (f[i][j] + sum[i][j - 1]) % mo; } for (i = 1; i <= K; i++) { ans = (ans + (N - i + 1) * sum[i][n - 1]) % mo; for (j = 0; j < r; j++) { z = upper_bound(c, c + n, a[j]) - c - 1; ans = (ans + sum[i - 1][z]) % mo; } } if (r && K + 1 <= k) { i = K + 1; for (j = 0; j < r; j++) { z = upper_bound(c, c + n, a[j]) - c - 1; ans = (ans + sum[i - 1][z]) % mo; } } ans = (ans + mo) % mo; printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, c; cin >> n >> m >> c; vector<int> A(n), B(m); for (auto &a : A) cin >> a; for (auto &b : B) cin >> b; int i = 0, x = 0; for (int i = 0; i < n; ++i) { if (i < m) x = (x + B[i]) % c; if (i > n - m) x = (x - B[i - n + m - 1] + c) % c; A[i] = (A[i] + x) % c; } for (auto a : A) cout << a << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int tosub = 0; int pls = 1; int mins = 0; string s; char a; cin >> a; while (a != = ) { if (a == + ) { s.push_back(a); pls++; } else if (a == - ) { mins++; s.push_back(a); } cin >> a; } int tmp; cin >> tmp; int mn = pls - mins * tmp; int mx = pls * tmp - mins; if (tmp < mn || tmp > mx) { cout << Impossible n ; return 0; } cout << Possible n ; int curr = 0; for (int i = (-1); i < (int)s.size(); ++i) { if (!(~i) || s[i] == + ) { if (i >= 0) { cout << s[i] << ; } for (int j = 1; j <= tmp; ++j) { int mn = (pls - 1) - mins * tmp; int mx = (pls - 1) * tmp - mins; if (mn <= tmp - (curr + j) && mx >= tmp - (curr + j)) { cout << j << ; pls--; curr += j; break; } } } else { cout << s[i] << ; for (int j = 1; j <= tmp; ++j) { int mn = pls - (mins - 1) * tmp; int mx = pls * tmp - (mins - 1); if (mn <= tmp - (curr - j) && mx >= tmp - (curr - j)) { cout << j << ; mins--; curr -= j; break; } } } } cout << = << tmp << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, d = 0, e = 0, f = 0, sum = 0, c = 0, n; cin >> n; char a[4][4]; map<int, int> m; for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { cin >> a[i][j]; } } for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { if (a[i][j] >= 49 && a[i][j] <= 57) { m[a[i][j]]++; } } } for (auto x : m) { if (x.second > (2 * n)) { c++; } } if (c == 0) { cout << YES ; } else cout << NO ; }
|
#include <bits/stdc++.h> const int N = 1050000; const double pi = acos(-1.0); int a[N], ans[N], rev[N << 1]; std::complex<double> b[N << 1]; void FFT(std::complex<double> *a, int n, int f) { for (int i = 0; i < n; i++) if (i < rev[i]) std::swap(a[i], a[rev[i]]); for (int i = 1; i < n; i <<= 1) { std::complex<double> wn(cos(pi / i), f * sin(pi / i)); for (int j = 0; j < n; j += i << 1) { std::complex<double> w(1, 0); for (int k = j; k < j + i; k++, w *= wn) { std::complex<double> x = a[k], y = w * a[k + i]; a[k] = x + y; a[k + i] = x - y; } } } if (f == -1) for (int i = 0; i < n; i++) a[i] /= n; } int main() { int n, m; scanf( %d%d n , &n, &m); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); b[x] = a[x] = 1; } int len = 0, L = 1; for (; L <= m * 2; len++) L <<= 1; for (int i = 0; i < L; i++) rev[i] = rev[i >> 1] >> 1 ^ ((i & 1) << (len - 1)); FFT(b, L, 1); for (int i = 0; i < L; i++) b[i] *= b[i]; FFT(b, L, -1); int k = 0; for (int i = 1; i <= m; i++) if (!a[i] && b[i].real() >= 0.5) { printf( NO n ); return 0; } else if (a[i] && b[i].real() < 0.5) ans[++k] = i; printf( YES n%d n , k); for (int i = 1; i <= k; i++) printf( %d , ans[i]); }
|
#include <bits/stdc++.h> using ll = long long; using ld = long double; using ull = unsigned long long; using namespace std; const int N = 1e5 + 2, SQ = 400; int n, q, a[N], jump[N], cost[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> q; for (int i = (0); i <= (n - 1); ++i) cin >> a[i]; for (int i = (n - 1); i >= (0); --i) { int nxt = min(n, i + a[i]); if (nxt == n) { jump[i] = i; continue; } if (nxt / SQ > i / SQ) jump[i] = nxt, cost[i] = 1; else jump[i] = jump[nxt], cost[i] = cost[nxt] + 1; } while (q--) { int t; cin >> t; if (t == 0) { int x, y; cin >> x >> y; x--; a[x] = y; for (int i = (x); i >= (x / SQ * SQ); --i) { int nxt = min(n, i + a[i]); if (nxt == n) { jump[i] = i; cost[i] = 0; continue; } if (nxt / SQ > i / SQ) jump[i] = nxt, cost[i] = 1; else jump[i] = jump[nxt], cost[i] = cost[nxt] + 1; } } else { int x, res = 1; cin >> x; x--; while (cost[x]) res += cost[x], x = jump[x]; cout << x + 1 << << res << n ; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_TB_V
`define SKY130_FD_SC_MS__O2BB2AI_TB_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2ai.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ms__o2bb2ai dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A221OI_BEHAVIORAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_BEHAVIORAL_PP_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores MC68HC11E based SPI interface ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: simple_spi_top.v,v 1.5 2004-02-28 15:59:50 rherveille Exp $
//
// $Date: 2004-02-28 15:59:50 $
// $Revision: 1.5 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/08/01 11:41:54 rherveille
// Fixed some timing bugs.
//
// Revision 1.3 2003/01/09 16:47:59 rherveille
// Updated clkcnt size and decoding due to new SPR bit assignments.
//
// Revision 1.2 2003/01/07 13:29:52 rherveille
// Changed SPR bits coding.
//
// Revision 1.1.1.1 2002/12/22 16:07:15 rherveille
// Initial release
//
//
//
// Motorola MC68HC11E based SPI interface
//
// Currently only MASTER mode is supported
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module simple_spi_top(
// 8bit WISHBONE bus slave interface
input wire clk_i, // clock
input wire rst_i, // reset (asynchronous active low)
input wire cyc_i, // cycle
input wire stb_i, // strobe
input wire [1:0] adr_i, // address
input wire we_i, // write enable
input wire [7:0] dat_i, // data input
output reg [7:0] dat_o, // data output
output reg ack_o, // normal bus termination
output reg inta_o, // interrupt output
// SPI port
output reg sck_o, // serial clock output
output wire mosi_o, // MasterOut SlaveIN
input wire miso_i // MasterIn SlaveOut
);
//
// Module body
//
reg [7:0] spcr; // Serial Peripheral Control Register ('HC11 naming)
wire [7:0] spsr; // Serial Peripheral Status register ('HC11 naming)
reg [7:0] sper; // Serial Peripheral Extension register
reg [7:0] treg, rreg; // Transmit/Receive register
// fifo signals
wire [7:0] rfdout;
reg wfre, rfwe;
wire rfre, rffull, rfempty;
wire [7:0] wfdout;
wire wfwe, wffull, wfempty;
// misc signals
wire tirq; // transfer interrupt (selected number of transfers done)
wire wfov; // write fifo overrun (writing while fifo full)
reg [1:0] state; // statemachine state
reg [2:0] bcnt;
//
// Wishbone interface
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
// dat_i
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
begin
spcr <= #1 8'h10; // set master bit
sper <= #1 8'h00;
end
else if (wb_wr)
begin
if (adr_i == 2'b00)
spcr <= #1 dat_i | 8'h10; // always set master bit
if (adr_i == 2'b11)
sper <= #1 dat_i;
end
// write fifo
assign wfwe = wb_acc & (adr_i == 2'b10) & ack_o & we_i;
assign wfov = wfwe & wffull;
// dat_o
always @(posedge clk_i)
case(adr_i) // synopsys full_case parallel_case
2'b00: dat_o <= #1 spcr;
2'b01: dat_o <= #1 spsr;
2'b10: dat_o <= #1 rfdout;
2'b11: dat_o <= #1 sper;
endcase
// read fifo
assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;
// ack_o
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
ack_o <= #1 1'b0;
else
ack_o <= #1 wb_acc & !ack_o;
// decode Serial Peripheral Control Register
wire spie = spcr[7]; // Interrupt enable bit
wire spe = spcr[6]; // System Enable bit
wire dwom = spcr[5]; // Port D Wired-OR Mode Bit
wire mstr = spcr[4]; // Master Mode Select Bit
wire cpol = spcr[3]; // Clock Polarity Bit
wire cpha = spcr[2]; // Clock Phase Bit
wire [1:0] spr = spcr[1:0]; // Clock Rate Select Bits
// decode Serial Peripheral Extension Register
wire [1:0] icnt = sper[7:6]; // interrupt on transfer count
wire [1:0] spre = sper[1:0]; // extended clock rate select
wire [3:0] espr = {spre, spr};
// generate status register
wire wr_spsr = wb_wr & (adr_i == 2'b01);
reg spif;
always @(posedge clk_i)
if (~spe)
spif <= #1 1'b0;
else
spif <= #1 (tirq | spif) & ~(wr_spsr & dat_i[7]);
reg wcol;
always @(posedge clk_i)
if (~spe)
wcol <= #1 1'b0;
else
wcol <= #1 (wfov | wcol) & ~(wr_spsr & dat_i[6]);
assign spsr[7] = spif;
assign spsr[6] = wcol;
assign spsr[5:4] = 2'b00;
assign spsr[3] = wffull;
assign spsr[2] = wfempty;
assign spsr[1] = rffull;
assign spsr[0] = rfempty;
// generate IRQ output (inta_o)
always @(posedge clk_i)
inta_o <= #1 spif & spie;
//
// hookup read/write buffer fifo
fifo4 #(8)
rfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( treg ),
.we ( rfwe ),
.dout ( rfdout ),
.re ( rfre ),
.full ( rffull ),
.empty ( rfempty )
),
wfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( dat_i ),
.we ( wfwe ),
.dout ( wfdout ),
.re ( wfre ),
.full ( wffull ),
.empty ( wfempty )
);
//
// generate clk divider
reg [11:0] clkcnt;
always @(posedge clk_i)
if(spe & (|clkcnt & |state))
clkcnt <= #1 clkcnt - 11'h1;
else
case (espr) // synopsys full_case parallel_case
4'b0000: clkcnt <= #1 12'h0; // 2 -- original M68HC11 coding
4'b0001: clkcnt <= #1 12'h1; // 4 -- original M68HC11 coding
4'b0010: clkcnt <= #1 12'h3; // 16 -- original M68HC11 coding
4'b0011: clkcnt <= #1 12'hf; // 32 -- original M68HC11 coding
4'b0100: clkcnt <= #1 12'h1f; // 8
4'b0101: clkcnt <= #1 12'h7; // 64
4'b0110: clkcnt <= #1 12'h3f; // 128
4'b0111: clkcnt <= #1 12'h7f; // 256
4'b1000: clkcnt <= #1 12'hff; // 512
4'b1001: clkcnt <= #1 12'h1ff; // 1024
4'b1010: clkcnt <= #1 12'h3ff; // 2048
4'b1011: clkcnt <= #1 12'h7ff; // 4096
endcase
// generate clock enable signal
wire ena = ~|clkcnt;
// transfer statemachine
always @(posedge clk_i)
if (~spe)
begin
state <= #1 2'b00; // idle
bcnt <= #1 3'h0;
treg <= #1 8'h00;
wfre <= #1 1'b0;
rfwe <= #1 1'b0;
sck_o <= #1 1'b0;
end
else
begin
wfre <= #1 1'b0;
rfwe <= #1 1'b0;
case (state) //synopsys full_case parallel_case
2'b00: // idle state
begin
bcnt <= #1 3'h7; // set transfer counter
treg <= #1 wfdout; // load transfer register
sck_o <= #1 cpol; // set sck
if (~wfempty) begin
wfre <= #1 1'b1;
state <= #1 2'b01;
if (cpha) sck_o <= #1 ~sck_o;
end
end
2'b01: // clock-phase2, next data
if (ena) begin
sck_o <= #1 ~sck_o;
state <= #1 2'b11;
end
2'b11: // clock phase1
if (ena) begin
treg <= #1 {treg[6:0], miso_i};
bcnt <= #1 bcnt -3'h1;
if (~|bcnt) begin
state <= #1 2'b00;
sck_o <= #1 cpol;
rfwe <= #1 1'b1;
end else begin
state <= #1 2'b01;
sck_o <= #1 ~sck_o;
end
end
2'b10: state <= #1 2'b00;
endcase
end
assign mosi_o = treg[7];
// count number of transfers (for interrupt generation)
reg [1:0] tcnt; // transfer count
always @(posedge clk_i)
if (~spe)
tcnt <= #1 icnt;
else if (rfwe) // rfwe gets asserted when all bits have been transfered
if (|tcnt)
tcnt <= #1 tcnt - 2'h1;
else
tcnt <= #1 icnt;
assign tirq = ~|tcnt & rfwe;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int arr[n + 1]; int i, s = 0; for (i = 0; i < n; i++) { cin >> arr[i]; } int j; for (i = 1; i < n - 1; i++) { if (arr[i - 1] < arr[i] && arr[i + 1] < arr[i]) { cout << YES << endl << i << << i + 1 << << i + 2 << endl; s = 1; break; } } if (s != 1) cout << NO << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
|
#include <bits/stdc++.h> const int offs = 350; int n, d, f[30005][705], gem[30005]; int main() { scanf( %d%d , &n, &d); for (int i = 0, t; i < n; i++) scanf( %d , &t), gem[t]++; memset(f, -1, sizeof(f)); f[d][offs] = gem[d]; for (int i = d + 1, t; i < 30005; i++) for (int j = 0; j < 705 - 1; j++) if ((t = d + j - offs) > 0 && (i - t >= 0)) { if (t - 1 > 0 && ~f[i - t][j - 1]) f[i][j] = std::max(f[i][j], f[i - t][j - 1]); if (~f[i - t][j]) f[i][j] = std::max(f[i][j], f[i - t][j]); if (~f[i - t][j + 1]) f[i][j] = std::max(f[i][j], f[i - t][j + 1]); if (~f[i][j]) f[i][j] += gem[i]; } int ans = 0; for (int i = 0; i < 30005; i++) for (int j = 0; j < 705; j++) ans = std::max(ans, f[i][j]); printf( %d n , ans); return 0; }
|
// EE 454
// Spring 2015
// Lab 2 Part 2
// John Timms
// accumulator_processor.v
`timescale 1 ns / 100 ps
module accumulator_processor (clk, reset, op, signal, read, write, req, grant, state);
input clk, reset, signal, grant;
input [1:0] op;
input [31:0] read;
output [31:0] write;
output req;
output [6:0] state;
reg req = 0;
reg [6:0] state;
reg [1:0] op_internal;
reg [31:0] A;
reg [31:0] B;
reg [31:0] result;
integer slowdown = 0;
integer seed = ;
localparam
NOP = 2'b00, // No operation
FETCH = 2'b01, // Fetch an operand from the memory
SEND = 2'b10; // Send a result to the memory
localparam
REQ1 = 7'b0000001, // Request 1 state - requests the bus to receive A
RECA = 7'b0000010, // Receive A state - receives A from the bus
REQ2 = 7'b0000100, // Request 2 state - requests the bus to receive B
RECB = 7'b0001000, // Receive B state - receives B from the bus
ADD = 7'b0010000, // Add state - adds A and B
REQ3 = 7'b0100000, // Request 3 state - requests the bus to send the result
RSLT = 7'b1000000; // Result state - sends the result over the bus
assign op = (op_internal == FETCH || op_internal == SEND) ? op_internal : 2'bz;
assign write = (state == RSLT) ? result : 32'bz;
reg [4*8:1] state_string;
always @(*)
begin
case (state)
7'b0000001: state_string = "REQ1";
7'b0000010: state_string = "RECA";
7'b0000100: state_string = "REQ2";
7'b0001000: state_string = "RECB";
7'b0010000: state_string = "ADD ";
7'b0100000: state_string = "REQ3";
7'b1000000: state_string = "RSLT";
default: state_string = "UNKN";
endcase
end
always @(posedge clk, posedge reset)
begin
if (reset) begin
state <= REQ1;
op_internal <= NOP;
end
else begin
case (state)
REQ1:
begin
req <= 1'b1;
if (grant && !signal) begin
state <= RECA;
end
end
RECA:
begin
op_internal <= FETCH;
A <= read;
if (signal) begin
op_internal <= NOP;
req <= 1'b0;
state <= REQ2;
end
end
REQ2:
begin
req <= 1'b1;
if (grant && !signal) begin
state <= RECB;
end
end
RECB:
begin
op_internal <= FETCH;
B <= read;
if (signal) begin
op_internal <= NOP;
req <= 1'b0;
state <= ADD;
// Set the slowdown here
slowdown <= 1000 + ({$random(seed)} % 9000);
end
end
ADD:
begin
result <= A + B;
if (slowdown != 0) begin
slowdown <= slowdown - 1;
end
else begin
state <= REQ3;
end
end
REQ3:
begin
req <= 1'b1;
if (grant && !signal) begin
state <= RSLT;
end
end
RSLT:
begin
op_internal <= SEND;
if (signal) begin
op_internal <= NOP;
req <= 1'b0;
state <= REQ1;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxl = 2 * 1000 * 100 + 5; const int maxlg = 22; vector<pair<int, int> > adj[maxl]; vector<int> tree[maxl]; int n, m, q; int mark[maxl], depth[maxl]; bool cut[maxl]; int dsu[maxl]; int arr[maxl]; int lca[maxl][maxlg]; int psum1[maxl], psum2[maxl]; bool flag = true; int par(int index) { if (dsu[index] < 0) return index; return dsu[index] = par(dsu[index]); } inline void merge(int a, int b) { a = par(a); b = par(b); if (a == b) return; if (dsu[a] < dsu[b]) swap(a, b); dsu[b] += dsu[a]; dsu[a] = b; return; } inline int getPar(int index, int x) { int ind = 0; while (x) { if (x & 1) index = lca[index][ind]; ind++; x /= 2; } return index; } inline int Lca(int a, int b) { if (depth[a] < depth[b]) swap(a, b); a = getPar(a, depth[a] - depth[b]); if (a == b) return a; for (int i = maxlg - 1; i >= 0; i--) if (lca[a][i] != lca[b][i]) { a = lca[a][i]; b = lca[b][i]; } return lca[a][0]; } int dfs_cut(int index, int par = -1) { mark[index] = 1; int mn = depth[index]; for (int i = 0; i < adj[index].size(); i++) { int node = adj[index][i].first, edge = adj[index][i].second; if (mark[node] == 1 && edge != par) mn = min(mn, depth[node]); if (!mark[node]) { depth[node] = depth[index] + 1; int tmp = dfs_cut(node, edge); mn = min(mn, tmp); cut[edge] = (tmp >= depth[node]); } } mark[index] = 2; return mn; } void dfs(int index, int par = -1) { lca[index][0] = par; if (par == -1) lca[index][0] = index; for (int i = 0; i < tree[index].size(); i++) { int node = tree[index][i]; if (node != par) { depth[node] = depth[index] + 1; dfs(node, index); psum1[index] += psum1[node]; psum2[index] += psum2[node]; if (psum1[node] && psum2[node]) flag = false; } } } int main() { memset(dsu, -1, sizeof dsu); memset(lca, -1, sizeof lca); scanf( %d %d %d , &n, &m, &q); for (int i = 0; i < m; i++) { int a, b; scanf( %d %d , &a, &b); a--; b--; adj[a].push_back(make_pair(b, i)); adj[b].push_back(make_pair(a, i)); } for (int i = 0; i < n; i++) if (!mark[i]) dfs_cut(i); for (int i = 0; i < n; i++) for (int j = 0; j < adj[i].size(); j++) { int node = adj[i][j].first, edge = adj[i][j].second; if (!cut[edge]) merge(i, node); } for (int i = 0; i < n; i++) arr[i] = par(i); for (int i = 0; i < n; i++) for (int j = 0; j < adj[i].size(); j++) { int node = adj[i][j].first, edge = adj[i][j].second; merge(i, node); int x = arr[i], y = arr[node]; if (x == y) continue; tree[x].push_back(y); } memset(depth, 0, sizeof depth); for (int i = 0; i < n; i++) if (arr[i] == i && lca[i][0] == -1) dfs(i); for (int j = 1; j < maxlg; j++) for (int i = 0; i < n; i++) if (arr[i] == i) lca[i][j] = lca[lca[i][j - 1]][j - 1]; for (int i = 0; i < q; i++) { int x, y; scanf( %d %d , &x, &y); x--; y--; x = arr[x]; y = arr[y]; if (par(x) != par(y)) { flag = false; continue; } int node = Lca(x, y); psum1[x]++; psum1[node]--; psum2[y]++; psum2[node]--; } for (int i = 0; i < n; i++) if (arr[i] == i && lca[i][0] == i) dfs(i); if (flag) printf( Yes n ); else printf( No n ); }
|
/*
* Copyright (C) 2009 Onno Kortmann <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* THIS FILE HAS BEEN AUTOMATICALLY GENERATED FROM avr_tmpl.v.
* --- DO NOT EDIT MANUALLY! ---
*/
module $(part)(clk,
#set exclast=sorted($io_ports)[:-1]
#set onlylast=sorted($io_ports)[-1:][0]
#for $Letter in $exclast
P$Letter,
#end for
P$onlylast
#slurp
);
parameter progfile="UNSPECIFIED";
input clk;
#for $Letter in $io_ports
##FIXME: Only specify needed bits!
inout [7:0] P$Letter;
#end for
integer handle;
defparam core.progfile=progfile;
defparam core.name="$part";
AVRCORE core(clk);
#for $Letter in $io_ports
#set $letter=$Letter.lower
#for $bit in range(8)
avr_pin #("$(Letter)$(bit)") p$(letter)$(bit)(P$(Letter)[$(bit)]);
#end for
#end for
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; map<int, int> m; for (int i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] != 0) { m[arr[i]]++; } } cout << m.size() << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, a[300005], tp, lt, ans; int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); for (int i = 1; i <= n; i++) { tp = min(a[i] / 2, lt); lt -= tp; a[i] -= tp * 2; ans += tp + a[i] / 3; lt += a[i] % 3; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long sum = 0; string s; cin >> s; s += a ; int now_number = 0, buf_number = 0, size_buf = 0, point = 0; for (int i = 0; i < s.size(); ++i) { if (s[i] >= a && s[i] <= z ) { now_number = now_number * pow(10, size_buf) + buf_number; buf_number = 0; if (size_buf != 2 || !point) { now_number *= 100; } size_buf = 0; sum += now_number; now_number = 0; point = 0; } else { if (s[i] == . ) { now_number = now_number * pow(10, size_buf) + buf_number; buf_number = 0; size_buf = 0; point = 1; } else { buf_number = buf_number * 10 + (s[i] - 0 ); size_buf++; } } } int kop = sum % 100; sum /= 100; if (sum == 0) { cout << 0. << kop / 10 << kop % 10; return 0; } vector<string> ss; while (sum != 0) { int tri = sum % 1000; sum /= 1000; string ans = ; if (sum != 0) { ans = (char)(tri % 10 + 48) + ans; tri /= 10; ans = (char)(tri % 10 + 48) + ans; tri /= 10; ans = (char)(tri % 10 + 48) + ans; tri /= 10; } else { ans = to_string(tri); } ss.push_back(ans); } reverse(ss.begin(), ss.end()); for (int i = 0; i < ss.size(); ++i) { if (i == ss.size() - 1) { cout << ss[i]; } else { cout << ss[i] << . ; } } if (kop != 0) { cout << . << kop / 10 << kop % 10; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int abs(long long int a, long long int b) { if (a < b) { return -1 * (a - b); } return (a - b); } bool comp(long long int a, long long int b) { if (a > b) { return true; } return false; } int main() { int n, a, b; cin >> n >> a >> b; vector<long long int> v; for (int i = 0; i < n; i++) { long long int t; cin >> t; v.push_back(t); } sort(v.begin(), v.end(), comp); long long int ans = abs(v[n - b], v[n - b - 1]); cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int ans[maxn]; vector<int> xs[maxn], ys[maxn]; struct query { int l, r, d, u, id; query(int aa, int bb, int cc, int dd, int ee) { l = aa; r = bb; d = cc; u = dd; id = ee; } query() {} }; query qry[maxn]; vector<int> xq[maxn], yq[maxn]; struct SegmentTree { SegmentTree *lc, *rc; static SegmentTree mem[2000000]; static SegmentTree *ptr; int pos; SegmentTree() {} ~SegmentTree() {} SegmentTree(int L, int R) { lc = rc = nullptr; pos = 0; if (L == R) return; lc = new (ptr++) SegmentTree(L, ((L + R) >> 1)); rc = new SegmentTree(((L + R) >> 1) + 1, R); } void pull() { pos = min(lc->pos, rc->pos); } void modify(int L, int R, int x, int v) { if (L == R) { pos = v; return; } if (x <= ((L + R) >> 1)) lc->modify(L, ((L + R) >> 1), x, v); else rc->modify(((L + R) >> 1) + 1, R, x, v); pull(); } int ask(int L, int R, int l, int r) { if (L > r || l > R) return maxn; if (L >= l && R <= r) return pos; return min(lc->ask(L, ((L + R) >> 1), l, r), rc->ask(((L + R) >> 1) + 1, R, l, r)); } } * stx, *sty; SegmentTree SegmentTree::mem[2000000]; SegmentTree *SegmentTree::ptr = mem; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m, k, q; cin >> n >> m >> k >> q; for (int i = 0; i < k; ++i) { int x, y; cin >> x >> y; xs[x].push_back(y); ys[y].push_back(x); } for (int i = 0; i < q; ++i) { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; qry[i] = query(x1, x2, y1, y2, i); xq[x2].push_back(i); yq[y2].push_back(i); } stx = new (SegmentTree::ptr++) SegmentTree(0, maxn - 1); sty = new (SegmentTree::ptr++) SegmentTree(0, maxn - 1); for (int i = 0; i < maxn; ++i) if (xs[i].size() || xq[i].size()) { for (int j : xs[i]) stx->modify(0, maxn - 1, j, i); for (int j : xq[i]) { if (stx->ask(0, maxn - 1, qry[j].d, qry[j].u) < qry[j].l) ++ans[j]; } } for (int i = 0; i < maxn; ++i) if (ys[i].size() || yq[i].size()) { for (int j : ys[i]) sty->modify(0, maxn - 1, j, i); for (int j : yq[i]) { if (sty->ask(0, maxn - 1, qry[j].l, qry[j].r) < qry[j].d) ++ans[j]; } } for (int i = 0; i < q; ++i) { if (ans[i] == 2) cout << NO << endl; else cout << YES << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); long long l, r; long long g(long long x) { long long t = 1; while (t <= x) t *= 10; return (t - 1 - x) * x; } int n, m; const char let[] = ACGT ; char buf[1600]; int len[16]; int a[16][16]; vector<int> st; struct Node { Node* ch[4]; Node* next[4]; int end; Node() { memset(a, 0, sizeof a); ; } void mark(Node* root) { end = 0; for (int i = 0, _n = (m); i < _n; i++) if (len[i] <= (int)(st).size()) { bool eq = true; for (int k = 0, _n = (len[i]); k < _n; k++) if (st[(int)(st).size() - len[i] + k] != a[i][k]) { eq = false; break; } if (eq) { end = max(end, len[i]); } } for (int i = 0, _n = (4); i < _n; i++) if (ch[i]) { st.push_back(i); ch[i]->mark(root); st.pop_back(); next[i] = ch[i]; } else { st.push_back(i); next[i] = 0; for (int j = 0, _n = ((int)(st).size() + 1); j < _n; j++) if (j > 0) { Node* v = root; for (int jj = j; jj < (int)(st).size() && v; jj++) v = v->ch[st[jj]]; if (v) { next[i] = v; break; } } st.pop_back(); } } }; Node nodes[1024]; int w; int d[1024][128][11]; int main() { gets(buf); sscanf(buf, %d%d , &n, &m); for (int i = 0, _n = (m); i < _n; i++) { gets(buf); len[i] = strlen(buf); for (int j = 0, _n = (len[i]); j < _n; j++) a[i][j] = strchr(let, buf[j]) - let; } w = 1; for (int i = 0, _n = (m); i < _n; i++) { Node* v = &nodes[0]; for (int j = 0, _n = (len[i]); j < _n; j++) { if (v->ch[a[i][j]] == 0) v->ch[a[i][j]] = &nodes[w++]; v = v->ch[a[i][j]]; } } nodes[0].mark(&nodes[0]); memset(d, 0, sizeof d); ; d[0][0][0] = 1; for (int i = 0, _n = (n); i < _n; i++) for (int j = 0, _n = (w); j < _n; j++) for (int c = 0, _n = (11); c < _n; c++) if (d[i][j][c]) for (int add = 0, _n = (4); add < _n; add++) { int nc = c + 1; Node* v = nodes[j].next[add]; if (v->end >= nc) nc = 0; if (nc == 10) continue; d[i + 1][v - nodes][nc] = (d[i + 1][v - nodes][nc] + d[i][j][c]) % 1000000009; } long long res = 0; for (int j = 0, _n = (w); j < _n; j++) res = (res + d[n][j][0]) % 1000000009; cout << res << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { vector<int> seq; int n; long e; cin >> n; int first = 0; long long s = 0; int f = 0; for (int i = 0; i < n; i++) { cin >> e; if (e != 1) { s += e; f++; } else { first++; } if (s > f && (s - f + 1) % 2 == 0) { cout << 1 << endl; } else { cout << 2 << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, a[100001]; long long s[100001], ans[100001]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + n + 1); reverse(a + 1, a + n + 1); for (int i = 1; i <= n; i++) s[i] = s[i - 1] + a[i]; cin >> m; for (int i = 0; i < m; i++) { int k; cin >> k; if (!ans[k]) { long long res = 0; long long koef = 1, cnt = k, j0 = 2, j1; while (j0 <= n) { j1 = min((long long)n, j0 + cnt - 1); res += (s[j1] - s[j0 - 1]) * koef; j0 = j0 + cnt; koef++; cnt *= k; } ans[k] = res; } cout << ans[k] << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, m; cin >> n >> m; double num; num = (double)m / n; if (n == m) { cout << 0 ; } else { long long int x = num, counter1 = 0, counter2 = 0; if (ceil(num) == num) { if (x % 2 == 0 || x % 3 == 0) { while (x % 2 == 0) { x = x / 2; counter1++; } while (x % 3 == 0) { x = x / 3; counter2++; } if (pow(2, counter1) * pow(3, counter2) == num) cout << counter1 + counter2; else cout << -1 ; } else cout << -1 ; } else cout << -1 ; } return 0; }
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, Andrew "bunnie" Huang
//
// See the NOTICE file distributed with this work for additional
// information regarding copyright ownership. The copyright holder
// licenses this file to you under the Apache License, Version 2.0
// (the "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// code distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module adc_rx(
input wire [7:0] data_i_p,
input wire [7:0] data_i_n,
input wire [7:0] data_q_p,
input wire [7:0] data_q_n,
input wire clk_p,
input wire clk_n,
output reg [63:0] adc_i,
output reg [63:0] adc_q,
output wire oclk,
output wire oclkx2,
input wire reset
);
wire adc_gclk;
wire adc_bitslip;
wire adc_pll_locked;
wire adc_bufpll_locked;
wire adc_clk;
wire [63:0] adc_i_fast;
wire [63:0] adc_q_fast;
always @(posedge oclk) begin
// i-channel: 0100_0000 // swaps due to P/N pair swapping for routability
// q-channel: 1010_1000
adc_i <= adc_i_fast ^ 64'h4848_4848_4848_4848;
adc_q <= adc_q_fast ^ 64'hA8A8_A8A8_A8A8_A8A8;
end
serdes_1_to_n_clk_pll_s8_diff input_adc_clk (
.clkin_p(clk_p),
.clkin_n(clk_n),
.rxioclk(adc_clk),
.pattern1(2'b10),
.pattern2(2'b01),
.rx_serdesstrobe(adc_serdesstrobe),
.reset(reset),
.rx_bufg_pll_x1(adc_gclk),
.rx_pll_lckd(adc_pll_locked),
.rx_pllout_div8(oclk),
.rx_pllout_div4(oclkx2),
// .rx_pllout_xs(),
.bitslip(adc_bitslip),
.rx_bufpll_lckd(adc_bufpll_locked)
// .datain()
) ;
serdes_1_to_n_data_s8_diff input_adc_i (
.use_phase_detector(1'b1),
.datain_p(data_i_p[7:0]),
.datain_n(data_i_n[7:0]),
.rxioclk(adc_clk),
.rxserdesstrobe(adc_serdesstrobe),
.reset(reset),
.gclk(oclk),
.bitslip(adc_bitslip),
// .debug_in(),
// .debug(),
.data_out(adc_i_fast)
) ;
serdes_1_to_n_data_s8_diff input_adc_q (
.use_phase_detector(1'b1),
.datain_p(data_q_p[7:0]),
.datain_n(data_q_n[7:0]),
.rxioclk(adc_clk),
.rxserdesstrobe(adc_serdesstrobe),
.reset(reset),
.gclk(oclk),
.bitslip(adc_bitslip), // not used for now
// .debug_in(),
// .debug(),
.data_out(adc_q_fast)
) ;
endmodule // adc_rx
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output branch3_enable,
output gsu_enable
);
parameter [2:0]
//FEAT_DSPX = 0,
//FEAT_ST0010 = 1,
//FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_2100 = 6
;
wire [23:0] SRAM_SNES_ADDR;
assign IS_ROM = ~SNES_ROMSEL;
assign IS_SAVERAM = SAVERAM_MASK[0]
& ( // 60-7D/E0-FF:0000-FFFF
( &SNES_ADDR[22:21]
& ~SNES_ROMSEL
)
// 00-3F/80-BF:6000-7FFF
| ( ~SNES_ADDR[22]
& ~SNES_ADDR[15]
& &SNES_ADDR[14:13]
)
);
assign IS_WRITABLE = IS_SAVERAM;
// GSU has a weird hybrid of Lo and Hi ROM formats.
// TODO: add programmable address map
assign SRAM_SNES_ADDR = (IS_SAVERAM
// 60-7D/E0-FF:0000-FFFF or 00-3F/80-BF:6000-7FFF (first 8K mirror)
? (24'hE00000 + ((SNES_ADDR[22] ? SNES_ADDR[16:0] : SNES_ADDR[12:0]) & SAVERAM_MASK))
// 40-5F/C0-DF:0000-FFFF or 00-3F/80-BF:8000-FFFF
: ((SNES_ADDR[22] ? {2'b00, SNES_ADDR[21:0]} : {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}) & ROM_MASK)
);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
assign branch1_enable = (SNES_ADDR == 24'h002A1F);
assign branch2_enable = (SNES_ADDR == 24'h002A59);
assign branch3_enable = (SNES_ADDR == 24'h002A5E);
// 00-3F/80-BF:3000-32FF gsu registers. TODO: some emulators go to $34FF???
assign gsu_enable = (!SNES_ADDR[22] && ({SNES_ADDR[15:10],2'h0} == 8'h30)) && (SNES_ADDR[9:8] != 2'h3);
endmodule
|
#include <bits/stdc++.h> using namespace std; unsigned long long x1, out; unsigned long long Fac(unsigned long long x1) { unsigned long long out = 1; for (int i = 1; i <= x1; i++) out = out * i; return out; } unsigned long long Cnk(unsigned long long a, unsigned long long b, unsigned long long c) { unsigned long long outL = 1; vector<int> fac; if (b > c) { unsigned long long nCount = a - b; for (int i = 2; i <= c; i++) fac.push_back(i); while (nCount > 0) { outL = outL * a; a--; nCount--; for (int i = 0; i < fac.size(); i++) { if (fac[i] > -1 && outL % fac[i] == 0) { outL = outL / fac[i]; fac[i] = -1; } } } } else { unsigned long long nCount = a - c; for (int i = 2; i <= b; i++) fac.push_back(i); while (nCount > 0) { outL = outL * a; a--; nCount--; for (int i = 0; i < fac.size(); i++) { if (fac[i] > -1 && outL % fac[i] == 0) { outL = outL / fac[i]; fac[i] = -1; } } } } for (int i = 0; i < fac.size(); i++) { if (fac[i] > -1) outL = outL / fac[i]; } return outL; } int main() { int n, m, t; cin >> n >> m >> t; for (int i = 4; i <= n; i++) { for (int y = 1; y <= m; y++) { if (i + y != t) continue; out += (Cnk(n, i, n - i) * Cnk(m, y, m - y)); } } cout << out; cin >> x1; }
|
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; stack<char> s; map<char, char> type = {{ ( , ) }, { { , } }, { < , > }, { [ , ] }}; int ans = 0; for (auto it : str) { if (it == { || it == ( || it == < || it == [ ) { s.push(it); } else { if (s.empty()) { cout << Impossible n ; return 0; } else { if (type[s.top()] != it) { ans += 1; } s.pop(); } } } if (s.empty()) { cout << ans << n ; return 0; } cout << Impossible n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int mod = 1e9 + 7; void show2d(const vector<vector<int>>& adj) { for (auto x : adj) { for (auto y : x) { cout << y << ; } cout << n ; } } long long int modexp(long long int a, long long int b, long long int mod) { long long int x = 1; while (b) { if (b & 1) x = ((x % mod) * (a % mod)) % mod; a = ((a % mod) * (a % mod)) % mod; b = b / 2; } return x; } void rf() {} int32_t main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, k; cin >> n >> m >> k; int o = 0; int tt = 0; for (int i = 0; i < n; ++i) { int ch; cin >> ch; if (ch == 1) ++o; else ++tt; } tt = max(tt - k, 0); cout << max((o + tt) - m, 0) << n ; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:17:13 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_stub.v
// Design : system_inverter_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "inverter,Vivado 2016.4" *)
module system_inverter_0_0(x, x_not)
/* synthesis syn_black_box black_box_pad_pin="x,x_not" */;
input x;
output x_not;
endmodule
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 29-10-2018
*/
module jt12_eg (
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input zero,
input eg_stop,
// envelope configuration
input [4:0] keycode_II,
input [4:0] arate_I, // attack rate
input [4:0] rate1_I, // decay rate
input [4:0] rate2_I, // sustain rate
input [3:0] rrate_I, // release rate
input [3:0] sl_I, // sustain level
input [1:0] ks_II, // key scale
// SSG operation
input ssg_en_I,
input [2:0] ssg_eg_I,
// envelope operation
input keyon_I,
// envelope number
input [6:0] lfo_mod,
input amsen_IV,
input [1:0] ams_IV,
input [6:0] tl_IV,
output reg [9:0] eg_V,
output reg pg_rst_II
);
parameter num_ch=6;
wire [14:0] eg_cnt;
jt12_eg_cnt u_egcnt(
.rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en & ~eg_stop ),
.zero ( zero ),
.eg_cnt ( eg_cnt)
);
wire keyon_last_I;
wire keyon_now_I = !keyon_last_I && keyon_I;
wire keyoff_now_I = keyon_last_I && !keyon_I;
wire cnt_in_II, cnt_lsb_II, step_II, pg_rst_I;
wire ssg_inv_in_I, ssg_inv_out_I;
reg ssg_inv_II, ssg_inv_III, ssg_inv_IV;
wire [2:0] state_in_I, state_next_I;
reg attack_II, attack_III;
wire [4:0] base_rate_I;
reg [4:0] base_rate_II;
wire [5:0] rate_out_II;
reg [5:1] rate_in_III;
reg step_III, ssg_en_II, ssg_en_III;
wire sum_out_II;
reg sum_in_III;
wire [9:0] eg_in_I, pure_eg_out_III, eg_next_III, eg_out_IV;
reg [9:0] eg_in_II, eg_in_III, eg_in_IV;
jt12_eg_comb u_comb(
///////////////////////////////////
// I
.keyon_now ( keyon_now_I ),
.keyoff_now ( keyoff_now_I ),
.state_in ( state_in_I ),
.eg_in ( eg_in_I ),
// envelope configuration
.arate ( arate_I ), // attack rate
.rate1 ( rate1_I ), // decay rate
.rate2 ( rate2_I ), // sustain rate
.rrate ( rrate_I ),
.sl ( sl_I ), // sustain level
// SSG operation
.ssg_en ( ssg_en_I ),
.ssg_eg ( ssg_eg_I ),
// SSG output inversion
.ssg_inv_in ( ssg_inv_in_I ),
.ssg_inv_out ( ssg_inv_out_I ),
.base_rate ( base_rate_I ),
.state_next ( state_next_I ),
.pg_rst ( pg_rst_I ),
///////////////////////////////////
// II
.step_attack ( attack_II ),
.step_rate_in ( base_rate_II ),
.keycode ( keycode_II ),
.eg_cnt ( eg_cnt ),
.cnt_in ( cnt_in_II ),
.ks ( ks_II ),
.cnt_lsb ( cnt_lsb_II ),
.step ( step_II ),
.step_rate_out ( rate_out_II ),
.sum_up_out ( sum_out_II ),
///////////////////////////////////
// III
.pure_attack ( attack_III ),
.pure_step ( step_III ),
.pure_rate ( rate_in_III[5:1] ),
.pure_ssg_en ( ssg_en_III ),
.pure_eg_in ( eg_in_III ),
.pure_eg_out ( pure_eg_out_III ),
.sum_up_in ( sum_in_III ),
///////////////////////////////////
// IV
.lfo_mod ( lfo_mod ),
.amsen ( amsen_IV ),
.ams ( ams_IV ),
.tl ( tl_IV ),
.final_ssg_inv ( ssg_inv_IV ),
.final_eg_in ( eg_in_IV ),
.final_eg_out ( eg_out_IV )
);
always @(posedge clk) if(clk_en) begin
eg_in_II <= eg_in_I;
attack_II <= state_next_I[0];
base_rate_II<= base_rate_I;
ssg_en_II <= ssg_en_I;
ssg_inv_II <= ssg_inv_out_I;
pg_rst_II <= pg_rst_I;
eg_in_III <= eg_in_II;
attack_III <= attack_II;
rate_in_III <= rate_out_II[5:1];
ssg_en_III <= ssg_en_II;
ssg_inv_III <= ssg_inv_II;
step_III <= step_II;
sum_in_III <= sum_out_II;
ssg_inv_IV <= ssg_inv_III;
eg_in_IV <= pure_eg_out_III;
eg_V <= eg_out_IV;
end
jt12_sh #( .width(1), .stages(4*num_ch) ) u_cntsh(
.clk ( clk ),
.clk_en ( clk_en ),
.din ( cnt_lsb_II),
.drop ( cnt_in_II )
);
jt12_sh_rst #( .width(10), .stages(4*num_ch-3), .rstval(1'b1) ) u_egsh(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( eg_in_IV ),
.drop ( eg_in_I )
);
jt12_sh_rst #( .width(3), .stages(4*num_ch), .rstval(1'b1) ) u_egstate(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( state_next_I ),
.drop ( state_in_I )
);
jt12_sh_rst #( .width(1), .stages(4*num_ch-3), .rstval(1'b0) ) u_ssg_inv(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( ssg_inv_IV ),
.drop ( ssg_inv_in_I )
);
jt12_sh_rst #( .width(1), .stages(4*num_ch), .rstval(1'b0) ) u_konsh(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( keyon_I ),
.drop ( keyon_last_I )
);
endmodule // jt12_eg
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2010-2012 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may be reproduced or transmitted in any form or by any
// means, electronic or mechanical, including photocopying, recording, or any
// information storage and retrieval system in violation of the license under
// which the source code is released.
//
// The souce code contained herein is free; it may be redistributed and/or
// modified in accordance with the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either version 2.1 of
// the GNU Lesser General Public License, or any later version.
//
// The souce code contained herein is freely released WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
// more details.)
//
// A copy of the GNU Lesser General Public License should have been received
// along with the source code contained herein; if not, a copy can be obtained
// by writing to:
//
// Free Software Foundation, Inc.
// 51 Franklin Street, Fifth Floor
// Boston, MA 02110-1301 USA
//
// Further, no use of this source code is permitted in any form or means
// without inclusion of this banner prominently in any derived works.
//
// Michael A. Morris
// Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: M. A. Morris & Associates
// Engineer: Michael A. Morris
//
// Create Date: 21:48:39 07/10/2010
// Design Name: Booth_Multiplier
// Module Name: C:/XProjects/ISE10.1i/F9408/tb_Booth_Multiplier.v
// Project Name: Booth_Multiplier
// Target Devices: Spartan-3AN
// Tool versions: Xilinx ISE 10.1 SP3
//
// Description:
//
// Verilog Test Fixture created by ISE for module: Booth_Multiplier
//
// Dependencies:
//
// Revision:
//
// 0.01 10G10 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Booth_Multiplier_1xA;
parameter N = 3; // Number of bits = 2**N
// UUT Signals
reg Rst;
reg Clk;
reg Ld;
reg [(2**N - 1):0] M;
reg [(2**N - 1):0] R;
wire Valid, Valid_A;
wire [(2**(N+1) - 1):0] P, P_A;
// Simulation Variables
reg [2**(N+1):0] i;
// Instantiate the Unit Under Test (UUT)
Booth_Multiplier #(
.pN(N)
) uut (
.Rst(Rst),
.Clk(Clk),
.Ld(Ld),
.M(M),
.R(R),
.Valid(Valid),
.P(P)
);
Booth_Multiplier_1xA #(
.N(2**N)
) RevA (
.Rst(Rst),
.Clk(Clk),
.Ld(Ld),
.M(M),
.R(R),
.Valid(Valid_A),
.P(P_A)
);
initial begin
// Initialize Inputs
Rst = 1;
Clk = 1;
Ld = 0;
M = 0;
R = 0;
i = 0;
// Wait 100 ns for global reset to finish
#101 Rst = 0;
// Add stimulus here
@(posedge Clk) #1;
for(i = 0; i < (2**(2**(N+1))); i = i + 1) begin
Ld = 1; M = i[(2**(N+1) - 1):2**N]; R = i[(2**N - 1):0];
@(posedge Clk) #1 Ld = 0;
@(posedge Valid);
if(Valid_A != 1) begin
$display(" Fail - Module did not complete in expected # cycles\n");
$stop;
end
if(P_A != P) begin
$display(" Fail - Module output does not equal expected value\n");
$stop;
end
end
// Exit - End of Test
M = 0; R = 0;
@(posedge Clk) #1;
@(posedge Clk) #1;
@(posedge Clk) #1;
@(posedge Clk) #1;
$display(" Pass - Module performed as expected\n");
$stop;
end
////////////////////////////////////////////////////////////////////////////////
always #5 Clk = ~Clk;
////////////////////////////////////////////////////////////////////////////////
endmodule
|
#include <bits/stdc++.h> using namespace std; int rec[40][40][40][40], con[40][40][40][40], r[40][40]; int main() { int n, m, q, a, c, b, d, i, j, k, l; string s[50]; scanf( %d %d %d , &n, &m, &q); for (i = 0; i < n; i++) { cin >> s[i]; } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { r[i][j] = s[i][j] - 0 ; } } rec[0][0][0][0] = r[0][0]; for (j = 1; j < m; j++) { rec[0][0][0][j] = rec[0][0][0][j - 1] + r[0][j]; } for (i = 1; i < n; i++) { rec[0][0][i][0] = rec[0][0][i - 1][0] + r[i][0]; for (j = 1; j < m; j++) { rec[0][0][i][j] = rec[0][0][i - 1][j] + rec[0][0][i][j - 1] - rec[0][0][i - 1][j - 1] + r[i][j]; } } for (j = 1; j < m; j++) { for (k = 0; k < n; k++) { for (l = j; l < m; l++) { rec[0][j][k][l] = rec[0][0][k][l] - rec[0][0][k][j - 1]; } } } for (i = 1; i < n; i++) { for (k = i; k < n; k++) { for (l = 0; l < m; l++) { rec[i][0][k][l] = rec[0][0][k][l] - rec[0][0][i - 1][l]; } } } for (i = 1; i < n; i++) { for (j = 1; j < m; j++) { for (k = i; k < n; k++) { for (l = j; l < m; l++) { rec[i][j][k][l] = rec[0][0][k][l] - rec[0][0][i - 1][l] - rec[0][0][k][j - 1] + rec[0][0][i - 1][j - 1]; } } } } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { for (k = i; k < n; k++) { for (l = j; l < m; l++) { if (rec[i][j][k][l] == 0) rec[i][j][k][l] = 1; else rec[i][j][k][l] = 0; } } } } for (a = 0; a < n; a++) { for (b = 0; b < m; b++) { con[a][b][a][b] = rec[a][b][a][b]; for (k = a + 1; k < n; k++) { con[a][b][k][b] = con[a][b][k - 1][b]; for (i = a; i <= k; i++) { con[a][b][k][b] += rec[i][b][k][b]; } } for (l = b + 1; l < m; l++) { con[a][b][a][l] = con[a][b][a][l - 1]; for (j = b; j <= l; j++) { con[a][b][a][l] += rec[a][j][a][l]; } } for (k = a + 1; k < n; k++) { for (l = b + 1; l < m; l++) { con[a][b][k][l] = con[a][b][k - 1][l] + con[a][b][k][l - 1] - con[a][b][k - 1][l - 1]; for (i = a; i <= k; i++) { for (j = b; j <= l; j++) { con[a][b][k][l] += rec[i][j][k][l]; } } } } } } for (i = 0; i < q; i++) { scanf( %d %d %d %d , &a, &b, &c, &d); printf( %d n , con[a - 1][b - 1][c - 1][d - 1]); } }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 2000 * 100 + 100; vector<pair<int, int> > c[maxN]; bool mark[maxN]; bool used[maxN]; int arr[maxN], ind; int st[maxN]; struct Ans { int x, y, z; }; void dfs(int s) { mark[s] = true; st[s] = ind; arr[ind++] = s; for (auto x : c[s]) if (!mark[x.first]) dfs(x.first); } vector<Ans> ans; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--; v--; c[u].push_back({v, i}); c[v].push_back({u, i}); } for (int i = 0; i < n; i++) if (!mark[i]) dfs(i); reverse(arr, arr + n); for (int t = 0; t < n; t++) { int s = arr[t]; sort(c[s].begin(), c[s].end(), [](pair<int, int> a, pair<int, int> b) { return st[a.first] > st[b.first]; }); pair<int, int> last(-1, -1); for (auto x : c[s]) if (!used[x.second]) { if (last.first == -1) last = x; else { ans.push_back({last.first + 1, s + 1, x.first + 1}); used[last.second] = true; used[x.second] = true; last = pair<int, int>(-1, -1); } } } cout << ans.size() << n ; for (auto x : ans) cout << x.x << << x.y << << x.z << n ; }
|
#include <bits/stdc++.h> using namespace std; long long a[31]; int main() { long long t, n; long long q = 0; cin >> t; for (int i = 0; i <= 29; i++) { a[i] = pow(2, i); } for (int i = 1; i <= t; i++) { cin >> n; if (n % 2 == 0) { q = (n + 1) * (n / 2); } else { q = ((n / 2) + 1) * n; } for (int i = 0; i <= 29; i++) { if (a[i] <= n) { q = q - (a[i] * 2); } else { break; } } cout << q << endl; q = 0; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Point { double x, y; Point() {} Point(double a, double b) { x = a; y = b; } Point operator+(Point who) { return {x + who.x, y + who.y}; } Point operator-(Point who) { return {x - who.x, y - who.y}; } Point operator/(double val) { return {x / val, y / val}; } Point operator*(double val) { return {x * val, y * val}; } bool operator==(const Point who) const { return max(abs(x - who.x), abs(y - who.y)) <= 1e-7; } bool operator<(const Point who) const { if (*this == who) return false; return make_pair(x, y) < make_pair(who.x, who.y); } }; struct Line { double a, b, c; Line(){}; Line(double _a, double _b, double _c) { a = _a; b = _b; c = _c; } Line(Point A, Point B) { a = B.y - A.y; b = A.x - B.x; c = -(A.x * a + B.x * b); } Line operator||(Point A) { return {a, b, -(a * A.x + b * A.y)}; } Line perp() { Line ans = {a, b, c}; swap(ans.a, ans.b); ans.a *= -1; return ans; } Point intersect(Line who) { double up_x = who.c * b - c * who.b; double up_y = c * who.a - a * who.c; double down = a * who.b - b * who.a; return {up_x / down, up_y / down}; } bool is_parallel(Line who) { return abs(a * who.b - b * who.a) <= 1e-7; } }; int n, i, j, ans; Point P[2017], mid, Origin(0.00, 0.00); bool used[2017]; Line aux; Point _P[2017], _mid; map<Point, int> M; vector<Line> ant; void remove_sym() { int i, j; for (i = 1; i <= n; i++) { for (j = i; j <= n; j++) { if (used[j]) continue; if (P[i] + P[j] == mid * 2) { used[i] = used[j] = true; break; } } } } Point get_proj(Point A, Line L) { Line aux = (L.perp() || A); return aux.intersect(L); } bool check(Line act) { int i; int rm = 0; Point sym; M.clear(); _mid = get_proj(mid, act); for (i = 1; i <= n; i++) { _P[i] = get_proj(P[i], act); if (_P[i] == _mid) { rm++; continue; } sym = _mid * 2 - _P[i]; if (M[sym] > 0) { rm += 2; M[sym]--; continue; } M[_P[i]]++; } if (rm != n) return false; return true; } int main() { scanf( %d , &n); mid = {0, 0}; for (i = 1; i <= n; i++) { scanf( %lf%lf , &P[i].x, &P[i].y); mid = mid + P[i]; } mid = mid / n; remove_sym(); for (i = 1; used[i] && i <= n; i++) ; if (i == n + 1) { printf( -1 ); return 0; } for (j = i; j <= n; j++) { if (used[j]) continue; aux = Line(mid, (P[i] + P[j]) / 2); aux = (aux.perp() || Origin); bool ok = true; for (auto e : ant) { if (e.is_parallel(aux)) { ok = false; break; } } if (!ok) continue; ant.push_back(aux); if (check(aux)) ans++; } printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[2][100100]; int visit[100100]; int v[100100]; int main() { int i, j; int n, m; while (scanf( %d %d , &n, &m) != EOF) { memset(dp, 0, sizeof(dp)); for (i = 1; i <= n; i++) { scanf( %d , &v[i]); if (v[i] < 0) { dp[0][-v[i]]++; dp[0][0]++; } else { dp[1][v[i]]++; dp[1][0]++; } } memset(visit, 0, sizeof(visit)); int flag = 0; for (i = 1; i <= n; i++) { if (dp[1][i] + dp[0][0] - dp[0][i] == m) { visit[i] += 1; flag++; } } for (i = 1; i <= n; i++) { int now = v[i]; if (now < 0) now = 0 - now; if (v[i] > 0) { if (visit[v[i]] != 1) printf( Lie n ); else if (flag == 1) printf( Truth n ); else printf( Not defined n ); } else { if (visit[-v[i]] == 0) printf( Truth n ); else if (flag == 1) printf( Lie n ); else printf( Not defined n ); } } } return 0; }
|
// Copyright 2009, Brian Swetland. Use at your own risk.
// Hacked by Travis Geiselbrecht, 2009-2012
/*
* Copyright (c) 2011-2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
module regfile_zero #(parameter WIDTH=32, parameter RSELWIDTH=4) (
input clk,
input rst,
input we,
input [RSELWIDTH-1:0] wsel, input [WIDTH-1:0] wdata,
input [RSELWIDTH-1:0] asel, output [WIDTH-1:0] adata,
input [RSELWIDTH-1:0] bsel, output [WIDTH-1:0] bdata
);
reg [WIDTH-1:0] R[0:2**RSELWIDTH-1];
integer k;
always @ (posedge clk)
begin
if (rst) begin
for (k = 0; k < 2**RSELWIDTH; k = k + 1) R[k] = 0;
end else if (we && wsel != 0) begin
R[wsel] = wdata;
$display("reg write %h data %h", wsel, wdata);
end
end
assign adata = R[asel];
assign bdata = R[bsel];
endmodule
// regfile1out
module regfile1out #(parameter WIDTH=32, parameter RSELWIDTH=4) (
input clk,
input we, input [RSELWIDTH-1:0] wsel, input [WIDTH-1:0] wdata,
input [RSELWIDTH-1:0] asel, output [WIDTH-1:0] adata
);
reg [WIDTH-1:0] R[0:2**RSELWIDTH-1];
integer k;
initial begin
for (k = 0; k < 2**RSELWIDTH; k = k + 1) R[k] = 0;
end
always @ (posedge clk)
begin
if (we)
begin
R[wsel] <= wdata;
$display("reg write %h data %h", wsel, wdata);
end
end
assign adata = R[asel];
endmodule
// regfile_cr
module regfile_cr #(parameter WIDTH=32, parameter RSELWIDTH=4) (
input clk,
input we, input [RSELWIDTH-1:0] wsel, input [WIDTH-1:0] wdata,
input [RSELWIDTH-1:0] asel, output [WIDTH-1:0] adata
);
reg [WIDTH-1:0] R[0:2**RSELWIDTH-1];
integer k;
initial begin
for (k = 0; k < 2**RSELWIDTH; k = k + 1) R[k] = 0;
end
always @ (posedge clk)
begin
if (we)
begin
if (wsel[RSELWIDTH-1]) begin
R[wsel[RSELWIDTH-2:0]] <= ~wdata;
end else begin
R[wsel[RSELWIDTH-2:0]] <= wdata;
end
$display("reg write %h data %h", wsel, wdata);
end
end
assign adata = (asel[RSELWIDTH-1] ? ~R[asel[RSELWIDTH-2:0]] : R[asel]);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FA_BEHAVIORAL_V
`define SKY130_FD_SC_HD__FA_BEHAVIORAL_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FA_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int min(int a, int b) { if (a < b) return a; return b; } int Abs(int a) { if (a < 0) return -a; else return a; } double Abs(double a) { if (a < 0) return -a; else return a; } unsigned long long sqr(unsigned long long a) { return a * a; } double sqr(double a) { return a * a; } int main() { int a, b, c; cin >> a >> b; c = 0; while (b) { c = c * 10 + b % 10; b /= 10; } cout << a + c << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int solve(int w, int h, int S) { if (S == (2 * w + 1) * (2 * h + 1)) return 2 * (w + 1) * (h + 1) - 1; if (S > (2 * w + 1) * (2 * h + 1)) return 0; S = (2 * w + 1) * (2 * h + 1) - S; if (S & 3) return 0; S /= 4; int res = 0; for (int w2 = 0; w2 < w; w2++) { if (S % (w - w2)) continue; int h2 = h - S / (w - w2); if (h2 < 0 || h2 >= h) continue; res++; } return 2 * res; } int main() { int W, H, s; while (scanf( %d%d%d , &W, &H, &s) >= 1) { long long ans = 0; for (int w = 0; 2 * w + 1 <= W; w++) { for (int h = 0; 2 * h + 1 <= H; h++) { ans += solve(w, h, s) * (long long)(W - (2 * w + 1) + 1) * (H - (2 * h + 1) + 1); } } printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int H_MAX = 100100; const int N_MAX = 200100; int H, N; int layers[H_MAX]; int tree1[N_MAX]; int tree2[N_MAX]; int main() { N = 0; cin >> H; for (int i = 0; i <= H; i++) { cin >> layers[i]; N += layers[i]; } assert(layers[0] == 1); tree1[0] = tree2[0] = -1; bool ambiguous = false; int cur = 1; for (int i = 1; i <= H; i++) { for (int j = 0; j < layers[i]; j++) tree1[cur + j] = tree2[cur + j] = cur - 1; if (layers[i - 1] > 1 && layers[i] > 1) { ambiguous = true; tree2[cur + layers[i] - 1] = cur - 2; } cur += layers[i]; } if (ambiguous) { cout << ambiguous n ; for (int i = 0; i < N; i++) cout << tree1[i] + 1 << (i < N - 1 ? : n ); for (int i = 0; i < N; i++) cout << tree2[i] + 1 << (i < N - 1 ? : n ); } else { cout << perfect n ; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/13/2015 11:06:55 AM
// Design Name:
// Module Name: SD_Control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Need to add timeouts for command response states and handle additional response errors.
//
//////////////////////////////////////////////////////////////////////////////////
module SD_Control(
input SD_Clock, //200MHz
input Reset, //Active-High
input [7:0] SD_Data_in,
output reg Write_out, //Active-High
output Clock_Speed, // 0 = 400KHz, 1 = 25MHz
output reg [7:0] SD_Data_out,
output CS_out,
input Data_Send_Complete,
output reg [4:0] CurrentState,
input Read_in,
input Write_in,
output Ready_out,
input [29:0] Address_in,
input [4095:0] DDR_Data_out,
output reg [4095:0] DDR_Data_in);
wire [2:0] BitCount;
wire [8:0] ByteCount;
reg [4:0] NextState;
wire CountReset, BitEnable, ByteEnable;
parameter SD_STATE_INIT = 5'b00000;
parameter SD_STATE_CMD0 = 5'b00001;
parameter SD_STATE_CMD0_Response = 5'b00010;
parameter SD_STATE_DELAY1 = 5'b00011;
parameter SD_STATE_CMD55 = 5'b00100;
parameter SD_STATE_CMD55_Response = 5'b00101;
parameter SD_STATE_DELAY2 = 5'b00110;
parameter SD_STATE_ACMD41 = 5'b00111;
parameter SD_STATE_ACMD41_Response = 5'b01000;
parameter SD_STATE_IDLE = 5'b01001;
parameter SD_STATE_CMD17 = 5'b01010;
parameter SD_STATE_CMD17_Response = 5'b01011;
parameter SD_STATE_READTOKEN = 5'b01100;
parameter SD_STATE_READBLOCK = 5'b01101;
parameter SD_STATE_READCRC = 5'b01110;
parameter SD_STATE_READACK = 5'b01111;
parameter SD_STATE_CMD24 = 5'b10000;
parameter SD_STATE_CMD24_Response = 5'b10001;
parameter SD_STATE_WRITEDELAY = 5'b10010;
parameter SD_STATE_WRITETOKEN = 5'b10011;
parameter SD_STATE_WRITEBLOCK = 5'b10100;
parameter SD_STATE_WRITECRC = 5'b10101;
parameter SD_STATE_WRITERESPONSE = 5'b10110;
parameter SD_STATE_WRITEACK = 5'b10111;
initial DDR_Data_in = 4095'd0;
Counter #(.CountWidth(3)) Bit(
.Clock_in (SD_Clock),
.Enable_in (BitEnable),
.Reset_in (CountReset),
.Count_out (BitCount));
Counter #(.CountWidth(9)) Byte(
.Clock_in (SD_Clock),
.Enable_in (ByteEnable),
.Reset_in (CountReset),
.Count_out (ByteCount));
// Assignments
assign Ready_out = (CurrentState == SD_STATE_READACK || CurrentState == SD_STATE_WRITEACK);
assign CS_out = (CurrentState == SD_STATE_INIT);
assign Clock_Speed = ~(CurrentState == SD_STATE_INIT || CurrentState == SD_STATE_CMD0 || CurrentState == SD_STATE_CMD0_Response
|| CurrentState == SD_STATE_DELAY1 || CurrentState == SD_STATE_CMD55 || CurrentState == SD_STATE_CMD55_Response
|| CurrentState == SD_STATE_DELAY2 || CurrentState == SD_STATE_ACMD41 || CurrentState == SD_STATE_ACMD41_Response);
assign BitEnable = ~((CurrentState == SD_STATE_IDLE) && (SD_Data_in[0] == 1'b0)); //Disable all counting while SD card is busy.
assign ByteEnable = ((BitCount==3'd7)&&~(CurrentState == SD_STATE_IDLE && ByteCount == 9'd1))||(CurrentState == SD_STATE_WRITEBLOCK); //Ensure atleast 1Byte delay between end of reads and writes.
assign CountReset = (Reset) || ((CurrentState == SD_STATE_INIT) && (ByteCount == 9'd9) && (BitCount == 3'd2)) ||
((CurrentState == SD_STATE_CMD0_Response) && (~SD_Data_in[7])) ||
((CurrentState == SD_STATE_CMD55_Response) && (~SD_Data_in[7])) ||
((CurrentState == SD_STATE_ACMD41_Response) && (~SD_Data_in[7])) ||
((CurrentState == SD_STATE_DELAY1) && (ByteCount == 9'd1)) ||
((CurrentState == SD_STATE_DELAY2) && (ByteCount == 9'd1)) ||
((CurrentState == SD_STATE_IDLE) && (ByteCount == 9'd1) && ((~Write_in)||(~Read_in))) ||
((CurrentState == SD_STATE_READTOKEN) && (~SD_Data_in[0])) ||
((CurrentState == SD_STATE_CMD24_Response) && (~SD_Data_in[7])) ||
(CurrentState == SD_STATE_WRITETOKEN);
always @ (posedge SD_Clock)
begin
Write_out = ((CurrentState == SD_STATE_CMD0)||(CurrentState == SD_STATE_CMD55)||(CurrentState == SD_STATE_ACMD41)||
(CurrentState == SD_STATE_CMD17)||(CurrentState == SD_STATE_CMD24)||(CurrentState == SD_STATE_WRITETOKEN)||
(CurrentState == SD_STATE_WRITEBLOCK)||(CurrentState == SD_STATE_WRITECRC));
//Data Out
case (CurrentState)
SD_STATE_CMD0:
case (BitCount)
3'd0 : SD_Data_out = 8'h40;
3'd5 : SD_Data_out = 8'h95;
default : SD_Data_out = 8'h00;
endcase
SD_STATE_CMD55:
case (BitCount)
3'd0 : SD_Data_out = 8'h77;
default : SD_Data_out = 8'h00;
endcase
SD_STATE_ACMD41:
case (BitCount)
3'd0 : SD_Data_out = 8'h69;
default : SD_Data_out = 8'h00;
endcase
SD_STATE_CMD17:
case (BitCount)
3'd0 : SD_Data_out = 8'h51;
3'd1 : SD_Data_out = Address_in[29:22];
3'd2 : SD_Data_out = Address_in[21:14];
3'd3 : SD_Data_out = Address_in[13:6];
3'd4 : SD_Data_out = {Address_in[5:0],2'b0};
default : SD_Data_out = 8'h00;
endcase
SD_STATE_CMD24:
case (BitCount)
3'd0 : SD_Data_out = 8'h58;
3'd1 : SD_Data_out = Address_in[29:22];
3'd2 : SD_Data_out = Address_in[21:14];
3'd3 : SD_Data_out = Address_in[13:6];
3'd4 : SD_Data_out = {Address_in[5:0],2'b0};
default : SD_Data_out = 8'h00;
endcase
SD_STATE_WRITETOKEN:
SD_Data_out = 8'hfe;
SD_STATE_WRITEBLOCK:
SD_Data_out = DDR_Data_out[4095-(8*ByteCount)-:8];
default : SD_Data_out = 8'hff;
endcase
//Data In
if ((CurrentState == SD_STATE_READBLOCK) && (BitCount == 3'd7)) DDR_Data_in[4095-(8*ByteCount)-:8] = SD_Data_in;
end
// Synchronous State Transistion
always @ (posedge SD_Clock) CurrentState = (Reset) ? SD_STATE_INIT : NextState;
// State Logic
always @ (*)
case (CurrentState)
SD_STATE_INIT : NextState = (ByteCount == 9'd9 && BitCount == 3'd2) ? SD_STATE_CMD0 : SD_STATE_INIT;
SD_STATE_CMD0 : NextState = (BitCount == 3'd5) ? SD_STATE_CMD0_Response : SD_STATE_CMD0;
SD_STATE_CMD0_Response : NextState = (~SD_Data_in[7]) ? (SD_Data_in == 8'h01) ? SD_STATE_DELAY1 : SD_STATE_INIT : SD_STATE_CMD0_Response;
SD_STATE_DELAY1 : NextState = (ByteCount == 9'd1) ? SD_STATE_CMD55 : SD_STATE_DELAY1;
SD_STATE_CMD55 : NextState = (BitCount == 3'd5) ? SD_STATE_CMD55_Response : SD_STATE_CMD55;
SD_STATE_CMD55_Response : NextState = (~SD_Data_in[7]) ? (SD_Data_in == 8'h01) ? SD_STATE_DELAY2 : SD_STATE_INIT : SD_STATE_CMD55_Response;
SD_STATE_DELAY2 : NextState = (ByteCount == 9'd1) ? SD_STATE_ACMD41 : SD_STATE_DELAY2;
SD_STATE_ACMD41 : NextState = (BitCount == 3'd5) ? SD_STATE_ACMD41_Response : SD_STATE_ACMD41;
SD_STATE_ACMD41_Response : NextState = (~SD_Data_in[7]) ? (SD_Data_in == 8'h00) ? SD_STATE_IDLE : (SD_Data_in == 8'b01) ? SD_STATE_CMD55 : SD_STATE_INIT : SD_STATE_ACMD41_Response;
SD_STATE_IDLE : NextState = (ByteCount == 9'd1) ? (Write_in) ? SD_STATE_CMD24 : (Read_in) ? SD_STATE_CMD17 : SD_STATE_IDLE : SD_STATE_IDLE;
SD_STATE_CMD17 : NextState = (BitCount == 3'd5) ? SD_STATE_CMD17_Response : SD_STATE_CMD17;
SD_STATE_CMD17_Response : NextState = (ByteCount == 9'd20) ? SD_STATE_CMD17 : (~SD_Data_in[7]) ? (SD_Data_in == 8'h00) ? SD_STATE_READTOKEN : (SD_Data_in == 8'h01) ? SD_STATE_INIT : SD_STATE_CMD24 : SD_STATE_CMD17_Response;
SD_STATE_READTOKEN : NextState = (~SD_Data_in[0]) ? SD_STATE_READBLOCK : SD_STATE_READTOKEN;
SD_STATE_READBLOCK : NextState = ((ByteCount == 9'd511) && (BitCount == 3'd7)) ? SD_STATE_READCRC : SD_STATE_READBLOCK;
SD_STATE_READCRC : NextState = (ByteCount == 9'd2) ? SD_STATE_READACK : SD_STATE_READCRC;
SD_STATE_READACK : NextState = (~Read_in) ? SD_STATE_IDLE : SD_STATE_READACK;
SD_STATE_CMD24 : NextState = (BitCount == 3'd5) ? SD_STATE_CMD24_Response : SD_STATE_CMD24;
SD_STATE_CMD24_Response : NextState = (ByteCount == 9'd20) ? SD_STATE_CMD24 : (~SD_Data_in[7]) ? (SD_Data_in == 8'h00) ? SD_STATE_WRITEDELAY : (SD_Data_in == 8'h01) ? SD_STATE_INIT : SD_STATE_CMD24 : SD_STATE_CMD24_Response;
SD_STATE_WRITEDELAY : NextState = (ByteCount == 9'd1) ? SD_STATE_WRITETOKEN : SD_STATE_WRITEDELAY;
SD_STATE_WRITETOKEN : NextState = SD_STATE_WRITEBLOCK;
SD_STATE_WRITEBLOCK : NextState = (ByteCount == 9'd511) ? SD_STATE_WRITECRC : SD_STATE_WRITEBLOCK;
SD_STATE_WRITECRC : NextState = (ByteCount == 9'd2) ? SD_STATE_WRITERESPONSE : SD_STATE_WRITECRC;
SD_STATE_WRITERESPONSE : NextState = (SD_Data_in[4:0]==5'b00101) ? SD_STATE_WRITEACK : (SD_Data_in[4:0]==5'b01011 || SD_Data_in[4:0]==5'b01101) ? SD_STATE_IDLE : SD_STATE_WRITERESPONSE;
SD_STATE_WRITEACK : NextState = (~Write_in) ? SD_STATE_IDLE : SD_STATE_WRITEACK;
default : NextState = SD_STATE_INIT;
endcase
endmodule
|
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : gmii_if.v
// Version : 0.2
// Author : Shreejith S
//
// Description: GMII Interface Description - XILINX
//
//-----------------------------------------------------------------------------
//
// (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// Description: This module creates a Gigabit Media Independent
// Interface (GMII) by instantiating Input/Output buffers
// and Input/Output flip-flops as required.
//
// This interface is used to connect the Ethernet MAC to
// an external Ethernet PHY via GMII connection.
//
// The GMII receiver clocking logic is also defined here: the
// receiver clock received from the PHY is unique and cannot be
// shared across multiple instantiations of the core. For the
// receiver clock:
//
// A BUFIO/BUFR combination is used for the input clock to allow
// the use of IODELAYs on the DATA.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module gmii_if (
// Synchronous resets
input tx_reset,
input rx_reset,
// Current operating speed is 10/100
input speed_is_10_100,
// The following ports are the GMII physical interface: these will be at
// pins on the FPGA
(* IOB = "TRUE" *)
output reg [7:0] gmii_txd,
(* IOB = "TRUE" *)
output reg gmii_tx_en,
(* IOB = "TRUE" *)
output reg gmii_tx_er,
output gmii_tx_clk,
input gmii_crs,
input gmii_col,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
input gmii_rx_clk,
// The following ports are the internal GMII connections from IOB logic to
// the TEMAC core
input [7:0] txd_from_mac,
input tx_en_from_mac,
input tx_er_from_mac,
input tx_clk,
output crs_to_mac,
output col_to_mac,
(* IOB = "TRUE" *)
output reg [7:0] rxd_to_mac,
(* IOB = "TRUE" *)
output reg rx_dv_to_mac,
(* IOB = "TRUE" *)
output reg rx_er_to_mac,
// Receiver clock for the MAC and Client Logic
output rx_clk
);
//----------------------------------------------------------------------------
// internal signals
//----------------------------------------------------------------------------
(* ASYNC_REG = "TRUE" *)
reg gmii_col_reg;
reg gmii_col_reg_reg ;
wire gmii_rx_dv_delay;
wire gmii_rx_er_delay;
wire [7:0] gmii_rxd_delay;
wire gmii_rx_clk_bufio;
wire rx_clk_int;
//----------------------------------------------------------------------------
// GMII Transmitter Clock Management :
// drive gmii_tx_clk through IOB onto GMII interface
//----------------------------------------------------------------------------
// Instantiate a DDR output register. This is a good way to drive
// GMII_TX_CLK since the clock-to-PAD delay will be the same as that
// for data driven from IOB Ouput flip-flops eg gmii_rxd[7:0].
// This is set to produce an inverted clock w.r.t. gmii_tx_clk_int
// so that the rising edge is centralised within the
// gmii_rxd[7:0] valid window.
ODDR gmii_tx_clk_ddr_iob (
.Q (gmii_tx_clk),
.C (tx_clk),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (1'b0),
.S (1'b0)
);
//---------------------------------------------------------------------------
// GMII Transmitter Logic : drive TX signals through IOBs registers onto
// GMII interface
//---------------------------------------------------------------------------
// Infer IOB Output flip-flops.
always @(posedge tx_clk)
begin
gmii_tx_en <= tx_en_from_mac;
gmii_tx_er <= tx_er_from_mac;
gmii_txd <= txd_from_mac;
end
// GMII_CRS is an asynchronous signal which is routed straight through to the
// core
assign crs_to_mac = gmii_crs;
// GMII_COL is an asynchronous signal. Here is registered, then 'stretched'
// to ensure that the MAC will see it.
always @(posedge tx_clk)
begin
if (tx_reset == 1'b1) begin
gmii_col_reg <= 1'b0;
gmii_col_reg_reg <= 1'b0;
end
else begin
gmii_col_reg <= gmii_col;
gmii_col_reg_reg <= gmii_col_reg;
end
end
assign col_to_mac = gmii_col_reg_reg | gmii_col_reg | gmii_col;
//---------------------------------------------------------------------------
// GMII Receiver Clock Logic
//---------------------------------------------------------------------------
// Route gmii_rx_clk through a BUFIO/BUFR and onto regional clock routing
BUFIO bufio_gmii_rx_clk (
.I (gmii_rx_clk),
.O (gmii_rx_clk_bufio)
);
// Route rx_clk through a BUFR onto regional clock routing
BUFR bufr_gmii_rx_clk (
.I (gmii_rx_clk),
.CE (1'b1),
.CLR (1'b0),
.O (rx_clk_int)
);
// Assign the internal clock signal to the output port
assign rx_clk = rx_clk_int;
//---------------------------------------------------------------------------
// GMII Receiver Logic : receive RX signals through IOBs from GMII interface
//---------------------------------------------------------------------------
// Use IDELAY to delay data to the capturing register.
// Note: Delay value is set in UCF file
// Please modify the IOBDELAY_VALUE according to your design.
// For more information on IDELAYCTRL and IDELAY, please refer to
// the User Guide.
IODELAYE1 #(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("I"),
.IDELAY_VALUE (23)
)
delay_gmii_rx_dv (
.IDATAIN (gmii_rx_dv),
.ODATAIN (1'b0),
.DATAOUT (gmii_rx_dv_delay),
.DATAIN (1'b0),
.C (1'b0),
.T (1'b1),
.CE (1'b0),
.CINVCTRL (1'b0),
.CLKIN (1'b0),
.CNTVALUEIN (5'h0),
.INC (1'b0),
.RST (1'b0)
);
IODELAYE1 #(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("I"),
.IDELAY_VALUE (23)
)
delay_gmii_rx_er (
.IDATAIN (gmii_rx_er),
.ODATAIN (1'b0),
.DATAOUT (gmii_rx_er_delay),
.DATAIN (1'b0),
.C (1'b0),
.T (1'b1),
.CE (1'b0),
.CINVCTRL (1'b0),
.CLKIN (1'b0),
.CNTVALUEIN (5'h0),
.INC (1'b0),
.RST (1'b0)
);
genvar i;
generate for (i=0; i<8; i=i+1)
begin : gmii_data_bus0
IODELAYE1 #(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("I"),
.IDELAY_VALUE (23)
)
delay_gmii_rxd (
.IDATAIN (gmii_rxd[i]),
.ODATAIN (1'b0),
.DATAOUT (gmii_rxd_delay[i]),
.DATAIN (1'b0),
.C (1'b0),
.T (1'b1),
.CE (1'b0),
.CINVCTRL (1'b0),
.CLKIN (1'b0),
.CNTVALUEIN (5'h0),
.INC (1'b0),
.RST (1'b0)
);
end
endgenerate
// Infer IOB Input flip-flops.
always @(posedge gmii_rx_clk_bufio)
begin
rx_dv_to_mac <= gmii_rx_dv_delay;
rx_er_to_mac <= gmii_rx_er_delay;
rxd_to_mac <= gmii_rxd_delay;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); long count[] = {0, 0, 0, 0}; long n; cin >> n; while (n--) { long x; cin >> x; count[x] += 1; } cout << min(min(count[1] + count[2], count[1] + count[3]), count[2] + count[3]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int max_n = 300005; int n, m; int p[max_n]; int rk[max_n]; bool vis[max_n]; vector<int> G[max_n]; set<int> s; void dfs(int u) { for (auto v : G[u]) s.erase(rk[v]); vector<int> can; for (auto v : s) { if (v < rk[u]) { v = p[v]; can.push_back(v); vis[rk[v]] = true; } else break; } for (auto v : G[u]) if (!vis[rk[v]]) s.insert(rk[v]); for (auto v : can) s.erase(rk[v]); for (auto v : can) dfs(v); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , p + i), rk[p[i]] = i; for (int i = 0; i < m; i++) { int u, v; scanf( %d%d , &u, &v); G[v].push_back(u); } for (int i = 1; i <= n - 1; i++) s.insert(i); vis[n] = true; dfs(p[n]); printf( %d n , s.size()); return 0; }
|
module top (
fpga_clk_50,
fpga_reset_n,
fpga_led_output,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl
);
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [3:0] fpga_led_output;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
wire [29:0] fpga_internal_led;
wire kernel_clk;
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl)
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
endmodule
module async_counter_30(clk, count);
input clk;
output [29:0] count;
reg [14:0] count_a;
reg [14:0] count_b;
initial count_a = 15'b0;
initial count_b = 15'b0;
always @(negedge clk)
count_a <= count_a + 1'b1;
always @(negedge count_a[14])
count_b <= count_b + 1'b1;
assign count = {count_b, count_a};
endmodule
|
module main(
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
output int_n,
output nmi_n,
output wait_n,
output res,
inout [7:0] d,
input [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
output rompg0_n,
output dos_n, // aka rompg1
output rompg2,
output rompg3,
output rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
inout [15:0] rd,
output [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
output [1:0] vred,
output [1:0] vgrn,
output [1:0] vblu,
output vhsync,
output vvsync,
output vcsync,
// AY control and audio/tape
output ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
output [2:0] ide_a,
inout [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
output vg_clk,
output vg_cs_n,
output vg_res_n,
output vg_hrdy,
output vg_rclk,
output vg_rawr,
output [1:0] vg_a, // disk drive selection
output vg_wrd,
output vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
output spiint_n
);
wire zclk; // z80 clock for short
reg [2:0] zclk_gen; // make 3.5 mhz clock
wire rst_n; // global reset
wire rrdy;
wire cbeg;
wire [15:0] rddata;
wire [4:0] rompg;
wire [7:0] zports_dout;
wire zports_dataout;
wire porthit;
wire [4:0] keys;
wire tape_in;
wire [15:0] ideout;
wire [15:0] idein;
wire [7:0] zmem_dout;
wire zmem_dataout;
wire [7:0] sd_dout_to_zports;
wire start_from_zports;
wire sd_inserted;
wire sd_readonly;
reg [3:0] ayclk_gen;
wire [7:0] received;
wire [7:0] tobesent;
wire intrq,drq;
wire vg_wrFF;
// Z80 clock control
assign zclk = clkz_in;
always @(posedge fclk)
zclk_gen <= zclk_gen + 3'd1;
assign clkz_out = zclk_gen[2];
/* // RESETTER
resetter myrst( .clk(fclk),
.rst_in1_n(1'b1),
.rst_in2_n(1'b1),
.rst_out_n(rst_n) );
defparam myrst.RST_CNT_SIZE = 6;
*/
dram mydram( .clk(fclk),
.rst_n(1'b1),
.ra(ra),
.rd(rd),
.rwe_n(rwe_n),
.rras0_n(rras0_n),
.rras1_n(rras1_n),
.rucas_n(rucas_n),
.rlcas_n(rlcas_n),
.req(1'b0),
.rnw(1'b1)//,
//.rrdy(rrdy),
//.cbeg(cbeg),
//.bsel({a[0],~a[0]}),
//.wrdata({d,~d}),
//.rddata(rddata),
/*.addr({a[5:0],a[15:1]})*/ );
assign int_n=1'b1;
assign nmi_n=1'b1;
assign wait_n=1'b1;
assign res=1'b1;
assign d=8'hZZ;
assign csrom=1'b0;
assign romoe_n=1'b1;
assign romwe_n=1'b1;
assign iorq1_n=1'b1;
assign iorq2_n=1'b1;
assign rd=16'hZZZZ;
assign ay_bdir=1'b0;
assign ay_bc1=1'b0;
assign ide_d=16'hZZZZ;
assign ide_dir=1'b1;
assign ide_rs_n = 1'b0;
assign ide_cs1_n = 1'b1;
assign ide_rd_n = 1'b1;
assign ide_wr_n = 1'b1;
assign vg_cs_n=1'b1;
assign vg_res_n=1'b0;
assign sdcs_n=1'b1;
assign spiint_n=1'b1;
//AY control
always @(posedge fclk)
begin
ayclk_gen <= ayclk_gen + 4'd1;
end
assign ay_clk = ayclk_gen[3];
reg [23:0] counter;
reg blinker;
always @(posedge fclk)
begin
if( !counter )
begin
counter <= 24'd13999999;
blinker <= ~blinker;
end
else
counter <= counter - 24'd1;
end
assign ide_cs0_n = blinker;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_TB_V
`define SKY130_FD_SC_LP__EINVN_TB_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__einvn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, nn = 0, range; int a, b, c, d, pos, neg, ok = 1, finddd = 0; int ara[200], ara2[200]; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d %d , &ara[i], &ara2[i]); if (ara2[i] == m || ara[i] == m) { finddd = 1; } } if (n == 1 && ara[0] == 1) { finddd = 0; } for (int i = 1; i < n; i++) { for (int j = 0; j < i; j++) { if (ara[i] <= ara2[j]) { pos = 1; } } if (pos == 1) { ok = 1; } else { ok = 0; break; } pos = 0; neg = 0; } if (ok == 1 && finddd == 1) { printf( YES n ); } else { printf( NO n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; constexpr int N = 3e3; uint16_t a[N], lst[N], nxt[N], cnxt[20], dp[N][N]; int main() { cin.tie(0), ios::sync_with_stdio(0); int t, n; cin >> t; while (t--) { cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i], --a[i]; } memset(lst, 0, n * sizeof *lst); for (int i = 0; i < n; ++i) { ++lst[a[i]]; } int w = -1, r = 0, purged = 0; while (r < n) { if (w >= 0 && a[w] == a[r]) { if (--lst[a[r++]] == 1) { --w; ++purged; } } else if (lst[a[r]] == 1) { ++r; ++purged; } else { a[++w] = a[r++]; } } memset(lst, -1, n * sizeof *lst); n = w + 1; memset(nxt, 127, n * sizeof *nxt); for (int i = 0; i < n; ++i) { if (lst[a[i]] != (uint16_t)-1) { nxt[lst[a[i]]] = i; } lst[a[i]] = i; } for (int i = n - 1; i > -1; --i) { auto* cnxte = cnxt; for (int z = nxt[i]; z < n; z = nxt[z]) { *cnxte++ = z; } *cnxte = n; cnxte = cnxt; for (int j = i + 1; j < n; ++j) { if (a[j] == a[i]) { ++cnxte; } int t = dp[i + 1][j] - 1; #pragma GCC unroll 20 for (const auto* z = cnxt; z < cnxte; ++z) { t = max(t, dp[i + 1][*z - 1] + dp[*z][j]); } dp[i][j] = t + 1; } } cout << (n ? n - dp[0][n - 1] : 0) - 1 + purged << n ; ; } }
|
#include <bits/stdc++.h> using namespace std; int T[1000010][30], cnt = 0, fa[1000010]; char s[400010]; struct Q { int id, x; }; int A[400010], val[400010]; vector<Q> g[1000010]; vector<int> gg[1000010]; queue<int> q; void insert(int id) { int f = 0, i, v; for (i = 0; s[i]; i++) { v = s[i] - a ; if (T[f][v] == 0) T[f][v] = ++cnt; f = T[f][v]; } A[id] = f; } void build() { int i, u, v, p; for (i = 0; i < 27; i++) if (T[0][i]) q.push(T[0][i]); for (; q.size(); q.pop()) { u = q.front(); gg[fa[u]].push_back(u); for (i = 0; i < 27; i++) { v = T[u][i]; if (v) { p = fa[u]; while (p && T[p][i] == 0) p = fa[p]; fa[v] = T[p][i]; q.push(v); } } } } int in[1000010], out[1000010], dfn = 0; void dfs(int u) { int i, v; in[u] = ++dfn; for (i = 0; i < gg[u].size(); i++) { v = gg[u][i]; dfs(v); } out[u] = dfn; } int sum[1000100], ans[400010]; int lb(int x) { return x & -x; } void add(int x, int v) { for (; x <= 1e6; x += lb(x)) sum[x] += v; } int qsum(int x) { int k = 0; for (; x; x -= lb(x)) k += sum[x]; return k; } void dfs1(int u) { int i, v; add(in[u], 1); Q x; for (i = 0; i < g[u].size(); i++) { x = g[u][i]; ans[x.id] = qsum(out[x.x]) - qsum(in[x.x] - 1); } for (i = 0; i < 27; i++) if (T[u][i]) dfs1(T[u][i]); add(in[u], -1); } int main() { int i, n, k, v, u, m, j; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &k); if (k == 1) { scanf( %s , s); v = s[0] - a ; if (T[0][v] == 0) T[0][v] = ++cnt; val[i] = T[0][v]; } else { scanf( %d%s , &k, s); v = s[0] - a ; u = val[k]; if (T[u][v] == 0) T[u][v] = ++cnt; val[i] = T[u][v]; } } scanf( %d , &m); for (i = 1; i <= m; i++) { scanf( %d%s , &k, s); insert(i); g[val[k]].push_back(Q({i, A[i]})); } build(); dfs(0); dfs1(0); for (i = 1; i <= m; i++) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const int Mod = 1000000007; const int INF = 0x3f3f3f3f; const long long LL_INF = 0x3f3f3f3f3f3f3f3f; const double e = exp(1); const double PI = acos(-1); const double ERR = 1e-10; int main() { long long n; scanf( %lld , &n); long long ans = (1LL * (1 + n) * n) / 2; if (ans % 2 == 0) printf( 0 n ); else printf( 1 n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:200000000 ) const double EPS = 1E-9; const int INF = 1000000000; const long long INF64 = (long long)1E18; const double PI = 3.1415926535897932384626433832795; string s[110000]; int n, k, z[110][110], dp[1100000]; char buf[110000]; int main() { scanf( %d%d n , &n, &k); for (int i = 0; i < (int)(n); i++) { scanf( %s , buf); s[i] = buf; } for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(n); j++) { int ans = 0; while (ans < (int)s[i].size() && ans < (int)s[j].size() && s[i][ans] == s[j][ans]) ans++; z[i][j] = ans; } int res = 0; for (int msk = 1; msk < (1 << n); msk++) { int cur; for (int i = 0; i < (int)(n); i++) if (msk & (1 << i)) { cur = i; break; } int val = dp[msk ^ (1 << cur)], cnt = 0; for (int i = 0; i < (int)(n); i++) if ((msk & (1 << i)) && i != cur) { val += z[i][cur]; cnt++; } if (cnt + 1 == k) res = max(res, val); dp[msk] = val; } cout << res << endl; return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 6345 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w2048,
w2047,
w16,
w17,
w68,
w2115,
w8460,
w6345;
assign w1 = i_data0;
assign w16 = w1 << 4;
assign w17 = w1 + w16;
assign w2047 = w2048 - w1;
assign w2048 = w1 << 11;
assign w2115 = w2047 + w68;
assign w6345 = w8460 - w2115;
assign w68 = w17 << 2;
assign w8460 = w2115 << 2;
assign o_data0 = w6345;
//multiplier_block area estimate = 7221.61438694412;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { long long st, en; node() {} node(long long _st, long long _en) : st(_st), en(_en) {} }; int main() { int n, b, t, d; long long etime[200000]; long long ftime; int qlen = 0; cin >> n >> b; cin >> t >> d; etime[0] = t + d; ftime = 1ll * t + d; int len = 0; queue<node> ws; node temp; cout << etime[0] << ; for (int i = 1; i < n; i++) { cin >> t >> d; while (!ws.empty()) { temp = ws.front(); if (t >= temp.st) { ws.pop(); len--; } else break; } if (t < ftime) { if (len < b) { ws.push(node(ftime, ftime + d)); len++; etime[i] = ftime + d; ftime += d; } else { etime[i] = -1; } } else { etime[i] = 1ll * t + d; ftime = 1ll * t + d; } cout << etime[i] << ; } }
|
#include <bits/stdc++.h> using namespace std; template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } const double EPS = 1e-9; const double PI = acos(-1.); const int INF = 1e9; const int MAXN = 2e5 + 5; const long long MOD = 1e9 + 7; void output_path(int n, int a, int b, int c, int d) { cout << a << << c << ; for (int i = (1); i <= (int)(n); i++) { if (i != a && i != b && i != c && i != d) { cout << i << ; } } cout << d << << b << endl; } void solve() { int n, k, a, b, c, d; cin >> n >> k >> a >> b >> c >> d; if (n == 4 || k <= n) { cout << -1 << endl; return; } output_path(n, a, b, c, d); output_path(n, c, d, a, b); } int main() { int t = 1; while (t--) { solve(); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__MUX4_PP_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_PP_BLACKBOX_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Thu Aug 25 17:35:25 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/4-way/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_BEHAVIORAL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd2 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_BEHAVIORAL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc (
clk,
// control ports
control,
status,
// FIFO interface
src_adc_dwr,
src_adc_dsync,
src_adc_ddata,
src_adc_dovf,
dst_adc_dwr,
dst_adc_dsync,
dst_adc_ddata,
dst_adc_dovf
);
parameter CHANNEL_ID = 0;
parameter DATA_WIDTH = 32;
localparam SYMBOL_WIDTH = 2;
localparam RP_ID = 8'hA2;
input clk;
input [31:0] control;
output [31:0] status;
input src_adc_dwr;
input src_adc_dsync;
input [(DATA_WIDTH-1):0] src_adc_ddata;
output src_adc_dovf;
output dst_adc_dwr;
output dst_adc_dsync;
output [(DATA_WIDTH-1):0] dst_adc_ddata;
input dst_adc_dovf;
reg src_adc_dovf = 'h0;
reg dst_adc_dwr = 'h0;
reg dst_adc_dsync = 'h0;
reg [(DATA_WIDTH-1):0] dst_adc_ddata = 'h0;
reg [ 7:0] adc_pn_data = 'hF1;
reg [31:0] status = 'h0;
reg [ 3:0] mode = 'h0;
reg [ 3:0] channel_sel = 'h0;
wire adc_dvalid;
wire [(SYMBOL_WIDTH-1):0] adc_ddata_s;
wire [ 7:0] adc_pn_data_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
reg [ 7:0] dout;
begin
dout[7] = din[6];
dout[6] = din[5];
dout[5] = din[4];
dout[4] = din[3];
dout[3] = din[2];
dout[2] = din[1];
dout[1] = din[7] ^ din[4];
dout[0] = din[6] ^ din[3];
pn = dout;
end
endfunction
// update control and status registers
always @(posedge clk) begin
channel_sel <= control[ 3:0];
mode <= control[ 7:4];
end
assign adc_dvalid = src_adc_dwr & src_adc_dsync;
assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? {adc_pn_data[7:2], adc_ddata_s} : adc_pn_data;
ad_pnmon #(
.DATA_WIDTH(8)
) i_pn_mon (
.adc_clk(clk),
.adc_valid_in(adc_dvalid),
.adc_data_in({adc_pn_data[7:2], adc_ddata_s}),
.adc_data_pn(adc_pn_data_s),
.adc_pn_oos(adc_pn_oos_s),
.adc_pn_err(adc_pn_err_s));
// prbs generation
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
adc_pn_data <= pn(adc_pn_data);
end
end
// qpsk demodulator
qpsk_demod i_qpsk_demod1 (
.clk(clk),
.data_qpsk_i(src_adc_ddata[15: 0]),
.data_qpsk_q(src_adc_ddata[31:16]),
.data_valid(adc_dvalid),
.data_output(adc_ddata_s)
);
// output logic for data ans status
always @(posedge clk) begin
dst_adc_dsync <= src_adc_dsync;
dst_adc_dwr <= src_adc_dwr;
case(mode)
4'h0 : begin
dst_adc_ddata <= src_adc_ddata;
src_adc_dovf <= dst_adc_dovf;
end
4'h1 : begin
dst_adc_ddata <= 32'h0;
src_adc_dovf <= 1'b0;
end
4'h2 : begin
dst_adc_ddata <= {30'h0, adc_ddata_s};
src_adc_dovf <= dst_adc_dovf;
end
default : begin
dst_adc_ddata <= src_adc_ddata;
src_adc_dovf <= dst_adc_dovf;
end
endcase
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end
end
endmodule
|
#include <bits/stdc++.h> long long k, L, R, a[2222222], b[2222222], ans, sum[2222222]; int n, r; long long min(long long a, long long b) { return a < b ? a : b; } long long max(long long a, long long b) { return a > b ? a : b; } bool check(long long x) { long long ans = 0, now = 0; memset(b, 0, sizeof(b)); for (int i = 1; i <= n; i++) { now += b[i]; if (a[i] + now < x) ans += x - a[i] - now, b[i + 2 * r + 1] -= x - a[i] - now, now += x - a[i] - now; if (ans > k) return 0; } return 1; } int main() { scanf( %d%d%lld , &n, &r, &k); L = 2e18; for (int i = 1; i <= n; i++) scanf( %lld , &sum[i]), L = min(L, sum[i]), sum[i] += sum[i - 1]; for (int i = 1; i <= n; i++) a[i] = sum[min(i + r, n)] - sum[max(0, i - r - 1)]; R = 1e20; while (L <= R) { long long mid = L + R >> 1; if (check(mid)) L = mid + 1, ans = mid; else R = mid - 1; } printf( %lld n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAP_2_V
`define SKY130_FD_SC_HD__TAP_2_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__tap_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__tap_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAP_2_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fifo_address_gray_pipelined #(
parameter ADDRESS_WIDTH = 4
) (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [ADDRESS_WIDTH-1:0] m_axis_raddr,
output reg [ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
output reg [ADDRESS_WIDTH:0] s_axis_room
);
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
wire [ADDRESS_WIDTH:0] _s_axis_raddr;
reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
wire [ADDRESS_WIDTH:0] _m_axis_waddr;
assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1'b1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1'b1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
end
sync_gray #(
.DATA_WIDTH(ADDRESS_WIDTH + 1)
) i_waddr_sync (
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
);
sync_gray #(
.DATA_WIDTH(ADDRESS_WIDTH + 1)
) i_raddr_sync (
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
s_axis_room <= MAX_ROOM;
end else begin
s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
_s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + MAX_ROOM;
end
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
m_axis_valid <= 1'b0;
m_axis_level <= 'h00;
end else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
end
end
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long long int ll; ll mod=1e9+7; int main() { int t; cin>>t; while(t--) { ll n,k; cin>>n>>k; ll ans=1; for(ll i=0;i<k;i++) { ans=(ans*n)%mod; } cout<<ans<<endl; } }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module video_scaler_mul_jbC_MulnS_0(clk, ce, a, b, p);
input clk;
input ce;
input[32 - 1 : 0] a;
input[16 - 1 : 0] b;
output[32 - 1 : 0] p;
reg signed [32 - 1 : 0] a_reg0;
reg signed [16 - 1 : 0] b_reg0;
wire signed [32 - 1 : 0] tmp_product;
reg signed [32 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module video_scaler_mul_jbC(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
video_scaler_mul_jbC_MulnS_0 video_scaler_mul_jbC_MulnS_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { if (x < 0) return -x; return x; } template <class T> T sqr(T a) { return a * a; } const double pi = acos(-1.0); const double eps = 1e-8; int ar[150010]; int flag[150010]; int i, n; int main() { while (1 == scanf( %d , &n)) { memset(flag, 0, sizeof flag); for (i = 0; i < n; i++) scanf( %d , &ar[i]); sort(&ar[0], &ar[n]); for (i = 0; i < n; i++) { if (flag[ar[i] - 1] == 0 && ar[i] > 1) flag[ar[i] - 1]++; else if (flag[ar[i]] == 0) flag[ar[i]]++; else if (flag[ar[i] + 1] == 0) flag[ar[i] + 1]++; } int cnt = 0; for (i = 1; i <= 150001; i++) if (flag[i]) cnt++; printf( %d n , cnt); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 10; long long arr[MAX], arr2[MAX]; int n, m; bool check(long long mid) { int prv = 0; for (int i = 0; i < n; ++i) { while (prv < m && arr2[prv] + mid < arr[i]) ++prv; if (prv == m || arr2[prv] - mid > arr[i]) return 0; } return 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 0; i < n; ++i) cin >> arr[i]; for (int i = 0; i < m; ++i) cin >> arr2[i]; sort(arr, arr + n); sort(arr2, arr2 + m); long long l = 0, r = 2e9; long long ans = r; while (l <= r) { long long mid = (l + r) >> 1; if (check(mid)) ans = mid, r = mid - 1; else l = mid + 1; } return cout << ans << n , 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int MAXN = 1e5 + 5; ll x; string s; int ans[MAXN]; void init() { ; ; } void solve(int casei) { ll n = s.length(); s = # + s; for (int i = 1; i <= n; ++i) { ans[i] = -1; } for (int i = 1; i <= n; ++i) { if (s[i] == 0 ) { if (i + x <= n) ans[i + x] = 0; if (i - x >= 1) ans[i - x] = 0; } } for (int i = 1; i <= n; ++i) { if (s[i] == 1 ) { bool flg = false; if (i + x <= n && ans[i + x] != 0) ans[i + x] = 1, flg = true; if (i - x >= 1 && ans[i - x] != 0) ans[i - x] = 1, flg = true; if (flg == false) { cout << -1 n ; return; } } } for (int i = 1; i <= n; ++i) { if (ans[i] == -1) ans[i] = 1; } for (int i = 1; i <= n; ++i) cout << ans[i]; cout << endl; } int main() { int Case = 1; ios::sync_with_stdio(false); cin.tie(0); cin >> Case; for (int casei = 1; casei <= Case; ++casei) { cin >> s >> x; init(); solve(casei); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int kk[(100010)]; map<int, int> possible; int main() { int t, m, k, tj, rj, pre(0); bool first(false), already(false); scanf( %d , &t); for (int i = 0; i < t; ++i) { first = false; already = false; pre = 0; possible.clear(); scanf( %d%d , &m, &k); for (int j = 1; j <= k; ++j) { scanf( %d , &kk[j]); } for (int j = 0; j < m - 1; ++j) { scanf( %d%d , &tj, &rj); if (rj == 1 && !first) { first = true; for (int l = 1; l <= k; ++l) { if (kk[l] == 0) { already = true; break; } } if (!already) { for (int l = 1; l <= k; ++l) { if (kk[l] <= pre) { possible[l] = kk[l]; } } } } if (tj == 0) { pre += 1; } else { kk[tj] -= 1; if (first && !already) { if (possible[tj] != 0) { possible.erase(tj); } } } } if (!already && first) { int min = 100001; map<int, int>::iterator it = possible.begin(); while (it != possible.end()) { int count = (*it).second; if (count != 0 && count < min) { min = (*it).second; } it++; } pre -= min; } for (int j = 1; j <= k; ++j) { if (possible[j] != 0) { printf( %c , Y ); } else if (kk[j] <= pre) { printf( %c , Y ); } else { printf( %c , N ); } } printf( n ); } }
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int a, long long int b) { long long int result = 1; while (b > 0) { int lastbit = (b & 1); if (lastbit) { result = (result * a); } a = (a * a); b = b >> 1; } return result; } long long int power2(long long int a, long long int b, long long int p) { long long int result = 1; while (b > 0) { int lastbit = (b & 1); if (lastbit) { result = (result * a) % p; } a = (a * a) % p; b = b >> 1; } return result % p; } long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } vector<int> SieveOfEratosthenes(int n) { bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } vector<int> v; v.push_back(0); for (int p = 2; p <= n; p++) if (prime[p]) v.push_back(p); return v; } void InverseofNumber(long long int p) { long long int n[1000001]; n[0] = n[1] = 1; for (int i = 2; i <= 1000000; i++) n[i] = n[p % i] * (p - p / i) % p; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int xxx; cin >> xxx; for (int tt = 1; tt <= xxx; tt++) { long long int n; cin >> n; long long int t = ceil(sqrt(n)); long long int x = n / t; if (n % t == 0) { x--; } cout << t + x - 1; cout << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for lpflow_isobufsrc with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_16 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_16 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
|
#include <bits/stdc++.h> using namespace std; bool cmp(int a, int b) { return a > b; } int h[2005]; int main() { int i, n, a, b, ans = 0; scanf( %d %d %d , &n, &a, &b); for (i = 0; i < n; ++i) scanf( %d , &h[i]); sort(h, h + n, cmp); if (h[a - 1] > h[a]) ans = h[a - 1] - h[a]; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main(int argc, const char* argv[]) { int x1, x2, y1, y2, dx, dy, px, py; cin >> x1 >> y1 >> x2 >> y2 >> px >> py; dx = abs(x2 - x1); dy = abs(y2 - y1); if (dx % px != 0 || dy % py != 0) { cout << NO ; exit(0); } int a = dx / px; int b = dy / py; if (a % 2 == b % 2) { cout << YES ; } else { cout << NO ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_BLACKBOX_V
`define SKY130_FD_SC_MS__O2111A_BLACKBOX_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; vector<long long> fact(10005); long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long power(long long x, long long y) { long long temp; if (y == 0) return 1; temp = power(x, y / 2); if (y % 2 == 0) return temp * temp; else return x * temp * temp; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long modInv(long long n, long long p) { return power(n, p - 2, p); } long long ncr(long long n, long long r) { return (n >= r ? (fact[n] * modInv(fact[r], mod)) % mod * modInv(fact[n - r], mod) % mod : 0); } long long add(long long a, long long b) { long long z = a + b; if (z >= mod) z -= mod; return z; } long long mul(long long a, long long b) { return (a * b) % mod; } long long sub(long long a, long long b) { return (a - b + mod) % mod; } int main() { long long t = 1, n, i, j, m, cnt, f, ff; cin >> t; while (t--) { cin >> n >> mod; long long z = log2(n) - 1; long long ans = (n - (1 << (z + 1)) + 2) % mod; for (i = 0; i <= z; i++) { ans = mul(ans, (1 << i) + 1); } if (ans == 0) cout << mod - 1 << n ; else cout << ans - 1 << n ; } }
|
//
// Copyright (c) 2014 Jan Adelsbach <>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module nova_io_pio_dummy(pclk, bs_rst, bs_stb, bs_we, bs_adr, bs_din, bs_dout);
input pclk;
input bs_rst;
input bs_stb;
input bs_we;
input [0:7] bs_adr;
input [0:15] bs_din;
output reg [0:15] bs_dout;
parameter device_addr = 6'o00;
reg r_DONE;
reg r_BUSY;
always @(posedge pclk) begin
if(bs_rst) begin
bs_dout <= 16'hzzzz;
r_DONE <= 1'b1;
r_BUSY <= 1'b0;
end
else begin
if(bs_stb & bs_adr[0:5] == device_addr) begin
if(bs_we) begin
case(bs_adr[6:7])
2'b00:
begin
case(bs_din[14:15])
2'b01:
begin
r_DONE <= 1'b0;
r_BUSY <= 1'b1;
end
2'b10:
begin
r_DONE <= 1'b0;
r_BUSY <= 1'b0;
end
2'b11:
begin
// Pulse
end
endcase // case (bs_din[14:15])
end // case: 2'b00
2'b01:
$display("DOA");
2'b10:
$display("DOB");
2'b11:
$display("DOC");
endcase // case (bs_adr[6:7])
end // if (bs_we)
else begin
case(bs_adr[6:7])
2'b00:
bs_dout <= {r_BUSY, r_DONE, 14'h0000};
2'b01:
$display("%m DIA");
2'b10:
$display("%m DIB");
2'b11:
$display("%m DIC");
endcase // case (bs_adr[6:7])
end // else: !if(bs_we)
end // if (bs_stb & bs_adr[0:5] == device_addr)
else
bs_dout <= 16'hzzzz;
end
end
endmodule // nova_io_pio_dummy
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:56:44 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
// Design : design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[63:0],m_axi_awprot[5:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_araddr[63:0],m_axi_arprot[5:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rvalid[1:0],m_axi_rready[1:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [63:0]m_axi_awaddr;
output [5:0]m_axi_awprot;
output [1:0]m_axi_awvalid;
input [1:0]m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output [1:0]m_axi_wvalid;
input [1:0]m_axi_wready;
input [3:0]m_axi_bresp;
input [1:0]m_axi_bvalid;
output [1:0]m_axi_bready;
output [63:0]m_axi_araddr;
output [5:0]m_axi_arprot;
output [1:0]m_axi_arvalid;
input [1:0]m_axi_arready;
input [63:0]m_axi_rdata;
input [3:0]m_axi_rresp;
input [1:0]m_axi_rvalid;
output [1:0]m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int tt; cin >> tt; while (tt--) { int n; cin >> n; vector<int> a(n + 1); for (int i = 1; i <= n; i++) { cin >> a[i]; } int lo = 1, hi = n; while (a[lo] == lo && lo <= n) lo++; while (a[hi] == hi && hi >= 0) hi--; if (lo == n + 1 || hi == -1) { cout << 0 << n ; continue; } int ans = 1; for (int i = lo; i <= hi; i++) { if (a[i] == i) { ans++; break; } } cout << ans << n ; } return 0; }
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram (
address,
clock,
data,
wren,
q);
input [15:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "ROM.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SUPT",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 16,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "SUPT"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "ROM.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "ROM.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SUPT"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long n, k, a, b; long long mini = (long long)1e15; long long maxi = 0; long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } void calc(long long l) { if (l <= 0 || l > n * k) return; long long tmp = n * k / gcd(n * k, l); mini = min(tmp, mini); maxi = max(tmp, maxi); } int main() { cin >> n >> k >> a >> b; for (int i = -2; i <= n; ++i) { calc(k * i + b - a); calc(k * i - b - a); calc(k * i + b + a); calc(k * i - b + a); } cout << mini << << maxi << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 4e4; int main() { ios::sync_with_stdio(false); int n; while (cin >> n) { int a[12]; for (int i = 0; i < n; ++i) cin >> a[i]; sort(a, a + n); long long p = clock(); while (clock() - p < 1400) ; cout << a[0]; for (int i = 1; i < n; ++i) cout << << a[i]; cout << endl; } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: LOG_Table.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module LOG_Table (
address,
clock,
q);
input [12:0] address;
input clock;
output [7:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "log"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "LOG_Table.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "LOG_Table.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=log"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL address[12..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; vector<int> a; for (int i = 1; i <= n; i++) if (n % i == 0) a.push_back(i); for (int i = 1; i < a.size(); i++) { for (int j = 0; j < a[i] / 2; j++) swap(s[j], s[a[i] - j - 1]); } cout << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int N; vector<int> adj[200001]; vector<int> L[200001]; vector<int> R[200001]; int dp[200001]; int ans[200001]; inline void addmod(int& x, int v) { x += v; if (x >= MOD) x -= MOD; } void dfs(int u, int p) { for (auto& v : adj[u]) if (v != p) dfs(v, u); dp[u] = 1; L[u].resize(adj[u].size()); R[u].resize(adj[u].size()); int tmp = 1; for (size_t i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == p) { if (i == 0) L[u][i] = 1; else L[u][i] = L[u][i - 1]; continue; } tmp = 1LL * tmp * (dp[v] + 1) % MOD; L[u][i] = tmp; } tmp = 1; for (int i = adj[u].size() - 1; i >= 0; i--) { int v = adj[u][i]; if (v == p) { if (i == (int)adj[u].size() - 1) R[u][i] = 1; else R[u][i] = R[u][i + 1]; continue; } tmp = 1LL * tmp * (dp[v] + 1) % MOD; R[u][i] = tmp; } dp[u] = R[u][0]; } void dfs2(int u, int p, int x) { ans[u] = dp[u]; for (size_t i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == p) continue; int tmpu = dp[u]; int tmpv = dp[v]; dp[u] = 1LL * (i ? L[u][i - 1] : 1) * (i + 1 < adj[u].size() ? R[u][i + 1] : 1) % MOD * x % MOD; dp[v] = 1LL * dp[v] * (dp[u] + 1) % MOD; dfs2(v, u, dp[u] + 1); dp[u] = tmpu; dp[v] = tmpv; } } int main() { scanf( %d , &N); int a; for (int i = 2; i <= N; i++) { scanf( %d , &a); adj[a].push_back(i); adj[i].push_back(a); } dfs(1, -1); dfs2(1, -1, 1); for (int i = 1; i <= N; i++) printf( %d%c , ans[i], n [i == N]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_4_V
`define SKY130_FD_SC_HD__EBUFN_4_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ebufn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ebufn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__CONB_FUNCTIONAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_hdll__udp_pwrgood_pp_p.v"
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_hdll__udp_pwrgood_pp_g.v"
`celldefine
module sky130_fd_sc_hdll__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hdll__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hdll__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_FUNCTIONAL_PP_V
|
(************************************************************************)
(* Copyright (c) 2010, Martijn Vermaat <> *)
(* *)
(* Licensed under the MIT license, see the LICENSE file or *)
(* http://en.wikipedia.org/wiki/Mit_license *)
(************************************************************************)
(** This library defines substition of terms for variables in terms. *)
Require Export List.
Require Export FiniteTerm.
Require Export Term.
Require Import TermEquality.
Require Import Equality.
Set Implicit Arguments.
Section Substitution.
Variable F : signature.
Variable X : variables.
Notation term := (term F X).
Notation fterm := (finite_term F X).
(** A substitution is a function from variables to terms. *)
Definition substitution := X -> term.
(** Equality of substitutions on a list of variables. *)
Fixpoint substitution_eq (vars : list X) (sigma sigma' : substitution) :=
match vars with
| nil => True
| x :: xs => (substitution_eq xs sigma sigma') /\ (sigma x = sigma' x)
end.
(** Equality of substitutions on a list of variables is invariant under
list inclusion.
We have not yet proven this lemma. This taints the lemma [step_eq__target]
in [Rewriting]. *)
Lemma substitution_eq_incl :
forall sigma theta l l',
incl l' l ->
substitution_eq l sigma theta ->
substitution_eq l' sigma theta.
Proof.
intros sigma theta l l' H1 H2.
revert l' H1.
induction l as [| x l IH]; intros l' H1; simpl.
destruct l' as [| y l'].
exact I.
elim (H1 y).
left; reflexivity.
induction l' as [| y l' IH']; simpl.
exact I.
split.
apply IH'.
intros z H.
apply H1.
right.
assumption.
destruct (H1 y).
left; reflexivity.
rewrite H in H2.
apply H2.
simpl in H2.
(** This should not be too hard. (Problem is whether [x] is in [l']. *)
Admitted.
Lemma substitution_eq_app_left :
forall sigma theta l l',
substitution_eq (l ++ l') sigma theta ->
substitution_eq l sigma theta.
Proof.
intros sigma theta l l' H.
induction l as [| x l IH]; simpl.
exact I.
split.
apply IH.
apply H.
apply H.
Qed.
Lemma substitution_eq_app_right :
forall sigma theta l l',
substitution_eq (l ++ l') sigma theta ->
substitution_eq l' sigma theta.
Proof.
intros sigma theta l l' H.
induction l as [| x l IH]; simpl.
assumption.
apply IH.
apply H.
Qed.
Implicit Arguments substitution_eq_app_left [l l'].
Implicit Arguments substitution_eq_app_right [l l'].
(** We show [substitution_eq] is an equivalence. *)
Lemma substitution_eq_refl :
forall vars sigma, substitution_eq vars sigma sigma.
Proof.
induction vars; [simpl | split]; trivial.
Qed.
Lemma substitution_eq_symm :
forall vars sigma theta,
substitution_eq vars sigma theta ->
substitution_eq vars theta sigma.
Proof.
intros vars sigma theta H.
induction vars as [| x vars IH]; simpl.
exact I.
split.
apply IH.
apply H.
symmetry.
apply H.
Qed.
Lemma substitution_eq_trans :
forall vars sigma theta upsilon,
substitution_eq vars sigma theta ->
substitution_eq vars theta upsilon ->
substitution_eq vars sigma upsilon.
Proof.
intros vars sigma theta upsilon H1 H2.
induction vars as [| x vars IH]; simpl.
exact I.
split.
apply IH.
apply H1.
apply H2.
apply eq_trans with (theta x).
apply H1.
apply H2.
Qed.
(** The identity substitution. *)
Definition empty_substitution (x : X) : term := Var x.
(** We define two substitution functions. The first, [substitute], defines
substitution on finite terms. The second, [substitute'], defines
substitution on infinite terms.
In principle, [substitute'] works fine and is a generalisation of
[substitute]. However, it yields a (potentially) infinite term (of type
[term] instead of [finite_term]) and this makes it somewhat painful to
work with (corecursive definitions have to be manually unfolded in Coq).
Since we almost always apply substitutions on finite terms, we define
this seperately and provide the more general [substitute'] for
completeness. *)
(** Apply a substitution to a finite term. *)
Fixpoint substitute (sigma : substitution) (t : fterm) {struct t} : term :=
match t with
| FVar x => sigma x
| FFun f args => Fun f (vmap (substitute sigma) args)
end.
(** Applying the empty substitution to a finite term gives the trivial
infinite term image. The only reason we cannot prove coq-equality here
is equality on vectors. *)
Lemma empty_substitution_is_id :
forall (t : fterm), substitute empty_substitution t [~] t.
Proof.
induction t.
apply term_bis_refl.
constructor.
assumption.
Qed.
(** Applying equal substitutions yields equal terms.
We have not yet proven this lemma. This taints the lemmas
[step_eq_source] and [step_eq_target] in [Rewriting]. *)
Lemma substitution_eq_substitute :
forall sigma theta t,
substitution_eq (vars t) sigma theta ->
substitute sigma t [~] substitute theta t.
Proof.
intros sigma theta t H.
induction t as [x | f args IH]; simpl.
rewrite (proj2 H).
apply term_bis_refl.
constructor.
intro i.
apply IH; clear IH.
simpl in H.
unfold vmap in H.
induction (arity f) as [| n IH]; clear f.
inversion i.
dependent destruction i.
simpl in H.
unfold vhead in H.
unfold vtail in H.
apply (substitution_eq_app_left sigma theta H).
specialize IH with (vtail args) i.
apply IH.
unfold vtail.
(** Here we are stuck, need some more lemmas on [vector], for example:
[[
Lemma a :
forall x n v,
In x (vfold nil app (fun i0 : Fin n => vars (v (Next i0)))) ->
In x (vfold nil app (fun i : Fin (S n) => vars (v i))).
]]
*)
Admitted.
(** Apply a substitution to an infinite term. Note that this definition is
not in guarded form if we were to use the inductive vector type from the
standard library. It is in guarded form here, because we use [vector]
from the [Vector] library, where [vmap] is just an abstraction (which
ensures the corecursive call to [substitute'] to be guarded). *)
CoFixpoint substitute' (sigma : substitution) (t : term) : term :=
match t with
| Var x => sigma x
| Fun f args => Fun f (vmap (substitute' sigma) args)
end.
(** Applying the empty substitution to a term gives the same term. *)
Lemma empty_substitution_is_id' :
forall (t : term), substitute' empty_substitution t [~] t.
Proof.
cofix IH.
destruct t.
rewrite (peek_eq (substitute' empty_substitution (Var v))).
apply term_bis_refl.
rewrite (peek_eq (substitute' empty_substitution (Fun f v))).
simpl.
constructor.
intro i.
unfold vmap.
apply IH.
Qed.
(** We prove that both substitution functions do the same thing (on finite
terms). We can almost prove this for coq-equality, but we cannot equate
[vmap finite_term_as_term v] and [v]. *)
Lemma substitutions_related :
forall (s : substitution) (t : fterm), substitute s t [~] substitute' s t.
Proof.
induction t.
simpl.
rewrite (peek_eq (substitute' s (Var v))).
simpl.
destruct (s v); apply term_bis_refl.
simpl.
rewrite (peek_eq (substitute' s (Fun f (vmap (@finite_term_as_term F X) v)))).
simpl.
constructor.
intro i.
unfold vmap.
apply H.
Qed.
End Substitution.
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Response Down-Sizer
// Collect MI-side responses and set the SI-side response to the most critical
// level (in descending order):
// DECERR, SLVERROR and OKAY.
// EXOKAY cannot occur for split transactions.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// wr_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Don�t propagate.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire [4-1:0] cmd_repeat,
output wire cmd_ready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Repeat handling related.
reg [4-1:0] repeat_cnt_pre;
reg [4-1:0] repeat_cnt;
wire [4-1:0] next_repeat_cnt;
reg first_mi_word;
wire last_word;
// Ongoing split transaction.
wire load_bresp;
wire need_to_update_bresp;
reg [2-1:0] S_AXI_BRESP_ACC;
// Internal signals for MI-side.
wire M_AXI_BREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID_I;
reg [2-1:0] S_AXI_BRESP_I;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER_I;
wire S_AXI_BVALID_I;
wire S_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// The MI-side BRESP is popped when at once for split transactions, except
// for the last cycle that behaves like a "normal" transaction.
// A "normal" BRESP is popped once the SI-side is able to use it,
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from MI-side.
assign M_AXI_BREADY_I = M_AXI_BVALID & ~mi_stalling;
assign M_AXI_BREADY = M_AXI_BREADY_I;
// Indicate when there is a BRESP available @ SI-side.
assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
// Get MI-side data.
assign pop_mi_data = M_AXI_BVALID & M_AXI_BREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = (~S_AXI_BREADY_I & last_word);
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of BRESP.
//
// Forward the accumulated or MI-side BRESP value depending on state:
// * MI-side BRESP is forwarded untouched when it is a non split cycle.
// (MI-side BRESP value is also used when updating the accumulated for
// the last access during a split access).
// * The accumulated BRESP is for a split transaction.
//
// The accumulated BRESP register is updated for each MI-side response that
// is used.
//
/////////////////////////////////////////////////////////////////////////////
// Force load accumulated BRESPs to first value
assign load_bresp = (cmd_split & first_mi_word);
// Update if more critical.
assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
// Select accumultated or direct depending on setting.
always @ *
begin
if ( cmd_split ) begin
if ( load_bresp || need_to_update_bresp ) begin
S_AXI_BRESP_I = M_AXI_BRESP;
end else begin
S_AXI_BRESP_I = S_AXI_BRESP_ACC;
end
end else begin
S_AXI_BRESP_I = M_AXI_BRESP;
end
end
// Accumulate MI-side BRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_BRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Keep track of BRESP repeat counter.
//
// Last BRESP word is either:
// * The first and only word when not merging.
// * The last value when merging.
//
// The internal counter is taken from the external command interface during
// the first response when merging. The counter is updated each time a
// BRESP is popped from the MI-side interface.
//
/////////////////////////////////////////////////////////////////////////////
// Determine last BRESP cycle.
assign last_word = ( ( repeat_cnt == 4'b0 ) & ~first_mi_word ) |
~cmd_split;
// Select command reapeat or counted repeat value.
always @ *
begin
if ( first_mi_word ) begin
repeat_cnt_pre = cmd_repeat;
end else begin
repeat_cnt_pre = repeat_cnt;
end
end
// Calculate next repeat counter value.
assign next_repeat_cnt = repeat_cnt_pre - 1'b1;
// Keep track of the repeat count.
always @ (posedge ACLK) begin
if (ARESET) begin
repeat_cnt <= 4'b0;
first_mi_word <= 1'b1;
end else begin
if ( pop_mi_data ) begin
repeat_cnt <= next_repeat_cnt;
first_mi_word <= last_word;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// BID Handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_BID_I = M_AXI_BID;
/////////////////////////////////////////////////////////////////////////////
// USER Data bits
//
// The last USER bits are simply taken from the last BRESP that is merged.
// Ground USER bits when unused.
/////////////////////////////////////////////////////////////////////////////
// Select USER bits.
assign S_AXI_BUSER_I = {C_AXI_BUSER_WIDTH{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_BID = S_AXI_BID_I;
assign S_AXI_BRESP = S_AXI_BRESP_I;
assign S_AXI_BUSER = S_AXI_BUSER_I;
assign S_AXI_BVALID = S_AXI_BVALID_I;
assign S_AXI_BREADY_I = S_AXI_BREADY;
endmodule
|
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