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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_8_V
`define SKY130_FD_SC_MS__CLKBUF_8_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_8_V
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); void solve() { int n, k, d; cin >> n >> k >> d; vector<int> dist(n, -1); vector<vector<pair<int, int>>> za(n); vector<int> keep(n - 1), par(n); queue<int> q; for (int i = (0); i < (k); ++i) { int p; cin >> p; --p; dist[p] = 0; q.push(p); par[p] = -1; } for (int i = (0); i < (n - 1); ++i) { int x, y; cin >> x >> y; --x; --y; za[x].emplace_back(y, i); za[y].emplace_back(x, i); } int res = 0; while (!q.empty()) { int cur = q.front(); q.pop(); for (auto edge : za[cur]) { int u = edge.first; int edge_no = edge.second; if (dist[u] == -1) { ++res; dist[u] = dist[cur] + 1; keep[edge_no] = 1; q.push(u); } } } vector<int> shut; for (int i = (0); i < (n - 1); ++i) { if (keep[i] == 0) { shut.push_back(i + 1); } } cout << ((int)((shut).size())) << endl; for (auto s : shut) { cout << s << ; } cout << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; t = 1; while (t--) { solve(); } }
|
// Modified 2010 by Matt Ettus to remove old verilog style and
// allow 16-bit operation
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
module spi_top16
(input wb_clk_i, input wb_rst_i,
input [4:0] wb_adr_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input [1:0] wb_sel_i,
input wb_we_i, input wb_stb_i, input wb_cyc_i,
output reg wb_ack_o, output wb_err_o, output reg wb_int_o,
// SPI signals
output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i);
// Internal signals
reg [15:0] divider; // Divider register
reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register
reg [15:0] ss; // Slave select register
reg [31:0] wb_dat; // wb data out
wire [31:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len
wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
// Address decoder
assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE);
assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL);
assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0);
assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1);
assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2);
assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3);
assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);
always @(wb_adr_i or rx or ctrl or divider or ss)
case (wb_adr_i[4:2])
`SPI_RX_0: wb_dat = rx[31:0];
`SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
`SPI_DIVIDE: wb_dat = {16'b0, divider};
`SPI_SS: wb_dat = {16'b0, ss};
default : wb_dat = 32'd0;
endcase // case (wb_adr_i[4:2])
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_dat_o <= 32'b0;
else
wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0];
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
assign wb_err_o = 1'b0;
// Interrupt
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_int_o <= 1'b0;
else if (ie && tip && last_bit && pos_edge)
wb_int_o <= 1'b1;
else if (wb_ack_o)
wb_int_o <= 1'b0;
// Divider register
always @(posedge wb_clk_i)
if (wb_rst_i)
divider <= 16'b0;
else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1])
divider <= wb_dat_i;
// Ctrl register
always @(posedge wb_clk_i)
if (wb_rst_i)
ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1])
begin
if (wb_sel_i[0])
ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
if (wb_sel_i[1])
ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
end
else if(tip && last_bit && pos_edge)
ctrl[`SPI_CTRL_GO] <= 1'b0;
assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
assign go = ctrl[`SPI_CTRL_GO];
assign char_len = ctrl[`SPI_CTRL_CHAR_LEN];
assign lsb = ctrl[`SPI_CTRL_LSB];
assign ie = ctrl[`SPI_CTRL_IE];
assign ass = ctrl[`SPI_CTRL_ASS];
// Slave select register
always @(posedge wb_clk_i)
if (wb_rst_i)
ss <= 16'b0;
else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1])
begin
if (wb_sel_i[0])
ss[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
ss[15:8] <= wb_dat_i[15:8];
end
assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}}));
spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
.divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]),
(~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) };
spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
.latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb),
.go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in({wb_dat_i,wb_dat_i}), .p_out(rx),
.s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
endmodule // spi_top16
|
`include "reg_define.v"
`include "version.v"
module AXI2SREG
(
clk,
rst,
en,
wen,
din,
dout,
addr,
ien,
oen,
async,
tddmode,
ibase,
isize,
obase,
osize,
frame_len,
frame_adj,
tstart,
tend,
rstart,
rend,
iacnt,
ibcnt,
oacnt,
obcnt,
test,
axiwresp,
axirresp,
axistatus,
axiraddr,
axiwaddr,
adj_pending
);
parameter BASE = `AXI2SREG_BASE;
input clk,rst,en,wen;
input [31:0]din;
input [17:0]addr;
output reg ien,oen,async,tddmode;
output reg [31:0]dout;
output reg [31:0]ibase;
output reg [31:0]obase;
output reg [23:6]isize;
output reg [23:6]osize;
output reg [23:0]frame_len;
output reg [23:0]tstart;
output reg [23:0]tend;
output reg [23:0]rstart;
output reg [23:0]rend;
output reg [23:0]frame_adj;
output reg test;
input [23:6]iacnt;
input [23:6]oacnt;
input [31:0]ibcnt;
input [31:0]obcnt;
input [31:0]axiwresp;
input [31:0]axirresp;
input [31:0]axistatus;
input [31:0]axiraddr;
input [31:0]axiwaddr;
input adj_pending;
wire [159:0]version_git;
reg [31:0]ibcnt_reg;
reg [31:0]obcnt_reg;
always @(posedge clk or posedge rst)
begin
if(rst) begin
ien <= 1'b0;
oen <= 1'b0;
tddmode <= 1'b0;
ibase <= 32'hfffc0000;
isize <= 18'h400;
obase <= 32'hfffd0000;
osize <= 18'h400;
frame_len <= 24'd1920;
frame_len <= 24'd1920;
tstart <= 24'h0;
tend <= 24'd1919;
rstart <= 24'h0;
rend <= 24'd1919;
test <= 1'b0;
end
else if(clk) begin
if( en==1'b1 ) begin
// write
if( wen==1'b1 ) begin
case( addr )
// define AXI2S_EN 18'h00
`AXI2S_EN: begin
ien <= din[0];
oen <= din[1];
async <= din[2];
tddmode <= din[3];
end
// define AXI2S_TEST 18'h04
`AXI2S_TEST: begin
test <= din[0];
end
// define AXI2S_IBASE 18'h10
`AXI2S_IBASE: begin
ibase <= din;
end
// define AXI2S_ISIZE 18'h14
`AXI2S_ISIZE: begin
isize <= din[23:6];
end
// define AXI2S_OBASE 18'h18
`AXI2S_OBASE: begin
obase <= din;
end
// define AXI2S_OSIZE 18'h1C
`AXI2S_OSIZE: begin
osize <= din[23:6];
end
// define FRAME_LEN 18'h20
`FRAME_LEN: begin
frame_len <= din[23:0];
end
// define FRAME_ADJ 18'h24
`FRAME_ADJ: begin
frame_adj <= din[23:0];
end
// define TSTART 18'h30
`TSTART: begin
tstart <= din[23:0];
end
// define TEND 18'h34
`TEND: begin
tend <= din[23:0];
end
// define RSTART 18'h38
`RSTART: begin
rstart <= din[23:0];
end
// define REND 18'h3C
`REND: begin
rend <= din[23:0];
end
endcase
end
end
end
end
always @(posedge clk) begin
if(addr[17:8]==BASE[17:8] && en==1'b1 ) begin
case( addr )
// define AXI2S_IACNT 18'h10
`AXI2S_IACNT: begin
ibcnt_reg <= ibcnt;
end
// define AXI2S_OACNT 18'h18
`AXI2S_OACNT: begin
obcnt_reg <= obcnt;
end
endcase
end
end
always @(*) begin
if(addr[17:8]==BASE[17:8] && en==1'b1 ) begin
case( addr )
// define AXI2S_STATE 18'h00
`AXI2S_STATE: begin
dout[0] <= ien;
dout[1] <= oen;
dout[2] <= tddmode;
dout[3] <= adj_pending;
dout[31:4] <= 28'd0;
end
// define AXI2S_IACNT 18'h10
`AXI2S_IACNT: begin
dout[23:6] <= iacnt;
dout[31:24] <= 8'd0;
dout[5:0] <= 6'd0;
end
// define AXI2S_IBCNT 18'h14
`AXI2S_IBCNT: begin
dout <= ibcnt_reg;
end
// define AXI2S_OACNT 18'h18
`AXI2S_OACNT: begin
dout[23:6] <= oacnt;
dout[31:24] <= 8'd0;
dout[5:0] <= 6'd0;
end
// define AXI2S_OBCNT 18'h1c
`AXI2S_OBCNT: begin
dout <= obcnt_reg;
end
`ifdef DEBUG
// define AXI_RRESP 18'h20
`AXI_RRESP: begin
dout <= axirresp;
end
// define AXI_WRESP 18'h24
`AXI_WRESP: begin
dout <= axiwresp;
end
// define AXI_STATUS 18'h28
`AXI_STATUS: begin
dout <= axistatus;
end
// define AXI_RADDR 18'h30
`AXI_RADDR: begin
dout <= axiraddr;
end
// define AXI_WADDR 18'h34
`AXI_WADDR: begin
dout <= axiwaddr;
end
`endif
// define VER_MAJOR 18'h40
`VER_MAJOR: begin
dout <= `VERSION_MAJOR;
end
// define VER_MINOR0 18'h50
`VER_MINOR0: begin
dout <= version_git[31:0];
end
// define VER_MINOR1 18'h54
`VER_MINOR1: begin
dout <= version_git[63:32];
end
// define VER_MINOR2 18'h58
`VER_MINOR2: begin
dout <= version_git[95:64];
end
// define VER_MINOR3 18'h5c
`VER_MINOR3: begin
dout <= version_git[127:96];
end
// define VER_MINOR4 18'h60
`VER_MINOR4: begin
dout <= version_git[159:128];
end
endcase
end
else dout <= 32'h0;
end
assign version_git = `VERSION;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_2_V
`define SKY130_FD_SC_HD__AND3B_2_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int i1, i2, a1, a2; cout << ? ; for (int i = 1; i <= k; ++i) cout << i << ; cout << n ; cout.flush(); cin >> i1 >> a1; cout << ? ; for (int i = 1; i <= k + 1; ++i) { if (i == i1) ++i; cout << i << ; } cout << n ; cout.flush(); cin >> i2 >> a2; if (a1 < a2) { swap(i1, i2); swap(a1, a2); } int count = 0, c1 = 0, c2; for (int ch = 1; ch <= k + 10; ++ch) { if (ch == i1 || ch == i2) ++ch; if (ch == i1 || ch == i2) ++ch; ++c1; if (c1 > k - 1) break; cout << ? ; c2 = 0; for (int i = 1; i <= k + 10; ++i) { ++c2; if (c2 > k) break; if (i == i2) ++i; if (i == ch) cout << i2 << ; else cout << i << ; } cout << n ; cout.flush(); int ich, ach; cin >> ich >> ach; if (ich == i1) ++count; } cout << ! << count + 1; cout.flush(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const long long Inf = 0x3f3f3f3f3f3f3f3f; int n, x, y, z, cnt, tot, head[maxn], vis[maxn]; long long res, r[maxn], l[maxn], l0[maxn], r0[maxn], sum[maxn], ans1, ans2 = Inf, f[maxn], cir[maxn]; struct Edge { int to, next, w; } e[maxn << 1]; void add(int u, int v, int w) { e[++cnt].to = v; e[cnt].w = w; e[cnt].next = head[u]; head[u] = cnt; } int fnd(int u, int fa = -1) { if (vis[u]) return u; vis[u] = -1; for (int i = head[u]; i; i = e[i].next) { int v = e[i].to; if (v != fa) { res = fnd(v, u); if (res) return cir[++tot] = u, sum[tot] = e[i].w, vis[u] = 1, res == u ? 0 : res; } } return 0; } void dfs(int u, int fa = -1) { for (int i = head[u]; i; i = e[i].next) { int v = e[i].to; if (vis[v] != 1 && v != fa) { dfs(v, u); ans1 = max(ans1, f[u] + f[v] + e[i].w); f[u] = max(f[u], f[v] + e[i].w); } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d%d , &x, &y, &z); add(x, y, z); add(y, x, z); } fnd(1); sum[0] = 0; for (int i = 1; i <= tot; i++) { dfs(cir[i]); sum[i] += sum[i - 1]; } res = l[0] = l0[0] = -Inf; for (int i = 1; i <= tot; i++) { l0[i] = max(l0[i - 1], f[cir[i]] + sum[i] + res); l[i] = max(l[i - 1], f[cir[i]] + sum[i]); res = max(res, f[cir[i]] - sum[i]); } res = r[tot + 1], r0[tot + 1] = -Inf; for (int i = tot; i >= 1; i--) { r0[i] = max(r0[i + 1], f[cir[i]] - sum[i] + res); r[i] = max(r[i + 1], f[cir[i]] + sum[tot] - sum[i]); res = max(res, f[cir[i]] + sum[i]); } for (int i = 1; i <= tot; i++) { ans2 = min(ans2, max(l[i - 1] + r[i], max(l0[i - 1], r0[i]))); } printf( %lld n , max(ans1, ans2)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false), cin.tie(0); int opx, t, c; cin >> t >> c; int dfx = 1; long long lorenzo = 0; while (c--) { cin >> opx; if (dfx != 1) lorenzo += t - dfx + 1; dfx = opx + 1; } cout << lorenzo; }
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#include <bits/stdc++.h> using namespace std; int x, s, t; int main(void) { cin >> t >> s >> x; int a = (x - t) / s; if (t == x) { cout << YES << endl; } else if (a <= 0) { cout << NO << endl; } else if (t + a * s == x || t + a * s + 1 == x) { cout << YES << endl; } else { cout << NO << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 100005; const double eps = 1e-9; const double pi = acos(-1); struct P { int x, y; } a[N]; int n, vi[N], t[N]; double l[N], r[N], q[N]; long long k; void change(int k, int v) { for (; k; k -= k & (-k)) t[k] += v; } int ask(int k) { int s = 0; for (; k < N; k += k & (-k)) s += t[k]; return s; } struct node { double p1, p2; int v; } op[N * 2]; bool cmp(node a, node b) { return a.p1 < b.p1; } long long count(double R) { int top = 0, op_top = 0; memset(t, 0, sizeof(t)); for (int i = (int)(1); i <= (int)(n); i++) { l[i] = r[i] = -1; double d = sqrt(a[i].x * a[i].x + a[i].y * a[i].y); if (d < R + eps) continue; double theta = atan2(a[i].y, a[i].x); double delta = acos(R / d); l[i] = theta - delta; r[i] = theta + delta; for (; l[i] < 0; l[i] += 2 * pi) ; for (; r[i] < 0; r[i] += 2 * pi) ; for (; l[i] >= 2 * pi; l[i] -= 2 * pi) ; for (; r[i] >= 2 * pi; r[i] -= 2 * pi) ; if (l[i] > r[i]) swap(l[i], r[i]); q[++top] = l[i]; op[++op_top] = (node){l[i], l[i], 1}; op[++op_top] = (node){r[i], l[i], -1}; } sort(q + 1, q + top + 1); sort(op + 1, op + op_top + 1, cmp); long long sum = 0; for (int i = (int)(1); i <= (int)(op_top); i++) { int p = lower_bound(q + 1, q + top + 1, op[i].p2) - q; change(p, op[i].v); if (op[i].v == -1) sum += ask(p); } return sum; } int main() { scanf( %d%lld , &n, &k); for (int i = (int)(1); i <= (int)(n); i++) scanf( %d%d , &a[i].x, &a[i].y); double l = 0, r = 15000; for (int T = (int)(1); T <= (int)(50); T++) { double mid = (l + r) / 2; if (1ll * n * (n - 1) / 2 - count(mid) < k) l = mid; else r = mid; } printf( %.10lf n , (l + r) / 2); }
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#include <bits/stdc++.h> using namespace std; void BFS(double, double, double &a); double pSquares(double, double); double n, m, k, r; struct queue_compare { bool operator()(const pair<double, double> &p1, const pair<double, double> &p2) const { return pSquares(p1.first, p1.second) < pSquares(p2.first, p2.second); } } typedef pqc; struct set_compare { bool operator()(const pair<double, double> &p1, const pair<double, double> &p2) const { if (p1.first != p2.first) { return p1.first < p2.first; } else { return p1.second < p2.second; } } } typedef sc; int main() { cin >> n >> m >> r >> k; double numer = 0; double denom = (n - r + 1) * (m - r + 1); BFS(floor((m + 1) / 2), floor((n + 1) / 2), numer); cout << setprecision(15) << (numer / denom) << endl; } double pSquares(double i, double j) { double x, y; y = abs(min(j - 1, r - 1) + 1 - (r - (min(n - j, r - 1)))) + 1; x = abs(min(i - 1, r - 1) + 1 - (r - (min(m - i, r - 1)))) + 1; return x * y; } void BFS(double i, double j, double &numerator) { priority_queue<pair<double, double>, vector<pair<double, double> >, pqc> pq; set<pair<double, double>, sc> s; pair<double, double> p(i, j); pq.push(p); s.insert(p); for (int i = 0; i < k; i++) { pair<double, double> tp = pq.top(); pq.pop(); numerator += pSquares(tp.first, tp.second); pair<double, double> left(tp.first, tp.second - 1); pair<double, double> right(tp.first, tp.second + 1); pair<double, double> above(tp.first - 1, tp.second); pair<double, double> bot(tp.first + 1, tp.second); if (tp.second - 1 >= 1 && s.find(left) == s.end()) { s.insert(left); pq.push(left); } if (tp.first - 1 >= 1 && s.find(above) == s.end()) { s.insert(above); pq.push(above); } if (tp.first + 1 <= m && s.find(bot) == s.end()) { s.insert(bot); pq.push(bot); } if (tp.second + 1 <= n && s.find(right) == s.end()) { s.insert(right); pq.push(right); } } }
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 11:35:36 10/17/2016
// Module Name: REG_tb
// Project Name: MIPS
// Description: Testing the registers module of the DECODE stage.
//
// Dependencies: REG.v
//
////////////////////////////////////////////////////////////////////////////////
module REG_tb;
// Inputs
reg clk;
reg regwrite;
reg [4:0] rs;
reg [4:0] rt;
reg [4:0] rd;
reg [31:0] writedata;
// Outputs
wire [31:0] A;
wire [31:0] B;
// Instantiate the REG module
REG gp_regs(.clk(clk), .regwrite(regwrite), .rs(rs), .rt(rt), .rd(rd),
.writedata(writedata), .A(A), .B(B));
initial begin
// Initialize Inputs
clk = 1;
regwrite = 0;
rs = 0;
rt = 0;
rd = 0;
writedata = 0;
// Wait 100 ns for global reset to finish
$display("Initializing and waiting for reset...");
#100;
// Write test data to the first nine locations
$display("Writing data...");
regwrite = 1;
writedata = 32'h002300AA;
#20;
rd = rd + 1;
writedata = 32'h10654321;
#20;
rd = rd + 1;
writedata = 32'h00100022;
#20;
rd = rd + 1;
writedata = 32'h8C123456;
#20;
rd = rd + 1;
writedata = 32'h8F123456;
#20;
rd = rd + 1;
writedata = 32'hAD654321;
#20;
rd = rd + 1;
writedata = 32'h13012345;
#20;
rd = rd + 1;
writedata = 32'hAC654321;
#20;
rd = rd + 1;
writedata = 32'h12012345;
// Read test data from the nine test locations.
// rs will read evens and rt will read odds until the last register,
// where both will read the ninth register together.
#20;
$display("Reading data...");
regwrite = 0;
rt = rt + 1;
#20
rs = rs + 2;
rt = rt + 2;
#20
rs = rs + 2;
rt = rt + 2;
#20
rs = rs + 2;
rt = rt + 2;
#20
rs = rs + 2;
rt = rt + 1;
#20 $finish;
end
initial begin
$monitor("rs = %b\trt = %b\tregwrite = %b\trd = %b\twritedata = %h\tA = %h\tB = %h",
rs, rt, regwrite, rd, writedata, A, B);
forever begin
#10 clk = ~clk;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main(void) { long long int n = 0ll, k = 0ll, p = 0ll, pn = 0ll, even = 0ll, odd = 0ll; while (cin >> n) { cin >> k >> p; if (k == 0) { for (long long int i = 0; i < p; i++) { cin >> pn; cout << . ; } cout << endl; } else { if (n % 2 == 0) { if (k >= (n >> 1)) { even = 2; k -= (n >> 1); odd = n + 1 - (k << 1); } else { odd = n + 1; even = n + 2 - (k << 1); } for (int i = 0; i < p; i++) { cin >> pn; if (pn % 2 == 0) { if (pn >= even) { cout << X ; } else { cout << . ; } } else { if (pn >= odd) { cout << X ; } else { cout << . ; } } } cout << endl; } else { n--; k--; if (k >= (n >> 1)) { even = 2; k -= (n >> 1); odd = n + 1 - (k << 1); } else { odd = n + 1; even = n + 2 - (k << 1); } for (int i = 0; i < p; i++) { cin >> pn; if (pn == n + 1) { cout << X ; } else if (pn % 2 == 0) { if (pn >= even) { cout << X ; } else { cout << . ; } } else { if (pn >= odd) { cout << X ; } else { cout << . ; } } } cout << endl; } } } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long>> bpow = {{1, 1}}; struct HashArr { const long long base = 137137, mod[2] = {(int)1e9 + 7, (int)1e9 + 9}; vector<pair<long long, long long>> h; void init(vector<int>& a) { int n = a.size(); h.resize(n + 1); bpow[0] = {1, 1}; for (int i = 0; i < n; i++) { h[i + 1].first = (h[i].first * base + a[i]) % mod[0]; h[i + 1].second = (h[i].second * base + a[i]) % mod[1]; } while ((int)bpow.size() < n + 1) { bpow.push_back({bpow.back().first * base % mod[0], bpow.back().second * base % mod[1]}); } } long long getHash(int l, int r) { assert(r >= l); long long a = (bpow[r - l].first * h[l].first - h[r].first + mod[0]) % mod[0]; long long b = (bpow[r - l].second * h[l].second - h[r].second + mod[1]) % mod[1]; return a << 32 | b; } }; const int nax = 1e5; const int B = 300; struct Block { bool bad; vector<int> ends, starts; HashArr endh, starth; void init(vector<int>& a, int l, int r) { ends.clear(), starts.clear(); bad = false; for (int i = l; i < r; i++) { if (a[i] < 0) { if (starts.empty()) { ends.push_back(-a[i]); } else { if (starts.back() != -a[i]) { bad = true; return; } else { starts.pop_back(); } } } else { assert(a[i] > 0); starts.push_back(a[i]); } } reverse(ends.begin(), ends.end()); endh.init(ends); starth.init(starts); } }; Block block[nax / B + 2]; struct Range { Block& block; int l, r; Range(Block& b) : block(b) { l = 0; r = b.starts.size(); } }; struct Joiner { bool bad; Joiner() { bad = false; } vector<Range> starts; void operator()(Block& b) { bad |= b.bad; if (bad) return; bad = true; int bl = 0, br = b.ends.size(); while (br > bl) { if (starts.empty()) return; Range& r = starts.back(); int aw = r.r - r.l; int w = min(aw, br - bl); if (r.block.starth.getHash(r.r - w, r.r) != b.endh.getHash(br - w, br)) return; br -= w; r.r -= w; if (r.r == r.l) starts.pop_back(); } if (b.starts.size()) starts.emplace_back(b); bad = false; } }; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, k; cin >> n >> k; vector<int> a(n); for (int& v : a) cin >> v; for (int i = 0; i < n; i += B) { block[i / B].init(a, i, min(i + B, n)); } int q; cin >> q; while (q--) { int type; cin >> type; if (type == 1) { int i, t; cin >> i >> t; i--; a[i] = t; int l = i / B * B; block[i / B].init(a, l, min(l + B, n)); } else if (type == 2) { int l, r; cin >> l >> r; l--; vector<Block> tmps; tmps.reserve(2); Joiner joiner; int i = l; while (i < r) { int ni = min(i / B * B + B, r); if (i % B == 0 && ni % B == 0) { joiner(block[i / B]); } else { tmps.push_back(Block()); tmps.back().init(a, i, ni); joiner(tmps.back()); } i = ni; } cout << (joiner.bad || joiner.starts.size() ? No : Yes ) << n ; } else assert(0); } }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_jesd_cntrl (
// gtx interface
rx_rst,
rx_clk,
rx_data,
rx_charisk,
rx_disperr,
rx_notintable,
// jesd interface
rx_sysref,
rx_sync,
// jesd controls
rx_sysref_enb,
rx_sync_enb,
// monitor signals
mon_trigger,
mon_data);
// gtx interface
input rx_rst;
input rx_clk;
input [31:0] rx_data;
input [ 3:0] rx_charisk;
input [ 3:0] rx_disperr;
input [ 3:0] rx_notintable;
// jesd interface
input rx_sysref;
input rx_sync;
// jesd controls
output rx_sysref_enb;
output rx_sync_enb;
// monitor signals
output [ 4:0] mon_trigger;
output [55:0] mon_data;
// receive state machine parameters
localparam RX_FSM_IDLE = 4'h0;
localparam RX_FSM_CGS = 4'h1;
localparam RX_FSM_SYSREF = 4'h2;
localparam RX_FSM_SYNC = 4'h3;
localparam RX_FSM_DATA = 4'h4;
// internal registers
reg rx_sysref_enb = 'd0;
reg rx_sync_enb = 'd0;
reg [ 3:0] rx_fsm = 'd0;
// internal signals
wire rx_ilas_f_s;
wire rx_ilas_q_s;
wire rx_ilas_a_s;
wire rx_ilas_r_s;
wire rx_cgs_k_s;
wire [ 3:0] rx_valid_k_s;
wire rx_valid_k_1_s;
// monitor interface
assign mon_data[55:55] = rx_ilas_f_s;
assign mon_data[54:54] = rx_ilas_q_s;
assign mon_data[53:53] = rx_ilas_a_s;
assign mon_data[52:52] = rx_ilas_r_s;
assign mon_data[51:51] = rx_cgs_k_s;
assign mon_data[50:50] = rx_valid_k_1_s;
assign mon_data[49:49] = rx_sysref_enb;
assign mon_data[48:48] = rx_sync_enb;
assign mon_data[47:44] = rx_fsm;
assign mon_data[43:40] = rx_charisk;
assign mon_data[39:36] = rx_disperr;
assign mon_data[35:32] = rx_notintable;
assign mon_data[31: 0] = rx_data;
assign mon_trigger = {rx_valid_k_1_s, rx_fsm};
// assert sysref and indicate data phase
always @(posedge rx_clk) begin
if (rx_rst == 1'b1) begin
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd0;
rx_fsm <= 'd0;
end else begin
case (rx_fsm)
RX_FSM_DATA: begin // data phase
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd1;
if (rx_sync == 1'b0) begin
rx_fsm <= RX_FSM_IDLE;
end else begin
rx_fsm <= RX_FSM_DATA;
end
end
RX_FSM_SYNC: begin // sync assertion
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd1;
if (rx_sync == 1'b1) begin
rx_fsm <= RX_FSM_DATA;
end else begin
rx_fsm <= RX_FSM_SYNC;
end
end
RX_FSM_CGS: begin // check for cgs
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd0;
if (rx_cgs_k_s == 1'b0) begin
rx_fsm <= RX_FSM_SYNC;
end else begin
rx_fsm <= RX_FSM_CGS;
end
end
RX_FSM_SYSREF: begin // assert sysref
rx_sysref_enb <= 'd1;
rx_sync_enb <= 'd0;
if (rx_sysref == 1'b1) begin
rx_fsm <= RX_FSM_CGS;
end else begin
rx_fsm <= RX_FSM_SYSREF;
end
end
RX_FSM_IDLE: begin // reset done
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd0;
rx_fsm <= RX_FSM_SYSREF;
end
default: begin
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd0;
rx_fsm <= RX_FSM_IDLE;
end
endcase
end
end
// ilas frame characters
assign rx_ilas_f_s =
(((rx_data[31:24] == 8'hfc) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'hfc) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'hfc) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'hfc) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_q_s =
(((rx_data[31:24] == 8'h9c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h9c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h9c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h9c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_a_s =
(((rx_data[31:24] == 8'h7c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h7c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h7c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h7c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_r_s =
(((rx_data[31:24] == 8'h1c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h1c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h1c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h1c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_cgs_k_s =
(((rx_data[31:24] == 8'hbc) && (rx_valid_k_s[ 3] == 1'b1)) &&
((rx_data[23:16] == 8'hbc) && (rx_valid_k_s[ 2] == 1'b1)) &&
((rx_data[15: 8] == 8'hbc) && (rx_valid_k_s[ 1] == 1'b1)) &&
((rx_data[ 7: 0] == 8'hbc) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
// validate all characters
assign rx_valid_k_s = rx_charisk & (~rx_disperr) & (~rx_notintable);
assign rx_valid_k_1_s = (rx_valid_k_s == 4'd0) ? 1'b0 : 1'b1;
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int y, b, r; int l, m, n; int ans; cin >> y >> b >> r; l = y; m = b; n = r; int mins = min(min(y, b), r); if (mins == r) { ans = r + (r - 1) + (r - 2); } else if (mins == b) { y = b - 1; r = b + 1; ans = y + b + r; } else if (mins == y) { b = y + 1; r = y + 2; if (r > n) { y--; ans = y + (y + 1) + (y + 2); } else { ans = y + b + r; } } cout << ans << endl; return 0; }
|
// ====================================================================
// MAH PONK
//
// Copyright (C) 2007, Viacheslav Slavinsky
// This design and core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
// An open table tennis game for VGA displays.
//
// Author: Viacheslav Slavinsky, http://sensi.org/~svo
//
// Design File: scores2.v
// Score keeper and character generator.
//
// Pins description:
// clk input master clock
// neglineclk input line clock (hsync)
// realx input x-coordinate
// realy input y-coordinate
// score_addA input left score increment
// score_addB input right score increment
// score_reset input score reset
// scoreA output left score bcd value
// scoreB output right score bcd value
// score_scan output score scan
//
// Contains additional modules:
// module bcdcounterx(reset, c, cout, q);
// module unicounter(c, r, en, q1, q2, q3);
// module mux2x4(sel, d0, d1, d2, d3, q); -- can be used instead of scorecopymux macro
// module textramx(clk, d, a, q);
// module charrom(clk, char, line, q);
// module digit(scanline, pixels);
// module counter_mod4(c, r, q, cout);
// module counter_mod8(c, r, q, cout);
module scores(clk, neglineclk, realx, realy, score_addA, score_addB, score_reset, scoreA, scoreB, score_scan);
input clk;
input neglineclk;
input [9:0] realx, realy;
input score_addA, score_addB, score_reset;
output [7:0]scoreA, scoreB;
output score_scan;
// score counters
wire scout1, scout2, scout3, scout4;
wire [3:0] score0;
wire [3:0] score1;
wire [3:0] score2;
wire [3:0] score3;
bcdcounterx bcdcounter1(score_reset, score_addA, scout1, score1);
bcdcounterx bcdcounter2(score_reset, scout1, scout2, score0);
bcdcounterx bcdcounter3(score_reset, score_addB, scout3, score3);
bcdcounterx bcdcounter4(score_reset, scout3, scout4, score2);
reg [7:0] scoreA, scoreB;
always @(score0 or score1 or score2 or score3) begin
scoreA <= {score0,score1};
scoreB <= {score2,score3};
end
parameter XSTART = 640/2-3*8*4;
parameter YSTART = 6*8;
reg rscxr;
wire scxr = rscxr; //= realx == XSTART; // reset of x counters
always @(negedge clk) begin
if (realx == XSTART) rscxr <= 1;
else rscxr <= 0;
end
wire newline = !neglineclk;//realx == 0;
wire scyr = realy == YSTART; // reset of y counters
reg [7:0] xwide;
always @(posedge clk) begin
if (scxr)
xwide <= 6*8*4;
else
if (xwide > 0) xwide <= xwide - 1;
end
wire display_ax = xwide != 0;
wire display_ay = realy >= YSTART && realy < YSTART+5*8;
wire displayactive = display_ax & display_ay & skippy;
// leap skippy
reg skippy;
always @(posedge clk) begin
if (realx == XSTART + 2*8*4) begin
skippy <= 0;
end else if (realx == XSTART + 4*8*4) begin
skippy <= 1;
end
end
wire [3:0] dummy;
wire [1:0] bitnumber; // this selects the bit from charrom out
wire [1:0] textadr;
unicounter unicounter(clk, scxr, skippy & display_ax, dummy[2:0], bitnumber, textadr);
wire [2:0] y;
unicounter ycounter(newline, scyr, display_ay, dummy[2:0], y[1:0], {dummy[0],y[2]});
// mux score counters
wire [3:0] textd; // this goes into text ram
//mux2x4 muxscorbles(textadr, score[0], score[1], score[2], score[3], textd);
scorecopymux scorecopymux(score0, score1, score2, score3, textadr, textd);
// the character rom and pixels
wire [3:0] pixels;
charrom charrom(clk, charcode, y, pixels);
// where the actual digits are!
wire [3:0] charcode;
textramx displaymem(clk, textd, textadr, charcode);
reg sscan;
always @(posedge clk) begin
sscan <= displayactive & pixels[bitnumber];
end
assign score_scan = sscan;
//assign score_scan = displayactive & pixels[bitnumber];
endmodule
module bcdcounterx(reset, c, cout, q);
input reset, c;
output reg cout;
output reg [3:0]q;
always @(posedge reset or posedge c) begin
if (reset) {cout, q} <= 0;
else begin
if (q == 9)
{cout, q} <= {5'b10000};
else
{cout, q} <= q + 1'b1;
end
end
endmodule
module unicounter(c, r, en, q1, q2, q3);
input c, r, en;
output [2:0] q1;
output [1:0] q2;
output [1:0] q3;
reg [6:0]q;
assign q1 = q[2:0];
assign q2 = q[4:3];
assign q3 = q[6:5];
always @(posedge c)
if (r)
q <= 0;
else if (en)
q <= q + 1'b1;
endmodule
module mux2x4(sel, d0, d1, d2, d3, q);
input [1:0] sel;
input [3:0] d0, d1, d2, d3;
output [3:0] q;
assign q = sel == 2'b00 ? d0 :
2'b01 ? d1 :
2'b10 ? d2 : d3;
endmodule
module textramx(clk, d, a, q);
input clk;
input [3:0] d;
input [1:0] a;
output [3:0] q;
reg [3:0] ram[3:0]; // 4 locations 4-bit wide each
reg [3:0] q;
//assign q = ram[a];
// always @(posedge clk) begin
// q <= ram[a];
// ram[a] <= d;
// end
always @(d or a) begin
q <= ram[a];
ram[a] <= d;
end
endmodule
module charrom(clk, char, line, q);
input clk;
input [3:0] char;
input [2:0] line;
output reg[3:0] q;
always @(char or pixels0 or pixels1 or pixels2 or pixels3 or pixels4 or pixels5 or pixels6 or pixels7 or pixels8 or pixels9)
case (char)
4'd0 : q <= pixels0;
4'd1 : q <= pixels1;
4'd2 : q <= pixels2;
4'd3 : q <= pixels3;
4'd4 : q <= pixels4;
4'd5 : q <= pixels5;
4'd6 : q <= pixels6;
4'd7 : q <= pixels7;
4'd8 : q <= pixels8;
4'd9 : q <= pixels9;
default:
q <= 0;
endcase
wire [3:0] pixels0;
digit #(
4'b1110,
4'b1010,
4'b1010,
4'b1010,
4'b1110
) dzigit0(line, pixels0);
wire [3:0] pixels1;
digit #(
4'b1100,
4'b0100,
4'b0100,
4'b0100,
4'b1110
) dzigit1(line, pixels1);
wire [3:0] pixels2;
digit #(
4'b1110,
4'b0010,
4'b1110,
4'b1000,
4'b1110
) dzigit2(line, pixels2);
wire [3:0] pixels3;
digit #(
4'b1110,
4'b0010,
4'b0110,
4'b0010,
4'b1110
) dzigit3(line, pixels3);
wire [3:0] pixels4;
digit #(
4'b1010,
4'b1010,
4'b1110,
4'b0010,
4'b0010
) dzigit4(line, pixels4);
wire [3:0] pixels5;
digit #(
4'b1110,
4'b1000,
4'b1110,
4'b0010,
4'b1110
) dzigit5(line, pixels5);
wire [3:0] pixels6;
digit #(
4'b1110,
4'b1000,
4'b1110,
4'b1010,
4'b1110
) dzigit6(line, pixels6);
wire [3:0] pixels7;
digit #(
4'b1110,
4'b0010,
4'b0010,
4'b0010,
4'b0010
) dzigit7(line, pixels7);
wire [3:0] pixels8;
digit #(
4'b1110,
4'b1010,
4'b1110,
4'b1010,
4'b1110
) dzigit8(line, pixels8);
wire [3:0] pixels9;
digit #(
4'b1110,
4'b1010,
4'b1110,
4'b0010,
4'b1110
) dzigit9(line, pixels9);
endmodule
module digit(scanline, pixels);
input [2:0] scanline;
output [3:0] pixels;
parameter a=0,b=0,c=0,d=0,e=0;
assign pixels = scanline == 3'd0 ? {a[0],a[1],a[2],a[3]} :
scanline == 3'd1 ? {b[0],b[1],b[2],b[3]} :
scanline == 3'd2 ? {c[0],c[1],c[2],c[3]} :
scanline == 3'd3 ? {d[0],d[1],d[2],d[3]} :
scanline == 3'd4 ? {e[0],e[1],e[2],e[3]} : 4'b0000;
endmodule
module counter_mod8(c, r, q, cout);
input c, r;
output [2:0] q;
output reg cout;
reg[2:0] ctval;
assign q = ctval;
always @(posedge c or posedge r)
if (r)
{cout, ctval} <= 0;
else
{cout,ctval} <= ctval + 1'b1;
endmodule
module counter_mod4(c, r, q, cout);
input c, r;
output reg[1:0] q;
output reg cout;
always @(posedge c)
if (r)
{cout, q} <= 0;
else
{cout, q} <= q + 1'b1;
endmodule
// $Id: scores2.v,v 1.9 2007/08/27 22:14:51 svo Exp $
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int a[n], b[n], o = 0, z = 0, sorted = 1; for (int i = 0; i < n; i++) { cin >> a[i]; if (i > 0 && a[i] < a[i - 1]) sorted = 0; } for (int i = 0; i < n; i++) { cin >> b[i]; if (b[i]) o++; else z++; } if ((z && o) || (sorted)) cout << Yes << endl; else cout << No << endl; } }
|
#include <bits/stdc++.h> using namespace std; vector<int> a; int k, t, n, mx; string s; int main() { cin >> n >> k; cin >> s; for (int i = 0; i < s.size(); i++) if (s[i] == . ) a.push_back(i); for (int i = 0; i < a.size() - 1; i++) mx = max(mx, a[i + 1] - a[i]); if (mx > k) cout << NO ; else cout << YES ; }
|
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency read mode. In this case
// we are generating the unmodulated low frequency carrier.
// The A/D samples at that same rate and the result is serialized.
//
// Jonathan Westhues, April 2006
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
module lo_read(
input pck0, input [7:0] pck_cnt, input pck_divclk,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk,
output ssp_frame, output ssp_din, output ssp_clk,
output dbg,
input lf_field
);
reg [7:0] to_arm_shiftreg;
// this task also runs at pck0 frequency (24MHz) and is used to serialize
// the ADC output which is then clocked into the ARM SSP.
// because pck_divclk always transitions when pck_cnt = 0 we use the
// pck_div counter to sync our other signals off it
// we read the ADC value when pck_cnt=7 and shift it out on counts 8..15
always @(posedge pck0)
begin
if((pck_cnt == 8'd7) && !pck_divclk)
to_arm_shiftreg <= adc_d;
else begin
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
// simulation showed a glitch occuring due to the LSB of the shifter
// not being set as we shift bits out
// this ensures the ssp_din remains low after a transfer and suppresses
// the glitch that would occur when the last data shifted out ended in
// a 1 bit and the next data shifted out started with a 0 bit
to_arm_shiftreg[0] <= 1'b0;
end
end
// ADC samples on falling edge of adc_clk, data available on the rising edge
// example of ssp transfer of binary value
// start of transfer is indicated by the rise of the ssp_frame signal
// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
// the ARM by the falling edge of ssp_clk
// _______________________________
// ssp_frame__| |__
// _______ ___ ___
// ssp_din __| |_______| |___| |______
// _ _ _ _ _ _ _ _ _ _
// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
// serialized SSP data is gated by ant_lo to suppress unwanted signal
assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
// SSP clock always runs at 24MHz
assign ssp_clk = pck0;
// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;
// unused signals tied low
assign pwr_hi = 1'b0;
assign pwr_oe1 = 1'b0;
assign pwr_oe2 = 1'b0;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
// this is the antenna driver signal
assign pwr_lo = lf_field & pck_divclk;
// ADC clock out of phase with antenna driver
assign adc_clk = ~pck_divclk;
// ADC clock also routed to debug pin
assign dbg = adc_clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n = 0, m = 0, q = 0; long long ans = 0; vector<vector<int>> G = vector<std::vector<int>>(100001); vector<long long> f(112345), fa(100001), dep(100001), val(100001), sz(100001), s(100001); long long F(long long x) { return x == f[x] ? x : (f[x] = F(f[x])); } void dfs(long long u, long long ff) { sz[u] = 1; dep[u] = dep[ff] + 1; fa[u] = ff; for (int i = 0; i < G[u].size(); ++i) { long long v = G[u][i]; if (v == ff) { continue; } dfs(v, u); sz[u] += sz[v]; val[u] += sz[v] * sz[v]; } val[u] += (n - sz[u]) * (n - sz[u]); ans -= val[u]; } void merge(int x, int y) { ans -= s[x] * (s[x] - 1) * (s[x] - 2); ans -= s[y] * (s[y] - 1) * (s[y] - 2); ans -= s[x] * (s[x] - 1) * (n - s[x]) * 2; ans -= s[y] * (s[y] - 1) * (n - s[y]) * 2; ans -= (n - s[x]) * (n - s[x]) * s[x]; ans -= (n - s[y]) * (n - s[y]) * s[y]; ans += val[x] * s[x]; ans += val[y] * s[y]; val[x] += val[y] - sz[y] * sz[y] - (n - sz[y]) * (n - sz[y]); s[x] += s[y]; f[y] = x; ans += s[x] * (s[x] - 1) * (s[x] - 2); ans += s[x] * (s[x] - 1) * (n - s[x]) * 2; ans += (n - s[x]) * (n - s[x]) * s[x]; ans -= val[x] * s[x]; } int main() { cin >> n; for (int i = 1; i <= n; ++i) { G[i] = std::vector<int>(); s[i] = 1; f[i] = i; } for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } ans = 1LL * n * (n - 1) * (n - 1); dfs(1, 0); cout << ans << endl; cin >> q; while (q-- > 0) { int u, v; cin >> u >> v; u = F(u); v = F(v); while (u != v) { if (dep[u] < dep[v]) { int o = v; v = u; u = o; } merge(F(fa[u]), u); u = F(u); } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void prv(vector<int> v) { int n = v.size(); for (int i = 0; i < n; i++) cout << v[i] << ; } void swap(long long int &a, long long int &b) { int tm = a; a = b; b = tm; } bool comp(const pair<int, int> &p1, const pair<int, int> &p2) { if (p1.first > p2.first) return 1; else return 0; } const int N = 3e5 + 5; void findPrefix(string pattern, int m, int prefArray[]) { int length = 0; prefArray[0] = 0; for (int i = 1; i < m; i++) { if (pattern[i] == pattern[length]) { length++; prefArray[i] = length; } else { if (length != 0) { length = prefArray[length - 1]; i--; } else prefArray[i] = 0; } } } int kmpPattSearch(string mainString, string pattern) { int n, m, i = 0, j = 0, fr = 0; n = mainString.size(); m = pattern.size(); int prefixArray[m]; findPrefix(pattern, m, prefixArray); while (i < n) { if (mainString[i] == pattern[j]) { i++; j++; } if (j == m) { fr++; j = prefixArray[j - 1]; } else if (i < n && pattern[j] != mainString[i]) { if (j != 0) j = prefixArray[j - 1]; else i++; } } return fr; } string crts(int d, int m, int y) { string t; t.clear(); while (y != 0) { t.push_back(y % 10 + 0 ); y = y / 10; } t.push_back( - ); while (m != 0) { t.push_back(m % 10 + 0 ); m = m / 10; } if (t.size() == 6) t.push_back( 0 ); t.push_back( - ); while (d != 0) { t.push_back(d % 10 + 0 ); d = d / 10; } if (t.size() == 9) t.push_back( 0 ); reverse((t).begin(), (t).end()); return t; } void solve() { string s, ans; cin >> s; int mx = 0; for (int i = 2013; i < 2016; ++i) { for (int j = 1; j <= 12; j++) { int k; if (j == 2) k = 28; else if (j == 1 || j == 3 || j == 5 || j == 7 || j == 8 || j == 10 || j == 12) k = 31; else k = 30; for (int l = 1; l <= k; l++) { string t; int frq; t = crts(l, j, i); frq = kmpPattSearch(s, t); if (frq > mx) { mx = frq; ans = t; } } } } cout << ans; } signed int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); cout << n ; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 10:58:35 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_stub.v
// Design : system_vga_hessian_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_hessian,Vivado 2016.4" *)
module system_vga_hessian_0_0(clk_x16, active, rst, x_addr, y_addr, g_in,
hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]" */;
input clk_x16;
input active;
input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_BLACKBOX_V
`define SKY130_FD_SC_HVL__XNOR2_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_BLACKBOX_V
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_divide
// ============================================================
// File Name: DIV.v
// Megafunction Name(s):
// lpm_divide
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DIV (
aclr,
clock,
denom,
numer,
quotient,
remain);
input aclr;
input clock;
input [3:0] denom;
input [9:0] numer;
output [9:0] quotient;
output [3:0] remain;
wire [9:0] sub_wire0;
wire [3:0] sub_wire1;
wire [9:0] quotient = sub_wire0[9:0];
wire [3:0] remain = sub_wire1[3:0];
lpm_divide lpm_divide_component (
.denom (denom),
.aclr (aclr),
.clock (clock),
.numer (numer),
.quotient (sub_wire0),
.remain (sub_wire1),
.clken (1'b1));
defparam
lpm_divide_component.lpm_drepresentation = "UNSIGNED",
lpm_divide_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
lpm_divide_component.lpm_nrepresentation = "UNSIGNED",
lpm_divide_component.lpm_pipeline = 1,
lpm_divide_component.lpm_type = "LPM_DIVIDE",
lpm_divide_component.lpm_widthd = 4,
lpm_divide_component.lpm_widthn = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "10"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: denom 0 0 4 0 INPUT NODEFVAL denom[3..0]
// Retrieval info: USED_PORT: numer 0 0 10 0 INPUT NODEFVAL numer[9..0]
// Retrieval info: USED_PORT: quotient 0 0 10 0 OUTPUT NODEFVAL quotient[9..0]
// Retrieval info: USED_PORT: remain 0 0 4 0 OUTPUT NODEFVAL remain[3..0]
// Retrieval info: CONNECT: @numer 0 0 10 0 numer 0 0 10 0
// Retrieval info: CONNECT: @denom 0 0 4 0 denom 0 0 4 0
// Retrieval info: CONNECT: quotient 0 0 10 0 @quotient 0 0 10 0
// Retrieval info: CONNECT: remain 0 0 4 0 @remain 0 0 4 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV_bb.v FALSE
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
module recF16ToF16 (input [16:0] in, output [15:0] out);
recFNToFN#(5, 11) recFNToFN(in, out);
endmodule
module recF32ToF32 (input [32:0] in, output [31:0] out);
recFNToFN#(8, 24) recFNToFN(in, out);
endmodule
module recF64ToF64 (input [64:0] in, output [63:0] out);
recFNToFN#(11, 53) recFNToFN(in, out);
endmodule
module recF128ToF128 (input [128:0] in, output [127:0] out);
recFNToFN#(15, 113) recFNToFN(in, out);
endmodule
|
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
`include "isa.h"
`include "cpu.h"
module if_reg (
input wire clk,
input wire reset,
input wire [`WordDataBus] insn,
input wire stall,
input wire flush,
input wire [`WordAddrBus] new_pc,
input wire br_taken,
input wire [`WordAddrBus] br_addr,
output reg [`WordAddrBus] if_pc,
output reg [`WordDataBus] if_insn,
output reg if_en
);
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
if_pc <= #1 `RESET_VECTOR;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else begin
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin
if_pc <= #1 new_pc;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else if (br_taken == `ENABLE) begin
if_pc <= #1 br_addr;
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end else begin
if_pc <= #1 if_pc + 1'd1;
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end
end
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
parameter DATA_WIDTH = 16;
parameter ADDRESS_WIDTH = 5;
localparam DW = DATA_WIDTH - 1;
localparam AW = ADDRESS_WIDTH - 1;
input clka;
input wea;
input [AW:0] addra;
input [DW:0] dina;
input clkb;
input [AW:0] addrb;
output [DW:0] doutb;
reg [DW:0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
reg [DW:0] doutb;
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
doutb <= m_ram[addrb];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; char ans[1000000]; int main() { int n, c, k = 1, u = 0, w = 1, h = 0; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int m = 0; while (w) { u = 0; for (int i = 0; i < n; i++) { if (a[i] == 0) u++; } if (u == n) break; c = 0; for (int i = h; i < n; i++) { if (a[i] != 0) { ans[m] = P ; a[i]--; m++; u = 0; for (int i = 0; i < n; i++) { if (a[i] == 0) u++; } if (u == n) { break; w = 0; } if ((i + 1) != n) { ans[m] = R ; m++; } u = 0; for (int i = 0; i < n; i++) { if (a[i] == 0) u++; } if (u == n) { break; w = 0; } } else if (a[i] == 0) { u = 0; for (int i = 0; i < n; i++) { if (a[i] == 0) u++; } if (u == n) { break; w = 0; } if ((i + 1) != n) { ans[m] = R ; m++; } } } u = 0; for (int i = 0; i < n; i++) { if (a[i] == 0) u++; } if (u == n) break; ans[m] = L ; m++; for (int i = (n - 2); i >= 0; i--) { if (a[i] != 0) { ans[m] = P ; a[i]--; m++; u = 0; for (int i = 0; i < n; i++) { if (a[i] == 0) u++; } if (u == n) { break; w = 0; } if ((i - 1) != -1) { ans[m] = L ; m++; } u = 0; for (int i = 0; i < n; i++) { if (a[i] == 0) u++; } if (u == n) { break; w = 0; } } else if (a[i] == 0) { u = 0; for (int i = 0; i < n; i++) { if (a[i] == 0) u++; } if (u == n) { break; w = 0; } if ((i - 1) != -1) { ans[m] = L ; m++; } } if (i == 0) { ans[m] = R ; m++; } } u = 0; for (int i = 0; i < n; i++) { if (a[i] == 0) u++; } if (u == n) break; h = 1; } for (int i = 0; i < m; i++) cout << ans[i]; cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10; int n, m; struct bian { int from, to; }; struct tree { bian eg[N << 2]; int num, front[N << 1]; int zong; int fa[N << 1], siz[N << 1]; void add(int x, int y) { eg[++num].to = y; eg[num].from = front[x]; front[x] = num; } void init() { zong = n; for (int i = 1; i <= zong; ++i) fa[i] = i, siz[i] = 1; } int find(int x) { return x == fa[x] ? x : fa[x] = find(fa[x]); } int tot, now; int son[N << 4][2]; long long tag[N << 4]; int root[N]; void merge(int x, int y) { int d1 = find(x), d2 = find(y); fa[++zong] = zong; add(zong, d1); add(zong, d2); siz[zong] = siz[find(x)] + siz[find(y)]; fa[d1] = zong; fa[d2] = zong; } int ll[N << 1], rr[N << 1], ids[N], p; void dfs(int o) { if (o <= n) { ids[o] = ++p; ll[o] = rr[o] = ids[o]; return; } ll[o] = 1e9; for (int i = front[o]; i; i = eg[i].from) { int to = eg[i].to; dfs(to); ll[o] = min(ll[o], ll[to]); rr[o] = max(rr[o], rr[to]); } } void opt1(int be, int &o, int l, int r, int L, int R, int w) { if (o == 0) o = ++tot; tag[o] = tag[be]; if (L <= l && r <= R) { tag[o] += w; son[o][0] = son[be][0]; son[o][1] = son[be][1]; return; } int mid = (l + r) >> 1; if (mid >= L) opt1(son[be][0], son[o][0], l, mid, L, R, w); else son[o][0] = son[be][0]; if (mid < R) opt1(son[be][1], son[o][1], mid + 1, r, L, R, w); else son[o][1] = son[be][1]; } long long opt2(int o, int l, int r, int i, long long now) { if (o == 0) return now; if (l == r) return now + tag[o]; int mid = (l + r) >> 1; if (mid >= i) return opt2(son[o][0], l, mid, i, now + tag[o]); else return opt2(son[o][1], mid + 1, r, i, now + tag[o]); } } T1; struct tree_ { bian eg[N << 2]; int num, front[N << 1]; int zong; int fa[N << 1]; void add(int x, int y) { eg[++num].to = y; eg[num].from = front[x]; front[x] = num; } void init() { zong = n; for (int i = 1; i <= zong; ++i) fa[i] = i; } int find(int x) { return x == fa[x] ? x : fa[x] = find(fa[x]); } void merge(int x, int y) { int d1 = find(x), d2 = find(y); fa[++zong] = zong; add(zong, d1); add(zong, d2); fa[d1] = zong; fa[d2] = zong; } int ll[N << 1], rr[N << 1], ids[N], p; void dfs(int o) { if (o <= n) { ids[o] = ++p; ll[o] = rr[o] = ids[o]; return; } ll[o] = 1e9; for (int i = front[o]; i; i = eg[i].from) { int to = eg[i].to; dfs(to); ll[o] = min(ll[o], ll[to]); rr[o] = max(rr[o], rr[to]); } } int col[N << 2]; void opt3(int o, int l, int r, int L, int R, int w) { if (L <= l && r <= R) { col[o] = w; return; } int mid = (l + r) >> 1; if (col[o]) { col[o << 1] = col[o << 1 | 1] = col[o]; col[o] = 0; } if (mid >= L) opt3(o << 1, l, mid, L, R, w); if (mid < R) opt3(o << 1 | 1, mid + 1, r, L, R, w); } int opt4(int o, int l, int r, int i) { if (l == r) return col[o]; int mid = (l + r) >> 1; if (col[o]) { col[o << 1] = col[o << 1 | 1] = col[o]; col[o] = 0; } if (mid >= i) return opt4(o << 1, l, mid, i); else return opt4(o << 1 | 1, mid + 1, r, i); } } T2; int que[N][3]; struct b { int fa[N << 1], zong; void init() { zong = n; for (int i = 1; i <= n; ++i) fa[i] = i; } int find(int o) { return fa[o] == o ? o : fa[o] = find(fa[o]); } void merge(int x, int y) { int d1 = find(x), d2 = find(y); fa[++zong] = zong; fa[d1] = zong; fa[d2] = zong; } } B1, B2; int main() { scanf( %d%d , &n, &m); T1.init(); T2.init(); for (int i = 1; i <= m; ++i) { char s[10]; scanf( %s , s); if (s[0] == U ) { int x, y; scanf( %d%d , &x, &y); que[i][0] = 1; que[i][1] = x; que[i][2] = y; T1.merge(x, y); } if (s[0] == M ) { int x, y; scanf( %d%d , &x, &y); que[i][0] = 2; que[i][1] = x; que[i][2] = y; T2.merge(x, y); } if (s[0] == A ) { int x; scanf( %d , &x); que[i][0] = 3; que[i][1] = x; } if (s[0] == Z ) { int x; scanf( %d , &x); que[i][0] = 4; que[i][1] = x; } if (s[0] == Q ) { int x; scanf( %d , &x); que[i][0] = 5; que[i][1] = x; } } for (int i = 1; i <= T1.zong; ++i) if (T1.find(i) == i) T1.dfs(i); for (int i = 1; i <= T2.zong; ++i) if (T2.find(i) == i) T2.dfs(i); B1.init(); B2.init(); for (int i = 1; i <= m; ++i) { if (que[i][0] == 1) { B1.merge(que[i][1], que[i][2]); } if (que[i][0] == 2) { B2.merge(que[i][1], que[i][2]); } if (que[i][0] == 3) { ++T1.now; T1.opt1(T1.root[T1.now - 1], T1.root[T1.now], 1, n, T1.ll[B1.find(que[i][1])], T1.rr[B1.find(que[i][1])], T1.siz[B1.find(que[i][1])]); } if (que[i][0] == 4) { T2.opt3(1, 1, n, T2.ll[B2.find(que[i][1])], T2.rr[B2.find(que[i][1])], T1.now); } if (que[i][0] == 5) { printf( %lld n , T1.opt2(T1.root[T1.now], 1, n, T1.ids[que[i][1]], 0) - T1.opt2(T1.root[T2.opt4(1, 1, n, T2.ids[que[i][1]])], 1, n, T1.ids[que[i][1]], 0)); } } }
|
`timescale 1ns / 1ps
module spi_amba_connector(
input clk,
input rst,
input hwrite,
input [31:0] hwdata,
input [31:0] haddr,
input hsel,
output [31:0] hrdata,
input [ 7:0] spi_data_out,
input spi_busy,
output reg [ 7:0] spi_data_in,
output reg spi_ready_send
);
reg [7:0] spi_data_out_reg;
reg [7:0] spi_data_in_reg;
assign hrdata = {{25'b0, phase || spi_busy || spi_ready_send, spi_busy ? spi_data_out_reg : spi_data_out}};
localparam IDLE = 0, DATA = 1;
reg phase;
always @(posedge clk) begin
if (rst) begin
spi_data_in <= 0;
spi_ready_send <= 0;
phase <= 0;
end else if (spi_ready_send && spi_busy) begin
spi_ready_send <= 0;
end else if (!spi_ready_send && !spi_busy) begin
if (!phase) begin
if (hsel && haddr[15:0] == 'h0000 && hwrite) phase <= 1;
end else begin
spi_data_out_reg <= spi_data_in;
spi_data_in <= spi_data_in_reg;
spi_ready_send <= 1;
phase <= 0;
end
end
end
always @(negedge clk) begin
if (phase) spi_data_in_reg <= hwdata[7:0];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; if (n <= 30) { cout << NO n ; } else if (n == 36) { cout << YES n ; cout << 5 6 10 15 << n ; } else if (n == 40) { cout << YES n ; cout << 9 6 10 15 << n ; } else if (n == 44) { cout << YES n ; cout << 6 7 10 21 << n ; } else { cout << YES n ; cout << 6 10 14 << n - 30 << n ; } } return 0; }
|
module TopLevel (
input wire clk,
input wire rst_in,
input wire[3:0] switch_in,
output wire buzzer,
output wire[3:0] led_out,
inout wire ps2CLK_in,
input wire ps2DATA_in,
//output wire vgaR_out,
//output wire vgaG_out,
//output wire vgaB_out,
//output wire vgaHSYNC_out,
//output wire vgaVSYNC_out,
output wire[3:0] tubeDig_out,
output wire[7:0] tubeSeg_out,
output wire[7:0] lcdData,
output wire lcdRS,
output wire lcdRW,
output wire lcdE,
input wire ir_in,
output wire uartTXD_out,
input wire uartRXD_in
);
parameter DIVISIONREGSIZE = 18;
reg[DIVISIONREGSIZE-1 : 0] adder = {DIVISIONREGSIZE{1'b0}};
always @ (posedge clk)
adder <= adder + 18'b1;
wire[3:0] led;
wire[3:0] tubeDig;
wire[7:0] tubeSeg;
//wire[2:0] vgaRGB;
//wire vgaH;
//wire vgaV;
wire uartTXD;
wire[3:0] switch = ~switch_in;
wire rst = ~rst_in;
wire ps2Inhibit;
reg ps2InhibitPrev = 0;
reg[10:0] inhibitCounter = 11'h7FF;
always @ (posedge clk) begin
ps2InhibitPrev <= ps2Inhibit;
if (ps2Inhibit && !ps2InhibitPrev) inhibitCounter <= 0;
else if (inhibitCounter != 11'h7FF) inhibitCounter <= inhibitCounter + 1;
end
//wire ps2CLK = ps2CLK_in;
//wire ps2DATA = ps2DATA_in;
//assign ps2CLK_in = (inhibitCounter == 11'h7FF)? 1'bz : 1'b0;
assign led_out = ~led;
assign tubeSeg_out = ~tubeSeg;
assign tubeDig_out = ~tubeDig;
assign buzzer = 0;
//assign {vgaR_out, vgaG_out, vgaB_out} = vgaRGB;
//assign vgaHSYNC_out = vgaH;
//assign vgaVSYNC_out = vgaV;
assign uartTXD_out = uartTXD;
wire uartRXD = uartRXD_in;
wire ir = ~ir_in;
reg[1:0] dig;
always @ (posedge adder[17])
dig <= dig + 2'b1;
wire[10:0] lcdPins;
assign {lcdRS, lcdRW, lcdE, lcdData} = lcdPins;
wire bttnClk;
wire irq;
PushButton_Debouncer debouncer (clk, switch_in[3], bttnClk);
wire[1:0] cpuClkMode;
wire cpuClk = cpuClkMode[1] == 1'b0 ? bttnClk :
cpuClkMode[0] == 1'b0 ? adder[15] : adder[6];
Rintaro rintaro (
.fastClk (clk),
.clk1 (!cpuClk),
.clk2 (cpuClk),
.rst (rst),
.dig (dig),
.switch (switch[2:0]),
.tubeDig (tubeDig),
.tubeSeg (tubeSeg),
.lcdPins (lcdPins),
.ps2CLK (ps2CLK_in),
.ps2DATA (ps2DATA_in),
.irqOut (irq),
.ir (ir),
.err (err),
.stateOut (stateOut),
.cpuClkMode (cpuClkMode)
);
wire[7:0] rs232Data;
wire rs232Ready;
RS232Controller rs232 (
.clk (clk),
.rst (rst),
.rs232RX (uartRXD),
.rs232TX (uartTXD),
.rxData (rs232Data),
.rxReady (rs232Ready),
.txData (rs232Data),
.txStart (rs232Ready)
);
assign led = {lcdRS, lcdRW, lcdE, lcdData[0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9; int n, m; long long a[200100], fibo[200100], sumfibo[200100]; struct Segment_Tree { int left, right, len; long long s0, s1; } tree[200100 << 2]; struct Data { long long a[2][2]; } bb[200100], one, b; Data operator*(const Data x, const Data y) { Data res; res.a[0][0] = (x.a[0][0] * y.a[0][0] % mod + x.a[0][1] * y.a[1][0] % mod) % mod; res.a[0][1] = (x.a[0][0] * y.a[0][1] % mod + x.a[0][1] * y.a[1][1] % mod) % mod; res.a[1][0] = (x.a[1][0] * y.a[0][0] % mod + x.a[1][1] * y.a[1][0] % mod) % mod; res.a[1][1] = (x.a[1][0] * y.a[0][1] % mod + x.a[1][1] * y.a[1][1] % mod) % mod; return res; } long long cal_fx(long long s0, long long s1, int l) { long long res; res = (bb[l - 1].a[0][0] * s1 % mod + bb[l - 1].a[0][1] * s0 % mod) % mod; return res; } void plant_tree(int id, int l, int r) { tree[id].left = l, tree[id].right = r; tree[id].len = r - l + 1; if (l == r) { tree[id].s0 = fibo[0] * a[l] % mod; tree[id].s1 = fibo[1] * a[l] % mod; return; } int mid = (l + r) >> 1; plant_tree(id << 1, l, mid); plant_tree(id << 1 | 1, mid + 1, r); tree[id].s0 = (tree[id << 1].s0 + cal_fx(tree[id << 1 | 1].s0, tree[id << 1 | 1].s1, tree[id << 1].len)) % mod; tree[id].s1 = (tree[id << 1].s1 + cal_fx(tree[id << 1 | 1].s0, tree[id << 1 | 1].s1, tree[id << 1].len + 1)) % mod; } void push_down() {} void update_pos(int id, int pos, long long val) { if (tree[id].left == tree[id].right) { tree[id].s0 = fibo[0] * val % mod; tree[id].s1 = fibo[1] * val % mod; return; } int mid = (tree[id].left + tree[id].right) >> 1; if (pos <= mid) update_pos(id << 1, pos, val); else update_pos(id << 1 | 1, pos, val); tree[id].s0 = (tree[id << 1].s0 + cal_fx(tree[id << 1 | 1].s0, tree[id << 1 | 1].s1, tree[id << 1].len)) % mod; tree[id].s1 = (tree[id << 1].s1 + cal_fx(tree[id << 1 | 1].s0, tree[id << 1 | 1].s1, tree[id << 1].len + 1)) % mod; } Segment_Tree query(int id, int l, int r) { if (tree[id].left == l && tree[id].right == r) { return tree[id]; } int mid = (tree[id].left + tree[id].right) >> 1; if (r <= mid) return query(id << 1, l, r); else if (mid < l) return query(id << 1 | 1, l, r); else { Segment_Tree leftson, rightson, now; leftson = query(id << 1, l, mid); rightson = query(id << 1 | 1, mid + 1, r); now.s0 = (leftson.s0 + cal_fx(rightson.s0, rightson.s1, leftson.len)) % mod; now.s1 = (leftson.s1 + cal_fx(rightson.s0, rightson.s1, leftson.len + 1)) % mod; now.len = leftson.len + rightson.len; return now; } } int main() { fibo[0] = fibo[1] = 1; for (int i = 2; i < 200100; i++) { fibo[i] = (fibo[i - 2] + fibo[i - 1]) % mod; } sumfibo[0] = fibo[0]; for (int i = 1; i < 200100; i++) { sumfibo[i] = (sumfibo[i - 1] + fibo[i]) % mod; } one.a[0][0] = one.a[1][1] = 1; one.a[1][0] = one.a[0][1] = 0; b.a[0][0] = b.a[0][1] = b.a[1][0] = 1; b.a[1][1] = 0; bb[0] = one; for (int i = 1; i < 200100; i++) { bb[i] = bb[i - 1] * b; } scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %lld , a + i); } plant_tree(1, 1, n); while (m--) { int type; scanf( %d , &type); if (type == 1) { int x, v; scanf( %d %d , &x, &v); update_pos(1, x, v); } else if (type == 2) { int l, r; scanf( %d %d , &l, &r); Segment_Tree res = query(1, l, r); printf( %lld n , res.s0); } else if (type == 3) { int l, r, d; scanf( %d %d %d , &l, &r, &d); } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__AND4B_BEHAVIORAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4b (
VPWR,
VGND,
X ,
A_N ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
input C ;
input D ;
// Local signals
wire D not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4B_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long l1, l2, r1, r2, k; int main() { cin >> l1 >> r1 >> l2 >> r2 >> k; if (l2 > r1 || r2 < l1) { cout << 0 << n ; return 0; } long long l, r; if (r1 < r2) { r = r1; } else { r = r2; } if (l1 > l2) { l = l1; } else { l = l2; } long long flag = 0; if (k >= l && k <= r) { flag = 1; } cout << r - l - flag + 1 << n ; return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_128x512a.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_128x512a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [127:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [127:0] q;
output rdempty;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [127:0] sub_wire1;
wire sub_wire2;
wire [9:0] sub_wire3;
wire wrfull = sub_wire0;
wire [127:0] q = sub_wire1[127:0];
wire rdempty = sub_wire2;
wire [9:0] wrusedw = sub_wire3[9:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdfull (),
.rdusedw (),
.wrempty ());
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_numwords = 1024,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 128,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "128"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "128"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]"
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: register.v
// Version: 1.00
// Verilog Standard: Verilog-2001
// Description: A simple parameterized register
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module register
#(parameter C_WIDTH = 1,
parameter C_VALUE = 0
)
(input CLK,
input RST_IN,
output [C_WIDTH-1:0] RD_DATA,
input [C_WIDTH-1:0] WR_DATA,
input WR_EN
);
reg [C_WIDTH-1:0] rData;
assign RD_DATA = rData;
always @(posedge CLK) begin
if(RST_IN) begin
rData <= C_VALUE;
end else if(WR_EN) begin
rData <= WR_DATA;
end
end
endmodule
|
`include "mux.v"
`include "addsub32.v"
`include "shifter.v"
module alu(
input [31:0] a,
input [31:0] b,
input [3:0] aluc,
output [31:0] r,
output zero,
output carry,
output negative,
output overflow
);
reg zero_temp;
reg carry_temp;
reg negative_temp;
reg overflow_temp;
reg [31:0] r_temp;
assign r=r_temp;
assign zero=zero_temp;
assign carry=carry_temp;
assign negative=negative_temp;
assign overflow=overflow_temp;
wire [31:0] result_temp [7:0];
wire [7:0] zero_flag;
wire [7:0] carry_flag;
wire [7:0] negative_flag;
wire [7:0] overflow_flag;
addsub32 as32_1(a,b,aluc[1],aluc[0],result_temp[0],zero_flag[0],carry_flag[0],negative_flag[0],overflow_flag[0]);
addsub32 as32_2(a,b,aluc[1],aluc[0],result_temp[1],zero_flag[1],carry_flag[1],negative_flag[1],overflow_flag[1]);
addsub32 as32_3(a,b,aluc[1],aluc[0],result_temp[2],zero_flag[2],carry_flag[2],negative_flag[2],overflow_flag[2]);
addsub32 as32_4(a,b,aluc[1],aluc[0],result_temp[3],zero_flag[3],carry_flag[3],negative_flag[3],overflow_flag[3]);
shifter shift_1(a,b,aluc[1],aluc[0],result_temp[4],zero_flag[4],carry_flag[4],negative_flag[4],overflow_flag[4]);
shifter shift_2(a,b,aluc[1],aluc[0],result_temp[5],zero_flag[5],carry_flag[5],negative_flag[5],overflow_flag[5]);
shifter shift_3(a,b,aluc[1],aluc[0],result_temp[6],zero_flag[6],carry_flag[6],negative_flag[6],overflow_flag[6]);
shifter shift_4(a,b,aluc[1],aluc[0],result_temp[7],zero_flag[7],carry_flag[7],negative_flag[7],overflow_flag[7]);
always @(*) begin
casex(aluc)
4'b0000:begin // a + b (unsigned)
r_temp=result_temp[0];
zero_temp=zero_flag[0];
carry_temp=carry_flag[0];
negative_temp=negative_flag[0];
overflow_temp=overflow_flag[0];
end
4'b0010:begin // a + b (signed)
zero_temp=zero_flag[1];
carry_temp=carry_flag[1];
negative_temp=negative_flag[1];
overflow_temp=overflow_flag[1];
if ( ~overflow_temp ) begin //fix bug
r_temp=result_temp[3];
end
end
4'b0001:begin // a - b(unsigned)
r_temp=result_temp[2];
zero_temp=zero_flag[2];
carry_temp=carry_flag[2];
negative_temp=negative_flag[2];
overflow_temp=overflow_flag[2];
end
4'b0011:begin // a - b(signed)
zero_temp=zero_flag[3];
carry_temp=carry_flag[3];
negative_temp=negative_flag[3];
overflow_temp=overflow_flag[3];
if ( ~overflow_temp ) begin //fix bug
r_temp=result_temp[3];
end
end
4'b1100: begin //sra
r_temp=result_temp[4];
zero_temp=zero_flag[4];
carry_temp=carry_flag[4];
negative_temp=negative_flag[4];
overflow_temp=overflow_flag[4];
end
4'b1110:begin //srl
r_temp=result_temp[5];
zero_temp=zero_flag[5];
carry_temp=carry_flag[5];
negative_temp=negative_flag[5];
overflow_temp=overflow_flag[5];
end
4'b1111:begin //sll
r_temp=result_temp[6];
zero_temp=zero_flag[6];
carry_temp=carry_flag[6];
negative_temp=negative_flag[6];
overflow_temp=overflow_flag[6];
end
4'b1101:begin //slv
r_temp=result_temp[7];
zero_temp=zero_flag[7];
carry_temp=carry_flag[7];
negative_temp=negative_flag[7];
overflow_temp=overflow_flag[7];
end
4'b0100:begin // AND
r_temp = a & b;
if( r_temp == 0 )
zero_temp = 1;
else
zero_temp = 0;
carry_temp = 0;
overflow_temp = 0;
if( r_temp[31] == 1 )
negative_temp = 1;
else if( r_temp[31] == 0 )
negative_temp = 0;
end
4'b0101: begin //OR
r_temp = a | b;
if( r_temp == 0 )
zero_temp=1;
else
zero_temp=0;
carry_temp=0;
overflow_temp=0;
if( r_temp[31] == 1 )
negative_temp = 1;
else if( r_temp[31] == 0 )
negative_temp=0;
end
4'b0110:begin //XOR
r_temp = a^b;
if(r_temp==0)
zero_temp=1;
else
zero_temp=0;
carry_temp=0;
overflow_temp=0;
if( r_temp[31] == 1 )
negative_temp = 1;
else if(r_temp[31] == 0 )
negative_temp = 0;
end
4'b0111:begin //NOR
r_temp = ~(a|b);
if( r_temp == 0 )
zero_temp = 1;
else
zero_temp = 0;
carry_temp=0;
overflow_temp=0;
if(r_temp[31]==1)
negative_temp=1;
else if(r_temp[31]==0)
negative_temp=0;
end
4'b1000:begin //LUI
r_temp = {b[15:0],16'b0};
if (r_temp == 0 )
zero_temp = 1;
else zero_temp = 0;
if (r_temp[31])
negative_temp = 1;
else negative_temp = 0;
carry_temp = 0;
overflow_temp = 0;
end
4'b1001:begin //LUI
r_temp = {b[15:0],16'b0};
if (r_temp ==0)
zero_temp =1;
else zero_temp = 0;
if (r_temp[31])
negative_temp = 1;
else negative_temp = 0;
carry_temp = 0;
overflow_temp = 0;
end
4'b1011:begin //SLT, SLTI
r_temp=($signed(a)<$signed(b))?1:0;
end
4'b1010:begin //SLTU, SLTIU
r_temp=(a<b)?1:0;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41AI_1_V
`define SKY130_FD_SC_HS__O41AI_1_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41ai_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41AI_1_V
|
#include <bits/stdc++.h> using namespace std; struct num { static const int MA = 1e9 + 7, MB = 1e9 + 9; int a, b; num() {} num(int x) : a(x), b(x) {} num(int a, int b) : a(a), b(b) {} num operator+(const num& x) const { return num((a + x.a) % MA, (b + x.b) % MB); } num operator-(const num& x) const { return num((a + MA - x.a) % MA, (b + MB - x.b) % MB); } num operator*(int x) const { return num(((long long)a * x) % MA, ((long long)b * x) % MB); } num operator*(const num& x) const { return num(((long long)a * x.a) % MA, ((long long)b * x.b) % MB); } bool operator==(const num& x) const { return a == x.a && b == x.b; } }; struct num2 { static const int MB = 1e9 + 9; int b; num2() {} num2(int x) : b(x) {} num2 operator+(const num2& x) const { return num2((b + x.b) % MB); } num2 operator-(const num2& x) const { return num2((b + MB - x.b) % MB); } num2 operator*(int x) const { return num2(((long long)b * x) % MB); } num2 operator*(const num2& x) const { return num2(((long long)b * x.b) % MB); } bool operator==(const num2& x) const { return b == x.b; } }; const int MODP = 701; template <class T> struct StringOps { StringOps() {} StringOps(const string& s) : s(s) { n = s.length(); deg.resize(n + 1); hashes.resize(n); deg[0] = T(1); for (int i = 1; i <= n; ++i) { deg[i] = deg[i - 1] * T(MODP); } T curhash = T(0); for (int i = 0; i < n; ++i) { curhash = curhash * T(MODP) + T(s[i]); hashes[i] = curhash; } } char get(int idx) { return s[idx]; } T get_hash(int l, int r) { T cur(0); if (l > 0) { cur = hashes[l - 1]; } return hashes[r] - cur * deg[r - l + 1]; } int string_lcp(int l, int r, int lim = 1e9) { int cleft = 1, cright = min(n - r, n - l); cright = min(lim, cright); int res = 0; while (cleft <= cright) { int key = (cleft + cright) / 2; if (s[l + key - 1] != s[r + key - 1]) { cright = key - 1; } else if (get_hash(l, l + key - 1) == get_hash(r, r + key - 1)) { res = key; cleft = key + 1; } else { cright = key - 1; } } return res; } bool substring_cmp(int l1, int r1, int l2, int r2) { int lcp = string_lcp(l1, l2); int len1 = r1 - l1 + 1, len2 = r2 - l2 + 1; if (lcp >= len1 && lcp >= len2) { return len1 < len2; } if (lcp >= len1) { return true; } if (lcp >= len2) { return false; } return s[l1 + lcp] < s[l2 + lcp]; } vector<T> hashes; vector<T> deg; string s; int n; }; const int maxN = 1000100; const int MOD = 1e9 + 7; int len1, len2; int u, v; StringOps<num2> sops; int get_nlength(const pair<int, int>& a) { if (a.first == u) { if (a.second != len1) { return len1 - 1; } else { return len1; } } if (a.second != len2) { return len2 - 1; } else { return len2; } } void fill_segs(int& l1, int& r1, int& l2, int& r2, const pair<int, int>& a) { if (a.first == u) { l2 = r2 = -1; if (a.second == 0) { l1 = 1, r1 = len1 - 1; } else if (a.second >= len1 - 1) { l1 = 0, r1 = a.second - 1; } else { l1 = 0, r1 = a.second - 1; l2 = a.second + 1, r2 = len1 - 1; } return; } l2 = r2 = -1; if (a.second == 0) { l1 = 1, r1 = len2 - 1; } else if (a.second >= len2 - 1) { l1 = 0, r1 = a.second - 1; } else { l1 = 0, r1 = a.second - 1; l2 = a.second + 1, r2 = len2 - 1; } l1 += len1, r1 += len1; if (l2 != -1) { l2 += len1, r2 += len1; } } int cmp2(vector<pair<int, int>>& a, vector<pair<int, int>>& b, int p1 = 0, int p2 = 0) { if (p1 == a.size() && p2 < b.size()) { return -1; } if (p1 == a.size() && p2 == b.size()) { return 0; } if (p2 == b.size() && p1 < a.size()) { return 1; } if (p1 + 1 == a.size() && p2 + 1 == b.size() && a[0] == b[0]) { return 0; } if (p1 + 2 == a.size() && p2 + 2 == b.size() && a[0] == b[0] && a[1] == b[1]) { return 0; } if (sops.get(a[p1].first) != sops.get(b[p2].first)) { char c1 = sops.get(a[p1].first); char c2 = sops.get(b[p2].first); if (c1 < c2) { return -1; } return 1; } int lcp = sops.string_lcp( a[p1].first, b[p2].first, min(a[p1].second - a[p1].first + 1, b[p2].second - b[p2].first + 1)); lcp = min( lcp, min(a[p1].second - a[p1].first + 1, b[p2].second - b[p2].first + 1)); int nx = a[p1].first + lcp - 1, ny = b[p2].first + lcp - 1; if (nx >= a[p1].second) { ++p1; } else { a[p1].first = nx + 1; } if (ny >= b[p2].second) { ++p2; } else { b[p2].first = ny + 1; } return cmp2(a, b, p1, p2); } bool cmp(const pair<int, int>& a, const pair<int, int>& b) { int nlen1 = get_nlength(a); int nlen2 = get_nlength(b); if (nlen1 == 0 && nlen2 == 0) { if (a.first == u & b.first == v) { return true; } return false; } if (nlen1 == 0) { return true; } if (nlen2 == 0) { return false; } int l1, r1, l2, r2; fill_segs(l1, r1, l2, r2, a); int p1, q1, p2, q2; fill_segs(p1, q1, p2, q2, b); vector<pair<int, int>> na; vector<pair<int, int>> nb; na.push_back(make_pair(l1, r1)); if (l2 != -1) { na.push_back(make_pair(l2, r2)); } nb.push_back(make_pair(p1, q1)); if (p2 != -1) { nb.push_back(make_pair(p2, q2)); } int val = cmp2(na, nb); if (val == 0) { if (a.first == u && b.first == v) { return true; } return false; } return val == -1; } struct Node { Node() { left = right = nullptr; } int idxleft, idxright; Node* left; Node* right; }; int curorder[maxN]; int lenorder; void dfs(Node* root) { if (!root) { return; } if (root->left) { dfs(root->left); } for (int i = root->idxleft; i <= root->idxright; ++i) { curorder[lenorder] = i; ++lenorder; } if (root->right) { dfs(root->right); } } pair<int, int> order[2][maxN]; int clen[2]; void get_order(const string& s, int p) { int n = s.length(); Node* root = new Node(); Node* curnode = root; for (int i = 0; i < n;) { int cur = i; while (cur < n && s[cur] == s[i]) { ++cur; } curnode->idxleft = i, curnode->idxright = cur - 1; if (cur == n) { break; } if (s[i] < s[cur]) { Node* left = new Node(); curnode->left = left; curnode = curnode->left; } else { Node* right = new Node(); curnode->right = right; curnode = curnode->right; } i = cur; } lenorder = 0; dfs(root); int ps = n; for (int i = 0; i < n; ++i) { if (curorder[i] == n - 1) { ps = i + 1; break; } } vector<pair<int, int>> result; clen[p] = 0; for (int i = 0; i < ps; ++i) { order[p][clen[p]] = make_pair(v, curorder[i]); ++clen[p]; } order[p][clen[p]] = make_pair(v, n); ++clen[p]; for (int i = ps; i < n; ++i) { order[p][clen[p]] = make_pair(v, curorder[i]); ++clen[p]; } } int dp[2][maxN]; int dp2[2][maxN]; void gen() { cout << 10 << endl; for (int i = 0; i < 10; ++i) { for (int j = 0; j < 100000; ++j) { cout << char(rand() % 26 + a ); } cout << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; vector<string> s(n); for (int i = 0; i < n; ++i) { cin >> s[i]; } for (int i = 0; i <= s[0].length(); ++i) { dp[u][i] = 1; dp2[u][i] = 1; } sops = StringOps<num2>(s[0]); len1 = 0, len2 = s[0].length(); u = 1, v = 0; get_order(s[0], 0); swap(u, v); for (int i = 0; i + 1 < n; ++i) { string& s1 = s[i]; string& s2 = s[i + 1]; string nw = s1 + s2; len1 = s1.length(), len2 = s2.length(); sops = StringOps<num2>(nw); get_order(s[i + 1], v); int cadd = 0; int head1 = 0, head2 = 0; while (head1 < clen[u] || head2 < clen[v]) { if (head1 == clen[u]) { dp[v][order[v][head2].second] = cadd; ++head2; } else if (head2 == clen[v]) { break; } else { if (cmp(order[u][head1], order[v][head2])) { int nhead1 = head1; while (nhead1 < clen[u] && s1[order[u][nhead1].second] == s1[order[u][head1].second] && order[u][nhead1].second - order[u][head1].second == nhead1 - head1) { ++nhead1; } for (int j = head1; j < nhead1; ++j) { cadd += dp[u][order[u][j].second]; if (cadd >= MOD) { cadd -= MOD; } } head1 = nhead1; } else { int nhead2 = head2; while (nhead2 < clen[v] && s2[order[v][nhead2].second] == s2[order[v][head2].second] && order[v][nhead2].second - order[v][head2].second == nhead2 - head2) { ++nhead2; } for (int j = head2; j < nhead2; ++j) { dp[v][order[v][j].second] = cadd; } head2 = nhead2; } } } swap(u, v); } int res = 0; int res2 = 0; for (int i = 0; i <= s.back().length(); ++i) { res += dp[u][i]; if (res >= MOD) { res -= MOD; } res2 += dp2[u][i]; if (res2 >= MOD) { res2 -= MOD; } } cout << res << endl; cerr << (double)clock() / CLOCKS_PER_SEC << endl; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__EDFXBP_PP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXBP_PP_SYMBOL_V
|
// File: DEMUX1_4_DMS_TBV.v
// Generated by MyHDL 0.10
// Date: Sun Sep 23 18:24:21 2018
`timescale 1ns/10ps
module DEMUX1_4_DMS_TBV (
);
// myHDL -> testbench for module `DEMUX1_4_DMS`
reg x = 0;
wire y0;
wire y1;
reg s0 = 0;
reg s1 = 0;
wire y2;
wire y3;
wire [17:0] xTV;
wire [17:0] s0TV;
wire [17:0] s1TV;
wire DEMUX1_4_DMS0_0_s0_y2y3_WIRE;
wire DEMUX1_4_DMS0_0_s0_y0y1_WIRE;
assign xTV = 18'd87399;
assign s0TV = 18'd52982;
assign s1TV = 18'd16277;
always @(x, y0, s1, s0, y3, y2, y1) begin: DEMUX1_4_DMS_TBV_PRINT_DATA
$write("%h", x);
$write(" ");
$write("%h", s0);
$write(" ");
$write("%h", s1);
$write(" ");
$write("%h", y0);
$write(" ");
$write("%h", y1);
$write(" ");
$write("%h", y2);
$write(" ");
$write("%h", y3);
$write("\n");
end
assign DEMUX1_4_DMS0_0_s0_y0y1_WIRE = ((!s1) && x);
assign DEMUX1_4_DMS0_0_s0_y2y3_WIRE = (s1 && x);
assign y0 = ((!s0) && DEMUX1_4_DMS0_0_s0_y0y1_WIRE);
assign y1 = (s0 && DEMUX1_4_DMS0_0_s0_y0y1_WIRE);
assign y2 = ((!s0) && DEMUX1_4_DMS0_0_s0_y2y3_WIRE);
assign y3 = (s0 && DEMUX1_4_DMS0_0_s0_y2y3_WIRE);
initial begin: DEMUX1_4_DMS_TBV_STIMULES
integer i;
for (i=0; i<18; i=i+1) begin
x <= xTV[i];
s0 <= s0TV[i];
s1 <= s1TV[i];
# 1;
end
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_TB_V
`define SKY130_FD_SC_MS__A21BO_TB_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21bo.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ms__a21bo dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_BEHAVIORAL_V
|
//
`timescale 1ns/1ps
module test_afifo
();
parameter DEPTH = 8, ADDRESS_WIDTH = 3, WIDTH=8;
parameter clk_period = 2;
parameter half_period = 1;
reg CLK;
reg REN;
reg WEN;
reg RESET;
reg valid;
reg [WIDTH-1:0] Data_in [DEPTH-1:0];
wire [WIDTH-1:0] Data_out [DEPTH-1:0];
wire [DEPTH-1:0] Full_out;
wire [DEPTH-1:0] Empty_out;
MatrixInput #(.DEPTH(DEPTH),.ADDRESS_WIDTH(ADDRESS_WIDTH),.WIDTH(WIDTH)) DUT (
.CLK(CLK),.valid(valid),.REN(REN),.WEN(WEN),.RESET(RESET),
.Data_in(Data_in),.Data_out(Data_out),.Full_out(Full_out),.Empty_out(Empty_out));
always begin
#half_period
CLK = ~CLK;
end
initial begin
RESET = 1'b1;
valid = 1'b0;
REN = 1'b0;
WEN = 1'b0;
CLK = 1'b0;
$dumpfile("test.vcd") ;
$dumpvars;
#20 RESET=1'b0;
#clk_period
for (integer i=0;i<DEPTH;i++)
Data_in[i] = 8'haa;
writeMem();
#clk_period
for (integer i=0;i<DEPTH;i++)
Data_in[i] = 8'hbb;
writeMem();
#clk_period
#clk_period
#clk_period readMem();
#clk_period readMem();
#clk_period
#clk_period
#clk_period $finish;
end
task writeMem;
//input [WIDTH-1:0] wdata [DEPTH-1:0];
begin
WEN = 1;
//D = wdata;
#clk_period
WEN = 0;
end
endtask
task readMem;
begin
REN = 1;
valid = 1;
#clk_period
REN = 0;
valid = 0;
end
endtask
endmodule
|
//
// Copyright (c) 2014 Colin Rothwell
// Copyright (c) 2014 A. Theodore Markettos
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
// intermediary between Bluespec, which outputs an enable signal,
// and Megawizard's verilog, which doesn't have that input
module doubleMulWrapper (
clock,
dataa,
datab,
result,
dummy_enable);
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
input dummy_enable;
doubleMul doubleMul (
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isrange(int second, int first, int n, int m) { if (0 <= second && second < n && 0 <= first && first < m) return true; return false; } int dy[4] = {1, 0, -1, 0}, dx[4] = {0, 1, 0, -1}, ddy[8] = {1, 0, -1, 0, 1, 1, -1, -1}, ddx[8] = {0, 1, 0, -1, 1, -1, 1, -1}; const int MAX = 101010; long long int a[6], arr[MAX]; vector<pair<long long int, int> > v; vector<int> tmp; int num[MAX], start = 1; long long int seg[MAX * 4]; multiset<long long int> s[MAX]; long long int getn(int l, int r) { l += start; r += start; long long int ans = 0; while (l <= r) { if (l % 2) { ans = max(ans, seg[l]); l++; } if ((r % 2) == 0) { ans = max(ans, seg[r]); r--; } l /= 2; r /= 2; } return ans; } void upd(int first, long long int second) { first += start; seg[first] = second; for (int e = (first / 2); e >= 1; e /= 2) seg[e] = max(seg[e * 2], seg[e * 2 + 1]); } void del(int first) { long long int second = *s[first].begin(); s[first].erase(s[first].lower_bound(second)); second = *s[first].begin(); upd(first, second); } int main(void) { while (start < MAX) start *= 2; for (int e = 0; e < 6; e++) scanf( %lld , &a[e]); int n; scanf( %d , &n); for (int e = 0; e < n; e++) { long long int r; scanf( %lld , &r); for (int p = 0; p < 6; p++) { v.push_back(make_pair(r - a[p], e)); s[e].insert(r - a[p]); } } if (n == 1) return !printf( 0 ); for (int e = 0; e < n; e++) { long long int first = *s[e].begin(); upd(e, first); } sort(v.begin(), v.end()); memset(num, 0, sizeof(num)); long long int ans = 1e18, lx = 0; for (int e = 0; e < (int)v.size(); e++) { if (lx != v[e].first) { bool suc = false; for (int p = 0; p < (int)tmp.size(); p++) { num[tmp[p]]++; if (num[tmp[p]] == 6) { suc = true; break; } del(tmp[p]); } if (suc) break; tmp.clear(); } long long int vv = 0; if (0 <= v[e].second - 1) vv = max(vv, getn(0, v[e].second - 1)); if (v[e].second + 1 < n) vv = max(vv, getn(v[e].second + 1, n - 1)); ans = min(ans, vv - v[e].first); tmp.push_back(v[e].second); lx = v[e].first; } printf( %lld , ans); return 0; }
|
#include <bits/stdc++.h> using i64 = long long; using u64 = unsigned long long; using u32 = unsigned; int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); int n; std::cin >> n; std::vector<int> c0(n, 0); std::vector<int> c1(n, 0); for (int i = 0; i < n; i++) { std::cin >> c0[i] >> c1[i]; } std::vector<int> tmp{0}; for (int i = 0; i < n; i++) { tmp.emplace_back(c0[i]); tmp.emplace_back(c1[i]); } std::sort(tmp.begin(), tmp.end()); tmp.resize(std::unique(tmp.begin(), tmp.end()) - tmp.begin()); for (int i = 0; i < n; i++) { c0[i] = std::lower_bound(tmp.begin(), tmp.end(), c0[i]) - tmp.begin(); c1[i] = std::lower_bound(tmp.begin(), tmp.end(), c1[i]) - tmp.begin(); } std::vector<int> p(tmp.size(), 0); std::iota(p.begin(), p.end(), 0); auto find = [&](int x) { while (x != p[x]) { x = p[x] = p[p[x]]; } return x; }; int ans = 0; for (int i = 0; i < n; i++) { int x = c0[i]; int y = c1[i]; x = find(x); y = find(y); if (!x && !y) { std::cout << -1, exit(0); } else { if (x == y || !x || !y) { ans = std::max({ans, x, y}); p[x] = p[y] = 0; } else { ans = std::max(ans, std::min(x, y)); p[std::min(x, y)] = std::max(x, y); } } } std::cout << tmp[ans] << n ; return 0; }
|
//caution do not edit this file manually it is a template in tenjin format
`define Buff_size 32
////////////////////////////////////////////
#{MODULE_TEXT}
///////////////////////////////////////////
input clk; // 50MHz
input rst_n; //reset, neg edge.
input rs232_rx; // RS232 rec
//output rs232_tx; // RS232 transfer
/////////////////////////////////////////
#{INOUT_TEXT}
////////////////////////////////////////
output led; // debug led
// state control
parameter IDLE = 3'b000;
parameter S1 = 3'b001;
parameter WAIT = 3'b010;
parameter SAVE = 3'b100;
// commond reg
parameter A=8'h41 ;
parameter B=8'h42 ;
parameter C=8'h43 ;
parameter D=8'h44 ;
parameter E=8'h45 ;
parameter F=8'h46 ;
parameter G=8'h47 ;
parameter H=8'h48 ;
parameter I=8'h49 ;
parameter J=8'h4a ;
parameter K=8'h4b ;
parameter L=8'h4c ;
parameter M=8'h4d ;
parameter N=8'h4e ;
parameter O=8'h4f ;
parameter P=8'h50 ;
parameter Q=8'h51 ;
parameter R=8'h52 ;
parameter S=8'h53 ;
parameter T=8'h54 ;
parameter U=8'h55 ;
parameter V=8'h56 ;
parameter W=8'h57 ;
parameter X=8'h58 ;
parameter Y=8'h59 ;
parameter Z=8'h5a ;
parameter Z0=8'h30 ;
parameter I1=8'h31 ;
parameter II=8'h32 ;
parameter III=8'h33 ;
parameter IV=8'h34 ;
parameter V5=8'h35 ;
parameter VI=8'h36 ;
parameter VII=8'h37 ;
parameter VIII=8'h38 ;
parameter VIIII=8'h39 ;
//definition of inputs/outputs
wire test;
wire Flag; // signal the uart has data
wire rs232_rx;
wire clk,rst_n;
wire bps_start; // start receive
wire bps_start_t; // start tranmit
wire clk_bps; // uart bps
wire clk_bps_t; // uart bps
wire[7:0] rx_data; // receive data to parser
wire rx_int; // receive interrupt
wire rx_error;
wire tx_error;
wire rx_complete;
wire tx_complete;
wire[7:0] tx_data;
wire rs232_tx;
#{WIRE_TEXT}
////////////////////////////////////////////////////////////////////////////////////////////////
//debug led
reg led;
reg cmd_red;
// settings for log register
reg [`Buff_size-1:0] Buff_temp;
reg [`Buff_size-9:0] Rx_cmd;
reg [2:0] Current, Next;
reg Flag_temp;
//build in module enable
reg linkBIM;
reg capture_rst;
#{REG_TEXT}
#{ASSIGN_TEXT}
#{IP_TEXT}
/////////////////////////////////////////////////////////////////////////////////////////////////////
reg flag_reg;
always @ (negedge bps_start or negedge rst_n)
begin
if (!rst_n)
flag_reg <= 1'b0;
else if (!bps_start)
flag_reg <= ~flag_reg;
end
assign Flag = flag_reg;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
Current <= IDLE;
else
Current <= Next;
end
// the state machine for receive data bytes
always @ (*)
begin
Next = IDLE;
case (Current)
IDLE:
if (rx_data == 8'h24) //$
Next = S1;
else
Next = IDLE;
S1:
if (Flag_temp != Flag)
begin
if (rx_data != 8'h0d) //\n
Next = S1;
else
Next = SAVE;
end
else
Next = WAIT;
WAIT:
if (Flag_temp!=Flag)
begin
if (rx_data != 8'h0d)
Next = S1;
else
Next = SAVE;
end
else
Next = WAIT;
default: Next = IDLE;
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
Flag_temp <= 1'b0;
end
else
begin
Flag_temp <= Flag;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
Buff_temp <= `Buff_size'b0;
Rx_cmd <= `Buff_size'b0;
cmd_red <= 1'b0;
end
else
begin
case (Current)
IDLE:
begin
Buff_temp <= `Buff_size'b0;
end
S1:
begin
cmd_red <= 1'b1;
Buff_temp <= {{Buff_temp[`Buff_size - 9 : 0]}, rx_data};
end
WAIT:
begin
Buff_temp <= Buff_temp;
end
SAVE:
begin
Rx_cmd <= Buff_temp[`Buff_size - 9 : 0];
Buff_temp <= `Buff_size'b0;
cmd_red <= 1'b0;
end
default:
begin
end
endcase
end
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
//////////////////add link here////////////////
#{INIT_REG_TEXT}
///////////////////////////////////////////////
led <= 1'b0; // for debug led
linkBIM <= 1'b1;
end
else if(cmd_red) begin
#{RST_REG_TEXT}
led <= 1'b0;
capture_rst <= 1'b0;
end
else
begin
case(Rx_cmd)
///////////////////add case here/////////////
#{CMD_CASE_TEXT}
/////////////////////////////////////////////
{R,S,T}: //RESET
begin
#{RST_REG_TEXT}
led <= 1'b0;
linkBIM <= 1'b1;
capture_rst <= 1'b0;
end
default:
begin
#{DFT_REG_TEXT}
led <= 1'b0;
linkBIM <= 1'b1;
capture_rst <= 1'b0;
end
endcase
end
end
/////////////////////////////////////////////////////////////
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate various module formats
module foo(a);
output a;
wire a = 1'b1 ;
endmodule
module main;
wire b;
foo foo1 (.a());
foo foo2 (.a(b));
initial
if(!b)
$display("FAILED - 3.12B - Module with output only failed");
else
$display("PASSED");
endmodule // main
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 21:13:46 07/24/2014
// Design Name: EMU Device
// Module Name: DigiMic_Interface
//////////////////////////////////////////////////////////////////////////////////
module DigiMic_Interface(
CLK,
DesiredDMMemoryLocationToRead,
DMLocationWritingTo,
SampleDelayZero,
DesiredDMInterfaceOutput,
DMCLK,
DMDATA1,
DMDATA2,
DMDATA3,
DMDATA4,
DesiredDM
);
input CLK, DMDATA1, DMDATA2, DMDATA3, DMDATA4;
input [1:0] DesiredDM;
input [9:0] DesiredDMMemoryLocationToRead; //Selects location from chosen array.
output DMCLK, SampleDelayZero;
output [9:0] DMLocationWritingTo; //Beware of simultaneous write + read.
output [8:0] DesiredDMInterfaceOutput; //The value from the chosen array and location.
reg [8:0] DMAdder1, DMAdder2, DMAdder3, DMAdder4;
reg [9:0] DMLocationWritingTo;
reg [8:0] DesiredDMInterfaceOutput1, DesiredDMInterfaceOutput2, DesiredDMInterfaceOutput3, DesiredDMInterfaceOutput4;
reg [12:0] SampleDelayCount;
wire DMCLK, DMDATA1, DMDATA2, DMDATA3, DMDATA4, SampleDelayZero;
wire [1:0] DesiredDM;
reg [8:0] DesiredDMInterfaceOutput;
(* RAM_STYLE="{auto | block | block_power1 | block_power2}" *)
reg [8:0] StoredDMValues1 [1023:0]; //512*2 = 1024
(* RAM_STYLE="{auto | block | block_power1 | block_power2}" *)
reg [8:0] StoredDMValues2 [1023:0]; //512*2 = 1024
(* RAM_STYLE="{auto | block | block_power1 | block_power2}" *)
reg [8:0] StoredDMValues3 [1023:0]; //512*2 = 1024
(* RAM_STYLE="{auto | block | block_power1 | block_power2}" *)
reg [8:0] StoredDMValues4 [1023:0]; //512*2 = 1024
/* ////////////////////////////////////////////////////////////
Main Code
*/ ////////////////////////////////////////////////////////////
assign DMCLK = SampleDelayCount[3];
//Divides the clock by 16, giving a result that syncs with the SampleDelayCount.
//Every sampling interval, this will send 8,192 / 16, or 512 clock signals to the DigiMic.
// SampleDelayCount 50000000 / 16........./512 .... Should be 512 * 16 = 8192, or 13 bits gives 12:0
assign SampleDelayZero = ~| SampleDelayCount; // States that a single data point has been made, ie all 512 bits have been counted
always @(posedge CLK)
begin
SampleDelayCount <= SampleDelayCount + 1; // Out of a maximum of 8,191.
end
always @(posedge CLK)
begin
if (SampleDelayZero)
begin
DMLocationWritingTo <= DMLocationWritingTo + 1;
end
end
assign DMRead = (SampleDelayCount[3] && SampleDelayCount[2] && SampleDelayCount[1] && !SampleDelayCount[0]);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge CLK)
begin
if (DMRead || SampleDelayZero)
begin
if (SampleDelayZero)
begin
DMAdder1 <= 0;
end
else
begin
DMAdder1 <= DMAdder1 + DMDATA1;
end
end
end
always @(posedge CLK)
begin
if (DMRead || SampleDelayZero)
begin
if (SampleDelayZero)
begin
DMAdder2 <= 0;
end
else
begin
DMAdder2 <= DMAdder2 + DMDATA2;
end
end
end
always @(posedge CLK)
begin
if (DMRead || SampleDelayZero)
begin
if (SampleDelayZero)
begin
DMAdder3 <= 0;
end
else
begin
DMAdder3 <= DMAdder3 + DMDATA3;
end
end
end
always @(posedge CLK)
begin
if (DMRead || SampleDelayZero)
begin
if (SampleDelayZero)
begin
DMAdder4 <= 0;
end
else
begin
DMAdder4 <= DMAdder4 + DMDATA4;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge CLK)
begin
if (SampleDelayZero)
begin
StoredDMValues1[DMLocationWritingTo] <= DMAdder1[8:0];
end
DesiredDMInterfaceOutput1[8:0] <= StoredDMValues1[DesiredDMMemoryLocationToRead];
end
always @(posedge CLK)
begin
if (SampleDelayZero)
begin
StoredDMValues2[DMLocationWritingTo] <= DMAdder2[8:0];
end
DesiredDMInterfaceOutput2[8:0] <= StoredDMValues2[DesiredDMMemoryLocationToRead];
end
always @(posedge CLK)
begin
if (SampleDelayZero)
begin
StoredDMValues3[DMLocationWritingTo] <= DMAdder3[8:0];
end
DesiredDMInterfaceOutput3[8:0] <= StoredDMValues3[DesiredDMMemoryLocationToRead];
end
always @(posedge CLK)
begin
if (SampleDelayZero)
begin
StoredDMValues4[DMLocationWritingTo] <= DMAdder4[8:0];
end
DesiredDMInterfaceOutput4[8:0] <= StoredDMValues4[DesiredDMMemoryLocationToRead];
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(DesiredDM or DesiredDMInterfaceOutput1 or DesiredDMInterfaceOutput2 or DesiredDMInterfaceOutput3 or DesiredDMInterfaceOutput4)
begin
case (DesiredDM)
2'b00 : begin
DesiredDMInterfaceOutput = DesiredDMInterfaceOutput1;
end
2'b01 : begin
DesiredDMInterfaceOutput = DesiredDMInterfaceOutput2;
end
2'b10 : begin
DesiredDMInterfaceOutput = DesiredDMInterfaceOutput3;
end
2'b11 : begin
DesiredDMInterfaceOutput = DesiredDMInterfaceOutput4;
end
default: begin
DesiredDMInterfaceOutput = 9'b0000_0000_0;
end
endcase
end
/*
***********************************************************************
* *
* DMRead > **** *
* *
* *
* DMMIC > _________________________________ *
* ________________________________ *
* *
* | | | | | | | | | | | | | | | | *
* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ^ *
* *
* **Each number is the positive edge of a clock pulse. *
* *
***********************************************************************
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; const bool debug = false; const int maxn = 1002003; const long long magic = 1000 * 1000 * 1000 + 7; int n, k; long long aa[maxn]; struct RMQ { int l, r; RMQ *left, *right; long long res; int resIndex; }; RMQ* build(long long* vs, int l, int r) { RMQ* res = new RMQ(); res->l = l; res->r = r; if (r - l >= 2) { int m = (l + r) / 2; res->left = build(vs, l, m); res->right = build(vs, m, r); if (res->left->res >= res->right->res) { res->res = res->left->res; res->resIndex = res->left->resIndex; } else { res->res = res->right->res; res->resIndex = res->right->resIndex; } } else { res->left = nullptr; res->right = nullptr; res->res = vs[l]; res->resIndex = l; } return res; } pair<long long, int> rmqGet(RMQ* q, int l, int r) { if (q->r <= l || r <= q->l) return make_pair(-100, -1); if (l <= q->l && q->r <= r) return make_pair(q->res, q->resIndex); auto [res1, res1index] = rmqGet(q->left, l, r); auto [res2, res2index] = rmqGet(q->right, l, r); if (res1 >= res2) return make_pair(res1, res1index); else return make_pair(res2, res2index); } int ls[maxn]; int rs[maxn]; RMQ* rmq; void findLR(int l, int r) { if (debug) cout << findLR: << l << << r << endl; if (r - l < 2) return; auto [res, resIndex] = rmqGet(rmq, l + 1, r); if (debug) cout << rmqGet: << (l + 1) << << r << << res << << resIndex << endl; ls[resIndex] = l; rs[resIndex] = r; findLR(l, resIndex); findLR(resIndex, r); } long long countLen(int len) { if (len < k) return 0; int rest = len - k; long long count = rest / (k - 1); long long res = (len + 1) * (count + 1) - (count + 1) * (k + k + count * (k - 1)) / 2; return res; } long long countIndex(int i) { int len = rs[i] - (ls[i] + 1); long long res = countLen(len) - countLen(i - (ls[i] + 1)) - countLen(rs[i] - (i + 1)); if (debug) cout << countIndex: << i << << res << endl; return res; } int main() { ios::sync_with_stdio(false); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> aa[i]; aa[0] = aa[n + 1] = 1200ll * 1000 * 1000; rmq = build(aa, 0, n + 2); findLR(0, n + 1); if (debug) for (int i = 1; i <= n; i++) cout << ls[i] << << rs[i] << endl; long long res = 0; for (int i = 1; i <= n; i++) { long long c = countIndex(i) % magic; res = (res + aa[i] * c) % magic; } cout << res << endl; if (debug) for (int i = 0; i <= 20; i++) cout << len: << i << : << countLen(i) << endl; return 0; }
|
// TOOL: vlog2tf
// DATE: Wed May 28 10:38:34 2014
// TITLE: Lattice Semiconductor Corporation
// MODULE: Section5_Top
// DESIGN: Section5_Top
// FILENAME: Section5_Top_tf.v
// PROJECT: Unknown
// VERSION: 2.0
// This file is auto generated by the Diamond
`timescale 1 ms / 1 ms
// Define Module for Test Fixture
module Section5_Top_tf();
// Inputs
reg DigitalLDir;
reg DigitalRDir;
reg reset_n;
// Outputs
wire [3:0] outputs;
// Bidirs
// Instantiate the UUT
// Please check and add your parameters manually
Section5_Top UUT (
.DigitalLDir(DigitalLDir),
.DigitalRDir(DigitalRDir),
.reset_n(reset_n),
.outputs(outputs)
);
// Initialize Inputs
// You can add your stimulus here
initial begin
DigitalLDir = 1; DigitalRDir = 1; reset_n = 1;
#1 DigitalLDir = 1; DigitalRDir = 1; reset_n = 0;
#1 DigitalLDir = 1; DigitalRDir = 1; reset_n = 1;
#100 DigitalLDir = 1; DigitalRDir = 0; reset_n = 1;
#500 DigitalLDir = 1; DigitalRDir = 1; reset_n = 1;
end
endmodule // Section5_Top_tf
|
/*
main function:
1)allocate cpuid for pkt by the key
2)only achive round robin mode in this version
tips: all fifo are showahead mode
*/
`timescale 1 ps / 1 ps
module DISPATHER_INPUT(
input clk,
input reset,
//--------------------------------CPUID Manage Module-------------------------
input [4:0] in_cpuid,//id of cpu thread which pkt would be send to
input in_cpuid_ack,
input in_cpuid_valid,
output reg out_cpuid_ctl,
output reg [4:0] out_cpuid_key,
//--------------------------------INGRESS Module<Data Input>-------------------------
input in_ingress_pkt_wr,
input [133:0] in_ingress_pkt,
input in_ingress_valid_wr,
input in_ingress_valid,
output out_ingress_pkt_almostfull,
//--------------------------------OUTPUT Module<Data Output Path 1>-------------------------
output reg out_output_pkt_wr,
output reg [133:0] out_output_pkt,
output reg out_output_valid_wr,
output reg out_output_valid,
input in_output_pkt_almostfull,
//--------------------------------PPC_SUBSYS Module<Data Output Path 2>-------------------------
output reg out_ppc_pkt_wr,
output reg [133:0] out_ppc_pkt,
output reg out_ppc_valid_wr,
output reg out_ppc_valid,
input in_ppc_pkt_almostfull
);
wire in_ingress_valid_q;
wire in_ingress_valid_empty;
reg out_ingress_valid_rd;
wire [7:0] out_ingress_pkt_usedw;
wire out_ingress_pkt_empty;
assign out_ingress_pkt_almostfull = out_ingress_pkt_usedw[7];//lxj0107
reg out_ingress_pkt_rd;
wire [133:0]in_ingress_pkt_q;
reg [2:0] current_state;
parameter idle_s = 3'd0,
wait_s = 3'd1,
send_output_s = 3'd2,
send_ppc_s = 3'd3,
discard_s = 3'd4;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_cpuid_ctl<=1'b0;
out_cpuid_key<=5'b0;
out_output_pkt_wr<=1'b0;
out_output_pkt<=134'b0;
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_ppc_pkt_wr<=1'b0;
out_ppc_pkt<=134'b0;
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ingress_valid_rd<=1'b0;
out_ingress_pkt_rd<=1'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
out_output_pkt_wr<=1'b0;
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_ppc_pkt_wr<=1'b0;
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ingress_pkt_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
if((out_ingress_pkt_empty == 1'b0)&&(in_ingress_pkt_q[133:132]==2'b01)) begin
out_cpuid_ctl<=1'b1;
if(in_ingress_pkt_q[111:110]==2'b0)//slot_id
out_cpuid_key<=in_ingress_pkt_q[62:58];//inport
else
out_cpuid_key<=in_ingress_pkt_q[62:58]+5'd5;
current_state <= wait_s;
end
else begin
out_cpuid_ctl<=1'b0;
current_state <= idle_s;
end
end
wait_s: begin
out_cpuid_ctl<=1'b1;
if((in_cpuid_ack==1'b1) &&(in_ingress_valid_empty==1'b0)) begin
if((in_ingress_valid_q == 1'b1)&&(in_cpuid_valid==1'b1)) begin//pkt is valid && the sum of pkt which mount in it's cpuid have too more ,so discard this pkt
if((in_ingress_pkt_q[124]==1'b0)&&(in_output_pkt_almostfull==1'b0))begin//send to OUTPUT Module && OUTPUT Moudle can receive this pkt
out_ingress_pkt_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
current_state <= send_output_s;
end
else if((in_ingress_pkt_q[124]==1'b1)&&(in_ppc_pkt_almostfull==1'b0)) begin //send to PPC Module && PPC Moudle can receive this pkt
out_ingress_pkt_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
current_state <= send_ppc_s;
end
else begin
out_ingress_pkt_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
current_state <= wait_s;
end
end
else begin
out_ingress_pkt_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
current_state <= discard_s;
end
end
else begin
out_ingress_pkt_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
current_state <= wait_s;
end
end
send_output_s: begin
out_cpuid_ctl<=1'b0;
out_ingress_valid_rd<=1'b0;
out_output_pkt_wr<=1'b1;
out_output_pkt<=in_ingress_pkt_q;
if(in_ingress_pkt_q[133:132]==2'b01) begin
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_output_pkt[55:47]<={4'b0,in_cpuid};
out_ingress_pkt_rd<=1'b1;
current_state <= send_output_s;
end
else if(in_ingress_pkt_q[133:132]==2'b10) begin
out_output_valid_wr<=1'b1;
out_output_valid<=1'b1;
out_ingress_pkt_rd<=1'b0;
current_state <= idle_s;
end
else begin
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_ingress_pkt_rd<=1'b1;
current_state <= send_output_s;
end
end
send_ppc_s: begin
out_cpuid_ctl<=1'b0;
out_ingress_valid_rd<=1'b0;
out_output_pkt_wr<=1'b1;
out_ppc_pkt<=in_ingress_pkt_q;
if(in_ingress_pkt_q[133:132]==2'b01) begin
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ppc_pkt[55:47]<={4'b0,in_cpuid};
out_ingress_pkt_rd<=1'b1;
current_state <= send_ppc_s;
end
else if(in_ingress_pkt_q[133:132]==2'b10) begin
out_ppc_valid_wr<=1'b1;
out_ppc_valid<=1'b1;
out_ingress_pkt_rd<=1'b0;
current_state <= idle_s;
end
else begin
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ingress_pkt_rd<=1'b1;
current_state <= send_ppc_s;
end
end
discard_s: begin
out_ingress_valid_rd<=1'b0;
if(in_ingress_pkt_q[133:132]==2'b10) begin
out_ingress_pkt_rd<=1'b0;
current_state <= idle_s;
end
else begin
out_ingress_pkt_rd<=1'b1;
current_state <= discard_s;
end
end
default: begin
out_output_pkt_wr<=1'b0;
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_ppc_pkt_wr<=1'b0;
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ingress_pkt_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_cpuid_ctl<=1'b0;
current_state <= idle_s;
end
endcase
end
end
//--------------------------------From INGRESS Module-------------------------
fifo_64_1 FIFO_VALID_INGRESS (
.aclr(!reset),
.data(in_ingress_valid),
.clock(clk),
.rdreq(out_ingress_valid_rd),
.wrreq(in_ingress_valid_wr),
.q(in_ingress_valid_q),
.empty(in_ingress_valid_empty)
);
fifo_256_134 FIFO_PKT_INGRESS (
.aclr(!reset),
.data(in_ingress_pkt),
.clock(clk),
.rdreq(out_ingress_pkt_rd),
.wrreq(in_ingress_pkt_wr),
.q(in_ingress_pkt_q),
.usedw(out_ingress_pkt_usedw),
.empty(out_ingress_pkt_empty)
);
endmodule
|
module ringbuffer #(parameter AW = 8, DW = 48)
(
input reset,
input clock,
input read_clock_enable,
input write_clock_enable,
output [DW-1:0] read_data,
input [DW-1:0] write_data,
output reg empty,
output reg overflow);
reg [AW-1:0] next_write_addr;
reg [AW-1:0] read_addr;
reg [AW-1:0] write_addr;
wire mem_read_clock_enable;
wire mem_write_clock_enable;
assign empty = read_addr == write_addr;
assign overflow = next_write_addr == read_addr;
always @(negedge reset or negedge clock) begin
if (~reset) begin
write_addr <= 0;
next_write_addr <= 1;
end
else
if (write_clock_enable)
if (~overflow) begin
write_addr <= write_addr + 1;
next_write_addr <= next_write_addr + 1;
end
end
always @(negedge reset or negedge clock) begin
if (~reset) begin
read_addr <= 0;
end
else begin
if (read_clock_enable)
if (~empty)
read_addr <= read_addr + 1;
end
end
assign mem_read_clock_enable = ~empty & read_clock_enable;
assign mem_write_clock_enable = ~overflow & write_clock_enable;
buffer #(.AW(AW), .DW(DW))
MEM (
.clock(clock),
.write_clock_enable(mem_write_clock_enable),
.write_data(write_data),
.write_addr(write_addr),
.read_clock_enable(mem_read_clock_enable),
.read_data(read_data),
.read_addr(read_addr));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int OO = 0x3f3f3f3f, N = 1e5 + 5, mod = 1e9 + 9; int n, k, indx[10], ans = OO; char arr[10][10]; int num(int r) { int ret = 0; for (int i = 0; i < k; ++i) { ret = ret * 10 + (arr[r][indx[i]] - 0 ); } return ret; } int main() { cin >> n >> k; for (int i = 0; i < k; ++i) indx[i] = i; for (int i = 0; i < n; ++i) scanf( %s , arr[i]); do { int mn = OO, mx = 0; for (int i = 0; i < n; ++i) { mn = min(mn, num(i)); mx = max(mx, num(i)); } ans = min(ans, mx - mn); } while (next_permutation(indx, indx + k)); cout << ans; return 0; }
|
#include <iostream> #include <vector> #include <string> #include <cstring> #include <cmath> #include <climits> #include <algorithm> #include <map> #include <stack> #include <unordered_map> #include <set> #include <unordered_set> #include <utility> #include <iomanip> using namespace std; typedef long long int ll; ll pw(ll a, ll b, ll m){ ll ans=1; while(b>0){ if(b&1) ans=(ans*a)%m; a=(a*a)%m; b>>=1; } return ans; } ll gcd(ll a,ll b){ if(a==0) return b; return gcd(b % a , a); } bool comp(const pair<int,int> &a,const pair<int,int> &b){ return a.second>b.second; } ll n,m; set<ll> has; vector<ll> input; void solve(ll l,ll r){ ll sum=0; for(ll i=l;i<r+1;i++){ sum+=input[i]; } has.insert(sum); ll mid=(input[l]+input[r])/2; ll pos=-1; for(ll i=l;i<r+1;i++){ if(input[i]<=mid){ pos=i; } else{ break; } } if(pos==-1 || pos==r) return; solve(l,pos); solve(pos+1,r); } void randomevent(){ ll right=n; while(right>=0 && input[right-1]==right){ right--; } double f=(right>0) ? 1:0; for(ll i=0;i<m;i++){ ll r;cin>>r; double p;cin>>p; if(r>=right){ f*=(1-p); } } cout<<fixed<<setprecision(12)<<(1-f)<<endl; } int main(){ #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif int t;cin>>t; while(t--){ cin>>n>>m; for(ll i=0;i<n;i++){ ll p;cin>>p; input.push_back(p); } randomevent(); input.clear(); } }
|
#include <bits/stdc++.h> using namespace std; const unsigned long long Mode = 1e9 + 7; void Modulo(unsigned long long &x) { x = ((x % Mode + Mode) % Mode); } unsigned long long Pow(unsigned long long x, unsigned long long y) { unsigned long long res = 1; for (unsigned long long i = 0; (1ULL << i) <= y; i++, x *= x, Modulo(x)) if (y & (1ULL << i)) res *= x, Modulo(res); return res; } int main() { unsigned long long n, ans = 1, D = 1; cin >> n; D = n; for (unsigned long long i = 2ULL * n - 1; i > 0; i--) ans *= i, Modulo(ans); for (unsigned long long i = 1; i <= n - 1; i++) D *= i * i, Modulo(D); ans *= Pow(D, Mode - 2); ans *= 2ULL; Modulo(ans); ans -= n; Modulo(ans); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int maxn = 2 * 1e5; char s[maxn]; int n; int l, r; int is_pal(int l, int r) { for (int i = l; i <= (r + l) / 2; i++) { if (s[i] != s[r - (i - l)]) return 0; } return 1; } int main() { cin >> (s + 1); r = strlen(s + 1); while (is_pal(1, r) && r % 2 == 0 && r) { r /= 2; } if (!is_pal(1, r)) { cout << 1 << endl; } else { r = strlen(s + 1); for (int i = 1; i <= r / 2; i++) { if (!is_pal(1, i)) { cout << 2 << endl; return 0; } } cout << Impossible << endl; } return 0; }
|
#include <bits/stdc++.h> #pragma GCC target( avx,tune=native ) using namespace std; template <class T> ostream &operator<<(ostream &os, vector<T> V) { os << [ ; for (auto const &vv : V) os << vv << , ; os << ] ; return os; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { os << ( << P.first << , << P.second << ) ; return os; } template <typename T> inline void print_128(T num) { if (!num) return; print_128(num / 10); cout.put((num % 10) + 0 ); } inline int fstoi(const string &str) { auto it = str.begin(); bool neg = 0; int num = 0; if (*it == - ) neg = 1; else num = *it - 0 ; ++it; while (it < str.end()) num = num * 10 + (*it++ - 0 ); if (neg) num *= -1; return num; } inline void getch(char &x) { while (x = getchar_unlocked(), x < 33) { ; } } inline void getstr(string &str) { str.clear(); char cur; while (cur = getchar_unlocked(), cur < 33) { ; } while (cur > 32) { str += cur; cur = getchar_unlocked(); } } template <typename... Args> inline void getstr(string &str, Args &...arg) { str.clear(); char cur; while (cur = getchar_unlocked(), cur < 33) { ; } while (cur > 32) { str += cur; cur = getchar_unlocked(); } getstr(arg...); } template <typename T> inline bool sc(T &num) { bool neg = 0; int c; num = 0; while (c = getchar_unlocked(), c < 33) { if (c == EOF) return false; } if (c == - ) { neg = 1; c = getchar_unlocked(); } for (; c > 47; c = getchar_unlocked()) num = num * 10 + c - 48; if (neg) num *= -1; return true; } template <typename T, typename... Args> inline void sc(T &num, Args &...args) { bool neg = 0; int c; num = 0; while (c = getchar_unlocked(), c < 33) { ; } if (c == - ) { neg = 1; c = getchar_unlocked(); } for (; c > 47; c = getchar_unlocked()) num = num * 10 + c - 48; if (neg) num *= -1; sc(args...); } template <typename T> inline T mod(T i, T n) { return (i % n + n) % n; } inline void chkmax(int &a, const int &b) { if (b > a) a = b; } inline void chkmin(int &a, const int &b) { if (b < a) a = b; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, l, r, k, t; int posa[100001]; int posb[100001]; memset(posa, 127, sizeof posa); memset(posb, 127, sizeof posb); sc(n); while (n--) { sc(t, l, r); --r; if (t == 1) { sc(k); if (k > 0) { int count = r - l + 1; int n = (count + 7) >> 3; int i = l; switch (count % 8) { case 0: do { chkmin(posa[i], k); ++i; case 7: chkmin(posa[i], k); ++i; case 6: chkmin(posa[i], k); ++i; case 5: chkmin(posa[i], k); ++i; case 4: chkmin(posa[i], k); ++i; case 3: chkmin(posa[i], k); ++i; case 2: chkmin(posa[i], k); ++i; case 1: chkmin(posa[i], k); ++i; } while (--n > 0); } } else { k = -k; int count = r - l + 1; int n = (count + 7) >> 3; int i = l; switch (count % 8) { case 0: do { chkmin(posb[i], k); ++i; case 7: chkmin(posb[i], k); ++i; case 6: chkmin(posb[i], k); ++i; case 5: chkmin(posb[i], k); ++i; case 4: chkmin(posb[i], k); ++i; case 3: chkmin(posb[i], k); ++i; case 2: chkmin(posb[i], k); ++i; case 1: chkmin(posb[i], k); ++i; } while (--n > 0); } } } else { long long ans = 0; int count = r - l + 1; int i = l; int n = (count + 7) >> 3; switch (count % 8) { case 0: do { if (posa[i] < 0x7F7F7F7F && posb[i] < 0x7F7F7F7F) ans += posa[i] + posb[i]; ++i; case 7: if (posa[i] < 0x7F7F7F7F && posb[i] < 0x7F7F7F7F) ans += posa[i] + posb[i]; ++i; case 6: if (posa[i] < 0x7F7F7F7F && posb[i] < 0x7F7F7F7F) ans += posa[i] + posb[i]; ++i; case 5: if (posa[i] < 0x7F7F7F7F && posb[i] < 0x7F7F7F7F) ans += posa[i] + posb[i]; ++i; case 4: if (posa[i] < 0x7F7F7F7F && posb[i] < 0x7F7F7F7F) ans += posa[i] + posb[i]; ++i; case 3: if (posa[i] < 0x7F7F7F7F && posb[i] < 0x7F7F7F7F) ans += posa[i] + posb[i]; ++i; case 2: if (posa[i] < 0x7F7F7F7F && posb[i] < 0x7F7F7F7F) ans += posa[i] + posb[i]; ++i; case 1: if (posa[i] < 0x7F7F7F7F && posb[i] < 0x7F7F7F7F) ans += posa[i] + posb[i]; ++i; } while (--n > 0); } cout << ans << n ; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_HD__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_hd__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_MUX_4TO2_TB_V
|
#include <bits/stdc++.h> using namespace std; long long int con = 0; vector<pair<long long int, long long int> > v; long long int t[5000][5001]; vector<vector<pair<long long int, long long int> > > ans(5001); bool istrue[5001]; vector<long long int> a[5001]; long long int dis[5001]; int n; int ppp = 0; queue<int> q; void bfs(int src) { q.push(src); istrue[src] = true; dis[src] = 0; while (!q.empty()) { int p = q.front(); q.pop(); ans[con].push_back({(dis[p] + 1) % 2, p}); for (auto u : a[p]) { if (!istrue[u]) { dis[u] = dis[p] + 1; if (dis[u] % 2) v[con].second++; else v[con].first++; istrue[u] = true; q.push(u); } else { if (dis[u] % 2 == dis[p] % 2) { cout << NO << n ; ppp = 1; return; } } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tt = 1; while (tt--) { long long int m; cin >> n >> m; long long int n1, n2, n3; cin >> n1 >> n2 >> n3; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; a[x].push_back(y); a[y].push_back(x); } for (int i = 1; i <= n; i++) { if (!istrue[i]) { v.push_back({1, 0}); bfs(i); con++; } if (ppp == 1) return 0; } memset(t, -1, sizeof(t)); if (v[0].first <= n2) t[0][v[0].first] = 0; if (v[0].second <= n2) t[0][v[0].second] = 0; for (int i = 1; i <= (long long int)v.size() - 1; i++) { for (int j = 0; j < n2 + 1; j++) { long long int vv = j - v[i].first; if (vv >= 0 && t[i - 1][vv] != -1) t[i][j] = vv; vv = j - v[i].second; if (vv >= 0 && t[i - 1][vv] != -1) t[i][j] = vv; } } char ss[n + 1]; if (t[(long long int)v.size() - 1][n2] == -1) cout << NO << n ; else { cout << YES << n ; long long int i = (long long int)v.size() - 1, ind = n2; while (i != -1) { long long int pp = ind - t[i][ind], kk = 0; if (v[i].first == pp) kk = 1; for (auto u : ans[i]) { if (u.first == kk) ss[u.second] = 2 ; else ss[u.second] = 1 ; } ind = t[i][ind]; i--; } for (int j = 1; j <= n; j++) { if (ss[j] == 1 ) { if (n1 == 0) ss[j] = 3 ; else n1--; } cout << ss[j]; } cout << n ; } } return 0; }
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* XGMII control/data deinterleave
*/
module xgmii_deinterleave
(
input wire [72:0] input_xgmii_dc,
output wire [63:0] output_xgmii_d,
output wire [7:0] output_xgmii_c
);
assign output_xgmii_d[7:0] = input_xgmii_dc[7:0];
assign output_xgmii_c[0] = input_xgmii_dc[8];
assign output_xgmii_d[15:8] = input_xgmii_dc[16:9];
assign output_xgmii_c[1] = input_xgmii_dc[17];
assign output_xgmii_d[23:16] = input_xgmii_dc[25:18];
assign output_xgmii_c[2] = input_xgmii_dc[26];
assign output_xgmii_d[31:24] = input_xgmii_dc[34:27];
assign output_xgmii_c[3] = input_xgmii_dc[35];
assign output_xgmii_d[39:32] = input_xgmii_dc[43:36];
assign output_xgmii_c[4] = input_xgmii_dc[44];
assign output_xgmii_d[47:40] = input_xgmii_dc[52:45];
assign output_xgmii_c[5] = input_xgmii_dc[53];
assign output_xgmii_d[55:48] = input_xgmii_dc[61:54];
assign output_xgmii_c[6] = input_xgmii_dc[62];
assign output_xgmii_d[63:56] = input_xgmii_dc[70:63];
assign output_xgmii_c[7] = input_xgmii_dc[71];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mn = 2010; long long a[mn], b[mn]; int main() { int n, k; long long p; scanf( %d %d %lld , &n, &k, &p); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); for (int i = 1; i <= k; i++) scanf( %lld , &b[i]); sort(a + 1, a + n + 1); sort(b + 1, b + k + 1); long long ans = 4e18; for (int st = 0; st + n <= k; st++) { long long tans = 0; for (int i = 1; i <= n; i++) { long long temp = 0; long long now = b[st + i]; if (a[i] <= p && now <= p) { if (a[i] <= now) temp += p - a[i]; else temp += a[i] - now + p - now; } else if (a[i] <= p && p < now) temp += now - a[i] + now - p; else if (now <= p && p < a[i]) temp += a[i] - now + p - now; else if (p < a[i] && p < now) { if (now <= a[i]) temp += a[i] - p; else temp += now - a[i] + now - p; } tans = max(tans, temp); } ans = min(ans, tans); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> const int MaxN = 1000; using namespace std; char s[MaxN + 5]; int n; int vis[200 + 5]; int main() { while (~scanf( %d , &n)) { scanf( %s , s + 1); int Max = 0; for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) { memset(vis, 0, sizeof(vis)); int ans = 0; bool ok = 1; for (int k = i; k <= j; k++) { if (s[k] >= A && s[k] <= Z ) ok = 0; else { if (!vis[s[k]]) ans++, vis[s[k]] = 1; } } if (ok) Max = max(Max, ans); } } printf( %d n , Max); } }
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); int n, k; cin >> n >> k; for (int i = 1; i <= k; ++i) cout << 2 * i << << 2 * i - 1 << ; for (int i = 2 * k + 1; i <= 2 * n; ++i) cout << i << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[5001], n; int dfs(int l, int r) { int Min = a[l], ans = 0; for (int i = l + 1; i <= r; i++) Min = min(Min, a[i]); ans = Min; for (int i = l; i <= r; i++) a[i] -= Min; for (int i = l; i <= r; i++) if (a[i]) { int tmp = i + 1; while (tmp <= r && a[tmp]) ++tmp; ans += dfs(i, tmp - 1); i = tmp - 1; } return min(ans, r - l + 1); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); printf( %d n , dfs(1, n)); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { register int x = 0, f = 1, ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * f; } int n; int a[1010]; int b[1010]; int main() { n = read(); for (int i = 1; i <= n; i++) { a[i] = read(); } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { if (i & 1) printf( %d , a[(i + 1) / 2]); else printf( %d , a[n - i / 2 + 1]); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long DP[1000000]; long long counter[1000000]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { int x; cin >> x; counter[x]++; } DP[0] = 0; DP[1] = counter[1]; for (int i = 0; i < 1000000; i++) { DP[i] = max(DP[i - 1], DP[i - 2] + counter[i] * i); } cout << DP[1000000 - 1]; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 20; long long a[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, sum = 0, mx = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; mx = max(mx, a[i]); sum += a[i]; } cout << max((long long)((sum + n - 2) / (n - 1)), mx) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; unsigned long long ans = 0; for (int i = 0; i < s.size(); i++) { int x = s[i] - 0 ; if (x % 4 == 0) ans++; if (i > 0) { x += 10 * (s[i - 1] - 0 ); if (x % 4 == 0) ans += i; } } cout << ans << endl; return 0; }
|
#include<bits/stdc++.h> using namespace std; namespace program { const int N = 100005; struct edge { int to, nxt; edge() {} edge(int to_, int nxt_): to(to_), nxt(nxt_) {} } e[N << 1]; int hd[N], cnt, fir[N], end[N]; vector<pair<int, int> > del, ins; void adde(int u, int v) { e[++cnt] = edge(v, hd[u]); hd[u] = cnt; e[++cnt] = edge(u, hd[v]); hd[v] = cnt; } bool dfs(int u, int fa) { vector<int> son1, son2; for(int i = hd[u]; i; i = e[i].nxt) { int v = e[i].to; if(v == fa) continue; if(dfs(v, u)) { son1.push_back(v); } else { son2.push_back(v); } } if(!son1.size()) { end[u] = u; } else if(son1.size() == 1) { end[u] = end[son1[0]]; } else { end[u] = end[son1[0]]; fir[u] = end[son1[1]]; if(fa) del.push_back(make_pair(fa, u)); for(int i = 2; i < son1.size(); ++i) { del.push_back(make_pair(u, son1[i])); ins.push_back(make_pair(end[u], son1[i])); end[u] = end[son1[i]]; } } for(int i = 0; i < son2.size(); ++i) { ins.push_back(make_pair(end[u], fir[son2[i]])); end[u] = end[son2[i]]; } return son1.size() <= 1; } int main() { int T; scanf( %d , &T); while(T--) { int n; scanf( %d , &n); cnt = 0; memset(hd + 1, 0, sizeof(int) * n); for(int i = 1; i < n; ++i) { int u, v; scanf( %d%d , &u, &v); adde(u, v); } del.clear(); ins.clear(); dfs(1, 0); printf( %d n , del.size()); for(int i = 0; i < del.size(); ++i) { printf( %d %d %d %d n , del[i].first, del[i].second, ins[i].first, ins[i].second); } } return 0; } } int main() { return program::main(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_TB_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_TB_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv3sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkdlyinv3sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_TB_V
|
#include <bits/stdc++.h> using namespace std; int arr[200005], arr2[200005], n, repeat = 1, maxi, mas; long double result[200005]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); } for (int i = 0; i < n; i++) { scanf( %d , &arr2[i]); if (arr[i] != 0) { result[i] = (arr2[i] / (arr[i] * 1.00000000) * -1.00); } else if (arr2[i] == 0) { mas++; result[i] = -1000000004; } else result[i] = -1000000004; } sort(result, result + n); for (int i = 1; i < n; i++) { if (result[i] == result[i - 1] and result[i] != -1000000004) repeat++; else { if (repeat > maxi and result[i - 1] != -1000000004) maxi = repeat; repeat = 1; } } if (repeat > maxi and result[n - 1] != -1000000004) { maxi = repeat; } printf( %d , maxi + mas); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, mid, ans = 0; int all[100001]; all[0] = 0; cin >> n; for (int i = 1; i <= n; i++) { cin >> a; all[i] = all[i - 1] + a; } if (all[n] % 2 == 1) { cout << 0; return 0; } mid = all[n] / 2; for (int i = 1; i < n; i++) { if (all[i] == all[n] - all[i]) ans++; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const long double ESP = 1E-8; long double cal(long double x, long double y, long double z) { return log(x) * pow(y, z); } long double ca(long double x, long double y, long double z) { return y * z * log(x); } int main() { const char* result[12] = { x^y^z , x^z^y , (x^y)^z , (x^z)^y , y^x^z , y^z^x , (y^x)^z , (y^z)^x , z^x^y , z^y^x , (z^x)^y , (z^y)^x }; long double a[20]; long double x, y, z; cin >> x >> y >> z; a[0] = cal(x, y, z); a[1] = cal(x, z, y); a[2] = ca(x, y, z); a[3] = ca(x, z, y); a[4] = cal(y, x, z); a[5] = cal(y, z, x); a[6] = ca(y, x, z); a[7] = ca(y, z, x); a[8] = cal(z, x, y); a[9] = cal(z, y, x); a[10] = ca(z, x, y); a[11] = ca(z, y, x); long double maxn = a[0]; int res = 0; for (int i = 1; i < 12; ++i) { if (maxn < a[i] - ESP) { maxn = a[i]; res = i; } } printf( %s , result[res]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> g[100005]; int dep[100005], f[20][100005], mrk[100005], ans[100005]; map<pair<int, int>, int> mp; void dfs(int x, int p, int d) { for (int i = 0; i < g[x].size(); i++) if (g[x][i] != p) dfs(g[x][i], f[0][g[x][i]] = x, dep[g[x][i]] = d + 1); } int dfs2(int x, int p) { int cnt = 0; for (int i = 0; i < g[x].size(); i++) if (g[x][i] != p) { int num = dfs2(g[x][i], x); ans[mp[make_pair(x, g[x][i])]] = num; cnt += num; } cnt += mrk[x]; return cnt; } int lca(int x, int y) { if (dep[x] < dep[y]) swap(x, y); int sub = dep[x] - dep[y]; for (int i = 0; i < 20; i++) if (sub & (1 << i)) x = f[i][x]; if (x == y) return x; for (int i = 19; i >= 0; i--) if (f[i][x] != f[i][y]) { x = f[i][x]; y = f[i][y]; } x = f[0][x]; y = f[0][y]; return x; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); g[x].push_back(y); g[y].push_back(x); mp[make_pair(x, y)] = i; mp[make_pair(y, x)] = i; } dfs(1, f[0][1] = 0, dep[1] = 1); for (int i = 1; i < 20; i++) for (int j = 1; j <= n; j++) f[i][j] = f[i - 1][f[i - 1][j]]; int q; scanf( %d , &q); while (q--) { int x, y; scanf( %d%d , &x, &y); mrk[x]++; mrk[y]++; mrk[lca(x, y)] -= 2; } dfs2(1, 0); for (int i = 1; i < n; i++) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < 10; i++) { } set<int> s(a.begin(), a.end()); if (s.size() < k) { cout << NO << endl; } else { cout << YES << endl; int cnt = 0; for (auto item : s) { if (cnt == k) { break; } for (int i = 0; i < n; i++) { if (a[i] == item) { cout << i + 1 << ; cnt++; break; } } } for (int i = 0; i < 10; i++) { } cout << endl; } for (int i = 0; i < 10; i++) { } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> vec[100010]; long long a[100010]; long long s; int n; long long dfs(int f, int u, long long val) { int sz = vec[u].size(), v; long long ret = 0, mv = ((long long)1e18), tmp; if (sz == 1 && vec[u][0] == f) return (a[u] = ((val) < (a[u]) ? (val) : (a[u]))); if (u != 1) val = val / (sz - 1) * (sz - 1) / (sz - 1); else val = val / sz * sz / sz; for (int i = 0; i < sz; i++) { v = vec[u][i]; if (v == f) continue; tmp = dfs(u, v, val); mv = ((mv) < (tmp) ? (mv) : (tmp)); } while (true) { tmp = mv; for (int i = 0; i < sz; i++) { v = vec[u][i]; if (v == f) continue; if (a[v] > tmp) tmp = ((dfs(u, v, mv)) < (tmp) ? (dfs(u, v, mv)) : (tmp)); } if (tmp == mv) break; else mv = tmp; } for (int i = 0; i < sz; i++) if (vec[u][i] != f) ret += a[vec[u][i]]; return a[u] = ret; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %I64d , a + i), s += a[i]; for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); vec[u].push_back(v); vec[v].push_back(u); } long long ret = dfs(0, 1, ((long long)1e18)); cout << s - ret << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int fx[] = {1, -1, 0, 0}; int fy[] = {0, 0, 1, -1}; int main() { long long n; cin >> n; if (n == 1) cout << 1; else if (n == 2) cout << 3; else { n += 3; long long a = 0, b = 1; for (int i = 2; i <= n; i++) { long long c = (a + b) % 1000000007; a = b % 1000000007; b = c % 1000000007; } cout << (b - 2 + 1000000007) % 1000000007 << n ; } }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module nco_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 5,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
// user signals
input wire [15:0] sine_sample_V,
input wire sine_sample_V_ap_vld,
output wire [15:0] step_size_V
);
//------------------------Address Info-------------------
// 0x00 : reserved
// 0x04 : reserved
// 0x08 : reserved
// 0x0c : reserved
// 0x10 : Data signal of sine_sample_V
// bit 15~0 - sine_sample_V[15:0] (Read)
// others - reserved
// 0x14 : Control signal of sine_sample_V
// bit 0 - sine_sample_V_ap_vld (Read/COR)
// others - reserved
// 0x18 : Data signal of step_size_V
// bit 15~0 - step_size_V[15:0] (Read/Write)
// others - reserved
// 0x1c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
// address bits
localparam
ADDR_BITS = 5;
// address
localparam
ADDR_SINE_SAMPLE_V_DATA_0 = 5'h10,
ADDR_SINE_SAMPLE_V_CTRL = 5'h14,
ADDR_STEP_SIZE_V_DATA_0 = 5'h18,
ADDR_STEP_SIZE_V_CTRL = 5'h1c;
// axi write fsm
localparam
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2;
// axi read fsm
localparam
RDIDLE = 2'd0,
RDDATA = 2'd1;
//------------------------Local signal-------------------
// axi write
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
// axi read
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg [15:0] int_sine_sample_V;
reg int_sine_sample_V_ap_vld;
reg [15:0] int_step_size_V;
//------------------------Body---------------------------
//++++++++++++++++++++++++axi write++++++++++++++++++++++
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRIDLE;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++axi read+++++++++++++++++++++++
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDIDLE;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_SINE_SAMPLE_V_DATA_0: begin
rdata <= int_sine_sample_V[15:0];
end
ADDR_SINE_SAMPLE_V_CTRL: begin
rdata[0] <= int_sine_sample_V_ap_vld;
end
ADDR_STEP_SIZE_V_DATA_0: begin
rdata <= int_step_size_V[15:0];
end
endcase
end
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++internal registers+++++++++++++
assign step_size_V = int_step_size_V;
// int_sine_sample_V
always @(posedge ACLK) begin
if (ARESET)
int_sine_sample_V <= 0;
else if (ACLK_EN) begin
if (sine_sample_V_ap_vld)
int_sine_sample_V <= sine_sample_V;
end
end
// int_sine_sample_V_ap_vld
always @(posedge ACLK) begin
if (ARESET)
int_sine_sample_V_ap_vld <= 1'b0;
else if (ACLK_EN) begin
if (sine_sample_V_ap_vld)
int_sine_sample_V_ap_vld <= 1'b1;
else if (ar_hs && raddr == ADDR_SINE_SAMPLE_V_CTRL)
int_sine_sample_V_ap_vld <= 1'b0; // clear on read
end
end
// int_step_size_V[15:0]
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (w_hs && waddr == ADDR_STEP_SIZE_V_DATA_0)
int_step_size_V[15:0] <= (WDATA[31:0] & wmask) | (int_step_size_V[15:0] & ~wmask);
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m = 3, l, c[20000]; char s[500]; int main() { cin >> n; while (c[m] <= n) m++, c[m] = (long long)m * (m - 1) * (m - 2) * (m - 3) / 24; for (int i = m - 1; i >= 1; i--) { while (c[i] >= 1 && n >= c[i]) { s[++l] = a ; n -= c[i]; } s[++l] = b ; } printf( %s abbbb n , s + 1); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O221AI_PP_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3f; const double eps = 1e-12; const double PI = acos(-1.0); const int mod = 998244353; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } int ar[100050]; void solve() { int n, k; cin >> n >> k; bool exi = false, gp = false; for (int i = 1; i <= n; i++) { cin >> ar[i]; if (ar[i] == k) exi = true; } for (int i = 1; i < n; i++) { if (ar[i] >= k && (ar[i + 1] >= k || i < n - 1 && ar[i + 2] >= k)) { gp = true; break; } } if (n == 1 && ar[1] == k || exi && gp) cout << yes n ; else cout << no n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int T; cin >> T; for (int t = 1; t <= T; t++) { solve(); } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// data format (offset binary or 2's complement only)
`timescale 1ps/1ps
module ad_datafmt (
// data path
clk,
valid,
data,
valid_out,
data_out,
// control signals
dfmt_enable,
dfmt_type,
dfmt_se);
// delayed data bus width
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// data path
input clk;
input valid;
input [DW:0] data;
output valid_out;
output [15:0] data_out;
// control signals
input dfmt_enable;
input dfmt_type;
input dfmt_se;
// internal registers
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// internal signals
wire type_s;
wire signext_s;
wire [DW:0] data_s;
wire [23:0] sign_s;
wire [23:0] data_out_s;
// if offset-binary convert to 2's complement first
assign type_s = dfmt_enable & dfmt_type;
assign signext_s = dfmt_enable & dfmt_se;
assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data;
assign sign_s = (signext_s == 1'b1) ? {{24{data_s[DW]}}} : 24'd0;
assign data_out_s = {sign_s[23:(DW+1)], data_s};
always @(posedge clk) begin
valid_out <= valid;
data_out <= data_out_s[15:0];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// DO NOT EDIT
// This file is automatically generated!
// $ smg.shen rtl/SMG/kseq.smg
//
// https://github.com/sam-falvo/smg
module kseq(
input ram_wait_i,
input cfg,
input t5,
input t4,
input t3,
input t2,
input t1,
input wb_we_i,
input t0,
input wb_cyc_i,
input wb_stb_i,
input reset_i,
output clk_en,
output adr_bcrcfg,
output ram_cre_o,
output cfg_o,
output ram_be_valid,
output wb_ack_o,
output dq_dati,
output dato_dq,
output ram_we_o,
output ram_oe_o,
output ram_ce_o,
output ram_adv_o,
output nt5,
output nt4,
output nt3,
output nt2,
output nt1,
output nt0
);
wire R1391 = (|reset_i) ;
wire R1392 = ~(|reset_i) & ~(|wb_stb_i) & ~(|cfg) ;
wire R1393 = ~(|reset_i) & ~(|wb_cyc_i) & ~(|cfg) ;
wire R1394 = ~(|reset_i) & (|cfg) & (|t0) ;
wire R1395 = ~(|reset_i) & (|cfg) & (|t1) ;
wire R1396 = ~(|reset_i) & (|cfg) & (|t2) ;
wire R1397 = ~(|reset_i) & (|cfg) & (|t3) ;
wire R1398 = ~(|reset_i) & (|cfg) & (|t4) ;
wire R1399 = ~(|reset_i) & (|cfg) & (|t5) ;
wire R1400 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & ~(|wb_we_i) & (|t0) ;
wire R1401 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & ~(|wb_we_i) & (|t1) ;
wire R1402 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & ~(|wb_we_i) & (|ram_wait_i) & (|t1) ;
wire R1403 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & ~(|wb_we_i) & ~(|ram_wait_i) & (|t1) ;
wire R1404 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & ~(|wb_we_i) & (|t2) ;
wire R1405 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & ~(|wb_we_i) & (|t3) ;
wire R1406 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & (|wb_we_i) & (|t0) ;
wire R1407 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & (|wb_we_i) & (|t1) ;
wire R1408 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & (|wb_we_i) & (|ram_wait_i) & (|t1) ;
wire R1409 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & (|wb_we_i) & ~(|ram_wait_i) & (|t1) ;
wire R1410 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & (|wb_we_i) & (|t2) ;
wire R1411 = ~(|reset_i) & (|wb_stb_i) & (|wb_cyc_i) & ~(|cfg) & (|wb_we_i) & (|t3) ;
wire out1412 = R1391 ? 1 : 0 ;
wire out1413 = R1391 ? 1 : 0 ;
wire out1414 = R1392 ? 1 : 0 ;
wire out1415 = R1393 ? 1 : 0 ;
wire out1416 = R1394 ? 1 : 0 ;
wire out1417 = R1394 ? 1 : 0 ;
wire out1418 = R1394 ? 1 : 0 ;
wire out1419 = R1394 ? 1 : 0 ;
wire out1420 = R1394 ? 1 : 0 ;
wire out1421 = R1394 ? 1 : 0 ;
wire out1422 = R1394 ? 1 : 0 ;
wire out1423 = R1395 ? 1 : 0 ;
wire out1424 = R1395 ? 1 : 0 ;
wire out1425 = R1395 ? 1 : 0 ;
wire out1426 = R1395 ? 1 : 0 ;
wire out1427 = R1395 ? 1 : 0 ;
wire out1428 = R1396 ? 1 : 0 ;
wire out1429 = R1396 ? 1 : 0 ;
wire out1430 = R1396 ? 1 : 0 ;
wire out1431 = R1396 ? 1 : 0 ;
wire out1432 = R1397 ? 1 : 0 ;
wire out1433 = R1397 ? 1 : 0 ;
wire out1434 = R1397 ? 1 : 0 ;
wire out1435 = R1397 ? 1 : 0 ;
wire out1436 = R1398 ? 1 : 0 ;
wire out1437 = R1398 ? 1 : 0 ;
wire out1438 = R1398 ? 1 : 0 ;
wire out1439 = R1398 ? 1 : 0 ;
wire out1440 = R1399 ? 1 : 0 ;
wire out1441 = R1400 ? 1 : 0 ;
wire out1442 = R1400 ? 1 : 0 ;
wire out1443 = R1400 ? 1 : 0 ;
wire out1444 = R1400 ? 1 : 0 ;
wire out1445 = R1400 ? 1 : 0 ;
wire out1446 = R1401 ? 1 : 0 ;
wire out1447 = R1401 ? 1 : 0 ;
wire out1448 = R1402 ? 1 : 0 ;
wire out1449 = R1402 ? 1 : 0 ;
wire out1450 = R1402 ? 1 : 0 ;
wire out1451 = R1403 ? 1 : 0 ;
wire out1452 = R1403 ? 1 : 0 ;
wire out1453 = R1403 ? 1 : 0 ;
wire out1454 = R1404 ? 1 : 0 ;
wire out1455 = R1404 ? 1 : 0 ;
wire out1456 = R1404 ? 1 : 0 ;
wire out1457 = R1404 ? 1 : 0 ;
wire out1458 = R1404 ? 1 : 0 ;
wire out1459 = R1405 ? 1 : 0 ;
wire out1460 = R1405 ? 1 : 0 ;
wire out1461 = R1405 ? 1 : 0 ;
wire out1462 = R1406 ? 1 : 0 ;
wire out1463 = R1406 ? 1 : 0 ;
wire out1464 = R1406 ? 1 : 0 ;
wire out1465 = R1406 ? 1 : 0 ;
wire out1466 = R1406 ? 1 : 0 ;
wire out1467 = R1407 ? 1 : 0 ;
wire out1468 = R1407 ? 1 : 0 ;
wire out1469 = R1408 ? 1 : 0 ;
wire out1470 = R1409 ? 1 : 0 ;
wire out1471 = R1409 ? 1 : 0 ;
wire out1472 = R1409 ? 1 : 0 ;
wire out1473 = R1410 ? 1 : 0 ;
wire out1474 = R1410 ? 1 : 0 ;
wire out1475 = R1410 ? 1 : 0 ;
wire out1476 = R1410 ? 1 : 0 ;
wire out1477 = R1410 ? 1 : 0 ;
wire out1478 = R1411 ? 1 : 0 ;
wire out1479 = R1411 ? 1 : 0 ;
wire out1480 = R1411 ? 1 : 0 ;
assign cfg_o = out1439|out1435|out1431|out1427|out1422|out1413;
assign clk_en = out1480|out1477|out1468|out1466|out1461|out1458|out1450|out1447|out1445;
assign ram_ce_o = out1476|out1467|out1463|out1457|out1449|out1446|out1442|out1437|out1433|out1429|out1424|out1417;
assign adr_bcrcfg = out1425|out1420;
assign wb_ack_o = out1479|out1460;
assign dq_dati = out1475|out1472;
assign dato_dq = out1456|out1453;
assign ram_oe_o = out1455|out1452;
assign ram_cre_o = out1418;
assign ram_adv_o = out1464|out1443|out1419;
assign ram_be_valid = out1474|out1471|out1444;
assign ram_we_o = out1465|out1438|out1434|out1430|out1426|out1421;
assign nt0 = out1478|out1459|out1440|out1415|out1414|out1412;
assign nt1 = out1469|out1462|out1448|out1441|out1416;
assign nt2 = out1470|out1451|out1423;
assign nt3 = out1473|out1454|out1428;
assign nt4 = out1432;
assign nt5 = out1436;
endmodule
|
#include <bits/stdc++.h> int main(void) { int matrix[12][12]; memset(matrix, 0, sizeof(matrix)); int i; char s[3]; int col_r, row_r, col_k, row_k; scanf( %s , s); col_r = s[0] - a + 2; row_r = s[1] - 1 + 2; scanf( %s , s); col_k = s[0] - a + 2; row_k = s[1] - 1 + 2; for (i = 2; i < 10; i++) { matrix[row_r][i] = 1; matrix[i][col_r] = 1; } matrix[row_k][col_k] = 1; matrix[row_k - 1][col_k + 2] = 1; matrix[row_k - 1][col_k - 2] = 1; matrix[row_k + 1][col_k - 2] = 1; matrix[row_k + 1][col_k + 2] = 1; matrix[row_k - 2][col_k + 1] = 1; matrix[row_k - 2][col_k - 1] = 1; matrix[row_k + 2][col_k + 1] = 1; matrix[row_k + 2][col_k - 1] = 1; matrix[row_r - 1][col_r + 2] = 1; matrix[row_r - 1][col_r - 2] = 1; matrix[row_r + 1][col_r + 2] = 1; matrix[row_r + 1][col_r - 2] = 1; matrix[row_r - 2][col_r + 1] = 1; matrix[row_r - 2][col_r - 1] = 1; matrix[row_r + 2][col_r + 1] = 1; matrix[row_r + 2][col_r - 1] = 1; int j, sum = 0; for (i = 2; i < 10; i++) for (j = 2; j < 10; j++) if (matrix[i][j] == 0) sum++; printf( %d n , sum); return 0; }
|
#include <bits/stdc++.h> const int MAXN = 2e6 + 5; using namespace std; pair<int, int> arr[MAXN]; bool cmp(const pair<int, int> a, const pair<int, int> b) { return a.second > b.second; } int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { int q, w; scanf( %d %d , &q, &w); arr[i] = {q, w}; } sort(arr, arr + m, cmp); int N = (int(sqrt(8 * n - 7)) + 1) >> 1; long long ans = 0ll; int tmp = (N * (N - 1)) >> 1; if ((N & 1) == 0 && tmp + ((N - 1) >> 1) > n - 1) N--; for (int i = 0; i < min(N, m); i++) ans += (long long)arr[i].second; printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char ch = getchar(); while (ch - 0 < 0 || ch - 0 > 9) { if (ch == - ) f = -1; ch = getchar(); } while (ch - 0 >= 0 && ch - 0 <= 9) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, m; int a[55], w[55]; int A, B; int f[55][55][55]; int inv[3010]; int quick_pow(int x, int p) { int an = 1; int po = x; while (p) { if (p & 1) an = 1ll * an * po % 998244353; po = 1ll * po * po % 998244353; p >>= 1; } return an; } void solve(int id) { memset(f, 0, sizeof(f)); f[0][0][0] = 1; for (int i = 0; i < m; i++) { for (int j = 0; j <= i; j++) { for (int k = 0; k <= i; k++) { if (!f[i][j][k]) continue; if (a[id]) { int nowA = A + k, nowB = B - (i - k), sum = A + B + k - (i - k), noww = w[id] + j; f[i + 1][j + 1][k + 1] += 1ll * f[i][j][k] * noww % 998244353 * inv[sum] % 998244353; f[i + 1][j + 1][k + 1] %= 998244353; f[i + 1][j][k + 1] += 1ll * f[i][j][k] * (nowA - noww) % 998244353 * inv[sum] % 998244353; f[i + 1][j][k + 1] %= 998244353; f[i + 1][j][k] += 1ll * f[i][j][k] * nowB % 998244353 * inv[sum] % 998244353; f[i + 1][j][k] %= 998244353; } else { int nowA = A + k, nowB = B - (i - k), sum = A + B + k - (i - k), noww = w[id] - j; f[i + 1][j + 1][k] += 1ll * f[i][j][k] * noww % 998244353 * inv[sum] % 998244353; f[i + 1][j + 1][k] %= 998244353; f[i + 1][j][k + 1] += 1ll * f[i][j][k] * nowA % 998244353 * inv[sum] % 998244353; f[i + 1][j][k + 1] %= 998244353; f[i + 1][j][k] += 1ll * f[i][j][k] * (nowB - noww) % 998244353 * inv[sum] % 998244353; f[i + 1][j][k] %= 998244353; } } } } int res = 0; for (int j = 0; j <= m; j++) { for (int k = 0; k <= m; k++) { if (!f[m][j][k]) continue; if (a[id]) res = (res + 1ll * (w[id] + j) * f[m][j][k] % 998244353) % 998244353; else res = (res + 1ll * (w[id] - j) * f[m][j][k] % 998244353) % 998244353; } } printf( %d n , res); } int main() { n = read(); m = read(); for (int i = 1; i <= 3000; i++) inv[i] = quick_pow(i, 998244353 - 2); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= n; i++) w[i] = read(); for (int i = 1; i <= n; i++) A += w[i] * (a[i] == 1), B += w[i] * (a[i] == 0); for (int i = 1; i <= n; i++) solve(i); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1 << 18; int n, r; double sum = 0; long long c[MAXN + 10]; int main() { scanf( %d%d , &n, &r); for (int i = 0; i < (1 << n); i++) { scanf( %lld , &c[i]); sum += c[i]; } double dv = 1 << n; printf( %.9lf n , sum / dv); for (int i = 0; i < r; i++) { int z; long long x; scanf( %d%lld , &z, &x); sum += x - c[z]; c[z] = x; printf( %.9lf n , sum / dv); } }
|
#include <bits/stdc++.h> using namespace std; template <class T> T gcd(T a, T b) { return (b != 0 ? gcd<T>(b, a % b) : a); } template <class T> T lcm(T a, T b) { return (a / gcd<T>(a, b) * b); } long long pwr(long long base, long long p) { long long ans = 1; while (p) { if (p & 1) ans = (ans * base) % (1000000007LL); base = (base * base) % (1000000007LL); p >>= 1; } return ans; } long long modInv(long long n, long long mod) { return pwr(n, mod - 2); } int bitCount(int n) { int c = 0; while (n) { c++; n &= n - 1; } return c; } int main() { double n, m, cost; ; int i, a, b; cin >> n >> m; int ver[100000]; for (i = 1; i < n + 1; i++) { scanf( %d , &ver[i]); } double ans = 0; for (i = 0; i < m; i++) { cin >> a >> b >> cost; ans = max(ans, (ver[a] + ver[b]) / cost); } printf( %.12lf n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cout << *it << = << a << endl; err(++it, args...); } const long long MOD = 1e9 + 7; long long modExp(long long b, long long p) { long long res = 1; while (p > 0) { if (p & 1) { res = (res * b) % MOD; } b = (b * b) % MOD; p >>= 1; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; long long ans = 1; for (int i = 1; i <= n; i++) { ans = ((2 * m - 1) * ans + modExp(m, i - 1)) % MOD; } cout << ans; return 0; }
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Stratix IV" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 11.0SP1 cbx_altiobuf_out 2011:07:03:21:10:33:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ cbx_stratixv 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_io_obuf 2 stratixiv_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] oe_b;
wire [0:0] oe_w;
stratixiv_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(oe_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "stratixiv_io_obuf";
stratixiv_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(oe_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.shift_series_termination_control = "false",
obufa_0.lpm_type = "stratixiv_io_obuf";
stratixiv_pseudo_diff_out pseudo_diffa_0
(
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]));
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_b = 1'b1,
oe_w = 1'b1;
endmodule //ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; const int N = 605; int dp[N][N]; int l[N], r[N]; string res; void fill(int i, int j, int a, int b) { int k = j - i; if (i > j || a > b) return; if (l[i] <= 2 * k + 1 && 2 * k + 1 <= r[i] && (i == j || dp[i + 1][j])) { res[a] = ( , res[b] = ) ; fill(i + 1, j, a + 1, b - 1); } else { for (int k = i; k < j; ++k) if (dp[i][k] && dp[k + 1][j]) { int diff = k - i + 1; fill(i, k, a, a + 2 * diff - 1); fill(k + 1, j, a + 2 * diff, b); break; } } } int main() { std::ios::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> l[i] >> r[i]; } memset(dp, 0, sizeof(dp)); for (int i = n; i >= 1; --i) { for (int j = i; j <= n; ++j) { int k = j - i; if (l[i] <= 2 * k + 1 && 2 * k + 1 <= r[i] && (i == j || dp[i + 1][j])) dp[i][j] = 1; for (int k = i; k < j; ++k) dp[i][j] |= (dp[i][k] && dp[k + 1][j]); } } if (dp[1][n]) { res.resize(2 * n, # ); fill(1, n, 0, 2 * n - 1); cout << res << endl; } else { cout << IMPOSSIBLE << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int x, y; cin >> x >> y; int ans = 0; int d = max(abs(x), abs(y)); if (d == 0) { cout << 0 << n ; return 0; } else ans = (d - 1) * 4; if (x == d && y != -1 * (d - 1) && y != -1 * (d)) ans++; if (y == d && x != d) ans += 2; if (x == -1 * d && y != d) ans += 3; if (y == -1 * d && x != -1 * d) ans += 4; cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; string s; int pos[1000]; int n, a, b; int main() { cin >> n; cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == x ) a++; else b++; } cout << abs(n / 2 - a) << endl; int t = abs(n / 2 - a); if (a > b) { for (int i = 0; i < s.size(); i++) if (s[i] == x && t) { s[i] = X ; t--; } } else if (a < b) { for (int i = 0; i < s.size(); i++) if (s[i] == X && t) { s[i] = x ; t--; } } cout << s << endl; return 0; }
|
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