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#include <bits/stdc++.h> using namespace std; using lint = long long int; int main() { lint n; cin >> n; vector<lint> v(n); for (lint i = 0; i < n; i++) { cin >> v[i]; } lint val = 2 * accumulate(v.begin(), v.end(), 0ll) / n; vector<lint> visited(n); for (lint i = 0; i < n; i++) { if (visited[i]) { continue; } for (lint j = i + 1; j < n; j++) { if (visited[j]) { continue; } if (v[i] + v[j] == val) { visited[i] = 1; visited[j] = 1; cout << (i + 1) << << (j + 1) << endl; break; } } } }
|
#include <bits/stdc++.h> using namespace std; const int maxm = 2e5 + 10; set<int> g; queue<set<int> > q; int m, n, x, y; int dfs(int top) { if (abs(top) <= 1) return 0; int now = 0; if ((-top) % 2 == 0) now = top / 2; else now = (top + 1) / 2; if (g.find(now) == g.end()) { g.erase(top); g.insert(now); return 1; } else return dfs(now); } int main() { cin >> m; for (int i = 1; i <= m; i++) { cin >> x; g.insert(-x); } for (;;) { int top = *g.begin(); if (!dfs(top)) break; } for (auto e : g) cout << -e << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x(0); cin >> n; string s; while (n--) { cin >> s; if (s[1] == + ) { ++x; } else { --x; } } cout << x << endl; return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`resetall
`timescale 1 ns / 1 ps
`default_nettype none
/*
* Synchronizes switch and button inputs with a slow sampled shift register
*/
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule
`resetall
|
// Copyright (c) 2016 Min Chen
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
module SMUL(a, b, c);
parameter WIDTH_A = 1;
parameter WIDTH_B = 1;
input [WIDTH_A-1:0] a;
input [WIDTH_B-1:0] b;
output [WIDTH_A+WIDTH_B-2:0] c;
assign c = $signed(a) * $signed(b);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long T; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> T; int a, b, c, d; while (T--) { cin >> a >> b >> c >> d; bool ok = 0; if (a == c) { if (d + b == a) ok = 1; } if (a == d) { if (c + b == a) ok = 1; } if (b == c) { if (a + d == b) ok = 1; } if (b == d) { if (a + c == b) ok = 1; } if (ok) cout << Yes n ; else cout << No n ; } return 0; }
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_ex_fifo.v
// Version : v1.0
// Description: FIFO used on all address/data channels to store/forward
// address/data/control information.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_ex_fifo
#(
parameter WIDTH = 10,
parameter DEPTH = 8 ,
parameter DEPTHBITS = 3 ,
parameter HEADREG = 1 ,
parameter ZERO_INVALID = 0 ,
parameter FULL_LEVEL = 6 ,
parameter BLOCK_ACTIVE = 0 //Ability to block notfull and valid
) (
input Clk ,
input rst_l ,
input [WIDTH-1:0] in_data ,
input in_push ,
input in_pop ,
//input in_block_notfull ,
//input in_block_outvalid,
output [WIDTH-1:0] out_data ,
output is_full ,
output is_notfull ,
output is_empty ,
output out_valid ,
output [15:0] ex_fifo_dbgout
);
reg [WIDTH-1:0 ] data_ff[DEPTH-1:0];
reg [DEPTHBITS-1:0] out_ptr_ff;
reg [DEPTHBITS-1:0] in_ptr_ff;
reg [DEPTHBITS:0 ] depth_ff;
reg [WIDTH-1:0 ] headreg_ff;
reg full_ff, notfull_ff, valid_ff, valid_filt_ff;
wire [DEPTHBITS-1:0] in_ptr = (in_push) ? in_ptr_ff[DEPTHBITS-1:0] + 'h1 :
in_ptr_ff[DEPTHBITS-1:0];
wire [DEPTHBITS:0] depth =
(in_push && ~in_pop) ? depth_ff[DEPTHBITS:0] + 'h1 :
(~in_push && in_pop) ? depth_ff[DEPTHBITS:0] - 'h1 :
depth_ff[DEPTHBITS:0];
wire depth_was1 = (depth_ff[DEPTHBITS:0] == 'h1);
wire valid = (depth[DEPTHBITS:0] != 'h0);
wire full ;
generate if(BLOCK_ACTIVE == 1 ) begin : BLOCK_ACTIVE_FULL_YES
// assign full = (depth[DEPTHBITS:0] >= FULL_LEVEL) || in_block_notfull;
end
endgenerate
generate if(BLOCK_ACTIVE == 0 ) begin : BLOCK_ACTIVE_FULL_NO
assign full = (depth[DEPTHBITS:0] >= FULL_LEVEL) ;
end
endgenerate
wire notfull = ~full;
wire [WIDTH-1:0] raw_data = data_ff[out_ptr_ff[DEPTHBITS-1:0]];
wire [DEPTHBITS-1:0] out_ptr = (in_pop) ? out_ptr_ff[DEPTHBITS-1:0] + 'h1 :
out_ptr_ff[DEPTHBITS-1:0];
wire [WIDTH-1:0] head_raw_data = (depth_was1) ? in_data[WIDTH-1:0] :
raw_data[WIDTH-1:0];
wire [WIDTH-1:0] headreg = (!valid_ff && in_push) ? in_data[WIDTH-1:0] :
(in_pop) ? head_raw_data[WIDTH-1:0] : headreg_ff[WIDTH-1:0];
wire valid_filt ;
generate if(BLOCK_ACTIVE == 1 ) begin : BLOCK_ACTIVE_VALID_YES
// assign valid_filt = valid &&
// ((valid_filt_ff && ~in_pop) || ~in_block_outvalid);
end
endgenerate
generate if(BLOCK_ACTIVE == 0 ) begin : BLOCK_ACTIVE_VALID_NO
assign valid_filt = valid ;
// Deassert output valid sometimes, without changing
// internal valid logic. Do not deassert valid once
// its been asserted, until other agent drives ready
end
endgenerate
always @(posedge Clk) begin
in_ptr_ff[DEPTHBITS-1:0] <= (rst_l) ? in_ptr[DEPTHBITS-1:0] : {DEPTHBITS{1'b0}};
out_ptr_ff[DEPTHBITS-1:0] <= (rst_l) ? out_ptr[DEPTHBITS-1:0] :
((HEADREG) ? {{(DEPTHBITS-1){1'b0}},{1'b1}} : {DEPTHBITS{1'b0}});
depth_ff[DEPTHBITS:0] <= (rst_l) ? depth[DEPTHBITS:0] : {DEPTHBITS{1'b0}};
valid_ff <= (rst_l) ? valid : 1'b0;
valid_filt_ff <= (rst_l) ? valid_filt : 1'b0;
full_ff <= (rst_l) ? full : 1'b1;
notfull_ff <= (rst_l) ? notfull : 1'b0;
headreg_ff[WIDTH-1:0] <= (rst_l) ? headreg[WIDTH-1:0] : {WIDTH{1'b0}};
end
integer i;
always @(posedge Clk) begin
if(in_push) begin
data_ff[in_ptr_ff[DEPTHBITS-1:0]] <= in_data[WIDTH-1:0];
end
`ifdef FOO_BAR
for(i = 0; i < DEPTH; i = i + 1) begin
if(~rst_l && (HEADREG == 0)) begin
data_ff[i] <= {WIDTH{1'b0}};
end else if((i == in_ptr_ff[DEPTHBITS-1:0]) && in_push) begin
data_ff[i] <= in_data[WIDTH-1:0];
end
end
`endif
end
assign out_data[WIDTH-1:0] = (ZERO_INVALID && ~valid_filt_ff) ? { WIDTH {1'b0}}:
(HEADREG) ? headreg_ff[WIDTH-1:0] :
raw_data[WIDTH-1:0];
assign out_valid = valid_filt_ff;
assign is_full = full_ff ;
assign is_notfull = notfull_ff ;
assign is_empty = ~valid_ff ;
assign ex_fifo_dbgout = 16'b0 | depth_ff;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e9; const int M = 1e9; int ix, iy, fx, fy; map<pair<int, int>, int> pres; map<pair<int, int>, int> dist; map<pair<int, int>, bool> vis; int dx[] = {-1, -1, -1, 0, 0, 0, 1, 1, 1}; int dy[] = {-1, 0, 1, -1, 0, 1, -1, 0, 1}; bool check(int x, int y) { if (x >= 1 && x <= 1e9 && y >= 1 && y <= 1e9) { if (pres[make_pair(x, y)]) return true; return false; } return false; } void bfs(int x, int y) { queue<pair<int, int> > q; pair<int, int> tmp; q.push(make_pair(x, y)); while (q.size() > 0) { tmp = q.front(); q.pop(); for (int i = 0; i < 9; ++i) { int x1 = tmp.first + dx[i]; int y1 = tmp.second + dy[i]; if (check(x1, y1) && vis[make_pair(x1, y1)] == 0) { vis[make_pair(x1, y1)] = 1; dist[make_pair(x1, y1)] = dist[tmp] + 1; q.push(make_pair(x1, y1)); } } } } int main() { cin >> ix >> iy >> fx >> fy; int Q; cin >> Q; int x, y, z; for (int q = 1; q <= Q; ++q) { scanf( %d%d%d , &x, &y, &z); for (int i = y; i <= z; ++i) { pres[make_pair(x, i)] = 1; } } dist[make_pair(ix, iy)] = 0; dist[make_pair(fx, fy)] = 1e9; vis[make_pair(ix, iy)] = 1; bfs(ix, iy); int res = dist[make_pair(fx, fy)]; if (res >= 1e9) res = -1; cout << res << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAH_2_V
`define SKY130_FD_SC_MS__FAH_2_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fah_2 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fah_2 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAH_2_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverycud_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 19;
parameter MEM_SIZE = 480000;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./contact_discoverycud_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverycud(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd480000;
parameter AddressWidth = 32'd19;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
contact_discoverycud_ram contact_discoverycud_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; double f, s, v, l, omega, r; const double tol = 1.0e-7; scanf( %d %lf %lf , &n, &r, &v); omega = v / r; double xt, xb, a, b; for (int i = 0; i < n; i++) { scanf( %lf %lf , &s, &f); l = (f - s) / 2.; a = (l + r + 0.1) / v; b = -0.1; xt = (a + b) / 2.; while (abs((b - a) / xt) > tol) { if ((v * xt + r * sin(xt * omega) - l) * (v * a + r * sin(a * omega) - l) < 0.) b = xt; else a = xt; xt = (a + b) / 2.; } a = (l + r + 0.1) / v; b = -0.1; do { xb = (a + b) / 2.; if ((v * xb - r * sin(xb * omega) - l) * (v * a - r * sin(a * omega) - l) < 0.) b = xb; else a = xb; } while (abs((b - a) / xb) > tol); printf( %.10lf n , 2. * min(xb, xt)); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_2_V
`define SKY130_FD_SC_MS__AND3B_2_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFXTP_BLACKBOX_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); return (b == 0) ? a : gcd(b, a % b); } const double EPS = 1e-10; const double PI = acos(-1.0); const int INF = 1 << 29; const int mod = 1000000007; const int MAX_V = 1000 + 10; const int MAX_M = 10000 + 10; const int maxm = 1 + 5; const int maxn = 50000 + 5; int used[20]; int n; int main() { scanf( %d , &n); int i, j, sum = 0, a; memset(used, 0, sizeof(used)); for (int i = 0; i < n; i++) { scanf( %d , &a); sum += a; used[a]++; } if (used[0] == 0) cout << -1 << endl; else { int flag = 0; if (sum % 3 == 1) { if (used[1] + used[4] + used[7]) { for (int i = 1; i <= 7; i += 3) { if (used[i]) { used[i]--, sum -= i; break; } } } else if (used[2] + used[5] + used[8] >= 2) { for (j = 1, i = 2; i <= 8; i += 3) { while (used[i] && j <= 2) used[i]--, sum -= i, j++; } } } if (sum % 3 == 2) { if (used[2] + used[5] + used[8]) { for (i = 2; i <= 8; i += 3) if (used[i]) { used[i]--, sum -= i; break; } } else if (used[1] + used[4] + used[7] >= 2) { for (j = 1, i = 1; i <= 7; i += 3) while (used[i] && j <= 2) used[i]--, sum -= i, j++; } else flag = 1; } if (!flag) { if (used[1] + used[2] + used[3] + used[4] + used[5] + used[6] + used[7] + used[8] + used[9]) { for (i = 9; i >= 0; i--) while (used[i]--) printf( %d , i); printf( n ); } else printf( 0 n ); } else printf( 0 n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_4_V
`define SKY130_FD_SC_HD__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_SYMBOL_V
`define SKY130_FD_SC_LP__DFXBP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_SYMBOL_V
|
// Taken from:
// http://electrosofts.com/verilog/fifo.html
`define BUF_WIDTH 4 // BUF_SIZE = 16 -> BUF_WIDTH = 4, no. of bits to be used in pointer
`define BUF_SIZE ( 1<<`BUF_WIDTH )
module fifo(input clk,
input reset,
input [31:0] data_in,
input data_in_wr,
output reg [31:0] data_out,
input data_out_en,
output reg full,
output reg empty
);
parameter DEBUG = 0;
reg [`BUF_WIDTH :0] fifo_counter;
reg [`BUF_WIDTH -1:0] rd_ptr, wr_ptr; // pointer to read and write addresses
reg [31:0] buf_mem[`BUF_SIZE -1 : 0]; //
always @(fifo_counter)
begin
empty = (fifo_counter==0);
full = (fifo_counter== `BUF_SIZE);
end
always @(posedge clk)
begin
if( !reset )
fifo_counter <= 0;
else if( (!full && data_in_wr) &&
( !empty && data_out_en ) )
fifo_counter <= fifo_counter;
else if( !full && data_in_wr )
fifo_counter <= fifo_counter + 1;
else if( !empty && data_out_en )
fifo_counter <= fifo_counter - 1;
else
fifo_counter <= fifo_counter;
end
always @( posedge clk)
begin
if( !reset )
data_out <= 0;
else
begin
if( data_out_en && !empty ) begin
if (DEBUG)
$display("FIFO OUT -> [%x]", buf_mem[rd_ptr]);
data_out <= buf_mem[rd_ptr];
end
else
data_out <= data_out;
end
end
always @(posedge clk)
begin
if( data_in_wr && !full ) begin
if(DEBUG)
$display("FIFO IN <- [%x]", data_in);
buf_mem[ wr_ptr ] <= data_in;
end
else
buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];
end
always@(posedge clk)
begin
if( !reset )
begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else
begin
if( !full && data_in_wr ) wr_ptr <= wr_ptr + 1;
else wr_ptr <= wr_ptr;
if( !empty && data_out_en ) rd_ptr <= rd_ptr + 1;
else rd_ptr <= rd_ptr;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_1_V
`define SKY130_FD_SC_MS__NAND4_1_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_1_V
|
`include "vscale_hasti_constants.vh"
module vscale_hasti_bridge(
output [`HASTI_ADDR_WIDTH-1:0] haddr,
output hwrite,
output [`HASTI_SIZE_WIDTH-1:0] hsize,
output [`HASTI_BURST_WIDTH-1:0] hburst,
output hmastlock,
output [`HASTI_PROT_WIDTH-1:0] hprot,
output [`HASTI_TRANS_WIDTH-1:0] htrans,
output [`HASTI_BUS_WIDTH-1:0] hwdata,
input [`HASTI_BUS_WIDTH-1:0] hrdata,
input hready,
input [`HASTI_RESP_WIDTH-1:0] hresp,
input core_mem_en,
input core_mem_wen,
input [`HASTI_SIZE_WIDTH-1:0] core_mem_size,
input [`HASTI_ADDR_WIDTH-1:0] core_mem_addr,
input [`HASTI_BUS_WIDTH-1:0] core_mem_wdata_delayed,
output [`HASTI_BUS_WIDTH-1:0] core_mem_rdata,
output core_mem_wait,
output core_badmem_e
);
assign haddr = core_mem_addr;
assign hwrite = core_mem_en && core_mem_wen;
assign hsize = core_mem_size;
assign hburst = `HASTI_BURST_SINGLE;
assign hmastlock = `HASTI_MASTER_NO_LOCK;
assign hprot = `HASTI_NO_PROT;
assign htrans = core_mem_en ? `HASTI_TRANS_NONSEQ : `HASTI_TRANS_IDLE;
assign hwdata = core_mem_wdata_delayed;
assign core_mem_rdata = hrdata;
assign core_mem_wait = ~hready;
assign core_badmem_e = hresp == `HASTI_RESP_ERROR;
endmodule // vscale_hasti_bridge
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
// module, then calculates a CRC on the Test module's outputs.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by ____YOUR_NAME_HERE____.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [31:0] in;
output reg [31:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
wire signed [7:0] sgn_wide;
wire [7:0] unsgn_wide;
// The instantiation will Z extend, not sign extend
// verilator lint_off WIDTH
sub sub (.clk,
.sgn(sgn_wide), .unsgn(unsgn_wide),
.iss(3'sh7), .isu(3'h7),
.ius(3'sh7), .iuu(3'h7));
// verilator lint_on WIDTH
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide);
`endif
if (sgn_wide[2:0] != 3'sh7) $stop;
if (unsgn_wide[2:0] != 3'h7) $stop;
// Simulators differ here.
if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC
&& sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS
if (unsgn_wide !== 8'sbzzzzz111
&& unsgn_wide!== 8'sb00000111) $stop;
cyc <= cyc + 1;
if (cyc==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (
input clk,
output wire signed [2:0] sgn,
output wire [2:0] unsgn,
input signed [7:0] iss,
input signed [7:0] isu,
input [7:0] ius,
input [7:0] iuu);
assign sgn = 3'sh7;
assign unsgn = 3'h7;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("in: %x %x %x %x\n", iss, isu, ius, iuu);
if (iss != 8'hff) $stop;
if (isu != 8'h07) $stop;
if (ius != 8'hff) $stop;
if (iuu != 8'h07) $stop;
`endif
end
endmodule
|
module divider(divident,divisor,quotient);
input wire [31:0] divident;
input wire [31:0] divisor;
output reg [31:0] quotient;
reg [47:0]tmpDivident;
reg [23:0]tmpDivisor;
reg [25:0]tmpQuotient;
reg [25:0] remainder;
reg [8:0]exponent;
reg [8:0]tmp;
integer i; // 整数,用于计数
always @(divident or divisor) // 被除数,除数
begin
quotient=0;
remainder=0;
tmpDivident={1,divident[22:0],24'b0};
tmpDivisor={1,divisor[22:0]};
exponent=divident[30:23]+128-divisor[30:23];
tmpQuotient=0;
// 开始余数和商清零
tmp=divident[30:23]+127;
if(tmp<divisor[30:23])
begin
quotient=0;
end
else if(tmp-divisor[30:23]>254)
begin
quotient={divident[31]^divisor[31],8'b1,23'b0};
end
else if(divident==0||divisor[30:23]-255==0)
begin
quotient=0;
end // 若除数为0则显示错误
else if(divident[30:23]==255)
begin
quotient=divident;
end
else if(divisor==0)
begin // 商0,余数为除数
quotient={divident[31],8'b1,23'b0};
end
else
begin
for (i=48;i>0;i=i-1) // 循环48次
begin
remainder={remainder[25:0],tmpDivident[i-1]}; // 把did[i-1]连接到rem后
tmpQuotient=tmpQuotient<<1; // 商左移一位
if(remainder>=tmpDivisor) // 若拼接后rem>=除数dis
begin
tmpQuotient=tmpQuotient+1; // 商值自加1
remainder=remainder-tmpDivisor; // 新余数变为旧余数减除数
end
end
for(i=3;i>0;i=i-1)
begin
if(tmpQuotient[25]!=1)
begin
tmpQuotient=tmpQuotient*2;//左移
exponent=exponent-1;
end
end
quotient={divident[31]^divisor[31],exponent[7:0],tmpQuotient[24:2]};
end
end // 结束
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_2_V
`define SKY130_FD_SC_LP__MUX4_2_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_2 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_2_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Round function of main datapath for HIGHT Crypto Core ////
//// ////
//// This file is part of the HIGHT Crypto Core project ////
//// http://github.com/OpenSoCPlus/hight_crypto_core ////
//// http://www.opencores.org/project,hight ////
//// ////
//// Description ////
//// __description__ ////
//// ////
//// Author(s): ////
//// - JoonSoo Ha, ////
//// - Younjoo Kim, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module RF(
i_op ,
i_rsk ,
i_rf_in ,
i_rf_final ,
o_rf_out
);
//=====================================
//
// PARAMETERS
//
//=====================================
//=====================================
//
// I/O PORTS
//
//=====================================
input i_op ;
input[31:0] i_rsk ;
input[63:0] i_rf_in ;
input i_rf_final ;
output[63:0] o_rf_out ;
//=====================================
//
// REGISTERS
//
//=====================================
//=====================================
//
// WIRES
//
//=====================================
// w_rf_out
wire[63:0] w_rf_out ;
// w_rf_out (7 ~ 0)
wire[7:0] w_rf_out7 ;
wire[7:0] w_rf_out6 ;
wire[7:0] w_rf_out5 ;
wire[7:0] w_rf_out4 ;
wire[7:0] w_rf_out3 ;
wire[7:0] w_rf_out2 ;
wire[7:0] w_rf_out1 ;
wire[7:0] w_rf_out0 ;
// w_f_function
wire[7:0] w_f0_6 ;
wire[7:0] w_f1_4 ;
wire[7:0] w_f0_2 ;
wire[7:0] w_f1_0 ;
// w_rf_median_value
wire[7:0] w_rf_mv[0:3];
//=====================================
//
// MAIN
//
//=====================================
assign w_f0_6 = {i_rf_in[54:48],i_rf_in[55]} ^
{i_rf_in[53:48],i_rf_in[55:54]} ^
{i_rf_in[48] ,i_rf_in[55:49]};
assign w_f1_4 = {i_rf_in[36:32],i_rf_in[39:37]} ^
{i_rf_in[35:32],i_rf_in[39:36]} ^
{i_rf_in[33:32],i_rf_in[39:34]};
assign w_f0_2 = {i_rf_in[22:16],i_rf_in[23]} ^
{i_rf_in[21:16],i_rf_in[23:22]} ^
{i_rf_in[16] ,i_rf_in[23:17]};
assign w_f1_0 = {i_rf_in[4:0] ,i_rf_in[7:5]} ^
{i_rf_in[3:0] ,i_rf_in[7:4]} ^
{i_rf_in[1:0] ,i_rf_in[7:2]};
assign w_rf_mv[3] = (i_op == 0) ? i_rf_in[63:56] ^ (w_f0_6 + i_rsk[31:24]):
i_rf_in[63:56] ^ (w_f0_6 + i_rsk[7:0]);
assign w_rf_mv[2] = (i_op == 0) ? i_rf_in[47:40] + (w_f1_4 ^ i_rsk[23:16]):
i_rf_in[47:40] - (w_f1_4 ^ i_rsk[15:8]);
assign w_rf_mv[1] = (i_op == 0) ? i_rf_in[31:24] ^ (w_f0_2 + i_rsk[15:8]):
i_rf_in[31:24] ^ (w_f0_2 + i_rsk[23:16]);
assign w_rf_mv[0] = (i_op == 0) ? i_rf_in[15:8] + (w_f1_0 ^ i_rsk[7:0]):
i_rf_in[15:8] - (w_f1_0 ^ i_rsk[31:24]);
assign w_rf_out7 = (i_rf_final == 1) ? w_rf_mv[3] :
(i_op == 0) ? i_rf_in[55:48] :
i_rf_in[7:0];
assign w_rf_out6 = (i_rf_final == 1) ? i_rf_in[55:48] :
(i_op == 0) ? w_rf_mv[2] :
w_rf_mv[3];
assign w_rf_out5 = (i_rf_final == 1) ? w_rf_mv[2] :
(i_op == 0) ? i_rf_in[39:32] :
i_rf_in[55:48];
assign w_rf_out4 = (i_rf_final == 1) ? i_rf_in[39:32] :
(i_op == 0) ? w_rf_mv[1] :
w_rf_mv[2];
assign w_rf_out3 = (i_rf_final == 1) ? w_rf_mv[1] :
(i_op == 0) ? i_rf_in[23:16] :
i_rf_in[39:32];
assign w_rf_out2 = (i_rf_final == 1) ? i_rf_in[23:16] :
(i_op == 0) ? w_rf_mv[0] :
w_rf_mv[1];
assign w_rf_out1 = (i_rf_final == 1) ? w_rf_mv[0] :
(i_op == 0) ? i_rf_in[7:0] :
i_rf_in[23:16];
assign w_rf_out0 = (i_rf_final == 1) ? i_rf_in[7:0] :
(i_op == 0) ? w_rf_mv[3] :
w_rf_mv[0];
assign w_rf_out = {w_rf_out7, w_rf_out6, w_rf_out5, w_rf_out4, w_rf_out3, w_rf_out2, w_rf_out1, w_rf_out0};
assign o_rf_out = w_rf_out;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// both inputs are considered unsigned 16 bits-
// ddata is delay matched generic data
`timescale 1ps/1ps
module ad_mul_u16 (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0] data_a;
input [15:0] data_b;
output [31:0] data_p;
// delay interface
input [DW:0] ddata_in;
output [DW:0] ddata_out;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [DW:0] ddata_out = 'd0;
// internal signals
wire [33:0] data_p_s;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
assign data_p = data_p_s[31:0];
MULT_MACRO #(
.LATENCY (3),
.WIDTH_A (17),
.WIDTH_B (17))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),
.CLK (clk),
.A ({1'b0, data_a}),
.B ({1'b0, data_b}),
.P (data_p_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_BLACKBOX_V
`define SKY130_FD_SC_HS__AND3B_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and3b (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_BLACKBOX_V
|
module PLLE2_BASE (/*AUTOARG*/
// Outputs
LOCKED, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5,
CLKFBOUT,
// Inputs
CLKIN1, RST, PWRDWN, CLKFBIN
);
parameter BANDWIDTH = 0;
parameter CLKFBOUT_MULT = 1;
parameter CLKFBOUT_PHASE = 0;
parameter CLKIN1_PERIOD = 10;
parameter DIVCLK_DIVIDE = 1;
parameter REF_JITTER1 = 0;
parameter STARTUP_WAIT = 0;
parameter CLKOUT0_DIVIDE = 1;
parameter CLKOUT0_DUTY_CYCLE = 0.5;
parameter CLKOUT0_PHASE = 0;
parameter CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 0.5;
parameter CLKOUT1_PHASE = 0;
parameter CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 0.5;
parameter CLKOUT2_PHASE = 0;
parameter CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 0.5;
parameter CLKOUT3_PHASE = 0;
parameter CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 0.5;
parameter CLKOUT4_PHASE = 0;
parameter CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 0.5;
parameter CLKOUT5_PHASE = 0;
//#LOCAL DERIVED PARAMETERS
parameter VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT;
parameter CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE * (CLKOUT0_PHASE/360);
parameter CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
parameter CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
parameter CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
parameter CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
parameter CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
//inputs
input CLKIN1;
input RST;
input PWRDWN;
input CLKFBIN;
//outputs
output LOCKED;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output CLKFBOUT;
//##############
//#VCO
//##############
reg vco_clk;
initial
begin
vco_clk = 1'b0;
end
always
#(VCO_PERIOD/2) vco_clk = ~vco_clk;
//##############
//#DIVIDERS
//##############
wire [3:0] DIVCFG[5:0];
wire [5:0] CLKOUT_DIV;
assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE);
assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
//ugly POR reset
reg POR;
initial
begin
POR=1'b1;
#1
POR=1'b0;
end
genvar i;
generate for(i=0; i<6; i=i+1)
begin : gen_clkdiv
clock_divider clkdiv (/*AUTOINST*/
// Outputs
.clkout (CLKOUT_DIV[i]),
// Inputs
.clkin (vco_clk),
.divcfg (DIVCFG[i]),
.reset (RST | POR)
);
end
endgenerate
//##############
//#PHASE DELAY
//##############
reg CLKOUT0;
reg CLKOUT1;
reg CLKOUT2;
reg CLKOUT3;
reg CLKOUT4;
reg CLKOUT5;
always @ (CLKOUT_DIV)
begin
CLKOUT0 <= #(CLK0_DELAY) CLKOUT_DIV[0];
CLKOUT1 <= #(CLK1_DELAY) CLKOUT_DIV[1];
CLKOUT2 <= #(CLK2_DELAY) CLKOUT_DIV[2];
CLKOUT3 <= #(CLK3_DELAY) CLKOUT_DIV[3];
CLKOUT4 <= #(CLK4_DELAY) CLKOUT_DIV[4];
CLKOUT5 <= #(CLK5_DELAY) CLKOUT_DIV[5];
end
//##############
//#DUMMY DRIVES
//##############
assign CLKFBOUT=CLKIN1;
assign LOCKED=1'b0;
endmodule // PLLE2_BASE
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; long long p(long long b, long long e) { if (e == 0) return 1; if (e == 1) return b; if (e & 1) { return ((b % 998244353) * p((b * b) % 998244353, e / 2)) % 998244353; } return (p((b * b) % 998244353, e / 2)) % 998244353; } int32_t main() { long long n, m; cin >> n >> m; cout << p(2, (m + n)); }
|
#include <bits/stdc++.h> using namespace std; int main() { long pos = 0; long long distance; int n, flag = 1; char dir[20]; cin >> n; for (int j = 0; j < n; j++) { cin >> distance >> dir; if (pos == 0 && strcmp(dir, South ) != 0) { flag = 0; } else if (pos == 20000 && strcmp(dir, North ) != 0) { flag = 0; } else { if (strcmp(dir, South ) == 0) { pos = pos + distance; if (pos > 20000) flag = 0; } else if (strcmp(dir, North ) == 0) { pos = pos - distance; if (pos < 0) { flag = 0; } } } } if (pos) flag = 0; if (flag) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; cin >> a >> b >> c >> d; if (a != d) { cout << 0; } else if (c && !a) { cout << 0; } else { cout << 1; } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_datrom.v when simulating
// the core, upd77c25_datrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_datrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [15 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1536),
.C_READ_DEPTH_B(1536),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1536),
.C_WRITE_DEPTH_B(1536),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//-----------------------------------------------------------------------------
// Title : Finite Precision Symmetric Reduction module
// Introduces 2 clock cycles of latency
`timescale 1 ns / 100 ps
module FinitePrecRndNrst
#(
parameter C_IN_SZ=37,
C_OUT_SZ=16,
C_FRAC_SZ=15
)
( input wire CLK,
input wire RST,
input wire signed [C_IN_SZ-1:0] datain,
input wire dataval,
output wire signed [C_OUT_SZ-1:0] dataout,
output reg clip_inc,
output reg dval_out
);
wire sign;
wire signed [C_IN_SZ-1:0] rc_val;
reg signed [C_IN_SZ-1:0] data_round_f;
wire signed [C_IN_SZ-C_FRAC_SZ-1:0] data_round;
reg signed [C_OUT_SZ-1:0] data_rs;
reg dataval_d1;
reg sign_d1;
assign sign = datain[C_IN_SZ-1];
assign rc_val = { {(C_IN_SZ-C_FRAC_SZ){1'b0}}, 1'b1, {(C_FRAC_SZ-1){1'b0}} };
always @(posedge CLK or posedge RST)
if(RST)
begin
data_round_f <= 'b0;
dataval_d1 <= 1'b0;
sign_d1 <= 1'b0;
dval_out <= 1'b0;
end
else
begin
data_round_f <= datain + rc_val;
dataval_d1 <= dataval;
dval_out <= dataval_d1;
sign_d1 <= sign;
end
assign data_round = data_round_f[C_IN_SZ-1:C_FRAC_SZ];
// saturation / clipping
always @(posedge CLK or posedge RST)
if(RST)
begin
data_rs <= 'b0;
clip_inc <= 1'b0;
end
else
begin
clip_inc <= 1'b0;
// clipping condition
if(
(
(C_IN_SZ-C_FRAC_SZ != C_OUT_SZ) &&
(~(&data_round[C_IN_SZ-C_FRAC_SZ-1 : C_OUT_SZ-1])) ==
(|(data_round[C_IN_SZ-C_FRAC_SZ-1 : C_OUT_SZ-1]))
)
|| // special case
(
(C_IN_SZ-C_FRAC_SZ == C_OUT_SZ) &&
(data_round[C_IN_SZ-C_FRAC_SZ-1] != sign_d1) &&
data_round != {C_OUT_SZ{1'b0}}
)
)
begin
// clipping counter
if(dataval_d1)
clip_inc <= 1'b1;
if(sign_d1)
// do saturation
data_rs <= -(2**(C_OUT_SZ)/2)+1;
else
// do saturation
data_rs <= (2**(C_OUT_SZ)/2)-1;
end
else
data_rs <= data_round[C_OUT_SZ-1:0];
end
assign dataout = data_rs;
//always @(posedge CLK or posedge RST)
// if(RST)
// begin
// dataout <= 0;
// end
// else
// begin
// dataout <= data_rs;
// end
endmodule
|
// file: ocxo_clk_pll.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______597.520____892.144
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary__________10.000___________0.00100
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ocxo_clk_pll,clk_wiz_v5_1,{component_name=ocxo_clk_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_ONCHIP,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ocxo_clk_pll
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked
);
ocxo_clk_pll_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.resetn(resetn),
.locked(locked)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Z = (int)2e6 + 111; const int inf = (int)1e9 + 111; const long long llinf = (long long)1e18 + 5; const int MOD = (int)1e9 + 7; vector<pair<int, int> > g[Z]; vector<long long> d[Z], pref[Z]; long long f[Z]; void dfs(int v) { for (auto to : g[v]) { dfs(to.first); } vector<long long> v1, v2; int f = 0; for (auto to : g[v]) { f++; for (int i = 0; i < (int)d[to.first].size(); ++i) { if (f % 2) v1.push_back(d[to.first][i] + to.second); if (f % 2 == 0) v2.push_back(d[to.first][i] + to.second); } } merge((v1).begin(), (v1).end(), (v2).begin(), (v2).end(), back_inserter(d[v])); d[v].resize((int)d[v].size() + 1); for (int i = (int)d[v].size() - 1; i >= 1; --i) { d[v][i] = d[v][i - 1]; } d[v][0] = 0; } int main() { srand(time(0)); int n, m; scanf( %d%d , &n, &m); for (int i = 1; i < n; ++i) { int w; scanf( %d , &w); g[(i + 1) / 2].push_back(make_pair(i + 1, w)); f[i + 1] = w; } dfs(1); for (int i = 1; i <= n; ++i) { pref[i].resize((int)d[i].size()); pref[i][0] = d[i][0]; for (int j = 1; j < (int)d[i].size(); ++j) { pref[i][j] = pref[i][j - 1] + d[i][j]; } } while (m--) { long long v, h; scanf( %I64d%I64d , &v, &h); int pr = -1; long long ans = 0, len = 0; while (v) { int cntL = --upper_bound((d[2 * v]).begin(), (d[2 * v]).end(), h - len - f[2 * v]) - d[2 * v].begin(); int cntR = --upper_bound((d[2 * v + 1]).begin(), (d[2 * v + 1]).end(), h - len - f[2 * v + 1]) - d[2 * v + 1].begin(); if (pr == -1 && cntL != -1) ans += 1LL * h * (cntL + 1) - (len + f[2 * v]) * (cntL + 1) - pref[2 * v][cntL]; if (pr == -1 && cntR != -1) ans += 1LL * h * (cntR + 1) - (len + f[2 * v + 1]) * (cntR + 1) - pref[2 * v + 1][cntR]; if (pr == 0 && cntL != -1) ans += 1LL * h * (cntL + 1) - (len + f[2 * v]) * (cntL + 1) - pref[2 * v][cntL]; if (pr == 1 && cntR != -1) ans += 1LL * h * (cntR + 1) - (len + f[2 * v + 1]) * (cntR + 1) - pref[2 * v + 1][cntR]; if (len < h) ans += h - len; len += f[v]; pr = v % 2 ^ 1; v /= 2; } printf( %I64d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long A; vector<pair<long long, int> > ls; vector<long long> M2[100000]; vector<long long> ls2; long long my_stp(long long first, int stp) { if (stp == 0) { return 1ll; } long long res = my_stp(first, stp / 2); res = res * res; if (stp & 1) { res = res * first; } return res; } inline pair<bool, long long> sqrtn(long long first, int stp) { long long t = (long long)pow((long double)first, (long double)1 / stp); for (long long k = max(2ll, t - 1); k <= t + 1; k++) { if (my_stp(k, stp) == first) { return make_pair(true, k); } } return make_pair(false, 0ll); } inline bool is_prime(long long first) { for (long long i = 2; i * i <= first; i++) { if (first % i == 0) return false; } return true; } void obr(long long term, int id) { for (int i = 1; (1ll << i) <= term - 1; i++) { pair<bool, long long> sq = sqrtn(term - 1, i); if (sq.first && is_prime(sq.second)) { ls2.push_back(sq.second); M2[id].push_back(sq.second); break; } } } vector<long long> ls3; void bct(int k, long long mul, int id) { if (k == (int)(ls).size()) { obr(mul, id); ls3[id] = mul; return; } for (int j = 0; j <= ls[k].second; j++) { bct(k + 1, mul, id * (ls[k].second + 1) + j); mul *= ls[k].first; } } vector<pair<int, int> > G[100000]; void bct2(int k, int mul1, int mul2) { if (k == (int)(ls).size()) { if (mul2 != mul1) G[mul1].push_back(make_pair(mul2 - mul1, mul2)); return; } for (int j = 0; j <= ls[k].second; j++) { for (int j1 = j; j1 <= ls[k].second; j1++) { bct2(k + 1, mul1 * (ls[k].second + 1) + j, mul2 * (ls[k].second + 1) + j1); } } } int main() { cin >> A; long long cur = A; for (long long i = 2; i * i <= cur; i++) { int cnt = 0; while (cur % i == 0) { cnt++; cur /= i; } if (cnt) { ls.push_back(make_pair(i, cnt)); } } if (cur > 1) { ls.push_back(make_pair(cur, 1)); } int szls3 = 1; for (auto first : ls) { szls3 *= (first.second + 1); } ls3.resize(szls3); bct(0, (long long)1, 0); { sort((ls2).begin(), (ls2).end()), ls2.resize(unique((ls2).begin(), (ls2).end()) - ls2.begin()); }; bct2(0, 0, 0); vector<vector<int> > DP((int)(ls3).size(), vector<int>((int)(ls2).size() + 1, 0)); DP[0][0] = 1; for (int first = 0; first < (int)(ls3).size(); first++) { for (auto& second : M2[first]) { second = lower_bound((ls2).begin(), (ls2).end(), second) - ls2.begin(); } } for (int i = 0; i < (int)(ls3).size(); i++) { for (int j = 0; j < (int)(ls2).size(); j++) { DP[i][j + 1] += DP[i][j]; } for (auto first : G[i]) { for (int second : M2[first.first]) { DP[first.second][second + 1] += DP[i][second]; } } } cout << DP[(int)(ls3).size() - 1][(int)(ls2).size()] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int i, j; if (k == 1 && n == 1) { cout << a ; return 0; } if (k > n || (k == 1)) { cout << -1; return 0; } i = 1; while (n - i >= k - 2) { cout << char( a + !(i % 2)); ++i; } for (i = 2; i < k; i++) cout << char( a + i); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; struct node { long long x, s[8]; int id; } a[N]; int n, p, t; long long f[N][(1 << 8) + 5]; bool cmp(node a, node b) { return a.x > b.x; } int main() { scanf( %d%d%d , &n, &p, &t); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i].x); a[i].id = i; } for (int i = 1; i <= n; i++) for (int j = 1; j <= p; j++) scanf( %lld , &a[i].s[j]); sort(a + 1, a + n + 1, cmp); memset(f, -1, sizeof(f)); f[0][0] = 0; for (int i = 1; i <= n; i++) { for (int j = 0; j < (1 << p); j++) { f[i][j] = f[i - 1][j]; int sum = 0; for (int k = 0; k < p; k++) if (j & (1 << k)) sum++; int tmp = i - 1 - sum; if (tmp < t && f[i - 1][j] != -1) f[i][j] += a[i].x; for (int k = 0; k < p; k++) { if (((j & (1 << k))) && f[i - 1][j ^ (1 << k)] != -1) f[i][j] = max(f[i][j], f[i - 1][j ^ (1 << k)] + a[i].s[k + 1]); } } } printf( %lld , f[n][(1 << p) - 1]); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:54:48 02/29/2016
// Design Name:
// Module Name: DivFrec
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DivFrec(clk,rst,div,clkd,clk_1kHz);
input wire clk,rst;
input wire [10:0]div;
output wire clkd;
output wire clk_1kHz;
reg [10:0]q = 0;
reg cd = 0;
reg [15:0]q_1kHz = 0;
reg cd_1kHz = 0;
// Para generar el clock dividido variable a partir de la cuenta
always@(posedge clk, posedge rst)
if (rst)
begin
q <= 0;
cd <=0;
end
else
if (q==div)
begin
q <= 0;
cd <= ~cd;
end
else
q <= q + 11'b1;
assign clkd = cd;
// Para generar el clock dividido fijo de 1 kHz
always@(posedge clk, posedge rst)
if (rst)
begin
q_1kHz <= 0;
cd_1kHz <=0;
end
else
if (q_1kHz==16'd49999)
begin
q_1kHz <= 0;
cd_1kHz <= ~cd_1kHz;
end
else
q_1kHz <= q_1kHz + 16'b1;
assign clk_1kHz = cd_1kHz;
endmodule
|
// $Id: c_decr.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic modulo decrementer (i.e., decrementer with wraparound)
module c_decr
(data_in, data_out);
`include "c_functions.v"
parameter width = 3;
parameter [0:width-1] min_value = 0;
parameter [0:width-1] max_value = (1 << width) - 1;
localparam num_values = max_value - min_value + 1;
localparam cwidth = clogb(num_values);
// operand inputs
input [0:width-1] data_in;
// sum output
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire carry;
assign carry = ~|data_in[(width-cwidth):width-1];
wire wrap;
assign wrap = (data_in[(width-cwidth):width-1] ==
min_value[(width-cwidth):width-1]);
generate
if((1 << cwidth) == num_values)
begin
// if the range is a power of two, we can take advantage of natural
// wraparound for the LSBs
assign data_out[(width-cwidth):width-1]
= data_in[(width-cwidth):width-1] - 1'b1;
end
else
begin
// if the range is not a power of two, we need to implement
// explicit wraparound
assign data_out[(width-cwidth):width-1]
= wrap ?
max_value[(width-cwidth):width-1] :
(data_in[(width-cwidth):width-1] - 1'b1);
end
if(width > cwidth)
begin
if(min_value[0:(width-cwidth)-1] == max_value[0:(width-cwidth)-1])
begin
// if the MSBs are identical for the first and last value, we
// never need to change them
assign data_out[0:(width-cwidth)-1]
= data_in[0:(width-cwidth)-1];
end
else
begin
// if the first and last value have differing MSBs, we need to
// adjust them whenever either the LSBs overflow or wraparound
// occurs
assign data_out[0:(width-cwidth)-1]
= data_in[0:(width-cwidth)-1] - carry + wrap;
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o31a (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
|
#include <bits/stdc++.h> int main() { int n, m, x, nn, j, mm, y, z, i, tmp, p; int a, b; scanf( %d%d%d%d%d%d , &nn, &mm, &x, &y, &z, &p); for (j = 1; j <= p; j++) { n = nn; m = mm; scanf( %d%d , &a, &b); x %= 4; z %= 4; if (y % 2 == 0) { for (i = 1; i <= (x + 4 - z) % 4; i++) { tmp = a; a = b; b = n - tmp + 1; tmp = n; n = m; m = tmp; } printf( %d %d n , a, b); } else { for (i = 1; i <= (x + z) % 4; i++) { tmp = a; a = b; b = n - tmp + 1; tmp = n; n = m; m = tmp; } printf( %d %d n , a, m - b + 1); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int b[200005]; vector<int> a; cin >> n; a.push_back(31); a.push_back(28); a.push_back(31); a.push_back(30); a.push_back(31); a.push_back(30); a.push_back(31); a.push_back(31); a.push_back(30); a.push_back(31); a.push_back(30); a.push_back(31); for (int i = 0; i < n; i++) { cin >> b[i]; } for (int i = 0; i < 12; i++) { int count = 0, f = 0; for (int j = 0; j < n; j++) { if ((i + j) % 12 == 1) { if (a[(i + j) % 12] == b[j]) continue; else { if (a[(i + j) % 12] == 28 && b[j] == 29 && count == 0) { count = 1; continue; } } } if (a[(i + j) % 12] != b[j]) { f = 1; break; } } if (f == 0) { cout << YES << endl; return 0; } } cout << NO << endl; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverybkb_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 512;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./contact_discoverybkb_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverybkb(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd512;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
contact_discoverybkb_ram contact_discoverybkb_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { x = 0; bool f = 0; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = 1; for (; isdigit(c); c = getchar()) x = x * 10 + (c ^ 48); if (f) x = -x; } template <typename F> inline void write(F x, char ed = n ) { static short st[30]; short tp = 0; if (x < 0) putchar( - ), x = -x; do st[++tp] = x % 10, x /= 10; while (x); while (tp) putchar( 0 | st[tp--]); putchar(ed); } template <typename T> inline void Mx(T &x, T y) { x < y && (x = y); } template <typename T> inline void Mn(T &x, T y) { x > y && (x = y); } const int P = 1e9 + 9; const int N = 200, M = N * N; long long inv[N]; int f[N], siz[N], deg[N]; int h[N], ne[M << 1], to[M << 1], tot, m, n; int vis[N], val[N], g[N][N]; inline void adde(int x, int y) { ne[++tot] = h[x], to[h[x] = tot] = y; } inline void add(int &x, int y) { x += y, x >= P && (x -= P); } vector<int> v; long long Inv[N], fac[N]; long long C(long long n, long long m) { return fac[n] * Inv[m] % P * Inv[n - m] % P; } void perwork(void) { Inv[0] = fac[0] = 1; for (int i = 1; i <= n; i++) Inv[i] = Inv[i - 1] * inv[i] % P, fac[i] = fac[i - 1] * i % P; } void dfs(int x, int fa) { memset(g[x], 0, sizeof(g[x])); siz[x] = g[x][0] = 1; for (int i = h[x]; i; i = ne[i]) { int y = to[i]; if (!vis[y] || y == fa) continue; dfs(y, x); for (int j = siz[x] + siz[y]; j >= 0; j--) for (int k = min(siz[y], j); k >= 1 && j - k <= siz[x]; k--) add(g[x][j], 1ll * g[x][j - k] * g[y][k] % P * C(j, k) % P); siz[x] += siz[y]; } g[x][siz[x]] = g[x][siz[x] - 1]; } void efs(int x) { vis[x] = 0; for (int i = h[x]; i; i = ne[i]) if (vis[to[i]]) efs(to[i]); } void getans(int x, int fa) { v.push_back(x); for (int i = h[x]; i; i = ne[i]) if (vis[to[i]] && to[i] != fa) getans(to[i], x); } int main() { read(n), read(m); for (int i = 1, x, y; i <= m; i++) { read(x), read(y), deg[x]++, deg[y]++; adde(x, y), adde(y, x); } queue<int> q; for (int i = 1; i <= n; i++) if (deg[i] <= 1) q.push(i), vis[i] = 1; while (q.size()) { int x = q.front(); q.pop(); for (int i = h[x]; i; i = ne[i]) { int y = to[i]; deg[y]--; if (!vis[y] && deg[y] <= 1) vis[y] = 1, q.push(y); } } inv[0] = inv[1] = 1; for (int i = 2; i <= n; i++) inv[i] = (P - P / i) * inv[P % i] % P; f[0] = 1; perwork(); for (int i = 1; i <= n; i++) { if (!vis[i] || deg[i] != 1) continue; dfs(i, 0); for (int j = n; j >= 0; j--) for (int k = siz[i]; k >= 1; k--) add(f[j], 1ll * f[j - k] * g[i][k] % P * C(j, k) % P); efs(i); } for (int i = 1; i <= n; i++) { if (!vis[i]) continue; v.clear(), getans(i, 0); for (int j = 0; j <= n; j++) val[j] = 0; int rt = i; for (auto t : v) { dfs(t, 0); rt = t; for (int j = 0; j <= siz[t]; j++) add(val[j], g[t][j]); } for (int j = 0; j <= siz[rt]; j++) val[j] = val[j] * inv[siz[rt] - j] % P; for (int j = n; j >= 0; j--) for (int k = siz[rt]; k >= 1; k--) add(f[j], 1ll * f[j - k] * val[k] % P * C(j, k) % P); efs(i); } for (int i = 0; i <= n; i++) write(f[i]); return 0; }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* blackbox *)
module box(
(* invertible_pin="INV_A" *)
input wire A,
input wire B,
(* invertible_pin="INV_C" *)
input wire C,
input wire D,
output wire Y
);
parameter [0:0] INV_A = 1'b0;
parameter [0:0] INV_C = 1'b0;
endmodule
module top(
input wire [3:0] di,
output wire do
);
wire [3:0] d;
\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
\$_NOT_ n2 (.A(di[2]), .Y(d[2]));
\$_NOT_ n3 (.A(di[3]), .Y(d[3]));
box #(.INV_A(1'b1)) the_box (
.A (d[0]),
.B (d[1]),
.C (d[2]),
.D (d[3]),
.Y (do)
);
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifndef _NO_FFS
// Async reset, enable.
module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// Async set and reset, enable.
module \$_DFFSRE_NPPP_ (input D, C, E, S, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFSRE_PPPP_ (input D, C, E, S, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// Sync reset, enable.
module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// Latches with reset.
module \$_DLATCH_NP0_ (input E, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DLATCH_PP0_ (input E, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DLATCH_NP1_ (input E, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DLATCH_PP1_ (input E, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// Latches with set and reset.
module \$_DLATCH_NPP_ (input E, S, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DLATCH_PPP_ (input E, S, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; int k; cin >> n >> k; int ar[n]; for (int i = 0; i < n; i++) { cin >> ar[i]; } sort(ar, ar + n); long long lista[n]; int cantidad[n]; int index = 0; for (int i = 0; i < n; i++) { if (i == 0) { lista[i] = ar[i]; cantidad[index] = 1; } else if (ar[i] == ar[i - 1]) { cantidad[index]++; } else { index++; cantidad[index] = 1; lista[index] = ar[i]; } } int diferentes = index + 1; long long L[diferentes]; long long R[diferentes]; int LeftAmount[diferentes]; int RightAmount[diferentes]; L[0] = 0; LeftAmount[0] = 0; R[diferentes - 1] = 0; RightAmount[diferentes - 1] = 0; for (int i = 1; i < diferentes; i++) { LeftAmount[i] = LeftAmount[i - 1] + cantidad[i - 1]; L[i] = L[i - 1] + (lista[i] - 1 - lista[i - 1]) * cantidad[i - 1]; L[i] += (lista[i] - 1 - (lista[i - 1] - 1)) * LeftAmount[i - 1]; } for (int i = diferentes - 2; i >= 0; i--) { RightAmount[i] = RightAmount[i + 1] + cantidad[i + 1]; R[i] = R[i + 1] + (lista[i + 1] - (lista[i] + 1)) * cantidad[i + 1]; R[i] += (lista[i + 1] - lista[i]) * RightAmount[i + 1]; } long long ans = 1000000000000000005; for (int i = 0; i < diferentes; i++) { if (cantidad[i] >= k) { ans = 0; } else { int needed = k - cantidad[i]; if ((LeftAmount[i] >= needed) && (RightAmount[i] >= needed)) { ans = min(min(L[i], R[i]) + needed, ans); } else if (LeftAmount[i] >= needed) { ans = min(L[i] + needed, ans); } else if (RightAmount[i] >= needed) { ans = min(R[i] + needed, ans); } else { ans = min(L[i] + R[i] + needed, ans); } } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using str = string; using pi = pair<int, int>; using pl = pair<ll, ll>; using pd = pair<ld, ld>; using vi = vector<int>; using vb = vector<bool>; using vl = vector<ll>; using vd = vector<ld>; using vs = vector<str>; using vpi = vector<pi>; using vpl = vector<pl>; using vpd = vector<pd>; str Tout[2] = { NO , YES }; str tout[2] = { No , Yes }; int main() { ll n, k; cin >> n >> k; ll a[n + 17]; for (int i = (0); i < (n); i++) cin >> a[i]; if (k == 2) { cout << max(a[0], a[n - 1]); return 0; } sort(a, a + n); if (k == 1) cout << a[0]; else cout << a[n - 1]; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios::sync_with_stdio(false); cin.tie(0); int T; cin >> T; while (T--) { int n, k; cin >> n >> k; string N = to_string(n); string ans = 99999999999999 ; set<char> S; for (auto c : N) { S.insert(c); } if ((int)S.size() <= k) { cout << N << n ; continue; } for (int d = 0; d < (int)N.size(); d++) { string base = N.substr(0, d); for (int v = N[d] - 0 + 1; v <= 9; v++) { string s = base + to_string(v); set<char> have; for (int i = 0; i < d; i++) { have.insert(N[i]); } have.insert((char)(v + 0 )); if ((int)have.size() > k) { continue; } if ((int)have.size() < k) { have.insert( 0 ); } while (s.size() < N.size()) { s += *have.begin(); } assert(s >= N); ans = min(ans, s); } } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> struct Node { Node(int v = 1, int pos = 1e9) { min = (v == 1 ? int(1e9) : pos); } Node(Node l, Node r) { min = std::min(l.min, r.min); } int min; }; template <class i_t, class e_t> class SegmentTree { public: void init(std::vector<e_t> base) { n = base.size(); tree.resize(2 * n); for (int i = 0; i < n; i++) { tree[i + n] = i_t(base[i], i); } for (int i = n - 1; i > 0; i--) { tree[i] = i_t(tree[i + i], tree[i + i + 1]); } } i_t qry(int l, int r) { i_t lp, rp; for (l += n, r += n; l < r; l /= 2, r /= 2) { if (l & 1) lp = i_t(lp, tree[l++]); if (r & 1) rp = i_t(tree[--r], rp); } return i_t(lp, rp); } void upd(int x, e_t v) { x += n; tree[x] = i_t(v, x - n); build(x); } private: int n; std::vector<i_t> tree; void build(int x) { for (x /= 2; x > 0; x /= 2) { tree[x] = i_t(tree[x + x + 1], tree[x + x]); } } }; struct Bucket { int n; SegmentTree<Node, int> tree; void init(int n) { this->n = n; tree.init(std::vector<int>(n, 0)); } void erase(int pos) { tree.upd(pos, 0); } int insert(int pos) { int x = tree.qry(pos, n).min; int ans = 0; if (x >= n) { x = tree.qry(0, pos).min; ans += n - pos + x; } else { ans += x - pos; } tree.upd(x, 1); return ans; } }; int main() { int h, m, n; std::cin >> h >> m >> n; int size = 1; for (int i = 2; i <= h; i++) { if (h % i == 0 && m % i == 0) { size = i; } } std::vector<Bucket> buckets(size); std::vector<int> hashBucket(h, 0); std::vector<int> posBucket(h, 0); std::map<int, std::pair<int, int> > idBucket; for (int i = 0; i < size; i++) { for (int j = 0, pos = i; j < h / size; j++, pos = (pos + m) % h) { posBucket[pos] = j; hashBucket[pos] = i; } buckets[i].init(h / size); } long long ans = 0; for (int i = 0; i < n; i++) { char t; int id; scanf( %c %d , &t, &id); if (t == + ) { int hash; scanf( %d , &hash); int got = buckets[hashBucket[hash]].insert(posBucket[hash]); idBucket[id] = std::pair<int, int>(hashBucket[hash], (posBucket[hash] + got) % (h / size)); ans += got; } else { auto it = idBucket.find(id); buckets[it->second.first].erase(it->second.second); idBucket.erase(it); } } std::cout << ans << std::endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, k; cin >> n >> k; string s; cin >> s; sort(s.begin(), s.end()); map<char, int> store; for (int i = 0; i < n; i++) { store[s[i]]++; } if (store.size() == 1) { int temp = n / k; if (n % k != 0) temp++; for (int i = 0; i < temp; i++) cout << s[0]; } else if (store.size() == 2 && store[s[0]] == k) { cout << s[0]; int temp = n / k; if (n % k != 0) temp++; for (int i = 0; i < temp - 1; i++) cout << s[k]; } else { if (s[0] != s[k - 1]) cout << s[k - 1]; else { for (int i = k - 1; i < n; i++) cout << s[i]; } } cout << n ; } return 0; }
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build Fri Jun 26 16:35:25 MDT 2015
// Date : Mon Nov 30 13:52:22 2015
// Host : centennial.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
// Command : write_verilog -force -mode synth_stub
// /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7900/Atari7900.srcs/sources_1/ip/DIGDUG_ROM_1/DIGDUG_ROM_stub.v
// Design : DIGDUG_ROM
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
module DIGDUG_ROM(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[13:0],douta[7:0]" */;
input clka;
input [13:0]addra;
output [7:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int64_t M = 1e2 + 5; int64_t n, t[M], w[M], dp[M][20005], totalW; int64_t solve(int64_t idx, int64_t wt) { if (idx > n) { if (wt >= 0) return 0; return 1e9; } if (dp[idx][1001 + wt] != -1) return dp[idx][1001 + wt]; int64_t ans = t[idx] + solve(idx + 1, wt + t[idx]); ans = min(ans, solve(idx + 1, wt - w[idx])); return dp[idx][1001 + wt] = ans; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int64_t i = 1; i <= n; i++) cin >> t[i] >> w[i]; memset(dp, -1, sizeof(dp)); cout << solve(1, 0); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i; cin >> n; if (n == 1) cout << n; else { cout << n << ; for (i = 1; i < n - 1; i++) cout << i << ; cout << n - 1; } return 0; }
|
/*
--------------------------------------------------------------------------
Pegasus - Copyright (C) 2012 Gregory Matthew James.
This file is part of Pegasus.
Pegasus is free; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Pegasus is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- Project Code : pegasus
-- Module Name : peg_l2_mac_pause_cntr
-- Author : mammenx
-- Associated modules:
-- Function : This block is a counter used to generate pause
intervals.
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module peg_l2_mac_pause_cntr #(
parameter BPCLK = 64, //Bits per clock cycle
parameter MAC_SPEED = 100000000 //bps
)
(
input clk,
input rst_n,
//Config
input pause_en,
//Inputs from Parser
input pause_time_valid,
input [15:0] pause_time,
//Pause Status
output pause_valid
);
//----------------------- Global parameters Declarations ------------------
localparam PAUSE_SCALE_FAC = $clog(512 / BPCLK);
localparam CNTR_W = 16 + PAUSE_SCALE_FAC;
//----------------------- Input Declarations ------------------------------
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
reg [15:0] pause_time_f;
reg [CNTR_W-1:0] pause_cntr_f;
//----------------------- Internal Wire Declarations ----------------------
//----------------------- Input/Output Registers --------------------------
//----------------------- Start of Code -----------------------------------
always@(posedge clk, negedge rst_n)
begin
if(~rst_n)
begin
pause_time_f <= 0;
pause_cntr_f <= 0;
end
else
begin
//Register the pause time from parser
pause_time_f <= pause_time_valid ? pause_time : pause_time_f;
//Counter logic
if(pause_valid)
begin
pause_cntr_f <= 0;
end
else if(pause_en)
begin
pause_cntr_f <= pause_cntr_f + 1'b1;
end
else
begin
pause_cntr_f <= pause_cntr_f;
end
end
end
//Generate status
assign pause_en = (pause_time_f > pause_cntr_f[CNTR_W-1:PAUSE_SCALE_FAC]) ? 1'b1 : 1'b0;
endmodule // peg_l2_mac_pause_cntr
/*
--------------------------------------------------------------------------
-- <Header>
-- <Log>
[02-07-2014 12:52:58 AM][mammenx] Initial version
[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file
--------------------------------------------------------------------------
*/
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; cin >> a >> b >> c >> d; if (abs(a + c - b - d) > 1) { cout << NO n ; } else { vector<int> v(a + b + c + d); if (a + c > b + d) { for (int i = 0; i < v.size(); i += 2) { if (a) { v[i] = 0; a--; } else { v[i] = 2; c--; } } for (int i = 1; i < v.size(); i += 2) { if (b) { v[i] = 1; b--; } else { v[i] = 3; d--; } } } else { for (int i = 1; i < v.size(); i += 2) { if (a) { v[i] = 0; a--; } else { v[i] = 2; c--; } } for (int i = 0; i < v.size(); i += 2) { if (b) { v[i] = 1; b--; } else { v[i] = 3; d--; } } } bool check = true; for (int i = 0; i < (int)v.size() - 1; i++) { if (abs(v[i] - v[i + 1]) != 1) { check = false; break; } } if (a + c == b + d && check == false) { for (int i = 0; i < (int)v.size() - 1; i += 2) { swap(v[i], v[i + 1]); } check = true; for (int i = 0; i < (int)v.size() - 1; i++) { if (abs(v[i] - v[i + 1]) != 1) { check = false; break; } } } if (check) { cout << YES n ; for (int i : v) cout << i << ; cout << n ; } else cout << NO ; } return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:40 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_rst_ps7_0_100M_1_stub.v
// Design : zynq_design_1_rst_ps7_0_100M_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include <bits/stdc++.h> int main() { int i, j, a = 0, b = 0, n, y; char x[10][10]; for (i = 0; i < 8; i++) scanf( %s , x[i]); for (i = 0; i < 8; i++) { n = 0; for (j = 0; j < 8; j++) { if (x[i][j] == B ) { n++; } } if (n == 8) a++; } for (i = 0; i < 8; i++) { n = 0; for (j = 0; j < 8; j++) { if (x[j][i] == B ) { n++; } } if (n == 8) b++; } y = a + b; if (a == 8) y = 8; printf( %d , y); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31OI_SYMBOL_V
`define SKY130_FD_SC_HS__A31OI_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a31oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double EPS = (1e-10); int main() { int tc; cin >> tc; while (tc--) { int n; cin >> n; vector<pair<int, int> > stud(n); for (int i = 0; i < n; i++) { int a, b; cin >> a >> b; stud[i] = make_pair(a, b); } int ans[n]; ans[0] = stud[0].first; int cs = ans[0] + 1; for (int i = 1; i < n; i++) { if (cs < stud[i].first) { ans[i] = stud[i].first; cs = ans[i] + 1; } else { if (cs <= stud[i].second) { ans[i] = cs; cs++; } else { ans[i] = 0; } } } for (int i = 0; i < n; i++) cout << ans[i] << ; cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long n, k, l, a[1000010], m, p, q, b[1000010], d, c[1000010], f[1000010], g[1000010], ans; struct BIT { long long a[1000010]; void clear() { memset(a, 0, sizeof(a)); } void add(int x, long long v) { for (; x <= 1000010 - 5; x += x & (-x)) a[x] = (a[x] + v + mod) % mod; } long long get(int x) { long long ans = 0; for (; x; x -= x & (-x)) ans = (ans + a[x]) % mod; return ans; } } tr; int main() { scanf( %lld%lld%lld , &n, &l, &k); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]), b[i] = a[i]; sort(b + 1, b + n + 1); d = unique(b + 1, b + n + 1) - b - 1; for (int i = 1; i <= n; i++) a[i] = lower_bound(b + 1, b + d + 1, a[i]) - b; m = l / n; p = l % n; if (!p) { m--; p += n; } q = max(0ll, m - k + 1); q %= mod; int cnt = 0; for (int i = 1; i <= k - 1; i++) for (int j = 1; j <= n; j++) c[++cnt] = a[j]; for (int i = 1; i <= p; i++) c[++cnt] = a[i]; for (int i = cnt - p + 1; i <= cnt; i++) f[i] = 1, tr.add(c[i], f[i]); for (int i = k - 1; i; --i) { for (int j = 1; j <= n; j++) { int pos = (i - 1) * n + j; f[pos] = (tr.get(1000010 - 5) - tr.get(c[pos] - 1) + mod) % mod; } for (int j = 1; j <= n; j++) { int pos = (i - 1) * n + j; if (pos + n <= cnt) tr.add(c[pos + n], -f[pos + n]); tr.add(c[pos], f[pos]); } } for (int i = max(cnt - p - m * n + 1, 1ll); i <= cnt; i++) ans = (ans + f[i]) % mod; memset(c, 0, sizeof(c)); tr.clear(); cnt = 0; for (int i = 1; i <= k; i++) for (int j = 1; j <= n; j++) c[++cnt] = a[j]; for (int i = cnt - n + 1; i <= cnt; i++) g[i] = 1, tr.add(c[i], g[i]); for (int i = k - 1; i; --i) { for (int j = 1; j <= n; j++) { int pos = (i - 1) * n + j; g[pos] = (tr.get(1000010 - 5) - tr.get(c[pos] - 1) + mod) % mod; } for (int j = 1; j <= n; j++) { int pos = (i - 1) * n + j; tr.add(c[pos + n], -g[pos + n]); tr.add(c[pos], g[pos]); } } long long tmp = 0; for (int i = 1; i <= min(m, k - 1); i++) { for (int j = 1; j <= n; j++) { int pos = (k - i) * n + j; tmp = (tmp + g[pos]) % mod; } ans = (ans + tmp) % mod; } tmp = 0; for (int i = 1; i <= k; i++) for (int j = 1; j <= n; j++) { int pos = (i - 1) * n + j; tmp = (tmp + g[pos]) % mod; } tmp = tmp * q % mod; ans = (ans + tmp) % mod; printf( %lld n , ans); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/05/2017 10:52:10 AM
// Design Name:
// Module Name: IMM_EXTENDER
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IMM_EXTENDER #(
parameter IMM_MAX_IN_WIDTH = 25 ,
parameter DATA_WIDTH = 32 ,
parameter IMM_FORMAT_SELECT = 3 ,
parameter R_FORMAT = 3'b000 ,
parameter I_FORMAT = 3'b001 ,
parameter S_FORMAT = 3'b010 ,
parameter U_FORMAT = 3'b011 ,
parameter SB_FORMAT = 3'b100 ,
parameter UJ_FORMAT = 3'b101
) (
input [IMM_MAX_IN_WIDTH - 1 : 0] IMM_INPUT ,
input [IMM_FORMAT_SELECT - 1 : 0] IMM_FORMAT ,
output [DATA_WIDTH - 1 : 0] IMM_OUTPUT
);
reg [DATA_WIDTH - 1 : 0] imm_output_reg ;
always@(*)
begin
case(IMM_FORMAT)
R_FORMAT:
begin
imm_output_reg = 32'b0;
end
I_FORMAT:
begin
if(IMM_INPUT[24] == 1'b1)
imm_output_reg = {20'b11111111111111111111,IMM_INPUT[24:13]};
else
imm_output_reg = {20'b0,IMM_INPUT[24:13]};
end
S_FORMAT:
begin
if(IMM_INPUT[24] == 1'b1)
imm_output_reg = {20'b11111111111111111111,IMM_INPUT[24:18],IMM_INPUT[4:0]};
else
imm_output_reg = {20'b0,IMM_INPUT[24:18],IMM_INPUT[4:0]};
end
U_FORMAT:
begin
imm_output_reg = {IMM_INPUT[24:5],12'b0};
end
SB_FORMAT:
begin
if(IMM_INPUT[24] == 1'b1)
imm_output_reg = {20'b11111111111111111111,IMM_INPUT[0],IMM_INPUT[23:18],IMM_INPUT[4:1],1'b0};
else
imm_output_reg = {20'b0,IMM_INPUT[0],IMM_INPUT[23:18],IMM_INPUT[4:1],1'b0};
end
UJ_FORMAT:
begin
if(IMM_INPUT[24] == 1'b1)
imm_output_reg = {12'b111111111111,IMM_INPUT[12:5],IMM_INPUT[13],IMM_INPUT[23:18],IMM_INPUT[17:14],1'b0};
else
imm_output_reg = {12'b0,IMM_INPUT[12:5],IMM_INPUT[13],IMM_INPUT[23:18],IMM_INPUT[17:14],1'b0};
end
default:
begin
imm_output_reg = 32'b0;
end
endcase
end
assign IMM_OUTPUT = imm_output_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_2_V
`define SKY130_FD_SC_MS__AND4BB_2_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND3_PP_BLACKBOX_V
/**
* nand3: 3-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 2; long long arr[N]; long long pos[N]; long long chance[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t, i, j; long long n; cin >> n; for (i = 1; i <= n; i++) { cin >> arr[i]; pos[arr[i]] = i; } long long high = 0, low = 0; long long ans = 0, ind = 0; for (i = 1; i <= n; i++) { if (arr[i] == i) { high++; } else if (arr[i] < i) { high++; ans += i - arr[i]; chance[arr[i] - i + n]++; } else { low++; ans += arr[i] - i; chance[arr[i] - i]++; } } long long prev_ans = ans; for (i = 1; i < n; i++) { long long lst_elem = arr[n - (i - 1)]; long long cur_ans = prev_ans + high - 1 - low - abs(n - lst_elem) + abs(1 - lst_elem); if (cur_ans < ans) { ans = cur_ans; ind = i; } prev_ans = cur_ans; high--; high += chance[i]; low -= chance[i]; low++; } cout << ans << << ind; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR2_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2018 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));; end while(0);
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
int cyc;
int vr;
int va[2];
`ifdef T_NOINLINE
// verilator no_inline_module
`endif
//====
task fun(ref int r, const ref int c);
`ifdef T_NOINLINE
// verilator no_inline_task
`endif
`checkh(c, 32'h1234);
r = 32'h4567;
endtask
initial begin
int ci;
int ri;
ci = 32'h1234;
fun(ri, ci);
`checkh(ri, 32'h4567);
end
//====
task fun_array(ref int af[2], const ref int cf[2]);
`ifdef T_NOINLINE
// verilator no_inline_task
`endif
`checkh(cf[0], 32'h1234);
`checkh(cf[1], 32'h2345);
af[0] = 32'h5678;
af[1] = 32'h6789;
endtask
// Not checkint - element of unpacked array
initial begin
int ca[2];
int ra[2];
ca[0] = 32'h1234;
ca[1] = 32'h2345;
fun_array(ra, ca);
`checkh(ra[0], 32'h5678);
`checkh(ra[1], 32'h6789);
end
//====
sub sub(.clk, .vr, .va);
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 0) begin
vr <= 32'h789;
va[0] <= 32'h89a;
va[1] <= 32'h9ab;
end
else if (cyc == 2) begin
`checkh(vr, 32'h987);
`checkh(va[0], 32'ha98);
`checkh(va[1], 32'ha9b);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub(input clk, ref int vr, ref int va[2]);
always @(posedge clk) begin
vr <= 32'h987;
va[0] <= 32'ha98;
va[1] <= 32'ha9b;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> g[200005]; queue<pair<int, int> > q; int deg[200005], a, n; bool v[200005]; set<int> s[200005]; int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int a, b; scanf( %d%d , &a, &b); g[a].push_back(b); g[b].push_back(a); deg[a]++, deg[b]++; } for (int i = 1; i <= n; i++) if (deg[i] == 1) q.push(pair<int, int>(i, 0)); int c = 0, lst = -1; while (!q.empty()) { int x = q.front().first, d = q.front().second; q.pop(); v[x] = true; lst = x, c++; for (auto y : g[x]) { if (v[y]) continue; deg[y]--; s[y].insert(d + 1); if (deg[y] == 1 and s[y].size() == 1) q.push(pair<int, int>(y, d + 1)); } } if (c < n - 1) a = -1; else { if (c == n - 1) for (int i = 1; i <= n; i++) if (!v[i]) lst = i; if (s[lst].size() > 2) a = -1; else { for (auto e : s[lst]) a += e; } } while (a % 2 == 0) a /= 2; printf( %d n , a); }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 505; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; char dc[] = { R , L , D , U }; string ans; int n; bool grid[MAX][MAX], vis[MAX][MAX]; int dp[MAX][MAX][4]; bool valid(int x, int y, int dir) { return dp[x][y][dir] = ~dp[x][y][dir] ? dp[x][y][dir] : (!x || !y || x > n || y > n) ? 0 : grid[x][y] ? 1 : valid(x + dx[dir], y + dy[dir], dir); } void dfs1(int x, int y) { vis[x][y] = 1; if (!grid[x][y]) ans += 1 , grid[x][y] = 1; for (int i = 0; i < 4; ++i) { int nx = x + dx[i], ny = y + dy[i]; if (vis[nx][ny] || !valid(nx, ny, i)) continue; ans += dc[i]; dfs1(nx, ny); ans += dc[i ^ 1]; } } void dfs0(int x, int y) { grid[x][y] = 0; for (int i = 0; i < 4; ++i) { int nx = x + dx[i], ny = y + dy[i]; if (!grid[nx][ny]) continue; ans += dc[i]; dfs0(nx, ny); ans += dc[i ^ 1]; } ans += 2 ; } int main() { int sx, sy; memset(dp, -1, sizeof dp); cin >> n >> sx >> sy; for (int i = 1; i <= n; ++i) { vis[0][i] = vis[i][0] = vis[0][n + 1] = vis[n + 1][0] = 1; for (int j = 1; j <= n; ++j) scanf( %d , grid[i] + j); } dfs1(sx, sy); dfs0(sx, sy); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) if (grid[i][j]) return puts( NO ), 0; puts( YES ); puts(ans.c_str()); return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Achronix eFPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board/custom chip.
// > Input/Output buffers <
// Input buffer map
module \$__inpad (input I, output O);
PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
endmodule
// > end buffers <
// > Look-Up table <
// > VT: I still think Achronix folks would have chosen a better \
// > logic architecture.
// LUT Map
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
// VT: This is not consistent and ACE will complain: assign Y = ~A[0];
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
end else
if (WIDTH == 2) begin
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
end else
if(WIDTH == 3) begin
LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
end else
if(WIDTH == 4) begin
LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
// > end LUT <
// > Flops <
// DFF flop
module \$_DFF_P_ (input D, C, output Q);
DFF _TECHMAP_REPLACE_
(.q(Q), .d(D), .ck(C));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
/**
* udp_dff$NR_pp$PKG$sN: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$NR_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; scanf( %d%d , &n, &k); int mat[n + 1][n + 1]; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) mat[i][j] = 0; } int br = 0; for (int i = 1; i <= n; i += 2) { for (int j = 1, x = i; j <= n && x <= n; j++, x++) { mat[x][j] = 1; br++; } } for (int i = 3; i <= n; i += 2) { for (int h = 1, j = i; h <= n && j <= n; h++, j++) { mat[h][j] = 1; br++; } } if (br < k) { printf( NO ); return 0; } printf( YES n ); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (k > 0) { if (mat[i][j]) { printf( L ); k--; } else printf( S ); } else printf( S ); } printf( n ); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_V
|
module bemicro
(
// Clock inputs
input wire CLK_FPGA_50M, // CLK 1
input wire RX_CLK, // CLK 4
input wire TX_CLK, // CLK 5
input wire P1, // CLK 12 / Diff CLK 7n
input wire P2, // CLK 13 / Diff CLK 7p
input wire P35, // CLK 14 / Diff CLK 6n
input wire P36, // CLK 15 / Diff CLK 6p
// Extension connector
output wire RESET_EXP_N,
input wire EXP_PRESENT,
inout wire P3,
inout wire P4,
inout wire P5,
inout wire P6,
inout wire P7,
inout wire P8,
inout wire P9,
inout wire P10,
inout wire P11,
inout wire P12,
inout wire P13,
inout wire P14,
inout wire P15,
inout wire P16,
inout wire P17,
inout wire P18,
inout wire P19,
inout wire P20,
inout wire P21,
inout wire P22,
inout wire P23,
inout wire P24,
inout wire P25,
inout wire P26,
inout wire P27,
inout wire P28,
inout wire P29,
inout wire P37,
inout wire P38,
inout wire P39,
inout wire P40,
inout wire P41,
inout wire P42,
inout wire P43,
inout wire P44,
inout wire P45,
inout wire P46,
inout wire P47,
inout wire P48,
inout wire P49,
inout wire P50,
inout wire P51,
inout wire P52,
inout wire P53,
inout wire P54,
inout wire P55,
inout wire P56,
inout wire P57,
inout wire P58,
inout wire P59,
inout wire P60,
// SDRAM
output wire RAM_A0,
output wire RAM_A1,
output wire RAM_A2,
output wire RAM_A3,
output wire RAM_A4,
output wire RAM_A5,
output wire RAM_A6,
output wire RAM_A7,
output wire RAM_A8,
output wire RAM_A9,
output wire RAM_A10,
output wire RAM_A11,
output wire RAM_A12,
output wire RAM_A13,
output wire RAM_BA0,
output wire RAM_BA1,
output wire RAM_RAS_N,
output wire RAM_CAS_N,
output wire RAM_CS_N,
output wire RAM_WS_N,
output wire RAM_CKE,
output wire RAM_CK_N,
output wire RAM_CK_P,
output wire RAM_LDM,
output wire RAM_UDM,
inout wire RAM_LDQS,
inout wire RAM_UDQS,
inout wire RAM_D0,
inout wire RAM_D1,
inout wire RAM_D2,
inout wire RAM_D3,
inout wire RAM_D4,
inout wire RAM_D5,
inout wire RAM_D6,
inout wire RAM_D7,
inout wire RAM_D8,
inout wire RAM_D9,
inout wire RAM_D10,
inout wire RAM_D11,
inout wire RAM_D12,
inout wire RAM_D13,
inout wire RAM_D14,
inout wire RAM_D15,
// Ethernet
// MicroSD card
output wire SD_CLK,
output wire SD_CMD,
inout wire SD_DAT0,
inout wire SD_DAT1,
inout wire SD_DAT2,
inout wire SD_DAT3,
// SPI to temperature sensor (LM71)
output wire TEMP_CS_N,
output wire TEMP_SC,
output wire TEMP_MOSI,
input wire TEMP_MISO,
// Switches / buttons / LEDs
input wire RECONFIG_SW1,
input wire RECONFIG_SW2,
input wire CPU_RST_N,
input wire PBSW_N,
output wire F_LED0,
output wire F_LED1,
output wire F_LED2,
output wire F_LED3,
output wire F_LED4,
output wire F_LED5,
output wire F_LED6,
output wire F_LED7
);
wire clk_in_50m;
wire pllrst;
wire plllock;
wire reset_n;
wire sysclk;
wire sysrst;
wire sysrst_n;
wire [7:0] led;
assign RESET_EXP_N = sysrst_n;
assign F_LED0 = ~led[0];
assign F_LED1 = ~led[1];
assign F_LED2 = ~led[2];
assign F_LED3 = ~led[3];
assign F_LED4 = ~led[4];
assign F_LED5 = ~led[5];
assign F_LED6 = ~led[6];
assign F_LED7 = ~led[7];
assign P3 = 1'bZ;
assign P4 = 1'bZ;
assign P5 = 1'bZ;
assign P6 = 1'bZ;
assign P7 = 1'bZ;
assign P8 = 1'bZ;
assign P9 = 1'bZ;
assign P10 = 1'bZ;
assign P11 = 1'bZ;
assign P12 = 1'bZ;
assign P13 = 1'bZ;
assign P14 = 1'bZ;
assign P15 = 1'bZ;
assign P16 = 1'bZ;
assign P17 = 1'bZ;
assign P18 = 1'bZ;
assign P19 = 1'bZ;
assign P20 = 1'bZ;
assign P21 = 1'bZ;
assign P22 = 1'bZ;
assign P23 = 1'bZ;
assign P24 = 1'bZ;
assign P25 = 1'bZ;
assign P26 = 1'bZ;
assign P27 = 1'bZ;
assign P28 = 1'bZ;
assign P29 = 1'bZ;
// assign P35 = 1'bZ;
// assign P36 = 1'bZ;
assign P37 = 1'bZ;
assign P38 = 1'bZ;
assign P39 = 1'bZ;
assign P40 = 1'bZ;
assign P41 = 1'bZ;
assign P42 = 1'bZ;
assign P43 = 1'bZ;
assign P44 = 1'bZ;
assign P45 = 1'bZ;
assign P46 = 1'bZ;
assign P47 = 1'bZ;
assign P48 = 1'bZ;
assign P49 = 1'bZ;
assign P50 = 1'bZ;
assign P51 = 1'bZ;
assign P52 = 1'bZ;
assign P53 = 1'bZ;
assign P54 = 1'bZ;
assign P55 = 1'bZ;
assign P56 = 1'bZ;
assign P57 = 1'bZ;
assign P58 = 1'bZ;
assign P59 = 1'bZ;
assign P60 = 1'bZ;
assign SD_CLK = 1'b0;
assign SD_CMD = 1'b0;
assign SD_DAT0 = 1'bZ;
assign SD_DAT1 = 1'bZ;
assign SD_DAT2 = 1'bZ;
assign SD_DAT3 = 1'bZ;
// Define open drain output for TEMP_MOSI
// OPNDRN iTEMP_MOSI_OD (.in(wTEMP_MOSI), .out(TEMP_MOSI));
assign TEMP_CS_N = 1'b1;
assign TEMP_SC = 1'b0;
assign TEMP_MOSI = 1'b0;
assign RAM_A0 = 1'b0;
assign RAM_A1 = 1'b0;
assign RAM_A2 = 1'b0;
assign RAM_A3 = 1'b0;
assign RAM_A4 = 1'b0;
assign RAM_A5 = 1'b0;
assign RAM_A6 = 1'b0;
assign RAM_A7 = 1'b0;
assign RAM_A8 = 1'b0;
assign RAM_A9 = 1'b0;
assign RAM_A10 = 1'b0;
assign RAM_A11 = 1'b0;
assign RAM_A12 = 1'b0;
assign RAM_A13 = 1'b0;
assign RAM_BA0 = 1'b0;
assign RAM_BA1 = 1'b0;
assign RAM_RAS_N = 1'b0;
assign RAM_CAS_N = 1'b0;
assign RAM_CS_N = 1'b0;
assign RAM_WS_N = 1'b0;
assign RAM_CKE = 1'b0;
assign RAM_CK_N = 1'b0;
assign RAM_CK_P = 1'b0;
assign RAM_LDM = 1'b0;
assign RAM_UDM = 1'b0;
assign RAM_LDQS = 1'bZ;
assign RAM_UDQS = 1'bZ;
assign RAM_D0 = 1'bZ;
assign RAM_D1 = 1'bZ;
assign RAM_D2 = 1'bZ;
assign RAM_D3 = 1'bZ;
assign RAM_D4 = 1'bZ;
assign RAM_D5 = 1'bZ;
assign RAM_D6 = 1'bZ;
assign RAM_D7 = 1'bZ;
assign RAM_D8 = 1'bZ;
assign RAM_D9 = 1'bZ;
assign RAM_D10 = 1'bZ;
assign RAM_D11 = 1'bZ;
assign RAM_D12 = 1'bZ;
assign RAM_D13 = 1'bZ;
assign RAM_D14 = 1'bZ;
assign RAM_D15 = 1'bZ;
assign clk_in_50m = CLK_FPGA_50M;
assign reset_n = !(pllrst | !plllock);
sys_pll sys_pll_inst (
.areset ( 1'b0 ),
.inclk0 ( clk_in_50m ),
.c0 ( sysclk ),
.locked ( plllock )
);
sync_rst rst_in(
.clk(clk_in_50m),
.resetn_in(CPU_RST_N),
.reset(pllrst),
.reset_n()
);
sync_rst srst(
.clk(sysclk),
.resetn_in(reset_n),
.reset(sysrst),
.reset_n(sysrst_n)
);
zscale_wrapper zs (
.clk(sysclk),
.reset(sysrst),
.led(led)
);
endmodule
|
//Testbench for the integer instruction pipe.
module intpipe_testbench();
reg clk, pause, empty;
reg [4:0] opCode;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
reg [15:0] aDat;
reg [15:0] bDat;
wire [3:0] aSel;
wire [3:0] bSel;
wire [3:0] cSel;
wire [15:0] cOut;
wire cWrite;
reg [15:0] ctr; //This allows me to change some things for validation
intpipe p(clk, pause, empty, opCode, a, b, c, aDat, bDat, aSel, bSel, cSel, cOut, cWrite);
initial begin
ctr=0;
clk=0;
pause=0;
empty=0;
opCode=1; //Add.
a=0;
b=1;
c=2;
aDat=1;
bDat=1;
end
always begin
#0 clk=!clk;
if(clk==1) begin
#1 aDat=aDat+1;
end
else begin
#1 aDat=aDat;
end
ctr=ctr+1;
//Send some NOPs through the pipe.
if(ctr==10) begin
opCode=0;
end
if(ctr==15) begin //Set it to subtract B from A.
opCode=3;
end
//Now pause for a few cycles.
if(ctr==20) begin
pause=1;
end
if(ctr==30) begin //Resume normal operations.
pause=0;
end
end
initial begin
$dumpfile("intpipe_testbench.vcd");
$dumpvars;
end
initial begin
$display("\t\tTime, \tClock, \tA, \tB, \tOp, \tOut, \tcWrite");
$monitor("%d, \t%b, \t%b, \t%b, \t%b, \t%b, \t%b", $time, clk, opCode, aDat, bDat, cOut, cWrite);
end
initial
#128 $finish;
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[105][105]; int main() { ios::sync_with_stdio(false); int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) cin >> a[i][j]; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) cout << a[j][i] << a[j][i]; cout << endl; for (int j = 1; j <= m; j++) cout << a[j][i] << a[j][i]; cout << endl; } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int N = 3e5 + 5, M = 1e8 + 5, OO = 1000000; int T, n, m; int u, v; int deg[N]; int main() { scanf( %d , &n); for (int i = 1; i < n; ++i) { scanf( %d %d , &u, &v); ++deg[u], ++deg[v]; } for (int i = 1; i <= n; ++i) { if (deg[i] == 2) { printf( NO n ); return 0; } } printf( YES n ); }
|
#include <bits/stdc++.h> using namespace std; #pragma optimize( -Ofast ) const int mod = 998244353; struct num { int x; num(int x_ = 0) { x = x_; } } G, _1[2222222], X[2222222], rot[2222222], inv[2222222]; inline bool operator<(const num x, const num y) { return x.x > y.x; } inline num operator+(const num x, const num y) { int z = x.x + y.x; return z < mod ? num(z) : num(z - mod); } inline num operator-(const num x, const num y) { int z = x.x - y.x; return z >= 0 ? num(z) : num(z + mod); } inline num operator*(const num x, const num y) { return num((long long)x.x * y.x % mod); } inline num operator*(const int x, const num y) { return num((long long)x * y.x % mod); } inline num operator^(num x, int y) { num z = num(1); while (y) { if (y & 1) { z = z * x; } x = x * x; y >>= 1; } return z; } void _(int n) { inv[1] = num(1); for (int i = 2; i <= n; i++) { inv[i] = (mod - mod / i) * inv[mod % i]; } for (int i = 2; i <= n; i <<= 1) { rot[i] = G ^ ((mod - 1) / i); } } void rader(num x[], int n) { int i, j = 0, k; for (register int i = 0; i != n; i++) { if (i > j) { swap(x[i], x[j]); } k = n >> 1; while ((j ^= k) < k) { k >>= 1; } } } void NTT(num x[], int n, int o) { int k; num r, u, v, w; rader(x, n); for (int l = 2; l <= n; l <<= 1) { k = l >> 1; r = rot[l]; for (int i = 0; i < n; i += l) { w = num(1); for (register int j = i; j < i + k; j++) { u = x[j]; v = x[j + k] * w; x[j] = u + v; x[j + k] = u - v; w = w * r; } } } if (o == -1) { for (register int i = 0; i < n; i++) { x[i] = x[i] * inv[n]; } for (register int i = 1; i < (n >> 1); i++) { swap(x[i], x[n - i]); } } } int main() { int n, k, z[11], oo[11] = {0}; G = num(3); scanf( %d%d , &n, &k); n /= 2; for (int i = 1; i <= k; i++) { scanf( %d , &z[i]); oo[z[i]] = 1; } for (int i = 0; i <= 9; i++) { if (oo[i]) { _1[i] = num(1); } } int xxx = n; n *= 10; int S = 1; while (S <= n) { S <<= 1; } S <<= 1; _(S); X[0] = num(1); NTT(_1, S, 1); NTT(X, S, 1); while (xxx) { if (xxx & 1) { for (register int i = 0; i < S; i++) { X[i] = X[i] * _1[i]; } } for (register int i = 0; i < S; i++) { _1[i] = _1[i] * _1[i]; } xxx >>= 1; } NTT(X, S, -1); num ans = num(0); for (int i = 0; i <= S; i++) { ans = ans + (X[i] * X[i]); } printf( %d , ans.x); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int i = 0, a = 0, b = 0; string s; cin >> s; while (s[i] != 0 ) { if (s[i] >= 65 && s[i] <= 90) { a++; } else if (s[i] >= 97 && s[i] <= 122) b++; i++; } i = 0; if (a > b) { while (s[i] != 0 ) { s[i] = toupper(s[i]); i++; } } else if (a < b) { while (s[i] != 0 ) { s[i] = tolower(s[i]); i++; } } else if (a == b) { while (s[i] != 0 ) { s[i] = tolower(s[i]); i++; } } cout << s; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 3700, maxd = 1850, mod = 998244353; int h, w, tr[maxn], tc[maxn], x, y, n; vector<int> rs, cs; long long f[maxd], c[maxn][maxn], dpr[maxn][maxd], dpc[maxn][maxd], ans; long long C(int a, int b) { if (a < 0 || b < 0 || a < b) return 0; return c[a][b]; } int main() { ios::sync_with_stdio(0); cin.tie(0); f[0] = 1; for (int i = 1; i < maxd; i++) f[i] = (f[i - 1] * i) % mod; for (int i = 0; i < maxn; i++) c[i][0] = 1; for (int i = 1; i < maxn; i++) { for (int j = 1; j < maxn; j++) c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % mod; } cin >> h >> w >> n; for (int i = 0; i < 2 * n; i++) { cin >> x >> y; x--; y--; tr[x]++; tc[y]++; } dpr[0][0] = dpc[0][0] = 1; for (int i = 0; i < h; i++) { if (tr[i] == 0) { for (int j = 0; j <= ((((int)rs.size())) + 1) / 2; j++) { dpr[(((int)rs.size())) + 1][j] = dpr[(((int)rs.size()))][j]; if (!rs.empty() && rs.back() == i - 1 && j > 0) { dpr[(((int)rs.size())) + 1][j] += dpr[(((int)rs.size())) - 1][j - 1]; dpr[(((int)rs.size())) + 1][j] %= mod; } } rs.push_back(i); } } for (int i = 0; i < w; i++) { if (tc[i] == 0) { for (int j = 0; j <= ((((int)cs.size())) + 1) / 2; j++) { dpc[(((int)cs.size())) + 1][j] = dpc[(((int)cs.size()))][j]; if (!cs.empty() && cs.back() == i - 1 && j > 0) { dpc[(((int)cs.size())) + 1][j] += dpc[(((int)cs.size())) - 1][j - 1]; dpc[(((int)cs.size())) + 1][j] %= mod; } } cs.push_back(i); } } for (int i = 0; i <= (((int)rs.size())) / 2; i++) { for (int j = 0; j <= (((int)cs.size())) / 2; j++) { ans += ((((dpr[(((int)rs.size()))][i] * dpc[(((int)cs.size()))][j]) % mod) * ((C((((int)rs.size())) - 2 * i, j) * C((((int)cs.size())) - 2 * j, i)) % mod)) % mod) * ((f[i] * f[j]) % mod); ans %= mod; } } cout << ans; return 0; }
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// File : ../RTL/hostController/softransmit.v
// Generated : 11/10/06 05:37:21
// From : ../RTL/hostController/softransmit.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// softransmit
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostControl_h.v"
module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, fullSpeedRate);
input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
input SOFSyncEn;
input [15:0] SOFTimer;
input clk;
input rst;
input sendPacketArbiterGnt;
input sendPacketRdy;
output SOFSent; // single cycle pulse
output SOFTimerClr; // Single cycle pulse
output sendPacketArbiterReq;
output sendPacketWEn;
input fullSpeedRate;
wire SOFEnable;
reg SOFSent, next_SOFSent;
wire SOFSyncEn;
reg SOFTimerClr, next_SOFTimerClr;
wire [15:0] SOFTimer;
wire clk;
wire rst;
wire sendPacketArbiterGnt;
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
wire sendPacketRdy;
reg sendPacketWEn, next_sendPacketWEn;
reg [15:0] SOFNearTime;
// diagram signals declarations
reg [7:0]i, next_i;
// BINARY ENCODED state machine: SOFTx
// State codes definitions:
`define START_STX 3'b000
`define WAIT_SOF_NEAR 3'b001
`define WAIT_SP_GNT 3'b010
`define WAIT_SOF_NOW 3'b011
`define SOF_FIN 3'b100
`define DLY_SOF_CHK1 3'b101
`define DLY_SOF_CHK2 3'b110
reg [2:0] CurrState_SOFTx;
reg [2:0] NextState_SOFTx;
//--------------------------------------------------------------------
// Machine: SOFTx
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (i or SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
begin : SOFTx_NextState
NextState_SOFTx <= CurrState_SOFTx;
// Set default values for outputs and signals
next_sendPacketArbiterReq <= sendPacketArbiterReq;
next_sendPacketWEn <= sendPacketWEn;
next_SOFTimerClr <= SOFTimerClr;
next_SOFSent <= SOFSent;
next_i <= i;
case (CurrState_SOFTx)
`START_STX:
NextState_SOFTx <= `WAIT_SOF_NEAR;
`WAIT_SOF_NEAR:
if (SOFTimer >= SOFNearTime ||
(SOFSyncEn == 1'b1 &&
SOFEnable == 1'b1))
begin
NextState_SOFTx <= `WAIT_SP_GNT;
next_sendPacketArbiterReq <= 1'b1;
end
`WAIT_SP_GNT:
if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
NextState_SOFTx <= `WAIT_SOF_NOW;
`WAIT_SOF_NOW:
if (SOFTimer >= `SOF_TX_TIME)
begin
NextState_SOFTx <= `SOF_FIN;
next_sendPacketWEn <= 1'b1;
next_SOFTimerClr <= 1'b1;
next_SOFSent <= 1'b1;
end
else if (SOFEnable == 1'b0)
begin
NextState_SOFTx <= `SOF_FIN;
next_SOFTimerClr <= 1'b1;
end
`SOF_FIN:
begin
next_sendPacketWEn <= 1'b0;
next_SOFTimerClr <= 1'b0;
next_SOFSent <= 1'b0;
if (sendPacketRdy == 1'b1)
begin
NextState_SOFTx <= `DLY_SOF_CHK1;
next_i <= 8'h00;
end
end
`DLY_SOF_CHK1:
begin
next_i <= i + 1'b1;
if (i==8'hff)
begin
NextState_SOFTx <= `DLY_SOF_CHK2;
next_sendPacketArbiterReq <= 1'b0;
next_i <= 8'h00;
end
end
`DLY_SOF_CHK2:
begin
next_i <= i + 1'b1;
if (i==8'hff)
NextState_SOFTx <= `WAIT_SOF_NEAR;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SOFTx_CurrentState
if (rst)
CurrState_SOFTx <= `START_STX;
else
CurrState_SOFTx <= NextState_SOFTx;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SOFTx_RegOutput
if (rst)
begin
i <= 8'h00;
SOFSent <= 1'b0;
SOFTimerClr <= 1'b0;
sendPacketArbiterReq <= 1'b0;
sendPacketWEn <= 1'b0;
SOFNearTime <= 16'h0000;
end
else
begin
i <= next_i;
SOFSent <= next_SOFSent;
SOFTimerClr <= next_SOFTimerClr;
sendPacketArbiterReq <= next_sendPacketArbiterReq;
sendPacketWEn <= next_sendPacketWEn;
if (fullSpeedRate == 1'b1)
SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN;
else
SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN_LOW_SPEED;
end
end
endmodule
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int inf = 1000000000; const long long INF = 1LL * inf * inf; const long double eps = 1e-9; const long long md = 1e9 + 7; const long double EPS = 1e-5; const long long maxll = std::numeric_limits<long long>::max(); const long double PI = acos(-1.0); template <typename name> inline name sqr(name x) { return x * x; } long double log(long double base, long double n) { return log(n) / log(base); } inline long long multmod(long long a, long long b, long long md) { if (!a) return 0; if (a % 2 == 1) return (multmod(a - 1, b, md) + b) % md; else return sqr(multmod(a / 2, b, md)) % md; } template <typename name> inline name bpow(const name &base, long long exp, const long long &md = maxll) { if (exp == 1) return base; if (exp % 2 == 1) return (bpow<name>(base, exp - 1, md) * base) % md; else { name k = bpow<name>(base, exp / 2, md); return (k * k) % md; } } unsigned char ccc; inline void read(int &n) { n = 0; bool _minus = false; while (true) { ccc = getchar(); if (ccc == || ccc == n ) break; if (ccc == - ) { _minus = true; continue; } n = n * 10 + ccc - 0 ; } if (_minus) n *= -1; } inline void read(int &n, int &m) { read(n); read(m); } inline void read(int &n, int &m, int &k) { read(n); read(m); read(k); } inline void read(std::string &s) { s = ; while (true) { ccc = getchar(); if (ccc == || ccc == n ) break; s += ccc; } } template <typename T1, typename T2> inline T1 min(const T1 x, const T2 y) { return (x > y ? y : x); } template <typename T1, typename T2> inline T1 max(const T1 x, const T2 y) { return (x < y ? y : x); } const int MAXN = 3e5; int n, k[2], a[2][MAXN], cnt[2][MAXN], win[2][MAXN], lose[2][MAXN]; void solve0() { std::vector<int> bad(0); for (int i = 0; i < k[0]; i++) { int x = (n - a[0][i]) % n; win[0][x] = 1; for (int j = 0; j < k[1]; j++) { cnt[1][(n + x - (a[1][j])) % n]--; if (cnt[1][(n + x - (a[1][j])) % n] == 0) bad.push_back((n + x - (a[1][j])) % n); } } while (!bad.empty()) { std::vector<int> buff(0); for (int x : bad) { lose[1][x] = 1; for (int i = 0; i < k[0]; i++) { int y = (n + x - a[0][i]) % n; if (!y) continue; if (!win[0][y]) { win[0][y] = 1; for (int j = 0; j < k[1]; j++) { cnt[1][(n + y - (a[1][j])) % n]--; if (cnt[1][(n + y - (a[1][j])) % n] == 0) buff.push_back((n + y - (a[1][j])) % n); } } } } bad.clear(); bad = buff; } } void solve1() { std::vector<int> bad(0); for (int i = 0; i < k[1]; i++) { int x = (n - a[1][i]) % n; win[1][x] = 1; for (int j = 0; j < k[0]; j++) { cnt[0][(n + x - (a[0][j])) % n]--; if (cnt[0][(n + x - (a[0][j])) % n] == 0) bad.push_back((n + x - (a[0][j])) % n); } } while (!bad.empty()) { std::vector<int> buff(0); for (int x : bad) { lose[0][x] = 1; for (int i = 0; i < k[1]; i++) { int y = (n + x - a[1][i]) % n; if (!win[1][y] && y) { win[1][y] = 1; for (int j = 0; j < k[0]; j++) { cnt[0][(n + y - (a[0][j])) % n]--; if (cnt[0][(n + y - (a[0][j])) % n] == 0) buff.push_back((n + y - (a[0][j])) % n); } } } } bad.clear(); bad = buff; } } int main() { (( != ) ? freopen( .dat , r , stdin), freopen( .sol , w , stdout) : 0); scanf( %d , &n); scanf( %d , &k[0]); for (int i = 0; i < k[0]; i++) scanf( %d , &a[0][i]); scanf( %d , &k[1]); for (int i = 0; i < k[1]; i++) scanf( %d , &a[1][i]); for (int i = 1; i < n; i++) cnt[0][i] = k[0], cnt[1][i] = k[1]; solve0(); solve1(); for (int i = 1; i < n; i++) { assert(!win[0][i] || !lose[0][i]); if (win[0][i]) cout << Win ; else if (lose[0][i]) cout << Lose ; else cout << Loop ; } cout << n ; for (int i = 1; i < n; i++) { assert(!win[1][i] || !lose[1][i]); if (win[1][i]) cout << Win ; else if (lose[1][i]) cout << Lose ; else cout << Loop ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB8TO1_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUXB8TO1_BLACKBOX_V
/**
* muxb8to1: Buffered 8-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb8to1 (
Z,
D,
S
);
output Z;
input [7:0] D;
input [7:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB8TO1_BLACKBOX_V
|
/* ------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
*
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*/
//`timescale 1ps/1ps
module LAG_test_random ();
parameter CLOCK_PERIOD = 10_000;
flit_t flit_in[network_x-1:0][network_y-1:0];
flit_t flit_out[network_x-1:0][network_y-1:0][router_num_pls_on_exit-1:0];
logic [router_num_pls_on_entry-1:0] input_full_flag [network_x-1:0][network_y-1:0];
chan_cntrl_t cntrl_in [network_x-1:0][network_y-1:0];
integer rec_count [network_x-1:0][network_y-1:0];
sim_stats_t stats [network_x-1:0][network_y-1:0];
real av_lat[network_x-1:0][network_y-1:0];
genvar x,y;
integer i,j,k;
integer sys_time, total_packets, total_hops, min_latency, max_latency, total_latency;
integer min_hops, max_hops;
integer total_rec_count;
integer total_lat_for_hop_count [(network_x+network_y):0];
integer total_packets_with_hop_count[(network_x+network_y):0];
integer hc_total_packets, hc_total_latency;
integer lat_freq[100:0];
logic clk, rst_n;
// clock generator
initial begin
clk=0;
end
always #(CLOCK_PERIOD/2) clk = ~clk;
always@(posedge clk) begin
if (!rst_n) begin
sys_time=0;
end else begin
sys_time++;
end
end
// ########################
// Network
// ########################
LAG_mesh_network #(.XS(network_x), .YS(network_y), .NT(router_radix), .NPL(router_num_pls),
.channel_latency(channel_latency))
network
(flit_in, flit_out,
input_full_flag,
cntrl_in,
clk, rst_n);
// ########################
// Traffic Sources
// ########################
generate
for (x=0; x<network_x; x++) begin:xl
for (y=0; y<network_y; y++) begin:yl
LAG_random_traffic_source #(.nv(router_num_pls_on_entry),
.xdim(network_x), .ydim(network_y), .xpos(x), .ypos(y),
.packet_length(sim_packet_length),
.rate(sim_injection_rate),
.router_radix(router_radix)
)
traf_src (.flit_out(flit_in[x][y]),
.network_ready(~input_full_flag[x][y]),
.clk, .rst_n);
end
end
endgenerate
// ########################
// Traffic Sinks
// ########################
generate
for (x=0; x<network_x; x++) begin:xl2
for (y=0; y<network_y; y++) begin:yl2
LAG_traffic_sink #(.xdim(network_x), .ydim(network_y), .xpos(x), .ypos(y),
.warmup_packets(sim_warmup_packets), .measurement_packets(sim_measurement_packets),
.router_num_pls_on_exit(router_num_pls_on_exit))
traf_sink (.flit_in(flit_out[x][y]),
.cntrl_out(cntrl_in[x][y]),
.rec_count(rec_count[x][y]),
.stats(stats[x][y]),
.clk, .rst_n);
end
end
endgenerate
//
// All measurement packets must be received before we end the simulation
// (this includes a drain phase)
//
always@(posedge clk) begin
total_rec_count=0;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
total_rec_count=total_rec_count+rec_count[i][j];
end
end
end
initial begin
$display ("**********************************************");
$display ("* NOC with LAG - Uniform Random Traffic Test *");
$display ("**********************************************");
total_hops=0;
total_latency=0;
//
// reset
//
rst_n=0;
// reset
#(CLOCK_PERIOD*20);
rst_n=1;
$display ("-- Reset Complete");
$display ("-- Entering warmup phase (%1d packets per node)", sim_warmup_packets);
`ifdef DUMPTRACE
$dumpfile ("/tmp/trace.pld");
$dumpvars;
`endif
// #################################################################
// wait for all traffic sinks to rec. all measurement packets
// #################################################################
wait (total_rec_count==sim_measurement_packets*network_x*network_y);
$display ("** Simulation End **\n");
total_packets = sim_measurement_packets*network_x*network_y;
min_latency=stats[0][0].min_latency;
max_latency=stats[0][0].max_latency;
min_hops=stats[0][0].min_hops;
max_hops=stats[0][0].max_hops;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
av_lat[i][j] = $itor(stats[i][j].total_latency)/$itor(rec_count[i][j]);
total_latency = total_latency + stats[i][j].total_latency;
total_hops=total_hops+stats[i][j].total_hops;
min_latency = min(min_latency, stats[i][j].min_latency);
max_latency = max(max_latency, stats[i][j].max_latency);
min_hops = min(min_hops, stats[i][j].min_hops);
max_hops = max(max_hops, stats[i][j].max_hops);
end
end
for (k=min_hops;k<=max_hops;k++) begin
total_lat_for_hop_count[k] = 0;
total_packets_with_hop_count[k] = 0;
end
for (k=0; k<=100; k++) lat_freq[k]=0;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
for (k=min_hops;k<=max_hops;k++) begin
total_lat_for_hop_count[k] = total_lat_for_hop_count[k]+stats[i][j].total_lat_for_hop_count[k];
total_packets_with_hop_count[k] =
total_packets_with_hop_count[k]+stats[i][j].total_packets_with_hop_count[k];
end
for (k=0; k<=100; k++) begin
lat_freq[k]=lat_freq[k]+stats[i][j].lat_freq[k];
end
end
end
$display ("***********************************************************************************");
$display ("-- Channel Latency = %1d", channel_latency);
$display ("***********************************************************************************");
$display ("-- Packet Length = %1d", sim_packet_length);
$display ("-- Injection Rate = %1.4f (flits/cycle/node)", sim_injection_rate);
$display ("-- Average Latency = %1.2f (cycles)", $itor(total_latency)/$itor(total_packets));
$display ("-- Min. Latency = %1d, Max. Latency = %1d", min_latency, max_latency);
$display ("-- Average no. of hops taken by packet = %1.2f hops (min=%1d, max=%1d)",
$itor(total_hops)/$itor(total_packets), min_hops, max_hops);
$display ("***********************************************************************************");
$display ("\n");
$display ("Average Latencies for packets rec'd at nodes [x,y] and (no. of packets received)");
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y;j++) $write ("%1.2f (%1d)\t", av_lat[i][j], rec_count[i][j]);
$display ("");
end
$display ("Flits/cycle received at each node: (should approx. injection rate)");
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
$write ("%1.2f\t", $itor(stats[i][j].flit_count)/$itor(stats[i][j].measure_end-stats[i][j].measure_start));
end
$display ("");
end
$display ("");
$display ("Distribution of packet latencies: ");
$display ("Latency : Frequency (as percentage of total)");
$display ("-------------------");
for (k=0; k<100; k++) begin
$display ("%1d %1.2f", k, $itor(lat_freq[k]*100)/$itor(total_packets));
end
$display ("100+ %1.2f", $itor(lat_freq[k]*100)/$itor(total_packets));
$display ("");
$display ("Journey length (hops) : Av.Latency ");
$display ("----------------------------------- ");
hc_total_packets=0;
hc_total_latency=0;
for (i=min_hops; i<=max_hops; i++) begin
$display ("%1d %1.2f", i, $itor(total_lat_for_hop_count[i])/$itor(total_packets_with_hop_count[i]));
hc_total_packets=hc_total_packets+total_packets_with_hop_count[i];
hc_total_latency=hc_total_latency+total_lat_for_hop_count[i];
end
$display ("\n\n");
// sanity checks
if (hc_total_packets!=total_packets) begin
$display ("Error: hc_total_packets=%1d, total_packets=%1d (should be equal)", hc_total_packets, total_packets);
end
if (hc_total_latency!=total_latency) begin
$display ("Error: hc_total_latency=%1d, total_latency=%1d (should be equal)", hc_total_latency, total_latency);
end
$finish;
end
endmodule // LAG_test_random
|
#include <bits/stdc++.h> using namespace std; pair<int, int> afis[1503]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, cnt = 0, i, x = 1; cin >> n; afis[++cnt] = {0, 0}; while (x <= n + 1) { afis[++cnt] = {x, x}; afis[++cnt] = {x, x - 1}; afis[++cnt] = {x - 1, x}; x++; } cout << cnt << n ; for (i = 1; i <= cnt; i++) cout << afis[i].first << << afis[i].second << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, a[100001], b[100001]; vector<long long> v[100001]; signed main() { cin >> n; long long i; for (i = 1; i < n + 1; i++) { cin >> a[i]; v[a[i]].push_back(i); } bool ok = 1; long long clr = 1; for (i = 0; i < 100001; i++) { if (!v[i].empty()) { long long k = v[i].size(); long long j; if (k % (n - i) != 0) { ok = 0; break; } long long t = k / (n - i); long long temp = 1; j = 0; while (temp <= t) { while (j < temp * (n - i)) { b[v[i][j]] = clr; j++; } clr++; temp++; } } } if (ok) { cout << Possible n ; for (i = 1; i < n + 1; i++) cout << b[i] << ; } else cout << Impossible ; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::pair<T, U> operator+(const std::pair<T, U>& l, const std::pair<T, U>& r) { return {l.first + r.first, l.second + r.second}; } typedef void (*callback_function)(void); const long long ZERO = 0LL; const long long INF64 = 1e18; const long long INF32 = 1e9; const long long MOD = 1e9 + 7; const long double PI = acos(-1.0L); const long double EPS = static_cast<long double>(1e-9); inline long long Pow(long long a, long long k) { long long s = 1; for (; k; k >>= 1) { k& 1 ? s = 1LL * s * a % MOD : 0; a = 1LL * a * a % MOD; } return s; } const long long N = 1e6 + 7; void input() {} void preprocess() {} void debug() { if (true) { } } void solve() { preprocess(); long long n, m; cin >> n >> m; long long a[n]; for (long long i = (0); i < (n); i++) { cin >> a[i]; } for (long long i = (0); i < (m); i++) { long long L, R, x; cin >> L >> R >> x; L--; x--; long long y = L; for (long long j = (L); j < (R); j++) { if (a[j] < a[x]) { y++; } } cout << (y == x ? Yes : No ) << endl; } } void output() {} int main() { ios_base::sync_with_stdio(false); cin.tie(); { input(); solve(); output(); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 11:52:43 AM
// Design Name:
// Module Name: Oper_Start_In
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//dc_script_begin
// set LIB_NAME scx3_cmos8rf_lpvt_tt_1p2v_25c.db
// create_clock -period 10 [get_ports clk]
// set_max_delay -from [get_ports {intDX intDY load_b_i}] -to [get_ports {DMP_o DmP_o}] 4
// set_min_delay -from [get_ports {intDX intDY load_b_i}] -to [get_ports {DMP_o DmP_o}] 3
//set_clock_transition 0.5 [get_clocks clk]
// set_flatten true -effort high
//dc_script_end
`ifdef FRANCIS
module Oper_Start_In
# (parameter W = 32 ) // This parameter could be adjust based
//on the desire precision format
//W = 64 indicates the double precision format
//W = 32 indicates the single precision format
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,//The ctrl_x signals are used to load certain registers within the module
input wire load_b_i,
input wire add_subt_i, //This signal selects if the operations is an add o subtract operation
input wire [W-1:0] Data_X_i, //Data_X and Data_y are both operands of the module
//they are expected in ieee 754 format
input wire [W-1:0] Data_Y_i,
//////////////////////////////////////////////////////////////////////
output wire [W-2:0] DMP_o, //Because the algorithm these outputs contain the largest and smallest operand
output wire [W-2:0] DmP_o,
output wire zero_flag_o, //Flag for FSM when the subt result is zero
output wire real_op_o, //bit for real add/subt operation in case for -DataY
output wire sign_final_result_o //bit for sign result
);
//Wire Signals useful to interconnect the components of the module
wire [W-1:0] intDX; //Output of register DATA_X
wire [W-1:0] intDY; //Output of register DATA_Y
wire intAS; //Output of register add_subt
wire gtXY; //Output for magntiude_comparator (X>Y)
wire eqXY; //Output for magntiude_comparator (X=Y)
wire [W-2:0] intM; //Output of MuxXY for bigger value
wire [W-2:0] intm; //Output of MuxXY for small value
wire sign_result;
///////////////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) XRegister ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Data_X_i),
.Q(intDX)
);
RegisterAdd #(.W(W)) YRegister ( //Data Y input register
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Data_Y_i),
.Q(intDY)
);
RegisterAdd #(.W(1)) ASRegister ( //Data Add_Subtract input register
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(add_subt_i),
.Q(intAS)
);
Comparator #(.W(W-1)) Magnitude_Comparator ( //Compare between magnitude for DATA_X and DATA_Y and select whos bigger and if there's a equality
.Data_X_i(intDX[W-2:0]),
.Data_Y_i(intDY[W-2:0]),
.gtXY_o(gtXY),
.eqXY_o(eqXY)
);
xor_tri #(.W(W)) Op_verification ( //Operation between the DATA_X & Y's sign bit and the operation bit to find the real operation for ADDER/SUBTRACT
.A_i(intDX[W-1]),
.B_i(intDY[W-1]),
.C_i(intAS),
.Z_o(real_op_o)
);
sgn_result result_sign_bit (//Calculate the sign bit for the final result
.Add_Subt_i(intAS),
.sgn_X_i(intDX[W-1]),
.sgn_Y_i(intDY[W-1]),
.gtXY_i(gtXY),
.eqXY_i(eqXY),
.sgn_result_o(sign_result)
);
MultiplexTxT #(.W(W-1)) MuxXY (//Classify in the registers the bigger value (M) and the smaller value (m)
.select(gtXY),
.D0_i(intDX[W-2:0]),
.D1_i(intDY[W-2:0]),
.S0_o(intM),
.S1_o(intm)
);
RegisterAdd #(.W(W-1)) MRegister ( //Data_M register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(intM),
.Q(DMP_o)
);
RegisterAdd #(.W(W-1)) mRegister ( //Data_m register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(intm),
.Q(DmP_o)
);
RegisterAdd #(.W(1)) SignRegister (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(sign_result),
.Q(sign_final_result_o)
);
assign zero_flag_o = real_op_o & eqXY;
endmodule
`endif
`ifndef FRANCIS
module Oper_Start_In_2
# (parameter W = 32 ) // This parameter could be adjust based
//on the desire precision format
//W = 64 indicates the double precision format
//W = 32 indicates the single precision format
(
input wire clk, //system clock
input wire rst, //reset of the module
//input wire load_a_i,//The ctrl_x signals are used to load certain registers within the module
input wire load_b_i,
input wire intAS, //This signal selects if the operations is an add o subtract operation
input wire [W-1:0] intDX, //Data_X and Data_y are both operands of the module
//they are expected in ieee 754 format
input wire [W-1:0] intDY,
//////////////////////////////////////////////////////////////////////
output wire [W-2:0] DMP_o, //Because the algorithm these outputs contain the largest and smallest operand
output wire [W-2:0] DmP_o,
output wire zero_flag_o, //Flag for FSM when the subt result is zero
output wire real_op_o, //bit for real add/subt operation in case for -DataY
output wire sign_final_result_o //bit for sign result
);
//Wire Signals useful to interconnect the components of the module
wire gtXY; //Output for magntiude_comparator (X>Y)
wire eqXY; //Output for magntiude_comparator (X=Y)
wire [W-2:0] intM; //Output of MuxXY for bigger value
wire [W-2:0] intm; //Output of MuxXY for small value
wire sign_result;
///////////////////////////////////////////////////////////////////
Comparator #(.W(W-1)) Magnitude_Comparator ( //Compare between magnitude for DATA_X and DATA_Y and select whos bigger and if there's a equality
.Data_X_i(intDX[W-2:0]),
.Data_Y_i(intDY[W-2:0]),
.gtXY_o(gtXY),
.eqXY_o(eqXY)
);
xor_tri #(.W(W)) Op_verification ( //Operation between the DATA_X & Y's sign bit and the operation bit to find the real operation for ADDER/SUBTRACT
.A_i(intDX[W-1]),
.B_i(intDY[W-1]),
.C_i(intAS),
.Z_o(real_op_o)
);
sgn_result result_sign_bit (//Calculate the sign bit for the final result
.Add_Subt_i(intAS),
.sgn_X_i(intDX[W-1]),
.sgn_Y_i(intDY[W-1]),
.gtXY_i(gtXY),
.eqXY_i(eqXY),
.sgn_result_o(sign_result)
);
MultiplexTxT #(.W(W-1)) MuxXY (//Classify in the registers the bigger value (M) and the smaller value (m)
.select(gtXY),
.D0_i(intDX[W-2:0]),
.D1_i(intDY[W-2:0]),
.S0_o(intM),
.S1_o(intm)
);
RegisterAdd #(.W(W-1)) MRegister ( //Data_M register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(intM),
.Q(DMP_o)
);
RegisterAdd #(.W(W-1)) mRegister ( //Data_m register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(intm),
.Q(DmP_o)
);
RegisterAdd #(.W(1)) SignRegister (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(sign_result),
.Q(sign_final_result_o)
);
assign zero_flag_o = real_op_o & eqXY;
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int n, A[100005]; cin >> n; for (int i = 0; i < n; i++) cin >> A[i]; int mx = 0; long long sum = 0; for (int i = 0; i < n; i++) { sum += A[i]; if (A[i] > mx) mx = A[i]; } sum -= mx; if (sum <= mx) { cout << mx - sum + 1 << endl; } else { cout << 0; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n, i, j; cin >> t; while (t--) { cin >> n; if (n % 2 == 0) { cout << n / 2 << << n / 2; } else { for (i = 3, j = 0; i * i <= n; i++) { if (n % i == 0) { cout << n / i << << n - (n / i); j = 1; break; } } if (j == 0) cout << 1 << << n - 1; } printf( n ); } }
|
#include <bits/stdc++.h> using namespace std; vector<int> e[111]; int used[111], cnt, cnt2; void dfs(int x) { used[x] = 1; cnt += e[x].size(); cnt2++; for (int i = 0; i < e[x].size(); i++) if (used[e[x][i]] == 0) dfs(e[x][i]); } int main() { int i, j, k, n, m, stop = 0; scanf( %d%d , &n, &m); for (i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); e[x].push_back(y); e[y].push_back(x); } for (i = 1; i <= n; i++) { if (!used[i]) { cnt = 0; cnt2 = 0; dfs(i); if (cnt2 % 2 == 1 && cnt2 * 2 == cnt) { stop++; } } } printf( %d n , stop + (n - stop) % 2); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int q; cin >> q; for (long long int l = 0; l < q; l++) { long long int n; cin >> n; long long int ans = 0; while (n != 1) { long long int track = ans; while (n % 2 == 0) { n = n / 2; ans++; } while (n % 3 == 0) { n = 2 * n / 3; ans++; } while (n % 5 == 0) { n = 4 * n / 5; ans++; } if (track == ans) break; } if (n != 1) cout << -1 << endl; else cout << ans << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_2_V
`define SKY130_FD_SC_HS__O211AI_2_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o211ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o211ai_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_2_V
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; vector<vector<int>> a(n, vector<int>(m)); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) cin >> a[i][j]; } vector<vector<int>> b(n, vector<int>(m)); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) cin >> b[i][j]; } vector<vector<int>> bb; for (int i = 0; i < n; ++i) bb.push_back(b[i]); sort(bb.begin(), bb.end()); bb.erase(unique(bb.begin(), bb.end()), bb.end()); vector<vector<int>> who_a(bb.size()); vector<vector<int>> who_b(bb.size()); for (int i = 0; i < n; ++i) { int ind = lower_bound(bb.begin(), bb.end(), a[i]) - bb.begin(); if (ind == (int)bb.size() || bb[ind] != a[i]) { cout << -1 << endl; return 0; } who_a[ind].push_back(i); ind = lower_bound(bb.begin(), bb.end(), b[i]) - bb.begin(); who_b[ind].push_back(i); } vector<int> p(n); for (int i = 0; i < (int)bb.size(); ++i) { if (who_a[i].size() != who_b[i].size()) { cout << -1 << endl; return 0; } for (int j = 0; j < (int)who_a[i].size(); ++j) { p[who_a[i][j]] = who_b[i][j]; } } vector<int> q(n); for (int i = 0; i < n; ++i) q[p[i]] = i; vector<bool> good(n, 0); vector<int> cnt_bad(m, 0), cnt_kek(m, 0); for (int j = 0; j < m; ++j) { for (int i = 0; i < n - 1; ++i) { if (a[q[i]][j] < a[q[i + 1]][j]) ++cnt_kek[j]; if (a[q[i]][j] > a[q[i + 1]][j]) ++cnt_bad[j]; } } vector<int> ans; while (true) { bool ok = true; for (int i = 0; i < n - 1; ++i) ok &= good[i] || q[i] < q[i + 1]; if (ok) break; int col = -1; for (int j = 0; j < m; ++j) { if (cnt_bad[j] == 0 && cnt_kek[j] > 0) { col = j; break; } } if (col == -1) break; ans.push_back(col); for (int i = 0; i < n - 1; ++i) { if (!good[i] && a[q[i]][col] < a[q[i + 1]][col]) { good[i] = true; for (int j = 0; j < m; ++j) { if (a[q[i]][j] < a[q[i + 1]][j]) --cnt_kek[j]; if (a[q[i]][j] > a[q[i + 1]][j]) --cnt_bad[j]; } } } } bool ok = true; for (int i = 0; i < n - 1; ++i) ok &= good[i] || q[i] < q[i + 1]; if (ok) { cout << (int)ans.size() << endl; reverse(ans.begin(), ans.end()); for (int i : ans) cout << i + 1 << ; cout << endl; } else { cout << -1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, q; const int N = 2e5 + 10; const int inf = 1e9; char s[N]; struct Node { Node() { for (int i = 0; i < 5; i++) { for (int j = 0; j < 5; j++) { dp[i][j] = (i == j) ? 0 : inf; } } } int dp[5][5]; }; Node operator*(const Node& u, const Node& v) { Node ans; for (int i = 0; i < 5; i++) { for (int j = 0; j < 5; j++) { ans.dp[i][j] = inf; for (int k = 0; k < 5; k++) { ans.dp[i][j] = min(u.dp[i][k] + v.dp[k][j], ans.dp[i][j]); } } } return ans; } Node nodes[N * 4]; void build_tree(int l, int r, int rt) { Node& v = nodes[rt]; if (l == r) { char c = s[l - 1]; if (c == 2 ) { v.dp[0][0] = 1; v.dp[0][1] = 0; } else if (c == 0 ) { v.dp[1][1] = 1; v.dp[1][2] = 0; } else if (c == 1 ) { v.dp[2][2] = 1; v.dp[2][3] = 0; } else if (c == 7 ) { v.dp[3][3] = 1; v.dp[3][4] = 0; } else if (c == 6 ) { v.dp[3][3] = 1; v.dp[4][4] = 1; } return; } int m = (l + r) >> 1; build_tree(l, m, 2 * rt); build_tree(m + 1, r, 2 * rt + 1); v = nodes[2 * rt] * nodes[2 * rt + 1]; } Node query(int L, int R, int l, int r, int rt) { Node& v = nodes[rt]; if (L <= l && R >= r) return v; int m = (l + r) >> 1; bool left = false, right = false; Node ltemp, rtemp; if (L <= m) { ltemp = query(L, R, l, m, rt * 2); left = true; } if (R > m) { rtemp = query(L, R, m + 1, r, rt * 2 + 1); right = true; } if (left && right) return ltemp * rtemp; if (left) return ltemp; if (right) return rtemp; } int main() { scanf( %d %d , &n, &q); scanf( %s , s); build_tree(1, n, 1); for (int i = 0; i < q; i++) { int l, r; scanf( %d %d , &l, &r); Node v = query(l, r, 1, n, 1); if (v.dp[0][4] == inf) cout << -1 << endl; else cout << v.dp[0][4] << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m; string grid[105]; int check_bomb(int i, int j) { if ((i > 0 && grid[i - 1][j] == * ) || (i < n - 1 && grid[i + 1][j] == * ) || (j > 0 && grid[i][j - 1] == * ) || (j < m - 1 && grid[i][j + 1] == * ) || (i > 0 && j > 0 && grid[i - 1][j - 1] == * ) || (i > 0 && j < m - 1 && grid[i - 1][j + 1] == * ) || (i < n - 1 && j > 0 && grid[i + 1][j - 1] == * ) || (i < n - 1 && j < m - 1 && grid[i + 1][j + 1] == * )) { printf( NO ); return 1; } return 0; } int count_bomb(int i, int j) { int k = grid[i][j] - 48; int cnt = 0; if (i > 0 && grid[i - 1][j] == * ) cnt++; if (i < n - 1 && grid[i + 1][j] == * ) cnt++; if (j > 0 && grid[i][j - 1] == * ) cnt++; if (j < m - 1 && grid[i][j + 1] == * ) cnt++; if (i > 0 && j > 0 && grid[i - 1][j - 1] == * ) cnt++; if (i > 0 && j < m - 1 && grid[i - 1][j + 1] == * ) cnt++; if (i < n - 1 && j > 0 && grid[i + 1][j - 1] == * ) cnt++; if (i < n - 1 && j < m - 1 && grid[i + 1][j + 1] == * ) cnt++; if (cnt != k) { printf( NO ); return 1; } return 0; } int main() { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { cin >> grid[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (grid[i][j] == . ) { int check = check_bomb(i, j); if (check == 1) return 0; } else if (grid[i][j] >= 1 && grid[i][j] <= 9 ) { int bomb = count_bomb(i, j); if (bomb == 1) return 0; } } } printf( YES ); return 0; }
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#include <bits/stdc++.h> using namespace std; void Swap(int &a, int &b) { a = a ^ b; b = a ^ b; a = a ^ b; } int Max(int a, int b) { if (a > b) return a; return b; } int Scan() { int res = 0; char ch; ch = getchar(); if (ch >= 0 && ch <= 9 ) res = ch - 0 ; while ((ch = getchar()) >= 0 && ch <= 9 ) res = res * 10 + (ch - 0 ); return res; } int main() { int T = Scan(); int X = 0, Y = 0; while (T--) { char c; cin >> c; int a = Scan(); int b = Scan(); if (a < b) Swap(a, b); if (c == + ) X = Max(X, a), Y = Max(Y, b); else if (a >= X && b >= Y) cout << YES n ; else cout << NO n ; } }
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/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
/*
* the module of constants
*
* addr out effective
* 1 0 1
* 2 1 1
* 4 + 1
* 8 - 1
* 16 cubic 1
* other 0 0
*/
module const_ (clk, addr, out, effective);
input clk;
input [5:0] addr;
output reg [`WIDTH_D0:0] out;
output reg effective; // active high if out is effective
always @ (posedge clk)
begin
effective <= 1;
case (addr)
1: out <= 0;
2: out <= 1;
4: out <= {6'b000101, 1002'd0};
8: out <= {6'b001001, 1002'd0};
16: out <= {6'b010101, 1002'd0};
default:
begin out <= 0; effective <= 0; end
endcase
end
endmodule
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#include <bits/stdc++.h> long long int binpow(long long int a, long long int b) { if (b == 0) return 1; long long int res = binpow(a, b / 2); if (b % 2) return res * res * a; else return res * res; } using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> v(n, 0); for (int i = 0; i < v.size(); i++) cin >> v[i]; sort(v.begin(), v.end(), greater<int>()); for (int i = 0; i < n; i++) cout << v[i] << ; cout << endl; } return 0; }
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