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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_SYMBOL_V
`define SKY130_FD_SC_MS__NAND4BB_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_SYMBOL_V
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: RF writeback mux for espresso pipeline
Choose between ALU and LSU input. All combinatorial
Copyright (C) 2012 Authors
Author(s): Julius Baxter <>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_wb_mux_espresso
(/*AUTOARG*/
// Outputs
rf_result_o,
// Inputs
clk, rst, alu_result_i, lsu_result_i, ppc_i, pc_fetch_next_i,
spr_i, op_jal_i, op_lsu_load_i, op_mfspr_i
);
parameter OPTION_OPERAND_WIDTH = 32;
input clk, rst;
input [OPTION_OPERAND_WIDTH-1:0] alu_result_i;
input [OPTION_OPERAND_WIDTH-1:0] lsu_result_i;
input [OPTION_OPERAND_WIDTH-1:0] ppc_i;
input [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_i;
input [OPTION_OPERAND_WIDTH-1:0] spr_i;
output [OPTION_OPERAND_WIDTH-1:0] rf_result_o;
input op_jal_i;
input op_lsu_load_i;
input op_mfspr_i;
assign rf_result_o = op_lsu_load_i ? lsu_result_i :
op_mfspr_i ? spr_i :
// Use the PC we've calcuated from the fetch unit
// to save inferring a 32-bit adder here like we
// would if we did "ppc_i + 8"
op_jal_i ? pc_fetch_next_i:
alu_result_i;
endmodule // mor1kx_wb_mux_espresso
|
#include<bits/stdc++.h> using namespace std; #define ll long long int #define v vector<ll> #define pb push_back #define fr(i,a,n) for(ll i=a;i<n;i++) #define Fast ios::sync_with_stdio(false);cin.tie(NULL); #define in(a) ll a;cin>>a #define ip(a) string a;cin>>a #define R(a,n) for(int i=0;i<n;i++)cin>>a[i]; #define all(a) sort(a.begin(),a.end()) #define e endl #define MOD (int)1e9 + 7 inline ll powe(ll a,ll b , ll p = MOD){ ll ans=1;for(;b;b>>=1){if(b&1) ans=ans*a%p;a=a*a%p;} return ans;} void solve(){ in(n); if(n==2)cout<< -1 <<e; else{ ll pp=1; ll size=n*n; fr(i,0,n){ fr(j,0,n){ cout<<pp<< ; if(pp+2>size){ pp=2; } else{ pp+=2; } } cout<<e; } } } int main() { Fast ll t;cin>>t; while(t--){ solve(); } }
|
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency simulation mode. In this
// case just pass everything through to the ARM, which can bit-bang this
// (because it is so slow).
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module lo_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
// No logic, straight through.
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign ssp_clk = cross_lo;
assign pwr_lo = 1'b0;
assign pwr_hi = 1'b0;
assign dbg = ssp_frame;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
assign adc_clk = ~clk_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above 200
// Set to low if the ADC value is below 64
reg is_high;
reg is_low;
reg output_state;
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd200);
is_low = (adc_d <= 8'd64);
end
end
always @(posedge is_high or posedge is_low)
begin
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
end
assign ssp_frame = output_state;
endmodule
|
//==================================================================================================
// Filename : musoc.v
// Created On : 2015-01-10 21:18:59
// Last Modified : 2015-05-31 21:23:11
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Implementation of the SoC:
// - Core
// - XBAR
// - RAM
// - GPIO
// - UART/Bootloader
//==================================================================================================
module musoc#(
parameter SIM_MODE = "NONE", // Simulation Mode. "SIM" = simulation. "NONE": synthesis mode.
// Core configuration
parameter ENABLE_HW_MULT = 1, // Implement the multiplier
parameter ENABLE_HW_DIV = 1, // Implement the divider
parameter ENABLE_HW_CLO_Z = 1, // Enable CLO/CLZ instructions
// UARTboot
parameter BUS_FREQ = 50, // Bus frequency
// Memory
parameter MEM_ADDR_WIDTH = 12 // 16 KB/4 KW of internal memory
)(
input clk,
input rst,
output halted,
// GPIO
inout [31:0] gpio_a_inout,
// UART
input uart_rx,
output uart_tx
);
//--------------------------------------------------------------------------
// wires
//--------------------------------------------------------------------------
// master
wire [31:0] master0_address;
wire [3:0] master0_wr;
wire master0_enable;
wire master0_ready;
wire master0_error;
wire [31:0] master1_address;
wire [31:0] master1_data_i;
wire [3:0] master1_wr;
wire master1_enable;
wire master1_ready;
wire master1_error;
wire [31:0] master2_address;
wire [31:0] master2_data_i;
wire [3:0] master2_wr;
wire master2_enable;
wire master2_ready;
wire master2_error; // unused (Bootloader)
wire [31:0] master_data_o;
// slaves
wire [31:0] slave0_data_i;
wire [31:0] slave1_data_i;
wire [31:0] slave2_data_i;
wire slave0_enable;
wire slave1_enable;
wire slave2_enable;
wire slave0_ready;
wire slave1_ready;
wire slave2_ready;
wire [31:0] slave_address;
wire [31:0] slave_data_o;
wire [3:0] slave_wr;
wire [31:0] ms_address;
wire [31:0] ms_data_oi;
wire [31:0] ms_data_io;
wire [3:0] ms_wr;
wire ms_enable;
wire ms_ready;
wire ms_error;
wire [3:0] gpio_interrupt;
wire uart_rx_ready_int;
wire bootloader_reset_core;
wire rst_module;
wire clk_core;
wire clk_bus;
//--------------------------------------------------------------------------
// Clock frequency generator.
//--------------------------------------------------------------------------
clk_generator clock_manager(
.clk_i ( clk ),
.clk_core ( clk_core ),
.clk_bus ( clk_bus )
);
//--------------------------------------------------------------------------
// Reset Manager
// Hold reset for 8 cycles
//--------------------------------------------------------------------------
rst_generator reset_manager(
.clk ( clk_core ),
.rst_i ( rst ),
.rst_o ( rst_module )
);
//--------------------------------------------------------------------------
// MIPS CORE
//--------------------------------------------------------------------------
musb_core #(
.ENABLE_HW_MULT ( ENABLE_HW_MULT ),
.ENABLE_HW_DIV ( ENABLE_HW_DIV ),
.ENABLE_HW_CLO_Z ( ENABLE_HW_CLO_Z )
)
musb_core0(/*AUTOINST*/
.halted ( halted ),
.iport_address ( master0_address[31:0] ),
.iport_wr ( master0_wr[3:0] ),
.iport_enable ( master0_enable ),
.dport_address ( master1_address[31:0] ),
.dport_data_o ( master1_data_i[31:0] ),
.dport_wr ( master1_wr[3:0] ),
.dport_enable ( master1_enable ),
.clk ( clk_core ),
.rst_i ( rst_module | bootloader_reset_core ),
.interrupts ( {uart_rx_ready_int, gpio_interrupt[3:0]} ),
.nmi ( 1'b0 ),
.iport_data_i ( master_data_o[31:0] ),
.iport_ready ( master0_ready ),
.iport_error ( master0_error ),
.dport_data_i ( master_data_o[31:0] ),
.dport_ready ( master1_ready ),
.dport_error ( master1_error )
);
//--------------------------------------------------------------------------
// XBAR
//--------------------------------------------------------------------------
arbiter #(
.nmasters(3)
)
arbiter0(/*autoinst*/
.clk ( clk_bus ),
.rst ( rst_module ),
.master_address ( {master2_address[31:0], master1_address[31:0], master0_address[31:0]} ),
.master_data_i ( {master2_data_i[31:0], master1_data_i[31:0], 32'hDEAD_C0DE} ),
.master_wr ( {master2_wr[3:0], master1_wr[3:0], master0_wr[3:0]} ),
.master_enable ( {master2_enable, master1_enable ,master0_enable} ),
.master_data_o ( master_data_o[31:0] ),
.master_ready ( {master2_ready, master1_ready, master0_ready} ),
.master_error ( {master2_error, master1_error, master0_error} ),
.slave_data_i ( ms_data_io[31:0] ),
.slave_ready ( ms_ready ),
.slave_error ( ms_error ),
.slave_address ( ms_address[31:0] ),
.slave_data_o ( ms_data_oi[31:0] ),
.slave_wr ( ms_wr[3:0] ),
.slave_enable ( ms_enable )
);
mux_switch #(
.nslaves (3),
// Slaves
// To generate the mask (easy way): (32'hFFFF_FFFF << N-bits).
// TODO: find a way to get "N-bits" (non-magical way).
// UART GPIO Internal Memory
// 3-bits 5-bits (MEM_ADDR_WIDTH)-bits
.MATCH_ADDR ({32'h1100_0000, 32'h1000_0000, 32'h0000_0000}), // Adjust the mask to avoid address aliasing.
.MATCH_MASK ({32'hFFFF_FFF8, 32'hFFFF_FFE0, 32'hFFFF_0000}) // Adjust the mask to avoid address aliasing.
)
mux_switch0(
.clk ( clk_bus ),
.master_address ( ms_address[31:0] ),
.master_data_i ( ms_data_oi[31:0] ),
.master_wr ( ms_wr[3:0] ),
.master_enable ( ms_enable ),
.master_data_o ( ms_data_io[31:0] ),
.master_ready ( ms_ready ),
.master_error ( ms_error ),
.slave_data_i ( {slave2_data_i[31:0], slave1_data_i[31:0], slave0_data_i[31:0]} ),
.slave_ready ( {slave2_ready, slave1_ready, slave0_ready} ),
.slave_address ( slave_address[31:0] ),
.slave_data_o ( slave_data_o[31:0] ),
.slave_wr ( slave_wr[3:0] ),
.slave_enable ( {slave2_enable, slave1_enable, slave0_enable} )
);
//--------------------------------------------------------------------------
// Internal memory
//--------------------------------------------------------------------------
memory #(
.addr_size( MEM_ADDR_WIDTH ) // Memory size
)
memory0(
.clk ( clk_bus ),
.rst ( rst_module ),
.a_addr ( slave_address[2 +: MEM_ADDR_WIDTH] ), // MEM_ADDR_WIDTH bits address.
.a_din ( slave_data_o[31:0] ),
.a_wr ( slave_wr[3:0] ),
.a_enable ( slave0_enable ),
.a_dout ( slave0_data_i[31:0] ),
.a_ready ( slave0_ready ),
.b_addr ( ), // DO NOT CONNECT
.b_din ( ), // DO NOT CONNECT
.b_wr ( ), // DO NOT CONNECT
.b_enable ( ), // DO NOT CONNECT
.b_dout ( ), // DO NOT CONNECT
.b_ready ( ) // DO NOT CONNECT
);
//--------------------------------------------------------------------------
// I/O
//--------------------------------------------------------------------------
gpio gpio0(/*autoinst*/
.gpio_inout ( gpio_a_inout[31:0] ),
.gpio_data_o ( slave1_data_i[31:0] ),
.gpio_ready ( slave1_ready ),
.gpio_interrupt ( gpio_interrupt[3:0] ),
.clk ( clk_bus ),
.rst ( rst_module ),
.gpio_address ( slave_address[4:0] ),
.gpio_data_i ( slave_data_o[31:0] ),
.gpio_wr ( slave_wr[3:0] ),
.gpio_enable ( slave1_enable )
);
uart_bootloader #(
.SIM_MODE ( SIM_MODE ), // Simulation Mode
.BUS_FREQ ( BUS_FREQ ) // Bus frequency
)
uart_bootloader0(
.clk ( clk_bus ),
.rst ( rst_module ),
.uart_address ( slave_address[2:0] ),
.uart_data_i ( slave_data_o[7:0] ),
.uart_wr ( slave_wr[0] ),
.uart_enable ( slave2_enable ),
.uart_data_o ( slave2_data_i[31:0] ),
.uart_ready ( slave2_ready ),
.boot_master_data_i ( master_data_o[31:0] ),
.boot_master_ready ( master2_ready ),
.boot_master_address ( master2_address[31:0] ),
.boot_master_data_o ( master2_data_i[31:0] ),
.boot_master_wr ( master2_wr[3:0] ),
.boot_master_enable ( master2_enable ),
.uart_rx_ready_int ( uart_rx_ready_int ), // unused.
.uart_rx_full_int ( ), // unused.
.bootloader_reset_core ( bootloader_reset_core ),
.uart_rx ( uart_rx ),
.uart_tx ( uart_tx )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct camel { int pos; int tof; }; int main() { cout << setprecision(8) << fixed; double l, d, v, g, r; cin >> l >> d >> v >> g >> r; double temp; double T; temp = d / v; double q; bool yer = 1; while (temp >= 0) { if (yer) { temp -= g; T = 0; yer = !yer; } else { T = r - temp; temp -= r; yer = !yer; } } cout << ((l / v) + T); }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 520; long long A[N]; long long dp[N]; long long maxl[N]; long long n, m; long long get(long long x, long long y) { if (x == 0) return N - 1; return (x - 1) * m + y; } int main() { cin >> n >> m; A[N - 1] = 0; for (long long i = 1; i <= n * m; i++) cin >> A[i]; for (long long i = 1; i <= m; i++) for (long long j = 1; j <= n; j++) { if (j == 1) { long long a = get(j, i); dp[a] = 1; maxl[j] = max(maxl[j], 1ll); continue; } long long a = get(j, i); long long b = get(j - 1, i); long long xia = A[a]; long long shang = A[b]; if (xia >= shang) { dp[a] = dp[b] + 1; maxl[j] = max(maxl[j], dp[a]); } else { dp[a] = 1; maxl[j] = max(maxl[j], dp[a]); } } long long t; cin >> t; while (t--) { long long l, r; cin >> l >> r; if (r - maxl[r] + 1 <= l) { cout << Yes << endl; continue; } cout << No << endl; } }
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: linebuf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.1 Build 190 01/19/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module linebuf (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [23:0] data;
input [11:0] rdaddress;
input rdclock;
input [11:0] wraddress;
input wrclock;
input wren;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "98304"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 12 0 INPUT NODEFVAL "rdaddress[11..0]"
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
// Retrieval info: USED_PORT: wraddress 0 0 12 0 INPUT NODEFVAL "wraddress[11..0]"
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 wraddress 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 rdaddress 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`define WIDTH_P ?
`define PERIOD 10
module test_bsg;
// Enable VPD file dump
initial
begin
$vcdpluson;
$vcdplusmemon;
end
longint ticks = 0;
longint t1 = 0;
longint t2 = 0;
logic clock_in;
logic clock_out;
logic reset;
logic [`WIDTH_P-1:0] value;
bsg_nonsynth_clock_gen #(`PERIOD) clk_gen (clock_in);
bsg_counter_clock_downsample #(.width_p(`WIDTH_P)) DUT
(.clk_i(clock_in)
,.reset_i(reset)
,.val_i(value)
,.clk_r_o(clock_out)
);
initial
begin
$display(" ");
$display("***********************************************************");
$display("* *");
$display("* SIMULATION BEGIN *");
$display("* *");
$display("***********************************************************");
$display(" ");
value = `WIDTH_P'd0;
reset = 1'b0;
@(negedge clock_in);
reset = 1'b1;
@(negedge clock_in);
reset = 1'b0;
// Check each overflow value for the downsampler
for (integer i = 0; i < 2**`WIDTH_P; i++)
begin
// set the overflow value
value = i;
// Measure the output clock period
@(posedge clock_out);
t1 = ticks;
@(posedge clock_out);
t2 = ticks;
// Assert the expected period
assert(t2-t1 == 2*`PERIOD*(i+1))
$display("Passed: val=%d -- per=%-d", value, t2-t1);
else
$error("Failed: val=%-d -- per=%-d -- expected per=%-d", value, t2-t1, 2*`PERIOD*(i+1));
end
$display(" ");
$display("***********************************************************");
$display("* *");
$display("* SIMULATION FINISHED *");
$display("* *");
$display("***********************************************************");
$display(" ");
$finish;
end
always #1 ticks = ticks + 1;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 14:48:00 01/25/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #2 Project
// Module Name: CLS_Scan_Rate_Timer
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v15.0
// Description: CLS Scan Rate Timer
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module CLS_Scan_Rate_Timer
#(
parameter CLK_RATE_HZ = 50000000 // Hz
)
(
// Input Signals
input [1:0] RATE_SELECT,
// Output Signals
output reg SRT_TICK,
// System Signals
input CLK
);
// Include Standard Functions header file (needed for bit_index())
`include "StdFunctions.vh"
//
// Compute Parameter Values used by the rollover counters
//
// Set the scan rate frequency
localparam SCAN_RATE_FASTER = 32; // Hz
localparam SCAN_RATE_FAST = 16; // Hz
localparam SCAN_RATE_SLOW = 8; // Hz
localparam SCAN_RATE_SLOWER = 2; // Hz
// Compute maximum number of ticks to set the counter reg width
localparam SRT_TICKS_MAX = CLK_RATE_HZ / SCAN_RATE_SLOWER;
localparam SRT_REG_WIDTH = bit_index(SRT_TICKS_MAX);
// Compute number of ticks for each scan rate
localparam [SRT_REG_WIDTH:0] SRT_TICKS_FASTER = 1.0 * CLK_RATE_HZ / SCAN_RATE_FASTER;
localparam [SRT_REG_WIDTH:0] SRT_TICKS_FAST = 1.0 * CLK_RATE_HZ / SCAN_RATE_FAST;
localparam [SRT_REG_WIDTH:0] SRT_TICKS_SLOW = 1.0 * CLK_RATE_HZ / SCAN_RATE_SLOW;
localparam [SRT_REG_WIDTH:0] SRT_TICKS_SLOWER = 1.0 * CLK_RATE_HZ / SCAN_RATE_SLOWER;
// Compute the rollover counter load values for each scan rate
localparam [SRT_REG_WIDTH:0] SRT_FASTER_LOADVAL = {1'b1, {(SRT_REG_WIDTH){1'b0}}} - SRT_TICKS_FASTER + 1'b1;
localparam [SRT_REG_WIDTH:0] SRT_FAST_LOADVAL = {1'b1, {(SRT_REG_WIDTH){1'b0}}} - SRT_TICKS_FAST + 1'b1;
localparam [SRT_REG_WIDTH:0] SRT_SLOW_LOADVAL = {1'b1, {(SRT_REG_WIDTH){1'b0}}} - SRT_TICKS_SLOW + 1'b1;
localparam [SRT_REG_WIDTH:0] SRT_SLOWER_LOADVAL = {1'b1, {(SRT_REG_WIDTH){1'b0}}} - SRT_TICKS_SLOWER + 1'b1;
reg [SRT_REG_WIDTH:0] srt_cnt_loadval;
reg [SRT_REG_WIDTH:0] srt_cnt_reg;
wire srt_cnt_tick;
// Initial register settings
initial
begin
SRT_TICK = 1'b0;
srt_cnt_loadval = SRT_FASTER_LOADVAL;
srt_cnt_reg = SRT_FASTER_LOADVAL;
end
//!! Add Implementation Here !!
always @*
begin
case (RATE_SELECT)
2'h0 : srt_cnt_loadval <= SRT_SLOWER_LOADVAL;
2'h1 : srt_cnt_loadval <= SRT_SLOW_LOADVAL;
2'h2 : srt_cnt_loadval <= SRT_FAST_LOADVAL;
2'h3 : srt_cnt_loadval <= SRT_FASTER_LOADVAL;
endcase
end
always @(posedge CLK)
begin
if (srt_cnt_reg[SRT_REG_WIDTH])
srt_cnt_reg <= srt_cnt_loadval;
else
srt_cnt_reg <= srt_cnt_reg + 1'b1;
end
assign srt_cnt_tick = srt_cnt_reg[SRT_REG_WIDTH];
always @(posedge CLK)
begin
SRT_TICK <= srt_cnt_tick;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n, m; vector<long long int> a[200005]; long long int rankof[200005]; long long int parentof[200005]; long long int maxof[200005]; void initialize() { for (long long int i = 0; i <= 200005; i++) { rankof[i] = 1; parentof[i] = i; maxof[i] = i; } } long long int root(long long int x) { if (x == parentof[x]) { return x; } parentof[x] = root(parentof[x]); return parentof[x]; } void combine(long long int x, long long int y) { x = root(x); y = root(y); long long int maxx = max(maxof[x], maxof[y]); if (x != y) { if (rankof[x] >= rankof[y]) { parentof[y] = x; rankof[x] += rankof[y]; maxof[x] = maxx; } else { parentof[x] = y; rankof[y] += rankof[x]; maxof[y] = maxx; } } return; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int i, j; cin >> n >> m; initialize(); for (i = 0; i < m; i++) { long long int u, v; cin >> u >> v; combine(u, v); } long long int curmax, cnt = 0; for (i = 1; i <= n;) { curmax = maxof[root(i)]; j = i + 1; while (j <= curmax) { if (root(j) != root(i)) { combine(i, j); cnt++; } curmax = maxof[root(i)]; j++; } i = j; } cout << cnt; return 0; }
|
#include <bits/stdc++.h> using namespace std; int q, n, a[200000 + 5], cnt[200000 + 5]; int main() { scanf( %d , &q); for (; q--;) { memset(cnt, 0, sizeof(cnt)); int sum1 = 0, sum2 = 0, tot = 0, m = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); cnt[a[i]]++; m = max(a[i], m); } if (m % 30 == 0 && cnt[m / 2] && cnt[m / 3] && cnt[m / 5]) sum1 = m / 30 * 31; for (int i = 200000; i >= 1; i--) if (cnt[i]) { for (int j = i - 1; j >= 1; j--) if (i % j == 0) cnt[j] = 0; tot++; sum2 += i; if (tot == 3) break; } printf( %d n , max(sum1, sum2)); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A22OI_FUNCTIONAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a22oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_FUNCTIONAL_PP_V
|
/***************************************************************************************************
** fpga_nes/hw/src/cmn/fifo/fifo.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Circular first in first out buffer implementation.
***************************************************************************************************/
module fifo
#(
parameter DATA_BITS = 8,
parameter ADDR_BITS = 3
)
(
input wire clk, // 50MHz system clock
input wire reset, // Reset signal
input wire rd_en, // Read enable, pop front of queue
input wire wr_en, // Write enable, add wr_data to end of queue
input wire [DATA_BITS-1:0] wr_data, // Data to be written on wr_en
output wire [DATA_BITS-1:0] rd_data, // Current front of fifo data
output wire full, // FIFO is full (writes invalid)
output wire empty // FIFO is empty (reads invalid)
);
reg [ADDR_BITS-1:0] q_rd_ptr;
wire [ADDR_BITS-1:0] d_rd_ptr;
reg [ADDR_BITS-1:0] q_wr_ptr;
wire [ADDR_BITS-1:0] d_wr_ptr;
reg q_empty;
wire d_empty;
reg q_full;
wire d_full;
reg [DATA_BITS-1:0] q_data_array [2**ADDR_BITS-1:0];
wire [DATA_BITS-1:0] d_data;
wire rd_en_prot;
wire wr_en_prot;
// FF update logic. Synchronous reset.
always @(posedge clk)
begin
if (reset)
begin
q_rd_ptr <= 0;
q_wr_ptr <= 0;
q_empty <= 1'b1;
q_full <= 1'b0;
end
else
begin
q_rd_ptr <= d_rd_ptr;
q_wr_ptr <= d_wr_ptr;
q_empty <= d_empty;
q_full <= d_full;
q_data_array[q_wr_ptr] <= d_data;
end
end
// Derive "protected" read/write signals.
assign rd_en_prot = (rd_en && !q_empty);
assign wr_en_prot = (wr_en && !q_full);
// Handle writes.
assign d_wr_ptr = (wr_en_prot) ? q_wr_ptr + 1'h1 : q_wr_ptr;
assign d_data = (wr_en_prot) ? wr_data : q_data_array[q_wr_ptr];
// Handle reads.
assign d_rd_ptr = (rd_en_prot) ? q_rd_ptr + 1'h1 : q_rd_ptr;
wire [ADDR_BITS-1:0] addr_bits_wide_1;
assign addr_bits_wide_1 = 1;
// Detect empty state:
// 1) We were empty before and there was no write.
// 2) We had one entry and there was a read.
assign d_empty = ((q_empty && !wr_en_prot) ||
(((q_wr_ptr - q_rd_ptr) == addr_bits_wide_1) && rd_en_prot));
// Detect full state:
// 1) We were full before and there was no read.
// 2) We had n-1 entries and there was a write.
assign d_full = ((q_full && !rd_en_prot) ||
(((q_rd_ptr - q_wr_ptr) == addr_bits_wide_1) && wr_en_prot));
// Assign output signals to appropriate FFs.
assign rd_data = q_data_array[q_rd_ptr];
assign full = q_full;
assign empty = q_empty;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k, l, r, st; map<pair<long long, long long>, long long> M[2]; long long Count(long long len, long long t, bool w) { if (M[w].count({len, t})) return (M[w][{len, t}]); if (t > len) return (M[w][{len, t}] = 0); if (len == t) return (M[w][{len, t}] = 1); return (M[w][{len, t}] = Count(len / 2, t, w) + Count((len - 1) / 2, t, w) + w); } long long get(long long len, long long t) { return (Count(len, t, 0) + Count(len, t + 1, 0)); } int main() { scanf( %I64d%I64d , &n, &k); if (k == 1) return !printf( 1 ); if (k == 2) return !printf( %I64d , n); n -= 2; k -= 2; l = 1; r = n; while (r - l > 1) { if (k > Count(n, (l + r) / 2 * 2 - 1, 1)) r = (l + r) / 2; else l = (l + r) / 2; } st = l * 2 - 1; l = 1; r = n; k -= Count(n, st + 2, 1); while (get(r - l + 1, st) && !(st == 1 && r - l <= 1)) { if (k <= get((l + r) / 2 - l, st)) r = (l + r) / 2 - 1; else k -= get((l + r) / 2 - l, st), l = (l + r) / 2 + 1; } if (st == 1 && r - l <= 1) l += k; return !printf( %I64d , l); }
|
`timescale 1ns/10ps
module ssram
(
// global
input wire clk_i,
input wire clk_en_i,
input wire reset_i,
//
output wire treqready_o,
input wire treqvalid_i,
input wire treqdvalid_i,
input wire [31:0] treqaddr_i,
input wire [31:0] treqdata_i,
input wire trspready_i,
output reg trspvalid_o,
output reg [31:0] trspdata_o
);
//--------------------------------------------------------------
parameter C_SSRAM_SZBX = 22;
parameter C_SSRAM_SZB = 2**C_SSRAM_SZBX;
//
parameter C_VIRTUAL_UART = 32'h80000000;
//
reg [7:0] mem[0:C_SSRAM_SZB-1];
wire [C_SSRAM_SZBX-1:0] reqaddr;
//--------------------------------------------------------------
assign treqready_o = treqvalid_i;
initial
begin
$display("********************************************************");
$display("SSRAM Size = %0d Ki Bytes.", 2**(C_SSRAM_SZBX-10));
$display("\nWrites to address 0x%08X will be interpreted as\nASCII characters and will be printed to the console.", C_VIRTUAL_UART);
$display("\nWrites to address 0xFFFFFFFC will be end the simulation.");
$display("********************************************************");
$readmemh("mem.hex", mem);
end
//
//
assign reqaddr = treqaddr_i[C_SSRAM_SZBX-1:0];
always @ (posedge clk_i or posedge reset_i)
begin
if (reset_i) begin
trspvalid_o <= 1'b0;
trspdata_o <= 32'hbaadf00d;
end else if (clk_en_i) begin
if (treqvalid_i) begin
trspvalid_o <= 1'b0;
if (treqdvalid_i) begin
if (treqaddr_i == C_VIRTUAL_UART) begin
$write("%c", treqdata_i[7:0]);
$fflush();
end else if (treqaddr_i == 32'hfffffffc) begin
$display();
$display();
$display("(%0tns) Program wrote to address 0xFFFFFFFC => End of test!", $time/100.0);
$display("******************** SIMULATION END ********************");
$finish();
end else if (treqaddr_i == reqaddr) begin
mem[reqaddr+3] <= treqdata_i[31:24];
mem[reqaddr+2] <= treqdata_i[23:16];
mem[reqaddr+1] <= treqdata_i[15: 8];
mem[reqaddr+0] <= treqdata_i[ 7: 0];
`ifdef TESTBENCH_DBG_MSG
$display("SSRAM Write: ADDR=0x%08X, DATA=0x%08X", treqaddr_i, treqdata_i);
`endif
end else begin
$display("FATAL ERROR (%0t): Memory Write Out Of Range! Address 0x%08X", $time, treqaddr_i);
$fatal();
end
end else begin
trspvalid_o <= 1'b1;
if (treqaddr_i == reqaddr) begin
trspdata_o <= { mem[reqaddr+3], mem[reqaddr+2], mem[reqaddr+1], mem[reqaddr+0] };
`ifdef TESTBENCH_DBG_MSG
$display("SSRAM Read : ADDR=0x%08X, DATA=0x%08X", treqaddr_i, { mem[reqaddr+3], mem[reqaddr+2], mem[reqaddr+1], mem[reqaddr+0] });
`endif
end else begin
$display("FATAL ERROR (%0t): Memory Read Out Of Range! Address 0x%08X", $time, treqaddr_i);
$fatal();
end
end
end else begin
trspvalid_o <= 1'b0;
trspdata_o <= 32'hbaadf00d;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i, n, sum = 0, t; vector<int> a; cin >> n; for (i = 0; i < n; i++) { cin >> t; sum += t; a.push_back(sum); } cin >> n; for (i = 0; i < n; i++) { cin >> t; cout << lower_bound(a.begin(), a.end(), t) - a.begin() + 1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char str[50][50]; bool test(int a, int b, int w, int h) { int i, j; for (i = 0; i <= w; i++) { for (j = 0; j <= h; j++) { if (str[i + a][j + b] == 1 ) return 0; } } return 1; } int main() { int n, m, i, j, k, r; scanf( %d %d , &n, &m); for (i = 0; i < n; i++) { scanf( %s , str[i]); } int ans = 0; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { for (k = 0; k + i < n; k++) { for (r = 0; r + j < m; r++) { if (test(i, j, k, r)) { if (2 * (k + r + 2) > ans) ans = 2 * (k + 2 + r); } } } } } printf( %d n , ans); return 0; }
|
`timescale 1ns/1ps
module I2CFSM (
input Reset_n_i,
input Clk_i,
// FSM control
input QueryLocal_i,
input QueryRemote_i,
output reg Done_o,
output reg Error_o,
output reg [7:0] Byte0_o,
output reg [7:0] Byte1_o,
// to/from I2C_Master
// I2C control
output reg I2C_ReceiveSend_n_o,
output reg [7:0] I2C_ReadCount_o,
output reg I2C_StartProcess_o,
input I2C_Busy_i,
// I2C FIFO
output reg I2C_FIFOReadNext_o,
output reg I2C_FIFOWrite_o,
output reg [7:0] I2C_Data_o,
input [7:0] I2C_Data_i,
// I2C error
input I2C_Error_i
);
// TMP421 I2C Temperature Sensor
// - has local sensor and a remote sensor (TMP422 has 2 remote, TMP423 has 3 remote)
// - default configuration (without dedicated setup):
// - run (=periodic measurements)
// - local and external channel 1 enabled
// - 8 conversions/second (but reduced to 4 per second due to two enabled channels)
// - read local temperature:
// - set pointer register: "10011000" "00000000"
// - read 2 bytes: "10011001" "mmmmmmmm" "llll00ff"
// - read remote temperature:
// - set pointer register: "10011000" "00000001"
// - read 2 bytes: "10011001" "mmmmmmmm" "llll00ff"
//
// I2C Master
// - write address + N bytes, see I2C Bus Controller Documentation, testcase 4
// - ReceiveSend_o = '0'
// - FIFOWrite_o = '1', Data_o = ..., N+1 cycles
// - FIFOWrite_o = '0', StartProcess_o = '1' for 1 cycles only, Busy_i
// goes high immediately <-- really?
// - wait until Busy_i goes low again
// - read N bytes, see testcase 7
// - ReceiveSend_o = '1', ReadCount_o = N
// - FIFOWrite_o = '1', Data_o = address, 1 cycle
// - FIFOWrite_o = '0', StartProcess_o = '1' for 1 cycles only, Busy_i
// goes high immediately
// - wait until Busy_i goes low again
// - read bytes from FIFO via Data_i and FIFOReadNext_o
//
// I2C FSM
localparam stIdle = 4'd0;
localparam stReqLocWrPtr = 4'd1; // I2C transfer: set pointer register to local temperature register
localparam stReqLocStart = 4'd2;
localparam stReqLocWait = 4'd3;
localparam stReqRemWrPtr = 4'd4; // I2C transfer: set pointer register to local temperature register
localparam stReqRemStart = 4'd5;
localparam stReqRemWait = 4'd6;
localparam stReadWrRdAddr = 4'd7; // I2C transfer: read 2 bytes and store to Byte1_o and Byte0_o
localparam stRead = 4'd8;
localparam stReadStart = 4'd9;
localparam stReadWait = 4'd10;
localparam stReadStoreLSB = 4'd11;
localparam stPause = 4'd12;
reg [3:0] I2C_FSM_State;
reg [3:0] I2C_FSM_NextState;
wire I2C_FSM_TimerOvfl;
reg I2C_FSM_TimerPreset;
reg I2C_FSM_TimerEnable;
reg I2C_FSM_Wr1;
reg I2C_FSM_Wr0;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
I2C_FSM_State <= stIdle;
end
else
begin
I2C_FSM_State <= I2C_FSM_NextState;
end
end
always @(I2C_FSM_State, QueryLocal_i, QueryRemote_i, I2C_Busy_i, I2C_Error_i, I2C_FSM_TimerOvfl)
begin // process I2C_FSM_CombProc
I2C_FSM_NextState = I2C_FSM_State;
// control signal default values
Done_o = 1'b0;
Error_o = 1'b0;
// to I2C Master
I2C_ReceiveSend_n_o = 1'b0;
I2C_ReadCount_o = 8'h00;
I2C_StartProcess_o = 1'b0;
I2C_FIFOReadNext_o = 1'b0;
I2C_FIFOWrite_o = 1'b0;
I2C_Data_o = 8'h00;
// to other processes in this module
I2C_FSM_TimerPreset = 1'b1;
I2C_FSM_TimerEnable = 1'b0;
I2C_FSM_Wr1 = 1'b0;
I2C_FSM_Wr0 = 1'b0;
// next state and output logic
case (I2C_FSM_State)
stIdle: begin
if (QueryLocal_i == 1'b1)
begin
// query local temperature: set pointer register
// "10011000" "00000000"
I2C_FSM_NextState = stReqLocWrPtr;
I2C_Data_o = 8'b10011000;
I2C_FIFOWrite_o = 1'b1;
end
else if (QueryRemote_i == 1'b1)
begin
// query local temperature: set pointer register
// "10011000" "00000001"
I2C_FSM_NextState = stReqRemWrPtr;
I2C_Data_o = 8'b10011000;
I2C_FIFOWrite_o = 1'b1;
end
else
begin
// nobody cares about the value, so simplify the MUX
I2C_Data_o = 8'b10011000;
end
end
stReqLocWrPtr: begin
I2C_FSM_NextState = stReqLocStart;
I2C_Data_o = 8'b00000000;
I2C_FIFOWrite_o = 1'b1;
end
stReqLocStart: begin
I2C_StartProcess_o = 1'b1;
I2C_FSM_NextState = stReqLocWait;
end
stReqLocWait: begin
// wait until I2C transmission has finished
if (I2C_Error_i == 1'b1)
begin
I2C_FSM_NextState = stIdle;
Error_o = 1'b1;
end
else if (I2C_Busy_i == 1'b0)
begin
I2C_FSM_NextState = stRead;
end
end
stReqRemWrPtr: begin
I2C_FSM_NextState = stReqRemStart;
I2C_Data_o = 8'b00000001;
I2C_FIFOWrite_o = 1'b1;
end
stReqRemStart: begin
I2C_StartProcess_o = 1'b1;
I2C_FSM_NextState = stReqRemWait;
end
stReqRemWait: begin
// wait until I2C transmission has finished
if (I2C_Error_i == 1'b1)
begin
I2C_FSM_NextState = stIdle;
Error_o = 1'b1;
end
else if (I2C_Busy_i == 1'b0)
begin
I2C_FSM_NextState = stRead;
end
end
stRead: begin
// read value: initiate I2C read transfer
I2C_FSM_NextState = stReadStart;
I2C_Data_o = 8'b10011001;
I2C_FIFOWrite_o = 1'b1;
end
stReadStart: begin
// start sending read transfer
I2C_ReceiveSend_n_o = 1'b1;
I2C_ReadCount_o = 8'h02;
I2C_StartProcess_o = 1'b1;
I2C_FSM_NextState = stReadWait;
end
stReadWait: begin
I2C_ReceiveSend_n_o = 1'b1;
I2C_ReadCount_o = 8'h02;
// wait until I2C transmission has finished
if (I2C_Busy_i == 1'b0)
begin
I2C_FSM_NextState = stReadStoreLSB;
// consume and store first byte
I2C_FIFOReadNext_o = 1'b1;
I2C_FSM_Wr1 = 1'b1;
end
end
stReadStoreLSB: begin
// consume and store second byte
I2C_FIFOReadNext_o = 1'b1;
I2C_FSM_Wr0 = 1'b1;
I2C_FSM_NextState = stPause;
end
stPause: begin
Done_o = 1'b1;
I2C_FSM_NextState = stIdle;
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Byte-wide Memory /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Byte0_o <= 8'd0;
Byte1_o <= 8'd0;
end
else
begin
if (I2C_FSM_Wr0)
begin
Byte0_o <= I2C_Data_i;
end
if (I2C_FSM_Wr1)
begin
Byte1_o <= I2C_Data_i;
end
end
end
endmodule // I2CFSM
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int next_x[8] = {0, 1, -1, 0, 1, 1, -1, -1}; const int next_y[8] = {1, 0, 0, -1, 1, -1, -1, 1}; const int inf = 1e9 + 5; const long long linf = 1e18 + 5; const double PI = acos(-1.0); const int MAXN = 1e6 + 5; const int N = 4e6 + 5; const long double eps = 1e-8; const long double fix = 1e-2; int n; int a[MAXN], b[MAXN]; int l[MAXN], r[MAXN]; int s[MAXN], h = 0; vector<int> st[MAXN], ed[MAXN]; int cnt[MAXN]; bool flag = 1; struct node { int i; bool operator<(const node &t) const { return r[i] < r[t.i]; } }; int work() { scanf( %d , &n); for (int i = (1), I = (2 * n) + 1; i < I; ++i) { char t[5]; scanf( %s , t); if (t[0] == + ) continue; scanf( %d , &a[i]); } for (int i = (1), I = (2 * n) + 1; i < I; ++i) if (a[i]) { while (h && a[i] > a[s[h]]) --h; l[a[i]] = s[h] + 1, r[a[i]] = i - 1, s[++h] = i; } for (int x = (1), I = (n) + 1; x < I; ++x) st[l[x]].push_back(x), ed[r[x]].push_back(x), flag &= (r[x] >= l[x]); set<node> s; for (int i = (1), I = (2 * n) + 1; i < I; ++i) { for (auto x : st[i]) s.insert({x}); if (!a[i]) { if (s.empty()) flag = 0; else b[i] = s.begin()->i, s.erase(s.begin()); } for (auto x : ed[i]) if (s.find({x}) != s.end()) flag = 0; } for (int i = (1), I = (2 * n) + 1; i < I; ++i) if (b[i]) cnt[b[i]]++; for (int i = (1), I = (n) + 1; i < I; ++i) flag &= (cnt[i] == 1); if (!flag) return puts( NO ); puts( YES ); for (int i = (1), I = (2 * n) + 1; i < I; ++i) if (b[i]) printf( %d , b[i]); return 0; } int main() { work(); return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: playback_dump.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "sys.h"
module playback_dump();
integer fid;
reg clk_start;
reg clk;
initial begin
fid = $fopen("stimuli.txt","w");
clk_start = 1'b0;
clk = 1'b0;
forever #418 clk = ~clk;
end
wire [156:0] input_vector = {
cmp_top.iop.sparc0.pcx_spc_grant_px,
cmp_top.iop.sparc0.cpx_spc_data_rdy_cx2,
cmp_top.iop.sparc0.cpx_spc_data_cx2,
cmp_top.iop.sparc0.cluster_cken,
cmp_top.iop.sparc0.cmp_grst_l,
cmp_top.iop.sparc0.cmp_arst_l,
cmp_top.iop.sparc0.ctu_tst_pre_grst_l,
cmp_top.iop.sparc0.adbginit_l,
cmp_top.iop.sparc0.gdbginit_l};
wire [129:0] output_vector = {
cmp_top.iop.sparc0.spc_pcx_req_pq,
cmp_top.iop.sparc0.spc_pcx_atom_pq,
cmp_top.iop.sparc0.spc_pcx_data_pa};
wire clock_vector = cmp_top.iop.sparc0.gclk;
always @(posedge clk) begin
if(~clk_start) begin
$fdisplay(fid, "%b\n%b\n", input_vector, output_vector);
end
end
always @(posedge clock_vector) begin
clk_start = 1'b1;
$fdisplay(fid, "%b\n%b\n", input_vector, output_vector);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000007; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int n, h; cin >> n >> h; long long int arr[n]; for (long long int i = 0; i < n; i++) cin >> arr[i]; long long int ans = 0; for (long long int i = 0; i < n; i++) { vector<long long int> op; for (long long int j = 0; j <= i; j++) op.push_back(arr[j]); sort(op.begin(), op.end()); if (op.size() == 1) { if (op[0] <= h) ans = i + 1; continue; } long long int sum = 0; for (long long int j = op.size() - 1; j >= 0; j -= 2) sum += op[j]; if (sum <= h) ans = i + 1; else break; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 7, mod = 1e9 + 7, inf = 1e9 + 7; const long long linf = (long long)1e18 + 7; const long double eps = 1e-15, pi = 3.141592; const int dx[] = {-1, 0, 1, 0, 1, -1, -1, 1}, dy[] = {0, 1, 0, -1, 1, -1, 1, -1}; inline long long get_ll() { char x = getchar(); long long ret = 0; while ( 0 <= x && x <= 9 ) ret = (ret << 3LL) + (ret << 1LL) + x - 0 , x = getchar(); return ret; } int n, sz; long long ans; long long a[N], suff[N]; int t[N * 20][2]; inline void add(long long x) { int v = 0; for (int i = 40; i >= 0; --i) { int type = ((x & (1LL << i)) > 0); if (!t[v][type]) t[v][type] = ++sz; v = t[v][type]; } } inline long long get(long long x) { int v = 0; long long res = 0; for (int i = 40; i >= 0; --i) { int type = 1 - ((x & (1LL << i)) > 0); if (t[v][type]) res += 1LL << i, v = t[v][type]; else v = t[v][1 - type]; } return res; } int main() { n = get_ll(); for (int i = 1; i <= n; ++i) a[i] = get_ll(); for (int i = n; i >= 1; --i) suff[i] = suff[i + 1] ^ a[i]; long long pref = 0; add(0); for (int i = 1; i <= n + 1; ++i) { ans = max(ans, get(suff[i])); add(pref ^= a[i]); } cout << ans; exit(0); }
|
#include <bits/stdc++.h> using namespace std; int cnt = 0; int SM[100000]; int ans[500][500][2], FC[500][500][2], H[5]; vector<int> Q[500]; int dfs(int a, int b) { int sum = 0; bool A = false, B = false; for (int i = 0; i < 5; i++) { if (Q[a][i] > 0) { for (int j = 0; j < 5; j++) if (Q[b][j] > 0 && i * j != 0) { sum++; } } } return sum; } struct T { int a, b, c; }; queue<T> G; int main() { int sum = 0, k, g = 10000; for (int i = 0; i < 5; i++) H[i] = g, g /= 10; for (int i = 0; i < 500; i++) for (int j = 0; j < 5; j++) Q[i].push_back(0); for (int i = 1; i < 100000; i++) { int u = 0, p = i + 100000, r = 4; while (p > 1) u += p % 10, Q[cnt][r--] = p % 10, p /= 10; if (u == 8) { SM[i] = cnt; sum++, cnt++; } } for (int i = 0; i < cnt; i++) for (int j = 0; j < cnt; j++) FC[i][j][0] = FC[i][j][1] = dfs(i, j); for (int i = 0; i < cnt; i++) for (int j = 0; j < cnt; j++) for (int k = 0; k < 2; k++) { if (i == cnt - 1) ans[i][j][k] = 1; else if (j == cnt - 1) ans[i][j][k] = 2; else continue; G.push({i, j, k}); } while (!G.empty()) { T p = G.front(); G.pop(); int a = p.a, b = p.b, c = p.c; for (int i = 0; i < 5; i++) if (Q[a][i] > 0) for (int j = 0; j < 5; j++) if (Q[b][j] > 0) { int q = (c == 0 ? b : a), res = 0, l = 10000, f; for (int k = 0; k < 5; k++) res += l * Q[q][k], l /= 10; if (c == 0) { f = (j - i + 5) % 5; if (i == 0 || f == 0) continue; res -= H[j]; res += H[f]; if (ans[a][b][c] == 2) { int& U = ans[a][SM[res]][!c]; if (U == 0) G.push({a, SM[res], !c}); U = 2; } else { if (--FC[a][SM[res]][!c] == 0) { ans[a][SM[res]][!c] = 1; G.push({a, SM[res], !c}); } } } else { f = (i - j + 5) % 5; if (j == 0 || f == 0) continue; res -= H[i]; res += H[f]; if (ans[a][b][c] == 1) { int& U = ans[SM[res]][b][!c]; if (U == 0) G.push({SM[res], b, !c}); U = 1; } else { if (--FC[SM[res]][b][!c] == 0) { ans[SM[res]][b][!c] = 2; G.push({SM[res], b, !c}); } } } } } int t; scanf( %d , &t); while (t--) { int x, h; scanf( %d , &x); int W[5] = {}, g = 10000, a = 0, b = 0; for (int i = 0; i < 8; i++) scanf( %d , &h), W[h]++; for (int i = 0; i < 5; i++) a += g * W[i], g /= 10; g = 10000; int W1[5] = {}; for (int i = 0; i < 8; i++) scanf( %d , &h), W1[h]++; for (int i = 0; i < 5; i++) b += g * W1[i], g /= 10; int res = ans[SM[a]][SM[b]][x]; if (res == 0) cout << Deal n ; else if (res == 1) cout << Alice n ; else if (res == 2) cout << Bob n ; } }
|
// rigidly assume clock = 10mhz.
module rfid_reader_tx (
// basic setup connections
reset, clk, reader_modulation,
// control signals
tx_done, tx_running, tx_go, send_trcal,
// timing information
delim_counts, pw_counts, rtcal_counts, trcal_counts, tari_counts,
// payload information
tx_packet_length, tx_packet_data
);
input reset, clk, send_trcal, tx_go;
output reader_modulation;
output tx_done, tx_running;
input [15:0] delim_counts, pw_counts, rtcal_counts, trcal_counts, tari_counts;
input [6:0] tx_packet_length;
input [127:0] tx_packet_data;
reg [2:0] tx_state;
parameter STATE_IDLE = 3'd0;
parameter STATE_DELIM = 3'd2;
parameter STATE_DATA0 = 3'd3;
parameter STATE_RTCAL = 3'd4;
parameter STATE_TRCAL = 3'd5;
parameter STATE_DATA = 3'd6;
parameter STATE_WAIT_FOR_RX = 3'd7;
reg modout;
assign reader_modulation = modout;
reg [15:0] count;
reg [6:0] current_tx_bit;
reg tx_done, tx_running;
wire current_bit, data0_bit_end, data0_bit_transition, data1_bit_end, data1_bit_transition, bit_transition, bit_end;
wire [15:0] data0_end_count, data1_end_count, data0_tran_count, data1_tran_count;
assign current_bit = tx_packet_data[current_tx_bit];
assign data0_end_count = tari_counts+pw_counts;
assign data1_end_count = tari_counts+tari_counts+pw_counts;
assign data0_tran_count = tari_counts;
assign data1_tran_count = tari_counts+tari_counts;
assign data0_bit_end = (count >= data0_end_count);
assign data0_bit_transition = (count >= data0_tran_count);
assign data1_bit_end = (count >= data1_end_count);
assign data1_bit_transition = (count >= data1_tran_count);
assign bit_transition = data1_bit_transition | (!current_bit & data0_bit_transition);
assign bit_end = data1_bit_end | (!current_bit & data0_bit_end);
wire rtcal_end, rtcal_transition, trcal_end, trcal_transition;
wire [15:0] rtcal_end_count, trcal_end_count;
assign rtcal_end_count = rtcal_counts+pw_counts;
assign trcal_end_count = trcal_counts+pw_counts;
assign rtcal_end = (count >= rtcal_end_count);
assign rtcal_transition = (count >= rtcal_counts);
assign trcal_end = (count >= trcal_end_count);
assign trcal_transition = (count >= trcal_counts);
always @ (posedge clk or posedge reset) begin
if (reset) begin
tx_state <= 0;
modout <= 0;
count <= 0;
current_tx_bit <= 0;
tx_done <= 0;
tx_running <= 0;
end else begin
case(tx_state)
STATE_IDLE: begin
tx_done <= 0;
if(tx_go) begin
tx_state <= STATE_DELIM;
count <= 1;
tx_running <= 1;
modout <= 0;
current_tx_bit <= tx_packet_length - 1;
end else begin
tx_running <= 0;
modout <= 1;
end
end
STATE_DELIM: begin
if( count >= delim_counts ) begin
modout <= 1;
count <= 1;
tx_state <= STATE_DATA0;
end else begin
count <= count + 1;
end
end
STATE_DATA0: begin
if( data0_bit_end ) begin
tx_state <= STATE_RTCAL;
count <= 1;
modout <= 1;
end else if ( data0_bit_transition ) begin
modout <= 0;
count <= count + 1;
end else begin
count <= count + 1;
end
end
STATE_RTCAL: begin
if( rtcal_end ) begin
if (send_trcal) tx_state <= STATE_TRCAL;
else tx_state <= STATE_DATA;
count <= 1;
modout <= 1;
end else if( rtcal_transition ) begin
modout <= 0;
count <= count + 1;
end else begin
count <= count + 1;
end
end
STATE_TRCAL: begin
if( trcal_end ) begin
tx_state <= STATE_DATA;
count <= 1;
modout <= 1;
end else if( trcal_transition ) begin
modout <= 0;
count <= count + 1;
end else begin
count <= count + 1;
end
end
STATE_DATA: begin
if (bit_end) begin
count <= 1;
modout <= 1;
if (current_tx_bit == 0) begin
tx_state <= STATE_WAIT_FOR_RX;
tx_done <= 1;
end else begin
current_tx_bit <= current_tx_bit - 1;
end
end else if (bit_transition) begin
modout <= 0;
count <= count + 1;
end else begin
count <= count + 1;
end
end
STATE_WAIT_FOR_RX: begin
modout <= 1;
if(!tx_go) tx_state <= 0;
end
default: begin
tx_state <= 0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[200005]; int main() { int t; cin >> t; while (t--) { memset(a, 0, sizeof(a)); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); if (a[0] != a[n - 1]) { printf( 1 n ); } else { printf( %d n , n); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct pInfo { int idx; long long reach; pInfo(int i, long long r) { idx = i, reach = r; }; }; long long n, pos[200005], len[200005], R[200005], U[200005][19], S[200005][19], q, a, b; int main() { ios_base::sync_with_stdio(0); cin.tie(0); while (cin >> n) { memset(R, -1, sizeof R); memset(U, -1, sizeof U); for (int i = 0; i < n; ++i) cin >> pos[i] >> len[i]; pos[n] = 9990000000LL; stack<pInfo> st; st.push(pInfo(n, 9990000000LL)); for (int i = n - 1; i >= 0; --i) { long long lim = pos[i] + len[i], reach = lim; while (pos[st.top().idx] <= lim) { reach = max(reach, st.top().reach); st.pop(); } R[i] = reach; U[i][0] = st.top().idx; S[i][0] = max(pos[U[i][0]] - reach, 0LL); st.push(pInfo(i, reach)); } for (int j = 1; j < 19; ++j) { for (int i = 0; i < n; ++i) { if (U[i][j - 1] == -1) continue; U[i][j] = U[U[i][j - 1]][j - 1]; S[i][j] = S[i][j - 1] + S[U[i][j - 1]][j - 1]; } } cin >> q; while (q--) { cin >> a >> b; --a; --b; long long res = 0; while (a >= 0 && a <= b) { int jmp = 0; while (U[a][jmp] >= 0 && U[a][jmp] <= b) jmp++; if (!jmp) break; res += S[a][jmp - 1]; a = U[a][jmp - 1]; } cout << res << n ; } } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2015 12:30:30
// Design Name:
// Module Name: testcase_basic
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "packet_type.vh"
`include "system.vh"
module testcase_basic();
localparam X_LOCAL = 2;
localparam Y_LOCAL = 2;
localparam xpos_packets = 10;
localparam ypos_packets = 10;
localparam xneg_packets = 32;
localparam yneg_packets = 14;
localparam pe_packets = 21;
// --------------------------------------------------------------- >>>>>
//
// Area de modulos
//
// --------------------------------------------------------------- >>>>>
reg xpos = 1'b0;
reg ypos = 1'b0;
reg xneg = 1'b0;
reg yneg = 1'b0;
reg pe = 1'b0;
harness harness();
// -- x+
always
harness.xpos_in_channel.receive_credit();
// -- y+
always
harness.ypos_in_channel.receive_credit();
// -- x-
always
harness.xneg_in_channel.receive_credit();
// -- y-
always
harness.yneg_in_channel.receive_credit();
// -- pe
always
harness.pe_in_channel.receive_credit();
packet_generator
#(
.port(`X_POS),
.pe_percent(8),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
xpos_gen();
initial
begin: xpos_injector
integer index;
@(negedge harness.reset);
for (index = 0; index < xpos_packets; index = index + 1)
begin
xpos_gen.random_packet(index);
harness.xpos_in_channel.send_packet(xpos_gen.packet);
end
xpos = 1'b1;
end
packet_generator
#(
.port(`X_NEG),
.pe_percent(1),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
xneg_gen();
initial
begin: xneg_injector
integer index;
@(negedge harness.reset);
for (index = 0; index < xneg_packets; index = index + 1)
begin
xneg_gen.random_packet(index);
harness.xneg_in_channel.send_packet(xneg_gen.packet);
end
xneg = 1'b1;
end
packet_generator
#(
.port(`Y_POS),
.pe_percent(1),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
ypos_gen();
initial
begin: ypos_injector
integer index;
@(negedge harness.reset);
for (index = 0; index < ypos_packets; index = index + 1)
begin
ypos_gen.random_packet(index);
harness.ypos_in_channel.send_packet(ypos_gen.packet);
end
ypos = 1'b1;
end
packet_generator
#(
.port(`Y_NEG),
.pe_percent(1),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
yneg_gen();
initial
begin: yneg_injector
integer index;
@(negedge harness.reset);
//harness.yneg_in_channel.send_packet({"DAT4", "DAT3", "DAT2", "DAT1", {2'b10, 3'd2, 3'd4, "Y--"}});
for (index = 0; index < yneg_packets; index = index + 1)
begin
yneg_gen.random_packet(index);
harness.yneg_in_channel.send_packet(yneg_gen.packet);
end
yneg = 1'b1;
end
packet_generator
#(
.port(`PE),
.pe_percent(0),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
pe_gen();
initial
begin: pe_injector
integer index;
@(negedge harness.reset);
//harness.yneg_in_channel.send_packet({"DAT4", "DAT3", "DAT2", "DAT1", {2'b10, 3'd2, 3'd4, "Y--"}});
for (index = 0; index < pe_packets; index = index + 1)
begin
pe_gen.random_packet(index);
harness.pe_in_channel.send_packet(pe_gen.packet);
end
pe = 1'b1;
end
initial
begin : ciclo_principal
integer total_envio;
integer total_recepcion;
harness.sync_reset();
//repeat(120)
// @(negedge harness.clk);
@(xpos & ypos & xneg & yneg & pe)
repeat(20)
@(negedge harness.clk);
total_envio = harness.xpos_in_channel.packet_count +
harness.xneg_in_channel.packet_count +
harness.ypos_in_channel.packet_count +
harness.yneg_in_channel.packet_count +
harness.pe_in_channel.packet_count;
total_recepcion = harness.xpos_out_channel.packet_count +
harness.xneg_out_channel.packet_count +
harness.ypos_out_channel.packet_count +
harness.yneg_out_channel.packet_count +
harness.pe_out_channel.packet_count;
$display("",);
$display("",);
$display("",);
$display("|| -- PAQUETES ENVIADOS ---------------- >>>>>",);
$display("",);
$display("Paquetes enviados por x+: ", harness.xpos_in_channel.packet_count);
$display("Paquetes enviados por x-: ", harness.xneg_in_channel.packet_count);
$display("Paquetes enviados por y+: ", harness.ypos_in_channel.packet_count);
$display("Paquetes enviados por y-: ", harness.yneg_in_channel.packet_count);
$display("Paquetes enviados por pe: ", harness.pe_in_channel.packet_count);
$display("",);
$display("Total de paquetes enviados'testcase': ", total_envio);
$display("",);
$display("|| -- PAQUETES RECIBIDOS --------------- >>>>>",);
$display("",);
$display("Paquetes recibidos por x+: ", harness.xpos_out_channel.packet_count);
$display("Paquetes recibidos por x-: ", harness.xneg_out_channel.packet_count);
$display("Paquetes recibidos por y+: ", harness.ypos_out_channel.packet_count);
$display("Paquetes recibidos por y-: ", harness.yneg_out_channel.packet_count);
$display("Paquetes recibidos por pe: ", harness.pe_out_channel.packet_count);
$display("",);
$display("Total de paquetes recibidos'testcase': ", total_recepcion);
$display("",);
$display("|| -- TOTALES -------------------------- >>>>>",);
$display("",);
$display("",);
if(total_envio == total_recepcion)
$display("prueba satisfactoria",);
else
$display("prueba no satisfactoria",);
$display("",);
$display("",);
$display("",);
$finish;
end
endmodule // testcase_basic
|
#include <bits/stdc++.h> using namespace std; struct Node { int sum = 0; Node *L = 0, *R = 0; Node() {} Node(int s, Node* l, Node* r) : sum(s), L(l), R(r) {} }; typedef Node* Ptr; Ptr tree[100100]; Ptr create() { Ptr p = new Node(); p->L = p->R = p; return p; } Ptr add(Ptr root, int fr, int to, int i) { if (fr == to) { return new Node(1, 0, 0); } if (i <= ((fr + to) / 2)) return new Node(1 + root->sum, add(root->L, fr, ((fr + to) / 2), i), root->R); return new Node(1 + root->sum, root->L, add(root->R, ((fr + to) / 2) + 1, to, i)); } void print(Ptr root, int fr, int to) { if (fr == to) return; print(root->L, fr, ((fr + to) / 2)); print(root->R, ((fr + to) / 2) + 1, to); } int getSum(Ptr root, int fr, int to, int a, int b) { if (fr == a && to == b) return root->sum; if (b <= ((fr + to) / 2)) return getSum(root->L, fr, ((fr + to) / 2), a, b); if (a > ((fr + to) / 2)) return getSum(root->R, ((fr + to) / 2) + 1, to, a, b); return getSum(root->L, fr, ((fr + to) / 2), a, ((fr + to) / 2)) + getSum(root->R, ((fr + to) / 2) + 1, to, ((fr + to) / 2) + 1, b); } int getKth(Ptr root, int fr, int to, int k) { if (to - fr + 1 == root->sum) return fr + k - 1; if (root->L->sum >= k) return getKth(root->L, fr, ((fr + to) / 2), k); return getKth(root->R, ((fr + to) / 2) + 1, to, k - root->L->sum); } int n; int getKth(Ptr root, int i, int k) { const int countBefore = i == 1 ? 0 : getSum(root, 1, n, 1, i - 1); k += countBefore; if (root->sum < k) return n + 1; return getKth(root, 1, n, k); } int solve(int k) { int i = 1; int ans = 0; while (i <= n) { const int newI = getKth(tree[i - 1], i, k + 1); i = newI; ans++; } return ans; } int color[100100]; int lastSeen[100100]; int prv[100100]; int ans[100100]; vector<int> prvInv[100100]; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , color + i); prv[i] = lastSeen[color[i]]; prvInv[prv[i]].push_back(i); lastSeen[color[i]] = i; } for (int i = 0; i <= n; ++i) { tree[i] = !i ? create() : tree[i - 1]; for (int j : prvInv[i]) tree[i] = add(tree[i], 1, n, j); } for (int k = 1; k <= n; ++k) ans[k] = solve(k); for (int k = 1; k <= n; ++k) printf( %d%c , ans[k], n [k == n]); return 0; }
|
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Title : PCI Express BFM Request Interface Common Variables
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcietb_bfm_req_intf_common.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This module provides the common variables for passing the requests between the
// Read/Write Request package and ultimately the user's driver and the VC
// Interface Entitites
//-----------------------------------------------------------------------------
// Copyright (c) 2005 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcietb_bfm_req_intf_common(dummy_out) ;
`include "altpcietb_bfm_constants.v"
`include "altpcietb_bfm_log.v"
`include "altpcietb_bfm_req_intf.v"
output dummy_out;
// Contains the performance measurement information
reg [0:EBFM_NUM_VC-1] perf_req;
reg [0:EBFM_NUM_VC-1] perf_ack;
integer perf_tx_pkts[0:EBFM_NUM_VC-1];
integer perf_tx_qwords[0:EBFM_NUM_VC-1];
integer perf_rx_pkts[0:EBFM_NUM_VC-1];
integer perf_rx_qwords[0:EBFM_NUM_VC-1];
integer last_perf_timestamp;
reg [192:0] req_info[0:EBFM_NUM_VC-1] ;
reg req_info_valid[0:EBFM_NUM_VC-1] ;
reg req_info_ack[0:EBFM_NUM_VC-1] ;
reg tag_busy[0:EBFM_NUM_TAG-1] ;
reg [2:0] tag_status[0:EBFM_NUM_TAG-1] ;
reg hnd_busy[0:EBFM_NUM_TAG-1] ;
integer tag_lcl_addr[0:EBFM_NUM_TAG-1] ;
reg reset_in_progress ;
integer bfm_max_payload_size ;
integer bfm_ep_max_rd_req ;
integer bfm_rp_max_rd_req ;
// This variable holds the TC to VC mapping
reg [23:0] tc2vc_map;
integer i ;
initial
begin
for (i = 0; i < EBFM_NUM_VC; i = i + 1 )
begin
req_info[i] = {193{1'b0}} ;
req_info_valid[i] = 1'b0 ;
req_info_ack[i] = 1'b0 ;
perf_req[i] = 1'b0 ;
perf_ack[i] = 1'b0 ;
perf_tx_pkts[i] = 0 ;
perf_tx_qwords[i] = 0 ;
perf_rx_pkts[i] = 0 ;
perf_rx_qwords[i] = 0 ;
last_perf_timestamp[i] = 0 ;
end
for (i = 0; i < EBFM_NUM_TAG; i = i + 1)
begin
tag_busy[i] = 1'b0 ;
tag_status[i] = 3'b000 ;
hnd_busy[i] = 1'b0 ;
tag_lcl_addr[i] = 0 ;
end
reset_in_progress = 1'b0 ;
bfm_max_payload_size = 128 ;
bfm_ep_max_rd_req = 128 ;
bfm_rp_max_rd_req = 128 ;
tc2vc_map = 24'h000000 ;
end
endmodule // altpcietb_bfm_req_intf_common
|
#include <bits/stdc++.h> using namespace std; const long long oo = 1e18; const long long maxn = 2e5, maxm = 1e6, M = 20; struct girl { long long w, id; bool operator<(const girl a) const { return w > a.w; } }; pair<long long, long long> operator+(pair<long long, long long> a, pair<long long, long long> b) { return make_pair(a.first + b.first, a.second + b.second); } vector<girl> gf[maxn]; vector<int> g[maxn]; priority_queue<girl> Q[maxn]; pair<long long, long long> Min[maxm]; long long c[maxn], d[maxn], X[maxn][2], Y[maxn]; long long f[maxn][22]; long long nex[maxn], par[maxn], size[maxn], per[maxn]; long long Z[maxm], pos[maxm]; girl sta[maxn]; long long tot, L, R; long long n, m, q, i, j, x, y, z, la; void partition(long long o, long long fa) { f[o][0] = fa; size[o] = 1; d[o] = d[fa] + 1; long long len = g[o].size(), i; for (i = 0; i < len; i++) { long long v = g[o][i]; if (v == fa) continue; partition(v, o); size[o] += size[v]; if (size[v] > size[nex[o]]) nex[o] = v; } } void dfs(long long o, long long fa) { X[o][0] = ++tot; Y[tot] = o; if (nex[o]) dfs(nex[o], o); long long len = g[o].size(), i; for (i = 0; i < len; i++) { long long v = g[o][i]; if (v == fa || v == nex[o]) continue; dfs(v, o); } X[o][1] = tot; } void getPar(long long o, long long fa) { if (nex[o]) getPar(nex[o], fa); par[o] = fa; } void update(long long o) { if (Min[2 * o] + make_pair(Z[2 * o], 0) < Min[2 * o + 1] + make_pair(Z[2 * o + 1], 0)) { Min[o] = Min[2 * o] + make_pair(Z[2 * o], 0); pos[o] = pos[2 * o]; } else { Min[o] = Min[2 * o + 1] + make_pair(Z[2 * o + 1], 0); pos[o] = pos[2 * o + 1]; } } void pushdown(long long o) { Z[2 * o] += Z[o]; Z[2 * o + 1] += Z[o]; Z[o] = 0; } void build(long long o, long long l, long long r) { if (l + 1 == r) { Q[l].push((girl){oo, 0}); long long len = gf[Y[l]].size(), i; for (i = 0; i < len; i++) Q[l].push(gf[Y[l]][i]); Min[o] = make_pair(Q[l].top().w, Y[l]); pos[o] = l; return; } long long m = (l + r) >> 1; build(2 * o, l, m); build(2 * o + 1, m, r); update(o); } void change(long long o, long long l, long long r, long long x, long long y, long long z) { if (x <= l && r <= y) { Z[o] += z; return; } pushdown(o); long long m = (l + r) >> 1; if (x < m) change(2 * o, l, m, x, y, z); if (m < y) change(2 * o + 1, m, r, x, y, z); update(o); } void find(long long o, long long l, long long r, long long x, long long y, pair<long long, long long> &MIN, long long &POS) { if (x <= l && r <= y) { if (Min[o] + make_pair(Z[o], 0) < MIN) { MIN = Min[o] + make_pair(Z[o], 0); POS = pos[o]; } return; } pushdown(o); long long m = (l + r) >> 1; if (x < m) find(2 * o, l, m, x, y, MIN, POS); if (m < y) find(2 * o + 1, m, r, x, y, MIN, POS); update(o); } void take(long long o, long long l, long long r, long long v, girl &re) { if (l + 1 == r) { re = Q[l].top(); re.w += Z[o]; Q[l].pop(); Min[o] = make_pair(Q[l].top().w, Y[l]); pos[o] = l; return; } pushdown(o); long long m = (l + r) >> 1; if (v < m) take(2 * o, l, m, v, re); else take(2 * o + 1, m, r, v, re); update(o); } void insert(long long o, long long l, long long r, long long v, girl re) { if (l + 1 == r) { re.w -= Z[o]; Q[l].push(re); Min[o] = make_pair(Q[l].top().w, Y[l]); pos[o] = l; return; } pushdown(o); long long m = (l + r) >> 1; if (v < m) insert(2 * o, l, m, v, re); else insert(2 * o + 1, m, r, v, re); update(o); } long long lca(long long x, long long y) { if (d[x] < d[y]) swap(x, y); long long i; for (i = M; i >= 0; i--) if (d[f[x][i]] >= d[y]) x = f[x][i]; if (x == y) return x; for (i = M; i >= 0; i--) if (f[x][i] != f[y][i]) x = f[x][i], y = f[y][i]; return f[x][0]; } girl find(long long u, long long v) { long long a = lca(u, v); pair<long long, long long> MIN = make_pair(oo, 0); long long POS = 0; for (long long i = 1; i <= 2; i++) { while (d[u] >= d[a]) { if (d[par[u]] >= d[a]) { find(1, L, R, X[par[u]][0], X[u][0] + 1, MIN, POS); u = f[par[u]][0]; } else { find(1, L, R, X[a][0], X[u][0] + 1, MIN, POS); u = f[a][0]; } } u = v; } girl re = (girl){oo, 0}; if (MIN == make_pair(oo, 0ll)) return re; take(1, L, R, POS, re); return re; } void solve(long long u, long long v, long long K) { long long i, j; for (i = 1; i <= K; i++) { sta[i] = find(u, v); if (sta[i].id == 0) break; } printf( %lld , i - 1); for (j = 1; j < i; j++) printf( %lld , sta[j].id); printf( n ); } bool cmp(long long a, long long b) { return d[a] < d[b]; } int main() { scanf( %lld%lld%lld , &n, &m, &q); for (i = 1; i < n; i++) { scanf( %lld%lld , &x, &y); g[x].push_back(y); g[y].push_back(x); } for (i = 1; i <= m; i++) { scanf( %lld , &x); c[i] = x; gf[x].push_back((girl){i, i}); } partition(1, 0); dfs(1, 0); for (i = 1; i <= n; i++) per[i] = i; sort(per + 1, per + n + 1, cmp); for (i = 1; i <= n; i++) if (!par[per[i]]) getPar(per[i], per[i]); for (i = 1; i <= M; i++) for (j = 1; j <= n; j++) f[j][i] = f[f[j][i - 1]][i - 1]; L = 1; R = n + 1; build(1, L, R); for (long long qq = 1; qq <= q; qq++) { scanf( %lld , &x); if (x == 1) { scanf( %lld%lld%lld , &x, &y, &z); solve(x, y, z); } else { scanf( %lld%lld , &x, &y); change(1, L, R, X[x][0], X[x][1] + 1, y); } } return 0; }
|
/* S-box using all normal bases */
/* case # 4 : [d^16, d], [alpha^8, alpha^2], [Omega^2, Omega] */
/* beta^8 = N^2*alpha^2, N = w^2 */
/* optimized using OR gates and NAND gates */
/* square in GF(2^2), using normal basis [Omega^2,Omega] */
/* inverse is the same as square in GF(2^2), using any normal basis */
module GF_SQ_2 ( A, Q );
input [1:0] A;
output [1:0] Q;
assign Q = { A[0], A[1] };
endmodule
/* multiply in GF(2^2), shared factors, using normal basis [Omega^2,Omega] */
module GF_MULS_2 ( A, ab, B, cd, Y );
input [1:0] A;
input ab;
input [1:0] B;
input cd;
output [1:0] Y;
wire abcd, p, q;
assign abcd = ~(ab & cd); /* note: ~& syntax for NAND won¡¯t compile */
assign p = (~(A[1] & B[1])) ^ abcd;
assign q = (~(A[0] & B[0])) ^ abcd;
assign Y = { p, q };
endmodule
/* multiply & scale by N in GF(2^2), shared factors, basis [Omega^2,Omega] */
module GF_MULS_SCL_2 ( A, ab, B, cd, Y );
input [1:0] A;
input ab;
input [1:0] B;
input cd;
output [1:0] Y;
wire t, p, q;
assign t = ~(A[0] & B[0]); /* note: ~& syntax for NAND won¡¯t compile */
assign p = (~(ab & cd)) ^ t;
assign q = (~(A[1] & B[1])) ^ t;
assign Y = { p, q };
endmodule
/* inverse in GF(2^4)/GF(2^2), using normal basis [alpha^8, alpha^2] */
module GF_INV_4 ( X, Y );
input [3:0] X;
output [3:0] Y;
wire [1:0] a, b, c, d, p, q;
wire sa, sb, sd; /* for shared factors in multipliers */
assign a = X[3:2];
assign b = X[1:0];
assign sa = a[1] ^ a[0];
assign sb = b[1] ^ b[0];
/* optimize this section as shown below
GF_MULS_2 abmul(a, sa, b, sb, ab);
GF_SQ_2 absq( (a ^ b), ab2);
GF_SCLW2_2 absclN( ab2, ab2N);
GF_SQ_2 dinv( (ab ^ ab2N), d);
*/
assign c = { /* note: ~| syntax for NOR won¡¯t compile */
~(a[1] | b[1]) ^ (~(sa & sb)) ,
~(sa | sb) ^ (~(a[0] & b[0])) };
GF_SQ_2 dinv( c, d);
/* end of optimization */
assign sd = d[1] ^ d[0];
GF_MULS_2 pmul(d, sd, b, sb, p);
GF_MULS_2 qmul(d, sd, a, sa, q);
assign Y = { p, q };
endmodule
/* multiply in GF(2^4)/GF(2^2), shared factors, basis [alpha^8, alpha^2] */
module GF_MULS_4 ( A, a1, Al, Ah, aa, B, b1, Bl, Bh, bb, Q );
input [3:0] A;
input [1:0] a1;
input Al;
input Ah;
input aa;
input [3:0] B;
input [1:0] b1;
input Bl;
input Bh;
input bb;
output [3:0] Q;
wire [1:0] ph, pl, p;
GF_MULS_2 himul(A[3:2], Ah, B[3:2], Bh, ph);
GF_MULS_2 lomul(A[1:0], Al, B[1:0], Bl, pl);
GF_MULS_SCL_2 summul( a1, aa, b1, bb, p);
assign Q = { (ph ^ p), (pl ^ p) };
endmodule
/* inverse in GF(2^8)/GF(2^4), using normal basis [d^16, d] */
module GF_INV_8 ( X, Y );
input [7:0] X;
output [7:0] Y;
wire [3:0] a, b, c, d, p, q;
wire [1:0] sa, sb, sd; /* for shared factors in multipliers */
wire al, ah, aa, bl, bh, bb, dl, dh, dd; /* for shared factors */
wire c1, c2, c3; /* for temp var */
assign a = X[7:4];
assign b = X[3:0];
assign sa = a[3:2] ^ a[1:0];
assign sb = b[3:2] ^ b[1:0];
assign al = a[1] ^ a[0];
assign ah = a[3] ^ a[2];
assign aa = sa[1] ^ sa[0];
assign bl = b[1] ^ b[0];
assign bh = b[3] ^ b[2];
assign bb = sb[1] ^ sb[0];
// optimize this section as shown below
/*GF_MULS_4 abmul(a, sa, al, ah, aa, b, sb, bl, bh, bb, ab);
GF_SQ_SCL_4 absq( (a ^ b), ab2);
GF_INV_4 dinv( (ab ^ ab2), d);*/
assign c1 = ~(ah & bh);
assign c2 = ~(sa[0] & sb[0]);
assign c3 = ~(aa & bb);
assign c = {
(~(sa[0] | sb[0]) ^ (~(a[3] & b[3]))) ^ c1 ^ c3 ,
(~(sa[1] | sb[1]) ^ (~(a[2] & b[2]))) ^ c1 ^ c2 ,
(~(al | bl) ^ (~(a[1] & b[1]))) ^ c2 ^ c3 ,
(~(a[0] | b[0]) ^ (~(al & bl))) ^ (~(sa[1] & sb[1])) ^ c2 };
GF_INV_4 dinv( c, d);
/* end of optimization */
assign sd = d[3:2] ^ d[1:0];
assign dl = d[1] ^ d[0];
assign dh = d[3] ^ d[2];
assign dd = sd[1] ^ sd[0];
GF_MULS_4 pmul(d, sd, dl, dh, dd, b, sb, bl, bh, bb, p);
GF_MULS_4 qmul(d, sd, dl, dh, dd, a, sa, al, ah, aa, q);
assign Y = { p, q };
endmodule
/* find either Sbox or its inverse in GF(2^8), by Canright Algorithm */
module bSbox ( A, Q );
input [7:0] A;
output [7:0] Q;
wire [7:0] B, C;
wire R1, R2, R3, R4, R5, R6, R7, R8, R9;
wire T1, T2, T3, T4, T5, T6, T7, T8, T9;
/* change basis from GF(2^8) to GF(2^8)/GF(2^4)/GF(2^2) */
/* combine with bit inverse matrix multiply of Sbox */
assign R1 = A[7] ^ A[5] ;
assign R2 = A[7] ^ A[4] ;
assign R3 = A[6] ^ A[0] ;
assign R4 = A[5] ^ R3 ;
assign R5 = A[4] ^ R4 ;
assign R6 = A[3] ^ A[0] ;
assign R7 = A[2] ^ R1 ;
assign R8 = A[1] ^ R3 ;
assign R9 = A[3] ^ R8 ;
assign B[7] = R7 ^ R8 ;
assign B[6] = R5 ;
assign B[5] = A[1] ^ R4 ;
assign B[4] = R1 ^ R3 ;
assign B[3] = A[1] ^ R2 ^ R6 ;
assign B[2] = A[0] ;
assign B[1] = R4 ;
assign B[0] = A[2] ^ R9 ;
GF_INV_8 inv( B, C );
/* change basis back from GF(2^8)/GF(2^4)/GF(2^2) to GF(2^8) */
assign T1 = C[7] ^ C[3] ;
assign T2 = C[6] ^ C[4] ;
assign T3 = C[6] ^ C[0] ;
assign T4 = C[5] ^ C[3] ;
assign T5 = C[5] ^ T1 ;
assign T6 = C[5] ^ C[1] ;
assign T7 = C[4] ^ T6 ;
assign T8 = C[2] ^ T4 ;
assign T9 = C[1] ^ T2 ;
assign Q[7] = T4 ;
assign Q[6] = ~T1 ;
assign Q[5] = ~T3 ;
assign Q[4] = T5 ;
assign Q[3] = T2 ^ T5 ;
assign Q[2] = T3 ^ T8 ;
assign Q[1] = ~T7 ;
assign Q[0] = ~T9 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int pri[100003], top, n; bool ntp[100002]; struct node { int a, b; bool operator<(const node &rhs) const { return b > rhs.b; } }; void euler() { for (int i = 2; i <= 100000; ++i) { if (!ntp[i]) pri[top++] = i; for (int j = 0; j < top && pri[j] * i <= 100000; ++j) { ntp[pri[j] * i] = 1; if (i % pri[j] == 0) break; } } } int main() { ios::sync_with_stdio(false); cin.tie(0); euler(); int t; cin >> t; while (t--) { cin >> n; int bn = n; vector<node> v; int sz = 1; for (int i = 0; i < top && n != 1; ++i) { if (n % pri[i] == 0) { node x; x.a = pri[i]; x.b = 0; while (n % pri[i] == 0) ++x.b, n /= pri[i]; sz *= (x.b + 1); v.push_back(x); } } if (n != 1) { node x; x.a = n; x.b = 1; v.push_back(x); } if (v.size() == 0) { cout << NO n ; } else if (v.size() == 1) { if (v[0].b < 6) { cout << NO n ; } else { cout << YES n ; const int &t = v[0].a; cout << t << << t * t << << bn / (t * t * t) << n ; } } else if (v.size() == 2) { if (v[0].b + v[1].b < 4) { cout << NO n ; } else { cout << YES n ; cout << v[0].a << << v[1].a << << bn / v[0].a / v[1].a << n ; } } else { cout << YES n ; cout << v[0].a << << v[1].a << << bn / v[0].a / v[1].a << n ; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_SYMBOL_V
`define SKY130_FD_SC_LS__FILL_DIODE_SYMBOL_V
/**
* fill_diode: Fill diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fill_diode ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:35:40 05/31/2016
// Design Name:
// Module Name: Contador_AD_Dia
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_AD_Dia(
input rst,
input [7:0]estado,
input [1:0] en,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 7;
parameter X = 99;
always @(posedge clk)
if (rst)
Cuenta <= 1;
else if (en == 2'd2 && estado == 8'h7D)
begin
if (Cambio == 8'h73 && got_data)
begin
if (Cuenta == X)
Cuenta <= 1;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h72 && got_data)
begin
if (Cuenta == 1)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
end
else
Cuenta <= Cuenta;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 105; const int oo = 1e9; int g[N][N], n, m; int col[N]; vector<pair<int, int> > ans; pair<int, int> get(int val) { for (int i = 1; i <= m; ++i) { if (g[1][i] < val) return {oo, val}; } memset(col, 0, sizeof(col)); ans.clear(); int ret = val; for (int i = 1; i <= m; ++i) col[i] = g[1][i] - val; ans.push_back({1, val}); for (int i = 2; i <= n; ++i) { int mn = oo, mx = -oo; for (int j = 1; j <= m; ++j) { if (g[i][j] < col[j]) return {oo, val}; mn = min(mn, g[i][j] - col[j]); mx = max(mx, g[i][j] - col[j]); } if (mn != mx) return {oo, val}; ans.push_back({i, mn}); ret += mn; } for (int i = 1; i <= m; ++i) { ans.push_back({-i, col[i]}); ret += col[i]; } return {ret, val}; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { scanf( %d , &g[i][j]); } } pair<int, int> ret = {oo, -1}; for (int i = 0; i <= 500; ++i) ret = min(ret, get(i)); if (ret.first == oo) { printf( -1 n ); return 0; } get(ret.second); printf( %d n , ret.first); for (auto u : ans) { if (u.first < 0) { for (int i = 1; i <= u.second; ++i) printf( col %d n , -u.first); } else { for (int i = 1; i <= u.second; ++i) printf( row %d n , u.first); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int maxN = 1e5 + 10; long long int n, i, a[maxN], mx, cnt, nxt; stack<pair<long long int, long long int> > st; int main() { cin >> n; for (long long int i = 0; i < n; i++) cin >> a[i]; for (long long int i = n - 1; i >= 0; i--) { while (!st.empty()) { if (a[i] < st.top().first) break; cnt++; cnt = max(cnt, st.top().second); st.pop(); } mx = max(mx, cnt); st.push(make_pair(a[i], cnt)); cnt = 0; } cout << mx << endl; }
|
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Single-Ported BRAM with byte enables and ability to load from file
module BRAM1BELoad(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter FILENAME = "";
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
parameter BINARY = 0;
input CLK;
input EN;
input [WE_WIDTH-1:0] WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;
// synopsys translate_off
initial
begin : init_block
`ifdef BSV_NO_INITIAL_BLOCKS
`else
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
end
// synopsys translate_on
initial
begin : init_rom_block
if (BINARY)
$readmemb(FILENAME, RAM, 0, MEMSIZE-1);
else
$readmemh(FILENAME, RAM, 0, MEMSIZE-1);
end
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASK, IMASK;
reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
assign DATAwr = RAM[ADDR] ;
always @(WE or DI or DATAwr) begin : combo1
integer j;
MASK = 0;
IMASK = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASK = (MASK << 8);
end
IMASK = ~MASK;
DATA = (DATAwr & IMASK) | (DI & MASK);
end
always @(posedge CLK) begin
if (EN) begin
if (WE) begin
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
DO_R <= `BSV_ASSIGNMENT_DELAY DATA;
end
else begin
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
end
end
end
`else
generate
genvar i;
for(i = 0; i < WE_WIDTH; i = i + 1) begin: porta_we
always @(posedge CLK) begin
if (EN) begin
if (WE[i]) begin
RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
end
else begin
DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
end
end
end
end
endgenerate
`endif // !`ifdef __ICARUS__
// Output driver
always @(posedge CLK) begin
DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
end
assign DO = (PIPELINED) ? DO_R2 : DO_R;
endmodule // BRAM1BELoad
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module t (/*AUTOARG*/);
`define DRAM1(bank) mem.mem_bank[bank].dccm.dccm_bank.ram_core
`define DRAM2(bank) mem.mem_bank2[bank].dccm.dccm_bank.ram_core
`define DRAM3(bank) mem.mem_bank3[bank].dccm.dccm_bank.ram_core
`define DRAM4(bank) mem.sub4.mem_bank4[bank].dccm.dccm_bank.ram_core
initial begin
`DRAM1(0)[3] = 130;
`DRAM1(1)[3] = 131;
`DRAM2(0)[3] = 230;
`DRAM2(1)[3] = 231;
`DRAM3(0)[3] = 330;
`DRAM3(1)[3] = 331;
`DRAM4(0)[3] = 430;
`DRAM4(1)[3] = 431;
if (`DRAM1(0)[3] !== 130) $stop;
if (`DRAM1(1)[3] !== 131) $stop;
if (`DRAM2(0)[3] !== 230) $stop;
if (`DRAM2(1)[3] !== 231) $stop;
if (`DRAM3(0)[3] !== 330) $stop;
if (`DRAM3(1)[3] !== 331) $stop;
if (`DRAM4(0)[3] !== 430) $stop;
if (`DRAM4(1)[3] !== 431) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
eh2_lsu_dccm_mem mem (/*AUTOINST*/);
endmodule
module eh2_lsu_dccm_mem
#(
DCCM_INDEX_DEPTH = 8192,
DCCM_NUM_BANKS = 2
)(
);
`INLINE_MODULE
// 8 Banks, 16KB each (2048 x 72)
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank
if (DCCM_INDEX_DEPTH == 16384) begin : dccm
eh2_ram
#(.depth(16384), .width(32))
dccm_bank (.*);
end
else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
eh2_ram
#(.depth(8192), .width(32))
dccm_bank (.*);
end
else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
eh2_ram
#(.depth(4096), .width(32))
dccm_bank (.*);
end
end : mem_bank
// Check that generate doesn't also add a genblk
generate
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank2
if (DCCM_INDEX_DEPTH == 8192) begin : dccm
eh2_ram
#(.depth(8192), .width(32))
dccm_bank (.*);
end
end
endgenerate
// Nor this
generate
begin
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank3
if (DCCM_INDEX_DEPTH == 8192) begin : dccm
eh2_ram
#(.depth(8192), .width(32))
dccm_bank (.*);
end
end
end
endgenerate
// This does
generate
begin : sub4
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank4
if (DCCM_INDEX_DEPTH == 8192) begin : dccm
eh2_ram
#(.depth(8192), .width(32))
dccm_bank (.*);
end
end
end
endgenerate
// This is an error (previously declared)
//generate
// begin
// eh2_ram
// #(.depth(8192), .width(32))
// dccm_bank (.*);
// end
// begin
// eh2_ram
// #(.depth(8192), .width(32))
// dccm_bank (.*);
// end
//endgenerate
endmodule
module eh2_ram #(depth=4096, width=39)
();
`INLINE_MODULE
reg [(width-1):0] ram_core [(depth-1):0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; const int INF = 0x3f3f3f3f; const int iinf = 1 << 30; const long long linf = 2e18; const int MOD = 1000000007; void print(int x) { cout << x << endl; exit(0); } void PRINT(string x) { cout << x << endl; exit(0); } void douout(double x) { printf( %lf n , x + 0.0000000001); } char s[N], t[N]; int nxt[N], val[N], f[N], sum[N]; int n, m; signed main() { scanf( %s , s + 1); scanf( %s , t + 1); n = strlen(s + 1); m = strlen(t + 1); nxt[1] = 0; for (int i = 2, j = 0; i <= m; i++) { while (j && t[i] != t[j + 1]) j = nxt[j]; if (t[i] == t[j + 1]) j++; nxt[i] = j; } for (int i = 1, j = 0; i <= n; i++) { while (j && s[i] != t[j + 1]) j = nxt[j]; if (s[i] == t[j + 1]) j++; if (j == m) { val[i] = i - m + 1; j = nxt[j]; } } for (int i = 1; i <= n; i++) if (!val[i]) val[i] = val[i - 1]; for (int i = 1; i <= n; i++) { f[i] = f[i - 1]; if (val[i]) f[i] = (f[i] + sum[val[i] - 1] + val[i]) % MOD; sum[i] = (sum[i] + sum[i - 1] + f[i]) % MOD; } printf( %d n , f[n]); return 0; }
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG.v,v 1.7 2007/05/23 21:43:34 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Input Clock Buffer
// /___/ /\ Filename : IBUFG.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
module IBUFG (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
buf B1 (O, I);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFG instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFG instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
end // initial begin
endmodule
|
//-----------------------------------------------------------------------------
// Title : Block-level Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_5_block.v
// Version : 1.5
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Description: This is the block-level wrapper for the Virtex-6 Embedded
// Tri-Mode Ethernet MAC. It is intended that this example design
// can be quickly adapted and downloaded onto an FPGA to provide
// a hardware test environment.
//
// The block-level wrapper:
//
// * instantiates appropriate PHY interface modules (GMII, MII,
// RGMII, SGMII or 1000BASE-X) as required per the user
// configuration;
//
// * instantiates some clocking and reset resources to operate
// the EMAC and its example design.
//
// Please refer to the Datasheet, Getting Started Guide, and
// the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
// further information.
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Module declaration for the block-level wrapper
//-----------------------------------------------------------------------------
module v6_emac_v1_5_block
(
// TX clock output
TX_CLK_OUT,
// TX clock input from BUFG
TX_CLK,
// Client receiver interface
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client transmitter interface
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC control interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Receive-side PHY clock on regional buffer, to EMAC
PHY_RX_CLK,
// Clock signal
GTX_CLK,
// GMII interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// Asynchronous reset
RESET
);
//-----------------------------------------------------------------------------
// Port declarations
//-----------------------------------------------------------------------------
// TX clock output
output TX_CLK_OUT;
// TX clock input from BUFG
input TX_CLK;
// Client receiver interface
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client transmitter interface
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC control interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Receive-side PHY clock on regional buffer, to EMAC
input PHY_RX_CLK;
// Clock signal
input GTX_CLK;
// GMII interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// Asynchronous reset
input RESET;
//-----------------------------------------------------------------------------
// Wire and register declarations
//-----------------------------------------------------------------------------
// Asynchronous reset signals
wire reset_ibuf_i;
wire reset_i;
// Client clocking signals
wire rx_client_clk_out_i;
wire rx_client_clk_in_i;
wire tx_client_clk_out_i;
wire tx_client_clk_in_i;
wire tx_gmii_mii_clk_out_i;
wire tx_gmii_mii_clk_in_i;
// Physical interface signals
wire gmii_tx_en_i;
wire gmii_tx_er_i;
wire [7:0] gmii_txd_i;
wire gmii_rx_dv_r;
wire gmii_rx_er_r;
wire [7:0] gmii_rxd_r;
wire gmii_rx_clk_i;
// 125MHz reference clock
wire gtx_clk_ibufg_i;
//-----------------------------------------------------------------------------
// Main body of code
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Main reset circuitry
//-------------------------------------------------------------------------
assign reset_ibuf_i = RESET;
assign reset_i = reset_ibuf_i;
//-------------------------------------------------------------------------
// GMII circuitry for the physical interface
//-------------------------------------------------------------------------
gmii_if gmii (
.RESET (reset_i),
.GMII_TXD (GMII_TXD),
.GMII_TX_EN (GMII_TX_EN),
.GMII_TX_ER (GMII_TX_ER),
.GMII_TX_CLK (GMII_TX_CLK),
.GMII_RXD (GMII_RXD),
.GMII_RX_DV (GMII_RX_DV),
.GMII_RX_ER (GMII_RX_ER),
.TXD_FROM_MAC (gmii_txd_i),
.TX_EN_FROM_MAC (gmii_tx_en_i),
.TX_ER_FROM_MAC (gmii_tx_er_i),
.TX_CLK (tx_gmii_mii_clk_in_i),
.RXD_TO_MAC (gmii_rxd_r),
.RX_DV_TO_MAC (gmii_rx_dv_r),
.RX_ER_TO_MAC (gmii_rx_er_r),
.RX_CLK (GMII_RX_CLK)
);
// GTX reference clock
assign gtx_clk_ibufg_i = GTX_CLK;
// GMII PHY-side transmit clock
assign tx_gmii_mii_clk_in_i = TX_CLK;
// GMII PHY-side receive clock, regionally-buffered
assign gmii_rx_clk_i = PHY_RX_CLK;
// GMII client-side transmit clock
assign tx_client_clk_in_i = TX_CLK;
// GMII client-side receive clock
assign rx_client_clk_in_i = gmii_rx_clk_i;
// TX clock output
assign TX_CLK_OUT = tx_gmii_mii_clk_out_i;
//------------------------------------------------------------------------
// Instantiate the primitive-level EMAC wrapper (v6_emac_v1_5.v)
//------------------------------------------------------------------------
v6_emac_v1_5 v6_emac_v1_5_inst
(
// Client receiver interface
.EMACCLIENTRXCLIENTCLKOUT (rx_client_clk_out_i),
.CLIENTEMACRXCLIENTCLKIN (rx_client_clk_in_i),
.EMACCLIENTRXD (EMACCLIENTRXD),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
// Client transmitter interface
.EMACCLIENTTXCLIENTCLKOUT (tx_client_clk_out_i),
.CLIENTEMACTXCLIENTCLKIN (tx_client_clk_in_i),
.CLIENTEMACTXD (CLIENTEMACTXD),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (1'b0),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
// MAC control interface
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
// Clock signals
.GTX_CLK (gtx_clk_ibufg_i),
.EMACPHYTXGMIIMIICLKOUT (tx_gmii_mii_clk_out_i),
.PHYEMACTXGMIIMIICLKIN (tx_gmii_mii_clk_in_i),
// GMII interface
.GMII_TXD (gmii_txd_i),
.GMII_TX_EN (gmii_tx_en_i),
.GMII_TX_ER (gmii_tx_er_i),
.GMII_RXD (gmii_rxd_r),
.GMII_RX_DV (gmii_rx_dv_r),
.GMII_RX_ER (gmii_rx_er_r),
.GMII_RX_CLK (gmii_rx_clk_i),
// MMCM lock indicator
.MMCM_LOCKED (1'b1),
// Asynchronous reset
.RESET (reset_i)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_SYMBOL_V
`define SKY130_FD_SC_HD__AND4BB_SYMBOL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void solve() { string s, s1; cin >> s; int count = 0; sort(s.begin(), s.end()); for (int i = 0; i < s.length(); ++i) { if (s[i] == + ) count++; } std::vector<string> v(s.length()); for (int i = count; i < s.length(); ++i) { v[i] = s[i]; } if (count != 0) for (int i = count; i < v.size() - 1; ++i) { cout << v[i] << + ; } cout << v[v.size() - 1]; } int main() { solve(); }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_3_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_3_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_3_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_3_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:50:03 03/02/2016
// Design Name:
// Module Name: Control_visualizador_numerico
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Control_visualizador_numerico
(
input wire [3:0] cuenta_frec,
input wire [3:0] cuenta_CT,
input wire clock,
input wire reset,
input wire funct_select,
output wire [7:0] code_digitos_decimal, //secuencia para mostrar el digito correcto
output wire [3:0] code_7seg //secuencia para encender el 7 segmentos correcto
);
wire [3:0] OutFSM_InConversorBCD; //Conexion entre la maquina de estados y el conversor BCD a 7 segmentos
FSM Instancia_FSM
(
.clk(clock),
.rst(reset),
.Funct_Select(funct_select),
.Count_CT(cuenta_CT),
.Count_F(cuenta_frec),
.C_Digit(OutFSM_InConversorBCD),
.C_7Seg(code_7seg)
);
Conversor_BCD_7seg Instancia_Conversor_BCD_7seg
(
.Valor_Decimal(OutFSM_InConversorBCD),
.Code_7seg(code_digitos_decimal)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int countdigits(int n) { int i, b = 0; while (n) { b++; n = n / 10; } return b; } int main() { int t, i, n, x, cnt = 0; cin >> t; for (i = 0; i < t; i++) { cin >> n; cnt = countdigits(n); n = n % 10; if (cnt == 1) { x = (n - 1) * 10 + 1; } if (cnt == 2) { x = (n - 1) * 10 + 3; } if (cnt == 3) { x = (n - 1) * 10 + 6; } if (cnt == 4) { x = (n - 1) * 10 + 10; } cout << x << endl; x = 0; } }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: trellis.vh
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The reset_controller module will safely reset a single stage
// pipeline without using an asychronous reset (bleh). It is intended for use in
// the TX engines, where it will control the output stage of the engine, and
// provide a gracefull end-of-packet reset
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`define S_RC_IDLE 3'b001
`define S_RC_WAIT 3'b010
`define S_RC_ACTIVE 3'b100
`include "trellis.vh"
module reset_controller
#(parameter C_RST_COUNT = 10)
(
input CLK,
input RST_IN,
output DONE_RST,
output WAITING_RESET,
output RST_OUT,
input SIGNAL_RST,
input WAIT_RST,
input NEXT_CYC_RST);
`include "functions.vh"
localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
reg [2:0] _rState,rState;
wire [C_CLOG2_RST_COUNT:0] wRstCount;
assign DONE_RST = rState[0];
assign WAITING_RESET = rState[1] & NEXT_CYC_RST;
assign RST_OUT = rState[2];
counter
#(// Parameters
.C_MAX_VALUE (C_CEIL2_RST_COUNT),
.C_SAT_VALUE (C_CEIL2_RST_COUNT),
.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
/*AUTOINSTPARAM*/)
rst_counter
(// Outputs
.VALUE (wRstCount),
// Inputs
.ENABLE (1'b1),
.RST_IN (~rState[2] | RST_IN),
/*AUTOINST*/
// Inputs
.CLK (CLK));
always @(posedge CLK) begin
if(RST_IN) begin
rState <= `S_RC_ACTIVE;
end else begin
rState <= _rState;
end
end
always @(*) begin
_rState = rState;
case(rState)
`S_RC_IDLE:begin
if(SIGNAL_RST & WAIT_RST) begin
_rState = `S_RC_WAIT;
end else if(SIGNAL_RST) begin
_rState = `S_RC_ACTIVE;
end
end
`S_RC_WAIT:begin
if(NEXT_CYC_RST) begin
_rState = `S_RC_ACTIVE;
end
end
`S_RC_ACTIVE:begin
if(wRstCount[C_CLOG2_RST_COUNT] & ~SIGNAL_RST) begin
_rState = `S_RC_IDLE;
end
end
default: _rState = rState;
endcase
end
endmodule
|
// Murabito-B 21/04/13 #include <bits/stdc++.h> using namespace std; using ll = long long; void solve() { int a, b, c; cin >> a >> b >> c; for (int i = 0; i <= a - c; ++i) cout << 1; for (int i = 1; i < c; ++i) cout << 0; cout << 1 ; for (int i = 1; i < b; ++i) cout << 0; cout << n ; } int main() { ios_base::sync_with_stdio(false), cin.tie(0); int _; for (cin >> _; _--;) solve(); return 0; }
|
/* This file is part of jt51.
jt51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
jt51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with jt51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 7th 2017
*/
`timescale 1ns / 1ps
module jt51_fir4
#(parameter data_width=9, output_width=12)
(
input clk,
input rst,
input sample,
input signed [data_width-1:0] left_in,
input signed [data_width-1:0] right_in,
output signed [output_width-1:0] left_out,
output signed [output_width-1:0] right_out,
output sample_out
);
parameter coeff_width=9;
parameter stages=21;
parameter addr_width=5;
parameter acc_extra=1;
reg signed [coeff_width-1:0] coeff;
wire [addr_width-1:0] cnt;
jt51_fir #(
.data_width (data_width),
.output_width(output_width),
.coeff_width (coeff_width),
.stages (stages),
.addr_width (addr_width),
.acc_extra (acc_extra)
) i_jt51_fir (
.clk (clk ),
.rst (rst ),
.sample (sample ),
.left_in (left_in ),
.right_in (right_in ),
.left_out (left_out ),
.right_out (right_out ),
.sample_out(sample_out),
.cnt (cnt ),
.coeff (coeff )
);
always @(*)
case( cnt )
5'd0: coeff = 9'd18;
5'd1: coeff = 9'd24;
5'd2: coeff = 9'd40;
5'd3: coeff = 9'd66;
5'd4: coeff = 9'd99;
5'd5: coeff = 9'd134;
5'd6: coeff = 9'd171;
5'd7: coeff = 9'd205;
5'd8: coeff = 9'd231;
5'd9: coeff = 9'd249;
5'd10: coeff = 9'd255;
default: coeff = 9'd0;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxx = 500 + 7; const int maxn = 100 + 7; const long long mod = 1E9 + 7; const int maxs = 2 * (1E7) + 5; const int maxm = 100 + 3; const long long maxk = 1e13; long double dp[maxn][maxn]; int last[1000]; char seq[maxn]; long long n, k; void init() { cin >> n >> k; cin >> seq; memset(last, -1, sizeof(last)); } void solve() { dp[0][0] = 1; for (int i = 1; i <= n; i++) { for (int j = 0; j <= i; j++) { if (!j) { dp[i][j] = 1; continue; } dp[i][j] = dp[i - 1][j] + dp[i - 1][j - 1]; if (last[seq[i - 1]] != -1) dp[i][j] -= dp[last[seq[i - 1]]][j - 1]; } last[seq[i - 1]] = i - 1; } long long cost = 0; long double kk = k; for (long long i = n; i >= 0; i--) { long double tt = min(kk, dp[n][i]); cost += tt * (n - i); kk -= min(tt, kk); } if (kk > 0) cout << -1 << endl; else cout << (long long)cost << endl; } int main(void) { init(); solve(); return 0; }
|
`timescale 1 ns/100 ps
//------------------------------------------------------------------------------
// Copyright (c) 2012 Kirk Weedman, KD7IRS,
//------------------------------------------------------------------------------
// NOTE: 1. Input angle is a modulo of 2*PI scaled to fit in a 32bit register. The user must translate
// this angle to a value from 0 - (2^32-1). 0 deg = 32'h0, ... = 32'hFF_FF_FF_FF
// To translate from degrees to a 32 bit value, multiply 2^32 by the angle (in degrees),
// then divide by 360
// 2. Size of Xout, Yout is 1 bit larger due to a system gain of 1.647 (which is < 2)
module CORDIC (clock, angle, Xin, Yin, Xout, Yout);
parameter XY_SZ = 16; // width of input and output data
localparam STG = XY_SZ; // same as bit width of X and Y
input clock;
// angle is a signed value in the range of -PI to +PI that must be represented as a 32 bit signed number
input signed [31:0] angle;
input signed [XY_SZ-1:0] Xin;
input signed [XY_SZ-1:0] Yin;
output signed [XY_SZ:0] Xout;
output signed [XY_SZ:0] Yout;
//------------------------------------------------------------------------------
// arctan table
//------------------------------------------------------------------------------
// Note: The atan_table was chosen to be 31 bits wide giving resolution up to atan(2^-30)
wire signed [31:0] atan_table [0:30];
// upper 2 bits = 2'b00 which represents 0 - PI/2 range
// upper 2 bits = 2'b01 which represents PI/2 to PI range
// upper 2 bits = 2'b10 which represents PI to 3*PI/2 range (i.e. -PI/2 to -PI)
// upper 2 bits = 2'b11 which represents 3*PI/2 to 2*PI range (i.e. 0 to -PI/2)
// The upper 2 bits therefore tell us which quadrant we are in.
assign atan_table[00] = 32'b00100000000000000000000000000000; // 45.000 degrees -> atan(2^0)
assign atan_table[01] = 32'b00010010111001000000010100011101; // 26.565 degrees -> atan(2^-1)
assign atan_table[02] = 32'b00001001111110110011100001011011; // 14.036 degrees -> atan(2^-2)
assign atan_table[03] = 32'b00000101000100010001000111010100; // atan(2^-3)
assign atan_table[04] = 32'b00000010100010110000110101000011;
assign atan_table[05] = 32'b00000001010001011101011111100001;
assign atan_table[06] = 32'b00000000101000101111011000011110;
assign atan_table[07] = 32'b00000000010100010111110001010101;
assign atan_table[08] = 32'b00000000001010001011111001010011;
assign atan_table[09] = 32'b00000000000101000101111100101110;
assign atan_table[10] = 32'b00000000000010100010111110011000;
assign atan_table[11] = 32'b00000000000001010001011111001100;
assign atan_table[12] = 32'b00000000000000101000101111100110;
assign atan_table[13] = 32'b00000000000000010100010111110011;
assign atan_table[14] = 32'b00000000000000001010001011111001;
assign atan_table[15] = 32'b00000000000000000101000101111101;
assign atan_table[16] = 32'b00000000000000000010100010111110;
assign atan_table[17] = 32'b00000000000000000001010001011111;
assign atan_table[18] = 32'b00000000000000000000101000101111;
assign atan_table[19] = 32'b00000000000000000000010100011000;
assign atan_table[20] = 32'b00000000000000000000001010001100;
assign atan_table[21] = 32'b00000000000000000000000101000110;
assign atan_table[22] = 32'b00000000000000000000000010100011;
assign atan_table[23] = 32'b00000000000000000000000001010001;
assign atan_table[24] = 32'b00000000000000000000000000101000;
assign atan_table[25] = 32'b00000000000000000000000000010100;
assign atan_table[26] = 32'b00000000000000000000000000001010;
assign atan_table[27] = 32'b00000000000000000000000000000101;
assign atan_table[28] = 32'b00000000000000000000000000000010;
assign atan_table[29] = 32'b00000000000000000000000000000001; // atan(2^-29)
assign atan_table[30] = 32'b00000000000000000000000000000000;
//------------------------------------------------------------------------------
// registers
//------------------------------------------------------------------------------
//stage outputs
reg signed [XY_SZ:0] X [0:STG-1];
reg signed [XY_SZ:0] Y [0:STG-1];
reg signed [31:0] Z [0:STG-1]; // 32bit
//------------------------------------------------------------------------------
// stage 0
//------------------------------------------------------------------------------
wire [1:0] quadrant;
assign quadrant = angle[31:30];
always @(posedge clock)
begin // make sure the rotation angle is in the -pi/2 to pi/2 range. If not then pre-rotate
case (quadrant)
2'b00,
2'b11: // no pre-rotation needed for these quadrants
begin // X[n], Y[n] is 1 bit larger than Xin, Yin, but Verilog handles the assignments properly
X[0] <= Xin;
Y[0] <= Yin;
Z[0] <= angle;
end
2'b01:
begin
X[0] <= -Yin;
Y[0] <= Xin;
Z[0] <= {2'b00,angle[29:0]}; // subtract pi/2 from angle for this quadrant
end
2'b10:
begin
X[0] <= Yin;
Y[0] <= -Xin;
Z[0] <= {2'b11,angle[29:0]}; // add pi/2 to angle for this quadrant
end
endcase
end
//------------------------------------------------------------------------------
// generate stages 1 to STG-1
//------------------------------------------------------------------------------
genvar i;
generate
for (i=0; i < (STG-1); i=i+1)
begin: XYZ
wire Z_sign;
wire signed [XY_SZ:0] X_shr, Y_shr;
assign X_shr = X[i] >>> i; // signed shift right
assign Y_shr = Y[i] >>> i;
//the sign of the current rotation angle
assign Z_sign = Z[i][31]; // Z_sign = 1 if Z[i] < 0
always @(posedge clock)
begin
// add/subtract shifted data
X[i+1] <= Z_sign ? X[i] + Y_shr : X[i] - Y_shr;
Y[i+1] <= Z_sign ? Y[i] - X_shr : Y[i] + X_shr;
Z[i+1] <= Z_sign ? Z[i] + atan_table[i] : Z[i] - atan_table[i];
end
end
endgenerate
//------------------------------------------------------------------------------
// output
//------------------------------------------------------------------------------
assign Xout = X[STG-1];
assign Yout = Y[STG-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; using point = complex<double>; const int T = 1 << 16; point root[T]; void fft(vector<point>& a) { int n = a.size(); vector<int> reverse(n); for (int i = 0; i < n; ++i) { reverse[i] = (reverse[i / 2] + (i % 2) * n) / 2; if (i < reverse[i]) { swap(a[i], a[reverse[i]]); } } for (int i = 1; i < n; i *= 2) { for (int j = 0; j < n; j += 2 * i) { for (int k = 0; k < i; ++k) { point l = a[j + k]; point r = a[i + j + k] * root[i + k]; a[j + k] = l + r; a[i + j + k] = l - r; } } } } vector<point> mul(vector<point> a, vector<point> b) { int n = 1, m = a.size() + b.size(); while (n < m) { n *= 2; } a.resize(n), b.resize(n); fft(a), fft(b); for (int i = 0; i < n; ++i) { a[i] *= b[i]; } fft(a); for (auto& i : a) { i /= n; } reverse(a.begin() + 1, a.end()); a.resize(m - 1); return a; } const int M = 100; const int N = 50; double prob[M][T], expect[M][T], ans[N][T]; array<int, 3> edges[M]; long long dist[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout << fixed << setprecision(6); for (int i = 1; i < T; i *= 2) { for (int j = 0; j < i; ++j) { root[i + j] = polar(1.0, j * M_PI / i); } } int n, m, t, x; cin >> n >> m >> t >> x; for (int i = 0; i < m; ++i) { int u, v, w; cin >> u >> v >> w; edges[i] = {u - 1, v - 1, w}; for (int j = 1; j <= t; ++j) { int p; cin >> p; prob[i][j] = p / 100000.0; } } fill(dist, dist + n - 1, LLONG_MAX); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { auto [u, v, w] = edges[j]; if (dist[v] < LLONG_MAX) { dist[u] = min(dist[u], dist[v] + w); } } } for (int i = 0; i < n - 1; ++i) { fill(ans[i], ans[i] + t + 1, HUGE_VAL); } for (int i = 0; i < m; ++i) { auto [u, v, w] = edges[i]; double sum = 0.0; for (int j = t; j >= 0; --j) { expect[i][j] = w + sum * (dist[v] + x); sum += prob[i][j]; } ans[u][0] = min(ans[u][0], expect[i][0]); } for (int i = 1; i <= t; ++i) { for (int j = 0; j < m; ++j) { auto [u, v, w] = edges[j]; for (int k = 1; i % k == 0; k *= 2) { vector<point> poly = mul(vector<point>(ans[v] + i - k, ans[v] + i), vector<point>(prob[j] + k, prob[j] + min(2 * k, t + 1))); for (int l = 0; l <= t - i && l <= (int)poly.size(); ++l) { expect[j][l + i] += poly[l].real(); } } ans[u][i] = min(ans[u][i], expect[j][i]); } } cout << ans[0][t] << n ; }
|
// handle receives over UART
module uart_rx
(
input wire clk,
input wire reset,
input wire rx,
input wire s_tick,
output reg rx_done_tick,
output wire [7:0] dout
);
parameter DBIT = 8;
parameter SB_TICK = 16;
localparam IDLE = 0;
localparam START = 1;
localparam DATA = 2;
localparam STOP = 3;
reg [1:0] state_reg, state_next;
reg [3:0] s_reg, s_next;
reg [3:0] n_reg, n_next;
reg [7:0] b_reg, b_next;
always @ (posedge clk, posedge reset) begin
if (reset) begin
state_reg <= IDLE;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
end
else begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end
end
// state machine works as follows:
// if it is in idle mode, it waits for a start based on a signal
// to begin. once it has some data, it will
// loop through the data sending bit by bit until it is done, then it goes back to idle mode
always @ (state_reg, s_reg, n_reg, b_reg, s_tick, rx) begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
rx_done_tick <= 0;
case (state_reg)
IDLE: begin
if (!rx) begin
state_next <= START;
s_next <= 0;
end
end
START: begin
if (s_tick) begin
if (s_reg == 7) begin
state_next <= DATA;
s_next <= 0;
n_next <= 0;
end
else
s_next <= s_reg + 1;
end
end
DATA: begin
if (s_tick) begin
if (s_reg == 15) begin
s_next <= 0;
b_next <= {rx, b_reg[7:1]};
if (n_reg == DBIT-1)
state_next <= STOP;
else
n_next <= n_reg + 1;
end
else
s_next <= s_reg + 1;
end
end
STOP: begin
if (s_tick) begin
if (s_reg == SB_TICK-1) begin
state_next <= IDLE;
rx_done_tick <= 1;
end
else
s_next <= s_reg + 1;
end
end
endcase
end
assign dout = b_reg;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A32OI_FUNCTIONAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 nand0_out ;
wire B1 nand1_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long int n, k; string str[400007]; long long int a[400007], p[400007][4]; long long int m1[200005], m2[200005]; int main() { string s; cin >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == A ) { p[i][0] = 1; if (i - 1 >= 0) p[i - 1][0] = 1; if (i + 1 < s.length()) p[i + 1][0] = 1; } if (s[i] == B ) { p[i][1] = 1; if (i - 1 >= 0) p[i - 1][1] = 1; if (i + 1 < s.length()) p[i + 1][1] = 1; } if (s[i] == C ) { p[i][2] = 1; if (i - 1 >= 0) p[i - 1][2] = 1; if (i + 1 < s.length()) p[i + 1][2] = 1; } } for (int i = 0; i < s.length(); i++) { if (p[i][0] == 1 && p[i][1] == 1 && p[i][2] == 1) { cout << Yes ; return 0; } } cout << No ; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg gendlyclk_r;
reg [31:0] gendlydata_r;
reg [31:0] dlydata_gr;
reg genblkclk;
reg [31:0] genblkdata;
reg [31:0] blkdata_gr;
wire [31:0] constwire = 32'h11;
reg [31:0] initwire;
integer i;
initial begin
for (i=0; i<10000; i=i+1) begin
initwire = 32'h2200;
end
end
wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
always @ (posedge clk) begin
gendlydata_r <= 32'h0011_0000;
gendlyclk_r <= 0;
// surefire lint_off SEQASS
genblkclk = 0;
genblkdata = 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
gendlyclk_r <= 1;
gendlydata_r <= 32'h00540000;
genblkclk = 1;
genblkdata = 32'hace;
$write("[%0t] Send pulse\n", $time);
end
if (cyc==3) begin
genblkdata = 32'hdce;
gendlydata_r <= 32'h00ff0000;
if (either != 32'h87542211) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// surefire lint_on SEQASS
end
always @ (posedge gendlyclk_r) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
dlydata_gr <= 32'h80000000;
// Delayed activity list will already be completed for gendlydata
// because genclk is from a delayed assignment.
// Thus we get the NEW not old value of gendlydata_r
if (gendlydata_r != 32'h00540000) $stop;
if (genblkdata != 32'hace) $stop;
end
end
always @ (posedge genblkclk) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
blkdata_gr <= 32'h07000000;
// Clock from non-delayed assignment, we get old value of gendlydata_r
`ifdef verilator `else // V3.2 races... technically legal
if (gendlydata_r != 32'h00110000) $stop;
`endif
if (genblkdata != 32'hace) $stop;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long a[n]; for (int i = 0; i < n; i++) cin >> a[i]; long long mx = 1e9 + 9, r = 0; for (int i = n - 1; i >= 0; i--) { a[i] = min(mx, a[i]); r += a[i]; mx = min(mx, max(0ll, a[i] - 1)); } cout << r << n ; return 0; }
|
module cast_large_real;
reg [63:0] u64;
reg signed [63:0] i64;
reg [64:0] u65;
reg signed [64:0] i65;
real r;
reg fail;
initial begin
fail = 0;
u64 = {1'b1, 63'd0};
r = u64;
$display("Convert u64 to real");
$display("Expect : %0f", 2.0**63);
$display("Got : %0f", r);
if (r != 2.0**63) fail = 1;
u64 = r;
$display("Convert real to u64");
$display("Expect : %0d", {1'b1, 63'd0});
$display("Got : %0d", u64);
if (u64 != {1'b1, 63'd0}) fail = 1;
i64 = {1'b1, 63'd0};
r = i64;
$display("Convert i64 to real");
$display("Expect : %0f", -(2.0**63));
$display("Got : %0f", r);
if (r != -(2.0**63)) fail = 1;
i64 = r;
$display("Convert real to i64");
$display("Expect : %0d", $signed({1'b1, 63'd0}));
$display("Got : %0d", i64);
if (i64 != {1'b1, 63'd0}) fail = 1;
u65 = {1'b1, 64'd0};
r = u65;
$display("Convert u65 to real");
$display("Expect : %0f", 2.0**64);
$display("Got : %0f", r);
if (r != 2.0**64) fail = 1;
u65 = r;
$display("Convert real to u65");
$display("Expect : %0d", {1'b1, 64'd0});
$display("Got : %0d", u65);
if (u65 != {1'b1, 64'd0}) fail = 1;
i65 = {1'b1, 64'd0};
r = i65;
$display("Convert i65 to real");
$display("Expect : %0f", -(2.0**64));
$display("Got : %0f", r);
if (r != -(2.0**64)) fail = 1;
i65 = r;
$display("Convert real to i65");
$display("Expect : %0d", $signed({1'b1, 64'd0}));
$display("Got : %0d", i65);
if (i65 != {1'b1, 64'd0}) fail = 1;
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } const int maxx = 10005; const int INF = 0x3f3f3f3f; int n, m, k; int vis[maxx]; int ans = 0, cnt = 0, pos = 0; int l = 0, r = 0; string a, b; string s1, s2; int main() { scanf( %d%d , &n, &m); cin >> a >> b; if (n > m + 1) { printf( NO n ); return 0; } int fk = 0; int tag = 0; for (int i = 0; i < n; i++) { if (a[i] == * ) { tag = 1; continue; } if (tag == 0) s1.push_back(a[i]); else s2.push_back(a[i]); } if (tag) { fk = 0; for (int i = 0; i < ((int)(s1).size()); i++) { if (b[i] != s1[i]) fk = 1; } for (int i = ((int)(s2).size()) - 1; i >= 0; i--) { if (b[m - ((int)(s2).size()) + i] != s2[i]) { fk = 1; } } } else { if (n != m) fk = 1; else { for (int i = 0; i < n; i++) { if (a[i] != b[i]) { fk = 1; break; } } } } if (a == * ) fk = 0; if (fk) printf( NO n ); else printf( YES n ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD1_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLYGATE4SD1_BEHAVIORAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd1 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD1_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, tf = 0, f = 0, hun = 0; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 25) tf++; else if (a[i] == 50) { f++; tf--; } else { hun++; if (f >= 1) { f--; tf--; } else tf = tf - 3; } if (tf < 0) { cout << NO ; break; } } if (tf >= 0) cout << YES ; return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_hostif #(
parameter csr_addr = 4'h0,
parameter pmem_width = 12
) (
input sys_clk,
input sys_rst,
input usb_clk,
output reg usb_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output irq,
input io_we,
input [5:0] io_a,
input [pmem_width-1:0] dbg_pc
);
wire csr_selected = csr_a[13:10] == csr_addr;
reg usb_rst0;
always @(posedge sys_clk) begin
if(sys_rst) begin
usb_rst0 <= 1'b1;
csr_do <= 1'b0;
end else begin
csr_do <= 1'b0;
if(csr_selected) begin
if(csr_we)
usb_rst0 <= csr_di[0];
csr_do <= { dbg_pc, 1'b0 };
end
end
end
/* Synchronize USB Reset to the USB clock domain */
reg usb_rst1;
always @(posedge usb_clk) begin
usb_rst1 <= usb_rst0;
usb_rst <= usb_rst1;
end
/* Generate IRQs */
reg irq_flip;
always @(posedge usb_clk) begin
if(usb_rst)
irq_flip <= 1'b0;
else if(io_we && (io_a == 6'h15))
irq_flip <= ~irq_flip;
end
reg irq_flip0;
reg irq_flip1;
reg irq_flip2;
always @(posedge sys_clk) begin
irq_flip0 <= irq_flip;
irq_flip1 <= irq_flip0;
irq_flip2 <= irq_flip1;
end
assign irq = irq_flip1 != irq_flip2;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__A21OI_PP_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_PP_BLACKBOX_V
|
// Icarus 0.7, cvs files from Feb 2, 2003
// --------------------------------------
//
// iverilog precision.v
// or
// iverilog -D DUMP precision.v
// vvp a.out
//
// Use & display of real time periods with `timescale set to 1 ns / 10 ps
//
// $simtime keeps time in 10ps increments
// $simtime cannot be displayed (yet)
// $simtime can be used in comparisons -- compared to times in 10 ps units
// $time should be $simtime-rounded-to-ns
// $time displays according to `timescale and $timeformat
// $time can be used in comparisons -- compared to times in 1 ns units
//
// Assuming that the simulation runs on units of 10ps, a clock which is set to
// change value every (15.2 ns)/2 should change every 7.6 ns, i.e. 760*10ps.
//
// The dumpfile shows a timescale of 10ps; therefore, it should show the clock
// changing every 760*10ps. It doesn't. The clock is changing every 700*10ps.
// The checks on the clock using $simtime below verify that the dumpfile is
// seeing what the simulation is, in fact, doing.
//
`timescale 1 ns / 10 ps
`define PERIODI 15
`define PERIODR 15.2
module top;
reg tick,clk, fail;
reg [31:0] ii;
`ifdef DUMP
initial begin
$dumpvars;
end
`endif
initial begin
$timeformat(-9, 2, "ns", 20);
$display("integer & real periods: 'd%0d 'd%0d",`PERIODI,`PERIODR);
$display("integer & real periods (15.00, 15.20): 't%0t 't%0t",`PERIODI,`PERIODR);
$display("......... %s should be displayed as 15.20 in its timeformat.", ``PERIODR);
$display("integer & real periods: 'b%0b 'b%0b",`PERIODI,`PERIODR);
$display("integer & real periods: 'h%0h 'h%0h",`PERIODI,`PERIODR);
clk = 0;
tick = 0;
fail = 0;
#1;
if($time === 1) $display("\t$time is in ns");
if($time === 100) $display("\t$time is in 10 ps");
$display("\ttime (1, 1h): 'd%0d, 't%0t, 'h%0h",$time,$time,$time);
if($simtime === 1) $display("\t$simtime is in ns");
if($simtime === 100) $display("\t$simtime is in 10 ps");
$display("\tsimtime (100, 64h): 'd%0d, 't%0t, 'h%0h",$simtime,$simtime,$simtime);
#(`PERIODI - 1);
tick = 1;
if($time !== 15) begin fail = 1;$display("time (15, Fh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end
if($simtime !== 1500) begin fail=1; $display("simtime not 1500"); end
#(`PERIODR);
tick = 0;
if($time !== 30) begin fail = 1; $display("time (30, 1Eh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end
if($simtime !== 3020) begin fail=1; $display("simtime not 3020"); end
#(`PERIODR);
tick = 1;
if($time !== 45) begin fail = 1; $display("time (45, 2Dh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end
if($simtime !== 4540) begin fail=1; $display("simtime not 4540"); end
#(`PERIODR);
tick = 0;
if($time !== 61) begin fail = 1; $display("time (61, 3Dh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end
if($simtime !== 6060) begin fail=1; $display("simtime not 6060"); end
#(`PERIODR);
tick = 1;
if($time !== 76) begin fail = 1; $display("time (76, 4Ch): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end
if($simtime !== 7580) begin fail=1; $display("simtime not 7580"); end
#(`PERIODR);
tick = 1;
if($time !== 91) begin fail = 1; $display("time (91, 5Bh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end
if($simtime !== 9100) begin fail=1; $display("simtime not 9100"); end
$display("\t\t**********************************************");
if(fail) $display("\t\t****** time precision test FAILED *******");
else $display("\t\t****** time precision test PASSED *******");
$display("\t\t**********************************************\n");
$finish(0);
end
initial begin
for(ii = 0; ii < 1524; ii = ii + 1) begin
#(0.01);
if(($simtime == 659) && (clk !== 0)) begin fail=1; $display("time: 659, clk wrong"); end
if(($simtime == 701) && (clk !== 0)) begin fail=1; $display("time: 701, clk wrong"); end
if(($simtime == 759) && (clk !== 0)) begin fail=1; $display("time: 759, clk wrong"); end
if(($simtime == 761) && (clk !== 1)) begin fail=1; $display("time: 761, clk wrong"); end
if(($simtime == 1399) && (clk !== 1)) begin fail=1; $display("time: 1399, clk wrong"); end
if(($simtime == 1401) && (clk !== 1)) begin fail=1; $display("time: 1401, clk wrong"); end
if(($simtime == 1519) && (clk !== 1)) begin fail=1; $display("time: 1519, clk wrong"); end
if(($simtime == 1521) && (clk !== 0)) begin fail=1; $display("time: 1521, clk wrong"); end
end
end
always begin
#(`PERIODR/2) clk <= ~clk;
// clock should change as follows:
// T (10ps) : clk
// 0 : 0
// 760 : 1
// 1520 : 0
// 2280 : 1
// 3040 : 0
// etc.
end
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Packets to Bytes Component
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_packets_to_bytes
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0)
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST in with packets
output reg in_ready,
input in_valid,
input [7: 0] in_data,
input [CHANNEL_WIDTH-1: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
reg sent_esc, sent_sop, sent_eop;
reg sent_channel_char, channel_escaped, sent_channel;
reg [CHANNEL_WIDTH:0] stored_channel;
reg [4:0] channel_count;
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
reg channel_needs_esc;
wire need_sop, need_eop, need_esc, need_channel;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign need_esc = (in_data === 8'h7a |
in_data === 8'h7b |
in_data === 8'h7c |
in_data === 8'h7d );
assign need_eop = (in_endofpacket);
assign need_sop = (in_startofpacket);
generate
if( CHANNEL_WIDTH > 0) begin
wire channel_changed;
assign channel_changed = (in_channel != stored_channel);
assign need_channel = (need_sop | channel_changed);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
out_data <= 0;
out_valid <= 0;
channel_count <= 0;
channel_needs_esc <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin
sent_channel_char <= 1;
out_data <= 8'h7c;
channel_count <= CHN_COUNT[4:0];
stored_varchannel <= in_channel;
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
channel_needs_esc <= (in_channel == 8'h7a |
in_channel == 8'h7b |
in_channel == 8'h7c |
in_channel == 8'h7d );
end
end else if (channel_needs_esc & ~channel_escaped) begin
out_data <= 8'h7d;
channel_escaped <= 1;
end else if (~sent_channel) begin
if (ENCODING) begin
// Sending out MSB=1, while not last 7 bits of Channel
if (channel_count > 0) begin
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
stored_varchannel <= stored_varchannel<<7;
channel_count <= channel_count - 1'b1;
// check whether the last 7 bits need escape or not
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
channel_needs_esc <=
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
end
end else begin
// Sending out MSB=0, last 7 bits of Channel
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
sent_channel <= 1;
end
end else begin
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= in_channel ^ 8'h20;
end else out_data <= in_channel;
sent_channel <= 1;
end
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
end
end
end
end
//channel related signals
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
//extra bit in stored_channel to force reset
stored_channel <= {CHANNEL_WIDTH{1'b1}};
end else begin
//update stored_channel only when it is sent out
if (sent_channel) stored_channel <= in_channel;
end
end
always @* begin
// in_ready. Low when:
// back pressured, or when
// we are outputting a control character, which means that one of
// {escape_char, start of packet, end of packet, channel}
// needs to be, but has not yet, been handled.
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end else begin
assign need_channel = (need_sop);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
out_data <= 0;
out_valid <= 0;
sent_channel <= 0;
sent_channel_char <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
sent_channel_char <= 1;
out_data <= 8'h7c;
end else if (~sent_channel) begin
out_data <= 'h0;
sent_channel <= 1;
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
end
end
end
end
always @* begin
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_TB_V
`define SKY130_FD_SC_LP__BUFLP_TB_V
/**
* buflp: Buffer, Low Power.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buflp.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__buflp dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_TB_V
|
#include <bits/stdc++.h> using namespace std; int treas[310][310]; long long dp[310][310]; long long d[310][310]; vector<pair<int, int> > G[110000]; vector<pair<long long, pair<int, int> > > lst; queue<pair<long long, pair<int, int> > > bfs; int dir[4][2] = {{-1, 0}, {1, 0}, {0, 1}, {0, -1}}; long long n, m; long long Dist(int x1, int y1, int x2, int y2) { return abs(x1 - x2) + abs(y1 - y2); } int main() { ios_base::sync_with_stdio(0); int p, fx, fy; cin >> n >> m >> p; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> treas[i][j]; G[treas[i][j]].push_back({i, j}); if (treas[i][j] == p) fx = i, fy = j; if (treas[i][j] == 1) dp[i][j] = i + j; } for (int i = 2; i <= p; i++) { long long cur_size = G[i].size(); long long prev_size = G[i - 1].size(); if (cur_size * prev_size <= n * m) { for (int j = 0; j < cur_size; j++) { int cur_x = G[i][j].first; int cur_y = G[i][j].second; dp[cur_x][cur_y] = 1e9; for (int k = 0; k < prev_size; k++) { int prev_x = G[i - 1][k].first; int prev_y = G[i - 1][k].second; dp[cur_x][cur_y] = min(dp[cur_x][cur_y], dp[prev_x][prev_y] + Dist(cur_x, cur_y, prev_x, prev_y)); } } } else { lst.clear(); for (int j = 0; j < n; j++) for (int k = 0; k < n; k++) d[j][k] = -1; for (int j = 0; j < prev_size; j++) { int prev_x = G[i - 1][j].first; int prev_y = G[i - 1][j].second; lst.push_back({dp[prev_x][prev_y], {prev_x, prev_y}}); } sort(lst.begin(), lst.end()); int ptr = 1; bfs.push(lst[0]); d[lst[0].second.first][lst[0].second.second] = lst[0].first; while (!bfs.empty()) { int x = bfs.front().second.first; int y = bfs.front().second.second; long long val = bfs.front().first; bfs.pop(); while (ptr < lst.size() && lst[ptr].first <= val) bfs.push(lst[ptr++]); int X, Y; for (int k = 0; k < 4; k++) { X = x + dir[k][0]; Y = y + dir[k][1]; if (X >= 0 && X <= n && Y >= 0 && Y < m && d[X][Y] == -1) { d[X][Y] = val + 1; bfs.push({val + 1, {X, Y}}); } } } for (int j = 0; j < cur_size; j++) { int x = G[i][j].first; int y = G[i][j].second; dp[x][y] = d[x][y]; } } } cout << dp[fx][fy] << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O221A_FUNCTIONAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PR_TB_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PR_TB_V
/**
* udp_dff$PR: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_dff_pr.v"
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__udp_dff$PR dut (.D(D), .RESET(RESET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PR_TB_V
|
#include <bits/stdc++.h> using namespace std; vector<long long> v; bool vis[10005]; long long n, m, k; int main() { cin >> n >> m >> k; if ((n * m * 2) % k != 0) puts( NO ); else { puts( YES ); puts( 0 0 ); if ((n * 2) % k == 0) { printf( %lld 0 n , n * 2 / k); printf( %lld %lld n , n / 2, m); } else if ((m * 2) % k == 0) { printf( %lld 0 n , n); printf( %lld %lld n , n / 2, m * 2 / k); } else { for (int i = 2; i * i <= k; i++) { if (k % i == 0) { while (k % i == 0) { v.push_back(i); k /= i; } } } if (k != 1) v.push_back(k); long long len = v.size(), N = n, M = m; for (int i = 0; i < len; i++) { if (N % v[i] == 0) { N /= v[i]; vis[i] = 1; } } for (int i = 0; i < len; i++) { if (vis[i]) continue; if (M % v[i] == 0) { M /= v[i]; vis[i] = 1; } } long long cnt = 2; for (int i = 0; i < len; i++) { if (!vis[i]) cnt = 1; } if (N < n) { printf( %lld 0 n , N * cnt); printf( %lld %lld n , N, M); } else { printf( %lld 0 n , N); printf( %lld %lld n , N, M * cnt); } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_SYMBOL_V
`define SKY130_FD_SC_HDLL__O211A_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_SYMBOL_V
|
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the given
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the time is 0
//-- Once enabled, the pulse is generated just in the middle of the period
//-- This is necessary for the implementation of the receptor
//--------------------------------------------------------------------------------
//-- (c) BQ. December 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "baudgen.vh"
//----------------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle. Output not registered
//-- It tells the uart_rx when to sample the next bit
//-- __ __
//-- ____________________| |________________________________________| |_____________________
//-- | -> <- 1 clock cycle |
//-- <------- Period ------------------------->
//--
//---------------------------------------------------------------------------------------
module baudgen_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire rstn, //-- Reset (active low)
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
localparam N = $clog2(BAUDRATE);
//-- Value for generating the pulse in the middle of the period
localparam M2 = (N >> 1);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
if (!rstn)
divcounter <= 0;
else if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is in the middle of the period, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == M2) ? clk_ena : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mx = 5005; int type[mx], dp[mx]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { double x; cin >> type[i] >> x; } for (int i = 1; i <= n; i++) { int j = type[i]; for (int k = j; k >= 1; k--) dp[j] = max(dp[j], 1 + dp[k]); } int ret = 0; for (int i = 1; i <= n; i++) ret = max(ret, dp[i]); cout << n - ret << endl; return 0; }
|
module CY7C67200_IF( // HOST Side
iDATA,
oDATA,
iADDR, //for HPI register selection
iRD_N,
iWR_N,
iCS_N,
iRST_N,
iCLK,
oINT,
// CY7C67200 Side
// OTG_ID, //HPI mode selection(host or peripheral)
HPI_DATA,
HPI_ADDR,
HPI_RD_N,
HPI_WR_N,
HPI_CS_N,
HPI_RST_N,
HPI_INT
// I2C_SCL, //I2C interface
// I2C_SDA
);
//=====================================
// PORT Declaration
//=====================================
// HOST Side
input [31:0] iDATA; //input data from nios
input [1:0] iADDR; //address for sel for HPI interface
input iRD_N; //read enable
input iWR_N; //write enable
input iCS_N; //chip sel
input iRST_N; //reset
input iCLK; //clk
output [31:0] oDATA; //read data from EZO
output oINT; //
// ISP1362 Side
//output OTG_ID;
inout [15:0] HPI_DATA;
output [1:0] HPI_ADDR;
output HPI_RD_N;
output HPI_WR_N;
output HPI_CS_N;
output HPI_RST_N;
input HPI_INT;
//output I2C_SCL;
//inout I2C_SDA;
//=====================================
// reg/wire Declaration
//=====================================
reg [1:0] HPI_ADDR;
reg HPI_RD_N;
reg HPI_WR_N;
reg HPI_CS_N;
reg [15:0] TMP_DATA;
reg [31:0] oDATA;
reg oINT;
assign HPI_DATA = HPI_WR_N ? 16'hzzzz : TMP_DATA ;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
TMP_DATA <= 0;
HPI_ADDR <= 0;
HPI_RD_N <= 1;
HPI_WR_N <= 1;
HPI_CS_N <= 1;
TMP_DATA <= 0;
oDATA <= 0;
oINT <= 0;
end
else
begin
oDATA <= {16'h0000,HPI_DATA};
oINT <= HPI_INT;
TMP_DATA <= iDATA[15:0];
HPI_ADDR <= iADDR[1:0];
HPI_RD_N <= iRD_N;
HPI_WR_N <= iWR_N;
HPI_CS_N <= iCS_N;
end
end
assign HPI_RST_N = iRST_N;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int t[n + 1]; for (int i = 0; i < n; i++) { cin >> t[i]; } for (int i = 0; i < n; i++) { int tt = t[i]; for (int j = 1; j <= tt; j++) cout << j << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; long long c[N << 2], a[N]; void pushup(int rt) { c[rt] = c[rt << 1] | c[rt << 1 | 1]; } void build(int rt, int l, int r) { if (l == r) { scanf( %I64d , c + rt); a[l] = c[rt]; return; } int mid = (l + r) >> 1; build(rt << 1, l, mid); build(rt << 1 | 1, mid + 1, r); pushup(rt); } long long query(int rt, int l, int r, int x, int y) { if (x > y) return 0; if (x <= l && r <= y) { return c[rt]; } int mid = (l + r) >> 1; long long ret = 0; if (x <= mid) ret |= query(rt << 1, l, mid, x, y); if (mid < y) ret |= query(rt << 1 | 1, mid + 1, r, x, y); return ret; } int main() { int n, k, c; while (~scanf( %d%d%d , &n, &c, &k)) { long long tmp = 1; for (int i = 1; i <= c; i++) { tmp *= k; } build(1, 1, n); long long ans = (tmp * a[1]) | query(1, 1, n, 2, n); ans = max(ans, (tmp * a[n]) | query(1, 1, n, 1, n - 1)); for (int i = 2; i < n; i++) { ans = max(ans, query(1, 1, n, 1, i - 1) | (tmp * a[i]) | query(1, 1, n, i + 1, n)); } printf( %I64d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBN_1_V
`define SKY130_FD_SC_HD__DFBBN_1_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfbbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBN_1_V
|
#include <bits/stdc++.h> using namespace std; const int mxn = 300001; int n; long long a[mxn], dp[mxn]; map<int, int> first[mxn]; void answer() { cin >> n; long long ret = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; first[i].clear(); if (first[i - 1].count(a[i])) { int x = first[i - 1][a[i]]; ret += (dp[i] = (x ? dp[x - 1] : 0) + 1); swap(first[i], first[x - 1]); first[i][a[x - 1]] = x - 1; } else { dp[i] = 0; } first[i][a[i]] = i; } cout << ret << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; for (int i = 0; i < t; i++) answer(); return 0; }
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top level module of qspi_1cs
//
// ====================================================================
module sirv_qspi_1cs_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_tl_i_0_0
);
wire io_tl_r_0_a_ready;
assign i_icb_cmd_ready = io_tl_r_0_a_ready;
wire io_tl_r_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_r_0_a_bits_param = 3'b0;
wire [2:0] io_tl_r_0_a_bits_size = 3'd2;
wire [4:0] io_tl_r_0_a_bits_source = 5'b0;
wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata;
wire io_tl_r_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_tl_r_0_d_bits_opcode;
wire [1:0] io_tl_r_0_d_bits_param;
wire [2:0] io_tl_r_0_d_bits_size;
wire [4:0] io_tl_r_0_d_bits_source;
wire io_tl_r_0_d_bits_sink;
wire [1:0] io_tl_r_0_d_bits_addr_lo;
wire [31:0] io_tl_r_0_d_bits_data;
wire io_tl_r_0_d_bits_error;
wire io_tl_r_0_d_valid;
assign i_icb_rsp_valid = io_tl_r_0_d_valid;
assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data;
// Not used
wire io_tl_r_0_b_ready = 1'b0;
wire io_tl_r_0_b_valid;
wire [2:0] io_tl_r_0_b_bits_opcode;
wire [1:0] io_tl_r_0_b_bits_param;
wire [2:0] io_tl_r_0_b_bits_size;
wire [4:0] io_tl_r_0_b_bits_source;
wire [28:0] io_tl_r_0_b_bits_address;
wire [3:0] io_tl_r_0_b_bits_mask;
wire [31:0] io_tl_r_0_b_bits_data;
// Not used
wire io_tl_r_0_c_ready;
wire io_tl_r_0_c_valid = 1'b0;
wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_r_0_c_bits_param = 3'b0;
wire [2:0] io_tl_r_0_c_bits_size = 3'd2;
wire [4:0] io_tl_r_0_c_bits_source = 5'b0;
wire [28:0] io_tl_r_0_c_bits_address = 29'b0;
wire [31:0] io_tl_r_0_c_bits_data = 32'b0;
wire io_tl_r_0_c_bits_error = 1'b0;
// Not used
wire io_tl_r_0_e_ready;
wire io_tl_r_0_e_valid = 1'b0;
wire io_tl_r_0_e_bits_sink = 1'b0;
sirv_qspi_1cs u_sirv_qspi_1cs(
.clock (clk ),
.reset (~rst_n ),
.io_tl_r_0_a_ready (io_tl_r_0_a_ready ),
.io_tl_r_0_a_valid (io_tl_r_0_a_valid ),
.io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ),
.io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ),
.io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ),
.io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ),
.io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ),
.io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ),
.io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ),
.io_tl_r_0_b_ready (io_tl_r_0_b_ready ),
.io_tl_r_0_b_valid (io_tl_r_0_b_valid ),
.io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ),
.io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ),
.io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ),
.io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ),
.io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ),
.io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ),
.io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ),
.io_tl_r_0_c_ready (io_tl_r_0_c_ready ),
.io_tl_r_0_c_valid (io_tl_r_0_c_valid ),
.io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ),
.io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ),
.io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ),
.io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ),
.io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ),
.io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ),
.io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ),
.io_tl_r_0_d_ready (io_tl_r_0_d_ready ),
.io_tl_r_0_d_valid (io_tl_r_0_d_valid ),
.io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ),
.io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ),
.io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ),
.io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ),
.io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ),
.io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ),
.io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ),
.io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ),
.io_tl_r_0_e_ready (io_tl_r_0_e_ready ),
.io_tl_r_0_e_valid (io_tl_r_0_e_valid ),
.io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ),
.io_port_sck (io_port_sck ),
.io_port_dq_0_i (io_port_dq_0_i ),
.io_port_dq_0_o (io_port_dq_0_o ),
.io_port_dq_0_oe (io_port_dq_0_oe),
.io_port_dq_1_i (io_port_dq_1_i ),
.io_port_dq_1_o (io_port_dq_1_o ),
.io_port_dq_1_oe (io_port_dq_1_oe),
.io_port_dq_2_i (io_port_dq_2_i ),
.io_port_dq_2_o (io_port_dq_2_o ),
.io_port_dq_2_oe (io_port_dq_2_oe),
.io_port_dq_3_i (io_port_dq_3_i ),
.io_port_dq_3_o (io_port_dq_3_o ),
.io_port_dq_3_oe (io_port_dq_3_oe),
.io_port_cs_0 (io_port_cs_0 ),
.io_tl_i_0_0 (io_tl_i_0_0 )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void scanv(vector<T>& v, int n) { v.resize(n); for (int i = 0; i < n; i++) cin >> v[i]; } template <typename T> void scanvv(vector<vector<T> >& v, int n, int m) { v.resize(n); for (int i = 0; i < n; i++) scanv(v[i], m); } vector<int> p, s; int main() { ios_base::sync_with_stdio(false); int cs, n, i, j; cin >> cs; while (cs--) { cin >> n; scanv(p, n); s.clear(); s.emplace_back(p[0]); for (i = 1; i < n; i++) { if (p[i] < p[i - 1]) { j = i + 1; while (j < n && p[j] < p[j - 1]) j++; s.emplace_back(p[j - 1]); i = j - 1; } else { j = i + 1; while (j < n && p[j] > p[j - 1]) j++; s.emplace_back(p[j - 1]); i = j - 1; } } cout << s.size() << n ; for (i = 0; i < s.size(); i++) { if (i) cout << ; cout << s[i]; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long num[200000]; pair<long long, long long> p[200000]; int main() { long long n, m, k, sum = 0, cnt = 1; cin >> n >> m >> k; for (int i = 1; i <= n; i++) { cin >> p[i].first; p[i].second = i; } sort(p + 1, p + n + 1); for (int i = n; i > n - m * k; i--) { sum += p[i].first; num[cnt++] = p[i].second; } cout << sum << n ; sort(num + 1, num + m * k + 1); for (int i = m; i < m * k; i += m) cout << num[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a, b, c, d, k, t; int main() { cin >> t; while (t--) { cin >> a >> b >> c >> d >> k; bool isok = 0; for (int i = 1; i <= k; i++) { if (i * c >= a && (k - i) * d >= b) { isok = 1; cout << i << << k - i << endl; break; } } if (!isok) cout << -1 << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__AND4_FUNCTIONAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4_FUNCTIONAL_PP_V
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_crosspoint_4x4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg [7:0] input_1_axis_tdata = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg [7:0] input_2_axis_tdata = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg [7:0] input_3_axis_tdata = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg [1:0] output_0_select = 0;
reg [1:0] output_1_select = 0;
reg [1:0] output_2_select = 0;
reg [1:0] output_3_select = 0;
// Outputs
wire [7:0] output_0_axis_tdata;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire [7:0] output_1_axis_tdata;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire [7:0] output_2_axis_tdata;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire [7:0] output_3_axis_tdata;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
output_0_select,
output_1_select,
output_2_select,
output_3_select);
$to_myhdl(output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast);
// dump file
$dumpfile("test_axis_crosspoint_4x4.lxt");
$dumpvars(0, test_axis_crosspoint_4x4);
end
axis_crosspoint_4x4 #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tlast(input_0_axis_tlast),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tlast(input_1_axis_tlast),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tlast(input_2_axis_tlast),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tlast(input_3_axis_tlast),
// AXI outputs
.output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tlast(output_0_axis_tlast),
.output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tlast(output_1_axis_tlast),
.output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tlast(output_2_axis_tlast),
.output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tlast(output_3_axis_tlast),
// Control
.output_0_select(output_0_select),
.output_1_select(output_1_select),
.output_2_select(output_2_select),
.output_3_select(output_3_select)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction TLB ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of ITLB. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_immu_tlb.v,v $
// Revision 1.9 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6 2002/10/28 16:34:32 mohor
// RAMs wrong connected to the BIST scan chain.
//
// Revision 1.5 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.4 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
//
// Insn TLB
//
module or1200_immu_tlb(
// Rst and clk
clk, rst,
// I/F for translation
tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// I/F for translation
//
input tlb_en;
input [aw-1:0] vaddr;
output hit;
output [31:`OR1200_IMMU_PS] ppn;
output uxe;
output sxe;
output ci;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [`OR1200_ITLB_TAG] vpn;
wire v;
wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
wire tlb_mr_en;
wire tlb_mr_we;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
wire tlb_tr_en;
wire tlb_tr_we;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
// BIST
`ifdef OR1200_BIST
wire itlb_mr_ram_si;
wire itlb_mr_ram_so;
wire itlb_tr_ram_si;
wire itlb_tr_ram_so;
`endif
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-19 v 0
// itlbwYtrX: ppn 31-13 uxe 7 sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Output to SPRS unit
//
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
32'h00000000;
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
//
// Assign outputs from Translate registers
//
assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
//
// Instantiation of ITLB Match Registers
//
or1200_spram_64x14 itlb_mr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_mr_ram_si),
.mbist_so_o(itlb_mr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
);
//
// Instantiation of ITLB Translate Registers
//
or1200_spram_64x22 itlb_tr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_tr_ram_si),
.mbist_so_o(itlb_tr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e15; const int N = 2e5 + 10; int I[N], st[N], fn[N], par[N], h[N], sz[N], big[N], hd[N], n, m, q, timer; long long w[N]; vector<int> g[N], V[N]; struct Node { pair<long long, long long> Mn; long long Lazy = 0; } seg[N << 2]; void apply(int id, long long val) { seg[id].Mn.first += val; seg[id].Lazy += val; } void shift(int id) { if (seg[id].Lazy == 0) return; apply(id << 1, seg[id].Lazy); apply(id << 1 | 1, seg[id].Lazy); seg[id].Lazy = 0; } void add(int l, int r, long long val, int L = 0, int R = n + m, int id = 1) { if (r <= L || R <= l) return; if (l <= L && R <= r) { apply(id, val); return; } shift(id); add(l, r, val, L, (L + R) >> 1, id << 1); add(l, r, val, (L + R) >> 1, R, id << 1 | 1); seg[id].Mn = min(seg[id << 1].Mn, seg[id << 1 | 1].Mn); } pair<long long, long long> get(int l, int r, int L = 0, int R = n + m, int id = 1) { if (r <= L || R <= l) return {inf, inf}; if (l <= L && R <= r) return seg[id].Mn; shift(id); return min(get(l, r, L, (L + R) >> 1, id << 1), get(l, r, (L + R) >> 1, R, id << 1 | 1)); } void Build(int L = 0, int R = n + m, int id = 1) { if (R - L == 1) { seg[id].Mn = {w[I[L]], I[L]}; return; } Build(L, (L + R) >> 1, id << 1); Build((L + R) >> 1, R, id << 1 | 1); seg[id].Mn = min(seg[id << 1].Mn, seg[id << 1 | 1].Mn); return; } int dfs_size(int v) { for (int u : g[v]) if (u != par[v]) { par[u] = v, h[u] = h[v] + 1; sz[v] += dfs_size(u); if (sz[u] > sz[big[v]]) big[v] = u; } return ++sz[v]; } void dfs_hld(int v) { for (int i : V[v]) I[timer] = i, st[i] = timer++; if (big[v]) hd[big[v]] = hd[v], dfs_hld(big[v]); for (int u : g[v]) if (u != par[v] & u != big[v]) hd[u] = u, dfs_hld(u); for (int i : V[v]) fn[i] = timer; } pair<long long, long long> getmin(int u, int v) { pair<long long, long long> res = {inf, inf}; while (hd[u] != hd[v]) { if (h[hd[v]] > h[hd[u]]) swap(u, v); res = min(res, get(st[hd[u]], st[u] + (int)V[u].size())); u = par[hd[u]]; } if (h[v] < h[u]) swap(u, v); res = min(res, get(st[u], st[v] + (int)V[v].size())); return res; } void query(int u, int v, int k) { vector<int> ans; while (k--) { pair<long long, long long> p = getmin(u, v); if (p.first >= inf) break; ans.push_back(p.second); add(st[p.second], st[p.second] + 1, inf); } cout << ans.size() << ; for (int i : ans) cout << i - n << ; cout << n ; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m >> q; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } for (int i = 1; i <= n + m; i++) { if (i <= n) { V[i].push_back(i), w[i] = inf; continue; } int c; cin >> c; V[c].push_back(i), w[i] = i - n; } dfs_size(1), hd[1] = 1, dfs_hld(1), Build(); while (q--) { int t; cin >> t; if (t == 1) { int u, v, k; cin >> u >> v >> k; query(u, v, k); } if (t == 2) { int v, k; cin >> v >> k; add(st[v], fn[v], k); } } return 0; }
|
#include <bits/stdc++.h> template <typename T> void MACRO_VAR_Scan(T& t) { std::cin >> t; } template <typename First, typename... Rest> void MACRO_VAR_Scan(First& first, Rest&... rest) { std::cin >> first; MACRO_VAR_Scan(rest...); } template <typename T> void MACRO_VEC_ROW_Init(int n, T& t) { t.resize(n); } template <typename First, typename... Rest> void MACRO_VEC_ROW_Init(int n, First& first, Rest&... rest) { first.resize(n); MACRO_VEC_ROW_Init(n, rest...); } template <typename T> void MACRO_VEC_ROW_Scan(int p, T& t) { std::cin >> t[p]; } template <typename First, typename... Rest> void MACRO_VEC_ROW_Scan(int p, First& first, Rest&... rest) { std::cin >> first[p]; MACRO_VEC_ROW_Scan(p, rest...); } template <typename T> inline T CHMAX(T& a, const T b) { return a = (a < b) ? b : a; } template <typename T> inline T CHMIN(T& a, const T b) { return a = (a > b) ? b : a; } void CHECKTIME(std::function<void()> f) { auto start = std::chrono::system_clock::now(); f(); auto end = std::chrono::system_clock::now(); auto res = std::chrono::duration_cast<std::chrono::nanoseconds>((end - start)) .count(); std::cerr << [Time: << res << ns ( << res / (1.0e9) << s)] n ; } template <class T> std::vector<std::vector<T>> VV(int n, int m, T init = T()) { return std::vector<std::vector<T>>(n, std::vector<T>(m, init)); } template <typename S, typename T> std::ostream& operator<<(std::ostream& os, std::pair<S, T> p) { os << ( << p.first << , << p.second << ) ; return os; } using ll = long long; using ull = unsigned long long; using ld = long double; using PAIR = std::pair<ll, ll>; using PAIRLL = std::pair<ll, ll>; constexpr ll INFINT = 1 << 30; constexpr ll INFINT_LIM = (1LL << 31) - 1; constexpr ll INFLL = 1LL << 60; constexpr ll INFLL_LIM = (1LL << 62) - 1 + (1LL << 62); constexpr double EPS = 1e-9; constexpr ll MOD = 1000000007; constexpr double PI = 3.141592653589793238462643383279; template <class T, size_t N> void FILL(T (&a)[N], const T& val) { for (auto& x : a) x = val; } template <class ARY, size_t N, size_t M, class T> void FILL(ARY (&a)[N][M], const T& val) { for (auto& b : a) FILL(b, val); } template <class T> void FILL(std::vector<T>& a, const T& val) { for (auto& x : a) x = val; } template <class ARY, class T> void FILL(std::vector<std::vector<ARY>>& a, const T& val) { for (auto& b : a) FILL(b, val); } namespace FFT { const double pi = std::acos(-1); std::vector<std::complex<double>> tmp; size_t sz = 1; std::vector<std::complex<double>> fft(std::vector<std::complex<double>> a, bool inv = false) { size_t mask = sz - 1; size_t p = 0; for (size_t i = sz >> 1; i >= 1; i >>= 1) { auto& cur = (p & 1) ? tmp : a; auto& nex = (p & 1) ? a : tmp; std::complex<double> e = std::polar(1., 2 * pi * i * (inv ? -1 : 1) / sz); std::complex<double> w = 1; for (size_t j = 0; j < sz; j += i) { for (size_t k = 0; k < i; ++k) { nex[j + k] = cur[((j << 1) & mask) + k] + w * cur[(((j << 1) + i) & mask) + k]; } w *= e; } ++p; } if (p & 1) std::swap(a, tmp); if (inv) for (size_t i = 0; i < sz; ++i) a[i] /= sz; return a; } std::vector<ll> mul(std::vector<ll> a, std::vector<ll> b) { size_t m = a.size() + b.size() - 1; sz = 1; while (m > sz) sz <<= 1; tmp.resize(sz); std::vector<std::complex<double>> A(sz), B(sz); for (size_t i = 0; i < a.size(); ++i) A[i].real(a[i]); for (size_t i = 0; i < b.size(); ++i) B[i].real(b[i]); A = fft(A); B = fft(B); for (size_t i = 0; i < sz; ++i) A[i] *= B[i]; A = fft(A, true); a.resize(m); for (size_t i = 0; i < m; ++i) a[i] = std::round(A[i].real()); return a; } }; // namespace FFT signed main() { std::ios::sync_with_stdio(false); std::cin.tie(0); ; ll n, x; MACRO_VAR_Scan(n, x); ; std::vector<ll> a(n); for (auto& i : a) std::cin >> i; ; for (ll i = 0; i < ll(n); ++i) a[i] = a[i] < x; std::vector<ll> b; { ll cnt = 0; for (ll i = 0; i < ll(n + 1); ++i) { if (i == n || a[i]) { b.emplace_back(cnt); cnt = 0; } else { ++cnt; } } } ll m = b.size(); { ll ans = 0; for (ll i = 0; i < ll(m); ++i) { ans += (ll)b[i] * (b[i] + 1) / 2; } std::cout << (ans); ; } { for (ll i = 0; i < ll(m); ++i) ++b[i]; auto bb(b); std::reverse((bb).begin(), (bb).end()); auto c = FFT::mul(b, bb); std::vector<ll> ans(n, 0); ll p = 0; for (ll i = ll(m - 1) - 1; i >= 0; --i) { ans[p++] = c[i]; } for (ll i = 0; i < ll(n); ++i) { std::cout << ; std::cout << (ans[i]); ; } std::cout << n ; ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR3_PP_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, nxt[100010], pre[100010]; pair<int, int> b[100010]; struct Frog { int p, a, id; } a[100010]; set<pair<int, int> > s; inline bool operator<(Frog a, Frog b) { return a.p < b.p; } inline int cal(int i, int j) { if (i == j) return 0x7fffffff; int p1 = a[i].p, p2 = a[j].p; if (i > j) (p2 += a[j].a) %= m; int d = (p2 - p1 + m) % m, step = (a[i].a - a[j].a); if (d <= a[i].a) return 1; if (a[j].a >= a[i].a) return 0x7fffffff; return (d - a[j].a + step - 1) / step; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %d%d , &a[i].p, &a[i].a), a[i].p--, b[i] = make_pair(a[i].p, i); sort(b, b + n); for (int i = 0; i < n; i++) { nxt[b[i].second] = b[(i + 1) % n].second; pre[b[(i + 1) % n].second] = b[i].second; } for (int i = 0; i < n; i++) s.insert(make_pair(cal(i, nxt[i]), i)); while (!s.empty()) { set<pair<int, int> >::iterator it = s.begin(); int i = it->second; if (it->first == 0x7fffffff) break; s.erase(it); s.erase(make_pair(cal(nxt[i], nxt[nxt[i]]), nxt[i])); s.erase(make_pair(cal(pre[i], i), pre[i])); a[i].p += cal(i, nxt[i]); a[i].a--; nxt[i] = nxt[nxt[i]]; pre[nxt[i]] = i; s.insert(make_pair(cal(pre[i], i), pre[i])); s.insert(make_pair(cal(i, nxt[i]), i)); } printf( %d n , s.size()); for (set<pair<int, int> >::iterator it = s.begin(); it != s.end(); it++) printf( %d , it->second + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; ostream &operator<<(ostream &out, vector<long long> &a) { for (auto i : a) out << i << ; return out; } istream &operator>>(istream &in, vector<long long> &a) { for (auto &i : a) in >> i; return in; } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); long long q; cin >> q; while (q--) { string a, b, c; cin >> a >> b >> c; bool boo = 0; for (long long i = 0; i < a.size(); ++i) { if (c[i] != b[i] && c[i] != a[i]) { cout << NO << n ; boo = 1; break; } } if (!boo) cout << YES << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_2_V
`define SKY130_FD_SC_LS__FAH_2_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fah_2 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fah_2 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_2_V
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Extraction to Ocaml : use of basic Ocaml types *)
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
|
#include <bits/stdc++.h> const long long mod = 1000000007; long long qpow(long long v, long long st) { long long r = 1; while (st) { if (st & 1) { r *= v; r %= mod; } v = v * v; v %= mod; st = st / 2; } return r; } long long f[1024]; long long dp[1024][1024]; long long sdp[1024][1024]; long long getDP(int, int); long long getSdp(int b1, int b2) { if (sdp[b1][b2] != -1) return sdp[b1][b2]; if (b2 == 0) return getDP(b1 - 2, 0); sdp[b1][b2] = getSdp(b1, b2 - 1) + getDP(b1 - 2, b2) * qpow(f[b2], mod - 2); sdp[b1][b2] %= mod; return sdp[b1][b2]; } long long getDP(int b1, int b2) { if (dp[b1][b2] != -1) return dp[b1][b2]; if (!b1) return f[b2]; long long sol = 0; if (b1 >= 2) { long long p = getSdp(b1, b2); p *= f[b2]; p %= mod; p *= (b1 - 1); p %= mod; sol += p; sol %= mod; } if (b2 > 0) { sol += getDP(b1, b2 - 1) * b2; sol %= mod; } sol += getDP(b1 - 1, b2); if (sol >= mod) sol %= mod; dp[b1][b2] = sol; return dp[b1][b2]; } int main() { int i, j, k; f[0] = 1; for (i = 1; i <= 1000; i++) { f[i] = f[i - 1] * i; f[i] %= mod; } j = k = 0; int n, l; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &l); if (l == 1) j++; else k++; } memset(dp, -1, sizeof(dp)); memset(sdp, -1, sizeof(sdp)); printf( %d n , (int)getDP(j, k)); return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<pair<long long, long long>, long long> merge_p( pair<long long, long long> a, pair<long long, long long> b) { if (a.first > b.first) swap(a, b); if (b.first <= a.second) { if (b.second <= a.second) return make_pair(b, 0); else return make_pair(make_pair(b.first, a.second), 0); } else { return make_pair(make_pair(a.second, b.first), b.first - a.second); } } void solve() { int n, x; cin >> n >> x; pair<long long, long long> opt = make_pair(x, x); long long ans = 0; pair<long long, long long> tmp; for (int i = 0; i < n; ++i) { cin >> tmp.first >> tmp.second; pair<pair<long long, long long>, long long> f = merge_p(opt, tmp); opt = f.first; ans += f.second; } cout << ans << endl; } int main() { time_t t1 = clock(); solve(); time_t t2 = clock(); }
|
#include <bits/stdc++.h> using namespace std; long long a[1000009]; int pre[10000009]; vector<long long> alr; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); reverse(a, a + n); long long ans = 0, ans1 = 0; int taken = 0; for (int i = 0; i < n; i++) { pre[a[i]]++; } for (int i = 0; i < n; i++) { if (pre[a[i]] % 2 == 1) { if (pre[a[i] - 1] > 0) pre[a[i]]--, pre[a[i] - 1]++; else pre[a[i]]--; } } int x = 0, y = 0, l = 0, r = 2; while (l < n && r < n) { if (pre[a[l]] >= 2 && pre[a[r]] >= 2) { if (a[l] == a[r] && pre[a[r]] < 4) { r++; continue; } pre[a[l]] -= 2; pre[a[r]] -= 2; ans += a[l] * a[r]; } else if (pre[a[r]] < 2 && pre[a[l]] >= 2) r++; else if (pre[a[r]] >= 2 && pre[a[l]] < 2) l++; else if (pre[a[r]] < 2 && pre[a[l]] < 2) l++, r++; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 205; const int mod = 1e9 + 7; long long f[2][N][N]; int n, tot; struct point { long long x, y; point(long long _x = 0, long long _y = 0) { x = _x; y = _y; } point operator-(const point &rhs) const { return point(x - rhs.x, y - rhs.y); } } p[N], p2[N]; long long cross(point a, point b) { return a.x * b.y - a.y * b.x; } long long dp(int i, int j, int op, point p[]) { if (f[op][i][j] != -1) return f[op][i][j]; if (j - i < 2) return 1; f[op][i][j] = 0; for (int k = i + 1; k <= j - 1; k++) { if (cross(p[k] - p[i], p[j] - p[i]) > 0) { f[op][i][j] += (dp(i, k, op, p) * dp(k, j, op, p)) % mod; f[op][i][j] %= mod; } } return f[op][i][j]; } int main() { memset(f, -1, sizeof(f)); scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lld%lld , &p[i].x, &p[i].y); p2[n - i - 1].x = p[i].x; p2[n - i - 1].y = p[i].y; } long long ans1, ans2; ans1 = dp(0, n - 1, 0, p); ans2 = dp(0, n - 1, 1, p2); printf( %lld n , max(ans1, ans2)); return 0; }
|
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
`define assert(condition) if(!((|{condition{)===1)) begin $display("FAIL"); $finish(1); end
module pixels_lost_test;
reg[9:0] x1;
reg[8:0] y1;
reg[9:0] x2;
reg[8:0] y2;
reg[9:0] x3;
reg[8:0] y3;
reg[9:0] x4;
reg[8:0] y4;
wire[6:0] percent_lost;
initial begin
x1 = 10'd80;
y1 = 9'd80;
x2 = 10'd80;
y2 = 9'd160;
x3 = 10'd160;
y3 = 9'd160;
x4 = 10'd160;
y4 = 9'd80;
end
reg clock = 0;
pixels_lost pixels_lost(clock, x1, y1, x2, y2, x3, y3, x4, y4, percent_lost);
always #1 clock <= !clock;
always @(posedge clock) begin
$display("%d, %d, %d, %d, %d, %d, %d, %d, %d", x1, y1, x2, y2, x3, y3, x4, y4, percent_lost);
end
endmodule
|
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