text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; int mb[3], cd[3]; int mn[] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; bool chk() { if (mb[1] > 12) return 0; int i, j, k, tm; tm = mn[mb[1]]; if (mb[1] == 2 && !(mb[2] & 3)) tm++; if (tm < mb[0]) return 0; for (i = mb[2]; i < cd[2]; i++) ; i -= (mb[2] + 1); int dy, m; if (mb[0] == 29 && mb[1] == 2 && (cd[2] & 3)) { dy = 1; m = 3; } else { dy = mb[0]; m = mb[1]; } if (cd[1] > m || (cd[1] == m && cd[0] >= dy)) i++; return i >= 18; } int main() { bool f = 0; scanf( %d.%d.%d %d.%d.%d , &cd[0], &cd[1], &cd[2], &mb[0], &mb[1], &mb[2]); sort(mb, mb + 3); do { if (chk()) { f = 1; break; } } while (next_permutation(mb, mb + 3)); if (f) puts( YES ); else puts( NO ); return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dec_table.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dec_table (
address,
clock,
q);
input [7:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "dec_table.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "dec_table.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "dec_table.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* This program demonstrates non-constant part selects
* applied to a signal value.
*/
module main;
wire [31:0] foo = 32'h76543210;
reg [3:0] tmp;
reg [3:0] idx;
initial begin
#1 /* Wait for initial assignments to settle. */ ;
if (foo[0 +: 4] !== 4'h0) begin
$display("FAILED -- %b !== 0", foo[0 +: 4]);
$finish;
end
if (foo[4 +: 4] !== 4'h1) begin
$display("FAILED -- %b !== 1", foo[4 +: 4]);
$finish;
end
if (foo[8 +: 4] !== 4'h2) begin
$display("FAILED -- %b !== 2", foo[8 +: 4]);
$finish;
end
if (foo[12+: 4] !== 4'h3) begin
$display("FAILED -- %b !== 3", foo[12 +: 4]);
$finish;
end
for (idx = 0 ; idx < 8 ; idx = idx + 1) begin
tmp = foo[(idx*4) +: 4];
if (tmp !== idx) begin
$display("FAILED -- %b !== %b", idx, tmp);
$finish;
end
end
for (idx = 0 ; idx < 8 ; idx = idx + 1) begin
tmp = foo[(idx*4+3) -: 4];
if (tmp !== idx) begin
$display("FAILED -- %b !== %b", idx, tmp);
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_1_V
`define SKY130_FD_SC_HDLL__O21BAI_1_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21bai_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21bai_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_1_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_implication_assert
assert_implication_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.antecedent_expr(antecedent_expr),
.consequent_expr(consequent_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_implication_assume
assert_implication_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.antecedent_expr(antecedent_expr),
.consequent_expr(consequent_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_implication_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_implication_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.antecedent_expr(antecedent_expr));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_implication.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_implication_assert (clk, reset_n, antecedent_expr, consequent_expr, xzcheck_enable);
input clk, reset_n, antecedent_expr, consequent_expr, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_implication_assume (clk, reset_n, antecedent_expr, consequent_expr, xzcheck_enable);
input clk, reset_n, antecedent_expr, consequent_expr, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_implication_cover (clk, reset_n, antecedent_expr);
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n, antecedent_expr;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:26:26 05/17/2016
// Design Name:
// Module Name: Driver_bus_bidireccional
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Driver_bus_bidireccional(
input clk,
input in_flag_escritura,//bandera para capturar dato
input in_flag_lectura,
input in_direccion_dato,
input [7:0]in_dato,//Datos de entrada para rtc
output reg [7:0]out_reg_dato,//Datos de salida para banco de registros
input [7:0]addr_RAM,//Dato de direccion para RAM
inout tri [7:0]dato //Dato de RTC
);
reg [7:0]dato_secundario;
reg [7:0]next_out_dato;
//*********************************************************
// ASIGNACION DE BUS DE 3 ESTADOS
assign dato = (in_flag_escritura)? dato_secundario : 8'bZ;
//LOGICA SECUENCIAL
always@(posedge clk) begin
out_reg_dato <= next_out_dato;
end
//CONTROLADOR DE SALIDA
always @(*)
begin
case({in_flag_escritura,in_flag_lectura,in_direccion_dato})
3'b000: begin dato_secundario = 8'd0; //NO DEBE PASAR
next_out_dato = out_reg_dato;
end
3'b011: begin dato_secundario = 8'd0;//LEER DATO
next_out_dato = dato;
end
3'b100: begin dato_secundario = addr_RAM;// ESCRIBIR DIRECCION RAM
next_out_dato = out_reg_dato;
end
3'b101: begin dato_secundario = in_dato;// ESCRIBE DATO
next_out_dato = out_reg_dato;
end
default: begin
dato_secundario = 8'd0; //NO DEBE PASAR
next_out_dato = out_reg_dato;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cout.setf(ios::fixed); cout.precision(20); int n; cin >> n; if (n == 5) return 0 * puts( 1 ); cout << n % 3 + 1 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, tot, m, l, r, len; char c; int po[400005], ha[400005], ys[400005], fi[400005], la[400005]; int s[400005], id[400005], t[400005], sum[400005], it[400005]; struct pi { int num, hai; }; pi find(int li, int ri) { int f1 = 0, f2 = 0, lp = li, rp = ri; pi tmp; if (it[li] == it[ri]) { if (s[li] == 1) { if ((ri - li + 1) % 2 == 1) { tmp.hai = (long long)2 * po[2 * n] % 1000000007; } else tmp.hai = 0; tmp.num = (ri - li + 1) / 2; } else { tmp.num = 0; tmp.hai = (long long)(ha[ys[ri]] - ha[ys[li] - 1] + 1000000007) % 1000000007 * po[2 * n - ys[ri]] % 1000000007; } return tmp; } if (s[li] == 1) lp = la[lp] + 1; if (s[ri] == 1) rp = fi[rp] - 1; if ((lp - li) & 1) f1 = 1; if ((ri - rp) & 1) f2 = 1; tmp.hai = (long long)(ha[ys[rp]] - ha[ys[lp] - 1] + 1000000007) % 1000000007 * po[2 * n - 1 - ys[rp]] % 1000000007; tmp.num = sum[rp] - sum[lp]; tmp.num += (lp - li) / 2; tmp.num += (ri - rp) / 2; if (f2 == 1) tmp.hai = (tmp.hai + (long long)2 * po[2 * n] % 1000000007) % 1000000007; else tmp.hai = (long long)tmp.hai * po[1] % 1000000007; int len = ri - li + 1 - tmp.num * 2; if (f1 == 1) tmp.hai = (tmp.hai + (long long)2 * po[2 * n - len + 1] % 1000000007) % 1000000007; return tmp; } int main() { scanf( %d , &n); s[0] = -1; s[n + 1] = -1; for (int i = 1; i <= n; i++) { scanf( %c , &c); s[i] = c - 0 ; } int tit = 0; for (int i = 1; i <= n; i++) { if (s[i] != s[i - 1]) fi[i] = i, tit++; else fi[i] = fi[i - 1]; it[i] = tit; } for (int i = n; i >= 1; i--) { if (s[i] != s[i + 1]) la[i] = i; else la[i] = la[i + 1]; } po[0] = 1; for (int i = 1; i <= 2 * n; i++) po[i] = (long long)po[i - 1] * 1500007 % 1000000007; for (int i = 1; i <= n; i++) { t[++tot] = s[i]; id[tot] = i; if (t[tot] == 1 && t[tot - 1] == 1) tot -= 2, sum[i]++; ys[i] = tot; } for (int i = 1; i <= n; i++) sum[i] += sum[i - 1]; for (int i = 1; i <= tot; i++) ha[i] = (ha[i - 1] + (long long)po[i] * (t[i] + 1) % 1000000007) % 1000000007; scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &l, &r, &len); pi t1 = find(l, l + len - 1), t2 = find(r, r + len - 1); if (t1.hai == t2.hai && t1.num == t2.num) puts( Yes ); else puts( No ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100; char ch[maxn][maxn]; int main() { int n; scanf( %d , &n); for (int i = 0; i <= n + 1; i++) { for (int j = 0; j <= n + 1; j++) { ch[i][j] = # ; } } for (int i = 1; i <= n; i++) { getchar(); for (int j = 1; j <= n; j++) { scanf( %c , &ch[i][j]); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (ch[i][j] == # ) { continue; } if (ch[i - 1][j] == # ) { continue; } if (ch[i][j - 1] == # ) { continue; } if (ch[i + 1][j] == # ) { continue; } if (ch[i][j + 1] == # ) { continue; } ch[i][j] = # ; ch[i][j + 1] = # ; ch[i][j - 1] = # ; ch[i + 1][j] = # ; ch[i - 1][j] = # ; } } bool ans = true; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (ch[i][j] == . ) { ans = false; } } } if (ans) { printf( YES n ); } else { printf( NO n ); } return 0; }
|
module sequence_detector_fsm(data_out, state, reset, data_in, clk);
output data_out;
output reg [2:0] state; // Matching progress.
input reset, data_in, clk;
// For data_out.
parameter FOUND = 1'b1,
NOT_FOUND = 1'b0;
// For state.
parameter S0 = 3'd0,
S1 = 3'd1,
S2 = 3'd2,
S3 = 3'd3,
S4 = 3'd4,
S5 = 3'd5,
S6 = 3'd6;
reg this_data_in;
reg [2:0] next_state;
// Update state.
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= S0;
this_data_in <= 1'b0;
end else begin
state <= next_state;
this_data_in <= data_in;
end
end
// Calculate data_out.
assign data_out = (state == S6 ? FOUND : NOT_FOUND);
// Calculate next state.
always @(state, this_data_in) begin
case (state)
S0: next_state = (this_data_in ? S1 : S0);
S1: next_state = (this_data_in ? S1 : S2);
S2: next_state = (this_data_in ? S3 : S0);
S3: next_state = (this_data_in ? S1 : S4);
S4: next_state = (this_data_in ? S5 : S0);
S5: next_state = (this_data_in ? S6 : S4);
S6: next_state = (this_data_in ? S1 : S2);
default: next_state = S0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double pi = 3.1415926535897932384626433; const long long inf = 1e18; const long long mod = 1e9 + 7; void solve() { long long n; cin >> n; vector<long long> a(n); vector<vector<long long> > cnt(100001); long long me = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; cnt[a[i]].push_back(i); me = max(me, a[i]); } bool ok = 1; for (long long i = me; i >= 2; i--) { if (cnt[i].size() > cnt[i - 1].size()) { ok = 0; break; } } if (!ok) { cout << -1 n ; return; } vector<long long> ans(n); long long c = 0; for (long long i = 1; i <= me; i++) { long long k = 1; for (auto x : cnt[i]) { ans[x] = k; k++; c = max(c, k); } } cout << c - 1 << n ; for (long long i = 0; i < n; i++) { cout << ans[i] << ; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; t = 1; while (t--) { solve(); } }
|
`timescale 1ns/1ps
/*
This file contains analog / mixed signal cells, or other things that are not possible to fully model
in behavioral Verilog.
It also contains some stuff like oscillators that use non-synthesizeable constructs such as delays.
TODO: do we want a third file for those cells?
*/
module GP_ABUF(input wire IN, output wire OUT);
assign OUT = IN;
//must be 1, 5, 20, 50
//values >1 only available with Vdd > 2.7V
parameter BANDWIDTH_KHZ = 1;
endmodule
module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
parameter BANDWIDTH = "HIGH";
parameter VIN_ATTEN = 1;
parameter VIN_ISRC_EN = 0;
parameter HYSTERESIS = 0;
initial OUT = 0;
endmodule
module GP_BANDGAP(output reg OK);
parameter AUTO_PWRDN = 1;
parameter CHOPPER_EN = 1;
parameter OUT_DELAY = 100;
endmodule
module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
initial VOUT = 0;
//analog hard IP is not supported for simulation
endmodule
module GP_LFOSC(input PWRDN, output reg CLKOUT);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter OUT_DIV = 1;
initial CLKOUT = 0;
//auto powerdown not implemented for simulation
//output dividers not implemented for simulation
always begin
if(PWRDN)
CLKOUT = 0;
else begin
//half period of 1730 Hz
#289017;
CLKOUT = ~CLKOUT;
end
end
endmodule
module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
parameter GAIN = 1;
parameter INPUT_MODE = "SINGLE";
initial VOUT = 0;
//cannot simulate mixed signal IP
endmodule
module GP_PWRDET(output reg VDD_LOW);
initial VDD_LOW = 0;
endmodule
module GP_VREF(input VIN, output reg VOUT);
parameter VIN_DIV = 1;
parameter VREF = 0;
//cannot simulate mixed signal IP
endmodule
module GP_POR(output reg RST_DONE);
parameter POR_TIME = 500;
initial begin
RST_DONE = 0;
if(POR_TIME == 4)
#4000;
else if(POR_TIME == 500)
#500000;
else begin
$display("ERROR: bad POR_TIME for GP_POR cell");
$finish;
end
RST_DONE = 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_TB_V
`define SKY130_FD_SC_MS__O2111AI_TB_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2111ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__o2111ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 15, OO = 1e6 + 3; int n, q, t1, t2; int inv[N], y[15], de[15]; long long MOD(long long a, long long b) { a %= b; if (a < 0) a += b; return a; } void rangeInv(long long m) { inv[1] = 1; for (long long i = 2; i < m; ++i) inv[i] = (m - (m / i) * inv[m % i] % m) % m; } int f(int x) { printf( ? %d n , x); fflush(stdout); scanf( %d , &x); return x; } int F(int x) { int ret = 0; for (int i = 0; i < 11; ++i) { int l = 1; for (int j = 0; j < 11; ++j) { if (j == i) continue; l = MOD(1ll * l * (x - j), OO); } int li = de[i]; l = (1ll * li * l) % OO; ret += (1ll * l * y[i]) % OO; if (ret >= OO) ret -= OO; } return ret; } int main() { rangeInv(OO); for (int i = 0; i < 11; ++i) { y[i] = f(i); de[i] = 1; for (int j = 0; j < 11; ++j) { if (j == i) continue; de[i] = MOD(de[i] * (i - j), OO); } de[i] = inv[de[i]]; } for (int i = 0; i <= OO; ++i) { if (F(i) == 0) { printf( ! %d n , i); fflush(stdout); return 0; } } printf( ! -1 n ); fflush(stdout); }
|
#include <bits/stdc++.h> using namespace std; const int pri[26] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, -1}; const long long mo[5] = {223092870ll, 2756205443ll, 907383479ll, 42600829ll, 97ll}; long long a[10000], c, ans; vector<long long> f[17][5]; int b[100], n, m, t, d, k, l; char s[40]; void prework() { int j = 0; for (int i = 2; i <= 16; i++) { for (j = 0, k = l = 1; k <= n; k *= i, l *= i + 1) ; for (j = 0; j < 5; j++) f[i][j].resize(l, -1); } } int calc(int d, int p) { int x = 0, y = 0; for (int i = 0; i < t; i++) x = x * (d + 1) + b[i]; if (f[d][p][x] != -1) return x; f[d][p][x] = 1; for (int i = 0; i < t; i++) if (b[i] == d) { for (int j = 0; j < d; j++) { b[i] = j; f[d][p][x] = f[d][p][x] * f[d][p][calc(d, p)] % mo[p]; } b[i] = d; return x; } for (int i = 0; i < t; i++) y = y * d + b[i]; if (y < n) f[d][p][x] = a[y] % mo[p]; return x; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %I64d , &a[i]); prework(); scanf( %d , &m); int flag; while (m--) { scanf( %d , &d); scanf( %s , s); scanf( %I64d , &c); t = 0; for (int j = 1; j <= n; t++, j *= d) ; for (int j = 0; j < t; j++) { k = strlen(s) - t + j; b[j] = k >= 0 ? (s[k] == ? ? d : (s[k] <= 9 ? s[k] - 0 : s[k] + 10 - A )) : 0; } flag = 25; for (int i = 0; i < 5; i++) { int key = calc(d, i); ans = (f[d][i][key] + c) % mo[i]; for (int j = 0; j < 25; j++) if ((mo[i] % pri[j] == 0) && (ans % pri[j] == 0)) { flag = j; break; } if (flag < 25) break; } printf( %d n , pri[flag]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long dis(long long x1, long long x2, long long y1, long long y2) { return (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); } int main() { int n; cin >> n; long long x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; long long x[n + 1], y[n + 1]; for (int i = 0; i < (int)(n); ++i) { cin >> x[i] >> y[i]; } x[n] = x1, y[n] = y1; long long ans = 1e18; for (int i = 0; i < n + 1; i++) { long long r1 = dis(x[i], x1, y[i], y1); long long r2 = 0; for (int j = 0; j < n + 1; j++) { long long val = dis(x[j], x2, y[j], y2); long long val1 = dis(x[j], x1, y[j], y1); if (val1 > r1) { r2 = max(r2, val); } } ans = min(ans, r1 + r2); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace FGF { int n, m; const int N = 2e5 + 5; const double eps = 1e-10; struct Node { double x, t; } a[N]; double sum, ans; bool cmp(Node u, Node v) { return u.t < v.t; } void work() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %lf , &a[i].x); for (int i = 1; i <= n; i++) { scanf( %lf , &a[i].t), a[i].t -= m; sum += a[i].x * a[i].t; } sort(a + 1, a + n + 1, cmp); if (a[1].t > 0 || a[n].t < 0) { puts( 0 ); return; } if (sum > 0) { sum = 0; for (int i = 1; i <= n; i++) { if (sum + a[i].x * a[i].t > 0) { ans = ans + sum / (-a[i].t); break; } else ans += a[i].x, sum += a[i].x * a[i].t; } } else { sum = 0; for (int i = n; i; i--) { if (sum + a[i].x * a[i].t < 0) { ans = ans + sum / (-a[i].t); break; } else ans += a[i].x, sum += a[i].x * a[i].t; } } printf( %.12f , ans); } } // namespace FGF int main() { FGF::work(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A22O_BEHAVIORAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int k, l, m, n, i, j, d, fucked = 0; cin >> k >> l >> m >> n >> d; int p[100010]; if (k == 1 || l == 1 || m == 1 || n == 1) { cout << d; } else { for (i = 1; i <= d; i++) { if (i % (k) == 0 || i % (l) == 0 || i % (m) == 0 || i % (n) == 0) { p[i] = -1; } else { p[i] = 0; } } for (j = 1; j <= d; j++) { if (p[j] == -1) { fucked++; } } cout << fucked << endl; } return 0; }
|
#include <bits/stdc++.h> const double eps = 1e-10, pi = acos(-1.0); const int maxS = 1e2 + 10; const int maxS2 = 5e4 + 10; const unsigned long long MOD = 1e9 + 7; using namespace std; struct point { int x, y, z; }; int n, m, i, j, k, x, y, z, T, ii, t, l, r, pos; int tot = 0, cnt = 0, ans = 0, sum = 0; bool chk, chk2[maxS], flag; string s, s1, s2; char c[maxS][maxS]; vector<point> res; void print(int x, int y, int l) { int i; for (i = x - l; i <= x + l; i++) c[i][y] = # ; for (i = y - l; i <= y + l; i++) c[x][i] = # ; } bool deal(int x, int y, int l) { int i; if (x - l < 0 || x + l >= n || y - l < 0 || y + l >= m) return false; for (i = x - l; i <= x + l; i++) if (c[i][y] == . ) return false; for (i = y - l; i <= y + l; i++) if (c[x][i] == . ) return false; print(x, y, l); res.push_back({x, y, l}); chk = true; return true; } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (i = 0; i < n; i++) for (j = 0; j < m; j++) cin >> c[i][j]; for (i = 0; i < n; i++) for (j = 0; j < m; j++) if (c[i][j] == * ) { chk = false; for (k = 1; k < min(n, m); k++) if (deal(i, j, k)) break; if (!chk) for (k = 1; k < min(n, m); k++) if (deal(i + k, j, k)) break; if (!chk) for (k = 1; k < min(n, m); k++) if (deal(i - k, j, k)) break; if (!chk) for (k = 1; k < min(n, m); k++) if (deal(i, j + k, k)) break; if (!chk) for (k = 1; k < min(n, m); k++) if (deal(i, j - k, k)) break; } chk = true; for (i = 0; i < n; i++) for (j = 0; j < m; j++) if (c[i][j] == * ) chk = false; if (!chk) cout << -1 << endl; else { cout << res.size() << endl; for (i = 0; i < res.size(); i++) cout << res[i].x + 1 << << res[i].y + 1 << << res[i].z << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; long long prime[16] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53}; long long n, ans; void DFS(int x, int limit, long long num, long long cnt) { if (cnt > n) return; if (cnt == n && num < ans) ans = num; for (int i = 1; i <= limit; i++) { if (ans / prime[x] < num) break; num *= prime[x]; DFS(x + 1, i, num, cnt * (i + 1)); } } int main() { scanf( %lld , &n); ans = INF; DFS(0, 64, 1, 1); printf( %lld n , ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { int ans, h, r; double tmp; scanf( %d%d , &r, &h); ans = h / r * 2; tmp = h % r; if (r / 2.0 - tmp > 1e-8) ans++; else if (sqrt(3) / 2 * r - tmp > 1e-8) ans += 2; else ans += 3; printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 2000000000; struct pkt { int k, r; }; struct prze { int k, r1, r2; }; bool porownanie(pkt a, pkt b) { if (a.k < b.k) return true; if (a.k > b.k) return false; if (a.r < b.r) return true; return false; } int main() { ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; vector<pkt> pkty(m); for (int i = 0; i < m; ++i) { cin >> pkty[i].r >> pkty[i].k; --pkty[i].r; --pkty[i].k; } sort(pkty.begin(), pkty.end(), porownanie); vector<vector<prze> > zab; for (int L = 0; L < m;) { int P = L; while (P < m && pkty[L].k == pkty[P].k) ++P; --P; vector<prze> t; for (int l = L; l <= P;) { int p = l; while (p <= P && pkty[p].r - pkty[l].r == p - l) ++p; --p; t.push_back({pkty[l].k, pkty[l].r, pkty[p].r}); l = p + 1; } zab.push_back(t); L = P + 1; } for (int i = 0; i < zab.size(); ++i) { if (zab[i].size() == 1 && zab[i][0].r1 == 0 && zab[i][0].r2 == n - 1) { cout << -1 ; return 0; } } vector<vector<prze> > doz; if (zab[0][0].k != 0) { vector<prze> t; t.push_back({0, 0, n - 1}); doz.push_back(t); } for (int i = 0; i < zab.size(); ++i) { if (i != 0) { if (zab[i - 1][0].k != zab[i][0].k - 1) { vector<prze> t; t.push_back({zab[i][0].k - 1, 0, n - 1}); doz.push_back(t); } } int ile_prze = zab[i].size(); vector<prze> t; if (zab[i][0].r1 - 1 >= 0) t.push_back({zab[i][0].k, 0, zab[i][0].r1 - 1}); for (int j = 0; j < ile_prze - 1; ++j) t.push_back({zab[i][0].k, zab[i][j].r2 + 1, zab[i][j + 1].r1 - 1}); if (zab[i][ile_prze - 1].r2 < n - 1) t.push_back({zab[i][0].k, zab[i][ile_prze - 1].r2 + 1, n - 1}); doz.push_back(t); } if (zab.back()[0].k != n - 1) { vector<prze> t; t.push_back({n - 1, 0, n - 1}); doz.push_back(t); } zab.clear(); vector<vector<int> > lo(doz.size()); for (int i = 0; i < doz.size(); ++i) for (int j = 0; j < doz[i].size(); ++j) lo[i].push_back(INF); for (int i = 0; i < lo[0].size(); ++i) { if (i == 0) lo[0][i] = 0; else lo[0][i] = INF; } for (int i = 1; i < doz.size(); ++i) { vector<int> g(doz[i].size(), INF); int k = 0; for (int j = 0; j < doz[i].size(); ++j) { while (k < doz[i - 1].size() && doz[i - 1][k].r2 < doz[i][j].r1) ++k; if (k < doz[i - 1].size()) g[j] = k; } vector<int> d(doz[i].size(), INF); k = doz[i - 1].size() - 1; for (int j = doz[i].size() - 1; j >= 0; --j) { while (k >= 0 && doz[i - 1][k].r1 > doz[i][j].r2) --k; if (k >= 0) d[j] = k; } for (int j = 0; j < doz[i].size(); ++j) { if (d[j] != INF && g[j] != INF && g[j] <= d[j]) { for (int k = g[j]; k <= d[j]; ++k) { if (lo[i - 1][k] != INF) { if (lo[i - 1][k] < doz[i][j].r1) lo[i][j] = min(lo[i][j], doz[i][j].r1); else { if (lo[i - 1][k] <= doz[i][j].r2) lo[i][j] = min(lo[i][j], lo[i - 1][k]); } } } } } } int x = doz.size(); int y = doz[x - 1].size(); if (doz[x - 1][y - 1].r2 == n - 1 && lo[x - 1][y - 1] != INF) cout << 2 * (n - 1); else cout << -1 ; return 0; }
|
/* Atari on an FPGA
Masters of Engineering Project
Cornell University, 2007
Daniel Beer
RIOT.v
Redesign of the MOS 6532 chip. Provides RAM, I/O and timers to the Atari.
*/
`timescale 1ns / 1ps
`include "riot.vh"
module RIOT(A, // Address bus input
Din, // Data bus input
Dout, // Data bus output
CS, // Chip select input
CS_n, // Active low chip select input
R_W_n, // Active low read/write input
RS_n, // Active low rom select input
RES_n, // Active low reset input
IRQ_n, // Active low interrupt output
CLK, // Clock input
PAin, // 8 bit port A input
PAout, // 8 bit port A output
PBin, // 8 bit port B input
PBout);// 8 bit port B output
input [6:0] A;
input [7:0] Din;
output [7:0] Dout;
input CS, CS_n, R_W_n, RS_n, RES_n, CLK;
output IRQ_n;
input [7:0] PAin, PBin;
output [7:0] PAout, PBout; // Output register
reg [7:0] Dout; // RAM allocation
reg [7:0] RAM[127:0]; // I/O registers
reg [7:0] DRA, DRB; // Data registers
reg [7:0] DDRA, DDRB; // Data direction registers
wire PA7;
reg R_PA7;
assign PA7 = (PAin[7] & ~DDRA[7]) | (DRA[7] & DDRA[7]);
assign PAout = DRA & DDRA;
assign PBout = DRB & DDRB;
// Timer registers
reg [8:0] Timer;
reg [9:0] Prescaler;
reg [1:0] Timer_Mode;
reg Timer_Int_Flag, PA7_Int_Flag, Timer_Int_Enable, PA7_Int_Enable, PA7_Int_Mode; // Timer prescaler constants
wire [9:0] PRESCALER_VALS[3:0];
assign PRESCALER_VALS[0] = 10'd0;
assign PRESCALER_VALS[1] = 10'd7;
assign PRESCALER_VALS[2] = 10'd63;
assign PRESCALER_VALS[3] = 10'd1023;
// Interrupt
assign IRQ_n = ~(Timer_Int_Flag & Timer_Int_Enable | PA7_Int_Flag & PA7_Int_Enable);
// Operation decoding
wire [6:0] op;
reg [6:0] R_op;
assign op = {RS_n, R_W_n, A[4:0]};
// Registered data in
reg [7:0] R_Din;
integer cnt;
// Software operations
always @(posedge CLK)
begin
// Reset operation
if (~RES_n) begin
DRA <= 8'b0;
DDRA <= 8'b0;
DRB <= 8'b00010100;
DDRB <= 8'b00010100;
Timer_Int_Flag <= 1'b0;
PA7_Int_Flag <= 1'b0;
PA7_Int_Enable <= 1'b0;
PA7_Int_Mode <= 1'b0;
// Fill RAM with 0s
for (cnt = 0; cnt < 128; cnt = cnt + 1)
RAM[cnt] <= 8'b0;
R_PA7 <= 1'b0;
R_op <= `NOP;
R_Din <= 8'b0;
end
// If the chip is enabled, execute an operation
else if (CS & ~CS_n) begin
// Register inputs for use later
R_PA7 <= PA7;
R_op <= op;
R_Din <= Din;
// Update the timer interrupt flag
casex (op)
`WRITE_TIMER: Timer_Int_Flag <= 1'b0;
`READ_TIMER: Timer_Int_Flag <= 1'b0;
default: if (Timer == 9'b111111111) Timer_Int_Flag <= 1'b1;
endcase
// Update the port A interrupt flag
casex (op)
`READ_INT_FLAG: PA7_Int_Flag <= 1'b0;
default: PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode);
endcase
// Process the current operation
casex(op) // RAM access
`READ_RAM: Dout <= RAM[A];
`WRITE_RAM: RAM[A] <= Din;
// Port A data access
`READ_DRA : Dout <= (PAin & ~DDRA) | (DRA & DDRA);
`WRITE_DRA: DRA <= Din;
// Port A direction register access
`READ_DDRA: Dout <= DDRA;
`WRITE_DDRA: DDRA <= Din;
// Port B data access
`READ_DRB: Dout <= (PBin & ~DDRB) | (DRB & DDRB);
`WRITE_DRB: DRB <= Din;
// Port B direction register access
`READ_DDRB: Dout <= DDRB;
`WRITE_DDRB: DDRB <= Din;
// Timer access
`READ_TIMER: Dout <= Timer[7:0];
// Status register access
`READ_INT_FLAG: Dout <= {Timer_Int_Flag, PA7_Int_Flag, 6'b0};
// Enable the port A interrupt
`WRITE_EDGE_DETECT: begin
PA7_Int_Mode <= A[0]; PA7_Int_Enable <= A[1];
end
endcase
end
// Even if the chip is not enabled, update background functions
else begin
// Update the timer interrupt
if (Timer == 9'b111111111)
Timer_Int_Flag <= 1'b1;
// Update the port A interrupt
R_PA7 <= PA7;
PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode);
// Set the operation to a NOP
R_op <=`NOP;
end
end
// Update the timer at the negative edge of the clock
always @(negedge CLK)begin
// Reset operation
if (~RES_n) begin
Timer <= 9'b0;
Timer_Mode <= 2'b0;
Prescaler <= 10'b0;
Timer_Int_Enable <= 1'b0;
end
// Otherwise, process timer operations
else
casex
(R_op)
// Write value to the timer and update the prescaler based on the address
`WRITE_TIMER:begin
Timer <= {1'b0, R_Din};
Timer_Mode <= R_op[1:0];
Prescaler <= PRESCALER_VALS[R_op[1:0]];
Timer_Int_Enable <= R_op[3];
end
// Otherwise decrement the prescaler and if necessary the timer.
// The prescaler holds a variable number of counts that must be
// run before the timer is decremented
default:if (Timer != 9'b100000000) begin
if (Prescaler != 10'b0)
Prescaler <= Prescaler - 10'b1;
else begin
if (Timer == 9'b0)
begin
Prescaler <= 10'b0;
Timer_Mode <= 2'b0;
end
else
Prescaler <= PRESCALER_VALS[Timer_Mode];
Timer <= Timer - 9'b1;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ans; int main() { vector<int> a(3); for (size_t i = 0; i < 3; i++) { cin >> a[i]; } sort(a.begin(), a.end()); cout << ((a[1] + a[0] > a[2]) ? 0 : (-a[1] - a[0] + a[2] + 1)); }
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2010 www.xilinx.com
//
// XAPPxxx
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : dvi_decoder.v
//
// Description : Spartan-6 DVI decoder top module
//
//
// Author : Bob Feng
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors makeand you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specificallydisclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does notwarrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designswill be
// uninterrupted or error free, or that defects in theDesigns
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results ofthe
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or forany
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on anytheory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure ofthe
// essential purpose of any limited remedies herein.
//
// Copyright © 2004 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1ps
module dvi_decoder (
input wire tmdsclk_p, // tmds clock
input wire tmdsclk_n, // tmds clock
input wire blue_p, // Blue data in
input wire green_p, // Green data in
input wire red_p, // Red data in
input wire blue_n, // Blue data in
input wire green_n, // Green data in
input wire red_n, // Red data in
input wire exrst, // external reset input, e.g. reset button
output wire reset, // rx reset
output wire pclk, // regenerated pixel clock
output wire pclkx2, // double rate pixel clock
output wire pclkx10, // 10x pixel as IOCLK
output wire pllclk0, // send pllclk0 out so it can be fed into a different BUFPLL
output wire pllclk1, // PLL x1 output
output wire pllclk2, // PLL x2 output
output wire pll_lckd, // send pll_lckd out so it can be fed into a different BUFPLL
output wire serdesstrobe, // BUFPLL serdesstrobe output
output wire tmdsclk, // TMDS cable clock
output wire hsync, // hsync data
output wire vsync, // vsync data
output wire de, // data enable
output wire blue_vld,
output wire green_vld,
output wire red_vld,
output wire blue_rdy,
output wire green_rdy,
output wire red_rdy,
output wire psalgnerr,
output wire [29:0] sdout,
output wire [7:0] red, // pixel data out
output wire [7:0] green, // pixel data out
output wire [7:0] blue); // pixel data out
wire [9:0] sdout_blue, sdout_green, sdout_red;
/*
assign sdout = {sdout_red[9], sdout_green[9], sdout_blue[9], sdout_red[8], sdout_green[8], sdout_blue[8],
sdout_red[7], sdout_green[7], sdout_blue[7], sdout_red[6], sdout_green[6], sdout_blue[6],
sdout_red[5], sdout_green[5], sdout_blue[5], sdout_red[4], sdout_green[4], sdout_blue[4],
sdout_red[3], sdout_green[3], sdout_blue[3], sdout_red[2], sdout_green[2], sdout_blue[2],
sdout_red[1], sdout_green[1], sdout_blue[1], sdout_red[0], sdout_green[0], sdout_blue[0]} ;
*/
assign sdout = {sdout_red[9:5], sdout_green[9:5], sdout_blue[9:5],
sdout_red[4:0], sdout_green[4:0], sdout_blue[4:0]};
wire de_b, de_g, de_r;
assign de = de_b;
//wire blue_vld, green_vld, red_vld;
//wire blue_rdy, green_rdy, red_rdy;
wire blue_psalgnerr, green_psalgnerr, red_psalgnerr;
//
// Send TMDS clock to a differential buffer and then a BUFIO2
// This is a required path in Spartan-6 feed a PLL CLKIN
//
wire rxclkint;
IBUFDS #(.IOSTANDARD("TMDS_33"), .DIFF_TERM("FALSE")
) ibuf_rxclk (.I(tmdsclk_p), .IB(tmdsclk_n), .O(rxclkint));
wire rxclk;
BUFIO2 #(.DIVIDE_BYPASS("TRUE"), .DIVIDE(1))
bufio_tmdsclk (.DIVCLK(rxclk), .IOCLK(), .SERDESSTROBE(), .I(rxclkint));
BUFG tmdsclk_bufg (.I(rxclk), .O(tmdsclk));
//
// PLL is used to generate three clocks:
// 1. pclk: same rate as TMDS clock
// 2. pclkx2: double rate of pclk used for 5:10 soft gear box and ISERDES DIVCLK
// 3. pclkx10: 10x rate of pclk used as IO clock
//
PLL_BASE # (
.CLKIN_PERIOD(10),
.CLKFBOUT_MULT(10), //set VCO to 10x of CLKIN
.CLKOUT0_DIVIDE(1),
.CLKOUT1_DIVIDE(10),
.CLKOUT2_DIVIDE(5),
.COMPENSATION("INTERNAL")
) PLL_ISERDES (
.CLKFBOUT(clkfbout),
.CLKOUT0(pllclk0),
.CLKOUT1(pllclk1),
.CLKOUT2(pllclk2),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(pll_lckd),
.CLKFBIN(clkfbout),
.CLKIN(rxclk),
.RST(exrst)
);
//
// Pixel Rate clock buffer
//
BUFG pclkbufg (.I(pllclk1), .O(pclk));
//////////////////////////////////////////////////////////////////
// 2x pclk is going to be used to drive IOSERDES2 DIVCLK
//////////////////////////////////////////////////////////////////
BUFG pclkx2bufg (.I(pllclk2), .O(pclkx2));
//////////////////////////////////////////////////////////////////
// 10x pclk is used to drive IOCLK network so a bit rate reference
// can be used by IOSERDES2
//////////////////////////////////////////////////////////////////
wire bufpll_lock;
BUFPLL #(.DIVIDE(5)) ioclk_buf (.PLLIN(pllclk0), .GCLK(pclkx2), .LOCKED(pll_lckd),
.IOCLK(pclkx10), .SERDESSTROBE(serdesstrobe), .LOCK(bufpll_lock));
assign reset = ~bufpll_lock;
decode dec_b (
.reset (reset),
.pclk (pclk),
.pclkx2 (pclkx2),
.pclkx10 (pclkx10),
.serdesstrobe (serdesstrobe),
.din_p (blue_p),
.din_n (blue_n),
.other_ch0_rdy(green_rdy),
.other_ch1_rdy(red_rdy),
.other_ch0_vld(green_vld),
.other_ch1_vld(red_vld),
.iamvld (blue_vld),
.iamrdy (blue_rdy),
.psalgnerr (blue_psalgnerr),
.c0 (hsync),
.c1 (vsync),
.de (de_b),
.sdout (sdout_blue),
.dout (blue)) ;
decode dec_g (
.reset (reset),
.pclk (pclk),
.pclkx2 (pclkx2),
.pclkx10 (pclkx10),
.serdesstrobe (serdesstrobe),
.din_p (green_p),
.din_n (green_n),
.other_ch0_rdy(blue_rdy),
.other_ch1_rdy(red_rdy),
.other_ch0_vld(blue_vld),
.other_ch1_vld(red_vld),
.iamvld (green_vld),
.iamrdy (green_rdy),
.psalgnerr (green_psalgnerr),
.c0 (),
.c1 (),
.de (de_g),
.sdout (sdout_green),
.dout (green)) ;
decode dec_r (
.reset (reset),
.pclk (pclk),
.pclkx2 (pclkx2),
.pclkx10 (pclkx10),
.serdesstrobe (serdesstrobe),
.din_p (red_p),
.din_n (red_n),
.other_ch0_rdy(blue_rdy),
.other_ch1_rdy(green_rdy),
.other_ch0_vld(blue_vld),
.other_ch1_vld(green_vld),
.iamvld (red_vld),
.iamrdy (red_rdy),
.psalgnerr (red_psalgnerr),
.c0 (),
.c1 (),
.de (de_r),
.sdout (sdout_red),
.dout (red)) ;
assign psalgnerr = red_psalgnerr | blue_psalgnerr | green_psalgnerr;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; char tmp[11]; deque<string> dq; set<string> st; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s , &tmp); dq.push_front(tmp); } for (deque<string>::iterator i = dq.begin(); i != dq.end(); i++) { if (st.count(*i) == 0) { printf( %s n , (*i).c_str()); st.insert(*i); } } return 0; }
|
// "multidimensional-a.v"
// @vcs-flags@ -P pli.tab -sverilog
// -sverilog to support multidimensional arrays
`timescale 1ps / 1ps
`include "multidimensional-reverse.v-wrap"
// wrapper needs repack_arrays=1 workaround
`include "clkgen.v"
//-----------------------------------------------------------------------------
module _timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg a;
wire clk;
wire z1, z2;
// clk_gen #(.HALF_PERIOD(80)) ag(a);
clk_gen #(.HALF_PERIOD(50)) cg(clk);
initial
begin
$prsim_confirm_connections();
$prsim_verbose_transport(1);
// @haco@ multidimensional-a.haco-c
$prsim("multidimensional-a.haco-c");
$display("$start of simulation");
$prsim_cmd("watchall");
end
HAC_three_dee f0();
defparam f0.prsim_name="foo_1";
assign f0.CLK = clk;
// assign f0.A[1][2] = {8{a}}; // only care about [1][2][3]
// assign z = f0.B[1][2][3];
assign f0.C[1] = a; // bus works
assign z1 = f0.D[1];
// assign f0.E[2] = a; // array fails, no input transported
// assign z = f0.F[2];
assign f0.G[1][2][0] = a; // only care about [1][2][3]
assign z2 = f0.H[1][2][0];
initial
begin
#20 a <= 1'b0;
#400 a <= 1'b1;
#400 a <= 1'b0;
#100 a <= 1'b1;
#100 a <= 1'b0;
#100 a <= 1'b1;
#300 a <= 1'b0;
#50 $finish;
end
always @(a)
begin
$display("at time %7.3f, observed a = %b", $realtime, a);
end
always @(z1)
begin
$display("at time %7.3f, observed z1 = %b", $realtime, z1);
end
always @(z2)
begin
$display("at time %7.3f, observed z2 = %b", $realtime, z2);
end
endmodule
|
`ifndef MEMORY_V
`define MEMORY_V
`define MEM_CMD_WIDTH 1
`define MEM_CMD_READ 1'b0
`define MEM_CMD_WRITE 1'b1
module memory#(
parameter ADDRESS_WIDTH=32,
parameter DATA_WIDTH=32,
parameter SIZE = 1024*1024,
parameter READ_DELAY = 22,
parameter WRITE_DELAY = 15
)(
input clk,
input reset,
input [ADDRESS_WIDTH-1:0]i_address,
input [DATA_WIDTH-1:0]i_data,
input i_valid,
input i_res_ready,
input i_cmd,
output [DATA_WIDTH-1:0]o_data,
output o_res_valid,
output o_ready
);
`define CELLS (SIZE / (DATA_WIDTH / 8))
reg [DATA_WIDTH-1:0]memory_cells [0:`CELLS];
wire [ADDRESS_WIDTH-1:0]cell_address = i_address >> $clog2(DATA_WIDTH/8);
reg ready;
reg res_valid;
reg [DATA_WIDTH-1:0]data;
assign o_data = data;
assign o_res_valid = res_valid;
assign o_ready = ready;
//load data
initial begin
string file;
integer fd, size, result;
if ($value$plusargs("img=%s", file)) begin
// get file size
fd = $fopen(file, "r");
result = $fseek(fd, 0, 2);
result = $ftell(fd);
$fclose(fd);
size = (result / 11); // '0' + 'x' + 8chars + lf,
//one cell -- one line no matter the cell size
$display("Loading img file: %s, file size: %d, cells: %d", file, result, size);
$readmemh(file, memory_cells, 0, size - 1); // '0' + 'x' + 8chars + lf
$display("The first word is: %x", memory_cells[0]);
$display("The second word is: %x", memory_cells[1]);
end else begin
$display("Please specify input image file '+img'");
end
end
// reset
always @(posedge clk) begin
if (reset) begin
ready = 1'b1;
res_valid = 1'b0;
data = 1'bx;
end
if (!reset && i_valid && o_ready) begin
case (i_cmd)
//read takes
`MEM_CMD_READ: begin
#READ_DELAY data <= memory_cells[cell_address];
#READ_DELAY res_valid <= 1'b1;
ready <= 1'b0;
end
`MEM_CMD_WRITE: begin
#WRITE_DELAY memory_cells[cell_address] <= i_data;
#WRITE_DELAY res_valid <= 1'b1;
ready <= 1'b0;
end
endcase
end
if (!reset && res_valid && i_res_ready) begin
ready <= 1'b1;
res_valid <= 1'b0;
data <= 1'bx;
end
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_LS__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_ls__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_MUX_4TO2_TB_V
|
#include <bits/stdc++.h> using namespace std; char s[110000]; char res[110000]; int main() { scanf( %s , s); int resLen = 0; int last = 0; int index = 0; for (int i = 0; i < 110000; i++) res[i] = 0; for (char c = z ; c >= a ; c--) for (int i = index; s[i]; i++) if (s[i] == c) { res[resLen] = c; resLen++; index = i + 1; } printf( %s n , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; void sll(long long &x) { register char c = getchar(); x = 0; int neg = 0; for (; ((c < 48 || c > 57) && c != - ); c = getchar()) ; if (c == - ) { neg = 1; c = getchar(); } for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } if (neg) x = -x; } void wll(long long a) { if (a < 0) { putchar( - ); a = -a; } char snum[100]; int i = 0; do { snum[i++] = a % 10 + 48; a = a / 10; } while (a != 0); --i; while (i >= 0) putchar(snum[i--]); putchar( n ); } void wi(int a) { if (a < 0) { putchar( - ); a = -a; } char snum[100]; int i = 0; do { snum[i++] = a % 10 + 48; a = a / 10; } while (a != 0); --i; while (i >= 0) putchar(snum[i--]); putchar( n ); } void wl(long a) { if (a < 0) { putchar( - ); a = -a; } char snum[100]; int i = 0; do { snum[i++] = a % 10 + 48; a = a / 10; } while (a != 0); --i; while (i >= 0) putchar(snum[i--]); putchar( n ); } void sl(long &x) { register char c = getchar(); x = 0; int neg = 0; for (; ((c < 48 || c > 57) && c != - ); c = getchar()) ; if (c == - ) { neg = 1; c = getchar(); } for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } if (neg) x = -x; } void si(int &x) { register char c = getchar(); x = 0; int neg = 0; for (; ((c < 48 || c > 57) && c != - ); c = getchar()) ; if (c == - ) { neg = 1; c = getchar(); } for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } if (neg) x = -x; } long long power(long long a, long long b, long long mod) { long long ret = 1; while (b) { if (b & 1) ret = ret * a % mod; a = a * a % mod; b >>= 1; } return ret; } long long gcd(long long a, long long b) { while (b) b ^= a ^= b ^= a %= b; return a; } int main() { long long t, i, j, k, l; long long a, b, c, d; sll(a); sll(b); sll(c); sll(l); t = (l + 1) * (l + 2) * (l + 3) / 6; long long ans = 0; for (i = 0; i <= l; i++) { long long x = min(l - i, i + a - b - c); if (x >= 0) { x = ((x + 1) * (x + 2)) >> 1; ans += x; } x = min(l - i, i + c - b - a); if (x >= 0) { x = ((x + 1) * (x + 2)) >> 1; ans += x; } x = min(l - i, i + b - c - a); if (x >= 0) { x = ((x + 1) * (x + 2)) >> 1; ans += x; } } wll(t - ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_SYMBOL_V
`define SKY130_FD_SC_HD__CLKBUF_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_SYMBOL_V
|
#include <bits/stdc++.h> template <class T> T Min(const T &a, const T &b) { return a < b ? a : b; } template <class T> T Max(const T &a, const T &b) { return a > b ? a : b; } template <class T> bool Chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <class T> bool Chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } struct fast_input { static const int L = 1 << 15 | 1; char buf[L], *l, *r; fast_input() { l = r = buf; } void Next(char &c) { if (l == r) r = (l = buf) + fread(buf, 1, L, stdin); c = l == r ? (char)EOF : *l++; } template <class T> void operator()(T &x) { char c, f = 0; for (Next(c); !isdigit(c); Next(c)) if (c == - ) f = 1; for (x = 0; isdigit(c); Next(c)) x = x * 10 + c - 0 ; if (f) x = -x; } } input; const int N = 1000 + 3; const int M = 100000 + 7; const int MOD = 998244353; int n, m, a[N], f[N][N], ans[M], b[M]; int Power(int x, int y) { int ret = 1; while (y) { if (y & 1) ret = 1LL * x * ret % MOD; x = 1LL * x * x % MOD, y >>= 1; } return ret; } int main() { int x, y, z; input(n), input(m); for (int i = (1), i_end = (n); i <= i_end; ++i) input(a[i]), b[a[i]] = 1; std::sort(a + 1, a + n + 1); ans[0] = 1; for (int i = (m + 1), i_end = (n); i <= i_end; ++i) ans[0] = 1LL * ans[0] * i % MOD; for (int i = (2), i_end = (n - m); i <= i_end; ++i) ans[0] = 1LL * ans[0] * Power(i, MOD - 2) % MOD; int maxans = 0; while (ans[maxans++]) { x = 0; for (int i = (1), i_end = (n); i <= i_end; ++i) x |= (a[i] - maxans + 1 >= 0 && b[a[i] - maxans + 1]); if (!x) { ans[maxans] = ans[maxans - 1]; continue; } f[0][0] = 1, x = 0; for (int j = (1), j_end = (n); j <= j_end; ++j) { for (int k = (1), k_end = (m); k <= k_end; ++k) { while (a[j] - a[x + 1] >= maxans) ++x; f[j][k] = (f[j - 1][k] + f[x][k - 1]) % MOD; } f[j][0] = f[j - 1][0]; } ans[maxans] = f[n][m]; } int ret = 0; for (int i = (1), i_end = (maxans - 2); i <= i_end; ++i) ret = (ret + 1LL * (ans[i] - ans[i + 1]) * i) % MOD; printf( %d n , (ret + MOD) % MOD); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e3 + 10; int tim[maxn]; int ans[30][30]; set<int> q; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 0; i < n * n; i++) { int t; cin >> t; q.insert(t); tim[t]++; } if (n % 2 == 0) { for (auto idx : q) if (tim[idx] % 4) { cout << NO << endl; return 0; } vector<int> p; for (auto idx : q) { for (int i = 0; i < tim[idx] / 4; i++) p.push_back(idx); } int idx = 0; for (int i = 0; i < n / 2; i++) for (int j = 0; j < n / 2; j++) ans[i][j] = ans[i][n - 1 - j] = ans[n - 1 - i][j] = ans[n - 1 - i][n - 1 - j] = p[idx++]; cout << YES << endl; for (int i = 0; i < n; i++, cout << endl) for (int j = 0; j < n; j++) cout << ans[i][j] << ; } else { int odd = 0; vector<int> two; for (auto idx : q) if (tim[idx] % 2) odd++; if (odd > 1) { cout << NO << endl; return 0; } for (auto idx : q) { if (tim[idx] % 2) { ans[n / 2][n / 2] = idx; tim[idx]--; } if (tim[idx] % 4) { two.push_back(idx); tim[idx] -= 2; } } if (two.size() > n - 1 || (n - 1 - two.size()) % 2) { cout << NO << endl; return 0; } if (two.size() < n - 1) for (auto idx : q) { if (tim[idx] > 0 && tim[idx] % 4 == 0) { int qt = tim[idx]; for (int i = 0; i < qt / 2 && two.size() < n - 1; i++) { two.push_back(idx); tim[idx] -= 2; } if (two.size() == n - 1) break; } } vector<int> p; for (auto idx : q) { if (tim[idx] % 4 == 0 && tim[idx] > 0) for (int i = 0; i < tim[idx] / 4; i++) p.push_back(idx); } int idx = 0; for (int i = 0; i < n / 2; i++) for (int j = 0; j < n / 2; j++) ans[i][j] = ans[i][n - 1 - j] = ans[n - 1 - i][j] = ans[n - 1 - i][n - 1 - j] = p[idx++]; idx = 0; for (int i = 0; i < n / 2; i++) { ans[n / 2][i] = ans[n / 2][n - 1 - i] = two[idx++]; ans[i][n / 2] = ans[n - 1 - i][n / 2] = two[idx++]; } cout << YES << endl; for (int i = 0; i < n; i++, cout << endl) for (int j = 0; j < n; j++) cout << ans[i][j] << ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_SYMBOL_V
`define SKY130_FD_SC_HD__O311A_SYMBOL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o311a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_SYMBOL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module sparse_mm_mul_31ns_32s_32_3_Mul3S_1(clk, ce, a, b, p);
input clk;
input ce;
input[31 - 1 : 0] a; // synthesis attribute keep a "true"
input[32 - 1 : 0] b; // synthesis attribute keep b "true"
output[32 - 1 : 0] p;
reg [31 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_reg0;
wire signed [32 - 1 : 0] tmp_product;
reg signed [32 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = $signed({1'b0, a_reg0}) * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module sparse_mm_mul_31ns_32s_32_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
sparse_mm_mul_31ns_32s_32_3_Mul3S_1 sparse_mm_mul_31ns_32s_32_3_Mul3S_1_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_BLACKBOX_V
`define SKY130_FD_SC_LS__O21BAI_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m, a[3010][6010], fa[18010000]; int dx[9] = {-1, -1, -1, 0, 0, 1, 1, 1}, dy[9] = {-1, 0, 1, -1, 1, -1, 0, 1}; inline int read() { int x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f = ch == - , ch = getchar(); while (isdigit(ch)) x = (x << 3) + (x << 1) + ch - 48, ch = getchar(); return f ? -x : x; } inline int find(int x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } inline int calc(int x, int y) { return (x - 1) * m * 2 + y; } int main() { int ans = 0; n = read(), m = read(); int Q = read(); for (int i = 1; i <= n; i++) for (int j = 1; j <= 2 * m; j++) fa[calc(i, j)] = calc(i, j); if (m == 1) { puts( 0 ); return 0; } while (Q--) { int x = read(), y = read(); int flag = 0; for (int i = 0; i < 8; i++) { int xx = x + dx[i], yy = y + dy[i]; if (yy == 0) yy = 2 * m; if (xx < 1 || xx > n || !a[xx][yy]) continue; for (int j = 0; j < 8; j++) { int xxx = x + dx[j], yyy = y + m + dy[j]; if (yyy > 2 * m) yyy = 1; if (xxx < 1 || xxx > n || !a[xxx][yyy]) continue; if (find(calc(xx, yy)) == find(calc(xxx, yyy))) { flag = 1; break; } } } if (flag) continue; a[x][y] = a[x][y + m] = 1; ans++; int fx1 = find(calc(x, y)), fx2 = find(calc(x, y + m)); for (int i = 0; i < 8; i++) { int xx = x + dx[i], yy = y + dy[i]; if (yy > m) { if (a[xx][yy]) fa[find(calc(xx, yy))] = fx1; if (a[xx][1]) fa[find(calc(xx, 1))] = fx2; } else if (yy < 1) { if (a[xx][yy + m]) fa[find(calc(xx, yy + m))] = fx2; if (a[xx][2 * m]) fa[find(calc(xx, 2 * m))] = fx1; } else { if (a[xx][yy]) fa[find(calc(xx, yy))] = fx1; if (a[xx][yy + m]) fa[find(calc(xx, yy + m))] = fx2; } } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 102, T = 1000 * 1000 * 1000 + 7; int a[2600][M]; bool mrk[2600][M]; string s; int ff(long long sum, int n) { if (sum < 0) return 0; if (mrk[sum][n]) return a[sum][n]; if (sum > 25 && n == 1) return 0; if (sum <= 25 && n == 1) return 1; long long temp = 0; for (int i = 0; i < 26; i++) temp += ff(sum - i, n - 1), temp %= T; a[sum][n] = temp; mrk[sum][n] = true; return temp; } int main() { int t; cin >> t; while (t--) { string s; cin >> s; long long sum = 0; for (int i = 0; i < s.length(); i++) sum += s[i] - a ; cout << (ff(sum, s.length()) + T - 1) % T << endl; } return 0; ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_1_V
`define SKY130_FD_SC_MS__O211AI_1_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_1_V
|
#include <bits/stdc++.h> const int inf = 2e9; using namespace std; int dp[505][505], change[505][505]; pair<int, int> parent[505][505]; string second; int calc(int l, int r) { int ans = 0; while (l < r) { if (second[l] != second[r]) ans++; l++; r--; } return ans; } void _try(int l, int r) { while (l < r) { if (second[l] != second[r]) second[r] = second[l]; l++; r--; } } int main() { ios_base::sync_with_stdio(0); int k; cin >> second >> k; int n = second.length(); for (int i = 0; i < 505; i++) for (int j = 0; j < 505; j++) { dp[i][j] = inf; parent[i][j] = make_pair(i, j); } for (int i = 0; i < n; i++) for (int j = i; j < n; j++) { change[i][j] = calc(i, j); } for (int pos = 0; pos < n; pos++) for (int cnt = 1; cnt <= k; cnt++) { if (cnt == 1) { dp[pos][cnt] = change[0][pos]; } else { for (int pos1 = 0; pos1 < pos; pos1++) { int new_v = dp[pos1][cnt - 1] + change[pos1 + 1][pos]; if (dp[pos][cnt] > new_v) { dp[pos][cnt] = new_v; parent[pos][cnt] = make_pair(pos1, cnt - 1); } } } } int ansi = 1; for (int i = 2; i <= k; i++) { if (dp[n - 1][i] < dp[n - 1][ansi]) ansi = i; } int pos = n - 1, j = ansi; vector<pair<int, int> > split; while (parent[pos][j] != make_pair(pos, j)) { pair<int, int> next = parent[pos][j]; pos = next.first; j = next.second; split.push_back(make_pair(pos, j)); } reverse(split.begin(), split.end()); cout << dp[n - 1][ansi] << endl; int l = 0; if (split.empty()) { _try(0, n - 1); cout << second; return 0; } for (int i = 0; i < split.size(); i++) { _try(l, split[i].first); for (int j = l; j <= split[i].first; j++) { cout << second[j]; cout.flush(); } cout << + ; l = split[i].first + 1; } _try(l, n - 1); for (int i = l; i < n; i++) { cout << second[i]; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/30 20:05:42
// Design Name:
// Module Name: Mealy_FSM_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mealy_FSM_tb(
);
reg Clk, reset, ain;
wire [3:0] count;
wire yout;
integer i;
Mealy_FSM DUT (Clk, reset, ain, count, yout);
initial begin
#330 $finish;
end
initial begin
Clk = 0;
for (i = 0; i < 66;i = i + 1) begin
#5 Clk = ~Clk;
end
end
initial begin
reset = 1;
#20 reset = 0;
#170 reset = 1;
#10 reset = 0;
end
initial begin
ain = 0;
#40 ain = 1;
#20 ain = 0;
#60 ain = 1;
#40 ain = 0;
#20 ain = 1;
#30 ain = 0;
#30 ain = 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int n, k, x, y; cin >> n >> k; if (n > k) { x = k * (k + 1); x = x / 2; cout << x << endl; } else { y = n - 1; x = y * (y + 1); x = x / 2; cout << x + 1 << endl; } } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// software programmable clock generator (still needs a reference input!)
module axi_clkgen (
// clocks
clk,
clk_0,
clk_1,
drp_clk,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_CLKIN_PERIOD = 5.0;
parameter PCORE_VCO_DIV = 11;
parameter PCORE_VCO_MUL = 49;
parameter PCORE_CLK0_DIV = 6;
parameter PCORE_CLK1_DIV = 6;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// clocks
input clk;
output clk_0;
output clk_1;
input drp_clk;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// reset and clocks
wire mmcm_rst;
wire drp_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire drp_sel_s;
wire drp_wr_s;
wire [11:0] drp_addr_s;
wire [15:0] drp_wdata_s;
wire [15:0] drp_rdata_s;
wire drp_ack_t_s;
wire drp_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
// processor interface
up_clkgen i_up_clkgen (
.mmcm_rst (mmcm_rst),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_s),
.drp_ack_t (drp_ack_t_s),
.drp_locked (drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
// mmcm instantiations
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (PCORE_CLKIN_PERIOD),
.MMCM_VCO_DIV (PCORE_VCO_DIV),
.MMCM_VCO_MUL (PCORE_VCO_MUL),
.MMCM_CLK0_DIV (PCORE_CLK0_DIV),
.MMCM_CLK1_DIV (PCORE_CLK1_DIV))
i_mmcm_drp (
.clk (clk),
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk_0),
.mmcm_clk_1 (clk_1),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_s),
.drp_ack_t (drp_ack_t_s),
.drp_locked (drp_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__MUX2I_BEHAVIORAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_hdll__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_hdll__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O221AI_FUNCTIONAL_PP_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o221ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, arr[100], k; set<int> todo; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> arr[i]; k += arr[i]; for (long long x = 1; x * x <= arr[i]; x++) { todo.insert(x); todo.insert(arr[i] / x); todo.insert(arr[i] / x + 1); } } long long best = 1; auto nxtIt = todo.begin(); for (int i : todo) { nxtIt++; long long nxtVal = (nxtIt == todo.end()) ? 1LL << 55 : *nxtIt; long long sum = 0; for (int j = 0; j < n; j++) sum += (arr[j] + i - 1) / i; if (sum * i <= k) best = max(best, min(nxtVal - 1, k / sum)); } cout << best; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_TB_V
`define SKY130_FD_SC_HD__BUFBUF_TB_V
/**
* bufbuf: Double buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__bufbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__bufbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR3_PP_SYMBOL_V
`define SKY130_FD_SC_LP__XOR3_PP_SYMBOL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR3_PP_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC optimize(3) using namespace std; const long long INF = 2e18; const int maxn = 1e6 + 6; const int mod = 1e9 + 6; const double eps = 1e-15; inline bool read(long long &num) { char in; bool IsN = false; in = getchar(); if (in == EOF) return false; while (in != - && (in < 0 || in > 9 )) in = getchar(); if (in == - ) { IsN = true; num = 0; } else num = in - 0 ; while (in = getchar(), in >= 0 && in <= 9 ) { num *= 10, num += in - 0 ; } if (IsN) num = -num; return true; } long long n, m, p; long long num[maxn]; vector<long long> v; int vis[maxn]; int getid(long long x) { return lower_bound(v.begin(), v.end(), x) - v.begin() + 1; } long long dp[maxn][2]; long long pre[maxn], first[maxn], sc[maxn]; int main() { int T; scanf( %d , &T); while (T--) { read(n); v.clear(); for (int i = 1; i <= n; i++) { vis[i] = 0; dp[i][0] = dp[i][1] = 0; pre[i] = 0; first[i] = 0; sc[i] = -(1e9 + 7); } for (int i = 1; i <= n; i++) { read(num[i]); v.push_back(num[i]); } long long maxl = 0; sort(v.begin(), v.end()); v.erase((unique(v.begin(), v.end())), v.end()); for (int i = 1; i <= n; i++) vis[getid(num[i])]++; for (int i = 1; i <= n; i++) { int id = getid(num[i]); pre[id]++; dp[id][0] = dp[id][0] + 1; if (pre[id] == 1) first[id] = max(dp[id - 1][0], dp[id - 1][1]); if (pre[id] == vis[id]) dp[id][1] = first[id] + vis[id]; sc[id] = max(sc[id], max(dp[id - 1][0] - pre[id], dp[id - 1][1] - pre[id])); maxl = max(maxl, sc[id] + pre[id] + 1); maxl = max(maxl, max(dp[id][0], dp[id][1])); } printf( %lld n , n - maxl); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/29/2016 07:18:32 PM
// Design Name:
// Module Name: Priority_Encoder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Encoder (
input wire [31:0] d_in,
output wire [7:0] d_out
);
assign d_out = (d_in[31]==1'b1) ? 8'b00011111:
(d_in[30]==1'b1) ? 8'b00011110:
(d_in[29]==1'b1) ? 8'b00011101:
(d_in[28]==1'b1) ? 8'b00011100:
(d_in[27]==1'b1) ? 8'b00011011:
(d_in[26]==1'b1) ? 8'b00011010:
(d_in[25]==1'b1) ? 8'b00011001:
(d_in[24]==1'b1) ? 8'b00011000:
(d_in[23]==1'b1) ? 8'b00010111:
(d_in[22]==1'b1) ? 8'b00010110:
(d_in[21]==1'b1) ? 8'b00010101:
(d_in[20]==1'b1) ? 8'b00010100:
(d_in[19]==1'b1) ? 8'b00010011:
(d_in[18]==1'b1) ? 8'b00010010:
(d_in[17]==1'b1) ? 8'b00010001:
(d_in[16]==1'b1) ? 8'b00010000:
(d_in[15]==1'b1) ? 8'b00001111:
(d_in[14]==1'b1) ? 8'b00001110:
(d_in[13]==1'b1) ? 8'b00001101:
(d_in[12]==1'b1) ? 8'b00001100:
(d_in[11]==1'b1) ? 8'b00001011:
(d_in[10]==1'b1) ? 8'b00001010:
(d_in[9]==1'b1) ? 8'b00001001:
(d_in[8]==1'b1) ? 8'b00001000:
(d_in[7]==1'b1) ? 8'b00000111:
(d_in[6]==1'b1) ? 8'b00000110:
(d_in[5]==1'b1) ? 8'b00000101:
(d_in[4]==1'b1) ? 8'b00000100:
(d_in[3]==1'b1) ? 8'b00000011:
(d_in[2]==1'b1) ? 8'b00000010:
(d_in[1]==1'b1) ? 8'b00000001: 8'b00000000;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, m; cin >> n >> k; m = n * (n - 1) / 2; if ((double)k > ((double)n - 1) / 2) { cout << -1; return 0; } else { cout << k * n << endl; for (int i = 1; i <= n; ++i) { for (int j = 0; j < k; ++j) { cout << i << << (i + j) % n + 1 << endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T BigMod(T b, T p, T m) { if (p == 0) return 1; if (p % 2 == 0) { T s = BigMod(b, p / 2, m); return ((s % m) * (s % m)) % m; } return ((b % m) * (BigMod(b, p - 1, m) % m)) % m; } template <typename T> inline T ModInv(T b, T m) { return BigMod(b, m - 2, m); } template <typename T> inline T Bigmod(T b, T p, T m) { if (p == 0) return 1; else if (!(p & 1)) return (Bigmod(b, p / 2, m) * Bigmod(b, p / 2, m)) % m; else return ((b % m) * Bigmod(b, p - 1, m)) % m; } template <typename T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <typename T> inline T lcm(T a, T b) { if (a < 0) return lcm(-a, b); if (b < 0) return lcm(a, -b); return a * (b / gcd(a, b)); } template <typename T> inline T euclide(T a, T b, T &x, T &y) { if (a < 0) { T d = euclide(-a, b, x, y); x = -x; return d; } if (b < 0) { T d = euclide(a, -b, x, y); y = -y; return d; } if (b == 0) { x = 1; y = 0; return a; } else { T d = euclide(b, a % b, x, y); T t = x; x = y; y = t - (a / b) * y; return d; } } template <typename T> inline T Dis(T x1, T y1, T x2, T y2) { return sqrt((((x1 - x2) * (x1 - x2)) + ((y1 - y2) * (y1 - y2)))); } template <typename T> inline T Angle(T x1, T y1, T x2, T y2) { return atan(double(y1 - y2) / double(x1 - x2)); } template <typename T> inline T DIFF(T a, T b) { T d = a - b; if (d < (T)0) return -d; else return d; } template <typename T> inline T ABS(T a) { if (a < 0) return -a; else return a; } template <typename T> inline long long isLeft(T a, T b, T c) { return (a.x - b.x) * (b.y - c.y) - (b.x - c.x) * (a.y - b.y); } template <typename T> inline void _in(T &x) { register int c = getchar(); x = 0; bool neg = 0; for (; ((c<48 | c> 57) && c != - ); c = getchar()) ; if (c == - ) { neg = 1; c = getchar(); } for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } if (neg) x = -x; } template <typename T> inline bool isLeapYear(T N) { if (N % 4) return 0; else if (N % 100) return 1; else if (N % 400) return 0; else return 1; } template <typename T> inline T Set(T N, T pos) { T A = 1; return N = N | (A << pos); } template <typename T> inline T Reset(T N, T pos) { T A = 1; return N = N & ~(A << pos); } template <typename T> inline bool Check(T N, T pos) { T A = 1; return (bool)(N & (A << pos)); } template <class T, class X> inline T togglebit(T a, X i) { T t = 1; return (a ^ (t << i)); } template <class T, class X> inline T toInt(T &sm, X s) { stringstream ss(s); ss >> sm; return sm; } template <typename T> inline int cdigittoint(T ch) { return ch - 0 ; } template <typename T> inline bool isVowel(T ch) { ch = toupper(ch); if (ch == A || ch == U || ch == I || ch == O || ch == E ) return true; return false; } template <typename T> inline bool isConst(T ch) { if (isalpha(ch) && !isVowel(ch)) return true; return false; } inline double DEG(double x) { return (180.0 * x) / (2 * acos(0.0)); } inline double RAD(double x) { return (x * (double)2 * acos(0.0)) / (180.0); } int main() { long long b1 = ({ long long a; _in(a); a; }), q = ({ long long a; _in(a); a; }), l = ({ long long a; _in(a); a; }), m = ({ long long a; _in(a); a; }); map<long long, bool> A; for (long long i = 1; i <= m; i++) A[({ long long a; _in(a); a; })] = true; if (abs(b1) > l) { printf( 0 n ); return 0; } if (q == 0 || q == 1 || q == -1) { if (q == 0) { if (A[b1]) { if (A[0] == 0) printf( inf n ); else printf( 0 n ); } else { if (A[0] == 0) printf( inf n ); else { if (abs(b1) <= l) printf( 1 n ); else printf( 0 n ); } } } else if (q == 1) { if (A[b1]) printf( 0 n ); else { if (abs(b1) <= l) printf( inf n ); else printf( 0 n ); } } else { if (A[-b1] == 1 && A[b1] == 1) printf( 0 n ); else if (A[-b1] == 1 || A[b1] == 1) { if (abs(b1) <= l) printf( inf n ); else printf( 0 n ); } else { if (abs(b1) <= l) printf( inf n ); else printf( 0 n ); } } } else { if (b1 == 0) { if (A[b1] == 0) printf( inf n ); else printf( 0 n ); return 0; } long long count = 0; while (true) { if (A[b1] == 0 && abs(b1) <= l) count++; b1 *= q; if (abs(b1) > l) break; } printf( %lld n , count); } return 0; }
|
// soc_system_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module soc_system_hps_0 #(
parameter F2S_Width = 0,
parameter S2F_Width = 0
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire [28:0] f2h_sdram0_ADDRESS, // f2h_sdram0_data.address
input wire [7:0] f2h_sdram0_BURSTCOUNT, // .burstcount
output wire f2h_sdram0_WAITREQUEST, // .waitrequest
output wire [63:0] f2h_sdram0_READDATA, // .readdata
output wire f2h_sdram0_READDATAVALID, // .readdatavalid
input wire f2h_sdram0_READ, // .read
input wire f2h_sdram0_clk, // f2h_sdram0_clock.clk
input wire [28:0] f2h_sdram1_ADDRESS, // f2h_sdram1_data.address
input wire [7:0] f2h_sdram1_BURSTCOUNT, // .burstcount
output wire f2h_sdram1_WAITREQUEST, // .waitrequest
output wire [63:0] f2h_sdram1_READDATA, // .readdata
output wire f2h_sdram1_READDATAVALID, // .readdatavalid
input wire f2h_sdram1_READ, // .read
input wire f2h_sdram1_clk, // f2h_sdram1_clock.clk
input wire [28:0] f2h_sdram2_ADDRESS, // f2h_sdram2_data.address
input wire [7:0] f2h_sdram2_BURSTCOUNT, // .burstcount
output wire f2h_sdram2_WAITREQUEST, // .waitrequest
output wire [63:0] f2h_sdram2_READDATA, // .readdata
output wire f2h_sdram2_READDATAVALID, // .readdatavalid
input wire f2h_sdram2_READ, // .read
input wire f2h_sdram2_clk, // f2h_sdram2_clock.clk
input wire [28:0] f2h_sdram3_ADDRESS, // f2h_sdram3_data.address
input wire [7:0] f2h_sdram3_BURSTCOUNT, // .burstcount
output wire f2h_sdram3_WAITREQUEST, // .waitrequest
input wire [63:0] f2h_sdram3_WRITEDATA, // .writedata
input wire [7:0] f2h_sdram3_BYTEENABLE, // .byteenable
input wire f2h_sdram3_WRITE, // .write
input wire f2h_sdram3_clk, // f2h_sdram3_clock.clk
input wire [28:0] f2h_sdram4_ADDRESS, // f2h_sdram4_data.address
input wire [7:0] f2h_sdram4_BURSTCOUNT, // .burstcount
output wire f2h_sdram4_WAITREQUEST, // .waitrequest
input wire [63:0] f2h_sdram4_WRITEDATA, // .writedata
input wire [7:0] f2h_sdram4_BYTEENABLE, // .byteenable
input wire f2h_sdram4_WRITE, // .write
input wire f2h_sdram4_clk, // f2h_sdram4_clock.clk
input wire i2c1_scl, // i2c1_scl_in.clk
output wire i2c1_out_clk, // i2c1_clk.clk
output wire i2c1_out_data, // i2c1.out_data
input wire i2c1_sda, // .sda
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
soc_system_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_sdram0_ADDRESS (f2h_sdram0_ADDRESS), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (f2h_sdram0_BURSTCOUNT), // .burstcount
.f2h_sdram0_WAITREQUEST (f2h_sdram0_WAITREQUEST), // .waitrequest
.f2h_sdram0_READDATA (f2h_sdram0_READDATA), // .readdata
.f2h_sdram0_READDATAVALID (f2h_sdram0_READDATAVALID), // .readdatavalid
.f2h_sdram0_READ (f2h_sdram0_READ), // .read
.f2h_sdram0_clk (f2h_sdram0_clk), // f2h_sdram0_clock.clk
.f2h_sdram1_ADDRESS (f2h_sdram1_ADDRESS), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (f2h_sdram1_BURSTCOUNT), // .burstcount
.f2h_sdram1_WAITREQUEST (f2h_sdram1_WAITREQUEST), // .waitrequest
.f2h_sdram1_READDATA (f2h_sdram1_READDATA), // .readdata
.f2h_sdram1_READDATAVALID (f2h_sdram1_READDATAVALID), // .readdatavalid
.f2h_sdram1_READ (f2h_sdram1_READ), // .read
.f2h_sdram1_clk (f2h_sdram1_clk), // f2h_sdram1_clock.clk
.f2h_sdram2_ADDRESS (f2h_sdram2_ADDRESS), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (f2h_sdram2_BURSTCOUNT), // .burstcount
.f2h_sdram2_WAITREQUEST (f2h_sdram2_WAITREQUEST), // .waitrequest
.f2h_sdram2_READDATA (f2h_sdram2_READDATA), // .readdata
.f2h_sdram2_READDATAVALID (f2h_sdram2_READDATAVALID), // .readdatavalid
.f2h_sdram2_READ (f2h_sdram2_READ), // .read
.f2h_sdram2_clk (f2h_sdram2_clk), // f2h_sdram2_clock.clk
.f2h_sdram3_ADDRESS (f2h_sdram3_ADDRESS), // f2h_sdram3_data.address
.f2h_sdram3_BURSTCOUNT (f2h_sdram3_BURSTCOUNT), // .burstcount
.f2h_sdram3_WAITREQUEST (f2h_sdram3_WAITREQUEST), // .waitrequest
.f2h_sdram3_WRITEDATA (f2h_sdram3_WRITEDATA), // .writedata
.f2h_sdram3_BYTEENABLE (f2h_sdram3_BYTEENABLE), // .byteenable
.f2h_sdram3_WRITE (f2h_sdram3_WRITE), // .write
.f2h_sdram3_clk (f2h_sdram3_clk), // f2h_sdram3_clock.clk
.f2h_sdram4_ADDRESS (f2h_sdram4_ADDRESS), // f2h_sdram4_data.address
.f2h_sdram4_BURSTCOUNT (f2h_sdram4_BURSTCOUNT), // .burstcount
.f2h_sdram4_WAITREQUEST (f2h_sdram4_WAITREQUEST), // .waitrequest
.f2h_sdram4_WRITEDATA (f2h_sdram4_WRITEDATA), // .writedata
.f2h_sdram4_BYTEENABLE (f2h_sdram4_BYTEENABLE), // .byteenable
.f2h_sdram4_WRITE (f2h_sdram4_WRITE), // .write
.f2h_sdram4_clk (f2h_sdram4_clk), // f2h_sdram4_clock.clk
.i2c1_scl (i2c1_scl), // i2c1_scl_in.clk
.i2c1_out_clk (i2c1_out_clk), // i2c1_clk.clk
.i2c1_out_data (i2c1_out_data), // i2c1.out_data
.i2c1_sda (i2c1_sda) // .sda
);
soc_system_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_mul #(
parameter A_DATA_WIDTH = 17,
parameter B_DATA_WIDTH = 17,
parameter DELAY_DATA_WIDTH = 16) (
// data_p = data_a * data_b;
input clk,
input [ A_DATA_WIDTH-1:0] data_a,
input [ B_DATA_WIDTH-1:0] data_b,
output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p,
// delay interface
input [(DELAY_DATA_WIDTH-1):0] ddata_in,
output reg [(DELAY_DATA_WIDTH-1):0] ddata_out);
// internal registers
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
MULT_MACRO #(
.LATENCY (3),
.WIDTH_A (A_DATA_WIDTH),
.WIDTH_B (B_DATA_WIDTH))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),
.CLK (clk),
.A (data_a),
.B (data_b),
.P (data_p));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:26:17 03/17/2015
// Design Name:
// Module Name: alt_ctl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alt_ctl(op,func,aluc
);
input [5:0] op,func;
output reg [4:0] aluc;
always @*
begin
case(op)
6'b000000 : begin //R type
case(func)//Same op, distinguished by function code. 17 instructions
6'b100000 : aluc = 0; //add
6'b100001 : aluc = 1; //addu
6'b100010 : aluc = 2; //sub
6'b100011 : aluc = 3; //subu
6'b100100 : aluc = 4; //and
6'b100101 : aluc = 5; //or
6'b100110 : aluc = 6; //xor
6'b100111 : aluc = 7; //nor
6'b101010 : aluc = 8; //slt
6'b101011 : aluc = 9; //sltu
6'b000000 : aluc = 10; //sll
6'b000010 : aluc = 11; //srl
6'b000011 : aluc = 12; //sra
6'b000100 : aluc = 10; //sllv
6'b000110 : aluc = 11; //srlv
6'b000111 : aluc = 12; //srav
6'b000001 : aluc = 13; //slc?
6'b000010 : aluc = 13; //slcv?
default : aluc = 0;
endcase
end // I type
6'b001000 : aluc = 0; //addi
6'b001001 : aluc = 1; //addiu
6'b001100 : aluc = 4; //andi
6'b001101 : aluc = 5; //ori
6'b001101 : aluc = 6; //xori
6'b001010 : aluc = 8; //slti
6'b001101 : aluc = 9; //sltiu
6'b001111 : aluc = 14;//lui
default : aluc = 0;
endcase
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 3
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_xlconstant_0_0 (
dout
);
output wire [0 : 0] dout;
xlconstant_v1_1_3_xlconstant #(
.CONST_WIDTH(1),
.CONST_VAL('H1)
) inst (
.dout(dout)
);
endmodule
|
module finished_wf
(/*AUTOARG*/
// Outputs
fetchwave_wf_done_en, fetchwave_wf_done_wf_id,
max_instr_inflight_array,
// Inputs
clk, rst, f_decode_wfid, f_sgpr_alu_wr_done_wfid,
f_vgpr_alu_wr_done_wfid, alu_wfid, f_salu_branch_wfid, f_decode_valid,
f_decode_wf_halt, f_vgpr_alu_wr_done, f_sgpr_alu_wr_done, alu_valid,
f_salu_branch_en, mem_wait_arry
);
input clk,rst;
input [`WF_ID_LENGTH-1:0] f_decode_wfid, f_sgpr_alu_wr_done_wfid,
f_vgpr_alu_wr_done_wfid, alu_wfid,
f_salu_branch_wfid;
input f_decode_valid, f_decode_wf_halt, f_vgpr_alu_wr_done,
f_sgpr_alu_wr_done, alu_valid, f_salu_branch_en;
input [`WF_PER_CU-1:0] mem_wait_arry;
output fetchwave_wf_done_en;
output [`WF_ID_LENGTH-1:0] fetchwave_wf_done_wf_id;
output [`WF_PER_CU-1:0] max_instr_inflight_array;
wire decode_wf_halt_valid;
wire [`WF_PER_CU-1:0] decoded_retired_sgpr, decoded_retired_vgpr,
decoded_retired_branch;
wire [`WF_PER_CU-1:0] decoded_decode_wf_halt, decoded_decode_valid,
decoded_wf_done, decoded_no_inflight_instr;
wire [`WF_PER_CU-1:0] done_wf_array;
wire [`WF_PER_CU-1:0] halted_reg_out, halted_reg_in, halted_reg_wr_en;
wire [`WF_PER_CU-1:0] decoded_alu_valid;
// Decoder for the retired instructions
decoder_6b_40b_en decoder_retired_sgpr
(
.addr_in(f_sgpr_alu_wr_done_wfid),
.out(decoded_retired_sgpr),
.en(f_sgpr_alu_wr_done)
);
decoder_6b_40b_en decoder_retired_vgpr
(
.addr_in(f_vgpr_alu_wr_done_wfid),
.out(decoded_retired_vgpr),
.en(f_vgpr_alu_wr_done)
);
decoder_6b_40b_en decoder_retired_branch
(
.addr_in(f_salu_branch_wfid),
.out(decoded_retired_branch),
.en(f_salu_branch_en)
);
// Decoder for the issued instructions
decoder_6b_40b_en decoder_issued_inst
(
.addr_in(alu_wfid),
.out(decoded_alu_valid),
.en(alu_valid)
);
// Decoder for the halt signal
decoder_6b_40b_en decode_wf_halt_decoder
(
.addr_in(f_decode_wfid),
.out(decoded_decode_wf_halt),
.en(decode_wf_halt_valid)
);
decoder_6b_40b_en decode_wf_halt_decoder_valid
(
.addr_in(f_decode_wfid),
.out(decoded_decode_valid),
.en(f_decode_valid)
);
// Decoder for the done wf signal
decoder_6b_40b_en decode_finished_wf
(
.addr_in(fetchwave_wf_done_wf_id),
.out(decoded_wf_done),
.en(fetchwave_wf_done_en)
);
// Register to record witch registers had a halt signals
dff_en halted_reg[`WF_PER_CU-1:0]
(
.q(halted_reg_out),
.d(halted_reg_in),
.en(halted_reg_wr_en),
.clk(clk),
.rst(rst)
);
// Arbiter to chose witch finished wf signal will be issued
arbiter finished_arbiter
(
.issued_en(fetchwave_wf_done_en),
.issued_wf_id(fetchwave_wf_done_wf_id),
.input_arry(done_wf_array),
.choosen_valid(fetchwave_wf_done_en),
.choosen_wf_id(fetchwave_wf_done_wf_id),
.clk(clk),
.rst(rst)
);
// Counter for the inflight instructions
inflight_instr_counter inflight_instr_counters[`WF_PER_CU-1:0]
(
.clk(clk),
.rst(rst),
// Input from retired instructions
.retire_vgpr_1_en(decoded_retired_vgpr),
.retire_branch_en(decoded_retired_branch),
.retire_sgpr_en(decoded_retired_sgpr),
// Input from issued instructions
.issued_en(decoded_alu_valid),
// Output
.no_inflight_instr_flag(decoded_no_inflight_instr),
.max_inflight_instr_flag(max_instr_inflight_array)
);
assign decode_wf_halt_valid = f_decode_valid && f_decode_wf_halt;
assign done_wf_array = halted_reg_out & decoded_no_inflight_instr & ~mem_wait_arry;
assign halted_reg_in = decoded_decode_wf_halt | (~decoded_wf_done & halted_reg_out);
assign halted_reg_wr_en = decoded_decode_valid | decoded_wf_done;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/13/2016 05:51:29 PM
// Design Name:
// Module Name: Testbench_Barrel_Shifter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/11/2016 11:27:29 AM
// Design Name:
// Module Name: Barrel_shifter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
localparam integer lvl = 2**(LEVEL);
localparam integer x = (SWR - 1);
generate for (j=0;j<=SWR-1;j=j+1) begin : MUX_ODDNORM
case ((lvl+j)>(x))
1'b1: begin :BSHITMUX
//assign mux_out = (sel) ? din_1 : din_0;
assign Data_o[j] = (select_i) ? bit_shift_i : Data_i[j];
end
1'b0: begin : FSHITMUX
assign Data_o[j] = (select_i) ? Data_i[lvl+j] : Data_i[j];
end
endcase
end
endgenerate
endmodule
module Testbench_Barrel_Shifter ();
parameter PERIOD = 10;
parameter EWR=5;
parameter SWR=26;
//inputs
reg clk;
reg rst;
reg load_i;
reg [EWR-1:0] Shift_Value_i;
reg [SWR-1:0] Shift_Data_i;
reg Left_Right_i;
reg Bit_Shift_i;
///////////////////OUTPUT//////////////////////////7
wire [SWR-1:0] N_mant_o;
wire [SWR-1:0] Data_array[EWR+1:0];
wire [SWR-1:0] Data_arrayHW[EWR+1:0];
//////////////////7
genvar k;//Level
generate for (k=0; k < EWR; k=k+1) begin : SHIFT1
shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array(
.Data_i(Data_array[k]),
.select_i(Shift_Value_i[k]),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_array[k+1])
);
end
endgenerate
//////////////////////////////////////
shift_mux_array #(.SWR(SWR), .LEVEL(0)) shift_mux_array1(
.Data_i(Data_arrayHW[0]),
.select_i(Shift_Value_i[0]),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_arrayHW[1])
);
shift_mux_array #(.SWR(SWR), .LEVEL(1)) shift_mux_array2(
.Data_i(Data_arrayHW[1]),
.select_i(Shift_Value_i[1]),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_arrayHW[2])
);
shift_mux_array #(.SWR(SWR), .LEVEL(2)) shift_mux_array3(
.Data_i(Data_arrayHW[2]),
.select_i(Shift_Value_i[2]),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_arrayHW[3])
);
shift_mux_array #(.SWR(SWR), .LEVEL(3)) shift_mux_array4(
.Data_i(Data_arrayHW[3]),
.select_i(Shift_Value_i[3]),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_arrayHW[4])
);
shift_mux_array #(.SWR(SWR), .LEVEL(4)) shift_mux_array5(
.Data_i(Data_arrayHW[4]),
.select_i(Shift_Value_i[4]),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_arrayHW[5])
);
//////////////////////////////////////
Barrel_Shifter #(.SWR(SWR),.EWR(EWR)) uut(
.clk(clk),
.rst(rst),
.load_i(load_i),
.Shift_Value_i(Shift_Value_i),
.Shift_Data_i(Shift_Data_i),
.Left_Right_i(Left_Right_i),
.Bit_Shift_i(Bit_Shift_i),
.N_mant_o(N_mant_o)
);
integer Contador_shiftvalue = 0;
always begin
#(8*PERIOD/2) Contador_shiftvalue = Contador_shiftvalue + 1;
Shift_Value_i = Contador_shiftvalue;
#(8*PERIOD/2);
end
always @ (N_mant_o )
begin
$monitor($time,"REA Salida = %b Entrada = %b Numero de Corrimiento: %d",N_mant_o,Shift_Data_i, Shift_Value_i);
$display($time,"TEO Salida = %b Entrada = %b Numero de Corrimiento: %d",(Shift_Data_i>>Shift_Value_i),Shift_Data_i,Shift_Value_i);
end
assign Data_array [0][SWR-1:0] = Shift_Data_i;
assign Data_arrayHW [0][SWR-1:0] = Shift_Data_i;
initial begin
// Initialize Input
rst = 1;
clk = 0;
load_i = 0;
Shift_Value_i = 0;
Shift_Data_i = $random;
Left_Right_i = 0;
Bit_Shift_i = 0;
#40 rst = 0;
load_i = 1;
end
initial begin
#(PERIOD * 1024);
$finish;
end
initial begin
clk = 1'b0;
#(PERIOD/2);
forever
#(PERIOD/2) clk = ~clk;
end
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; typedef long double ld; typedef string ss ; typedef pair<int, int> pi; typedef pair<ll,ll> pl; typedef vector<int> vi; typedef vector<ll> vl; #define mp make_pair #define pb push_back void solve(){ ll n,k=0,q=0; string s; cin >> n >> k ; ll x[n],y[n]; for(int i=0 ; i<n ; i++){ cin >> x[i] >> y[i]; } bool ok=false; for(int i=0 ; i<n ; i++){ for(int j=0 ; j<n ; j++){ if(abs(x[i]-x[j]) + abs(y[i]-y[j]) <= k){ q++; } if(q==n) ok=true; } q=0; } cout << (ok ? 1 n : -1 n ) ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t=1; cin >> t; while(t--) solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_SYMBOL_V
`define SKY130_FD_SC_HVL__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_SYMBOL_V
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module: ram - dual port block RAM
//-----------------------------------------------------------------
module ram
(
// Port A
input clka_i /*verilator public*/,
input rsta_i /*verilator public*/,
input stba_i /*verilator public*/,
input wea_i /*verilator public*/,
input [3:0] sela_i /*verilator public*/,
input [31:2] addra_i /*verilator public*/,
input [31:0] dataa_i /*verilator public*/,
output [31:0] dataa_o /*verilator public*/,
output reg acka_o /*verilator public*/,
// Port B
input clkb_i /*verilator public*/,
input rstb_i /*verilator public*/,
input stbb_i /*verilator public*/,
input web_i /*verilator public*/,
input [3:0] selb_i /*verilator public*/,
input [31:2] addrb_i /*verilator public*/,
input [31:0] datab_i /*verilator public*/,
output [31:0] datab_o /*verilator public*/,
output reg ackb_o /*verilator public*/
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] SIZE = 14;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
wire [3:0] wr_a = {4{stba_i}} & {4{wea_i}} & sela_i;
wire [3:0] wr_b = {4{stbb_i}} & {4{web_i}} & selb_i;
ram_dp8
#(
.WIDTH(8),
.SIZE(SIZE),
.FILENAME("mem_3.hex")
)
u0
(
.aclk_i(clka_i),
.aadr_i(addra_i[SIZE+2-1:2]),
.adat_o(dataa_o[7:0]),
.adat_i(dataa_i[7:0]),
.awr_i(wr_a[0]),
.bclk_i(clkb_i),
.badr_i(addrb_i[SIZE+2-1:2]),
.bdat_o(datab_o[7:0]),
.bdat_i(datab_i[7:0]),
.bwr_i(wr_b[0])
);
ram_dp8
#(
.WIDTH(8),
.SIZE(SIZE),
.FILENAME("mem_2.hex")
)
u1
(
.aclk_i(clka_i),
.aadr_i(addra_i[SIZE+2-1:2]),
.adat_o(dataa_o[15:8]),
.adat_i(dataa_i[15:8]),
.awr_i(wr_a[1]),
.bclk_i(clkb_i),
.badr_i(addrb_i[SIZE+2-1:2]),
.bdat_o(datab_o[15:8]),
.bdat_i(datab_i[15:8]),
.bwr_i(wr_b[1])
);
ram_dp8
#(
.WIDTH(8),
.SIZE(SIZE),
.FILENAME("mem_1.hex")
)
u2
(
.aclk_i(clka_i),
.aadr_i(addra_i[SIZE+2-1:2]),
.adat_o(dataa_o[23:16]),
.adat_i(dataa_i[23:16]),
.awr_i(wr_a[2]),
.bclk_i(clkb_i),
.badr_i(addrb_i[SIZE+2-1:2]),
.bdat_o(datab_o[23:16]),
.bdat_i(datab_i[23:16]),
.bwr_i(wr_b[2])
);
ram_dp8
#(
.WIDTH(8),
.SIZE(SIZE),
.FILENAME("mem_0.hex")
)
u3
(
.aclk_i(clka_i),
.aadr_i(addra_i[SIZE+2-1:2]),
.adat_o(dataa_o[31:24]),
.adat_i(dataa_i[31:24]),
.awr_i(wr_a[3]),
.bclk_i(clkb_i),
.badr_i(addrb_i[SIZE+2-1:2]),
.bdat_o(datab_o[31:24]),
.bdat_i(datab_i[31:24]),
.bwr_i(wr_b[3])
);
// AckA
always @(posedge clka_i or posedge rsta_i)
begin
if (rsta_i == 1'b1)
begin
acka_o <= 1'b0;
end
else
begin
acka_o <= stba_i;
end
end
// AckB
always @(posedge clkb_i or posedge rstb_i)
begin
if (rstb_i == 1'b1)
begin
ackb_o <= 1'b0;
end
else
begin
ackb_o <= stbb_i;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000 * 1000 * 1000; vector<int> g[100100]; int deg[100100]; bool vis[100100]; void dfs(int v) { vis[v] = true; for (int to : g[v]) if (!vis[to]) { dfs(to); } } int main() { int N, M; scanf( %d%d , &N, &M); for (int i = 0; i < (M); ++i) { int u, v; scanf( %d%d , &u, &v); --u; --v; g[u].push_back(v); g[v].push_back(u); ++deg[u]; ++deg[v]; } int q = 0; for (int i = 0; i < (N); ++i) if (!vis[i]) { dfs(i); ++q; } if (q > 1) { puts( unknown topology ); return 0; } sort(deg, deg + N); if (deg[0] == 1 && deg[1] == 1) { bool check = true; for (int i = 2; i < N; ++i) if (deg[i] != 2) { check = false; break; } if (check) { puts( bus topology ); return 0; } } bool check = true; for (int i = 0; i < (N); ++i) if (deg[i] != 2) { check = false; break; } if (check) { puts( ring topology ); return 0; } check = true; if (deg[N - 1] == N - 1) { for (int i = 0; i < (N - 1); ++i) if (deg[i] != 1) { check = false; break; } if (check) { puts( star topology ); return 0; } } puts( unknown topology ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const int maxn = 100000 + 10; struct Point { double x, y; Point() {} Point(double x, double y) : x(x), y(y) {} } inter; struct Line { int a, b, c, id; Line() {} Line(int a, int b, int c, int id) : a(a), b(b), c(c), id(id) {} } e[maxn]; struct Node { int x, y; Node() {} Node(int x, int y) : x(x), y(y) {} } ans[10]; int n, k, cnt, tot, pos; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline int dcmp(double x) { if (fabs(x) < eps) return 0; return x < 0 ? -1 : 1; } bool judge(int l, int r) { if (dcmp((double)e[l].a * e[r].b - (double)e[r].a * e[l].b) == 0) return 0; inter = Point(((double)e[l].b * e[r].c - (double)e[l].c * e[r].b) / ((double)e[l].a * e[r].b - (double)e[r].a * e[l].b), ((double)e[l].a * e[r].c - (double)e[l].c * e[r].a) / ((double)e[l].b * e[r].a - (double)e[l].a * e[r].b)); return 1; } int main() { n = read(), k = read(); for (int i = 1, a, b, c; i <= n; i++) { a = read(), b = read(), c = read(); e[i] = Line(a, b, c, i); } cnt = n; bool exis = 1; while (cnt) { if (k >= cnt) { ans[++tot] = Node(e[cnt].id, -1); cnt--; continue; } for (pos = 1; pos <= 100; pos++) { int a = rand() % cnt + 1, b = rand() % cnt + 1, sz = 0; if (!judge(a, b)) continue; for (int i = 1; i <= cnt; i++) if (dcmp((double)e[i].a * inter.x + (double)e[i].b * inter.y + e[i].c) == 0) sz++; if (sz * k >= cnt) { ans[++tot] = Node(e[a].id, e[b].id); break; } } if (pos > 100) { exis = 0; break; } for (int i = cnt; i >= 1; i--) if (dcmp((double)e[i].a * inter.x + (double)e[i].b * inter.y + (double)e[i].c) == 0) { swap(e[i], e[cnt]); cnt--; } k--; } if (!exis) puts( NO ); else { puts( YES ); printf( %d n , tot); for (int i = 1; i <= tot; i++) printf( %d %d n , ans[i].x, ans[i].y); } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int X = 0, w = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) w = -1; c = getchar(); } while (c >= 0 && c <= 9 ) X = X * 10 + c - 0 , c = getchar(); return X * w; } const int N = 100 + 10; inline int id(int x, int y) { if (x & 1) return (x - 1) * 10 + y; else return (x - 1) * 10 + 11 - y; } int to[N]; double dp[N]; int main() { for (register int i = 1; i <= 10; ++i) for (register int j = 1; j <= 10; ++j) to[id(i, j)] = id(i - read(), j); for (register int i = 2; i <= 6; ++i) { for (register int j = 1; j < i; ++j) dp[i] += dp[j] / 6; dp[i] = (dp[i] + 1) / (i - 1) * 6; } for (register int i = 7; i <= 100; ++i) { for (register int j = 1; j <= 6; ++j) dp[i] += min(dp[i - j], dp[to[i - j]]); dp[i] = dp[i] / 6 + 1; } printf( %.10lf n , dp[100]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[10]; long long ans = 0; void DFS(long long n, long long u, long long r[10]) { if (n == 10) { long long sum = 1; for (long long i = 2; i <= u; i++) sum *= i; for (long long i = 1; i < 10; i++) for (long long j = 2; j <= r[i]; j++) sum /= j; long long b = 0; for (long long i = 1; i <= a[0]; i++) { long long d = 1, f = 1; for (long long j = 0; j < i; j++) { d *= u + j; f *= j + 1; } b += d / f; } if (a[0] == 0) b = 1; ans += b * sum; return; } if (a[n] == 0) { r[n] = 0; DFS(n + 1, u, r); return; } for (long long i = 1; i <= a[n]; i++) { r[n] = i; DFS(n + 1, u + i, r); } } int main() { long long d[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; long long s; cin >> s; while (s) { a[s % 10]++; s /= 10; } DFS(1, 0, d); cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NAND2_FUNCTIONAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_BLACKBOX_V
`define SKY130_FD_SC_LP__OR4_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e15; const int MOD = 1e9 + 7; const double EPS = 1e-9; const double PI = acos(-1.0); mt19937 rng((int)chrono::steady_clock::now().time_since_epoch().count()); const int N = 105; pair<long long, long long> e[N]; long long n, m, a[N]; vector<vector<int>> capacity; vector<vector<int>> adj; int bfs(int s, int t, vector<int>& parent) { fill(parent.begin(), parent.end(), -1); parent[s] = -2; queue<pair<int, int>> q; q.push({s, MOD}); while (!q.empty()) { int cur = q.front().first; int flow = q.front().second; q.pop(); for (int next : adj[cur]) { if (parent[next] == -1 && capacity[cur][next]) { parent[next] = cur; int new_flow = min(flow, capacity[cur][next]); if (next == t) return new_flow; q.push({next, new_flow}); } } } return 0; } int maxflow(int s, int t) { int flow = 0; vector<int> parent(N); int new_flow; while (new_flow = bfs(s, t, parent)) { flow += new_flow; int cur = t; while (cur != s) { int prev = parent[cur]; capacity[prev][cur] -= new_flow; capacity[cur][prev] += new_flow; cur = prev; } } return flow; } void add_primes(long long x, set<long long>& primes) { for (int i = 2; i <= x / i; ++i) { if (x % i == 0) { primes.insert(i); while (x % i == 0) x /= i; } } if (x != 1) primes.insert(x); } long long cnt(long long x, long long p) { long long ret = 0; while (x && x % p == 0) { ++ret; x /= p; } return ret; } int main() { ios::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); cin >> n >> m; adj = vector<vector<int>>(N); capacity = vector<vector<int>>(N, vector<int>(N)); set<long long> primes; for (int i = 1; i <= n; ++i) { cin >> a[i]; add_primes(a[i], primes); } for (int i = 1; i <= n; ++i) { if (i & 1) { adj[0].push_back(i); adj[i].push_back(0); } else { adj[n + 1].push_back(i); adj[i].push_back(n + 1); } } for (int i = 0; i < m; ++i) { cin >> e[i].first >> e[i].second; int u = e[i].first; int v = e[i].second; adj[u].push_back(v); adj[v].push_back(u); } long long ans = 0; for (auto p : primes) { for (int i = 1; i <= n; ++i) { if (i & 1) capacity[0][i] = cnt(a[i], p); else capacity[i][n + 1] = cnt(a[i], p); } for (int i = 0; i < m; ++i) { int u = e[i].first; int v = e[i].second; if (u & 1) capacity[u][v] = cnt(a[u], p); else capacity[v][u] = cnt(a[v], p); } ans += maxflow(0, n + 1); } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int j1 = 0; j1 < t; j1++) { long long int n; cin >> n; long long int arr[n]; long long int sum1 = 0; long long int sum2 = 0; for (int j = 0; j < (n / 2); j++) { arr[j] = ((2 * j) + 2); sum1 += arr[j]; } long long int p = 1; for (int k = n / 2; k < n - 1; k++) { arr[k] = (2 * p - 1); p++; sum2 += (arr[k]); } arr[n - 1] = sum1 - sum2; if (n % 4 == 0) { cout << YES << endl; for (int m = 0; m < n; m++) { cout << arr[m] << ; } cout << endl; } else { cout << NO << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PSA_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PSA_PP_PKG_S_SYMBOL_V
/**
* udp_dlatch$PSa_pp$PKG$s: Positive level sensitive D-type -latch
* with active low
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$PSa_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_ASYNC,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PSA_PP_PKG_S_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 1000 + 10; const int INF = 0x7f7f7f7f; const double eps = 1e-8; const double pi = 3.1415926535897932384626433832795; double p[Maxn], f[Maxn][Maxn]; long long L[Maxn], R[Maxn]; inline long long power(int a, int b) { long long ans = 1; for (int i = 1; i <= b; i++) ans *= a; return ans; } double calc(long long a, long long b) { char ch[50]; int len1, len2; long long ansa = 0, ansb = 0; a--; sprintf(ch, %I64d , a); len1 = (int)strlen(ch); for (int i = 1; i < len1; i++) ansa += power(10, i - 1); if (ch[0] != 1 && ch[0] != 0 ) ansa += power(10, len1 - 1); else if (ch[0] == 1 ) ansa += a - power(10, len1 - 1) + 1; sprintf(ch, %I64d , b); len2 = (int)strlen(ch); for (int i = 1; i < len2; i++) ansb += power(10, i - 1); if (ch[0] != 1 && ch[0] != 0 ) ansb += power(10, len2 - 1); else if (ch[0] == 1 ) ansb += b - power(10, len2 - 1) + 1; return (ansb - ansa) * 1.0 / (b - a); } int main() { int n, K; cin >> n; for (int i = 1; i <= n; i++) { cin >> L[i] >> R[i]; p[i] = calc(L[i], R[i]); } cin >> K; f[0][0] = 1; for (int i = 1; i <= n; i++) { f[i][0] = 1; for (int j = 1; j <= i; j++) f[i][0] *= (1 - p[j]); } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) f[i][j] = f[i - 1][j] * (1 - p[i]) + f[i - 1][j - 1] * p[i]; double ans = 0; for (int i = 0; i <= n; i++) if (100 * i >= K * n) ans += f[n][i]; printf( %.11f n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline char nc() { return getchar(); static char buf[100000], *l = buf, *r = buf; return l == r && (r = (l = buf) + fread(buf, 1, 100000, stdin), l == r) ? EOF : *l++; } template <class T> void read(T &x) { x = 0; int f = 1, ch = nc(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = nc(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 - 0 + ch; ch = nc(); } x *= f; } const int inf = 1e9 + 1; const int maxn = 100 + 5; const int maxs = 1e5 + 5; const int maxb = 1e5 + 5; int n, m; int s, b, k; int st, ed; int val[maxn]; int dis[maxn][maxn]; int head[maxs]; vector<int> adj[maxn]; struct data { int a, b, c, d, id; inline bool operator<(const data &other) const { return b < other.b; } } A[maxs], B[maxb]; struct edge { int to, nex; long long cap, flow; edge(int to = 0, int nex = 0, long long cap = 0, long long flow = 0) : to(to), nex(nex), cap(cap), flow(flow) {} }; vector<edge> G; inline void adde(int u, int v) { adj[u].push_back(v); adj[v].push_back(u); } inline void addedge(int u, int v, long long c) { G.push_back(edge(v, head[u], c, 0)), head[u] = G.size() - 1; G.push_back(edge(u, head[v], 0, 0)), head[v] = G.size() - 1; } namespace dinic { int dis[maxs], cur[maxs]; bool BFS() { static int q[maxs]; int hd = 0, tl = 0; memset(dis, -1, sizeof(dis)); dis[st] = 0; q[tl++] = st; while (hd < tl) { int u = q[hd++]; for (int i = head[u]; ~i; i = G[i].nex) { int v = G[i].to; if (dis[v] == -1 && G[i].cap != G[i].flow) { dis[v] = dis[u] + 1; q[tl++] = v; } } } return dis[ed] != -1; } long long DFS(int u, long long flow) { if (u == ed || flow == 0) return flow; long long rec = flow; for (int &i = cur[u]; ~i; i = G[i].nex) { int v = G[i].to; if (dis[v] == dis[u] + 1) { long long d = DFS(v, min(flow, G[i].cap - G[i].flow)); G[i].flow += d; G[i ^ 1].flow -= d; flow -= d; if (flow == 0) break; } } return rec - flow; } long long maxflow() { long long flow = 0; while (BFS()) { memcpy(cur, head, sizeof(head)); flow += DFS(st, 1e18); } return flow; } } // namespace dinic int adde(int x) { int mx = -1; for (int i = 1; i <= n; ++i) if (dis[A[x].a][i] <= A[x].c) { mx = max(mx, val[i]); } if (mx == -1) { addedge(A[x].id, ed, 1e18); return 0; } mx -= A[x].d; if (mx < 0) { addedge(A[x].id, ed, -mx); return 0; } addedge(st, A[x].id, mx); return mx; } void BFS(int st) { static int q[maxn]; int hd = 0, tl = 0; for (int i = 1; i <= n; ++i) dis[st][i] = inf; dis[st][st] = 0; q[tl++] = st; while (hd < tl) { int u = q[hd++]; for (unsigned int i = 0; i < adj[u].size(); ++i) { int v = adj[u][i]; if (dis[st][v] == inf) { dis[st][v] = dis[st][u] + 1; q[tl++] = v; } } } } void init() { for (int i = 1; i <= n; ++i) BFS(i); } long long solve() { init(); sort(A + 1, A + s + 1); sort(B + 1, B + b + 1); long long an = 0; int i = 1, j = 1; st = 0, ed = s + 1; memset(val, -1, sizeof(val)); while (i <= s && j <= b) { if (B[j].b <= A[i].b) { val[B[j].a] = max(val[B[j].a], B[j].c); ++j; } else { an += adde(i++); } } while (i <= s) an += adde(i++); return an - dinic ::maxflow(); } int main() { read(n), read(m); for (int i = 1; i <= m; ++i) { int u, v; read(u), read(v); adde(u, v); } read(s), read(b), read(k); for (int i = 1; i <= s; ++i) { read(A[i].a), read(A[i].b), read(A[i].c), read(A[i].d); A[i].id = i; } for (int i = 1; i <= b; ++i) { read(B[i].a), read(B[i].b), read(B[i].c); } memset(head, -1, sizeof(head)); for (int i = 1; i <= k; ++i) { int s1, s2; read(s1), read(s2); addedge(s1, s2, 1e18); } printf( %I64d n , solve()); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 10; int n, m, q, v[maxn], lp[maxn]; vector<int> e[maxn], t[maxn]; vector<long long> ps[maxn]; int mx, argmx; void dfs(int id, int p, int d, int cpn) { if (cpn) v[id] = cpn; lp[id] = max(lp[id], d); if (d > mx) { mx = d; argmx = id; } if (cpn) t[cpn].push_back(lp[id]); for (int i = 0; i < e[id].size(); i++) if (e[id][i] != p) dfs(e[id][i], id, d + 1, cpn); } int main() { scanf( %d %d %d , &n, &m, &q); for (int i = 0; i < m; i++) { int x, y; scanf( %d %d , &x, &y); e[x].push_back(y); e[y].push_back(x); } int cpn = 0; for (int i = 1; i <= n; i++) if (!v[i]) { mx = -1; dfs(i, 0, 0, 0); mx = -1; dfs(argmx, 0, 0, 0); mx = -1; dfs(argmx, 0, 0, ++cpn); sort(t[cpn].begin(), t[cpn].end()); ps[cpn].push_back(0); for (int j = 0; j < t[cpn].size(); j++) ps[cpn].push_back(ps[cpn].back() + t[cpn][j]); } map<pair<int, int>, double> res; for (int i = 0; i < q; i++) { int x, y; scanf( %d %d , &x, &y); x = v[x]; y = v[y]; if (x == y) printf( -1 n ); else { if (t[x].size() > t[y].size()) swap(x, y); if (!res.count({x, y})) { auto ans = 0LL; int mxd = max(t[x].back(), t[y].back()); for (int j = 0; j < t[x].size(); j++) { int l = lower_bound(t[y].begin(), t[y].end(), mxd - 1 - t[x][j]) - t[y].begin(); ans += 1LL * l * mxd + 1LL * (t[y].size() - l) * (t[x][j] + 1) + ps[y].back() - ps[y][l]; } res.insert({{x, y}, ans * 1.0 / t[x].size() / t[y].size()}); } printf( %.10lf n , res[{x, y}]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; string res = ; if (s.find( . ) == string::npos) { s += . ; } int d = s.find( . ); int i = d - 1; int c = 0; while (i >= 0) { if (s[i] != - ) res = s[i] + res; c++; if (c == 3 && i > 0) { if (i - 1 >= 0 && s[i - 1] != - ) res = , + res; c = 0; } i--; } res += . ; int dc = s.length() - 1 - d; if (dc == 0) { res += 00 ; } else if (dc == 1) { res += s[d + 1]; res += 0 ; } else if (dc >= 2) { res += s[d + 1]; res += s[d + 2]; } res = $ + res; if (s[0] == - ) res = ( + res + ) ; cout << res << endl; }
|
`timescale 1ns / 1ps
`include "../src/mutex_buffer.v"
module test_mutex_buffer(
);
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
reg[11:0] ori_height = 320;
reg[11:0] ori_width = 240;
reg[11:0] w_left = 3;
reg[11:0] w_top = 3;
reg[11:0] w_width = 5;
reg[11:0] w_height = 6;
reg resetn;
reg clk;
reg w_sof;
reg r0_sof;
reg r1_sof;
wire [31:0] w_addr;
wire [31:0] r0_addr;
wire [31:0] r1_addr;
mutex_buffer #(
.C_ADDR_WIDTH(32)
)uut(
.buf0_addr(32'h3FF00000),
.buf1_addr(32'h3FF10000),
.buf2_addr(32'h3FF20000),
.buf3_addr(32'h3FF30000),
.w_sof(w_sof),
.r0_sof(r0_sof),
.r1_sof(r1_sof),
.w_addr(w_addr),
.r0_addr(r0_addr),
.r1_addr(r1_addr),
.clk(clk),
.resetn(resetn));
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
parameter integer C_RAN_FACTOR = 50;
always @(posedge clk) begin
if (resetn == 1'b0) begin
w_sof <= 0;
r0_sof <= 0;
r1_sof <= 0;
end
else begin
w_sof <= w_sof ? 0 : ({$random}%C_RAN_FACTOR == 0);
r0_sof <= r0_sof ? 0 : ({$random}%C_RAN_FACTOR == 0);
r1_sof <= r1_sof ? 0 : ({$random}%C_RAN_FACTOR == 0);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename...> static inline int getchar_unlocked(void) { return getchar(); } template <typename...> static inline void putchar_unlocked(int c) { putchar(c); } void reader(int& x) { int k, m = 0; x = 0; for (;;) { (k) = getchar_unlocked(); if (k == - ) { m = 1; break; } if ( 0 <= k && k <= 9 ) { x = k - 0 ; break; } } for (;;) { (k) = getchar_unlocked(); if (k < 0 || k > 9 ) break; x = x * 10 + k - 0 ; } if (m) x = -x; } void reader(long long& x) { int k, m = 0; x = 0; for (;;) { (k) = getchar_unlocked(); if (k == - ) { m = 1; break; } if ( 0 <= k && k <= 9 ) { x = k - 0 ; break; } } for (;;) { (k) = getchar_unlocked(); if (k < 0 || k > 9 ) break; x = x * 10 + k - 0 ; } if (m) x = -x; } int reader(char c[]) { int i, s = 0; for (;;) { (i) = getchar_unlocked(); if (i != && i != n && i != r && i != t && i != EOF) break; } c[s++] = i; for (;;) { (i) = getchar_unlocked(); if (i == || i == n || i == r || i == t || i == EOF) break; c[s++] = i; } c[s] = 0 ; return s; } template <class T, class S> void reader(T& x, S& y) { reader(x); reader(y); } template <class T, class S, class U> void reader(T& x, S& y, U& z) { reader(x); reader(y); reader(z); } template <class T, class S, class U, class V> void reader(T& x, S& y, U& z, V& w) { reader(x); reader(y); reader(z); reader(w); } void writer(int x, char c) { int s = 0, m = 0; char f[10]; if (x < 0) m = 1, x = -x; while (x) f[s++] = x % 10, x /= 10; if (!s) f[s++] = 0; if (m) putchar_unlocked( - ); while (s--) putchar_unlocked(f[s] + 0 ); putchar_unlocked(c); } void writer(long long x, char c) { int s = 0, m = 0; char f[20]; if (x < 0) m = 1, x = -x; while (x) f[s++] = x % 10, x /= 10; if (!s) f[s++] = 0; if (m) putchar_unlocked( - ); while (s--) putchar_unlocked(f[s] + 0 ); putchar_unlocked(c); } void writer(const char c[]) { int i; for (i = 0; c[i] != 0 ; i++) putchar_unlocked(c[i]); } void writer(const char x[], char c) { int i; for (i = 0; x[i] != 0 ; i++) putchar_unlocked(x[i]); putchar_unlocked(c); } template <class T> void writerLn(T x) { writer(x, n ); } template <class T, class S> void writerLn(T x, S y) { writer(x, ); writer(y, n ); } template <class T, class S, class U> void writerLn(T x, S y, U z) { writer(x, ); writer(y, ); writer(z, n ); } template <class T> void writerArr(T x[], int n) { if (!n) { putchar_unlocked( n ); return; } for (int i = 0; i < (n - 1); i++) writer(x[i], ); writer(x[n - 1], n ); } template <class T> void chmax(T& l, const T r) { l = max(l, r); } template <class T> void chmin(T& l, const T r) { l = min(l, r); } template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <class T> T extgcd(T a, T b, T& x, T& y) { for (T u = y = 1, v = x = 0; a;) { T q = b / a; swap(x -= q * u, u); swap(y -= q * v, v); swap(b -= q * a, a); } return b; } template <class T> T mod_inv(T a, T m) { T x, y; extgcd(a, m, x, y); return (m + x % m) % m; } long long mod_pow(long long a, long long n, long long mod) { long long ret = 1; long long p = a % mod; while (n) { if (n & 1) ret = ret * p % mod; p = p * p % mod; n >>= 1; } return ret; } struct P { long double x, y; P() : x(0), y(0) {} P(const long double& x, const long double& y) : x(x), y(y) {} P operator+(const P& a) const { return P(x + a.x, y + a.y); } P& operator+=(const P& a) { x += a.x; y += a.y; return *this; } P operator-(const P& a) const { return P(x - a.x, y - a.y); } P& operator-=(const P& a) { x -= a.x; y -= a.y; return *this; } P operator*(const long double a) const { return P(a * x, a * y); } P& operator*=(const long double a) { x *= a; y *= a; return *this; } P operator/(const long double a) const { return P(x / a, y / a); } P& operator/=(const long double a) { x /= a; y /= a; return *this; } bool operator<(const P& a) const { return (x != a.x) ? (x < a.x) : (y < a.y); } }; const double PI = acos(-1); P rot(const P& a, double theta) { theta = -theta / 180 * PI; return P(a.x * cos(theta) - a.y * sin(theta), a.x * sin(theta) + a.y * cos(theta)); } long double SQ(long double x) { return x * x; } long double dist2(const P& a, const P& b) { return SQ(a.x - b.x) + SQ(a.y - b.y); } long double abs2(const P& p) { return SQ(p.x) + SQ(p.y); } long double dot(const P& a, const P& b) { return a.x * b.x + a.y * b.y; } long double cross(const P& a, const P& b) { return a.x * b.y - a.y * b.x; } long double abs(const P& p) { return sqrt(abs2(p)); } double arg(const P& a) { double t = atan2(a.y, a.x); return t < 0 ? t + 2 * PI : t; } struct Q { long double x, y; int argsum; static Q zero() { Q ret = {0, 0, 0}; return ret; } bool is_zero() const { return x == 0 && y == 0; } Q operator+(const Q& r) const { if (is_zero()) return r; else if (r.is_zero()) return *this; P p1(x, y); P p2(r.x, r.y); p2 = rot(p2, argsum); P cur = p1 + p2; Q ret; ret.x = cur.x; ret.y = cur.y; ret.argsum = argsum + r.argsum; return ret; } }; class seg_tree { public: vector<int> len, args; vector<Q> dat; int n; void propagate(int i) { dat[i] = dat[i * 2 + 1] + dat[i * 2 + 2]; } void init(int size) { n = 1; len.resize(size, 1); args.resize(size); while (n < size) n <<= 1; dat.resize(2 * n - 1); fill(dat.begin(), dat.end(), Q::zero()); for (int i = 0; i < size; i++) dat[n - 1 + i].x = 1.0; for (int i = n - 2; i >= 0; i--) propagate(i); } void update_k(int k) { P cur(len[k], 0); cur = rot(cur, args[k]); k += n - 1; dat[k].x = cur.x; dat[k].y = cur.y; dat[k].argsum = args[k - n + 1]; } void update_len(int k, int len) { this->len[k] += len; update_k(k); k += n - 1; while (k > 0) { k = (k - 1) / 2; propagate(k); } } void update_arg(int k, int arg) { args[k] += arg; update_k(k); k += n - 1; while (k > 0) { k = (k - 1) / 2; propagate(k); } } void update_query(int t, int id, int val) { id--; if (t == 1) { update_len(id, val); } else { update_arg(id, val); } } Q query(int a, int b) { return query(a, b, 0, 0, n); } Q query(int a, int b, int k, int l, int r) { if (r <= a || b <= l) return Q::zero(); if (a <= l && r <= b) return dat[k]; int md = (l + r) / 2; int nl = k * 2 + 1, nr = nl + 1; Q lval = query(a, b, nl, l, md); Q rval = query(a, b, nr, md, r); return lval + rval; } }; P q2p(Q& q) { return P(q.x, q.y); } void print(seg_tree& seg, int n) { for (int i = 0; i < (n); i++) { Q q = seg.dat[seg.n - 1 + i]; P p = q2p(q); printf( %d : (%lf,%lf) n , i, p.x, p.y); } } int main() { int n, q; reader(n, q); seg_tree seg; seg.init(n); for (int i = 0; i < (q); i++) { int t, a, b; reader(t, a, b); seg.update_query(t, a, b); Q val = seg.query(0, n); P cur = q2p(val); printf( %.10lf %.10lf n , (double)cur.x, (double)cur.y); } return 0; }
|
#include <bits/stdc++.h> using namespace std; clock_t time_p = clock(); void ktj() { time_p = clock() - time_p; cerr << Time elapsed : << (float)(time_p) / CLOCKS_PER_SEC << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, i, j, k; cin >> n; vector<long long> a(n); for (i = 0; i < n; i++) { cin >> a[i]; } if (n % 2) { for (i = 0; i < n; i++) { if (a[i] >= 0) { a[i] = -a[i] - 1; } } auto mn = min_element(a.begin(), a.end()); a[mn - a.begin()] = -a[mn - a.begin()] - 1; for (i = 0; i < n; i++) { cout << a[i] << ; } cout << n ; } else { for (i = 0; i < n; i++) { if (a[i] >= 0) cout << -a[i] - 1 << ; else cout << a[i] << ; } cout << n ; } ktj(); }
|
#include<bits/stdc++.h> #define int long long int #define pb push_back #define all(x) (x).begin(), (x).end() using namespace std; int solve(int a,int b) { if(a<=0) return 0; return min(1+solve(a/b,b), 2+solve(a/(b+1),b+1)); } signed main() { ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); int t; cin>>t; while(t--) { int a,b; cin>>a>>b; int ans=1e9; for(int i=0;i<100;i++) { int x=b+i; int temp= i; int xa=a; int xb=x; for(int j=0;j<100;j++) { if(xa<=0) break; xa/=xb; temp++; } ans=min(ans,temp); } cout<<ans<<endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_1_V
`define SKY130_FD_SC_HS__EDFXBP_1_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for edfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__edfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__edfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__edfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_1_V
|
//`define SKIP_MIXER
module dmix_top #(
parameter NUM_SPDIF_IN = 1,
parameter NUM_CH = 2,
parameter NUM_CH_LOG2 = 1,
parameter NUM_RATE = 5,
parameter VOL_WIDTH = 32
)(
input wire clk245760_pad,
input wire rst,
input wire [0:(NUM_SPDIF_IN-1)] spdif_i,
// I2S to DAC
output wire dac_sck_o,
output wire dac_bck_o,
output wire dac_lrck_o,
output wire dac_data_o,
// SPI
input wire spi_sck,
input wire spi_mosi,
output wire spi_miso,
input wire spi_ss,
// debug
output wire led_o, // T3
output wire [3:0] debug_o
);
wire clk245760;
wire clk491520;
wire clk983040;
dmix_dcm dcm(
.clk245760_pad(clk245760_pad),
.clk245760(clk245760),
.clk491520(clk491520),
.clk983040(clk983040));
wire rst_ip;
wire rst_dcm;
reg [19:0] rst_counter;
always @(posedge clk245760)
if(rst)
rst_counter <= 0;
else if(rst_counter != 20'hfffff)
rst_counter <= rst_counter + 1;
assign rst_dcm = (rst_counter[19:3] == 17'h00000);
assign rst_ip = (rst_counter[19:3] == 17'h0000e);
wire [(NUM_CH*VOL_WIDTH-1):0] vol;
wire [(NUM_CH*NUM_RATE-1):0] rate;
wire [(NUM_CH-1):0] rst_ch;
wire [(NUM_CH-1):0] fifo_ack;
wire [(NUM_CH*24-1):0] fifo_data;
wire [(NUM_SPDIF_IN*192-1):0] udata;
wire [(NUM_SPDIF_IN*192-1):0] cdata;
csr_spi #(.NUM_CH(NUM_CH), .NUM_SPDIF_IN(NUM_SPDIF_IN)) csr_spi(
.clk(clk491520),
.rst(rst_ip),
.sck(spi_sck), .miso(spi_miso), .mosi(spi_mosi), .ss(spi_ss),
.vol_o(vol), .rate_i(rate), .udata_i(udata), .cdata_i(cdata));
genvar ig;
generate
for(ig = 0; ig < NUM_SPDIF_IN; ig = ig + 1) begin:g
wire [23:0] dai_data_983040;
wire dai_lrck_983040;
wire dai_ack_983040;
wire dai_locked;
wire [(NUM_RATE-1):0] dai_rate;
wire [191:0] dai_udata;
wire [191:0] dai_cdata;
spdif_dai_varclk dai(
.clk(clk983040),
.rst(rst_ip),
.signal_i(spdif_i[ig]),
.data_o(dai_data_983040),
.ack_o(dai_ack_983040),
// .rst_o(dai_rst_983040),
.lrck_o(dai_lrck_983040),
.locked_o(dai_locked),
.udata_o(dai_udata),
.cdata_o(dai_cdata),
.rate_o(dai_rate));
wire [23:0] dai_data_491520;
wire dai_lrck_491520;
reg fifo_pop_ff;
wire fifo_empty;
async_fifo #(.DATA_WIDTH(24 + 1)) fifo(
.wclk(clk983040),
.wrst(rst_ip),
.data_i({dai_data_983040, dai_lrck_983040}),
.ack_i(dai_ack_983040),
// NC: .full_o
.rclk(clk491520),
.rrst(rst_ip),
.data_o({dai_data_491520, dai_lrck_491520}),
.pop_i(fifo_pop_ff),
.empty_o(fifo_empty));
always @(posedge clk491520) begin
if (rst_ip)
fifo_pop_ff <= 0;
else
fifo_pop_ff <= fifo_empty ? 0 : 1;
end
assign rate[(ig*NUM_RATE*2) +: (NUM_RATE*2)] = {2{dai_rate}};
assign udata[(ig*192) +: 192] = dai_udata;
assign cdata[(ig*192) +: 192] = dai_cdata;
assign rst_ch[(ig*2) +: 2] = {2{~dai_locked}};
assign fifo_ack[(ig*2) +: 2] = {fifo_pop_ff & ~dai_lrck_491520, fifo_pop_ff & dai_lrck_491520};
assign fifo_data[(ig*24*2) +: (24*2)] = {2{dai_data_491520}};
end
endgenerate
wire [(NUM_CH-1):0] resampler_pop;
wire [47:0] resampler_data;
wire [(NUM_CH-1):0] resampler_ack;
resample_pipeline #(.NUM_CH(NUM_CH), .NUM_CH_LOG2(NUM_CH_LOG2)) resampler(
.clk(clk491520),
.rst(rst_ip),
.rst_ch(rst_ch),
.rate_i(rate),
.ack_i(fifo_ack),
.data_i(fifo_data),
// .pop_o(fifo_pop) NC???
.pop_i(resampler_pop),
.data_o(resampler_data),
.ack_o(resampler_ack));
`ifndef SKIP_MIXER
wire [1:0] mixer_ack;
wire [23:0] mixer_data;
wire [1:0] mixer_pop;
mixer #(.NUM_CH_IN(NUM_CH), .NUM_CH_IN_LOG2(NUM_CH_LOG2),
.NUM_CH_OUT(2), .NUM_CH_OUT_LOG2(1), .VOL_WIDTH(32)) mixer(
.clk(clk491520), .rst(rst_ip), .rst_ch(rst_ch),
.pop_o(resampler_pop), .ack_i(resampler_ack), .data_i(resampler_data),
.vol_i(vol),
.pop_i(mixer_pop), .data_o(mixer_data), .ack_o(mixer_ack));
dac_drv dac_drv(
.clk(clk491520),
.rst(rst_ip),
.bck_o(dac_bck_o),
.lrck_o(dac_lrck_o),
.data_o(dac_data_o),
.ack_i(mixer_ack),
.data_i(mixer_data),
.pop_o(mixer_pop));
`else
wire [23:0] resampler_data_sel = resampler_ack[1] ? resampler_data[47:24] : resampler_data[23:0];
dac_drv dac_drv(
.clk(clk491520),
.rst(rst_ip),
.bck_o(dac_bck_o),
.lrck_o(dac_lrck_o),
.data_o(dac_data_o),
.ack_i(resampler_ack),
.data_i(resampler_data_sel),
.pop_o(resampler_pop));
`endif
assign dac_sck_o = clk245760;//_pad;
assign led_o = g[0].dai_locked;
assign debug_o[0] = spi_sck;
assign debug_o[1] = spi_mosi;
assign debug_o[2] = spi_miso;
assign debug_o[3] = spi_ss;
endmodule
|
#include <bits/stdc++.h> using namespace std; char rep; void query(long long x, long long y) { cout << ? << x << << y << endl; cin >> rep; return; } void solve() { long long x = 0; long long y = 1; while (true) { query(x, y); if (rep == x ) { break; } x = y; y = y * 2; } long long l = x + 1; long long r = y; while (l != r) { long long med = (l + r) / 2; query(med, y); if (rep == x ) { l = med + 1; } else { r = med; } } cout << ! << l << endl; return; } int main() { string s; while (true) { cin >> s; if (s[0] == s ) { solve(); } else { break; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 1e4; int a[maxn], mod; int b[maxn]; int n; int pow(int a, int b) { if (b == 1) return a; int t = pow(a, b >> 1); t = 1LL * t * t % mod; if (b & 1) t = 1LL * t * a % mod; return t; } int ny(int a) { return pow(a, mod - 2); } int ans, dd; void solve(int a[], int n) { if (n == 1) { ans = a[1]; dd = 1; return; } int cc = a[2] - a[1]; int s = 0; for (int i = (1); i <= (n); ++i) if (!binary_search(a + 1, a + n + 1, (a[i] + cc) % mod)) ++s; cc = 1LL * cc * ny(s) % mod; ans = -1, dd = mod - cc; for (int i = (1); i <= (n); ++i) if (!binary_search(a + 1, a + n + 1, (a[i] + cc) % mod)) { if (ans == -1) ans = a[i]; else { ans = -1; break; } } } void init() { scanf( %d%d , &mod, &n); for (int i = (1); i <= (n); ++i) scanf( %d , &a[i]); if (n == mod) { printf( %d %d n , 0, 1); return; } sort(a + 1, a + n + 1); if (n * 2 > mod) { int t = 0; for (int i = (0); i <= (mod - 1); ++i) if (!binary_search(a + 1, a + n + 1, i)) b[++t] = i; solve(b, t); if (ans != -1) (ans += 1LL * dd * t % mod) %= mod; } else solve(a, n); if (ans == -1) printf( %d n , ans); else printf( %d %d n , ans, dd); } int main() { init(); return 0; }
|
/****************************************************************************************
*
* File Name: mobile_ddr_mcp.v
*
* Dependencies: mobile_ddr.v, mobile_ddr_parameters.vh
*
* Description: Micron MOBILE DDR SDRAM multi-chip package model
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2008 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
`timescale 1ns / 1ps
module mobile_ddr_mcp (
Clk ,
Clk_n ,
Cke ,
Cs_n ,
Ras_n ,
Cas_n ,
We_n ,
Addr ,
Ba ,
Dq ,
Dqs ,
Dm
);
`include "mobile_ddr_parameters.vh"
// Declare Ports
input Clk ;
input Clk_n ;
input [CS_BITS - 1 : 0] Cke ;
input [CS_BITS - 1 : 0] Cs_n ;
input Ras_n ;
input Cas_n ;
input We_n ;
input [ADDR_BITS - 1 : 0] Addr ;
input [1 : 0] Ba ;
inout [DQ_BITS - 1 : 0] Dq ;
inout [DQS_BITS - 1 : 0] Dqs ;
input [DM_BITS - 1 : 0] Dm ;
wire [RANKS - 1 : 0] Cke_mcp = Cke ;
wire [RANKS - 1 : 0] Cs_n_mcp = Cs_n ;
mobile_ddr rank [RANKS - 1:0] (
.Clk ( Clk ) ,
.Clk_n ( Clk_n ) ,
.Cke ( Cke_mcp ) ,
.Cs_n ( Cs_n_mcp ) ,
.Ras_n ( Ras_n ) ,
.Cas_n ( Cas_n ) ,
.We_n ( We_n ) ,
.Addr ( Addr ) ,
.Ba ( Ba ) ,
.Dq ( Dq ) ,
.Dqs ( Dqs ) ,
.Dm ( Dm )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 110; int n, m, z; int mapp[maxn][maxn][maxn]; bool vis[maxn][maxn][maxn]; string s; int main() { int ans = 0, num; memset(vis, false, sizeof(vis)); memset(mapp, 0, sizeof(mapp)); scanf( %d%d%d , &n, &m, &z); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> s; for (int k = 0; k < z; k++) { if (s[k] == 1 ) mapp[i][j][k + 1] = 1; } } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) for (int k = 1; k <= z; k++) { if (mapp[i][j][k]) { if (mapp[i - 1][j][k] && mapp[i + 1][j][k] && !vis[i][j][k]) { ans++; vis[i][j][k] = true; } if (mapp[i][j - 1][k] && mapp[i][j + 1][k] && !vis[i][j][k]) { ans++; vis[i][j][k] = true; } if (mapp[i][j][k - 1] && mapp[i][j][k + 1] && !vis[i][j][k]) { ans++; vis[i][j][k] = true; } if (mapp[i + 1][j][k] && mapp[i][j - 1][k] && !mapp[i + 1][j - 1][k] && !vis[i][j][k]) { ans++; vis[i][j][k] = true; } if (!mapp[i - 1][j + 1][k] && mapp[i][j + 1][k] && mapp[i - 1][j][k] && !vis[i][j][k]) { ans++; vis[i][j][k] = true; } if (mapp[i + 1][j][k] && mapp[i][j][k - 1] && !mapp[i + 1][j][k - 1] && !vis[i][j][k]) { ans++; vis[i][j][k] = true; } if (!mapp[i - 1][j][k + 1] && mapp[i][j][k + 1] && mapp[i - 1][j][k] && !vis[i][j][k]) { ans++; vis[i][j][k] = true; } if (mapp[i][j + 1][k] && mapp[i][j][k - 1] && !mapp[i][j + 1][k - 1] && !vis[i][j][k]) { ans++; vis[i][j][k] = true; } if (!mapp[i][j - 1][k + 1] && mapp[i][j][k + 1] && mapp[i][j - 1][k] && !vis[i][j][k]) { ans++; vis[i][j][k] = true; } } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; const double pi = acos(-1); const int inf = 1 << 30; const int mod = 1e9 + 9; struct point { int x, flag; bool operator<(const point &a) const { return flag > a.flag; } } s, q; bool check(long long a[], int n, long long h, int x) { priority_queue<int, vector<int>, less<int> > qwe; for (int i = 1; i <= min(n, x); i++) qwe.push(a[i]); int f = 1, pos; while (!qwe.empty()) { pos = qwe.top(); qwe.pop(); if (f) h -= pos; f ^= 1; } if (h >= 0ll) return true; else return false; } int main() { int n; long long h, a[maxn]; scanf( %d %lld , &n, &h); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); int l = 0, r = n, ans = 0; while (l <= r) { int mid = (l + r) >> 1; if (check(a, n, h, mid)) l = mid + 1, ans = mid; else r = mid - 1; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[1005], b[1005]; int main() { int n; string s, ss; cin >> n >> s >> ss; for (int i = 0; i < n; i++) { a[i] = s[i] - 0 ; b[i] = ss[i] - 0 ; } sort(a, a + n); sort(b, b + n); int sum1 = 0, sum2 = 0; for (int i = 0, j = 0; i < n && j < n;) { while (j < n) { if (a[i] <= b[j]) { i++; j++; sum1++; break; } else { j++; } } } int sum = n - sum1; cout << sum << endl; for (int i = 0, j = 0; i < n && j < n;) { while (j < n) { if (a[i] < b[j]) { i++; j++; sum2++; break; } else { j++; } } } cout << sum2; }
|
#include <bits/stdc++.h> using namespace std; using uint = unsigned int; using ll = long long; using ull = unsigned long long; using pii = pair<int, int>; using pll = pair<ll, ll>; template <typename T1, typename T2> ostream &operator<<(ostream &out, const pair<T1, T2> &item) { out << ( << item.first << , << item.second << ) ; return out; } template <typename T> ostream &operator<<(ostream &out, const vector<T> &v) { for (const auto &item : v) out << item << ; return out; } const int NMAX = 200010; struct lol { int lv; int v0; int v1; int v2; int v3; int v4; lol(int v = 0) { lv = v; v0 = v; v1 = v; v2 = -v; v3 = -v; v4 = 0; } friend ostream &operator<<(ostream &out, const lol &a) { return out << ( << a.lv << << a.v0 << << a.v1 << << a.v2 << << a.v3 << << a.v4 << ) ; } }; int m; string s; lol st[NMAX << 2]; int val(char ch) { return (ch == ( ? 1 : -1); } lol combine(const lol &a, const lol &b) { lol ret; ret.lv = a.lv + b.lv; ret.v0 = min(a.v0, a.lv + b.v0); ret.v1 = max(a.v1, a.lv + b.v1); ret.v2 = max(max(a.v2, -a.lv + b.v2), a.v1 - 2 * (a.lv + b.v0)); ret.v3 = max(max(a.v3, -a.lv + b.v3), -2 * a.v0 + (a.lv + b.v1)); ret.v4 = max(max(a.v4, b.v4), max(a.v1 - a.lv + b.v3, a.v2 + a.lv + b.v1)); return ret; } void build(int node, int l, int r) { if (l == r) return void(st[node] = lol(val(s[l]))); int mid = (l + r) / 2; build(2 * node, l, mid); build(2 * node + 1, mid + 1, r); st[node] = combine(st[2 * node], st[2 * node + 1]); } void update(int node, int l, int r, int p) { if (l == r) return void(st[node] = lol(val(s[p]))); int mid = (l + r) / 2; if (p <= mid) update(2 * node, l, mid, p); else update(2 * node + 1, mid + 1, r, p); st[node] = combine(st[2 * node], st[2 * node + 1]); } int main() { ios_base::sync_with_stdio(false); int n, q; cin >> n >> q; m = 2 * n - 2; cin >> s; build(1, 0, m - 1); cout << st[1].v4 << n ; while (q--) { int a, b; cin >> a >> b; --a; --b; swap(s[a], s[b]); update(1, 0, m - 1, a); update(1, 0, m - 1, b); cout << st[1].v4 << n ; } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n; long long a[N], b[N]; int f[N][2]; long long WIN(long long x, long long y) { assert(x <= y); if (y & 1) return !(x & 1); if (x * 2 > y) return x & 1; if (x * 4 > y) return 1; return WIN(x, y / 4); } long long LOSE(long long x, long long y) { assert(x <= y); if (x * 2 > y) return 1; return WIN(x, y / 2); } int main() { scanf( %d , &n); for (int i = (int)(1); i <= (int)(n); i++) scanf( %lld%lld , &a[i], &b[i]); f[n][0] = WIN(a[n], b[n]); f[n][1] = LOSE(a[n], b[n]); for (int i = (int)(n - 1); i >= (int)(1); i--) { if (f[i + 1][0] == 0 && WIN(a[i], b[i])) f[i][0] = 1; if (f[i + 1][0] == 1 && LOSE(a[i], b[i])) f[i][0] = 1; if (f[i + 1][1] == 0 && WIN(a[i], b[i])) f[i][1] = 1; if (f[i + 1][1] == 1 && LOSE(a[i], b[i])) f[i][1] = 1; } cout << f[1][0] << << f[1][1] << endl; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:268435456 ) using namespace std; template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& t) { return in >> t.first >> t.second; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2>& t) { return out << t.first << << t.second << endl; } template <typename T> istream& operator>>(istream& in, vector<T>& t) { for (long long i = 0; i < t.size(); i++) in >> t[i]; return in; } template <typename T> ostream& operator<<(ostream& out, vector<T>& t) { for (long long i = 0; i < t.size(); i++) out << t[i] << ; return out; } long long n, d, k; vector<vector<long long> > g; long long in = 1; void printg(long long x, long long p = -1) { for (long long to : g[x]) { cout << x + 1 << << to + 1 << endl; printg(to, x); } } void con(long long x) { g[x].push_back(in++); if (in >= n) { puts( YES ); printg(0); exit(0); } } void add(long long h) { long long t = 0; for (long long i = 1; i <= h; ++i) { con(t); t = in - 1; } } void build(long long x, long long p, long long h, long long curh = 1) { if (curh >= h) return; for (long long i : g[x]) { build(i, x, h, curh + 1); } while (g[x].size() < k - 1) { con(x); build(in - 1, x, h, curh + 1); } } signed main() { long long rrrr = 1e5; cin >> n >> d >> k; d++; if (n < d) return puts( NO ), 0; if (k == 1) { if (n == d && n == 2) { cout << YES << endl; for (long long i = 0; i < n - 1; ++i) { cout << i + 1 << << i + 2 << endl; } return 0; } else return puts( NO ), 0; } --d; g.resize(n); add(d / 2); add((d + 1) / 2); build(g[0][0], 0, d / 2); build(g[0][1], 0, (d + 1) / 2); for (long long i = 2; i < k; ++i) { if (d / 2 == 0) continue; con(0); build(in - 1, 0, d / 2); } cout << NO << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int maxl = 200005; int T, n, mk, seq[maxl]; char s[maxl]; inline char read() { char ch = getchar(); while (ch != < && ch != > ) ch = getchar(); return ch; } int main() { scanf( %d , &T); while (T--) { scanf( %d , &n); mk = 0; memset(seq, 0, sizeof(seq)); for (register int i = 1; i < n; i++) s[i] = read(); s[0] = > ; s[n] = < ; for (register int i = n; i; i--) if (s[i - 1] == > && s[i] == < ) seq[i] = ++mk; mk = n; for (register int i = 1, j, tmp; i <= n; i++) { if (seq[i]) continue; if (s[i - 1] == > ) seq[i] = mk--; else { for (j = i; s[j] != > && j < n; j++) ; tmp = j; for (; j >= i; j--) seq[j] = mk--; i = tmp; } } for (register int i = 1; i <= n; i++) printf( %d , seq[i]); printf( n ); memset(seq, 0, sizeof(seq)); mk = 0; for (register int i = 1; i <= n; i++) if (s[i - 1] == > && s[i] == < ) seq[i] = ++mk; mk = n; for (register int i = n, j, tmp; i; i--) { if (seq[i]) continue; if (s[i] == < ) seq[i] = mk--; else { for (j = i; s[j - 1] != < && j > 1; j--) ; tmp = j; for (; j <= i; j++) seq[j] = mk--; i = tmp; } } for (register int i = 1; i <= n; i++) printf( %d , seq[i]); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-9; const int inf = 2000000000; const long long infLL = 9000000000000000000; inline bool checkBit(long long n, int i) { return n & (1LL << i); } inline long long setBit(long long n, int i) { return n | (1LL << i); ; } inline long long resetBit(long long n, int i) { return n & (~(1LL << i)); } int dx[] = {0, 0, +1, -1}; int dy[] = {+1, -1, 0, 0}; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool isLeapYear(long long year) { return (year % 400 == 0) || (year % 4 == 0 && year % 100 != 0); } inline void normal(long long &a) { a %= 1000000007; (a < 0) && (a += 1000000007); } inline long long modMul(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); return (a * b) % 1000000007; } inline long long modAdd(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); return (a + b) % 1000000007; } inline long long modSub(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); a -= b; normal(a); return a; } inline long long modPow(long long b, long long p) { long long r = 1; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1; } return r; } inline long long modInverse(long long a) { return modPow(a, 1000000007 - 2); } inline long long modDiv(long long a, long long b) { return modMul(a, modInverse(b)); } inline long long power(long long bs, long long k) { long long x = 1LL, y = bs; if (k == 0) return 1LL; while (k > 0) { if (k % 2) x *= y; y *= y; k /= 2; } return x; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cout.unsetf(ios::floatfield); cout.precision(10); cout.setf(ios::fixed, ios::floatfield); ; long long n; cin >> n; if (n % 2) cout << black ; else { cout << white << n ; cout << 1 2 ; } return 0; }
|
module DMA(
clock , // clock
reset , // Active high, syn reset
req_0 , // Request 0
req_1 , // Request 1
gnt_0 , // Grant 0
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3
;
parameter ST_STOP = 2'b00,ST_FDS = 2'b01,ST_CADR = 2'b10, ST_TFR = 2'b11;
reg [SIZE-1:0] state ;// Seq part of the FSM
wire [SIZE-1:0] next_state ;// combo part of FSM
assign next_state = fsm_function(state, req_0, req_1);
function [SIZE-1:0] fsm_function;
input [SIZE-1:0] state ;
input req_0 ;
input req_1 ;
case(state)
ST_STOP : if (req_0 == 1'b1) begin /* ADMA2 stays in this state in following cases:
(1) After Power on reset or software reset.
(2) All descriptor data transfers are completed
If a new ADMA2 operation is started by writing Command register, go to
ST_FDS state. */
fsm_function = ST_STOP;
end else if (req_1 == 1'b1) begin
fsm_function= ST_FDS;
end else begin
fsm_function = ST_CADR;
end
ST_FDS : if (req_0 == 1'b1) begin /* ADMA2 fetches a descriptor line and set parameters in internal registers.
Next go to ST_CADR state.*/
fsm_function = ST_TFR;
end else begin
fsm_function = ST_STOP;
end
ST_CADR : if (req_1 == 1'b1) begin /* Link operation loads another Descriptor address to ADMA System Address
register. In other operations, ADMA System Address register is
incremented to point next descriptor line. If End=0, go to ST_TFR state.
ADMA2 shall not be stopped at this state even if some errors occur. */
fsm_function = ST_CADR;
end else begin
fsm_function = ST_TFR;
end
ST_TFR : if(req_0 == 1'b1) begin /* Data transfer of one descriptor line is executed between system memory
and SD card. If data transfer continues (End=0) go to ST_FDS state. If data
transfer completes, go to ST_STOP state. */
fsm_function = ST_STOP;
end else begin
fsm_function = ST_TFR;
end
// default : fsm_function = IDLE;
endcase
endfunction
endmodule
|
/* AUTHOR: lz.askey CREATED: 23.07.2021 13:57:23 LANG: C++11 */ #include <assert.h> #include <algorithm> #include <bitset> #include <cmath> #include <cstdio> #include <cstdlib> #include <cstring> #include <deque> #include <iostream> #include <iterator> #include <map> #include <new> #include <queue> #include <set> #include <sstream> #include <stack> #include <string> #include <unordered_map> #include <unordered_set> #include <vector> using namespace std; typedef vector<int> vi; typedef pair<int, int> ii; typedef vector<pair<int, int> > vii; typedef long long ll; #define bit(x, i) (x & (1 << i)) #define in(i, l, r) (l < i && i < r) #define linr(i, l, r) (l <= i && i <= r) #define lin(i, l, r) (l <= i && i < r) #define inr(i, l, r) (l < i && i <= r) #define gi(a) scanf( %d , &a) #define gii(a, b) scanf( %d%d , &a, &b) #define giii(a, b, c) scanf( %d%d%d , &a, &b, &c) #define gs(x) scanf( %s , x) #define clr(a, x) memset(a, x, sizeof(a)) #define c2i(c) (c - 0 ) #define sz(x) ((int)((x).size())) #define all(c) (c).begin(), (c).end() #define mp make_pair #define pb push_back #define eb emplace_back #define ff first #define ss second // for debug #define what_is(x) cerr << Line << __LINE__ << : << #x << is << (x) << endl; #define error(args...) { string _s = #args; replace(_s.begin(), _s.end(), , , ); stringstream _ss(_s); istream_iterator<string> _it(_ss); err(_it, args); } void err(istream_iterator<string> it) { cerr << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << endl; err(++it, args...); } #define REP(i, a, b) for (int i = int(a); i < int(b); i++) const int inf = 0x3f3f3f3f; const int mod = 1e9 + 7; const int fx[4][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; const int fxx[8][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}, {1, 1}, {1, -1}, {-1, 1}, {-1, -1}}; // struct // data int m, k, ans1, ans2; ll a[1010][1010], c[1010]; ll x, y; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> m >> k; REP(i, 0, k) { REP(j, 0, m) { cin >> a[i][j]; c[i] += a[i][j]; } } x = (c[k - 1] - c[0]) / (k - 1); REP(i, 1, k) { if (c[i] - c[0] != x * i) { ans1 = i; y = c[i] - c[0] - x * i; break; } } REP(i, 1, k - 1) { if (i - 1 != ans1 && i != ans1 && i + 1 != ans1) { x = 0; REP(j, 0, m) { x += a[i - 1][j] * a[i - 1][j] + a[i + 1][j] * a[i + 1][j] - 2 * a[i][j] * a[i][j]; } break; } } ll ad = 0, mi = 0; REP(j, 0, m) { ad += a[ans1 - 1][j] * a[ans1 - 1][j] + a[ans1 + 1][j] * a[ans1 + 1][j]; mi += a[ans1][j] * a[ans1][j] * 2; } ad -= x; REP(i, 0, m) { ll temp = mi - a[ans1][i] * a[ans1][i] * 2 + (a[ans1][i] - y) * (a[ans1][i] - y) * 2; if (temp == ad) { ans2 = a[ans1][i] - y; break; } } cout << ans1 << << ans2 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; } v.insert(v.begin(), 0); for (int i = 1; i <= n; i++) { v[i] += v[i - 1]; } int ans = 0; int l, r; cin >> l >> r; if (l > r) swap(l, r); ans = v[r - 1] - v[l - 1]; ans = min(ans, v[n] - ans); cout << ans << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
module some_module (
input wrclk
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
always @(posedge wrclk) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (wrclk)
some_other_state <= 0;
end
endmodule
`define BROKEN
module t1(
input [3:0] i_clks,
input i_clk0,
input i_clk1
);
generate
genvar i;
for (i = 0; i < 2; i = i + 1) begin: a_generate_block
some_module
some_module
(
`ifdef BROKEN
.wrclk (i_clks[3])
`else
.wrclk (i_clk1)
`endif
);
end
endgenerate
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [3:0] the_clks;
logic data_q;
assign the_clks[3] = i_clk1;
assign the_clks[2] = i_clk2;
assign the_clks[1] = i_clk1;
assign the_clks[0] = i_clk0;
always @(posedge i_clk0) begin
data_q <= i_data;
end
t1 t1
(
.i_clks (the_clks),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk1),
.i_clk2 (clk2),
.i_data (data_in)
);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.