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#include <bits/stdc++.h> using namespace std; int s[10000], g[10000]; set<int> v; int main() { int k, n; cin >> k >> n; for (int i = 0; i < n; i++) { cin >> s[i] >> g[i]; } for (int i = 1; i <= 100; i++) { bool f = 1; for (int j = 0; j < n; j++) { if ((s[j] + i - 1) / i != g[j]) { f = 0; break; } } if (f) { v.insert((k + i - 1) / i); } } if (v.size() != 1) { cout << -1; } else { cout << *v.begin(); } }
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#include <bits/stdc++.h> using namespace std; const int maxn = 100 * 1005; bool bad[maxn]; vector<int> blocked; vector<int> g[maxn]; bool seen[maxn]; int deg[maxn]; vector<int> good; int n, m, k; bool can(double mid) { memset(bad, 0, sizeof(bad)); memset(deg, 0, sizeof(deg)); memset(seen, 0, sizeof(seen)); queue<int> q; for (int i = 0; i < n; ++i) deg[i] = ((int)((g[i]).size())); for (int i = 0; i < ((int)((blocked).size())); i++) q.push(blocked[i]); while (!q.empty()) { int u = q.front(); q.pop(); if (seen[u]) continue; seen[u] = 1; for (int i = 0; i < ((int)((g[u]).size())); i++) { int v = g[u][i]; if (bad[v]) continue; deg[v]--; if (double(deg[v] / (1.0 * ((int)((g[v]).size())))) < mid) q.push(v); } } good.clear(); for (int i = 0; i < n; ++i) if (!seen[i]) good.push_back(i); return ((int)((good).size())) > 0; } int main() { int u, v; scanf( %d %d %d , &n, &m, &k); for (int i = 0; i < k; ++i) scanf( %d , &u), --u, blocked.push_back(u); for (int i = 0; i < m; ++i) scanf( %d %d , &u, &v), --u, --v, g[u].push_back(v), g[v].push_back(u); double l = 0, r = 1.0; double ans = 0.0; for (int i = 0; i < 80; ++i) { double mid = (l + r) / 2.0; if (can(mid)) l = mid, ans = mid; else r = mid; } can(ans); assert(((int)((good).size())) <= n - k); assert(((int)((good).size())) != 0); printf( %d n , ((int)((good).size()))); for (int i = 0; i < ((int)((good).size())); i++) printf( %d , good[i] + 1); return 0; }
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`default_nettype none
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief Receiver for RPC network, protocol version 3
Network-side interface is standard RPCv3
Router-side interface is a FIFO.
space_available Asserted by router if it has at least one *packet* worth of buffer space.
packet_start Asserted by transceiver for one clock at start of message.
Asserted before first assertion of data_valid.
data_valid Asserted by transceiver if data should be processed.
Will be asserted for one clock every (OUT_DATA_WIDTH / IN_DATA_WIDTH) clocks.
data One word of message data.
packet_done Asserted by transceiver for one clock at end of message.
Concurrent with last assertion of data_valid.
RESOURCE USAGE (XST A7 rough estimate)
Width FF LUT Slice
16 -> 16 22 7 7
16 -> 32 38 12 14
16 -> 64 70 10 21
16 -> 128 133 5 37
32 -> 16 40 76 43
32 -> 32 37 5 10
32 -> 64 69 4 20
32 -> 128 132 48 24
64 -> 16 72 154 73
64 -> 32 71 89 39
64 -> 64 68 3 20
64 -> 128 131 27 30
128 -> 16 136 104 36
128 -> 32 134 102 49
128 -> 64 132 164 68
128 -> 128 131 30 28
*/
module RPCv3RouterReceiver
#(
parameter OUT_DATA_WIDTH = 32,
parameter IN_DATA_WIDTH = 16
)
(
//Interface clock
input wire clk,
//Network interface, inbound side
input wire rpc_rx_en,
input wire[IN_DATA_WIDTH-1:0] rpc_rx_data,
output wire rpc_rx_ready,
//Router interface, outbound side
input wire rpc_fab_rx_space_available,
output wire rpc_fab_rx_packet_start,
output wire rpc_fab_rx_data_valid,
output wire[OUT_DATA_WIDTH-1:0] rpc_fab_rx_data,
output wire rpc_fab_rx_packet_done
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Create the right receiver depending on link widths
localparam EXPANDING = (IN_DATA_WIDTH < OUT_DATA_WIDTH);
localparam COLLAPSING = (IN_DATA_WIDTH > OUT_DATA_WIDTH);
localparam BUFFERING = (IN_DATA_WIDTH == OUT_DATA_WIDTH);
generate
if(EXPANDING) begin
RPCv3RouterReceiver_expanding #(
.IN_DATA_WIDTH(IN_DATA_WIDTH),
.OUT_DATA_WIDTH(OUT_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(rpc_rx_en),
.rpc_rx_data(rpc_rx_data),
.rpc_rx_ready(rpc_rx_ready),
.rpc_fab_rx_space_available(rpc_fab_rx_space_available),
.rpc_fab_rx_packet_start(rpc_fab_rx_packet_start),
.rpc_fab_rx_data_valid(rpc_fab_rx_data_valid),
.rpc_fab_rx_data(rpc_fab_rx_data),
.rpc_fab_rx_packet_done(rpc_fab_rx_packet_done)
);
end
else if(COLLAPSING) begin
RPCv3RouterReceiver_collapsing #(
.IN_DATA_WIDTH(IN_DATA_WIDTH),
.OUT_DATA_WIDTH(OUT_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(rpc_rx_en),
.rpc_rx_data(rpc_rx_data),
.rpc_rx_ready(rpc_rx_ready),
.rpc_fab_rx_space_available(rpc_fab_rx_space_available),
.rpc_fab_rx_packet_start(rpc_fab_rx_packet_start),
.rpc_fab_rx_data_valid(rpc_fab_rx_data_valid),
.rpc_fab_rx_data(rpc_fab_rx_data),
.rpc_fab_rx_packet_done(rpc_fab_rx_packet_done)
);
end
else begin
RPCv3RouterReceiver_buffering #(
.IN_DATA_WIDTH(IN_DATA_WIDTH),
.OUT_DATA_WIDTH(OUT_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(rpc_rx_en),
.rpc_rx_data(rpc_rx_data),
.rpc_rx_ready(rpc_rx_ready),
.rpc_fab_rx_space_available(rpc_fab_rx_space_available),
.rpc_fab_rx_packet_start(rpc_fab_rx_packet_start),
.rpc_fab_rx_data_valid(rpc_fab_rx_data_valid),
.rpc_fab_rx_data(rpc_fab_rx_data),
.rpc_fab_rx_packet_done(rpc_fab_rx_packet_done)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > seq; const int mod = 1e6; const long long A = 42344; const long long B = 333; int seed = 239; int mrand() { static int now = -1; if (now == -1) now = seed; else now = (A * now + B) % mod; return now; } struct line { long long a, b, c; int id; line() {} line(long long A, long long B, long long C, int i) : a(A), b(B), c(C), id(i) {} }; void run(vector<line> a, int k) { int n = (int)a.size(); if (k >= n) { for (int i = 0; i < n; i++) seq.push_back(make_pair(a[i].id, -1)); sort(seq.begin(), seq.end()); seq.resize(unique(seq.begin(), seq.end()) - seq.begin()); puts( YES ); printf( %d n , (int)seq.size()); for (int i = 0; i < (int)seq.size(); i++) printf( %d %d n , seq[i].first, seq[i].second); exit(0); } if (k == 0) return; vector<line> go; for (int iter = 0; iter < k * k; iter++) { int i = mrand() % n, j = mrand() % (n - 1); if (j >= i) j++; if (a[i].a * a[j].b == a[j].a * a[i].b) continue; go.resize(0); int kol = 0; double lim = max(1.0 * kol, n * (1.0 - 1.0 / (2.0 * k))); for (int q = 0; q < n; q++) if (a[i].a * a[j].b * a[q].c + a[i].b * a[j].c * a[q].a + a[i].c * a[j].a * a[q].b != a[i].c * a[j].b * a[q].a + a[i].b * a[j].a * a[q].c + a[i].a * a[j].c * a[q].b) { go.push_back(a[q]); kol++; if (kol > lim) break; } if (kol > lim) continue; seq.push_back(make_pair(a[i].id, a[j].id)); run(go, k - 1); seq.pop_back(); } } int main() { srand(123654); int n, k; scanf( %d%d , &n, &k); vector<line> l(n); for (int i = 0; i < n; i++) { int a, b, c; scanf( %d%d%d , &a, &b, &c); l[i] = line(a, b, c, i + 1); } run(l, k); puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int N; char s[1005], z[1005]; int solve1() { int ans = 0; int lz, rz, ls, rs; lz = ls = 0; rz = rs = N - 1; while (ls <= rs) { if (z[rz] >= s[rs]) rz--, rs--; else ans++, lz++, rs--; } return ans; } int solve2() { int ans = 0; int lz, rz, ls, rs; lz = ls = 0; rz = rs = N - 1; while (ls <= rs) { if (z[rz] > s[rs]) ans++, rz--, rs--; else lz++, rs--; } return ans; } int main() { scanf( %d%s%s , &N, s, z); sort(s, s + N); sort(z, z + N); printf( %d n%d , solve1(), solve2()); return 0; }
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
Require Import Eqdep List.
Require Omega.
Set Implicit Arguments.
(** A version of [injection] that does some standard simplifications afterward: clear the hypothesis in question, bring the new facts above the double line, and attempt substitution for known variables. *)
Ltac inject H := injection H; clear H; intros; try subst.
(** Try calling tactic function [f] on all hypotheses, keeping the first application that doesn't fail. *)
Ltac appHyps f :=
match goal with
| [ H : _ |- _ ] => f H
end.
(** Succeed iff [x] is in the list [ls], represented with left-associated nested tuples. *)
Ltac inList x ls :=
match ls with
| x => idtac
| (_, x) => idtac
| (?LS, _) => inList x LS
end.
(** Try calling tactic function [f] on every element of tupled list [ls], keeping the first call not to fail. *)
Ltac app f ls :=
match ls with
| (?LS, ?X) => f X || app f LS || fail 1
| _ => f ls
end.
(** Run [f] on every element of [ls], not just the first that doesn't fail. *)
Ltac all f ls :=
match ls with
| (?LS, ?X) => f X; all f LS
| (_, _) => fail 1
| _ => f ls
end.
(** Workhorse tactic to simplify hypotheses for a variety of proofs.
* Argument [invOne] is a tuple-list of predicates for which we always do inversion automatically. *)
Ltac simplHyp invOne :=
(** Helper function to do inversion on certain hypotheses, where [H] is the hypothesis and [F] its head symbol *)
let invert H F :=
(** We only proceed for those predicates in [invOne]. *)
inList F invOne;
(** This case covers an inversion that succeeds immediately, meaning no constructors of [F] applied. *)
(inversion H; fail)
(** Otherwise, we only proceed if inversion eliminates all but one constructor case. *)
|| (inversion H; [idtac]; clear H; try subst) in
match goal with
(** Eliminate all existential hypotheses. *)
| [ H : ex _ |- _ ] => destruct H
(** Find opportunities to take advantage of injectivity of data constructors, for several different arities. *)
| [ H : ?F ?X = ?F ?Y |- ?G ] =>
(** This first branch of the [||] fails the whole attempt iff the arguments of the constructor applications are already easy to prove equal. *)
(assert (X = Y); [ assumption | fail 1 ])
(** If we pass that filter, then we use injection on [H] and do some simplification as in [inject].
* The odd-looking check of the goal form is to avoid cases where [injection] gives a more complex result because of dependent typing, which we aren't equipped to handle here. *)
|| (injection H;
match goal with
| [ |- X = Y -> G ] =>
try clear H; intros; try subst
end)
| [ H : ?F ?X ?U = ?F ?Y ?V |- ?G ] =>
(assert (X = Y); [ assumption
| assert (U = V); [ assumption | fail 1 ] ])
|| (injection H;
match goal with
| [ |- U = V -> X = Y -> G ] =>
try clear H; intros; try subst
end)
(** Consider some different arities of a predicate [F] in a hypothesis that we might want to invert. *)
| [ H : ?F _ |- _ ] => invert H F
| [ H : ?F _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ _ |- _ ] => invert H F
(** Use an (axiom-dependent!) inversion principle for dependent pairs, from the standard library. *)
| [ H : existT _ ?T _ = existT _ ?T _ |- _ ] => generalize (inj_pair2 _ _ _ _ _ H); clear H
(** If we're not ready to use that principle yet, try the standard inversion, which often enables the previous rule. *)
| [ H : existT _ _ _ = existT _ _ _ |- _ ] => inversion H; clear H
(** Similar logic to the cases for constructor injectivity above, but specialized to [Some], since the above cases won't deal with polymorphic constructors. *)
| [ H : Some _ = Some _ |- _ ] => injection H; clear H
end.
(** Find some hypothesis to rewrite with, ensuring that [auto] proves all of the extra subgoals added by [rewrite]. *)
Ltac rewriteHyp :=
match goal with
| [ H : _ |- _ ] => rewrite H by solve [ auto ]
end.
(** Combine [autorewrite] with automatic hypothesis rewrites. *)
Ltac rewriterP := repeat (rewriteHyp; autorewrite with core in *).
Ltac rewriter := autorewrite with core in *; rewriterP.
(** This one is just so darned useful, let's add it as a hint here. *)
Hint Rewrite app_ass.
(** Devious marker predicate to use for encoding state within proof goals *)
Definition done (T : Type) (x : T) := True.
(** Try a new instantiation of a universally quantified fact, proved by [e].
* [trace] is an accumulator recording which instantiations we choose. *)
Ltac inster e trace :=
(** Does [e] have any quantifiers left? *)
match type of e with
| forall x : _, _ =>
(** Yes, so let's pick the first context variable of the right type. *)
match goal with
| [ H : _ |- _ ] =>
inster (e H) (trace, H)
| _ => fail 2
end
| _ =>
(** No more quantifiers, so now we check if the trace we computed was already used. *)
match trace with
| (_, _) =>
(** We only reach this case if the trace is nonempty, ensuring that [inster] fails if no progress can be made. *)
match goal with
| [ H : done (trace, _) |- _ ] =>
(** Uh oh, found a record of this trace in the context! Abort to backtrack to try another trace. *)
fail 1
| _ =>
(** What is the type of the proof [e] now? *)
let T := type of e in
match type of T with
| Prop =>
(** [e] should be thought of as a proof, so let's add it to the context, and also add a new marker hypothesis recording our choice of trace. *)
generalize e; intro;
assert (done (trace, tt)) by constructor
| _ =>
(** [e] is something beside a proof. Better make sure no element of our current trace was generated by a previous call to [inster], or we might get stuck in an infinite loop! (We store previous [inster] terms in second positions of tuples used as arguments to [done] in hypotheses. Proofs instantiated by [inster] merely use [tt] in such positions.) *)
all ltac:(fun X =>
match goal with
| [ H : done (_, X) |- _ ] => fail 1
| _ => idtac
end) trace;
(** Pick a new name for our new instantiation. *)
let i := fresh "i" in (pose (i := e);
assert (done (trace, i)) by constructor)
end
end
end
end.
(** After a round of application with the above, we will have a lot of junk [done] markers to clean up; hence this tactic. *)
Ltac un_done :=
repeat match goal with
| [ H : done _ |- _ ] => clear H
end.
Require Import JMeq.
(** A more parameterized version of the famous [crush]. Extra arguments are:
* - A tuple-list of lemmas we try [inster]-ing
* - A tuple-list of predicates we try inversion for *)
Ltac crush' lemmas invOne :=
(** A useful combination of standard automation *)
let sintuition := simpl in *; intuition; try subst;
repeat (simplHyp invOne; intuition; try subst); try congruence in
(** A fancier version of [rewriter] from above, which uses [crush'] to discharge side conditions *)
let rewriter := autorewrite with core in *;
repeat (match goal with
| [ H : ?P |- _ ] =>
match P with
| context[JMeq] => fail 1 (** JMeq is too fancy to deal with here. *)
| _ => rewrite H by crush' lemmas invOne
end
end; autorewrite with core in *) in
(** Now the main sequence of heuristics: *)
(sintuition; rewriter;
match lemmas with
| false => idtac (** No lemmas? Nothing to do here *)
| _ =>
(** Try a loop of instantiating lemmas... *)
repeat ((app ltac:(fun L => inster L L) lemmas
(** ...or instantiating hypotheses... *)
|| appHyps ltac:(fun L => inster L L));
(** ...and then simplifying hypotheses. *)
repeat (simplHyp invOne; intuition)); un_done
end;
sintuition; rewriter; sintuition;
(** End with a last attempt to prove an arithmetic fact with [omega], or prove any sort of fact in a context that is contradictory by reasoning that [omega] can do. *)
try omega; try (elimtype False; omega)).
(** [crush] instantiates [crush'] with the simplest possible parameters. *)
Ltac crush := crush' false fail.
(** * Wrap Program's [dependent destruction] in a slightly more pleasant form *)
Require Import Program.Equality.
(** Run [dependent destruction] on [E] and look for opportunities to simplify the result.
The weird introduction of [x] helps get around limitations of [dependent destruction], in terms of which sorts of arguments it will accept (e.g., variables bound to hypotheses within Ltac [match]es). *)
Ltac dep_destruct E :=
let x := fresh "x" in
remember E as x; simpl in x; dependent destruction x;
try match goal with
| [ H : _ = E |- _ ] => rewrite <- H in *; clear H
end.
(** Nuke all hypotheses that we can get away with, without invalidating the goal statement. *)
Ltac clear_all :=
repeat match goal with
| [ H : _ |- _ ] => clear H
end.
(** Instantiate a quantifier in a hypothesis [H] with value [v], or, if [v] doesn't have the right type, with a new unification variable.
* Also prove the lefthand sides of any implications that this exposes, simplifying [H] to leave out those implications. *)
Ltac guess v H :=
repeat match type of H with
| forall x : ?T, _ =>
match type of T with
| Prop =>
(let H' := fresh "H'" in
assert (H' : T); [
solve [ eauto 6 ]
| specialize (H H'); clear H' ])
|| fail 1
| _ =>
specialize (H v)
|| let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end
end.
(** Version of [guess] that leaves the original [H] intact *)
Ltac guessKeep v H :=
let H' := fresh "H'" in
generalize H; intro H'; guess v H'.
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t, s, q; cin >> t >> s >> q; int ans = 0; int tot = s; while (tot < t) { tot *= q; ++ans; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, k; int nums[1005]; cin >> t; while (t--) { cin >> n >> k; for (int i = 0; i < n; i++) cin >> nums[i]; sort(nums, nums + n); int sum = 0; for (int i = 1; i < n; i++) sum += (k - nums[i]) / nums[0]; cout << sum << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, d; cin >> n >> d; int ld = 0, rd = n * (n - 1) / 2; for (int i = 1, cd = 0; i <= n; ++i) { if (!(i & (i - 1))) ++cd; ld += cd - 1; } if (!(ld <= d && d <= rd)) { cout << NO << endl; continue; } vector<int> par(n); iota(par.begin(), par.end(), -1); vector<int> cnt(n, 1); cnt[n - 1] = 0; vector<int> bad(n); vector<int> dep(n); iota(dep.begin(), dep.end(), 0); int cur = n * (n - 1) / 2; while (cur > d) { int v = -1; for (int i = 0; i < n; ++i) { if (!bad[i] && cnt[i] == 0 && (v == -1 || dep[v] > dep[i])) { v = i; } } assert(v != -1); int p = -1; for (int i = 0; i < n; ++i) { if (cnt[i] < 2 && dep[i] < dep[v] - 1 && (p == -1 || dep[p] < dep[i])) { p = i; } } if (p == -1) { bad[v] = 1; continue; } assert(dep[v] - dep[p] == 2); --cnt[par[v]]; --dep[v]; ++cnt[p]; par[v] = p; --cur; } cout << YES << endl; for (int i = 1; i < n; ++i) cout << par[i] + 1 << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, max; vector<int> a[100000]; bool visited[100000] = {0}; char col[100000] = { Z }; void f(int x) { queue<int> q; q.push(x); visited[x] = 1; char temp = A ; col[x] = temp; while (!q.empty()) { int p = q.front(); q.pop(); temp = col[p]; if (temp == A ) temp = B ; else temp = A ; for (int i = 0; i < a[p].size(); i++) { if (visited[a[p][i]] == false) { q.push(a[p][i]); visited[a[p][i]] = true; col[a[p][i]] = temp; } else if (col[a[p][i]] != temp) { puts( -1 ); exit(0); } } } } int main() { cin >> n >> m; int x, y; for (int i = 0; i < m; i++) { cin >> x >> y; x--; y--; a[x].push_back(y); a[y].push_back(x); } f(x); for (int i = 0; i < 100000; i++) { if (a[i].size() && visited[i] == 0) f(i); } int c1 = 0; for (int i = 0; i < 100000; i++) if (col[i] == B ) c1++; cout << c1 << n ; for (int i = 0; i < 100000; i++) if (col[i] == B ) cout << i + 1 << ; cout << n ; c1 = 0; for (int i = 0; i < 100000; i++) if (col[i] == A ) c1++; cout << c1 << n ; for (int i = 0; i < 100000; i++) if (col[i] == A ) cout << i + 1 << ; cout << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int x1, y1, z, x, y; cin >> x1 >> y1 >> z; x = x1 - y1 + z; y = x1 - y1 - z; if (x > 0 && y > 0) cout << + << n ; else if (x < 0 && y < 0) cout << - << n ; else if (x == 0 && y == 0) cout << 0 << n ; else cout << ? << n ; }
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#include <bits/stdc++.h> using namespace std; long long st; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m, k; cin >> n >> m >> k; if (k < n) { cout << (long long)(k + 1) << << 1; return 0; } k -= (long long)(n - 1); long long row = k / (long long)(m - 1), col; if ((long long)row * (long long)(m - 1) != (long long)k) row++; if ((long long)(row % (long long)2) == (long long)1) { st = (long long)(row - (long long)1) * (long long)(m - (long long)1); st++; col = k - st + (long long)2; } else { st = (long long)row * (long long)(m - 1); col = (long long)2 + st - k; } cout << (long long)(n - row + 1) << << col; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_SYMBOL_V
`define SKY130_FD_SC_HD__NAND4B_SYMBOL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
input D ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_SYMBOL_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
(* X_CORE_INFO = "xlconcat,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlconcat_0_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=2,IN1_WIDTH=14,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_W\
IDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=16,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [1 : 0] In0;
input wire [13 : 0] In1;
output wire [15 : 0] dout;
xlconcat #(
.IN0_WIDTH(2),
.IN1_WIDTH(14),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(16),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBN_PP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFBBN_PP_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBN_PP_SYMBOL_V
|
/*
This file was generated automatically by the Mojo IDE version B1.3.6.
Do not edit this file directly. Instead edit the original Lucid source.
This is a temporary file and any changes made to it will be destroyed.
*/
module dvi_encoder_13 (
input pclk,
input pclkx2,
input pclkx10,
input strobe,
input rst,
input [7:0] red,
input [7:0] green,
input [7:0] blue,
input hsync,
input vsync,
input de,
output reg [3:0] tmds,
output reg [3:0] tmdsb
);
reg M_toggle_d, M_toggle_q = 1'h0;
wire [1-1:0] M_clkser_iob_out;
reg [5-1:0] M_clkser_data;
serdes_n_to_1_22 clkser (
.ioclk(pclkx10),
.strobe(strobe),
.gclk(pclkx2),
.rst(rst),
.data(M_clkser_data),
.iob_out(M_clkser_iob_out)
);
wire [1-1:0] M_clkbuf_O;
wire [1-1:0] M_clkbuf_OB;
OBUFDS clkbuf (
.I(M_clkser_iob_out),
.O(M_clkbuf_O),
.OB(M_clkbuf_OB)
);
wire [10-1:0] M_enc_blue_data_out;
reg [8-1:0] M_enc_blue_data_in;
reg [1-1:0] M_enc_blue_c0;
reg [1-1:0] M_enc_blue_c1;
reg [1-1:0] M_enc_blue_de;
tmds_encoder_24 enc_blue (
.clk(pclk),
.rst(rst),
.data_in(M_enc_blue_data_in),
.c0(M_enc_blue_c0),
.c1(M_enc_blue_c1),
.de(M_enc_blue_de),
.data_out(M_enc_blue_data_out)
);
wire [10-1:0] M_enc_green_data_out;
reg [8-1:0] M_enc_green_data_in;
reg [1-1:0] M_enc_green_c0;
reg [1-1:0] M_enc_green_c1;
reg [1-1:0] M_enc_green_de;
tmds_encoder_24 enc_green (
.clk(pclk),
.rst(rst),
.data_in(M_enc_green_data_in),
.c0(M_enc_green_c0),
.c1(M_enc_green_c1),
.de(M_enc_green_de),
.data_out(M_enc_green_data_out)
);
wire [10-1:0] M_enc_red_data_out;
reg [8-1:0] M_enc_red_data_in;
reg [1-1:0] M_enc_red_c0;
reg [1-1:0] M_enc_red_c1;
reg [1-1:0] M_enc_red_de;
tmds_encoder_24 enc_red (
.clk(pclk),
.rst(rst),
.data_in(M_enc_red_data_in),
.c0(M_enc_red_c0),
.c1(M_enc_red_c1),
.de(M_enc_red_de),
.data_out(M_enc_red_data_out)
);
wire [15-1:0] M_fifo_data_out;
reg [30-1:0] M_fifo_data_in;
fifo_2x_reducer_27 fifo (
.rst(rst),
.clk(pclk),
.clkx2(pclkx2),
.data_in(M_fifo_data_in),
.data_out(M_fifo_data_out)
);
wire [1-1:0] M_redser_iob_out;
reg [5-1:0] M_redser_data;
serdes_n_to_1_22 redser (
.ioclk(pclkx10),
.strobe(strobe),
.gclk(pclkx2),
.rst(rst),
.data(M_redser_data),
.iob_out(M_redser_iob_out)
);
wire [1-1:0] M_greenser_iob_out;
reg [5-1:0] M_greenser_data;
serdes_n_to_1_22 greenser (
.ioclk(pclkx10),
.strobe(strobe),
.gclk(pclkx2),
.rst(rst),
.data(M_greenser_data),
.iob_out(M_greenser_iob_out)
);
wire [1-1:0] M_blueser_iob_out;
reg [5-1:0] M_blueser_data;
serdes_n_to_1_22 blueser (
.ioclk(pclkx10),
.strobe(strobe),
.gclk(pclkx2),
.rst(rst),
.data(M_blueser_data),
.iob_out(M_blueser_iob_out)
);
wire [1-1:0] M_redbuf_O;
wire [1-1:0] M_redbuf_OB;
OBUFDS redbuf (
.I(M_redser_iob_out),
.O(M_redbuf_O),
.OB(M_redbuf_OB)
);
wire [1-1:0] M_greenbuf_O;
wire [1-1:0] M_greenbuf_OB;
OBUFDS greenbuf (
.I(M_greenser_iob_out),
.O(M_greenbuf_O),
.OB(M_greenbuf_OB)
);
wire [1-1:0] M_bluebuf_O;
wire [1-1:0] M_bluebuf_OB;
OBUFDS bluebuf (
.I(M_blueser_iob_out),
.O(M_bluebuf_O),
.OB(M_bluebuf_OB)
);
always @* begin
M_toggle_d = M_toggle_q;
M_toggle_d = ~M_toggle_q;
M_clkser_data = {3'h5{~M_toggle_q}};
tmds[3+0-:1] = M_clkbuf_O;
tmdsb[3+0-:1] = M_clkbuf_OB;
M_enc_red_data_in = red;
M_enc_green_data_in = green;
M_enc_blue_data_in = blue;
M_enc_red_c0 = hsync;
M_enc_red_c1 = vsync;
M_enc_red_de = de;
M_enc_green_c0 = hsync;
M_enc_green_c1 = vsync;
M_enc_green_de = de;
M_enc_blue_c0 = hsync;
M_enc_blue_c1 = vsync;
M_enc_blue_de = de;
M_fifo_data_in = {M_enc_red_data_out[5+4-:5], M_enc_green_data_out[5+4-:5], M_enc_blue_data_out[5+4-:5], M_enc_red_data_out[0+4-:5], M_enc_green_data_out[0+4-:5], M_enc_blue_data_out[0+4-:5]};
M_redser_data = M_fifo_data_out[10+4-:5];
M_greenser_data = M_fifo_data_out[5+4-:5];
M_blueser_data = M_fifo_data_out[0+4-:5];
tmds[0+0-:1] = M_bluebuf_O;
tmdsb[0+0-:1] = M_bluebuf_OB;
tmds[1+0-:1] = M_greenbuf_O;
tmdsb[1+0-:1] = M_greenbuf_OB;
tmds[2+0-:1] = M_redbuf_O;
tmdsb[2+0-:1] = M_redbuf_OB;
end
always @(posedge pclkx2) begin
if (rst == 1'b1) begin
M_toggle_q <= 1'h0;
end else begin
M_toggle_q <= M_toggle_d;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_register.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/08/16 12:33:27 mohor
// Parameter ResetValue changed to capital letters.
//
// Revision 1.4 2002/02/26 16:18:08 mohor
// Reset values are passed to registers through parameters
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
//
//
//
//
//
//
`include "timescale.v"
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input SyncReset;
output [WIDTH-1:0] DataOut;
reg [WIDTH-1:0] DataOut;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
DataOut<= RESET_VALUE;
else
if(SyncReset)
DataOut<= RESET_VALUE;
else
if(Write) // write
DataOut<= DataIn;
end
endmodule // Register
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND4B_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4b (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CLKINVLP_BLACKBOX_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinvlp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> void pv(T a, T b) { for (T i = a; i != b; ++i) cout << *i << ; cout << endl; } template <typename T> void chmin(T &t, const T &f) { if (t > f) t = f; } template <typename T> void chmax(T &t, const T &f) { if (t < f) t = f; } int in() { int x; scanf( %d , &x); return x; } const long long MO = 1000000007; namespace SA { int n; char t[300010]; int ki[300010], ik[300010], is[300010], hh; bool cmp(const int &a, const int &b) { return (a == b) ? 0 : (ik[a] != ik[b]) ? (ik[a] < ik[b]) : (ik[a + hh] < ik[b + hh]); } void makeSA() { n = strlen(t); int i; for (i = 0; i <= n; ++i) ik[ki[i] = i] = t[i]; is[0] = is[n] = hh = 0; sort(ki, ki + n + 1, cmp); for (hh = 1; is[n] != n; hh <<= 1) { sort(ki, ki + n + 1, cmp); for (i = 0; i < n; ++i) is[i + 1] = is[i] + (cmp(ki[i], ki[i + 1]) ? 1 : 0); for (i = 0; i <= n; ++i) ik[ki[i]] = is[i]; } } int lcp[300010]; void makeHA() { int h = 0, i, j; for (i = 0; i < n; ++i) { for (j = ki[ik[i] - 1]; t[j + h] == t[i + h]; ++h) ; lcp[ik[i] - 1] = h; if (h) --h; } } } // namespace SA int LA, LB, LC; long long ans[300010]; int eventsLen; pair<int, int> events[300010]; int uf[300010]; long long cnt[300010][3]; long long prodSum; int root(int u) { return (uf[u] < 0) ? u : (uf[u] = root(uf[u])); } void conn(int u, int v) { u = root(u); v = root(v); if (u == v) return; if (uf[u] > uf[v]) swap(u, v); uf[u] += uf[v]; uf[v] = u; prodSum -= cnt[u][0] * cnt[u][1] * cnt[u][2]; prodSum -= cnt[v][0] * cnt[v][1] * cnt[v][2]; cnt[u][0] += cnt[v][0]; cnt[u][1] += cnt[v][1]; cnt[u][2] += cnt[v][2]; prodSum += cnt[u][0] * cnt[u][1] * cnt[u][2]; } int main() { using namespace SA; for (; ~scanf( %s , t);) { LA = strlen(t); t[LA] = 0 ; scanf( %s , t + LA + 1); LB = strlen(t + LA + 1); t[LA + 1 + LB] = 1 ; scanf( %s , t + LA + 1 + LB + 1); LC = strlen(t + LA + 1 + LB + 1); t[LA + 1 + LB + 1 + LC] = 2 ; t[LA + 1 + LB + 1 + LC + 1] = 0; makeSA(); makeHA(); eventsLen = 0; for (int i = 0; i < n; ++i) { events[eventsLen++] = make_pair(lcp[i], i); } sort(events, events + eventsLen); reverse(events, events + eventsLen); fill(uf, uf + n + 1, -1); for (int i = 0; i <= n; ++i) { cnt[i][0] = 0; cnt[i][1] = 0; cnt[i][2] = 0; if (0 <= ki[i] && ki[i] < LA) { cnt[i][0] = 1; } else if (LA + 1 <= ki[i] && ki[i] < LA + 1 + LB) { cnt[i][1] = 1; } else if (LA + 1 + LB + 1 <= ki[i] && ki[i] < LA + 1 + LB + 1 + LC) { cnt[i][2] = 1; } } prodSum = 0; for (int h = 0, k = n; k >= 0; --k) { for (; h < eventsLen && events[h].first == k; ++h) { const int i = events[h].second; conn(i, i + 1); } ans[k] = prodSum; } const int ansLen = min({LA, LB, LC}); for (int k = 1; k <= ansLen; ++k) { if (k > 1) printf( ); printf( %d , (int)(ans[k] % MO)); } puts( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, first, second, third, fourth; cin >> a >> b >> c; first = a + b + c; second = 2 * (a + b); third = 2 * (b + c); fourth = 2 * (a + c); cout << min(first, min(second, min(third, fourth))); }
|
#include <bits/stdc++.h> const int N = 50; std::vector<int> *graph[N][N], *igraph[N][N]; std::vector<int> expand(std::vector<int> *graph[N][N], std::vector<int> queue, int max) { for (int t = 0; t + 1 < (int)queue.size() && (int)queue.size() <= max; ++t) { int u = queue[t]; int v = queue[t + 1]; if (graph[u][v] == NULL) { return std::vector<int>(); } else { for (int w : *graph[u][v]) { queue.push_back(w); } } } return queue; } int main() { int n, m; scanf( %d%d , &n, &m); memset(graph, 0, sizeof(graph)); for (int i = 0; i < m; ++i) { int x, y, k; scanf( %d%d%d , &x, &y, &k); x--; y--; std::vector<int> seq; while (k--) { int v; scanf( %d , &v); seq.push_back(--v); } graph[x][y] = new std::vector<int>(seq); std::reverse(seq.begin(), seq.end()); igraph[y][x] = new std::vector<int>(seq); } bool found = false; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (graph[i][j] != NULL) { std::vector<int> seq = *graph[i][j]; for (int k = 1; k < (int)seq.size(); ++k) { if (seq[k - 1] == i && seq[k] == j) { std::vector<int> fw = expand( graph, std::vector<int>(seq.begin() + k, seq.end()), 2 * n); std::vector<int> iseq(seq.begin(), seq.begin() + k); std::reverse(iseq.begin(), iseq.end()); std::vector<int> bw = expand(igraph, iseq, 2 * n); if (!fw.empty() && !bw.empty()) { std::reverse(bw.begin(), bw.end()); for (int t : fw) { bw.push_back(t); } if ((int)bw.size() <= 2 * n && !found) { found = true; printf( %d n , (int)bw.size()); for (int i = 0; i < (int)bw.size(); ++i) { printf( %d%c , bw[i] + 1, n [i == (int)bw.size() - 1]); } } } } } } } } if (!found) { puts( 0 ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_4_V
`define SKY130_FD_SC_HD__SDFSTP_4_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_4_V
|
#include <bits/stdc++.h> int main() { int n, i, c = 0; char s[500]; scanf( %d %s , &n, s); for (i = 0; i < n - 1; i++) { if (((s[i] == R ) && (s[i + 1] == U )) || ((s[i] == U ) && (s[i + 1] == R ))) { c++; i++; } } printf( %d n , n - c); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_2_V
`define SKY130_FD_SC_MS__NAND3B_2_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3b_2 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3b_2 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_2_V
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/BUFR.v,v 1.6 2011/08/09 22:45:10 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.72)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Regional Clock Buffer
// /___/ /\ Filename : BUFR.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 04/04/2005 - Add SIM_DEVICE paramter to support rainier. CE pin has 4 clock
// latency for Virtex 4 and none for Rainier
// 07/25/05 - Updated names to Virtex5
// 08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch.
// 05/23/06 - Add count =0 and first_rise=1 when CE = 0 (CR232206).
// 07/19/06 - Add wire declaration for undeclared wire signals.
// 04/01/09 - CR 517236 -- Added VIRTEX6 support
// 11/13/09 - Added VIRTEX7
// 01/20/10 - Change VIRTEX7 to FUJI (CR545223)
// 02/23/10 - Use assign for o_out (CR543271)
// 06/09/10 - Change FUJI to 7_SERIES
// 08/18/10 - Change 7_SERIES to 7SERIES (CR571653)
// 08/09/11 - Add 7SERIES to ce_en logic (CR620544)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/15/12 - Match with hardware (CR 650440)
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFR (O, CE, CLR, I);
output O;
input CE;
input CLR;
input I;
parameter BUFR_DIVIDE = "BYPASS";
parameter SIM_DEVICE = "VIRTEX4";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
integer count, period_toggle, half_period_toggle;
reg first_rise, half_period_done;
reg notifier;
reg o_out_divide = 0;
wire o_out;
reg ce_enable1, ce_enable2, ce_enable3, ce_enable4;
tri0 GSR = glbl.GSR;
wire i_in, ce_in, clr_in, gsr_in, ce_en, i_ce;
buf buf_i (i_in, I);
buf buf_ce (ce_in, CE);
buf buf_clr (clr_in, CLR);
buf buf_gsr (gsr_in, GSR);
buf buf_o (O, o_out);
initial begin
case (BUFR_DIVIDE)
"BYPASS" : period_toggle = 0;
"1" : begin
period_toggle = 1;
half_period_toggle = 1;
end
"2" : begin
period_toggle = 2;
half_period_toggle = 2;
end
"3" : begin
period_toggle = 4;
half_period_toggle = 2;
end
"4" : begin
period_toggle = 4;
half_period_toggle = 4;
end
"5" : begin
period_toggle = 6;
half_period_toggle = 4;
end
"6" : begin
period_toggle = 6;
half_period_toggle = 6;
end
"7" : begin
period_toggle = 8;
half_period_toggle = 6;
end
"8" : begin
period_toggle = 8;
half_period_toggle = 8;
end
default : begin
$display("Attribute Syntax Error : The attribute BUFR_DIVIDE on BUFR instance %m is set to %s. Legal values for this attribute are BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8.", BUFR_DIVIDE);
$finish;
end
endcase // case(BUFR_DIVIDE)
case (SIM_DEVICE)
"VIRTEX4" : ;
"VIRTEX5" : ;
"VIRTEX6" : ;
"7SERIES" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on BUFR instance %m is set to %s. Legal values for this attribute are VIRTEX4 or VIRTEX5 or VIRTEX6 or 7SERIES.", SIM_DEVICE);
$finish;
end
endcase
end // initial begin
always @(gsr_in or clr_in)
if (gsr_in == 1'b1 || clr_in == 1'b1) begin
assign o_out_divide = 1'b0;
assign count = 0;
assign first_rise = 1'b1;
assign half_period_done = 1'b0;
if (gsr_in == 1'b1) begin
assign ce_enable1 = 1'b0;
assign ce_enable2 = 1'b0;
assign ce_enable3 = 1'b0;
assign ce_enable4 = 1'b0;
end
end
else if (gsr_in == 1'b0 || clr_in == 1'b0) begin
deassign o_out_divide;
deassign count;
deassign first_rise;
deassign half_period_done;
if (gsr_in == 1'b0) begin
deassign ce_enable1;
deassign ce_enable2;
deassign ce_enable3;
deassign ce_enable4;
end
end
always @(negedge i_in)
begin
ce_enable1 <= ce_in;
ce_enable2 <= ce_enable1;
ce_enable3 <= ce_enable2;
ce_enable4 <= ce_enable3;
end
assign ce_en = ((SIM_DEVICE == "VIRTEX5") || (SIM_DEVICE == "VIRTEX6") || (SIM_DEVICE == "7SERIES")) ? ce_in : ce_enable4;
assign i_ce = i_in & ce_en;
generate
case (SIM_DEVICE)
"VIRTEX4" : begin
always @(i_in or ce_en)
if (ce_en == 1'b1) begin
if (i_in == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0)
count = count + 1;
end // if (ce_in == 1'b1)
else begin
count = 0;
first_rise = 1;
end
end
"VIRTEX5","VIRTEX6","7SERIES" : begin
always @(i_ce)
begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0) begin
count = count + 1;
end // if (ce_in == 1'b1)
end
end
endcase
endgenerate
assign o_out = (period_toggle == 0) ? i_in : o_out_divide;
//*** Timing Checks Start here
always @(notifier) begin
o_out_divide <= 1'bx;
end
`ifdef XIL_TIMING
specify
(CLR => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge I, 0:0:0, 0, notifier);
$width (negedge I, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // BUFR
`endcelldefine
|
/*
* Copyright (c) 2011, Stefan Kristiansson <>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module bufram #(
parameter ADDR_WIDTH = 3
)
(
input clk_a,
input [ADDR_WIDTH-1:0] addr_a,
input [3:0] we_a,
input [31:0] di_a,
output [31:0] do_a,
input clk_b,
input [ADDR_WIDTH-1:0] addr_b,
input [3:0] we_b,
input [31:0] di_b,
output [31:0] do_b
);
dpram_altera #(
.ADDR_WIDTH(ADDR_WIDTH)
) dpram_altera (
.clk_a (clk_a),
.addr_a (addr_a),
.we_a (we_a),
.di_a (di_a),
.do_a (do_a),
.clk_b (clk_b),
.addr_b (addr_b),
.we_b (we_b),
.di_b (di_b),
.do_b (do_b)
);
endmodule
|
// 4 3 2 1 0
// L W S E N
// sram: x: 00 y: 10
// scheduler: x: 00 y: 01
module mapreduce(clk, rst, scheduler_wen);
parameter WIDTH=36;
parameter DEPTH=8;
parameter ADDR=4;
parameter lhsCount=5;
parameter rhsCount=5;
input clk;
input rst;
// Start the scheduler from the outside.
// Since the scheduler is the trigger of the whole system, thus start the whole system.
input scheduler_wen;
// For version 0.0, the communication is only:
// from scheduler to sram
// from sram to scheduler
// from scheduler to mapper
// from mapper to reducer
wire [WIDTH-1:0] link_sramtoscheduler;
wire [WIDTH-1:0] link_schedulertosram;
wire [WIDTH-1:0] link_schedulertonode;
wire [WIDTH-1:0] link_nodetoreducer;
// Define the locations of each submodule
reg [1:0] sram_locationx;
reg [1:0] sram_locationy;
reg [1:0] scheduler_locationx;
reg [1:0] scheduler_locationy;
reg [1:0] node_locationx;
reg [1:0] node_locationy;
reg [1:0] reducer_locationx;
reg [1:0] reducer_locationy;
wire [4:0] scheduler_valid_in_0;
reg [4:0] scheduler_valid_in_1;
reg [4:0] scheduler_valid_in_2;
// Modulate the timing
// Delay the input to scheduler_valide_in_L.
assign scheduler_valid_in_0[4] = scheduler_router0.sch0.enableout;
always@(posedge clk or negedge rst)
if(!rst)
scheduler_valid_in_1 <= 5'd0;
else
scheduler_valid_in_1 <= scheduler_valid_in_0;
always@(posedge clk or negedge rst)
if(!rst)
scheduler_valid_in_2 <= 5'd0;
else
scheduler_valid_in_2 <= scheduler_valid_in_1;
wire scheduler_valid_in_N;
wire scheduler_valid_in_S;
wire scheduler_valid_in_W;
wire scheduler_valid_in_E;
assign scheduler_router0.Data_in_valid[4] = scheduler_valid_in_1[4];
// Valid_in Definitions
wire sram_valid_in_N;
wire sram_valid_in_S;
wire sram_valid_in_W;
wire sram_valid_in_E;
wire node_valid_in_N;
wire node_valid_in_S;
wire node_valid_in_W;
wire node_valid_in_E;
// Valid_out Definitions
wire scheduler_valid_out_N;
wire scheduler_valid_out_S;
wire scheduler_valid_out_W;
wire scheduler_valid_out_E;
wire sram_valid_out_N;
wire sram_valid_out_S;
wire sram_valid_out_W;
wire sram_valid_out_E;
wire node_valid_out_N;
wire node_valid_out_S;
wire node_valid_out_W;
wire node_valid_out_E;
// Cross-router valid signal connection.
assign scheduler_valid_in_W = sram_valid_out_E;
assign scheduler_valid_in_S = 0;
assign scheduler_valid_in_E = 0;
assign scheduler_valid_in_N = 0;
assign sram_valid_in_W = 0;
assign sram_valid_in_S = 0;
assign sram_valid_in_E = scheduler_valid_out_W;
assign sram_valid_in_N = 0;
assign node_valid_in_W = scheduler_valid_out_E;
assign node_valid_in_S = 0;
assign node_valid_in_E = 0;
assign node_valid_in_N = 0;
// PE locations.
always@*
if(!rst) begin
sram_locationx = 2'b00;
sram_locationy = 2'b01;
scheduler_locationx = 2'b01;
scheduler_locationy = 2'b01;
node_locationx = 2'b10;
node_locationy = 2'b01;
end
else begin
sram_locationx = 2'b00;
sram_locationy = 2'b01;
scheduler_locationx = 2'b01;
scheduler_locationy = 2'b01;
node_locationx = 2'b10;
node_locationy = 2'b01;
end
// Instantiations
sram_router sram_router0(
.clk(clk),
.rst(rst),
.Data_in_N(),
.Data_in_S(),
.Data_in_W(),
.Data_in_E(link_schedulertosram),
.Data_in_ready_N(),
.Data_in_ready_S(),
.Data_in_ready_W(),
.Data_in_ready_E(),
.Data_out_N(),
.Data_out_S(),
.Data_out_W(),
.Data_out_E(link_sramtoscheduler),
.Data_out_ready_N(),
.Data_out_ready_S(),
.Data_out_ready_W(),
.Data_out_ready_E(),
.Data_in_valid_N(sram_valid_in_N),
.Data_in_valid_S(sram_valid_in_S),
.Data_in_valid_W(sram_valid_in_W),
.Data_in_valid_E(sram_valid_in_E),
.Data_out_valid_N(sram_valid_out_N),
.Data_out_valid_S(sram_valid_out_S),
.Data_out_valid_W(sram_valid_out_W),
.Data_out_valid_E(sram_valid_out_E),
.noc_locationx(sram_locationx),
.noc_locationy(sram_locationy)
);
scheduler_router scheduler_router0(
.clk(clk),
.rst(rst),
.wen(scheduler_wen),
.Data_in_N(),
.Data_in_S(),
.Data_in_W(link_sramtoscheduler),
.Data_in_E(),
.Data_in_ready_N(),
.Data_in_ready_S(),
.Data_in_ready_W(),
.Data_in_ready_E(),
.Data_out_N(),
.Data_out_S(),
.Data_out_W(link_schedulertosram),
.Data_out_E(link_schedulertonode),
.Data_out_ready_N(),
.Data_out_ready_S(),
.Data_out_ready_W(),
.Data_out_ready_E(),
.Data_out_valid_N(scheduler_valid_out_N),
.Data_out_valid_S(scheduler_valid_out_S),
.Data_out_valid_W(scheduler_valid_out_W),
.Data_out_valid_E(scheduler_valid_out_E),
//.bustorouter_valid(scheduler_valid_in),
.Data_in_valid_N(scheduler_valid_in_N),
.Data_in_valid_E(scheduler_valid_in_E),
.Data_in_valid_S(scheduler_valid_in_S),
.Data_in_valid_W(scheduler_valid_in_W),
.noc_locationx(scheduler_locationx),
.noc_locationy(scheduler_locationy)
);
node_router node_router0(
.clk(clk),
.rst(rst),
.Data_in_N(),
.Data_in_S(),
.Data_in_W(link_schedulertonode),
.Data_in_E(),
.Data_in_ready_N(),
.Data_in_ready_S(),
.Data_in_ready_W(),
.Data_in_ready_E(),
.Data_out_N(),
.Data_out_S(),
.Data_out_W(),
.Data_out_E(),
.Data_out_ready_N(),
.Data_out_ready_S(),
.Data_out_ready_W(),
.Data_out_ready_E(),
.Data_out_valid_N(node_valid_out_N),
.Data_out_valid_S(node_valid_out_S),
.Data_out_valid_W(node_valid_out_W),
.Data_out_valid_E(node_valid_out_E),
.Data_in_valid_N(node_valid_in_N),
.Data_in_valid_E(node_valid_in_E),
.Data_in_valid_S(node_valid_in_S),
.Data_in_valid_W(node_valid_in_W),
.noc_locationx(node_locationx),
.noc_locationy(node_locationy)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_16_V
`define SKY130_FD_SC_LS__INV_16_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_16_V
|
#include <bits/stdc++.h> using namespace std; int n, c[3010]; struct info { int x, y; }; struct as { int a, b, c; } ans; struct node { int x, id; } a[3010]; inline bool cmp(node a, node b) { return a.x > b.x; } inline info max(info a, info b) { if (a.x < b.x) return b; return a; } struct seg { int lt[12010], rt[12010]; info mx[12010]; inline void build(int i, int l, int r) { lt[i] = l; rt[i] = r; if (l == r) { mx[i] = (info){a[l].x - a[l + 1].x, l}; return; } int mid = l + r >> 1; build(i * 2, l, mid); build(i * 2 + 1, mid + 1, r); mx[i] = max(mx[i * 2], mx[i * 2 + 1]); } inline info query(int i, int l, int r) { if (l <= lt[i] && r >= rt[i]) return mx[i]; int mid = lt[i] + rt[i] >> 1; info ans = {-1, 0}; if (l <= mid) ans = query(i * 2, l, r); if (r > mid) ans = max(ans, query(i * 2 + 1, l, r)); return ans; } } A; inline as max(as t1, as t2) { if (t1.a == 0) return t2; if (a[t1.a].x - a[t1.a + 1].x != a[t2.a].x - a[t2.a + 1].x) return a[t1.a].x - a[t1.a + 1].x > a[t2.a].x - a[t2.a + 1].x ? t1 : t2; if (a[t1.b].x - a[t1.b + 1].x != a[t2.b].x - a[t2.b + 1].x) return a[t1.b].x - a[t1.b + 1].x > a[t2.b].x - a[t2.b + 1].x ? t1 : t2; if (a[t1.c].x - a[t1.c + 1].x != a[t2.c].x - a[t2.c + 1].x) return a[t1.c].x - a[t1.c + 1].x > a[t2.c].x - a[t2.c + 1].x ? t1 : t2; } int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %d , &a[i].x), a[i].id = i; sort(a + 1, a + n + 1, cmp); A.build(1, 1, n); for (int i = 1; i <= n; i++) for (int j = i + 1; j < n; j++) if (2 * (j - i) >= i && i * 2 >= j - i) { int lk = max(j + (max(i, j - i) + 1) / 2, j + 1), rk = min(j + 2 * min(i, j - i), n); if (lk <= rk) ans = max(ans, (as){i, j, A.query(1, lk, rk).y}); } for (int i = 1; i <= ans.a; i++) c[a[i].id] = 1; for (int i = ans.a + 1; i <= ans.b; i++) c[a[i].id] = 2; for (int i = ans.b + 1; i <= ans.c; i++) c[a[i].id] = 3; for (int i = ans.c + 1; i <= n; i++) c[a[i].id] = -1; for (int i = 1; i <= n; i++) printf( %d , c[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005, logN = 18; int n, q, l, r, tim; struct vec { int x, y, num; bool operator<(const vec &A) const { return x < A.x || x == A.x && y > A.y; } } a[N]; inline long long calc(vec *a) { return a->x + 1LL * tim * a->y; } inline long long cross(vec &a, vec &b, vec &c) { return (long long)(b.x - a.x) * (c.y - a.y) - (long long)(b.y - a.y) * (c.x - a.x); } vec mem[N * logN * 2], *newmem = mem; struct data { vec *st, *en; } t[N * 4]; void build(int i, int beg, int end) { t[i].st = newmem; if (end - beg == 1) { scanf( %d%d , &t[i].st->x, &t[i].st->y); t[i].st->num = end; newmem++; t[i].en = newmem; return; } int mid = beg + end >> 1; build(i << 1, beg, mid); build(i << 1 | 1, mid, end); t[i].st = t[i].en = newmem; for (vec *l = t[i << 1].st, *r = t[i << 1 | 1].st; l < t[i << 1].en || r < t[i << 1 | 1].en;) if (l < t[i << 1].en && (r == t[i << 1 | 1].en || *l < *r)) { while (t[i].en - t[i].st > 1 && cross(t[i].en[-2], t[i].en[-1], *l) >= 0) t[i].en--; *t[i].en++ = *l++; } else { while (t[i].en - t[i].st > 1 && cross(t[i].en[-2], t[i].en[-1], *r) >= 0) t[i].en--; *t[i].en++ = *r++; } newmem = t[i].en; } vec *query(int i, int beg, int end) { if (r <= beg || l >= end) return a; if (l <= beg && r >= end) { vec *a = t[i].st, *b = t[i].en - 1; long long fa = calc(a), fb = calc(b); while (b - a + 1 >= 3) { vec *mid1 = a + (b - a + 1) / 3, *mid2 = b - (b - a + 1) / 3; long long f1 = calc(mid1), f2 = calc(mid2); if (fa <= f1 && f1 <= f2) a = mid1, fa = f1; else if (fb <= f2 && f2 <= f1) b = mid2, fb = f2; else puts( Error ); } vec *res = b; for (; a < b; a++) if (calc(res) < calc(a)) res = a; return res; } int mid = beg + end >> 1; vec *a = query(i << 1, beg, mid), *b = query(i << 1 | 1, mid, end); return calc(a) > calc(b) ? a : b; } int main() { scanf( %d%d , &n, &q); build(1, 0, n); while (q--) { scanf( %d%d%d , &l, &r, &tim); l--; printf( %d n , query(1, 0, n)->num); } }
|
#include <bits/stdc++.h> using namespace std; pair<long long, long long> a[100001]; long long start = 0; long long h; long long res; long long c[100001]; long long n; int main() { ios_base::sync_with_stdio(false); cin >> n >> h; for (int i = 1; i <= n; ++i) { cin >> a[i].first; a[i].second = i; } sort(a + 1, a + n + 1); res = a[n].first + a[n - 1].first - a[1].first - a[2].first; for (int i = n; i >= 2; --i) { long long curmax, curmin; if (i == n) curmax = max(a[n].first + a[n - 1].first + h, a[n - 1].first + a[n - 2].first); else curmax = max(a[n].first + a[n - 1].first, a[n].first + a[i - 1].first + h); if (i != 2) curmin = min(a[i].first + a[1].first + h, a[1].first + a[2].first); else curmin = min(a[2].first + a[1].first + h, a[2].first + a[3].first); long long curdif = curmax - curmin; if (curdif < res) { res = curdif; start = i - 1; } } for (int i = 1; i <= start; ++i) { c[a[i].second] = 1; } cout << res << endl; for (int i = 1; i <= n; ++i) { if (c[i]) cout << c[i] << ; else cout << 2 << ; } }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6; const long long MX = -1e7 - 3; const long long MN = 1e7 + 3; long long n, m, cnt, ans, x, y, mx = MX, mn = MN, a, b, c, d, T, l, r, k; float p = 3.14159; bool bl, bl1; string str = , s; map<char, long long> mp, mp1; vector<long long> v; deque<long long> q; bool used[N]; pair<long long, long long> pr[N]; pair<long long, char> pr1[N]; int main() { cin >> T; for (long long i = 0; i < T; i++) { cin >> n >> x >> a >> b; if (a > b) { c = a; a = b; b = c; } if (a - x >= 1) { a -= x; x = 0; } else { x -= a - 1; a = 1; } if (b + x <= n) { b += x; x = 0; } else b = n; v.push_back(b - a); } for (long long i = 0; i < v.size(); i++) cout << v[i] << n ; cout << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32O_SYMBOL_V
`define SKY130_FD_SC_HD__A32O_SYMBOL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a32o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32O_SYMBOL_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_timer_ms (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_interrupt_enable;
reg control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire status_wr_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'h3E7;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = 1;
assign do_stop_counter = 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[0];
end
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T sqr(T x) { return x * x; } struct sp { int x, y; bool operator<(const sp &a) const { return x < a.x || x == a.x && y < a.y; } bool operator==(const sp &a) const { return x == a.x && y == a.y; } }; namespace std { template <> struct hash<sp> { size_t operator()(sp a) const { return a.x * 9875321 + a.y; } }; } // namespace std unordered_map<sp, int> m1; vector<int> b; vector<int> a[110000]; int n, m, ans; int main() { int i, j, k, x, y, d; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d%d , &x, &y); a[x].push_back(y); m1[sp{x, y}] = 1; } m = sqrt(n); for (i = 0; i <= 100000; i++) if (a[i].size() >= m) b.push_back(i); for (i = 0; i < b.size(); i++) for (j = i + 1; j < b.size(); j++) { d = b[j] - b[i]; x = b[i]; for (k = 0; k < a[x].size(); k++) { y = a[x][k]; if (m1.count(sp{x + d, y}) && m1.count(sp{x, y + d}) && m1.count(sp{x + d, y + d})) ans++; } } for (i = 0; i <= 100000; i++) if (a[i].size() < m) { sort(a[i].begin(), a[i].end()); x = i; for (j = 0; j < a[x].size(); j++) { y = a[x][j]; for (k = j + 1; k < a[x].size(); k++) { d = a[x][k] - a[x][j]; if (m1.count(sp{x + d, y}) && m1.count(sp{x + d, y + d})) ans++; if (x - d >= 0 && a[x - d].size() >= m) if (m1.count(sp{x - d, y}) && m1.count(sp{x - d, y + d})) ans++; } } } printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; void imprimirVector(vector<int> v) { if (!v.empty()) { int p = v.size(); cout << [ ; for (int i = 0; i < (int)(p - 1); i++) cout << v[i] << , ; cout << v[p - 1] << ] << endl; } else cout << [] << endl; } int toNumber(string s) { int Number; if (!(istringstream(s) >> Number)) Number = 0; return Number; } string toString(int number) { ostringstream ostr; ostr << number; return ostr.str(); } int main() { long long n; cin >> n; vector<bool> v(n + 1, false); vector<long long> a(n); vector<long long> ans(n); vector<long long> faltan; for (int i = 0; i < (int)(n); i++) { cin >> a[i]; if (a[i] <= n && !v[a[i]]) { ans[i] = a[i]; v[a[i]] = true; } else faltan.push_back(i); } for (int i = (1); i < (int)(n + 1); i++) { if (!v[i]) { long long r = faltan.back(); faltan.pop_back(); ans[r] = i; } } for (int i = 0; i < (int)(n); i++) { if (i) cout << ; cout << ans[i]; } cout << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC FSM ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Insn cache state machine ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_ic_fsm.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Bugs fixed.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_ICFSM_IDLE 2'd0
`define OR1200_ICFSM_CFETCH 2'd1
`define OR1200_ICFSM_LREFILL3 2'd2
`define OR1200_ICFSM_IFETCH 2'd3
//
// Instruction cache FSM
//
module or1200_ic_fsm(
// Clock and reset
clk, rst,
// Internal i/f to top level IC
ic_en, icqmem_cycstb_i, icqmem_ci_i,
tagcomp_miss,
biudata_valid, biudata_error,
start_addr, saved_addr,
icram_we, tag_we,
biu_read,
first_hit_ack, first_miss_ack, first_miss_err,
burst
);
//
// I/O
//
input clk;
input rst;
input ic_en;
input icqmem_cycstb_i;
input icqmem_ci_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
input [31:0] start_addr;
output [31:0] saved_addr;
output [3:0] icram_we;
output biu_read;
output first_hit_ack;
output first_miss_ack;
output first_miss_err;
output burst;
output tag_we;
//
// Internal wires and regs
//
reg [31:0] saved_addr_r;
reg [1:0] state;
reg [`OR1200_ICLS-1:0] cnt;
reg hitmiss_eval;
reg load;
reg cache_inhibit;
reg last_eval_miss; // JPB
//
// Generate of ICRAM write enables
//
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;
// Asserted when a cache hit occurs and the first word is ready/valid
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval &
!tagcomp_miss & !cache_inhibit;
// Asserted when a cache miss occurs, but the first word of the new
// cache line is ready (on the bus)
// Cache hits overpower bus data
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid &
~first_hit_ack;
// Asserted when a cache occurs, but there was a bus error with handling
// the old line or fetching the new line
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss &
!cache_inhibit | (state == `OR1200_ICFSM_LREFILL3);
//
// Main IC FSM
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
state <= `OR1200_ICFSM_IDLE;
saved_addr_r <= 32'b0;
hitmiss_eval <= 1'b0;
load <= 1'b0;
cnt <= `OR1200_ICLS'd0;
cache_inhibit <= 1'b0;
last_eval_miss <= 0; // JPB
end
else
case (state) // synopsys parallel_case
`OR1200_ICFSM_IDLE :
if (ic_en & icqmem_cycstb_i) begin // fetch
state <= `OR1200_ICFSM_CFETCH;
saved_addr_r <= start_addr;
hitmiss_eval <= 1'b1;
load <= 1'b1;
cache_inhibit <= icqmem_ci_i;
last_eval_miss <= 0; // JPB
end
else begin // idle
hitmiss_eval <= 1'b0;
load <= 1'b0;
cache_inhibit <= 1'b0;
end
`OR1200_ICFSM_CFETCH: begin // fetch
if (icqmem_cycstb_i & icqmem_ci_i)
cache_inhibit <= 1'b1;
if (hitmiss_eval)
saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];
// Check for stopped cache loads
// instruction cache turned-off
if ((!ic_en) ||
// fetch aborted (usually caused by IMMU)
(hitmiss_eval & !icqmem_cycstb_i) ||
(biudata_error) || // fetch terminated with an error
// fetch from cache-inhibited page
(cache_inhibit & biudata_valid)) begin
state <= `OR1200_ICFSM_IDLE;
hitmiss_eval <= 1'b0;
load <= 1'b0;
cache_inhibit <= 1'b0;
end // if ((!ic_en) ||...
// fetch missed, wait for first fetch and continue filling line
else if (tagcomp_miss & biudata_valid) begin
state <= `OR1200_ICFSM_LREFILL3;
saved_addr_r[`OR1200_ICLS-1:2]
<= saved_addr_r[`OR1200_ICLS-1:2] + 1;
hitmiss_eval <= 1'b0;
cnt <= ((1 << `OR1200_ICLS) - (2 * 4));
cache_inhibit <= 1'b0;
end
// fetch aborted (usually caused by exception)
else if (!icqmem_cycstb_i
& !last_eval_miss // JPB
) begin
state <= `OR1200_ICFSM_IDLE;
hitmiss_eval <= 1'b0;
load <= 1'b0;
cache_inhibit <= 1'b0;
end
// fetch hit, wait in this state for now
else if (!tagcomp_miss & !icqmem_ci_i) begin
saved_addr_r <= start_addr;
cache_inhibit <= 1'b0;
end
else // fetch in-progress
hitmiss_eval <= 1'b0;
if (hitmiss_eval & !tagcomp_miss) // JPB
last_eval_miss <= 1; // JPB
end
`OR1200_ICFSM_LREFILL3 : begin
// abort because IC has just been turned off
if (!ic_en) begin
// invalidate before IC can be turned on
state <= `OR1200_ICFSM_IDLE;
saved_addr_r <= start_addr;
hitmiss_eval <= 1'b0;
load <= 1'b0;
end
// refill ack, more fetchs to come
else if (biudata_valid && (|cnt)) begin
cnt <= cnt - `OR1200_ICLS'd4;
saved_addr_r[`OR1200_ICLS-1:2]
<= saved_addr_r[`OR1200_ICLS-1:2] + 1;
end
// last fetch of line refill
else if (biudata_valid) begin
state <= `OR1200_ICFSM_IDLE;
saved_addr_r <= start_addr;
hitmiss_eval <= 1'b0;
load <= 1'b0;
end
end
default:
state <= `OR1200_ICFSM_IDLE;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_2_V
`define SKY130_FD_SC_HS__FILL_2_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hs__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hs__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_2_V
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
* two registers.
*/
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__AND4BB_PP_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
/* All files are owned by Kris Kalavantavanich.
* Feel free to use/modify/distribute in the condition that this copyright header is kept unmodified.
* Github: https://github.com/kkalavantavanich/SD2017 */
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 05/19/2017 12:40:27 PM
// Design Name: CRC Generator - Master
// Module Name: crcGenMaster
// Project Name: SD2017
// Target Devices: Basys3
// Revision: 1.02
// Revision 1.02 - General CRC generator and size
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// CRC-7 Generator
module crcGenMaster # (
parameter bitLength = 40,
parameter crcLength = 7
)(
clk, // Clock
useModule, // sync. CRC Slave will start on posedge and keeps crc until negedge
instream, // input bit stream. length defined by parameter 'bitLength'. Should not change while useModule.
generator, // crc generator polynomial
crc, // crc value
finish, // sync. 1 = isFinished
state // {_start, _running, _waiting}, used for debugging
);
// 'public' variables
input clk;
input useModule;
input [bitLength - 1:0] instream;
input [crcLength:0] generator;
output wire [crcLength - 1:0] crc;
output reg finish = 0;
output [2:0] state;
// 'private' variables
wire [crcLength - 1:0] _crc;
reg _enable = 0, _clear = 1, _sync_enable;
reg _start = 0, _running = 0, _waiting = 0;
reg [9:0] _i = 0; // loop index
wire _datain;
assign _datain = _enable ? instream[_i] : 1'b0;
reg _sync_useModule;
reg [1:0] _edge_useModule;
assign crc = (_sync_useModule || _running ? _crc : {crcLength{1'bZ}});
reg [1:0] _error = 0;
// 'Private' Slave CRC Generator
crcGenerator c0 (_datain, clk, _clear, _sync_enable, generator, _crc);
always @ (posedge clk) begin
if (_edge_useModule == 2'b01 && ~_start && ~_running && ~_waiting) begin
// start condition
finish <= 0;
_clear <= 0;
_enable <= 1;
_start <= 1; // state start & not running & not waiting
end else if (_edge_useModule == 2'b11 && _start && _waiting) begin
// end condition
_start <= 0; // state not start & not running & waiting
_enable <= 0;
end else if (_edge_useModule == 2'b11 && ~_start && _waiting) begin
finish <= 1;
end else if (_edge_useModule == 2'b10) begin
// unuse module
finish <= 0;
_clear <= 1;
_enable <= 0;
end else begin
// => should not enter this always loop : rw/s, r/w/s, r/ws
_error[0] = 1;
end
end
// 'for loop'
always @ (posedge clk) begin
if (_start && ~_running && ~_waiting) begin
// start loop with index i > 0 (doesn't handle i = 0)
_running <= 1;
_i = bitLength - 2; // first bit is always 0 (sent in this if-block)
if (_i == 0) begin
// end loop condition
_running <= 0;
_waiting <= 1;
end
end else if (_start && _running & ~_waiting) begin
// looping
_i = _i - 1;
if (_i == 1) begin // signal delay to control block (this::line 60) compensation
// end loop condition
_running <= 0;
_waiting <= 1;
end
end else if (_start && _waiting) begin
// do nothing if waiting
end else begin
// iff not started
_running = 0;
_waiting = 0;
end
end
assign state = {_start, _running, _waiting};
always @ (posedge clk) begin
_sync_enable <= _enable;
end
always @ (posedge clk) begin
_edge_useModule[1] <= _edge_useModule[0];
_edge_useModule[0] <= useModule;
end
always @ (posedge clk) begin
_sync_useModule <= useModule;
end
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream consistent overhead byte stuffing (COBS) decoder
*/
module axis_cobs_decode
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [7:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* AXI output
*/
output wire [7:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser
);
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_SEGMENT = 2'd1,
STATE_NEXT_SEGMENT = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [7:0] count_reg = 8'd0, count_next;
reg suppress_zero_reg = 1'b0, suppress_zero_next;
reg [7:0] temp_tdata_reg = 8'd0, temp_tdata_next;
reg temp_tvalid_reg = 1'b0, temp_tvalid_next;
// internal datapath
reg [7:0] m_axis_tdata_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
assign s_axis_tready = s_axis_tready_reg;
always @* begin
state_next = STATE_IDLE;
count_next = count_reg;
suppress_zero_next = suppress_zero_reg;
temp_tdata_next = temp_tdata_reg;
temp_tvalid_next = temp_tvalid_reg;
m_axis_tdata_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
s_axis_tready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state
s_axis_tready_next = m_axis_tready_int_early || !temp_tvalid_reg;
// output final word
m_axis_tdata_int = temp_tdata_reg;
m_axis_tvalid_int = temp_tvalid_reg;
m_axis_tlast_int = temp_tvalid_reg;
temp_tvalid_next = temp_tvalid_reg && !m_axis_tready_int_reg;
if (s_axis_tready && s_axis_tvalid) begin
// valid input data
// skip any leading zeros
if (s_axis_tdata != 8'd0) begin
// store count value and zero suppress
count_next = s_axis_tdata-1;
suppress_zero_next = (s_axis_tdata == 8'd255);
s_axis_tready_next = m_axis_tready_int_early;
if (s_axis_tdata == 8'd1) begin
// next byte will be count value
state_next = STATE_NEXT_SEGMENT;
end else begin
// next byte will be data
state_next = STATE_SEGMENT;
end
end else begin
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_SEGMENT: begin
// receive segment
s_axis_tready_next = m_axis_tready_int_early;
if (s_axis_tready && s_axis_tvalid) begin
// valid input data
// store in temp register
temp_tdata_next = s_axis_tdata;
temp_tvalid_next = 1'b1;
// move temp to output
m_axis_tdata_int = temp_tdata_reg;
m_axis_tvalid_int = temp_tvalid_reg;
// decrement count
count_next = count_reg - 1;
if (s_axis_tdata == 8'd0) begin
// got a zero byte in a frame - mark it as an error and re-sync
temp_tvalid_next = 1'b0;
m_axis_tvalid_int = 1'b1;
m_axis_tuser_int = 1'b1;
m_axis_tlast_int = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end else if (s_axis_tlast) begin
// end of frame
if (count_reg == 8'd1 && !s_axis_tuser) begin
// end of frame indication at correct time, go to idle to output final byte
state_next = STATE_IDLE;
end else begin
// end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
temp_tvalid_next = 1'b0;
m_axis_tvalid_int = 1'b1;
m_axis_tuser_int = 1'b1;
m_axis_tlast_int = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else if (count_reg == 8'd1) begin
// next byte will be count value
state_next = STATE_NEXT_SEGMENT;
end else begin
// next byte will be data
state_next = STATE_SEGMENT;
end
end else begin
state_next = STATE_SEGMENT;
end
end
STATE_NEXT_SEGMENT: begin
// next segment
s_axis_tready_next = m_axis_tready_int_early;
if (s_axis_tready && s_axis_tvalid) begin
// valid input data
// store zero in temp if not suppressed
temp_tdata_next = 8'd0;
temp_tvalid_next = !suppress_zero_reg;
// move temp to output
m_axis_tdata_int = temp_tdata_reg;
m_axis_tvalid_int = temp_tvalid_reg;
if (s_axis_tdata == 8'd0) begin
// got a zero byte delineating the end of the frame, so mark as such and re-sync
temp_tvalid_next = 1'b0;
m_axis_tuser_int = s_axis_tuser;
m_axis_tlast_int = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end else if (s_axis_tlast) begin
if (s_axis_tdata == 8'd1 && !s_axis_tuser) begin
// end of frame indication at correct time, go to idle to output final byte
state_next = STATE_IDLE;
end else begin
// end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
temp_tvalid_next = 1'b0;
m_axis_tvalid_int = 1'b1;
m_axis_tuser_int = 1'b1;
m_axis_tlast_int = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
// otherwise, store count value and zero suppress
count_next = s_axis_tdata-1;
suppress_zero_next = (s_axis_tdata == 8'd255);
s_axis_tready_next = m_axis_tready_int_early;
if (s_axis_tdata == 8'd1) begin
// next byte will be count value
state_next = STATE_NEXT_SEGMENT;
end else begin
// next byte will be data
state_next = STATE_SEGMENT;
end
end
end else begin
state_next = STATE_NEXT_SEGMENT;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
temp_tvalid_reg <= 1'b0;
s_axis_tready_reg <= 1'b0;
end else begin
state_reg <= state_next;
temp_tvalid_reg <= temp_tvalid_next;
s_axis_tready_reg <= s_axis_tready_next;
end
temp_tdata_reg <= temp_tdata_next;
count_reg <= count_next;
suppress_zero_reg <= suppress_zero_next;
end
// output datapath logic
reg [7:0] m_axis_tdata_reg = 8'd0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_axis_tdata_reg = 8'd0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_ram
*/
module test_wb_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] adr_i = 0;
reg [DATA_WIDTH-1:0] dat_i = 0;
reg we_i = 0;
reg [SELECT_WIDTH-1:0] sel_i = 0;
reg stb_i = 0;
reg cyc_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] dat_o;
wire ack_o;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
adr_i,
dat_i,
we_i,
sel_i,
stb_i,
cyc_i
);
$to_myhdl(
dat_o,
ack_o
);
// dump file
$dumpfile("test_wb_ram.lxt");
$dumpvars(0, test_wb_ram);
end
wb_ram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.adr_i(adr_i),
.dat_i(dat_i),
.dat_o(dat_o),
.we_i(we_i),
.sel_i(sel_i),
.stb_i(stb_i),
.ack_o(ack_o),
.cyc_i(cyc_i)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int n; cin >> n; long long int ans = 0; long long int t = 1; long long int x = 2; while (n - (t * (t + 1) / 2) >= 0) { long long int val = t * (t + 1) / 2; n -= val; t += x; x *= 2; ans++; } cout << ans << endl; } int main() { int t; cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; typedef int arr32[5000010]; arr32 x, rk, l, r; int n; long long ans; bool cmp(const int &a, const int &b) { return x[a] < x[b]; } void erase(int x) { r[l[x]] = r[x], l[r[x]] = l[x]; } int main() { cin >> n; for (int i = 1; i <= n; ++i) { scanf( %d , x + i); rk[i] = i, l[i] = i - 1, r[i] = i + 1; } sort(rk + 1, rk + n + 1, cmp); for (int i = 1; i <= n - 2; ++i) { int p = rk[i]; if (l[p] == 0) ans += x[p], erase(p); else if (r[p] == n + 1) ans += x[p], erase(p); else ans += min(x[l[p]], x[r[p]]), erase(p); } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 100; const long long inf = 1e18; vector<int> g[maxn]; bool visit[maxn]; int cnt = 0; void dfs(int u) { cnt = 0; queue<int> q; q.push(u); visit[u] = true; cnt++; while (!q.empty()) { int u = q.front(); q.pop(); for (auto v : g[u]) if (visit[v] == false) { q.push(v); visit[v] = true; cnt++; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n, m; cin >> n >> m; vector<int> st; int u, v; memset(visit, false, sizeof visit); for (int i = 1; i <= m; i++) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); st.push_back(u); st.push_back(v); } int ans = 0; for (auto v : st) { if (visit[v] == false) { dfs(v); ans += (cnt - 1); cnt = 0; } } cout << (m - ans) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int xa, ya, xb, yb, n, count = 0; cin >> xa >> ya >> xb >> yb; if (xa > xb) { int t = xa; xa = xb; xb = t; } if (ya > yb) { int t = ya; ya = yb; yb = t; } cin >> n; int x[n], y[n], r[n]; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i] >> r[i]; } for (int i = xa; i <= xb; i++) { for (int h = 0; h < n; h++) { double diff = sqrt((x[h] - i) * (x[h] - i) + (y[h] - ya) * (y[h] - ya)); if (diff <= r[h]) { count++; break; } } for (int h = 0; h < n; h++) { double diff = sqrt((x[h] - i) * (x[h] - i) + (y[h] - yb) * (y[h] - yb)); if (diff <= r[h]) { count++; break; } } } for (int j = (ya + 1); j < yb; j++) { for (int h = 0; h < n; h++) { double diff = sqrt((x[h] - xa) * (x[h] - xa) + (y[h] - j) * (y[h] - j)); if (diff <= r[h]) { count++; break; } } for (int h = 0; h < n; h++) { double diff = sqrt((x[h] - xb) * (x[h] - xb) + (y[h] - j) * (y[h] - j)); if (diff <= r[h]) { count++; break; } } } int ans = (2 * (xb - xa + yb - ya)) - count; cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int s, n, a[10000] = {0}, m = -1, y, i; cin >> s >> n; int c = n; while (n--) { cin >> i >> y; a[i] += y; m = max(m, i); } for (int i = 0; i < 10000; i++) { if (s > i) { s += a[i]; } } s > m ? cout << YES : cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > ans; void gen(int n) { for (int e = 0; e < n; e++) ans.push_back({6 * e + 1, 6 * e + 2, 6 * e + 3, 6 * e + 5}); } int main() { int n, k; cin >> n >> k; cout << k * (6 * n - 1) << endl; gen(n); for (auto &it : ans) for (int e = 0; e < 4; e++) cout << k * it[e] << n [e == 3]; return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
wasca_nios2_gen2_0_cpu_debug_slave_tck the_wasca_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
wasca_nios2_gen2_0_cpu_debug_slave_sysclk the_wasca_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic wasca_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; constexpr int MAXN = 100005; int SQRTN; int n, k; int t[MAXN], a[MAXN]; ll p[MAXN]; ll ans[MAXN]; ll cur = 0; int ind[MAXN], left_ind[MAXN], right_ind[MAXN]; int freq[3 * MAXN]; struct query { int l, r, i; } queries[MAXN]; bool cmp(const query& a, const query& b) { return a.l / SQRTN < b.l / SQRTN || (a.l / SQRTN == b.l / SQRTN and a.r < b.r); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); scanf( %d %d , &n, &k); for (int i = 1; i <= n; ++i) { scanf( %d , t + i); } for (int i = 1; i <= n; ++i) { scanf( %d , a + i); } vector<ll> vals; vals.push_back(0LL); vals.push_back(k); vals.push_back(-k); p[0] = 0LL; for (int i = 1; i <= n; ++i) { if (t[i] == 1) p[i] = p[i - 1] + a[i]; else p[i] = p[i - 1] - a[i]; vals.push_back(p[i]); vals.push_back(p[i] - k); vals.push_back(p[i] + k); } sort(begin(vals), end(vals)); vals.erase(unique(begin(vals), end(vals)), end(vals)); for (int i = 0; i <= n; ++i) { ind[i] = lower_bound(begin(vals), end(vals), p[i]) - begin(vals); left_ind[i] = lower_bound(begin(vals), end(vals), p[i] - k) - begin(vals); right_ind[i] = lower_bound(begin(vals), end(vals), p[i] + k) - begin(vals); } SQRTN = sqrt(n); int q; int l, r; scanf( %d , &q); for (int i = 0; i < q; ++i) { scanf( %d %d , &l, &r); --l; queries[i] = {l, r, i}; } sort(queries, queries + q, cmp); int left_ptr = 0; int right_ptr = -1; for (int i = 0; i < q; ++i) { while (right_ptr < queries[i].r) { ++right_ptr; cur += freq[left_ind[right_ptr]]; ++freq[ind[right_ptr]]; } while (right_ptr > queries[i].r) { --freq[ind[right_ptr]]; cur -= freq[left_ind[right_ptr]]; --right_ptr; } while (left_ptr < queries[i].l) { --freq[ind[left_ptr]]; cur -= freq[right_ind[left_ptr]]; ++left_ptr; } while (left_ptr > queries[i].l) { --left_ptr; cur += freq[right_ind[left_ptr]]; ++freq[ind[left_ptr]]; } ans[queries[i].i] = cur; } for (int i = 0; i < q; ++i) { printf( %lld n , ans[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 1e5 + 10; vector<int> v[N]; void init() { int tot = 0; for (int i = 1; i < N; i++) { for (int j = i; j < N; j += i) { v[j].push_back(i); } tot = max(tot, (int)v[i].size()); } } int C(int n, int m) { int U = 1, D = 1; while (m) { U *= n++; D *= m--; } return U / D; } void solve(int n) { int ret = 0; for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) { ret++; } } cout << n << << ret << endl; } int main() { map<tuple<int, int, int>, int> mp; for (int i = 1; i < 8; i++) { if (((i >> 0) & 1) == 0) continue; for (int j = 1; j < 8; j++) { if (((j >> 1) & 1) == 0) continue; for (int k = 1; k < 8; k++) { if (((k >> 2) & 1) == 0) continue; int a = i, b = j, c = k; if (a > b) swap(a, b); if (b > c) swap(b, c); if (a > b) swap(a, b); mp[{a, b, c}] = 1; } } } init(); int ncase; scanf( %d , &ncase); while (ncase--) { map<int, int> mc; int a, b, c; scanf( %d%d%d , &a, &b, &c); vector<int> v1, v2; merge(v[a].begin(), v[a].end(), v[b].begin(), v[b].end(), back_inserter(v1)); merge(v[c].begin(), v[c].end(), v1.begin(), v1.end(), back_inserter(v2)); v2.erase(unique(v2.begin(), v2.end()), v2.end()); int sz[8]; memset((sz), (0), sizeof(sz)); for (auto &x : v2) { int f = 0; if (a % x == 0) f |= 1; if (b % x == 0) f |= 2; if (c % x == 0) f |= 4; sz[f]++; } int ans = 0; for (auto &t : mp) { int a, b, c; tie(a, b, c) = t.first; if (a == c) ans += C(sz[a], 3); else if (a == b) ans += C(sz[a], 2) * sz[c]; else if (b == c) ans += C(sz[b], 2) * sz[a]; else ans += sz[a] * sz[b] * sz[c]; } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a, b, n; int main() { cin >> a >> b >> n; for (int i = 0; i < n - 1; ++i) { b = a + b; a = b - a; } cout << b << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_SYMBOL_V
`define SKY130_FD_SC_LP__OR4_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int count = 0, size; cin >> size; char c; vector<char> num; for (int i = 0; i < size; i++) { cin >> c; num.push_back(c); } for (int i = 0; i < num.size(); i++) { if (num[i] == 8 ) count++; if ((size / 11) < count) count = (size / 11); } cout << count << endl; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_control_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 4,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle
);
//------------------------Address Info-------------------
// 0x0 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x4 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x8 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0xc : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 4'h0,
ADDR_GIE = 4'h4,
ADDR_IER = 4'h8,
ADDR_ISR = 4'hc,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 4;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg int_ap_idle;
reg int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 1'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_ap_idle
always @(posedge ACLK) begin
if (ARESET)
int_ap_idle <= 1'b0;
else if (ACLK_EN) begin
int_ap_idle <= ap_idle;
end
end
// int_ap_ready
always @(posedge ACLK) begin
if (ARESET)
int_ap_ready <= 1'b0;
else if (ACLK_EN) begin
int_ap_ready <= ap_ready;
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
//------------------------Memory logic-------------------
endmodule
|
#include <bits/stdc++.h> int inp() { char c = getchar(); int neg = 1; while (c < 0 || c > 9 ) { if (c == - ) neg = -1; c = getchar(); } int sum = 0; while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } return sum * neg; } int a[110]; int f[110][110][110][2]; bool flg[110]; int main() { int n = inp(); int l1 = (n >> 1), l2 = (n >> 1); if (n & 1) l2++; int ans = 0; for (int i = 1; i <= n; i++) { a[i] = inp(); if (a[i] != 0) { if (a[i] & 1) l2--; else l1--; if (a[i - 1] && ((a[i] ^ a[i - 1]) & 1)) ans++; } else flg[i] = true; } memset(f, 0x3f, sizeof(f)); f[1][l1][l2][0] = f[1][l1][l2][1] = 0; for (int i = 1; i <= n; i++) for (int j = 0; j <= n; j++) for (int u = 0; u <= n; u++) { for (int k = 0; k <= 1; k++) { if (f[i][j][u][k] > 1e9) continue; if (flg[i - 1]) a[i - 1] = k; if (a[i] != 0) { if (i > 1 && ((a[i] ^ a[i - 1]) & 1)) f[i][j][u][k]++; f[i + 1][j][u][k] = f[i][j][u][k]; continue; } if (j) { int ret = f[i][j][u][k]; if (i > 1) ret += (a[i - 1] & 1); f[i + 1][j - 1][u][0] = std::min(f[i + 1][j - 1][u][0], ret); } if (u) { int ret = f[i][j][u][k]; if (i > 1) ret += (a[i - 1] & 1) ^ 1; f[i + 1][j][u - 1][1] = std::min(f[i + 1][j][u - 1][1], ret); } } } printf( %d n , std::min(f[n + 1][0][0][0], f[n + 1][0][0][1])); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRDLSTP_PP_BLACKBOX_V
/**
* srdlstp: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlstp (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_PP_BLACKBOX_V
|
// FGPA Test of TOP functional block.
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// Maps FPGA IO onto RFID tag (top.v)
module toptest(LEDR, LEDG, GPIO_0, KEY, SW, EXT_CLOCK,
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
input [3:0] KEY;
inout [35:0] GPIO_0;
output [17:0] LEDR;
output [8:0] LEDG;
input EXT_CLOCK;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
// basic tag IO
wire clk, reset, demodin, modout;
// Functionality control
wire use_uid, use_q, comm_enable;
// read data connections
wire adc_sample_ctl, adc_sample_clk, adc_sample_datain;
wire msp_sample_ctl, msp_sample_clk, msp_sample_datain;
// write data connections
wire writedataout, writedataclk;
// EPC ID source
wire [7:0] uid_byte_in;
wire [3:0] uid_addr_out;
wire uid_clk_out;
// debugging connections
wire debug_clk, debug_out;
assign debug_clk = SW[5];
assign GPIO_0[35:3] = 33'bZ;
// Basic tag connections
assign clk = EXT_CLOCK;
assign reset = ~KEY[1];
assign demodin = GPIO_0[3];
assign use_q = SW[4];
assign comm_enable = SW[3];
assign use_uid = SW[2];
assign uid_byte_in = SW[17:10];
// adc connections
assign msp_sample_datain = SW[1];
assign adc_sample_datain = SW[0];
/*
// for debugging purposes: hold on to packet type after rx reset.
reg [8:0] rx_packet_reg;
wire [8:0] rx_packet;
always @ (posedge cmd_complete or posedge reset) begin
if (reset) rx_packet_reg <= 0;
else rx_packet_reg <= rx_packet;
end
wire [1:0] readwritebank;
wire [7:0] readwriteptr;
wire [7:0] readwords;
reg [1:0] readwritebank_reg;
reg [7:0] readwriteptr_reg;
reg [7:0] readwords_reg;
always @ (posedge packet_complete or posedge reset) begin
if (reset) begin
readwritebank_reg <= 0;
readwriteptr_reg <= 0;
readwords_reg <= 0;
end else if (rx_packet_reg[7] | rx_packet_reg[8]) begin
readwritebank_reg <= readwritebank;
readwriteptr_reg <= readwriteptr;
readwords_reg <= readwords;
end
end
*/
// red LED debugging connections
assign LEDR[17] = reset; // assign reset to LED for sanity check.
assign LEDR[16] = 0;
assign LEDR[15] = 0;
assign LEDR[14] = 0;
assign LEDR[13] = 0;
assign LEDR[12] = 0;
assign LEDR[11] = 0;
assign LEDR[10:4] = 0;
assign LEDR[3] = 0;
assign LEDR[2] = 0;
assign LEDR[1:0] = 0;
assign LEDG[8:0] = 0;
assign GPIO_0[2] = modout;
assign GPIO_0[1] = debug_clk;
assign GPIO_0[0] = debug_out;
/*
sevenseg U_SEG0 (HEX0,readwritebank_reg);
sevenseg U_SEG1 (HEX1,readwriteptr_reg);
sevenseg U_SEG2 (HEX2,readwords_reg);
sevenseg U_SEG3 (HEX3,4'd3);
sevenseg U_SEG4 (HEX4,slotcounter[3:0]);
sevenseg U_SEG5 (HEX5,slotcounter[7:4]);
sevenseg U_SEG6 (HEX6,slotcounter[11:8]);
sevenseg U_SEG7 (HEX7,{1'b0,slotcounter[14:12]});
*/
top U_TOP (reset, clk, demodin, modout, // regular IO
adc_sample_ctl, adc_sample_clk, adc_sample_datain, // adc connections
msp_sample_ctl, msp_sample_clk, msp_sample_datain, // msp430 connections
uid_byte_in, uid_addr_out, uid_clk_out,
writedataout, writedataclk,
use_uid, use_q, comm_enable,
debug_clk, debug_out);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, cnt, num, sub_d[(2600)], d[(2600)], root, cut[(2600)], t; char s[55][55]; bool mark[(2600)], p, cycle; vector<long long> e[(2600)]; void dfs(long long x, long long par = 0) { bool tmp = 0; if (!t) cnt++; mark[x] = 1; sub_d[x] = d[x]; for (int i = 0; i < e[x].size(); i++) { if (mark[e[x][i]] && e[x][i] != par) cycle = 1; if (!mark[e[x][i]]) { d[e[x][i]] = d[x] + 1; dfs(e[x][i], x); sub_d[x] = min(sub_d[x], sub_d[e[x][i]]); if (sub_d[e[x][i]] >= d[x]) tmp = 1; } else if (e[x][i] != par) sub_d[x] = min(sub_d[x], d[e[x][i]]); } cut[x] += tmp; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> s[i][j]; if (s[i][j] == # ) num++; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) for (int p = -1; p <= 1; p++) for (int q = -1; q <= 1; q++) if ((!p ^ !q) && i + p >= 0 && j + q >= 0 && i + p < n && j + q < m && s[i][j] == # && s[i + p][j + q] == # ) e[i * m + j].push_back((i + p) * m + j + q); for (int i = 0; i < n * m && t < 2; i++) if (s[i / m][i % m] == # ) { for (int j = 0; j < n * m; j++) mark[j] = d[j] = sub_d[j] = 0; root = i; dfs(i); t++; } for (int i = 0; i < n * m; i++) if (cut[i] == 2) p = 1; if (p) cout << 1; else if (cnt != num) cout << 0; else if (cycle) cout << 2; else cout << -1; return 0; }
|
#include <bits/stdc++.h> std::vector<int> V[200010], V2[200010]; int check[200010]; std::stack<int> St; void init(int k) { if (check[k] == 1) return; check[k] = 1; for (int i = 0; i < V[k].size(); i++) init(V[k][i]); St.push(k); } int color[200010]; void makeSCC(int k, int c) { if (color[k] > 0) return; color[k] = c; for (int i = 0; i < V2[k].size(); i++) makeSCC(V2[k][i], c); } int x[200010], cost[200010]; std::vector<int> V3[200010]; int main() { int a; scanf( %d , &a); for (int i = 1; i <= a; i++) scanf( %d , &x[i]); for (int i = 1; i <= a; i++) { int b; scanf( %d , &b); V[i].push_back(b); V2[b].push_back(i); } for (int i = 1; i <= a; i++) init(i); int c = 1; while (!St.empty()) { int k = St.top(); St.pop(); if (color[k] == 0) makeSCC(k, c++); } for (int i = 1; i <= a; i++) cost[i] = 123456789; for (int i = 1; i <= a; i++) cost[color[i]] = cost[color[i]] < x[i] ? cost[color[i]] : x[i]; for (int i = 1; i <= a; i++) if (color[i] != color[V[i][0]]) V3[color[i]].push_back(color[V[i][0]]); long long int ans = 0; for (int i = 1; i <= a; i++) if (V3[i].size() == 0 && cost[i] < 123456789) ans += cost[i]; printf( %lld , ans); }
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//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module time_receiver
(input clk, input rst,
output reg [63:0] vita_time,
output reg sync_rcvd,
input exp_time_in);
wire code_err, disp_err, dispout, complete_word;
reg disp_reg;
reg [9:0] shiftreg;
reg [3:0] bit_count;
wire [8:0] dataout;
reg [8:0] dataout_reg;
reg exp_time_in_reg, exp_time_in_reg2;
always @(posedge clk) exp_time_in_reg <= exp_time_in;
always @(posedge clk) exp_time_in_reg2 <= exp_time_in_reg;
always @(posedge clk)
shiftreg <= {exp_time_in_reg2, shiftreg[9:1]};
localparam COMMA_0 = 10'h283;
localparam COMMA_1 = 10'h17c;
wire found_comma = (shiftreg == COMMA_0) | (shiftreg == COMMA_1);
wire set_disp = (shiftreg == COMMA_1);
always @(posedge clk)
if(rst)
bit_count <= 0;
else if(found_comma | complete_word)
bit_count <= 0;
else
bit_count <= bit_count + 1;
assign complete_word = (bit_count == 9);
always @(posedge clk)
if(set_disp)
disp_reg <= 1;
else if(complete_word)
disp_reg <= dispout;
always @(posedge clk)
if(complete_word)
dataout_reg <= dataout;
decode_8b10b decode_8b10b
(.datain(shiftreg),.dispin(disp_reg),
.dataout(dataout),.dispout(dispout),
.code_err(code_err),.disp_err(disp_err) );
reg error;
always @(posedge clk)
if(complete_word)
error <= code_err | disp_err;
localparam STATE_IDLE = 0;
localparam STATE_T0 = 1;
localparam STATE_T1 = 2;
localparam STATE_T2 = 3;
localparam STATE_T3 = 4;
localparam STATE_T4 = 5;
localparam STATE_T5 = 6;
localparam STATE_T6 = 7;
localparam STATE_T7 = 8;
localparam STATE_TAIL = 9;
localparam HEAD = 9'h13c;
localparam TAIL = 9'h1F7;
reg [3:0] state;
reg [63:0] vita_time_pre;
reg sync_rcvd_pre;
always @(posedge clk)
if(rst)
state <= STATE_IDLE;
else if(complete_word)
if(code_err | disp_err)
state <= STATE_IDLE;
else
case(state)
STATE_IDLE :
if(dataout_reg == HEAD)
state <= STATE_T0;
STATE_T0 :
begin
vita_time_pre[63:56] <= dataout_reg[7:0];
state <= STATE_T1;
end
STATE_T1 :
begin
vita_time_pre[55:48] <= dataout_reg[7:0];
state <= STATE_T2;
end
STATE_T2 :
begin
vita_time_pre[47:40] <= dataout_reg[7:0];
state <= STATE_T3;
end
STATE_T3 :
begin
vita_time_pre[39:32] <= dataout_reg[7:0];
state <= STATE_T4;
end
STATE_T4 :
begin
vita_time_pre[31:24] <= dataout_reg[7:0];
state <= STATE_T5;
end
STATE_T5 :
begin
vita_time_pre[23:16] <= dataout_reg[7:0];
state <= STATE_T6;
end
STATE_T6 :
begin
vita_time_pre[15:8] <= dataout_reg[7:0];
state <= STATE_T7;
end
STATE_T7 :
begin
vita_time_pre[7:0] <= dataout_reg[7:0];
state <= STATE_TAIL;
end
STATE_TAIL :
state <= STATE_IDLE;
endcase // case(state)
always @(posedge clk)
if(rst)
sync_rcvd_pre <= 0;
else
sync_rcvd_pre <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL));
always @(posedge clk) sync_rcvd <= sync_rcvd_pre;
always @(posedge clk) vita_time <= vita_time_pre;
endmodule // time_sender
|
#include <bits/stdc++.h> using namespace std; const int MAX = 500004, inf = 0x3f3f3f3f; int a[MAX]; int no[102]; int nex[MAX][102]; int f[102][102 * 102]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, k, p; cin >> n >> k >> p; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i] += a[i - 1]; a[i] %= p; } for (int i = 0; i < p; i++) no[i] = n + 1; for (int i = n; i >= 0; i--) { for (int j = 0; j < p; j++) { nex[i][j] = no[j]; } no[a[i]] = i; } int M = (p - 1) * k; memset(f, 0x3f, sizeof f); f[0][0] = 0; for (int i = 1; i <= k; i++) { for (int j = 0; j <= M; j++) { for (int u = min(p - 1, j); u >= 0; u--) { if (f[i - 1][j - u] <= n) f[i][j] = min(nex[f[i - 1][j - u]][j % p], f[i][j]); } } } for (int j = a[n]; j <= M; j += p) if (f[k][j] <= n) { cout << j; return 0; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n; int a[n], i; for (i = 0; i < n; ++i) cin >> a[i]; cin >> m; int b[m]; for (i = 0; i < m; ++i) cin >> b[i]; sort(a, a + n, greater<int>()); sort(b, b + m, greater<int>()); cout << a[0] << << b[0] << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, K, bs[500005], hs[500005], ht[500005], ht2[500005], lpos[500005], rpos[500005], ansl, ansr; bool flag; set<int> S; set<int>::iterator it; struct node { int len, id; } a[500005]; char s[500005], t[500005]; int Hashs(int fr, int to) { return (-(long long)hs[fr - 1] * bs[to - fr + 1] % 1000000007 + hs[to] + 1000000007) % 1000000007; } bool check(int fr, int l) { return ht[l] == Hashs(fr, fr + l - 1); } bool check2(int to, int l) { return ht2[m - l + 1] == Hashs(to - l + 1, to); } bool cmp1(const node &lhs, const node &rhs) { return lhs.len > rhs.len; } int main() { scanf( %d%d%d , &n, &m, &K); scanf( %s , s + 1); scanf( %s , t + 1); bs[0] = 1; for (int i = 1; i <= n; ++i) bs[i] = (long long)bs[i - 1] * 8741 % 1000000007; for (int i = 1; i <= n; ++i) hs[i] = ((long long)hs[i - 1] * 8741 + s[i]) % 1000000007; for (int i = 1; i <= m; ++i) ht[i] = ((long long)ht[i - 1] * 8741 + t[i]) % 1000000007; for (int i = 1; i <= n; ++i) { int l = 0, r = min(m, n - i + 1), mid; while (l < r) { mid = (l + r + 1) >> 1; if (check(i, mid)) l = mid; else r = mid - 1; } a[i] = (node){l, i}; } sort(a + 1, a + n + 1, cmp1); S.clear(); int now = 1; for (int i = m; i >= 1; --i) { for (; a[now].len == i && now <= n; now++) { S.insert(a[now].id); } if (i == m) { it = S.lower_bound(1); if (it != S.end()) lpos[i] = *it; else lpos[i] = 1000000000; } else { it = S.lower_bound(K - i + 1); if (it != S.end()) lpos[i] = *it; else lpos[i] = 1000000000; } } for (int i = m; i >= 1; --i) { ht2[i] = (-(long long)ht[i - 1] * bs[m - i + 1] % 1000000007 + ht[m] + 1000000007) % 1000000007; } S.clear(); for (int i = 1; i <= n; ++i) { int l = 0, r = i, mid; while (l < r) { mid = (l + r + 1) >> 1; if (check2(i, mid)) l = mid; else r = mid - 1; } a[i] = (node){l, i}; } sort(a + 1, a + n + 1, cmp1); now = 1; for (int i = m; i >= 1; --i) { for (; a[now].len == i && now <= n; now++) { S.insert(a[now].id); } if (i == m) { it = S.lower_bound(K); if (it != S.end()) rpos[i] = *it; else rpos[i] = -1000000000; } else { it = S.upper_bound(n + i - K); if (it != S.begin()) { it--; rpos[i] = *it; } else rpos[i] = -1000000000; } } flag = 0; for (int i = 1; i < m; ++i) { int x = lpos[i], y = rpos[m - i]; if (i > K || m - i > K) continue; if (x + i - 1 <= y - m + i) { flag = 1; ansl = x + i - K, ansr = y - m + i + 1; break; } } if (!flag && m <= K) { if (max(K, lpos[m] + m - 1) + K <= n) { flag = 1; ansl = max(lpos[m] + m - 1, K) - K + 1, ansr = n - K + 1; } if (min(n - K + 1, rpos[m] - m + 1) - K >= 1) { flag = 1; ansl = 1, ansr = min(n - K + 1, rpos[m] - m + 1); } } if (flag) printf( Yes n%d %d n , ansl, ansr); else printf( No n ); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
//
// --------------------------------------------------------
// Bug Description:
//
// Issue: The gated clock gclk_vld[0] toggles but dvld[0]
// input to the flop does not propagate to the output
// signal entry_vld[0] correctly. The value that propagates
// is the new value of dvld[0] not the one just before the
// posedge of gclk_vld[0].
// --------------------------------------------------------
// Define to see the bug with test failing with gated clock 'gclk_vld'
// Comment out the define to see the test passing with ungated clock 'clk'
`define GATED_CLK_TESTCASE 1
// A side effect of the problem is this warning, disabled by default
//verilator lint_on IMPERFECTSCH
// Test Bench
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
// Take CRC data and apply to testblock inputs
wire [7:0] dvld = crc[7:0];
wire [7:0] ff_en_e1 = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] entry_vld; // From test of Test.v
wire [7:0] ff_en_vld; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_en_vld (ff_en_vld[7:0]),
.entry_vld (entry_vld[7:0]),
// Inputs
.clk (clk),
.dvld (dvld[7:0]),
.ff_en_e1 (ff_en_e1[7:0]));
reg err_code;
reg ffq_clk_active;
reg [7:0] prv_dvld;
initial begin
err_code = 0;
ffq_clk_active = 0;
end
always @ (posedge clk) begin
prv_dvld = test.dvld;
end
always @ (negedge test.ff_entry_dvld_0.clk) begin
ffq_clk_active = 1;
if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
$display(" en=%b fen=%b d=%b ev=%b",
test.flop_en_vld[0], test.ff_en_vld[0],
test.dvld[0], test.entry_vld[0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc<3) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (ffq_clk_active == 0) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
$display ("----");
$stop;
end
else if (err_code) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs");
$display ("----");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module llq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
/* verilator lint_off COMBDLY */
always @(clk or d)
if (clk == 1'b0)
qr <= d;
/* verilator lint_on COMBDLY */
assign q = qr;
endmodule
module ffq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
always @(posedge clk)
qr <= d;
assign q = qr;
endmodule
// DUT module
module Test (/*AUTOARG*/
// Outputs
ff_en_vld, entry_vld,
// Inputs
clk, dvld, ff_en_e1
);
input clk;
input [7:0] dvld;
input [7:0] ff_en_e1;
output [7:0] ff_en_vld;
output wire [7:0] entry_vld;
wire [7:0] gclk_vld;
wire [7:0] ff_en_vld /*verilator clock_enable*/;
reg [7:0] flop_en_vld;
always @(posedge clk) flop_en_vld <= ff_en_e1;
// clock gating
`ifdef GATED_CLK_TESTCASE
assign gclk_vld = {8{clk}} & ff_en_vld;
`else
assign gclk_vld = {8{clk}};
`endif
// latch for avoiding glitch on the clock gating control
llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld));
// flops that use the gated clock signal
ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0]));
ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1]));
ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2]));
ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3]));
ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4]));
ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5]));
ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6]));
ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7]));
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, pair<int, int> > > v[100005]; vector<int> ans; int n; bool has_cycle(int mid) { int indeg[100005]; int cnt = 0, x; memset(indeg, 0, sizeof(indeg)); for (int i = 1; i <= n; ++i) { for (auto g : v[i]) { if (g.second.first > mid) { indeg[g.first]++; } } } queue<int> q; for (int i = 1; i <= n; ++i) { if (indeg[i] == 0) { q.push(i); } } while (!q.empty()) { x = q.front(); cnt++; q.pop(); for (auto g : v[x]) { if (g.second.first > mid) { indeg[g.first]--; if (indeg[g.first] == 0) q.push(g.first); } } } if (cnt == n) return false; else return true; } void topological_sort(int res) { int indeg[100005]; int cnt = 0, x; memset(indeg, 0, sizeof(indeg)); for (int i = 1; i <= n; ++i) { for (auto g : v[i]) { if (g.second.first > res) { indeg[g.first]++; } } } queue<int> q; bool vis[100005]; memset(vis, false, sizeof(vis)); for (int i = 1; i <= n; ++i) { if (indeg[i] == 0) q.push(i); } while (!q.empty()) { x = q.front(); vis[x] = true; q.pop(); for (auto g : v[x]) { if (g.second.first > res) { indeg[g.first]--; if (indeg[g.first] == 0) q.push(g.first); } else { if (vis[g.first] == true) { ans.push_back(g.second.second); } } } } } bool check(int mid) { if (has_cycle(mid)) return false; else return true; } int binary_search() { int lo = 0, hi = 1e9; while (hi - lo > 1) { int mid = (lo + hi) / 2; if (check(mid)) hi = mid; else lo = mid; } if (check(lo)) return lo; return hi; } int main() { int m, x, y, c, res; cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> x >> y >> c; v[x].push_back({y, {c, i}}); } res = binary_search(); topological_sort(res); cout << res << << (int)ans.size() << n ; for (auto g : ans) cout << g << ; }
|
module midi_in(CLK, RES, MIDI_IN,
CH_MESSAGE,
CHAN, NOTE, VELOCITY, LSB, MSB //параметры сообщений
);
input wire CLK; // 50 MHz clock
input wire RES; // reset
input wire MIDI_IN; // MIDI in data
//note control
output reg [3:0] CHAN; // номер канала, в который отправляется нота. в ПО считаются от 1 до 16. тут считаются с 0. То есть барабаны - 10й, тут будет 9.
output reg [6:0] NOTE; // номер ноты 0 - это С-1, 12 - С0, 24 - С1
output reg [6:0] VELOCITY;
output reg [6:0] LSB;
output reg [6:0] MSB;
output reg [3:0] CH_MESSAGE;
reg [23:0] midi_command; //миди команда 3 байта
reg [7:0] rcv_state;
//состояние приемника
//0 - ожидаем любой байт
//1 - принят первый байт сообщения канала nnnn одно из сообщений ниже, и ждем еще двух байт данных, у которых старший бит = 0, иначе это реалтайм сообщения
// 1000nnnn - Note Off (Номер ноты(NOTE); Динамика(VELOCITY))
// 1001nnnn - Note On (Номер ноты(NOTE); Динамика(VELOCITY))
// 1010nnnn - Polyphonic Key Pressure (Номер ноты(NOTE); Давление(VELOCITY))
// 1011nnnn - Control Change (Номер контроллера(LSB); Значение контроллера(MSB))
// 1100nnnn - Program Change (Номер программы(LSB); -)
// 1101nnnn - Channel Pressure (Давление(LSB); -)
// 1110nnnn - Pitch Wheel Change (LSB;MSB)
//2 - принят второй байт сообщения канала
//3 - принят третий байт сообщения канала и переход в 0
reg [7:0] byte1;
reg [7:0] byte2;
reg [7:0] byte3;
initial begin
CHAN <= 4'b0000;
NOTE <= 7'd0;
VELOCITY <= 7'd0;
LSB <= 7'd0;
MSB <= 7'd0;
CH_MESSAGE <= 4'd0;
rcv_state <= 8'b00000000;
byte1 <= 8'd0;
byte2 <= 8'd0;
byte3 <= 8'd0;
end
//midi rx
//бодген - модуль для генерации клока UART
// first register:
// baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
//Greatest Common Divisor - наибольший общий делитель. http://www.alcula.com/calculators/math/gcd/
//baud_freq = 16*31250 / gcd(50000000, 50000) = 500000 / 500000 = 1
// second register:
// baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
//baud_limit = (50000000 / gcd(50000000, 500000)) - 1
// = ( 50000000 / 500000) - 1 = 99
wire port_clk;
wire [7:0] uart_command;
wire ucom_ready;
baud_gen BG( CLK, RES, port_clk, 1, 99);
uart_rx URX( CLK, RES, port_clk, MIDI_IN, uart_command, ucom_ready );
always @ (posedge CLK) begin
if (ucom_ready==1) begin
//Ожидаем сообщение
if (rcv_state==8'd0) begin
//если старший бит = 1, то это сообщение
//запоминаем байт
if (uart_command[7:7]==1'b1) byte1 <= uart_command;
//в любом случае сбрасываем выходы NOTE_ON, NOTE_OFF, NOTE, VELOCITY
CH_MESSAGE <= 4'd0;
CHAN <= 4'b0000;
NOTE <= 7'd0;
LSB <= 7'd00;
MSB <= 7'd00;
VELOCITY <= 7'd0;
//смена стейта
rcv_state <= ((uart_command[7:4]>=4'b1000)&&(uart_command[7:4]<=4'b1110)) ? 8'd01 : rcv_state;
end else if (rcv_state==8'd01) begin //ждем первый байт данных
//если старший бит = 0, то это данные
if (uart_command[7:7]==1'b0) byte2 <= uart_command;
//сменf стейта
rcv_state <= (uart_command[7:7]==1'b0) ? 8'd2 : rcv_state;
end else if (rcv_state==8'd02) begin //ждем второй байт данных
//если старший бит = 0, то это данные
if (uart_command[7:7]==1'b0) begin
byte3 = uart_command; // = вместо <= для присвоения сразу. чтобы все данные были сразу в byte1, 2, 3
//Обрабатываем три принятых байта
//номер канала (в первом байте, 4 младших бита)
CHAN <= byte1[3:0];
//декодируем сообщение
if ((byte1[7:4]==4'b1000)||(byte1[7:4]==4'b1001)||(byte1[7:4]==4'b1010)) begin //note off, note on, poly key pressure
CH_MESSAGE <= byte1[7:4];
//нота
NOTE <= byte2[6:0];
//значение velocity или pressure
VELOCITY <= byte3[6:0];
end else if ((byte1[7:4]==4'b1100)||(byte1[7:4]==4'b1101)) begin // Program change, Channel pressure
CH_MESSAGE <= byte1[7:4];
LSB <= byte2[6:0];
MSB <= 0;
end else if ((byte1[7:4]==4'b1011)||(byte1[7:4]==4'b1110)) begin
CH_MESSAGE <= byte1[7:4];
LSB <= byte2[6:0];
MSB <= byte3[6:0];
end
end
//смена стейта
rcv_state <= (uart_command[7:7]==1'b0) ? 8'd0 : rcv_state;
end
end //ucom_ready
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, l, r, c, ans; cin >> a >> b >> l >> r; c = l % (a + b); if (c > a) { ans = 1; l += (a + b - c + 1); if (l <= r) ans += min(a, r - l + 1); if (a > b) { l += (2 * b); if (l <= r) ans += min(a - b, r - l + 1); } } else { ans = min(a - c + 1, r - l + 1); l += (a - c + 1); if (l <= r) { ans++; l += b; if ((a <= b && a >= r - l + 1) || a > b) ans--; } if (l <= r) ans += min(c - 1, r - l + 1); l += (c - 1); if (a > b) { if ((a - c + 1) > (a - b)) { l += (b - c + 1); if (l <= r) ans += min(a - b, r - l + 1); } else { if (l <= r) ans += min(a - c + 1, r - l + 1); l += (a - c + 1); l += (b + b); if (l <= r) ans += min(c - b - 1, r - l + 1); } } } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int getRand(int l, int r) { uniform_int_distribution<int> uid(l, r); return uid(rng); } unordered_map<string, int> X; long long get_sum(long long n) { if (n == 1) { return 1; } return get_sum(n / 2) + n; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t, num; long long n, sum = 0, temp; string str; cin >> t; while (t--) { sum = 0; temp = 1; cin >> n; while (n > 0) { temp = 1; while (temp <= n) { temp *= 2; } sum += get_sum(temp / 2); n = n - (temp / 2); } cout << sum << endl; } }
|
#include <bits/stdc++.h> using namespace std; int v, m, d, f; int main() { int n, a, b, c; cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b >> c; if (a == 1) { v += b; m += c; } else { d += b; f += c; } } if (v >= m) cout << LIVE << n ; else cout << DEAD << n ; if (d >= f) cout << LIVE << n ; else cout << DEAD << n ; return 0; }
|
`timescale 1ns / 1ps
module display_data(
input clk,
input [15:0] decimal_nybble,
output reg [3:0] seg_an_reg,
output reg [7:0] seg_cat_reg
);
integer slowdown;
reg [1:0] state;
//reg [3:0] seg_an_reg;
//reg [7:0] seg_cat_reg;
integer ID;
integer digit;
integer dig0;
integer dig1;
integer dig2;
integer dig3;
integer temp0;
integer temp1;
initial begin
slowdown = 0;
state = 0;
digit = 0;
dig0 = 0;
dig1 = 0;
dig2 = 0;
dig3 = 0;
ID = 0;
seg_an_reg = 4'b0000;
seg_cat_reg = 8'b00000000;
end
//assign seg_an = seg_an_reg;
//assign seg_cat = seg_cat_reg;
//TODO: Calculate digits from data
always @(decimal_nybble) begin
dig3 <= decimal_nybble[15:12];
dig2 <= decimal_nybble[11:8];
dig1 <= decimal_nybble[7:4];
dig0 <= decimal_nybble[3:0];
end
always @(posedge clk) begin
if(slowdown==200000) begin //only update once every 200000 clock cycles
//seg_an_reg <= 4'b1111; //clear anodes (no digit active)
case(state) //choose a new active digit
2'd0: begin
digit = dig0;
seg_an_reg[0] <= 0;
seg_an_reg[1] <= 1;
seg_an_reg[2] <= 1;
seg_an_reg[3] <= 1;
end
2'd1: begin
digit = dig1;
seg_an_reg[0] <= 1;
seg_an_reg[1] <= 0;
seg_an_reg[2] <= 1;
seg_an_reg[3] <= 1;
end
2'd2: begin
digit = dig2;
seg_an_reg[0] <= 1;
seg_an_reg[1] <= 1;
seg_an_reg[2] <= 0;
seg_an_reg[3] <= 1;
end
2'd3: begin
digit = dig3;
seg_an_reg[0] <= 1;
seg_an_reg[1] <= 1;
seg_an_reg[2] <= 1;
seg_an_reg[3] <= 0;
end
endcase
case(digit)
'd0: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 1;
seg_cat_reg[7] = 1;
end
'd1: begin
seg_cat_reg[0] = 1;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 1;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 1;
seg_cat_reg[7] = 1;
end
'd2: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 1;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd3: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd4: begin
seg_cat_reg[0] = 1;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 1;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd5: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 1;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd6: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 1;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd7: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 1;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 1;
seg_cat_reg[6] = 1;
seg_cat_reg[7] = 1;
end
'd8: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 0;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
'd9: begin
seg_cat_reg[0] = 0;
seg_cat_reg[1] = 0;
seg_cat_reg[2] = 0;
seg_cat_reg[3] = 0;
seg_cat_reg[4] = 1;
seg_cat_reg[5] = 0;
seg_cat_reg[6] = 0;
seg_cat_reg[7] = 1;
end
endcase
case(state)
2'd3: state <= 0;
default: state <= state + 1;
endcase
slowdown <= 0;
end else slowdown <= slowdown + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void Solve() { int n; string a, b; cin >> n >> a >> b; a = - + a + - ; b = - + b + - ; int val = 0; for (int i = 1; i <= n; i++) { if (a[i] != b[i]) val += 2; else if (a[i] == 0 ) { val++; if (a[i - 1] == 1 && b[i - 1] == 1 ) val++; else if (a[i + 1] == 1 && b[i + 1] == 1 ) { val++; a[i + 1] = b[i + 1] = - ; } } } cout << val << endl; } int main() { int t; cin >> t; while (t--) Solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND3_PP_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long t[5005], c[5005], ans[5005], n, i, l, b, v; int main() { cin >> n; for (i = 1; i <= n; i++) cin >> t[i]; for (l = 1; l <= n; l++) { for (i = 1; i <= n; i++) c[i] = 0; b = 0; for (i = l; i <= n; i++) { v = t[i]; c[v]++; if (c[v] > c[b] || (c[v] == c[b] && v < b)) b = v; ans[b]++; } } for (i = 1; i <= n - 1; i++) cout << ans[i] << ; cout << ans[n] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 4010; int N; long long V[MAXN], D[MAXN], P[MAXN]; set<int> st; int main() { if (fopen( input.txt , r )) { freopen( input.txt , r , stdin); } ios::sync_with_stdio(false); cin >> N; for (int i = 1; i <= N; i++) { cin >> V[i] >> D[i] >> P[i]; st.insert(i); } vector<int> ans; while (!st.empty()) { int b = *st.begin(); ans.push_back(b); st.erase(st.begin()); long long val = V[b]; for (int i : st) { P[i] -= val; val--; if (val == 0) { break; } } for (auto it = st.begin(); it != st.end();) { int i = *it; if (P[i] >= 0) { it++; continue; } st.erase(it++); for (auto jt = it; jt != st.end(); jt++) { P[*jt] -= D[i]; } } } cout << ans.size() << endl; for (int i : ans) { cout << i << ; } }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n = 0; cin >> n; vector<int> ans; int k = 0; if (n == 1) { cout << 1 << endl << 1; return 0; } for (int i = 1; i <= n; i++) { ans.push_back(i); if (n - i >= 0) n -= i; else break; } if (n == 0) { cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; } else { cout << ans.size() << endl; sort(ans.begin(), ans.end()); for (int i = 0; i < ans.size() - 1; i++) cout << ans[i] << ; cout << ans[ans.size() - 1] + n; return 0; } }
|
#include <bits/stdc++.h> const int N = 157, inf = 1e9 + 500; int n, m, del, t, dis[N]; int ans = inf; std::queue<int> q; struct node { int u, v, w; bool operator<(const node &a) const { return w < a.w; } } e[N]; inline int read() { int x = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) x = (x << 3) + (x << 1) + c - 48, c = getchar(); return x; } struct matrix { std::bitset<N> v[N]; matrix() { for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) v[i][j] = 0; } void I() { for (int i = 1; i <= n; ++i) v[i][i] = 1; } friend matrix operator*(matrix a, matrix b) { matrix ret; for (int i = 1; i <= n; ++i) { for (int k = 1; k <= n; ++k) { if (a.v[i][k]) ret.v[i] |= b.v[k]; } } return ret; } } a, g; matrix qp(matrix base, int p) { matrix ret; ret.I(); while (p) { if (p & 1) ret = ret * base; base = base * base; p >>= 1; } return ret; } void bfs() { while (!q.empty()) q.pop(); for (int i = 1; i <= n; ++i) dis[i] = inf; for (int i = 1; i <= n; ++i) if (a.v[1][i]) q.push(i), dis[i] = 0; while (!q.empty()) { int u = q.front(); q.pop(); for (int v = 1; v <= n; ++v) { if (g.v[u][v] && dis[v] == inf) { dis[v] = dis[u] + 1; q.push(v); } } } } int main() { n = read(), m = read(); for (int i = 1; i <= m; ++i) e[i].u = read(), e[i].v = read(), e[i].w = read(); std::sort(e + 1, e + 1 + m); a.v[1][1] = 1; dis[n] = inf; for (int i = 1; i <= m; ++i) { if (ans < e[i].w) break; del = e[i].w - t; t = e[i].w; a = a * qp(g, del); g.v[e[i].u][e[i].v] = 1; if (i == m || e[i + 1].w != e[i].w) bfs(); ans = std::min(ans, dis[n] + t); } if (ans == inf) puts( Impossible ); else printf( %d n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_LP_V
`define SKY130_FD_SC_LP__NAND3_LP_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_lp (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_lp (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_LP_V
|
#include <bits/stdc++.h> using namespace std; const int mod = int(1e9 + 7); const double PI = acos(-1.0); const int N = 200000; long long n, a; long long p[N], b[N]; bool check(int x) { long long i, m; m = a; for (i = 0; i < x; i++) if (b[n - x + i] < p[i]) m -= p[i] - b[n - x + i]; return (m >= 0); } int main() { long long m, l, r, i; cin >> n >> m >> a; for (i = 0; i < n; i++) cin >> b[i]; for (i = 0; i < m; i++) cin >> p[i]; sort(b, b + n); sort(p, p + m); l = 0; r = min(n, m); while (l < r) { m = (l + r + 1) / 2; if (check(m)) l = m; else r = m - 1; } m = 0; for (i = 0; i < l; i++) m += p[i]; cout << l << << max(0ll, m - a); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 111111; int N; char s[MAX]; int f[MAX]; int sum[MAX]; bool match(int i, int j) { if (i < 1 || j < 1) return 0; if (s[i - 1] == ) ) return s[j - 1] == ( ; else return s[j - 1] == [ ; } int get(int i) { return f[i - 1] < N ? f[i - 1] : i; } int main() { int i, j, k; while (cin >> s) { N = strlen(s); sum[0] = 0; for (i = 1; i <= N; ++i) sum[i] = sum[i - 1] + (s[i - 1] == ] ); memset(f, 127, sizeof f); for (i = 2; i <= N; ++i) { if (s[i - 1] == ( || s[i - 1] == [ ) continue; if (match(i, i - 1)) f[i] = get(i - 1); if (f[i - 1] < N && match(i, f[i - 1] - 1)) f[i] = min(f[i], get(f[i - 1] - 1)); } int ans = 0, ansi; for (i = 1; i <= N; ++i) if (f[i] < N && sum[i] - sum[f[i] - 1] > ans) { ans = sum[i] - sum[f[i] - 1]; ansi = i; } printf( %d n , ans, ansi); if (ans > 0) { for (i = f[ansi] - 1; i < ansi; ++i) putchar(s[i]); } puts( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; int dp[maxn], num[30]; int main() { int i, j, k, n, m, t, l, ans, x, y, z; char s[maxn]; scanf( %d , &t); while (t--) { scanf( %d%d%d , &n, &m, &k); scanf( %s , s); ans = 1e9; memset(num, 0, sizeof(num)); for (i = 0; i < k; i++) { num[s[i] - A + 1]++; } for (l = 1; l <= 26; l++) { if (num[l] == 0) continue; for (i = 0; i <= k; i++) dp[i] = 0; dp[0] = 1; for (i = 1; i <= 26; i++) { if (num[i] == 0 || i == l) continue; for (j = k; j >= num[i]; j--) if (dp[j - num[i]] == 1) dp[j] = 1; } for (i = 0; i <= k; i++) { if (dp[i] == 1) { if (i + num[l] >= n) { x = max(0, n - i); z = k - num[l] - i; if (z + num[l] - x >= m) { y = max(0, m - z); ans = min(ans, x * y); } } } } } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> ostream& operator<<(ostream& os, const pair<T1, T2>& v) { os << ( << v.first << << v.second << ) ; return os; } template <typename T, typename U = typename T::value_type, typename = typename enable_if<!is_same<T, string>::value>::type> ostream& operator<<(ostream& os, const T& v) { os << [ ; for (const auto& it : v) os << it << ; if (!v.empty()) os << b ; os << ] ; return os; } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); int n, x; cin >> n; int cnt[6] = {0, 0, 0, 0, 0, 0}; for (int i = 0; i < (n); i++) { cin >> x; if (x == 4) { cnt[0]++; continue; } if (x == 8 && cnt[0]) { cnt[0]--; cnt[1]++; continue; } if (x == 15 && cnt[1]) { cnt[1]--; cnt[2]++; continue; } if (x == 16 && cnt[2]) { cnt[2]--; cnt[3]++; continue; } if (x == 23 && cnt[3]) { cnt[3]--; cnt[4]++; continue; } if (x == 42 && cnt[4]) { cnt[4]--; cnt[5]++; continue; } } cout << n - 6 * cnt[5] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; char c[503][503]; vector<pair<int, int> > v[503][503]; int main() { int n, m, k; cin >> n >> m >> k; int s = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> c[i][j]; if (c[i][j] == . ) s++; } } pair<int, int> st; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (c[i][j] == . ) { st.first = i; st.second = j; if (c[i - 1][j] == c[i][j]) { v[i][j].push_back(make_pair(i - 1, j)); } if (c[i + 1][j] == c[i][j]) { v[i][j].push_back(make_pair(i + 1, j)); } if (c[i][j - 1] == c[i][j]) { v[i][j].push_back(make_pair(i, j - 1)); } if (c[i][j + 1] == c[i][j]) { v[i][j].push_back(make_pair(i, j + 1)); } } } } queue<pair<int, int> > q; q.push(st); int num = s - k; if (num) { c[st.first][st.second] = q ; num--; } while (!q.empty()) { pair<int, int> tp = q.front(); q.pop(); for (pair<int, int> kom : v[tp.first][tp.second]) { if (c[kom.first][kom.second] == . && num > 0) { c[kom.first][kom.second] = q ; num--; q.push(make_pair(kom.first, kom.second)); } } } for (int i = 1; i < n + 1; i++) { for (int j = 1; j <= m; j++) { if (c[i][j] == q ) cout << . ; else if (c[i][j] == . && k) cout << X ; else cout << c[i][j]; } cout << endl; } }
|
//
// chrgen.v -- character generator
//
module chrgen(clk, pixclk,
chrcode, chrrow, chrcol,
pixel,
attcode_in, blank_in, hsync_in, vsync_in, blink_in,
attcode_out, blank_out, hsync_out, vsync_out, blink_out);
input clk;
input pixclk;
input [7:0] chrcode;
input [3:0] chrrow;
input [2:0] chrcol;
output pixel;
input [7:0] attcode_in;
input blank_in;
input hsync_in;
input vsync_in;
input blink_in;
output reg [7:0] attcode_out;
output reg blank_out;
output reg hsync_out;
output reg vsync_out;
output reg blink_out;
wire [13:0] addr;
wire [0:0] pixel_lo;
wire [0:0] pixel_hi;
reg mux_ctrl;
assign addr[13:7] = chrcode[6:0];
assign addr[6:3] = chrrow[3:0];
assign addr[2:0] = chrcol[2:0];
assign pixel = (mux_ctrl == 0) ? pixel_lo[0] : pixel_hi[0];
// RAMB16_S1: Spartan-3 16kx1 Single-Port RAM
RAMB16_S1 character_rom_lo (
.DO(pixel_lo), // 1-bit Data Output
.ADDR(addr), // 14-bit Address Input
.CLK(clk), // Clock
.DI(1'b0), // 1-bit Data Input
.EN(pixclk), // RAM Enable Input
.SSR(1'b0), // Synchronous Set/Reset Input
.WE(1'b0) // Write Enable Input
);
`include "chrgenlo.init"
// RAMB16_S1: Spartan-3 16kx1 Single-Port RAM
RAMB16_S1 character_rom_hi (
.DO(pixel_hi), // 1-bit Data Output
.ADDR(addr), // 14-bit Address Input
.CLK(clk), // Clock
.DI(1'b0), // 1-bit Data Input
.EN(pixclk), // RAM Enable Input
.SSR(1'b0), // Synchronous Set/Reset Input
.WE(1'b0) // Write Enable Input
);
`include "chrgenhi.init"
always @(posedge clk) begin
if (pixclk == 1) begin
attcode_out[7:0] <= attcode_in[7:0];
blank_out <= blank_in;
hsync_out <= hsync_in;
vsync_out <= vsync_in;
blink_out <= blink_in;
mux_ctrl <= chrcode[7];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, r; long long A[1000005], sum; int main() { scanf( %d %d , &n, &r); for (int i = (0); i < (1 << n); i++) scanf( %lld , &A[i]), sum += A[i]; printf( %.12lf n , 1.0 * sum / (1 << n)); for (int i = (0); i < (r); i++) { int x; long long y; scanf( %d %lld , &x, &y); sum += y - A[x]; A[x] = y; printf( %.12lf n , 1.0 * sum / (1 << n)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; char a[5]; char s1[3], s2[3]; void solve() { int i, vt, kq1, kq2; scanf( %d , &n); n = n % 4; a[0] = v ; a[1] = < ; a[2] = ^ ; a[3] = > ; for (i = 0; i < 4; i++) if (a[i] == s1[0]) vt = i; kq1 = 0; kq2 = 0; if (a[(vt + n) % 4] == s2[0]) kq1 = 1; if (a[(vt - n + 4) % 4] == s2[0]) kq2 = 1; if (kq1 == 1 && kq2 == 0) printf( cw n ); if (kq1 == 0 && kq2 == 1) printf( ccw n ); if ((kq1 == 0 && kq2 == 0) || (kq1 == 1 && kq2 == 1)) printf( undefined n ); } int main() { while (scanf( %s %s , &s1, &s2) > 0) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace ioput { template <typename T> T read() { T x = 0, f = 1; char c = getchar_unlocked(); while ((c < 0 ) || (c > 9 )) { if (c == - ) f = -1; c = getchar_unlocked(); } while ((c >= 0 ) && (c <= 9 )) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar_unlocked(); return x * f; } template <typename T> void write(T x, char c) { static char t[20]; static int tlen; t[tlen = 1] = c; if (x < 0) putchar_unlocked( - ), x = -x; do t[++tlen] = x % 10 + 0 , x /= 10; while (x); while (tlen) putchar_unlocked(t[tlen--]); } } // namespace ioput using namespace ioput; const int maxn = 100005; struct seg { int id, pos, t; bool operator<(const seg &A) const { return pos - t == A.pos - A.t ? pos < A.pos : pos - t < A.pos - A.t; } } a[maxn], b[maxn], tmp[maxn]; int a_cnt, b_cnt; int p[maxn], n, W, H; pair<int, int> ans[maxn]; int main() { n = read<int>(), W = read<int>(), H = read<int>(); int type, pos, t; for (int i = 1, iend = n; i <= iend; ++i) { type = read<int>(), pos = read<int>(), t = read<int>(); if (type == 1) a[++a_cnt] = (seg){i, pos, t}; else b[++b_cnt] = (seg){i, pos, t}; } sort(a + 1, a + 1 + a_cnt); sort(b + 1, b + 1 + b_cnt); int cur = 1; for (int i = 1, iend = a_cnt; i <= iend; ++i) { static stack<int> stk; int j = i; while ((j < a_cnt) && (a[j + 1].pos - a[j + 1].t == a[i].pos - a[i].t)) ++j; int pos = j, tmpcur; while ((cur <= b_cnt) && (b[cur].pos - b[cur].t < a[i].pos - a[i].t)) ++cur; tmpcur = cur; for (int k = j, kend = i; k >= kend; --k) stk.push(a[k].id); while ((cur <= b_cnt) && (b[cur].pos - b[cur].t == a[i].pos - a[i].t)) stk.push(b[cur].id), ++cur; for (int k = i, kend = j; k <= kend; ++k) a[k].id = stk.top(), stk.pop(); for (int k = cur - 1, kend = tmpcur; k >= kend; --k) b[k].id = stk.top(), stk.pop(); i = j; } for (int i = 1, iend = a_cnt; i <= iend; ++i) ans[a[i].id] = make_pair(a[i].pos, H); for (int i = 1, iend = b_cnt; i <= iend; ++i) ans[b[i].id] = make_pair(W, b[i].pos); for (int i = 1, iend = n; i <= iend; ++i) printf( %d %d n , ans[i].first, ans[i].second); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[1005]; int main() { int i, t, mini = 1000000, s, val, tfin; cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; for (t = 1; t <= 105; t++) { s = 0; for (i = 1; i <= n; i++) { val = abs(t + 1 - a[i]); val = min(val, abs(t - a[i])); val = min(val, abs(t - 1 - a[i])); s += val; } if (mini > s) { mini = s; tfin = t; } } cout << tfin << << mini; return 0; }
|
/*
* Copyright (c) 2000 Intrinsity, Inc.
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test_pmos ();
reg gnd, vdd, x, z;
wire t0, t1, t2, t3, t4, t5, t6, t7,
t8, t9, ta, tb, tc, td, te, tf;
wire StH, StL;
assign (strong1, highz0) StH = 1'bx;
assign (highz1, strong0) StL = 1'bx;
reg failed;
pmos n0 ( t0, gnd, gnd);
pmos n1 ( t1, gnd, vdd);
pmos n2 ( t2, gnd, x);
pmos n3 ( t3, gnd, z);
pmos n4 ( t4, vdd, gnd);
pmos n5 ( t5, vdd, vdd);
pmos n6 ( t6, vdd, x);
pmos n7 ( t7, vdd, z);
pmos n8 ( t8, x, gnd);
pmos n9 ( t9, x, vdd);
pmos na ( ta, x, x);
pmos nb ( tb, x, z);
pmos nc ( tc, z, gnd);
pmos nd ( td, z, vdd);
pmos ne ( te, z, x);
pmos nf ( tf, z, z);
initial begin
assign gnd = 1'b1;
assign vdd = 1'b0;
assign x = 1'b0;
assign z = 1'b0;
#10;
assign gnd = 1'b0;
assign vdd = 1'b1;
assign x = 1'b1;
assign z = 1'b1;
#10;
assign gnd = 1'b0;
assign vdd = 1'b1;
assign x = 1'bx;
assign z = 1'bz;
#10;
failed = 0;
if (t0 !== gnd)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:0", gnd, gnd, t0 );
end
if (t1 !== z)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:z", gnd, vdd, t1 );
end
if (t2 !== StL)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:StL", gnd, x, t2 );
end
if (t3 !== StL)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:StL", gnd, z, t3 );
end
if (t4 !== 1'b1)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:1", vdd, gnd, t4 );
end
if (t5 !== z)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:z", vdd, vdd, t5 );
end
if (t6 !== StH)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:StH", vdd, x, t6 );
end
if (t7 !== StH)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:StH", vdd, z, t7 );
end
if (t8 !== 1'bx)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:x", x, gnd, t8 );
end
if (t9 !== 1'bz)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:z", x, vdd, t9 );
end
if (ta !== 1'bx)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:x", x, x, ta );
end
if (tb !== 1'bx)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:x", x, z, tb );
end
if (tc !== 1'bz)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:z", z, gnd, tc );
end
if (td !== 1'bz)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:z", z, vdd, td );
end
if (te !== 1'bz)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:z", z, x, te );
end
if (tf !== 1'bz)
begin
failed = 1;
$display ("FAILED: pmos s:%d g:%d d:%d expected:z", z, z, tf );
end
if (failed == 0)
$display ("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int dpr[300005]; int dpl[300005]; int A[300005]; pair<int, int> B[300005]; int fr(int pos) { if (A[pos] == 0) return pos - 1; if (pos == n - 1) return n - 1; if (dpr[pos] != -1) return dpr[pos]; dpr[pos] = fr(pos + 1); return dpr[pos]; } int fl(int pos) { if (A[pos] == 0) return pos + 1; if (pos == 0) return 0; if (dpl[pos] != -1) return dpl[pos]; dpl[pos] = fl(pos - 1); return dpl[pos]; } int main() { int k; cin >> n >> k; memset(dpl, -1, sizeof dpl); memset(dpr, -1, sizeof dpr); int maxx = 0; int coun = 0; for (int i = 0; i < n; i++) { cin >> A[i]; if (A[i] == 0) { if (coun > maxx) { maxx = coun; } coun = 0; } else { coun++; } } if (coun > maxx) maxx = coun; coun = maxx; vector<int> C; for (int i = 0; i < n; i++) { if (A[i] == 0) { if (i == 0) { B[i].first = 0; B[i].second = fr(i + 1); } else if (i == n - 1) { B[i].second = n - 1; B[i].first = fl(i - 1); } else { B[i].first = fl(i - 1); B[i].second = fr(i + 1); } C.push_back(i); } } int sta = 0; int fin = k - 1; int a; int smax = 0; while ((fin < C.size()) && (k > 0) && (C.size() > 0)) { a = (C[fin] - C[sta] + 1) + (C[sta] - B[C[sta]].first) + (B[C[fin]].second - C[fin]); if (a > maxx) { maxx = a; smax = B[C[sta]].first; } sta++; fin++; } if ((sta < C.size()) && (C.size() > 0) && (k > 0)) { a = n - C[sta] + (C[sta] - B[C[sta]].first); if (a > maxx) { maxx = a; smax = B[C[sta]].first; } } cout << maxx << endl; if (coun != maxx) { for (int i = smax; i < smax + maxx; i++) { A[i] = 1; } } for (int i = 0; i < n - 1; i++) { cout << A[i] << ; } cout << A[n - 1] << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:36 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: rx_stream.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// RX_STREAM
//
//
// Description: The RX_LL module receives data from the Aurora Channel,
// converts it to a simple streaming format. This module expects
// all data to be carried in a single, infinite frame, and it
// expects the data data in lanes to be all valid or all invalid
//
// This module supports 1 2-byte lane designs.
//
//
`timescale 1 ns / 10 ps
module aurora_201_RX_STREAM
(
// LocalLink PDU Interface
RX_D,
RX_SRC_RDY_N,
// Global Logic Interface
START_RX,
// Aurora Lane Interface
RX_PAD,
RX_PE_DATA,
RX_PE_DATA_V,
RX_SCP,
RX_ECP,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
output [0:15] RX_D;
output RX_SRC_RDY_N;
// Global Logic Interface
input START_RX;
// Aurora Lane Interface
input RX_PAD;
input [0:15] RX_PE_DATA;
input RX_PE_DATA_V;
input RX_SCP;
input RX_ECP;
// System Interface
input USER_CLK;
//************************Register Declarations********************
reg infinite_frame_started_r;
//***********************Main Body of Code*************************
//Don't start presenting data until the infinite frame starts
always @(posedge USER_CLK)
if(!START_RX)
infinite_frame_started_r <= `DLY 1'b0;
else if(RX_SCP > 1'd0)
infinite_frame_started_r <= `DLY 1'b1;
assign RX_D = RX_PE_DATA;
assign RX_SRC_RDY_N = !(RX_PE_DATA_V && infinite_frame_started_r);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100050; const int inf = 0x3f3f3f3f; struct Edge { int v, w; }; vector<Edge> G[maxn]; bool vis[maxn]; vector<int> st; int dep[maxn], f[maxn][20]; long long dis[maxn]; void dfs(int x, int par, long long sum) { f[x][0] = par; dep[x] = dep[par] + 1; dis[x] = sum; vis[x] = true; for (int i = 1; f[x][i - 1]; ++i) f[x][i] = f[f[x][i - 1]][i - 1]; for (auto e : G[x]) { int v = e.v; if (v != par && vis[v]) { st.push_back(v), st.push_back(x); } if (v != par && !vis[v]) dfs(v, x, sum + e.w); } } int lca(int x, int y) { if (dep[x] < dep[y]) swap(x, y); int h = dep[x] - dep[y]; for (int i = 0; h; ++i) { if (h & (1 << i)) { x = f[x][i]; h ^= (1 << i); } } if (x == y) return x; for (int i = 17; i >= 0; --i) { if (f[x][i] != f[y][i]) x = f[x][i], y = f[y][i]; } return f[x][0]; } long long Dis(int x, int y) { int z = lca(x, y); return dis[x] + dis[y] - dis[z] * 2; } struct Dijkstra { long long d[maxn]; struct node { int x; long long d; node(int x = 0, long long d = 0) : x(x), d(d) {} bool operator<(const node& t) const { return d > t.d; } }; void run(int s) { memset(d, 0x3f, sizeof d); memset(vis, false, sizeof vis); priority_queue<node> q; q.push(node(s, 0)), d[s] = 0; while (!q.empty()) { node u = q.top(); q.pop(); if (vis[u.x]) continue; vis[u.x] = true; for (auto e : G[u.x]) { int v = e.v; if (!vis[v] && d[v] > u.d + e.w) { d[v] = u.d + e.w; q.push(node(v, d[v])); } } } } } dij[50]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; ++i) { int x, y, w; scanf( %d%d%d , &x, &y, &w); G[x].push_back({y, w}); G[y].push_back({x, w}); } dfs(1, 0, 0); sort(st.begin(), st.end()); int sz = unique(st.begin(), st.end()) - st.begin(); while (st.size() > sz) st.pop_back(); for (int i = 0; i < sz; ++i) { dij[i].run(st[i]); } int q; scanf( %d , &q); while (q--) { int u, v; scanf( %d%d , &u, &v); long long ans = Dis(u, v); for (int i = 0; i < sz; ++i) ans = min(ans, dij[i].d[u] + dij[i].d[v]); printf( %lld n , ans); } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_in (
// data interface
rx_clk,
rx_data_in_p,
rx_data_in_n,
rx_data_p,
rx_data_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
// parameters
parameter SINGLE_ENDED = 0;
parameter DEVICE_TYPE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
// data interface
input rx_clk;
input rx_data_in_p;
input rx_data_in_n;
output rx_data_p;
output rx_data_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg rx_data_n;
// internal signals
wire rx_data_n_s;
wire rx_data_ibuf_s;
wire rx_data_idelay_s;
// delay controller
generate
if (IODELAY_CTRL == 1) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end else begin
assign delay_locked = 1'b1;
end
endgenerate
// receive data interface, ibuf -> idelay -> iddr
generate
if (SINGLE_ENDED == 1) begin
assign tx_data_out_n = 1'b0;
IBUF i_rx_data_ibuf (
.I (rx_data_in_p),
.O (rx_data_ibuf_s));
end else begin
IBUFDS i_rx_data_ibuf (
.I (rx_data_in_p),
.IB (rx_data_in_n),
.O (rx_data_ibuf_s));
end
endgenerate
if (DEVICE_TYPE == VIRTEX6) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.RST (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end else begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("ASYNC"))
i_rx_data_iddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n_s));
always @(posedge rx_clk) begin
rx_data_n <= rx_data_n_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, h, a, b, k, t1, f1, t2, f2; scanf( %lld%lld%lld%lld%lld , &n, &h, &a, &b, &k); while (k--) { scanf( %lld%lld%lld%lld , &t1, &f1, &t2, &f2); if (t1 == t2) printf( %lld n , abs(f2 - f1)); else { long long int ans = abs(t1 - t2); if (f1 > b) { ans += f1 - b; f1 = b; } else if (f1 < a) { ans += a - f1; f1 = a; } ans += abs(f2 - f1); printf( %lld n , ans); } } return 0; }
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#include <bits/stdc++.h> using namespace std; unsigned long long power(unsigned long long x, unsigned long long y) { if (y == 0) return 1; unsigned long long tmp = power(x, y / 2); tmp *= tmp; if (y % 2) tmp *= x; return tmp; } unsigned long long get(unsigned long long n) { if (n <= 9) return n; unsigned long long cnt, temp, d = 0; unsigned long long tmp = n; while (tmp / 10) { tmp /= 10; d++; } stringstream s; s << n; string str = s.str(); unsigned long long x = str[0] - 0 ; temp = power(10, d); n -= (str[0] - 0 ) * temp; n /= 10; if (str[0] <= str[str.size() - 1]) cnt = n + 1; else cnt = n; cnt += ((power(10, d - 1)) * (x - 1)); return cnt + get(power(10, d) - 1); } int main() { unsigned long long l, r; cin >> l >> r; cout << get(r) - get(l - 1) << endl; }
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//#pragma GCC target ( avx2 ) //#pragma GCC optimization ( O3 ) //#pragma GCC optimization ( unroll-loops ) #include<bits/stdc++.h> //#include <ext/pb_ds/assoc_container.hpp> //#include <ext/pb_ds/tree_policy.hpp> //using namespace __gnu_pbds; #define eps 1e-8 #define eq(x,y) (fabs((x)-(y)) < eps) using namespace std; typedef long long ll; typedef long double ld; typedef pair<int,int>pii; const ll mod= 998244353; long double PI = acosl(-1); const ll infl = 1e17+100; const int inf = 1e9+100; const int nmax = 3e5+5; //const int MAXLG = log2(nmax)+1; //mt19937 rng(chrono::system_clock::now().time_since_epoch().count()); //typedef tree< int, null_type, less<int>, rb_tree_tag, tree_order_statistics_node_update> ost; bool vis[nmax]; vector<int>g[nmax]; void dfs(int u){ vis[u] = true; for(int v : g[u]) if(!vis[v]) dfs(v); } int main(){ ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tc; cin>>tc; while(tc--){ int n,m; cin>>n>>m; for(int i=0; i<m; i++){ int u,v; cin>>u>>v; g[u].push_back(v); g[v].push_back(u); } bool hoise = false; bool unposibol = false; for(int i=1; i<=n; i++){ if(!vis[i]){ if(!hoise){ dfs(i); hoise = true; } else unposibol = true; } } if(unposibol) cout<< NO n ; else{ cout<< YES n ; for(int i=1; i<=n; i++) vis[i] = false; vector<int>ans; set<int>st; st.insert(1); while(st.size()){ int u = *st.begin(); st.erase(u); if(vis[u]) continue; vis[u] = true; ans.push_back(u); vector<int>tmp; for(int v : g[u]) if(!vis[v]){ vis[v] = true; tmp.push_back(v); } for(int v : tmp){ for(int z : g[v]) if(!vis[z]){ st.insert(z); } } } cout<<ans.size()<< n ; for(int x : ans) cout<<x<< ; cout<< n ; } for(int i=1; i<=n; i++) vis[i] = false, g[i].clear(); } } /* */
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