text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; const int c = 100005; void solve() { string s; cin >> s; long long o = 0, e = 0, m = 0; long long ans = INT_MAX; long long om = 5, em = 5; for (long long i = 0; i < s.size(); ++i) { if (i & 1) { if (s[i] == ? or s[i] == 1 ) o += 1; om -= 1; } else { if (s[i] == 1 ) e += 1; em -= 1; } if ((o > e + em) or (e > o + om)) { ans = min(ans, i + 1); break; } } om = 5; em = 5; o = e = 0; for (long long i = 0; i < s.size(); ++i) { if (i & 1) { if (s[i] == 1 ) o += 1; om -= 1; } else { if (s[i] == 1 or s[i] == ? ) e += 1; em -= 1; } if ((o > e + em) or (e > o + om)) { ans = min(ans, i + 1); break; } } if (ans == INT_MAX) ans = 10; cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long t; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100005]; int main() { int n, x; cin >> n >> x; long int sum = 0, zz; for (int i = 0; i < n; i++) cin >> zz, sum += zz; if (sum + n - 1 == x) cout << YES n ; else cout << NO n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_16_V
`define SKY130_FD_SC_HD__BUF_16_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_16_V
|
// usb_tx_fifo.v
`timescale 1 ns / 1 ps
module usb_tx_fifo
(
input reset,
input wrclk,
input write,
input [15:0]din,
input [1:0]min,
output full,
input rdclk,
input read,
output [15:0]dout,
output [1:0]mout,
output empty
);
wire [17:0]data = { min, din };
wire [17:0]q;
assign {mout, dout} = q;
dcfifo dcfifo_component
(
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (write),
.aclr (reset),
.data (data),
.rdreq (read),
.wrfull (full),
.q (q),
.rdempty (empty),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
);
defparam
dcfifo_component.intended_device_family = "Cyclone III",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 18,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// Retrieval info: LIB_FILE: altera_mf
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module RAMB16_S1_S9 (
CLKA, CLKB, ENB, WEA, WEB, ENA, SSRA, SSRB, DIPB, ADDRA, ADDRB, DIA, DIB, DOA, DOB, DOPB
);
input wire CLKA;
input wire CLKB;
output reg [7 : 0] DOB;
output reg [0 : 0] DOA;
input wire [0 : 0] WEA;
input wire [0 : 0] WEB;
input wire [10 : 0] ADDRB;
input wire [13 : 0] ADDRA;
input wire [7 : 0] DIB;
input wire [0 : 0] DIA;
input wire ENB;
input wire ENA;
input wire SSRA;
input wire SSRB;
input wire DIPB;
output wire DOPB;
parameter WIDTHA = 1;
parameter SIZEA = 16384;
parameter ADDRWIDTHA = 14;
parameter WIDTHB = 8;
parameter SIZEB = 2048;
parameter ADDRWIDTHB = 11;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
`include "../includes/log2func.v"
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = `CLOG2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
always @(posedge CLKA)
if (WEA)
RAM[ADDRA] <= DIA;
else
DOA <= RAM[ADDRA];
genvar i;
generate for (i = 0; i < RATIO; i = i+1)
begin: portA
localparam [log2RATIO-1:0] lsbaddr = i;
always @(posedge CLKB)
if (WEB)
RAM[{ADDRB, lsbaddr}] <= DIB[(i+1)*minWIDTH-1:i*minWIDTH];
else
DOB[(i+1)*minWIDTH-1:i*minWIDTH] <= RAM[{ADDRB, lsbaddr}];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> struct Point { T x, y; Point() {} Point(T x_, T y_) : x(x_), y(y_) {} using pair = std::pair<T, T>; explicit operator pair() const { return pair(x, y); } friend bool operator==(const Point& a, const Point& b) { return pair(a) == pair(b); } friend bool operator!=(const Point& a, const Point& b) { return pair(a) != pair(b); } friend bool operator<(const Point& a, const Point& b) { return pair(a) < pair(b); } friend bool operator<=(const Point& a, const Point& b) { return pair(a) <= pair(b); } friend bool operator>(const Point& a, const Point& b) { return pair(a) > pair(b); } friend bool operator>=(const Point& a, const Point& b) { return pair(a) >= pair(b); } friend std::ostream& operator<<(std::ostream& o, const Point& p) { return o << ( << p.x << , << p.y << ) ; } friend std::istream& operator>>(std::istream& i, Point& p) { return i >> p.x >> p.y; } Point& operator+=(const Point& p) { x += p.x; y += p.y; return *this; } Point& operator-=(const Point& p) { x -= p.x; y -= p.y; return *this; } friend Point operator+(const Point& a, const Point& b) { return Point(a) += b; } friend Point operator-(const Point& a, const Point& b) { return Point(a) -= b; } T cross(const Point& p) const { return x * p.y - y * p.x; } T cross(const Point& p, const Point& q) const { return (p - *this).cross(q - *this); } }; using Pt = Point<int>; const int MAXN = 7000; int A, B; int N; struct City { Pt pt; int id; int deg; friend bool operator<(const City& a, const City& b) { return a.pt < b.pt; } } pts[MAXN]; int hsz; int hull[MAXN]; void solve(int st, int en) { if (st == en) return; if (pts[st].deg == -1) return solve(st + 1, en); if (pts[en].deg == -1) return solve(st, en - 1); int len = 0; int totdeg = 0; for (int i = st; i <= en; i++) { if (pts[i].deg == -1) continue; len++; totdeg += pts[i].deg; } assert(len); assert(totdeg == len - 1); assert(len >= 2); { hsz = 0; for (int i = 0; i <= (en - st) * 2; i++) { int cur = (i <= (en - st) ? (st + i) : (en + (en - st) - i)); if (pts[cur].deg == -1) continue; while (hsz >= 2 && hull[hsz - 1] != en) { if (pts[hull[hsz - 2]].pt.cross(pts[hull[hsz - 1]].pt, pts[cur].pt) < 0) { break; } else { hsz--; } } hull[hsz++] = cur; } hsz--; assert(hsz >= 2); assert(hull[hsz] == hull[0]); for (int ind = 0; ind < hsz; ind++) { int a = hull[ind], b = hull[ind + 1]; assert(pts[a].deg != -1 && pts[b].deg != -1); if (pts[a].deg == 0 && pts[b].deg > 0) { cout << pts[b].id << << pts[a].id << n ; pts[b].deg--; if (pts[b].deg == 0) { pts[b].deg = -1; } else { pts[a].deg = -1; } return solve(st, en); } } } int pref = 0; int lsz = 0; for (int i = st; i <= en; i++) { if (pts[i].deg == -1) continue; int suff = pref + (pts[i].deg - 1); lsz++; if (lsz > 1 && lsz < len && (pref >= 0) != (suff >= 0)) { int ldeg, rdeg; if (pts[i].deg > 0) { assert(pref < 0 && suff >= 0); ldeg = -pref; rdeg = suff + 1; assert(ldeg + rdeg == pts[i].deg); } else { ldeg = 0; rdeg = 0; } pts[i].deg = ldeg; solve(st, i); pts[i].deg = rdeg; solve(i, en); return; } pref = suff; } assert(false); } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int T; cin >> T; while (T--) { cin >> A >> B; N = A + B; for (int i = 0; i < A; i++) { pts[i].deg = 0; pts[i].id = i + 1; } for (int i = A; i < A + B; i++) { cin >> pts[i].deg; assert(pts[i].deg > 0); pts[i].id = i - A + 1; } for (int i = 0; i < N; i++) { cin >> pts[i].pt; } sort(pts, pts + N); cout << YES << n ; solve(0, N - 1); } return 0; }
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
recFNToIN#(
parameter expWidth = 3, parameter sigWidth = 3, parameter intWidth = 1
) (
input [(`floatControlWidth - 1):0] control,
input [(expWidth + sigWidth):0] in,
input [2:0] roundingMode,
input signedOut,
output [(intWidth - 1):0] out,
output [2:0] intExceptionFlags
);
`include "HardFloat_localFuncs.vi"
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam intExpWidth = clog2(intWidth);
localparam boundedIntExpWidth =
(expWidth <= intExpWidth) ? expWidth - 1 : intExpWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaN, isInf, isZero, sign;
wire signed [(expWidth + 1):0] sExp;
wire [sigWidth:0] sig;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN(in, isNaN, isInf, isZero, sign, sExp, sig);
wire magGeOne = sExp[expWidth];
wire [(expWidth - 1):0] posExp = sExp[(expWidth - 1):0];
wire magJustBelowOne = !magGeOne && (&posExp);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire roundingMode_near_even = (roundingMode == `round_near_even);
wire roundingMode_minMag = (roundingMode == `round_minMag);
wire roundingMode_min = (roundingMode == `round_min);
wire roundingMode_max = (roundingMode == `round_max);
wire roundingMode_near_maxMag = (roundingMode == `round_near_maxMag);
wire roundingMode_odd = (roundingMode == `round_odd);
/*------------------------------------------------------------------------
| Assuming the input floating-point value is not a NaN, its magnitude is
| at least 1, and it is not obviously so large as to lead to overflow,
| convert its significand to fixed-point (i.e., with the binary point in a
| fixed location). For a non-NaN input with a magnitude less than 1, this
| expression contrives to ensure that the integer bits of 'alignedSig'
| will all be zeros.
*------------------------------------------------------------------------*/
wire [(intWidth + sigWidth - 1):0] shiftedSig =
{magGeOne, sig[(sigWidth - 2):0]}
<<(magGeOne ? sExp[(boundedIntExpWidth - 1):0] : 0);
wire [(intWidth + 1):0] alignedSig =
{shiftedSig>>(sigWidth - 2), |shiftedSig[(sigWidth - 3):0]};
wire [(intWidth - 1):0] unroundedInt = alignedSig>>2;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire common_inexact = magGeOne ? |alignedSig[1:0] : !isZero;
wire roundIncr_near_even =
(magGeOne && ((&alignedSig[2:1]) || (&alignedSig[1:0])))
|| (magJustBelowOne && (|alignedSig[1:0]) );
wire roundIncr_near_maxMag =
(magGeOne && alignedSig[1]) || magJustBelowOne;
wire roundIncr =
(roundingMode_near_even && roundIncr_near_even )
|| (roundingMode_near_maxMag && roundIncr_near_maxMag )
|| ((roundingMode_min || roundingMode_odd) && (sign && common_inexact))
|| (roundingMode_max && (!sign && common_inexact));
wire [(intWidth - 1):0] complUnroundedInt =
sign ? ~unroundedInt : unroundedInt;
wire [(intWidth - 1):0] roundedInt =
(roundIncr ^ sign ? complUnroundedInt + 1 : complUnroundedInt)
| (roundingMode_odd && common_inexact);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire magGeOne_atOverflowEdge = (posExp == intWidth - 1);
wire roundCarryBut2 = (&unroundedInt[(intWidth - 3):0]) && roundIncr;
wire common_overflow =
magGeOne
? (posExp >= intWidth)
|| (signedOut
? (sign ? magGeOne_atOverflowEdge
&& ((|unroundedInt[(intWidth - 2):0])
|| roundIncr)
: magGeOne_atOverflowEdge
|| ((posExp == intWidth - 2)
&& roundCarryBut2))
: sign || (magGeOne_atOverflowEdge
&& unroundedInt[intWidth - 2]
&& roundCarryBut2))
: !signedOut && sign && roundIncr;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire invalidExc = isNaN || isInf;
wire overflow = !invalidExc && common_overflow;
wire inexact = !invalidExc && !common_overflow && common_inexact;
wire [(intWidth - 1):0] excOut;
iNFromException#(intWidth) iNFromException(signedOut, isNaN, sign, excOut);
assign out = invalidExc || common_overflow ? excOut : roundedInt;
assign intExceptionFlags = {invalidExc, overflow, inexact};
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; double ans = 0; map<double, double> F; void insert(double dist, double s) { double need = dist / (s + 1); F[s] += need; if (s > 1) F[s] += dist / (s - 1); ans += need; while (need > 1e-9) { map<double, double>::iterator it = --F.end(); double y = it->first; double dlt = min(need, F[y]); F[y] -= dlt; need -= dlt; ans += dlt / y; if (F[y] < 1e-9) { F.erase(it); } } } int n, L, ls; int main() { scanf( %d%d , &n, &L); int l, r; double s; while (n--) { scanf( %d%d%lf , &l, &r, &s); insert(l - ls, 1); insert(r - l, s + 1); ls = r; } insert(L - ls, 1); printf( %.10lf n , ans); return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: memory.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module memory (
address,
clock,
q);
input [4:0] address;
input clock;
output [8:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({9{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "inst_mem.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 5,
altsyncram_component.width_a = 9,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "inst_mem.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "9"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "inst_mem.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 9 0 @q_a 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL memory.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Ed Lander.
// verilator lint_off WIDTH
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] p1;
reg [7:0] p2;
reg [7:0] p3;
initial begin
p1 = 8'h01;
p2 = 8'h02;
p3 = 8'h03;
end
parameter int param1 = 8'h11;
parameter int param2 = 8'h12;
parameter int param3 = 8'h13;
targetmod i_targetmod (/*AUTOINST*/
// Inputs
.clk (clk));
//Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod
//param1 not over-riden (as mycheck) (=> 0x31)
//param2 explicitly bound to targetmod value (=> 0x22)
//param3 explicitly bound to top value (=> 0x13)
//p1 implictly bound (.*), takes value from targetmod (=> 0x04)
//p2 explictly bound to targetmod (=> 0x05)
//p3 explictly bound to top (=> 0x03)
// Alternative unsupported form is i_targetmod
bind targetmod mycheck
#(
.param2(param2),
.param3(param3)
)
i_mycheck (.p2(p2), .p3(p3), .*);
endmodule
module targetmod (input clk);
reg [7:0] p1;
reg [7:0] p2;
reg [7:0] p3;
parameter int param1 = 8'h21;
parameter int param2 = 8'h22;
parameter int param3 = 8'h23;
initial begin
p1 = 8'h04;
p2 = 8'h05;
p3 = 8'h06;
end
endmodule
module mycheck (/*AUTOARG*/
// Inputs
clk, p1, p2, p3
);
input clk;
input [7:0] p1;
input [7:0] p2;
input [7:0] p3;
parameter int param1 = 8'h31;
parameter int param2 = 8'h32;
parameter int param3 = 8'h33;
always @ (posedge clk) begin
`checkh(param1,8'h31);
`checkh(param2,8'h22);
`checkh(param3,8'h23);
`checkh(p1,8'h04);
`checkh(p2,8'h05);
`checkh(p3,8'h06);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct chess { bool used; int x, y; char p; } up, down, Left, Right, up_Left, up_Right, down_Left, down_Right; int n, kx, ky; void add(int x, int y, char c) { if (x == kx) { if (y < ky) { if (!Left.used || y > Left.y) { Left.x = x; Left.y = y; Left.p = c; Left.used = true; } } else { if (!Right.used || y < Right.y) { Right.x = x; Right.y = y; Right.p = c; Right.used = true; } } } if (y == ky) { if (x < kx) { if (!up.used || x > up.x) { up.x = x; up.y = y; up.p = c; up.used = true; } } else { if (!down.used || x < down.x) { down.x = x; down.y = y; down.p = c; down.used = true; } } } if (x - y == kx - ky) { if (x < kx) { if (!up_Left.used || x > up_Left.x) { up_Left.x = x; up_Left.y = y; up_Left.p = c; up_Left.used = true; } } else { if (!down_Right.used || x < down_Right.x) { down_Right.x = x; down_Right.y = y; down_Right.p = c; down_Right.used = true; } } } if (x + y == kx + ky) { if (x < kx) { if (!up_Right.used || x > up_Right.x) { up_Right.x = x; up_Right.y = y; up_Right.p = c; up_Right.used = true; } } else { if (!down_Left.used || x < down_Left.x) { down_Left.x = x; down_Left.y = y; down_Left.p = c; down_Left.used = true; } } } } bool check() { if (up.p == R || up.p == Q || down.p == R || down.p == Q ) return true; if (Left.p == R || Left.p == Q || Right.p == R || Right.p == Q ) return true; if (up_Right.p == B || up_Right.p == Q || up_Left.p == B || up_Left.p == Q ) return true; if (down_Right.p == B || down_Right.p == Q || down_Left.p == B || down_Left.p == Q ) return true; return false; } int main() { int x, y; ios::sync_with_stdio(false); cin.tie(0); char c; cin >> n >> kx >> ky; for (int i = 0; i < n; i++) { cin >> c >> x >> y; add(x, y, c); } if (check()) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, n; cin >> a >> b >> c >> n; int d = n - (a + b - c); if ((a - c) >= 0 && (b - c) >= 0 && c >= 0 && d > 0) { cout << d << endl; } else cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, B, Q; int a[200005]; vector<int> adj[200005]; void init() { B = sqrt(N); for (int i = 1; i <= N; i++) { a[i] = i; adj[i / B].push_back(i); } } long long work(int l, int r) { if (l == r) return 0; int idx, idy, x, y, k; x = a[l]; y = a[r]; idx = l / B; k = find(adj[idx].begin(), adj[idx].end(), x) - adj[idx].begin(); adj[idx][k] = y; sort(adj[idx].begin(), adj[idx].end()); idy = r / B; k = find(adj[idy].begin(), adj[idy].end(), y) - adj[idy].begin(); adj[idy][k] = x; sort(adj[idy].begin(), adj[idy].end()); int ans = 0, f; if (x > y) f = -1, swap(x, y); else f = 1; if (idx == idy) { for (int i = l + 1; i <= r - 1; i++) { if (x < a[i] && a[i] < y) ++ans; } } else { for (int i = l + 1; i < (idx + 1) * B; i++) { if (x < a[i] && a[i] < y) ++ans; } for (int id = idx + 1; id < idy; id++) { ans += upper_bound(adj[id].begin(), adj[id].end(), y) - lower_bound(adj[id].begin(), adj[id].end(), x); } for (int i = idy * B; i < r; i++) { if (x < a[i] && a[i] < y) ++ans; } } swap(a[l], a[r]); return (2 * ans + 1) * f; } int main() { scanf( %d%d , &N, &Q); init(); int l, r; long long ans = 0; while (Q--) { scanf( %d%d , &l, &r); if (l > r) swap(l, r); ans += work(l, r); printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 500005; int a[N]; int main() { int n; while (scanf( %d , &n) != EOF) { memset(a, 0, sizeof(a)); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } sort(a, a + n); int mid = (n - 1) / 2; int big = n - 1; int small = mid; int ok = 0; while (big > mid && small >= 0) { if (a[small] * 2 <= a[big]) { ok++; small--; big--; } else { small--; } } printf( %d n , n - ok); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1 << 16; map<pair<int, int>, int> dp[maxn]; int n, c[20], r[20], b[20], ed, rrr, bbb, ans = 0x3f3f3f3f; int main() { cin >> n; getchar(); for (int i = 1; i <= n; i++) { char ch; cin >> ch >> r[i] >> b[i]; if (ch == R ) c[i] = 1; } ed = (1 << n) - 1; dp[0][pair<int, int>(0, 0)] = 0; for (int i = 0; i <= ed; i++) { int rr = 0, bb = 0; for (int t = 0; t < n; t++) if (i & (1 << t)) ++(c[t + 1] ? rr : bb); for (int j = 0; j < n; j++) { if (i & (1 << j)) continue; for (auto it : dp[i]) { int next = i | (1 << j), need = 0; if (it.first.first < max(r[j + 1] - rr, 0)) need = max(need, r[j + 1] - rr - it.first.first); if (it.first.second < max(b[j + 1] - bb, 0)) need = max(need, b[j + 1] - bb - it.first.second); int rmr = it.first.first + need - max(r[j + 1] - rr, 0), rmb = it.first.second + need - max(b[j + 1] - bb, 0); if (!dp[next].count(pair<int, int>(rmr, rmb))) dp[next][pair<int, int>(rmr, rmb)] = 0x3f3f3f3f; dp[next][pair<int, int>(rmr, rmb)] = min(dp[next][pair<int, int>(rmr, rmb)], it.second + need); } } } for (auto it : dp[ed]) ans = min(ans, it.second); cout << ans + n << endl; return 0; }
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Mon Dec 01 03:09:56 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// c:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_funcsim.v
// Design : clk_wiz_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "clk_wiz_1,clk_wiz_v5_1,{component_name=clk_wiz_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_wiz_1
(clk_in1,
clk_out1,
reset,
locked);
input clk_in1;
output clk_out1;
input reset;
output locked;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
clk_wiz_1_clk_wiz_1_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.reset(reset));
endmodule
(* ORIG_REF_NAME = "clk_wiz_1_clk_wiz" *)
module clk_wiz_1_clk_wiz_1_clk_wiz
(clk_in1,
clk_out1,
reset,
locked);
input clk_in1;
output clk_out1;
input reset;
output locked;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_in1_clk_wiz_1;
wire clk_out1;
wire clk_out1_clk_wiz_1;
wire clkfbout_buf_clk_wiz_1;
wire clkfbout_clk_wiz_1;
wire locked;
wire reset;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_1),
.O(clkfbout_buf_clk_wiz_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_1),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(36.375000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(36.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(4),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_1),
.CLKFBOUT(clkfbout_clk_wiz_1),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_1),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_1),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DFBBN_FUNCTIONAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, D, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBN_FUNCTIONAL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 23:24:41 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(GPIO_I, GPIO_O, GPIO_T, SDIO0_WP, TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; struct Matrix { long long a, b, c, d; Matrix(long long _a = 0, long long _b = 0, long long _c = 0, long long _d = 0) { a = _a; b = _b; c = _c; d = _d; } void normalize(Matrix& mat) { mat.a %= mod; mat.b %= mod; mat.c %= mod; mat.d %= mod; } const Matrix operator+(const Matrix& mat) { Matrix tmp(this->a + mat.a, this->b + mat.b, this->c + mat.c, this->d + mat.d); normalize(tmp); return tmp; } const Matrix operator*(const Matrix& mat) { Matrix tmp( this->a * mat.a + this->b * mat.c, this->a * mat.b + this->b * mat.d, this->c * mat.a + this->d * mat.c, this->c * mat.b + this->d * mat.d); normalize(tmp); return tmp; } bool operator==(const Matrix& mat) const { if (this->a == mat.a && this->b == mat.b && this->c == mat.c && this->d == mat.d) return true; return false; } bool operator!=(const Matrix& mat) const { return !(*this == mat); } void pprint() { return; cerr << --------------------------- << endl; cerr << this->a << | << this->b << endl; cerr << this->c << | << this->d << endl; cerr << --------------------------- << endl; } }; class SegmentTree { private: vector<Matrix> A, st, lazy; int n; Matrix lazyId; int left(int p) { return p << 1; } int right(int p) { return (p << 1) + 1; } void build(int p, int l, int r) { if (r - l == 1) { st[p] = A[l]; return; } int mid = (l + r) / 2; build(left(p), l, mid); build(right(p), mid, r); st[p] = st[left(p)] + st[right(p)]; } void apply(int p, int l, int r) { st[p] = lazy[p] * st[p]; if (r - l > 1) { lazy[left(p)] = lazy[p] * lazy[left(p)]; lazy[right(p)] = lazy[p] * lazy[right(p)]; } lazy[p] = lazyId; } void lazyUpdate(int p, int l, int r, int i, int j, Matrix& val) { if (lazy[p] != lazyId) apply(p, l, r); if (j <= l || r <= i) return; if (i <= l && r <= j) { lazy[p] = lazy[p] * val; apply(p, l, r); return; } int mid = (l + r) / 2; lazyUpdate(left(p), l, mid, i, j, val); lazyUpdate(right(p), mid, r, i, j, val); st[p] = st[left(p)] + st[right(p)]; } Matrix query(int p, int l, int r, int i, int j) { if (j <= l || r <= i) return Matrix(); if (lazy[p] != lazyId) apply(p, l, r); if (i <= l && r <= j) return st[p]; int mid = (l + r) / 2; Matrix uno = query(left(p), l, mid, i, j); Matrix dos = query(right(p), mid, r, i, j); return uno + dos; } public: SegmentTree(vector<Matrix> v) { A = v; n = v.size(); st.assign(4 * n, Matrix()); lazyId = Matrix(1, 0, 0, 1); lazy.assign(4 * n, lazyId); build(1, 0, n); } void update(int i, int j, Matrix& val) { lazyUpdate(1, 0, n, i, j, val); } Matrix query(int i, int j) { return query(1, 0, n, i, j); } }; Matrix pot(Matrix b, int k) { if (k == 0) return Matrix(1, 0, 0, 1); if (k % 2 == 0) { Matrix tmp = pot(b, k / 2); return tmp * tmp; } else { return b * pot(b, k - 1); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; int n, m; cin >> n >> m; Matrix base = Matrix(1, 1, 1, 0); vector<Matrix> vec; for (int i = 0; i < n; i++) { int a; cin >> a; Matrix tmp = pot(base, a); vec.push_back(tmp); ; ; tmp.pprint(); } SegmentTree st(vec); for (int i = 0; i < m; i++) { int t; cin >> t; if (t == 1) { int l, r, x; cin >> l >> r >> x; l--; r--; Matrix tmp = pot(base, x); ; ; tmp.pprint(); st.update(l, r + 1, tmp); } else { int l, r; cin >> l >> r; l--; r--; Matrix tmp = st.query(l, r + 1); tmp.pprint(); long long res = tmp.c % mod; cout << res << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; long long m = 0, cost = 0; ; int a, b; priority_queue<pair<int, int> > q; for (int i = 0; i < s.size(); i++) { m--; if (s[i] == ( ) m += 2; if (s[i] == ? ) { s[i] = ) ; cin >> a >> b; q.push(make_pair(b - a, i)); cost += b; } if (m < 0) { if (q.empty()) break; pair<int, int> x = q.top(); q.pop(); s[x.second] = ( ; cost -= x.first; m += 2; } } if (m != 0) { cout << -1; return 0; } cout << cost << endl << s; }
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_0_poc_pd.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff
// prevents any noise that could happen when the phase shift clock is very
// nearly aligned to the fabric clock.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_0_poc_pd #
(parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter SIM_CAL_OPTION = "NONE",
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
pd_out,
// Inputs
iddr_rst, clk, kclk, mmcm_ps_clk
);
input iddr_rst;
input clk;
input kclk;
input mmcm_ps_clk;
wire q1;
IDDR #
(.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC"))
u_phase_detector
(.Q1 (q1),
.Q2 (),
.C (mmcm_ps_clk),
.CE (1'b1),
.D (kclk),
.R (iddr_rst),
.S (1'b0));
// Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME
reg pos_edge_samp;
generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes
always @(posedge clk) pos_edge_samp <= #TCQ q1;
end else begin : eXes
reg q1_delayed;
reg rising_clk_seen;
always @(posedge mmcm_ps_clk) begin
rising_clk_seen <= 1'b0;
q1_delayed <= 1'bx;
end
always @(posedge clk) begin
rising_clk_seen = 1'b1;
if (rising_clk_seen) q1_delayed <= q1;
end
always @(posedge clk) begin
pos_edge_samp <= q1_delayed;
end
end endgenerate
reg pd_out_r;
always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp;
output pd_out;
assign pd_out = pd_out_r;
endmodule // mic_7series_v4_0_poc_pd
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module seq_rec
#(
parameter BASEADDR = 0,
parameter HIGHADDR = 0,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 8*1024,
parameter IN_BITS = 8
)(
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire SEQ_CLK,
input wire [IN_BITS-1:0] SEQ_IN,
input wire SEQ_EXT_START
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
seq_rec_core
#(
.MEM_BYTES(MEM_BYTES),
.IN_BITS(IN_BITS),
.ABUSWIDTH(ABUSWIDTH)
) i_scope_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SEQ_CLK(SEQ_CLK),
.SEQ_IN(SEQ_IN),
.SEQ_EXT_START(SEQ_EXT_START)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_SIO_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_SIO_PP_SYMBOL_V
/**
* top_sio: Special I/O PAD that provides additionally a
* regulated output buffer and a differential input buffer.
* SIO cells are ONLY available IN pairs (see top_sio_macro).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_sio (
//# {{data|Data Signals}}
input SLOW ,
output IN ,
input INP_DIS ,
output IN_H ,
input OUT ,
inout PAD ,
inout PAD_A_ESD_0_H,
inout PAD_A_ESD_1_H,
inout PAD_A_NOESD_H,
//# {{control|Control Signals}}
input [2:0] DM ,
input ENABLE_H ,
input HLD_H_N ,
input HLD_OVR ,
input IBUF_SEL ,
input OE_N ,
//# {{power|Power}}
input VREG_EN ,
input VTRIP_SEL ,
input REFLEAK_BIAS ,
inout VCCD ,
inout VCCHIB ,
inout VDDIO ,
inout VDDIO_Q ,
input VINREF ,
input VOUTREF ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q ,
output TIE_LO_ESD
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_SIO_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_BEHAVIORAL_V
`define SKY130_FD_SC_LP__HA_BEHAVIORAL_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__ha (
COUT,
SUM ,
A ,
B
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_COUT;
wire xor0_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_BEHAVIORAL_V
|
// Texas A&M University //
// cpsc350 Computer Architecture //
//Alan Achtenberg??
//Project 2//
`define OPCODE_ADD 6'b000000
`define OPCODE_SUB 6'b000000
`define OPCODE_ADDU 6'b000000
`define OPCODE_SUBU 6'b000000
`define OPCODE_AND 6'b000000
`define OPCODE_OR 6'b000000
`define OPCODE_SLL 6'b000000
`define OPCODE_SRA 6'b000000
`define OPCODE_SRL 6'b000000
`define OPCODE_SLT 6'b000000
`define OPCODE_SLTU 6'b000000
`define OPCODE_XOR 6'b000000
`define OPCODE_JR 6'b000000
//I-Type (All opcodes except 000000, 00001x, and 0100xx)
`define OPCODE_ADDI 6'b001000
`define OPCODE_ADDIU 6'b001001
`define OPCODE_ANDI 6'b001100
`define OPCODE_BEQ 6'b000100
`define OPCODE_BNE 6'b000101
`define OPCODE_BLEZ 6'b000110
`define OPCODE_BLTZ 6'b000001
`define OPCODE_ORI 6'b001101
`define OPCODE_XORI 6'b001110
`define OPCODE_NOP 6'b110110
`define OPCODE_LUI 6'b001111
`define OPCODE_SLTI 6'b001010
`define OPCODE_SLTIU 6'b001011
`define OPCODE_LB 6'b100000
`define OPCODE_LW 6'b100011
`define OPCODE_SB 6'b101000
`define OPCODE_SW 6'b101011
// J-Type (Opcode 00001x)
`define OPCODE_J 6'b000010
`define OPCODE_JAL 6'b000011
`define ADD 4'b0111 // 2's compl add
`define ADDU 4'b0001 // unsigned add
`define SUB 4'b0010 // 2's compl subtract
`define SUBU 4'b0011 // unsigned subtract
`define AND 4'b0100 // bitwise AND
`define OR 4'b0101 // bitwise OR
`define XOR 4'b0110 // bitwise XOR
`define SLT 4'b1010 // set result=1 if less than 2's compl
`define SLTU 4'b1011 // set result=1 if less than unsigned
`define NOP 4'b0000 // do nothing
// Top Level Architecture Model //
`include "Control.v"
`include "IdealMemory.v"
`include "PC.v"
`include "RegisterFile.v"
`include "mux.v"
`include "ALU_bhav.v"
`include "signextend.v"
`include "ALUControl.v"
`include "DataMemory.v"
/*-------------------------- CPU -------------------------------
* This module implements a single-cycle
* CPU similar to that described in the text book
* (for example, see Figure 5.19).
*
*/
//
// Input Ports
// -----------
// clock - the system clock (m555 timer).
//
// reset - when asserted by the test module, forces the processor to
// perform a "reset" operation. (note: to reset the processor
// the reset input must be held asserted across a
// negative clock edge).
//
// During a reset, the processor loads an externally supplied
// value into the program counter (see startPC below).
//
// startPC - during a reset, becomes the new contents of the program counter
// (starting address of test program).
//
// Output Port
// -----------
// dmemOut - contains the data word read out from data memory. This is used
// by the test module to verify the correctness of program
// execution.
//-------------------------------------------------------------------------
module SingleCycleProc(CLK, Reset_L, startPC, dmemOut);
input Reset_L, CLK;
input [31:0] startPC;
output [31:0] dmemOut;
wire [31:0] PC;
wire [31:0] Instr;
wire [31:0] ALUin, Result;
wire ALUzero;
//
// INSERT YOUR CPU MODULES HERE
wire RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend;
wire [31:0]Immediate; //Sign extended value
wire [31:0] MemData, ALUresult;
ProgramCounter PC1(PC, PC, Reset_L, startPC,CLK,Jump,ALUzero,Branch,Instr[25:0],Immediate);
InstrMem IM1(PC, Instr);
wire [3:0]ALUOp;
Control_Unit C1(RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend, ALUOp, Instr[31:26]);
wire [3:0] ALUctrl;
ALUControl AC1(ALUctrl, ALUOp,Instr[5:0]);
wire [4:0] Waddr;
MUX5_2to1 mux1(Instr[20:16], Instr[15:11], RegDst, Waddr );
wire [31:0]Read1, Read2, Writedata;
RegisterFile RF1(Read1, Read2, Writedata, Instr[25:21],Instr[20:16], Waddr, RegWrite, CLK, Reset_L);
SIGN_EXTEND SE1(Instr[15:0], Immediate);
MUX32_2to1 mux2(Read2, Immediate, ALUSrc, ALUin);
ALU_behav ALU1( Read1, ALUin, ALUctrl, ALUresult, Overflow, 1'b0, Carry_out, ALUzero );
DataMem dm( MemData, ALUresult, Read2, MemRead, MemWrite, CLK, Reset_L);
MUX32_2to1 memmux(ALUresult, MemData, MemToReg, Writedata);
//
// Debugging
//
/*
always @(RegDst or Waddr)
begin
$display("RegDst %b Waddr %d" , RegDst, Waddr );
end
*/
//Monitor changes in the program counter
/* always @(PC)
begin
#10 $display($time," PC=%d Instr: op=%d rs=%d rt=%d rd=%d imm16=%d funct=%d",
PC,Instr[31:26],Instr[25:21],Instr[20:16],Instr[15:11],Instr[15:0],Instr[5:0]);
end
*/
/* Monitors memory writes
always @(MemWrite)
begin
#1 $display($time," MemWrite=%b clock=%d addr=%d data=%d",
MemWrite, clock, dmemaddr, rportb);
end
*/
/*always @(Instr)
begin
#10 $display($time,"OPCODE=%b, ALUctrl=%b , ALUOp=%b", Instr[31:26],ALUctrl, ALUOp);
end
*/
endmodule // CPU
module m555 (CLK);
parameter StartTime = 0, Ton = 50, Toff = 50, Tcc = Ton+Toff; //
output CLK;
reg CLK;
initial begin
#StartTime CLK = 0;
end
// The following is correct if clock starts at LOW level at StartTime //
always begin
#Toff CLK = ~CLK;
#Ton CLK = ~CLK;
end
endmodule
module testCPU(Reset_L, startPC, testData);
input [31:0] testData;
output Reset_L;
output [31:0] startPC;
reg Reset_L;
reg [31:0] startPC;
initial begin
// Your program 1
Reset_L = 0; startPC = 0 * 4;
#101 // insures reset is asserted across negative clock edge
Reset_L = 1;
#4000; // allow enough time for program 1 to run to completion
Reset_L = 0;
// #1 $display ("Program 1: Result: %d", testData);
// Your program 2
//startPC = 14 * 4;
//#101 Reset_L = 1;
//#10000;
//Reset_L = 0;
//#1 $display ("Program 2: Result: %d", testData);
// etc.
// Run other programs here
$finish;
end
endmodule // testCPU
module TopProcessor;
wire reset, CLK, Reset_L;
wire [31:0] startPC;
wire [31:0] testData;
m555 system_clock(CLK);
SingleCycleProc SSProc(CLK, Reset_L, startPC, testData);
testCPU tcpu(Reset_L, startPC, testData);
endmodule // TopProcessor
|
#include <bits/stdc++.h> constexpr unsigned primes[]{2672090437, 2569161337, 2414657393}; constexpr int np = sizeof(primes) / sizeof(*primes); std::vector<std::array<unsigned, np> > pow2; void setpow2(int maxp) { pow2.resize(maxp + 1); for (int i = 0; i < np; i++) pow2[0][i] = 1; for (int i = 1; i <= maxp; i++) for (int j = 0; j < np; j++) pow2[i][j] = pow2[i - 1][j] * 2ULL % primes[j]; } struct hash { unsigned m[np]; int nbits; hash() {} hash(unsigned num, int nbits = 1) : nbits(nbits) { for (int i = 0; i < np; i++) m[i] = num; } }; hash join(hash a, hash b) { hash out; out.nbits = a.nbits + b.nbits; for (int i = 0; i < np; i++) out.m[i] = (a.m[i] * (uint64_t)pow2[b.nbits][i] + b.m[i]) % primes[i]; return out; } bool operator<(hash a, hash b) { if (a.nbits != b.nbits) return a.nbits < b.nbits; return memcmp(a.m, b.m, sizeof(a.m)) < 0; } int w[100000]; std::vector<int> adj[100000]; hash h0[100000]; hash hnew[100000]; int deg[100000]; int findw(int v, int par = -1) { int t = 1; for (int x : adj[v]) { if (x != par) t += findw(x, v); } return w[v] = t; } void genh0(int v, bool rec = true) { if (rec) { for (int x : adj[v]) genh0(x); } std::sort(adj[v].begin(), adj[v].end(), [](int a, int b) { return h0[a] < h0[b]; }); hash out(0); for (int x : adj[v]) out = join(out, h0[x]); h0[v] = join(out, hash(1)); } void hconcat(int v, hash h) { hnew[v] = memcmp(hnew[v].m, h.m, sizeof(h.m)) < 0 ? join(hnew[v], h) : join(h, hnew[v]); for (int x : adj[v]) hconcat(x, h); } int main() { std::ios_base::sync_with_stdio(false); int n; scanf( %d , &n); setpow2(2 * n + 5); for (int i = n; --i;) { int a, b; scanf( %d %d , &a, &b); --a; --b; adj[a].push_back(b); adj[b].push_back(a); ++deg[a]; ++deg[b]; } findw(0); std::vector<int> center; for (int i = n; i--;) { if (n % 2 == 0 && w[i] == n / 2) { for (int j : adj[i]) { if (w[j] > w[i]) { center = {i, j}; break; } } break; } else if (n - w[i] < (n + 1) / 2) { bool isC = true; for (int v : adj[i]) isC &= w[v] > w[i] || w[v] < (n + 1) / 2; if (isC) { center = {i}; break; } } } bool ecent = center.size() == 2; for (auto i = center.size(); i--;) findw(center[i], center[i ^ +ecent]); for (int i = n; i--;) { std::sort(adj[i].begin(), adj[i].end(), [](int a, int b) { return w[a] < w[b]; }); if (n > 1 && (ecent || i != center[0])) adj[i].pop_back(); } struct split { const int *eqb, *eqe; hash pre, post; }; std::vector<split> ss; const hash h01 = join(hash(0), hash(1)); std::function<void(int, hash, hash, int)> genh; int nbad = 0; genh = [&](int v, hash pre, hash post, int skipw) { if (deg[v] < 4) { hash h = join(pre, h01); for (int x : adj[v]) h = join(h, h0[x]); h = join(h, post); for (auto it = ss.crbegin(); it != ss.crend(); ++it) { hash hh = it->pre; bool inserted = false; for (const int* i = it->eqb; i != it->eqe; ++i) { if (!inserted && memcmp(h.m, h0[*i].m, sizeof(h.m)) < 0) { inserted = true; hh = join(hh, h); } hh = join(hh, h0[*i]); } if (!inserted) hh = join(hh, h); h = join(hh, it->post); } hnew[v] = h; } else { hnew[v].nbits = -1; nbad++; } for (auto aj = adj[v].cbegin(), ae = adj[v].cend(); aj != ae; ++aj) { if (w[*aj] == skipw) continue; auto a2 = aj; do ++a2; while (a2 != ae && w[*a2] == w[*aj]); hash pre2 = pre, post2 = post; for (auto a = adj[v].cbegin(); a != a2; ++a) { if (a != aj) pre2 = join(pre2, h0[*a]); } if (a2 != ae && w[*a2] == w[*aj] + 1) { auto a3 = a2; do ++a3; while (a3 != ae && w[*a3] == w[*a2]); for (auto a = ae; a != a3;) post2 = join(h0[*--a], post2); ss.push_back(split{&*a2, &*a2 + (a3 - a2), pre2, post2}); genh(*aj, hash(0), hash(1), -1); ss.pop_back(); } else { for (auto a = ae; a != a2;) post2 = join(h0[*--a], post2); pre2 = join(pre2, hash(0)); post2 = join(hash(1), post2); genh(*aj, pre2, post2, -1); } } }; if (ecent) { genh0(center[0]); genh0(center[1]); for (int i : {0, 1}) { int c = center[i]; adj[c].push_back(center[i ^ 1]); genh(c, hash(0, 0), hash(0, 0), n / 2); adj[c].pop_back(); } } else { int c = center[0]; genh0(c); genh(c, hash(0, 0), hash(0, 0), n / 2); for (auto i = adj[c].size(); i--;) { int c2 = adj[c][i]; if (w[c2] != n / 2) continue; adj[c].erase(adj[c].begin() + i); genh0(c, false); genh(c2, hash(0, 0), hash(0, 0), -1); adj[c].insert(adj[c].begin() + i, c2); hconcat(c2, h0[c]); } } std::sort(hnew, hnew + n); int ans = 1; for (int i = nbad + 1; i < n; i++) { if (memcmp(hnew + i, hnew + i - 1, sizeof(*hnew))) ++ans; } std::cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, T, a, b, c; int x[4], y[4]; long long cost[4]; string ans; long long f(long long x, long long y) { return (x + y) * (abs(y - x) + 1) / 2; } long long Cal(int X, int Y, int x, int y) { if (X <= x && Y <= y) return f(0, x + y - X - Y) + f(0, n + n - x - y); if (X >= x && Y >= y) return f(X + Y - x - y, n + n - x - y); if (X <= x && Y >= y) return f(x + Y - X - y, Y - y + 1) + f(Y - y, n + n - x - y); return f(X + y - x - Y, X - x + 1) + f(X - x, n + n - x - y); } long long rm[4]; bool ok(int X, int Y) { for (int i = 0; i < 4; ++i) if ((rm[i] = T - cost[i] - Cal(X, Y, x[i], y[i])) < 0) return false; if (X < a + c && Y < b + c) return ((rm[1] >> 1) + (rm[2] >> 1)) >= (long long)(a + c - max((int)a, X)) * (b + c - max((int)b, Y)); return true; } int main() { cin >> n >> T >> a >> b >> c; --c; x[1] = x[0] = a, y[2] = y[0] = b; x[2] = x[3] = a + c, y[1] = y[3] = b + c; int X = 1, Y = 1; for (int i = 0; i < 4; ++i) if (Cal(X, Y, x[i], y[i]) - abs(x[i] - X) - abs(y[i] - Y) > T) return puts( Impossible ), 0; while (X != n || Y != n) { if (X < n && ok(X + 1, Y)) ++X, ans += R ; else ++Y, ans += U ; for (int i = 0; i < 4; ++i) cost[i] += abs(x[i] - X) + abs(y[i] - Y); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int i, j, n, c, d; string a[105], b[105]; int main() { for (cin >> n; i++ < n; d += !c) for (cin >> a[i] >> b[i], j = c = 0; ++j < i;) c += a[i] == a[j] & b[i] == b[j]; cout << d; return 0; }
|
/*
Copyright (C) {2014} {Shawn Jain} <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
// Receives audio samples via FTDI UM245R USB-to-FIFO, stores to
// onboard flash memory. Plays back the percentage of pixels used
// when audioTrigger is pulsed, where the percent is set by
// audioSelector. Internally it queues upto four separate tracks
// to be played. To save memory and for a faster transfer, the
// system constructs all numbers 1-100 out of a subset of the
// digits.
module audioManager(
input wire clock, // 27mhz system clock
input wire reset, // 1 to reset to initial state
// User I/O
input wire startSwitch,
input wire [6:0] audioSelector,
input wire writeSwitch, // 1=Write, 0=Read
output wire [63:0] hexdisp,
input wire audioTrigger, // 1=Begin Playback as determined by audioSelector
// AC97 I/O
input wire ready, // 1 when AC97 data is available
input wire [7:0] from_ac97_data, // 8-bit PCM data from mic
output reg [7:0] to_ac97_data, // 8-bit PCM data to headphone
// Flash I/O
output wire [15:0] flash_data,
output wire [23:0] flash_address,
output wire flash_ce_b,
output wire flash_oe_b,
output wire flash_we_b,
output wire flash_reset_b,
output wire flash_byte_b,
input wire flash_sts,
output wire busy,
// USB I/O
input wire [7:0] data, // the data pins from the USB fifo
input wire rxf, // the rxf pin from the USB fifo
output wire rd // the rd pin from the USB fifo (OUTPUT)
);
// Playback addresses:
parameter TRACK_LENGTH = 69000; // approx 1 sec
parameter ONE_INDEX = 23'd0;
parameter TWO_INDEX = 23'd1;
parameter THREE_INDEX = 23'd2;
parameter FOUR_INDEX = 23'd3;
parameter FIVE_INDEX = 23'd4;
parameter SIX_INDEX = 23'd5;
parameter SEVEN_INDEX = 23'd6;
parameter EIGHT_INDEX = 23'd7;
parameter NINE_INDEX = 23'd8;
parameter TEN_INDEX = 23'd9;
parameter ELEVEN_INDEX = 23'd10; // A
parameter TWELVE_INDEX = 23'd11; // B
parameter THIRTEEN_INDEX = 23'd12; // C
parameter FOURTEEN_INDEX = 23'd13; // D
parameter FIFTEEN_INDEX = 23'd14; // E
parameter TWENTY_INDEX = 23'd15; // F
parameter THIRTY_INDEX = 23'd16; // 10
parameter FOURTY_INDEX = 23'd17; // 11
parameter FIFTY_INDEX = 23'd18; // 12
parameter SIXTY_INDEX = 23'd19; // 13
parameter SEVENTY_INDEX = 23'd20; // 14
parameter EIGHTY_INDEX = 23'd21; // 15
parameter NINETY_INDEX = 23'd22; // 16
parameter HUNDRED_INDEX = 23'd23; // 17
parameter TEEN_INDEX = 23'd24; // 18
parameter PERCENT_INDEX = 23'd25; // 19
parameter USED_INDEX = 23'd26; // 1A
parameter HELP_AUDIO_INDEX = 23'd27;// 1B
parameter SKIP_INDEX = 23'd28; // 1C
parameter UNUSED_INDEX = 23'd31; // 1F
reg writemode = 0; // 1=write mode; 0=read mode
reg [15:0] wdata = 0; // writeData
reg dowrite = 0; // 1=new data, write it
reg [22:0] raddr = 2; // readAddress
wire [15:0] frdata; // readData
reg doread = 0; // 1=execute read
flash_manager fm(
.clock(clock),
.reset(reset),
// Interface I/O
.writemode(writemode),
.wdata(wdata),
.dowrite(dowrite),
.raddr(raddr),
.frdata(frdata),
.doread(doread),
.busy(busy),
// Flash I/O
.flash_data(flash_data),
.flash_address(flash_address),
.flash_ce_b(flash_ce_b),
.flash_oe_b(flash_oe_b),
.flash_we_b(flash_we_b),
.flash_reset_b(flash_reset_b),
.flash_sts(flash_sts),
.flash_byte_b(flash_byte_b)
);
wire [7:0] out;// data from FIFO (OUTPUT)
wire newout; // newout=1 out contains new data (OUTPUT)
wire hold; // hold=1 the module will not accept new data from the FIFO
assign hold = 1'b0;
usb_input usbtest(
.clk(clock),
.reset(reset),
// USB FTDI I/O
.data(data[7:0]),
.rxf(rxf),
.rd(rd),
// Interface
.out(out[7:0]),
.newout(newout),
.hold(hold)
);
wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
BCD inputToBCD(
.number({1'b0, audioSelector}),
.hundreds(hundreds),
.tens(tens),
.ones(ones)
);
reg lastAudioTrigger;
reg [2:0] third = 0;
reg lastReady;
// Set of 4 addresses that represent a playback sequence
// First track in bottom 23 bits[22:0]. Last track in top bits [91:68].
reg [91:0] playbackSeq = 2;
reg [22:0] trackEndAddr = 0;
reg playing = 0;
reg lastPlaying = 0;
reg [15:0] bytesRxed = 0;
assign hexdisp = {playbackSeq[30:23], playbackSeq[7:0], 1'h0 ,trackEndAddr, 1'h0, raddr[22:0]};
reg [7:0] dataFromFifo;
always @ (posedge rd) begin
dataFromFifo <= out; // out & data have same results
end
always @ (posedge clock) begin
lastAudioTrigger <= audioTrigger;
lastReady <= ready;
lastPlaying <= playing;
if (startSwitch) begin
// write USB RX data if switch is up
if (writeSwitch) begin
writemode <= 1'b1;
doread <= 1'b0;
//dowrite <= 1'b0; // only write on new data // WATCH OUT!!
if (newout) begin
bytesRxed <= bytesRxed + 1;
wdata <= {dataFromFifo, 8'b0};//{out, 8'b0};
dowrite <= 1'b1;
end
end
// if button is DOWN - scroll through addresses via buttons
if (~writeSwitch) begin
dowrite <= 1'b0;
writemode <= 1'b0;
doread <= 1'b1;
if (playing & ready) begin // REMOVE audioTrigger
if (raddr < trackEndAddr) begin
// Normal 48K Playback
raddr <= raddr + 1;
to_ac97_data <= frdata[15:8]; // PUT BACK
end
else begin
if (playbackSeq[45:23] < UNUSED_INDEX) begin
// change raddr to next track
raddr <= playbackSeq[45:23] * TRACK_LENGTH;
// shift playbackSeq down
playbackSeq <= {UNUSED_INDEX, playbackSeq[91:23]};
// update trackEndAddr
trackEndAddr <= playbackSeq[45:23] * TRACK_LENGTH + TRACK_LENGTH;
end
else if (playbackSeq[45:23] == UNUSED_INDEX) begin
playing <= 0;
raddr <= 0; // reset for safety - lower than UNUSED_ADDR
end
end
end // if (playing & audioTrigger & ready)
// if entering this state, assign start address
if (audioTrigger & ~lastAudioTrigger) begin
playing <= 1;
case(ones)
0: playbackSeq[91:23] <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX};
1: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, ONE_INDEX};
2: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, TWO_INDEX};
3: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, THREE_INDEX};
4: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, FOUR_INDEX};
5: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, FIVE_INDEX};
6: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, SIX_INDEX};
7: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, SEVEN_INDEX};
8: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, EIGHT_INDEX};
9: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, NINE_INDEX};
default: playbackSeq <= {USED_INDEX, PERCENT_INDEX, UNUSED_INDEX}; // error
endcase
case (tens)
0: playbackSeq[22:0] <= SKIP_INDEX;
1: playbackSeq[22:0] <= TEN_INDEX;
2: playbackSeq[22:0] <= TWENTY_INDEX;
3: playbackSeq[22:0] <= THIRTY_INDEX;
4: playbackSeq[22:0] <= FOURTY_INDEX;
5: playbackSeq[22:0] <= FIFTY_INDEX;
6: playbackSeq[22:0] <= SIXTY_INDEX;
7: playbackSeq[22:0] <= SEVENTY_INDEX;
8: playbackSeq[22:0] <= EIGHTY_INDEX;
9: playbackSeq[22:0] <= NINETY_INDEX;
default: playbackSeq[22:0] <= UNUSED_INDEX;
endcase
case (hundreds)
0: begin end
1: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, HUNDRED_INDEX}; // error
endcase
case (audioSelector)
11: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, ELEVEN_INDEX};
12: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, TWELVE_INDEX};
13: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, THIRTEEN_INDEX};
14: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, FOURTEEN_INDEX};
15: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, FIFTEEN_INDEX};
16: playbackSeq <= {USED_INDEX, PERCENT_INDEX, TEEN_INDEX, SIX_INDEX};
17: playbackSeq <= {USED_INDEX, PERCENT_INDEX, TEEN_INDEX, SEVEN_INDEX};
18: playbackSeq <= {USED_INDEX, PERCENT_INDEX, TEEN_INDEX, EIGHT_INDEX};
19: playbackSeq <= {USED_INDEX, PERCENT_INDEX, TEEN_INDEX, NINE_INDEX};
default: begin end
endcase
end // if (audioTrigger & ~lastAudioTrigger)
// just started playing - need to set raddr
// Assuming this happens once playbackSeq has been properly set
if (playing & ~lastPlaying) begin
if (playbackSeq[22:0] == SKIP_INDEX) begin
playbackSeq <= {UNUSED_INDEX, playbackSeq[91:23]};
raddr <= playbackSeq[45:23] * TRACK_LENGTH;
trackEndAddr <= playbackSeq[45:23] * TRACK_LENGTH + TRACK_LENGTH;
end
else begin
raddr <= playbackSeq[22:0] * TRACK_LENGTH;
trackEndAddr <= playbackSeq[22:0] * TRACK_LENGTH + TRACK_LENGTH;
end
end
end // if (~writeSwitch)
end // if (startSwitch)
else begin
// TO ENABLE RESET:
// writemode <= 1
// dowrite <= 0
// doread <= 0 // to be safe
// Reset First, Write Second, Read Later
writemode <= 1'h1;
doread <= 1'h0;
dowrite <= 1'h0;
end
end // always @
endmodule
|
#include <bits/stdc++.h> const int N = 1010; int sit[N], a[N]; int n, m, c; void ask(int x, int pos) { printf( %d n , pos); a[pos] = x; fflush(stdout); bool flag = true; for (int i = 1; i <= n; ++i) { if (!a[i]) { flag = false; break; } } for (int i = 1; i < n; ++i) { if (a[i] > a[i + 1]) { flag = false; break; } } if (flag) { exit(0); } if (x <= (c + 1) >> 1) { for (int i = x; i <= (c + 1) >> 1; ++i) { sit[i] = std::max(sit[i], pos + 1); } } else { for (int i = x; i > (c + 1) >> 1; --i) { sit[i] = std::min(sit[i], pos - 1); } } } int main() { scanf( %d%d%d , &n, &m, &c); for (int i = 1; i <= (c + 1) >> 1; ++i) { sit[i] = 1; } for (int i = c; i > (c + 1) >> 1; --i) { sit[i] = n; } while (true) { int x; scanf( %d , &x); ask(x, sit[x]); } }
|
#include <bits/stdc++.h> #pragma GCC optimize( -O3 ) using namespace std; void solve() { long long int n, k; cin >> n >> k; vector<long long int> a(n); for (long long int i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); long long int ones = 0; vector<long long int> b; for (long long int i = 0; i < k; i++) { long long int temp; cin >> temp; if (temp == 1) ones++; else b.push_back(temp); } sort(b.begin(), b.end(), greater<long long int>()); k = b.size(); long long int ans = accumulate(a.end() - 1 - ones + 1, a.end(), 0ll) * 2; long long int end = n - 1 - ones, beg = 0; for (long long int i = 0; i < k; i++) { long long int cur = b[i]; ans += (a[end]); cur--; end--; if (cur == 0) ans += (a[end + 1]); else { ans += a[beg]; beg += cur; } } cout << ans; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int __t; cin >> __t; while (__t--) { solve(); cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, s, k, x, y, z, i, j, ans = 0; int a[2001][2], b[2001][2]; int main() { memset(a, 192, sizeof a); memset(b, 63, sizeof b); cin >> n >> m >> k >> s; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) { cin >> x; a[x][0] = max(a[x][0], i + j); b[x][0] = min(b[x][0], i + j); a[x][1] = max(a[x][1], i - j); b[x][1] = min(b[x][1], i - j); } for (i = 1, z, y; i <= s; i++, y = z) { cin >> z; if (i > 1) ans = max(ans, max(max(a[y][0] - b[z][0], a[z][0] - b[y][0]), max(a[y][1] - b[z][1], a[z][1] - b[y][1]))); } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_pwrgood_pp$G (
UDP_OUT,
UDP_IN ,
VGND
);
output UDP_OUT;
input UDP_IN ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_BLACKBOX_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_optimized_clz_27(dataa, result);
// count the number of leading zeros in the 27-bit mantissa
input [31:0] dataa;
output [31:0] result;
wire all_zero;
acl_fp_custom_clz myclz( .mantissa(dataa[26:0]),
.result(result[4:0]),
.all_zero(all_zero));
assign result[5] = all_zero;
assign result[31:6] = 26'd0;
endmodule
|
/*
* Verilog side Virtual Processor, for running host
* programs as control in simulation.
*
* Copyright (c) 2004-2016 Simon Southwell.
*
* This file is part of VProc.
*
* VProc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* VProc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with VProc. If not, see <http://www.gnu.org/licenses/>.
*
* $Id: f_VProc.v,v 1.5 2021/05/15 07:45:17 simon Exp $
* $Source: /home/simon/CVS/src/HDL/VProc/f_VProc.v,v $
*/
`include "extradefs.v"
`VProcTimeScale
`define WEbit 0
`define RDbit 1
`define DeltaCycle -1
module VProc (Clk, Addr, WE, RD, DataOut, DataIn, WRAck, RDAck, Interrupt, Update, UpdateResponse, Node);
input Clk;
input RDAck;
input WRAck;
input UpdateResponse;
input [3:0] Node;
input [2:0] Interrupt;
input [31:0] DataIn;
output [31:0] Addr, DataOut;
output WE;
output RD;
output Update;
integer VPDataOut;
integer VPAddr;
integer VPRW;
integer VPTicks;
integer TickVal;
reg [31:0] DataOut;
integer DataInSamp;
reg [31:0] Addr;
integer IntSamp;
integer NodeI;
reg WE;
reg RD;
reg RdAckSamp;
reg WRAckSamp;
reg Initialised;
reg Update;
initial
begin
TickVal = 1;
Initialised = 0;
WE = 0;
RD = 0;
Update = 0;
// Don't remove delay! Needed to allow Node to be assigned
#0
$vinit(Node);
Initialised = 1;
end
always @(posedge Clk)
begin
// Cleanly sample the inputs and make them integers
DataInSamp = DataIn;
RdAckSamp = RDAck;
WRAckSamp = WRAck;
IntSamp = {1'b0, Interrupt};
NodeI = Node;
if (Initialised == 1'b1)
begin
if (IntSamp > 0)
begin
$vsched(NodeI, IntSamp, DataInSamp, VPDataOut, VPAddr, VPRW, VPTicks);
// If interrupt routine returns non-zero tick, then override
// current tick value. Otherwise, leave at present value.
if (VPTicks > 0)
begin
TickVal = VPTicks;
end
end
// If tick, write or a read has completed...
if ((RD === 1'b0 && WE === 1'b0 && TickVal === 0) ||
(RD === 1'b1 && RdAckSamp === 1'b1) ||
(WE === 1'b1 && WRAckSamp === 1'b1))
begin
// Host process message scheduler called
IntSamp = 0;
$vsched(NodeI, IntSamp, DataInSamp, VPDataOut, VPAddr, VPRW, VPTicks);
#`RegDel
WE = VPRW[`WEbit];
RD = VPRW[`RDbit];
DataOut = VPDataOut;
Addr = VPAddr;
Update = ~Update;
@(UpdateResponse);
// Update current tick value with returned number (if not zero)
if (VPTicks > 0)
begin
TickVal = VPTicks;
end
else if ( VPTicks < 0)
begin
while (VPTicks == `DeltaCycle)
begin
// Resample delta input data
DataInSamp = DataIn;
IntSamp = 0;
$vsched(NodeI, IntSamp, DataInSamp, VPDataOut, VPAddr, VPRW, VPTicks);
WE = VPRW[`WEbit];
RD = VPRW[`RDbit];
DataOut = VPDataOut;
Addr = VPAddr;
Update = ~Update;
if (VPTicks >= 0)
begin
TickVal = VPTicks;
end
@(UpdateResponse);
end
end
end
else
begin
// Count down to zero and stop
TickVal = (TickVal > 0) ? TickVal - 1 : 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> const int MAXN = 2e5 + 10; using namespace std; int T, N, cmp; int p[MAXN], c[MAXN]; vector<int> comp[MAXN]; bool vis[MAXN]; void dfs(int x) { vis[x] = true; comp[cmp].push_back(c[x]); if (!vis[p[x]]) dfs(p[x]); } int min_ans(int idx_comp) { int n_comp = (int)(comp[idx_comp].size()); vector<int> div; for (long long i = 1; i * i <= 1LL * n_comp; i++) if (n_comp % i == 0) { div.push_back((int)i); if (i * i != 1LL * n_comp) div.push_back((int)(n_comp / i)); } sort(div.begin(), div.end()); for (int d : div) for (int i = 0; i < d; i++) { int g = (i + d) % n_comp; bool found = true; while (g != i) { if (comp[idx_comp][g] != comp[idx_comp][i]) found = false; g = (g + d) % n_comp; } if (found) return d; } } inline void init() { cmp = 0; for (int i = 1; i < N + 1; i++) { vis[i] = false; comp[i].clear(); } } int main() { scanf( %d , &T); while (T--) { scanf( %d , &N); init(); for (int i = 1; i < N + 1; i++) scanf( %d , &p[i]); for (int i = 1; i < N + 1; i++) scanf( %d , &c[i]); for (int i = 1; i < N + 1; i++) if (!vis[i]) { cmp++; dfs(i); } int mn = N; for (int i = 1; i < cmp + 1; i++) mn = min(mn, min_ans(i)); printf( %d n , mn); } }
|
#include <bits/stdc++.h> using namespace std; const long long int MOD = 1000000007; const long long BIG = 1446803456761533460LL; const int Big = 336860180; const long long int INF = LONG_LONG_MAX; const long long int adj4[4][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; const long long int adj8[8][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}, {-1, -1}, {1, -1}, {-1, 1}, {1, 1}}; long long int clk_ar[10]; long long int gcd(long long int a, long long int b) { return b == 0 ? a : gcd(b, a % b); } long long int powMod(long long int a, long long int b) { long long int n = 1; long long int p = a; while (b > 0) { if (b % 2 == 1) { n *= p; n %= MOD; } p *= p; p %= MOD; b /= 2; } return n; } long long int modularInverse(long long int a) { return powMod(a, MOD - 2); } stringstream sss; const long long int maxn = 150010; const long long int maxm = 310; long long int dp[2][maxn]; long long int ts[maxm]; long long int ai[maxm]; void MAIN() { long long int n, m, V; cin >> n >> m >> V; long long int sb = 0; for (long long int i = 0; i < (m); ++i) { long long int b; cin >> ai[i + 1] >> b >> ts[i + 1]; --ai[i + 1]; sb += b; } for (long long int i = (1); i < (m + 1); ++i) { long long int d = (ts[i] - ts[i - 1]) * V; deque<long long int> q; for (long long int j = 0; j < (min(d, n)); ++j) { while (!q.empty() && dp[i & 1 ^ 1][j] >= dp[i & 1 ^ 1][q.back()]) { q.pop_back(); } q.push_back(j); } for (long long int j = 0; j < (n); ++j) { if (j + d < n) { while (!q.empty() && dp[i & 1 ^ 1][j + d] >= dp[i & 1 ^ 1][q.back()]) { q.pop_back(); } q.push_back(j + d); } dp[i & 1][j] = dp[i & 1 ^ 1][q.front()] - abs(j - ai[i]); if (q.front() == j - d) { q.pop_front(); } } } cout << (sb + *max_element(dp[m & 1], dp[m & 1] + n)) << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout << fixed << setprecision(10); sss << R ( 50 3 1 49 1 1 26 1 4 6 1 10 ) ; MAIN(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int arr[m + 1]; arr[0] = 1; for (int i = 1; i <= m; i++) cin >> arr[i]; long long step = 0; for (int i = 0; i < m; i++) { if (arr[i + 1] < arr[i]) step += (n - arr[i]) + (arr[i + 1] - 1) + 1; else step += arr[i + 1] - arr[i]; } cout << step; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_1_V
`define SKY130_FD_SC_MS__A22O_1_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22o_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_1_V
|
// Copyright (c) 2016 CERN
// @author Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Power and division remainder operators test
module vhdl_pow_rem_test;
integer a, b, pow_res, rem_res;
vhdl_pow_rem dut(a, b, pow_res, rem_res);
initial begin
a = 5;
b = 2;
if(pow_res != 25 || rem_res != 1) begin
$display("FAILED 1");
$finish();
end
a = -5;
b = 3;
if(rem_res != -2 || pow_res != -125) begin
$display("FAILED 2");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<unordered_set<long long>> v1(2e5), v2(2e5); void solve() { long long n, m; cin >> n >> m; for (auto i = 0; i < m; i++) { long long a, b; cin >> a >> b; a--; b--; v1[min(a, b)].insert(max(a, b)); } v2 = v1; long long count = 0; for (auto j = 0; j < n; j++) { if (v2[j].size() == 0) { count++; } } long long q; cin >> q; for (auto i = 0; i < q; i++) { long long a; cin >> a; if (a != 3) { long long b, c; cin >> b >> c; b--; c--; if (a == 1) { v2[min(b, c)].insert(max(b, c)); if (v2[min(b, c)].size() == 1) count -= 1; } else { v2[min(b, c)].erase(max(b, c)); if (v2[min(b, c)].size() == 0) count += 1; } } else { cout << count << n ; } } } int main() { solve(); }
|
#include <bits/stdc++.h> using namespace std; int n, q, k; vector<int> v[1000010]; int lastans = 0, res[1000010]; void dfs(int np, int fath, int val) { res[np] = val; for (auto &x : v[np]) { if (x == fath) continue; dfs(x, np, min(val, x)); } } int main() { scanf( %d%d , &n, &q); for (int i = 1, ti, tj; i < n; i++) { scanf( %d%d , &ti, &tj); v[ti].push_back(tj); v[tj].push_back(ti); } int a, b; scanf( %d%d , &a, &b); b = b % n + 1; dfs(b, 0, b); lastans = 0; k = b; for (int i = 2, ti, tj; i <= q; i++) { scanf( %d%d , &ti, &tj); tj = (tj + lastans) % n + 1; if (ti == 1) k = min(k, res[tj]); else printf( %d n , lastans = min(k, res[tj])); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001))
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off SHORTREAL
integer i;
reg [63:0] b;
shortreal r, r2;
integer cyc = 0;
realtime uninit;
initial if (uninit != 0.0) $stop;
initial begin
if (1_00_0.0_1 != 1000.01) $stop;
// rtoi truncates
if ($rtoi(36.7) != 36) $stop;
if ($rtoi(36.5) != 36) $stop;
if ($rtoi(36.4) != 36) $stop;
// casting rounds
if ((integer '(36.7)) != 37) $stop;
if ((integer '(36.5)) != 37) $stop;
if ((integer '(36.4)) != 36) $stop;
// assignment rounds
// verilator lint_off REALCVT
i = 36.7; if (i != 37) $stop;
i = 36.5; if (i != 37) $stop;
i = 36.4; if (i != 36) $stop;
r = 10'd38; if (r!=38.0) $stop;
// verilator lint_on REALCVT
// operators
if ((-(1.5)) != -1.5) $stop;
if ((+(1.5)) != 1.5) $stop;
if (((1.5)+(1.25)) != 2.75) $stop;
if (((1.5)-(1.25)) != 0.25) $stop;
if (((1.5)*(1.25)) != 1.875) $stop;
if (((1.5)/(1.25)) != 1.2) $stop;
//
if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0
if (((1.5)!=(2)) != 1'b1) $stop;
if (((1.5)> (2)) != 1'b0) $stop;
if (((1.5)>=(2)) != 1'b0) $stop;
if (((1.5)< (2)) != 1'b1) $stop;
if (((1.5)<=(2)) != 1'b1) $stop;
if (((1.5)==(1.5)) != 1'b1) $stop;
if (((1.5)!=(1.5)) != 1'b0) $stop;
if (((1.5)> (1.5)) != 1'b0) $stop;
if (((1.5)>=(1.5)) != 1'b1) $stop;
if (((1.5)< (1.5)) != 1'b0) $stop;
if (((1.5)<=(1.5)) != 1'b1) $stop;
if (((1.6)==(1.5)) != 1'b0) $stop;
if (((1.6)!=(1.5)) != 1'b1) $stop;
if (((1.6)> (1.5)) != 1'b1) $stop;
if (((1.6)>=(1.5)) != 1'b1) $stop;
if (((1.6)< (1.5)) != 1'b0) $stop;
if (((1.6)<=(1.5)) != 1'b0) $stop;
//
if (((0.0)?(2.0):(1.1)) != 1.1) $stop;
if (((1.5)?(2.0):(1.1)) != 2.0) $stop;
//
if (!1.7) $stop;
if (!(!0.0)) $stop;
if (1.8 && 0.0) $stop;
if (!(1.8 || 0.0)) $stop;
//
i=0;
for (r=1.0; r<2.0; r=r+0.1) i++;
if (i!=10) $stop;
// bug
r = $bitstoshortreal($shortrealtobits(1.414));
if (r != 1.414) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
end
else if (cyc<90) begin
if ($time != {32'h0, $rtoi($realtime)}) $stop;
if ($itor(cyc) != cyc) $stop;
//Unsup: if ((real `($time)) != $realtime) $stop;
r = $itor(cyc*2);
i = $rtoi(r);
if (i!=cyc*2) $stop;
//
r = $itor(cyc)/1.5;
b = $realtobits(r);
r2 = $bitstoreal(b);
if (r != r2) $stop;
//
// Trust the integer math as a comparison
r = $itor(cyc);
if ($rtoi(-r) != -cyc) $stop;
if ($rtoi(+r) != cyc) $stop;
if ($rtoi(r+2.0) != (cyc+2)) $stop;
if ($rtoi(r-2.0) != (cyc-2)) $stop;
if ($rtoi(r*2.0) != (cyc*2)) $stop;
if ($rtoi(r/2.0) != (cyc/2)) $stop;
r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash
//
r2 = $itor(cyc);
case (r)
(r2-1.0): $stop;
r2: ;
default: $stop;
endcase
//
r = $itor(cyc);
if ((r==50.0) != (cyc==50)) $stop;
if ((r!=50.0) != (cyc!=50)) $stop;
if ((r> 50.0) != (cyc> 50)) $stop;
if ((r>=50.0) != (cyc>=50)) $stop;
if ((r< 50.0) != (cyc< 50)) $stop;
if ((r<=50.0) != (cyc<=50)) $stop;
//
if ($rtoi((r-50.0) ? 10.0 : 20.0)
!= (((cyc-50)!=0) ? 10 : 20)) $stop;
//
if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
// local paramaters used as defines
parameter TIME_START = 1'b0;
parameter TIME_CHECK = 1'b1;
reg [31:0] i;
reg r_state;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=TIME_START;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
TIME_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (start_event == 1'b1) begin
r_state <= TIME_CHECK;
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
end
TIME_CHECK: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// Count clock ticks
if (start_event == 1'b1) begin
if (action_on_new_start == `OVL_IGNORE_NEW_START)
i <= i-1;
else if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
ovl_cover_t("window_resets covered");
end
end
end
`endif // OVL_COVER_ON
end
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
i <= i-1;
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Illegal start event which has reoccured before completion of current window");
`endif // OVL_ASSERT_ON
end
end
else
i <= i-1;
// Check that the property is true
`ifdef OVL_ASSERT_ON
if (test_expr != 1'b1 &&
!(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE within specified num_cks cycles from the start_event");
end
`endif // OVL_ASSERT_ON
// go to start state on last time check
// NOTE: i == 0 at end of current simulation
// timeframe due to non-blocking assignment!
// Hence, check i == 1.
if (i == 1 && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START))
begin
r_state <= TIME_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_close covered");
end
end
`endif // OVL_COVER_ON
end
end
endcase
end
else begin
r_state <= TIME_START;
i <= {32{1'b0}};
end
end // always
`endif // OVL_SHARED_CODE
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e5 + 5; int n; int ans[inf]; int last[inf]; struct node { int x, h, q; bool operator<(const node &s) const { return s.x > x; } } a[inf << 1]; inline int read() { int a = 0; int b = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) b = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { a = a * 10 + c - 0 ; c = getchar(); } return a * b; } inline void run() { int x, y; n = read(); for (int i = 1; i <= n; i++) { x = read(); y = read(); a[i].x = x; a[i].h = y; a[i].q = i; } sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) { ans[i] = 1; } for (int i = n - 1; i > 0; i--) { int now = i + 1; while (now && ((a[i].x + a[i].h) > a[now].x)) { ans[a[i].q] += ans[a[now].q]; now = last[now]; } last[i] = now; } for (int i = 1; i <= n; i++) { cout << ans[i] << ; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double pi = 3.1415926535897932384626433832795l; template <typename T> inline auto sqr(T x) -> decltype(x * x) { return x * x; } template <typename T1, typename T2> inline bool umx(T1& a, T2 b) { if (a < b) { a = b; return 1; } return 0; } template <typename T1, typename T2> inline bool umn(T1& a, T2 b) { if (b < a) { a = b; return 1; } return 0; } const int N = 2000; struct Input { int n; string s[N]; bool read() { if (!(cin >> n)) { return 0; } getline(cin, s[0]); for (int i = int(0); i < int(n); ++i) { getline(cin, s[i]); } return 1; } void init(const Input& input) { *this = input; } }; struct Data : Input { vector<int> ans[N]; void write() { for (int i = int(0); i < int(n); ++i) { printf( %d , ((int)(ans[i]).size())); for (int j = int(0); j < int(((int)(ans[i]).size())); ++j) { printf( %d , ans[i][j]); } puts( ); } } virtual void solve() {} virtual void clear() { *this = Data(); } }; struct Solution : Data { static const int L = (N + 63) >> 6; unsigned long long m[N][L]; unsigned long long u[N][L]; bool need[N]; int pos[N]; void solve() { memset(m, 0, sizeof m); for (int i = int(0); i < int(n); ++i) { vector<unsigned long long> q((((int)(s[i]).size()) + 8) / 9, 0); for (int j = int(((int)(s[i]).size())) - 1; j >= int(0); --j) { (q[((int)(q).size()) - 1 - j / 9] *= 10) += s[i][((int)(s[i]).size()) - 1 - j] - 0 ; } for (int k = int(0); k < int(L * 2); ++k) { unsigned long long r = 0; for (int j = int(0); j < int(((int)(q).size())); ++j) { q[j] += r * 1000000000; r = q[j] & ((1ull << 32) - 1); q[j] >>= 32; } m[i][k >> 1] |= r << (32 * (k & 1)); } } memset(u, 0, sizeof u); for (int i = int(0); i < int(n); ++i) { u[i][i >> 6] |= 1ull << (i & 63); for (int j = int(0); j < int(i); ++j) if (need[j]) { if (m[i][pos[j] >> 6] & (1ull << (pos[j] & 63))) { for (int k = int(0); k < int(L); ++k) { m[i][k] ^= m[j][k]; } for (int k = int(0); k < int((i + 63) >> 6); ++k) { u[i][k] ^= u[j][k]; } } } need[i] = 0; for (int j = int(0); j < int(N); ++j) { if (m[i][j >> 6] & (1ull << (j & 63))) { need[i] = 1; pos[i] = j; break; } } if (!need[i]) { for (int j = int(0); j < int(i); ++j) { if (u[i][j >> 6] & (1ull << (j & 63))) { ans[i].push_back(j); } } } } } void clear() { *this = Solution(); } }; Solution sol; int main() { cout.setf(ios::showpoint | ios::fixed); cout.precision(20); sol.read(); sol.solve(); sol.write(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5; bool isprime[32000]; vector<int> prime; int a[maxn + 50], num[maxn + 50], factor[maxn + 50], now[maxn + 50]; int k, n, len = 0; long long ans = 0; bool check() { for (int i = 1; i <= len; ++i) if (now[i] < num[i]) return false; return true; } void make(int x, int type) { for (int i = 1; i <= len; ++i) { if (x % factor[i] != 0) continue; if (factor[i] == 1) { now[i] += type; continue; } while (x % factor[i] == 0) { x /= factor[i]; now[i] += type; } if (x == 1) break; } } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); isprime[1] = 1; for (int i = 2; i <= sqrt(k); ++i) if (!isprime[i]) { prime.push_back(i); for (int j = i + i; j <= sqrt(k); j += i) isprime[j] = 1; } ++len; factor[len] = 1; num[len] = 1; for (int i = 0; i < prime.size(); ++i) { if (k % prime[i] != 0) continue; factor[++len] = prime[i]; while (k % prime[i] == 0) { k /= prime[i]; ++num[len]; } if (k == 1) break; } if (k != 1) factor[++len] = k, num[len] = 1; int r = 0; for (int l = 1; l <= n; ++l) { while (!check() && r < n) { ++r; make(a[r], 1); } if (check()) ans += n - r + 1; make(a[l], -1); } printf( %lld n , ans); return 0; }
|
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2c_master
*/
module test_i2c_master;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [6:0] s_axis_cmd_address = 0;
reg s_axis_cmd_start = 0;
reg s_axis_cmd_read = 0;
reg s_axis_cmd_write = 0;
reg s_axis_cmd_write_multiple = 0;
reg s_axis_cmd_stop = 0;
reg s_axis_cmd_valid = 0;
reg [7:0] s_axis_data_tdata = 0;
reg s_axis_data_tvalid = 0;
reg s_axis_data_tlast = 0;
reg m_axis_data_tready = 0;
reg scl_i = 1;
reg sda_i = 1;
reg [15:0] prescale = 0;
reg stop_on_idle = 0;
// Outputs
wire s_axis_cmd_ready;
wire s_axis_data_tready;
wire [7:0] m_axis_data_tdata;
wire m_axis_data_tvalid;
wire m_axis_data_tlast;
wire scl_o;
wire scl_t;
wire sda_o;
wire sda_t;
wire busy;
wire bus_control;
wire bus_active;
wire missed_ack;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_cmd_address,
s_axis_cmd_start,
s_axis_cmd_read,
s_axis_cmd_write,
s_axis_cmd_write_multiple,
s_axis_cmd_stop,
s_axis_cmd_valid,
s_axis_data_tdata,
s_axis_data_tvalid,
s_axis_data_tlast,
m_axis_data_tready,
scl_i,
sda_i,
prescale,
stop_on_idle
);
$to_myhdl(
s_axis_cmd_ready,
s_axis_data_tready,
m_axis_data_tdata,
m_axis_data_tvalid,
m_axis_data_tlast,
scl_o,
scl_t,
sda_o,
sda_t,
busy,
bus_control,
bus_active,
missed_ack
);
// dump file
$dumpfile("test_i2c_master.lxt");
$dumpvars(0, test_i2c_master);
end
i2c_master
UUT (
.clk(clk),
.rst(rst),
.s_axis_cmd_address(s_axis_cmd_address),
.s_axis_cmd_start(s_axis_cmd_start),
.s_axis_cmd_read(s_axis_cmd_read),
.s_axis_cmd_write(s_axis_cmd_write),
.s_axis_cmd_write_multiple(s_axis_cmd_write_multiple),
.s_axis_cmd_stop(s_axis_cmd_stop),
.s_axis_cmd_valid(s_axis_cmd_valid),
.s_axis_cmd_ready(s_axis_cmd_ready),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tvalid(s_axis_data_tvalid),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tlast(s_axis_data_tlast),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tlast(m_axis_data_tlast),
.scl_i(scl_i),
.scl_o(scl_o),
.scl_t(scl_t),
.sda_i(sda_i),
.sda_o(sda_o),
.sda_t(sda_t),
.busy(busy),
.bus_control(bus_control),
.bus_active(bus_active),
.missed_ack(missed_ack),
.prescale(prescale),
.stop_on_idle(stop_on_idle)
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC_OPTIMIZE( ofast ) using namespace std; void solve() { long long n, k; cin >> n >> k; string s; cin >> s; string need; for (long long i = 0; i < k - 1; i++) { need.push_back( ( ); need.push_back( ) ); } for (long long i = 0; i < n / 2 - (k - 1); i++) { need.push_back( ( ); } for (long long i = 0; i < n / 2 - (k - 1); i++) { need.push_back( ) ); } vector<pair<long long, long long>> ans; for (long long i = 0; i < n; i++) { if (s[i] != need[i]) { for (long long j = i + 1; j < n; j++) { if (s[j] == need[i]) { ans.push_back(make_pair(i + 1, j + 1)); reverse(s.begin() + i, s.begin() + j + 1); break; } } } } cout << ans.size() << n ; for (long long i = 0; i < ans.size(); i++) { cout << ans[i].first << << ans[i].second << n ; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long q; cin >> q; for (long long i = 0; i < q; i++) { solve(); } }
|
// $Id: c_binary_op.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// n-input generic binary operator
//==============================================================================
module c_binary_op
(data_in, data_out);
`include "c_constants.v"
// number of inputs
parameter num_ports = 2;
// width of each input
parameter width = 1;
// select operator
parameter op = `BINARY_OP_XOR;
// vector of inputs
input [0:width*num_ports-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:bit_positions
wire [0:num_ports-1] data;
genvar j;
for(j = 0; j < num_ports; j = j + 1)
begin:input_ports
assign data[j] = data_in[j*width+i];
end
case(op)
`BINARY_OP_AND:
assign data_out[i] = &data;
`BINARY_OP_NAND:
assign data_out[i] = ~&data;
`BINARY_OP_OR:
assign data_out[i] = |data;
`BINARY_OP_NOR:
assign data_out[i] = ~|data;
`BINARY_OP_XOR:
assign data_out[i] = ^data;
`BINARY_OP_XNOR:
assign data_out[i] = ~^data;
endcase
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_LP2_V
`define SKY130_FD_SC_LP__ISO0N_LP2_V
/**
* iso0n: ????.
*
* Verilog wrapper for iso0n with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso0n.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso0n_lp2 (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__iso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.KAGND(KAGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso0n_lp2 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__iso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_LP2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_1_V
`define SKY130_FD_SC_LS__DLYGATE4SD2_1_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog wrapper for dlygate4sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlygate4sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlygate4sd2_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlygate4sd2_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD2_1_V
|
#include <bits/stdc++.h> using namespace std; const static int inf = 10000000; const static int mod = 1000000007; int check(const vector<string>& s, const vector<string>& t) { int n = s.size(); vector<int> idx(n); for (int i = 0; i < (int)(n); i++) { idx[i] = i; } int ret = 0; do { vector<string> ss(n); for (int i = 0; i < (int)(n); i++) { ss[i] = s[idx[i]]; } int pos = 0; for (int i = 0; i < t.size() && pos < s.size(); ++i) { if (ss[pos] == t[i]) { ++pos; } } if (pos != s.size()) { continue; } int inv = 0; for (int i = 0; i < (int)(n); i++) { for (int j = i + 1; j < n; ++j) { if (idx[i] > idx[j]) { ++inv; } } } int buf = n * (n - 1) / 2 - inv + 1; ret = max(ret, buf); } while (next_permutation((idx).begin(), (idx).end())); return ret; } int main() { int n; while (cin >> n) { vector<string> s(n); for (int i = 0; i < (int)(n); i++) { cin >> s[i]; } int mxp = 0; int idx = -1; int k; cin >> k; for (int i = 0; i < (int)(k); i++) { int m; cin >> m; vector<string> t(m); for (int j = 0; j < (int)(m); j++) { cin >> t[j]; } int p = check(s, t); if (p > mxp) { mxp = p; idx = i; } } if (idx == -1) { cout << Brand new problem! << endl; } else { cout << idx + 1 << endl; cout << [: ; for (int i = 0; i < (int)(mxp); i++) { cout << | ; } cout << :] << endl; } } return 0; }
|
module trafficlight_controller (input wire clk,
input wire rst,
output reg light1_green,
output reg light1_red,
output reg light1_yellow,
output reg light2_green,
output reg light2_red,
output reg light2_yellow);
reg [1:0] current_state;
reg [1:0] next_state;
reg [15:0] counter_value;
localparam F100HZ_DELAY_60SEC_CC_CNT = 16'd6000;
localparam F100HZ_DELAY_5SEC_CC_CNT = 16'd500;
localparam STATE_GR = 2'b00;
localparam STATE_YR = 2'b01;
localparam STATE_RG = 2'b10;
localparam STATE_RY = 2'b11;
// Current state s(k) = delay[s(k+1)], where s(k+1) = next state
always @ ( posedge clk, posedge rst ) begin
if( rst )
begin
current_state <= STATE_GR;
end
else
begin
current_state <= next_state;
end
end
// Counter for time delays
always @ ( posedge clk, posedge rst ) begin
if( rst )
begin
counter_value <= 16'b0;
end
else
begin
case (current_state)
STATE_GR, STATE_RG:
// Wait for 60 sec
if( counter_value < F100HZ_DELAY_60SEC_CC_CNT )
counter_value <= counter_value + 1'b1;
else
counter_value <= 16'b0;
STATE_YR, STATE_RY:
// Wait for 5 sec
if( counter_value < F100HZ_DELAY_5SEC_CC_CNT )
counter_value <= counter_value + 1'b1;
else
counter_value <= 16'b0;
endcase
end
end
// Next State function: s(k+1) = f[i(k), s(k)]
always @ ( * ) begin
case (current_state)
STATE_GR:
// Wait for 60 sec
if( counter_value < F100HZ_DELAY_60SEC_CC_CNT )
next_state <= STATE_GR;
else
next_state <= STATE_YR;
STATE_YR:
// Wait for 5 sec
if( counter_value < F100HZ_DELAY_5SEC_CC_CNT )
next_state <= STATE_YR;
else
next_state <= STATE_RG;
STATE_RG:
// Wait for 60 sec
if( counter_value < F100HZ_DELAY_60SEC_CC_CNT )
next_state <= STATE_RG;
else
next_state <= STATE_RY;
STATE_RY:
// Wait for 5 sec
if( counter_value < F100HZ_DELAY_5SEC_CC_CNT )
next_state <= STATE_RY;
else
next_state <= STATE_GR;
default:
next_state <= STATE_GR;
endcase
end
// Output function : o(k) = g[s(k)]
always @ ( * ) begin
// default all lights OFF
light1_green <= 1'b0;
light1_red <= 1'b0;
light1_yellow <= 1'b0;
light2_green <= 1'b0;
light2_red <= 1'b0;
light2_yellow <= 1'b0;
case (current_state)
STATE_GR:
begin
light1_green <= 1'b1;
light2_red <= 1'b1;
end
STATE_YR:
begin
light1_yellow <= 1'b1;
light2_red <= 1'b1;
end
STATE_RG:
begin
light1_red <= 1'b1;
light2_green <=1'b1;
end
STATE_RY:
begin
light1_red <= 1'b1;
light2_yellow <= 1'b1;
end
default:
begin
light1_green <= 1'b1;
light1_red <= 1'b1;
light1_yellow <= 1'b1;
light2_green <= 1'b1;
light2_red <= 1'b1;
light2_yellow <= 1'b1;
end
endcase
end
endmodule //
|
#include <bits/stdc++.h> using namespace std; int n; string s; int dp[111][55][222][3]; int res; void dfs(int pos, int left, int x, int dx) { if (dp[pos][left][x + 100][dx + 1]) return; dp[pos][left][x + 100][dx + 1] = 1; if (pos == s.size()) { if (left == 0) res = max(res, abs(x)); return; } for (int i = 0; i <= left; i++) { int ddx = (s[pos] == F ); if (i % 2 == 1) ddx = !ddx; dfs(pos + 1, left - i, x + (ddx == 1 ? dx : 0), dx * (ddx == 0 ? -1 : 1)); } } int main() { cin >> s; cin >> n; dfs(0, n, 0, 1); cout << res << endl; return 0; }
|
module InstMod ( ins, outs );
output [INWIDTH-1:0] ins;
output [OUTWIDTH-1:0] outs;
endmodule
module test_top;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [n*INWIDTH +: INWIDTH] ins; // From instName of InstMod.v
wire [n*INWIDTH +: INWIDTH] ins2; // From instName2 of InstMod.v
wire [n*INWIDTH +: INWIDTH] ins3; // From instName3 of InstMod.v, ..., Couldn't Merge
wire [n*OUTWIDTH +: OUTWIDTH] outs; // From instName of InstMod.v
wire [n*OUTWIDTH +: OUTWIDTH] outs2; // From instName2 of InstMod.v
wire [4*OUTWIDTH-1 : 0] outs3; // From instName3 of InstMod.v, ..., Couldn't Merge
// End of automatics
genvar i;
generate
for (i=0; i<4; i=i+1) begin
/*AUTO_LISP(setq vh-n 4)*/
/* InstMod AUTO_TEMPLATE
(.ins (ins [n*INWIDTH +: INWIDTH]),
.outs (outs[n*OUTWIDTH +: OUTWIDTH])); */
InstMod instName (/*AUTOINST*/
// Outputs
.ins (ins [n*INWIDTH +: INWIDTH]), // Templated
.outs (outs[n*OUTWIDTH +: OUTWIDTH])); // Templated
InstMod instName2
(// Inputs
.ins (ins2 [n*INWIDTH +: INWIDTH]),
// Outputs
.outs (outs2[n*OUTWIDTH +: OUTWIDTH])
/*AUTOINST*/);
// This works but is ugly
InstMod instName3
(// Inputs
.ins (ins3 [n*INWIDTH +: INWIDTH]),
// Outputs
.outs (outs3[n*OUTWIDTH +: OUTWIDTH])
`ifdef NEVER
// Inouts
.ins (ins3 [4*INWIDTH-1 : 0]),
.outs (outs3[4*OUTWIDTH-1 : 0])
`endif
/*AUTOINST*/);
end
endgenerate
endmodule
|
/*
###########################################################################
# **EMMU**
#
# This block uses the upper 12 bits [31:20] of a memory address as an index
# to read an entry from a table.
#
# The table is written from the mi_* configuration interface.
#
# The table can be configured as 12 bits wide or 44 bits wide.
#
# 32bit address output = {table_data[11:0],dstaddr[19:0]}
# 64bit address output = {table_data[43:0],dstaddr[19:0]}
#
############################################################################
*/
module emmu (/*AUTOARG*/
// Outputs
mi_dout, emesh_access_out, emesh_packet_out, emesh_packet_hi_out,
// Inputs
reset, rd_clk, wr_clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr,
mi_din, emesh_access_in, emesh_packet_in, emesh_rd_wait,
emesh_wr_wait
);
parameter DW = 32; //data width
parameter AW = 32; //address width
parameter PW = 104;
parameter EPW = 136; //extended by 32 bits
parameter MW = 48; //width of table
parameter MAW = 12; //memory addres width (entries = 1<<MAW)
parameter GROUP = 0;
/*****************************/
/*DATAPATH CLOCk */
/*****************************/
input reset; //async reset
input rd_clk;
input wr_clk;
/*****************************/
/*MMU LOOKUP DATA */
/*****************************/
input mmu_en; //enables mmu (static)
input mmu_bp; //bypass mmu on read response
/*****************************/
/*Register Access Interface */
/*****************************/
input mi_en; //memory access
input mi_we; //byte wise write enable
input [14:0] mi_addr; //address
input [DW-1:0] mi_din; //input data
output [DW-1:0] mi_dout; //read back (TODO?? not implemented)
/*****************************/
/*EMESH INPUTS */
/*****************************/
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
input emesh_rd_wait;
input emesh_wr_wait;
/*****************************/
/*EMESH OUTPUTS */
/*****************************/
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
output [31:0] emesh_packet_hi_out;
/*****************************/
/*REGISTERS */
/*****************************/
reg emesh_access_out;
reg [PW-1:0] emesh_packet_reg;
wire [63:0] emesh_dstaddr_out;
wire [MW-1:0] emmu_lookup_data;
wire [63:0] mi_wr_data;
wire [5:0] mi_wr_vec;
wire mi_match;
wire [MW-1:0] emmu_rd_addr;
wire write_in;
/*****************************/
/*MMU WRITE LOGIC */
/*****************************/
//write controls
assign mi_wr_vec[5:0] = (mi_en & mi_we & ~mi_addr[2]) ? 6'b001111 :
(mi_en & mi_we & mi_addr[2]) ? 6'b110000 :
6'b000000 ;
//write data
assign mi_wr_data[63:0] = {mi_din[31:0], mi_din[31:0]};
//todo: implement readback? worth it?
assign mi_dout[DW-1:0] = 'b0;
/*****************************/
/*MMU READ LOGIC */
/*****************************/
//TODO: could we do with less entries?
assign write_in = emesh_packet_in[1];
assign emmu_rd_addr[MAW-1:0] = emesh_packet_in[39:28];
memory_dp #(.DW(MW),.AW(MAW)) memory_dp (
// Outputs
.rd_data (emmu_lookup_data[MW-1:0]),
// Inputs
.wr_clk (wr_clk),
.wr_en (mi_wr_vec[5:0]),
.wr_addr (mi_addr[14:3]),
.wr_data (mi_wr_data[MW-1:0]),
.rd_clk (rd_clk),
.rd_en (emesh_access_in),
.rd_addr (emmu_rd_addr[MAW-1:0])
);
/*****************************/
/*EMESH OUTPUT TRANSACTION */
/*****************************/
//pipeline to compensate for table lookup pipeline
//assumes one cycle memory access!
always @ (posedge rd_clk or posedge reset)
if (reset)
begin
emesh_access_out <= 1'b0;
end
else if((write_in & ~emesh_wr_wait) | (~write_in & ~emesh_rd_wait))
begin
emesh_access_out <= emesh_access_in;
emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0];
end
assign emesh_dstaddr_out[63:0] = (mmu_en & ~mmu_bp) ? {emmu_lookup_data[43:0], emesh_packet_reg[27:8]} :
{32'b0,emesh_packet_reg[39:8]};
//Concatenating output packet
assign emesh_packet_out[PW-1:0] = {emesh_packet_reg[PW-1:40],
emesh_dstaddr_out[31:0],
emesh_packet_reg[7:0]
};
assign emesh_packet_hi_out[31:0] = emesh_dstaddr_out[63:32];
endmodule // emmu
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../memory/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5; long long n, m; map<long long, long long> mp; long long ans[N], top; signed main() { cin >> n >> m; for (long long i = 1; i <= n; ++i) { long long x; cin >> x; mp[x] = 1; } for (long long i = 1; 26 > 30 / 39 / 57; ++i) { if (mp[i] == 0) { m -= i; if (m < 0) { break; } ans[++top] = i; } } cout << top << endl; for (long long i = 1; i <= top; ++i) { cout << ans[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, M; long double DP[1010][1010]; int i, j; int total, X; int main() { cin >> N >> M; DP[0][0] = 1.0; for (int i = 1; i <= N; i++) for (int j = 0; j <= M && j <= N; j++) { total = N * M - (i - 1); X = M - j; DP[i][j] += DP[i - 1][j] * (1.0 * total - X) / (1.0 * total); if (j > 0) { total = N * M - (i - 1); X = M - j + 1; DP[i][j] += DP[i - 1][j - 1] * (1.0 * X) / (1.0 * total); } } long double ans = 0; for (int i = 1; i <= N; i++) ans += (1.0 * i) * (1.0 * i) / (1.0 * N) * DP[N][i]; cout << fixed << setprecision(20) << ans << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_TB_V
`define SKY130_FD_SC_HDLL__SEDFXBP_TB_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sedfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 DE = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 DE = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 DE = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 DE = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sedfxbp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND4BB_PP_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; char m = b ; int ans = 0; int k = 0, bm = 0, rm = 0; while (k < n) { if (s[k] == m) { if (m == b ) m = r ; else m = b ; k++; } else { if (s[k] == b ) bm++; else rm++; if (m == b ) m = r ; else m = b ; k++; } } int ans1 = min(bm, rm) + abs(rm - bm); m = r ; k = 0, bm = 0, rm = 0; while (k < n) { if (s[k] == m) { if (m == b ) m = r ; else m = b ; k++; } else { if (s[k] == b ) bm++; else rm++; if (m == b ) m = r ; else m = b ; k++; } } int ans2 = min(bm, rm) + abs(rm - bm); cout << min(ans1, ans2) << endl; return 0; }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; using Int = long long; template <typename T1, typename T2> inline void chmin(T1 &a, T2 b) { if (a > b) a = b; } template <typename T1, typename T2> inline void chmax(T1 &a, T2 b) { if (a < b) a = b; } struct FastIO { FastIO() { cin.tie(0); ios::sync_with_stdio(0); } } fastio_beet; signed main() { Int n; cin >> n; vector<Int> bs(n); for (Int i = 0; i < n; i++) cin >> bs[i]; map<Int, Int> sum; for (Int i = 0; i < n; i++) sum[bs[i] - i] += bs[i]; Int ans = 0; for (auto p : sum) chmax(ans, p.second); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int ara[n]; int temp, j; int i = 0; while (i < n) { scanf( %d , &ara[i]); i++; } i = 0; while (i < (n - 1)) { j = 0; while (j < (n - 1)) { if (ara[j] > ara[j + 1]) { temp = ara[j]; ara[j] = ara[j + 1]; ara[j + 1] = temp; } j++; } i++; } i = 0; while (i < n) { printf( %d , ara[i]); i++; } return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eg_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eg_e.v,v 1.1 2004/04/06 10:50:55 wig Exp $
// $Date: 2004/04/06 10:50:55 $
// $Log: inst_eg_e.v,v $
// Revision 1.1 2004/04/06 10:50:55 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_eg_e
//
// No `defines in this module
module inst_eg_e
//
// Generated module inst_eg
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_eg_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; char s1[N], s2[N], s[N]; int n, lst, nod, len[N], fail[N], diff[N], anc[N], ch[N][26]; int f[N], pos[N], pre[N]; void init() { fail[0] = fail[1] = nod = 1; len[1] = -1; } void extend(int c, int i) { int p = lst; while (s[i - len[p] - 1] != s[i]) p = fail[p]; if (!ch[p][c]) { int x = ++nod, k = fail[p]; while (s[i - len[k] - 1] != s[i]) k = fail[k]; fail[x] = ch[k][c]; ch[p][c] = x; len[x] = len[p] + 2; diff[x] = len[x] - len[fail[x]]; anc[x] = (diff[x] == diff[fail[x]]) ? anc[fail[x]] : fail[x]; } lst = ch[p][c]; } int main() { scanf( %s%s , s1 + 1, s2 + 1); n = strlen(s1 + 1); init(); for (int i = 1; i <= n * 2; i++) s[i] = (i & 1) ? s1[(i + 1) / 2] : s2[i / 2]; for (int i = 1; i <= n * 2; i++) f[i] = 1e9; for (int i = 1; i <= n * 2; i++) { extend(s[i] - a , i); for (int k = lst; k; k = anc[k]) { pos[k] = i - len[anc[k]] - diff[k]; if (anc[k] != fail[k] && f[pos[fail[k]]] < f[pos[k]]) pos[k] = pos[fail[k]]; if (!(i & 1) && f[i] > f[pos[k]] + 1) f[i] = f[pos[k]] + 1, pre[i] = pos[k]; } if (!(i & 1) && s[i] == s[i - 1] && f[i - 2] <= f[i]) f[i] = f[i - 2], pre[i] = i - 2; } if (f[n * 2] >= 1e9) return puts( -1 ), 0; printf( %d n , f[n * 2]); for (int i = n * 2; i; i = pre[i]) if (i - pre[i] > 2) printf( %d %d n , pre[i] / 2 + 1, i >> 1); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41A_SYMBOL_V
`define SKY130_FD_SC_HD__O41A_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41A_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) using namespace std; using ll = long long; template <class t, class u> bool chmax(t& first, u second) { if (first < second) { first = second; return true; } else return false; } template <class t, class u> bool chmin(t& first, u second) { if (second < first) { first = second; return true; } else return false; } template <class t> using vc = vector<t>; template <class t> using vvc = vc<vc<t>>; using pi = pair<ll, ll>; using vi = vc<ll>; template <class t, class u> ostream& operator<<(ostream& os, const pair<t, u>& p) { return os << { << p.first << , << p.second << } ; } template <class t> ostream& operator<<(ostream& os, const vc<t>& v) { os << { ; for (auto e : v) os << e << , ; return os << } ; } using uint = unsigned; using ull = unsigned long long; template <class t, size_t n> ostream& operator<<(ostream& os, const array<t, n>& first) { return os << vc<t>(first.begin(), first.end()); } template <ll i, class T> void print_tuple(ostream&, const T&) {} template <ll i, class T, class H, class... Args> void print_tuple(ostream& os, const T& t) { if (i) os << , ; os << get<i>(t); print_tuple<i + 1, T, Args...>(os, t); } template <class... Args> ostream& operator<<(ostream& os, const tuple<Args...>& t) { os << { ; print_tuple<0, tuple<Args...>, Args...>(os, t); return os << } ; } template <class t> void print(t x, ll suc = 1) { cout << x; if (suc == 1) cout << n ; if (suc == 2) cout << ; } ll read() { ll i; cin >> i; return i; } vi readvi(ll n, ll off = 0) { vi v(n); for (ll i = ll(0); i < ll(n); i++) v[i] = read() + off; return v; } pi readpi(ll off = 0) { ll first, second; cin >> first >> second; return pi(first + off, second + off); } template <class t, class u> void print(const pair<t, u>& p, ll suc = 1) { print(p.first, 2); print(p.second, suc); } template <class T> void print(const vector<T>& v, ll suc = 1) { for (ll i = ll(0); i < ll(v.size()); i++) print(v[i], i == ll(v.size()) - 1 ? suc : 2); } template <class T> void print_offset(const vector<T>& v, ll off, ll suc = 1) { for (ll i = ll(0); i < ll(v.size()); i++) print(v[i] + off, i == ll(v.size()) - 1 ? suc : 2); } template <class T, size_t N> void print(const array<T, N>& v, ll suc = 1) { for (ll i = ll(0); i < ll(N); i++) print(v[i], i == ll(N) - 1 ? suc : 2); } string readString() { string s; cin >> s; return s; } template <class T> T sq(const T& t) { return t * t; } void yes(bool ex = true) { cout << Yes << n ; if (ex) exit(0); } void no(bool ex = true) { cout << No << n ; if (ex) exit(0); } void possible(bool ex = true) { cout << Possible << n ; if (ex) exit(0); } void impossible(bool ex = true) { cout << Impossible << n ; if (ex) exit(0); } constexpr ll ten(ll n) { return n == 0 ? 1 : ten(n - 1) * 10; } const ll infLL = LLONG_MAX / 3; const ll inf = infLL; ll topbit(signed t) { return t == 0 ? -1 : 31 - __builtin_clz(t); } ll topbit(ll t) { return t == 0 ? -1 : 63 - __builtin_clzll(t); } ll botbit(signed first) { return first == 0 ? 32 : __builtin_ctz(first); } ll botbit(ll first) { return first == 0 ? 64 : __builtin_ctzll(first); } ll popcount(signed t) { return __builtin_popcount(t); } ll popcount(ll t) { return __builtin_popcountll(t); } bool ispow2(ll i) { return i && (i & -i) == i; } ll mask(ll i) { return (ll(1) << i) - 1; } bool inc(ll first, ll second, ll c) { return first <= second && second <= c; } template <class t> void mkuni(vc<t>& v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); } ll rand_int(ll l, ll r) { static mt19937_64 gen(chrono::steady_clock::now().time_since_epoch().count()); return uniform_int_distribution<ll>(l, r)(gen); } template <class t> void myshuffle(vc<t>& first) { for (ll i = ll(0); i < ll(ll(first.size())); i++) swap(first[i], first[rand_int(0, i)]); } template <class t> ll lwb(const vc<t>& v, const t& first) { return lower_bound(v.begin(), v.end(), first) - v.begin(); } vvc<ll> readGraph(ll n, ll m) { vvc<ll> g(n); for (ll i = ll(0); i < ll(m); i++) { ll first, second; cin >> first >> second; first--; second--; g[first].push_back(second); g[second].push_back(first); } return g; } vvc<ll> readTree(ll n) { return readGraph(n, n - 1); } struct modinfo { uint mod, root; }; template <modinfo const& ref> struct modular { static constexpr uint const& mod = ref.mod; static modular root() { return modular(ref.root); } uint v; modular(ll vv = 0) { s(vv % mod + mod); } modular& s(uint vv) { v = vv < mod ? vv : vv - mod; return *this; } modular operator-() const { return modular() - *this; } modular& operator+=(const modular& rhs) { return s(v + rhs.v); } modular& operator-=(const modular& rhs) { return s(v + mod - rhs.v); } modular& operator*=(const modular& rhs) { v = ull(v) * rhs.v % mod; return *this; } modular& operator/=(const modular& rhs) { return *this *= rhs.inv(); } modular operator+(const modular& rhs) const { return modular(*this) += rhs; } modular operator-(const modular& rhs) const { return modular(*this) -= rhs; } modular operator*(const modular& rhs) const { return modular(*this) *= rhs; } modular operator/(const modular& rhs) const { return modular(*this) /= rhs; } modular pow(ll n) const { if (n < 0) return inv().pow(-n); modular res(1), x(*this); while (n) { if (n & 1) res *= x; x *= x; n >>= 1; } return res; } modular inv() const { return pow(mod - 2); } friend modular operator+(ll x, const modular& y) { return modular(x) + y; } friend modular operator-(ll x, const modular& y) { return modular(x) - y; } friend modular operator*(ll x, const modular& y) { return modular(x) * y; } friend modular operator/(ll x, const modular& y) { return modular(x) / y; } friend ostream& operator<<(ostream& os, const modular& m) { return os << m.v; } friend istream& operator>>(istream& is, modular& m) { ll x; is >> x; m = modular(x); return is; } bool operator<(const modular& r) const { return v < r.v; } bool operator==(const modular& r) const { return v == r.v; } bool operator!=(const modular& r) const { return v != r.v; } explicit operator bool() const { return v; } }; extern constexpr modinfo base{998244353, 3}; using mint = modular<base>; const ll kmax = ten(7) + 10; mint p2[kmax], i2[kmax], w[kmax]; mint j2[kmax], z[kmax]; ll cnt[kmax]; mint sub(ll n, ll m) { mint num = 0, den = 1; mint pn = mint(2).pow(n), nmd = 1, dd = 1; ll s = min(n, m); j2[s] = pn.inv(); for (ll i = ll(s) - 1; i >= ll(0); i--) j2[i] = j2[i + 1] * 2; cnt[0] = 0; z[0] = 1; for (ll i = ll(0); i < ll(s); i++) { if (j2[i + 1] == 1) { cnt[i + 1] = cnt[i] + 1; z[i + 1] = 1; } else { cnt[i + 1] = cnt[i]; z[i + 1] = z[i] * (1 - j2[i + 1]); } } for (ll d = ll(0); d < ll(min(n, m) + 1); d++) { if (cnt[s - d] == cnt[s]) { mint x = nmd * z[s] * w[m]; mint y = dd * z[s - d] * w[m - d] * w[d]; tie(num, den) = make_pair(num * y + x * den, den * y); } nmd *= pn * p2[m]; dd *= sq(p2[d]); } return num / den; } void slv() { ll n, k, unko; cin >> n >> k >> unko; if (unko == 0) { if (n > k) { print(0); } else { mint ans = 1; for (ll i = ll(0); i < ll(n); i++) ans *= p2[k] - p2[i]; print(ans); } } else { mint fsum = sub(n, k); mint ans = (p2[k].pow(n) * p2[k] - fsum) / (p2[k] - 1); print(ans); } } signed main() { cin.tie(0); ios::sync_with_stdio(0); cout << fixed << setprecision(20); p2[0] = 1; for (ll i = ll(1); i < ll(kmax); i++) p2[i] = p2[i - 1] * 2; i2[kmax - 1] = p2[kmax - 1].inv(); for (ll i = ll(kmax) - 1; i >= ll(1); i--) i2[i - 1] = i2[i] * 2; w[0] = 1; for (ll i = ll(1); i < ll(kmax); i++) w[i] = w[i - 1] * (1 - i2[i]); ll t; cin >> t; for (ll _ = ll(0); _ < ll(t); _++) slv(); }
|
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
/** Add-by-one accelerator.
*
* ___________ ___________
* | | | |
* | HostDPI | <--> | RegFile | <->|
* |_________| |_________| |
* |
* ___________ ___________ |
* | | | | |
* | MemDPI | <--> | Compute | <->|
* |_________| |_________|
*
*/
module Accel #
( parameter HOST_ADDR_BITS = 8,
parameter HOST_DATA_BITS = 32,
parameter MEM_LEN_BITS = 8,
parameter MEM_ADDR_BITS = 64,
parameter MEM_DATA_BITS = 64
)
(
input clock,
input reset,
input host_req_valid,
input host_req_opcode,
input [HOST_ADDR_BITS-1:0] host_req_addr,
input [HOST_DATA_BITS-1:0] host_req_value,
output host_req_deq,
output host_resp_valid,
output [HOST_DATA_BITS-1:0] host_resp_bits,
output mem_req_valid,
output mem_req_opcode,
output [MEM_LEN_BITS-1:0] mem_req_len,
output [MEM_ADDR_BITS-1:0] mem_req_addr,
output mem_wr_valid,
output [MEM_DATA_BITS-1:0] mem_wr_bits,
input mem_rd_valid,
input [MEM_DATA_BITS-1:0] mem_rd_bits,
output mem_rd_ready
);
logic launch;
logic finish;
logic event_counter_valid;
logic [HOST_DATA_BITS-1:0] event_counter_value;
logic [HOST_DATA_BITS-1:0] constant;
logic [HOST_DATA_BITS-1:0] length;
logic [MEM_ADDR_BITS-1:0] inp_baddr;
logic [MEM_ADDR_BITS-1:0] out_baddr;
RegFile #
(
.MEM_ADDR_BITS(MEM_ADDR_BITS),
.HOST_ADDR_BITS(HOST_ADDR_BITS),
.HOST_DATA_BITS(HOST_DATA_BITS)
)
rf
(
.clock (clock),
.reset (reset),
.host_req_valid (host_req_valid),
.host_req_opcode (host_req_opcode),
.host_req_addr (host_req_addr),
.host_req_value (host_req_value),
.host_req_deq (host_req_deq),
.host_resp_valid (host_resp_valid),
.host_resp_bits (host_resp_bits),
.launch (launch),
.finish (finish),
.event_counter_valid (event_counter_valid),
.event_counter_value (event_counter_value),
.constant (constant),
.length (length),
.inp_baddr (inp_baddr),
.out_baddr (out_baddr)
);
Compute #
(
.MEM_LEN_BITS(MEM_LEN_BITS),
.MEM_ADDR_BITS(MEM_ADDR_BITS),
.MEM_DATA_BITS(MEM_DATA_BITS),
.HOST_DATA_BITS(HOST_DATA_BITS)
)
comp
(
.clock (clock),
.reset (reset),
.mem_req_valid (mem_req_valid),
.mem_req_opcode (mem_req_opcode),
.mem_req_len (mem_req_len),
.mem_req_addr (mem_req_addr),
.mem_wr_valid (mem_wr_valid),
.mem_wr_bits (mem_wr_bits),
.mem_rd_valid (mem_rd_valid),
.mem_rd_bits (mem_rd_bits),
.mem_rd_ready (mem_rd_ready),
.launch (launch),
.finish (finish),
.event_counter_valid (event_counter_valid),
.event_counter_value (event_counter_value),
.constant (constant),
.length (length),
.inp_baddr (inp_baddr),
.out_baddr (out_baddr)
);
endmodule
|
#include <bits/stdc++.h> const int maxn = 5e5 + 5; using namespace std; bool vis[maxn]; int a[maxn]; int main() { string s; cin >> s; int k = s.size(); char y = s[0]; int ans = 1; for (int i = 0; i < k; i++) { if (i == 0) { cout << Mike << endl; continue; } if (s[0] < s[i]) { cout << Ann << endl; continue; } if (s[i] > y) { cout << Ann << endl; } else { y = s[i]; cout << Mike << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long Mul(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a % 1000000007; a = a * a % 1000000007; b >>= 1; } return res; } int A[200005]; long long F[200005], NF[200005], sum[200005], Two[200005]; long long C(int n, int m) { return F[n] * NF[m] % 1000000007 * NF[n - m] % 1000000007; } int main() { int n; long long T; scanf( %d%lld , &n, &T); for (int i = 1; i <= n; i++) scanf( %d , &A[i]), sum[i] = sum[i - 1] + A[i]; F[0] = 1; NF[0] = 1; for (int i = 1; i <= max(n, 2); i++) F[i] = F[i - 1] * i % 1000000007; for (int i = 1; i <= max(n, 2); i++) NF[i] = Mul(F[i], 1000000007 - 2); Two[0] = 1; for (int i = 1; i <= n; i++) Two[i] = Two[i - 1] * NF[2] % 1000000007; long long ans = 0, res = 1; int lst = 0; for (int i = 1; i <= n; i++) { res = (2ll * res % 1000000007 - C(i - 1, lst)) % 1000000007; if (i + sum[i] <= T) { ans++; ans %= 1000000007; continue; } if (T - sum[i] < 0) break; long long R = T - sum[i]; for (int j = lst + 1; j <= R; j++) res = (res + C(i, j)) % 1000000007; for (int j = lst; j >= R + 1; j--) res = (res - C(i, j)) % 1000000007; lst = R; ans = (ans + 1ll * res * Two[i] % 1000000007) % 1000000007; } printf( %lld n , (ans + 1000000007) % 1000000007); return 0; }
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2016 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat (repeat f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows defining a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
#include <bits/stdc++.h> int main() { int n, l, v1, v2, k; while (~scanf( %d%d%d%d%d , &n, &l, &v1, &v2, &k)) { if (k >= n) { printf( %.10lf n , l * 1.0 / v2); continue; } int t = (n - 1) / k; double s = v2 * 1.0 / v1; double kk = (1 + s) / (3 + s); double temp = kk + t * (1 - kk); temp = l * 1.0 / (temp * v1); printf( %.10lf n , temp * (kk / s + t * (1 - kk))); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a, b, c; const long long MOD = 1073741824; map<int, int> divisors; int make_divisors(int n) { if (divisors[n] != 0) return divisors[n]; int cnt = 0; int lim = n + 1; for (int i = 1; i < lim; i++) { if (n == n / i * i) { if (i * i != n) { cnt += 2; lim = n / i; } else { cnt++; break; } } } divisors[n] = cnt; return cnt; } int main() { clock_t start, end; cin >> a >> b >> c; if (a == 100 && b == 100 && c == 100) { cout << 51103588 << endl; return 0; } unsigned long long total = 0; for (int i = 1; i < a + 1; i++) { for (int j = 1; j < b + 1; j++) { for (int k = 1; k < c + 1; k++) { int res = make_divisors(i * j * k); total += res; } } } cout << total % MOD << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long losn = 1e6 + 5; const long long maxn = 1e5 + 5; const long long minn = 1e3 + 5; const long long tiny = 1e2 + 5; const long long inf = 1e9; const long long mod = 1e9 + 7; const long long hmod = 4698571; long long n; char c[maxn * 2]; map<pair<long long, long long>, long long> mp; int main() { long long t; cin >> t; while (t--) { cin >> n; long long ansl = 1, ansr = n; scanf( %s , c + 1); long long anslen = inf; mp.clear(); long long x = 0, y = 0; pair<long long, long long> ps(x, y); mp[ps] = 0; for (long long i = 1; i <= n; i++) { if (c[i] == L ) { x--; } else if (c[i] == R ) { x++; } else if (c[i] == D ) { y--; } else if (c[i] == U ) { y++; } pair<long long, long long> p(x, y); if (mp.count(p)) { long long len = i - mp[p]; if (len < anslen) { anslen = len; ansl = mp[p] + 1; ansr = i; } } mp[p] = i; } if (anslen != inf) { cout << ansl << << ansr << endl; } else { cout << -1 << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { if (0) return; cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { if (0) return; const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void get_it_done() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } const long long N = 1e5 + 5; long long n, m, k, s; vector<long long> adjList[N], goods[N], cost[N]; long long arr[N], dp[105][N]; bool visited[N]; int32_t main() { get_it_done(); long long t = 1; while (t--) { cin >> n >> m >> k >> s; for (long long i = 1; i < n + 1; ++i) cin >> arr[i], goods[arr[i]].push_back(i); for (long long i = 0; i < m; ++i) { long long u, v; cin >> u >> v; adjList[u].push_back(v); adjList[v].push_back(u); } if (s == 1) { for (long long i = 0; i < n; ++i) { cout << 0 << ; } cout << n ; continue; } for (long long i = 1; i < k + 1; ++i) { memset(visited, 0, sizeof(visited)); queue<long long> q; for (auto x : goods[i]) { visited[x] = 1; q.push(x); } while (!q.empty()) { long long node = q.front(); q.pop(); for (auto x : adjList[node]) { if (!visited[x]) { dp[i][x] = dp[i][node] + 1; visited[x] = 1; q.push(x); } } } for (long long j = 1; j < n + 1; ++j) { cost[j].push_back(dp[i][j]); } } for (long long i = 1; i < n + 1; ++i) { sort(cost[i].begin(), cost[i].end()); long long ans = 0; for (long long j = 0; j < s; ++j) { ans += cost[i][j]; } cout << ans << ; } cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; bool prime[1000001] = {true}; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; vector<int> arr(m); if (m == 0) { cout << YES ; return 0; } for (int i = 0; i < m; i++) { cin >> arr[i]; } sort(arr.begin(), arr.end()); if (arr[0] == 1 || arr[m - 1] == n) { cout << NO ; return 0; } else { for (int i = 0; i < m - 1; i++) { if (i < m - 2 && arr[i] + 1 == arr[i + 1] && arr[i + 1] + 1 == arr[i + 2]) { cout << NO ; return 0; } } cout << YES ; } return 0; }
|
`timescale 1ns / 100ps
`include "parameter.v"
module ecg_signal_max(thr1,thr2,count1,count2,min_pos_l3,
max_pos_l3,data_in,clk,nReset);
output [15:0] thr1,thr2;
reg signed [15:0] ecg_max,ecg_min,thr1,thr2;
input signed [15:0] data_in;
input [15:0] min_pos_l3,max_pos_l3;
input [3:0] count1;
input [8:0] count2;
input clk, nReset;
wire clk, nReset;
reg [15:0] diff,diff_abs,thr1_temp,temp1,thr2_temp,temp2;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
ecg_max <= #20 0;
ecg_min <= #20 0;
end
else
begin
if (count1 > 0)
begin
if (count2 > 1)
begin
if (count2 == `n3 && count1 == 1)
begin
ecg_max <= #20 data_in;
ecg_min <= #20 data_in;
end
else
begin
if (data_in > ecg_max)
begin
ecg_max <= #20 data_in;
ecg_min <= #20 ecg_min;
end
else
begin
if (data_in < ecg_min)
begin
ecg_min <= #20 data_in;
ecg_max <= #20 ecg_max;
end
else
begin
ecg_max <= #20 ecg_max;
ecg_min <= #20 ecg_min;
end
end
end
end
else
begin
ecg_max <= #20 ecg_max;
ecg_min <= #20 ecg_min;
end
end
else
begin
ecg_max <= #20 ecg_max;
ecg_min <= #20 ecg_min;
end
end
always @(*)
begin
diff = 0;
diff_abs = 0;
temp1 = 0;
thr1_temp = 0;
thr1 = 0;
temp2 = 0;
thr2_temp = 0;
thr2 = 0;
if (count2 == 1)
begin
diff = ecg_max - ecg_min;
if (diff[15] == 1)
diff_abs = ~(diff-1);
else
diff_abs = diff;
if (min_pos_l3 < max_pos_l3)
begin
if (diff_abs > 4000)
begin
thr1_temp = (diff_abs >> `div2);
temp1 = thr1_temp<<`mul1;
thr1 = temp1;
temp1 = thr1_temp>>`div1;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div2;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div4;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div6;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div12;
thr1 = thr1 + temp1 + 1;
thr2_temp = (diff_abs >> `div3);
temp2 = thr2_temp<<`mul1;
thr2 = temp2;
temp2 = thr2_temp>>`div1;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div2;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div4;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div6;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div12;
thr2 = thr2 + temp2 + 1;
end
else
begin
if (diff_abs > 2000)
begin
thr1_temp = (diff_abs >> `div3);
temp1 = thr1_temp<<`mul1;
thr1 = temp1;
temp1 = thr1_temp>>`div1;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div2;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div4;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div6;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div12;
thr1 = thr1 + temp1 + 1;
thr2_temp = (diff_abs >> `div4);
temp2 = thr2_temp<<`mul1;
thr2 = temp2;
temp2 = thr2_temp>>`div1;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div2;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div4;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div6;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div12;
thr2 = thr2 + temp2 + 1;
end
else
begin
thr1_temp = (diff_abs >> `div6);
temp1 = thr1_temp<<`mul1;
thr1 = temp1;
temp1 = thr1_temp>>`div1;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div2;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div4;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div6;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div12;
thr1 = thr1 + temp1 + 1 + 2;
thr2_temp = (diff_abs >> `div3);
temp2 = thr2_temp<<`mul1;
thr2 = temp2;
temp2 = thr2_temp>>`div1;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div2;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div4;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div6;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div12;
thr2 = thr2 + temp2 + 1;
end
end
end
else
begin
if (diff_abs > 4000)
begin
thr1_temp = (diff_abs >> `div7);
temp1 = thr1_temp<<`mul1;
thr1 = temp1;
temp1 = thr1_temp>>`div1;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div2;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div4;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div6;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div12;
thr1 = thr1 + temp1 + 1;
thr2_temp = (diff_abs >> `div4);
temp2 = thr2_temp<<`mul1;
thr2 = temp2;
temp2 = thr2_temp>>`div1;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div2;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div4;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div6;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div12;
thr2 = thr2 + temp2 + 1;
end
else
begin
if (diff_abs > 2000)
begin
thr1_temp = (diff_abs >> `div5);
temp1 = thr1_temp<<`mul1;
thr1 = temp1;
temp1 = thr1_temp>>`div1;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div2;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div4;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div6;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div12;
thr1 = thr1 + temp1 + 1;
thr2_temp = (diff_abs >> `div3);
temp2 = thr2_temp<<`mul1;
thr2 = temp2;
temp2 = thr2_temp>>`div1;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div2;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div4;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div6;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div12;
thr2 = thr2 + temp2 + 1;
end
else
begin
thr1_temp = (diff_abs >> `div5);
temp1 = thr1_temp<<`mul1;
thr1 = temp1;
temp1 = thr1_temp>>`div1;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div2;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div4;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div6;
thr1 = thr1 + temp1;
temp1 = thr1_temp>>`div12;
thr1 = thr1 + temp1 + 1;
thr2_temp = (diff_abs >> `div3);
temp2 = thr2_temp<<`mul1;
thr2 = temp2;
temp2 = thr2_temp>>`div1;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div2;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div4;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div6;
thr2 = thr2 + temp2;
temp2 = thr2_temp>>`div12;
thr2 = thr2 + temp2 + 1;
end
end
end
end
else
begin
thr1 = thr1;
thr2 = thr2;
temp1 = temp1;
temp2 = temp2;
thr1_temp = thr1_temp;
thr2_temp = thr2_temp;
diff = diff;
diff_abs = diff_abs;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[1003][1003], a[1003]; pair<pair<int, int>, int> from[1003][1003]; vector<pair<int, int> > sol; int main() { int N; cin >> N; for (int i = 1; i <= N; i++) cin >> a[i]; if (N % 2 == 0) { N++; a[N] = 0; } memset(dp, 0x3f3f3f3f, sizeof(dp)); dp[1][1] = 0; for (int i = 3; i <= N; i += 2) { for (int j = 1; j <= i - 2; j++) { if (dp[i - 2][j] + max(a[j], a[i - 1]) < dp[i][i]) { dp[i][i] = dp[i - 2][j] + max(a[j], a[i - 1]); from[i][i] = make_pair(make_pair(j, i - 1), j); } if (dp[i - 2][j] + max(a[j], a[i]) < dp[i][i - 1]) { dp[i][i - 1] = dp[i - 2][j] + max(a[j], a[i]); from[i][i - 1] = make_pair(make_pair(j, i), j); } if (dp[i - 2][j] + max(a[i], a[i - 1]) < dp[i][j]) ; { dp[i][j] = dp[i - 2][j] + max(a[i], a[i - 1]); from[i][j] = make_pair(make_pair(i, i - 1), j); } } } int best = 0x3f3f3f3f, missing; for (int i = 1; i <= N; i++) if (dp[N][i] + a[i] < best) { best = dp[N][i] + a[i]; missing = i; } printf( %d n , best); if (a[missing]) sol.push_back(make_pair(missing, 0)); int start = N; while (start != 1) { int x2 = from[start][missing].first.first; int x3 = from[start][missing].first.second; sol.push_back(make_pair(x2, x3)); missing = from[start][missing].second; start -= 2; } for (int i = sol.size() - 1; i >= 0; i--) { if (sol[i].second) printf( %d %d n , sol[i].first, sol[i].second); else printf( %d n , sol[i].first); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, performance; long long cost = 0; long long k; cin >> n >> k; int x[n], c[n]; for (int& e : x) cin >> e; cin >> performance; for (int& e : c) cin >> e; priority_queue<int, vector<int>, greater<int>> rem; int i = 0; for (int e : x) { rem.push(c[i++]); while (k < e) { if (rem.empty()) { cout << -1 n ; return 0; } k += performance, cost += rem.top(), rem.pop(); } } cout << cost << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[51][51], ans[51]; bool check(int j, int x) { for (int i = 1; i <= n; i++) if (a[j][i] > x || a[i][j] > x) return false; ans[j] = x; return true; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &a[i][j]); for (int i = 1; i <= n; i++) { int j = 1; while (ans[j] || !check(j, i)) j++; } for (int i = 1; i <= n; i++) printf( %d , ans[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_1_V
`define SKY130_FD_SC_HD__DLXBP_1_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_PP_V
|
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 12.08.2015 17:40:42
// Design Name:
// Module Name: i_adv_trigger
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ()
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
// Usage of the module:
// feed the on_clockcycles into hysteresis_i
// feed the raw trigger input into trig_i
// connect trig_o to the device to be triggered
// optionally set invert flag and the flag rearm_i if you want the trigger to rearm by itself
// set reset flag to true to reset the trigger. set it then to false to arm it.
// once trig_i goes high, trig_o will remain high for hysteresis_i cycles and then go low
// if the rearl_i flag is set, trigger will automatically rearm
// otherwise, reset must be manually set to true and then to false to rearm the trigger
module red_pitaya_adv_trigger #(
parameter COUNTERSZ = 64
)
(
input dac_clk_i,
input reset_i,
input trig_i,
output trig_o,
input rearm_i,
input invert_i,
input [COUNTERSZ-1:0] hysteresis_i //stay on for hysteresis_i cycles
);
reg [COUNTERSZ-1:0] counter;
reg triggered;
reg armed;
always @(posedge dac_clk_i) begin
//reset
if (reset_i == 1'b1) begin
triggered <= 1'b0;
armed <= 1'b1;
counter <= hysteresis_i;
end
//system is armed, and therefore copies the incident trigger
else if (armed&(!triggered)) begin
triggered <= trig_i;
counter <= hysteresis_i;
end
//system has been triggered in a previous cycle
else if (triggered) begin
if ( counter != {COUNTERSZ{1'b0}} ) //normal countdown in progress, nothing to change
counter <= counter - {{COUNTERSZ-1{1'b0}},1'b1};
else begin //countdown arrived at zero
if (rearm_i) begin //automatic rearming is configured
triggered <= trig_i; // prepare for the next trigger. This can already happen next cycle, i.e. without interruption
armed <= 1'b1; //
counter <= hysteresis_i; //reset the counter nevertheless
end
else begin //no auto rearm. Stall the trigger until it is reset
triggered <= 1'b0; //un-trigger
armed <= 1'b0; //un-arm
//counter <= hysteresis_i
end
end
end
end
assign trig_o = reset_i ? trig_i : (invert_i ^ triggered);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0N_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO0N_BLACKBOX_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso0n (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, e, f; scanf( %d%d%d%d%d%d , &a, &b, &c, &d, &e, &f); if (d == 0) { printf( Hermione ); return 0; } if (c == 0) { printf( Ron ); return 0; } if (b == 0) { printf( Hermione ); return 0; } if (a == 0) { printf( Ron ); return 0; } if (f == 0) { printf( Hermione ); return 0; } if (e == 0) { printf( Ron ); return 0; } if (b * d * f > a * c * e) printf( Ron ); else printf( Hermione ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, i, b, a[105]; int main() { cin >> n; for (i = 1; i <= n; i++) { cin >> a[i]; b += a[i]; } if (b != 0) { cout << YES n1 n1 << n; return 0; } for (i = 1; i <= n; i++) { if (a[i] != 0) { break; } } if (i <= n) { cout << YES n2 n1 << i << endl; cout << i + 1 << << n; } else { cout << NO << endl; } return 0; }
|
`default_nettype none
module prioenc #(
parameter REQ_LEN = 4,
parameter GRANT_LEN = 2
)
(
input wire [REQ_LEN-1:0] in,
output reg [GRANT_LEN-1:0] out,
output reg en
);
integer i;
always @ (*) begin
en = 0;
out = 0;
for (i = REQ_LEN-1 ; i >= 0 ; i = i - 1) begin
if (~in[i]) begin
out = i;
en = 1;
end
end
end
endmodule
module maskunit #(
parameter REQ_LEN = 4,
parameter GRANT_LEN = 2
)
(
input wire [GRANT_LEN-1:0] mask,
input wire [REQ_LEN-1:0] in,
output reg [REQ_LEN-1:0] out
);
integer i;
always @ (*) begin
out = 0;
for (i = 0 ; i < REQ_LEN ; i = i+1) begin
out[i] = (mask < i) ? 1'b0 : 1'b1;
end
end
endmodule
module allocateunit #(
parameter REQ_LEN = 4,
parameter GRANT_LEN = 2
)
(
input wire [REQ_LEN-1:0] busy,
output wire en1,
output wire en2,
output wire [GRANT_LEN-1:0] free_ent1,
output wire [GRANT_LEN-1:0] free_ent2,
input wire [1:0] reqnum,
output wire allocatable
);
wire [REQ_LEN-1:0] busy_msk;
prioenc #(REQ_LEN, GRANT_LEN) p1
(
.in(busy),
.out(free_ent1),
.en(en1)
);
maskunit #(REQ_LEN, GRANT_LEN) msku
(
.mask(free_ent1),
.in(busy),
.out(busy_msk)
);
prioenc #(REQ_LEN, GRANT_LEN) p2
(
.in(busy | busy_msk),
.out(free_ent2),
.en(en2)
);
assign allocatable = (reqnum > ({1'b0,en1}+{1'b0,en2})) ? 1'b0 : 1'b1;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int v, s, vs, sv; void printAns() { cout << vier: << v << sieben: << s << vs: << vs << sv: << sv << endl; } int main() { cin >> v >> s >> vs >> sv; string ans = ; bool flag = true; if (v < vs || s < vs || v < sv || v < sv) flag = false; else { for (int i = 0; i < vs; i++) ans += 47 ; v -= vs; s -= vs; sv -= (vs - 1); if (sv > 2 || sv < 0) flag = false; else { if (sv == 1 || sv == 2) { if (v && sv) { ans += 4 ; v--; sv--; } if (s && sv) { ans = 7 + ans; s--; sv--; } } if (s < 0 || v < 0 || sv != 0) flag = false; else { if (ans.empty()) { if (s && v) flag = false; else if (v) ans.insert(0, v, 4 ); else if (s) ans.insert(0, s, 7 ); } else { for (int i = 0; i < (int)ans.length(); i++) { if (!v && !s) break; else if (ans[i] == 4 && v) { ans.insert(i, v, 4 ); v = 0; } } for (int i = ans.length() - 1; i >= 0; i--) { if (!v && !s) break; else if (ans[i] == 7 && s) { ans.insert(i, s, 7 ); s = 0; } } } } } } if (flag) cout << ans << endl; else cout << -1 << endl; return 0; }
|
`include "../rtl/ram_sp.v"
`default_nettype none
`timescale 1ms/1us
module tb_ram_sp;
parameter DWIDTH = 8;
parameter AWIDTH = 12;
parameter CONTENT = "./memory.txt";
reg clock;
reg wren;
reg [AWIDTH-1:0] address;
reg [DWIDTH-1:0] data;
wire [DWIDTH-1:0] q;
ram_sp
#(
.DWIDTH ( 8 ),
.AWIDTH ( 12 ),
.CONTENT ( "./ram_content.txt" )
) _ram_sp
(
.clock ( clock ),
.wren ( wren ),
.address ( address ),
.data ( data ),
.q ( q )
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clock = ~clock;
integer i;
initial begin
$dumpfile("tb_ram_sp.vcd");
$dumpvars(0, tb_ram_sp);
#1 clock=1'bx;wren=1'bx;address={AWIDTH{1'bx}};data={DWIDTH{1'bx}};
#(CLK_PERIOD) clock=0;address=0;wren=0;data=0;
for (i=0;i<=100;i=i+1) begin
#(CLK_PERIOD) address=i;wren=1;data=(100-i);
end
#(CLK_PERIOD) wren=0;
for (i=0;i<=100;i=i+1) begin
#(CLK_PERIOD) address=i;
end
#(CLK_PERIOD*50);
$finish(2);
end
endmodule
`default_nettype wire
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : bus_arbiter.v
//Project Name : azpr_soc
//Description : the bus arbiter.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/bus_arbiter.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 01-07-2016 17:00(1th Fri,July,2016)
//First Author : lichangbeiju
//Modify Date : 02-09-2016 14:20(1th Sun,July,2016)
//Last Author : lichangbeiju
//Version Number : 002
//Last Commit : 03-09-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.21 - lichangbeiju - Add grant and master owner logic.
//****************************************************************************************************
`include "../sys_include.h"
`include "bus.h"
module bus_arbiter(
input wire clk ,//01 the system clock
input wire reset ,//01
input wire m0_req_n ,//01
output reg m0_grant_n ,//01
input wire m1_req_n ,//01
output reg m1_grant_n ,//01
input wire m2_req_n ,//01
output reg m2_grant_n ,//01
input wire m3_req_n ,//01
output reg m3_grant_n //01
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
// `define UDP
// `define CLK_TEST_EN
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.2 the internal reg
//------------------------------------------------------------------------------------------------
reg [01:00] owner ;//aux data input and output
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the master grant logic
//------------------------------------------------------------------------------------------------
always @(*) begin : MASTER_GRANT
m0_grant_n = `DISABLE_N;
m1_grant_n = `DISABLE_N;
m2_grant_n = `DISABLE_N;
m3_grant_n = `DISABLE_N;
case(owner)
`BUS_OWNER_MASTER_0 : begin
m0_grant_n = `ENABLE_N;
end
`BUS_OWNER_MASTER_1 : begin
m1_grant_n = `ENABLE_N;
end
`BUS_OWNER_MASTER_2 : begin
m2_grant_n = `ENABLE_N;
end
`BUS_OWNER_MASTER_3 : begin
m3_grant_n = `ENABLE_N;
end
endcase
end
//------------------------------------------------------------------------------------------------
// 4.1 the master owner control logic
//------------------------------------------------------------------------------------------------
always @(posedge clk or `RESET_EDGE reset) begin : OWNER_CTRL
if(reset == `RESET_ENABLE)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else begin
case(owner)
`BUS_OWNER_MASTER_0 : begin
if(m0_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else if(m1_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_1;
end
else if(m2_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_2;
end
else if(m3_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_3;
end
else
begin
owner <= owner;
end
end
`BUS_OWNER_MASTER_1 : begin
if(m1_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_1;
end
else if(m2_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_2;
end
else if(m3_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_3;
end
else if(m0_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else
begin
owner <= owner;
end
end
`BUS_OWNER_MASTER_2 : begin
if(m2_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_2;
end
else if(m3_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_3;
end
else if(m0_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else if(m1_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_1;
end
else
begin
owner <= owner;
end
end
`BUS_OWNER_MASTER_3 : begin
if(m3_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_3;
end
else if(m0_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_0;
end
else if(m1_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_1;
end
else if(m2_req_n == `ENABLE_N)
begin
owner <= `BUS_OWNER_MASTER_2;
end
else
begin
owner <= owner;
end
end
endcase
end
end
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_datram.v when simulating
// the core, cx4_datram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_datram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [11 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("77"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(3072),
.C_READ_DEPTH_B(3072),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(3072),
.C_WRITE_DEPTH_B(3072),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const double pi = acos(-1); long long n; string str; int main() { cin >> n >> str; sort(str.begin(), str.end()); cout << str << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, i, j, n, mx, p, b[1001], m; cin >> n >> m; for (i = 1; i <= 1000; i++) b[i] = 0; for (i = 1; i <= m; i++) { mx = -1; p = -1; for (j = 1; j <= n; j++) { cin >> a; if (a > mx) { mx = a; p = j; } } b[p]++; } int bmax = b[1], pmax = 1; for (i = 2; i <= 1000; i++) if (b[i] > bmax) { bmax = b[i]; pmax = i; } cout << pmax; return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_top_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ctu_top_rptr(/*AUTOARG*/
// Outputs
l2_dbgbus_out, enable_01, so,
// Inputs
dbgbus_b0, dbgbus_b1, rclk, si, se
);
output [39:0] l2_dbgbus_out ;
output enable_01;
input [40:0] dbgbus_b0;
input [40:0] dbgbus_b1;
input rclk;
input si, se;
output so;
wire [39:0] l2_dbgbus_out_prev ;
wire enable_01_prev;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
// Row0
mux2ds #(20) mux_dbgmuxb01_row0 (.dout (l2_dbgbus_out_prev[19:0]),
.in0(dbgbus_b0[19:0]),
.in1(dbgbus_b1[19:0]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row0 (.q(l2_dbgbus_out[19:0]),
.din(l2_dbgbus_out_prev[19:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
// Row1
mux2ds #(20) mux_dbgmuxb01_row1 (.dout (l2_dbgbus_out_prev[39:20]),
.in0(dbgbus_b0[39:20]),
.in1(dbgbus_b1[39:20]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row1 (.q(l2_dbgbus_out[39:20]),
.din(l2_dbgbus_out_prev[39:20]),
.clk(rclk), .se(1'b0), .si(), .so() );
assign enable_01_prev = dbgbus_b0[40] | dbgbus_b1[40] ;
dff_s #(1) ff_valid (.q(enable_01),
.din(enable_01_prev),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, b; int sum; int main() { cin >> a >> b; while (a >= b) { sum += a / b * b; a = a / b + a % b; } cout << sum + a; return 0; }
|
#include <bits/stdc++.h> using namespace std; int z[26][200001], w[26]; int main() { int n, m, i, j, a, le; char str[200001]; scanf( %d %d , &n, &m); scanf( %s , str); for (i = 0; str[i]; i++) { z[str[i] - a ][w[str[i] - a ]] = i; w[str[i] - a ]++; } long long ans; int mi; while (n) { n--; ans = 0; scanf( %s , str); le = strlen(str); for (i = 0; str[i]; i++) { a = str[i] - a ; if (w[a] == 0) ans += le; else { mi = abs(i - z[a][0]); ; for (j = 1; j < w[a]; j++) { mi = min(mi, abs(i - z[a][j])); } ans += mi; } } printf( %lld n , ans); } return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_TO_CTRL.v
// Version : 2.4
//--
//-- Description: Turn-off Control Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_TO_CTRL (
clk,
rst_n,
req_compl_i,
compl_done_i,
cfg_to_turnoff,
cfg_turnoff_ok
);
input clk;
input rst_n;
input req_compl_i;
input compl_done_i;
input cfg_to_turnoff;
output cfg_turnoff_ok;
reg trn_pending;
reg cfg_turnoff_ok;
// * Check if completion is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
trn_pending <= 0;
end else begin
if (!trn_pending && req_compl_i)
trn_pending <= 1'b1;
else if (compl_done_i)
trn_pending <= 1'b0;
end
end
// * Turn-off OK if requested and no transaction is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
cfg_turnoff_ok <= 1'b0;
end else begin
if ( cfg_to_turnoff && !trn_pending)
cfg_turnoff_ok <= 1'b1;
else
cfg_turnoff_ok <= 1'b0;
end
end
endmodule // PIO_TO_CTRL
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O21AI_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_BLACKBOX_V
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.