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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_delay_cntrl (
// delay interface
delay_clk,
delay_rst,
delay_locked,
// io interface
up_dld,
up_dwdata,
up_drdata,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IO_WIDTH = 8;
parameter IO_BASEADDR = 6'h02;
// delay interface
input delay_clk;
output delay_rst;
input delay_locked;
// io interface
output [(IO_WIDTH-1):0] up_dld;
output [((IO_WIDTH*5)-1):0] up_dwdata;
input [((IO_WIDTH*5)-1):0] up_drdata;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_preset = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_dlocked_m1 = 'd0;
reg up_dlocked = 'd0;
reg [(IO_WIDTH-1):0] up_dld = 'd0;
reg [((IO_WIDTH*5)-1):0] up_dwdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [ 4:0] up_rdata_s;
wire [(IO_WIDTH-1):0] up_drdata4_s;
wire [(IO_WIDTH-1):0] up_drdata3_s;
wire [(IO_WIDTH-1):0] up_drdata2_s;
wire [(IO_WIDTH-1):0] up_drdata1_s;
wire [(IO_WIDTH-1):0] up_drdata0_s;
// variables
genvar n;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == IO_BASEADDR) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == IO_BASEADDR) ? up_rreq : 1'b0;
assign up_rdata_s[4] = | up_drdata4_s;
assign up_rdata_s[3] = | up_drdata3_s;
assign up_rdata_s[2] = | up_drdata2_s;
assign up_rdata_s[1] = | up_drdata1_s;
assign up_rdata_s[0] = | up_drdata0_s;
generate
for (n = 0; n < IO_WIDTH; n = n + 1) begin: g_drd
assign up_drdata4_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+4)] : 1'd0;
assign up_drdata3_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+3)] : 1'd0;
assign up_drdata2_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+2)] : 1'd0;
assign up_drdata1_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+1)] : 1'd0;
assign up_drdata0_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+0)] : 1'd0;
end
endgenerate
// processor interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_preset <= 1'd1;
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
up_dlocked_m1 <= 'd0;
up_dlocked <= 'd0;
end else begin
up_preset <= 1'd0;
up_wack <= up_wreq_s;
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
if (up_dlocked == 1'b0) begin
up_rdata <= 32'hffffffff;
end else begin
up_rdata <= {27'd0, up_rdata_s};
end
end else begin
up_rdata <= 32'd0;
end
up_dlocked_m1 <= delay_locked;
up_dlocked <= up_dlocked_m1;
end
end
// write does not hold- read back what goes into effect.
generate
for (n = 0; n < IO_WIDTH; n = n + 1) begin: g_dwr
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dld[n] <= 'd0;
up_dwdata[((n*5)+4):(n*5)] <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == n)) begin
up_dld[n] <= 1'd1;
up_dwdata[((n*5)+4):(n*5)] <= up_wdata[4:0];
end else begin
up_dld[n] <= 1'd0;
up_dwdata[((n*5)+4):(n*5)] <= up_dwdata[((n*5)+4):(n*5)];
end
end
end
end
endgenerate
// resets
ad_rst i_delay_rst_reg (
.preset (up_preset),
.clk (delay_clk),
.rst (delay_rst));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DECAP_BEHAVIORAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_BEHAVIORAL_V
|
#include <cstdio> #include <cstring> #include <queue> #include <cmath> #include <set> #include <cstdlib> #include <iostream> #include <map> #include <algorithm> using namespace std; typedef long long ll; typedef unsigned long long ull; typedef unsigned int uii; typedef pair<int, ll> pii; template<typename T> inline void rd(T& x) { int tmp = 1; char c = getchar(); x = 0; while (c > 9 || c < 0 ) { if (c == - )tmp = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } x *= tmp; } const int N = 2e5 + 10; const int M = 1e6 + 10; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; const double eps = 1e-5; int sgn(double x) { if (fabs(x) < eps) return 0; if (x > 0) return 1; return -1; } int n, m, k; int head[N], cntE; struct edge { int to, next; int w; }e[M]; void add(int u, int v, int w = 0) { e[cntE].to = v; e[cntE].next = head[u]; e[cntE].w = w; head[u] = cntE++; } bool vis[N]; int stk[N], top; bool dfs(int x) { if (vis[x ^ 1]) return false; if (vis[x]) return true; vis[x] = true; stk[++top] = x; for (int i = head[x]; ~i; i = e[i].next) { int v = e[i].to; if (!dfs(v)) return false; } return true; } bool two_sat() { memset(vis, false, sizeof(bool) * (2 * n + 10)); for (int i = 0; i < n; ++i) { if (vis[i << 1] || vis[i << 1 | 1]) continue; top = 0; if (!dfs(i << 1)) { while (top) vis[stk[top--]] = false; if (!dfs(i << 1 | 1)) return false; } } return true; } ll a[N], b[N], c[N], maxn[N]; ll solve() { maxn[n] = c[n] - 1 + 2; ll ans = 0; for (int i = n - 1; i > 0; --i) { ans = max(ans, maxn[i + 1] + b[i + 1] - a[i + 1]); maxn[i] = c[i] - 1; if (b[i+1] == a[i+1]) { // maxn[i] = c[i] + 1; } else { maxn[i] = max(maxn[i], maxn[i + 1] + (c[i] - 1 - (b[i + 1] - a[i + 1]))); } maxn[i] += 2; } return ans; } int main() { #ifdef _DEBUG FILE* _INPUT = freopen( input.txt , r , stdin); // FILE* _OUTPUT = freopen( output.txt , w , stdout); #endif // !_DEBUG int cas = 0, T; rd(T); while (T--) { // while (~scanf( %d , &n)) { rd(n); for (int i = 1; i <= n; ++i) rd(c[i]); for (int i = 1; i <= n; ++i) rd(a[i]); for (int i = 1; i <= n; ++i) rd(b[i]); for (int i = 1; i <= n; ++i) if (a[i] > b[i]) swap(a[i], b[i]); printf( %lld n , solve()); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> g[100010]; long long int weight[100010], add[100010], sub[100010]; int n; void dfs(int mom, int u) { for (vector<int>::iterator v = g[u].begin(); v != g[u].end(); v++) if (*v != mom) { dfs(u, *v); add[u] = max(add[*v], add[u]); sub[u] = max(sub[u], sub[*v]); } weight[u] += add[u] - sub[u]; if (weight[u] < 0) add[u] -= weight[u]; else sub[u] += weight[u]; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); g[u].push_back(v), g[v].push_back(u); } for (int i = 1; i <= n; i++) scanf( %I64d , weight + i); dfs(-1, 1); printf( %I64d n , add[1] + sub[1]); }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) template <class T> bool scanff(T &ret) { char c; int sgn; T bit = 0.1; if (c = getchar(), c == EOF) return 0; while (c != - && c != . && (c < 0 || c > 9 )) c = getchar(); sgn = (c == - ) ? -1 : 1; ret = (c == - ) ? 0 : (c - 0 ); while (c = getchar(), c >= 0 && c <= 9 ) ret = ret * 10 + (c - 0 ); if (c == || c == n ) { ret *= sgn; return 1; } while (c = getchar(), c >= 0 && c <= 9 ) ret += (c - 0 ) * bit, bit /= 10; ret *= sgn; return 1; } using namespace std; long long dp[55][55][55]; int a[55]; int n, sum; double ans; int main() { ans = 0.0; scanff(n); int tot = 0; for (int i = int(1); i <= int(n); i++) scanff(a[i]), tot += a[i]; scanff(sum); if (tot <= sum) { printf( %.10f n , n * 1.0); return 0; } for (int c = int(1); c <= int(n); c++) { memset(dp, 0, sizeof(dp)); dp[0][0][0] = 1; for (int i = int(1); i <= int(n); i++) { for (int j = int(0); j <= int(i - 1); j++) for (int k = int(0); k <= int(sum); k++) { if (dp[i - 1][j][k]) { dp[i][j][k] += dp[i - 1][j][k]; if (i != c && k + a[i] <= sum) dp[i][j + 1][k + a[i]] += dp[i - 1][j][k]; } } } for (int j = int(1); j <= int(n); j++) { for (int k = int(max(0, sum - a[c] + 1)); k <= int(50); k++) { if (dp[n][j][k]) { double temp = dp[n][j][k] * j; int num = n - j; int n1 = n - j, n2 = n; for (int l = int(1); l <= int(num); l++) { temp *= double(n1); temp /= double(n2); n1--; n2--; } temp /= double(n - j); ans += temp; } } } } printf( %.10f n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); unsigned long long t; cin >> t; while (t--) { unsigned long long x1, x2, y1, y2; cin >> x1 >> y1 >> x2 >> y2; if (x1 == x2 || y1 == y2) { cout << 1 << n ; } else { unsigned long long d = x2 - x1; unsigned long long r = y2 - y1; cout << d * r + 1 << n ; } } return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_no_transition (clock, reset, enable, test_expr, start_state, next_state, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr, start_state, next_state;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NO_TRANSITION";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_no_transition_logic.v"
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endif
`ifdef OVL_SVA
`include "./sva05/assert_no_transition_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_no_transition_psl_logic.v"
`else
`endmodule // ovl_no_transition
`endif
|
module __TFF_P_ALWAYS_ (C, Q);
input C;
output wire Q;
wire notout;
$_NOT_ notgate (
.A(Q),
.Y(notout),
);
$_DFF_P_ dff (
.C(C),
.D(notout),
.Q(Q),
);
endmodule
module __TFF_N_ALWAYS_ (C, Q);
input C;
output wire Q;
wire notout;
$_NOT_ notgate (
.A(Q),
.Y(notout),
);
$_DFF_N_ dff (
.C(C),
.D(notout),
.Q(Q),
);
endmodule
module __TFF_N_ (T, C, Q);
input T, C;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_N_ dff (
.C(C),
.D(xorout),
.Q(Q),
);
endmodule
module __TFF_P_ (T, C, Q);
input T, C;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_P_ dff (
.C(C),
.D(xorout),
.Q(Q),
);
endmodule
module __TFFE_NN_ (T, C, E, Q);
input T, C, E;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFE_NN_ dff (
.C(C),
.D(xorout),
.Q(Q),
.E(E),
);
endmodule
module __TFFE_NP_ (T, C, E, Q);
input T, C, E;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFE_NP_ dff (
.C(C),
.D(xorout),
.Q(Q),
.E(E),
);
endmodule
module __TFFE_PN_ (T, C, E, Q);
input T, C, E;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFE_PN_ dff (
.C(C),
.D(xorout),
.Q(Q),
.E(E),
);
endmodule
module __TFFE_PP_ (T, C, E, Q);
input T, C, E;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFE_PP_ dff (
.C(C),
.D(xorout),
.Q(Q),
.E(E),
);
endmodule
module __TFF_NN0_ (T, C, R, Q);
input T, C, R;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_NN0_ dff (
.C(C),
.D(xorout),
.Q(Q),
.R(R),
);
endmodule
module __TFF_NN1_ (T, C, R, Q);
input T, C, R;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_NN1_ dff (
.C(C),
.D(xorout),
.Q(Q),
.R(R),
);
endmodule
module __TFF_NP0_ (T, C, R, Q);
input T, C, R;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_NP0_ dff (
.C(C),
.D(xorout),
.Q(Q),
.R(R),
);
endmodule
module __TFF_NP1_ (T, C, R, Q);
input T, C, R;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_NP1_ dff (
.C(C),
.D(xorout),
.Q(Q),
.R(R),
);
endmodule
module __TFF_PN0_ (T, C, R, Q);
input T, C, R;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_PN0_ dff (
.C(C),
.D(xorout),
.Q(Q),
.R(R),
);
endmodule
module __TFF_PN1_ (T, C, R, Q);
input T, C, R;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_PN1_ dff (
.C(C),
.D(xorout),
.Q(Q),
.R(R),
);
endmodule
module __TFF_PP0_ (T, C, R, Q);
input T, C, R;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_PP0_ dff (
.C(C),
.D(xorout),
.Q(Q),
.R(R)
);
endmodule
module __TFF_PP1_ (T, C, R, Q);
input T, C, R;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFF_PP1_ dff (
.C(C),
.D(xorout),
.Q(Q),
.R(R),
);
endmodule
module __TFFSR_NNN_ (C, S, R, T, Q);
input C, S, R, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_NNN_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(S),
.R(R),
);
endmodule
module __TFFSR_NNP_ (C, S, R, T, Q);
input C, S, R, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_NNP_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(S),
.R(R),
);
endmodule
module __TFFSR_NPN_ (C, S, R, T, Q);
input C, S, R, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_NPN_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(S),
.R(R),
);
endmodule
module __TFFSR_NPP_ (C, S, R, T, Q);
input C, S, R, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_NPP_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(S),
.R(R),
);
endmodule
module __TFFSR_PNN_ (C, S, R, T, Q);
input C, S, R, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_PNN_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(S),
.R(R),
);
endmodule
module __TFFSR_PNP_ (C, S, R, T, Q);
input C, S, R, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_PNP_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(S),
.R(R),
);
endmodule
module __TFFSR_PPN_ (C, S, R, T, Q);
input C, S, R, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_PPN_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(S),
.R(R),
);
endmodule
module __TFFSR_PPP_ (C, S, R, T, Q);
input C, S, R, T;
output wire Q;
wire xorout;
$_XOR_ xorgate (
.A(T),
.B(Q),
.Y(xorout),
);
$_DFFSR_PPP_ dff (
.C(C),
.D(xorout),
.Q(Q),
.S(S),
.R(R),
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char dif(char c1) { if (c1 == a ) return b ; return a ; } char dif2(char c1, char c2) { if (c1 != a && c2 != a ) return a ; if (c1 != b && c2 != b ) return b ; return c ; } int main() { int n, t; cin >> n >> t; string s1, s2; cin >> s1 >> s2; vector<int> com; vector<int> nocom; for (long long i = 0; i < (n); i++) if (s1[i] == s2[i]) com.push_back(i); else nocom.push_back(i); int comsz = com.size(); int nocomsz = nocom.size(); if (!(2 * t >= nocomsz)) { cout << -1 << endl; return 0; } string s3 = s1; if (nocomsz & 1) { int ind = nocom[nocomsz - 1]; s3[ind] = dif2(s1[ind], s2[ind]); t--; } for (int i = 0; (i + 1 < nocomsz) && t > 0; i += 2) { int ind1 = nocom[i]; s3[ind1] = s2[ind1]; int ind2 = nocom[i + 1]; s3[ind2] = s1[ind2]; t--; } for (int i = 0; i < comsz && t > 0; i++) { int ind = com[i]; s3[ind] = dif(s1[ind]); t--; } for (int i = 0; (i + 1 < nocomsz) && t > 0; i += 2) { int ind1 = nocom[i]; int ind2 = nocom[i + 1]; s3[ind1] = dif2(s1[ind1], s2[ind1]); s3[ind2] = dif2(s1[ind2], s2[ind2]); t--; } cout << s3 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_SN_TB_V
/**
* udp_dff$PR_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_pr_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 RESET = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER = 1'b1;
#220 RESET = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER = 1'b0;
#360 RESET = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 RESET = 1'b1;
#520 NOTIFIER = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 RESET = 1'bx;
#660 NOTIFIER = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PR_pp$PKG$sN dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_SN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_PP_SYMBOL_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_PP_SYMBOL_V
|
//Alan Achtenberg
//Project 2
//Processor Control Unit
`define OPCODE_ADD 6'b000000
`define OPCODE_SUB 6'b000000
`define OPCODE_ADDU 6'b000000
`define OPCODE_SUBU 6'b000000
`define OPCODE_AND 6'b000000
`define OPCODE_OR 6'b000000
`define OPCODE_SLL 6'b000000
`define OPCODE_SRA 6'b000000
`define OPCODE_SRL 6'b000000
`define OPCODE_SLT 6'b000000
`define OPCODE_SLTU 6'b000000
`define OPCODE_XOR 6'b000000
`define OPCODE_JR 6'b000000
//I-Type (All opcodes except 000000, 00001x, and 0100xx)
`define OPCODE_ADDI 6'b001000
`define OPCODE_ADDIU 6'b001001
`define OPCODE_ANDI 6'b001100
`define OPCODE_BEQ 6'b000100
`define OPCODE_BNE 6'b000101
`define OPCODE_BLEZ 6'b000110
`define OPCODE_BLTZ 6'b000001
`define OPCODE_ORI 6'b001101
`define OPCODE_XORI 6'b001110
`define OPCODE_NOP 6'b110110
`define OPCODE_LUI 6'b001111
`define OPCODE_SLTI 6'b001010
`define OPCODE_SLTIU 6'b001011
`define OPCODE_LB 6'b100000
`define OPCODE_LW 6'b100011
`define OPCODE_SB 6'b101000
`define OPCODE_SW 6'b101011
// J-Type (Opcode 00001x)
`define OPCODE_J 6'b000010
`define OPCODE_JAL 6'b000011
`define ADD 4'b0111 // 2's compl add
`define ADDU 4'b0001 // unsigned add
`define SUB 4'b0010 // 2's compl subtract
`define SUBU 4'b0011 // unsigned subtract
`define AND 4'b0100 // bitwise AND
`define OR 4'b0101 // bitwise OR
`define XOR 4'b0110 // bitwise XOR
`define SLT 4'b1010 // set result=1 if less than 2's compl
`define SLTU 4'b1011 // set result=1 if less than unsigned
`define NOP 4'b0000 // do nothing
`define BNE 4'b1001 // Branch if not equal
module Control_Unit(RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend, ALUOp, Opcode);
input [5:0] Opcode;
output RegDst;
output ALUSrc;
output MemToReg;
output RegWrite;
output MemRead;
output MemWrite;
output Branch;
output Jump;
output SignExtend;
output [3:0] ALUOp;
reg RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend;
reg [3:0] ALUOp;
always @ (Opcode) begin
case(Opcode)
6'b000000: begin
RegDst <= 1;
ALUSrc <= 0;
MemToReg <= 0;
RegWrite <= 1;
MemRead <= 0;
MemWrite <= 0;
Branch <= 0;
Jump <= 0;
SignExtend <= 1'bX;
ALUOp <= 4'b1111;
end
`OPCODE_ADDI: begin
RegDst <= 0;
ALUSrc <= 1;
MemToReg <= 0;
RegWrite <= 1;
MemRead <= 0;
MemWrite <= 0;
Branch <= 0;
Jump <= 0;
SignExtend <= 1;
ALUOp <= `ADD;
end
`OPCODE_ADDIU: begin
RegDst <= 0;
ALUSrc <= 1;
MemToReg <= 0;
RegWrite <= 1;
MemRead <= 0;
MemWrite <= 0;
Branch <= 0;
Jump <= 0;
SignExtend <= 1;
ALUOp <= `ADDU;
end
`OPCODE_NOP: begin
RegDst <= 1'b0;
ALUSrc <= 1'b0;
MemToReg <= 1'b0;
RegWrite <= 1'b0;
MemRead <= 1'b0;
MemWrite <= 1'b0;
Branch <= 1'b0;
Jump <= 1'b0;
SignExtend <= 1'b0;
ALUOp <= `NOP;
end
`OPCODE_LW: begin
RegDst <= 0;
ALUSrc <= 1;
MemToReg <= 1;
RegWrite <= 1;
MemRead <= 1;
MemWrite <= 0;
Branch <= 0;
Jump <= 0;
SignExtend <= 1;
ALUOp <= `ADD;
end
`OPCODE_SW: begin
RegDst <= 1'bX;
ALUSrc <= 1;
MemToReg <= 1'bX;
RegWrite <= 0;
MemRead <= 0;
MemWrite <= 1;
Branch <= 0;
Jump <= 0;
SignExtend <= 1;
ALUOp <= `ADD;
end
`OPCODE_BEQ: begin
RegDst <= 1'bX;
ALUSrc <= 0;
MemToReg <= 1'bX;
RegWrite <= 0;
MemRead <= 0;
MemWrite <= 0;
Branch <= 1;
Jump <= 0;
SignExtend <= 1'bX;
ALUOp <= `SUB;
end
`OPCODE_BNE: begin
RegDst <= 1'bX;
ALUSrc <= 0;
MemToReg <= 1'bX;
RegWrite <= 0;
MemRead <= 0;
MemWrite <= 0;
Branch <= 1;
Jump <= 0;
SignExtend <= 1'bX;
ALUOp <= `BNE;
end
`OPCODE_J: begin
RegDst <= 1'bX;
ALUSrc <= 0;
MemToReg <= 1'bX;
RegWrite <= 0;
MemRead <= 0;
MemWrite <= 0;
Branch <= 0;
Jump <= 1;
SignExtend <= 1'bX;
ALUOp <= 4'bX;
end
`OPCODE_ORI: begin
RegDst <= 0;
ALUSrc <= 1;
MemToReg <= 0;
RegWrite <= 1;
MemRead <= 0;
MemWrite <= 0;
Branch <= 0;
Jump <= 0;
SignExtend <= 0;
ALUOp <= `OR;
end
`OPCODE_ANDI: begin
RegDst <= 0;
ALUSrc <= 1;
MemToReg <= 0;
RegWrite <= 1;
MemRead <= 0;
MemWrite <= 0;
Branch <= 0;
Jump <= 0;
SignExtend <= 0;
ALUOp <= `AND;
end
`OPCODE_SLTI: begin
RegDst <= 0;
ALUSrc <= 1;
MemToReg <= 0;
RegWrite <= 1;
MemRead <= 0;
MemWrite <= 0;
Branch <= 0;
Jump <= 0;
SignExtend <= 1;
ALUOp <= `SLT;
end
`OPCODE_SLTIU: begin
RegDst <= 0;
ALUSrc <= 1;
MemToReg <= 0;
RegWrite <= 1;
MemRead <= 0;
MemWrite <= 0;
Branch <= 0;
Jump <= 0;
SignExtend <= 1;
ALUOp <= `SLTU;
end
`OPCODE_XORI: begin
RegDst <= 0;
ALUSrc <= 1;
MemToReg <= 0;
RegWrite <= 1;
MemRead <= 0;
MemWrite <= 0;
Branch <= 0;
Jump <= 0;
SignExtend <= 0;
ALUOp <= `XOR;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_PP_BLACKBOX_V
/**
* sdfrtp_ov2: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp_ov2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:52:57 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top affine_block_ieee754_fp_to_uint_0_0 -prefix
// affine_block_ieee754_fp_to_uint_0_0_ affine_block_ieee754_fp_to_uint_0_1_stub.v
// Design : affine_block_ieee754_fp_to_uint_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ieee754_fp_to_uint,Vivado 2016.4" *)
module affine_block_ieee754_fp_to_uint_0_0(x, y)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[9:0]" */;
input [31:0]x;
output [9:0]y;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 14:50:26
// Design Name:
// Module Name: _8_to_3_priority_encoder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _8_to_3_priority_encoder(
input [7:0] v,
input en_in_n,
output reg [2:0] y,
output reg en_out,
output reg gs
);
always @(v or en_in_n) begin
case ({en_in_n, v})
9'b1_xxxx_xxxx: {y, gs, en_out} = 5'b1_1111;
9'b0_1111_1111: {y, gs, en_out} = 5'b1_1110;
9'b0_xxxx_xxx0: {y, gs, en_out} = 5'b0_0001;
9'b0_xxxx_xx01: {y, gs, en_out} = 5'b0_0101;
9'b0_xxxx_x011: {y, gs, en_out} = 5'b0_1001;
9'b0_xxxx_0111: {y, gs, en_out} = 5'b0_1101;
9'b0_xxx0_1111: {y, gs, en_out} = 5'b1_0001;
9'b0_xx01_1111: {y, gs, en_out} = 5'b1_0101;
9'b0_x011_1111: {y, gs, en_out} = 5'b1_1001;
9'b0_0111_1111: {y, gs, en_out} = 5'b1_1101;
endcase
end
endmodule
|
//
// N-dimensional wormhole dimension ordered decoder
//
// given input coordinates for the target of a message, and for the current node
// it will output a one hot vector which is which direction that header should be routed
//
//
`include "bsg_defines.v"
module bsg_wormhole_router_decoder_dor
#(parameter dims_p=2
// cord_dims_p is normally the same as dims_p. However, the override allows users to pass
// a larger cord array than necessary, useful for parameterizing between 1d/nd networks
,parameter cord_dims_p=dims_p
,parameter reverse_order_p=0 // e.g., 1->Y THEN X, 0->X THEN Y routing
// pass in the markers that delineates storage of dimension fields
// so for example {5, 4, 0} means dim0=[4-1:0], dim1=[5-1:4]
, parameter int cord_markers_pos_p[cord_dims_p:0] = '{ 5, 4, 0 }
, parameter output_dirs_lp=2*dims_p+1
)
(input [cord_markers_pos_p[dims_p]-1:0] target_cord_i
, input [cord_markers_pos_p[dims_p]-1:0] my_cord_i
, output [output_dirs_lp-1:0] req_o
);
genvar i;
logic [dims_p-1:0] eq, lt, gt;
for (i = 0; i < dims_p; i=i+1)
begin: rof
localparam upper_marker_lp = cord_markers_pos_p[i+1];
localparam lower_marker_lp = cord_markers_pos_p[i];
localparam local_cord_width_p = upper_marker_lp - lower_marker_lp;
wire [local_cord_width_p-1:0] targ_cord = target_cord_i[upper_marker_lp-1:lower_marker_lp];
wire [local_cord_width_p-1:0] my_cord = my_cord_i[upper_marker_lp-1:lower_marker_lp];
assign eq[i] = (targ_cord == my_cord);
assign lt[i] = (targ_cord < my_cord);
assign gt[i] = ~eq[i] & ~lt[i];
end // block: rof
// handle base case
assign req_o[0] = & eq; // processor is at 0 in enum
if (reverse_order_p)
begin: rev
assign req_o[(dims_p-1)*2+1] = lt[dims_p-1];
assign req_o[(dims_p-1)*2+1+1] = gt[dims_p-1];
if (dims_p > 1)
begin : fi1
for (i = (dims_p-1)-1; i >= 0; i--)
begin: rof3
assign req_o[i*2+1] = &eq[dims_p-1:i+1] & lt[i];
assign req_o[i*2+1+1] = &eq[dims_p-1:i+1] & gt[i];
end
end
end // if (reverse_order_p)
else
begin: fwd
assign req_o[1] = lt[0]; // down (W,N)
assign req_o[2] = gt[0]; // up (E,S)
for (i = 1; i < dims_p; i++)
begin: rof2
assign req_o[i*2+1] = (&eq[i-1:0]) & lt[i];
assign req_o[i*2+1+1] = (&eq[i-1:0]) & gt[i];
end
end // else: !if(reverse_order_p)
`ifndef SYNTHESIS
initial assert(bsg_noc_pkg::P == 0
&& bsg_noc_pkg::W == 1
&& bsg_noc_pkg::E == 2
&& bsg_noc_pkg::N == 3
&& bsg_noc_pkg::S == 4) else $error("%m: bsg_noc_pkg dirs are inconsistent with this module");
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long max3(long long a, long long b, long long c) { return (a) > (b) ? ((a) > (c) ? (a) : (c)) : ((b) > (c) ? (b) : (c)); } inline long long min3(long long a, long long b, long long c) { return (a) < (b) ? ((a) < (c) ? (a) : (c)) : ((b) < (c) ? (b) : (c)); } long long extgcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return a; } long long d = extgcd(b, a % b, y, x); y -= a / b * x; return d; } inline long long mod(long long a, long long m) { return (a % m + m) % m; } long long modinv(long long a) { long long x, y; extgcd(a, 1000000007, x, y); return mod(x, 1000000007); } long long gcd(long long u, long long v) { long long r; while (0 != v) { r = u % v; u = v; v = r; } return u; } long long lcm(long long u, long long v) { return u / gcd(u, v) * v; } void get_all_factors(int a[], long long int n) { long long int w = sqrt(n); for (int i = 1; i <= w; i++) { if (n % i == 0) { a[i]++; a[n / i]++; } } long long int x = ceil(sqrt(n)); if (sqrt(n) == ceil(sqrt(n))) a[(int)sqrt(n)]--; } long long int memo[100000][110] = {0}; long long C(long long n, long long r) { if (r == 0 || r == n) return 1; if (memo[n][r] != -1) return memo[n][r]; return memo[n][r] = (C(n - 1, r - 1) % 1000000007 + C(n - 1, r) % 1000000007) % 1000000007; } int valid(string s, int i) { if (s == lol or i == -1000050000) { return 0; } return 1; } void status(string s1 = lol , long long int i1 = -1000050000, string s2 = lol , long long int i2 = -1000050000, string s3 = lol , long long int i3 = -1000050000) { if (1) { if (valid(s1, i1)) { cout << s1 << = << i1 << ; } if (valid(s2, i2)) { cout << s2 << = << i2 << ; } if (valid(s3, i3)) { cout << s3 << = << i3 << ; } cout << endl; } } long long int poww(long long b, long long e) { if (e == 0) return 1; else if (e % 2 == 0) { long long a = pow(b, e / 2); return a * a; } else { long long a = pow(b, e / 2); return b * a * a; } } long long int powm(long long x, long long y, long long m = 1000000007) { x = x % m; long long res = 1; while (y) { if (y & 1) res = res * x; res %= m; y = y >> 1; x = x * x; x %= m; } return res; } vector<pair<int, int> > range(1000000); vector<int> adj[1000000]; vector<int> d(1000000, 0); int p[1000000] = {0}; int T = 0; void dfs(int v, int pa = -1, int dep = 0) { p[v] = pa; d[v] = dep; range[v].first = T; T++; for (auto i : adj[v]) { if (i != pa) { dfs(i, v, dep + 1); } } range[v].second = T; T++; } int main() { int n, m; cin >> n >> m; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1); while (m--) { int k; cin >> k; int a[k]; for (int i = 0; i < k; i++) { cin >> a[i]; } int it = a[0]; for (auto i : a) { if (d[i] > d[it]) { it = i; } } for (auto &i : a) { if (it == i) { continue; } if (p[i] != -1) { i = p[i]; } } int ok = 1; for (auto i : a) { if (range[i].first <= range[it].first and range[i].second >= range[it].second) { } else { ok = 0; break; } } if (ok) { cout << YES << endl; } else { cout << NO << endl; } } }
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
* This module generates a CRC7 value from an incomming bitstream
* the value is generated from bit that is currently shifting out
* The final crc is valid after the last bit is sent, it might be
* necessary to send this value one clock cycle before
*
* this value should be placed in the top bits of the last byte
* CCCCCCC1
* C = CRC bit
*
* Hold in reset when not using
*
* Changes:
* 2015.08.08: Initial Add
*/
module crc7 #(
parameter POLYNOMIAL = 8'h09,
parameter SEED = 8'h00
)(
input clk,
input rst,
input bit,
output [6:0] crc,
input hold
);
//local parameters
//registes/wires
reg [7:0] outval;
//submodules
//asynchronous logic
assign crc = outval[6:0];
//synchronous logic
//XXX: Does this need to be asynchronous?
always @ (posedge clk) begin
if (rst) begin
outval <= SEED;
end
else begin
//Shift the output value
if (!hold)
outval[7:0] <= bit ? ({outval[6:0], 1'b0} ^ POLYNOMIAL) : {outval[6:0], 1'b0};
end
end
endmodule
|
module spdif_tx(
input wire clk, // 24.576Mhz
input wire rst,
input wire [1:0] ack_i,
input [47:0] data_i,
output wire [1:0] pop_o,
input wire [191:0] udata_i,
input wire [191:0] cdata_i,
output wire spdif_o
);
reg halfbit_ff;
always @(posedge clk) begin
if (rst)
halfbit_ff <= 1'b0;
else
halfbit_ff <= ~halfbit_ff;
end
wire halfbit = halfbit_ff;
reg [47:0] data_latch;
always @(posedge clk) begin
if (ack_i[0])
data_latch[23:0] <= data_i[23:0];
if (ack_i[1])
data_latch[47:24] <= data_i[47:24];
end
parameter SYNCCODE_B0 = 8'b00010111;
parameter SYNCCODE_W0 = 8'b00011011;
parameter SYNCCODE_M0 = 8'b00011101;
parameter SYNCCODE_B1 = ~SYNCCODE_B0;
parameter SYNCCODE_W1 = ~SYNCCODE_W0;
parameter SYNCCODE_M1 = ~SYNCCODE_M0;
reg [4:0] subframe_pos_counter_ff;
always @(posedge clk) begin
if (rst) begin
subframe_pos_counter_ff <= 5'd0;
end else if (halfbit) begin
subframe_pos_counter_ff <= subframe_pos_counter_ff + 5'd1;
end
end
wire send_synccode = subframe_pos_counter_ff < 5'd4;
wire send_parity = subframe_pos_counter_ff == 5'd31;
wire prepare_subframe = halfbit & (subframe_pos_counter_ff == 5'd3);
wire prepare_synccode_type = ~halfbit & (subframe_pos_counter_ff == 5'd31);
wire prepare_synccode = halfbit & (subframe_pos_counter_ff == 5'd31);
wire prev_subframe_end;
reg [2:0] synccode_type_ff;
parameter SYNCCODE_TYPE_B = 0;
parameter SYNCCODE_TYPE_W = 1;
parameter SYNCCODE_TYPE_M = 2;
reg [7:0] frame_counter_ff;
wire end_of_frame = frame_counter_ff == 8'd191;
always @(posedge clk) begin
if (rst) begin
synccode_type_ff <= SYNCCODE_TYPE_B;
frame_counter_ff <= 8'd191;
end else if (prepare_synccode_type) begin
case (synccode_type_ff)
SYNCCODE_TYPE_B:
synccode_type_ff <= SYNCCODE_TYPE_W;
SYNCCODE_TYPE_W:
synccode_type_ff <= end_of_frame ? SYNCCODE_TYPE_B : SYNCCODE_TYPE_M;
SYNCCODE_TYPE_M:
synccode_type_ff <= SYNCCODE_TYPE_W;
endcase
if (end_of_frame)
frame_counter_ff <= 8'd0;
else
frame_counter_ff <= frame_counter_ff + 1;
end
end
assign pop_ch = (synccode_type_ff == SYNCCODE_TYPE_W) ? 1'b1 : 1'b0;
reg [7:0] synccode_shiftreg;
always @(posedge clk) begin
if (prepare_synccode) begin
case (synccode_type_ff)
SYNCCODE_TYPE_B:
synccode_shiftreg <= prev_subframe_end ? SYNCCODE_B0 : SYNCCODE_B1;
SYNCCODE_TYPE_W:
synccode_shiftreg <= prev_subframe_end ? SYNCCODE_W0 : SYNCCODE_W1;
SYNCCODE_TYPE_M:
synccode_shiftreg <= prev_subframe_end ? SYNCCODE_M0 : SYNCCODE_M1;
endcase
end else
synccode_shiftreg <= {synccode_shiftreg[6:0], 1'b0};
end
// FIXME
wire [23:0] data_active = pop_ch ? data_latch[47:24] : data_latch[23:0];
// {User,Control} data
reg [191:0] udata_shiftreg;
reg [191:0] cdata_shiftreg;
always @(posedge clk) begin
if (end_of_frame)
udata_shiftreg <= udata_i;
else if (prepare_subframe)
udata_shiftreg <= {udata_shiftreg[190:0], 1'b0};
if (end_of_frame)
cdata_shiftreg <= cdata_i;
else if (prepare_subframe)
cdata_shiftreg <= {cdata_shiftreg[190:0], 1'b0};
end
reg [26:0] subframe_shiftreg;
always @(posedge clk) begin
if (prepare_subframe) begin
subframe_shiftreg <= {data_active, 1'b1, udata_shiftreg[191], cdata_shiftreg[191]};
end else if (halfbit)
subframe_shiftreg <= {subframe_shiftreg[25:0], 1'b0};
end
wire subframe_bit = subframe_shiftreg[26];
reg parity_ff;
always @(posedge clk) begin
if (prepare_subframe)
parity_ff <= 0;
else if (halfbit)
parity_ff <= parity_ff ^ subframe_bit;
end
wire parity = parity_ff;
wire subframe_or_parity_bit = send_parity ? parity : subframe_shiftreg[26];
reg encoded_subframe_ff;
always @(posedge clk) begin
if (rst)
encoded_subframe_ff <= 0;
else
encoded_subframe_ff <= (subframe_or_parity_bit | halfbit) ^ encoded_subframe_ff;
end
wire spdif_tbo = send_synccode ? synccode_shiftreg[7] : encoded_subframe_ff;
assign prev_subframe_end = encoded_subframe_ff;
reg spdif_out_ff;
always @(posedge clk)
spdif_out_ff <= spdif_tbo;
assign spdif_o = spdif_out_ff;
assign pop_o = prepare_subframe ? {pop_ch, ~pop_ch} : 2'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_1_V
`define SKY130_FD_SC_HVL__DFRTP_1_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, ans = 0, sum = 0, sum2 = 0; cin >> n; int a[n + 1]; a[0] = 0; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a, a + (n + 1)); for (int i = 1; i <= n; i++) { sum = (sum, a[i]); sum2++; if ((ans + sum2) >= sum) { ans += sum2; sum2 = 0; } } cout << ans + 1 << endl; } }
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2011 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Extraction to Ocaml : use of basic Ocaml types *)
Scheme Equality for nat.
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
|
//Dummy tb for sound channel 4.
//Tb is only for debug this module.
`timescale 1ns / 1ps
`include "aDefinitions.v"
`include "collaterals.v"
`include "SoundControllerChannel4.v"
`include "SoundControllerOSC1.v"
`include "SoundControllerOSC2.v"
module tb;
reg clk;
wire clk64;
wire clk256;
wire clk131k;
wire clk262k;
reg rst;
wire [4:0] out;
reg [7:0] nr41;
reg [7:0] nr42;
reg [7:0] nr43;
reg [7:0] nr44;
always begin
#`CLOCK_CYCLE clk = ~clk;
end
osc1 o1
(
.iClock(clk),
.iReset(rst),
.oOut64(clk64),
.oOut256(clk256)
);
osc2 o2
(
.iClock(clk),
.iReset(rst),
.oOut131k(clk131k),
.oOut262k(clk262k)
);
SoundCtrlChannel4 # () scc2 (
.iClock(clk),
.iReset(rst),
.iOsc64(clk64),
.iOsc256(clk256),
.iNR41(nr41),
.iNR42(nr42),
.iNR43(nr43),
.iNR44(nr44),
.oOut(out)
);
integer i;
initial begin
// $dumpfile("dump_sound_channel4.vcd");
// $dumpvars();
// $display("tiempo \t\t out4");
// $monitor ("%0d \t\t %0d",$time, out);
clk = 0;
rst = 1'b0;
@(negedge clk) rst = 1'b1;
//test1
/*
nr41 = 8'h03; // length = $XX, timer disabled
nr42 = 8'hF4; // attenuate envelope, step time = 7. initial value = $F = 15.
nr43 = 8'h52; // div ratio = 3. lfrs = 15 stages , shifts = 3
nr44 = 8'h40; // timer disabled.
*/
//test2
///*
nr41 = 8'h00; // length = $XX, timer disabled
nr42 = 8'h1C; // amplify envelope, step time = 7. initial value = $2 = 2.
nr43 = 8'h52; // div ratio = 3. lfrs = 7 stages , shifts = 3
nr44 = 8'h00; // timer disabled.
//*/
repeat (2) @ (negedge clk);
rst = 1'b0;
// #50_000_000;
for ( i = 0; i < 10000; i = i+1) begin
#5120 $display ("%0d, ", out);
end
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_TB_V
`define SKY130_FD_SC_HDLL__A211O_TB_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a211o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hdll__a211o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_TB_V
|
#include <bits/stdc++.h> const int dx[] = {0, -1, 0, 1, -1, 1, 1, -1, -2, -2, 2, 2, -1, -1, 1, 1}; const int dy[] = {-1, 0, 1, 0, 1, 1, -1, -1, -1, 1, -1, 1, -2, 2, -2, 2}; using namespace std; int main(int argc, char const *argv[]) { int n, m; scanf( %d %d , &n, &m); while (n) { printf( 0 ); n--; if (!n) break; printf( 1 ); n--; } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long Length, X, Y; long long Dp[10000001]; int main(void) { register long long i; cin >> Length >> X >> Y; Dp[1] = X; for (i = 2; i <= Length; i++) { Dp[i] = Dp[i - 1] + X; if (i & 1) { Dp[i] = min(Dp[i], Dp[(i >> 1) + 1] + X + Y); } else { Dp[i] = min(Dp[i], Dp[i >> 1] + Y); } } cout << Dp[Length] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[2]; string ans[2] = { Vladik , Valera }; int main() { cin >> a[0] >> a[1]; int turn = 0; int sub = 1; while (true) { if (a[turn] - sub >= 0) { a[turn] -= sub; } else { break; } sub++; turn = 1 - turn; } cout << ans[turn] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const int mod = (int)1e9 + 7; const double pi = acos(-1.0); const double eps = 1e-9; const int maxn = (int)2e6 + 11; long long n; long long a[maxn]; long long sum[maxn]; int main() { cin >> n; a[1] = 2; sum[1] = 2; for (int i = 2; i <= 2000000; i++) { a[i] = a[i - 1] + 3; sum[i] = sum[i - 1] + a[i]; } int ans = 0; for (int i = 1; sum[i] <= n; i++) { if ((n - sum[i]) % 3 == 0) ans++; } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_SYMBOL_V
`define SKY130_FD_SC_LP__OR3B_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string s; cin >> n >> s; int a1[n], a2[n]; for (int i = 0; i < n; i++) a1[i] = s[i] - 0 ; for (int i = n; i < 2 * n; i++) a2[i - n] = s[i] - 0 ; for (int i = 0; i < n; i++) { int s1(i), s2(i); for (int j = i + 1; j < n; j++) { if (a1[j] < a1[s1]) s1 = j; if (a2[j] < a2[s2]) s2 = j; } swap(a1[i], a1[s1]); swap(a2[i], a2[s2]); } int l(0), m(0); for (int i = 0; i < n; i++) if (a1[i] < a2[i]) l += 1; else if (a1[i] > a2[i]) m += 1; else if (a1[i] == a2[i]) { cout << NO << endl; return 0; } if ((l == n) || (m == n)) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; string mt[1226], sc[1226], s[51], q1, q2; int n, k1, k2, c; map<string, int> O, Z, P; pair<pair<pair<int, int>, int>, string> p[51]; vector<string> v; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> s[i]; } for (int i = 1; i <= n * (n - 1) / 2; i++) { cin >> mt[i] >> sc[i]; c = 0; k1 = 0; k2 = 0; q1 = ; q2 = ; for (int j = 0; j < sc[i].size(); j++) { if (sc[i][j] == : ) { c++; continue; } if (c == 0) { k1 += sc[i][j] - 0 ; k1 *= 10; } else { k2 += sc[i][j] - 0 ; k2 *= 10; } } k1 /= 10; k2 /= 10; c = 0; for (int j = 0; j < mt[i].size(); j++) { if (mt[i][j] == - ) { c++; continue; } if (c == 0) { q1 += mt[i][j]; } if (c == 1) { q2 += mt[i][j]; } } if (k1 > k2) { O[q1] += 3; } else if (k1 < k2) { O[q2] += 3; } else { O[q1]++; O[q2]++; } Z[q1] += k1; Z[q2] += k2; P[q1] += k2; P[q2] += k1; } for (int i = 1; i <= n; i++) { p[i] = make_pair(make_pair(make_pair(O[s[i]], Z[s[i]] - P[s[i]]), Z[s[i]]), s[i]); } sort(p + 1, p + 1 + n); for (int i = n; i >= n / 2 + 1; i--) { v.push_back(p[i].second); } sort(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) { cout << v[i] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool comp(pair<long long, long long> a, pair<long long, long long> b) { if (a.first > a.second && a.first > b.first) return 1; return 0; } void solve() { long long n; cin >> n; vector<pair<double, pair<long long, long long>>> v(n); for (long long i = (0); i < (n); ++i) { cin >> v[i].second.first >> v[i].second.second; v[i].first = v[i].second.first - v[i].second.second; } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); long long s = 0; for (long long i = (0); i < (n); ++i) { s += v[i].second.first * i + v[i].second.second * (n - i - 1); } cout << s; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t1 = 1; while (t1--) { solve(); cout << n ; ; } }
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_ram
*
*/
`default_nettype none
module openhmc_ram #(
parameter DATASIZE = 78, // Memory data word width
parameter ADDRSIZE = 9, // Number of memory address bits
parameter PIPELINED = 0
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
//----------------------------------
//----Signals
//----------------------------------
input wire wen,
input wire [DATASIZE-1:0] wdata,
input wire [ADDRSIZE-1:0] waddr,
input wire ren,
input wire [ADDRSIZE-1:0] raddr,
output wire [DATASIZE-1:0] rdata
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire [DATASIZE-1:0] rdata_ram;
generate
if (PIPELINED == 0)
begin
assign rdata = rdata_ram;
end
else
begin
reg [DATASIZE-1:0] rdata_dly;
reg ren_dly;
assign rdata = rdata_dly;
always @(posedge clk)
begin
ren_dly <= ren;
if (ren_dly)
rdata_dly <= rdata_ram;
end
end
endgenerate
reg [DATASIZE-1:0] MEM [0:(2**ADDRSIZE)-1];
reg [DATASIZE-1:0] data_out;
assign rdata_ram = data_out;
always @(posedge clk)
begin
if (wen)
MEM[waddr] <= wdata;
end
always @(posedge clk)
begin
if (ren)
data_out <= MEM[raddr];
end
endmodule
`default_nettype wire
|
module SortX16 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-1:0] a7,
input [DSIZE-1:0] a8,
input [DSIZE-1:0] a9,
input [DSIZE-1:0] a10,
input [DSIZE-1:0] a11,
input [DSIZE-1:0] a12,
input [DSIZE-1:0] a13,
input [DSIZE-1:0] a14,
input [DSIZE-1:0] a15,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3,
output wire [DSIZE-1:0] sort4,
output wire [DSIZE-1:0] sort5,
output wire [DSIZE-1:0] sort6,
output wire [DSIZE-1:0] sort7,
output wire [DSIZE-1:0] sort8,
output wire [DSIZE-1:0] sort9,
output wire [DSIZE-1:0] sort10,
output wire [DSIZE-1:0] sort11,
output wire [DSIZE-1:0] sort12,
output wire [DSIZE-1:0] sort13,
output wire [DSIZE-1:0] sort14,
output wire [DSIZE-1:0] sort15
);
wire [DSIZE-1:0] sortX8_0_0;
wire [DSIZE-1:0] sortX8_0_1;
wire [DSIZE-1:0] sortX8_0_2;
wire [DSIZE-1:0] sortX8_0_3;
wire [DSIZE-1:0] sortX8_0_4;
wire [DSIZE-1:0] sortX8_0_5;
wire [DSIZE-1:0] sortX8_0_6;
wire [DSIZE-1:0] sortX8_0_7;
wire [DSIZE-1:0] sortX8_1_0;
wire [DSIZE-1:0] sortX8_1_1;
wire [DSIZE-1:0] sortX8_1_2;
wire [DSIZE-1:0] sortX8_1_3;
wire [DSIZE-1:0] sortX8_1_4;
wire [DSIZE-1:0] sortX8_1_5;
wire [DSIZE-1:0] sortX8_1_6;
wire [DSIZE-1:0] sortX8_1_7;
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
wire [DSIZE-1:0] sort4_0;
wire [DSIZE-1:0] sort4_1;
wire [DSIZE-1:0] sort5_0;
wire [DSIZE-1:0] sort5_1;
wire [DSIZE-1:0] sort6_0;
wire [DSIZE-1:0] sort6_1;
wire [DSIZE-1:0] sort7_0;
wire [DSIZE-1:0] sort7_1;
// divide sort
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.a4 (a4),
.a5 (a5),
.a6 (a6),
.a7 (a7),
.sort0 (sortX8_0_0),
.sort1 (sortX8_0_1),
.sort2 (sortX8_0_2),
.sort3 (sortX8_0_3),
.sort4 (sortX8_0_4),
.sort5 (sortX8_0_5),
.sort6 (sortX8_0_6),
.sort7 (sortX8_0_7)
);
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst1 (
.a0 (a8),
.a1 (a9),
.a2 (a10),
.a3 (a11),
.a4 (a12),
.a5 (a13),
.a6 (a14),
.a7 (a15),
.sort0 (sortX8_1_0),
.sort1 (sortX8_1_1),
.sort2 (sortX8_1_2),
.sort3 (sortX8_1_3),
.sort4 (sortX8_1_4),
.sort5 (sortX8_1_5),
.sort6 (sortX8_1_6),
.sort7 (sortX8_1_7)
);
// merge
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(sortX8_0_0),
.b(sortX8_1_7),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(sortX8_0_1),
.b(sortX8_1_6),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sortX8_0_2),
.b(sortX8_1_5),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sortX8_0_3),
.b(sortX8_1_4),
.sort0(sort3_0),
.sort1(sort3_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst4 (
.a(sortX8_0_4),
.b(sortX8_1_3),
.sort0(sort4_0),
.sort1(sort4_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst5 (
.a(sortX8_0_5),
.b(sortX8_1_2),
.sort0(sort5_0),
.sort1(sort5_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst6 (
.a(sortX8_0_6),
.b(sortX8_1_1),
.sort0(sort6_0),
.sort1(sort6_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst7 (
.a(sortX8_0_7),
.b(sortX8_1_0),
.sort0(sort7_0),
.sort1(sort7_1)
);
// bitonic
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst0 (
.a0 (sort0_0),
.a1 (sort1_0),
.a2 (sort2_0),
.a3 (sort3_0),
.a4 (sort4_0),
.a5 (sort5_0),
.a6 (sort6_0),
.a7 (sort7_0),
.sort0 (sort0),
.sort1 (sort1),
.sort2 (sort2),
.sort3 (sort3),
.sort4 (sort4),
.sort5 (sort5),
.sort6 (sort6),
.sort7 (sort7)
);
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst1 (
.a0 (sort7_1),
.a1 (sort6_1),
.a2 (sort5_1),
.a3 (sort4_1),
.a4 (sort3_1),
.a5 (sort2_1),
.a6 (sort1_1),
.a7 (sort0_1),
.sort0 (sort8),
.sort1 (sort9),
.sort2 (sort10),
.sort3 (sort11),
.sort4 (sort12),
.sort5 (sort13),
.sort6 (sort14),
.sort7 (sort15)
);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:12:25 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/clk_108MHz/clk_108MHz_funcsim.v
// Design : clk_108MHz
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_108MHz,clk_wiz_v5_1,{component_name=clk_108MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_108MHz
(clk_100MHz,
clk_108MHz,
locked);
input clk_100MHz;
output clk_108MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_108MHz;
wire locked;
clk_108MHzclk_108MHz_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_108MHz(clk_108MHz),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_108MHz_clk_wiz" *)
module clk_108MHzclk_108MHz_clk_wiz
(clk_100MHz,
clk_108MHz,
locked);
input clk_100MHz;
output clk_108MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_100MHz_clk_108MHz;
wire clk_108MHz;
wire clk_108MHz_clk_108MHz;
wire clkfbout_buf_clk_108MHz;
wire clkfbout_clk_108MHz;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_108MHz),
.O(clkfbout_buf_clk_108MHz));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_100MHz),
.O(clk_100MHz_clk_108MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_108MHz_clk_108MHz),
.O(clk_108MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.125000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(9.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_108MHz),
.CLKFBOUT(clkfbout_clk_108MHz),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_100MHz_clk_108MHz),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_108MHz_clk_108MHz),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000 * 1000 * 1000 + 7; const int INF = 2000 * 1000 * 1000; const double EPS = 1e-9; const double pi = acos(-1.0); const int maxn = 100010; inline long long sqr(int n) { return n * 1ll * n; } struct Point { int x, y; Point() {} inline bool operator<(const Point& p) const { return y < p.y; } inline long long dist_to(const Point& p) const { return sqr(x - p.x) + sqr(y - p.y); } }; Point a[maxn]; int n, x, sum; long long minans = INF * 1ll * INF; inline void update(const Point& p1, const Point& p2) { minans = min(minans, p1.dist_to(p2)); } inline void go(int l, int r) { if (r - l <= 3) { for (int i = l; i <= r; i++) for (int j = i + 1; j <= r; j++) update(a[i], a[j]); sort(a + l, a + r + 1); return; } int mid = (l + r) >> 1; int midx = a[mid].x; int buf_size = 0; go(l, mid - 1); go(mid, r); static Point buf[maxn]; merge(a + l, a + mid, a + mid, a + r + 1, buf); copy(buf, buf + (r - l + 1), a + l); for (int i = l; i <= r; i++) { if (sqr(abs(a[i].x - midx)) < minans) { for (int j = buf_size - 1; j >= 0 && sqr(a[i].y - buf[j].y) < minans; j--) update(a[i], buf[j]); buf[buf_size++] = a[i]; } } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &x); sum += x; a[i].x = i + 1; a[i].y = sum; } go(0, n - 1); printf( %I64d , minans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 1 << 23; char s[55][55]; int p[55], r[55], d[55], h[55], ans = 0; int f[maxn], g[maxn], bit[maxn]; int ff(int x) { if (p[x] != x) p[x] = ff(p[x]); return p[x]; } void funion(int x, int y) { x = ff(x); y = ff(y); if (x != y) p[y] = x; } int main() { int n, m, i, j; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %s , s[i]); for (i = 0; i < n; i++) p[i] = i; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (i == j) continue; if (s[i][j] == A ) funion(i, j); } } for (i = 0; i < n; i++) d[ff(i)]++; memset(h, -1, sizeof(h)); for (i = m = 0; i < n; i++) { if (d[i] > 1) h[i] = m++; } for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (i == j) continue; if (s[i][j] == X ) { if (ff(i) == ff(j)) { return puts( -1 ), 0; } if (d[ff(i)] > 1 && d[ff(j)] > 1) { r[h[ff(i)]] |= 1 << h[ff(j)]; r[h[ff(j)]] |= 1 << h[ff(i)]; } } } } if (!m) { printf( %d n , n - 1); return 0; } for (i = 0; i < m; i++) r[i] ^= (1 << m) - 1; for (i = 0; i < (1 << m); i++) { if ((i & (-i)) == i) f[i] = 1; else { j = i ^ (1 << (__builtin_ffs(i) - 1)); if (f[j] && (r[__builtin_ffs(i) - 1] & j) == j) f[i] = 1; } g[i] = 1; bit[i] = (m - __builtin_popcount(i)) & 1; } for (i = 0; i < m; i++) { for (j = 0; j < (1 << m); j++) { if ((j >> i) & 1) f[j] += f[j ^ (1 << i)]; } } for (i = 0; i < m; i++) { for (j = 0; j < (1 << m); j++) g[j] *= f[j]; int x = 0; for (j = 0; j < (1 << m); j++) { if (bit[j]) x -= g[j]; else x += g[j]; } if (x) break; } printf( %d n , n + i); return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; const int M = 1000000007; int t; int n, k; string s; int dp[1001][1002][2]; int get(int it, int d, bool complete, bool zero) { if (it == 0) return complete; if (zero && dp[it][d][complete] != -1) return dp[it][d][complete]; long long ret = 0; int to = zero ? 9 : s[n - it] - 0 ; for (int i = 0; i <= to; i++) { bool nxtZero = zero || (i < to); bool nxtComplete = complete || ((i == 4 || i == 7) && (d <= k)); int nxtD = min((i == 4 || i == 7) ? 1 : d + 1, 1001); ret += get(it - 1, nxtD, nxtComplete, nxtZero); } ret %= M; if (zero) dp[it][d][complete] = ret; return ret; } bool correct() { int prev = -1; for (int i = 0, _n = (n); i < _n; ++i) if (s[i] == 4 || s[i] == 7 ) { if (prev != -1 && i - prev <= k) return true; prev = i; } return false; } void solution() { cin >> t >> k; memset((dp), (-1), sizeof((dp))); while (t--) { cin >> s, n = (int)((s).size()); int ret = get(n, 1001, 0, 0); ret -= correct(); cin >> s, n = (int)((s).size()); ret = get(n, 1001, 0, 0) - ret; if (ret >= M) ret %= M; if (ret < 0) ret += M; cout << ret << endl; } } int main() { solution(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; scanf( %d%d%d , &a, &b, &c); int ok = 0; if (a == 1 || b == 1 || c == 1) ok = 1; if (a == 3 && b == 3 && c == 3) ok = 1; if (a == 2 && b == 2) ok = 1; if (b == 2 && c == 2) ok = 1; if (a == 2 && c == 2) ok = 1; if (a == 2 && b == 4 && c == 4) ok = 1; if (a == 4 && b == 2 && c == 4) ok = 1; if (a == 4 && b == 4 && c == 2) ok = 1; puts(ok ? YES : NO ); return 0; }
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#include <bits/stdc++.h> using namespace std; long long a[10], nd[10], dad[10], root, ans; int nopd(long long n) { long long now = 2, ans = 0; for (; now * now <= n; now++) while (n && n % now == 0) { n /= now; ans++; } if (n > 1) ans++; return ans; } bool prime(long long n) { if (n == 1) return false; for (long long i = 2; i * i <= n; i++) if (n % i == 0) return false; return true; } int nopd_pooyan(long long a) { int ans = 0; if (prime(a)) ans++; else { long long j = 2; while (a > 1) { if (a % j == 0) { while (a % j == 0) { a /= j; ans++; } if (prime(a)) { ans++; break; } } j++; } } return ans; } int main() { int n, best, ibest, flag; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); reverse(a, a + n); for (int i = 0; i < n; i++) { nd[i] = nopd_pooyan(a[i]); ans += nd[i]; if (nd[i] == 1) ans--; } for (int i = 0; i < n; i++) { if (!dad[i]) root++; flag = 1; while (flag) { best = ibest = -1; for (int j = i + 1; j < n; j++) if (a[i] % a[j] == 0 && !dad[j] && nd[j] > best) { best = nd[j]; ibest = j; } if (ibest == -1) flag = 0; else { ans -= (best - 1); dad[ibest] = i + 1; a[i] /= a[ibest]; } } } ans += root; if (root > 1) ans++; cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; long long n, a[1000003]; pair<long long, long long> b[1000003]; long long calc1() { for (int i = 0; i < n; i++) b[i] = make_pair(-a[i], i); sort(b, b + n); set<signed> s1; s1.insert(-1); s1.insert(n); long long ret = 0; for (int i = 0; i < n; i++) { set<int>::iterator tmpr = s1.lower_bound(b[i].second), tmpl = prev(tmpr); ret -= (b[i].second - *tmpl) * (*tmpr - b[i].second) * b[i].first; s1.insert(b[i].second); } return ret; } long long calc2() { for (int i = 0; i < n; i++) b[i] = make_pair(-b[i].first, b[i].second); for (int i = 0; i < n / 2; i++) swap(b[i], b[n - i - 1]); set<signed> s1; s1.insert(-1); s1.insert(n); long long ret = 0; for (int i = 0; i < n; i++) { set<int>::iterator tmpr = s1.lower_bound(b[i].second), tmpl = prev(tmpr); ret += (b[i].second - *tmpl) * (*tmpr - b[i].second) * b[i].first; s1.insert(b[i].second); } return ret; } int main() { cin >> n; for (int i = 0; i < n; i++) scanf( %lld , a + i); cout << calc1() - calc2(); }
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#include <bits/stdc++.h> using namespace std; int a[100], b[45], c[100]; int main() { int x; cin >> x; int p = 0, ans = 0, q = 0, f = 0; while (x) { c[p++] = x % 2; if (x % 2 == 0) f = 1; x = x / 2; } int pp = 0; for (int h = p - 1; h >= 0; h--) { a[pp++] = c[h]; } if (f) { while (ans + 1) { int flag = 0, flag1 = 0, flag2 = 0; for (int i = 0; i < p; i++) { if (flag) { if (a[i] == 1) a[i] = 0; else if (a[i] == 0) a[i] = 1; } else if (a[i] == 0) { ans++; a[i] = 1; flag = 1; b[q++] = p - i; } } for (int i = 0; i < p; i++) { if (a[i] == 0) { break; } if (i == p - 1) { flag1 = 1; } } if (flag1) { break; } ans++; for (int j = p - 1; j >= 0; j--) { a[j]++; if (a[j] == 2) a[j] = 0; else if (a[j] = 1) break; } for (int i = 0; i < p; i++) { if (a[i] == 0) { break; } if (i == p - 1) { flag2 = 1; } } if (flag2) { break; } } cout << ans << endl; for (int k = 0; k < q; k++) { if (k == 0) cout << b[k]; else cout << << b[k]; } cout << endl; } else { cout << 0 << endl; } }
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#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n; cin >> n; long long int a[n], b[n], c[n - 1]; b[n - 1] = 0, c[n - 2] = 0; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n - 1; i++) { cin >> b[i]; } for (int i = 0; i < n - 2; i++) { cin >> c[i]; } sort(a, a + n); sort(b, b + n - 1); sort(c, c + n - 2); for (int i = 0; i < n; i++) { if (a[i] != b[i]) { cout << a[i] << endl; break; } } for (int i = 0; i < n - 1; i++) { if (b[i] != c[i]) { cout << b[i] << endl; break; } } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2012.2
// Copyright (C) 2012 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module types_float_double_grp_fu_86_ACMP_dadd_2_io(
clk,
reset,
io_ce,
io_rdy,
io_a,
io_b,
io_result);
input clk;
input io_ce;
output io_rdy;
input reset;
input[64 - 1:0] io_a;
input[64 - 1:0] io_b;
output[64 - 1:0] io_result;
adder64fp m(
.clk(clk),
.ce(io_ce),
.rdy(io_rdy),
.a(io_a),
.b(io_b),
.operation(6'd0), //according to DSP core manual
.result(io_result));
endmodule
module adder64fp(
clk,
ce,
rdy,
a,
b,
operation,
result);
input clk;
input ce;
output rdy;
input [63 : 0] a;
input [63 : 0] b;
input [5 : 0] operation;
output [63 : 0] result;
//assign result = a + b;
//ACMP_dadd #(
//.ID( ID ),
//.NUM_STAGE( 16 ),
//.din0_WIDTH( din0_WIDTH ),
//.din1_WIDTH( din1_WIDTH ),
//.dout_WIDTH( dout_WIDTH ))
//ACMP_dadd_U(
// .clk( clk ),
// .reset( reset ),
// .ce( ce ),
// .din0( din0 ),
// .din1( din1 ),
// .dout( dout ));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_shiftreg.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:47 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.5 2002/08/14 18:16:59 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.4 2002/03/02 21:06:01 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`timescale 1ns/10ps
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
LatchByte, ShiftedBit, Prsd, LinkFail);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
input Mdi; // MII input data
input [4:0] Fiad; // PHY address
input [4:0] Rgad; // Register address (within the selected PHY)
input [15:0]CtrlData; // Control data (data to be written to the PHY)
input WriteOp; // The current operation is a PHY register write operation
input [3:0] ByteSelect; // Byte select
input [1:0] LatchByte; // Byte select for latching (read operation)
output ShiftedBit; // Bit shifted out of the shift register
output[15:0]Prsd; // Read Status Data (data read from the PHY)
output LinkFail; // Link Integrity Signal
reg [7:0] ShiftReg; // Shift register for shifting the data in and out
reg [15:0]Prsd;
reg LinkFail;
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
ShiftReg[7:0] <= #Tp 8'h0;
Prsd[15:0] <= #Tp 16'h0;
LinkFail <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
if(|ByteSelect)
begin
case (ByteSelect[3:0])
4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
default : ShiftReg[7:0] <= #Tp 8'h0;
endcase
end
else
begin
ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(LatchByte[0])
begin
Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
if(Rgad == 5'h01)
LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
end
else
begin
if(LatchByte[1])
Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
end
end
end
end
end
assign ShiftedBit = ShiftReg[7];
endmodule
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; long long ar[maxn]; int main() { long long n, m; cin >> n >> m; long long a, b, c; cin >> a >> b >> c; ar[a] = 1, ar[b] = 2, ar[c] = 3; for (int i = 1; i < m; ++i) { cin >> a >> b >> c; if (!ar[a] and !ar[b] and !ar[c]) ar[a] = 1, ar[b] = 2, ar[c] = 3; else { if (ar[a]) { if (ar[a] == 1) ar[b] = 2, ar[c] = 3; else if (ar[a] == 2) ar[b] = 1, ar[c] = 3; else ar[b] = 1, ar[c] = 2; } else if (ar[b]) { if (ar[b] == 1) ar[a] = 2, ar[c] = 3; else if (ar[b] == 2) ar[a] = 1, ar[c] = 3; else ar[a] = 1, ar[c] = 2; } else if (ar[c]) { if (ar[c] == 1) ar[a] = 2, ar[b] = 3; else if (ar[c] == 2) ar[a] = 1, ar[b] = 3; else ar[a] = 1, ar[b] = 2; } } } for (int i = 1; i < n + 1; ++i) cout << ar[i] << ; return 0; }
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#include <bits/stdc++.h> using namespace std; long long pos[11], neg[11], n, x, zero; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x; if (x == 0) zero++; if (x > 0) pos[x]++; if (x < 0) neg[abs(x)]++; } long long cnt = 0; cnt += zero * (zero - 1) / 2; for (int i = 1; i <= 10; i++) cnt += (pos[i] * neg[i]); cout << cnt; return 0; }
|
module Datapath(input clock,
input clear);
// PC register
wire[31:0] pc_in;
wire[31:0] pc_out;
PcRegister pc_register(
clock,
clear,
pc_in,
pc_out);
// Instruction memory
wire[31:0] instruction_memory_address;
wire[31:0] instruction_memory_instr;
InstructionMemory instruction_memory(
clock,
clear,
instruction_memory_address,
instruction_memory_instr);
// Connections for instruction memory
assign instruction_memory_address = pc_out;
// Adder4
wire[31:0] adder4_in;
wire[31:0] adder4_out;
Adder4 adder4(adder4_in,
adder4_out);
// Connections for Adder4
assign adder4_in = pc_out;
// PC MUX
wire[31:0] pc_mux_in0;
wire[31:0] pc_mux_in1;
wire[31:0] pc_mux_out;
wire pc_mux_sel;
Mux32Bit2To1 pc_mux(pc_mux_in0,
pc_mux_in1,
pc_mux_sel,
pc_mux_out);
// Connections for PC MUX
assign pc_in = pc_mux_out;
assign pc_mux_in0 = adder4_out;
// Register file MUX
wire[4:0] register_file_mux_in0;
wire[4:0] register_file_mux_in1;
wire[4:0] register_file_mux_out;
wire register_file_mux_sel;
Mux5Bit2To1 register_file_mux(
register_file_mux_in0,
register_file_mux_in1,
register_file_mux_sel,
register_file_mux_out);
// Connections for register file MUX
assign register_file_mux_in0 = instruction_memory_instr[20:16];
assign register_file_mux_in1 = instruction_memory_instr[15:11];
// Register file
wire[4:0] register_file_read_index1;
wire[31:0] register_file_read_data1;
wire[4:0] register_file_read_index2;
wire[31:0] register_file_read_data2;
wire register_file_write;
wire[4:0] register_file_write_index;
reg[31:0] register_file_write_data;
RegisterFile register_file(
clock,
clear,
register_file_read_index1,
register_file_read_data1,
register_file_read_index2,
register_file_read_data2,
register_file_write,
register_file_write_index,
register_file_write_data);
// Connections for register file
assign register_file_read_index1 = instruction_memory_instr[25:21];
assign register_file_read_index2 = instruction_memory_instr[20:16];
assign register_file_write_index = register_file_mux_out;
// ALU MUX
wire[31:0] alu_mux_in0;
wire[31:0] alu_mux_in1;
wire[31:0] alu_mux_in2;
wire[31:0] alu_mux_in3;
wire[31:0] alu_mux_out;
wire[1:0] alu_mux_sel;
Mux32Bit4To1 alu_mux(
alu_mux_in0,
alu_mux_in1,
alu_mux_in2,
alu_mux_in3,
alu_mux_sel,
alu_mux_out);
// Connections for ALU MUX
assign alu_mux_in0 = register_file_read_data2;
// ALU
wire[31:0] alu_op1;
wire[31:0] alu_op2;
wire[3:0] alu_f;
wire[31:0] alu_result;
wire alu_zero;
Alu alu(alu_op1,
alu_op2,
alu_f,
alu_result,
alu_zero);
// MULT/DIV ALU Module
wire mult_alu_en;
wire[31:0] alu_result_hi;
wire[31:0] alu_result_lo;
Mult_Div_Alu mult_div_alu(alu_op1,
alu_op2,
alu_f,
mult_alu_en,
alu_result_hi,
alu_result_lo);
// Connections for ALU(s)
assign alu_op1 = register_file_read_data1;
assign alu_op2 = alu_mux_out;
// Data memory
wire[31:0] data_memory_address;
wire data_memory_write;
wire[31:0] data_memory_write_data;
wire[31:0] data_memory_read_data;
DataMemory data_memory(
clock,
clear,
data_memory_address,
data_memory_write,
data_memory_write_data,
data_memory_read_data);
// Connections for data memory
assign data_memory_address = alu_result;
assign data_memory_write_data = register_file_read_data2;
// Data memory MUX
wire[31:0] data_memory_mux_in0;
wire[31:0] data_memory_mux_in1;
wire data_memory_mux_sel;
wire[31:0] data_memory_mux_out;
Mux32Bit2To1 data_memory_mux(
data_memory_mux_in0,
data_memory_mux_in1,
data_memory_mux_sel,
data_memory_mux_out);
// Connections for data memory MUX
assign data_memory_mux_in0 = alu_result;
assign data_memory_mux_in1 = data_memory_read_data;
//assign register_file_write_data = data_memory_mux_out;
// SignExtend
wire[15:0] sign_extend_in;
wire[31:0] sign_extend_out;
SignExtend sign_extend(
sign_extend_in,
sign_extend_out);
// Connections for SignExtend
assign sign_extend_in = instruction_memory_instr[15:0];
// ZeroExtend
wire[15:0] zero_extend_in;
wire[31:0] zero_extend_out;
ZeroExtend zero_extend(
zero_extend_in,
zero_extend_out);
// Connections for ZeroExtend
assign zero_extend_in = instruction_memory_instr[15:0];
// Zero_Sign_Ext MUX
wire[31:0] zero_sign_ext_mux_in0;
wire[31:0] zero_sign_ext_mux_in1;
wire zero_sign_ext_mux_sel;
wire[31:0] zero_sign_ext_mux_out;
Mux32Bit2To1 zero_sign_ext_mux(
zero_sign_ext_mux_in0,
zero_sign_ext_mux_in1,
zero_sign_ext_mux_sel,
zero_sign_ext_mux_out);
// Connections for Zero_Sign_Ext MUX
assign zero_sign_ext_mux_in0 = sign_extend_out;
assign zero_sign_ext_mux_in1 = zero_extend_out;
assign alu_mux_in1 = zero_sign_ext_mux_out;
// ShiftLeft
wire[31:0] shift_left_in;
wire[31:0] shift_left_out;
ShiftLeft shift_left(
shift_left_in,
shift_left_out);
// Connections for ShiftLeft
assign shift_left_in = sign_extend_out;
// Adder
wire[31:0] adder_op1;
wire[31:0] adder_op2;
wire[31:0] adder_result;
Adder adder(adder_op1,
adder_op2,
adder_result);
// Connections for adder
assign adder_op1 = shift_left_out;
assign adder_op2 = adder4_out;
assign pc_mux_in1 = adder_result;
// And gate
wire and_gate_in1;
wire and_gate_in2;
wire and_gate_out;
and and_gate(and_gate_out,
and_gate_in1,
and_gate_in2);
// Connections for and gate
assign and_gate_in2 = alu_zero;
assign pc_mux_sel = and_gate_out;
// ZeroExtendShamt
wire[4:0] zero_ext_shamt_in;
wire[31:0] zero_ext_shamt_out;
ZeroExtendShamt zero_ext_shamt(
zero_ext_shamt_in,
zero_ext_shamt_out);
// Connections for ZeroExtendShamt
assign zero_ext_shamt_in = instruction_memory_instr[10:6];
assign alu_mux_in2 = zero_ext_shamt_out;
// Control unit
wire[5:0] control_unit_opcode;
wire[5:0] control_unit_funct;
wire control_unit_reg_dst;
wire control_unit_reg_write;
wire[1:0] control_unit_alu_src;
wire[3:0] control_unit_alu_op;
wire control_unit_branch;
wire control_unit_mem_write;
wire control_unit_mem_to_reg;
wire control_unit_zero_sign_ext;
wire control_unit_mult_op;
wire control_unit_mfhi;
wire control_unit_mflo;
ControlUnit control_unit(
control_unit_opcode,
control_unit_funct,
control_unit_reg_dst,
control_unit_reg_write,
control_unit_alu_src,
control_unit_alu_op,
control_unit_branch,
control_unit_mem_write,
control_unit_mem_to_reg,
control_unit_zero_sign_ext,
control_unit_mult_op,
control_unit_mfhi,
control_unit_mflo);
// Connections for control unit
assign control_unit_opcode = instruction_memory_instr[31:26];
assign control_unit_funct = instruction_memory_instr[5:0];
assign register_file_mux_sel = control_unit_reg_dst;
assign register_file_write = control_unit_reg_write;
assign alu_mux_sel = control_unit_alu_src;
assign alu_f = control_unit_alu_op;
assign and_gate_in1 = control_unit_branch;
assign data_memory_write = control_unit_mem_write;
assign data_memory_mux_sel = control_unit_mem_to_reg;
assign mult_alu_en = control_unit_mult_op;
// NOTE: it's not possible for mflo and mfhi to both be enabled so this
// won't result in a race condition
always@(control_unit_mflo, control_unit_mfhi) begin
case({control_unit_mflo, control_unit_mfhi})
2'b10: register_file_write_data = alu_result_lo;
2'b01: register_file_write_data = alu_result_hi;
default: register_file_write_data = data_memory_mux_out;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_BLACKBOX_V
`define SKY130_FD_SC_MS__MUX4_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T> int chkmax(T &a, T b) { if (b > a) { a = b; return 1; } return 0; } template <class T> int chkmin(T &a, T b) { if (b < a) { a = b; return 1; } return 0; } template <class iterator> void output(iterator begin, iterator end, ostream &out = cerr) { while (begin != end) { out << (*begin) << ; begin++; } out << endl; } template <class T> void output(T x, ostream &out = cerr) { output(x.begin(), x.end(), out); } void fast_io() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } const int MOD = 1e9 + 7; const int _2 = (MOD + 1) / 2; void add(int &a, int b) { a += b; if (a >= MOD) { a -= MOD; } } int mul(int a, int b) { return (1LL * a * b) % MOD; } const int mx = 2e3 + 10; int n, m, cs, used[mx]; vector<vector<int> > g; vector<int> a; void read() { cin >> n >> m; g.resize(n); for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; u--; v--; g[u].push_back(v); g[v].push_back(u); } } int dfs(int v) { int res = 1; used[v] = 1; for (auto v1 : g[v]) { if (used[v1] == 0) { res += dfs(v1); } } return res; } void find_cycles() { used[0] = 1; for (auto v : g[0]) { if (used[v] == 0) { int len = dfs(v); a.push_back(len + 1); } } } int dp[mx][2 * mx], dpPref[mx][2 * mx], dpSuf[mx][2 * mx]; int dpPrefObl[mx][2 * mx], dpSufObl[mx][2 * mx]; void update_dp(int len, int idx, int stay) { fill(dp[idx + 1], dp[idx + 1] + m + 1, 0); for (int delta = 0; delta <= m; ++delta) { if (dp[idx][delta]) { add(dp[idx + 1][delta + len], dp[idx][delta]); add(dp[idx + 1][abs(delta - len)], dp[idx][delta]); if (stay) { add(dp[idx + 1][delta], dp[idx][delta]); } } } } void calc_dp(int stay) { fill(dp[0], dp[0] + m + 1, 0); dp[0][0] = 1; for (int i = 0; i < cs; ++i) { update_dp(a[i], i, stay); } } void process() { cs = a.size(); calc_dp(1); for (int i = 0; i <= cs; ++i) { copy(dp[i], dp[i] + m + 1, dpPref[i]); } calc_dp(0); for (int i = 0; i <= cs; ++i) { copy(dp[i], dp[i] + m + 1, dpPrefObl[i]); } reverse(a.begin(), a.end()); calc_dp(1); for (int i = 0; i <= cs; ++i) { copy(dp[i], dp[i] + m + 1, dpSuf[i]); } calc_dp(0); for (int i = 0; i <= cs; ++i) { copy(dp[i], dp[i] + m + 1, dpSufObl[i]); } reverse(a.begin(), a.end()); } int ans; int convert(int val, int pos) { return (pos == 0 ? val : mul(val, _2)); } int merge(int pos, int sum) { int res = 0; for (int delta1 = -m; delta1 <= m; ++delta1) { int delta2 = sum - delta1; if (abs(delta2) <= m) { add(res, mul(convert(dpPref[pos][abs(delta1)], delta1), convert(dpSuf[cs - 1 - pos][abs(delta2)], delta2))); } } return res; } int merge_obl(int pos, int sum) { int res = 0; for (int delta1 = -m; delta1 <= m; ++delta1) { int delta2 = sum - delta1; if (abs(delta2) <= m) { add(res, mul(convert(dpPrefObl[pos][abs(delta1)], delta1), convert(dpSufObl[cs - 1 - pos][abs(delta2)], delta2))); } } return res; } void mergeAns() { add(ans, dpPrefObl[cs][0]); for (int i = 0; i < cs; ++i) { add(ans, mul(merge_obl(i, a[i] - 1), 4)); for (int diff = 2 - a[i]; diff <= a[i] - 2; ++diff) { add(ans, mul(merge(i, diff), 2)); } } } signed main() { fast_io(); read(); find_cycles(); process(); mergeAns(); cout << ans << n ; }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the select of a bit from a vector.
*/
module main;
reg [3:0] a = 4'b0110;
reg [1:0] s = 0;
wire b = a[s];
initial begin
#1 if (b !== 0) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
s = 1;
#1 if (b !== 1) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
s = 2;
#1 if (b !== 1) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
s = 3;
#1 if (b !== 0) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
s = 2'bxx;
#1 if (b !== 1'bx) begin
$display("FAILED -- a=%b, s=%b, b=%b", a, s, b);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; bool vis[500009]; int siz[500009]; int rr[1005][1005]; char arr[1005][1005]; vector<int> d; int n; void dfs(int x, int y, int cn) { if (x > n or y > n or x < 1 or y < 1 or rr[x][y] != 0) return; rr[x][y] = cn; siz[cn]++; if (arr[x + 1][y] == . ) dfs(x + 1, y, cn); if (arr[x][y + 1] == . ) dfs(x, y + 1, cn); if (arr[x - 1][y] == . ) dfs(x - 1, y, cn); if (arr[x][y - 1] == . ) dfs(x, y - 1, cn); } void rem(int i, int j, int k) { for (int t = i; t < i + k; t++) { if (arr[t][j] == . ) siz[rr[t][j]]--; } } int count(int i, int j, int k) { vector<int> v; int e, ans = 0; for (int y = i; y < i + k && j - 1 >= 1; y++) { e = rr[y][j - 1]; if (!vis[e] && e) { v.push_back(e); vis[e] = 1; ans += siz[e]; } } for (int y = j; y < j + k && i - 1 >= 1; y++) { e = rr[i - 1][y]; if (!vis[e] && e) { v.push_back(e); vis[e] = 1; ans += siz[e]; } } for (int y = i; y < i + k && j + k <= n; y++) { e = rr[y][j + k]; if (!vis[e] && e) { v.push_back(e); vis[e] = 1; ans += siz[e]; } } for (int y = j; y < j + k && i + k <= n; y++) { e = rr[i + k][y]; if (!vis[e] && e) { v.push_back(e); vis[e] = 1; ans += siz[e]; } } for (int i = 0; i < v.size(); i++) { vis[v[i]] = 0; } return ans; } void add(int i, int j, int k) { for (int t = i; t < i + k; t++) { if (arr[t][j] == . ) siz[rr[t][j]]++; } } int main() { int k, e = 0, a = 0; cin >> n >> k; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cin >> arr[i][j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (arr[i][j] == . && rr[i][j] == 0) dfs(i, j, ++e); } } for (int i = 1; i <= n - k + 1; i++) { for (int y = 1; y <= k; y++) { rem(i, y, k); } a = count(i, 1, k); d.push_back(a); int last = 1; for (int j = 2; j <= n - k + 1; j++) { rem(i, j + k - 1, k); add(i, j - 1, k); last = j; a = count(i, j, k); d.push_back(a); } for (int y = last; y <= n; y++) { add(i, y, k); } } sort(d.begin(), d.end()); cout << d[d.size() - 1] + (k * k) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_1_V
`define SKY130_FD_SC_HD__EINVN_1_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_1_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// ROM ////
//// ////
//// Author(s): ////
//// - Michael Unneback () ////
//// - Julius Baxter () ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module rom
#(parameter addr_width = 5,
parameter b3_burst = 0)
(
input wb_clk,
input wb_rst,
input [(addr_width+2)-1:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o);
reg [addr_width-1:0] adr;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o <= 32'h15000000;
else
case (adr)
// Zero r0 and jump to 0x00000100
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
default:
wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
generate
if(b3_burst) begin : gen_b3_burst
reg wb_stb_i_r;
reg new_access_r;
reg burst_r;
wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
wire new_access = (wb_stb_i & !wb_stb_i_r);
wire new_burst = (burst & !burst_r);
always @(posedge wb_clk) begin
new_access_r <= new_access;
burst_r <= burst;
wb_stb_i_r <= wb_stb_i;
end
always @(posedge wb_clk)
if (wb_rst)
adr <= 0;
else if (new_access)
// New access, register address, ack a cycle later
adr <= wb_adr_i[(addr_width+2)-1:2];
else if (burst) begin
if (wb_cti_i == 3'b010)
case (wb_bte_i)
2'b00: adr <= adr + 1;
2'b01: adr[1:0] <= adr[1:0] + 1;
2'b10: adr[2:0] <= adr[2:0] + 1;
2'b11: adr[3:0] <= adr[3:0] + 1;
endcase // case (wb_bte_i)
else
adr <= wb_adr_i[(addr_width+2)-1:2];
end // if (burst)
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
wb_ack_o <= 0;
else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r)))
wb_ack_o <= 1;
else
wb_ack_o <= 0;
end else begin
always @(wb_adr_i)
adr <= wb_adr_i;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; vector<long long> v; long long h = 1, m; while (h <= 25820) { m = ((3 * h + 1) * h) / 2; v.push_back(m); h++; } for (long long j = 0; j < t; j++) { long long n, pos = 0; cin >> n; for (long long i = 0; i < v.size(); i++) { if (n <= v[i]) { pos = i; break; } } long long ans = 0; while (n > 0 && pos >= 0) { ans += (n / v[pos]); n %= v[pos]; pos--; } cout << ans << n ; } return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_b_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:26:55 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_b_e.v,v 1.1 2006/04/10 15:42:10 wig Exp $
// $Date: 2006/04/10 15:42:10 $
// $Log: inst_b_e.v,v $
// Revision 1.1 2006/04/10 15:42:10 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_b_e
//
// No user `defines in this module
module inst_b_e
//
// Generated module inst_b
//
(
port_b_1
);
// Generated Module Inputs:
input port_b_1;
// Generated Wires:
wire port_b_1;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of inst_b_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; int par[N], ran[N]; struct DSU { DSU() { for (int i = 1; i < N; ++i) par[i] = i, ran[i] = 1; } int find(int x) { return par[x] == x ? x : par[x] = find(par[x]); } bool unite(int a, int b) { a = find(a), b = find(b); if (a == b) return false; ran[a] += ran[a] == ran[b]; if (ran[a] < ran[b]) swap(a, b); par[b] = a; return true; } }; int a[N]; int n, q; vector<int> primes; int spf[N]; void sieve() { for (int i = 2; i < N; ++i) { if (spf[i] == 0) spf[i] = i, primes.push_back(i); int sz = primes.size(); for (int j = 0; j < sz && i * primes[j] < N && primes[j] <= spf[i]; ++j) { spf[i * primes[j]] = primes[j]; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); sieve(); cin >> n >> q; DSU ds; for (int i = 1; i <= n; ++i) { cin >> a[i]; } for (int i = 1; i <= n; ++i) { int x = a[i]; while (x > 1) { ds.unite(spf[a[i]], spf[x]); x /= spf[x]; } } set<pair<int, int>> pary; for (int i = 1; i <= n; ++i) { int x = a[i]; vector<int> v; while (x > 1) { v.push_back(spf[x]); x /= spf[x]; } x = a[i] + 1; while (x > 1) { v.push_back(spf[x]); x /= spf[x]; } v.resize(unique(v.begin(), v.end()) - v.begin()); for (auto &j : v) { j = ds.find(j); } for (auto j : v) { for (auto k : v) { if (j < k) pary.insert({j, k}); } } } while (q--) { int x, y; cin >> x >> y; x = spf[a[x]], y = spf[a[y]]; if (ds.find(x) == ds.find(y)) cout << 0 << endl; else { x = ds.find(x); y = ds.find(y); if (x > y) swap(x, y); if (pary.count({x, y})) cout << 1 << endl; else cout << 2 << endl; } } }
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#include <bits/stdc++.h> using namespace std; const long long INF = 1LL << 60; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int lcm(int a, int b) { return a * b / gcd(a, b); } const int N = 2e5 + 5; int v[N], in[N]; vector<int> e[N]; bool cmp(int a, int b) { return in[a] < in[b]; } void solve() { int n; cin >> n; for (auto &li : e) li.clear(); for (int i = (0); i < (n - 1); ++i) { int x, y; cin >> x >> y; x--, y--; e[x].push_back(y); e[y].push_back(x); } vector<int> ch, gen; for (int i = (0); i < (n); ++i) { v[i] = 0; int z; cin >> z; in[--z] = i; ch.push_back(z); } for (int i = (0); i < (n); ++i) sort((e[i]).begin(), (e[i]).end(), cmp); queue<int> q; q.push(0); v[0] = 1; while (!q.empty()) { int t = q.front(); q.pop(); gen.push_back(t); for (auto to : e[t]) { if (v[to]) continue; v[to] = 1; q.push(to); } } for (int i = (0); i < (n); ++i) if (gen[i] != ch[i]) { puts( No ); return; } puts( Yes ); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int a[4010][4010]; int n, m; int u[4010], v[4010], sz[4010]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &u[i], &v[i]); a[u[i]][v[i]] = a[v[i]][u[i]] = 1; sz[u[i]]++; sz[v[i]]++; } int ans = 1e9; for (int i = 1; i <= m; i++) { int x = u[i], y = v[i]; for (int j = i + 1; j <= m; j++) { int c = u[j], d = v[j]; if (x == c && a[y][d] == 1) { ans = min(ans, sz[x] + sz[y] + sz[d] - 6); } else if (x == d && a[y][c] == 1) { ans = min(ans, sz[x] + sz[c] + sz[y] - 6); } else if (y == c && a[x][d] == 1) { ans = min(ans, sz[y] + sz[x] + sz[d] - 6); } else if (y == d && a[x][c] == 1) { ans = min(ans, sz[y] + sz[x] + sz[c] - 6); } } } if (ans == 1e9) cout << -1 << endl; else cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; vector<int> a[1111]; queue<int> p; int ji[1111], f = 1, b[1111], c[1111]; void dfs(int p) { ji[p]++; for (int i = 0; i < a[p].size(); i++) { if (ji[a[p][i]] >= 3) { f = 0; return; } dfs(a[p][i]); } } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); a[x].push_back(y); b[y]++; c[x]++; c[y]++; } int h = 0; for (int i = 1; i <= n; i++) { if (!b[i] && c[i]) { p.push(i); ji[i]++; h++; } } while (!p.empty()) { int k = p.front(); p.pop(); ji[k]++; for (int i = 0; i < a[k].size(); i++) { int x = a[k][i]; b[x]--; if (!b[x] && !ji[x]) { p.push(x); h++; ji[x]++; } } } if (h == n) printf( yes n ); else printf( no n ); return 0; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_dest_fifo_inf (
input clk,
input resetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input en,
output [C_DATA_WIDTH-1:0] dout,
output valid,
output underflow,
output xfer_req,
output fifo_ready,
input fifo_valid,
input [C_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
assign sync_id_ret = sync_id;
wire data_enabled;
wire _fifo_ready;
assign fifo_ready = _fifo_ready | ~enabled;
reg en_d1;
wire data_ready;
wire data_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
en_d1 <= 1'b0;
end else begin
en_d1 <= en;
end
end
assign underflow = en_d1 & (~data_valid | ~enable);
assign data_ready = en_d1 & (data_valid | ~enable);
assign valid = en_d1 & data_valid & enable;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data),
.m_axi_ready(data_ready),
.m_axi_valid(data_valid),
.m_axi_data(dout),
.m_axi_last()
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_generator (
.clk(clk),
.resetn(resetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_BLACKBOX_V
`define SKY130_FD_SC_LS__MUX2_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_BLACKBOX_V
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#include<cstdio> #include<vector> #include<map> #include<set> #include<algorithm> #include<cstdlib> #include<cstring> #include<cmath> #include<string> #include<deque> #include<queue> using namespace std; #define db double #define ll long long int T; struct node{ ll x,y; }p[10]; int u[10], u2[10]; ll x[10],y[10],s[10], u3[10]; ll ans; void c1(ll px, ll py) { ll now = 0; now += abs(px - x[u2[1]]) + abs(py - y[u2[1]]); now += abs(px - x[u2[3]]); now += abs(py - y[u2[2]]); s[1] = u3[1] * (x[u2[2]] - px); s[2] = u3[2] * (y[u2[3]] - py); s[3] = u3[3] * (x[u2[4]] - px); s[4] = u3[4] * (y[u2[4]] - py); sort(s+1, s+5); for(int i=1; i<=4; i++) now+=abs(s[i] - s[2]); // if (now==4){ // printf( %lld %lld n , px, py); // for(int i=1; i<=4; i++) printf( %d ,u2[i]); // printf( n ); // for(int i=1; i<=4; i++) printf( %lld %lld n , x[i], y[i]); // printf( n ); // } ans = min(ans, now); } int main() { scanf( %d ,&T); for(;T--;) { int n = 4; ans = 0; for(int i=1; i<=n; i++) { scanf( %lld %lld ,&p[i].x, &p[i].y); ans += p[i].x + p[i].y; u[i] = i; } for(;1;) { for(int i=1; i<=n; i++) x[i] = p[u[i]].x, y[i] = p[u[i]].y; for(int i=1; i<=n; i++) u2[i] = i, u3[i] = 1; c1(x[1], y[1]); c1(x[1], y[2]); c1(x[3], y[1]); c1(x[3], y[2]); u2[1] = 2; u2[2] = 1; u2[3] = 4; u2[4] = 3; u3[1] = u3[3] = -1; c1(x[2], y[1]); c1(x[2], y[2]); c1(x[4], y[1]); c1(x[4], y[2]); u2[1] = 3; u2[2] = 4; u2[3] = 1; u2[4] = 2; u3[1] = 1; u3[2] = -1; u3[3] = 1; u3[4] = -1; c1(x[1], y[3]); c1(x[1], y[4]); c1(x[3], y[3]); c1(x[3], y[4]); u2[1] = 4; u2[2] = 3; u2[3] = 2; u2[4] = 1; u3[1] = u3[3] = -1; u3[2] = u3[4] = -1; c1(x[2], y[3]); c1(x[2], y[4]); c1(x[4], y[3]); c1(x[4], y[4]); if (!next_permutation(u+1, u+1+n)) break; } printf( %lld n , ans); } return 0; }
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// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; const int MAXN = 405; char G[405][405], P[405][405]; bitset<MAXN> nolet[405][27]; int main() { int N, M; scanf( %d%d , &N, &M); for (int i = 0; i < N; ++i) { scanf( %s , G[i]); for (int c = 0; c < 26; ++c) for (int j = 0; j < M; ++j) if (G[i][j] - a != c) nolet[i][c].set(j); } int R, C; scanf( %d%d , &R, &C); for (int i = 0; i < R; ++i) { scanf( %s , P[i]); } for (int i = 0; i < N; ++i) { bitset<MAXN> no; for (int r = 0; r < R; ++r) for (int c = 0; c < C; ++c) { if (P[r][c] == ? ) continue; int ii = (i + r) % N; auto b = nolet[ii][P[r][c] - a ]; no |= (b >> c) | (b << (M - c)); } for (int j = 0; j < M; ++j) printf( %d , !no[j]); printf( n ); } }
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#include <bits/stdc++.h> using namespace std; template <int M> struct static_mint { static_assert(0 < M, Module must be positive ); int val; static_mint() : val() {} static_mint(long long x) : val(x % M) { if (val < 0) val += M; } static_mint pow(long long n) const { static_mint ans = 1, x(*this); while (n) { if (n & 1) ans *= x; x *= x; n /= 2; } return ans; } static_mint inv() const { return pow(M - 2); } friend static_mint pow(const static_mint &m, long long n) { return m.pow(n); } friend static_mint inv(const static_mint &m) { return m.inv(); } static_mint operator+() const { static_mint m; m.val = val; return m; } static_mint operator-() const { static_mint m; m.val = M - val; return m; } static_mint &operator+=(const static_mint &m) { if ((val += m.val) >= M) val -= M; return *this; } static_mint &operator-=(const static_mint &m) { if ((val -= m.val) < 0) val += M; return *this; } static_mint &operator*=(const static_mint &m) { val = (long long)val * m.val % M; return *this; } static_mint &operator/=(const static_mint &m) { val = (long long)val * m.inv().val % M; return *this; } friend static_mint operator+(const static_mint &lhs, const static_mint &rhs) { return static_mint(lhs) += rhs; } friend static_mint operator-(const static_mint &lhs, const static_mint &rhs) { return static_mint(lhs) -= rhs; } friend static_mint operator*(const static_mint &lhs, const static_mint &rhs) { return static_mint(lhs) *= rhs; } friend static_mint operator/(const static_mint &lhs, const static_mint &rhs) { return static_mint(lhs) /= rhs; } friend bool operator==(const static_mint &lhs, const static_mint &rhs) { return lhs.val == rhs.val; } friend bool operator!=(const static_mint &lhs, const static_mint &rhs) { return lhs.val != rhs.val; } static_mint &operator++() { return *this += 1; } static_mint &operator--() { return *this -= 1; } static_mint operator++(int) { static_mint result(*this); *this += 1; return result; } static_mint operator--(int) { static_mint result(*this); *this -= 1; return result; } template <typename T> explicit operator T() const { return T(val); } friend std::ostream &operator<<(std::ostream &os, const static_mint &m) { return os << m.val; } friend std::istream &operator>>(std::istream &is, static_mint &m) { long long x; is >> x; m = x; return is; } }; template <typename> struct is_mint : public std::false_type {}; template <int M> struct is_mint<static_mint<M>> : public std::true_type {}; template <typename T> struct matrix : std::vector<std::vector<T>> { int n, m; matrix() : n(), m() {} matrix(int n, int m, const T val = T()) : n(n), m(m), std::vector<std::vector<T>>(n, std::vector<T>(m, val)) {} matrix(std::initializer_list<std::vector<T>> l) : std::vector<std::vector<T>>(l) { n = l.size(); if (l.size()) { m = l.begin()->size(); } } matrix &operator+=(const matrix &mat) { assert(n == mat.n && m == mat.m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { (*this)[i][j] += mat[i][j]; } } return *this; } matrix &operator-=(const matrix &mat) { assert(n == mat.n && m == mat.m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { (*this)[i][j] -= mat[i][j]; } } return *this; } matrix &operator*=(const matrix &mat) { assert(m == mat.n); matrix res(n, mat.m); for (int i = 0; i < n; i++) { for (int j = 0; j < mat.m; j++) { for (int k = 0; k < m; k++) { res[i][j] += (*this)[i][k] * mat[k][j]; } } } this->swap(res); return *this; } matrix &operator*=(const T &val) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { (*this)[i][j] *= val; } } return *this; } friend matrix operator+(matrix a, const matrix &b) { a += b; return a; } friend matrix operator-(matrix a, const matrix &b) { a -= b; return a; } friend matrix operator*(matrix a, const matrix &b) { a *= b; return a; } friend matrix operator*(matrix a, const T &val) { a *= val; return a; } friend matrix operator*(const T &val, matrix a) { a *= val; return a; } }; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); using mint = static_mint<1000000007>; int n, x; cin >> n >> x; vector<int> cnt(101); for (int i = 0, d; i < n; i++) { cin >> d, cnt[d] += 1; } matrix<mint> m(101, 101); m[0][0] = 1 + cnt[1]; for (int i = 1; i < 100; i++) { m[i][0] = cnt[i + 1] - cnt[i]; } m[100][0] = -cnt[100]; for (int j = 1; j < 101; j++) { m[j - 1][j] = 1; } matrix<mint> ans(101, 101); for (int i = 0; i < 101; i++) ans[0][0] = 1; for (; x; x /= 2) { if (x & 1) ans *= m; m *= m; } cout << ans[0][0] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; inline void output(long long int x) { if (x % 2) cout << x / 2 << n ; else cout << x / 2 - 1 << n ; return; } long long int N, K; int main() { cin >> N >> K; if (N >= K) output(K); else { if ((N << 1) - 1 < K) cout << 0 << n ; else output(N - (K - N) + 2); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t;
wire d1 = 1'b1;
wire d2 = 1'b1;
wire d3 = 1'b1;
wire o1,o2,o3;
add1 add1 (d1,o1);
add2 add2 (d2,o2);
`define ls left_side
`define rs right_side
`define noarg na//note extra space
`define thru(x) x
`define thruthru `ls `rs // Doesn't expand
`define msg(x,y) `"x: `\`"y`\`"`"
`define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string
initial begin
//$display(`msg( \`, \`)); // Illegal
$display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side));
$display(`msg(left side,right side));
$display(`msg( left side , right side ));
$display(`msg( `ls , `rs ));
$display(`msg( `noarg , `rs ));
$display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs ));
$display(`msg(`noarg,`noarg`noarg));
$display(`msg( `thruthru , `thruthru )); // Results vary between simulators
$display(`left(`msg( left side , right side ), left_replaced));
//$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error
`ifndef VCS // Sim bug - wrong number of arguments, but we're right
$display(`msg(`thru(),)); // Empty
`endif
$display(`msg(`thru(left side),`thru(right side)));
$display(`msg( `thru( left side ) , `thru( right side ) ));
`ifndef NC
$display(`"standalone`");
`endif
`ifdef VERILATOR
// Illegal on some simulators, as the "..." crosses two lines
`define twoline first \
second
$display(`msg(twoline, `twoline));
`endif
$display("Line %0d File \"%s\"",`__LINE__,`__FILE__);
//$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define ADD_UP(a,c) \
wire tmp_``a = a; \
wire tmp_``c = tmp_``a + 1; \
assign c = tmp_``c ;
module add1 ( input wire d1, output wire o1);
`ADD_UP(d1,o1) // expansion is OK
endmodule
module add2 ( input wire d2, output wire o2);
`ADD_UP( d2 , o2 ) // expansion is bad
endmodule
// `ADD_UP( \d3 , \o3 ) // This really is illegal
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module test_bench(clk, rst);
input clk;
input rst;
wire [63:0] wire_39069600;
wire wire_39069600_stb;
wire wire_39069600_ack;
wire [63:0] wire_39795024;
wire wire_39795024_stb;
wire wire_39795024_ack;
wire [63:0] wire_39795168;
wire wire_39795168_stb;
wire wire_39795168_ack;
file_reader_a file_reader_a_39796104(
.clk(clk),
.rst(rst),
.output_z(wire_39069600),
.output_z_stb(wire_39069600_stb),
.output_z_ack(wire_39069600_ack));
file_reader_b file_reader_b_39759816(
.clk(clk),
.rst(rst),
.output_z(wire_39795024),
.output_z_stb(wire_39795024_stb),
.output_z_ack(wire_39795024_ack));
file_writer file_writer_39028208(
.clk(clk),
.rst(rst),
.input_a(wire_39795168),
.input_a_stb(wire_39795168_stb),
.input_a_ack(wire_39795168_ack));
double_divider divider_39759952(
.clk(clk),
.rst(rst),
.input_a(wire_39069600),
.input_a_stb(wire_39069600_stb),
.input_a_ack(wire_39069600_ack),
.input_b(wire_39795024),
.input_b_stb(wire_39795024_stb),
.input_b_ack(wire_39795024_ack),
.output_z(wire_39795168),
.output_z_stb(wire_39795168_stb),
.output_z_ack(wire_39795168_ack));
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// AXI4MasterInterface for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: AXI4 master interface
// Module Name: AXI4MasterInterface
// File Name: AXI4MasterInterface.v
//
// Version: v1.0.0
//
// Description: AXI4 compliant master interface supporting transaction division
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module AXI4MasterInterface
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter MaxDivider = 16
)
(
ACLK ,
ARESETN ,
M_AWADDR ,
M_AWLEN ,
M_AWSIZE ,
M_AWBURST ,
M_AWCACHE ,
M_AWPROT ,
M_AWVALID ,
M_AWREADY ,
M_WDATA ,
M_WSTRB ,
M_WLAST ,
M_WVALID ,
M_WREADY ,
M_BRESP ,
M_BVALID ,
M_BREADY ,
M_ARADDR ,
M_ARLEN ,
M_ARSIZE ,
M_ARBURST ,
M_ARCACHE ,
M_ARPROT ,
M_ARVALID ,
M_ARREADY ,
M_RDATA ,
M_RRESP ,
M_RLAST ,
M_RVALID ,
M_RREADY ,
iWriteAddress ,
iWriteBeats ,
iWriteCommandReq ,
oWriteCommandAck ,
iWriteData ,
iWriteLast ,
iWriteValid ,
oWriteReady ,
iReadAddress ,
iReadBeats ,
iReadCommandReq ,
oReadCommandAck ,
oReadData ,
oReadLast ,
oReadValid ,
iReadReady
);
input ACLK ;
input ARESETN ;
// AXI4 Interface
output [AddressWidth - 1:0] M_AWADDR ;
output [7:0] M_AWLEN ;
output [2:0] M_AWSIZE ;
output [1:0] M_AWBURST ;
output [3:0] M_AWCACHE ;
output [2:0] M_AWPROT ;
output M_AWVALID ;
input M_AWREADY ;
output [DataWidth - 1:0] M_WDATA ;
output [(DataWidth/8) - 1:0] M_WSTRB ;
output M_WLAST ;
output M_WVALID ;
input M_WREADY ;
input [1:0] M_BRESP ;
input M_BVALID ;
output M_BREADY ;
output [AddressWidth - 1:0] M_ARADDR ;
output [7:0] M_ARLEN ;
output [2:0] M_ARSIZE ;
output [1:0] M_ARBURST ;
output [3:0] M_ARCACHE ;
output [2:0] M_ARPROT ;
output M_ARVALID ;
input M_ARREADY ;
input [DataWidth - 1:0] M_RDATA ;
input [1:0] M_RRESP ;
input M_RLAST ;
input M_RVALID ;
output M_RREADY ;
// Inner AXI-like Interface
input [AddressWidth - 1:0] iWriteAddress ;
input [InnerIFLengthWidth - 1:0] iWriteBeats ;
input iWriteCommandReq;
output oWriteCommandAck;
input [DataWidth - 1:0] iWriteData ;
input iWriteLast ;
input iWriteValid ;
output oWriteReady ;
;
input [AddressWidth - 1:0] iReadAddress ;
input [InnerIFLengthWidth - 1:0] iReadBeats ;
input iReadCommandReq ;
output oReadCommandAck ;
output [DataWidth - 1:0] oReadData ;
output oReadLast ;
output oReadValid ;
input iReadReady ;
AXI4MasterInterfaceWriteChannel
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth ),
.InnerIFLengthWidth (InnerIFLengthWidth ),
.MaxDivider (MaxDivider )
)
Inst_AXI4MasterInterfaceWriteChannel
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.OUTER_AWADDR (M_AWADDR ),
.OUTER_AWLEN (M_AWLEN ),
.OUTER_AWSIZE (M_AWSIZE ),
.OUTER_AWBURST (M_AWBURST ),
.OUTER_AWCACHE (M_AWCACHE ),
.OUTER_AWPROT (M_AWPROT ),
.OUTER_AWVALID (M_AWVALID ),
.OUTER_AWREADY (M_AWREADY ),
.OUTER_WDATA (M_WDATA ),
.OUTER_WSTRB (M_WSTRB ),
.OUTER_WLAST (M_WLAST ),
.OUTER_WVALID (M_WVALID ),
.OUTER_WREADY (M_WREADY ),
.OUTER_BRESP (M_BRESP ),
.OUTER_BVALID (M_BVALID ),
.OUTER_BREADY (M_BREADY ),
.INNER_AWADDR (iWriteAddress ),
.INNER_AWLEN (iWriteBeats ),
.INNER_AWVALID (iWriteCommandReq ),
.INNER_AWREADY (oWriteCommandAck ),
.INNER_WDATA (iWriteData ),
.INNER_WLAST (iWriteLast ),
.INNER_WVALID (iWriteValid ),
.INNER_WREADY (oWriteReady )
);
AXI4MasterInterfaceReadChannel
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth ),
.InnerIFLengthWidth (InnerIFLengthWidth ),
.MaxDivider (MaxDivider )
)
Inst_AXI4MasterInterfaceReadChannel
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.OUTER_ARADDR (M_ARADDR ),
.OUTER_ARLEN (M_ARLEN ),
.OUTER_ARSIZE (M_ARSIZE ),
.OUTER_ARBURST (M_ARBURST ),
.OUTER_ARCACHE (M_ARCACHE ),
.OUTER_ARPROT (M_ARPROT ),
.OUTER_ARVALID (M_ARVALID ),
.OUTER_ARREADY (M_ARREADY ),
.OUTER_RDATA (M_RDATA ),
.OUTER_RRESP (M_RRESP ),
.OUTER_RLAST (M_RLAST ),
.OUTER_RVALID (M_RVALID ),
.OUTER_RREADY (M_RREADY ),
.INNER_ARADDR (iReadAddress ),
.INNER_ARLEN (iReadBeats ),
.INNER_ARVALID (iReadCommandReq),
.INNER_ARREADY (oReadCommandAck),
.INNER_RDATA (oReadData ),
.INNER_RLAST (oReadLast ),
.INNER_RVALID (oReadValid ),
.INNER_RREADY (iReadReady )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_SYMBOL_V
`define SKY130_FD_SC_HD__NAND3B_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void solve() { long long h, w; cin >> h >> w; long long pow2max = 1; while (2 * pow2max <= h && 2 * pow2max <= w) pow2max *= 2; long long hmax = min(h, (long long)(1.25 * pow2max)); long long wmax = min(w, (long long)(1.25 * pow2max)); if (hmax >= wmax) cout << hmax << << pow2max; else cout << pow2max << << wmax; return; } signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long t = 1; while (t--) { solve(); } return 0; }
|
// Copyright (c) 2015 Kareem Matariyeh
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Creator: Kareem Matariyeh (asm2750)
//
// Create Date: 20:01:49 01/04/2015
// Design Name: neopixel_tx
// Module Name: neopixel_tx
// Project Name: neopixel (ws2812) transmitter
// Target Devices: Any device able to fit design at timing requirements
// Tool versions: Any tool able to synthesize design
// Description: Top level module containing a pair of (2^10) - 1 FIFOs and
// a neopixel transmitter.
//
// Dependencies: None.
//
// Revision:
// Revision 1.00 - Design Implmented and working on Spartan 6 XC6SLX6
// Additional Comments:
// Things to finish: Support xilinx and altera block memories, fork and add SPI
// interface.
//
//////////////////////////////////////////////////////////////////////////////////
module neopixel_tx(
input wire clk_20MHz_i, // 20 MHz clock input
input wire neo_rst_i, // reset input (active low)
input wire neo_mode_i, // output speed select pin
input wire neo_tx_enable_i, // transmitter enable pin
input wire neo_msgTyp_i, // message type fifo input
input wire [23:0] neo_rgb_i, // rgb data fifo input
input wire wr_en_i, // fifo write strobe
output wire fifo_full_flg_o, // fifo full flag output
output wire fifo_empty_flg_o, // fifo empty flag output
output wire neopixel_tx_o // neopixel protocol output
);
// connectors between FIFOs and TX_FSM
wire neoClk;
wire neo_msgTyp;
wire [23:0] neo_rgb;
wire neo_rdEn;
wire cmd_empty_flg;
wire cmd_full_flg;
wire rgb_empty_flg;
wire rgb_full_flg;
// data FIFO (1024*3 - 1 bytes)
FIFO_WxD #(
24,
10)
neo_rgbFIFO (
.rst(neo_rst_i),
.dataIn(neo_rgb_i),
.wr_en(wr_en_i),
.rd_en(neo_rdEn),
.dataOut(neo_rgb),
.full_flg(rgb_full_flg),
.empty_flg(rgb_empty_flg)
);
// command bit FIFO (31 bits)
FIFO_WxD #(
1,
10)
neo_cmdFIFO (
.rst(neo_rst_i),
.dataIn(neo_msgTyp_i),
.wr_en(wr_en_i),
.rd_en(neo_rdEn),
.dataOut(neo_msgTyp),
.full_flg(cmd_full_flg),
.empty_flg(cmd_empty_flg)
);
// Neopixel Transmitter
neopixel_tx_fsm neo_tx(
.clk(clk_20MHz_i),
.rst(neo_rst_i),
.mode(neo_mode_i),
.tx_enable(neo_tx_enable_i),
.empty_flg(fifo_empty_flg_o),
.neo_dIn(neo_rgb),
.rgb_msgTyp(neo_msgTyp),
.rd_next(neo_rdEn),
.neo_tx_out(neopixel_tx_o)
);
// combine the fifo flags
assign fifo_empty_flg_o = cmd_empty_flg | rgb_empty_flg;
assign fifo_full_flg_o = cmd_full_flg | rgb_full_flg;
endmodule
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#include <bits/stdc++.h> using namespace std; using Real = long double; Real g_err = 1e-9; bool r_eq(Real x, Real y, Real err = g_err) { return abs(x - y) <= err || abs(x - y) <= abs(x) * err; } bool r_le(Real x, Real y, Real err = g_err) { return x - y <= err || x - y <= abs(x) * err; } bool r_ge(Real x, Real y, Real err = g_err) { return r_le(y, x, err); } bool r_gt(Real x, Real y, Real err = g_err) { return !r_le(x, y, err); } bool r_lt(Real x, Real y, Real err = g_err) { return !r_le(y, x, err); } bool r_ne(Real x, Real y, Real err = g_err) { return !r_eq(x, y, err); } bool rp_eq(Real x, Real y, Real err = g_err) { return abs(x - y) <= err; } bool rp_le(Real x, Real y, Real err = g_err) { return x - y <= err; } bool rp_ge(Real x, Real y, Real err = g_err) { return rp_le(y, x, err); } bool rp_gt(Real x, Real y, Real err = g_err) { return !rp_le(x, y, err); } bool rp_lt(Real x, Real y, Real err = g_err) { return !rp_le(y, x, err); } bool rp_ne(Real x, Real y, Real err = g_err) { return !rp_eq(x, y, err); } template <typename T> bool updMax(T& tmax, const T& x) { if (x > tmax) { tmax = x; return true; } else { return false; } } template <typename T> bool updMin(T& tmin, const T& x) { if (x < tmin) { tmin = x; return true; } else { return false; } } struct Point { Real x; Real y; Point() : x(0), y(0) {} Point(Real x_, Real y_) : x(x_), y(y_) {} bool operator==(const Point& p) const { return x == p.x && y == p.y; } bool operator!=(const Point& p) const { return !(*this == p); } bool sim(const Point& p, Real err = g_err) const { return r_eq(x, p.x, err) && r_eq(y, p.y, err); } static bool sim(const Point& p1, const Point& p2, Real err = g_err) { return p1.sim(p2, err); } Point& operator+=(const Point& p) { x += p.x; y += p.y; return *this; } Point& operator-=(const Point& p) { x -= p.x; y -= p.y; return *this; } Point& operator*=(Real k) { x *= k; y *= k; return *this; } Point& operator/=(Real k) { x /= k; y /= k; return *this; } Point operator+(const Point& p) const { return Point(*this) += p; } Point operator-(const Point& p) const { return Point(*this) -= p; } Point operator*(Real k) const { return Point(*this) *= k; } Point operator/(Real k) const { return Point(*this) /= k; } Point operator-() const { return (*this) * (-1); } Real len() const { return hypot(x, y); } static Point polar(Real r, Real th) { return Point(r * cos(th), r * sin(th)); } Point rotate(Real th) const { return polar(len(), atan2(y, x) + th); } Point rotateQ() const { return Point(-y, x); } bool parallel(const Point& p, Real err = g_err) const { return r_eq(x * p.y, y * p.x, err); } Real innerProd(const Point& p) const { return x * p.x + y * p.y; } Real outerProd(const Point& p) const { return x * p.y - y * p.x; } Real arg() const { return atan2(y, x); } Real angle(const Point& p) const { Real th = atan2(p.y, p.x) - atan2(y, x); return th > 3.141592653589793238462643383279502884L ? th - 2 * 3.141592653589793238462643383279502884L : th <= -3.141592653589793238462643383279502884L ? th + 2 * 3.141592653589793238462643383279502884L : th; } }; Point operator*(Real k, const Point& p) { return p * k; } ostream& operator<<(ostream& os, const Point& p) { return os << ( << p.x << , << p.y << ) ; } struct Line; ostream& operator<<(ostream& os, const Line& l); struct Line { Point dir; Point base; static Line x_axis; static Line y_axis; static constexpr int SIDE_ON = 1; static constexpr int SIDE_P = 2; static constexpr int SIDE_N = 4; static constexpr int IST_NONE = -1; static constexpr int IST_ALL = -2; static constexpr int IST_ONE = 0; Line() : dir(0, 0), base(0, 0) {} Line(const Point& d, const Point& b) : dir(d), base(b) {} bool operator==(const Line& l) const { return dir == l.dir && base == l.base; } bool operator!=(const Line& l) const { return !(*this == l); } bool sim(const Line& l1, Real err = g_err) const { return dir.sim(l1.dir, err) && dir.sim(l1.base - base, err); } static bool sim(const Line& l1, const Line& l2, Real err = g_err) { return l1.sim(l2, err); } static Line connect(const Point& p1, const Point& p2) { return Line(p2 - p1, p1); } bool parallel(const Line& l, Real err = g_err) const { return dir.parallel(l.dir, err); } int ptSide(const Point& p, Real err = g_err) const { Real t1 = dir.y * (p.x - base.x); Real t2 = dir.x * (p.y - base.y); if (r_eq(t1, t2, err)) return SIDE_ON; if (r_lt(t1, t2, err)) return SIDE_P; return SIDE_N; } bool ptOn(const Point& p, Real err = g_err) const { return ptSide(p, err) == SIDE_ON; } tuple<int, Real, Real> intersect_coeff(const Line& l) const { if (dir.parallel(l.dir)) { if (ptOn(l.base)) return make_tuple(IST_ALL, 0, 0); else return make_tuple(IST_NONE, 0, 0); } else { Real d = dir.x * (-l.dir.y) - (-l.dir.x) * dir.y; Point z = l.base - base; Real t1 = ((-l.dir.y) * z.x + l.dir.x * z.y) / d; Real t2 = ((-dir.y) * z.x + dir.x * z.y) / d; return {IST_ONE, t1, t2}; } } Point unsafe_intersect(const Line& l) const { auto [rc, t1, t2] = intersect_coeff(l); assert(rc == IST_ONE); return base + t1 * dir; } Point perpend_foot(const Point& p) const { Real t1 = perpend_foot_coeff(p); return base + t1 * dir; } Real perpend_foot_coeff(const Point& p) const { auto [rc, t1, t2] = intersect_coeff(Line(dir.rotateQ(), p)); return t1; } Real len(const Point& p) const { return (p - perpend_foot(p)).len(); } }; ostream& operator<<(ostream& os, const Line& l) { return os << [d << l.dir << , b << l.base << ) ; } Line Line::x_axis(Point(1, 0), Point(0, 0)); Line Line::y_axis(Point(0, 1), Point(0, 0)); struct Circle { Point c; Real r; Circle() : c(0, 0), r(0) {} Circle(const Point& c_, Real r_) : c(c_), r(r_) {} bool operator==(const Circle& o) const { return c == o.c && r == o.r; } bool operator!=(const Circle& o) const { return !(*this == o); } bool sim(const Circle& o, Real err = g_err) const { return c.sim(o.c, err) && r_eq(r, o.r, err); } static bool sim(const Circle& c1, const Circle& c2, Real err = g_err) { return c1.sim(c2, err); } bool ptOn(const Point& p, Real err = g_err) const { return r_eq((p - c).len(), r, err); } tuple<bool, Point, Point> intersect(const Line& o) const { Point f = o.perpend_foot(c); Real d = (f - c).len(); if (d > r) return make_tuple(false, Point(), Point()); Real t = sqrt(r * r - d * d); Point e = o.dir / o.dir.len(); return make_tuple(true, f + t * e, f - t * e); } tuple<bool, Point, Point> intersect(const Circle& o) const { Real d = (o.c - c).len(); if (d + r < o.r || d + o.r < r || r + o.r < d) { return make_tuple(false, Point(), Point()); } Point v = (o.c - c) / d; Real t = (r * r - o.r * o.r + d * d) / (2 * d); Line l(v.rotateQ(), c + t * v); return intersect(l); } }; ostream& operator<<(ostream& os, const Circle& circ) { return os << [c << circ.c << , << circ.r << ] ; } Point circumcenter(const Point& z1, const Point& z2, const Point& z3) { Line l12((z2 - z1).rotateQ(), (z1 + z2) / 2); Line l23((z3 - z2).rotateQ(), (z2 + z3) / 2); return l12.unsafe_intersect(l23); } vector<Point> convex_hull(const vector<Point>& pts) { vector<Point> spts(pts); int n = pts.size(); if (n == 0) return vector<Point>(); auto sub = [&]() -> vector<Point> { vector<Point> ret; for (int i = 0; i < n; i++) { Point pt = spts.at(i); if (i > 0 && spts.at(i - 1).sim(spts.at(i))) continue; while (true) { int rs = ret.size(); if (rs - 2 < 0) break; Point q0 = ret.at(rs - 2); Point q1 = ret.at(rs - 1); if ((q0 - q1).outerProd(pt - q1) < 0) break; ret.pop_back(); } ret.push_back(pt); } ret.pop_back(); return ret; }; sort(spts.begin(), spts.end(), [](const Point& a, const Point& b) -> bool { if (a.x != b.x) return a.x < b.x; return a.y < b.y; }); auto vec1 = sub(); reverse(spts.begin(), spts.end()); auto vec2 = sub(); vec1.insert(vec1.end(), vec2.begin(), vec2.end()); if (vec1.empty()) return vector<Point>({pts.at(0)}); return vec1; } tuple<Real, int, int> convex_diameter(const vector<Point>& pts) { int n = pts.size(); if (n <= 1) { cerr << diameter is called with <=1 points. n ; exit(1); } auto conn = [&](long long int i, long long int j) -> Point { return pts.at(j % n) - pts.at(i % n); }; auto edge = [&](long long int i) -> Point { return conn(i, i + 1); }; if (n == 2) return make_tuple(conn(0, 1).len(), 0, 1); int k = -1; int m = -1; for (int i = 0, cnt = 0; cnt < 2; i++) { if (edge(i).y <= 0 && edge(i + 1).y > 0) { m = i + 1; cnt++; } if (edge(i).y >= 0 && edge(i + 1).y < 0) { k = i + 1; cnt++; } } Real vmax = 0; int k0 = -1, m0 = -1; bool run_k = true; bool run_m = true; while (run_k || run_m) { if (!run_m || (run_k && edge(k).arg() - (-3.141592653589793238462643383279502884L) <= edge(m).arg())) { if (updMax(vmax, conn(k + 1, m).len())) { k0 = k + 1, m0 = m; } k++; if (edge(k).y > 0) run_k = false; } else { if (updMax(vmax, conn(k, m + 1).len())) { k0 = k, m0 = m + 1; } m++; if (edge(m).y < 0) run_m = false; } } return make_tuple(vmax, k0 % n, m0 % n); } int in_triangle(const Point& pt, const Point& tr0, const Point& tr1, const Point& tr2) { auto chk = [&](const Point& b, const Point& e, const Point& p) -> bool { Point be = e - b; Point bp = p - b; Real r = r_eq(be.x, 0.0) ? bp.y / be.y : bp.x / be.x; return 0.0 <= r && r <= 1.0; }; Line l01 = Line::connect(tr0, tr1); Line l12 = Line::connect(tr1, tr2); Line l20 = Line::connect(tr2, tr0); int side = l01.ptSide(tr2); if (side == Line::SIDE_ON) { if (!l01.ptOn(pt)) return Line::SIDE_N; return chk(tr0, tr1, pt) || chk(tr1, tr2, pt) || chk(tr2, tr0, pt) ? Line::SIDE_ON : Line::SIDE_N; } int other = side ^ (Line::SIDE_P | Line::SIDE_N); if (l01.ptSide(pt) == other || l12.ptSide(pt) == other || l20.ptSide(pt) == other) return Line::SIDE_N; if (l01.ptSide(pt) == Line::SIDE_ON || l12.ptSide(pt) == Line::SIDE_ON || l20.ptSide(pt) == Line::SIDE_ON) return Line::SIDE_ON; return Line::SIDE_P; } template <typename T1, typename T2> ostream& operator<<(ostream& os, const pair<T1, T2>& p) { os << ( << p.first << , << p.second << ) ; return os; } template <typename T1, typename T2, typename T3> ostream& operator<<(ostream& os, const tuple<T1, T2, T3>& t) { os << ( << get<0>(t) << , << get<1>(t) << , << get<2>(t) << ) ; return os; } template <typename T1, typename T2, typename T3, typename T4> ostream& operator<<(ostream& os, const tuple<T1, T2, T3, T4>& t) { os << ( << get<0>(t) << , << get<1>(t) << , << get<2>(t) << , << get<3>(t) << ) ; return os; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { os << [ ; for (auto it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } os << ] ; return os; } template <typename T, typename C> ostream& operator<<(ostream& os, const set<T, C>& v) { os << { ; for (auto it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } os << } ; return os; } template <typename T, typename C> ostream& operator<<(ostream& os, const unordered_set<T, C>& v) { os << { ; for (auto it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } os << } ; return os; } template <typename T, typename C> ostream& operator<<(ostream& os, const multiset<T, C>& v) { os << { ; for (auto it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } os << } ; return os; } template <typename T1, typename T2, typename C> ostream& operator<<(ostream& os, const map<T1, T2, C>& mp) { os << [ ; for (auto it = mp.begin(); it != mp.end(); it++) { if (it != mp.begin()) os << , ; os << it->first << : << it->second; } os << ] ; return os; } template <typename T1, typename T2, typename C> ostream& operator<<(ostream& os, const unordered_map<T1, T2, C>& mp) { os << [ ; for (auto it = mp.begin(); it != mp.end(); it++) { if (it != mp.begin()) os << , ; os << it->first << : << it->second; } os << ] ; return os; } template <typename T, typename T2> ostream& operator<<(ostream& os, const queue<T, T2>& orig) { queue<T, T2> que(orig); bool first = true; os << [ ; while (!que.empty()) { T x = que.front(); que.pop(); if (!first) os << , ; os << x; first = false; } return os << ] ; } template <typename T, typename T2> ostream& operator<<(ostream& os, const deque<T, T2>& orig) { deque<T, T2> que(orig); bool first = true; os << [ ; while (!que.empty()) { T x = que.front(); que.pop_front(); if (!first) os << , ; os << x; first = false; } return os << ] ; } template <typename T, typename T2, typename T3> ostream& operator<<(ostream& os, const priority_queue<T, T2, T3>& orig) { priority_queue<T, T2, T3> pq(orig); bool first = true; os << [ ; while (!pq.empty()) { T x = pq.top(); pq.pop(); if (!first) os << , ; os << x; first = false; } return os << ] ; } template <typename T> ostream& operator<<(ostream& os, const stack<T>& st) { stack<T> tmp(st); os << [ ; bool first = true; while (!tmp.empty()) { T& t = tmp.top(); if (first) first = false; else os << , ; os << t; tmp.pop(); } os << ] ; return os; } ostream& operator<<(ostream& os, int8_t x) { os << (int32_t)x; return os; } template <class... Args> string dbgFormat(const char* fmt, Args... args) { size_t len = snprintf(nullptr, 0, fmt, args...); char buf[len + 1]; snprintf(buf, len + 1, fmt, args...); return string(buf); } template <class Head> void dbgLog(bool with_nl, Head&& head) { cerr << head; if (with_nl) cerr << endl; } template <class Head, class... Tail> void dbgLog(bool with_nl, Head&& head, Tail&&... tail) { cerr << head << ; dbgLog(with_nl, forward<Tail>(tail)...); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout << setprecision(20); long long int n, q; cin >> n >> q; vector<Point> P(n); for (long long int i = 0; i < n; i++) { long long int x, y; cin >> x >> y; P[i] = Point(x, y); } Point g(0, 0); Real tots = 0; for (long long int i = 1; i < n - 1; i++) { Point lg = (P[0] + P[i] + P[i + 1]) / 3.0; Point v0i = P[i] - P[0]; Point v0j = P[i + 1] - P[0]; Real s = abs(v0i.x * v0j.y - v0i.y * v0j.x); tots += s; g += s * lg; } g = g / tots; vector<Real> L(n), Th(n); for (long long int i = 0; i < n; i++) { L[i] = (P[i] - g).len(); Th[i] = (P[0] - g).angle(P[i] - g); }; ; ; Real th0 = (P[0] - g).arg(); ; long long int pinA = 0, pinB = 1; for (long long int _q = 0; _q < q; _q++) { long long int tp; cin >> tp; if (tp == 1) { long long int f, t; cin >> f >> t; f--; t--; if (f == pinA) { pinA = pinB; pinB = t; } else { pinB = t; }; Point e(L[pinA], 0); Point pa = g + e.rotate(th0 + Th[pinA]); g = pa + e.rotate(3 * 3.141592653589793238462643383279502884L / 2); ; th0 += 3.141592653589793238462643383279502884L / 2.0 - (th0 + Th[pinA]); ; } else if (tp == 2) { long long int v; cin >> v; v--; Point e(L[v], 0); Point pv = g + e.rotate(th0 + Th[v]); cout << pv.x << << pv.y << n ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, k, ans = 1, p, temp; cin >> n >> k; if (n == k) { cout << 1; return 0; } if (k == 1) { cout << n; return 0; } long long s, e, m; s = 1, e = (n - 1) / 2; while (s <= e) { m = (s + e) / 2; p = log2((n + 1) / (2 * m + 2)) + 1; temp = 2 * ((1LL << p) - 1) + max(1 + n - (1LL << p) * 2 * m, 0LL); if (temp >= k) { s = m + 1; ans = max(ans, 2 * m); } else e = m - 1; } s = 0, e = (n - 3) / 4; while (s <= e) { m = (s + e) / 2; p = log2((n + 1) / (4 * m + 4)) + 1; temp = 1 + 2 * ((1LL << p) - 1) + max(1 + n - (1LL << (p + 1)) * (2 * m + 1), 0LL); if (temp >= k) { s = m + 1; ans = max(ans, 2 * m + 1); } else e = m - 1; } cout << ans; return 0; }
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`timescale 1 ns / 1 ps
`include "Four_Digit_Seven_Segment_Display_v2_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module Four_Digit_Seven_Segment_Display_v2_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int f(int y) { return y % 400 == 0 ? 2 : y % 100 == 0 ? 1 : y % 4 == 0 ? 2 : 1; } int main() { int n, r = 0, t; scanf( %d , &n); t = f(n); while (r % 7 != 0 || r == 0 || t != f(n)) { r += f(n); n++; } printf( %d n , n); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZE = 8;
integer cnt = 0;
logic [SIZE-1:0] vld_for;
logic vld_if = 1'b0;
logic vld_else = 1'b0;
genvar i;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if (cnt==SIZE) begin : if_cnt_finish
$write("*-* All Finished *-*\n");
$finish;
end : if_cnt_finish
generate
for (i=0; i<SIZE; i=i+1) begin : generate_for
always @ (posedge clk)
if (cnt == i) vld_for[i] <= 1'b1;
end : generate_for
endgenerate
generate
if (SIZE>0) begin : generate_if_if
always @ (posedge clk)
vld_if <= 1'b1;
end : generate_if_if
else begin : generate_if_else
always @ (posedge clk)
vld_else <= 1'b1;
end : generate_if_else
endgenerate
endmodule : t
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; void compute() { long long n; cin >> n; n -= 2; string s[n]; cin >> s[0]; string ans = s[0]; for (long long i = 1; i < n; i++) { cin >> s[i]; if (s[i][0] == ans[ans.size() - 1]) ans.push_back(s[i][1]); else ans += s[i]; } if (ans.size() != n + 2) ans.push_back( a ); cout << ans << endl; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { compute(); } return 0; }
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [14:0] c;
// Output of stage 2
wire [14:0] cx;
// Output of stage 3
wire [3:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [3:0] b;
reg [3:0] r_b;
reg [14:0] e;
reg [14:0] r_e;
// 2nd stage
reg [14:0] r_c;
reg [14:0] rr_e;
reg [3:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [14:0] r_qx;
reg [3:0] rb;
reg clk,reset;
reg [14:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 15'b000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 15'b000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 15'b000001000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 15'b000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 15'b000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 15'b000000010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 15'b000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 15'b000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 15'b000001000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 15'b000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_ad.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ad
//
// No `defines in this module
module ent_ad
//
// Generated module inst_ad
//
(
port_ad_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ad_2;
// Generated Wires:
reg port_ad_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ad
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using ld = long double; using pii = pair<int, int>; using pll = pair<ll, ll>; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, b, d; cin >> n >> b >> d; int cur = 0, cnt = 0; for (int i = 0; i < n; i++) { int a; cin >> a; if (a > b) continue; cur += a; if (cur > d) { cnt++; cur = 0; } } if (cur > d) cnt++; cout << cnt << endl; return 0; }
|
#include<bits/stdc++.h> using namespace std; int main(){ int t; cin>>t; while(t--){ int n; cin>>n; int o=0,e=0; int a; for(int i=0;i<2*n;i++){ cin>>a; if(a%2==0) e++; else o++; } if(o == e) cout<< YES <<endl; else cout<< NO <<endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, M; vector<long long> cards; map<int, vector<int>> m; int sodd = 1, seven = 2; int oddbalance; int nextOdd() { for (int i = sodd;; i += 2) { if (m[i].empty()) { sodd = i + 2; if (i > M) { cout << -1 << endl; exit(0); } return i; } } } int nextEven() { for (int i = seven;; i += 2) { if (m[i].empty()) { seven = i + 2; if (i > M) { cout << -1 << endl; exit(0); } return i; } } } int cnt; int main() { cin >> n >> M; cards.resize(n); for (int i = 0; i < n; i++) { cin >> cards[i]; if (cards[i] % 2) oddbalance++; else oddbalance--; m[cards[i]].push_back(i); } for (auto p : m) { while (p.second.size() > 1) { cnt++; if (p.first % 2 == 1) oddbalance--; else oddbalance++; int pos = p.second.back(); p.second.pop_back(); int val; if (oddbalance > 0) { val = nextEven(); oddbalance--; } else { val = nextOdd(); oddbalance++; } m[val].push_back(pos); cards[pos] = val; } } for (int i = 0; i < n && oddbalance; i++) { if (oddbalance > 0 && cards[i] % 2 == 1) { cnt++; cards[i] = nextEven(); oddbalance -= 2; } else if (oddbalance < 0 && cards[i] % 2 == 0) { cnt++; cards[i] = nextOdd(); oddbalance += 2; } } if (oddbalance != 0) { cout << -1 << endl; exit(0); } cout << cnt << endl; for (int c : cards) { cout << c << ; } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200 * 1000 + 20; int p[N], q[N], n, ans[N], cnt[N], seg[N << 2]; void build(int id = 1, int st = 0, int en = n) { if (en - st == 1) { seg[id] = 1; return; } int mid = st + en >> 1; build(id << 1, st, mid); build(id << 1 | 1, mid, en); seg[id] = seg[id << 1] + seg[id << 1 | 1]; } void update(int idx, int id = 1, int st = 0, int en = n) { if (en - st == 1) { seg[id] = 0; return; } int mid = st + en >> 1; if (idx < mid) update(idx, id << 1, st, mid); else update(idx, id << 1 | 1, mid, en); seg[id] = seg[id << 1] + seg[id << 1 | 1]; } int get(int l, int r, int id = 1, int st = 0, int en = n) { if (l <= st && en <= r) return seg[id]; if (r <= st || en <= l) return 0; int mid = st + en >> 1; return get(l, r, id << 1, st, mid) + get(l, r, id << 1 | 1, mid, en); } int get2(int val, int id = 1, int st = 0, int en = n) { if (en - st == 1) return st; int mid = st + en >> 1; if (val < seg[id << 1]) return get2(val, id << 1, st, mid); else return get2(val - seg[id << 1], id << 1 | 1, mid, en); } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> p[i]; for (int i = 0; i < n; i++) cin >> q[i]; build(); for (int i = 0; i < n; i++) { cnt[n - i - 1] = get(0, p[i]); update(p[i]); } build(); for (int i = 0; i < n; i++) { cnt[n - i - 1] += get(0, q[i]); update(q[i]); } for (int i = 0; i < n; i++) { cnt[i + 1] += cnt[i] / (i + 1); cnt[i] %= i + 1; } build(); for (int i = n - 1; ~i; i--) { ans[n - i - 1] = get2(cnt[i]); update(ans[n - i - 1]); } for (int i = 0; i < n; i++) cout << ans[i] << ; return cout << n , 0; }
|
#include <bits/stdc++.h> using namespace std; int N; long long arr[100020]; long long prefix[100020]; multiset<long long> s; set<int> ded; long long range(int i, int j) { if (i == 0) { return prefix[j]; } else { return prefix[j] - prefix[i - 1]; } } int32_t main() { ios_base::sync_with_stdio(false); if (fopen( cf722c.in , r )) { freopen( cf722c.in , r , stdin); freopen( cf722c.out , w , stdout); } cin >> N; arr[0] = 0; for (int i = 1; i <= N; i++) { cin >> arr[i]; } prefix[0] = arr[0]; for (int i = 1; i <= N + 1; i++) { prefix[i] = prefix[i - 1] + arr[i]; } s.insert(0); s.insert(prefix[N + 1]); ded.insert(0); ded.insert(N + 1); for (int i = 0; i < N; i++) { int x; cin >> x; ded.insert(x); int l = 0, r = 0; auto lt = ded.lower_bound(x); if (lt == ded.begin()) { l = 0; } else { lt--; l = *lt; l++; } auto rt = ded.upper_bound(x); if (rt == ded.end()) { r = N + 1; } else { r = *rt; r--; } s.erase(s.find(range(l, r))); s.insert(range(l, x - 1)); s.insert(range(x + 1, r)); cout << *(s.rbegin()) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void si(T &x) { register int c = getchar(); x = 0; int neg = 0; for (; ((c<48 | c> 57) && c != - ); c = getchar()) ; if (c == - ) { neg = 1; c = getchar(); } for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } if (neg) x = -x; } long long bigmod(long long p, long long e, long long M) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return ret; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long modinverse(long long a, long long M) { return bigmod(a, M - 2, M); } void io() { freopen( /Users/MyMac/Desktop/in.txt , r , stdin); } const int N = 1e6 + 6; long long nxt[N]; const long long MOD = 1e9 + 7; bool vis[N]; void dfs(int u) { if (vis[u]) return; vis[u] = 1; dfs(nxt[u]); } int main() { long long p, k; cin >> p >> k; if (k == 0) { long long ans = 1; for (int i = 0; i < p - 1; i++) { ans *= p; ans %= MOD; } cout << ans << endl; return 0; } if (k == 1) { long long ans = 1; for (int i = 0; i < p; i++) { ans *= p; ans %= MOD; } cout << ans << endl; return 0; } for (long long i = 0; i < p; i++) { nxt[i * k % p] = i; } long long ans = 1; for (int i = 1; i < p; i++) { if (vis[i] == 0) { dfs(i); ans *= p; ans %= MOD; } } printf( %lld n , ans); }
|
#include <bits/stdc++.h> using namespace std; long long ar[200010]; void solve() { long long a, b, c = 0, i, j, t, k, lie, m, n, o, x, y, z; long long p = 0, sm = 0, cnt = 0; scanf( %lld , &n); string s; cin >> s; if (n == 1) { printf( Yes n ); return; } for (i = 0; i < n; i++) ar[s[i] - a ]++; for (i = 0; i < 26; i++) { if (ar[i] > 1) { printf( Yes n ); return; } } printf( No n ); } int main() { solve(); return 0; }
|
#include <bits/stdc++.h> int main() { uint64_t a, b, x; std::cin >> a >> b; a < b | a - b & 1 ? std::cout << -1 : (x = a - b >> 1, x ^ a - x ^ b ? std::cout << -1 : std::cout << x << << a - x); }
|
#include <bits/stdc++.h> using namespace std; const long long int N = 2e5 + 5; void solve() { long long int n, i, j, ans = 0; cin >> n; long long int a[n]; for (auto &x : a) { cin >> x; }; map<long long int, long long int> cnt; for (i = 0; i < n; i++) { for (j = i + 1; j < n; j++) { cnt[a[i] + a[j]]++; ans = max(ans, cnt[a[i] + a[j]]); } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(0), cin.tie(NULL), cout.tie(NULL); long long int t = 1; while (t--) { solve(); } }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_to_sw_port (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; set<pair<int, int> > s; std::vector<int> vv; std::vector<std::vector<int> > gr; std::vector<int> vis; int k; pair<int, int> dfs(int u, int l) { vis[u] = l; vv.emplace_back(u); for (int v : gr[u]) { if ((vis[v]) && (vis[u] - vis[v]) >= k) { return {vis[v], vis[u]}; } else if (!vis[v]) { return dfs(v, l + 1); } } return {-1, -1}; } int32_t main() { int n; cin >> n; int m; cin >> m; cin >> k; gr.resize(n); for (int i = 0; i < m; ++i) { int u; cin >> u; u--; int v; cin >> v; v--; gr[u].emplace_back(v); gr[v].emplace_back(u); } vis.resize(n, 0); auto pp = dfs(0, 1); cout << pp.second - pp.first + 1 << n ; for (int i = pp.first - 1; i < pp.second; ++i) { cout << vv[i] + 1 << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int ttt; cin >> ttt; for (long long int iq = 0; iq < ttt; ++iq) { long long int n, e = 0; cin >> n; long long int s = n % 10; while (n >= 10) { n = n / 10; n = n * 10; e += n; n = n / 10; n += s; s = n % 10; } cout << e + s << endl; } return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : pci_exp_8_lane_64b_ep.v
module endpoint_blk_plus_v1_14 (
// PCI Express Fabric Interface
//------------------------------
pci_exp_txp,
pci_exp_txn,
pci_exp_rxp,
pci_exp_rxn,
// Transaction (TRN) Interface
//----------------------------
trn_clk,
trn_reset_n,
trn_lnk_up_n,
// Tx
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_tsrc_rdy_n,
trn_tdst_rdy_n,
trn_tdst_dsc_n,
trn_tsrc_dsc_n,
trn_terrfwd_n,
trn_tbuf_av,
// Rx
trn_rd,
trn_rrem_n,
trn_rsof_n,
trn_reof_n,
trn_rsrc_rdy_n,
trn_rsrc_dsc_n,
trn_rdst_rdy_n,
trn_rerrfwd_n,
trn_rnp_ok_n,
trn_rbar_hit_n,
trn_rfc_nph_av,
trn_rfc_npd_av,
trn_rfc_ph_av,
trn_rfc_pd_av,
trn_rcpl_streaming_n,
// Host (CFG) Interface
//---------------------
cfg_do,
cfg_rd_wr_done_n,
cfg_di,
cfg_byte_en_n,
cfg_dwaddr,
cfg_wr_en_n,
cfg_rd_en_n,
cfg_err_ur_n,
cfg_err_cpl_rdy_n,
cfg_err_cor_n,
cfg_err_ecrc_n,
cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n,
cfg_err_cpl_unexpect_n,
cfg_err_posted_n,
cfg_err_tlp_cpl_header,
cfg_err_locked_n,
cfg_interrupt_n,
cfg_interrupt_rdy_n,
cfg_interrupt_assert_n,
cfg_interrupt_di,
cfg_interrupt_do,
cfg_interrupt_mmenable,
cfg_interrupt_msienable,
cfg_to_turnoff_n,
cfg_pm_wake_n,
cfg_pcie_link_state_n,
cfg_trn_pending_n,
cfg_dsn,
cfg_bus_number,
cfg_device_number,
cfg_function_number,
cfg_status,
cfg_command,
cfg_dstatus,
cfg_dcommand,
cfg_lstatus,
cfg_lcommand,
//cfg_cfg,
fast_train_simulation_only,
// System (SYS) Interface
//-----------------------
sys_clk,
sys_reset_n,
refclkout
); //synthesis syn_black_box
//-------------------------------------------------------
// 1. PCI-Express (PCI_EXP) Interface
//-------------------------------------------------------
// Tx
output [(8 - 1):0] pci_exp_txp;
output [(8 - 1):0] pci_exp_txn;
// Rx
input [(8 - 1):0] pci_exp_rxp;
input [(8 - 1):0] pci_exp_rxn;
//-------------------------------------------------------
// 2. Transaction (TRN) Interface
//-------------------------------------------------------
// Common
output trn_clk;
output trn_reset_n;
output trn_lnk_up_n;
// Tx
input [(64 - 1):0] trn_td;
input [(8 - 1):0] trn_trem_n;
input trn_tsof_n;
input trn_teof_n;
input trn_tsrc_rdy_n;
output trn_tdst_rdy_n;
output trn_tdst_dsc_n;
input trn_tsrc_dsc_n;
input trn_terrfwd_n;
output [(4 - 1):0] trn_tbuf_av;
// Rx
output [(64 - 1):0] trn_rd;
output [(8 - 1):0] trn_rrem_n;
output trn_rsof_n;
output trn_reof_n;
output trn_rsrc_rdy_n;
output trn_rsrc_dsc_n;
input trn_rdst_rdy_n;
output trn_rerrfwd_n;
input trn_rnp_ok_n;
output [(7 - 1):0] trn_rbar_hit_n;
output [(8 - 1):0] trn_rfc_nph_av;
output [(12 - 1):0] trn_rfc_npd_av;
output [(8 - 1):0] trn_rfc_ph_av;
output [(12 - 1):0] trn_rfc_pd_av;
input trn_rcpl_streaming_n;
//-------------------------------------------------------
// 3. Host (CFG) Interface
//-------------------------------------------------------
output [(32 - 1):0] cfg_do;
output cfg_rd_wr_done_n;
input [(32 - 1):0] cfg_di;
input [(32/8 - 1):0] cfg_byte_en_n;
input [(10 - 1):0] cfg_dwaddr;
input cfg_wr_en_n;
input cfg_rd_en_n;
input cfg_err_ur_n;
output cfg_err_cpl_rdy_n;
input cfg_err_cor_n;
input cfg_err_ecrc_n;
input cfg_err_cpl_timeout_n;
input cfg_err_cpl_abort_n;
input cfg_err_cpl_unexpect_n;
input cfg_err_posted_n;
input cfg_err_locked_n;
input [(48 - 1):0] cfg_err_tlp_cpl_header;
input cfg_interrupt_n;
output cfg_interrupt_rdy_n;
input cfg_interrupt_assert_n;
input [7:0] cfg_interrupt_di;
output [7:0] cfg_interrupt_do;
output [2:0] cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_to_turnoff_n;
input cfg_pm_wake_n;
output [(3 - 1):0] cfg_pcie_link_state_n;
input cfg_trn_pending_n;
input [(64 - 1):0] cfg_dsn;
output [(8 - 1):0] cfg_bus_number;
output [(5 - 1):0] cfg_device_number;
output [(3 - 1):0] cfg_function_number;
output [(16 - 1):0] cfg_status;
output [(16 - 1):0] cfg_command;
output [(16 - 1):0] cfg_dstatus;
output [(16 - 1):0] cfg_dcommand;
output [(16 - 1):0] cfg_lstatus;
output [(16 - 1):0] cfg_lcommand;
//input [(1024 - 1):0] cfg_cfg;
input fast_train_simulation_only;
//-------------------------------------------------------
// 4. System (SYS) Interface
//-------------------------------------------------------
input sys_clk;
input sys_reset_n;
output refclkout;
endmodule // endpoint_blk_plus_v1_14
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_8_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_8_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for isobufsrc with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_8 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_8 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_8_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<string> g(n); for (int i = 0; i < n; i++) cin >> g[i]; auto flip = [&](int i, int j) { if (g[i][j] == 0 ) g[i][j] = 1 ; else g[i][j] = 0 ; }; vector<array<int, 6> > v; for (int i = 0; i + 2 < n; i++) { for (int j = 0; j < m; j++) { if (g[i][j] == 1 ) { if (j == m - 1) { v.push_back({i, j, i + 1, j, i + 1, j - 1}); flip(i + 1, j); flip(i + 1, j - 1); flip(i, j); } else { v.push_back({i, j, i + 1, j, i + 1, j + 1}); flip(i + 1, j); flip(i + 1, j + 1); flip(i, j); } } } } for (int j = 0; j + 2 < m; j++) { if (g[n - 2][j] == 1 ) { v.push_back({n - 2, j, n - 2, j + 1, n - 1, j + 1}); flip(n - 2, j); flip(n - 2, j + 1); flip(n - 1, j + 1); } if (g[n - 1][j] == 1 ) { v.push_back({n - 1, j, n - 2, j + 1, n - 1, j + 1}); flip(n - 1, j); flip(n - 2, j + 1); flip(n - 1, j + 1); } } vector<vector<int> > r(2, vector<int>(2, 0)); if (g[n - 2][m - 2] == 1 ) { r[0][1] ^= 1; r[1][0] ^= 1; r[1][1] ^= 1; } if (g[n - 2][m - 1] == 1 ) { r[0][0] ^= 1; r[1][0] ^= 1; r[1][1] ^= 1; } if (g[n - 1][m - 2] == 1 ) { r[0][0] ^= 1; r[0][1] ^= 1; r[1][1] ^= 1; } if (g[n - 1][m - 1] == 1 ) { r[0][0] ^= 1; r[0][1] ^= 1; r[1][0] ^= 1; } if (r[0][0]) v.push_back({n - 2, m - 1, n - 1, m - 2, n - 1, m - 1}); if (r[0][1]) v.push_back({n - 2, m - 2, n - 1, m - 2, n - 1, m - 1}); if (r[1][0]) v.push_back({n - 2, m - 2, n - 2, m - 1, n - 1, m - 1}); if (r[1][1]) v.push_back({n - 2, m - 2, n - 2, m - 1, n - 1, m - 2}); cout << v.size() << n ; for (auto z : v) cout << z[0] + 1 << << z[1] + 1 << << z[2] + 1 << << z[3] + 1 << << z[4] + 1 << << z[5] + 1 << n ; } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:39:12 12/01/2015
// Design Name: peripheral_crc_16
// Module Name: /home/jorge/Documentos/SPI_SD/crc_16_peripheral_testbench.v
// Project Name: SPI_SD
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: peripheral_crc_16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module crc_16_peripheral_testbench;
// Inputs
reg clk;
reg rst;
reg [15:0] d_in;
reg cs;
reg [3:0] addr;
reg rd;
reg wr;
// Outputs
wire [15:0] d_out;
//parameters
parameter PERIOD = 10;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
// Instantiate the Unit Under Test (UUT)
peripheral_crc_16 uut (
.clk(clk),
.rst(rst),
.d_in(d_in),
.cs(cs),
.addr(addr),
.rd(rd),
.wr(wr),
.d_out(d_out)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
d_in = 0;
cs = 1;
addr = 0;
rd = 0;
wr = 0;
//clk
#OFFSET
forever
begin
clk = 1'b1;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b0;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
// Wait 10 ns for global reset to finish
#10;
rst = 1;
#10;
rst = 0;
#10
// se coloca en la direccion data in la primera parte del dato a operar
wr = 1;
addr = 4'h0;
d_in = 16'h00AE;
#10
// se coloca en la direccion data in la segunda parte del dato a operar
wr = 1;
addr = 4'h2;
d_in = 16'h3B05;
#10
//se coloca start en 1 en la direccion de start
wr = 1;
addr = 4'h4;
d_in [0] = 1;
#10
//se coloca start en 0 en la direccion de start
wr = 1;
addr = 4'h4;
d_in [0] = 0;
#10
// se lee la direccion done
wr = 0;
rd = 1;
addr = 4'h6;
#10
@(*)begin
if (d_out[0]) begin //si se tiene un nuevo dato se lee la direccion d_out y se resetea
addr = 4'h8;
#20
rst=1;
cs=0;
#10
rst=0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_2_V
`define SKY130_FD_SC_HD__O311A_2_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311a_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR4BB_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; bool check(long long x, long long y, long long p, long long q, long long t) { return p * t >= x && q * t - p * t >= y - x; } int main() { long long t; cin >> t; while (t--) { long long x, y, p, q, m; cin >> x >> y >> p >> q; long long l = -1; long long r = (long long)1e9; if (!check(x, y, p, q, r)) { printf( -1 n ); continue; } while (r - l > 1) { m = l + (r - l) / 2; if (check(x, y, p, q, m)) r = m; else l = m; } printf( %lld n , r * q - y); } return 0; }
|
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