repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio/sky130_fd_io__top_sio.functional.pp.v | 9,475 | module MODULE1 (VAR4, VAR57, VAR41, VAR64, VAR15, VAR19, VAR49,
VAR5, VAR36, VAR11, VAR63, VAR66, VAR52, VAR44, VAR58,
VAR9, VAR8, VAR62, VAR55, VAR31,
VAR22
,VAR7, VAR59, VAR42, VAR24, VAR20, VAR32, VAR68
);
output VAR4;
inout VAR57;
inout VAR41;
input [2:0] VAR64;
input VAR15;
input VAR19;
output VAR49;
input VAR5;
input VAR36;
input VAR11;
input VAR63;
input VAR66;
input VAR52;
input VAR44;
input VAR58;
input VAR9;
inout VAR8;
output VAR62;
input VAR55;
input VAR31;
inout VAR22;
inout VAR7;
inout VAR59;
inout VAR42;
inout VAR24;
inout VAR20;
inout VAR32;
inout VAR68;
reg [2:0] VAR26;
reg VAR46, VAR60, VAR17, VAR28, VAR16, VAR50;
reg VAR10, VAR3;
wire VAR67, VAR13, VAR34, VAR61, VAR30, VAR47, VAR69, VAR1,VAR27;
wire VAR25;
wire VAR6 = (VAR68===1) && (VAR20===1) && (VAR42===0) && (VAR32===1);
wire VAR56 = (VAR68===1) && (VAR20===1) && (VAR42===0) && (VAR24===1);
wire VAR23 = (VAR68===1) && (VAR20===1) && (VAR42===0);
wire VAR33 = (VAR68===1) && (VAR32===1) && (VAR42===0) && (VAR20===1) && (VAR7===0);
wire VAR53 = (VAR68===1) && (VAR42===0) && (VAR20===1) && (VAR7===0);
wire VAR35 = (VAR20===1) && (VAR68===1)&& (VAR7===0) && (VAR42===0);
wire VAR45 = VAR16 === 1 || VAR26 === 3'b000 || VAR26 === 3'b001;
wire VAR29 = !VAR35
|| (VAR26 !== 3'b000 && VAR26 !== 3'b001 && VAR16===1'VAR51)
|| (^VAR26[2:0] === 1'VAR51 && VAR16===1'b0)
|| (VAR46===1'VAR51 && VAR26 !== 3'b000 && VAR26 !== 3'b001 && VAR16===1'b0)
|| (VAR3===1'VAR51 && VAR26 !== 3'b000 && VAR26 !== 3'b001 && VAR16===1'b0)
|| ((VAR52!==1'b1 || VAR9!==1'b1) && VAR3===1'b1 && VAR26 !== 3'b000 && VAR26 !== 3'b001 && VAR16===1'b0 );
parameter VAR48= 101;
parameter VAR2= 42;
parameter VAR48= 0;
parameter VAR2= 0;
integer VAR12,VAR65,VAR43;
VAR18 VAR12 = VAR48;
VAR18 VAR65 = VAR2;
always @
begin : VAR54
if (^VAR5===1'VAR51 || !VAR23 || (VAR5===1 && ^VAR15===1'VAR51))
VAR26 <= 3'VAR39;
end
else if (VAR5===0)
VAR26 <= 3'b000;
else if (VAR15===1)
VAR26 <= (^VAR64[2:0] === 1'VAR51 || !VAR56) ? 3'VAR39 : VAR64;
end
always @(VAR25 or VAR67)
begin
disable VAR54; VAR26 <= 3'VAR39;
end
always @
begin : VAR40
if (^VAR5===1'VAR51 || !VAR23 || (VAR5===1 && ^VAR15===1'VAR51))
VAR60 <= 1'VAR51;
end
else if (VAR5===0)
VAR60 <= 1'b0;
else if (VAR15===1)
VAR60 <= (^VAR63 === 1'VAR51 || !VAR56) ? 1'VAR51 : VAR63;
end
always @(VAR25 or VAR30)
begin
disable VAR40; VAR60 <= 1'VAR51;
end
always @
begin : VAR21
if (^VAR5===1'VAR51 || !VAR23 || (VAR5===1 && ^VAR15===1'VAR51))
VAR50 <= 1'VAR51;
end
else if (VAR5===0)
VAR50 <= 1'b0;
else if (VAR15===1)
VAR50 <= (^VAR55 === 1'VAR51 || !VAR56) ? 1'VAR51 : VAR55;
end
always @(VAR25 or VAR47)
begin
disable VAR21; VAR50 <= 1'VAR51;
end
always @
begin : VAR38
if (^VAR5===1'VAR51 || !VAR23 || (VAR5===1 && ^VAR15===1'VAR51))
VAR10 <= 1'VAR51;
end
else if (VAR5===0)
VAR10 <= 1'b0;
else if (VAR15===1)
VAR10 <= (^VAR58 === 1'VAR51 || !VAR56) ? 1'VAR51 : VAR58;
end
always @(VAR25 or VAR27)
begin
disable VAR38; VAR10 <= 1'VAR51;
end
always @
begin : VAR37
if (^VAR5===1'VAR51 || !VAR23 || (VAR5===1 && (^VAR15===1'VAR51 || (VAR15===0 && VAR50===1'VAR51))))
VAR28 <= 1'VAR51;
end
else if (VAR5===0)
VAR28 <= 1'b0;
else if (VAR15===1 || VAR50===1)
VAR28 <= (^VAR31 === 1'VAR51 || !VAR6) ? 1'VAR51 : VAR31;
end
always @(VAR25 or VAR61)
begin
disable VAR37; VAR28 <= 1'VAR51;
end
reg VAR14;
begin
begin
begin | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/TECH/CLK_DIV2.v | 3,529 | module MODULE1 (
input VAR3,
input VAR2,
output reg VAR1
);
always @ (posedge VAR2 or posedge VAR3)
if (VAR3)
VAR1 <=0;
else
VAR1 <=!VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpiov2/sky130_fd_io__top_gpiov2.pp.blackbox.v | 3,314 | module MODULE1 (
VAR5 ,
VAR21 ,
VAR19 ,
VAR13 ,
VAR4 ,
VAR3 ,
VAR37,
VAR24 ,
VAR7 ,
VAR30 ,
VAR27 ,
VAR12 ,
VAR32 ,
VAR22 ,
VAR17 ,
VAR28 ,
VAR36 ,
VAR10 ,
VAR16 ,
VAR20 ,
VAR33 ,
VAR29 ,
VAR6 ,
VAR9 ,
VAR34 ,
VAR26 ,
VAR35 ,
VAR25 ,
VAR8 ,
VAR31 ,
VAR11 ,
VAR14 ,
VAR23 ,
VAR1 ,
VAR15 ,
VAR18 ,
VAR2
);
input VAR5 ;
input VAR21 ;
input VAR19 ;
input VAR13 ;
input VAR4 ;
input VAR3 ;
input VAR37;
input VAR24 ;
input VAR7 ;
input VAR30 ;
input VAR27 ;
input VAR12 ;
input VAR32 ;
input VAR22 ;
input VAR17 ;
input VAR28 ;
input [2:0] VAR36 ;
inout VAR10 ;
inout VAR16 ;
inout VAR20 ;
inout VAR33 ;
inout VAR29 ;
inout VAR6 ;
output VAR9 ;
output VAR34 ;
output VAR26 ;
output VAR35 ;
inout VAR25 ;
inout VAR8 ;
inout VAR31 ;
inout VAR11 ;
inout VAR14 ;
inout VAR23 ;
inout VAR1 ;
inout VAR15 ;
inout VAR18 ;
inout VAR2 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_eclbyplog_rs1.v | 7,785 | module MODULE1 (
VAR54, VAR14, VAR42, VAR47,
VAR28, VAR55, VAR22,
VAR8, VAR58, VAR48,
VAR50, VAR52,
VAR44, VAR1,
VAR7, VAR4,
VAR59, VAR62,
VAR61,
VAR23, VAR63, VAR51, VAR29, VAR32, VAR11, VAR26,
VAR18, VAR17, VAR39, VAR19,
VAR36, VAR43, VAR3, VAR57,
VAR5, VAR2, VAR25, VAR12,
VAR34, VAR10, VAR35, VAR37,
VAR13
) ;
input VAR23;
input VAR63;
input [4:0] VAR51; input [4:0] VAR29; input [4:0] VAR32;
input [4:0] VAR11;
input [4:0] VAR26;
input [4:0] VAR18;
input [4:0] VAR17;
input [1:0] VAR39;
input VAR19;
input VAR36;
input [1:0] VAR43;
input VAR3;
input [1:0] VAR57;
input VAR5;
input VAR2;
input VAR25; input VAR12; input VAR34;
input VAR10;
input VAR35;
input VAR37;
input VAR13;
output VAR54;
output VAR14;
output VAR42;
output VAR47;
output VAR28;
output VAR55;
output VAR22;
output VAR8;
output VAR58;
output VAR48;
output VAR50;
output VAR52;
output VAR44;
output VAR1;
output VAR7;
output VAR4;
output VAR59;
output VAR62;
output VAR61;
wire VAR40, VAR6, VAR31, VAR24, VAR33, VAR16, VAR53;
wire VAR15, VAR21, VAR56, VAR9, VAR46; wire VAR20;
wire VAR49; wire VAR27;
wire VAR41;
assign VAR27 = VAR51[0]|VAR51[1]|VAR51[2]|VAR51[3]|VAR51[4];
assign VAR49 = VAR27 & ~VAR63 & ~VAR23;
assign VAR40 = VAR15 & VAR25 & ~VAR2;
assign VAR6 = VAR21 & VAR12 & ~VAR40;
assign VAR31 = VAR56 & VAR10 & ~VAR6 & ~VAR40;
assign VAR16 = VAR46 & VAR34 & ~VAR13;
assign VAR53 = VAR46 & VAR13;
assign VAR24 = (VAR9 & VAR35 | VAR20 & VAR37) & ~VAR40 & ~VAR6;
assign VAR33 = ~VAR24 & ~VAR31 & ~VAR6 & ~VAR40 & ~VAR16 & ~VAR53;
assign VAR22 = (VAR40 & VAR49);
assign VAR55 = ((VAR33 | ~VAR49) & ~VAR63);
assign VAR8 = (VAR16 & ~VAR40 & ~VAR31 & ~VAR6 & ~VAR24 & VAR49);
assign VAR28 = (VAR63 & ~VAR23) | (~VAR47 & ~VAR40);
assign VAR47 = ~((VAR6 | VAR31 | VAR24 | VAR53) & VAR49);
assign VAR42 = ((VAR53 | VAR24) & VAR49);
assign VAR14 = (VAR31 & ~VAR24 & ~VAR53 & VAR49);
assign VAR54 = (VAR6 & ~VAR24 & ~VAR53 & VAR49);
assign VAR50 = VAR53;
assign VAR58 = VAR20 & VAR37 & ~VAR53;
assign VAR48 = ~VAR53 & ~(VAR20 & VAR37);
assign VAR41 = VAR27;
assign VAR62 = VAR40 & VAR41;
assign VAR59 = VAR33 | ~VAR41;
assign VAR61 = VAR16 & ~VAR40 & ~VAR31 & ~VAR6 & ~VAR24 & VAR41;
assign VAR4 = (VAR6 | VAR31 | VAR24 | VAR53) & VAR41 & ~VAR40;
assign VAR7 = ~(VAR6 | VAR31 | VAR24 | VAR53);
assign VAR1 = VAR24 | VAR53;
assign VAR44 = VAR31 & ~VAR24 & ~VAR53;
assign VAR52 = VAR6 & ~VAR24 & ~VAR53;
assign VAR15 = VAR19 & (VAR51[4:0] == VAR29[4:0]);
assign VAR21 = VAR36 & (VAR51[4:0] == VAR32[4:0]);
VAR38 VAR45(.out(VAR56), .VAR64({VAR39[1:0],VAR51[4:0]}),
.VAR30({VAR43[1:0],VAR11[4:0]}));
VAR38 VAR60(.out(VAR9), .VAR64({VAR39[1:0],VAR51[4:0]}),
.VAR30({VAR57[1:0],VAR18[4:0]}));
assign VAR46 = VAR3 & (VAR51[4:0] == VAR26[4:0]);
assign VAR20 = VAR5 & (VAR51[4:0] == VAR17[4:0]);
endmodule | gpl-2.0 |
ridecore/ridecore | src/fpga/reorderbuf.v | 5,028 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR49,
input wire [VAR40-1:0] VAR42,
input wire [VAR64-1:0] VAR25,
input wire VAR32,
input wire VAR15,
input wire [VAR45-1:0] VAR4,
input wire [VAR48-1:0] VAR38,
input wire VAR62,
input wire VAR39,
input wire [VAR40-1:0] VAR60,
input wire [VAR64-1:0] VAR55,
input wire VAR47,
input wire VAR43,
input wire [VAR45-1:0] VAR1,
input wire [VAR48-1:0] VAR6,
input wire VAR31,
input wire VAR50,
input wire [VAR40-1:0] VAR44,
input wire VAR12,
input wire [VAR40-1:0] VAR16,
input wire VAR13,
input wire [VAR40-1:0] VAR57,
input wire VAR28,
input wire [VAR40-1:0] VAR52,
input wire VAR24,
input wire [VAR40-1:0] VAR56,
input wire VAR26,
input wire [VAR2-1:0] VAR33,
output reg [VAR40-1:0] VAR11,
output wire [VAR40-1:0] VAR53,
output wire [1:0] VAR19,
output wire VAR34,
output wire VAR65,
output wire VAR10,
output wire [VAR45-1:0] VAR59,
output wire [VAR45-1:0] VAR20,
output wire [VAR2-1:0] VAR21,
output wire [VAR48-1:0] VAR3,
output wire VAR8,
output wire [VAR2-1:0] VAR37,
output wire VAR30,
input wire [VAR40-1:0] VAR35,
input wire [VAR40:0] VAR23,
input wire VAR9
);
reg [VAR7-1:0] VAR63;
reg [VAR7-1:0] VAR36;
reg [VAR7-1:0] VAR58;
reg [VAR7-1:0] VAR51;
reg [VAR7-1:0] VAR17;
reg [VAR2-1:0] VAR41 [0:VAR7-1];
reg [VAR2-1:0] VAR29 [0:VAR7-1];
reg [VAR45-1:0] VAR22 [0:VAR7-1];
reg [VAR48-1:0] VAR14 [0:VAR7-1];
assign VAR53 = VAR11+1;
wire VAR61 = (VAR11 > VAR35) || (VAR23 == 0) ?
1'b1 : 1'b0;
wire VAR5 = ({VAR61, VAR35} - {1'b0, VAR11}) > 0 ? 1'b1 : 1'b0;
wire VAR46 = ({VAR61, VAR35} - {1'b0, VAR11}) > 1 ? 1'b1 : 1'b0;
wire VAR54 = VAR5 & VAR63[VAR11];
wire VAR18 =
~(~VAR9 & VAR54 & VAR17[VAR11]) &
~(VAR54 & VAR36[VAR11] & ~VAR9) &
VAR54 & VAR46 & VAR63[VAR53];
assign VAR19 = {1'b0, VAR54} + {1'b0, VAR18};
assign VAR34 = (VAR54 & VAR36[VAR11] & ~VAR9) |
(VAR18 & VAR36[VAR53] & ~VAR9);
assign VAR65 = ~VAR9 & VAR54 & VAR58[VAR11];
assign VAR10 = ~VAR9 & VAR18 & VAR58[VAR53];
assign VAR59 = VAR22[VAR11];
assign VAR20 = VAR22[VAR53];
assign VAR30 = (~VAR9 & VAR54 & VAR17[VAR11]) |
(~VAR9 & VAR18 & VAR17[VAR53]);
assign VAR21 = (~VAR9 & VAR54 & VAR17[VAR11]) ?
VAR41[VAR11] : VAR41[VAR53];
assign VAR3 = (~VAR9 & VAR54 & VAR17[VAR11]) ?
VAR14[VAR11] : VAR14[VAR53];
assign VAR8 = (~VAR9 & VAR54 & VAR17[VAR11]) ?
VAR51[VAR11] : VAR51[VAR53];
assign VAR37 = (~VAR9 & VAR54 & VAR17[VAR11]) ?
VAR29[VAR11] : VAR29[VAR53];
always @ (posedge clk) begin
if (reset) begin
VAR11 <= 0;
end else if (~VAR9) begin
VAR11 <= VAR11 + VAR54 + VAR18;
end
end
always @ (posedge clk) begin
if (reset) begin
VAR63 <= 0;
VAR51 <= 0;
end else begin
if (VAR49)
VAR63[VAR42] <= 1'b0;
if (VAR39)
VAR63[VAR60] <= 1'b0;
if (VAR50)
VAR63[VAR44] <= 1'b1;
if (VAR12)
VAR63[VAR16] <= 1'b1;
if (VAR13)
VAR63[VAR57] <= 1'b1;
if (VAR28)
VAR63[VAR52] <= 1'b1;
if (VAR24) begin
VAR63[VAR56] <= 1'b1;
VAR51[VAR56] <= VAR26;
VAR29[VAR56] <= VAR33;
end
end
end
always @ (posedge clk) begin
if (VAR49) begin
VAR17[VAR42] <= VAR62;
VAR36[VAR42] <= VAR32;
VAR58[VAR42] <= VAR15;
VAR22[VAR42] <= VAR4;
VAR14[VAR42] <= VAR38;
VAR41[VAR42] <= VAR25;
end
if (VAR39) begin
VAR17[VAR60] <= VAR31;
VAR36[VAR60] <= VAR47;
VAR58[VAR60] <= VAR43;
VAR22[VAR60] <= VAR1;
VAR14[VAR60] <= VAR6;
VAR41[VAR60] <= VAR55;
end
end
endmodule VAR27 wire | bsd-3-clause |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/soc_system_button_pio.v | 3,760 | module MODULE1 (
address,
VAR10,
clk,
VAR5,
VAR2,
VAR14,
VAR11,
irq,
VAR3
)
;
output irq;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR10;
input clk;
input [ 1: 0] VAR5;
input VAR2;
input VAR14;
input [ 31: 0] VAR11;
wire VAR8;
reg [ 1: 0] VAR9;
reg [ 1: 0] VAR12;
wire [ 1: 0] VAR15;
reg [ 1: 0] VAR1;
wire VAR13;
wire [ 1: 0] VAR4;
wire irq;
reg [ 1: 0] VAR7;
wire [ 1: 0] VAR6;
reg [ 31: 0] VAR3;
assign VAR8 = 1;
assign VAR6 = ({2 {(address == 0)}} & VAR15) |
({2 {(address == 2)}} & VAR7) |
({2 {(address == 3)}} & VAR1);
always @(posedge clk or negedge VAR2)
begin
if (VAR2 == 0)
VAR3 <= 0;
end
else if (VAR8)
VAR3 <= {32'b0 | VAR6};
end
assign VAR15 = VAR5;
always @(posedge clk or negedge VAR2)
begin
if (VAR2 == 0)
VAR7 <= 0;
end
else if (VAR10 && ~VAR14 && (address == 2))
VAR7 <= VAR11[1 : 0];
end
assign irq = |(VAR1 & VAR7);
assign VAR13 = VAR10 && ~VAR14 && (address == 3);
always @(posedge clk or negedge VAR2)
begin
if (VAR2 == 0)
VAR1[0] <= 0;
end
else if (VAR8)
if (VAR13 && VAR11[0])
VAR1[0] <= 0;
else if (VAR4[0])
VAR1[0] <= -1;
end
always @(posedge clk or negedge VAR2)
begin
if (VAR2 == 0)
VAR1[1] <= 0;
end
else if (VAR8)
if (VAR13 && VAR11[1])
VAR1[1] <= 0;
else if (VAR4[1])
VAR1[1] <= -1;
end
always @(posedge clk or negedge VAR2)
begin
if (VAR2 == 0)
begin
VAR9 <= 0;
VAR12 <= 0;
end
else if (VAR8)
begin
VAR9 <= VAR15;
VAR12 <= VAR9;
end
end
assign VAR4 = ~VAR9 & VAR12;
endmodule | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_tielo.v | 1,630 | if (VAR4 && (VAR8==VAR3)) \
begin: VAR2 \
VAR15 VAR14 (.VAR6); \
end
module MODULE1 #(parameter VAR1(VAR8)
, parameter VAR4=1
)
(output [VAR8-1:0] VAR6
);
begin :VAR5
assign VAR6 = { VAR8 {1'b0} };
end
VAR13 assert(VAR4==0) else ("## %VAR16 VAR11 VAR7 VAR12 VAR9 VAR10 VAR2");
end
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a_4.v | 2,322 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR5 ,
VAR4 ,
VAR1 ,
VAR6,
VAR7,
VAR2 ,
VAR8
);
output VAR3 ;
input VAR10 ;
input VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR6;
input VAR7;
input VAR2 ;
input VAR8 ;
VAR11 VAR9 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR3 ,
VAR10,
VAR5,
VAR4,
VAR1
);
output VAR3 ;
input VAR10;
input VAR5;
input VAR4;
input VAR1;
supply1 VAR6;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR8 ;
VAR11 VAR9 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_iwb_biu.v | 15,504 | module MODULE1(
clk, rst, VAR9,
VAR31, VAR28, VAR24, VAR27, VAR46, VAR16,
VAR47, VAR29, VAR49, VAR11, VAR10, VAR1,
VAR42,
VAR13, VAR20,
VAR41, VAR6, VAR30, VAR2, VAR23, VAR43, VAR25,
VAR32, VAR3, VAR18
);
parameter VAR45 = VAR33;
parameter VAR38 = VAR33;
input clk; input rst; input [1:0] VAR9;
input VAR31; input VAR28; input VAR24; input VAR27; input VAR46; input [VAR45-1:0] VAR16; output VAR47; output [VAR38-1:0] VAR29; output VAR49; output VAR11; output [3:0] VAR10; output [VAR45-1:0] VAR1; VAR21 VAR5
output VAR42; VAR22
output [2:0] VAR13; output [1:0] VAR20; VAR22
input [VAR45-1:0] VAR41; input [VAR38-1:0] VAR6; input VAR30; input VAR2; input VAR23; input VAR25; input [3:0] VAR43; output [31:0] VAR32; output VAR3; output VAR18;
reg [1:0] VAR17; VAR21 VAR26
reg [VAR38-1:0] VAR29; reg VAR47; reg VAR49; reg VAR11; reg [3:0] VAR10; VAR21 VAR5
reg VAR42; VAR22
reg [1:0] VAR8; reg [2:0] VAR13; VAR22
reg [VAR45-1:0] VAR1; VAR22
reg VAR14; reg VAR36; reg [VAR45-1:0] VAR32; else
wire VAR14; wire VAR36; VAR22
wire VAR4; reg VAR35; wire VAR7; VAR21 VAR12
reg [VAR12-1:0] VAR40; VAR22
reg VAR34;
wire VAR15;
wire VAR39;
reg VAR48;
reg [VAR45-1:0] VAR19;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR29 <= {VAR38{1'b0}};
else if ((VAR30 & VAR2) & ~VAR24 & ~VAR4 & ~(VAR49 & ~VAR24) | VAR25 & (VAR34 | VAR3))
VAR29 <= VAR6;
assign VAR29 = VAR6;
assign VAR15 = VAR29 == VAR6;
assign VAR39 = VAR15 & VAR34;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR19 <= 32'h00000000;
else if (VAR24)
VAR19 <= VAR16;
always @(posedge clk or posedge rst)
if (rst)
VAR48 <= 1'b0;
else if (VAR39 & VAR30 & VAR2)
VAR48 <= 1'b1;
else
VAR48 <= 1'b0;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR34 <= 1'b1;
else if ((VAR30 & VAR2) & ~VAR24 & ~VAR4 & ~(VAR49 & ~VAR24))
VAR34 <= 1'b0;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR32 <= 32'h00000000;
else if (VAR24)
VAR32 <= VAR16;
assign VAR32 = VAR48 ? VAR19 : VAR16;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR1 <= {VAR45{1'b0}};
else if ((VAR30 & VAR2) & ~VAR24 & ~VAR4)
VAR1 <= VAR41;
assign VAR1 = VAR41;
always @(posedge clk or posedge rst)
if (rst)
VAR17 <= 2'b0;
else
VAR17 <= VAR17 + 1'd1;
assign VAR3 = (VAR48 | VAR14) & ~VAR35
& (VAR17[0] | ~VAR9[0])
& (VAR17[1] | ~VAR9[1])
;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR14 <= 1'b0;
else
VAR14 <= VAR24 & ~VAR4;
assign VAR14 = VAR24;
assign VAR18 = VAR36
& (VAR17[0] | ~VAR9[0])
& (VAR17[1] | ~VAR9[1])
;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR36 <= 1'b0;
else
VAR36 <= VAR27 & ~VAR4;
assign VAR36 = VAR27 & ~VAR35;
assign VAR7 = VAR46 | (|VAR40);
assign VAR7 = 1'b0;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR40 <= 1'b0;
else if (VAR46)
VAR40 <= {VAR12{1'b1}};
else if (VAR40)
VAR40 <= VAR40 - 7'd1;
assign VAR4 = VAR49 & ~(VAR30 & VAR2) & ~(VAR24 | VAR27);
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR35 <= 1'b0;
else if (VAR24 | VAR27)
VAR35 <= 1'b0;
else if (VAR4)
VAR35 <= 1'b1;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR47 <= 1'b0;
else
VAR47 <= VAR30 & ~VAR24 & ~VAR7 & ~VAR39 | VAR4 & ~VAR24;
VAR47 <= VAR30 & ~VAR24 & ~VAR7 & ~VAR39 | VAR25 | VAR4 & ~VAR24;
assign VAR47 = VAR30 & ~VAR7;
assign VAR47 = VAR30 | VAR25 & ~VAR7;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR49 <= 1'b0;
else
VAR49 <= (VAR30 & VAR2) & ~VAR24 & ~VAR7 & ~VAR39 | VAR4 & ~VAR24;
assign VAR49 = VAR30 & VAR2;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR11 <= 1'b0;
else
VAR11 <= VAR30 & VAR2 & VAR23 | VAR4 & VAR11;
assign VAR11 = VAR30 & VAR2 & VAR23;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR10 <= 4'b0000;
else
VAR10 <= VAR43;
assign VAR10 = VAR43;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR42 <= 1'b0;
else
VAR42 <= VAR25;
assign VAR42 = VAR25;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR8 <= 2'b00;
else if (VAR25 && VAR8 && VAR24)
VAR8 <= VAR8 - 1'b1;
else if (~VAR25)
VAR8 <= 2'b11;
always @(posedge VAR31 or posedge VAR28)
if (VAR28)
VAR13 <= 3'b000; VAR21 VAR37
else
VAR13 <= 3'b111; else
else if (VAR25 && VAR8[1])
VAR13 <= 3'b010; else if (VAR25 && VAR24)
VAR13 <= 3'b111; VAR22 else
VAR44 !!!;
assign VAR20 = 2'b01;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2.behavioral.pp.v | 1,186 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/bram_common.v | 8,107 | module MODULE1 #
(
parameter VAR59 = 16,
parameter VAR41 = 13,
parameter VAR52 = 3,
parameter VAR19 = 1,
parameter VAR48 = 0,
parameter VAR42 = 0,
parameter VAR75 = 0,
parameter VAR44 = 1 )
(
input VAR55, input VAR13, input VAR76, input [63:0] VAR61, output [63:0] VAR33, input [VAR41 - 1:0] VAR45, input VAR46, input VAR67, input VAR22, input [63:0] VAR18, output [63:0] VAR11, input [VAR41 - 1:0] VAR65 );
localparam VAR63 = 64/VAR59;
localparam VAR62 = 32 - VAR63;
parameter VAR29 = (VAR63 == 64) ? 6: (VAR63 == 32)
? 5: (VAR63 == 16)
? 4: (VAR63 == 8)
? 3: (VAR63 == 4)
? 2: (VAR63 == 2)
? 1:0;
parameter VAR7 = (VAR63 == 32) ? 36: (VAR63 == 16)? 18: (VAR63 == 8)? 9: VAR63;
localparam VAR27 = 15 - VAR29;
wire [31:0]VAR16 = 32'b0;
wire [31:0]VAR69 = 32'b0;
generate
genvar VAR3;
if (VAR59 == 1)
begin: VAR40
VAR4
.VAR20 (VAR44)
)
VAR15
(
.VAR37 (VAR61),
.VAR74 (VAR45[8:0]),
.VAR39 ({8{VAR76}}),
.VAR43 (VAR13),
.VAR38 (VAR55),
.VAR70 (VAR11),
.VAR58 (VAR65[8:0]),
.VAR28 (VAR67),
.VAR30 (1'b1),
.VAR25 (1'b0),
.VAR36 (VAR46),
.VAR53 (8'h00),
.VAR51(),
.VAR57(),
.VAR2(),
.VAR56()
);
end
else if (VAR59 ==2)
for (VAR3=0; VAR3 < VAR59; VAR3 = VAR3+1)
begin:VAR9
VAR12
.VAR66 (VAR7),
.VAR49 (VAR7),
.VAR77 (VAR7),
.VAR32 (VAR7),
.VAR26("VAR10"),
.VAR71("VAR10"),
.VAR8 (VAR44)
)
VAR21
(
.VAR34 (VAR33[(VAR3+1)*VAR63-1: VAR3*VAR63]),
.VAR1 (VAR61[(VAR3+1)*VAR63-1: VAR3*VAR63]),
.VAR24 ({ 1'b0, VAR45[VAR27 - 1:0], {VAR29{1'b0}} }),
.VAR5 ({4{VAR76}}),
.VAR50 (VAR13),
.VAR23 (VAR55),
.VAR14 (VAR11[(VAR3+1)*VAR63-1: VAR3*VAR63]),
.VAR31 (VAR18 [(VAR3+1)*VAR63-1: VAR3*VAR63]),
.VAR17 ({ 1'b0, VAR65[VAR27 - 1:0], {VAR29{1'b0}} }),
.VAR64 (4'b0),
.VAR60 (VAR67),
.VAR35 (1'b1),
.VAR72 (1'b1),
.VAR6 (1'b0),
.VAR47 (1'b0),
.VAR73 (VAR46)
);
end
else
for (VAR3=0; VAR3 < VAR59; VAR3 = VAR3+1)
begin:VAR68
VAR12
.VAR66 (VAR7),
.VAR49 (VAR7),
.VAR77 (VAR7),
.VAR32 (VAR7),
.VAR26("VAR10"),
.VAR71("VAR10"),
.VAR8 (VAR44)
)
VAR54
(
.VAR34 ({ VAR16[VAR62-1:0], VAR33[(VAR3+1)*VAR63-1: VAR3*VAR63] }),
.VAR1 ({ {VAR62{1'b0}} ,VAR61[(VAR3+1)*VAR63-1: VAR3*VAR63] }),
.VAR24 ({ 1'b0, VAR45[VAR27 - 1:0], {VAR29{1'b0}} }),
.VAR5 ({4{VAR76}}),
.VAR50 (VAR13),
.VAR23 (VAR55),
.VAR14 ({ VAR69[VAR62-1:0], VAR11[(VAR3+1)*VAR63-1: VAR3*VAR63] }),
.VAR31 ({ {VAR62{1'b0}}, VAR18 [(VAR3+1)*VAR63-1: VAR3*VAR63] }),
.VAR17 ({ 1'b0, VAR65[VAR27 - 1:0], {VAR29{1'b0}} }),
.VAR64 (4'b0),
.VAR60 (VAR67),
.VAR35 (1'b1),
.VAR72 (1'b1),
.VAR6 (1'b0),
.VAR47 (1'b0),
.VAR73 (VAR46)
);
end
endgenerate
endmodule | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/ip_top/iodelay_ctrl.v | 7,545 | module MODULE1 #
(
parameter VAR27 = 100, parameter VAR34 = "VAR33", parameter VAR7 = "VAR30", parameter VAR20 = 1 )
(
input VAR6,
input VAR10,
input VAR37,
input VAR18,
output VAR31
);
localparam VAR5 = 15;
wire VAR29;
wire VAR3;
wire VAR17;
reg [VAR5-1:0] VAR24 ;
wire VAR8;
wire VAR23;
assign VAR23 = VAR20 ? ~VAR18: VAR18;
generate
if (VAR7 == "VAR30") begin: VAR32
VAR26 #
(
.VAR1 ("VAR19"),
.VAR38 ("VAR4")
)
VAR2
(
.VAR21 (VAR6),
.VAR25 (VAR10),
.VAR16 (VAR3)
);
end else if (VAR7 == "VAR36") begin : VAR13
VAR28 #
(
.VAR38 ("VAR4")
)
VAR2
(
.VAR21 (VAR37),
.VAR16 (VAR3)
);
end
endgenerate
VAR14 VAR22
(
.VAR16 (VAR29),
.VAR21 (VAR3)
);
assign VAR8 = VAR23;
always @(posedge VAR29 or posedge VAR8)
if (VAR8)
end
else
assign VAR17 = VAR24[VAR5-1];
VAR12 VAR35
(
.VAR11 (VAR31),
.VAR9 (VAR29),
.VAR15 (VAR17)
);
endmodule | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/yacc/shifter.v | 6,135 | module
MODULE1(input [31:0] VAR10,
output reg [31:0] VAR8,
input [1:0] VAR3,
input [4:0] VAR1);
localparam [1:0] VAR5=VAR2,
VAR7=VAR4,
VAR6=VAR9;
always @ (*) begin if (!VAR3[1] ) begin
case (VAR1[4:0] )
5'b00000: VAR8=VAR10;
5'b00001: VAR8={VAR10[30:0],1'b0};
5'b00010: VAR8={VAR10[29:0],2'b00};
5'b00011: VAR8={VAR10[28:0],3'b000};
5'b00100: VAR8={VAR10[27:0],4'b0000};
5'b00101: VAR8={VAR10[26:0],5'b00000};
5'b00110: VAR8={VAR10[25:0],6'b000000};
5'b00111: VAR8={VAR10[24:0],7'b0000000};
5'b01000: VAR8={VAR10[23:0],8'b00000000};
5'b01001: VAR8={VAR10[22:0],9'b000000000};
5'b01010: VAR8={VAR10[21:0],10'b0000000000};
5'b01011: VAR8={VAR10[20:0],11'b00000000000};
5'b01100: VAR8={VAR10[19:0],12'b000000000000};
5'b01101: VAR8={VAR10[18:0],13'b0000000000000};
5'b01110: VAR8={VAR10[17:0],14'b00000000000000};
5'b01111: VAR8={VAR10[16:0],15'b000000000000000};
5'b10000: VAR8={VAR10[15:0],16'b0000000000000000};
5'b10001: VAR8={VAR10[14:0],16'b0000000000000000,1'b0};
5'b10010: VAR8={VAR10[13:0],16'b0000000000000000,2'b00};
5'b10011: VAR8={VAR10[12:0],16'b0000000000000000,3'b000};
5'b10100: VAR8={VAR10[11:0],16'b0000000000000000,4'b0000};
5'b10101: VAR8={VAR10[10:0],16'b0000000000000000,5'b00000};
5'b10110: VAR8={VAR10[9:0],16'b0000000000000000,6'b000000};
5'b10111: VAR8={VAR10[8:0],16'b0000000000000000,7'b0000000};
5'b11000: VAR8={VAR10[7:0],16'b0000000000000000,8'b00000000};
5'b11001: VAR8={VAR10[6:0],16'b0000000000000000,9'b000000000};
5'b11010: VAR8={VAR10[5:0],16'b0000000000000000,10'b0000000000};
5'b11011: VAR8={VAR10[4:0],16'b0000000000000000,11'b00000000000};
5'b11100: VAR8={VAR10[3:0],16'b0000000000000000,12'b000000000000};
5'b11101: VAR8={VAR10[2:0],16'b0000000000000000,13'b0000000000000};
5'b11110: VAR8={VAR10[1:0],16'b0000000000000000,14'b00000000000000};
5'b11111: VAR8={VAR10[0],16'b0000000000000000,15'b000000000000000};
endcase
end else if (VAR3==VAR4) begin
case (VAR1)
5'b00000: VAR8=VAR10;
5'b00001: VAR8={1'b0,VAR10[31:1]};
5'b00010: VAR8={2'b00,VAR10[31:2]};
5'b00011: VAR8={3'b000,VAR10[31:3]};
5'b00100: VAR8={4'b0000,VAR10[31:4]};
5'b00101: VAR8={5'b00000,VAR10[31:5]};
5'b00110: VAR8={6'b000000,VAR10[31:6]};
5'b00111: VAR8={7'b0000000,VAR10[31:7]};
5'b01000: VAR8={8'b00000000,VAR10[31:8]};
5'b01001: VAR8={9'b000000000,VAR10[31:9]};
5'b01010: VAR8={10'b0000000000,VAR10[31:10]};
5'b01011: VAR8={11'b00000000000,VAR10[31:11]};
5'b01100: VAR8={12'b000000000000,VAR10[31:12]};
5'b01101: VAR8={13'b0000000000000,VAR10[31:13]};
5'b01110: VAR8={14'b00000000000000,VAR10[31:14]};
5'b01111: VAR8={15'b000000000000000,VAR10[31:15]};
5'b10000: VAR8={16'b0000000000000000,VAR10[31:16]};
5'b10001: VAR8={16'b0000000000000000,1'b0,VAR10[31:17]};
5'b10010: VAR8={16'b0000000000000000,2'b00,VAR10[31:18]};
5'b10011: VAR8={16'b0000000000000000,3'b000,VAR10[31:19]};
5'b10100: VAR8={16'b0000000000000000,4'b0000,VAR10[31:20]};
5'b10101: VAR8={16'b0000000000000000,5'b00000,VAR10[31:21]};
5'b10110: VAR8={16'b0000000000000000,6'b000000,VAR10[31:22]};
5'b10111: VAR8={16'b0000000000000000,7'b0000000,VAR10[31:23]};
5'b11000: VAR8={16'b0000000000000000,8'b00000000,VAR10[31:24]};
5'b11001: VAR8={16'b0000000000000000,9'b000000000,VAR10[31:25]};
5'b11010: VAR8={16'b0000000000000000,10'b0000000000,VAR10[31:26]};
5'b11011: VAR8={16'b0000000000000000,11'b00000000000,VAR10[31:27]};
5'b11100: VAR8={16'b0000000000000000,12'b000000000000,VAR10[31:28]};
5'b11101: VAR8={16'b0000000000000000,13'b0000000000000,VAR10[31:29]};
5'b11110: VAR8={16'b0000000000000000,14'b00000000000000,VAR10[31:30]};
5'b11111: VAR8={16'b0000000000000000,15'b000000000000000,VAR10[31:31]};
endcase
end else begin case (VAR1)
5'b00000: VAR8=VAR10;
5'b00001: VAR8={VAR10[31],VAR10[31:1]};
5'b00010: VAR8={{2{VAR10[31]}},VAR10[31:2]};
5'b00011: VAR8={{3{VAR10[31]}},VAR10[31:3]};
5'b00100: VAR8={{4{VAR10[31]}},VAR10[31:4]};
5'b00101: VAR8={{5{VAR10[31]}},VAR10[31:5]};
5'b00110: VAR8={{6{VAR10[31]}},VAR10[31:6]};
5'b00111: VAR8={{7{VAR10[31]}},VAR10[31:7]};
5'b01000: VAR8={{8{VAR10[31]}},VAR10[31:8]};
5'b01001: VAR8={{9{VAR10[31]}},VAR10[31:9]};
5'b01010: VAR8={{10{VAR10[31]}},VAR10[31:10]};
5'b01011: VAR8={{11{VAR10[31]}},VAR10[31:11]};
5'b01100: VAR8={{12{VAR10[31]}},VAR10[31:12]};
5'b01101: VAR8={{13{VAR10[31]}},VAR10[31:13]};
5'b01110: VAR8={{14{VAR10[31]}},VAR10[31:14]};
5'b01111: VAR8={{15{VAR10[31]}},VAR10[31:15]};
5'b10000: VAR8={{16{VAR10[31]}},VAR10[31:16]};
5'b10001: VAR8={{17{VAR10[31]}},VAR10[31:17]};
5'b10010: VAR8={{18{VAR10[31]}},VAR10[31:18]};
5'b10011: VAR8={{19{VAR10[31]}},VAR10[31:19]};
5'b10100: VAR8={{20{VAR10[31]}},VAR10[31:20]};
5'b10101: VAR8={{21{VAR10[31]}},VAR10[31:21]};
5'b10110: VAR8={{22{VAR10[31]}},VAR10[31:22]};
5'b10111: VAR8={{23{VAR10[31]}},VAR10[31:23]};
5'b11000: VAR8={{24{VAR10[31]}},VAR10[31:24]};
5'b11001: VAR8={{25{VAR10[31]}},VAR10[31:25]};
5'b11010: VAR8={{26{VAR10[31]}},VAR10[31:26]};
5'b11011: VAR8={{27{VAR10[31]}},VAR10[31:27]};
5'b11100: VAR8={{28{VAR10[31]}},VAR10[31:28]};
5'b11101: VAR8={{29{VAR10[31]}},VAR10[31:29]};
5'b11110: VAR8={{30{VAR10[31]}},VAR10[31:30]};
5'b11111: VAR8={{31{VAR10[31]}},VAR10[31:31]};
endcase
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai.pp.blackbox.v | 1,306 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR3 ,
VAR4 ,
VAR1,
VAR2
);
output VAR5 ;
input VAR6 ;
input VAR3 ;
input VAR4 ;
input VAR1;
input VAR2;
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/system_mm_interconnect_1.v | 16,432 | module MODULE1 (
input wire VAR93, input wire VAR85, input wire [29:0] VAR103, output wire VAR86, input wire [0:0] VAR91, input wire [7:0] VAR23, input wire VAR3, output wire [63:0] VAR75, output wire VAR48, input wire VAR88, input wire [63:0] VAR4, input wire VAR96, output wire [3:0] VAR60, output wire VAR7, output wire VAR13, input wire [63:0] VAR34, output wire [63:0] VAR18, output wire [7:0] VAR56, input wire VAR68, input wire VAR37 );
wire VAR47; wire [3:0] VAR74; wire [63:0] VAR27; wire [29:0] VAR17; wire VAR9; wire VAR45; wire VAR90; wire [63:0] VAR14; wire VAR39; wire [7:0] VAR80; wire VAR49;
VAR82 #(
.VAR98 (30),
.VAR66 (64),
.VAR5 (1),
.VAR70 (8),
.VAR53 (30),
.VAR83 (4),
.VAR58 (1),
.VAR15 (1),
.VAR55 (0),
.VAR16 (0),
.VAR10 (0),
.VAR6 (1),
.VAR2 (1),
.VAR89 (1),
.VAR87 (0),
.VAR19 (0),
.VAR92 (8),
.VAR1 (1),
.VAR28 (0),
.VAR40 (0),
.VAR8 (0),
.VAR73 (0),
.VAR22 (0)
) VAR69 (
.clk (VAR93), .reset (VAR85), .VAR59 (VAR17), .VAR42 (VAR74), .VAR99 (VAR90), .VAR81 (VAR45), .VAR35 (VAR47), .VAR95 (VAR49), .VAR52 (VAR80), .VAR71 (VAR14), .VAR65 (VAR27), .VAR43 (VAR9), .VAR36 (VAR39), .VAR54 (VAR103), .VAR38 (VAR86), .VAR57 (VAR91), .VAR21 (VAR23), .VAR61 (VAR3), .VAR20 (VAR75), .VAR24 (VAR48), .VAR84 (VAR88), .VAR12 (VAR4), .VAR11 (VAR96), .VAR79 (1'b0), .VAR26 (1'b0), .VAR62 (1'b0), .VAR102 (1'b0), .VAR63 (), .VAR46 (1'b1), .VAR97 (2'b00), .VAR41 (), .VAR94 (), .VAR78 (1'b0), .VAR29 (1'b0), .VAR72 () );
VAR33 #(
.VAR98 (4),
.VAR66 (64),
.VAR44 (64),
.VAR5 (1),
.VAR70 (8),
.VAR51 (8),
.VAR53 (30),
.VAR83 (4),
.VAR67 (0),
.VAR2 (1),
.VAR89 (1),
.VAR30 (0),
.VAR87 (0),
.VAR19 (0),
.VAR92 (8),
.VAR1 (0),
.VAR28 (0),
.VAR40 (0),
.VAR8 (0),
.VAR25 (0),
.VAR101 (0),
.VAR100 (1),
.VAR31 (0),
.VAR77 (0),
.VAR50 (0)
) VAR32 (
.clk (VAR93), .reset (VAR85), .VAR59 (VAR17), .VAR42 (VAR74), .VAR99 (VAR90), .VAR81 (VAR45), .VAR35 (VAR47), .VAR95 (VAR49), .VAR52 (VAR80), .VAR71 (VAR14), .VAR65 (VAR27), .VAR43 (VAR9), .VAR36 (VAR39), .VAR54 (VAR60), .VAR84 (VAR7), .VAR61 (VAR13), .VAR20 (VAR34), .VAR12 (VAR18), .VAR21 (VAR56), .VAR24 (VAR68), .VAR38 (VAR37), .VAR26 (), .VAR79 (), .VAR57 (), .VAR76 (), .VAR102 (), .VAR62 (), .VAR46 (), .VAR63 (1'b0), .VAR11 (), .VAR64 (), .VAR97 (), .VAR41 (2'b00), .VAR94 (1'b0), .VAR78 (), .VAR29 (), .VAR72 (1'b0) );
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b_2.v | 2,127 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR6 ,
VAR8,
VAR2,
VAR5 ,
VAR7
);
output VAR9 ;
input VAR3 ;
input VAR6 ;
input VAR8;
input VAR2;
input VAR5 ;
input VAR7 ;
VAR1 VAR4 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR9 ,
VAR3 ,
VAR6
);
output VAR9 ;
input VAR3 ;
input VAR6;
supply1 VAR8;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR7 ;
VAR1 VAR4 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/synth/axi_traffic_gen_0.v | 15,178 | module MODULE1 (
VAR36,
VAR186,
VAR99,
VAR134,
VAR104,
VAR272,
VAR296,
VAR74,
VAR240,
VAR204,
VAR270,
VAR295,
VAR263,
VAR15,
VAR32
);
input wire VAR36;
input wire VAR186;
output wire [31 : 0] VAR99;
output wire [2 : 0] VAR134;
output wire VAR104;
input wire VAR272;
output wire [31 : 0] VAR296;
output wire [3 : 0] VAR74;
output wire VAR240;
input wire VAR204;
input wire [1 : 0] VAR270;
input wire VAR295;
output wire VAR263;
output wire VAR15;
output wire [31 : 0] VAR32;
VAR255 #(
.VAR287("VAR88"),
.VAR285('VAR100),
.VAR264('VAR19),
.VAR237(1),
.VAR170(0),
.VAR30(32),
.VAR217(8),
.VAR69(8),
.VAR40(1),
.VAR129(1),
.VAR183(32),
.VAR248(8),
.VAR275(8),
.VAR37(1),
.VAR115(1),
.VAR288(0),
.VAR280(0),
.VAR54(32),
.VAR189(8),
.VAR33(8),
.VAR304(8),
.VAR167(0),
.VAR286(0),
.VAR222(0),
.VAR97(0),
.VAR68(1),
.VAR302(0),
.VAR23(0),
.VAR51(1),
.VAR95(0),
.VAR87(0),
.VAR94(16),
.VAR91(1),
.VAR133(0),
.VAR7('VAR158),
.VAR38('VAR80),
.VAR181('VAR241),
.VAR242('VAR161),
.VAR4(0),
.VAR188(1),
.VAR12(1),
.VAR229(1),
.VAR152(3),
.VAR159(3),
.VAR212(256),
.VAR101(16),
.VAR225("VAR111.VAR44"),
.VAR93("VAR271.VAR44"),
.VAR52("VAR63.VAR44"),
.VAR235("VAR41.VAR44"),
.VAR192(16),
.VAR283(4),
.VAR281(256),
.VAR72(265000),
.VAR82('VAR135),
.VAR21('VAR100),
.VAR261('VAR142),
.VAR113('VAR42),
.VAR213('VAR195),
.VAR267('VAR26),
.VAR313('VAR282),
.VAR157('VAR96),
.VAR118('VAR179),
.VAR293('VAR123),
.VAR256('VAR185),
.VAR143("VAR227.VAR44"),
.VAR290("VAR254"),
.VAR258("VAR254"),
.VAR110("VAR254"),
.VAR244("VAR162.VAR44"),
.VAR102("VAR199.VAR44")
) VAR119 (
.VAR36(VAR36),
.VAR186(VAR186),
.VAR210(1'VAR131),
.VAR307(1'VAR131),
.VAR305(1'VAR131),
.VAR253(32'VAR131),
.VAR251(8'VAR131),
.VAR79(3'VAR131),
.VAR306(2'VAR131),
.VAR107(1'VAR131),
.VAR273(4'VAR131),
.VAR298(3'VAR131),
.VAR109(4'VAR131),
.VAR315(8'VAR131),
.VAR214(1'VAR131),
.VAR218(),
.VAR128(1'VAR131),
.VAR182(32'VAR131),
.VAR25(4'VAR131),
.VAR24(1'VAR131),
.VAR53(),
.VAR49(),
.VAR236(),
.VAR262(),
.VAR259(1'VAR131),
.VAR75(1'VAR131),
.VAR64(32'VAR131),
.VAR34(8'VAR131),
.VAR311(3'VAR131),
.VAR190(2'VAR131),
.VAR228(1'VAR131),
.VAR137(4'VAR131),
.VAR5(3'VAR131),
.VAR202(4'VAR131),
.VAR1(8'VAR131),
.VAR139(1'VAR131),
.VAR117(),
.VAR200(),
.VAR9(),
.VAR216(),
.VAR292(),
.VAR136(),
.VAR257(1'VAR131),
.VAR309(),
.VAR153(),
.VAR125(),
.VAR266(),
.VAR86(),
.VAR60(),
.VAR66(),
.VAR122(),
.VAR31(),
.VAR193(),
.VAR16(),
.VAR90(1'VAR131),
.VAR171(),
.VAR184(),
.VAR191(),
.VAR89(),
.VAR81(1'VAR131),
.VAR274(1'VAR131),
.VAR268(2'VAR131),
.VAR108(1'VAR131),
.VAR13(),
.VAR48(),
.VAR84(),
.VAR35(),
.VAR147(),
.VAR231(),
.VAR149(),
.VAR208(),
.VAR6(),
.VAR223(),
.VAR163(),
.VAR238(),
.VAR197(1'VAR131),
.VAR300(1'VAR131),
.VAR130(1'VAR131),
.VAR233(32'VAR131),
.VAR146(2'VAR131),
.VAR173(1'VAR131),
.VAR10(),
.VAR284(1'VAR308),
.VAR71(),
.VAR294(),
.VAR176(),
.VAR67(),
.VAR77(),
.VAR78(),
.VAR234(),
.VAR29(),
.VAR187(),
.VAR175(1'VAR131),
.VAR194(1'VAR131),
.VAR127(32'VAR131),
.VAR59(4'VAR83),
.VAR221(4'VAR83),
.VAR310(8'VAR131),
.VAR18(8'VAR131),
.VAR219(8'VAR131),
.VAR276(),
.VAR277(),
.VAR150(1'VAR131),
.VAR232(1'VAR131),
.VAR105(32'VAR131),
.VAR121(4'VAR83),
.VAR124(4'VAR83),
.VAR114(8'VAR131),
.VAR299(8'VAR131),
.VAR46(8'VAR131),
.VAR207(1'VAR308),
.VAR28(),
.VAR132(),
.VAR98(),
.VAR249(),
.VAR138(),
.VAR265(),
.VAR180(),
.VAR245(),
.VAR206(),
.VAR211(),
.VAR99(VAR99),
.VAR134(VAR134),
.VAR104(VAR104),
.VAR272(VAR272),
.VAR296(VAR296),
.VAR74(VAR74),
.VAR240(VAR240),
.VAR204(VAR204),
.VAR270(VAR270),
.VAR295(VAR295),
.VAR263(VAR263),
.VAR250(),
.VAR154(),
.VAR164(1'VAR131),
.VAR247(32'VAR131),
.VAR215(1'VAR131),
.VAR169(2'VAR131),
.VAR297(),
.VAR252(),
.VAR151(),
.VAR224(),
.VAR14(1'VAR131),
.VAR39(),
.VAR220(),
.VAR269(),
.VAR57(1'VAR131),
.VAR62(2'VAR131),
.VAR198(1'VAR131),
.VAR140(),
.VAR174(),
.VAR126(),
.VAR226(1'VAR131),
.VAR160(32'VAR131),
.VAR312(1'VAR131),
.VAR56(2'VAR131),
.VAR8(),
.VAR314(),
.VAR3(),
.VAR246(),
.VAR92(1'VAR131),
.VAR168(),
.VAR106(),
.VAR27(),
.VAR61(1'VAR131),
.VAR11(2'VAR131),
.VAR205(1'VAR131),
.VAR155(),
.VAR243(),
.VAR145(),
.VAR196(1'VAR131),
.VAR239(32'VAR131),
.VAR116(1'VAR131),
.VAR230(2'VAR131),
.VAR260(),
.VAR20(),
.VAR201(),
.VAR55(),
.VAR148(1'VAR131),
.VAR85(),
.VAR289(),
.VAR47(),
.VAR301(1'VAR131),
.VAR178(2'VAR131),
.VAR209(1'VAR131),
.VAR43(),
.VAR76(),
.VAR58(),
.VAR279(1'VAR131),
.VAR172(32'VAR131),
.VAR203(1'VAR131),
.VAR166(2'VAR131),
.VAR22(),
.VAR112(),
.VAR103(),
.VAR177(),
.VAR17(1'VAR131),
.VAR156(),
.VAR291(),
.VAR45(),
.VAR65(1'VAR131),
.VAR141(2'VAR131),
.VAR278(1'VAR131),
.VAR50(),
.VAR144(),
.VAR303(),
.VAR70(1'VAR131),
.VAR2(32'VAR131),
.VAR120(1'VAR131),
.VAR165(2'VAR131),
.VAR73(),
.VAR15(VAR15),
.VAR32(VAR32)
);
endmodule | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_statisticalInformation_1.v | 2,313 | module MODULE1 (
address,
VAR6,
clk,
VAR1,
VAR4,
VAR3,
VAR2,
VAR8
)
;
output [ 7: 0] VAR2;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR1;
input VAR4;
input [ 31: 0] VAR3;
wire VAR7;
reg [ 7: 0] VAR9;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR5;
wire [ 31: 0] VAR8;
assign VAR7 = 1;
assign VAR5 = {8 {(address == 0)}} & VAR9;
always @(posedge clk or negedge VAR1)
begin
if (VAR1 == 0)
VAR9 <= 0;
end
else if (VAR6 && ~VAR4 && (address == 0))
VAR9 <= VAR3[7 : 0];
end
assign VAR8 = {32'b0 | VAR5};
assign VAR2 = VAR9;
endmodule | gpl-3.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/sync_block.v | 3,601 | module MODULE1 #(
parameter VAR8 = 2'b00
)
(
input clk, input VAR5, output VAR9 );
wire VAR3;
wire VAR12;
VAR4 #(
.VAR10 (VAR8[0])
) VAR6 (
.VAR1 (clk),
.VAR11 (VAR5),
.VAR2 (VAR3)
);
VAR4 #(
.VAR10 (VAR8[1])
) VAR7 (
.VAR1 (clk),
.VAR11 (VAR3),
.VAR2 (VAR12)
);
assign VAR9 = VAR12;
endmodule | mit |
Rmin1995/NoC | mux1024to1.v | 55,011 | module MODULE1(output [0:VAR5-1]VAR3,
input [0:9]select,
input [0:VAR2-1]VAR4
);
genvar VAR1;
assign VAR3 = (
select[0:9] == 10'd0 ? VAR6[0] :
select[0:9] == 10'd1 ? VAR6[1] :
select[0:9] == 10'd2 ? VAR6[2] :
select[0:9] == 10'd3 ? VAR6[3] :
select[0:9] == 10'd4 ? VAR6[4] :
select[0:9] == 10'd5 ? VAR6[5] :
select[0:9] == 10'd6 ? VAR6[6] :
select[0:9] == 10'd7 ? VAR6[7] :
select[0:9] == 10'd8 ? VAR6[8] :
select[0:9] == 10'd9 ? VAR6[9] :
select[0:9] == 10'd10 ? VAR6[10] :
select[0:9] == 10'd11 ? VAR6[11] :
select[0:9] == 10'd12 ? VAR6[12] :
select[0:9] == 10'd13 ? VAR6[13] :
select[0:9] == 10'd14 ? VAR6[14] :
select[0:9] == 10'd15 ? VAR6[15] :
select[0:9] == 10'd16 ? VAR6[16] :
select[0:9] == 10'd17 ? VAR6[17] :
select[0:9] == 10'd18 ? VAR6[18] :
select[0:9] == 10'd19 ? VAR6[19] :
select[0:9] == 10'd20 ? VAR6[20] :
select[0:9] == 10'd21 ? VAR6[21] :
select[0:9] == 10'd22 ? VAR6[22] :
select[0:9] == 10'd23 ? VAR6[23] :
select[0:9] == 10'd24 ? VAR6[24] :
select[0:9] == 10'd25 ? VAR6[25] :
select[0:9] == 10'd26 ? VAR6[26] :
select[0:9] == 10'd27 ? VAR6[27] :
select[0:9] == 10'd28 ? VAR6[28] :
select[0:9] == 10'd29 ? VAR6[29] :
select[0:9] == 10'd30 ? VAR6[30] :
select[0:9] == 10'd31 ? VAR6[31] :
select[0:9] == 10'd32 ? VAR6[32] :
select[0:9] == 10'd33 ? VAR6[33] :
select[0:9] == 10'd34 ? VAR6[34] :
select[0:9] == 10'd35 ? VAR6[35] :
select[0:9] == 10'd36 ? VAR6[36] :
select[0:9] == 10'd37 ? VAR6[37] :
select[0:9] == 10'd38 ? VAR6[38] :
select[0:9] == 10'd39 ? VAR6[39] :
select[0:9] == 10'd40 ? VAR6[40] :
select[0:9] == 10'd41 ? VAR6[41] :
select[0:9] == 10'd42 ? VAR6[42] :
select[0:9] == 10'd43 ? VAR6[43] :
select[0:9] == 10'd44 ? VAR6[44] :
select[0:9] == 10'd45 ? VAR6[45] :
select[0:9] == 10'd46 ? VAR6[46] :
select[0:9] == 10'd47 ? VAR6[47] :
select[0:9] == 10'd48 ? VAR6[48] :
select[0:9] == 10'd49 ? VAR6[49] :
select[0:9] == 10'd50 ? VAR6[50] :
select[0:9] == 10'd51 ? VAR6[51] :
select[0:9] == 10'd52 ? VAR6[52] :
select[0:9] == 10'd53 ? VAR6[53] :
select[0:9] == 10'd54 ? VAR6[54] :
select[0:9] == 10'd55 ? VAR6[55] :
select[0:9] == 10'd56 ? VAR6[56] :
select[0:9] == 10'd57 ? VAR6[57] :
select[0:9] == 10'd58 ? VAR6[58] :
select[0:9] == 10'd59 ? VAR6[59] :
select[0:9] == 10'd60 ? VAR6[60] :
select[0:9] == 10'd61 ? VAR6[61] :
select[0:9] == 10'd62 ? VAR6[62] :
select[0:9] == 10'd63 ? VAR6[63] :
select[0:9] == 10'd64 ? VAR6[64] :
select[0:9] == 10'd65 ? VAR6[65] :
select[0:9] == 10'd66 ? VAR6[66] :
select[0:9] == 10'd67 ? VAR6[67] :
select[0:9] == 10'd68 ? VAR6[68] :
select[0:9] == 10'd69 ? VAR6[69] :
select[0:9] == 10'd70 ? VAR6[70] :
select[0:9] == 10'd71 ? VAR6[71] :
select[0:9] == 10'd72 ? VAR6[72] :
select[0:9] == 10'd73 ? VAR6[73] :
select[0:9] == 10'd74 ? VAR6[74] :
select[0:9] == 10'd75 ? VAR6[75] :
select[0:9] == 10'd76 ? VAR6[76] :
select[0:9] == 10'd77 ? VAR6[77] :
select[0:9] == 10'd78 ? VAR6[78] :
select[0:9] == 10'd79 ? VAR6[79] :
select[0:9] == 10'd80 ? VAR6[80] :
select[0:9] == 10'd81 ? VAR6[81] :
select[0:9] == 10'd82 ? VAR6[82] :
select[0:9] == 10'd83 ? VAR6[83] :
select[0:9] == 10'd84 ? VAR6[84] :
select[0:9] == 10'd85 ? VAR6[85] :
select[0:9] == 10'd86 ? VAR6[86] :
select[0:9] == 10'd87 ? VAR6[87] :
select[0:9] == 10'd88 ? VAR6[88] :
select[0:9] == 10'd89 ? VAR6[89] :
select[0:9] == 10'd90 ? VAR6[90] :
select[0:9] == 10'd91 ? VAR6[91] :
select[0:9] == 10'd92 ? VAR6[92] :
select[0:9] == 10'd93 ? VAR6[93] :
select[0:9] == 10'd94 ? VAR6[94] :
select[0:9] == 10'd95 ? VAR6[95] :
select[0:9] == 10'd96 ? VAR6[96] :
select[0:9] == 10'd97 ? VAR6[97] :
select[0:9] == 10'd98 ? VAR6[98] :
select[0:9] == 10'd99 ? VAR6[99] :
select[0:9] == 10'd100 ? VAR6[100] :
select[0:9] == 10'd101 ? VAR6[101] :
select[0:9] == 10'd102 ? VAR6[102] :
select[0:9] == 10'd103 ? VAR6[103] :
select[0:9] == 10'd104 ? VAR6[104] :
select[0:9] == 10'd105 ? VAR6[105] :
select[0:9] == 10'd106 ? VAR6[106] :
select[0:9] == 10'd107 ? VAR6[107] :
select[0:9] == 10'd108 ? VAR6[108] :
select[0:9] == 10'd109 ? VAR6[109] :
select[0:9] == 10'd110 ? VAR6[110] :
select[0:9] == 10'd111 ? VAR6[111] :
select[0:9] == 10'd112 ? VAR6[112] :
select[0:9] == 10'd113 ? VAR6[113] :
select[0:9] == 10'd114 ? VAR6[114] :
select[0:9] == 10'd115 ? VAR6[115] :
select[0:9] == 10'd116 ? VAR6[116] :
select[0:9] == 10'd117 ? VAR6[117] :
select[0:9] == 10'd118 ? VAR6[118] :
select[0:9] == 10'd119 ? VAR6[119] :
select[0:9] == 10'd120 ? VAR6[120] :
select[0:9] == 10'd121 ? VAR6[121] :
select[0:9] == 10'd122 ? VAR6[122] :
select[0:9] == 10'd123 ? VAR6[123] :
select[0:9] == 10'd124 ? VAR6[124] :
select[0:9] == 10'd125 ? VAR6[125] :
select[0:9] == 10'd126 ? VAR6[126] :
select[0:9] == 10'd127 ? VAR6[127] :
select[0:9] == 10'd128 ? VAR6[128] :
select[0:9] == 10'd129 ? VAR6[129] :
select[0:9] == 10'd130 ? VAR6[130] :
select[0:9] == 10'd131 ? VAR6[131] :
select[0:9] == 10'd132 ? VAR6[132] :
select[0:9] == 10'd133 ? VAR6[133] :
select[0:9] == 10'd134 ? VAR6[134] :
select[0:9] == 10'd135 ? VAR6[135] :
select[0:9] == 10'd136 ? VAR6[136] :
select[0:9] == 10'd137 ? VAR6[137] :
select[0:9] == 10'd138 ? VAR6[138] :
select[0:9] == 10'd139 ? VAR6[139] :
select[0:9] == 10'd140 ? VAR6[140] :
select[0:9] == 10'd141 ? VAR6[141] :
select[0:9] == 10'd142 ? VAR6[142] :
select[0:9] == 10'd143 ? VAR6[143] :
select[0:9] == 10'd144 ? VAR6[144] :
select[0:9] == 10'd145 ? VAR6[145] :
select[0:9] == 10'd146 ? VAR6[146] :
select[0:9] == 10'd147 ? VAR6[147] :
select[0:9] == 10'd148 ? VAR6[148] :
select[0:9] == 10'd149 ? VAR6[149] :
select[0:9] == 10'd150 ? VAR6[150] :
select[0:9] == 10'd151 ? VAR6[151] :
select[0:9] == 10'd152 ? VAR6[152] :
select[0:9] == 10'd153 ? VAR6[153] :
select[0:9] == 10'd154 ? VAR6[154] :
select[0:9] == 10'd155 ? VAR6[155] :
select[0:9] == 10'd156 ? VAR6[156] :
select[0:9] == 10'd157 ? VAR6[157] :
select[0:9] == 10'd158 ? VAR6[158] :
select[0:9] == 10'd159 ? VAR6[159] :
select[0:9] == 10'd160 ? VAR6[160] :
select[0:9] == 10'd161 ? VAR6[161] :
select[0:9] == 10'd162 ? VAR6[162] :
select[0:9] == 10'd163 ? VAR6[163] :
select[0:9] == 10'd164 ? VAR6[164] :
select[0:9] == 10'd165 ? VAR6[165] :
select[0:9] == 10'd166 ? VAR6[166] :
select[0:9] == 10'd167 ? VAR6[167] :
select[0:9] == 10'd168 ? VAR6[168] :
select[0:9] == 10'd169 ? VAR6[169] :
select[0:9] == 10'd170 ? VAR6[170] :
select[0:9] == 10'd171 ? VAR6[171] :
select[0:9] == 10'd172 ? VAR6[172] :
select[0:9] == 10'd173 ? VAR6[173] :
select[0:9] == 10'd174 ? VAR6[174] :
select[0:9] == 10'd175 ? VAR6[175] :
select[0:9] == 10'd176 ? VAR6[176] :
select[0:9] == 10'd177 ? VAR6[177] :
select[0:9] == 10'd178 ? VAR6[178] :
select[0:9] == 10'd179 ? VAR6[179] :
select[0:9] == 10'd180 ? VAR6[180] :
select[0:9] == 10'd181 ? VAR6[181] :
select[0:9] == 10'd182 ? VAR6[182] :
select[0:9] == 10'd183 ? VAR6[183] :
select[0:9] == 10'd184 ? VAR6[184] :
select[0:9] == 10'd185 ? VAR6[185] :
select[0:9] == 10'd186 ? VAR6[186] :
select[0:9] == 10'd187 ? VAR6[187] :
select[0:9] == 10'd188 ? VAR6[188] :
select[0:9] == 10'd189 ? VAR6[189] :
select[0:9] == 10'd190 ? VAR6[190] :
select[0:9] == 10'd191 ? VAR6[191] :
select[0:9] == 10'd192 ? VAR6[192] :
select[0:9] == 10'd193 ? VAR6[193] :
select[0:9] == 10'd194 ? VAR6[194] :
select[0:9] == 10'd195 ? VAR6[195] :
select[0:9] == 10'd196 ? VAR6[196] :
select[0:9] == 10'd197 ? VAR6[197] :
select[0:9] == 10'd198 ? VAR6[198] :
select[0:9] == 10'd199 ? VAR6[199] :
select[0:9] == 10'd200 ? VAR6[200] :
select[0:9] == 10'd201 ? VAR6[201] :
select[0:9] == 10'd202 ? VAR6[202] :
select[0:9] == 10'd203 ? VAR6[203] :
select[0:9] == 10'd204 ? VAR6[204] :
select[0:9] == 10'd205 ? VAR6[205] :
select[0:9] == 10'd206 ? VAR6[206] :
select[0:9] == 10'd207 ? VAR6[207] :
select[0:9] == 10'd208 ? VAR6[208] :
select[0:9] == 10'd209 ? VAR6[209] :
select[0:9] == 10'd210 ? VAR6[210] :
select[0:9] == 10'd211 ? VAR6[211] :
select[0:9] == 10'd212 ? VAR6[212] :
select[0:9] == 10'd213 ? VAR6[213] :
select[0:9] == 10'd214 ? VAR6[214] :
select[0:9] == 10'd215 ? VAR6[215] :
select[0:9] == 10'd216 ? VAR6[216] :
select[0:9] == 10'd217 ? VAR6[217] :
select[0:9] == 10'd218 ? VAR6[218] :
select[0:9] == 10'd219 ? VAR6[219] :
select[0:9] == 10'd220 ? VAR6[220] :
select[0:9] == 10'd221 ? VAR6[221] :
select[0:9] == 10'd222 ? VAR6[222] :
select[0:9] == 10'd223 ? VAR6[223] :
select[0:9] == 10'd224 ? VAR6[224] :
select[0:9] == 10'd225 ? VAR6[225] :
select[0:9] == 10'd226 ? VAR6[226] :
select[0:9] == 10'd227 ? VAR6[227] :
select[0:9] == 10'd228 ? VAR6[228] :
select[0:9] == 10'd229 ? VAR6[229] :
select[0:9] == 10'd230 ? VAR6[230] :
select[0:9] == 10'd231 ? VAR6[231] :
select[0:9] == 10'd232 ? VAR6[232] :
select[0:9] == 10'd233 ? VAR6[233] :
select[0:9] == 10'd234 ? VAR6[234] :
select[0:9] == 10'd235 ? VAR6[235] :
select[0:9] == 10'd236 ? VAR6[236] :
select[0:9] == 10'd237 ? VAR6[237] :
select[0:9] == 10'd238 ? VAR6[238] :
select[0:9] == 10'd239 ? VAR6[239] :
select[0:9] == 10'd240 ? VAR6[240] :
select[0:9] == 10'd241 ? VAR6[241] :
select[0:9] == 10'd242 ? VAR6[242] :
select[0:9] == 10'd243 ? VAR6[243] :
select[0:9] == 10'd244 ? VAR6[244] :
select[0:9] == 10'd245 ? VAR6[245] :
select[0:9] == 10'd246 ? VAR6[246] :
select[0:9] == 10'd247 ? VAR6[247] :
select[0:9] == 10'd248 ? VAR6[248] :
select[0:9] == 10'd249 ? VAR6[249] :
select[0:9] == 10'd250 ? VAR6[250] :
select[0:9] == 10'd251 ? VAR6[251] :
select[0:9] == 10'd252 ? VAR6[252] :
select[0:9] == 10'd253 ? VAR6[253] :
select[0:9] == 10'd254 ? VAR6[254] :
select[0:9] == 10'd255 ? VAR6[255] :
select[0:9] == 10'd256 ? VAR6[256] :
select[0:9] == 10'd257 ? VAR6[257] :
select[0:9] == 10'd258 ? VAR6[258] :
select[0:9] == 10'd259 ? VAR6[259] :
select[0:9] == 10'd260 ? VAR6[260] :
select[0:9] == 10'd261 ? VAR6[261] :
select[0:9] == 10'd262 ? VAR6[262] :
select[0:9] == 10'd263 ? VAR6[263] :
select[0:9] == 10'd264 ? VAR6[264] :
select[0:9] == 10'd265 ? VAR6[265] :
select[0:9] == 10'd266 ? VAR6[266] :
select[0:9] == 10'd267 ? VAR6[267] :
select[0:9] == 10'd268 ? VAR6[268] :
select[0:9] == 10'd269 ? VAR6[269] :
select[0:9] == 10'd270 ? VAR6[270] :
select[0:9] == 10'd271 ? VAR6[271] :
select[0:9] == 10'd272 ? VAR6[272] :
select[0:9] == 10'd273 ? VAR6[273] :
select[0:9] == 10'd274 ? VAR6[274] :
select[0:9] == 10'd275 ? VAR6[275] :
select[0:9] == 10'd276 ? VAR6[276] :
select[0:9] == 10'd277 ? VAR6[277] :
select[0:9] == 10'd278 ? VAR6[278] :
select[0:9] == 10'd279 ? VAR6[279] :
select[0:9] == 10'd280 ? VAR6[280] :
select[0:9] == 10'd281 ? VAR6[281] :
select[0:9] == 10'd282 ? VAR6[282] :
select[0:9] == 10'd283 ? VAR6[283] :
select[0:9] == 10'd284 ? VAR6[284] :
select[0:9] == 10'd285 ? VAR6[285] :
select[0:9] == 10'd286 ? VAR6[286] :
select[0:9] == 10'd287 ? VAR6[287] :
select[0:9] == 10'd288 ? VAR6[288] :
select[0:9] == 10'd289 ? VAR6[289] :
select[0:9] == 10'd290 ? VAR6[290] :
select[0:9] == 10'd291 ? VAR6[291] :
select[0:9] == 10'd292 ? VAR6[292] :
select[0:9] == 10'd293 ? VAR6[293] :
select[0:9] == 10'd294 ? VAR6[294] :
select[0:9] == 10'd295 ? VAR6[295] :
select[0:9] == 10'd296 ? VAR6[296] :
select[0:9] == 10'd297 ? VAR6[297] :
select[0:9] == 10'd298 ? VAR6[298] :
select[0:9] == 10'd299 ? VAR6[299] :
select[0:9] == 10'd300 ? VAR6[300] :
select[0:9] == 10'd301 ? VAR6[301] :
select[0:9] == 10'd302 ? VAR6[302] :
select[0:9] == 10'd303 ? VAR6[303] :
select[0:9] == 10'd304 ? VAR6[304] :
select[0:9] == 10'd305 ? VAR6[305] :
select[0:9] == 10'd306 ? VAR6[306] :
select[0:9] == 10'd307 ? VAR6[307] :
select[0:9] == 10'd308 ? VAR6[308] :
select[0:9] == 10'd309 ? VAR6[309] :
select[0:9] == 10'd310 ? VAR6[310] :
select[0:9] == 10'd311 ? VAR6[311] :
select[0:9] == 10'd312 ? VAR6[312] :
select[0:9] == 10'd313 ? VAR6[313] :
select[0:9] == 10'd314 ? VAR6[314] :
select[0:9] == 10'd315 ? VAR6[315] :
select[0:9] == 10'd316 ? VAR6[316] :
select[0:9] == 10'd317 ? VAR6[317] :
select[0:9] == 10'd318 ? VAR6[318] :
select[0:9] == 10'd319 ? VAR6[319] :
select[0:9] == 10'd320 ? VAR6[320] :
select[0:9] == 10'd321 ? VAR6[321] :
select[0:9] == 10'd322 ? VAR6[322] :
select[0:9] == 10'd323 ? VAR6[323] :
select[0:9] == 10'd324 ? VAR6[324] :
select[0:9] == 10'd325 ? VAR6[325] :
select[0:9] == 10'd326 ? VAR6[326] :
select[0:9] == 10'd327 ? VAR6[327] :
select[0:9] == 10'd328 ? VAR6[328] :
select[0:9] == 10'd329 ? VAR6[329] :
select[0:9] == 10'd330 ? VAR6[330] :
select[0:9] == 10'd331 ? VAR6[331] :
select[0:9] == 10'd332 ? VAR6[332] :
select[0:9] == 10'd333 ? VAR6[333] :
select[0:9] == 10'd334 ? VAR6[334] :
select[0:9] == 10'd335 ? VAR6[335] :
select[0:9] == 10'd336 ? VAR6[336] :
select[0:9] == 10'd337 ? VAR6[337] :
select[0:9] == 10'd338 ? VAR6[338] :
select[0:9] == 10'd339 ? VAR6[339] :
select[0:9] == 10'd340 ? VAR6[340] :
select[0:9] == 10'd341 ? VAR6[341] :
select[0:9] == 10'd342 ? VAR6[342] :
select[0:9] == 10'd343 ? VAR6[343] :
select[0:9] == 10'd344 ? VAR6[344] :
select[0:9] == 10'd345 ? VAR6[345] :
select[0:9] == 10'd346 ? VAR6[346] :
select[0:9] == 10'd347 ? VAR6[347] :
select[0:9] == 10'd348 ? VAR6[348] :
select[0:9] == 10'd349 ? VAR6[349] :
select[0:9] == 10'd350 ? VAR6[350] :
select[0:9] == 10'd351 ? VAR6[351] :
select[0:9] == 10'd352 ? VAR6[352] :
select[0:9] == 10'd353 ? VAR6[353] :
select[0:9] == 10'd354 ? VAR6[354] :
select[0:9] == 10'd355 ? VAR6[355] :
select[0:9] == 10'd356 ? VAR6[356] :
select[0:9] == 10'd357 ? VAR6[357] :
select[0:9] == 10'd358 ? VAR6[358] :
select[0:9] == 10'd359 ? VAR6[359] :
select[0:9] == 10'd360 ? VAR6[360] :
select[0:9] == 10'd361 ? VAR6[361] :
select[0:9] == 10'd362 ? VAR6[362] :
select[0:9] == 10'd363 ? VAR6[363] :
select[0:9] == 10'd364 ? VAR6[364] :
select[0:9] == 10'd365 ? VAR6[365] :
select[0:9] == 10'd366 ? VAR6[366] :
select[0:9] == 10'd367 ? VAR6[367] :
select[0:9] == 10'd368 ? VAR6[368] :
select[0:9] == 10'd369 ? VAR6[369] :
select[0:9] == 10'd370 ? VAR6[370] :
select[0:9] == 10'd371 ? VAR6[371] :
select[0:9] == 10'd372 ? VAR6[372] :
select[0:9] == 10'd373 ? VAR6[373] :
select[0:9] == 10'd374 ? VAR6[374] :
select[0:9] == 10'd375 ? VAR6[375] :
select[0:9] == 10'd376 ? VAR6[376] :
select[0:9] == 10'd377 ? VAR6[377] :
select[0:9] == 10'd378 ? VAR6[378] :
select[0:9] == 10'd379 ? VAR6[379] :
select[0:9] == 10'd380 ? VAR6[380] :
select[0:9] == 10'd381 ? VAR6[381] :
select[0:9] == 10'd382 ? VAR6[382] :
select[0:9] == 10'd383 ? VAR6[383] :
select[0:9] == 10'd384 ? VAR6[384] :
select[0:9] == 10'd385 ? VAR6[385] :
select[0:9] == 10'd386 ? VAR6[386] :
select[0:9] == 10'd387 ? VAR6[387] :
select[0:9] == 10'd388 ? VAR6[388] :
select[0:9] == 10'd389 ? VAR6[389] :
select[0:9] == 10'd390 ? VAR6[390] :
select[0:9] == 10'd391 ? VAR6[391] :
select[0:9] == 10'd392 ? VAR6[392] :
select[0:9] == 10'd393 ? VAR6[393] :
select[0:9] == 10'd394 ? VAR6[394] :
select[0:9] == 10'd395 ? VAR6[395] :
select[0:9] == 10'd396 ? VAR6[396] :
select[0:9] == 10'd397 ? VAR6[397] :
select[0:9] == 10'd398 ? VAR6[398] :
select[0:9] == 10'd399 ? VAR6[399] :
select[0:9] == 10'd400 ? VAR6[400] :
select[0:9] == 10'd401 ? VAR6[401] :
select[0:9] == 10'd402 ? VAR6[402] :
select[0:9] == 10'd403 ? VAR6[403] :
select[0:9] == 10'd404 ? VAR6[404] :
select[0:9] == 10'd405 ? VAR6[405] :
select[0:9] == 10'd406 ? VAR6[406] :
select[0:9] == 10'd407 ? VAR6[407] :
select[0:9] == 10'd408 ? VAR6[408] :
select[0:9] == 10'd409 ? VAR6[409] :
select[0:9] == 10'd410 ? VAR6[410] :
select[0:9] == 10'd411 ? VAR6[411] :
select[0:9] == 10'd412 ? VAR6[412] :
select[0:9] == 10'd413 ? VAR6[413] :
select[0:9] == 10'd414 ? VAR6[414] :
select[0:9] == 10'd415 ? VAR6[415] :
select[0:9] == 10'd416 ? VAR6[416] :
select[0:9] == 10'd417 ? VAR6[417] :
select[0:9] == 10'd418 ? VAR6[418] :
select[0:9] == 10'd419 ? VAR6[419] :
select[0:9] == 10'd420 ? VAR6[420] :
select[0:9] == 10'd421 ? VAR6[421] :
select[0:9] == 10'd422 ? VAR6[422] :
select[0:9] == 10'd423 ? VAR6[423] :
select[0:9] == 10'd424 ? VAR6[424] :
select[0:9] == 10'd425 ? VAR6[425] :
select[0:9] == 10'd426 ? VAR6[426] :
select[0:9] == 10'd427 ? VAR6[427] :
select[0:9] == 10'd428 ? VAR6[428] :
select[0:9] == 10'd429 ? VAR6[429] :
select[0:9] == 10'd430 ? VAR6[430] :
select[0:9] == 10'd431 ? VAR6[431] :
select[0:9] == 10'd432 ? VAR6[432] :
select[0:9] == 10'd433 ? VAR6[433] :
select[0:9] == 10'd434 ? VAR6[434] :
select[0:9] == 10'd435 ? VAR6[435] :
select[0:9] == 10'd436 ? VAR6[436] :
select[0:9] == 10'd437 ? VAR6[437] :
select[0:9] == 10'd438 ? VAR6[438] :
select[0:9] == 10'd439 ? VAR6[439] :
select[0:9] == 10'd440 ? VAR6[440] :
select[0:9] == 10'd441 ? VAR6[441] :
select[0:9] == 10'd442 ? VAR6[442] :
select[0:9] == 10'd443 ? VAR6[443] :
select[0:9] == 10'd444 ? VAR6[444] :
select[0:9] == 10'd445 ? VAR6[445] :
select[0:9] == 10'd446 ? VAR6[446] :
select[0:9] == 10'd447 ? VAR6[447] :
select[0:9] == 10'd448 ? VAR6[448] :
select[0:9] == 10'd449 ? VAR6[449] :
select[0:9] == 10'd450 ? VAR6[450] :
select[0:9] == 10'd451 ? VAR6[451] :
select[0:9] == 10'd452 ? VAR6[452] :
select[0:9] == 10'd453 ? VAR6[453] :
select[0:9] == 10'd454 ? VAR6[454] :
select[0:9] == 10'd455 ? VAR6[455] :
select[0:9] == 10'd456 ? VAR6[456] :
select[0:9] == 10'd457 ? VAR6[457] :
select[0:9] == 10'd458 ? VAR6[458] :
select[0:9] == 10'd459 ? VAR6[459] :
select[0:9] == 10'd460 ? VAR6[460] :
select[0:9] == 10'd461 ? VAR6[461] :
select[0:9] == 10'd462 ? VAR6[462] :
select[0:9] == 10'd463 ? VAR6[463] :
select[0:9] == 10'd464 ? VAR6[464] :
select[0:9] == 10'd465 ? VAR6[465] :
select[0:9] == 10'd466 ? VAR6[466] :
select[0:9] == 10'd467 ? VAR6[467] :
select[0:9] == 10'd468 ? VAR6[468] :
select[0:9] == 10'd469 ? VAR6[469] :
select[0:9] == 10'd470 ? VAR6[470] :
select[0:9] == 10'd471 ? VAR6[471] :
select[0:9] == 10'd472 ? VAR6[472] :
select[0:9] == 10'd473 ? VAR6[473] :
select[0:9] == 10'd474 ? VAR6[474] :
select[0:9] == 10'd475 ? VAR6[475] :
select[0:9] == 10'd476 ? VAR6[476] :
select[0:9] == 10'd477 ? VAR6[477] :
select[0:9] == 10'd478 ? VAR6[478] :
select[0:9] == 10'd479 ? VAR6[479] :
select[0:9] == 10'd480 ? VAR6[480] :
select[0:9] == 10'd481 ? VAR6[481] :
select[0:9] == 10'd482 ? VAR6[482] :
select[0:9] == 10'd483 ? VAR6[483] :
select[0:9] == 10'd484 ? VAR6[484] :
select[0:9] == 10'd485 ? VAR6[485] :
select[0:9] == 10'd486 ? VAR6[486] :
select[0:9] == 10'd487 ? VAR6[487] :
select[0:9] == 10'd488 ? VAR6[488] :
select[0:9] == 10'd489 ? VAR6[489] :
select[0:9] == 10'd490 ? VAR6[490] :
select[0:9] == 10'd491 ? VAR6[491] :
select[0:9] == 10'd492 ? VAR6[492] :
select[0:9] == 10'd493 ? VAR6[493] :
select[0:9] == 10'd494 ? VAR6[494] :
select[0:9] == 10'd495 ? VAR6[495] :
select[0:9] == 10'd496 ? VAR6[496] :
select[0:9] == 10'd497 ? VAR6[497] :
select[0:9] == 10'd498 ? VAR6[498] :
select[0:9] == 10'd499 ? VAR6[499] :
select[0:9] == 10'd500 ? VAR6[500] :
select[0:9] == 10'd501 ? VAR6[501] :
select[0:9] == 10'd502 ? VAR6[502] :
select[0:9] == 10'd503 ? VAR6[503] :
select[0:9] == 10'd504 ? VAR6[504] :
select[0:9] == 10'd505 ? VAR6[505] :
select[0:9] == 10'd506 ? VAR6[506] :
select[0:9] == 10'd507 ? VAR6[507] :
select[0:9] == 10'd508 ? VAR6[508] :
select[0:9] == 10'd509 ? VAR6[509] :
select[0:9] == 10'd510 ? VAR6[510] :
select[0:9] == 10'd511 ? VAR6[511] :
select[0:9] == 10'd512 ? VAR6[512] :
select[0:9] == 10'd513 ? VAR6[513] :
select[0:9] == 10'd514 ? VAR6[514] :
select[0:9] == 10'd515 ? VAR6[515] :
select[0:9] == 10'd516 ? VAR6[516] :
select[0:9] == 10'd517 ? VAR6[517] :
select[0:9] == 10'd518 ? VAR6[518] :
select[0:9] == 10'd519 ? VAR6[519] :
select[0:9] == 10'd520 ? VAR6[520] :
select[0:9] == 10'd521 ? VAR6[521] :
select[0:9] == 10'd522 ? VAR6[522] :
select[0:9] == 10'd523 ? VAR6[523] :
select[0:9] == 10'd524 ? VAR6[524] :
select[0:9] == 10'd525 ? VAR6[525] :
select[0:9] == 10'd526 ? VAR6[526] :
select[0:9] == 10'd527 ? VAR6[527] :
select[0:9] == 10'd528 ? VAR6[528] :
select[0:9] == 10'd529 ? VAR6[529] :
select[0:9] == 10'd530 ? VAR6[530] :
select[0:9] == 10'd531 ? VAR6[531] :
select[0:9] == 10'd532 ? VAR6[532] :
select[0:9] == 10'd533 ? VAR6[533] :
select[0:9] == 10'd534 ? VAR6[534] :
select[0:9] == 10'd535 ? VAR6[535] :
select[0:9] == 10'd536 ? VAR6[536] :
select[0:9] == 10'd537 ? VAR6[537] :
select[0:9] == 10'd538 ? VAR6[538] :
select[0:9] == 10'd539 ? VAR6[539] :
select[0:9] == 10'd540 ? VAR6[540] :
select[0:9] == 10'd541 ? VAR6[541] :
select[0:9] == 10'd542 ? VAR6[542] :
select[0:9] == 10'd543 ? VAR6[543] :
select[0:9] == 10'd544 ? VAR6[544] :
select[0:9] == 10'd545 ? VAR6[545] :
select[0:9] == 10'd546 ? VAR6[546] :
select[0:9] == 10'd547 ? VAR6[547] :
select[0:9] == 10'd548 ? VAR6[548] :
select[0:9] == 10'd549 ? VAR6[549] :
select[0:9] == 10'd550 ? VAR6[550] :
select[0:9] == 10'd551 ? VAR6[551] :
select[0:9] == 10'd552 ? VAR6[552] :
select[0:9] == 10'd553 ? VAR6[553] :
select[0:9] == 10'd554 ? VAR6[554] :
select[0:9] == 10'd555 ? VAR6[555] :
select[0:9] == 10'd556 ? VAR6[556] :
select[0:9] == 10'd557 ? VAR6[557] :
select[0:9] == 10'd558 ? VAR6[558] :
select[0:9] == 10'd559 ? VAR6[559] :
select[0:9] == 10'd560 ? VAR6[560] :
select[0:9] == 10'd561 ? VAR6[561] :
select[0:9] == 10'd562 ? VAR6[562] :
select[0:9] == 10'd563 ? VAR6[563] :
select[0:9] == 10'd564 ? VAR6[564] :
select[0:9] == 10'd565 ? VAR6[565] :
select[0:9] == 10'd566 ? VAR6[566] :
select[0:9] == 10'd567 ? VAR6[567] :
select[0:9] == 10'd568 ? VAR6[568] :
select[0:9] == 10'd569 ? VAR6[569] :
select[0:9] == 10'd570 ? VAR6[570] :
select[0:9] == 10'd571 ? VAR6[571] :
select[0:9] == 10'd572 ? VAR6[572] :
select[0:9] == 10'd573 ? VAR6[573] :
select[0:9] == 10'd574 ? VAR6[574] :
select[0:9] == 10'd575 ? VAR6[575] :
select[0:9] == 10'd576 ? VAR6[576] :
select[0:9] == 10'd577 ? VAR6[577] :
select[0:9] == 10'd578 ? VAR6[578] :
select[0:9] == 10'd579 ? VAR6[579] :
select[0:9] == 10'd580 ? VAR6[580] :
select[0:9] == 10'd581 ? VAR6[581] :
select[0:9] == 10'd582 ? VAR6[582] :
select[0:9] == 10'd583 ? VAR6[583] :
select[0:9] == 10'd584 ? VAR6[584] :
select[0:9] == 10'd585 ? VAR6[585] :
select[0:9] == 10'd586 ? VAR6[586] :
select[0:9] == 10'd587 ? VAR6[587] :
select[0:9] == 10'd588 ? VAR6[588] :
select[0:9] == 10'd589 ? VAR6[589] :
select[0:9] == 10'd590 ? VAR6[590] :
select[0:9] == 10'd591 ? VAR6[591] :
select[0:9] == 10'd592 ? VAR6[592] :
select[0:9] == 10'd593 ? VAR6[593] :
select[0:9] == 10'd594 ? VAR6[594] :
select[0:9] == 10'd595 ? VAR6[595] :
select[0:9] == 10'd596 ? VAR6[596] :
select[0:9] == 10'd597 ? VAR6[597] :
select[0:9] == 10'd598 ? VAR6[598] :
select[0:9] == 10'd599 ? VAR6[599] :
select[0:9] == 10'd600 ? VAR6[600] :
select[0:9] == 10'd601 ? VAR6[601] :
select[0:9] == 10'd602 ? VAR6[602] :
select[0:9] == 10'd603 ? VAR6[603] :
select[0:9] == 10'd604 ? VAR6[604] :
select[0:9] == 10'd605 ? VAR6[605] :
select[0:9] == 10'd606 ? VAR6[606] :
select[0:9] == 10'd607 ? VAR6[607] :
select[0:9] == 10'd608 ? VAR6[608] :
select[0:9] == 10'd609 ? VAR6[609] :
select[0:9] == 10'd610 ? VAR6[610] :
select[0:9] == 10'd611 ? VAR6[611] :
select[0:9] == 10'd612 ? VAR6[612] :
select[0:9] == 10'd613 ? VAR6[613] :
select[0:9] == 10'd614 ? VAR6[614] :
select[0:9] == 10'd615 ? VAR6[615] :
select[0:9] == 10'd616 ? VAR6[616] :
select[0:9] == 10'd617 ? VAR6[617] :
select[0:9] == 10'd618 ? VAR6[618] :
select[0:9] == 10'd619 ? VAR6[619] :
select[0:9] == 10'd620 ? VAR6[620] :
select[0:9] == 10'd621 ? VAR6[621] :
select[0:9] == 10'd622 ? VAR6[622] :
select[0:9] == 10'd623 ? VAR6[623] :
select[0:9] == 10'd624 ? VAR6[624] :
select[0:9] == 10'd625 ? VAR6[625] :
select[0:9] == 10'd626 ? VAR6[626] :
select[0:9] == 10'd627 ? VAR6[627] :
select[0:9] == 10'd628 ? VAR6[628] :
select[0:9] == 10'd629 ? VAR6[629] :
select[0:9] == 10'd630 ? VAR6[630] :
select[0:9] == 10'd631 ? VAR6[631] :
select[0:9] == 10'd632 ? VAR6[632] :
select[0:9] == 10'd633 ? VAR6[633] :
select[0:9] == 10'd634 ? VAR6[634] :
select[0:9] == 10'd635 ? VAR6[635] :
select[0:9] == 10'd636 ? VAR6[636] :
select[0:9] == 10'd637 ? VAR6[637] :
select[0:9] == 10'd638 ? VAR6[638] :
select[0:9] == 10'd639 ? VAR6[639] :
select[0:9] == 10'd640 ? VAR6[640] :
select[0:9] == 10'd641 ? VAR6[641] :
select[0:9] == 10'd642 ? VAR6[642] :
select[0:9] == 10'd643 ? VAR6[643] :
select[0:9] == 10'd644 ? VAR6[644] :
select[0:9] == 10'd645 ? VAR6[645] :
select[0:9] == 10'd646 ? VAR6[646] :
select[0:9] == 10'd647 ? VAR6[647] :
select[0:9] == 10'd648 ? VAR6[648] :
select[0:9] == 10'd649 ? VAR6[649] :
select[0:9] == 10'd650 ? VAR6[650] :
select[0:9] == 10'd651 ? VAR6[651] :
select[0:9] == 10'd652 ? VAR6[652] :
select[0:9] == 10'd653 ? VAR6[653] :
select[0:9] == 10'd654 ? VAR6[654] :
select[0:9] == 10'd655 ? VAR6[655] :
select[0:9] == 10'd656 ? VAR6[656] :
select[0:9] == 10'd657 ? VAR6[657] :
select[0:9] == 10'd658 ? VAR6[658] :
select[0:9] == 10'd659 ? VAR6[659] :
select[0:9] == 10'd660 ? VAR6[660] :
select[0:9] == 10'd661 ? VAR6[661] :
select[0:9] == 10'd662 ? VAR6[662] :
select[0:9] == 10'd663 ? VAR6[663] :
select[0:9] == 10'd664 ? VAR6[664] :
select[0:9] == 10'd665 ? VAR6[665] :
select[0:9] == 10'd666 ? VAR6[666] :
select[0:9] == 10'd667 ? VAR6[667] :
select[0:9] == 10'd668 ? VAR6[668] :
select[0:9] == 10'd669 ? VAR6[669] :
select[0:9] == 10'd670 ? VAR6[670] :
select[0:9] == 10'd671 ? VAR6[671] :
select[0:9] == 10'd672 ? VAR6[672] :
select[0:9] == 10'd673 ? VAR6[673] :
select[0:9] == 10'd674 ? VAR6[674] :
select[0:9] == 10'd675 ? VAR6[675] :
select[0:9] == 10'd676 ? VAR6[676] :
select[0:9] == 10'd677 ? VAR6[677] :
select[0:9] == 10'd678 ? VAR6[678] :
select[0:9] == 10'd679 ? VAR6[679] :
select[0:9] == 10'd680 ? VAR6[680] :
select[0:9] == 10'd681 ? VAR6[681] :
select[0:9] == 10'd682 ? VAR6[682] :
select[0:9] == 10'd683 ? VAR6[683] :
select[0:9] == 10'd684 ? VAR6[684] :
select[0:9] == 10'd685 ? VAR6[685] :
select[0:9] == 10'd686 ? VAR6[686] :
select[0:9] == 10'd687 ? VAR6[687] :
select[0:9] == 10'd688 ? VAR6[688] :
select[0:9] == 10'd689 ? VAR6[689] :
select[0:9] == 10'd690 ? VAR6[690] :
select[0:9] == 10'd691 ? VAR6[691] :
select[0:9] == 10'd692 ? VAR6[692] :
select[0:9] == 10'd693 ? VAR6[693] :
select[0:9] == 10'd694 ? VAR6[694] :
select[0:9] == 10'd695 ? VAR6[695] :
select[0:9] == 10'd696 ? VAR6[696] :
select[0:9] == 10'd697 ? VAR6[697] :
select[0:9] == 10'd698 ? VAR6[698] :
select[0:9] == 10'd699 ? VAR6[699] :
select[0:9] == 10'd700 ? VAR6[700] :
select[0:9] == 10'd701 ? VAR6[701] :
select[0:9] == 10'd702 ? VAR6[702] :
select[0:9] == 10'd703 ? VAR6[703] :
select[0:9] == 10'd704 ? VAR6[704] :
select[0:9] == 10'd705 ? VAR6[705] :
select[0:9] == 10'd706 ? VAR6[706] :
select[0:9] == 10'd707 ? VAR6[707] :
select[0:9] == 10'd708 ? VAR6[708] :
select[0:9] == 10'd709 ? VAR6[709] :
select[0:9] == 10'd710 ? VAR6[710] :
select[0:9] == 10'd711 ? VAR6[711] :
select[0:9] == 10'd712 ? VAR6[712] :
select[0:9] == 10'd713 ? VAR6[713] :
select[0:9] == 10'd714 ? VAR6[714] :
select[0:9] == 10'd715 ? VAR6[715] :
select[0:9] == 10'd716 ? VAR6[716] :
select[0:9] == 10'd717 ? VAR6[717] :
select[0:9] == 10'd718 ? VAR6[718] :
select[0:9] == 10'd719 ? VAR6[719] :
select[0:9] == 10'd720 ? VAR6[720] :
select[0:9] == 10'd721 ? VAR6[721] :
select[0:9] == 10'd722 ? VAR6[722] :
select[0:9] == 10'd723 ? VAR6[723] :
select[0:9] == 10'd724 ? VAR6[724] :
select[0:9] == 10'd725 ? VAR6[725] :
select[0:9] == 10'd726 ? VAR6[726] :
select[0:9] == 10'd727 ? VAR6[727] :
select[0:9] == 10'd728 ? VAR6[728] :
select[0:9] == 10'd729 ? VAR6[729] :
select[0:9] == 10'd730 ? VAR6[730] :
select[0:9] == 10'd731 ? VAR6[731] :
select[0:9] == 10'd732 ? VAR6[732] :
select[0:9] == 10'd733 ? VAR6[733] :
select[0:9] == 10'd734 ? VAR6[734] :
select[0:9] == 10'd735 ? VAR6[735] :
select[0:9] == 10'd736 ? VAR6[736] :
select[0:9] == 10'd737 ? VAR6[737] :
select[0:9] == 10'd738 ? VAR6[738] :
select[0:9] == 10'd739 ? VAR6[739] :
select[0:9] == 10'd740 ? VAR6[740] :
select[0:9] == 10'd741 ? VAR6[741] :
select[0:9] == 10'd742 ? VAR6[742] :
select[0:9] == 10'd743 ? VAR6[743] :
select[0:9] == 10'd744 ? VAR6[744] :
select[0:9] == 10'd745 ? VAR6[745] :
select[0:9] == 10'd746 ? VAR6[746] :
select[0:9] == 10'd747 ? VAR6[747] :
select[0:9] == 10'd748 ? VAR6[748] :
select[0:9] == 10'd749 ? VAR6[749] :
select[0:9] == 10'd750 ? VAR6[750] :
select[0:9] == 10'd751 ? VAR6[751] :
select[0:9] == 10'd752 ? VAR6[752] :
select[0:9] == 10'd753 ? VAR6[753] :
select[0:9] == 10'd754 ? VAR6[754] :
select[0:9] == 10'd755 ? VAR6[755] :
select[0:9] == 10'd756 ? VAR6[756] :
select[0:9] == 10'd757 ? VAR6[757] :
select[0:9] == 10'd758 ? VAR6[758] :
select[0:9] == 10'd759 ? VAR6[759] :
select[0:9] == 10'd760 ? VAR6[760] :
select[0:9] == 10'd761 ? VAR6[761] :
select[0:9] == 10'd762 ? VAR6[762] :
select[0:9] == 10'd763 ? VAR6[763] :
select[0:9] == 10'd764 ? VAR6[764] :
select[0:9] == 10'd765 ? VAR6[765] :
select[0:9] == 10'd766 ? VAR6[766] :
select[0:9] == 10'd767 ? VAR6[767] :
select[0:9] == 10'd768 ? VAR6[768] :
select[0:9] == 10'd769 ? VAR6[769] :
select[0:9] == 10'd770 ? VAR6[770] :
select[0:9] == 10'd771 ? VAR6[771] :
select[0:9] == 10'd772 ? VAR6[772] :
select[0:9] == 10'd773 ? VAR6[773] :
select[0:9] == 10'd774 ? VAR6[774] :
select[0:9] == 10'd775 ? VAR6[775] :
select[0:9] == 10'd776 ? VAR6[776] :
select[0:9] == 10'd777 ? VAR6[777] :
select[0:9] == 10'd778 ? VAR6[778] :
select[0:9] == 10'd779 ? VAR6[779] :
select[0:9] == 10'd780 ? VAR6[780] :
select[0:9] == 10'd781 ? VAR6[781] :
select[0:9] == 10'd782 ? VAR6[782] :
select[0:9] == 10'd783 ? VAR6[783] :
select[0:9] == 10'd784 ? VAR6[784] :
select[0:9] == 10'd785 ? VAR6[785] :
select[0:9] == 10'd786 ? VAR6[786] :
select[0:9] == 10'd787 ? VAR6[787] :
select[0:9] == 10'd788 ? VAR6[788] :
select[0:9] == 10'd789 ? VAR6[789] :
select[0:9] == 10'd790 ? VAR6[790] :
select[0:9] == 10'd791 ? VAR6[791] :
select[0:9] == 10'd792 ? VAR6[792] :
select[0:9] == 10'd793 ? VAR6[793] :
select[0:9] == 10'd794 ? VAR6[794] :
select[0:9] == 10'd795 ? VAR6[795] :
select[0:9] == 10'd796 ? VAR6[796] :
select[0:9] == 10'd797 ? VAR6[797] :
select[0:9] == 10'd798 ? VAR6[798] :
select[0:9] == 10'd799 ? VAR6[799] :
select[0:9] == 10'd800 ? VAR6[800] :
select[0:9] == 10'd801 ? VAR6[801] :
select[0:9] == 10'd802 ? VAR6[802] :
select[0:9] == 10'd803 ? VAR6[803] :
select[0:9] == 10'd804 ? VAR6[804] :
select[0:9] == 10'd805 ? VAR6[805] :
select[0:9] == 10'd806 ? VAR6[806] :
select[0:9] == 10'd807 ? VAR6[807] :
select[0:9] == 10'd808 ? VAR6[808] :
select[0:9] == 10'd809 ? VAR6[809] :
select[0:9] == 10'd810 ? VAR6[810] :
select[0:9] == 10'd811 ? VAR6[811] :
select[0:9] == 10'd812 ? VAR6[812] :
select[0:9] == 10'd813 ? VAR6[813] :
select[0:9] == 10'd814 ? VAR6[814] :
select[0:9] == 10'd815 ? VAR6[815] :
select[0:9] == 10'd816 ? VAR6[816] :
select[0:9] == 10'd817 ? VAR6[817] :
select[0:9] == 10'd818 ? VAR6[818] :
select[0:9] == 10'd819 ? VAR6[819] :
select[0:9] == 10'd820 ? VAR6[820] :
select[0:9] == 10'd821 ? VAR6[821] :
select[0:9] == 10'd822 ? VAR6[822] :
select[0:9] == 10'd823 ? VAR6[823] :
select[0:9] == 10'd824 ? VAR6[824] :
select[0:9] == 10'd825 ? VAR6[825] :
select[0:9] == 10'd826 ? VAR6[826] :
select[0:9] == 10'd827 ? VAR6[827] :
select[0:9] == 10'd828 ? VAR6[828] :
select[0:9] == 10'd829 ? VAR6[829] :
select[0:9] == 10'd830 ? VAR6[830] :
select[0:9] == 10'd831 ? VAR6[831] :
select[0:9] == 10'd832 ? VAR6[832] :
select[0:9] == 10'd833 ? VAR6[833] :
select[0:9] == 10'd834 ? VAR6[834] :
select[0:9] == 10'd835 ? VAR6[835] :
select[0:9] == 10'd836 ? VAR6[836] :
select[0:9] == 10'd837 ? VAR6[837] :
select[0:9] == 10'd838 ? VAR6[838] :
select[0:9] == 10'd839 ? VAR6[839] :
select[0:9] == 10'd840 ? VAR6[840] :
select[0:9] == 10'd841 ? VAR6[841] :
select[0:9] == 10'd842 ? VAR6[842] :
select[0:9] == 10'd843 ? VAR6[843] :
select[0:9] == 10'd844 ? VAR6[844] :
select[0:9] == 10'd845 ? VAR6[845] :
select[0:9] == 10'd846 ? VAR6[846] :
select[0:9] == 10'd847 ? VAR6[847] :
select[0:9] == 10'd848 ? VAR6[848] :
select[0:9] == 10'd849 ? VAR6[849] :
select[0:9] == 10'd850 ? VAR6[850] :
select[0:9] == 10'd851 ? VAR6[851] :
select[0:9] == 10'd852 ? VAR6[852] :
select[0:9] == 10'd853 ? VAR6[853] :
select[0:9] == 10'd854 ? VAR6[854] :
select[0:9] == 10'd855 ? VAR6[855] :
select[0:9] == 10'd856 ? VAR6[856] :
select[0:9] == 10'd857 ? VAR6[857] :
select[0:9] == 10'd858 ? VAR6[858] :
select[0:9] == 10'd859 ? VAR6[859] :
select[0:9] == 10'd860 ? VAR6[860] :
select[0:9] == 10'd861 ? VAR6[861] :
select[0:9] == 10'd862 ? VAR6[862] :
select[0:9] == 10'd863 ? VAR6[863] :
select[0:9] == 10'd864 ? VAR6[864] :
select[0:9] == 10'd865 ? VAR6[865] :
select[0:9] == 10'd866 ? VAR6[866] :
select[0:9] == 10'd867 ? VAR6[867] :
select[0:9] == 10'd868 ? VAR6[868] :
select[0:9] == 10'd869 ? VAR6[869] :
select[0:9] == 10'd870 ? VAR6[870] :
select[0:9] == 10'd871 ? VAR6[871] :
select[0:9] == 10'd872 ? VAR6[872] :
select[0:9] == 10'd873 ? VAR6[873] :
select[0:9] == 10'd874 ? VAR6[874] :
select[0:9] == 10'd875 ? VAR6[875] :
select[0:9] == 10'd876 ? VAR6[876] :
select[0:9] == 10'd877 ? VAR6[877] :
select[0:9] == 10'd878 ? VAR6[878] :
select[0:9] == 10'd879 ? VAR6[879] :
select[0:9] == 10'd880 ? VAR6[880] :
select[0:9] == 10'd881 ? VAR6[881] :
select[0:9] == 10'd882 ? VAR6[882] :
select[0:9] == 10'd883 ? VAR6[883] :
select[0:9] == 10'd884 ? VAR6[884] :
select[0:9] == 10'd885 ? VAR6[885] :
select[0:9] == 10'd886 ? VAR6[886] :
select[0:9] == 10'd887 ? VAR6[887] :
select[0:9] == 10'd888 ? VAR6[888] :
select[0:9] == 10'd889 ? VAR6[889] :
select[0:9] == 10'd890 ? VAR6[890] :
select[0:9] == 10'd891 ? VAR6[891] :
select[0:9] == 10'd892 ? VAR6[892] :
select[0:9] == 10'd893 ? VAR6[893] :
select[0:9] == 10'd894 ? VAR6[894] :
select[0:9] == 10'd895 ? VAR6[895] :
select[0:9] == 10'd896 ? VAR6[896] :
select[0:9] == 10'd897 ? VAR6[897] :
select[0:9] == 10'd898 ? VAR6[898] :
select[0:9] == 10'd899 ? VAR6[899] :
select[0:9] == 10'd900 ? VAR6[900] :
select[0:9] == 10'd901 ? VAR6[901] :
select[0:9] == 10'd902 ? VAR6[902] :
select[0:9] == 10'd903 ? VAR6[903] :
select[0:9] == 10'd904 ? VAR6[904] :
select[0:9] == 10'd905 ? VAR6[905] :
select[0:9] == 10'd906 ? VAR6[906] :
select[0:9] == 10'd907 ? VAR6[907] :
select[0:9] == 10'd908 ? VAR6[908] :
select[0:9] == 10'd909 ? VAR6[909] :
select[0:9] == 10'd910 ? VAR6[910] :
select[0:9] == 10'd911 ? VAR6[911] :
select[0:9] == 10'd912 ? VAR6[912] :
select[0:9] == 10'd913 ? VAR6[913] :
select[0:9] == 10'd914 ? VAR6[914] :
select[0:9] == 10'd915 ? VAR6[915] :
select[0:9] == 10'd916 ? VAR6[916] :
select[0:9] == 10'd917 ? VAR6[917] :
select[0:9] == 10'd918 ? VAR6[918] :
select[0:9] == 10'd919 ? VAR6[919] :
select[0:9] == 10'd920 ? VAR6[920] :
select[0:9] == 10'd921 ? VAR6[921] :
select[0:9] == 10'd922 ? VAR6[922] :
select[0:9] == 10'd923 ? VAR6[923] :
select[0:9] == 10'd924 ? VAR6[924] :
select[0:9] == 10'd925 ? VAR6[925] :
select[0:9] == 10'd926 ? VAR6[926] :
select[0:9] == 10'd927 ? VAR6[927] :
select[0:9] == 10'd928 ? VAR6[928] :
select[0:9] == 10'd929 ? VAR6[929] :
select[0:9] == 10'd930 ? VAR6[930] :
select[0:9] == 10'd931 ? VAR6[931] :
select[0:9] == 10'd932 ? VAR6[932] :
select[0:9] == 10'd933 ? VAR6[933] :
select[0:9] == 10'd934 ? VAR6[934] :
select[0:9] == 10'd935 ? VAR6[935] :
select[0:9] == 10'd936 ? VAR6[936] :
select[0:9] == 10'd937 ? VAR6[937] :
select[0:9] == 10'd938 ? VAR6[938] :
select[0:9] == 10'd939 ? VAR6[939] :
select[0:9] == 10'd940 ? VAR6[940] :
select[0:9] == 10'd941 ? VAR6[941] :
select[0:9] == 10'd942 ? VAR6[942] :
select[0:9] == 10'd943 ? VAR6[943] :
select[0:9] == 10'd944 ? VAR6[944] :
select[0:9] == 10'd945 ? VAR6[945] :
select[0:9] == 10'd946 ? VAR6[946] :
select[0:9] == 10'd947 ? VAR6[947] :
select[0:9] == 10'd948 ? VAR6[948] :
select[0:9] == 10'd949 ? VAR6[949] :
select[0:9] == 10'd950 ? VAR6[950] :
select[0:9] == 10'd951 ? VAR6[951] :
select[0:9] == 10'd952 ? VAR6[952] :
select[0:9] == 10'd953 ? VAR6[953] :
select[0:9] == 10'd954 ? VAR6[954] :
select[0:9] == 10'd955 ? VAR6[955] :
select[0:9] == 10'd956 ? VAR6[956] :
select[0:9] == 10'd957 ? VAR6[957] :
select[0:9] == 10'd958 ? VAR6[958] :
select[0:9] == 10'd959 ? VAR6[959] :
select[0:9] == 10'd960 ? VAR6[960] :
select[0:9] == 10'd961 ? VAR6[961] :
select[0:9] == 10'd962 ? VAR6[962] :
select[0:9] == 10'd963 ? VAR6[963] :
select[0:9] == 10'd964 ? VAR6[964] :
select[0:9] == 10'd965 ? VAR6[965] :
select[0:9] == 10'd966 ? VAR6[966] :
select[0:9] == 10'd967 ? VAR6[967] :
select[0:9] == 10'd968 ? VAR6[968] :
select[0:9] == 10'd969 ? VAR6[969] :
select[0:9] == 10'd970 ? VAR6[970] :
select[0:9] == 10'd971 ? VAR6[971] :
select[0:9] == 10'd972 ? VAR6[972] :
select[0:9] == 10'd973 ? VAR6[973] :
select[0:9] == 10'd974 ? VAR6[974] :
select[0:9] == 10'd975 ? VAR6[975] :
select[0:9] == 10'd976 ? VAR6[976] :
select[0:9] == 10'd977 ? VAR6[977] :
select[0:9] == 10'd978 ? VAR6[978] :
select[0:9] == 10'd979 ? VAR6[979] :
select[0:9] == 10'd980 ? VAR6[980] :
select[0:9] == 10'd981 ? VAR6[981] :
select[0:9] == 10'd982 ? VAR6[982] :
select[0:9] == 10'd983 ? VAR6[983] :
select[0:9] == 10'd984 ? VAR6[984] :
select[0:9] == 10'd985 ? VAR6[985] :
select[0:9] == 10'd986 ? VAR6[986] :
select[0:9] == 10'd987 ? VAR6[987] :
select[0:9] == 10'd988 ? VAR6[988] :
select[0:9] == 10'd989 ? VAR6[989] :
select[0:9] == 10'd990 ? VAR6[990] :
select[0:9] == 10'd991 ? VAR6[991] :
select[0:9] == 10'd992 ? VAR6[992] :
select[0:9] == 10'd993 ? VAR6[993] :
select[0:9] == 10'd994 ? VAR6[994] :
select[0:9] == 10'd995 ? VAR6[995] :
select[0:9] == 10'd996 ? VAR6[996] :
select[0:9] == 10'd997 ? VAR6[997] :
select[0:9] == 10'd998 ? VAR6[998] : VAR6[999]);
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.functional.v | 1,778 | module MODULE1( VAR18, VAR21, VAR4, VAR5, VAR6 );
input VAR6, VAR5, VAR21, VAR18;
output VAR4;
wire VAR14;
not VAR3( VAR14, VAR6 );
wire VAR1;
not VAR2( VAR1, VAR21 );
wire VAR10;
and VAR8( VAR10, VAR14, VAR1 );
wire VAR16;
not VAR22( VAR16, VAR18 );
wire VAR7;
and VAR20( VAR7, VAR14, VAR16 );
wire VAR19;
not VAR15( VAR19, VAR5 );
wire VAR17;
and VAR11( VAR17, VAR19, VAR1 );
wire VAR13;
and VAR9( VAR13, VAR19, VAR16 );
or VAR12( VAR4, VAR10, VAR7, VAR17, VAR13 );
endmodule | apache-2.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/LUT_SHIFT.v | 2,010 | module MODULE1 #(parameter VAR5 = 5) (
input wire VAR3,
input wire VAR2,
input wire [4:0] VAR1,
output reg [VAR5-1:0] VAR4
);
always @(posedge VAR3)
if (VAR2)
case (VAR1)
5'b00000: VAR4 <= 5'b00001;
5'b00001: VAR4 <= 5'b00010;
5'b00010: VAR4 <= 5'b00011;
5'b00011: VAR4 <= 5'b00100;
5'b00100: VAR4 <= 5'b00100;
5'b00101: VAR4 <= 5'b00101;
5'b00110: VAR4 <= 5'b00110;
5'b00111: VAR4 <= 5'b00111;
5'b01000: VAR4 <= 5'b01000;
5'b01001: VAR4 <= 5'b01001;
5'b01010: VAR4 <= 5'b01010;
5'b01011: VAR4 <= 5'b01011;
5'b01100: VAR4 <= 5'b01100;
5'b01101: VAR4 <= 5'b01101;
5'b01110: VAR4 <= 5'b01101;
5'b01111: VAR4 <= 5'b01110;
5'b10000: VAR4 <= 5'b01111;
5'b10001: VAR4 <= 5'b10000;
5'b10010: VAR4 <= 5'b10001;
5'b10011: VAR4 <= 5'b10010;
5'b10100: VAR4 <= 5'b10011;
5'b10101: VAR4 <= 5'b10100;
5'b10110: VAR4 <= 5'b10101;
5'b10111: VAR4 <= 5'b10110;
5'b11000: VAR4 <= 5'b10111;
5'b11001: VAR4 <= 5'b11000;
5'b11010: VAR4 <= 5'b11001;
5'b11011: VAR4 <= 5'b11010;
5'b11100: VAR4 <= 5'b11011;
5'b11101: VAR4 <= 5'b11100;
5'b11110: VAR4 <= 5'b11101;
5'b11111: VAR4 <= 5'b11110;
default: VAR4 <= 5'b00000;
endcase
endmodule | gpl-3.0 |
nlsynth/nli | lib/fp/fp16bmul.v | 1,808 | module MODULE1(
input clk,
input rst,
input [15:0] VAR20,
input [15:0] VAR19,
output VAR9,
output [7:0] VAR25,
output [7:0] VAR13,
output [8:0] VAR27);
wire VAR8;
wire VAR14;
wire [7:0] VAR16;
wire [7:0] VAR6;
wire [6:0] VAR24;
wire [6:0] VAR26;
wire [7:0] VAR15;
wire [7:0] VAR18;
wire [15:0] VAR10;
wire [8:0] VAR7;
assign VAR8 = VAR20[15:15];
assign VAR14 = VAR19[15:15];
assign VAR16 = VAR20[14:7];
assign VAR6 = VAR19[14:7];
assign VAR24 = VAR20[6:0];
assign VAR26 = VAR19[6:0];
assign VAR9 = VAR8 ^ VAR14;
assign VAR25 = VAR16;
assign VAR13 = VAR6;
assign VAR15 = {(VAR16 == 0 ? 1'b0 : 1'b1), VAR24};
assign VAR18 = {(VAR6 == 0 ? 1'b0 : 1'b1), VAR26};
assign VAR10 = VAR15 * VAR18;
assign VAR7 = VAR10[15:7];
assign VAR27 = VAR7;
endmodule
module MODULE2(
input clk,
input rst,
input VAR20,
input [7:0] VAR19,
input [7:0] VAR23,
input [8:0] VAR4,
output [15:0] VAR9);
wire VAR2;
wire VAR22;
wire [6:0] VAR5;
wire [6:0] VAR1;
wire [9:0] VAR3;
wire [7:0] VAR17;
wire VAR11;
wire VAR12;
wire VAR21;
assign VAR2 = VAR20;
assign VAR22 = VAR4[8:8];
assign VAR3 = VAR19 + VAR23 - 127 + VAR22;
assign VAR5 = VAR22 ? VAR4[7:1] : VAR4[6:0];
assign VAR21 = (VAR19 == 255) || (VAR23 == 255);
assign VAR11 = VAR3[9:9];
assign VAR12 = !VAR11 && (VAR3[8:8] || VAR3[7:0] == 255 || VAR21);
assign VAR17 = VAR11 ? 0 : (VAR12 ? 255 : VAR3[7:0]);
assign VAR1 = (VAR11 || VAR3[7:0] == 0) ? 0 : VAR5;
assign VAR9 = {VAR2, VAR17, VAR1};
endmodule | gpl-3.0 |
fbalakirev/red-pitaya-notes | cores/axis_circular_packetizer_v1_0/axis_circular_packetizer.v | 4,218 | module MODULE1 #
(
parameter integer VAR13 = 32,
parameter integer VAR14 = 32,
parameter VAR29 = "VAR19",
parameter VAR21 = "VAR19"
)
(
input wire VAR20,
input wire VAR3,
input wire [VAR14-1:0] VAR30,
output wire [VAR14-1:0] VAR31,
input wire VAR7,
output wire VAR12,
output wire VAR33,
output wire VAR15,
input wire [VAR13-1:0] VAR11,
input wire VAR10,
input wire VAR25,
output wire [VAR13-1:0] VAR1,
output wire VAR16,
output wire VAR9
);
reg [VAR14-1:0] VAR17, VAR5, VAR24, VAR28;
reg VAR23, VAR6;
reg VAR26, VAR27;
wire VAR8, VAR32, VAR22;
always @(posedge VAR20)
begin
if(~VAR3)
begin
VAR17 <= {(VAR14){1'b0}};
VAR24 <= {(VAR14){1'b0}};
VAR23 <= 1'b0;
VAR26 <= 1'b0;
end
else
begin
VAR17 <= VAR5;
VAR24 <= VAR28;
VAR23 <= VAR6;
VAR26 <= VAR27;
end
end
assign VAR8 = VAR17 < VAR30;
assign VAR32 = VAR23 & VAR10;
assign VAR22 = ~VAR8;
generate
if(VAR29 == "VAR4")
begin : VAR2
always @*
begin
VAR5 = VAR17;
VAR6 = VAR23;
VAR27 = VAR26;
VAR28 = VAR24;
if(~VAR23 & VAR8)
begin
VAR6 = 1'b1;
end
if(VAR25 & VAR32 & VAR8)
begin
VAR5 = VAR17 + 1'b1;
end
if(VAR25 & VAR32 & VAR22)
begin
VAR5 = {(VAR14){1'b0}};
end
end
end
else
begin : VAR18
always @*
begin
VAR5 = VAR17;
VAR28 = VAR24;
VAR6 = VAR23;
VAR27 = VAR26;
if(~VAR23 & VAR8)
begin
VAR6 = 1'b1;
end
if(VAR25 & VAR32 & VAR8)
begin
if(VAR7)
VAR5 = VAR17 + 1'b1;
end
else
VAR28 = VAR24 + 1'b1;
end
if(VAR25 & VAR32 & VAR22)
begin
VAR6 = 1'b0;
VAR27 = 1'b1;
end
end
end
endgenerate
if(VAR21 == "VAR4")
assign VAR15 = ~VAR23 | VAR25;
else
assign VAR15 = VAR23 & VAR25;
assign VAR1 = VAR11;
assign VAR16 = VAR32;
assign VAR9 = VAR23 & VAR22;
assign VAR31 = VAR24;
assign VAR12 = VAR23;
assign VAR33 = VAR26;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpad/sky130_fd_io__top_power_hvc_wpad.behavioral.pp.v | 1,160 | module MODULE1 ( VAR14, VAR12, VAR4
, VAR16, VAR7, VAR3, VAR5,VAR9, VAR13, VAR10, VAR15, VAR6, VAR17, VAR8, VAR11, VAR2, VAR1
);
inout VAR14;
inout VAR12;
inout VAR4;
inout VAR3;
inout VAR7;
inout VAR5;
inout VAR16;
inout VAR17;
inout VAR15;
inout VAR13;
inout VAR8;
inout VAR10;
inout VAR6;
inout VAR9;
inout VAR2;
inout VAR1;
inout VAR11;
assign VAR16 = VAR14;
endmodule | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/mips/PC_Next.v | 1,184 | module MODULE1
(
clk,
rst,
VAR5,
VAR6,
VAR7,
VAR3,
VAR2,
VAR8
);
input clk;
input rst;
input [31:2] VAR5;
input VAR6;
input [25:0] VAR7;
input [1:0] VAR3;
output [31:2] VAR2;
output [31:2] VAR8;
reg [31:2] VAR4;
reg [31:2] VAR9;
assign VAR2=VAR4;
assign VAR8=VAR4+1;
wire [31:2] VAR1;
assign VAR1 = VAR4+{{14{VAR7[15]}},VAR7[15:0]};
always@(*)
begin
VAR9<=VAR8;
case(VAR3)
VAR9<=VAR8;
VAR9<={VAR4[31:28],VAR7};
VAR9<=(VAR6)?VAR1:VAR8;
VAR9<=VAR5;
default:
VAR9<=VAR8;
endcase
end
always@(posedge clk or posedge rst)
begin
if(rst)
begin
VAR4<=30'b0;
end
else
begin
VAR4<=VAR9;
end
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a.behavioral.pp.v | 2,199 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR20 ,
VAR2 ,
VAR15 ,
VAR7 ,
VAR11,
VAR4,
VAR3 ,
VAR10
);
output VAR8 ;
input VAR1 ;
input VAR20 ;
input VAR2 ;
input VAR15 ;
input VAR7 ;
input VAR11;
input VAR4;
input VAR3 ;
input VAR10 ;
wire VAR16 ;
wire VAR18 ;
wire VAR14 ;
wire VAR6;
or VAR12 (VAR16 , VAR15, VAR2 );
or VAR5 (VAR18 , VAR20, VAR1 );
and VAR19 (VAR14 , VAR16, VAR18, VAR7 );
VAR17 VAR13 (VAR6, VAR14, VAR11, VAR4);
buf VAR9 (VAR8 , VAR6 );
endmodule | apache-2.0 |
tanelikaivola/blinkenlichten | fpga/asic.v | 7,357 | module MODULE1(
input VAR1,
input VAR5,
input [2:0] VAR3,
output [3:0] VAR2,
output VAR4,
output [255:0] VAR6,
output [7:0] VAR7
);
nand(VAR4,VAR6[240],VAR6[242]);
nand(VAR2[0],VAR6[9],VAR6[9]);
nand(VAR2[1],VAR6[8],VAR6[8]);
nand(VAR2[2],VAR6[6],VAR6[6]);
nand(VAR2[3],VAR6[2],VAR6[2]);
nand(VAR6[0],VAR5,VAR5);
nand(VAR6[1],VAR6[0],VAR6[0]);
nand(VAR6[2],VAR6[3],VAR6[4]);
nand(VAR6[3],VAR6[198],VAR6[200]);
nand(VAR6[4],VAR6[205],VAR6[207]);
nand(VAR6[5],VAR6[3],VAR6[3]);
nand(VAR6[6],VAR6[5],VAR6[4]);
nand(VAR6[7],VAR6[4],VAR6[4]);
nand(VAR6[8],VAR6[3],VAR6[7]);
nand(VAR6[9],VAR6[5],VAR6[7]);
nand(VAR6[10],VAR1,VAR1);
nand(VAR6[11],VAR3[0],VAR3[0]);
nand(VAR6[12],VAR3[1],VAR3[1]);
nand(VAR6[13],VAR3[2],VAR3[2]);
nand(VAR6[14],VAR6[13],VAR6[12]);
nand(VAR6[15],VAR6[14],VAR6[14]);
nand(VAR6[16],VAR6[15],VAR6[11]);
nand(VAR6[17],VAR6[16],VAR6[10]);
nand(VAR6[18],VAR6[17],VAR6[17]);
nand(VAR6[19],VAR6[20],VAR6[20]);
nand(VAR6[20],VAR6[191],VAR6[193]);
nand(VAR6[21],VAR6[16],VAR6[19]);
nand(VAR6[22],VAR6[21],VAR6[21]);
nand(VAR6[23],VAR6[24],VAR6[25]);
nand(VAR6[24],VAR6[233],VAR6[235]);
nand(VAR6[25],VAR6[226],VAR6[228]);
nand(VAR6[26],VAR6[23],VAR6[23]);
nand(VAR6[27],VAR3[2],VAR6[12]);
nand(VAR6[28],VAR6[27],VAR6[27]);
nand(VAR6[29],VAR6[28],VAR6[26]);
nand(VAR6[30],VAR6[29],VAR6[29]);
nand(VAR6[31],VAR6[32],VAR6[33]);
nand(VAR6[32],VAR6[212],VAR6[214]);
nand(VAR6[33],VAR6[219],VAR6[221]);
nand(VAR6[34],VAR6[31],VAR6[31]);
nand(VAR6[35],VAR6[34],VAR2[1]);
nand(VAR6[36],VAR6[35],VAR6[35]);
nand(VAR6[37],VAR6[36],VAR6[10]);
nand(VAR6[38],VAR6[37],VAR6[37]);
nand(VAR6[39],VAR6[38],VAR6[30]);
nand(VAR6[40],VAR6[39],VAR6[39]);
nand(VAR6[41],VAR6[40],VAR6[22]);
nand(VAR6[42],VAR6[41],VAR6[41]);
nand(VAR6[43],VAR6[21],VAR6[32]);
nand(VAR6[44],VAR6[15],VAR2[0]);
nand(VAR6[45],VAR6[44],VAR6[44]);
nand(VAR6[46],VAR6[33],VAR6[33]);
nand(VAR6[47],VAR6[32],VAR6[32]);
nand(VAR6[48],VAR6[47],VAR6[46]);
nand(VAR6[49],VAR6[48],VAR6[48]);
nand(VAR6[50],VAR6[49],VAR6[26]);
nand(VAR6[51],VAR6[50],VAR6[50]);
nand(VAR6[52],VAR6[51],VAR6[45]);
nand(VAR6[53],VAR6[47],VAR6[33]);
nand(VAR6[54],VAR6[53],VAR6[53]);
nand(VAR6[55],VAR6[54],VAR2[0]);
nand(VAR6[56],VAR6[55],VAR6[55]);
nand(VAR6[57],VAR6[56],VAR6[30]);
nand(VAR6[58],VAR6[57],VAR6[52]);
nand(VAR6[59],VAR6[58],VAR6[58]);
nand(VAR6[60],VAR6[25],VAR6[25]);
nand(VAR6[61],VAR6[24],VAR6[60]);
nand(VAR6[62],VAR6[61],VAR6[61]);
nand(VAR6[63],VAR6[62],VAR6[45]);
nand(VAR6[64],VAR6[63],VAR6[63]);
nand(VAR6[65],VAR6[64],VAR6[47]);
nand(VAR6[66],VAR6[65],VAR6[59]);
nand(VAR6[67],VAR6[66],VAR6[66]);
nand(VAR6[68],VAR6[13],VAR3[1]);
nand(VAR6[69],VAR6[68],VAR6[68]);
nand(VAR6[70],VAR6[69],VAR2[2]);
nand(VAR6[71],VAR6[70],VAR6[70]);
nand(VAR6[72],VAR6[24],VAR6[24]);
nand(VAR6[73],VAR6[72],VAR6[25]);
nand(VAR6[74],VAR6[73],VAR6[73]);
nand(VAR6[75],VAR6[74],VAR6[49]);
nand(VAR6[76],VAR6[75],VAR6[75]);
nand(VAR6[77],VAR6[76],VAR6[71]);
nand(VAR6[78],VAR6[72],VAR6[60]);
nand(VAR6[79],VAR6[78],VAR6[78]);
nand(VAR6[80],VAR6[79],VAR6[49]);
nand(VAR6[81],VAR6[80],VAR6[80]);
nand(VAR6[82],VAR6[81],VAR6[71]);
nand(VAR6[83],VAR6[82],VAR6[77]);
nand(VAR6[84],VAR6[83],VAR6[83]);
nand(VAR6[85],VAR6[74],VAR6[15]);
nand(VAR6[86],VAR6[85],VAR6[85]);
nand(VAR6[87],VAR6[54],VAR2[2]);
nand(VAR6[88],VAR6[87],VAR6[87]);
nand(VAR6[89],VAR6[88],VAR6[86]);
nand(VAR6[90],VAR6[79],VAR6[54]);
nand(VAR6[91],VAR6[90],VAR6[90]);
nand(VAR6[92],VAR6[91],VAR6[45]);
nand(VAR6[93],VAR6[92],VAR6[89]);
nand(VAR6[94],VAR6[93],VAR6[93]);
nand(VAR6[95],VAR6[94],VAR6[84]);
nand(VAR6[96],VAR6[95],VAR6[95]);
nand(VAR6[97],VAR6[96],VAR6[67]);
nand(VAR6[98],VAR6[97],VAR6[22]);
nand(VAR6[99],VAR6[98],VAR6[43]);
nand(VAR6[100],VAR6[99],VAR6[10]);
nand(VAR6[101],VAR6[100],VAR6[100]);
nand(VAR6[102],VAR6[21],VAR6[33]);
nand(VAR6[103],VAR6[15],VAR6[25]);
nand(VAR6[104],VAR6[103],VAR6[103]);
nand(VAR6[105],VAR6[32],VAR6[46]);
nand(VAR6[106],VAR6[105],VAR6[105]);
nand(VAR6[107],VAR6[106],VAR2[0]);
nand(VAR6[108],VAR6[107],VAR6[107]);
nand(VAR6[109],VAR6[108],VAR6[104]);
nand(VAR6[110],VAR6[62],VAR6[54]);
nand(VAR6[111],VAR6[110],VAR6[110]);
nand(VAR6[112],VAR6[111],VAR6[45]);
nand(VAR6[113],VAR6[112],VAR6[57]);
nand(VAR6[114],VAR6[113],VAR6[113]);
nand(VAR6[115],VAR6[114],VAR6[109]);
nand(VAR6[116],VAR6[115],VAR6[115]);
nand(VAR6[117],VAR6[62],VAR6[15]);
nand(VAR6[118],VAR6[117],VAR6[117]);
nand(VAR6[119],VAR6[106],VAR2[2]);
nand(VAR6[120],VAR6[119],VAR6[119]);
nand(VAR6[121],VAR6[120],VAR6[118]);
nand(VAR6[122],VAR6[28],VAR6[72]);
nand(VAR6[123],VAR6[122],VAR6[122]);
nand(VAR6[124],VAR6[123],VAR6[120]);
nand(VAR6[125],VAR6[124],VAR6[121]);
nand(VAR6[126],VAR6[125],VAR6[125]);
nand(VAR6[127],VAR6[126],VAR6[94]);
nand(VAR6[128],VAR6[127],VAR6[127]);
nand(VAR6[129],VAR6[128],VAR6[116]);
nand(VAR6[130],VAR6[129],VAR6[22]);
nand(VAR6[131],VAR6[130],VAR6[102]);
nand(VAR6[132],VAR6[131],VAR6[10]);
nand(VAR6[133],VAR6[132],VAR6[132]);
nand(VAR6[134],VAR6[21],VAR6[25]);
nand(VAR6[135],VAR6[69],VAR6[62]);
nand(VAR6[136],VAR6[135],VAR6[135]);
nand(VAR6[137],VAR6[136],VAR6[36]);
nand(VAR6[138],VAR6[137],VAR6[109]);
nand(VAR6[139],VAR6[138],VAR6[138]);
nand(VAR6[140],VAR6[139],VAR6[59]);
nand(VAR6[141],VAR6[140],VAR6[140]);
nand(VAR6[142],VAR6[15],VAR2[2]);
nand(VAR6[143],VAR6[142],VAR6[142]);
nand(VAR6[144],VAR6[79],VAR6[34]);
nand(VAR6[145],VAR6[144],VAR6[144]);
nand(VAR6[146],VAR6[145],VAR6[143]);
nand(VAR6[147],VAR6[77],VAR6[89]);
nand(VAR6[148],VAR6[147],VAR6[147]);
nand(VAR6[149],VAR6[148],VAR6[146]);
nand(VAR6[150],VAR6[149],VAR6[149]);
nand(VAR6[151],VAR6[150],VAR6[141]);
nand(VAR6[152],VAR6[151],VAR6[22]);
nand(VAR6[153],VAR6[152],VAR6[134]);
nand(VAR6[154],VAR6[153],VAR6[10]);
nand(VAR6[155],VAR6[154],VAR6[154]);
nand(VAR6[156],VAR6[21],VAR6[24]);
nand(VAR6[157],VAR6[26],VAR6[15]);
nand(VAR6[158],VAR6[157],VAR6[157]);
nand(VAR6[159],VAR6[108],VAR6[158]);
nand(VAR6[160],VAR6[159],VAR6[121]);
nand(VAR6[161],VAR6[160],VAR6[160]);
nand(VAR6[162],VAR6[86],VAR6[36]);
nand(VAR6[163],VAR6[162],VAR6[137]);
nand(VAR6[164],VAR6[163],VAR6[163]);
nand(VAR6[165],VAR6[164],VAR6[161]);
nand(VAR6[166],VAR6[165],VAR6[165]);
nand(VAR6[167],VAR6[166],VAR6[67]);
nand(VAR6[168],VAR6[167],VAR6[22]);
nand(VAR6[169],VAR6[168],VAR6[156]);
nand(VAR6[170],VAR6[169],VAR6[10]);
nand(VAR6[171],VAR6[170],VAR6[170]);
nand(VAR6[172],VAR6[16],VAR6[16]);
nand(VAR6[173],VAR6[19],VAR6[5]);
nand(VAR6[174],VAR6[173],VAR6[172]);
nand(VAR6[175],VAR6[16],VAR6[5]);
nand(VAR6[176],VAR6[175],VAR6[10]);
nand(VAR6[177],VAR6[176],VAR6[176]);
nand(VAR6[178],VAR6[177],VAR6[174]);
nand(VAR6[179],VAR6[178],VAR6[178]);
nand(VAR6[180],VAR6[174],VAR6[4]);
nand(VAR6[181],VAR2[1],VAR6[19]);
nand(VAR6[182],VAR6[181],VAR6[181]);
nand(VAR6[183],VAR6[182],VAR6[172]);
nand(VAR6[184],VAR6[183],VAR6[180]);
nand(VAR6[185],VAR6[184],VAR6[10]);
nand(VAR6[186],VAR6[185],VAR6[185]);
nand(VAR6[187],VAR6[0],VAR6[18]);
nand(VAR6[188],VAR6[0],VAR6[187]);
nand(VAR6[189],VAR6[188],VAR6[190]);
nand(VAR6[190],VAR6[187],VAR6[189]);
nand(VAR6[191],VAR6[1],VAR6[190]);
nand(VAR6[192],VAR6[1],VAR6[191]);
nand(VAR6[193],VAR6[192],VAR6[20]);
nand(VAR6[194],VAR6[0],VAR6[179]);
nand(VAR6[195],VAR6[0],VAR6[194]);
nand(VAR6[196],VAR6[195],VAR6[197]);
nand(VAR6[197],VAR6[194],VAR6[196]);
nand(VAR6[198],VAR6[1],VAR6[197]);
nand(VAR6[199],VAR6[1],VAR6[198]);
nand(VAR6[200],VAR6[199],VAR6[3]);
nand(VAR6[201],VAR6[0],VAR6[186]);
nand(VAR6[202],VAR6[0],VAR6[201]);
nand(VAR6[203],VAR6[202],VAR6[204]);
nand(VAR6[204],VAR6[201],VAR6[203]);
nand(VAR6[205],VAR6[1],VAR6[204]);
nand(VAR6[206],VAR6[1],VAR6[205]);
nand(VAR6[207],VAR6[206],VAR6[4]);
nand(VAR6[208],VAR6[0],VAR6[101]);
nand(VAR6[209],VAR6[0],VAR6[208]);
nand(VAR6[210],VAR6[209],VAR6[211]);
nand(VAR6[211],VAR6[208],VAR6[210]);
nand(VAR6[212],VAR6[1],VAR6[211]);
nand(VAR6[213],VAR6[1],VAR6[212]);
nand(VAR6[214],VAR6[213],VAR6[32]);
nand(VAR6[215],VAR6[0],VAR6[133]);
nand(VAR6[216],VAR6[0],VAR6[215]);
nand(VAR6[217],VAR6[216],VAR6[218]);
nand(VAR6[218],VAR6[215],VAR6[217]);
nand(VAR6[219],VAR6[1],VAR6[218]);
nand(VAR6[220],VAR6[1],VAR6[219]);
nand(VAR6[221],VAR6[220],VAR6[33]);
nand(VAR6[222],VAR6[0],VAR6[155]);
nand(VAR6[223],VAR6[0],VAR6[222]);
nand(VAR6[224],VAR6[223],VAR6[225]);
nand(VAR6[225],VAR6[222],VAR6[224]);
nand(VAR6[226],VAR6[1],VAR6[225]);
nand(VAR6[227],VAR6[1],VAR6[226]);
nand(VAR6[228],VAR6[227],VAR6[25]);
nand(VAR6[229],VAR6[0],VAR6[171]);
nand(VAR6[230],VAR6[0],VAR6[229]);
nand(VAR6[231],VAR6[230],VAR6[232]);
nand(VAR6[232],VAR6[229],VAR6[231]);
nand(VAR6[233],VAR6[1],VAR6[232]);
nand(VAR6[234],VAR6[1],VAR6[233]);
nand(VAR6[235],VAR6[234],VAR6[24]);
nand(VAR6[236],VAR6[0],VAR6[42]);
nand(VAR6[237],VAR6[0],VAR6[236]);
nand(VAR6[238],VAR6[237],VAR6[239]);
nand(VAR6[239],VAR6[236],VAR6[238]);
nand(VAR6[240],VAR6[1],VAR6[239]);
nand(VAR6[241],VAR6[1],VAR6[240]);
nand(VAR6[242],VAR6[241],VAR4);
assign VAR7 = {VAR2[3:0],VAR3[2:0],VAR5};
assign VAR6[243] = 1;
assign VAR6[244] = VAR1;
assign VAR6[245] = VAR5;
assign VAR6[249:246] = VAR2;
assign VAR6[252:250] = VAR3;
assign VAR6[253] = VAR4;
assign VAR6[254] = VAR4;
assign VAR6[255] = VAR4;
endmodule | mit |
silent-observer/RCPU | CPU/source/InstrROM.v | 6,872 | module MODULE1 (
address,
VAR31,
VAR9);
input [9:0] address;
input VAR31;
output [15:0] VAR9;
tri1 VAR31;
wire [15:0] VAR37;
wire [15:0] VAR9 = VAR37[15:0];
VAR10 VAR51 (
.VAR52 (address),
.VAR48 (VAR31),
.VAR45 (VAR37),
.VAR33 (1'b0),
.VAR3 (1'b0),
.VAR49 (1'b1),
.VAR8 (1'b0),
.VAR19 (1'b0),
.VAR41 (1'b1),
.VAR29 (1'b1),
.VAR20 (1'b1),
.VAR43 (1'b1),
.VAR34 (1'b1),
.VAR22 (1'b1),
.VAR24 (1'b1),
.VAR5 ({16{1'b1}}),
.VAR26 (1'b1),
.VAR40 (),
.VAR4 (),
.VAR28 (1'b1),
.VAR42 (1'b1),
.VAR21 (1'b0),
.VAR13 (1'b0));
VAR51.VAR12 = "VAR46",
VAR51.VAR32 = "VAR25",
VAR51.VAR44 = "VAR25",
VAR51.VAR15 = "../VAR47/VAR35.VAR18",
VAR51.VAR16 = "VAR17 VAR53 VAR14",
VAR51.VAR1 = "VAR6=VAR27",
VAR51.VAR54 = "VAR10",
VAR51.VAR50 = 1024,
VAR51.VAR11 = "VAR36",
VAR51.VAR23 = "VAR46",
VAR51.VAR7 = "VAR30",
VAR51.VAR2 = 10,
VAR51.VAR38 = 16,
VAR51.VAR39 = 1;
endmodule | mit |
freecores/altor32 | rtl/cpu/altor32_regfile_alt.v | 5,547 | module MODULE1
(
input VAR42 ,
input VAR24 ,
input VAR20 ,
input [4:0] VAR41 ,
input [4:0] VAR34 ,
input [4:0] VAR36 ,
output reg [31:0] VAR21 ,
output reg [31:0] VAR30 ,
input [31:0] VAR19
);
parameter VAR32 = "VAR33";
wire VAR39;
wire [31:0] VAR3;
wire [31:0] VAR16;
wire VAR13;
reg [4:0] VAR14;
reg [31:0] VAR10;
wire [31:0] VAR23;
wire [31:0] VAR31;
always @ (posedge VAR42 or posedge VAR24)
begin
if (VAR24)
begin
VAR14 <= 5'b00000;
VAR10 <= 32'h00000000;
end
else
begin
VAR14 <= VAR36;
VAR10 <= VAR19;
end
end
VAR26
.VAR4(32),
.VAR2(5),
.VAR28("VAR27"),
.VAR22("VAR37"),
.VAR18("VAR27"),
.VAR38("VAR27"),
.VAR12("VAR15"),
.VAR5("VAR26"),
.VAR44("VAR15")
)
VAR29
(
.VAR7(VAR39),
.VAR11(1'b1),
.VAR43(VAR41),
.VAR17(1'b1),
.VAR6(VAR19),
.VAR35(VAR36),
.VAR25(VAR13),
.VAR40(VAR42),
.VAR8(1'b1),
.VAR1(VAR23)
);
VAR26
.VAR4(32),
.VAR2(5),
.VAR28("VAR27"),
.VAR22("VAR37"),
.VAR18("VAR27"),
.VAR38("VAR27"),
.VAR12("VAR15"),
.VAR5("VAR26"),
.VAR44("VAR15")
)
VAR9
(
.VAR7(VAR39),
.VAR11(1'b1),
.VAR43(VAR34),
.VAR17(1'b1),
.VAR6(VAR19),
.VAR35(VAR36),
.VAR25(VAR13),
.VAR40(VAR42),
.VAR8(1'b1),
.VAR1(VAR31)
);
assign VAR39 = !VAR42;
always @ *
begin
if (VAR41 == 5'b00000)
VAR21 = 32'h00000000;
end
else
VAR21 = VAR3;
if (VAR34 == 5'b00000)
VAR30 = 32'h00000000;
else
VAR30 = VAR16;
end
assign VAR13 = (VAR36 != 5'b00000) & VAR20;
assign VAR3 = (VAR41 != VAR14) ? VAR23 : VAR10;
assign VAR16 = (VAR34 != VAR14) ? VAR31 : VAR10;
endmodule | lgpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/db/ip/niosII_system/submodules/niosII_system_altpll_0.v | 10,346 | module MODULE1
(
VAR8,
VAR4,
VAR9,
VAR7) ;
input VAR8;
input VAR4;
input [0:0] VAR9;
output [0:0] VAR7;
tri0 VAR8;
tri1 VAR4;
reg [0:0] VAR10;
reg [0:0] VAR5;
reg [0:0] VAR3;
wire VAR1;
wire VAR2;
wire VAR6; | gpl-2.0 |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v | 6,164 | module MODULE1 #(
parameter VAR25 = 34,
parameter VAR14 = 0,
parameter VAR9 = 34,
parameter VAR5 = 0,
parameter VAR24 = 0,
parameter VAR18 = 0,
parameter VAR12 = 1,
parameter VAR23 = 1,
parameter VAR15 = 0,
parameter VAR13 = 34,
parameter VAR10 = 0,
parameter VAR16 = 1,
parameter VAR3 = 0,
parameter VAR22 = 1,
parameter VAR4 = 1,
parameter VAR21 = 0
) (
input wire VAR11, input wire VAR20, input wire [33:0] VAR8, input wire VAR1, output wire VAR17, output wire [33:0] VAR2, output wire VAR7, input wire VAR6, output wire [0:0] VAR19 );
generate
if (VAR25 != 34)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | mit |
545/Atari7800 | maria/maria.srcs/sources_1/ip/clock_divider/clock_divider_clk_wiz.v | 6,303 | module MODULE1
( input VAR58,
output VAR70,
output VAR54,
output VAR27,
input reset,
output VAR44
);
VAR68 VAR55
(.VAR7 (VAR20),
.VAR34 (VAR58));
wire [15:0] VAR31;
wire VAR40;
wire VAR29;
wire VAR49;
wire VAR13;
wire VAR32;
wire VAR64;
wire VAR47;
wire VAR33;
wire VAR53;
wire VAR63;
wire VAR60;
wire VAR4;
wire VAR5;
VAR56
.VAR23 ("VAR19"),
.VAR9 (1),
.VAR25 (8),
.VAR3 (0.000),
.VAR51 (112),
.VAR35 (0.000),
.VAR14 (0.500),
.VAR1 (32),
.VAR66 (0.000),
.VAR52 (0.500),
.VAR2 (8),
.VAR12 (0.000),
.VAR37 (0.500),
.VAR57 (10.0))
VAR45
(
.VAR65 (VAR13),
.VAR22 (VAR10),
.VAR28 (VAR43),
.VAR69 (VAR6),
.VAR24 (VAR47),
.VAR21 (VAR33),
.VAR61 (VAR53),
.VAR18 (VAR32),
.VAR50 (VAR20),
.VAR46 (1'b0),
.VAR48 (1'b1),
.VAR16 (7'h0),
.VAR36 (1'b0),
.VAR38 (1'b0),
.VAR8 (16'h0),
.VAR11 (VAR31),
.VAR39 (VAR40),
.VAR30 (1'b0),
.VAR17 (VAR49),
.VAR62 (1'b0),
.VAR15 (VAR5));
assign VAR5 = reset;
assign VAR44 = VAR49;
VAR59 VAR42
(.VAR7 (VAR32),
.VAR34 (VAR13));
VAR59 VAR41
(.VAR7 (VAR70),
.VAR34 (VAR10));
VAR59 VAR26
(.VAR7 (VAR54),
.VAR34 (VAR43));
VAR59 VAR67
(.VAR7 (VAR27),
.VAR34 (VAR6));
endmodule | gpl-2.0 |
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner | projects/Verilog_Xilinx_Port/sources/hdl/main_pll.v | 3,244 | module MODULE1(VAR49,
VAR34,
VAR20,
VAR32,
VAR48,
VAR19,
VAR70,
VAR10,
VAR52);
input VAR49;
input VAR34;
input VAR20;
input VAR32;
output VAR48;
output VAR19;
output VAR70;
output VAR10;
output VAR52;
wire VAR67;
wire VAR56;
wire VAR37;
wire VAR24;
wire VAR12;
wire VAR71;
wire VAR18;
assign VAR71 = 0;
assign VAR18 = 1;
assign VAR48 = VAR67;
assign VAR19 = VAR24;
assign VAR70 = VAR12;
VAR26 VAR64 (.VAR55(VAR34),
.VAR39(VAR67));
VAR44 VAR30 (.VAR55(VAR56),
.VAR39(VAR24));
VAR44 VAR21 (.VAR55(VAR37),
.VAR39(VAR12));
VAR17 #( .VAR2("1X"), .VAR73(2.0), .VAR66(1),
.VAR3(4), .VAR31("VAR35"),
.VAR42(20.000), .VAR72("VAR63"),
.VAR59("VAR38"), .VAR11("VAR65"),
.VAR50("VAR65"), .VAR68("VAR53"),
.VAR54(16'hC080), .VAR29(0), .VAR61("VAR35") )
VAR8 (.VAR4(VAR24),
.VAR60(VAR67),
.VAR1(VAR71),
.VAR25(VAR71),
.VAR40(VAR71),
.VAR33(VAR71),
.VAR28(VAR71),
.VAR51(),
.VAR69(),
.VAR23(),
.VAR57(VAR56),
.VAR41(),
.VAR46(),
.VAR47(),
.VAR6(VAR37),
.VAR14(),
.VAR36(VAR52),
.VAR58(),
.VAR22());
VAR15 VAR45 (.VAR27(VAR49),
.VAR16(VAR20),
.VAR13(VAR24),
.VAR62(VAR12),
.VAR5(VAR18),
.VAR7(VAR71),
.VAR43(VAR32),
.VAR9(VAR10));
endmodule | gpl-3.0 |
jakubfi/mera400f | src/t.v | 1,150 | module MODULE1(
input VAR8,
input 0t,
input VAR2,
input VAR1,
input VAR5,
input VAR6,
input VAR4,
input VAR3,
input VAR9,
input [0:39] VAR10,
input VAR7,
output reg [-1:39] MODULE1
);
always @ (posedge VAR8, posedge 0t) begin
if (0t) MODULE1[0:15] <= 0;
end
else if (VAR6) case ({~VAR1, ~VAR2})
2'b00: MODULE1[0:15] <= MODULE1[0:15];
2'b01: MODULE1[0:15] <= MODULE1[-1:14];
2'b10: MODULE1[0:15] <= MODULE1[1:16];
2'b11: MODULE1[0:15] <= VAR10[0:15];
endcase
end
always @ (posedge VAR8, posedge 0t) begin
if (0t) MODULE1[16:31] <= 0;
end
else if (VAR4) case ({~VAR5, ~VAR2})
2'b00: MODULE1[16:31] <= MODULE1[16:31];
2'b01: MODULE1[16:31] <= MODULE1[15:30];
2'b10: MODULE1[16:31] <= MODULE1[17:32];
2'b11: MODULE1[16:31] <= VAR10[16:31];
endcase
end
always @ (posedge VAR8, posedge 0t) begin
if (0t) MODULE1[32:39] <= 0;
end
else if (VAR3) case ({~VAR5, ~VAR2})
2'b00: MODULE1[32:39] <= MODULE1[32:39];
2'b01: MODULE1[32:39] <= MODULE1[31:38];
2'b10: MODULE1[32:39] <= {MODULE1[33:39], VAR7};
2'b11: MODULE1[32:39] <= VAR10[32:39];
endcase
end
always @ (posedge VAR8, posedge 0t) begin
if (0t) MODULE1[-1] <= 1'b0;
end
else if (VAR6) MODULE1[-1] <= VAR9;
end
endmodule | gpl-2.0 |
hhuang25/uwaterloo_ece224 | ANT - Copy/lcd_display.v | 2,035 | module MODULE1 (
address,
VAR4,
read,
write,
VAR7,
VAR2,
VAR6,
VAR5,
VAR3,
VAR8
)
;
output VAR2;
output VAR6;
output VAR5;
inout [ 7: 0] VAR3;
output [ 7: 0] VAR8;
input [ 1: 0] address;
input VAR4;
input read;
input write;
input [ 7: 0] VAR7;
wire VAR2;
wire VAR6;
wire VAR5;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR8;
assign VAR5 = address[0];
assign VAR6 = address[1];
assign VAR2 = read | write;
assign VAR3 = (address[0]) ? 8'VAR1 : VAR7;
assign VAR8 = VAR3;
endmodule | mit |
lsnow/mips32 | decode.v | 12,159 | module MODULE1(
clk, VAR34, VAR58, VAR26, VAR11, VAR17,
VAR115, VAR116, VAR75,VAR78,VAR46,VAR4,VAR18,VAR2, VAR69,VAR28, VAR41, VAR113, VAR105, rd,
VAR44, VAR21, VAR112, VAR72, VAR99, VAR66, VAR23, VAR35, VAR16, VAR40, VAR114, VAR6);
input clk;
input VAR34;
input [31:0] VAR58;
reg [31:0] VAR68;
input [31:0] VAR26, VAR11;
input [31:0] VAR17;
output reg [31:0] VAR115, VAR116;
wire VAR25, VAR55, VAR12, VAR36, VAR77, VAR45;
wire [2:0] VAR48;
wire [3:0] logic;
wire VAR106;
wire [2:0] VAR29;
output [20:0] VAR75;
assign VAR75 = {VAR25, VAR55, VAR12, VAR36, VAR77, VAR45, VAR48, logic, VAR106, VAR29};
output [31:0] VAR78, VAR46, VAR4;
output VAR18;
output reg [4:0] VAR113, VAR105, rd;
output VAR2, VAR69;
output VAR28;
output reg VAR41;
output VAR44, VAR21, VAR112;
output wire [8:0] VAR72;
output wire [5:0] VAR99;
output wire [3:0] VAR66;
output VAR23, VAR16, VAR35, VAR114;
output [31:0] VAR40;
output [4:0] VAR6; wire [5:0] VAR79 = VAR68[31:26];
wire [5:0] VAR87 = VAR68[5:0];
wire VAR97 = (VAR79 == 6'b010000);
wire VAR56 = (VAR79[5:3] == 3'b001);
wire VAR5 = (VAR79 == 6'b000001);
wire VAR62 = (VAR79 == 6'b000000);
wire VAR101 = (VAR79 == 6'b011100);
wire VAR82 = (VAR79 == 6'b011111);
wire [15:0] VAR64 = VAR68[15:0];
wire [31:0] VAR9 = VAR17 + (VAR64[15] ? {14'h3fff, VAR64, 2'b00} : {14'h0000, VAR64, 2'b00});
assign VAR40 = VAR26 + VAR64;
wire [31:0] VAR38 = VAR68[15] ? {16'hffff, VAR68[15:0]} : {16'b0, VAR68[15:0]};
assign VAR78 = (VAR62 | VAR101) ? VAR11 : VAR38;
assign VAR46 = VAR26;
assign VAR4 = VAR68[10:6];
wire [25:0] VAR61 = VAR68[25:0];
assign VAR25 = (VAR62 && VAR87[5:1]==5'b10000) || (VAR79==5'b00100);
assign VAR55 = (VAR62 && VAR87[5:1]==5'b10001);
assign VAR12 = (VAR101 & VAR87 == 6'b000010) || (VAR62 && VAR87[5:1]==5'b01100);
assign VAR36 = (VAR62 && VAR87[5:1]==5'b01101);
assign VAR45 = (VAR101 && VAR87[5:1]==5'b00010);
assign VAR77 = (VAR101 && VAR87[5:1]==5'b00000);
assign VAR18 = (VAR25 && VAR79[0]) || ((VAR25 | VAR55 | VAR12 | VAR36| VAR77 | VAR45)&&VAR87[0]);
wire VAR91 = (VAR62 && VAR87 == 6'b000000);
wire VAR51 = (VAR62 && VAR87 == 6'b000100);
wire VAR54 = (VAR62 && VAR87 == 6'b000011);
wire VAR33 = (VAR62 && VAR87 == 6'b000111);
wire VAR83 = (VAR62 && VAR87 == 6'b000010);
wire VAR39 = (VAR62 && VAR87 == 6'b000110);
assign VAR48 = {(VAR91|VAR51), (VAR54|VAR33), (VAR83|VAR39)};
wire and = (VAR62 && VAR87 == 6'b100100);
wire VAR107 = (VAR79 == 6'b001100);
wire or = (VAR62 && VAR87 == 6'b100101);
wire VAR117 = (VAR79 == 6'b001101);
wire nor = (VAR62 && VAR87 == 6'b100111);
wire xor = (VAR62 && VAR87 == 6'b100110);
wire VAR42 = (VAR79 == 6'b001110);
assign logic = {xor, nor, (and|VAR107), (or|VAR117)};
wire VAR27 = VAR79 == 6'b000010;
wire VAR96 = VAR79 == 6'b000011;
wire VAR85 = (VAR62 && VAR87 == 6'b001001);
wire VAR13 = (VAR62 && VAR87 == 6'b001000);
assign VAR28 = VAR27 | VAR96 | VAR85 | VAR13;
wire VAR94 = (VAR79 == 6'b000100 && VAR113 == 5'b00000 && VAR105 == 5'b00000);
wire VAR120 = (VAR5 && VAR113 == 5'b00000 && VAR105 == 5'b10001);
wire VAR10 = VAR79 == 6'b000100;
wire VAR8 = VAR79 == 6'b010100;
wire VAR98 = (VAR5 && VAR105 == 5'b00001);
wire VAR3 = (VAR5 && VAR105 == 5'b10001);
wire VAR1 = (VAR5 && VAR105 == 5'b10011);
wire VAR37 = (VAR5 && VAR105 == 5'b00011);
wire VAR24 = VAR79 == 6'b000111;
wire VAR93 = VAR79 == 6'b010111;
wire VAR43 = VAR79 == 6'b000110;
wire VAR81 = VAR79 == 6'b010110;
wire VAR74 = (VAR5 && VAR105 == 5'b00000);
wire VAR80 = (VAR5 && VAR105 == 5'b10000);
wire VAR108 = (VAR5 && VAR105 == 5'b10010);
wire VAR53 = (VAR5 && VAR105 == 5'b00010);
wire VAR104 = VAR79 == 6'b000101;
wire VAR109 = VAR79 == 6'b010101;
always @* begin
case ({VAR94,VAR120,VAR10,VAR8,VAR98,VAR3,VAR1,VAR37,VAR24,VAR93,VAR43,VAR81,VAR74,VAR80,VAR108,VAR53,VAR104,VAR109})
18'b10000000000000000 : VAR41 <= 1; 18'b01000000000000000 : VAR41 <= 1; 18'b00100000000000000 ,
18'b00010000000000000 : VAR41 <= (VAR26 == VAR11) ? 1 : 0;
18'b00001000000000000 , 18'b00000100000000000 , 18'b00000010000000000 , 18'b00000001000000000 : begin VAR41 <= (VAR26 >= 32'b0) ? 1 : 0; end
18'b00000000100000000 , 18'b00000000010000000 : begin VAR41 <= (VAR26 > 32'b0) ? 1 : 0; end
18'b00000000001000000 , 18'b00000000000100000 , 18'b00000000000010000 , 18'b00000000000001000 , 18'b00000000000000100 : begin VAR41 <= (VAR26 < 32'b0) ? 1 : 0; end
18'b00000000000000010 , 18'b00000000000000001 : begin VAR41 <= (VAR26 != VAR11) ? 1 : 0; end
endcase
end
wire break = (VAR62 && VAR87 == 6'b001101);
wire VAR71 = VAR79 == 6'b101111;
wire VAR102 = VAR101 && (VAR87 == 6'b100001);
wire VAR30 = VAR101 && (VAR87 == 6'b100000);
assign VAR22 = {VAR30, VAR102};
wire VAR119 = (VAR79 == 6'b100000);
wire VAR67 = (VAR79 == 6'b100100);
wire VAR19 = (VAR79 == 6'b100001);
wire VAR32 = (VAR79 == 6'b100101);
wire VAR31 = (VAR79 == 6'b110000);
wire VAR49 = (VAR79 == 6'b001111);
wire VAR92 = (VAR79 == 6'b100011);
wire VAR60 = (VAR79 == 6'b100010);
wire VAR59 = (VAR79 == 6'b100110);
assign VAR44 = (VAR119 | VAR67 | VAR19 | VAR32 | VAR31 | VAR49 | VAR92 | VAR60 | VAR59);
assign VAR72 = {VAR119, VAR67, VAR19, VAR32, VAR31, VAR49, VAR92, VAR60, VAR59};
wire VAR65 = (VAR79 == 6'b101000);
wire VAR118 = (VAR79 == 6'b111000);
wire VAR110 = (VAR79 == 6'b101001);
wire VAR47 = (VAR79 == 6'b101011);
wire VAR95 = (VAR79 == 6'b101010);
wire VAR15 = (VAR79 == 6'b101110);
assign VAR21 = (VAR65 | VAR118 | VAR110 | VAR47 | VAR95 | VAR15);
assign VAR99 = {VAR65, VAR118, VAR110, VAR47, VAR95, VAR15};
wire sync = (VAR62 && VAR87 == 6'b001111);
wire VAR63 = VAR68[10:6];
wire VAR70 = (VAR62 && VAR87 == 6'b110100);
wire VAR14 = (VAR5 && VAR105 == 5'b01100);
wire VAR73 = (VAR62 && VAR87 == 6'b110000);
wire VAR76 = (VAR5 && VAR105 == 5'b01000);
wire VAR89 = (VAR5 && VAR105 == 5'b01001);
wire VAR52 = (VAR62 && VAR87 == 5'b11001);
wire VAR57 = (VAR62 && VAR87 == 6'b110010);
wire VAR20 = (VAR5 && VAR105 == 5'b01010);
wire VAR100 = (VAR5 && VAR105 == 5'b01011);
wire VAR84 = (VAR62 && VAR87 == 6'b110011);
wire VAR7 = (VAR62 && VAR87 == 6'b110110);
wire VAR103 = (VAR5 && VAR105 == 5'b01110);
wire VAR88 = (VAR62 && VAR87 == 6'b010000);
wire VAR86 = (VAR62 && VAR87 == 6'b010010);
wire VAR90 = (VAR62 && VAR87 == 6'b001011);
wire VAR50 = (VAR62 && VAR87 == 6'b001010);
assign VAR112 = (VAR88 | VAR86 | VAR90 | VAR50);
assign VAR66 = {VAR88, VAR86, VAR90, VAR50};
wire VAR111 = (VAR79 == 6'b110011);
assign VAR23 = (VAR25|VAR55|(|VAR48)|(|logic)|VAR112|VAR44|VAR120|VAR3|VAR1|VAR37|VAR80|VAR108|VAR96|VAR85);
assign VAR16 = VAR21;
assign VAR35 = VAR44;
assign VAR114 = VAR44;
assign VAR6 = (VAR62 && (VAR79 != 6'b001000)) ? rd : VAR105;
always @(posedge clk) begin
VAR68 <= VAR34 ? VAR68 : VAR58;
case ({VAR34, VAR27, VAR96, VAR85, VAR13,VAR41})
6'b100000 : VAR115 <= VAR17;
6'b010000 : VAR115 <= {VAR17[31:28], VAR61, 2'b00};
6'b001000 : VAR115 <= {VAR17[31:28], VAR61, 2'b00};
6'b000100 : VAR115 <= VAR26;
6'b000010 : VAR115 <= VAR26;
6'b000001 : VAR115 <= VAR9;
endcase
end
always @* begin
VAR113 <= VAR68[25:21];
VAR105 <= VAR68[20:16];
if (VAR120 | VAR3 | VAR1 | VAR37 | VAR80 | VAR108 | VAR96 | VAR85) begin
VAR116 <= VAR17 + 32'h0000008;
rd <= 5'b11111;
end else begin
rd <= VAR68[15:11];
end
end
endmodule | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab0-1v2/fsm.v | 1,588 | module MODULE1(VAR6, VAR5, clk, reset, VAR3);
input wire VAR6, clk, reset;
output wire VAR5;
output wire [2:0] VAR3;
reg [2:0] VAR10;
reg [2:0] VAR12;
localparam VAR11 = 3'b000,
VAR13 = 3'b001,
VAR9 = 3'b010,
VAR1 = 3'b011,
VAR2 = 3'b100,
VAR4 = 3'b101,
VAR8 = 3'b110,
VAR7 = 3'b111;
always @(posedge clk) begin
if (reset) VAR10 <= VAR11;
end
else VAR10 <= VAR12;
end
assign VAR5 = (VAR10 == VAR4) | (VAR10 == VAR8);
assign VAR3 = VAR10;
always @(*) begin
VAR12 = VAR10;
case (VAR10)
VAR11: begin
if (VAR6) VAR12 = VAR13;
end
else VAR12 = VAR11;
end
VAR13 : begin
if (VAR6) VAR12 = VAR13;
end
else VAR12 = VAR9;
end
VAR9 : begin
if (VAR6) VAR12 = VAR1;
end
else VAR12 = VAR11;
end
VAR1 : begin
if (VAR6) VAR12 = VAR2;
end
else VAR12 = VAR9;
end
VAR2 : begin
if (VAR6) VAR12 = VAR4;
end
else VAR12 = VAR8;
end
VAR4 : begin
if (VAR6) VAR12 = VAR13;
end
else VAR12 = VAR9;
end
VAR8 : begin
if (VAR6) VAR12 = VAR1;
end
else VAR12 = VAR11;
end
VAR7 : begin
VAR12 = VAR11;
end
endcase
end
endmodule | mit |
marqs85/ossc | rtl/ir_rcv.v | 5,867 | module MODULE1 (
input VAR8,
input VAR3,
input VAR11,
output reg [15:0] VAR14,
output reg VAR20,
output reg [7:0] VAR5
);
parameter VAR23 = 200000; parameter VAR15 = 100000; parameter VAR22 = 160000; parameter VAR7 = 54000; parameter VAR13 = 3240000; parameter VAR19 = 27000; parameter VAR12 = 7628; parameter VAR16 = 141480;
reg [1:0] state; reg [31:0] VAR10; reg [5:0] VAR6; reg [17:0] VAR1; reg [17:0] VAR18; reg [17:0] VAR21; reg [21:0] VAR17;
always @(posedge VAR8 or negedge VAR3)
begin
if (!VAR3)
VAR1 <= 0;
end
else
begin
if ((state == VAR4) & (~VAR11))
VAR1 <= VAR1 + 1'b1;
end
else
VAR1 <= 0;
end
end
always @(posedge VAR8 or negedge VAR3)
begin
if (!VAR3)
VAR18 <= 0;
end
else
begin
if ((state == VAR9) & VAR11)
VAR18 <= VAR18 + 1'b1;
end
else
VAR18 <= 0;
end
end
always @(posedge VAR8 or negedge VAR3)
begin
if (!VAR3)
begin
VAR21 <= 0;
VAR6 <= 0;
VAR10 <= 0;
end
else
begin
if (state == VAR2)
begin
if (VAR11)
VAR21 <= VAR21 + 1'b1;
end
else
VAR21 <= 0;
if (VAR21 == VAR12)
VAR6 <= VAR6 + 1'b1;
if (VAR21 == VAR19)
VAR10[32-VAR6] <= 1'b1;
end
else
begin
VAR21 <= 0;
VAR6 <= 0;
VAR10 <= 0;
end
end
end
always @(posedge VAR8 or negedge VAR3)
begin
if (!VAR3)
begin
VAR20 <= 1'b0;
VAR14 <= 16'h00000000;
end
else
begin
if ((VAR6 == 32) & (VAR10[31:24] == ~VAR10[23:16]) & (VAR10[15:8] == ~VAR10[7:0]))
begin
VAR14 <= {VAR10[31:24], VAR10[15:8]};
VAR20 <= 1'b1;
end
else if (VAR17 >= VAR13)
begin
VAR14 <= 16'h00000000;
VAR20 <= 1'b0;
end
else
VAR20 <= 1'b0;
end
end
always @(posedge VAR8 or negedge VAR3)
begin
if (!VAR3)
begin
state <= VAR4;
VAR17 <= 0;
VAR5 <= 0;
end
else
begin
VAR17 <= VAR17 + 1'b1;
case (state)
begin
if ((VAR1 >= VAR23) & VAR11)
state <= VAR9;
if (VAR17 >= VAR13)
VAR5 <= 0;
end
begin
if (VAR18 == VAR7)
begin
if (VAR14 != 0)
VAR5 <= VAR5 + 1'b1;
VAR17 <= 0;
end
if (!VAR11)
state <= (VAR18 >= VAR15) ? VAR2 : VAR4;
end
else if (VAR18 >= VAR22)
state <= VAR4;
end
begin
if (VAR20 == 1'b1)
VAR5 <= 1;
if ((VAR21 >= VAR16)|VAR6 >= 33)
state <= VAR4;
end
default:
state <= VAR4;
endcase
end
end
endmodule | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController4L/src/dev_tx_cmd_fifo.v | 9,581 | module MODULE1 # (
parameter VAR64 = 30,
parameter VAR55 = 4
)
(
input VAR24,
input VAR13,
input VAR67,
input [VAR64-1:0] VAR51,
output VAR27,
input VAR18,
input VAR52,
input VAR59,
output [VAR64-1:0] VAR14,
output VAR9
);
localparam VAR12 = 1;
localparam VAR21 = 3'b001;
localparam VAR58 = 3'b010;
localparam VAR7 = 3'b100;
reg [2:0] VAR45;
reg [2:0] VAR46;
reg [2:0] VAR65;
reg [2:0] VAR2;
reg [VAR55:0] VAR8;
reg VAR30;
reg VAR17;
reg [VAR55
:VAR12] VAR28;
reg VAR60;
reg VAR50;
reg [VAR55
:VAR12] VAR10;
reg [VAR55:0] VAR54;
reg [VAR55:0] VAR56;
reg VAR37;
reg VAR34;
reg [VAR55
:VAR12] VAR49;
reg VAR29;
reg VAR40;
reg [VAR55
:VAR12] VAR3;
wire [VAR55-1:0] VAR68;
assign VAR27 = ~((VAR8[VAR55] ^ VAR10[VAR55])
& (VAR8[VAR55-1:VAR12]
== VAR10[VAR55-1:VAR12]));
always @(posedge VAR24 or negedge VAR13)
begin
if (VAR13 == 0) begin
VAR8 <= 0;
end
else begin
if (VAR67 == 1)
VAR8 <= VAR8 + 1;
end
end
assign VAR9 = ~(VAR54[VAR55:VAR12]
== VAR3);
always @(posedge VAR18 or negedge VAR52)
begin
if (VAR52 == 0) begin
VAR54 <= 0;
VAR56 <= 1;
end
else begin
if (VAR59 == 1) begin
VAR54 <= VAR56;
VAR56 <= VAR56 + 1;
end
end
end
assign VAR68 = (VAR59 == 1) ? VAR56[VAR55-1:0]
: VAR54[VAR55-1:0];
always @ (posedge VAR24 or negedge VAR13)
begin
if(VAR13 == 0)
VAR45 <= VAR21;
end
else
VAR45 <= VAR46;
end
always @(posedge VAR24 or negedge VAR13)
begin
if(VAR13 == 0)
VAR17 <= 0;
end
else
VAR17 <= VAR30;
end
always @(posedge VAR24)
begin
VAR60 <= VAR34;
VAR50 <= VAR60;
end
always @
begin
case(VAR45)
VAR21: begin
VAR30 <= 0;
end
VAR58: begin
VAR30 <= 0;
end
VAR7: begin
VAR30 <= 1;
end
default: begin
VAR30 <= 0;
end
endcase
end
always @ (posedge VAR18 or negedge VAR52)
begin
if(VAR52 == 0)
VAR65 <= VAR21;
end
else
VAR65 <= VAR2;
end
always @(posedge VAR18 or negedge VAR52)
begin
if(VAR52 == 0)
VAR34 <= 0;
end
else
VAR34 <= VAR37;
end
always @(posedge VAR18)
begin
VAR29 <= VAR17;
VAR40 <= VAR29;
end
always @
begin
case(VAR65)
VAR21: begin
VAR37 <= 1;
end
VAR58: begin
VAR37 <= 1;
end
VAR7: begin
VAR37 <= 0;
end
default: begin
VAR37 <= 0;
end
endcase
end
localparam VAR62 = "7SERIES";
localparam VAR31 = "18Kb";
localparam VAR1 = 0;
localparam VAR4 = VAR64;
localparam VAR5 = VAR64;
localparam VAR69 = "VAR15";
localparam VAR44 = 4;
localparam VAR23 = 9;
localparam VAR19 = VAR23 - VAR55;
generate
wire [VAR23-1:0] VAR22;
wire [VAR23-1:0] VAR11;
wire [VAR19-1:0] VAR35 = 0;
if(VAR19 == 0) begin : VAR20
assign VAR22 = VAR68[VAR55-1:0];
assign VAR11 = VAR8[VAR55-1:0];
end
else begin
wire [VAR19-1:0] VAR35 = 0;
assign VAR22 = {VAR35, VAR68[VAR55-1:0]};
assign VAR11 = {VAR35, VAR8[VAR55-1:0]};
end
endgenerate
VAR39 #(
.VAR66 (VAR62),
.VAR25 (VAR31),
.VAR6 (VAR1),
.VAR53 (VAR4),
.VAR33 (VAR5),
.VAR47 (VAR69)
)
VAR32(
.VAR38 (VAR14),
.VAR41 (VAR51),
.VAR16 (VAR22),
.VAR61 (VAR18),
.VAR36 (1'b1),
.VAR48 (1'b1),
.VAR43 (1'b0),
.VAR57 ({VAR44{1'b1}}),
.VAR63 (VAR11),
.VAR26 (VAR24),
.VAR42 (VAR67)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb.pp.symbol.v | 1,334 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR9 ,
input VAR3 ,
output VAR2 ,
input VAR5 ,
input VAR4,
input VAR1,
input VAR7
);
endmodule | apache-2.0 |
marqs85/de2-vd | rtl/linebuf.v | 9,189 | module MODULE1 (
VAR39,
VAR43,
VAR13,
VAR40,
VAR32,
VAR41,
VAR17);
input [23:0] VAR39;
input [11:0] VAR43;
input VAR13;
input [11:0] VAR40;
input VAR32;
input VAR41;
output [23:0] VAR17;
tri1 VAR32;
tri0 VAR41;
wire [23:0] VAR3;
wire [23:0] VAR17 = VAR3[23:0];
VAR33 VAR58 (
.VAR34 (VAR40),
.VAR4 (VAR43),
.VAR14 (VAR32),
.VAR8 (VAR13),
.VAR51 (VAR39),
.VAR57 (VAR41),
.VAR53 (VAR3),
.VAR42 (1'b0),
.VAR52 (1'b0),
.VAR37 (1'b0),
.VAR26 (1'b0),
.VAR6 (1'b1),
.VAR19 (1'b1),
.VAR30 (1'b1),
.VAR56 (1'b1),
.VAR18 (1'b1),
.VAR25 (1'b1),
.VAR23 ({24{1'b1}}),
.VAR16 (),
.VAR20 (),
.VAR35 (1'b1),
.VAR9 (1'b1),
.VAR55 (1'b0));
VAR58.VAR28 = "VAR44",
VAR58.VAR21 = "VAR15",
VAR58.VAR24 = "VAR27",
VAR58.VAR11 = "VAR27",
VAR58.VAR59 = "VAR27",
VAR58.VAR29 = "VAR22 VAR46 VAR50",
VAR58.VAR12 = "VAR33",
VAR58.VAR7 = 4096,
VAR58.VAR47 = 4096,
VAR58.VAR36 = "VAR31",
VAR58.VAR48 = "VAR44",
VAR58.VAR2 = "VAR15",
VAR58.VAR1 = "VAR38",
VAR58.VAR54 = 12,
VAR58.VAR5 = 12,
VAR58.VAR49 = 24,
VAR58.VAR45 = 24,
VAR58.VAR10 = 1;
endmodule | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/pcie_data_sender.v | 4,415 | module MODULE1 #(parameter VAR22 = 128, VAR7 = 8) (
input clk,
input rst,
output VAR19,
input VAR4,
input[7:0] VAR27,
output VAR8,
input VAR1,
output VAR11,
output[VAR16 - 1:0] VAR9,
output[30:0] VAR5,
output[VAR22 - 1:0] VAR24,
output reg VAR26,
input VAR14,
input[VAR16 - 1:0] VAR10,
output VAR6,
input en
);
localparam VAR23 = VAR22/VAR7; parameter VAR25 = VAR21(VAR23);
reg state = VAR17;
localparam VAR17 = 1'b0;
localparam VAR15 = 1'b1;
reg[VAR16 - 1:0] VAR18, VAR2;
reg VAR20;
always@(posedge clk) begin
if(rst) begin
state <= VAR17;
VAR18 <= 0;
VAR2 <= 0;
end
else begin
case(state)
VAR17: begin
if(en) begin
VAR18 <= (VAR10 - 1) >> 4;
VAR2 <= (VAR10 - 1) >> 2;
state <= VAR15;
end
end VAR15: begin
if(VAR20) begin
VAR18 <= VAR18 - 1;
if(VAR18 == 1) begin
state <= VAR17;
end
end
end
endcase
end
end
assign VAR6 = (state == VAR17);
reg[VAR7 - 1:0] VAR28;
reg VAR12;
wire VAR3 = VAR19;
always@(posedge clk) begin
if(rst) begin
VAR28 <= 0;
VAR12 <= 0;
end
else begin
if(VAR3) begin
VAR28 <= VAR27;
VAR12 <= VAR4;
end
end
end
reg[VAR25 - 1:0] VAR30 = 0;
reg[VAR22 - 1:0] VAR13;
reg VAR29 = 0;
always@(posedge clk) begin
if(rst) begin
VAR13 <= 0;
VAR29 <= 0;
end
else begin
if(VAR12 && VAR19) begin
VAR13[VAR30*VAR7 +:VAR7] <= VAR28;
VAR30 <= VAR30 + 1'b1;
VAR29 <= &VAR30;
end
else if(VAR20) begin
VAR29 <= 1'b0;
end
end
end
assign VAR9 = VAR2; assign VAR11 = 1'b1; assign VAR5 = 0;
assign VAR24 = VAR13;
assign VAR8 = (state == VAR15);
always@* begin
VAR20 = 1'b0;
VAR26 = 1'b0;
if(state == VAR15) begin
if(VAR29) begin
VAR26 = 1'b1;
if(VAR14) begin
VAR20 = 1'b1;
end
end end
end
assign VAR19 = ~VAR29 || (VAR29 && VAR20);
endmodule | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/HPS/HPS_bb.v | 2,103 | module MODULE1 (
VAR24,
VAR11,
VAR3,
VAR27,
VAR34,
VAR21,
VAR25,
VAR4,
VAR26,
VAR9,
VAR30,
VAR36,
VAR32,
VAR31,
VAR17,
VAR5,
VAR6,
VAR22,
VAR20,
VAR7,
VAR14,
VAR8,
VAR16,
VAR29,
VAR12,
VAR19,
VAR33,
VAR2,
VAR15,
VAR10,
VAR35,
VAR28,
VAR23,
VAR13,
VAR18,
VAR1);
output [14:0] VAR24;
output [2:0] VAR11;
output VAR3;
output VAR27;
output VAR34;
output VAR21;
output VAR25;
output VAR4;
output VAR26;
output VAR9;
inout [31:0] VAR30;
inout [3:0] VAR36;
inout [3:0] VAR32;
output VAR31;
output [3:0] VAR17;
input VAR5;
inout VAR6;
inout VAR22;
inout VAR20;
inout VAR7;
inout VAR14;
inout VAR8;
inout VAR16;
inout VAR29;
inout VAR12;
inout VAR19;
inout VAR33;
inout VAR2;
inout VAR15;
inout VAR10;
inout VAR35;
output [66:0] VAR28;
input [66:0] VAR23;
input [66:0] VAR13;
input [31:0] VAR18;
output [31:0] VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvn/sky130_fd_sc_hvl__einvn.symbol.v | 1,339 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR1
);
supply1 VAR7;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o.pp.blackbox.v | 1,374 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR4 ,
VAR2 ,
VAR7,
VAR3
);
output VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR2 ;
input VAR7;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtn/sky130_fd_sc_ls__dlxtn.pp.symbol.v | 1,341 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR2,
input VAR1 ,
input VAR4 ,
input VAR7 ,
input VAR3
);
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/lsu_non_aligned_write.v | 11,877 | module MODULE1
(
clk, VAR4, reset, VAR22, VAR75, VAR25, VAR56, VAR38, VAR1, VAR41,
VAR20, VAR36, VAR57, VAR43, VAR60, VAR21, VAR65,
VAR70, VAR17
);
parameter VAR42=32; parameter VAR35=4; parameter VAR67=32; parameter VAR18=2; parameter VAR62=32; parameter VAR31=32;
parameter VAR68=6; parameter VAR16=0; parameter VAR27=1;
parameter VAR26=0;
localparam VAR29=8*VAR35;
localparam VAR33=8*VAR67;
localparam VAR30=VAR28(VAR67);
localparam VAR40 = VAR67/VAR35;
localparam VAR71 = VAR28(VAR40);
localparam VAR55=VAR28(VAR35)-VAR18;
input clk;
input VAR4;
input reset;
output VAR22;
input VAR75;
input [VAR42-1:0] VAR25;
input [VAR29-1:0] VAR56;
input VAR38;
output VAR41;
output reg VAR20;
input [VAR35-1:0] VAR1;
output [VAR42-1:0] VAR36;
output VAR57;
input VAR43;
output [VAR33-1:0] VAR60;
output [VAR67-1:0] VAR21;
input VAR65;
output [VAR68-1:0] VAR70;
input VAR17;
reg VAR52;
reg [VAR42-VAR30-1:0] VAR3;
reg [VAR42-1:0] VAR66;
reg [VAR29-1:0] VAR53;
reg VAR63;
reg VAR9;
reg [VAR35-1:0] VAR10;
reg [VAR55-1:0] VAR23 = 0;
wire VAR46;
assign VAR22 = VAR52 & VAR46;
always@(posedge clk or posedge reset)
begin
if (reset) VAR52 <= 1'b0;
end
else if (~VAR22) VAR52 <= VAR75;
end
always@(posedge clk) begin
if (~VAR22 & VAR75 & ~VAR17) begin
VAR66 <= VAR25;
VAR3 <= VAR25[VAR42-1:VAR30] + 1'b1;
VAR23 <= VAR25[VAR18+VAR55-1:VAR18];
VAR53 <= VAR56;
VAR10 <= VAR26? (VAR17? '0 : VAR1) : '1;
end
if (~VAR22) begin
VAR63 <= VAR17;
VAR9 <= !VAR17 & VAR3 === VAR25[VAR42-1:VAR30]
& VAR25[VAR18+VAR55-1:VAR18] > VAR23;
end
end
MODULE2 #(
.VAR62(VAR62),
.VAR31(VAR31),
.VAR42(VAR42),
.VAR35(VAR35),
.VAR67(VAR67),
.VAR68(VAR68),
.VAR18(VAR18),
.VAR16(VAR16),
.VAR26(1),
.VAR27(VAR27)
) VAR64 (
.clk(clk),
.VAR4(VAR4),
.reset(reset),
.VAR22(VAR46),
.VAR75(VAR52),
.VAR25(VAR66),
.VAR56(VAR53),
.VAR38(VAR38),
.VAR1(VAR10),
.VAR41(VAR41),
.VAR20(VAR20),
.VAR36(VAR36),
.VAR57(VAR57),
.VAR43(VAR43),
.VAR60(VAR60),
.VAR21(VAR21),
.VAR70(VAR70),
.VAR65(VAR65),
.VAR17(VAR63),
.VAR45(VAR9)
);
endmodule
module MODULE2
(
clk, VAR4, reset, VAR22, VAR75, VAR25, VAR56, VAR38, VAR1, VAR41,
VAR20, VAR36, VAR57, VAR43, VAR60, VAR21, VAR65,
VAR70,
VAR17,
VAR45
);
parameter VAR42=32; parameter VAR35=4; parameter VAR67=32; parameter VAR18=2; parameter VAR62=160; parameter VAR31=0; parameter VAR68=6; parameter VAR13=0;
parameter VAR16=0;
parameter VAR14=8;
parameter VAR27=1;
parameter VAR26=0;
localparam VAR29=VAR35*8;
localparam VAR33=VAR67*8;
localparam VAR19=VAR62+1;
localparam VAR11=VAR28(VAR35);
localparam VAR12=VAR28(VAR14);
localparam VAR30=VAR28(VAR67);
localparam VAR55=VAR28(VAR35)-VAR18;
localparam VAR61=2**VAR18;
localparam VAR76=8*VAR61;
localparam VAR73 = VAR67/VAR61;
input clk;
input VAR4;
input reset;
input VAR17;
output VAR22;
input VAR75;
input [VAR42-1:0] VAR25;
input [VAR29-1:0] VAR56;
input VAR38;
output VAR41;
output VAR20;
input [VAR35-1:0] VAR1;
output [VAR42-1:0] VAR36;
output VAR57;
input VAR43;
output [VAR33-1:0] VAR60;
output [VAR67-1:0] VAR21;
input VAR65;
output [VAR68-1:0] VAR70;
input VAR45;
wire VAR7;
wire VAR34;
wire [VAR42-1:0] VAR24;
wire [2*VAR29-1:0] VAR39;
wire [2*VAR35-1:0] VAR15;
wire [VAR42-VAR30-1:0] VAR32 = VAR25[VAR42-1:VAR30];
wire [VAR30-1:0] VAR37=VAR25[VAR30-1:0];
reg VAR52, VAR51, VAR2;
reg [VAR42-1:0] VAR66;
reg [VAR29-1:0] VAR53, VAR6;
reg [VAR35-1:0] VAR58, VAR69;
wire [VAR55-1:0] VAR23;
wire VAR59;
logic VAR54;
wire VAR46;
assign VAR7 = VAR52 & VAR46;
assign VAR22 = VAR7 | VAR54 & !VAR17 & !VAR45;
reg [VAR42-VAR30-1:0] VAR5;
assign VAR24[VAR42-1:VAR30] = VAR54? VAR5 : VAR32;
assign VAR24[VAR30-1:0] = VAR54? '0 : VAR59? VAR25[VAR30-1:0] : {VAR25[VAR30-1:VAR18] - VAR23, {VAR18{1'b0}}};
assign VAR23 = VAR25[VAR18+VAR55-1:VAR18];
assign VAR15 = {{VAR35{1'b0}},VAR1} << {VAR23, {VAR18{1'b0}}};
assign VAR39 = {{VAR29{1'b0}},VAR56} << {VAR23, {VAR18{1'b0}}, 3'd0};
assign VAR59 = (VAR25[VAR30-1:0]+ VAR35) <= VAR67;
assign request = VAR54 | VAR75;
assign VAR34 = VAR75 | VAR54;
always@(posedge clk or posedge reset)
begin
if (reset) begin
VAR52 <= 1'b0;
VAR2 <= 1'b0;
VAR54 <= 1'b0;
end
else begin
if (~VAR7) begin
VAR52 <= VAR34;
VAR2 <= VAR75 & (!VAR54 | VAR17 | VAR45); VAR54 <= VAR75 & !VAR22 & !VAR17 & !VAR59;
end
else if(!VAR46) VAR54 <= 1'b0;
end
end
reg [VAR30-1-VAR18:0]VAR48;
reg [VAR29-1:0] VAR72;
reg [VAR35-1:0] VAR44;
reg VAR74;
always @(posedge clk) begin
if(VAR75 & ~VAR17 & ~VAR22) VAR5 <= VAR32 + 1'b1;
if(~VAR7) begin
VAR66 <= VAR24;
VAR51 <= VAR54? 1'b0 : VAR17;
VAR6 <= VAR39[2*VAR29-1:VAR29];
VAR69 <= VAR15[2*VAR35-1:VAR35];
VAR53 <= VAR54 ? VAR6: VAR59? VAR56 : VAR39[VAR29-1:0];
VAR58 <= VAR54 ? VAR69: VAR59? VAR1 : VAR15[VAR35-1:0];
VAR74 <= VAR54 & VAR45;
VAR48 <= VAR25[VAR30-1:VAR18];
VAR72 <= VAR56;
VAR44 <= VAR1;
end
end
VAR8 #(
.VAR62(VAR62),
.VAR31(VAR31),
.VAR42(VAR42),
.VAR35(VAR35),
.VAR67(VAR67),
.VAR68(VAR68),
.VAR18(VAR18),
.VAR16(VAR16),
.VAR26(1'b1),
.VAR47(1),
.VAR27(VAR27)
) VAR49 (
.clk(clk),
.VAR4(VAR4),
.reset(reset),
.VAR17(VAR51),
.VAR22(VAR46),
.VAR75(VAR52),
.VAR50(VAR2),
.VAR25(VAR66),
.VAR56(VAR53),
.VAR48(VAR48),
.VAR72(VAR72),
.VAR44(VAR44),
.VAR74(VAR74),
.VAR38(VAR38),
.VAR41(VAR41),
.VAR20(VAR20),
.VAR1(VAR58),
.VAR36(VAR36),
.VAR57(VAR57),
.VAR43(VAR43),
.VAR60(VAR60),
.VAR21(VAR21),
.VAR70(VAR70),
.VAR65(VAR65)
);
endmodule | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_gtp_pipe_rate.v | 16,176 | module MODULE1 #
(
parameter VAR22 = "VAR25", parameter VAR39 = 4'd15
)
(
input VAR34,
input VAR10,
input [ 1:0] VAR50,
input VAR18,
input VAR9,
input VAR55,
input VAR12,
input VAR17,
input VAR48,
output VAR23,
output VAR4,
output VAR29,
output [ 2:0] VAR46,
output VAR11,
output VAR33,
output VAR6,
output [ 4:0] VAR54
);
reg [ 1:0] VAR31;
reg VAR7;
reg VAR45;
reg VAR13;
reg VAR53;
reg VAR30;
reg VAR37;
reg [ 1:0] VAR16;
reg VAR40;
reg VAR2;
reg VAR15;
reg VAR24;
reg VAR32;
reg VAR51;
wire [ 2:0] VAR47;
reg [ 3:0] VAR43 = 4'd0;
reg VAR42 = 1'd0;
reg VAR26 = 1'd0;
reg VAR27 = 1'd0;
reg VAR52 = 1'd0;
reg VAR36 = 1'd0;
reg [ 2:0] VAR5 = 3'd0;
reg [ 3:0] fsm = 0;
localparam VAR8 = 0;
localparam VAR49 = 1;
localparam VAR35 = 2;
localparam VAR41 = 3;
localparam VAR56 = 4;
localparam VAR28 = 5;
localparam VAR20 = 6;
localparam VAR38 = 7;
localparam VAR14 = 8;
localparam VAR3 = 9;
localparam VAR1 = 10;
localparam VAR44 = 11;
localparam VAR21 = 12;
always @ (posedge VAR34)
begin
if (!VAR10)
begin
VAR31 <= 2'd0;
VAR7 <= 1'd0;
VAR45 <= 1'd0;
VAR13 <= 1'd0;
VAR53 <= 1'd0;
VAR30 <= 1'd0;
VAR37 <= 1'd0;
VAR16 <= 2'd0;
VAR40 <= 1'd0;
VAR2 <= 1'd0;
VAR15 <= 1'd0;
VAR24 <= 1'd0;
VAR32 <= 1'd0;
VAR51 <= 1'd0;
end
else
begin
VAR31 <= VAR50;
VAR7 <= VAR18;
VAR45 <= VAR9;
VAR13 <= VAR55;
VAR53 <= VAR12;
VAR30 <= VAR48;
VAR37 <= VAR17;
VAR16 <= VAR31;
VAR40 <= VAR7;
VAR2 <= VAR45;
VAR15 <= VAR13;
VAR24 <= VAR53;
VAR32 <= VAR30;
VAR51 <= VAR37;
end
end
assign VAR47 = (VAR16 == 2'd1) ? 3'd1 : 3'd0;
always @ (posedge VAR34)
begin
if (!VAR10)
VAR43 <= 4'd0;
end
else
if ((fsm == VAR49) && (VAR43 < VAR39))
VAR43 <= VAR43 + 4'd1;
else if ((fsm == VAR49) && (VAR43 == VAR39))
VAR43 <= VAR43;
else
VAR43 <= 4'd0;
end
always @ (posedge VAR34)
begin
if (!VAR10)
begin
VAR42 <= 1'd0;
VAR26 <= 1'd0;
VAR27 <= 1'd0;
VAR52 <= 1'd0;
end
else
begin
if ((fsm == VAR3) || (fsm == VAR20) || (fsm == VAR38) || (fsm == VAR14))
begin
if (VAR15)
VAR42 <= 1'd1;
end
else
VAR42 <= VAR42;
if (VAR24)
VAR26 <= 1'd1;
end
else
VAR26 <= VAR26;
if (VAR32)
VAR27 <= 1'd1;
end
else
VAR27 <= VAR27;
if (VAR26 && VAR42 && VAR27)
VAR52 <= 1'd1;
else
VAR52 <= VAR52;
end
else
begin
VAR42 <= 1'd0;
VAR26 <= 1'd0;
VAR27 <= 1'd0;
VAR52 <= 1'd0;
end
end
end
always @ (posedge VAR34)
begin
if (!VAR10)
begin
fsm <= VAR8;
VAR36 <= 1'd0;
VAR5 <= 3'd0;
end
else
begin
case (fsm)
VAR8 :
begin
if (VAR16 != VAR31)
begin
fsm <= VAR49;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
else
begin
fsm <= VAR8;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
end
VAR49 :
begin
fsm <= (VAR43 == VAR39) ? VAR35 : VAR49;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
VAR35 :
begin
fsm <= (VAR22 == "VAR19") ? VAR28 : VAR41;
VAR36 <= (VAR16 == 2'd1);
VAR5 <= VAR5;
end
VAR41 :
begin
fsm <= (!VAR40) ? VAR56 : VAR41;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
VAR56 :
begin
fsm <= VAR40 ? VAR28 : VAR56;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
VAR28 :
begin
fsm <= (VAR22 == "VAR19") ? VAR3 : VAR20;
VAR36 <= VAR36;
VAR5 <= VAR47; end
VAR20 :
begin
fsm <= (!VAR2) ? VAR38 : VAR20;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
VAR38 :
begin
fsm <= (!VAR40) ? VAR14 : VAR38;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
VAR14 :
begin
fsm <= VAR40 ? VAR3 : VAR14;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
VAR3 :
begin
if (VAR52)
fsm <= VAR1;
end
else
fsm <= VAR3;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
VAR1:
begin
fsm <= (!VAR51 ? VAR44 : VAR1);
VAR36 <= VAR36;
VAR5 <= VAR5;
end
VAR44:
begin
fsm <= (VAR51 ? VAR21 : VAR44);
VAR36 <= VAR36;
VAR5 <= VAR5;
end
VAR21 :
begin
fsm <= VAR8;
VAR36 <= VAR36;
VAR5 <= VAR5;
end
default :
begin
fsm <= VAR8;
VAR36 <= 1'd0;
VAR5 <= 3'd0;
end
endcase
end
end
assign VAR23 = VAR36;
assign VAR4 = (fsm == VAR41) || (fsm == VAR38);
assign VAR29 = (fsm == VAR41) || (fsm == VAR56);
assign VAR46 = VAR5;
assign VAR11 = (fsm == VAR1);
assign VAR33 = (fsm == VAR21);
assign VAR6 = (fsm == VAR8);
assign VAR54 = {1'd0, fsm};
endmodule | lgpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_sdd1/msu.v | 5,513 | module MODULE1(
input VAR16,
input enable,
input [13:0] VAR41,
input [7:0] VAR12,
input VAR14,
input [2:0] VAR46,
input [7:0] VAR9,
output [7:0] VAR11,
input VAR39,
input VAR5,
input VAR23,
output [7:0] VAR4,
output [7:0] VAR22,
output VAR45,
output [31:0] VAR36,
output [15:0] VAR27,
input [5:0] VAR10,
input [5:0] VAR38,
input VAR35,
input [13:0] VAR15,
input VAR31,
output VAR33,
output VAR30,
output VAR42,
output [13:0] VAR32,
output VAR8
);
reg [1:0] VAR43;
always @(posedge VAR16) VAR43 = {VAR43[0], VAR35};
wire VAR20 = (VAR43 == 2'b01);
reg [13:0] VAR40;
wire [13:0] VAR3 = VAR40;
VAR19 VAR40 = 13'b0;
wire [7:0] VAR17;
reg [7:0] VAR21;
reg [2:0] VAR1;
always @(posedge VAR16)
VAR1 <= {VAR1[1:0], VAR31};
wire VAR24 = (VAR1[2:1] == 2'b01);
reg [31:0] VAR29;
assign VAR36 = VAR29;
reg [15:0] VAR25;
assign VAR27 = VAR25;
reg [7:0] VAR37;
assign VAR22 = VAR37;
reg VAR18;
assign VAR45 = VAR18;
reg VAR13;
reg VAR28;
reg VAR34;
reg VAR7;
reg VAR6;
reg VAR44;
reg [2:0] VAR26;
reg [1:0] VAR2; | gpl-2.0 |
olajep/oh | src/adi/hdl/library/common/up_hdmi_tx.v | 12,180 | module MODULE1 #(
parameter VAR44 = 0) (
input VAR87,
output VAR62,
output VAR31,
output VAR82,
output [ 1:0] VAR81,
output [23:0] VAR26,
output [15:0] VAR28,
output [15:0] VAR3,
output [15:0] VAR22,
output [15:0] VAR8,
output [15:0] VAR43,
output [15:0] VAR80,
output [15:0] VAR61,
output [15:0] VAR27,
output [15:0] VAR57,
output [15:0] VAR88,
output [23:0] VAR64,
output [23:0] VAR5,
input VAR51,
input VAR83,
input [31:0] VAR37,
input VAR84,
output VAR46,
input VAR35,
input VAR85,
input VAR6,
input VAR1,
input VAR19,
input VAR65,
input [13:0] VAR15,
input [31:0] VAR7,
output reg VAR34,
input VAR30,
input [13:0] VAR9,
output reg [31:0] VAR32,
output reg VAR58);
localparam VAR33 = 32'h00040063;
reg VAR59 = 'd0;
reg [31:0] VAR69 = 'd0;
reg VAR13 = 'd0;
reg VAR86 = 'd0;
reg VAR29 = 'd0;
reg [ 1:0] VAR68 = 'd1;
reg [23:0] VAR54 = 'd0;
reg VAR55 = 'd0;
reg VAR74 = 'd0;
reg VAR39 = 'd0;
reg VAR45 = 'd0;
reg [15:0] VAR2 = 'd0;
reg [15:0] VAR4 = 'd0;
reg [15:0] VAR53 = 'd0;
reg [15:0] VAR79 = 'd0;
reg [15:0] VAR63 = 'd0;
reg [15:0] VAR23 = 'd0;
reg [15:0] VAR49 = 'd0;
reg [15:0] VAR12 = 'd0;
reg [15:0] VAR70 = 'd0;
reg [15:0] VAR78 = 'd0;
reg [23:0] VAR56 = 'd0;
reg [23:0] VAR16 = 'd0;
wire VAR21;
wire VAR20;
wire VAR67;
wire VAR71;
wire [31:0] VAR89;
wire VAR40;
wire VAR50;
wire VAR14;
assign VAR21 = (VAR15[13:12] == 2'd0) ? VAR65 : 1'b0;
assign VAR20 = (VAR9[13:12] == 2'd0) ? VAR30 : 1'b0;
always @(negedge VAR1 or posedge VAR19) begin
if (VAR1 == 0) begin
VAR59 <= 1'd1;
VAR34 <= 'd0;
VAR69 <= 'd0;
VAR13 <= 'd0;
VAR86 <= 'd0;
VAR29 <= 'd0;
VAR68 <= 'd1;
VAR54 <= 'd0;
VAR55 <= 'd0;
VAR74 <= 'd0;
VAR39 <= 'd0;
VAR45 <= 'd0;
VAR2 <= 'd0;
VAR4 <= 'd0;
VAR53 <= 'd0;
VAR79 <= 'd0;
VAR63 <= 'd0;
VAR23 <= 'd0;
VAR49 <= 'd0;
VAR12 <= 'd0;
VAR70 <= 'd0;
VAR78 <= 'd0;
VAR56 <= 24'hf0ebf0;
VAR16 <= 24'h101010;
end else begin
VAR59 <= ~VAR13;
VAR34 <= VAR21;
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h002)) begin
VAR69 <= VAR7;
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h010)) begin
VAR13 <= VAR7[0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h011)) begin
VAR29 <= VAR7[2];
VAR86 <= VAR7[0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h012)) begin
VAR68 <= VAR7[1:0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h013)) begin
VAR54 <= VAR7[23:0];
end
if (VAR40 == 1'b1) begin
VAR55 <= 1'b1;
end else if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h018)) begin
VAR55 <= VAR55 & ~VAR7[1];
end
if (VAR50 == 1'b1) begin
VAR74 <= 1'b1;
end else if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h018)) begin
VAR74 <= VAR74 & ~VAR7[0];
end
if (VAR71 == 1'b1) begin
VAR39 <= 1'b1;
end else if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h019)) begin
VAR39 <= VAR39 & ~VAR7[1];
end
if (VAR14 == 1'b1) begin
VAR45 <= 1'b1;
end else if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h019)) begin
VAR45 <= VAR45 & ~VAR7[0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h01a)) begin
VAR56 <= VAR7[23:0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h01b)) begin
VAR16 <= VAR7[23:0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h100)) begin
VAR2 <= VAR7[31:16];
VAR4 <= VAR7[15:0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h101)) begin
VAR53 <= VAR7[15:0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h102)) begin
VAR79 <= VAR7[31:16];
VAR63 <= VAR7[15:0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h110)) begin
VAR23 <= VAR7[31:16];
VAR49 <= VAR7[15:0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h111)) begin
VAR12 <= VAR7[15:0];
end
if ((VAR21 == 1'b1) && (VAR15[11:0] == 12'h112)) begin
VAR70 <= VAR7[31:16];
VAR78 <= VAR7[15:0];
end
end
end
always @(negedge VAR1 or posedge VAR19) begin
if (VAR1 == 0) begin
VAR58 <= 'd0;
VAR32 <= 'd0;
end else begin
VAR58 <= VAR20;
if (VAR20 == 1'b1) begin
case (VAR9[11:0])
12'h000: VAR32 <= VAR33;
12'h001: VAR32 <= VAR44;
12'h002: VAR32 <= VAR69;
12'h010: VAR32 <= {31'd0, VAR13};
12'h011: VAR32 <= {29'd0, VAR29, 1'b0, VAR86};
12'h012: VAR32 <= {30'd0, VAR68};
12'h013: VAR32 <= {8'd0, VAR54};
12'h015: VAR32 <= VAR89;
12'h016: VAR32 <= VAR37;
12'h017: VAR32 <= {31'd0, VAR67};
12'h018: VAR32 <= {30'd0, VAR55, VAR74};
12'h019: VAR32 <= {30'd0, VAR39, VAR45};
12'h01a: VAR32 <= {8'd0, VAR56};
12'h01b: VAR32 <= {8'd0, VAR16};
12'h100: VAR32 <= {VAR2, VAR4};
12'h101: VAR32 <= {16'd0, VAR53};
12'h102: VAR32 <= {VAR79, VAR63};
12'h110: VAR32 <= {VAR23, VAR49};
12'h111: VAR32 <= {16'd0, VAR12};
12'h112: VAR32 <= {VAR70, VAR78};
default: VAR32 <= 0;
endcase
end else begin
VAR32 <= 32'd0;
end
end
end
VAR73 VAR60 (.VAR36(VAR59), .clk(VAR87), .VAR11(), .rst(VAR62));
VAR73 VAR38 (.VAR36(VAR59), .clk(VAR84), .VAR11(), .rst(VAR46));
VAR41 #(.VAR18(236)) VAR42 (
.VAR1 (VAR1),
.VAR19 (VAR19),
.VAR25 ({ VAR29,
VAR86,
VAR68,
VAR54,
VAR2,
VAR4,
VAR53,
VAR79,
VAR63,
VAR23,
VAR49,
VAR12,
VAR70,
VAR78,
VAR56,
VAR16}),
.VAR17 (),
.VAR66 (VAR62),
.VAR47 (VAR87),
.VAR90 ({ VAR82,
VAR31,
VAR81,
VAR26,
VAR28,
VAR3,
VAR22,
VAR8,
VAR43,
VAR80,
VAR61,
VAR27,
VAR57,
VAR88,
VAR64,
VAR5}));
VAR24 #(.VAR18(2)) VAR10 (
.VAR1 (VAR1),
.VAR19 (VAR19),
.VAR75 ({VAR67,
VAR71}),
.VAR66 (VAR62),
.VAR47 (VAR87),
.VAR72 ({ VAR51,
VAR83}));
VAR76 VAR48 (
.VAR1 (VAR1),
.VAR19 (VAR19),
.VAR52 (VAR89),
.VAR66 (VAR62),
.VAR47 (VAR87));
VAR24 #(.VAR18(3)) VAR77 (
.VAR1 (VAR1),
.VAR19 (VAR19),
.VAR75 ({VAR40,
VAR50,
VAR14}),
.VAR66 (VAR46),
.VAR47 (VAR84),
.VAR72 ({ VAR35,
VAR85,
VAR6}));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22ai/sky130_fd_sc_hs__o22ai.pp.blackbox.v | 1,340 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR2 ,
VAR6,
VAR3
);
output VAR5 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR6;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b.functional.pp.v | 1,988 | module MODULE1 (
VAR16 ,
VAR12 ,
VAR13 ,
VAR11 ,
VAR3 ,
VAR6,
VAR15,
VAR17 ,
VAR9
);
output VAR16 ;
input VAR12 ;
input VAR13 ;
input VAR11 ;
input VAR3 ;
input VAR6;
input VAR15;
input VAR17 ;
input VAR9 ;
wire VAR2 ;
wire VAR4 ;
wire VAR5;
not VAR7 (VAR2 , VAR12 );
and VAR1 (VAR4 , VAR2, VAR13, VAR11, VAR3 );
VAR8 VAR14 (VAR5, VAR4, VAR6, VAR15);
buf VAR10 (VAR16 , VAR5 );
endmodule | apache-2.0 |
ThotIP/async_fifo | src/vlog/wptr_full.v | 2,702 | module MODULE1
parameter VAR1 = 4
)(
input wire VAR13,
input wire VAR11,
input wire VAR6,
input wire [VAR1 :0] VAR4,
output reg VAR2,
output reg VAR15,
output wire [VAR1-1:0] VAR8,
output reg [VAR1 :0] VAR7
);
reg [VAR1:0] VAR5;
wire [VAR1:0] VAR3, VAR12, VAR14;
wire VAR9, VAR10;
always @(posedge VAR13 or negedge VAR11) begin
if (!VAR11)
{VAR5, VAR7} <= 0;
end
else
{VAR5, VAR7} <= {VAR12, VAR3};
end
assign VAR8 = VAR5[VAR1-1:0];
assign VAR12 = VAR5 + (VAR6 & ~VAR2);
assign VAR3 = (VAR12 >> 1) ^ VAR12;
assign VAR14 = ((VAR12 + 1'b1) >> 1) ^ (VAR12 + 1'b1);
assign VAR10 = (VAR3 == {~VAR4[VAR1:VAR1-1],VAR4[VAR1-2:0]});
assign VAR9 = (VAR14 == {~VAR4[VAR1:VAR1-1],VAR4[VAR1-2:0]});
always @(posedge VAR13 or negedge VAR11) begin
if (!VAR11) begin
VAR15 <= 1'b0;
VAR2 <= 1'b0;
end
else begin
VAR15 <= VAR9;
VAR2 <= VAR10;
end
end
endmodule | apache-2.0 |
hls-fpga-machine-learning/hls-fpga-machine-learning | hls4ml/templates/vivado_accelerator/alveo/krnl_rtl_src/krnl_rtl_control_s_axi.v | 12,999 | module MODULE1
VAR2 = 6,
VAR66 = 32
)(
input wire VAR6,
input wire VAR5,
input wire VAR71,
input wire [VAR2-1:0] VAR68,
input wire VAR53,
output wire VAR21,
input wire [VAR66-1:0] VAR8,
input wire [VAR66/8-1:0] VAR72,
input wire VAR38,
output wire VAR10,
output wire [1:0] VAR20,
output wire VAR28,
input wire VAR51,
input wire [VAR2-1:0] VAR36,
input wire VAR69,
output wire VAR27,
output wire [VAR66-1:0] VAR57,
output wire [1:0] VAR44,
output wire VAR24,
input wire VAR49,
output wire interrupt,
output wire VAR52,
input wire VAR61,
input wire VAR25,
input wire VAR29,
output wire [63:0] VAR41,
output wire [63:0] VAR64,
output wire [31:0] VAR18,
output wire [31:0] VAR50
);
localparam
VAR19 = 6'h00,
VAR48 = 6'h04,
VAR59 = 6'h08,
VAR26 = 6'h0c,
VAR14 = 6'h10,
VAR31 = 6'h14,
VAR43 = 6'h18,
VAR23 = 6'h1c,
VAR60 = 6'h20,
VAR42 = 6'h24,
VAR55 = 6'h28,
VAR15 = 6'h2c,
VAR13 = 6'h30,
VAR70 = 6'h34,
VAR56 = 2'd0,
VAR37 = 2'd1,
VAR39 = 2'd2,
VAR34 = 2'd0,
VAR32 = 2'd1,
VAR22 = 6;
reg [1:0] VAR3 = VAR56;
reg [1:0] VAR33;
reg [VAR22-1:0] VAR1;
wire [31:0] VAR63;
wire VAR45;
wire VAR17;
reg [1:0] VAR46 = VAR34;
reg [1:0] VAR9;
reg [31:0] VAR7;
wire VAR65;
wire [VAR22-1:0] VAR16;
wire VAR73;
wire VAR62;
reg VAR4 = 1'b0;
reg VAR54 = 1'b0;
reg VAR11 = 1'b0;
reg VAR30 = 2'b0;
reg [1:0] VAR47 = 2'b0;
reg [1:0] VAR40 = 2'b0;
reg [63:0] VAR58 = 64'b0;
reg [63:0] VAR12 = 64'b0;
reg [63:0] VAR67 = 32'b0;
reg [31:0] VAR35 = 32'b0;
assign VAR21 = (~VAR5) & (VAR3 == VAR56);
assign VAR10 = (VAR3 == VAR37);
assign VAR20 = 2'b00; assign VAR28 = (VAR3 == VAR39);
assign VAR63 = { {8{VAR72[3]}}, {8{VAR72[2]}}, {8{VAR72[1]}}, {8{VAR72[0]}} };
assign VAR45 = VAR53 & VAR21;
assign VAR17 = VAR38 & VAR10;
always @(posedge VAR6) begin
if (VAR5)
VAR3 <= VAR56;
end
else if (VAR71)
VAR3 <= VAR33;
end
always @ begin
case (VAR46)
VAR34:
if (VAR69)
VAR9 = VAR32;
end
else
VAR9 = VAR34;
VAR32:
if (VAR49 & VAR24)
VAR9 = VAR34;
else
VAR9 = VAR32;
default:
VAR9 = VAR34;
endcase
end
always @(posedge VAR6) begin
if (VAR71) begin
if (VAR65) begin
VAR7 <= 1'b0;
case (VAR16)
VAR19: begin
VAR7[0] <= VAR54;
VAR7[1] <= VAR4;
VAR7[2] <= VAR73;
VAR7[3] <= VAR62;
VAR7[7] <= VAR11;
end
VAR48: begin
VAR7 <= VAR30;
end
VAR59: begin
VAR7 <= VAR47;
end
VAR26: begin
VAR7 <= VAR40;
end
VAR14: begin
VAR7 <= VAR58[31:0];
end
VAR31: begin
VAR7 <= VAR58[63:32];
end
VAR23: begin
VAR7 <= VAR12[31:0];
end
VAR60: begin
VAR7 <= VAR12[63:32];
end
VAR55: begin
VAR7 <= VAR67[31:0];
end
VAR13: begin
VAR7 <= VAR35[31:0];
end
endcase
end
end
end
assign interrupt = VAR30 & (|VAR40);
assign VAR52 = VAR54;
assign VAR73 = VAR29;
assign VAR62 = VAR25;
assign VAR41 = VAR58;
assign VAR64 = VAR12;
assign VAR18 = VAR67;
assign VAR50 = VAR35;
always @(posedge VAR6) begin
if (VAR5)
VAR54 <= 1'b0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR19 && VAR72[0] && VAR8[0])
VAR54 <= 1'b1;
end
else if (VAR62)
VAR54 <= VAR11; end
end
always @(posedge VAR6) begin
if (VAR5)
VAR4 <= 1'b0;
end
else if (VAR71) begin
if (VAR61)
VAR4 <= 1'b1;
end
else if (VAR65 && VAR16 == VAR19)
VAR4 <= 1'b0; end
end
always @(posedge VAR6) begin
if (VAR5)
VAR11 <= 1'b0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR19 && VAR72[0])
VAR11 <= VAR8[7];
end
end
always @(posedge VAR6) begin
if (VAR5)
VAR30 <= 1'b0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR48 && VAR72[0])
VAR30 <= VAR8[0];
end
end
always @(posedge VAR6) begin
if (VAR5)
VAR47 <= 1'b0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR59 && VAR72[0])
VAR47 <= VAR8[1:0];
end
end
always @(posedge VAR6) begin
if (VAR5)
VAR40[0] <= 1'b0;
end
else if (VAR71) begin
if (VAR47[0] & VAR61)
VAR40[0] <= 1'b1;
end
else if (VAR17 && VAR1 == VAR26 && VAR72[0])
VAR40[0] <= VAR40[0] ^ VAR8[0]; end
end
always @(posedge VAR6) begin
if (VAR5)
VAR40[1] <= 1'b0;
end
else if (VAR71) begin
if (VAR47[1] & VAR25)
VAR40[1] <= 1'b1;
end
else if (VAR17 && VAR1 == VAR26 && VAR72[0])
VAR40[1] <= VAR40[1] ^ VAR8[1]; end
end
always @(posedge VAR6) begin
if (VAR5)
VAR58[31:0] <= 0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR14)
VAR58[31:0] <= (VAR8[31:0] & VAR63) | (VAR58[31:0] & ~VAR63);
end
end
always @(posedge VAR6) begin
if (VAR5)
VAR58[63:32] <= 0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR31)
VAR58[63:32] <= (VAR8[31:0] & VAR63) | (VAR58[63:32] & ~VAR63);
end
end
always @(posedge VAR6) begin
if (VAR5)
VAR12[31:0] <= 0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR23)
VAR12[31:0] <= (VAR8[31:0] & VAR63) | (VAR12[31:0] & ~VAR63);
end
end
always @(posedge VAR6) begin
if (VAR5)
VAR12[63:32] <= 0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR60)
VAR12[63:32] <= (VAR8[31:0] & VAR63) | (VAR12[63:32] & ~VAR63);
end
end
always @(posedge VAR6) begin
if (VAR5)
VAR67[31:0] <= 0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR55)
VAR67[31:0] <= (VAR8[31:0] & VAR63) | (VAR67[31:0] & ~VAR63);
end
end
always @(posedge VAR6) begin
if (VAR5)
VAR35[31:0] <= 0;
end
else if (VAR71) begin
if (VAR17 && VAR1 == VAR13)
VAR35[31:0] <= (VAR8[31:0] & VAR63) | (VAR35[31:0] & ~VAR63);
end
end
endmodule | gpl-3.0 |
dingzh/piplined-MIPS-CPU | src/LAB5/eueau.v | 1,403 | module MODULE1;
reg VAR2;
reg VAR3;
reg [4:0] VAR1;
reg [4:0] VAR4;
reg [4:0] VAR6;
reg [31:0] VAR5;
reg reset;
wire [31:0] VAR10;
wire [31:0] VAR8;
VAR7 VAR9 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.reset(reset),
.VAR10(VAR10),
.VAR8(VAR8)
); | gpl-3.0 |
lbl-cal/StanfordNoC | router/src/vcr_sw_alloc_wf.v | 16,096 | module MODULE1
(clk, reset, VAR92, VAR29, VAR48, VAR40,
VAR56, VAR7, VAR19, VAR26, VAR16);
parameter VAR34 = 4;
parameter VAR18 = 5;
parameter VAR73 = VAR82;
parameter VAR96 = VAR39;
parameter VAR67 = VAR77;
parameter VAR24 = VAR88;
input clk;
input reset;
input [0:VAR18-1] VAR92;
input [0:VAR18*VAR34*VAR18-1] VAR29;
input [0:VAR18*VAR34-1] VAR48;
input [0:VAR18*VAR34-1] VAR40;
output [0:VAR18-1] VAR56;
wire [0:VAR18-1] VAR56;
output [0:VAR18*VAR34-1] VAR7;
wire [0:VAR18*VAR34-1] VAR7;
output [0:VAR18-1] VAR19;
wire [0:VAR18-1] VAR19;
output [0:VAR18*VAR18-1] VAR26;
wire [0:VAR18*VAR18-1] VAR26;
output [0:VAR18*VAR34-1] VAR16;
wire [0:VAR18*VAR34-1] VAR16;
wire [0:VAR18*VAR18-1] VAR59;
wire [0:VAR18*VAR18-1] VAR43;
wire [0:VAR18*VAR18-1] VAR2;
wire [0:VAR18*VAR18-1] VAR89;
wire [0:VAR18-1] VAR37;
wire [0:VAR18-1] VAR3;
generate
genvar VAR81;
for(VAR81 = 0; VAR81 < VAR18; VAR81 = VAR81 + 1)
begin:VAR17
wire VAR84;
assign VAR84 = VAR92[VAR81];
wire [0:VAR34*VAR18-1] VAR4;
assign VAR4
= VAR29[VAR81*VAR34*VAR18:(VAR81+1)*VAR34*VAR18-1];
wire [0:VAR34-1] VAR33;
assign VAR33
= VAR48[VAR81*VAR34:(VAR81+1)*VAR34-1];
wire [0:VAR18-1] VAR94;
VAR25
.VAR18(VAR34))
VAR53
(.select(VAR33),
.VAR66(VAR4),
.VAR38(VAR94));
assign VAR59[VAR81*VAR18:(VAR81+1)*VAR18-1]
= VAR94;
wire [0:VAR18-1] VAR27;
assign VAR27
= VAR43[VAR81*VAR18:(VAR81+1)*VAR18-1];
wire [0:VAR34-1] VAR99;
VAR87
.VAR85(VAR18),
.VAR47(1),
.VAR80(VAR78),
.VAR70(VAR55))
VAR91
(.VAR1(VAR4),
.VAR31(VAR27),
.VAR22(VAR99));
wire [0:VAR34-1] VAR69;
assign VAR69 = VAR33 & VAR99;
wire VAR21;
assign VAR21 = |VAR27;
wire VAR36;
assign VAR36 = VAR21;
wire [0:VAR34-1] VAR95;
if(VAR67 != VAR41)
begin
VAR61
.VAR86(1),
.VAR24(VAR24),
.VAR96(VAR96))
VAR103
(.clk(clk),
.reset(reset),
.VAR84(VAR84),
.VAR90(VAR36),
.VAR11(VAR69),
.VAR45(VAR95),
.VAR101());
end
wire [0:VAR18-1] VAR32;
wire VAR101;
wire [0:VAR34-1] VAR20;
if(VAR67 != VAR76)
begin
wire [0:VAR34-1] VAR63;
assign VAR63
= VAR40[VAR81*VAR34:(VAR81+1)*VAR34-1];
VAR25
.VAR18(VAR34))
VAR98
(.select(VAR63),
.VAR66(VAR4),
.VAR38(VAR32));
wire [0:VAR18-1] VAR13;
assign VAR13
= VAR89[VAR81*VAR18:(VAR81+1)*VAR18-1];
wire [0:VAR34-1] VAR50;
VAR87
.VAR85(VAR18),
.VAR47(1),
.VAR80(VAR78),
.VAR70(VAR55))
VAR72
(.VAR1(VAR4),
.VAR31(VAR13),
.VAR22(VAR50));
wire [0:VAR34-1] VAR100;
assign VAR100 = VAR63 & VAR50;
wire VAR93;
assign VAR93 = |VAR13;
wire VAR79;
assign VAR79 = VAR93;
wire [0:VAR34-1] VAR9;
if(VAR67 == VAR41)
begin
wire VAR52;
assign VAR52 = VAR36 | VAR79;
VAR61
.VAR86(2),
.VAR24(VAR24),
.VAR96(VAR96))
VAR71
(.clk(clk),
.reset(reset),
.VAR84(VAR84),
.VAR90(VAR52),
.VAR11({VAR69, VAR100}),
.VAR45({VAR95, VAR9}),
.VAR101(VAR20));
assign VAR101 = VAR21 | VAR93;
end
else
begin
VAR61
.VAR86(1),
.VAR24(VAR24),
.VAR96(VAR96))
VAR71
(.clk(clk),
.reset(reset),
.VAR84(VAR84),
.VAR90(VAR79),
.VAR11(VAR100),
.VAR45(VAR9),
.VAR101());
wire VAR51;
assign VAR51 = VAR37[VAR81];
wire VAR57;
assign VAR57
= |(VAR13 & VAR3) &
VAR51;
assign VAR101 = VAR21 | VAR57;
case(VAR67)
begin
wire VAR23;
assign VAR23 = |VAR33;
assign VAR20 = VAR23 ?
VAR95 :
VAR9;
end
begin
assign VAR20 = VAR21 ?
VAR95 :
VAR9;
end
endcase
end
end
else
begin
assign VAR32 = {VAR18{1'b0}};
assign VAR20 = VAR95;
assign VAR101 = VAR21;
end
assign VAR2[VAR81*VAR18:(VAR81+1)*VAR18-1]
= VAR32;
assign VAR7[VAR81*VAR34:(VAR81+1)*VAR34-1] = VAR20;
assign VAR56[VAR81] = VAR101;
end
endgenerate
generate
case(VAR67)
begin
assign VAR37 = {VAR18{1'b0}};
assign VAR3 = {VAR18{1'b0}};
end
begin
VAR58
.VAR49(VAR18),
.VAR14(VAR64))
VAR68
(.VAR66(VAR59),
.VAR38(VAR37));
VAR83
.VAR18(VAR18),
.VAR14(VAR64))
VAR46
(.VAR66(VAR59),
.VAR38(VAR3));
end
begin
VAR58
.VAR49(VAR18),
.VAR14(VAR64))
VAR68
(.VAR66(VAR43),
.VAR38(VAR37));
VAR83
.VAR18(VAR18),
.VAR14(VAR64))
VAR46
(.VAR66(VAR43),
.VAR38(VAR3));
end
endcase
endgenerate
wire VAR84;
assign VAR84 = |VAR92;
wire VAR8;
assign VAR8 = |VAR48;
wire [0:VAR18*VAR18-1] VAR54;
generate
if(VAR67 != VAR41)
begin
VAR65
.VAR86(1),
.VAR10(1),
.VAR73(VAR73),
.VAR24(VAR24))
VAR42
(.clk(clk),
.reset(reset),
.VAR84(VAR84),
.VAR90(VAR8),
.VAR11(VAR59),
.VAR45(VAR43),
.VAR101());
end
if(VAR67 != VAR76)
begin
wire VAR35;
assign VAR35 = |VAR40;
if(VAR67 == VAR41)
begin
wire VAR30;
assign VAR30 = VAR8 | VAR35;
VAR65
.VAR86(2),
.VAR10(1),
.VAR73(VAR73),
.VAR24(VAR24))
VAR44
(.clk(clk),
.reset(reset),
.VAR84(VAR84),
.VAR90(VAR30),
.VAR11({VAR59, VAR2}),
.VAR45({VAR43, VAR89}),
.VAR101(VAR54));
end
else
begin
VAR65
.VAR86(1),
.VAR10(1),
.VAR73(VAR73),
.VAR24(VAR24))
VAR60
(.clk(clk),
.reset(reset),
.VAR84(VAR84),
.VAR90(VAR35),
.VAR11(VAR2),
.VAR45(VAR89),
.VAR101());
wire [0:VAR18*VAR18-1] VAR15;
VAR87
.VAR85(1),
.VAR47(VAR18),
.VAR80(VAR78),
.VAR70(VAR55))
VAR5
(.VAR1(VAR37),
.VAR31(VAR3),
.VAR22(VAR15));
wire [0:VAR18*VAR18-1] VAR74;
assign VAR74
= VAR89 & VAR15;
assign VAR54
= VAR43 | VAR74;
end
end
else
begin
assign VAR89 = {VAR18*VAR18{1'b0}};
assign VAR54 = VAR43;
end
endgenerate
VAR97
.VAR62(VAR18))
VAR75
(.VAR66(VAR54),
.VAR38(VAR26));
genvar VAR14;
generate
for(VAR14 = 0; VAR14 < VAR18; VAR14 = VAR14 + 1)
begin:VAR12
wire [0:VAR18-1] VAR28;
assign VAR28 = VAR26[VAR14*VAR18:(VAR14+1)*VAR18-1];
wire VAR101;
assign VAR101 = |VAR28;
wire [0:VAR34-1] VAR20;
VAR6
.VAR49(VAR34))
VAR102
(.select(VAR28),
.VAR66(VAR7),
.VAR38(VAR20));
assign VAR19[VAR14] = VAR101;
assign VAR16[VAR14*VAR34:(VAR14+1)*VAR34-1] = VAR20;
end
endgenerate
endmodule | bsd-2-clause |
karatekid/ultrasonic-fountain | hardware/src/mojo_top.v | 2,508 | module MODULE1(
input clk,
input VAR10,
input VAR6,
output[7:0]VAR42,
output VAR29,
input VAR34,
input VAR1,
input VAR13,
output [3:0] VAR21,
input VAR50, output VAR30, input VAR24,
output VAR54, input VAR17, output VAR25, input VAR20, input VAR52, input VAR18,
input [VAR55-1:0] VAR47, output [VAR55-1:0] VAR53 );
wire rst = ~VAR10; assign VAR29 = 1'VAR36;
assign VAR30 = 1'VAR36;
assign VAR21 = 4'VAR56;
assign VAR54 = 1'VAR36;
wire VAR48;
VAR39 #(.VAR7(500)) VAR26(
.clk(clk),
.rst(rst),
.VAR35(VAR48));
wire VAR38;
assign VAR38 = 1'b1;
parameter VAR55 = 9;
wire [VAR55 * 16 -1:0] VAR46;
wire [VAR55 - 1: 0] VAR44;
genvar VAR49;
generate
for (VAR49 = 0; VAR49 < VAR55; VAR49=VAR49+1) begin: VAR27
VAR23 #(
.VAR43(1),
.VAR41(3800)
) VAR40(
.clk(clk),
.VAR37(VAR48),
.rst(rst),
.VAR16(VAR38),
.VAR47(VAR47[VAR49]),
.VAR33(VAR46[16*VAR49+16 - 1: 16*VAR49]),
.valid(VAR44[VAR49]),
.VAR53(VAR53[VAR49]));
end
endgenerate
localparam VAR31 = 64;
wire [8*VAR31 -1:0] VAR22;
wire [8*VAR31 -1:0] VAR32;
assign VAR32 = {300'b0,8'hde,8'had,8'hbe,8'hef, VAR46[15:0]};
wire VAR4, VAR45, VAR9;
VAR11 #(
.VAR31(VAR31))
VAR2(
.clk(clk),
.rst(rst),
.VAR15(VAR52),
.VAR51(VAR18),
.VAR14(VAR20),
.VAR19(VAR25),
.VAR8(VAR22),
.VAR3(VAR4),
.VAR12(VAR45),
.VAR5(VAR32),
.VAR28(VAR9)
);
assign VAR42 = VAR22[15:8];
endmodule | gpl-3.0 |
linuxbest/lzs | encode/rtl/verilog/encode_dp.v | 5,792 | module MODULE1(
VAR23, VAR28, VAR40, VAR17, VAR32,
VAR18, VAR30, VAR25, VAR4, VAR7, VAR21,
VAR11, VAR35,
clk, rst, VAR38, VAR9, VAR39, VAR37, VAR13, VAR1
);
parameter VAR8 = 20;
input clk, rst, VAR38, VAR9;
input [63:0] VAR39;
input VAR37, VAR13;
output VAR23;
output VAR28;
reg VAR28;
parameter [2:0]
VAR20 = 3'b000,
VAR16 = 3'b010,
VAR12 = 3'b100,
VAR26 = 3'b111;
reg [7:0] VAR33;
reg [VAR8-1:0] VAR34;
reg VAR15, VAR14;
reg [2:0]
state, VAR19;
output [7:0] VAR40;
output VAR17;
reg [7:0] VAR40, VAR27;
reg VAR17, VAR10;
reg VAR31, VAR22;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= VAR20;
end
else
state <= VAR19;
end
always @(posedge clk or posedge rst)
begin
if (rst)
VAR22 <= 1;
end
else
VAR22 <= VAR31;
end
assign VAR23 = VAR38 ? VAR22 : 'VAR24;
reg VAR6;
always @(posedge clk)
begin
VAR17 <= VAR10;
VAR40 <= VAR27;
VAR28 <= VAR6;
end
reg [2:0] VAR29;
always @(posedge clk or posedge rst)
begin
if (rst)
VAR29 <= 0;
end
else if (VAR10)
VAR29 <= VAR29 + 1;
end
always @(posedge clk or posedge rst)
begin
if (rst)
VAR14 <= 0;
end
else if (VAR14 == 0 && (&VAR33))
VAR14 <= 1;
end
always @(posedge clk or posedge rst)
begin
if (rst)
VAR33 <= 0;
end
else if (VAR14 == 0)
VAR33 <= VAR33 + 1'b1;
else
VAR33 <= VAR27;
end
always @(posedge clk or posedge rst)
begin
if (rst)
VAR15 <= 0;
end
else if (VAR14 == 0)
VAR15 <= 1;
else
VAR15 <= VAR10;
end
always @(VAR38 or VAR9 or VAR14 or VAR29 or VAR13
or VAR37 or state)
begin
VAR19 = VAR20;
VAR10 = 0;
VAR31 = 1;
VAR6 = 0;
case (state)
VAR20: begin
if (VAR14 && (!VAR37) && VAR38)
VAR19 = VAR16;
end
else
VAR19 = VAR20;
end
VAR16: begin
if (VAR13) begin
VAR10 = 1;
VAR19 = VAR26;
end else if (VAR9 && (&VAR29)) begin
VAR10 = 1;
VAR19 = VAR12;
end else if (VAR37 && (!VAR13)) begin
VAR19 = VAR16;
end else if (VAR29 == 3'b110) begin
VAR10 = 1;
VAR19 = VAR16;
VAR31 = 0;
end else begin
VAR10 = 1;
VAR19 = VAR16;
end
end
VAR12: begin
if (VAR9)
VAR19 = VAR12;
end
else if (!VAR37 || VAR13) begin
VAR19 = VAR16;
end else
VAR19 = VAR12;
end
VAR26: begin
VAR19 = VAR26;
VAR6 = 1;
end
endcase end
always @(VAR39 or VAR29)
begin
VAR27 = 0;
case (VAR29)
3'h0: VAR27 = VAR39[07:00];
3'h1: VAR27 = VAR39[15:08];
3'h2: VAR27 = VAR39[23:16];
3'h3: VAR27 = VAR39[31:24];
3'h4: VAR27 = VAR39[39:32];
3'h5: VAR27 = VAR39[47:40];
3'h6: VAR27 = VAR39[55:48];
3'h7: VAR27 = VAR39[63:56];
endcase end
output [7:0] VAR32, VAR18;
output [VAR8-1:0] VAR30;
output [7:0] VAR25;
output [7:0] VAR4;
reg [VAR8+15:0] VAR36 [255:0];
reg [7:0] VAR32, VAR25, VAR4, VAR18, VAR3;
reg [VAR8-1:0] VAR30;
output [VAR8-1:0] VAR7;
reg [VAR8-1:0] VAR7;
always @(posedge clk)
begin
if (VAR15)
VAR36[VAR33] <= {VAR27, VAR25, VAR7};
if (VAR17)
{VAR18, VAR32, VAR30} <= VAR36[VAR3];
end
always @(posedge clk)
begin
VAR3 <= VAR27;
end
always @(posedge clk)
begin
if (VAR17)
VAR25 <= VAR40;
end
output [7:0] VAR21;
reg [7:0] VAR21;
always @(posedge clk)
begin
if (VAR17)
VAR21 <= VAR18;
end
output VAR11;
reg VAR11;
always @(VAR25 or VAR17 or VAR21)
begin
if (VAR17)
VAR11 = VAR25 == VAR21;
end
else
VAR11 = 1'b0;
end
always @(posedge clk or posedge rst)
begin
if (rst)
VAR4 <= 0;
end
else if (VAR17)
VAR4 <= VAR25;
end
always @(posedge clk or posedge rst)
begin
if (rst)
VAR7 <= 0;
end
else if (VAR17)
VAR7 <= VAR7 + 1;
end
input [10:0] VAR1;
output [7:0] VAR35;
reg [7:0] VAR35;
reg [10:0] VAR2;
always @(VAR7)
begin
VAR2 = VAR7[10:0];
end
reg [7:0] VAR5[2047:0];
always @(posedge clk)
begin
if (VAR17)
VAR5[VAR2] <= VAR40;
VAR35 <= VAR5[VAR1];
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31oi/sky130_fd_sc_hs__a31oi.blackbox.v | 1,326 | module MODULE1 (
VAR1 ,
VAR7,
VAR4,
VAR3,
VAR2
);
output VAR1 ;
input VAR7;
input VAR4;
input VAR3;
input VAR2;
supply1 VAR5;
supply0 VAR6;
endmodule | apache-2.0 |
jameshegarty/rigel | platform/axi/conf.v | 6,138 | module MODULE1(
input wire VAR72,
input wire VAR29,
input wire [31:0] VAR26,
input wire [11:0] VAR79,
output wire VAR48,
input wire VAR77,
input wire [31:0] VAR74,
input wire [11:0] VAR44,
output wire VAR13,
input wire VAR56,
output wire [11:0] VAR3,
input wire VAR4,
output wire [1:0] VAR67,
output wire VAR70,
output wire [31:0] VAR17,
output wire [11:0] VAR57,
output wire VAR49,
input wire VAR85,
output wire [1:0] VAR12,
output wire VAR54,
input wire [31:0] VAR68,
output wire VAR42,
input wire [3:0] VAR58,
input wire VAR52,
output wire VAR35,
input wire VAR40,
output wire [31:0] VAR82,
output wire [31:0] VAR28,
output wire [31:0] VAR24,
output wire [31:0] VAR75,
output wire VAR21
);
wire [31:0] VAR43;
wire VAR50;
wire VAR81;
wire [31:0] VAR76;
wire VAR45;
wire VAR64;
wire VAR1;
reg [1:0] VAR34;
wire VAR69;
reg [31:0] VAR37;
wire VAR38;
reg [1:0] VAR84;
wire VAR62;
wire [31:0] VAR22;
wire VAR20;
wire [3:0] VAR59;
wire VAR9;
VAR83 VAR8(
.VAR72(VAR72),
.VAR29(VAR29),
.VAR26(VAR26),
.VAR79(VAR79),
.VAR48(VAR48),
.VAR77(VAR77),
.VAR74(VAR74),
.VAR44(VAR44),
.VAR13(VAR13),
.VAR56(VAR56),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR67(VAR67),
.VAR70(VAR70),
.VAR17(VAR17),
.VAR57(VAR57),
.VAR49(VAR49),
.VAR85(VAR85),
.VAR12(VAR12),
.VAR54(VAR54),
.VAR68(VAR68),
.VAR42(VAR42),
.VAR58(VAR58),
.VAR52(VAR52),
.VAR55(VAR43),
.VAR2(VAR50),
.VAR36(VAR81),
.VAR25(VAR76),
.VAR27(VAR45),
.VAR10(VAR64),
.VAR80(VAR1),
.VAR5(VAR34),
.VAR53(VAR69),
.VAR71(VAR37),
.VAR39(VAR38),
.VAR33(VAR84),
.VAR23(VAR62),
.VAR11(VAR22),
.VAR15(VAR20),
.VAR47(VAR59),
.VAR63(VAR9)
);
parameter VAR41 = 32'd0;
parameter VAR60 = 4;
parameter VAR78 = 32;
reg [VAR78-1:0] VAR46[VAR60-1:0];
parameter VAR14 = 0, VAR51 = 1;
parameter VAR86 = 2'b00, VAR65 = 2'b10;
reg [31:0] counter;
reg VAR73 = VAR14;
wire [1:0] VAR61;
assign VAR61 = VAR43[3:2];
wire VAR16;
assign VAR16 = {VAR43[31:4], 2'b00, VAR43[1:0]} == VAR41;
assign VAR50 = (VAR73 == VAR14);
assign VAR62 = (VAR73 == VAR51);
always @(posedge VAR72) begin
if(VAR29 == 0) begin
VAR73 <= VAR14;
end else case(VAR73)
VAR14: begin
if(VAR81) begin
VAR84 <= VAR16 ? VAR86 : VAR65;
VAR37 <= (VAR61 == 2'b0) ? counter : VAR46[VAR61];
VAR73 <= VAR51;
end
end
VAR51: begin
if(VAR38)
VAR73 <= VAR14;
end
endcase
end
reg VAR32 = VAR14;
reg [1:0] VAR66;
reg VAR6 = 0;
reg VAR7 = 0;
wire [1:0] VAR30;
assign VAR30 = VAR76[3:2];
wire VAR19;
assign VAR19 = {VAR76[31:4], 2'b00, VAR76[1:0]} == VAR41;
assign VAR45 = (VAR32 == VAR14);
assign VAR20 = (VAR32 == VAR51) && !VAR6;
assign VAR69 = (VAR32 == VAR51) && !VAR7;
always @(posedge VAR72) begin
if(VAR29 == 0) begin
VAR32 <= VAR14;
VAR6 <= 0;
VAR7 <= 0;
end else case(VAR32)
VAR14: begin
if(VAR64) begin
VAR34 <= VAR19 ? VAR86 : VAR65;
VAR66 <= VAR30;
VAR32 <= VAR51;
VAR6 <= 0;
VAR7 <= 0;
end
end
VAR51: begin
if (VAR20)
VAR46[VAR66] <= VAR22;
if((VAR6 || VAR9) && (VAR7 || VAR1)) begin
VAR6 <= 0;
VAR7 <= 0;
VAR32 <= VAR14;
end else if (VAR9)
VAR6 <= 1;
end
else if (VAR1)
VAR7 <= 1;
end
endcase
end
reg VAR31 = VAR14;
assign VAR35 = (VAR31 == VAR51);
always @(posedge VAR72) begin
if (VAR29 == 0)
VAR31 <= VAR14;
end
else case(VAR31)
VAR14:
if (VAR9 && VAR20 && VAR66 == 2'b00)
VAR31 <= VAR51;
VAR51:
if (VAR40)
VAR31 <= VAR14;
endcase
end
assign VAR82 = VAR46[0];
assign VAR28 = VAR46[1];
assign VAR24 = VAR46[2];
assign VAR75 = VAR46[3];
always @(posedge VAR72) begin
if (VAR29 == 0)
counter <= 0;
end
else if (VAR40 && VAR35)
counter <= 0;
end
else if (!VAR40)
counter <= counter + 1;
end
reg VAR18 = 0;
reg VAR87 = 0;
always @(posedge VAR72) begin
if (VAR29 == 0) begin
VAR18 <= 0;
VAR87 <= 0;
end else begin
if (VAR40) begin
VAR18 <= VAR35 ? 1 : 0;
end
VAR87 <= VAR18;
end
end
assign VAR21 = !VAR18;
endmodule | mit |
idgaf/Verilog_codes | Ex9/FrameTrans.v | 1,872 | module MODULE1(VAR7,VAR9,VAR13,VAR10,VAR11);
input VAR7;
input VAR9;
input [1:0] VAR13;
output VAR10;
output reg VAR11;
reg [31:0] VAR16;
reg VAR2;
reg [7:0] VAR6;
reg [1:0] VAR19;
reg VAR3;
reg VAR5;
wire VAR1;
parameter VAR4 = 5;
parameter VAR20 = 8'b10011011;
parameter VAR15 = 8'b10001001;
assign VAR10 = VAR2;
always@(negedge VAR7 or posedge VAR9)
begin
if(VAR7 == 1'b0)
begin
VAR16 <= 0;
VAR2 <= 0;
end
else
begin
VAR16 <= VAR16 + 1;
if(VAR16 == VAR4)
begin
VAR16 <= 0;
VAR2 <= ~VAR2;
end
end
end
always@(negedge VAR7 or posedge VAR2)
begin
if(VAR7 == 1'b0)
begin
VAR6 <= 0;
VAR11 <= 0;
VAR3 <= 0;
VAR5 <= 0;
VAR19 <= 0;
end
else if(VAR13 > 0)
begin
VAR3 <= 0;
VAR6 <= VAR6 + 1;
if(VAR6)
VAR19 <= VAR19 + 1;
if(VAR6 < 8)
begin
VAR5 <= 0;
if(VAR13 == 3 && VAR19 == 2)
VAR11 <= VAR15>>(7 - VAR6);
end
else
VAR11 <= VAR20>>(7 - VAR6);
if(VAR6 == 5)
VAR3<=1;
end
else if (VAR6 > 5)
VAR5 <= 1;
end
else
begin
VAR11 <= VAR1;
if(VAR6 == 255 && VAR13 == 1)
begin
VAR6 <= 255;
VAR5 <= 0;
VAR11 <= 0;
end
end
end
else
begin
VAR6 <= 0;
VAR11 <= 0;
VAR3 <= 0;
VAR5 <= 0;
VAR19 <= 0;
end
end
VAR12 VAR8(.clk(VAR2),
.rst(VAR7),
.VAR18(VAR3),
.VAR14(VAR5),
.din(0),
.dout(VAR1),
.VAR17());
endmodule | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/Barrel_shifter_v2.v | 1,733 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR2,
input wire [VAR26-1:0] VAR30,
input wire [VAR20-1:0] VAR10,
input wire VAR11,
input wire VAR13,
output wire [VAR20-1:0] VAR8
);
wire [VAR20-1:0] VAR28[VAR26+1:0];
genvar VAR1;
VAR6 #(.VAR20(VAR20)) VAR27(
.VAR29(VAR10),
.VAR4(VAR11),
.VAR22(VAR28 [0][VAR20-1:0])
);
generate for (VAR1=0; VAR1 < VAR26; VAR1=VAR1+1) begin : VAR15
genvar VAR19;
for (VAR19=0; VAR19<=VAR20-1 ; VAR19=VAR19+1) begin
localparam integer VAR9=(2**VAR33)+VAR19; case (VAR9>VAR20-1)
1'b1:begin
assign VAR28[VAR1+1][VAR19] = (VAR30[VAR1]) ? VAR13 : VAR28[VAR1][VAR19];
end
1'b0:begin
assign VAR28[VAR1+1][VAR19] = (VAR30[VAR1]) ? VAR28[VAR1][VAR9] : VAR28[VAR1][VAR19];
end
endcase
end
endgenerate
genvar VAR19; generate for (VAR19=0; VAR19 <= VAR20-1; VAR19=VAR19+1) begin : VAR7
case (VAR19)
VAR20-1-VAR19:begin : VAR21
assign VAR22[VAR19]=VAR28[VAR26+1][VAR20-1-VAR19];
end
default:begin : VAR18
VAR34 #(.VAR17(1)) VAR14(
.VAR3(VAR11),
.VAR31 (VAR28[VAR26+1][VAR19]),
.VAR24 (VAR28[VAR26+1][VAR20-1-VAR19]),
.VAR16 (VAR22[VAR19])
);
end
endcase
end
endgenerate
VAR32 #(.VAR17(VAR20)) VAR23(
.clk(clk),
.rst(rst),
.VAR12(VAR2),
.VAR5(VAR22),
.VAR25(VAR8)
);
endmodule | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_tlwidthwidget_qspi.v | 15,734 | module MODULE1(
input VAR108,
input reset,
output VAR94,
input VAR197,
input [2:0] VAR102,
input [2:0] VAR130,
input [2:0] VAR133,
input [1:0] VAR164,
input [29:0] VAR28,
input [3:0] VAR214,
input [31:0] VAR154,
input VAR10,
output VAR95,
output [2:0] VAR236,
output [1:0] VAR258,
output [2:0] VAR22,
output [1:0] VAR157,
output [29:0] VAR152,
output [3:0] VAR169,
output [31:0] VAR151,
output VAR58,
input VAR44,
input [2:0] VAR124,
input [2:0] VAR247,
input [2:0] VAR140,
input [1:0] VAR122,
input [29:0] VAR92,
input [31:0] VAR245,
input VAR30,
input VAR111,
output VAR171,
output [2:0] VAR103,
output [1:0] VAR99,
output [2:0] VAR34,
output [1:0] VAR246,
output VAR51,
output [1:0] VAR222,
output [31:0] VAR202,
output VAR253,
output VAR200,
input VAR27,
input VAR93,
input VAR114,
output VAR5,
output [2:0] VAR173,
output [2:0] VAR244,
output [2:0] VAR240,
output [1:0] VAR118,
output [29:0] VAR52,
output VAR15,
output [7:0] VAR33,
output VAR155,
input VAR82,
input [2:0] VAR6,
input [1:0] VAR195,
input [2:0] VAR225,
input [1:0] VAR83,
input [29:0] VAR226,
input VAR146,
input [7:0] VAR87,
input VAR46,
output VAR61,
output [2:0] VAR138,
output [2:0] VAR26,
output [2:0] VAR84,
output [1:0] VAR254,
output [29:0] VAR144,
output [7:0] VAR60,
output VAR232,
output VAR76,
input VAR131,
input [2:0] VAR149,
input [1:0] VAR89,
input [2:0] VAR203,
input [1:0] VAR184,
input VAR189,
input VAR134,
input [7:0] VAR75,
input VAR237,
input VAR21,
output VAR35,
output VAR167
);
wire VAR185;
wire VAR191;
wire VAR179;
wire VAR172;
wire VAR228;
wire VAR62;
wire VAR132;
wire [2:0] VAR48;
wire [2:0] VAR32;
wire [2:0] VAR207;
wire [1:0] VAR20;
wire [29:0] VAR187;
wire [3:0] VAR230;
wire [31:0] VAR128;
wire VAR239;
wire VAR50;
wire [2:0] VAR231;
wire [2:0] VAR135;
wire [2:0] VAR18;
wire [1:0] VAR3;
wire [29:0] VAR38;
wire [3:0] VAR178;
wire [31:0] VAR206;
wire [7:0] VAR40;
wire [7:0] VAR70;
wire [7:0] VAR216;
wire [7:0] VAR160;
wire [7:0] VAR147;
wire [7:0] VAR53;
wire [7:0] VAR213;
wire [7:0] VAR235;
wire VAR112;
wire VAR148;
wire VAR175;
wire VAR91;
wire VAR201;
wire VAR97;
wire VAR242;
wire VAR223;
reg [3:0] VAR141;
reg [31:0] VAR139;
wire [8:0] VAR212;
wire [1:0] VAR241;
wire [1:0] VAR180;
wire VAR220;
wire VAR249;
wire VAR119;
wire VAR105;
wire VAR78;
wire [1:0] VAR210;
wire [1:0] VAR13;
wire [3:0] VAR37;
wire [4:0] VAR116;
wire [4:0] VAR19;
wire [4:0] VAR96;
wire VAR113;
wire [4:0] VAR120;
wire [1:0] VAR7;
wire [1:0] VAR109;
wire [3:0] VAR9;
wire [4:0] VAR45;
wire [4:0] VAR106;
wire VAR196;
wire VAR221;
wire VAR29;
wire VAR250;
wire VAR211;
wire VAR47;
wire VAR117;
wire VAR39;
wire VAR234;
wire VAR170;
wire VAR123;
wire VAR190;
reg [23:0] VAR77;
reg [31:0] VAR24;
reg [2:0] VAR188;
reg [31:0] VAR104;
wire [31:0] VAR205;
wire [3:0] VAR79;
reg [1:0] VAR159;
reg [31:0] VAR125;
wire [8:0] VAR59;
wire [1:0] VAR107;
wire [1:0] VAR74;
wire VAR163;
wire VAR1;
wire [23:0] VAR86;
wire [2:0] VAR177;
wire [2:0] VAR182;
wire [1:0] VAR17;
wire [1:0] VAR126;
wire [23:0] VAR11;
wire [2:0] VAR238;
wire [1:0] VAR90;
wire [7:0] VAR14;
wire [15:0] VAR243;
wire [31:0] VAR194;
wire VAR73;
wire [3:0] VAR229;
wire [15:0] VAR150;
wire [31:0] VAR233;
wire [1:0] VAR137;
wire [3:0] VAR98;
wire [31:0] VAR65;
wire [31:0] VAR257;
wire [31:0] VAR161;
wire [31:0] VAR215;
wire [31:0] VAR204;
wire [31:0] VAR256;
wire [3:0] VAR192;
wire [3:0] VAR4;
wire [3:0] VAR64;
wire [3:0] VAR2;
wire [3:0] VAR224;
wire [3:0] VAR198;
wire VAR56;
wire VAR72;
wire VAR71;
wire [31:0] VAR136;
wire [31:0] VAR165;
wire [31:0] VAR85;
wire [31:0] VAR16;
wire [31:0] VAR199;
wire [31:0] VAR25;
wire [2:0] VAR23 = 3'b0;
reg [31:0] VAR166;
wire [1:0] VAR127 = 2'b0;
reg [31:0] VAR168;
wire [2:0] VAR12 = 3'b0;
reg [31:0] VAR142;
wire [1:0] VAR156 = 2'b0;
reg [31:0] VAR68;
wire [29:0] VAR67 = 30'b0;
reg [31:0] VAR227;
wire [3:0] VAR217 = 4'b0;
reg [31:0] VAR209;
wire [31:0] VAR101 = 32'b0;
reg [31:0] VAR36;
wire [2:0] VAR176 = 3'b0;
reg [31:0] VAR219;
wire [2:0] VAR69 = 3'b0;
reg [31:0] VAR54;
wire [2:0] VAR218 = 3'b0;
reg [31:0] VAR100;
wire [1:0] VAR158 = 2'b0;
reg [31:0] VAR153;
wire [29:0] VAR252 = 30'b0;
reg [31:0] VAR49;
wire [7:0] VAR174 = 8'b0;
reg [31:0] VAR88;
wire VAR145 = 1'b0;
reg [31:0] VAR186;
wire VAR248 = 1'b0;
reg [31:0] VAR110;
VAR255 VAR43 (
.VAR108(VAR191),
.reset(VAR179),
.VAR42(VAR172),
.VAR162(VAR228),
.VAR193(VAR62),
.VAR251(VAR132),
.VAR81(VAR48),
.VAR115(VAR32),
.VAR183(VAR207),
.VAR208(VAR20),
.VAR8(VAR187),
.VAR41(VAR230),
.VAR63(VAR128),
.VAR129(VAR239),
.VAR121(VAR50),
.VAR57(VAR231),
.VAR181(VAR135),
.VAR31(VAR18),
.VAR55(VAR3),
.VAR80(VAR38),
.VAR66(VAR178),
.VAR143(VAR206)
);
assign VAR94 = VAR62;
assign VAR95 = 1'h0;
assign VAR236 = VAR23;
assign VAR258 = VAR127;
assign VAR22 = VAR12;
assign VAR157 = VAR156;
assign VAR152 = VAR67;
assign VAR169 = VAR217;
assign VAR151 = VAR101;
assign VAR58 = 1'h1;
assign VAR171 = VAR71;
assign VAR103 = VAR149;
assign VAR99 = VAR89;
assign VAR34 = VAR203;
assign VAR246 = VAR184;
assign VAR51 = VAR189;
assign VAR222 = {{1'd0}, VAR134};
assign VAR202 = VAR136;
assign VAR253 = VAR237;
assign VAR200 = 1'h1;
assign VAR5 = VAR50;
assign VAR173 = VAR231;
assign VAR244 = VAR135;
assign VAR240 = VAR18;
assign VAR118 = VAR3;
assign VAR52 = VAR38;
assign VAR15 = VAR190;
assign VAR33 = 8'h0;
assign VAR155 = 1'h1;
assign VAR61 = 1'h0;
assign VAR138 = VAR176;
assign VAR26 = VAR69;
assign VAR84 = VAR218;
assign VAR254 = VAR158;
assign VAR144 = VAR252;
assign VAR60 = VAR174;
assign VAR232 = VAR145;
assign VAR76 = VAR72;
assign VAR35 = 1'h0;
assign VAR167 = VAR248;
assign VAR185 = 1'h0;
assign VAR191 = VAR108;
assign VAR179 = reset;
assign VAR172 = VAR185;
assign VAR132 = VAR197;
assign VAR48 = VAR102;
assign VAR32 = VAR130;
assign VAR207 = VAR133;
assign VAR20 = VAR164;
assign VAR187 = VAR28;
assign VAR230 = VAR214;
assign VAR128 = VAR154;
assign VAR239 = VAR114;
assign VAR40 = VAR206[7:0];
assign VAR70 = VAR206[15:8];
assign VAR216 = VAR206[23:16];
assign VAR160 = VAR206[31:24];
assign VAR147 = VAR40;
assign VAR53 = VAR70;
assign VAR213 = VAR216;
assign VAR235 = VAR160;
assign VAR112 = VAR178[0];
assign VAR148 = VAR178[1];
assign VAR175 = VAR178[2];
assign VAR91 = VAR178[3];
assign VAR201 = VAR112;
assign VAR97 = VAR148;
assign VAR242 = VAR175;
assign VAR223 = VAR91;
assign VAR212 = 9'h3 << VAR18;
assign VAR241 = VAR212[1:0];
assign VAR180 = ~ VAR241;
assign VAR220 = VAR180[0];
assign VAR249 = VAR220 == 1'h0;
assign VAR119 = VAR180[1];
assign VAR105 = VAR119 == 1'h0;
assign VAR78 = VAR141[3];
assign VAR210 = {VAR249,1'h1};
assign VAR13 = {VAR249,VAR105};
assign VAR37 = {VAR13,VAR210};
assign VAR116 = {{1'd0}, VAR141};
assign VAR19 = VAR116 << 1;
assign VAR96 = VAR78 ? {{1'd0}, VAR37} : VAR19;
assign VAR113 = VAR114 & VAR5;
assign VAR120 = VAR113 ? 5'hf : {{1'd0}, VAR141};
assign VAR7 = {VAR97,VAR201};
assign VAR109 = {VAR223,VAR242};
assign VAR9 = {VAR109,VAR7};
assign VAR45 = {{1'd0}, VAR9};
assign VAR106 = VAR45 & VAR96;
assign VAR196 = VAR106[0];
assign VAR221 = VAR106[1];
assign VAR29 = VAR106[2];
assign VAR250 = VAR106[3];
assign VAR211 = VAR196 ? VAR201 : 1'h0;
assign VAR47 = VAR221 ? VAR97 : 1'h0;
assign VAR117 = VAR29 ? VAR242 : 1'h0;
assign VAR39 = VAR250 ? VAR223 : 1'h0;
assign VAR234 = VAR211 | VAR47;
assign VAR170 = VAR234 | VAR117;
assign VAR123 = VAR170 | VAR39;
assign VAR190 = VAR123;
assign VAR205 = {VAR75,VAR77};
assign VAR79 = {1'h1,VAR188};
assign VAR59 = 9'h3 << VAR203;
assign VAR107 = VAR59[1:0];
assign VAR74 = ~ VAR107;
assign VAR163 = VAR159 == VAR74;
assign VAR1 = VAR76 & VAR131;
assign VAR86 = VAR205[31:8];
assign VAR177 = VAR79[3:1];
assign VAR182 = VAR159 + 2'h1;
assign VAR17 = VAR182[1:0];
assign VAR126 = VAR163 ? 2'h0 : VAR17;
assign VAR11 = VAR1 ? VAR86 : VAR77;
assign VAR238 = VAR1 ? VAR177 : VAR188;
assign VAR90 = VAR1 ? VAR126 : VAR159;
assign VAR14 = VAR205[31:24];
assign VAR243 = {VAR14,VAR14};
assign VAR194 = {VAR243,VAR243};
assign VAR73 = VAR79[3];
assign VAR229 = VAR73 ? 4'hf : 4'h0;
assign VAR150 = VAR205[31:16];
assign VAR233 = {VAR150,VAR150};
assign VAR137 = VAR79[3:2];
assign VAR98 = {VAR137,VAR137};
assign VAR65 = VAR194;
assign VAR257 = VAR233;
assign VAR161 = VAR205;
assign VAR215 = VAR205;
assign VAR204 = VAR205;
assign VAR256 = VAR205;
assign VAR192 = VAR229;
assign VAR4 = VAR98;
assign VAR64 = VAR79;
assign VAR2 = VAR79;
assign VAR224 = VAR79;
assign VAR198 = VAR79;
assign VAR56 = VAR163 == 1'h0;
assign VAR72 = VAR111 | VAR56;
assign VAR71 = VAR131 & VAR163;
assign VAR136 = VAR25;
assign VAR165 = 3'h1 == VAR203 ? VAR257 : VAR65;
assign VAR85 = 3'h2 == VAR203 ? VAR161 : VAR165;
assign VAR16 = 3'h3 == VAR203 ? VAR215 : VAR85;
assign VAR199 = 3'h4 == VAR203 ? VAR204 : VAR16;
assign VAR25 = 3'h5 == VAR203 ? VAR256 : VAR199;
always @(posedge VAR108 or posedge reset)
if (reset) begin
VAR141 <= 4'hf;
end else begin
VAR141 <= VAR120[3:0];
end
always @(posedge VAR108 or posedge reset)
if (reset) begin
VAR77 <= 24'b0;
VAR188 <= 3'b0;
end
else begin
if (VAR1) begin
VAR77 <= VAR86;
end
if (VAR1) begin
VAR188 <= VAR177;
end
end
always @(posedge VAR108 or posedge reset)
if (reset) begin
VAR159 <= 2'h0;
end else begin
if (VAR1) begin
if (VAR163) begin
VAR159 <= 2'h0;
end else begin
VAR159 <= VAR17;
end
end
end
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.behavioral.v | 1,098 | module MODULE1( VAR1, VAR5 );
input VAR1;
output VAR5;
VAR2 VAR4(.VAR1(VAR1),.VAR5(VAR5));
VAR2 VAR3(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_061.v | 1,540 | module MODULE2 (
VAR4,
VAR8
);
input [31:0] VAR4;
output [31:0]
VAR8;
wire [31:0]
VAR12,
VAR2,
VAR3,
VAR14,
VAR10,
VAR6,
VAR11,
VAR9,
VAR7;
assign VAR12 = VAR4;
assign VAR6 = VAR12 << 10;
assign VAR9 = VAR11 << 2;
assign VAR14 = VAR12 << 8;
assign VAR7 = VAR11 + VAR9;
assign VAR3 = VAR2 - VAR12;
assign VAR2 = VAR12 << 12;
assign VAR10 = VAR3 + VAR14;
assign VAR11 = VAR10 + VAR6;
assign VAR8 = VAR7;
endmodule
module MODULE1(
VAR4,
VAR8,
clk
);
input [31:0] VAR4;
output [31:0] VAR8;
reg [31:0] VAR8;
input clk;
reg [31:0] VAR5;
wire [30:0] VAR13;
always @(posedge clk) begin
VAR5 <= VAR4;
VAR8 <= VAR13;
end
MODULE2 MODULE1(
.VAR4(VAR5),
.VAR8(VAR13)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi.behavioral.pp.v | 2,044 | module MODULE1 (
VAR9 ,
VAR14 ,
VAR8 ,
VAR2 ,
VAR12 ,
VAR6,
VAR16,
VAR7 ,
VAR4
);
output VAR9 ;
input VAR14 ;
input VAR8 ;
input VAR2 ;
input VAR12 ;
input VAR6;
input VAR16;
input VAR7 ;
input VAR4 ;
wire VAR15 ;
wire VAR1 ;
wire VAR10;
and VAR17 (VAR15 , VAR14, VAR8 );
nor VAR5 (VAR1 , VAR15, VAR2, VAR12 );
VAR11 VAR13 (VAR10, VAR1, VAR6, VAR16);
buf VAR3 (VAR9 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr.behavioral.v | 1,259 | module MODULE1 ();
supply1 VAR4 ;
supply1 VAR1;
supply0 VAR2 ;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/sasc_brg.v | 1,150 | module MODULE1(
VAR7, VAR5,
clk, VAR6
);
output VAR7; output VAR5;
input clk;
input VAR6;
reg VAR7;
reg VAR5;
parameter VAR2 = 103;
reg [6:0] VAR1;
reg [1:0] VAR4;
always @ (posedge clk or negedge VAR6)
if (~VAR6)
VAR1 <= 0;
else if (VAR3)
VAR1 <= 0;
else
VAR1 <= VAR1 + 1'b1;
always @ (posedge clk or negedge VAR6)
if (~VAR6)
VAR4 <= 0;
else if (VAR3)
VAR4 <= VAR4 + 1'b1;
always @ (posedge clk or negedge VAR6)
if (~VAR6)
begin
VAR5 <= 1'b0;
VAR7 <= 1'b0;
end
else
begin
VAR5 <= VAR3;
VAR7 <= (&VAR4) & (VAR3);
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a.pp.blackbox.v | 1,368 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR5 ,
VAR4 ,
VAR9 ,
VAR3,
VAR6,
VAR8 ,
VAR2
);
output VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR3;
input VAR6;
input VAR8 ;
input VAR2 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/cic_decim.v | 2,530 | module MODULE1
(input VAR20,
input reset,
input enable,
input [7:0] VAR7,
input VAR17,
input VAR13,
input [VAR2-1:0] VAR18,
output reg [VAR2-1:0] VAR4);
localparam VAR3 = VAR5 * VAR9;
wire [VAR2+VAR3-1:0] VAR19;
reg [VAR2+VAR3-1:0] VAR1 [0:VAR5-1];
reg [VAR2+VAR3-1:0] VAR15 [0:VAR5-1];
reg [VAR2+VAR3-1:0] VAR8 [0:VAR5-1];
reg [VAR2+VAR3-1:0] VAR11;
integer VAR14;
VAR10 #(VAR2,VAR2+VAR3)
VAR16 (.in(VAR18),.out(VAR19));
always @(posedge VAR20)
if(~enable)
for(VAR14=0;VAR14<VAR5;VAR14=VAR14+1)
VAR1[VAR14] <= 0;
else if (VAR17)
begin
VAR1[0] <= VAR1[0] + VAR19;
for(VAR14=1;VAR14<VAR5;VAR14=VAR14+1)
VAR1[VAR14] <= VAR1[VAR14] + VAR1[VAR14-1];
end
always @(posedge VAR20)
if(~enable)
begin
VAR11 <= 0;
for(VAR14=0;VAR14<VAR5;VAR14=VAR14+1)
begin
VAR8[VAR14] <= 0;
VAR15[VAR14] <= 0;
end
end
else if (VAR13)
begin
VAR11 <= VAR1[VAR5-1];
VAR15[0] <= VAR11;
VAR8[0] <= VAR11 - VAR15[0];
for(VAR14=1;VAR14<VAR5;VAR14=VAR14+1)
begin
VAR15[VAR14] <= VAR8[VAR14-1];
VAR8[VAR14] <= VAR8[VAR14-1] - VAR15[VAR14];
end
end
wire [VAR2-1:0] VAR6;
VAR12 #(VAR2)
VAR12(VAR7,VAR8[VAR5-1],VAR6);
always @(posedge VAR20)
VAR4 <= VAR6;
endmodule | gpl-2.0 |
esonghori/TinyGarbled | circuit_synthesis/stable_match/stable_match.v | 14,705 | module MODULE1
parameter VAR65 =8,
parameter VAR33 =8,
parameter VAR43 =8,
parameter VAR57 =8
)
(
clk,
rst,
VAR44,
VAR82,
VAR8
);
function integer VAR35;
input [31:0] VAR64;
reg [31:0] VAR3;
begin
VAR3 = VAR64 - 1;
for (VAR35=0; VAR3>0; VAR35=VAR35+1)
VAR3 = VAR3>>1;
end
endfunction
localparam VAR7 = VAR35(VAR43);
localparam VAR61 = VAR35(VAR57);
localparam VAR47 = VAR35(VAR33);
localparam VAR46 = VAR35(VAR65);
localparam VAR53=0;
localparam VAR16=2;
localparam VAR69 = 3;
localparam VAR73 = 4;
input clk,rst;
input [VAR43*VAR46+VAR33*VAR61-1:0] VAR44;
input [VAR43*VAR46+VAR33*VAR61-1:0] VAR82;
output [VAR57*VAR7-1:0] VAR8;
wire [VAR43*VAR46-1:0] VAR6;
wire [VAR33*VAR61-1:0] VAR51;
wire [VAR57*VAR7-1:0] VAR52;
wire [VAR47-1:0] VAR18;
wire [VAR61-1:0] VAR59;
wire [VAR7-1:0] VAR49;
wire [VAR47:0] VAR48;
wire VAR84;
wire [VAR47:0] VAR58;
wire [VAR61-1:0] VAR32;
wire VAR75;
wire VAR17;
wire VAR54;
wire [VAR61-1:0] VAR27;
wire [VAR7:0] VAR31;
wire VAR14;
wire [VAR7:0] VAR37;
wire [VAR7-1:0] VAR4;
wire [VAR46-1:0] VAR50;
wire [VAR7-1:0] VAR45;
wire [VAR46-1:0] VAR20;
wire [VAR7-1:0] VAR24;
wire VAR23;
wire VAR10;
wire [VAR7-1:0] VAR39;
wire VAR79;
wire VAR13;
wire [VAR7-1:0] VAR68;
wire VAR55;
wire [VAR7-1:0] VAR15;
wire [VAR61-1:0] VAR70;
wire [2:0] state;
wire [VAR7-1:0] VAR74;
wire [VAR61-1:0] VAR22;
wire [VAR43*VAR46+VAR33*VAR61-1:0] VAR11;
assign VAR11 = VAR44^VAR82;
assign VAR6 = VAR11[VAR43*VAR46-1:0];
assign VAR51 = VAR11[VAR43*VAR46+VAR33*VAR61-1:VAR43*VAR46];
assign VAR8 = VAR52;
MODULE4
.VAR65(VAR65),
.VAR33(VAR33),
.VAR43(VAR43),
.VAR57(VAR57)
)
MODULE4
(
.VAR51(VAR51),
.VAR78(VAR18),
.VAR26(VAR59)
);
MODULE5
.VAR65(VAR65),
.VAR33(VAR33),
.VAR43(VAR43),
.VAR57(VAR57)
)
MODULE5
(
.VAR6(VAR6),
.VAR66(VAR4),
.VAR12(VAR50),
.VAR29(VAR45),
.VAR1(VAR20)
);
MODULE8
.VAR65(VAR65),
.VAR33(VAR33),
.VAR43(VAR43),
.VAR57(VAR57)
)
MODULE8
(
.clk(clk),
.rst(rst),
.addr(VAR49),
.VAR62(VAR48),
.VAR71(VAR84),
.VAR26(VAR58)
);
MODULE2
.VAR65(VAR65),
.VAR33(VAR33),
.VAR43(VAR43),
.VAR57(VAR57)
)
MODULE2
(
.clk(clk),
.rst(rst),
.VAR60(VAR24),
.VAR38(VAR23),
.VAR72(VAR10),
.VAR77(VAR39),
.VAR42(VAR79),
.VAR76(VAR13),
.VAR78(VAR68),
.VAR26(VAR55)
);
MODULE3
.VAR65(VAR65),
.VAR33(VAR33),
.VAR43(VAR43),
.VAR57(VAR57)
)
MODULE3
(
.clk(clk),
.rst(rst),
.addr(VAR32),
.VAR62(VAR75),
.VAR71(VAR17),
.VAR26(VAR54)
);
MODULE6
.VAR65(VAR65),
.VAR33(VAR33),
.VAR43(VAR43),
.VAR57(VAR57)
)
MODULE6
(
.clk(clk),
.rst(rst),
.addr(VAR27),
.VAR62(VAR31),
.VAR71(VAR14),
.VAR26(VAR37),
.VAR52(VAR52)
);
MODULE7
.VAR65(VAR65),
.VAR33(VAR33),
.VAR43(VAR43),
.VAR57(VAR57)
)
MODULE7
(
.clk(clk),
.rst(rst),
.state(state),
.VAR15(VAR15),
.VAR70(VAR70),
.VAR74(VAR74),
.VAR22(VAR22),
.VAR18(VAR18),
.VAR59(VAR59),
.VAR49(VAR49),
.VAR48(VAR48),
.VAR84(VAR84),
.VAR58(VAR58),
.VAR32(VAR32),
.VAR75(VAR75),
.VAR17(VAR17),
.VAR54(VAR54),
.VAR27(VAR27),
.VAR31(VAR31),
.VAR14(VAR14),
.VAR37(VAR37),
.VAR4(VAR4),
.VAR50(VAR50),
.VAR45(VAR45),
.VAR20(VAR20),
.VAR24(VAR24),
.VAR23(VAR23),
.VAR10(VAR10),
.VAR39(VAR39),
.VAR79(VAR79),
.VAR13(VAR13),
.VAR68(VAR68),
.VAR55(VAR55)
);
endmodule
module MODULE7
parameter VAR65 =8,
parameter VAR33 =8,
parameter VAR43 =8,
parameter VAR57 =8
)
(
clk,
rst,
state,
VAR15,
VAR70,
VAR74,
VAR22,
VAR18,
VAR59,
VAR49,
VAR48,
VAR84,
VAR58,
VAR32,
VAR75,
VAR17,
VAR54,
VAR27,
VAR31,
VAR14,
VAR37,
VAR4,
VAR50,
VAR45,
VAR20,
VAR24,
VAR23,
VAR10,
VAR39,
VAR79,
VAR13,
VAR68,
VAR55
);
function integer VAR35;
input [31:0] VAR64;
reg [31:0] VAR3;
begin
VAR3 = VAR64 - 1;
for (VAR35=0; VAR3>0; VAR35=VAR35+1)
VAR3 = VAR3>>1;
end
endfunction
localparam VAR7 = VAR35(VAR43);
localparam VAR61 = VAR35(VAR57);
localparam VAR47 = VAR35(VAR33);
localparam VAR46 = VAR35(VAR65);
localparam VAR53=0;
localparam VAR16=2;
localparam VAR69 = 3;
localparam VAR73 = 4;
input clk,rst;
output reg [VAR7-1:0] VAR15;
output reg [VAR61-1:0] VAR70;
output reg [2:0] state;
output reg [VAR7-1:0] VAR74;
output reg [VAR61-1:0] VAR22;
output [VAR47-1:0] VAR18;
input [VAR61-1:0] VAR59;
output [VAR7-1:0] VAR49;
output [VAR47:0] VAR48;
output VAR84;
input [VAR47:0] VAR58;
output [VAR61-1:0] VAR32;
output VAR75;
output VAR17;
input VAR54;
output [VAR61-1:0] VAR27;
output [VAR7:0] VAR31;
output VAR14;
input [VAR7:0] VAR37;
output [VAR7-1:0] VAR4;
input [VAR46-1:0] VAR50;
output [VAR7-1:0] VAR45;
input [VAR46-1:0] VAR20;
output [VAR7-1:0] VAR24;
output VAR23;
output VAR10;
output [VAR7-1:0] VAR39;
output VAR79;
output VAR13;
output [VAR7-1:0] VAR68;
input VAR55;
reg [2:0] VAR56;
wire [VAR47:0] VAR19;
wire [VAR7-1:0] VAR9;
wire VAR2;
wire VAR21;
wire VAR5;
assign VAR9 = VAR37;
assign VAR2 = (VAR50 < VAR20);
assign VAR5 = |VAR19 & ~VAR55;
assign VAR18 = VAR33-VAR19;
assign VAR49 = VAR15;
assign VAR48 = VAR19-1;
assign VAR84 = state==VAR53 && VAR5;
assign VAR19 = VAR58;
assign VAR24 = VAR74;
assign VAR23 = 1'b1;
assign VAR10 = (state==VAR73) &&
(VAR54==0 || (VAR54!=0 && VAR2));
assign VAR39 = VAR9;
assign VAR79 = 1'b0;
assign VAR13 = (state==VAR73) &&
(VAR54!=0 && VAR2);
assign VAR68 = VAR15;
assign VAR32 = VAR22;
assign VAR75 = 1'b1;
assign VAR17 = state==VAR73 && VAR54;
assign VAR27 = VAR22;
assign VAR31 = VAR74;
assign VAR14 = (state==VAR73) &&
(VAR54==0 || (VAR54!=0 && VAR2));
assign VAR4 = VAR74;
assign VAR45 = VAR9;
always@(*) begin
VAR56 = VAR53;
case (state)
VAR53: begin
if(VAR5)
VAR56 = VAR69;
end
else
VAR56 = VAR53;
end
VAR69: begin
if (VAR70 + 1 == VAR22) begin
VAR56=VAR73;
end else begin
VAR56=VAR69;
end
end
VAR73: begin
VAR56=VAR53;
end
default: begin
VAR56=VAR53;
end
endcase
end
integer VAR81;
always@(posedge clk or posedge rst) begin
if(rst) begin
VAR74<=0;
VAR22<=0;
VAR15<=0;
VAR70<=0;
state<=VAR53;
end else begin
state <= VAR56;
VAR15 <= (VAR15+1);
VAR70 <= (VAR70+1);
if (state==VAR53) begin
VAR74 <= VAR15;
VAR22 <= VAR59;
end
end
end
endmodule
module MODULE4
parameter VAR65 =8,
parameter VAR33 =8,
parameter VAR43 =8,
parameter VAR57 =8
)
(
VAR51,
VAR78,
VAR26
);
function integer VAR35;
input [31:0] VAR64;
reg [31:0] VAR3;
begin
VAR3 = VAR64 - 1;
for (VAR35=0; VAR3>0; VAR35=VAR35+1)
VAR3 = VAR3>>1;
end
endfunction
localparam VAR7 = VAR35(VAR43);
localparam VAR61 = VAR35(VAR57);
localparam VAR47 = VAR35(VAR33);
localparam VAR46 = VAR35(VAR65);
input [VAR33*VAR61-1:0] VAR51;
input [VAR47-1:0] VAR78;
output [VAR61-1:0] VAR26;
wire [VAR61-1:0] VAR25 [VAR33-1:0];
genvar VAR28;
generate
for (VAR28=0;VAR28<VAR33;VAR28=VAR28+1) begin : VAR34
assign VAR25 [VAR28] = VAR51 [VAR61*(VAR28+1)-1:VAR61*VAR28];
end
endgenerate
assign VAR26 = VAR25[VAR78];
endmodule
module MODULE5
parameter VAR65 =8,
parameter VAR33 =8,
parameter VAR43 =8,
parameter VAR57 =8
)
(
VAR6,
VAR66,
VAR12,
VAR29,
VAR1
);
function integer VAR35;
input [31:0] VAR64;
reg [31:0] VAR3;
begin
VAR3 = VAR64 - 1;
for (VAR35=0; VAR3>0; VAR35=VAR35+1)
VAR3 = VAR3>>1;
end
endfunction
localparam VAR7 = VAR35(VAR43);
localparam VAR61 = VAR35(VAR57);
localparam VAR47 = VAR35(VAR33);
localparam VAR46 = VAR35(VAR65);
input [VAR43*VAR46-1:0] VAR6;
input [VAR7-1:0] VAR66;
output [VAR46-1:0] VAR12;
input [VAR7-1:0] VAR29;
output [VAR46-1:0] VAR1;
wire [VAR46-1:0] VAR67 [VAR43-1:0];
genvar VAR28;
generate
for (VAR28=0;VAR28<VAR65;VAR28=VAR28+1) begin : VAR85
assign VAR67 [VAR28] = VAR6 [VAR7*(VAR28+1)-1:VAR7*VAR28];
end
endgenerate
assign VAR12 = VAR67[VAR66];
assign VAR1 = VAR67[VAR29];
endmodule
module MODULE8
parameter VAR65 =8,
parameter VAR33 =8,
parameter VAR43 =8,
parameter VAR57 =8
)
(
clk,
rst,
addr,
VAR62,
VAR71,
VAR26
);
function integer VAR35;
input [31:0] VAR64;
reg [31:0] VAR3;
begin
VAR3 = VAR64 - 1;
for (VAR35=0; VAR3>0; VAR35=VAR35+1)
VAR3 = VAR3>>1;
end
endfunction
localparam VAR7 = VAR35(VAR43);
localparam VAR61 = VAR35(VAR57);
localparam VAR47 = VAR35(VAR33);
localparam VAR46 = VAR35(VAR65);
input clk,rst;
input [VAR7-1:0] addr;
input [VAR47:0] VAR62;
input VAR71;
output [VAR47:0] VAR26;
reg [VAR47:0] VAR63 [VAR43-1:0];
integer VAR81;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (VAR81=0;VAR81<VAR43;VAR81=VAR81+1) begin :VAR83
VAR63[VAR81] <= VAR33;
end
end
else if (VAR71) begin
VAR63[addr] <= VAR62;
end
end
assign VAR26 = VAR63[addr];
endmodule
module MODULE2
parameter VAR65 =8,
parameter VAR33 =8,
parameter VAR43 =8,
parameter VAR57 =8
)
(
clk,
rst,
VAR60,
VAR38,
VAR72,
VAR77,
VAR42,
VAR76,
VAR78,
VAR26
);
function integer VAR35;
input [31:0] VAR64;
reg [31:0] VAR3;
begin
VAR3 = VAR64 - 1;
for (VAR35=0; VAR3>0; VAR35=VAR35+1)
VAR3 = VAR3>>1;
end
endfunction
localparam VAR7 = VAR35(VAR43);
localparam VAR61 = VAR35(VAR57);
localparam VAR47 = VAR35(VAR33);
localparam VAR46 = VAR35(VAR65);
input clk,rst;
input [VAR7-1:0] VAR60;
input VAR38;
input VAR72;
input [VAR7-1:0] VAR77;
input VAR42;
input VAR76;
input [VAR7-1:0] VAR78;
output VAR26;
reg [VAR43-1:0] VAR41;
integer VAR81;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (VAR81=0;VAR81<VAR43;VAR81=VAR81+1) begin :VAR83
VAR41[VAR81] <= 1'b0;
end
end else if (VAR72) begin
VAR41[VAR60] <= VAR38;
end else if (VAR76) begin
VAR41[VAR77] <= VAR42;
end
end
assign VAR26 = VAR41[VAR78];
endmodule
module MODULE3
parameter VAR65 =8,
parameter VAR33 =8,
parameter VAR43 =8,
parameter VAR57 =8
)
(
clk,
rst,
addr,
VAR62,
VAR71,
VAR26
);
function integer VAR35;
input [31:0] VAR64;
reg [31:0] VAR3;
begin
VAR3 = VAR64 - 1;
for (VAR35=0; VAR3>0; VAR35=VAR35+1)
VAR3 = VAR3>>1;
end
endfunction
localparam VAR7 = VAR35(VAR43);
localparam VAR61 = VAR35(VAR57);
localparam VAR47 = VAR35(VAR33);
localparam VAR46 = VAR35(VAR65);
input clk,rst;
input [VAR61-1:0] addr;
input VAR62;
input VAR71;
output VAR26;
reg VAR30[VAR57-1:0];
integer VAR81;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (VAR81=0;VAR81<VAR57;VAR81=VAR81+1) begin :VAR83
VAR30[VAR81] <= 1'b0;
end
end
else if (VAR71) begin
VAR30[addr] <= VAR62;
end
end
assign VAR26 = VAR30[addr];
endmodule
module MODULE6
parameter VAR65 =8,
parameter VAR33 =8,
parameter VAR43 =8,
parameter VAR57 =8
)
(
clk,
rst,
addr,
VAR62,
VAR71,
VAR26,
VAR52
);
function integer VAR35;
input [31:0] VAR64;
reg [31:0] VAR3;
begin
VAR3 = VAR64 - 1;
for (VAR35=0; VAR3>0; VAR35=VAR35+1)
VAR3 = VAR3>>1;
end
endfunction
localparam VAR7 = VAR35(VAR43);
localparam VAR61 = VAR35(VAR57);
localparam VAR47 = VAR35(VAR33);
localparam VAR46 = VAR35(VAR65);
input clk,rst;
input [VAR61-1:0] addr;
input [VAR7:0] VAR62;
input VAR71;
output [VAR7:0] VAR26;
output [VAR57*VAR7-1:0] VAR52;
reg [VAR7-1:0] VAR36 [VAR57-1:0];
integer VAR81;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (VAR81=0;VAR81<VAR43;VAR81=VAR81+1) begin :VAR83
VAR36[VAR81] <= VAR33;
end
end
else if (VAR71) begin
VAR36[addr] <= VAR62;
end
end
assign VAR26 = VAR36[addr];
genvar VAR80;
generate
for (VAR80=0;VAR80<VAR57;VAR80=VAR80+1)begin : VAR40
assign VAR52 [VAR7*(VAR80+1)-1:VAR7*VAR80] = VAR36 [VAR80] ;
end
endgenerate
endmodule | gpl-3.0 |
secworks/mkmif | src/rtl/mkmif_core.v | 9,150 | module MODULE1(
input wire clk,
input wire VAR6,
output wire VAR45,
output wire VAR47,
input wire VAR7,
output wire VAR11,
input wire VAR4,
input wire VAR34,
input wire VAR8,
output wire ready,
output wire valid,
input wire [15 : 0] VAR35,
input wire [15 : 0] addr,
input wire [31 : 0] VAR33,
output wire [31 : 0] VAR40
);
localparam VAR44 = 8'h03;
localparam VAR28 = 8'h02;
localparam VAR42 = 8'h05;
localparam VAR26 = 8'h01;
localparam VAR5 = 8'b01000001;
localparam VAR19 = 0;
localparam VAR38 = 1;
localparam VAR21 = 2;
localparam VAR9 = 3;
localparam VAR43 = 4;
localparam VAR10 = 5;
localparam VAR15 = 6;
reg VAR18;
reg VAR22;
reg VAR49;
reg VAR25;
reg VAR46;
reg VAR20;
reg [31 : 0] VAR27;
reg VAR23;
reg [3 : 0] VAR37;
reg [3 : 0] VAR31;
reg VAR17;
wire [31 : 0] VAR48;
reg [55 : 0] VAR14;
reg VAR12;
reg VAR41;
wire VAR3;
reg [2 : 0] VAR2;
assign ready = VAR18;
assign valid = VAR25;
assign VAR40 = VAR27;
VAR30 VAR1(
.clk(clk),
.VAR6(VAR6),
.VAR45(VAR45),
.VAR47(VAR47),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR13(VAR12),
.VAR29(VAR41),
.VAR24(VAR2),
.VAR16(VAR35),
.ready(VAR3),
.VAR39(VAR14),
.VAR32(VAR48)
);
always @ (posedge clk or negedge VAR6)
begin
if (!VAR6)
begin
VAR18 <= 0;
VAR25 <= 0;
VAR27 <= 32'h0;
VAR37 <= VAR19;
end
else
begin
if (VAR49)
VAR18 <= VAR22;
if (VAR20)
VAR25 <= VAR46;
if (VAR23)
VAR27 <= VAR48;
if (VAR17)
VAR37 <= VAR31;
end
end
always @*
begin : VAR36
VAR12 = 0;
VAR41 = 0;
VAR2 = 3'h0;
VAR14 = 56'h0;
VAR23 = 0;
VAR22 = 0;
VAR49 = 0;
VAR46 = 0;
VAR20 = 0;
VAR31 = VAR19;
VAR17 = 0;
case (VAR37)
VAR19:
begin
VAR31 = VAR43;
VAR17 = 1;
end
VAR38:
begin
VAR22 = 1;
VAR49 = 1;
if (VAR4)
begin
VAR22 = 0;
VAR49 = 1;
VAR46 = 0;
VAR20 = 1;
VAR31 = VAR21;
VAR17 = 1;
end
if (VAR34)
begin
VAR22 = 0;
VAR49 = 1;
VAR31 = VAR9;
VAR17 = 1;
end
if (VAR8)
begin
VAR22 = 0;
VAR49 = 1;
VAR31 = VAR43;
VAR17 = 1;
end
end
VAR21:
begin
VAR12 = 1;
VAR14 = {VAR44, addr, 32'h0};
VAR2 = 3'h7;
VAR31 = VAR10;
VAR17 = 1;
end
VAR9:
begin
VAR12 = 1;
VAR14 = {VAR28, addr, VAR33};
VAR2 = 3'h7;
VAR31 = VAR10;
VAR17 = 1;
end
VAR43:
begin
if (VAR3)
begin
VAR12 = 1;
VAR14 = {VAR26, VAR5, 40'h0};
VAR2 = 3'h2;
VAR31 = VAR10;
VAR17 = 1;
end
end
VAR10:
begin
VAR41 = 1;
VAR31 = VAR15;
VAR17 = 1;
end
VAR15:
begin
if (VAR3)
begin
VAR23 = 1;
VAR46 = 1;
VAR20 = 1;
VAR31 = VAR38;
VAR17 = 1;
end
end
default:
begin
end
endcase end endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor2/sky130_fd_sc_hd__xor2.functional.pp.v | 1,814 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR12 ,
VAR7,
VAR11,
VAR9 ,
VAR4
);
output VAR13 ;
input VAR8 ;
input VAR12 ;
input VAR7;
input VAR11;
input VAR9 ;
input VAR4 ;
wire VAR6 ;
wire VAR2;
xor VAR5 (VAR6 , VAR12, VAR8 );
VAR10 VAR3 (VAR2, VAR6, VAR7, VAR11);
buf VAR1 (VAR13 , VAR2 );
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_124.v | 1,465 | module MODULE1 (
VAR11,
VAR10
);
input [31:0] VAR11;
output [31:0]
VAR10;
wire [31:0]
VAR3,
VAR6,
VAR5,
VAR13,
VAR7,
VAR4,
VAR9,
VAR8;
assign VAR3 = VAR11;
assign VAR8 = VAR9 << 2;
assign VAR9 = VAR4 - VAR7;
assign VAR4 = VAR5 << 9;
assign VAR6 = VAR3 << 2;
assign VAR13 = VAR5 << 3;
assign VAR7 = VAR5 + VAR13;
assign VAR5 = VAR3 + VAR6;
assign VAR10 = VAR8;
endmodule
module MODULE2(
VAR11,
VAR10,
clk
);
input [31:0] VAR11;
output [31:0] VAR10;
reg [31:0] VAR10;
input clk;
reg [31:0] VAR12;
wire [30:0] VAR2;
always @(posedge clk) begin
VAR12 <= VAR11;
VAR10 <= VAR2;
end
MODULE1 MODULE1(
.VAR11(VAR12),
.VAR10(VAR2)
);
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.behavioral.v | 1,495 | module MODULE1( VAR6, VAR2, VAR4, VAR1 );
input VAR4, VAR2, VAR1;
output VAR6;
VAR7 VAR3(.VAR6(VAR6),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1));
VAR7 VAR5(.VAR6(VAR6),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha_m.v | 2,181 | module MODULE2 (
VAR10,
VAR7 ,
VAR1 ,
VAR3 ,
VAR2,
VAR6,
VAR9 ,
VAR5
);
output VAR10;
output VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR2;
input VAR6;
input VAR9 ;
input VAR5 ;
VAR8 VAR4 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR10,
VAR7 ,
VAR1 ,
VAR3
);
output VAR10;
output VAR7 ;
input VAR1 ;
input VAR3 ;
supply1 VAR2;
supply0 VAR6;
supply1 VAR9 ;
supply0 VAR5 ;
VAR8 VAR4 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
grantae/uart | src/uart_clock.v | 2,002 | module MODULE1(
input VAR4,
output VAR3,
output VAR5
);
reg [14:0] VAR2 = 15'h0000;
always @(posedge VAR4) begin
VAR2 <= VAR2[13:0] + 453;
end
assign VAR5 = VAR2[14];
reg [3:0] VAR1 = 4'h0;
always @(posedge VAR4) begin
VAR1 <= (VAR5) ? VAR1 + 1'b1 : VAR1;
end
assign VAR3 = (VAR5==1'b1 && (VAR1 == 4'b1111));
endmodule | mit |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_fpga_only_master.v | 21,672 | module MODULE1 #(
parameter VAR8 = 0,
parameter VAR31 = 50000,
parameter VAR6 = 2
) (
input wire VAR5, input wire VAR27, output wire [31:0] VAR36, input wire [31:0] VAR41, output wire VAR16, output wire VAR34, output wire [31:0] VAR14, input wire VAR10, input wire VAR35, output wire [3:0] VAR7, output wire VAR26 );
wire VAR11; wire [7:0] VAR24; wire VAR21; wire [7:0] VAR46; wire VAR3; wire VAR38; wire [7:0] VAR1; wire VAR9; wire VAR22; wire [7:0] VAR48; wire VAR32; wire [7:0] VAR39; wire VAR12; wire VAR25; wire VAR20; wire [7:0] VAR15; wire VAR17; wire VAR2; wire VAR42; wire VAR30; wire [7:0] VAR29; wire VAR40; wire VAR33; wire VAR28; wire VAR18; wire [7:0] VAR45; wire VAR43; wire [7:0] VAR4; wire VAR47; wire VAR13; wire VAR44; wire [7:0] VAR19; wire VAR37; wire VAR23;
generate
if (VAR8 != 0)
begin
begin
begin | gpl-3.0 |
18545/FPGA | FPGA.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v | 1,424 | module MODULE1(VAR5, VAR4, VAR1, VAR6, VAR3, VAR7, VAR2)
;
input VAR5;
input [0:0]VAR4;
input [18:0]VAR1;
input [3:0]VAR6;
input VAR3;
input [18:0]VAR7;
output [3:0]VAR2;
endmodule | mit |
bsteinsbo/DE1-SoC-Sound | cores/i2s/i2s_shift_out.v | 3,954 | module MODULE1 (
input clk, input VAR14, input [31:0] VAR4, input [31:0] VAR17, input VAR15, output reg VAR6,
input enable, input VAR16, input VAR7, output VAR18 );
reg VAR5;
always @(posedge clk or negedge VAR14)
begin
if (~VAR14)
begin
VAR5 <= 0;
end
else
begin
VAR5 <= VAR16;
end
end
wire VAR11 = VAR16 & ~VAR5;
wire VAR19 = ~VAR16 & VAR5;
reg VAR10;
always @(posedge clk or negedge VAR14)
begin
if (~VAR14)
begin
VAR10 <= 0;
end
else
begin
VAR10 <= VAR7;
end
end
wire VAR9 = VAR7 & ~VAR10;
wire VAR1 = ~VAR7 & VAR10;
reg [1:0] VAR8;
always @(posedge clk or negedge VAR14)
begin
if (~VAR14)
begin
VAR8 <= 0;
end
else
begin
if (VAR9)
VAR8 <= 2'b01;
end
else if (VAR8 == 2'b01 && VAR11)
VAR8 <= 2'b10;
end
else if (VAR8 == 2'b10 && VAR19)
VAR8 <= 2'b11;
else if (VAR8 == 2'b11)
VAR8 <= 2'b00;
end
end
wire VAR12 = VAR8 == 2'b11;
reg [1:0] VAR13;
always @(posedge clk or negedge VAR14)
begin
if (~VAR14)
begin
VAR13 <= 0;
end
else
begin
if (VAR1)
VAR13 <= 2'b01;
end
else if (VAR13 == 2'b01 && VAR11)
VAR13 <= 2'b10;
end
else if (VAR13 == 2'b10 && VAR19)
VAR13 <= 2'b11;
else if (VAR13 == 2'b11)
VAR13 <= 2'b00;
end
end
wire VAR2 = VAR13 == 2'b11;
reg [31:0] VAR3;
always @(posedge clk or negedge VAR14)
begin
if (~VAR14)
begin
VAR3 <= 0;
end
else
begin
if (~enable)
VAR3 <= 0;
end
else if (VAR12)
VAR3 <= VAR4;
end
else if (VAR2)
VAR3 <= VAR17;
else if (VAR19)
VAR3 <= {VAR3[30:0], 1'b0};
end
end
assign VAR18 = VAR3[31];
always @(posedge clk or negedge VAR14)
begin
if (~VAR14)
begin
VAR6 <= 0;
end
else
begin
if (~enable | ~VAR15)
VAR6 <= 0;
end
else
VAR6 <= VAR12;
end
end
endmodule | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.blackbox.v | 1,228 | module MODULE1 (
VAR1,
VAR4,
VAR6,
VAR3
);
output VAR1;
input VAR4;
input VAR6;
input VAR3;
supply1 VAR2;
supply0 VAR5;
endmodule | apache-2.0 |
hakehuang/pycpld | ips/ip/led_capture/captuer_tx.v | 1,055 | module MODULE1(
clk,VAR2,VAR12,VAR6,VAR7,VAR13,counter,VAR9
);
input clk;
input VAR2;
input VAR6;
input [31:0] counter;
input VAR9;
input[31:0] VAR7;
output VAR12;
output [7:0] VAR13;
reg VAR12;
reg[7:0] VAR13;
always @ (posedge clk or negedge VAR2) begin
if (!VAR2)begin
VAR12 <= 1'b1;
VAR13 <= 'VAR4;
end
else if(VAR6)begin
VAR12 <= 1'b0;
VAR13 <= (VAR7 >= 'd100000000) ? "VAR1"
:((VAR7 < 'd100000000) && (VAR7 >= 'd10000000)) ? "VAR11"
:((VAR7 < 'd10000000) && (VAR7 >= 'd5000000)) ? "VAR5"
:(VAR7 < 'd5000000) ? "VAR8" : 'VAR4;
end
else if(counter > 'd300000000)begin
VAR12 <= 1'b0;
VAR13 <= VAR9 ? "VAR3" : "VAR10";
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p.symbol.v | 1,400 | module MODULE1 (
input VAR7 ,
output VAR4 ,
input VAR2
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/altera_mult_add_e9u2.v | 15,369 | module MODULE1
(
VAR69,
VAR135,
VAR227,
VAR271,
VAR280) ;
input VAR69;
input VAR135;
input [15:0] VAR227;
input [15:0] VAR271;
output [31:0] VAR280;
tri0 VAR69;
tri1 VAR135;
tri0 [15:0] VAR227;
tri0 [15:0] VAR271;
wire [31:0] VAR258;
VAR61 VAR117
(
.VAR69(VAR69),
.VAR24(),
.VAR135(VAR135),
.VAR227(VAR227),
.VAR271(VAR271),
.VAR260(),
.VAR149(),
.VAR79(),
.VAR51(),
.VAR138(),
.VAR280(VAR258),
.VAR33(),
.VAR197(),
.VAR191(1'b0),
.VAR35(1'b0),
.VAR285(1'b0),
.VAR186(1'b0),
.VAR272(1'b1),
.VAR12(1'b0),
.VAR161(1'b1),
.VAR214(1'b0),
.VAR203({1{1'b0}}),
.VAR44(1'b0),
.VAR34(1'b0),
.VAR94(1'b1),
.VAR212(1'b1),
.VAR181(1'b1),
.VAR36({3{1'b0}}),
.VAR287({3{1'b0}}),
.VAR146({3{1'b0}}),
.VAR164({3{1'b0}}),
.VAR40({22{1'b0}}),
.VAR11(1'b1),
.VAR157(1'b1),
.VAR1(1'b1),
.VAR92(1'b1),
.VAR215(1'b0),
.VAR47(1'b0),
.VAR31(1'b0),
.VAR57(1'b0),
.VAR188(1'b0),
.VAR248(1'b0),
.VAR241(1'b0),
.VAR201({16{1'b0}}),
.VAR151({16{1'b0}}),
.VAR71(1'b0),
.VAR73(1'b0),
.VAR85(1'b0),
.VAR46(1'b0),
.VAR233({1{1'b0}}),
.VAR183({1{1'b0}}),
.VAR3(1'b0),
.VAR265(1'b0)
);
VAR117.VAR28 = "VAR152",
VAR117.VAR194 = "VAR95",
VAR117.VAR54 = "VAR95",
VAR117.VAR257 = "VAR213",
VAR117.VAR172 = "VAR213",
VAR117.VAR228 = "VAR126",
VAR117.VAR109 = "VAR126",
VAR117.VAR4 = "VAR126",
VAR117.VAR221 = "VAR95",
VAR117.VAR250 = "VAR95",
VAR117.VAR98 = "VAR213",
VAR117.VAR235 = "VAR213",
VAR117.VAR262 = "VAR95",
VAR117.VAR269 = "VAR95",
VAR117.VAR211 = "VAR213",
VAR117.VAR15 = "VAR213",
VAR117.VAR115 = "VAR95",
VAR117.VAR141 = "VAR95",
VAR117.VAR169 = "VAR53",
VAR117.VAR143 = "VAR95",
VAR117.VAR195 = "VAR229",
VAR117.VAR82 = "VAR213",
VAR117.VAR10 = "VAR213",
VAR117.VAR49 = "VAR213",
VAR117.VAR67 = "VAR95",
VAR117.VAR175 = "VAR126",
VAR117.VAR234 = "VAR213",
VAR117.VAR238 = "VAR95",
VAR117.VAR270 = "VAR95",
VAR117.VAR219 = "VAR213",
VAR117.VAR267 = "VAR95",
VAR117.VAR274 = "VAR213",
VAR117.VAR43 = "VAR213",
VAR117.VAR105 = "VAR126",
VAR117.VAR75 = "VAR95",
VAR117.VAR216 = "VAR95",
VAR117.VAR87 = "VAR213",
VAR117.VAR127 = "VAR95",
VAR117.VAR41 = "VAR213",
VAR117.VAR263 = "VAR213",
VAR117.VAR178 = "VAR126",
VAR117.VAR121 = 0,
VAR117.VAR163 = 0,
VAR117.VAR206 = 0,
VAR117.VAR125 = 0,
VAR117.VAR184 = 0,
VAR117.VAR13 = 0,
VAR117.VAR55 = 0,
VAR117.VAR240 = 0,
VAR117.VAR182 = 0,
VAR117.VAR255 = 0,
VAR117.VAR89 = 0,
VAR117.VAR160 = 0,
VAR117.VAR281 = 0,
VAR117.VAR84 = 0,
VAR117.VAR72 = 0,
VAR117.VAR104 = 0,
VAR117.VAR101 = 0,
VAR117.VAR22 = 0,
VAR117.VAR256 = 0,
VAR117.VAR242 = 0,
VAR117.VAR14 = 0,
VAR117.VAR199 = 0,
VAR117.VAR62 = 0,
VAR117.VAR246 = 0,
VAR117.VAR124 = 0,
VAR117.VAR99 = 0,
VAR117.VAR110 = 0,
VAR117.VAR8 = 0,
VAR117.VAR159 = 0,
VAR117.VAR45 = 0,
VAR117.VAR16 = 0,
VAR117.VAR278 = 0,
VAR117.VAR218 = "VAR95",
VAR117.VAR96 = "VAR213",
VAR117.VAR76 = "VAR95",
VAR117.VAR196 = "VAR213",
VAR117.VAR120 = "VAR95",
VAR117.VAR158 = "VAR213",
VAR117.VAR170 = "VAR95",
VAR117.VAR225 = "VAR213",
VAR117.VAR131 = "VAR123",
VAR117.VAR166 = "VAR126",
VAR117.VAR26 = "VAR58",
VAR117.VAR289 = 0,
VAR117.VAR247 = "VAR95",
VAR117.VAR167 = "VAR95",
VAR117.VAR245 = "VAR95",
VAR117.VAR17 = "VAR95",
VAR117.VAR137 = "VAR95",
VAR117.VAR276 = "VAR95",
VAR117.VAR147 = "VAR95",
VAR117.VAR283 = "VAR95",
VAR117.VAR253 = "VAR95",
VAR117.VAR193 = "VAR95",
VAR117.VAR176 = "VAR95",
VAR117.VAR39 = "VAR95",
VAR117.VAR187 = "VAR213",
VAR117.VAR52 = "VAR213",
VAR117.VAR111 = "VAR213",
VAR117.VAR243 = "VAR213",
VAR117.VAR232 = "VAR213",
VAR117.VAR50 = "VAR213",
VAR117.VAR37 = "VAR213",
VAR117.VAR266 = "VAR213",
VAR117.VAR168 = "VAR213",
VAR117.VAR150 = "VAR213",
VAR117.VAR74 = "VAR213",
VAR117.VAR155 = "VAR213",
VAR117.VAR91 = "VAR180",
VAR117.VAR30 = "VAR180",
VAR117.VAR177 = "VAR180",
VAR117.VAR145 = "VAR180",
VAR117.VAR25 = "VAR38",
VAR117.VAR129 = "VAR38",
VAR117.VAR200 = "VAR38",
VAR117.VAR284 = "VAR38",
VAR117.VAR2 = "VAR95",
VAR117.VAR173 = "VAR213",
VAR117.VAR78 = 64,
VAR117.VAR189 = "VAR95",
VAR117.VAR65 = "VAR213",
VAR117.VAR156 = "VAR53",
VAR117.VAR207 = "VAR213",
VAR117.VAR29 = "VAR95",
VAR117.VAR171 = "VAR213",
VAR117.VAR130 = "VAR95",
VAR117.VAR18 = "VAR213",
VAR117.VAR116 = "VAR126",
VAR117.VAR226 = "VAR126",
VAR117.VAR230 = "VAR152",
VAR117.VAR237 = "VAR126",
VAR117.VAR106 = "VAR126",
VAR117.VAR27 = "VAR152",
VAR117.VAR134 = "VAR53",
VAR117.VAR208 = "VAR95",
VAR117.VAR259 = "VAR95",
VAR117.VAR251 = "VAR95",
VAR117.VAR80 = "VAR229",
VAR117.VAR100 = "VAR213",
VAR117.VAR90 = "VAR213",
VAR117.VAR6 = "VAR213",
VAR117.VAR20 = 1,
VAR117.VAR108 = "VAR95",
VAR117.VAR103 = "VAR213",
VAR117.VAR97 = "VAR95",
VAR117.VAR190 = "VAR95",
VAR117.VAR86 = "VAR213",
VAR117.VAR277 = "VAR213",
VAR117.VAR64 = "VAR114",
VAR117.VAR165 = "VAR126",
VAR117.VAR249 = "VAR95",
VAR117.VAR217 = "VAR95",
VAR117.VAR83 = "VAR213",
VAR117.VAR148 = "VAR213",
VAR117.VAR59 = "VAR133",
VAR117.VAR142 = "VAR126",
VAR117.VAR205 = "VAR77",
VAR117.VAR132 = "VAR77",
VAR117.VAR210 = "VAR77",
VAR117.VAR23 = "VAR77",
VAR117.VAR7 = "VAR77",
VAR117.VAR236 = "VAR77",
VAR117.VAR179 = "VAR152",
VAR117.VAR279 = "VAR152",
VAR117.VAR275 = "VAR152",
VAR117.VAR162 = "VAR152",
VAR117.VAR231 = "VAR113",
VAR117.VAR282 = "VAR21",
VAR117.VAR144 = "VAR21",
VAR117.VAR244 = "VAR95",
VAR117.VAR209 = "VAR95",
VAR117.VAR9 = "VAR213",
VAR117.VAR112 = "VAR95",
VAR117.VAR118 = "VAR213",
VAR117.VAR136 = "VAR213",
VAR117.VAR286 = "VAR95",
VAR117.VAR204 = "VAR213",
VAR117.VAR32 = "VAR107 VAR93 VAR185",
VAR117.VAR273 = "VAR126",
VAR117.VAR264 = "VAR95",
VAR117.VAR220 = "VAR95",
VAR117.VAR81 = "VAR213",
VAR117.VAR63 = "VAR95",
VAR117.VAR48 = "VAR213",
VAR117.VAR223 = "VAR213",
VAR117.VAR153 = "VAR95",
VAR117.VAR174 = "VAR95",
VAR117.VAR60 = "VAR53",
VAR117.VAR140 = "VAR53",
VAR117.VAR122 = "VAR229",
VAR117.VAR139 = "VAR229",
VAR117.VAR268 = "VAR213",
VAR117.VAR290 = "VAR213",
VAR117.VAR154 = "VAR95",
VAR117.VAR66 = "VAR95",
VAR117.VAR5 = "VAR213",
VAR117.VAR70 = "VAR213",
VAR117.VAR128 = "VAR126",
VAR117.VAR119 = 16,
VAR117.VAR222 = 16,
VAR117.VAR42 = 22,
VAR117.VAR202 = 1,
VAR117.VAR252 = 18,
VAR117.VAR239 = 17,
VAR117.VAR56 = 32,
VAR117.VAR68 = 1,
VAR117.VAR19 = "VAR95",
VAR117.VAR102 = "VAR213",
VAR117.VAR88 = "VAR95",
VAR117.VAR254 = "VAR95",
VAR117.VAR224 = "VAR213",
VAR117.VAR198 = "VAR95",
VAR117.VAR261 = "VAR213",
VAR117.VAR288 = "VAR213",
VAR117.VAR192 = "VAR61";
assign
VAR280 = VAR258;
endmodule | gpl-2.0 |
open-fpga-nvm/open-nvm-source | fpga/NAND/Top_NAND.v | 36,863 | module MODULE1(
input VAR10,
input rst,
input VAR49,
output VAR105, output VAR32, output VAR68, output VAR122, output VAR25, output VAR66, output VAR93, input VAR86, output VAR6, inout [7:0] VAR28,
output VAR127,
input VAR36,
output [7:0] VAR48,
output [7:0] VAR120,
output [3:0] VAR67
);
reg [1:0] VAR15; reg [4:0] VAR72;
wire clk;
assign clk = (VAR49) ? 1'b0 : VAR10;
reg [7:0] VAR88;
reg [3:0] VAR20;
assign VAR120[7:0] = VAR88[7:0];
assign VAR67[3:0] = VAR20[3:0];
reg [5:0] VAR62;
reg [7:0] VAR126;
always@(posedge VAR10)
begin
if (VAR126 >= 200)
begin
VAR126 <= 0;
case(VAR20)
4'b1110:
begin
VAR20 <= 4'b0111;
VAR62 <= {(VAR107 == 00), VAR128[3:0]};
end
4'b0111:
begin
VAR20 <= 4'b1011;
VAR62 <= { VAR137, VAR99[3:0] };
end
4'b1011:
begin
VAR20 <= 4'b1101;
VAR62 <={ 1'b0, VAR72[4:0] };
end
4'b1101:
begin
VAR20 <= 4'b1110;
VAR62 <= {(VAR107 == 08), VAR128[7:4]};
end
default:
VAR20 <= 4'b1011;
endcase
case( VAR62 )
5'h00: VAR88 <= 8'b00000011; 5'h01: VAR88 <= 8'b10011111; 5'h02: VAR88 <= 8'b00100101; 5'h03: VAR88 <= 8'b00001101; 5'h04: VAR88 <= 8'b10011001; 5'h05: VAR88 <= 8'b01001001; 5'h06: VAR88 <= 8'b01000001; 5'h07: VAR88 <= 8'b00011111; 5'h08: VAR88 <= 8'b00000001; 5'h09: VAR88 <= 8'b00001001; 5'h0A: VAR88 <= 8'b00010001; 5'h0B: VAR88 <= 8'b11000001; 5'h0C: VAR88 <= 8'b11100101; 5'h0D: VAR88 <= 8'b10000101; 5'h0E: VAR88 <= 8'b01100001; 5'h0F: VAR88 <= 8'b01110001;
5'h10: VAR88 <= 8'b00000010; 5'h11: VAR88 <= 8'b10011110; 5'h12: VAR88 <= 8'b00100100; 5'h13: VAR88 <= 8'b00001100; 5'h14: VAR88 <= 8'b10011000; 5'h15: VAR88 <= 8'b01001000; 5'h16: VAR88 <= 8'b01000000; 5'h17: VAR88 <= 8'b00011110; 5'h18: VAR88 <= 8'b00000000; 5'h19: VAR88 <= 8'b00001000; 5'h1A: VAR88 <= 8'b00010000; 5'h1B: VAR88 <= 8'b11000000; 5'h1C: VAR88 <= 8'b11100100; 5'h1D: VAR88 <= 8'b10000100; 5'h1E: VAR88 <= 8'b01100000; 5'h1F: VAR88 <= 8'b01110000;
default:
begin
VAR88 <= 8'b11111111;
end
endcase
end
else if(VAR126 < 200)
begin
VAR126 <= VAR126 + 1'b1;
end
else
begin
VAR126 <= 0;
end
end
wire [31:0] VAR87;
wire [31:0] VAR38;
wire [31:0] VAR85;
assign VAR85 = (VAR15==VAR3) ? VAR61 : VAR38;
reg VAR58;
reg [3:0] VAR97;
wire [7:0] VAR124;
wire [7:0] VAR128;
VAR14 VAR14(
.clk(VAR10),
.rst(rst),
.VAR92(VAR58),
.VAR121(VAR124),
.VAR59(VAR39),
.VAR79(VAR127)
);
VAR44 VAR44(
.clk(VAR10),
.rst(rst),
.VAR125(VAR128),
.VAR113(VAR110),
.VAR138(VAR36)
);
reg [6:0] VAR107;
reg [3:0] VAR99;
wire [ 7:0] VAR91, VAR56, VAR55, VAR78, VAR17, VAR132,
VAR46, VAR47, VAR100, VAR12, VAR4;
reg [95:0] VAR89;
assign { VAR4[7:0], VAR12[7:0], VAR100[7:0], VAR47[7:0], VAR46[7:0], VAR132[7:0],
VAR17[7:0], VAR78[7:0], VAR55[7:0], VAR56[7:0], VAR91[7:0] } = VAR89[87:0];
wire VAR136;
reg VAR69;
assign VAR136 = VAR69;
reg VAR137;
reg VAR1, VAR115 , VAR23, VAR34;
reg VAR22, VAR80, VAR90;
reg [11:0] VAR116, VAR21;
reg [31:0] VAR54, VAR111;
reg [16:0] VAR76, VAR98;
parameter VAR33 = 8'h00, VAR31 = 8'h01, VAR9 = 8'h02, VAR43 = 8'h03,
VAR83 = 8'h04, VAR35 = 8'h05,
VAR71= 8'hF0, VAR51 = 8'hF1;
always@(posedge VAR110 or posedge VAR136)
begin
if (VAR136)
begin
VAR107 <= 0;
VAR99 <= 0;
VAR89 <= 0;
VAR137 <= 0;
VAR116 <= 0;
VAR21 <= 1;
VAR1 <= 1;
VAR115 <= 1;
VAR23 <= 1;
VAR34<= 1;
VAR22 <= 1;
VAR80 <= 1;
VAR90 <= 1;
VAR54 <= 1;
VAR111 <= 0;
end
else
begin
if(VAR107 == 88 && VAR128 == 8'hEE)
begin
VAR107 <= 0;
VAR99 <= VAR99 + 1'b1;
case(VAR91)
VAR33 :
begin
VAR116 <= {16'd0, VAR78[3:0], VAR17[7:0]};
VAR21 <= {16'd0, VAR47[3:0], VAR100[7:0]};
end
VAR31 :
begin
VAR1 <= VAR56[0];
VAR115 <= VAR56[1];
VAR23 <= VAR56[2];
VAR34<= VAR56[3];
end
VAR9 :
begin
VAR54 <= {VAR56[7:0], VAR55[7:0], VAR78[7:0], VAR17[7:0]};
end
VAR43 :
begin
VAR111 <= {VAR56[7:0], VAR55[7:0], VAR78[7:0], VAR17[7:0]};
end
VAR83 :
begin
VAR22 <= VAR56[0];
VAR80 <= VAR56[1];
VAR90 <= VAR56[2];
VAR76[16] <= VAR78[0];
VAR76[15:0] <= {VAR132[7:0], VAR46[7:0]};
VAR98[16] <= VAR17[0];
VAR98[15:0] <= {VAR47[7:0], VAR100[7:0]};
end
VAR35 :
begin
VAR76[16] <= VAR78[0];
VAR76[15:0] <= {VAR132[7:0], VAR46[7:0]};
VAR98[16] <= VAR17[0];
VAR98[15:0] <= {VAR47[7:0], VAR100[7:0]};
end
VAR71 :
begin
VAR137 <= 1;
end
VAR51 :
begin
VAR137 <= 0;
end
default:
begin
;
end
endcase
end
else if(VAR107 == 88)
begin
VAR107 <= 0;
end
else
begin
VAR89[VAR107 + 3'd0] <= VAR128[0];
VAR89[VAR107 + 3'd1] <= VAR128[1];
VAR89[VAR107 + 3'd2] <= VAR128[2];
VAR89[VAR107 + 3'd3] <= VAR128[3];
VAR89[VAR107 + 3'd4] <= VAR128[4];
VAR89[VAR107 + 3'd5] <= VAR128[5];
VAR89[VAR107 + 3'd6] <= VAR128[6];
VAR89[VAR107 + 3'd7] <= VAR128[7];
VAR107 <= VAR107 + 4'd8;
end
end
end
wire VAR84;
wire VAR114;
wire VAR13;
wire VAR24;
wire VAR18;
wire VAR135;
wire [7:0] VAR19;
wire VAR29;
assign VAR105 = VAR117;
assign VAR32 = 0;
assign VAR68 = VAR84;
assign VAR122 = VAR114;
assign VAR25 = VAR13;
assign VAR66 = VAR24;
assign VAR93 = VAR18;
assign VAR135 = VAR37;
assign VAR6 = 0; assign VAR28[7:0] = VAR19[7:0];
assign VAR29 = VAR61[0];
reg [8:0] VAR64; reg [11:0] VAR2;
reg [31:0] VAR61;
reg [31:0] VAR95;
parameter VAR75 = 0, VAR70 = 1, VAR81 = 2;
reg [2:0] VAR101;
wire [39:0] addr;
assign addr[39:32] = 8'h0; assign addr[31:24] = 8'h0; assign {addr[ 8], addr[23:16]} = VAR64;
assign {addr[ 4: 0],addr[15: 9]} = VAR2;
assign addr[ 7: 5] = 0;
reg VAR94;
wire VAR106;
assign VAR124[7:0]=( (VAR97 == 0) ? { 6'h0, VAR15[1:0] } : ( (VAR97 == 1) ? { 8'h0 } : ( (VAR97 == 2) ? { 3'h0, VAR2[11:7]} : ( (VAR97 == 3) ? { VAR2[6:0], VAR64[8] } : ( (VAR97 == 4) ? { VAR64[7:0] } : ( (VAR97 == 5) ? { VAR87[31:24] } :
( (VAR97 == 6) ? { VAR87[23:16] } :
( (VAR97 == 7) ? { VAR87[15: 8] } :
( (VAR97 == 8) ? { VAR87[ 7: 0] } :
( (VAR97 == 9) ? { VAR85[31:24] } :
( (VAR97 == 10) ? { VAR85[23:16] } :
(VAR97 == 11) ? { VAR85[15: 8] } :
(VAR97 == 12) ? { VAR85[ 7: 0] } :
{ 8'hEE }
)
)
)
)
)
)
)
)
)
)
);
VAR26 VAR26(
.VAR77(clk),
.VAR103(rst),
.VAR65(VAR15),
.VAR11(addr),
.VAR29(VAR29),
.VAR96(VAR94),
.VAR129(VAR106),
.VAR87(VAR87),
.VAR38(VAR38),
.VAR48(VAR48),
.VAR104(VAR76[16]),
.VAR108(VAR76[7:0]),
.VAR40(VAR98[16]),
.VAR7(VAR98[7:0]),
.VAR117(VAR117),
.VAR84(VAR84),
.VAR114(VAR114),
.VAR13(VAR13),
.VAR24(VAR24),
.VAR18(VAR18),
.VAR135(VAR135),
.VAR19(VAR19)
);
parameter
VAR74 = 30, VAR30 = 29, VAR45 = 28,
VAR109= 01, VAR63= 02, VAR16= 03, VAR119= 04, VAR53= 05,
VAR52 = 06, VAR50 = 07, VAR57 = 08, VAR73 = 09, VAR130 = 10, VAR118 = 11, VAR134 = 12, VAR41 = 13, VAR123 = 14, VAR133 = 15, VAR82 = 16, VAR27 = 17, VAR102 = 18,
VAR8 = 19,
VAR5 = 31;
parameter
VAR42 = 2'd0,
VAR112 = 2'd1,
VAR131 = 2'd2,
VAR3 = 2'd3;
always@(posedge clk)
begin
if (rst==1)
begin
VAR72 <= VAR74;
end
else
begin
case(VAR72)
VAR74:
begin
VAR69 <= 0;
VAR72 <= VAR30;
end
VAR30:
begin
VAR69 <= 1;
VAR72 <= VAR45;
end
VAR45:
begin
VAR69 <= 0;
VAR94 <= 0;
VAR64 <= 0;
VAR2 <= VAR116;
VAR97 <= 0;
VAR58<= 0;
VAR101 <= 0; VAR61 <= 0;
VAR95 <= 0;
VAR15 <= VAR3;
if(VAR137)
VAR72 <= VAR109;
end
else
VAR72 <= VAR45;
end
VAR8:
begin
VAR94 <= 0;
VAR64 <= 0;
VAR2 <= VAR116;
VAR97 <= 0;
VAR58<= 0;
VAR101 <= 0; VAR61 <= VAR61 + 1'b1;
VAR15 <= VAR3;
VAR72 <= VAR109;
if(VAR95[31:0] == VAR111[31:0]) VAR95 <= 0;
end
else
VAR95 <= VAR95 + 1'b1;
end
VAR109: begin
if( (VAR64 <= 5) || (VAR64 == 8) || ( VAR101 == 5 ) )
end
VAR101 <= 0; else if( VAR64 <= 7 )
VAR101 <= 2; else
VAR101 <= VAR101 + 1'b1;
VAR72 <= VAR63;
end
VAR63:
begin
if (VAR15[1:0] == VAR3) begin
VAR72 <= VAR52;
end
else if (VAR15[1:0] == VAR131) begin
VAR72 <= VAR41;
end
else if(VAR101[2:1] == VAR75 && VAR22==0) begin
VAR72 <= VAR16;
end
else if(VAR101[2:1] == VAR70 && VAR80==0)
begin
VAR72 <= VAR16;
end
else if(VAR101[2:1] == VAR81 && VAR90==0)
begin
VAR72 <= VAR16;
end
else if (VAR15[1:0] == VAR112)
begin
VAR72 <= VAR118;
end
else begin
VAR72 <= VAR73;
end
end
VAR52:
begin
VAR94 <= 1; VAR72 <= VAR50;
end
VAR50:
begin
if (VAR106 == 1) begin
VAR72 <= VAR133;
end
else VAR72 <= VAR50;
end
VAR73:
begin
if(VAR1)
begin
VAR94 <= 1;
VAR72 <= VAR130;
end
else begin
VAR72 <= VAR16;
end
end
VAR130:
begin
if (VAR106 == 1)
begin
VAR72 <= VAR133;
end
else VAR72 <= VAR130;
end
VAR118:
begin
if(VAR115)
begin
VAR94 <= 1;
VAR72 <= VAR134;
end
else begin
VAR72 <= VAR16;
end
end
VAR134:
begin
if (VAR106 == 1)
begin
VAR72 <= VAR133;
end
else VAR72 <= VAR134;
end
VAR41: begin
if(VAR23)
begin
VAR94 <= 1;
VAR72 <= VAR123;
end
else begin
VAR72 <= VAR16;
end
end
VAR123:
begin
if (VAR106 == 1)
begin
VAR72 <= VAR133;
end
else VAR72 <= VAR123;
end
VAR133:
begin
if(VAR95[31:1] == VAR111[31:1]) begin
VAR72 <= VAR82;
end
else
begin
VAR72 <= VAR16;
end
end
VAR82:
begin
VAR58 <= 1;
VAR72 <= VAR27;
end
VAR27:
begin
if(VAR39 == 1)
begin
VAR58 <= 0;
VAR72 <= VAR102;
end
else
begin
VAR72 <= VAR82;
end
end
VAR102:
begin
if( VAR97[3:0] == 4'd14-1 )
begin
VAR97 <= 0;
VAR72 <= VAR16;
end
else
begin
VAR97 <= VAR97 + 1'b1;
VAR72 <= VAR133;
end
end
VAR16: begin
VAR94 <= 0;
if( VAR64[8:0] == VAR60 ) begin
VAR72 <= VAR119;
end
else if (VAR15[1] == 1) begin
VAR72 <= VAR119;
end
else
begin VAR64 <= VAR64 + 1'b1;
VAR72 <= VAR109;
end
end
VAR119: begin
VAR64 <= 0;
if (VAR15 == VAR131) begin
VAR15 <= VAR42;
VAR72 <= VAR53;
end
else begin
VAR15 <= VAR15 + 1'b1;
VAR72 <= VAR109;
end
end
VAR53: begin
if (VAR137 == 0) begin
VAR72 <= VAR45;
end
else if( VAR2[11:0] == VAR21 ) begin
VAR72 <= VAR5;
end
else begin
VAR2 <= VAR2 + 1'b1;
VAR72 <= VAR109;
end
end
VAR5:
begin
VAR94 <= 0;
VAR2 <= 12'hFFF;
if (VAR61 == VAR54-1)
begin
VAR72 <= VAR74;
end
else
begin
VAR72 <= VAR8;
end
end
default:
begin
VAR72 <= VAR74;
end
endcase
end
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfstp/sky130_fd_sc_lp__srsdfstp.symbol.v | 1,602 | module MODULE1 (
input VAR4 ,
output VAR12 ,
input VAR11 ,
input VAR2 ,
input VAR3 ,
input VAR9 ,
input VAR6
);
supply1 VAR1;
supply1 VAR8 ;
supply0 VAR10 ;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaReadDwordReg.v | 2,411 | module MODULE1
(
input wire reset, input wire VAR17, input wire VAR19, input wire [31:0] in,
input wire [11:0] VAR21, inout wire [7:0] VAR11
);
parameter VAR12 = 0;
wire [7:0] VAR3;
wire [7:0] VAR10;
wire [7:0] VAR14;
wire [7:0] VAR13;
wire VAR16 = (VAR12 == VAR21[11:4]);
wire read = VAR16 & VAR21[3];
wire enable = VAR19 & ~VAR16;
reg [1:0] select;
always @(posedge VAR21[0])
begin
if( reset | ~VAR16)
select <= 2'h0;
end
else if(VAR21[1] & VAR16)
select <= select + 2'h1;
end
VAR15 VAR4( .VAR6(in[31:24]), .VAR8( enable ), .VAR7(reset), .VAR2(VAR17), .VAR5(VAR13));
VAR15 VAR1( .VAR6(in[23:16]), .VAR8( enable ), .VAR7(reset), .VAR2(VAR17), .VAR5(VAR14));
VAR15 VAR18( .VAR6(in[15:8]), .VAR8( enable ), .VAR7(reset), .VAR2(VAR17), .VAR5(VAR10));
VAR15 VAR9( .VAR6(in[7:0]), .VAR8( enable ), .VAR7(reset), .VAR2(VAR17), .VAR5(VAR3));
assign VAR11 = (read & select == 2'h3) ? VAR13 : 8'VAR20;
assign VAR11 = (read & select == 2'h2) ? VAR14 : 8'VAR20;
assign VAR11 = (read & select == 2'h1) ? VAR10 : 8'VAR20;
assign VAR11 = (read & select == 2'h0) ? VAR3 : 8'VAR20;
endmodule | gpl-2.0 |
saiedhk/WhirlpoolHashEngine | whirlpool_wcipher_pi.v | 3,548 | module MODULE1 (
output [7:0] VAR76, VAR29, VAR122, VAR5, VAR50, VAR78, VAR19, VAR85,
VAR67, VAR17, VAR28, VAR89, VAR125, VAR90, VAR12, VAR66,
VAR43, VAR21, VAR101, VAR10, VAR14, VAR108, VAR44, VAR112,
VAR71, VAR46, VAR68, VAR34, VAR11, VAR63, VAR58, VAR103,
VAR106, VAR97, VAR127, VAR105, VAR109, VAR87, VAR128, VAR120,
VAR121, VAR9, VAR31, VAR25, VAR40, VAR49, VAR92, VAR70,
VAR4, VAR59, VAR39, VAR1, VAR18, VAR65, VAR69, VAR23,
VAR38, VAR86, VAR42, VAR24, VAR3, VAR47, VAR48, VAR52,
input [7:0] VAR32, VAR100, VAR115, VAR98, VAR55, VAR74, VAR104, VAR126,
VAR53, VAR113, VAR56, VAR45, VAR83, VAR2, VAR73, VAR81,
VAR96, VAR84, VAR60, VAR119, VAR7, VAR30, VAR91, VAR13,
VAR37, VAR107, VAR102, VAR94, VAR75, VAR27, VAR62, VAR118,
VAR116, VAR6, VAR35, VAR51, VAR22, VAR110, VAR16, VAR114,
VAR41, VAR61, VAR54, VAR64, VAR33, VAR82, VAR15, VAR123,
VAR57, VAR80, VAR26, VAR79, VAR20, VAR77, VAR124, VAR111,
VAR93, VAR72, VAR95, VAR99, VAR36, VAR117, VAR8, VAR88
);
assign VAR76 = VAR32;
assign VAR67 = VAR53;
assign VAR43 = VAR96;
assign VAR71 = VAR37;
assign VAR106 = VAR116;
assign VAR121 = VAR41;
assign VAR4 = VAR57;
assign VAR38 = VAR93;
assign VAR29 = VAR72;
assign VAR17 = VAR100;
assign VAR21 = VAR113;
assign VAR46 = VAR84;
assign VAR97 = VAR107;
assign VAR9 = VAR6;
assign VAR59 = VAR61;
assign VAR86 = VAR80;
assign VAR122 = VAR26;
assign VAR28 = VAR95;
assign VAR101 = VAR115;
assign VAR68 = VAR56;
assign VAR127 = VAR60;
assign VAR31 = VAR102;
assign VAR39 = VAR35;
assign VAR42 = VAR54;
assign VAR5 = VAR64;
assign VAR89 = VAR79;
assign VAR10 = VAR99;
assign VAR34 = VAR98;
assign VAR105 = VAR45;
assign VAR25 = VAR119;
assign VAR1 = VAR94;
assign VAR24 = VAR51;
assign VAR50 = VAR22;
assign VAR125 = VAR33;
assign VAR14 = VAR20;
assign VAR11 = VAR36;
assign VAR109 = VAR55;
assign VAR40 = VAR83;
assign VAR18 = VAR7;
assign VAR3 = VAR75;
assign VAR78 = VAR27;
assign VAR90 = VAR110;
assign VAR108 = VAR82;
assign VAR63 = VAR77;
assign VAR87 = VAR117;
assign VAR49 = VAR74;
assign VAR65 = VAR2;
assign VAR47 = VAR30;
assign VAR19 = VAR91;
assign VAR12 = VAR62;
assign VAR44 = VAR16;
assign VAR58 = VAR15;
assign VAR128 = VAR124;
assign VAR92 = VAR8;
assign VAR69 = VAR104;
assign VAR48 = VAR73;
assign VAR85 = VAR81;
assign VAR66 = VAR13;
assign VAR112 = VAR118;
assign VAR103 = VAR114;
assign VAR120 = VAR123;
assign VAR70 = VAR111;
assign VAR23 = VAR88;
assign VAR52 = VAR126;
endmodule | mit |
sh-chris110/chris | FPGA/chris/Qsys/soc_design/synthesis/submodules/soc_design_mm_interconnect_0_avalon_st_adapter_008.v | 6,176 | module MODULE1 #(
parameter VAR6 = 18,
parameter VAR3 = 0,
parameter VAR12 = 18,
parameter VAR20 = 0,
parameter VAR15 = 0,
parameter VAR10 = 0,
parameter VAR1 = 1,
parameter VAR11 = 1,
parameter VAR22 = 0,
parameter VAR5 = 18,
parameter VAR23 = 0,
parameter VAR4 = 1,
parameter VAR7 = 0,
parameter VAR13 = 1,
parameter VAR18 = 1,
parameter VAR25 = 0
) (
input wire VAR17, input wire VAR2, input wire [17:0] VAR16, input wire VAR24, output wire VAR8, output wire [17:0] VAR14, output wire VAR21, input wire VAR19, output wire [0:0] VAR9 );
generate
if (VAR6 != 18)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | gpl-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/bram_fifo/bram_fifo_core.v | 4,902 | module MODULE1 #(
parameter VAR43 = 32'h8000,
parameter VAR28 = 95, parameter VAR36 = 5, parameter VAR41 = 32
) (
input wire VAR14,
input wire VAR1,
input wire [VAR41-1:0] VAR39,
input wire [7:0] VAR31,
input wire VAR9,
input wire VAR6,
output reg [7:0] VAR33,
input wire VAR38,
output reg [31:0] VAR5,
input wire VAR40,
input wire [31:0] VAR15,
output wire VAR2,
input wire VAR23,
input wire [31:0] VAR13,
output wire VAR34,
output wire VAR21,
output reg VAR16,
output wire VAR4
);
localparam VAR35 = 2;
wire VAR37; assign VAR37 = (VAR39==0 && VAR6);
wire VAR27;
assign VAR27 = VAR1 | VAR37;
reg [7:0] VAR25[7:0];
wire [7:0] VAR42;
assign VAR42 = VAR25[1];
wire [7:0] VAR22;
assign VAR22 = VAR25[2];
always @(posedge VAR14)
begin
if(VAR27)
begin
VAR25[0] <= 8'b0;
VAR25[1] <= 255*VAR28/100;
VAR25[2] <= 255*VAR36/100;
VAR25[3] <= 8'b0;
VAR25[4] <= 8'b0;
VAR25[5] <= 8'b0;
VAR25[6] <= 8'b0;
VAR25[7] <= 8'b0;
end
else if(VAR6 && VAR39 < 8)
begin
VAR25[VAR39[2:0]] <= VAR31;
end
end
wire [31:0] VAR29; reg [31:0] VAR24;
reg [7:0] VAR26; wire [31:0] VAR12; assign VAR29 = VAR12 * 4;
always @(posedge VAR14) begin
if(VAR9) begin
if(VAR39 == 0)
VAR33 <= VAR35;
end
else if(VAR39 == 1)
VAR33 <= VAR42;
end
else if(VAR39 == 2)
VAR33 <= VAR22;
else if(VAR39 == 3)
VAR33 <= VAR26;
else if(VAR39 == 4)
VAR33 <= VAR29[7:0]; else if(VAR39 == 5)
VAR33 <= VAR24[15:8];
else if(VAR39 == 6)
VAR33 <= VAR24[23:16];
else if(VAR39 == 7)
VAR33 <= VAR24[31:24];
else
VAR33 <= 8'b0;
end
end
always @(posedge VAR14)
begin
if (VAR39 == 4 && VAR9)
VAR24 <= VAR29;
end
wire VAR30;
wire [31:0] VAR44;
wire VAR8;
assign VAR2 = !VAR8;
localparam VAR45 = VAR10(VAR43);
VAR18 #(
.VAR17(32),
.VAR43(VAR43)
) VAR32 (
.clk(VAR14),
.reset(VAR27),
.write(!VAR23 || VAR40),
.read(VAR38),
.VAR3(VAR40 ? VAR15 : VAR13),
.VAR7(VAR8),
.VAR20(VAR30),
.VAR11(VAR44[31:0]),
.VAR19(VAR12[VAR45-1:0])
);
assign VAR12[31:VAR45] = 0;
always @(posedge VAR14)
VAR5 <= VAR44;
assign VAR34 = !VAR30;
assign VAR21 = VAR8;
assign VAR4 = (VAR26 != 0);
always @(posedge VAR14) begin
if(VAR27)
VAR26 <= 0;
end
else if(VAR30 && VAR38 && VAR26 != 8'hff)
VAR26 <= VAR26 +1;
end
always @(posedge VAR14) begin
if(VAR27)
VAR16 <= 1'b0;
end
else if (((((VAR42+1)*VAR43)>>8) <= VAR12) || (VAR42 == 8'b0 && VAR12 >= 0))
VAR16 <= 1'b1;
else if (((((VAR22+1)*VAR43)>>8) >= VAR12 && VAR22 != 8'b0) || VAR12 == 0)
VAR16 <= 1'b0;
end
endmodule | bsd-3-clause |
asicguy/gplgpu | hdl/de_temp/der_top.v | 18,280 | module MODULE1
(
input VAR63, input VAR99, input VAR141, input VAR40, input [31:0] VAR3, input [8:2] VAR59, input [8:2] VAR23, input VAR33, input [3:0] VAR100, input VAR125, input [15:0] VAR37, input [53:0] VAR84, input [4:0] VAR90, input VAR54, input VAR105, input VAR50, input VAR121, input VAR81, input VAR144, input VAR31, input VAR86, input VAR29,
output VAR143, output VAR7, output VAR22, output VAR148, output VAR132, output VAR118, output VAR107, output VAR91,
output VAR146, output [11:0] VAR62, output [1:0] VAR8, output [27:0] VAR57, output [27:0] VAR34, output [31:0] VAR135, output [31:0] VAR69, output [11:0] VAR112, output [11:0] VAR25, output [3:0] VAR111, output [3:0] VAR35, output [3:0] VAR12, output [3:0] VAR18, output [4:0] VAR76, output VAR16, output VAR58, output VAR120, output VAR92, output [1:0] VAR83, output [2:0] hdf1, output [2:0] VAR82, output [31:0] VAR138, output [31:0] VAR109, output [31:0] VAR124, output [15:0] VAR88,
output [31:0] VAR48,
output [31:0] VAR130,
output [3:0] VAR36, output [23:0] VAR117, output [159:0] VAR97, output [15:0] VAR60, output [17:0] VAR73,
output [31:0] VAR51, output VAR137, output VAR77, output VAR2, output VAR38, output VAR139, output VAR89,
output [1:0] VAR108,
output interrupt,
output [6:0] VAR115, output [3:0] VAR145, output VAR104,
output VAR47
);
wire [1:0] VAR53;
wire [1:0] VAR114;
wire [13:0] VAR21;
wire [31:0] VAR15;
wire [31:0] VAR72;
wire [11:0] VAR13;
wire [11:0] VAR85;
wire [4:0] VAR64;
wire VAR80;
wire [1:0] VAR74;
wire [2:0] VAR147;
wire [31:0] VAR20;
wire [31:0] VAR140;
wire [3:0] VAR14;
wire [23:0] VAR96;
wire [31:0] VAR87;
wire [31:0] VAR78;
wire [31:0] VAR126;
wire [31:0] VAR93;
wire [31:0] VAR61;
wire [15:0] VAR10;
wire [17:0] VAR129;
wire [31:0] VAR45;
wire [31:0] VAR106;
wire VAR131;
wire VAR43;
wire VAR103;
wire [1:0] VAR94;
wire VAR102;
wire VAR71;
wire VAR11;
wire [3:0] VAR46;
VAR66 VAR128
(
.VAR63 (VAR63),
.VAR99 (VAR99),
.VAR141 (VAR141),
.VAR40 (VAR40),
.VAR3 (VAR3),
.VAR59 (VAR59),
.VAR33 (VAR33),
.VAR100 (VAR100),
.VAR125 (VAR125),
.VAR11 (VAR11),
.VAR105 (VAR105),
.VAR50 (VAR50),
.VAR1 (VAR1),
.VAR53 (VAR53),
.VAR114 (VAR114),
.VAR21 ({VAR131,VAR21}),
.VAR15 (VAR15),
.VAR72 (VAR72),
.VAR13 (VAR13),
.VAR85 (VAR85),
.VAR111 (VAR111),
.VAR12 (VAR12),
.VAR64 (VAR64),
.VAR4 ({VAR102,VAR80,VAR74}),
.hdf1 (hdf1),
.VAR147 (VAR147),
.VAR20 (VAR20),
.VAR140 (VAR140),
.VAR14 (VAR14),
.VAR96 (VAR96),
.VAR124 (VAR124),
.VAR88 (VAR88),
.VAR48 (VAR48),
.VAR130 (VAR130),
.VAR87 (VAR87),
.VAR78 (VAR78),
.VAR126 (VAR126),
.VAR93 (VAR93),
.VAR61 (VAR61),
.VAR10 (VAR10),
.VAR129 (VAR129),
.VAR71 (VAR71),
.VAR137 (VAR137),
.VAR77 (VAR77),
.VAR89 (VAR89),
.VAR94 (VAR94),
.interrupt (interrupt),
.VAR116 (VAR115),
.VAR127 (VAR145)
);
wire [13:0] VAR6;
wire [31:0] VAR24;
wire [31:0] VAR39;
wire [31:0] VAR44;
wire [31:0] VAR119;
wire [11:0] VAR110;
wire [11:0] VAR98;
wire [4:0] VAR55;
wire VAR26;
wire [1:0] VAR67;
wire [2:0] VAR27;
wire [31:0] VAR28;
wire [31:0] VAR56;
wire [3:0] VAR49;
wire [23:0] VAR9;
wire [31:0] VAR68;
wire [31:0] VAR134;
wire [31:0] VAR30;
wire [31:0] VAR142;
wire [31:0] VAR41;
wire [15:0] VAR17;
wire [17:0] VAR52;
wire [1:0] VAR32;
wire [3:0] VAR65;
assign VAR16 = VAR55[0];
assign VAR146 = VAR6[11];
assign VAR8 = VAR6[8:7];
assign VAR97 = {VAR68,VAR134,VAR30,VAR142,VAR41};
VAR122 VAR113
(
.VAR63 (VAR63),
.VAR99 (VAR99),
.VAR104 (VAR104),
.VAR21 ({VAR21[13:12], VAR21[10:0]}),
.VAR15 (VAR15),
.VAR72 (VAR72),
.VAR13 (VAR13),
.VAR85 (VAR85),
.VAR12 (VAR12),
.VAR64 (VAR64),
.VAR80 (VAR80),
.VAR74 (VAR74),
.VAR147 (VAR147),
.VAR20 (VAR20),
.VAR140 (VAR140),
.VAR14 (VAR14),
.VAR96 (VAR96),
.VAR10 (VAR10),
.VAR129 (VAR129),
.VAR94 (VAR94),
.VAR111 (VAR111),
.VAR87 (VAR87),
.VAR78 (VAR78),
.VAR126 (VAR126),
.VAR93 (VAR93),
.VAR61 (VAR61),
.VAR6 ({VAR103,VAR6}),
.VAR24 (VAR24),
.VAR39 (VAR39),
.VAR110 (VAR110),
.VAR98 (VAR98),
.VAR65 (VAR65),
.VAR55 (VAR55),
.VAR26 (VAR26),
.VAR67 (VAR67),
.VAR27 (VAR27),
.VAR28 (VAR28),
.VAR56 (VAR56),
.VAR49 (VAR49),
.VAR9 (VAR9),
.VAR17 (VAR17),
.VAR52 (VAR52),
.VAR32 (VAR32),
.VAR35 (VAR35),
.VAR68 (VAR68),
.VAR134 (VAR134),
.VAR30 (VAR30),
.VAR142 (VAR142),
.VAR41 (VAR41)
);
VAR95 VAR19
(
.VAR63 (VAR63),
.VAR99 (VAR99),
.VAR91 (VAR91),
.VAR107 (VAR107),
.VAR21 ({1'b0, VAR6[12], VAR6[10:0]}),
.VAR15 (VAR24),
.VAR72 (VAR39),
.VAR13 (VAR110),
.VAR85 (VAR98),
.VAR12 (VAR65),
.VAR111 (VAR35),
.VAR64 (VAR55),
.VAR80 (VAR26),
.VAR74 (VAR67),
.VAR147 (VAR27),
.VAR20 (VAR28),
.VAR140 (VAR56),
.VAR14 (VAR49),
.VAR96 (VAR9),
.VAR10 (VAR17),
.VAR129 (VAR52),
.VAR94 (VAR32),
assign VAR16 = VAR64[0];
assign VAR146 = VAR21[11];
assign VAR8 = VAR21[8:7];
assign VAR97 = {VAR87,VAR78,VAR126,VAR93,VAR61};
VAR95 VAR19
(
.VAR63 (VAR63),
.VAR99 (VAR99),
.VAR91 (VAR91),
.VAR107 (VAR107),
.VAR21 ({VAR21[13:12], VAR21[10:0]}),
.VAR15 (VAR15),
.VAR72 (VAR72),
.VAR13 (VAR13),
.VAR85 (VAR85),
.VAR12 (VAR12),
.VAR111 (VAR111),
.VAR64 (VAR64),
.VAR80 (VAR80),
.VAR74 (VAR74),
.VAR147 (VAR147),
.VAR20 (VAR20),
.VAR140 (VAR140),
.VAR14 (VAR14),
.VAR96 (VAR96),
.VAR10 (VAR10),
.VAR129 (VAR129),
.VAR94 (VAR94),
.VAR62 ({VAR103,VAR62}),
.VAR57 (VAR45),
.VAR34 (VAR106),
.VAR112 (VAR112),
.VAR25 (VAR25),
.VAR18 (VAR18),
.VAR76 (VAR76),
.VAR120 (VAR120),
.VAR83 (VAR83),
.VAR82 (VAR82),
.VAR138 (VAR138),
.VAR109 (VAR109),
.VAR36 (VAR36),
.VAR117 (VAR117),
.VAR60 (VAR60),
.VAR73 (VAR73),
.VAR108 (VAR108),
.VAR46 (VAR46)
);
VAR149 VAR133
(
.VAR5 (VAR23),
.VAR53 (VAR53),
.VAR114 (VAR114),
.VAR90 (VAR90),
.VAR42 (VAR54),
.VAR21 ({VAR43,VAR21}),
.VAR15 (VAR15),
.VAR72 (VAR72),
.VAR13 (VAR13),
.VAR85 (VAR85),
.VAR111 (VAR111),
.VAR12 (VAR12),
.VAR64 (VAR64),
.VAR4 ({VAR102,VAR80,VAR74}),
.hdf1 (hdf1),
.VAR147 (VAR147),
.VAR20 (VAR20),
.VAR140 (VAR140),
.VAR14 (VAR14),
.VAR96 (VAR96),
.VAR124 (VAR124),
.VAR88 (VAR88),
.VAR48 (VAR48),
.VAR130 (VAR130),
.VAR87 (VAR87),
.VAR78 (VAR78),
.VAR126 (VAR126),
.VAR93 (VAR93),
.VAR61 (VAR61),
.VAR10 (VAR10),
.VAR129 (VAR129),
.VAR37 (VAR37),
.VAR84 (VAR84),
.VAR94 (VAR94),
.VAR116 (VAR115),
.VAR127 (VAR145),
.VAR51 (VAR51)
);
VAR75 VAR123
(
.VAR63 (VAR63),
.VAR141 (VAR141),
.VAR102 (VAR102),
.VAR131 (VAR131),
.VAR136 (VAR62[10:9]),
.VAR103 (VAR103),
.VAR45 (VAR45),
.VAR106 (VAR106),
.VAR74 (VAR74),
.VAR79 (VAR62[4]),
.VAR58 (VAR58),
.VAR43 (VAR43),
.VAR2 (VAR2),
.VAR38 (VAR38),
.VAR139 (VAR139),
.VAR135 (VAR135),
.VAR69 (VAR69),
.VAR57 (VAR57),
.VAR34 (VAR34),
.VAR92 (VAR92)
);
VAR70 VAR101
(
.VAR63 (VAR63),
.VAR99 (VAR99),
.VAR1 (VAR1),
.VAR71 (VAR71),
.VAR121 (VAR121),
.VAR81 (VAR81),
.VAR144 (VAR144),
.VAR111 (VAR111),
.VAR35 (VAR35),
.VAR46 (VAR46),
.VAR31 (VAR31),
.VAR86 (VAR86),
.VAR29 (VAR29),
.VAR132 (VAR132),
.VAR104 (VAR104), .VAR91 (VAR91), .VAR118 (VAR118), .VAR143 (VAR143),
.VAR7 (VAR7),
.VAR22 (VAR22),
.VAR148 (VAR148),
.VAR11 (VAR11),
.VAR107 (VAR107),
.VAR47 (VAR47)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn.behavioral.pp.v | 3,017 | module MODULE1 (
VAR29 ,
VAR6 ,
VAR13 ,
VAR21 ,
VAR26 ,
VAR19,
VAR30 ,
VAR16 ,
VAR17 ,
VAR20
);
output VAR29 ;
input VAR6 ;
input VAR13 ;
input VAR21 ;
input VAR26 ;
input VAR19;
input VAR30 ;
input VAR16 ;
input VAR17 ;
input VAR20 ;
wire VAR2 ;
wire VAR31 ;
wire VAR24 ;
wire VAR18 ;
reg VAR9 ;
wire VAR15 ;
wire VAR4 ;
wire VAR12 ;
wire VAR25;
wire VAR11 ;
wire VAR7 ;
wire VAR8 ;
wire VAR10 ;
wire VAR1 ;
wire VAR28 ;
wire VAR14 ;
not VAR33 (VAR31 , VAR25 );
not VAR32 (VAR24 , VAR11 );
VAR5 VAR23 (VAR18, VAR15, VAR4, VAR12 );
VAR3 VAR27 (VAR2 , VAR18, VAR24, VAR31, VAR9, VAR30, VAR16);
assign VAR7 = ( VAR30 === 1'b1 );
assign VAR8 = ( VAR7 && ( VAR25 === 1'b1 ) );
assign VAR10 = ( ( VAR12 === 1'b0 ) && VAR8 );
assign VAR1 = ( ( VAR12 === 1'b1 ) && VAR8 );
assign VAR28 = ( ( VAR15 !== VAR4 ) && VAR8 );
assign VAR14 = ( VAR7 && ( VAR19 === 1'b1 ) );
buf VAR22 (VAR29 , VAR2 );
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | viterbi/pipe2.v | 6,994 | module MODULE1 (in,out,VAR5,reset);
output [1:0] out;
input [1:0] in; input VAR5; input reset;
reg [1:0] out;
reg [1:0] o1; reg [1:0] o2; reg [1:0] o3; reg [1:0] o4; reg [1:0] o5; reg [1:0] o6; reg [1:0] o7; reg [1:0] VAR7; reg [1:0] VAR2; reg [1:0] o10; reg [1:0] o11; reg [1:0] o12; reg [1:0] o13; reg [1:0] o14;
reg [1:0] o15; reg [1:0] o16; reg [1:0] o17; reg [1:0] VAR6; reg [1:0] VAR3; reg [1:0] o20; reg [1:0] o21; reg [1:0] o22; reg [1:0] o23; reg [1:0] o24; reg [1:0] o25; reg [1:0] o26; reg [1:0] o27; reg [1:0] VAR4; reg [1:0] VAR1; reg [1:0] o30; reg [1:0] o31;
always @(posedge VAR5)
begin
if(reset)
o1 = 2'd0;
end
else
o1 = in;
end
always @(posedge VAR5)
begin
if(reset)
o2 = 2'd0;
end
else
o2 = o1;
end
always @(posedge VAR5)
begin
if(reset)
o3 = 2'd0;
end
else
o3 = o2;
end
always @(posedge VAR5)
begin
if(reset)
o4 = 2'd0;
end
else
o4 = o3;
end
always @(posedge VAR5)
begin
if(reset)
o5 = 2'd0;
end
else
o5 = o4;
end
always @(posedge VAR5)
begin
if(reset)
o6 = 2'd0;
end
else
o6 = o5;
end
always @(posedge VAR5)
begin
if(reset)
o7 = 2'd0;
end
else
o7 = o6;
end
always @(posedge VAR5)
begin
if(reset)
VAR7 = 2'd0;
end
else
VAR7 = o7;
end
always @(posedge VAR5)
begin
if(reset)
VAR2 = 2'd0;
end
else
VAR2 = VAR7;
end
always @(posedge VAR5)
begin
if(reset)
o10 = 2'd0;
end
else
o10 = VAR2;
end
always @(posedge VAR5)
begin
if(reset)
o11 = 2'd0;
end
else
o11 = o10;
end
always @(posedge VAR5)
begin
if(reset)
o12 = 2'd0;
end
else
o12 = o11;
end
always @(posedge VAR5)
begin
if(reset)
o13 = 2'd0;
end
else
o13 = o12;
end
always @(posedge VAR5)
begin
if(reset)
o14 = 2'd0;
end
else
o14 = o13;
end
always @(posedge VAR5)
begin
if(reset)
o15 = 2'd0;
end
else
o15 = o14;
end
always @(posedge VAR5)
begin
if(reset)
o16 = 2'd0;
end
else
o16 = o15;
end
always @(posedge VAR5)
begin
if(reset)
o17 = 2'd0;
end
else
o17 = o16;
end
always @(posedge VAR5)
begin
if(reset)
VAR6 = 2'd0;
end
else
VAR6 = o17;
end
always @(posedge VAR5)
begin
if(reset)
VAR3 = 2'd0;
end
else
VAR3 = VAR6;
end
always @(posedge VAR5)
begin
if(reset)
o20 = 2'd0;
end
else
o20 = VAR3;
end
always @(posedge VAR5)
begin
if(reset)
o21 = 2'd0;
end
else
o21 = o20;
end
always @(posedge VAR5)
begin
if(reset)
o22 = 2'd0;
end
else
o22 = o21;
end
always @(posedge VAR5)
begin
if(reset)
o23 = 2'd0;
end
else
o23 = o22;
end
always @(posedge VAR5)
begin
if(reset)
o24 = 2'd0;
end
else
o24 = o23;
end
always @(posedge VAR5)
begin
if(reset)
o25 = 2'd0;
end
else
o25 = o24;
end
always @(posedge VAR5)
begin
if(reset)
o26 = 2'd0;
end
else
o26 = o25;
end
always @(posedge VAR5)
begin
if(reset)
o27 = 2'd0;
end
else
o27 = o26;
end
always @(posedge VAR5)
begin
if(reset)
VAR4 = 2'd0;
end
else
VAR4 = o27;
end
always @(posedge VAR5)
begin
if(reset)
VAR1 = 2'd0;
end
else
VAR1 = VAR4;
end
always @(posedge VAR5)
begin
if(reset)
o30 = 2'd0;
end
else
o30 = VAR1;
end
always @(posedge VAR5)
begin
if(reset)
o31 = 2'd0;
end
else
o31 = o30;
end
always @(posedge VAR5)
begin
if(reset)
out = 2'd0;
end
else
out = o31;
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3.behavioral.pp.v | 1,819 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR5 ,
VAR14 ,
VAR3,
VAR9,
VAR10 ,
VAR13
);
output VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR14 ;
input VAR3;
input VAR9;
input VAR10 ;
input VAR13 ;
wire VAR12 ;
wire VAR8;
nand VAR2 (VAR12 , VAR5, VAR7, VAR14 );
VAR6 VAR11 (VAR8, VAR12, VAR3, VAR9);
buf VAR1 (VAR4 , VAR8 );
endmodule | apache-2.0 |
valkwarble/finalProject | BWIMAGE/ntsc2zbt.v | 5,770 | module MODULE1(clk, VAR3, VAR5, VAR33, din, VAR14, VAR21, VAR4, VAR9);
input clk; input VAR3; input [2:0] VAR5;
input VAR33;
input [7:0] din;
output [18:0] VAR14;
output [35:0] VAR21;
output VAR4; input VAR9;
parameter VAR19 = 10'd30;
parameter VAR8 = 10'd30;
reg [9:0] VAR25 = 0;
reg [9:0] VAR7 = 0;
reg [7:0] VAR16 = 0;
reg VAR11;
reg VAR17;
reg VAR34; reg VAR30;
wire VAR13 = VAR5[2];
wire VAR27 = VAR13 & ~VAR34;
always @ (posedge VAR3) begin
VAR17 <= VAR33;
VAR11 <= VAR33 && !VAR5[2] & ~VAR17; VAR34 <= VAR13;
VAR30 = VAR27 ? ~VAR30 : VAR30;
if (!VAR5[2])
begin
VAR25 <= VAR5[0] ? VAR19 :
(!VAR5[2] && !VAR5[1] && VAR33 && (VAR25 < 1024)) ? VAR25 + 1 : VAR25;
VAR7 <= VAR5[1] ? VAR8 :
(!VAR5[2] && VAR5[0] && (VAR7 < 768)) ? VAR7 + 1 : VAR7;
VAR16 <= (VAR33 && !VAR5[2]) ? din : VAR16;
end
end
reg [9:0] VAR2[1:0],VAR6[1:0];
reg [7:0] VAR24[1:0];
reg VAR18[1:0];
reg VAR12[1:0];
always @(posedge clk)
begin
{VAR2[1],VAR2[0]} <= {VAR2[0],VAR25};
{VAR6[1],VAR6[0]} <= {VAR6[0],VAR7};
{VAR24[1],VAR24[0]} <= {VAR24[0],VAR16};
{VAR18[1],VAR18[0]} <= {VAR18[0],VAR11};
{VAR12[1],VAR12[0]} <= {VAR12[0],VAR30};
end
reg VAR26;
wire VAR15 = VAR18[1] & ~VAR26;
always @(posedge clk) VAR26 <= VAR18[1];
reg [31:0] VAR23;
always @(posedge clk)
if (VAR15)
VAR23 <= { VAR23[23:0], VAR24[1] };
reg [39:0] VAR32;
reg [39:0] VAR28;
reg [3:0] VAR35;
reg [3:0] VAR29;
always @ (posedge clk)
begin
VAR32 <= {VAR32[29:0], VAR2[1]};
VAR28 <= {VAR28[29:0], VAR6[1]};
VAR35 <= {VAR35[2:0], VAR18[1]};
VAR29 <= {VAR29[2:0], VAR12[1]};
end
wire [8:0] VAR22 = VAR28[38:30];
wire [9:0] VAR10 = VAR32[39:30];
wire [18:0] VAR31 = {1'b0, VAR22[8:0], VAR29[3], VAR10[9:2]};
wire [31:0] VAR1 = {VAR24[1],VAR24[1],VAR24[1],VAR24[1]};
wire [18:0] VAR20 = {1'b0, VAR22[8:0], VAR29[3], VAR10[7:0]};
reg [18:0] VAR14;
reg [35:0] VAR21;
wire VAR4 = VAR9 ? VAR15 : (VAR15 & (VAR32[31:30]==2'b00));
always @(posedge clk)
if ( VAR4 )
begin
VAR14 <= VAR9 ? VAR20 : VAR31; VAR21 <= VAR9 ? {4'b0,VAR1} : {4'b0,VAR23};
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbp/sky130_fd_sc_ls__dlrbp.symbol.v | 1,456 | module MODULE1 (
input VAR3 ,
output VAR5 ,
output VAR1 ,
input VAR6,
input VAR9
);
supply1 VAR4;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
megari/sd2snes | verilog/sd2snes_obc1/mcu_cmd.v | 12,203 | module MODULE1(
input clk,
input VAR43,
input VAR16,
input [7:0] VAR2,
input [7:0] VAR28,
output [2:0] VAR14,
output reg VAR42 = 0,
output VAR45,
output reg VAR52 = 0,
input VAR41,
output [7:0] VAR23,
input [7:0] VAR11,
output [7:0] VAR38,
input [31:0] VAR46,
input [2:0] VAR20,
output [23:0] VAR1,
output [23:0] VAR48,
output [23:0] VAR10,
output VAR47,
input VAR5,
input VAR3,
input [7:0] VAR21,
input VAR37,
output [1:0] VAR26,
output VAR9,
output [10:0] VAR53,
output [10:0] VAR15,
output reg VAR56,
output reg VAR22,
output [10:0] VAR7,
input VAR31,
output reg VAR40 = 0,
output reg VAR30 = 0,
output reg [2:0] VAR24 = 3'b000,
output reg VAR34 = 0,
output reg [8:0] VAR8 = 0,
output [13:0] VAR49,
input [7:0] VAR4,
output [5:0] VAR51,
output [5:0] VAR19,
output VAR54,
input [31:0] VAR29,
input [15:0] VAR17,
input [7:0] VAR6,
output [13:0] VAR25,
output VAR12,
output reg [7:0] VAR35,
output reg VAR50,
input VAR18,
input [7:0] VAR39,
output reg [7:0] VAR55,
output reg [8:0] VAR44,
output reg VAR27,
output reg [7:0] VAR36,
output reg [31:0] VAR33,
output reg VAR32,
output VAR13
); | gpl-2.0 |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/configuration.v | 4,066 | module MODULE1(
input [31:0] VAR10,
input [31:0] VAR11,
input VAR18,
input VAR1,
output reg VAR14,
output reg [31:0]VAR19,
input clk,
input reset,
output reg VAR15
);
reg [2:0]VAR7,VAR17;
localparam VAR6=0,
VAR5=1;
always@(posedge clk)
if(reset)
VAR7<=0;
else VAR7<=VAR17;
always@
if(reset)
VAR14=0;
else if(VAR7==VAR5)
VAR14=1;
else VAR14=0;
always@(posedge clk)
if(reset)
VAR15<=0;
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR3} && VAR1==0)
VAR15<=VAR10[0];
begin
always@
if(reset)
VAR19=0;
end
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR3} && VAR1)
VAR19=VAR15;
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR16} && VAR1)
VAR19=30;
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR9} && VAR1)
VAR19=VAR8;
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR2} && VAR1)
VAR19=VAR13;
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR4} && VAR1)
VAR19=VAR12;
else VAR19=32'hdeadbeef;
end
begin
always@(*)
if(reset)
VAR19=0;
end
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR3} && VAR1)
VAR19=VAR15;
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR16} && VAR1)
VAR19=45;
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR9} && VAR1)
VAR19=VAR8;
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR2} && VAR1)
VAR19=VAR13;
else if(VAR7==VAR5 && VAR11[23:0]=={16'h0,VAR4} && VAR1)
VAR19=VAR12;
else VAR19=32'hdeadbeef;
end
endmodule | lgpl-2.1 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Add-Subt/FPU_Add_Subtract_Function.v | 12,640 | module MODULE1
parameter VAR7=26, parameter VAR31 = 5)
wire [VAR7-1:0] VAR8;
assign VAR8 = ~VAR14;
VAR34 #(.VAR7(VAR7),.VAR31(VAR31)) VAR17 (
.clk(clk),
.rst(VAR15),
.VAR20(VAR5),
.VAR33(VAR8),
.VAR3(VAR32)
);
VAR37 VAR1(
.clk(clk),
.VAR9(VAR27[1:0]),
.VAR2(VAR4),
.VAR16(VAR19),
.VAR28(VAR35)
);
VAR26 #(.VAR24(VAR24),.VAR30(VAR30),.VAR36(VAR36)) VAR21(
.clk(clk),
.rst(VAR15),
.VAR20(VAR38),
.VAR23(VAR12),
.VAR22(VAR29),
.VAR25(VAR19),
.VAR18(VAR10),
.VAR11(VAR27[VAR7-2:2]),
.VAR6(VAR13)
);
endmodule | gpl-3.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.