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H: Output state of the AM26LS32AIDR
We are using AM26LS32AIDR in our design, as per the datasheet when input is open/floating, output should be high, but the output is in low state.
We are unable to trace out the issue.
We followed the schematic as below.
Edit:-
We are using this chip for controlling active low device. Default state should be high in order to disable the device.
AI: Since the input is terminated with 100 ohms resistance, the difference between input pins is in the order of 2.5 mV due to internal pull-up and pull-down resistors in the chip. Both inputs will have about 2.5V of common mode voltage.
The voltage is not high enough to cross the hysteresis threshold to neither positive or negative direction, so output will be whatever it previously was, or rather, undefined after powering the chip up.
Even the datasheet table 1 confirms this, if voltage is between high and low thresholds, output is indeterminate.
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H: How do I ground my chassis?
I'm working on a project with 90 solenoids mounted on a metal plate (see A below). Each solenoid could draw 2 Amps, however I will only be using 20 at max at a time.
I can switch between using a wired (to socket) power supply (B) and a battery (D) if a socket is not available.
(C) Is earth. Which won't be used when using battery.
My question: Do I need to ground the metal plate? If so, do I need to connect it to point C or B/D.
Note: B and D are connected.
I would connect it to point B/D, but I am afraid that the high currents might mess with this.
AI: If you have potentially lethal voltage (you do) and the equipment is not double insulated you must ground any exposed metalwork. This protective ground should be to the earth connection of the incoming mains.
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H: What is the formula or any method to calculate the value of the output capacitor and inductor in a buck converter
I have using a buck converter whose output is 5V and 1A.
Can someone tell me whether these is any formula to calculate the value of the output capacitor? Like, without involving the switching frequency or any other value.
I have gone through the app notes of various manufacturers. But there are giving some formulas related to the switching frequency.
But whether I can arrive at the formula of the output capacitor without any formula involving the switching frequency?
AI: But whether I can arrive at the formula of the output capacitor
without any formula involving the switching frequency?
The minimum value of output capacitance is based on the amount of ripple voltage; more capacitance means lower ripple voltage; higher switching frequency (same capacitance) also means lower ripple voltage.
The ripple voltage is directly related to the switching frequency so no, I would say you need to know the switching frequency to predict the ripple voltage based on values for the inductor and capacitor.
The inductor and capacitor form a low-pass filter and, that low-pass filter frequency has to be significantly lower than the switching frequency or you'll get large ripple artefacts. All normal (commonly used) buck converters are designed to reduce ripple significantly.
Hence, both the inductor's value and the capacitors value AND the switching frequency dictate ripple voltage on the output. Imagine an LC low pass filter and you apply a square wave to the input; if the cut-off frequency is significantly lower than the fundamental frequency of the square wave (aka the waveform from the switching transistor) then the output ripple is low.
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H: Soldering wire directly to a PCB through hole vias, what is acceptable proximity tolerance?
The wire gauge is 16 AWG. The hole size is 63 mil, and the overall via diameter is 98.5 mil.
What is the minimum spacing between two of these for voltage levels of 0-12V and 0-160V circuits?
I think I can get away with 150 mils between centers and solder wires ok and bend the wires ok as well.
AI: This is a table from IPC-2221A but it's not the latest version: -
You should aim to check the latest version and apply suitable extra dimensioning to be more secure. For more information on IPC see this wiki page.
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H: Are there any digital walkie talkies or radios with CPUs on them?
That's it! Are there any modern radios (not smartphones. More like walkie talkies or ham sets or those used in cars) that contain CPUs on them and somehow interact with the analog radio signals?
AI: 25-years ago, Motorola has made little walk-in-talkies that could be paired with another similar unit so you could avoid hearing other over the air traffic and others could not hear your traffic. Their claim was some type of encryption and signal processing so, I can't imagine anything was done without a microcontroller.
They are still available...
https://www.motorolasolutions.com/en_us/products/two-way-radios/consumer-two-way-radios.html
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H: What on a digital PCB could affect the boost converter output?
I have designed a fixed 12 volt boost converter module and it works.
I tried to implement the same booster on my project PCB, but with all same components it can't provide 12 volts when it gets any load at output. I tried to bypass the onboard boost converter and attached the module I designed (same mentioned first) and it works with load too.
All the components as well as trace's width seem to be capable of handling the load. I tried to find what is different but I could not see anything.
Now the only thing left is isolation. Is it possible that some traces in my PCB can cause problem here? All boost converter components are on top layer but on bottom layer there is dome switch mounted on the PCB and another power grid along with data lines. The inductor I used is not shielded.
The schematic and PCB for the boost converter part is below. I used an MT3608 IC, the capacitor on input output is 22uF.
Inductor part number CD54NP-330LC
AI: Here is a fragment from the datasheet you should have followed. As you can see, your PCB looks like someone was intentionally using every single recommendation backwards. Especially that pin 1 trace is outrageous. I suggest throwing your existing design out and starting from scratch.
One piece of advice that might help - don't rush to place components and start tracing. First, rotate and move components around to minimize rat's nest length as much as possible, and to reduce intersections - all the while keeping in mind specific requirements for important traces.
Note that while the layout suggested in the datasheet follows most of the rules, it is far from optimal. By placing components closer and with a bit of rotation here and there most of the traces can be shortened at least in half. The capacitors should be moved closer to the regulator pins (rules #1 and #3) and thermal VIAs added to GND (rule #2). Here is an example of such a rearrangement:
Another piece of advice, specific for power applications, is to keep in mind that CAD systems limit maximum possible trace width by local pin clearances. So, after making all required connections you have to supplement them with copper zones for current capacity and thermal dissipation. Alternatively, you can make all connections with copper zones only, making sure you switch their thermal clearance off.
Finally, as @Andyaka pointed out, the inductor you've used is not suitable. Again, it's as if somebody took the datasheet and did the opposite of what was written there.
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H: Inrush current when n-channel MOSFET turns off
We are using a FDN028N20 n-channel MOSFET for load switching. Load current is 80mA max. and it is controlled via processor's 3.3V pin (NRF52832).
Our schematic:
When the MOSFET turns off, I measure 6mA current peaks flowing into the processor pin. We make the measurement using a Power Profiler Kit II. This is expected since the gate behaves as a capacitor, and discharges.
You can see the peak in the screenshot below:
Sometimes these peaks may reach higher values (e.g. 15-20mA). It is said that overall current going in/coming from the pin shouldn't be above ~20mA. (https://devzone.nordicsemi.com/f/nordic-q-a/15800/gpio-sink-current-on-nrf52832/60290#60290).
That's why I am worried that in this design pins may be damaged in the future. I tried to reduce the peak current using a gate resistor, but surprisingly the peaks increased in frequency and sometimes even in amplitude (we tried various gate resistors - 100Ω, 1000Ω, etc).
Can someone please explain to me why the gate resistor doesn't reduce amplitude of peaks and how to protect the processor pin?
Note: I tried the same with other loads and observed the same behavior. This question is not about driving a motor with PWM, but a general problem we observe on other loads too (LEDs etc.).
Edit:
I made the same test with another load (resistor). See the circuit below:
As you can see there is no motor here, and I suppose there shouldn't be any EMF related issues here with a resistor as a load.
The processor switches its output state every 5 seconds (5 seconds high, 5 seconds low) infinitely.
You can see the measured current below:
As you can see, these peaks happen all the time. I tried removing the gate resistor, and had the same result.
AI: The peak you see is not actual current, it is an artifact of your measuring set-up, either due to a ground loop or due to radiation. To prove it, run the measurement again, but with no input. For example, if you are using a scope probe, connect the tip to the ground clip instead. Theoretically, it should read perfectly 0 V. If it reads that same 6 mA, then you know that the problem is an artifact of the measuring method, not actual current.
Now, as far as the original cause, the problem is that you need a way for the load current to go somewhere else when the MOSFET is turned off. You can do that with a diode across the load, with an RC snubber, or with a TVS diode across the MOSFET. Otherwise, you get an inductive kickback that radiates and is being picked up by your test equipment.
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H: Braking a brushed DC motor with a flyback diode
I've seen many references to braking a brushed DC motor by shorting its terminals. As I understand it, the motor torque is relative to the current through it, which should dissipate relative to its inductive time constant. Shorting the terminals should allow the current to dissipate at the fastest rate. I also understand that back EMF should assist in braking.
Many brushed DC motor designs include a flyback diode by default. I typically see Schottky diodes recommended. That would allow current to circulate similar to connecting the terminals, and would clamp the motor voltage to ~300mV or less (and also in the same direction as the back EMF.)
Is there really any significant difference between shorting the terminals and allowing current just to circulate through the diode? I feel like I'm missing something, either in my understanding of the circuit or brushed motor fundamentals.
I'm specifically referring to relatively small motors driven by PWMing a low-side transistor (such as shown in this question,) though it may also be relevant in other cases. I realize there are applications that require other forms of active breaking, but I'm specifically interested in the marginal effect of shorting the terminals over the flyback diode.
AI: If you disconnect power from a brushed DC motor, no current from the motor would flow through the flyback diode, because it would still be reverse biased. Therefore there would be no braking effect.
The motor would have to rotate in the opposite direction for current to flow through the flyback diode.
The positive terminal of a motor remains the positive terminal when operated as a generator if it is spinning in the same direction.
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H: Schematics Standard for Space between Value and Unit
On electrical schematics, is there a standard for whether there is a space between the numerical value and unit symbol? I can find standards that require it in general writing, but none that specifically address it for electrical schematics. Sometimes space is at a premium, e.g. 5A might fit within a circuit breaker symbol where 15 A would not, so that's the reason I could see that spaces are not required in schematics.
NIST succinctly summarizes the requirement for writing, which comes from section 7.2 of the NIST Guide for the Use of the International System of Units (SI) states
There is a space between the numerical value and unit symbol...
The International System of Units (SI) prescribes in section 5.4.3:
The numerical value always precedes the unit and a space is always used to separate the unit from the number.
ISO 1219-2:2012 for pneumatic/hydraulic schematics uses a space in almost all their examples, but page 39 does also show 0.03cm³/stroke without spaces.
I have access to and checked UL 489 (Apr 22, 2019) and UL 508A (Apr 24, 2018), but they do not address units directly and do not have example schematics, either.
Edit: And our own Electrical Engineering Stack Exchange Rules and guidelines for drawing good schematics also omit spaces, but those examples are for PCBs rather than electrical panels which is what I'm looking at.
AI: ANSI/IEEE Std 280-1995, "IEEE Standard Letter Symbols for Quantities Used", chapter 3.4 states
In the complete expression for a quantity, a space should be allowed
between the numerical value and the unit symbol.
They use should which means it is encouraged, but not necessary. In their example, you should write 35 mm, not 35mm.
The rules I go by:
In schematics, I omit spaces between number and unit to save space. I
figure schematics don't need to be grammatically correct. I adhere to
symbols and and reference designation letters put forth in IEEE Std 315.
When writing reports, I put a space between the number and unit, adhering to the recommendation in Std 280, chapter 3.4.
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H: With enough copper wire, can I attach one end to one side of a 9V battery, then circle the earth and connect it back?
This is a dead serious question I have not been able to find an answer to: if I had enough wire, could I make electricity pass through if I connected one end to a small 9V battery and then circled the earth and put the other end to the other side of the battery?
If not, how do you calculate how long a current can travel before it's "lost"?
AI: It is never lost: for every electron that leaves the negative terminal and enters one end of the wire, another electron will exit the other end of the wire and enter the positive terminal. Instantaneously! The length of the wire is irrelevant. Why instantaneously? Because the battery is so small, its distance within it (with respect to the speed of light) is practically 0.
When you initially connect the battery, it doesn't see the resistance of the wire (as other have calculated), it sees the capacitance of the two nearby ends of the wire with respect the earth ground. The first electron to leave the negative terminal of the battery goes into that capacitance. And the capacitance of the other end of the wire is what provides the electron that enters the positive terminal. That's why it's instantaneous - it doesn't have to wait for the current to travel along the wire.
Indeed, for the first 0.1 second or so, it makes no difference whether the wire is complete or is broken at the far end of the earth! Only after about 200 ms (the time that it takes to go around the Earth at close to the speed of light) would the current either continue (if the wire is complete) or stop (if the wire is broken at the far end of the Earth).
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H: How important is it for a device (laptop) to identify wattage of a charger?
I have several "old" Thinkpads. Recently I came across that Type-C PD mod to replace charge port with Type-C one. Description said:
Please pay attention what you order because normally your laptop
identifies the charger by an ID pin.
Also mentioned video explains some details of making that mode and pays attention to ID pin proper resistance "simulation".
I wondered before what that pin in the middle of a plug was for.
I've fixed several of my old chargers worn plugs with plugs from aliexpress, I've found they have only two wires so I soldered them, no extra wire for ID pin - and they work fine charging my old Thinkpads, chargers differ by wattage only, volts are same for them as far as I saw. What does that pin really add for laptops charging? Why chargers work w/out it when video explained its importance?
Added 1:
I've tried to measure resistance with multimeter as explained in the video (ground to pin). For 65w with original round (older) plug it: ~10 kOhm (video claimed for 65w resistance is ~ 286 Ohm, I was surprised - hypothesis is that video was about newer square one), for 45w newer square one ~110 Ohm, for 90w round to my surprise nothing (broken wire?). For power supply extended with aliexplress cord/plug resistance was infinite - my guess pin in the plug is just not connected to anything. Also I have round-to-square adapter - separated it measured ~ 550 Ohm - that could mean it has resistor and by comparing with other square ones: video ~286 for 65w, ~110 of 45w mine, I guess 550 Ohm supposed to signal high power available (not safe?).
AI: While people often call laptop power bricks "chargers", they are really just power supplies. The actual power management and charge control circuitry is inside the laptop itself.
To operate correctly the charge controller needs to know how much current it can safely draw from the power supply. If the charge controller thinks the power supply is smaller than it really is then charging will be slower than expected as much of the power brick's capacity is left unutilized.
If the charge controller thinks the power supply is larger than it really is then the charge controller will try to draw more current than the power supply can safely supply. What happens next depends on the design of the power supply, it might shut down on overload protection, it might get hotter than it should reducing it's lifetime, it might lower it's output voltage and therefore crudely limit the charge current (especially if the battery voltage is already near the top end of it's range) it might burn itself up.
As to the connectors you bought from Aliexpress it's difficult to comment without having one on the bench and making measurements, but my guess is that the connectors incorporate a fixed resistor, probably coded to claim to be one of the smaller power supplies.
Update:
Thinkwiki has a page describing Thinkpad power connectors. The page describes a whole bunch of connectors, most of which are either very old or used only on a handful of thinkpads.
There are two thinkpad power connectors* you are likely to encounter on machines still in use today. The "big barrel advanced connector" (round, older) and the "slim tip" (rectangular, newer). The two connector types use different resistor values. Interestingly on the older big barrel connector both open circuit and short circuit are valid codes. I've combined the resistor values for the two connector types in a table below.
Big barrel Slim tip
36W 7.3kΩ
45w 120 Ω
65W 10kΩ 280 Ω
90W Open 550 Ω
135W 0Ω 1 kΩ
170W 1.5kΩ 1.9 kΩ
230W 4.6 kΩ
So it does seem a bit risky that your adapter is coded for 90W when it could be used with a 65W power supply. It seems an official adapter did exist but was fairly rare, so I suspect your adapter was made by some third party.
It's also quite possible that you will never notice problems with an incorrectly coded charger either because the charger crudely limits the current or because the laptop you have in the way that you use it simply doesn't want any more power.
* On more modern thinkpad models you can also use USB C for charging.
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H: Why are 3 wires connected to the potentiometer?
It is a LM2577 boost converter schematic. In page 20 of datasheet: VOUT = 1.23V (1 + R1/R2). Here R1 is the 100k potentiometer, R2 is the 2k resistor.
Why are 3 wires connected to the potentiometer?
Why not just remove the wire in the red circle?
AI: When a three wire potentiometer is connected as a variable resistor it is standard practice to connect the third terminal to the wiper so that if the wiper temporarily disconnects from the track the circuit does not go open. It just goes to the maximum value of the variable resistor.
In the circuit shown the pot value is larger than desirable. To achieve a 12v output the pot setting only needs to be 17.4k because the feedback point is 1.23v. A 20 or 25k pot would be a better choice that would still give 20% over adjustment without being excessive.
With a 20k pot the output would jump to about 13-14V if the pot goes open whereas with a 100k pot it will be tricky to adjust since the setting in the bottom 20% of the adjustment and the output will attempt to go to about 70V if it goes open. Obviously it will not do that and will be limited by the input voltage.
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H: What is the difference between a linear regulator and an LDO
Can someone tell me what the difference between linear regulators and LDOs is?
From what I have read and understood, it is that linear regulators and LDOs don't use switching elements, but I think they are the same basically.
Is there something that I am missing to understand?
AI: They key property of the LDO type linear regulators is the P-type pass transistor. This allows controlling the pass transistor with a voltage below the input voltage \$V_{in}\$ for all possible output voltages. Therefore, the output voltage can in principle be set arbitrarily close to the input voltage, especially for MOSFETs.
Non-LDO type regulators that use N-type transistors have an inevitable dead band of output voltages close to \$V_{in}\$ in that they simply cannot reach, because those high output voltages would require a control voltage on the pass transistor above \$V_{in}\$.
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H: Why is closed loop frequency response hard to determine?
I'm learning about frequency domain control design and one of its advantages is said to be that: one can deduce the closed loop behaviour of a system by (experimental) data on frequency response on the open loop system through Bode/Nyquist plots. This is useful because I am told it is often easy to find frequency response of the open loop system, but not the closed loop system empirically. Why is this so? Can someone explain to me through a real-world example?
My background is in mathematics and I'm trying to learn control theory on my own, so the lack of practical experience makes some aspects of control design rather abstract and arbitrary to me.
Edit: Here is a quote from a book to clarify what I'm confused over: "In the early days of electronic communications, most instruments were judged in terms of their frequency response. It is therefore natural that when the feedback amplifier was introduced, techniques to determine stability in the presence of feedback were based on this response. Suppose the closed-loop transfer function of a system is known. We can determine the stability of a system by simply inspecting the denominator in factored form (because the factors give the system roots directly) to observe whether the real parts are positive or negative. However, the closed-loop transfer function is usually not known; in fact, the whole purpose behind understanding the root locus technique is to be able to find the factors of the denominator in the closed-loop transfer function, given only the open-loop transfer function. Another way to determine closed-loop stability is to evaluate the frequency response of the open-loop transfer function, then perform a test on that response. Note that this method also does not require factoring the denominator of the closed-loop transfer function"
AI: This is useful because I am told it is often easy to find frequency response of the open loop system, but not the closed loop system empirically. Why is this so?
It depends what the closed loop servo system is. If it's something big, expensive or dangerous, you want to be 100% sure that it's not going to go unstable before you 'close the loop'. The classic example I had in my coursework was a servo-controlled aiming loop for a battleship main gun, but it could be a robot manipulator or a nuclear power plant. You can't measure the closed loop emperically because you have to actually close the loop and power it up. If it turns out to be unstable though, then it could damage itself or its mountings.
Even if it's not expensive or dangerous, if it's unstable, then you have nothing to measure. It will be stuck on an endstop, or slamming between the two endstops.
What you do with a system like that is measure the open loop response of each part of the chain, to small and controlled stimulii, then deduce whether it's going to be stable. Adjust the parts until you're sure it will be stable, then close the loop and power up.
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H: How can I do a heatsink calculation and determine whether a heatsink is required or not?
I am designing a DC solid-state relay using an FQP30N06L (a MOSFET with 32 A, 60 V, Rds(on) = 0.035 Ω @Vgs = 10 V) to control using a Raspberry Pi.
I am trying to control an electric door lock with 6-12 V 1200 mA; the nominal resistance at 12 V is 9 Ω. I have seen many articles on the Internet, but all are confusing.
So, as per my specification:
The power dissipated by the MOSFET is P = I2 X R; I is the load current of electric door = 1.2 A; R is the Rds(on) of the MOSFET = 0.035 Ω.
This gives me a power dissipation of P = 1.2 A X 1.2 A X 0.035 Ω = 0.0504 W.
AI: In the datasheet you've linked, there is a table labelled Thermal Characteristics:
The value that is relevant is \$\mathrm{R}_{\Theta\mathrm{JA}}\$ - this is the thermal resistance between the junction (i.e., the active semiconductor region) and the surroundings with no heatsink. You can calculate (to a first approximation) the temperature rise using this value:
\$T_\mathrm{J} = T_\mathrm{A} + \mathrm{R}_{\Theta\mathrm{JA}}\times P\$
where \$T_\mathrm{A}\$ is the ambient temperature and \$P\$ is the power you've calculated. Using these figures, assuming \$T_\mathrm{A} = 25~^\circ \mathrm{C}\$, gives you a temperature of ~\$28~~^\circ \mathrm{C}\$. This means you are unlikely to need a heatsink for this application.
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H: How to add LEDs to a microcontroller's GPIO pins, without affecting the normal pin behaviour?
For educational purposes, I have to design a simple ATtiny24 based development board and add some LEDs to its IO ports for better demonstration of digital inputs or outputs. Despite being educational, I don't want to ignore the MCU's capabilities and limit them just by adding some LEDs. Despite looking very easy, I think it is going to be a little troublesome in some cases like ADC.
The first thing that comes to mind is just a resistor in front of an LED, and the second one, a BJT as low side switch. I'm not sure how it will affect the ADC.
simulate this circuit – Schematic created using CircuitLab
What are the concerns?
The MCU should be able to work at maximum speed (20MHz) and 3.3~5V supply (if possible, according to frequency-power supply limitations indicated in datasheet.)
The MCU should be fine to be programmed with various programmers (Arduino-as-ISP or USBasp) without the need to slow down the clock or other things that students may not be familiar with.
The MCU has an ADC with differential inputs and programmable gain up to 20x. I think the simple methods would affect this but I'm not sure. Using 20x gain with differential inputs may seem out of the book for a student but as said earlier, the board should not be limited. Of course, an error of few millivolts are tolerable and the ADC itself is not that precise either.
LED's are 0805 red SMD chips with 1.8V Vf and 5~10mA If. The brightness is not a concern.
AI: Just use a any suitable logic chip to buffer the signals to LEDs. For compatibility with the voltage range, CMOS type should be used. It does not matter if it is a buffer or inverter or AND gate etc.
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H: Should I remove extra unused copper from a power plane in 4 layer PCB?
I am designing 4 layer PCB which has the following stack up structure:
Layer 1 (top layer) signal
Layer 2 (inner layer 1) power plane
Layer 3 (inner layer 2) ground plane
Layer 4 (bottom layer) signal (consists of an RF antenna track)
I have connected all the 5V and 3.8V connections from top/bottom layer to power plane through the through hole vias.
As per the layer stack up, power plane and ground plane both are adjacent to each other and dielectric thickness is 1mm.
Will this create capacitance between PWR and GND planes? Will it create any problems?
Should I remove extra copper from the power plane?
As I have used through hole vias instead of blind vias, there are unused vias (via stubs) in PCB. Can these floating vias cause any problems with the PCB?
AI: Yes, it adds capacitance between power planes. Two conductors separated by an insulator is a capacitor. It will not create any problems, on the contrary, it is a very much desired property to have distributed capacitance between power planes.
Based on 1), definitely not.
It depends what signals will pass through the vias and will the stubs of a via be harmful. For RF and high speed data signals, maybe, for low frequency stuff, unlikely.
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H: Why do stepper motors draw less current at higher speeds?
I have an A4988 and a NEMA17, when I set the current limit to 1.5 A and the motor runs at a low speed of 0.2 RPS I measure the current and effectively it draws 1.5 A.
Now when I run the motor with the same limit current but with a speed higher than 6 RPS, the current drawn by one of the phases drops to about 0.6 A. Why?
AI: Basically because there is no back-EMF when the motor is turning slowly or not at all. Then the current is then only limited by the winding resistance. When increasing the speed, the back-EMF increases so that the current draw gets lower.
Of course, if you load the motor heavily it can draw pretty much as much current at high speed as when going slow.
The same applies to pretty much any electric motor. Only difference from for example a brushed DC-motor is that with the DC-motor the only way to get it to rotate slower without lowering the voltage, is by applying a load.
AC motors can be slowed down by decreasing the frequency, but if you apply full voltage at low speed/frequency, the motor will draw a lot of current.
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H: RC circuit waveforms not lining up on oscilloscope (capacitor starting negative)
I have a lab for a circuits class and in it we are building an RC series circuit with a square wave input. I am using a function generator to produce a square wave at 50Hz, period = 20ms, Amp = 500mV, Offset = 500mV. I am to measure the output voltage across both the resistor and capacitor.
The resistor is 10k-Ohm and the capacitor is 10nF. I know at T = 0 the resistor drops all the voltage and the capacitor drops effectively none, and that over 5 TC the capacitor charges and the current through the resistor lowers. So the graph for the resistor should be a jump to source voltage then taper off to 0V while the capacitor should start at 0V and ramp up to source. However, When I plug in my O-scope, I am getting the resistor behaviour as expected, and the shape of the capacitor waveform is as expected, but starts at -1 V and ramps to 0V. So it looks like on the O-scope that at 5TC neither component is dropping any voltage.
I have read some previous similar questions and applied some of the solutions found there to no avail, such as: I have checked for DC coupling and have verified the circuit is getting the input by using the O-scope to check the function generator output directly, as well as measuring the component voltage with a Fluke.
How do I get the capacitor to show starting at 0V and ramping to 1V?
Here is the input from the function generator:
Here is the output measured by the O-scope:
If I change the condition to falling edge, the waveforms overlap in a behavior mimicking what I anticipated, but goes from 0 to -1V, which I don't understand since the input voltage is never negative (and when changing the function generator input to a rising squarewave, the O-scope waverforms don't change).
AI: I am getting the resistor behaviour as expected, and the shape of the
capacitor waveform is as expected, but starts at -1 V and ramps to 0V.
A different point-of-view...the capacitor starts at 0V before the square-wave edge occurs, rather than -1V. In this state, no current is flowing, since the voltage across the resistor is 0V as measured by the oscilloscope.
So naturally you ask, "where does the -1V transient come from when the square wave switches?". Just before the transient occurs, voltage across the resistor is 0V but the function generator output is at +1V. The capacitor is charged with the difference (it is charged with 1V): its function-generator-end is at +1V, while its resistor-end is at 0V.
Now the square wave edge occurs very fast, and the capacitor's function-generator-end drops from +1V to 0V. The capacitor's charge tries to dump by causing current to flow. This current path includes the 10k resistor, but it also includes the function generator's internal 50 ohm source resistance. Since 10k > 50 ohms, almost all of the 1V change appears across the 10k resistor...if you were to look very closely, you'd see that the resistor voltage drop is actually -0.995V.
From there, the transient exponential rise to 0V proceeds while the capacitor charge dumps out.
simulate this circuit – Schematic created using CircuitLab
How do I get the capacitor to show starting at 0V and ramping to 1V?
OP's waveforms show that the oscilloscope trigger is from channel 1. Channel 2 is connected to function generator output, and should be the trigger source instead of channel 1.
When looking at the transient voltage across the resistor on channel 1, there are two transient directions (one going up, another going down). This is mightily confusing to the trigger slope direction (+/-).
If you trigger from the function generator waveform on channel 2, trigger edge direction is unambiguous, and you should have no trouble triggering on rising edge versus falling edge.
One other point...You might see on close inspection that function generator output is not entirely square-edged. This is caused by the 50-ohm internal resistance. This effect would be more apparent if you used a smaller load resistor than 10k.
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H: Understanding the reasoning behind these power calculations involving voltage and current sources in circuits
I'm currently studying the textbook Fundamentals of Electric Circuits, 7th edition, by Charles Alexander and Matthew Sadiku. Chapter 1.6 Circuit Elements gives the following example and practice problem:
Example 1.7
Calculate the power supplied or absorbed by each element in Fig. 1.15.
Solution:
...
For \$p_4\$, we should note that the voltage is 8 V (positive at the top), the same as the voltage for \$p_3\$ since both the passive element and the dependent source are connected to the same terminals. (Remember that voltage is always measured across an element in a circuit.) Since the current flows out of the positive terminal,
$$p_4 = 8(-0.2I) = 8(-0.2 \times 5) = -8 \ \text{W} \ \ \ \text{Supplied power}$$
Practice Problem 1.7
Compute the power absorbed or supplied by each component of the circuit in Fig. 1.16.
Answer: \$p_1 = -225 \ \text{W}\$, \$p_2 = 90 \ \text{W}\$, \$p_3 = 60 \ \text{W}\$, \$p_4 = 75 \ \text{W}\$.
I'm not totally clear on the reasoning behind the power calculations for element \$p_4\$ of example 1.7 and element \$p_3\$ of practice problem 1.7. My understanding is that, for element \$p_4\$ of example 1.7, we have that \$0.2I = 0.2(-5 \ \text{A})\$ because the current \$I = 5 \ \text{A}\$ is running counter-conventional, from the positive terminal of the \$20 \ \text{V}\$ ideal independent voltage source to its negative terminal. But why is the voltage over \$p_4\$ the \$8 \ \text{V}\$ over element \$p_3\$? Furthermore, for element \$p_3\$ of practice problem 1.7, we see that the current \$I = 25 \ \text{A}\$ is running in the conventional direction, from the negative terminal of the \$2 \ \text{V}\$ ideal independent voltage source to its positive terminal, so we have \$0.12I = 0.12(25 \ \text{A})\$. But why is the current through \$p_3\$ \$20 \ \text{A}\$, giving us a power of \$0.12(25 \ \text{A}) \times 20 \ \text{A} = 60 \ \text{W}\$, rather than the \$I = 25 \ \text{A}\$, which would then give us \$0.12(25 \ \text{A}) \times 25 \ \text{A} = 75 \ \text{W}\$?
To clarify, the textbook has not yet introduced the concept of a component being in parallel vs being in series, so the reader would not know this at this point in the textbook.
AI: For \$p_4 \$ in example 1.7 the current flows from the lower electric potential to the higher electric potential. It flows through a voltage increase. So the power dissipated in \$p_4 \$ is
$$P_{p4}=I_{p4}V_{p4} = (0.2\frac{\text{A}}{\text{A}} \cdot 5\text{A}) \cdot (-8\text{V}) = -8\text{W} \: \: \: \text{(power delivered)} $$
\$p_3 \$ and \$p_4 \$ have the same voltage drop across them, because they are in parallel connection.
For \$p_3 \$ in practice problem 1.7 the current flows from the higher electric potential to the lower electric potential. It flows through a voltage drop. So the power dissipated in \$p_3 \$ is
$$P_{p3} = I_{p3}V_{p3}=(20\text{A}) \cdot (0.12 \frac{\text{V}}{\text{A}}\cdot25\text{A}) =20\text{A} \cdot 3\text{V}=60\text{W} \: \: \: \text{(Power absorbed)}$$
Where the current comes from earlier in the circuit has no influence on the power dissipated in a particular passive circuit component. The only thing that matters are the current direction, and the voltage polarity - and the magnitudes of course.
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H: How can I multiplex the outputs of an XBEE and a MAX485's?
I have a microcontroller that gets fed with 8-bit commands that either come through wires (using the RS-485 standard) or by the RX pin of an XBEE (without using actual switches) I want to multiplex them somehow in order to automatically receive the right command coming from the right source. I tried using some logic-gate circuitry but it only works if the data is coming from the XBEE. I think the main problem is that the idle state of the XBEE is on 3.3V and the idle state of the MAX485 is 0V.
Does anyone have any idea how I could make it work? Also, another problem would be converting the 3.3V logic of the XBEE to a 5V logic, I thought of using a level converter IC, but I would like to know if it's possible only by using a transistor. Thanks in advance!
AI: In general, for the multiplexing you should use a multiplexer instead of fiddling with single gates. You only get race conditions, hence glitches etc. from trying this with simple logic. However, if I understand correctly, this is not the core of your problem.
You want some device to decide which input should be routed to your I/O. This isn't easy, because having two inputs leads to four possible states. No signal, a signal from either input or simultaneous signals from both inputs. In most cases the solution is to use two serial IOs at your microcontroller, because then you get rid of all such problems.
What is necessary to do it without spending another serial port?
You could trigger a latch with both inputs and have one of them inverted. The output of the latch represents the input where the last „non idle“ level was received. The output of the latch then can trigger a mux.
simulate this circuit – Schematic created using CircuitLab
However, this doesn't help you in the fourth case, when two I/O-signals arrive at the same time. Then you have to decide how to react on such collisions.
Edit
One option to deal with this priorization problem is to put another D-Latch after the R/S-Latch.
simulate this circuit
This allows the μC to control when to switch between input signals. As long as the output from the μC is high, either incoming signal can trigger the mux to change. The μC's duty is then to set the control pin to low as long as it wants to read the incoming data. At the end of the transmission the μC releases the pin to high again and the autoselect mechanism is reactivated.
You have to make sure that the propagation delay of the AND and OR-gate together is greater than the delay of the RS. Otherwise the wrong signal will be latched through the D-latch.
Still, if simultaneous transmissions aren't ruled out, you will face incomplete transmissions after releasing the gate pin.
Concerning the level shift, there are lots of solutions on the web and in most cases they are more cumbersome to build up and in any case more expensive than an level converter IC. Do you have a reason to do it discrete or is it just for learning?
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H: How can I specify in Altium to leave out the dielectric layer for a portion of the board?
I am trying to replace the dielectic layer in just a portion of the board and instead have that just be more copper. The idea is to essentially allow the PCB to use anything it lays flat on to be a heatsink. Kind of like a metal core PCB or a large rectangular via that is filled.
I'm banging my head on my PCB software (Altium) stack up and can't figure it out.
AI: You can set the board up as a Rigid Flex PCB. That will allow to to define multiple stackups in the PCB. You just won't have any flex regions.
To do this go into the layer stack manager and go to Features -> Rigid-Flex.
Then you can go into board planning mode and use split lines to create board regions for each part of the PCB and choose its stackup.
I also encourage you to make sure your PCB stackup is manufacturable with a PCB Fab house. Its a little unclear what you need and seems very non standard.
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H: How to randomize the seed-number in Modelsim?
In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number.
I was wondering if Modelsim has the similar automatic seed number option.
Thanks!
AI: If SystemVerilog, use the flag: -sv_seed random along with vsim command for ModelSim and QuestaSim.
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H: Mutual inductive coupling in a nodal admittance matrix
I have this question that has been haunting for quite a while now. To compute the nodal admittance matrix \$Y_N\$ of an electrical network, one can make use of the incidence matrix and the branch (or edge) admittance matrix. However, in the case of a transformer or a winding who have inductively coupled turns, how is this taken into account in the nodal admittance matrix? I can't comprehend it, and if it's not taken into account how can I take it into account?
Adding schematic to ease comprehension:
Take for instance this circuit:
Its graph is the following:
From which you can deduce the nodal admittance matrix:
$$Y_N = A_f Y A_f^{T} (1)$$
with both \$A_f\$ and \$Y\$ being the incidence matrix and the branch matrix, respectively, defined as follows:
and,
Eventually, we have the following nodal admittance matrix:
The difficulty that I am facing is for mutually coupled inductors (those in the circuit). I do not know how the take the mutual Mij into account in my nodal admittance matrix (well first in my branch matrix then \$Y_N\$ will be deduced from equation(1))
Thanks in advance :)
AI: In general I don't think you can. The method used in most circuit simulators is modified nodal analysis. Here a couple of extra equations are introduced where you solve for the currents through the inductors as well:
from this MNA lecture
In some situations you can eliminate the mutual inductance, for example if the two bottom legs of the transformer are connected there are transformations to circuits with three uncoupled inductors which allows you to use simple nodal analysis.
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H: Voltage Gain Expression
I had a homework problem where I was supposed to find an expression for H(ω) = Vo/Vs of the op-amp shown below:
However, when I found my own expression, it turned out to be a very messy fraction that may be difficult to solve.
Is there a simpler form or method of finding the expression? My work for the problem is shown below.
AI: I recommend taking a look at your first equation. It is a voltage divider, but this wont work for two reasons:
First, this divider implies Vo is at the other node of the R1-C1 branch, and implies the output of the op-amp is grounded.
Second, the negative terminal of the op amp is actually at ground potential.
You might remember from electronics that there is a “virtual short” between the two input nodes of an ideal op-amp, meaning they have equal voltage. The positive node of the op-amp input is at ground, so this means the negative input node is at ground. Also, there is a “virtual open-circuit” at the op-amp inputs, so current cannot flow into the op-amp. From this you can generate some different equations, which should hopefully get you squared away. I’ve attached some work to get you started.
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H: Programming an old school microcontroller (MSM80C49 from OKI semiconductor)
I've read the whole datasheet, there's no typical guidance on programming procedure/setup/circuitry.
It just mentions a few steps on how to order pre-programmed chips. (I guess) on page 18.
On a version of datasheet, it mentions a development tool called EASE80C49, and development softwares EASE49 & ASM49
A quick search didn't help me find any info on these tools and softwares.
These chips are very cheap.
How can I program them?
AI: (Putting my comments into an answer for posterity)
This type of microcontroller was intended for large volume production, so they are not programmable after manufacturing. The program is contained in mask ROM which was custom fabricated based on the customer's supplied code using a custom printed photomask. The program was literally etched onto the silicon. This had a high startup cost to create the mask, but very low manufactured unit cost.
I imagine the development kit circuit board would have included a version of the microcontroller whose ROM contained a only bootloader to run whatever code was being developed from an external EEPROM memory.
The ones you see as "new old stock" for sale are probably programmed with the firmware for some consumer or industrial product of the era. It would be difficult or impossible to make use of them outside their original environment.
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H: LED Lighting Question
I have a project that uses an array of LEDs as a lighting source.
Digi-Key's website has two categories of LEDs that seem to be of interest to me.
LED Indication - Discrete
https://www.digikey.com/en/products/filter/led-indication-discrete/105
LED Lighting
https://www.digikey.com/en/products/filter/led-lighting-white/124
What is the difference between these two categories?
In my mind, I am trying to get the maximum amount of "brightness per watt" or something like that, and it feels like one of the categories might feature LEDs with special characteristics (super fast recovery time, etc.) that I don't necessarily need.
Details of the LED spec (if it is of relevance):
5V power source
Driven by 3.3V GPIO
25mA Ic rating
AI: It's simple. Just think of the wording.
indication means some point in a apparatus indicating some state. The light being emitted bye the LED is directly received by the human eye.
lighting means a surface being illuminated. The light emitted by the LED illuminates something which is then seen by the eye.
Now, what's the difference concerning the devices used for that? It's the optimization for different purposes. In general, to perceive a signal from a LED doesn't need lot of luminous flux, so power output of the LEDs designed for indication is typically way below 0.5 W. In those devices efficiency is not the most important design yield. They are usually optimized to emit in a certain angle at a defined luminance.
LEDs for lighting are more likely to be optimized to emit certain luminous flux and to perform at a certain efficiency.
Another significant difference is color. Indication type LEDs are designed to be perceived with a distinctive color. When filtering only 2.6 k results of 23 k have a white color. So almost 90% of the indication LEDs are colored. Of course, when an indication is needed, the color should be fixed as it tends to represent a state as well. Most common: green=good, red=bad.
In comparison all of the lighting LEDs are white. So the purpose is, to deliver a full spectrum and let the dyes and pigments of the illuminated objects determine the impression at the eye of the viewer.
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H: How to decrease clipping in emitter follower
I have a small headphone amplifier with an class A output stage and some negative feedback. The result is not good, but the point is purely self-educational. The part are all jelly-beans and certainly not optimised for audio.
My test circuit can be simplified to this:
simulate this circuit – Schematic created using CircuitLab
\$V_{in}\$ has a maximum peak value of \$1.5\text{V}\$. One issue is certainly that the op-amp can't go close enough to its positive supply rail to compensate the \$V_{be}\$ drop, but that's not the one I'm interested in now.
The second issue is that the emitter can't go below \$-2.5\frac{R_L}{R_L+R_e}\$ without \$I_e\$ going to zero and thus reverse-biaising the base-emitter junction. It will mean that close to that negative voltage, there will be distortion (due to varying \$V_{be}\$ drop) and clipping below that value.
One solution would be to decrease \$R_e\$, but that would mean bigger losses. I know class A isn't supposed to be very efficient, but if I decrease \$R_L\$ to more common headphone impedance values, I would have to decrease \$R_e\$ even more and lose tons of power.
I could of course use a class B or AB instead, but, just for the sake of my own education, would there be another way?
AI: That type of output stage has a maximum efficiency of ~12-15%.
You can increase the efficiency a bit by biasing it asymmetrically with a larger negative than positive supply.
You can increase efficiency further by using a current source instead of the emitter resistor.
https://www.edn.com/distortion-in-power-amplifiers-part-viii-class-a-amplifiers/
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H: A question related to a NPN transistor having a DC bias
β = current gain
I made the circuit of the above picture with LTspice.
(A graph of Vce)
(A graph of Vbe)
And I was able to get 4.2966V for the value of Vce and 0.6543V for the value of Vbe.
However, when I solved it by hand, the value of Vce was very different.
Watch, please
I translated Korean to English, as follows:
Korean(English)
e.g. 등가회로(Equivalent circuit)
As you can see, the value of Vce solved by hand is 2.9181V.
I really don't understand. How can the error of Vce value occur so big?
Did I design the LTspice wrong? Or, did I solve it wrong?
Please, help me.....
AI: The KVL equation \$-10 + 7\,[\text k\Omega]\cdot1\,[\text{mA}] + V_{CE}\$ neglects the voltage drop across the current source I1, and that loop cannot be easily solved with KVL alone, because we don't have an equation that tells us the voltage across a current source.
Instead, you know that \$\beta = 100\$ so the base current is \$I_B = 10\,[\mu\text{A}]\$. You can instead solve KVL around this loop:
We can get \$-10\,[\mu\text{A}]\cdot60\,[\text k\Omega] - V_{BE} + V_{CE} + 7\,[\text k\Omega]\cdot1.01\,[\text{mA}] - 10 = 0\$. When we solve, we get around 4.3 V for Vce which agrees with LT Spice.
In closer detail, the above is equivalent to applying the same step by step logic:
The base is at -600 mV because of a voltage drop of \$R_B\cdot I_B\$.
The emitter is at -1.3 V because it's one \$V_{BE}\$ drop below the base.
The collector current is \$1\,[\text{mA}] \cdot (1 + \beta)\$ so the voltage drop across \$R_C\$ is 7.07 V.
This makes the collector voltage 2.93 V.
If emitter is at -1.3 V and collector is at 2.93 V, \$V_{CE}\$ is 4.23 V.
The error between this result and LT Spice probably arises because we assumed a fixed value for \$V_{BE}\$.
Edit to address comment:
In order to get a Vbe, you need to know a transistor parameter called Saturation Current (\$I_S\$) and then solve the equation \$I_E = I_S( e^{\frac{V_{BE}}{V_T}} - 1)\$. \$V_T\$ is proportional to temperature and is approximately 26 mV at room temperature.
Unfortunately this behavior is really sensitive to temperature and manufacturing variations, so it's hard to always get exact values for Vbe. 0.6 or 0.7 is a good estimate to start. You will find that many circuits use techniques like degeneration and feedback to make them less sensitive to these effects so that the exact saturation current or collector current isn't as important to get exactly right. Also, there are many circuits that have two transistors where we don't care about the actual value of Vbe, only that it's the same for both. In that case there are manufacturing techniques that help ensure this matching.
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H: Transistor collector current less than base current
What happens if the collector-emitter current is less than the base-emitter current? Do I need to increase the base resistor to lower the base current or is it okay to keep the transitor operating in this state?
The background is that I did connect a LED with a 2KOhm resistor to the collector side (5V) and I am using a 1kOhm resistor at the base side (3.3V, Arduino). Originally I used a 220Ohm resistor for the LED, but I just needed to reduce the LED brightness. I am not sure if I actually need to increase the base resistor value, just to keep the base current always lower than the collector-emitter current.
AI: There is no requirement that the base current be smaller than the collector current.
If you are driving more than is needed you are, however, wasting power so in a battery operated circuit it would be useful to drive a lower current into the base.
The usual design technique for driving a transistor into saturation is to assume an Hfe of 10-25 and select the base resistor appropriately. This ensures that even a worst case transistor will be driven adequately.
It is acceptable for the collector current to be zero, or it can even be negative in some circuits, especially where the transistor is switching AC.
The base current should be within the transistor's ratings and you may not want to drive so much that it causes significant thermal dissipation.
One disadvantage with driving the base very hard is that it will increase the amount of charge stored in the base that will cause the transistor to be slower to turn-off when the base current is reduced to zero. For many applications this is not a problem. If faster turn-off is required a capacitor in parallel with the base resistor can help by driving negative current into the base when turning off.
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H: Flash ADC - Why R/2 at the ends of the resistor ladder?
Why to use R/2 on the ends of the resistor ladder instead of using just R?
AI: Why to use R/2 on the ends of the resistor ladder instead of using just R?
Because it is better to have a max. error of \$\pm \frac{1}{2}\$ bit:
source
It looks wasteful with just 4 codes, but this trades off 2 half bits in the whole range for a represented range that crosses the origin. See below for a 0V to 10V input range:
The input values below 0V and above 10V may never occur for \$V_{ref}=10V\$, but the average error due to quantization is zero.
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H: Problem with identifying a component
What is this little part called?
It seems to be burnt, does this require the replacement of the whole motherboard?
AI: It's most likely a MOSFET, as part of a switching power supply- either the switch or a synchronous rectifier MOSFET.
As to whether it would work if the MOSFET (and possibly the one next it) were replaced, hard to say. Other things may have been destroyed.
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H: Headphones on a line output (vs. headphones output)
I'm designing a device using a DAC (TI PCM 2704 like this one to be precise,) and optionally a headphones amplifier.
I noticed that connecting (32 Ohms, closed-back Beyerdynamic) headphones to the line output of this TI PCM 2704 module seems to work with good audio level, even though there is no amplifier chip at all.
Does this mean this DAC has enough line output level to drive most headphones?
In general, which dB attenuation is there for a listener with headphones connected on line output instead of headphones output?
(I know it will vary from device to another, but I'm looking for a general estimation if the devices use the "standard" specifications for line level and headphones level.)
AI: The first headline of the datasheet says the chip can drive a headphone output. So yes, the chip can and is even intended for driving headphones.
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H: What is the input impedance of this circuit?
Here is the relevant part of the schematic of the Befaco InAmp, a Eurorack preamp for line level and instrument level signals:
I am trying to determine whether I can safely connect the AKG c1000S microphone to it, which has a 200Ω output impedance and, according to its manual, requires a preamp with at least 2000Ω input impedance.
Since the value of resistor R2 is 100k, can I assume that the input impedance is 100k? Since that is a lot higher than required, will that mean that my mic volume will be too low? Finally, could I use a passive transformer to increase the output impedance of the microphone before connecting it to the InAmp? Or is the only solution to use a dedicated mic preamp?
AI: The impedance is the ratio between the voltage of the input and the current which pass through. It would be R2 if R2 was connected directly to the ground. Here, R2 is connected to R3 which is connected to the output of the operational amplifier.
The output is at Vout = - Vin . R3/R2. (This is the voltage which makes equal the input levels of the operational amplifier).
The current is I = (Vin-Vout)/(R3+R2) = Vin (1+ R3/R2) / (R3+R2)
Then the impedance Z = Vin / I = (R3+R2)/(1+R3/R2).
I consider the case in which the capacitors has a null impedance… if it is not the case, we should take into account the frequency.
EDIT : developping Z = (R3+R2)/(R2+R3).R2 = R2… Then you where right. I could have infer it sooner (the right end to of R2 is not connected to the ground but to « other things which makes its voltage null », then it is as it was connected to the ground.
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H: How can I figure out the I2C address of an OLED display?
I've got an OLED display I am trying to write to from my Raspberry Pi Pico.
It's an SH1106 driver.
I can write fine when I set the I2C address to 0x3C, but behind the display there are two I2C address 0x78 and 0x7A - no 0x3C.
If I try either of the 0x78 or 0x7A numbers, I get a runtime error - device not found.
AI: There are two de facto notations for I2C addresses, 7-bit address values with separate read/write bit which is not considered as part of the address value, and 8-bit address values where the read/write bit is included in the address value. Sometimes the 8-bit write address is used as the base value for the address, or it is said as a pair of read and write addresses.
0x3C in 7-bit notation is equal to 8-bit notation write and read address pair for 0x78 and 0x79.
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H: Faster Timer0 overflow than 2 ms on Attiny85
I'm trying to get a Timer0 overflow with an overflow every 500us, but can't find a solution to get it so low.
I'm running the Attiny85 on its internal 1 MHz clock, so I know it is not gonna be the most precise thing. Right now the lowest overflow I can achieve is 2 ms.
In my setup, the Timer0 starts counting when a pin change happens on PCINT0 and stops after 4 counts. Timer0 is setup up to CTC and with the prescaler to 1024.
I set the value of OCR0A with SERIAL_BIT_TIME
The code I'm trying is here
#define F_CPU 1000000UL
#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#define SERIAL_SEND PB1
#define SERIAL_RECEIVE PB0
#define SERIAL_RATE 9600
#define SERIAL_BIT_TIME 0x01
int main() {
DDRB |= 1 << PB1;
DDRB &= ~(1 << PB0);
//PORTB |= 1 << PB1;
TCCR0A |= 1 << WGM01; // clear on compare
TCCR0B |= (1 << CS02) | (1 << CS00); // ( F_CPU/1024 = 976 Hz )
GIMSK = 1 << PCIE; // general intertupt mask enable pin change int
PCMSK |= 1 << PCINT0; // Pin change mask
sei(); // set interrupt enabled
while(1); // Do a heap of useful calculations
}
uint8_t position = 0;
ISR(TIM0_COMPA_vect) { // Timer interrupt
PORTB ^= (1 << PB1);
if (++position == 4) { // If at end of byte
TIMSK &= ~(1 << OCIE0A); // Disable interrupt for compare register A (this interrupt)
PCMSK |= 1 << SERIAL_RECEIVE; // Enable pin change interrupt to start next byte
} else {
OCR0A = SERIAL_BIT_TIME; // Set delay time equal to the length of a single bit
}
}
ISR(PCINT0_vect) {
TCNT0 = 0; // Set counter to 0
OCR0A = SERIAL_BIT_TIME; // Call timer interrupt in middle of first bit
position = 0; // Reset position and data
TIMSK |= 1 << OCIE0A; // Enable interrupt for compare register A (timer interrupt)
TIFR |= 1 << OCF0A; // Clear timer interrupt flag to prevent it jumping directly there
PCMSK &= ~(1 << SERIAL_RECEIVE); // Disable pin change interrupt
}
And the result measured with my Analog Discovery 2:
The yellow line is the pin that toggles in the overflow and the blue line is the output of a signal generator, used to change state of the input pin.
Any help or explanation would be lovely
New image with no prescaler
As per request from @G36 here is the result when the prescaler is set to 8 and OCR0A to 61.
With the suggestions, I got what I want. Thanks a lot guys.
AI: An interrupt every 500us is a rate of 2 kHz. As you have only a limites set of prescalers available and the resolution of the timer is only 8 bits, you can't use it without prescaler, and the next prescaler is 8.
As the MCU works at 1 MHz, the timer will run at 125 kHz. Divide by 62 and it is approximately 2 kHz.
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H: What is a correct approach to implemement an AXI stream interface?
I am designing several sumodules for FPGA and would like to interface them through an AXI stream.
Some of the modules I use are able to process the stream at data throughput speed same as clock one. Some are not able to process a continuous stream. Which means in the second case, the module is busy for a while (not able to accept data).
I have read that there exist some skid buffers or fifo between modules to garantee a smooth flow but I am lost when trying to represent it myself how it works.
My main concern is that the chain does not block or loose data.
Does anyone have an advice on the simplest approach to implement an AXI stream compatible module?
AI: If you’re using Xilinx, Altera, or Microsemi, the FPGA tool chain library will have a rich set of modules for AXI and AXI-S, including FIFOs, register slices and other blocks for rate and width adaptation. It’s unlikely you’ll need to build anything at all, except for your own user logic.
Lattice? Not so much, at least since the last time I looked at them. They do Wishbone.
Now, what will you need to build yourself? It’s pretty simple really when you’re dealing with AXI-S. Your user logic needs to understand the TREADY / TVALID handshake. The key rule to remember is that the definition of a completed transfer is both TREADY and TVALID are asserted.
Do you need a skid buffer? It depends. You need one if for some reason your data sink can’t send a back pressure signal (that is, negated TREADY) within one cycle. This would be the case regardless of using AXI-S or not.
Can your sources keep up with your sinks? Do you have situations where your sink can’t tolerate an underrun (like video refresh)? You’ll need to consider system response time to servicing these streams, and allocate enough buffer to cover that latency.
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H: Current sense pin detect too quickly (Flyback)
Here is my circuit:
simulate this circuit – Schematic created using CircuitLab
There is two problems:
Firstly, the sense circuit don't open the mosfet at 1V, yet the zener at the V+ in the amp op have a zener of 1v that limit the threshold to 1V (in the pwm circuit).
2)If I estimate the current slope E/L, I'm supposed to reach the 1a current in 2us, I don't understand why I reach 1a in 100ns, (maybe the current stuck in th drain capacitor increase the slope)
E=350 and Lp=750uH
Filtering my signal doesn't change anything.
Here is my curves picture, the sense current in yellow, and Vds in blue.
PWM:https://eu.mouser.com/datasheet/2/308/1/UC3844B_D-2320086.pdf
SMPS:https://docs.rs-online.com/696a/0900766b80107114.pdf
AI: Concentrate on what I'm telling you. This is important.
This is a flyback converter design and, when the MOSFET activates, current is drawn into the primary winding at a certain rate determined by primary inductance and input DC supply voltage. If the secondary winding does not appear to be open circuit when this happens, the whole idea of it being a flyback converter fails. The secondary circuit is made to be open circuit during the primary charge sequence by both the secondary diode direction and the effective winding dots between primary and secondary. If either the diode is the wrong way round or the dots are not as they should be then it won't behave as a flyback converter.
What you appear to be indicating in comments leads me to believe that you have got this muddled up and the converter will not behave as a flyback converter. It also appears to be incorrect in your updated circuit. In other words the secondary diode conducts when the primary MOSFET activates and this is wrong.
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H: Why do I get 0 volt output when I have a voltage divider with a square wave input?
I would like to state the problem I am dealing with which I cannot explain.
The set up I have is as follows:
2 x resistors 1 kΩ,
1 x breadboard,
Wires,
1 x Voltcraft DSO-6202FM oscilloscope which has 2 channels and dual channel arbitrary function generator.
I have a breadboard where I built a resistor voltage divider of two 1k Ohm resistors.
At one end of the first resistor I connected a probe coming from the function generator. The signal from the function generator is a square wave at 200 Hz, start phase 0 degrees, a high level 500 mV, low level 0 mV.
A probe is used to display the output signal at the measuring point and is connected to channel 1 CH1 of the oscilloscope.
First observation:
When I connect the output probe from the function generator to the probe connected to CH1 directly, I see a square wave, without needing to connect the two ground clips of both probes.
Q. How is this possible? I thought I need to connect the ground clips together to have a common ground and then be able to see the waveform from the function generator!
Second observation:
As shown in the diagram above, the output of the function generator is connected to the one end of the first 1 kΩ resistor.
The probe of CH1 is connected to the output resistor of the voltage divider. The second end of the output resistor is NOT connected to a common ground. A signal is recorded but the value of which is the same as in the first observation.
If I connect the ground clip of the function generator, the ground clip of CH1 and the second end of the output resistor together, the recorded waveform on CH1 of the oscilloscope is constant 0 volt.
Q. What is the explanation of this phenomenon that when I connect all the ground clips and the resistor of the voltage divider together to form ground I get a 0 volt signal on the oscilloscope?
Your wise comments and suggestions are welcomed with high regards.
AI: If you're using a 10x oscilloscope probe on the output of the function generator, there is a 9 Megohm resistor in series with the probe. When the floating end of the resistor divider is grounded, this will form a resistor divider that will severely attenuate your signal.
simulate this circuit – Schematic created using CircuitLab
As for the grounding bit, since the signal generator is part of your oscilloscope, they share grounds internally to the instrument.
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H: Adjusting input voltage for ESP8266 (difference between linear regulator to step down)
I need to supply 5V to power a Wemos mini MCU (ESP8266 based,) using a 12V source (in order to PWM a 12V LED strip.)
I wish to know what is the difference between using a linear regulator (such as AMS1117, asthis), to a buck/step down converter as this).
What considerations should I take when selecting one and not the other?
AI: What considerations should I take when selecting one and not the other ?
As Tirdad explained, the LDO will waste the difference between input and output voltage as heat. If you want to drop from 12V to 5V, then 7/12=58% of the input power will be burned as heat in the LDO, and the remaining 42% will power the micro.
ESP8266 uses on average about 40mA so that's not going to ruin your electricity bill, and that's only 0.28W average dissipation in the LDO, so it would probably work... except it draws peaks of up to 200mA when using the WiFi, which corresponds to 7V*200mA=1.4W, which is above what an AMS1117 in SOT-223 can dissipate. So if you use the WiFi a lot it could overheat.
Also AMS1117 requires a large output capacitor which is not present on the quoted aliexpress module, so it will probably not work reliably. This is a very cheap and low quality LDO, it is slow, output transient response is poor, and the built-in protections are not as reliable as one would expect. Basically, there are much better LDOs, if you need a LDO, don't buy this one. I've had problems with ESP32 modules getting temperamental, and replacing this part with a better one (LDL1117) fixed the issues.
The buck converter will have much better efficiency, so that's what you need.
Buying cheap DC-DCs off aliexpress is a bit risky. The ones with "LM2596" are all fake with garbage quality capacitors. The one you quote doesn't have electrolytic capacitors, so at least it won't have bad electrolytic capacitors. There is no diode so it's probably synchronous, which means better efficiency. It'll probably work fine.
I'm going to use an ESP32, the project has lots of relays so I went with a 24V power supply, and I'm using this Recom DC-DC which is definitely not expensive. There are also higher current versions, the usual shops (mouser, farnell, digikey...) have plenty of canned buck converters like this, from known manufacturers and with full specs and datasheet...
Note if you want good smooth high frequency PWM for your LEDs, ESP32 is a better option than ESP8266.
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H: How can use grounded primary coil transformer with BGJ/MOSFET
So, I have a pulse signal transformer like this (freq is 1MHz):
In the secondary coil I want to get bipolar pulses. How can I make it using BJT or MOSFET switches and wich is better?
I know, that typically primary coil is in the collector of BJT, but how can i use it with grounded coil.
I need something like this, but I understand that in this case BJT won`t switch on properly.
Can I use pnp type like this??
AI: Seems ok to me.
You can connect the collectors together and use one 5V source.
But more usual approach is to connect 5v to center tap and connect transistor low side (common emitter).
simulate this circuit – Schematic created using CircuitLab
With mosfets it's also possible.
Edit:
The pnp version controlled with npn:
simulate this circuit
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H: maximum memory supported by processor - why often stated less than 1TB?
I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki:
Modern 64-bit processors such as designs from ARM, Intel or AMD are
typically limited to supporting fewer than 64 bits for RAM addresses.
They commonly implement from 40 to 52 physical address
bits13 (supporting from 1 TB to 4 PB of RAM). Like previous
architectures described here, some of these are designed to support
higher limits of RAM addressing as technology improves. In both
Intel64 and AMD64, the 52-bit physical address limit is defined in the
architecture specifications (4 PB).
Crucial site, understanding-cpu-limitations-with-memory talks about speed only, point to Intel site. But as far as I know, info e.g. i7 tells 32Gb because at time of creating the processor only 16Gb modules was available, meaning it supports 2 modules only (2 modules is my guess now, wiki quote above talks about bits).
I'm only starting to understand technical details how memory works, like ranks. What exactly prevents all modern e.g. Intel processors to claim to being able to address as least 1Tb (per wiki above)?
Is the reason same for ARM in smartphones? E.g. 875:
Max size 24 GB
For ARM I have no experience changing amount of memory as all my devices had SoC, though I recently found ARM should have systems with modules, as web search indicate (e.g. https://www.anandtech.com/show/13635/apacer-launches-32bit-sodimm-for-arm-risc-v-systems).
AI: Your quote from Wikipedia is referring to physical address space, the size of all memory addresses available to the processor. It is just the sum of all addresses that can fit into physical memory space. However, not all physical memory is RAM. PCIe devices like GPUs, flash storage, etc also occupy physical memory addresses which are used to communicate with them or copy data to/from them. For this reason the physical memory address space should always be larger than the largest possible amount of RAM in the system. If it isn't you end up with situations where not all hardware can be installed at the same time or not all memory can be accessed, as actually happened in the old days of 32 bit x86.
So clearly if your system is well designed, a 40 bit address space does not imply that you can actually have 2^40 bytes of RAM. If it did you would lose access to your PCIe and other hardware. What actually limits your available RAM then? The memory controller on your CPU has to actually be able to map physical addresses to unique cells of RAM. There is a practical limit to how much memory it can actually access. Individual DIMMs have a maximum size set by the specification, and the memory controller itself has a maximum number of memory channels.
For example, a 10th generation Intel Comet Lake processor supports up to 4 DIMMs, with a maximum size of 64 GB per the DDR4 spec. Thus the maximum possible capacity is 256 GB (although Intel says only 128 GB so perhaps 64GB DIMMs are not actually supported). The remaining physical address space can still be used by other hardware, just not by the memory controller.
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H: maximum out put swing question - Transistor
For example, given two mosfets that have different Vd,sat, but their vout is situated at half the supply range, would it be possible for both transistors to have a maximum output swing? My thinking is that they cant since they have different Vd,sat, making the their output swing some "headroom" if one is maximized. However, I am confused because from what i understand, usually, a transistor's output swing is maximized if there its Vout is half the supply range. Any insight is appreciated, thank you.
AI: I understand what you are asking.
I think one can design it somehow.
I think nobody is ever interested because it's not a real need for electronics and yet it might cost much more in terms of part count that using a single MOSFET.
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H: Flux because of secondary coil in transformer
In a Transformer - Alternating current flows in primary winding
Causing alternating magnetic field in Iron core
Which causes alternating voltage in secondary coil.
But I am confused that what would be the polarity of the Flux caused by the secondary winding voltage.
Won't the Flux caused by the secondary voltage cancel the Flux caused by the primary voltage and thus making the net Flux zero in the coil if both the primary and secondary windings have the same number of turns?
AI: Two differing currents flow in the primary winding of a secondary loaded transformer. The first is the magnetization current and this is purely due to the primary being regarded as an inductor. That current is 90 degrees lagging the applied primary voltage. That current sets up the magnetic field and that current induces the secondary voltage.
The other primary current occurs when the secondary is loaded. This new additional primary current produces a magnetic flux that is exactly opposite to the magnetic flux caused by the loaded secondary current. In effect, the net flux addition due to loading the secondary is zero; fluxes due to loading are cancelled leaving only the original magnetic flux due to a voltage being applied across the primary.
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H: What is the difference in these feedback configurations
In both these cases, the feedback remains the same hence the relation between input and output must be the same. However, if I want to analyse the closed loop stability, will the additional \$K(s)\$ affect my analysis in any way? Considering the same input output relations, it should not affect it, but the \$K(s)\$ has to cause some distortion?
In the case I'm studying, \$K(s)\$ is a capacitor resistor combination which is grounded at the end.
I'm using the following amplifier:
AI: If A(s) has a non-zero output impedance, then K(s) will modify the signal at Vo. Assuming everything else is ideal, and A has an impedance of AZ(s), you can modify H(s) to H(s)*K(s)/(AZ(S)+K(s)).
You can see that if AZ(s) -> 0 (i.e. ideal), then it reduces to your first diagram.
Note that real circuits have other non-idealities - H(s) may also load A(s); there can be feedforward from the input, though the summer and H(s) also to the output (if AZ(s) is non-zero).
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H: Single Diode Mixer Port Isolation
I am an amateur radio enthusiast that would like to build an FM superhet receiver. I am stuck on a mixer design. Each block of my diagram is functional when running independently. However, once I delete R14 and R15 then connect their respective wires to R7 and R8, the voltage on RF and LO lines when probed have the same waveform. Their independent frequencies are lost and I get the wrong IF out of the diode.
How can I isolate the inputs of my mixer to prevent this?
Some info about the simulation: The RF Amplifier is amplifying a 50 mV 103 MHz signal to around 300 mV peak to peak.
The LO is at 93 MHz. This should give a 10 MHz IF among other things as far as I know.
AI: How can I isolate the inputs of my mixer to prevent this?
A single-diode mixer is a "no-balance" mixer: Local oscillator, R.F. input, I.F. output appear at all three ports. A single-balance mixer allows some isolation between two of the three ports. A doubly-balance mixer gives some isolation between all three ports.
Single diode mixers with no balance have been used back when transistor amplifiers had too-little gain at VHF frequencies. Not a reasonable design choice today.
simulate this circuit – Schematic created using CircuitLab
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H: I2S voltage shifters needed?
I am designing the schematics for my new PCB and I need to output some audio signals (totally new to this).
I am using an ESP32-SOLO-1 as MCU and the TFA9879HN as audio driver. The TFA9879HN is powered from 1.8 V, and the ESP-32 is powered from 3.3 V. I would like to know if it is necessary and possible to implement an I2C voltage level shifter with a MOSFET.
I have read that no pull-ups are needed, but the high frequencies concern me. SCK's frequency is 8..96 kHz and LRCK's frequency is 32~64 times SCK's frequency, so up to 6.144 MHz.
I think the MOSFET may not be fast enough. I am planning to use the Nexperia BSS138BKS from Nexperia and can simplify the BOM if I can use it for the multiple voltage shifts I need.
AI: Second page of datasheet says the digital inputs are 3.3V tolerant in the general features. Thus no I2S voltage shifting needed.
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H: DS3231 Question
Can someone help me understand the differences between:
"Adafruit DS3231 Precision RTC Breakout" and one of these generic breakout modules, "DS3231 AT24C32 IIC RTC Module"?
Why I would choose one over the other?
I am making a watch using the DS3231 and eventually I plan on putting all of my chips, LEDs, and a battery holder onto one custom board, but I don't quite see why there are so many different form factors for these boards when essentially they all provide the same function.
AI: Adafruit module:
Manufactured by a trusted designer with original parts, libraries and regularly updated walk-throughs to use the modules. The exact schematic and PCB layout is also provided.
Expensive; compared to the other module.
Unknown module:
Made by unknown manufacturers with no library, walk-through or website.
Not guaranteed to use the original part and for a "precision" timer, it's quite important.
The design may vary between manufacturers or later versions. For example you may find an exact looking module but with another eeprom chip or another default addressing or even different pin order.
It has an on-board eeprom IC. that would ease the burden of wiring another IC if you want to log data into a memory with timestamps or simply need more storage.
It's cheap.
Personal experience:
See this question I asked a few months ago while digging through some fake temperature ICs.
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H: Can an ideal diode pair (evaluation board) be used for backing up one battery with another?
I'm trying to use 2 ideal diodes [within a MAX40203 evaluation kit] for "OR-ing" two battery power sources... to extend the length of time for driving an outdoor flag light. My understanding was that the battery source with the higher voltage value should "rule". But my setup seems to temporarily make the spotlight brighter, rather than to provide a "switch" for the two battery sources--which is what I intended. {Each battery source actually consists of two Lithium batteries; each set is charged by its own photovoltaic [PV] module.}
https://www.mouser.com/datasheet/2/256/MAX40203_W_EVKIT-2006979.pdf
{edit}: I've attached a link to the pdf for the evaluation kit. But as its operation is that of an "ideal diode", I think the kit can be thought of as one input source feeding one diode, the other feeding a second diode, with the far end of the diodes tied--feeding the the output to the load. (i.e. it can be treated as a black box.
I'm asking if what I'm doing is even feasible? Most of what I've read about using OR-ing for backup power purposes describes using batteries as backups for plug-in (regulated) power supplies, not for "backing up batteries with batteries".
I also performed tests indoors "on the bench" with a duplicate setup. The type of spotlight used to light the flag consists of 7 LEDs--which ideally should be driven by a constant current source, etc. While I don't know the design internals of each PV/battery unit, it is clear that when tested separately, the output voltage values decrease over time... and the spotlight dims over time. Given the availability of only limited battery power, it is not surprising that there seems to be limited or no provision for regulation.
I did have one or two email exchanges with the company, but I'm not sure I was able to clearly explain what I was trying to get across. {edit}: They suggested the kit will work for my application.
Any insight would be appreciated. I'm doing this as a favor for a friend, and I will be moving out of the area shortly.
{edit}:
When I tested the duplicate setup indoors, I deliberately arranged for the two PV/Battery units to begin with two different states of charge. One was measured at 3.9VDC; the other at 3.5VDC (with no load attached). When the load (i.e. spotlight) was connected, the first unit's voltage value dropped from 3.9VDC to ≈3.1VDC; the second unit's voltage value dropped from 3.5VDC to ≈3.0VDC. What was striking here was that the two units began with fairly distinct voltage values, but once a load was applied the voltage values became quite similar. This perhaps suggests why the evaluation kit might share the power from the 2 sources... rather than pick a winner. Separate bench tests showed that the output current value from the evaluation kit exceeded that contributed by either source alone.
AI: You already observed that the battery voltage drops when it's under load, so think about that for a moment. If the two batteries are at anywhere near a similar state of charge, and you switch the load between them, then the one providing power will always have a lower voltage than the one not providing power. But you have them hooked up to something that tries to enforce the condition that the one with the higher voltage is always providing power.
So how can the battery providing power have the lower voltage and the higher voltage at the same time? Either the system has to be oscillating (rapidly switching between the two batteries as each one's voltage reacts to the load), or it has to be showing its analog nature by finding an operating point where the batteries supply enough current each to drop down to the same voltage*. Probably the latter, but I wouldn't rule out the former without an oscilloscope. Either way, it's not really going to do the thing you wanted.
*: well, within a few millivolts anyway. The "ideal diode" still isn't perfect, and its voltage drop does still vary a bit with current.
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H: PMOS reverse supply
I'm a little confused, can someone explain to me why this circuit conducts?
I thought that the body diode of the PMOS was in reverse polarity and the source node of PMOS should be at 0V, but simulation shows the opposite.
This is a reverse polarity protection circuit and normally it would be supplied from the source node, but I want to know why in this configuration the circuit behaves like this.
AI: The diode will be in reverse, but the FET is labeled wrong.
You are feeding the 10V to source and pulling the gate low, so FET is on.
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H: Clock divisor for 100Hz to 25Hz: my output "out_reg" remains "don't care"
I have written code for a clock divisor for 100Hz to 25Hz but my output out_reg remains don't care when I check it in ModelSim even though out_reg1 is correct.
module clock(clk, out_clk);
output reg out_clk;
reg out_clk1 = 0;
input clk ;
always @(posedge clk)
begin
out_clk1 <= ~out_clk1;
end
always @(posedge out_clk1)
begin
out_clk <= ~out_clk;
end
endmodule
AI: There is no initial value for out_clk, and therefore the simulator doesn't know what value to assign to it when inverting an unknown value.
The following will help ModelSim determine an initial value:
output reg out_clk = 0;
In most cases, using an initial value is less preferable to using a reset signal. However in this particular case, a reset is really not necessary given that all you have is two registers toggling. The initial value is purely for the benefit of the simulation. If unavailable for synthesis, it may be necessary to wrap in a tool specific directive to mark as not for synthesis.
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H: DC current rating of copper wire (SWG)
I want to use SWG-sized copper wire but I am a little bit confused about the following:
On the internet I found different charts with different maximum current ratings for the same wire diameter. The maximum current obviously depends on the situation the wire is applied in (AC or DC, straight wire or coil, etc.) and temperature changes.
I want to determine the required wire diameter for an electromagnet. The wires are closely packed together.
Can someone provide me some reliable sources? I already did some research but I am a little lost as I explained above.
AI: The limiting factor for the current carrying capacity of copper wire is the temperature rating of the insulation.
It's quite easy to determine how much power a length of copper wire dissipates at a given current. It's very difficult to estimate what temperature that is going to heat the wire to, as that depends on the surroundings, and how well they cool the conductor. The reason you have found multiple ratings is that some are for a single wire in free air, some are for bunched wires in a conduit, and some might assume different temperature ratings for the insulation.
As a very very rough rule of thumb, you can reckon on 10 A/mm2 for modest currents in single or paired wires that aren't deliberately thermally insulated, and 3 A/mm2 for the windings of transformers and solenoids of a modest (hold in your hand) sort of size. Needless to say, these figures come with wide margins of error, and are merely ballpark numbers for a 'smell test' of your initial designs.
Fortunately, the tempco of copper makes it very easy to measure the temperature of windings by measuring their resistance, it increases by about 10% for every 25°C temperature rise. Unless you have very reliable (expensive) thermal modelling facilities, it's best to just build something and see what your temperature rises are.
One further consideration, is this continuous operation, where it reaches equilibrium (isothermal), or short duty cycle, where the mass of the copper absorbs the heat and there's no practical cooling during the pulse (adiabatic). If the latter, you can calculate the temperature rise using the thermal capacity of copper. Or you can just calibrate it by delivering a pulse and then quickly measuring the temperature rise. Of course, the magnet still has to have time to cool down between pulses.
For any non-trivial electromagnet, cooling design is just as important as electrical and magnetic design.
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H: Can an insulated copper wire oxidize down its entire length?
I was doing some electrical wiring on a trailer today and was surprised to see black instead of shiny copper when I cut and stripped a section from the middle of a long section of uninterrupted wire. There was literally at least 6m of uninterrupted wire on either end from where I cut!
My question is: can wire oxidize INSIDE the protective rubber? And if so, is the wire still good to use or should I be ripping it out and redoing all the wiring on my trailer?
For context: the wire is 18 AWG copper; it simply used to run current from the vehicle 4-pin connector to the trailer lights.
Here are a few pictures:
You can see two of the oxidized wires at the top; I included a new/fresh wire for comparison.
The oxidation can be rubbed off with the edge of a knife, but it's not ideal - it seems to be really easy to damage/break off the copper strands.
AI: This is a common sight in old wires on trailers, machines etc.
Indeed, the wire can oxidize down its entire length. All it takes is some oxygen and time, and wires typically are not air tight. Also if an open end of a wire is exposed to liquid, the wire can suck up liquid by capillary force increasing the rate of oxidation.
This isn't that much of a problem in itself, only the fact that the copper has turned black doesn't make it much worse of a conductor. The issue is if you need to put new connectors on a wire like this.
If you clean it thoroughly before applying the new connector, it can work pretty well. I usually clean the end with fine sand paper, if you are careful and take your time it can be done without any damage to the wire.
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H: LTspice fails at a simple two-resistor voltage divider. How can I fix it?
During some simulations, I noticed some oddities and narrowed it down to the following problem:
This is is simple voltage divider using two resistors. The four traces show:
supply voltage
current through R1. Everything is good so far
the voltage across R1. The DC voltage is missing.
consequently, the resistance of R1 is not 1 ohm, but it deviates by 10s of ohms.
I thought that this was a problem with limited precision, so I added the .options numdgt=15, but it didn't change anything. How can I get this right?
AI: The problem is known and only happens in versions of LTspice XVII after May (or June? don't remember) 2019. It doesn't happen in version prior to that, or LTspice IV. If you add a VCVS across the 1 Ω resistor with the value of 1, you'll get the correct voltage.
Search in the LTspice group for problem with modified trap. There are also files similar to yours, ProblemWithModTrap.asc and ProblemWithModTrap2.asc (you'll need registration, to avoid spam).
I'll try to address at least a part of G36's comment.
As Ste Kulov mentions in the comments, there is a page in the help (LTspice > Integration Methods) that tries to explain why there is such a reading with the modified trapezoidal solver. The page has two parts: the first explains how the modified trap works, and the second explains why the readings are how they are. While the first part explains very well how the modified trap works, in my, personal opinion, the second part is wrong, for these reasons:
The exact same schematic, used with versions of LTspice XVII prior to May 2019, or LTspice IV, and which have the exact same settings, do not exhibit the same behaviour. Therefore whatever it is in the newer versions of LTspicethat affects the response must have been introduced around May 2019 or later.
The schematic (as seen in the help) is comprised of a simple voltage source, together with a resistive divider. There are no reactive elements, there are no behavioural expressions, therefore there are no states. Not only the integration routine is not even called, but it's a simple matter of a sine voltage and a divider, therefore there cannot be any oscillations. No oscillations means there is no average, whatsoever, and the only waveform that should be seen is the 1 mV peak one. What's more, for the versions of LTspice after May 2019, if the normal trap solver is used, there are no artifacts, which only reinforces the idea that there are no oscillations and, therefore, there cannot be any artifacts due to averaging.
What is certain: the modified trap is mostly a post-processing applied to the waveforms. If there are oscillations, they still exist as the solver finds them, but they are not displayed due to this post-processing.
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H: How to measure coupling coefficient?
I have an EE core with one winding on one outer leg and a second winding on the other outer leg. I am measuring the inductance on one winding by having the other winding open and vice versa.
For the mutual inductance I am measuring the aiding series inductance (L_aiding = L_1 + L_2 + 2M) and opposing series inductance (L_opposing = L_1 + L_2 - 2M) and substitute these two to end up with M = 1/4 * (L_aiding - L_opposing) which gives me the mutual inductance.
Now I can calculate the coupling factor using the following equation: K = M / sqrt(L_1 * L_2).
The problem is with no airgap I get a coupling of around 0.2 and with a 0.4mm airgap I get a coupling of 0.32, which doesn’t make any sense, since an airgap would give me more leakage inductance hence a lower coupling coefficient.
What could I be doing wrong?
AI: What could I be doing wrong?
When the centre limb of the EE core is acting as a "short" route for the driven magnetic field, most of the flux bypasses the undriven coil and hence the coupling appears to be low. As you introduce a gap between EE halves, the "short" route becomes less viable more immediately than the route via the secondary coil. Both routes are of course less viable but, relative to each other, their respective reluctances get closer. This means that coupling will tend to increase as you add a small gap.
What you see is how I would expect it to be.
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H: Programmable On/Off micro-controller to switch a lighting module on command
Having a lighting module that uses an 12V (3.8A) adaptor with an integrated manual switch, what are the available options on embedding a programmable micro controller so as to turn on/off the light using an arduino-like software?
As a programmer, rather than an electrical engineer, I assume that I could use the simplest micro controller with a USB capability preferentially. Nevertheless, I am not quite sure over the available options that could potentially be adopted.
Any clues would be appreciated!
AI: I suggest using a microcontroller with WiFi built-in. It is very likely that in the future atleast, you might need internet connectivity for your application. Try to use the lowest cost microcontroller with WiFi that supports the programming environment you prefer. Use the lowest priced one because for your switching purpose, you don't need much processing power.
It's a good idea to use a relay to switch the light. The microcontroller controls the relay. Think of adding functionality to detect when the power is off (say due to a power-cut) and report that to the end-user. Use a battery so your microcontroller works for enough time to report the power cut and possibly monitor the supply for a certain period of time.
Don't forget to refer to the voltage and current ranges in datasheets of all components so you don't burn any component.
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H: Why SBC contain EEPROM?
I have nanopc t2 SBC, its software is open source. However, it has an EEPROM. Why? Do they put some confidential information on it? What if I plan to redesign that board, will I need the contents of the EEPROM?
AI: The EEPROM in the schematics, 24AA025, has unique MAC address as well, that can be used for Ethernet and WIFI. The EEPROM can be used as an extra space, if needed. Kernel and uboot goes in EMMC, not into EEPROM.
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H: Will an FPGA perform better when it has a higher gate count?
I noticed that some FPGAs have the same LUTs while they have very different gate counts. Will an FPGA perform better when it has a higher gate count? What are the extra gates used for?
I mean are those FPGAs with more gates can Carry more complex circuits?
AI: No. Probably marginally worse as a higher gate count implies a larger die and thus longer (and slower) signal paths. It will also have higher static power consumption making it less efficient.
Of course you can find corner cases where a specific size of design will only just fit a smaller FPGA and the resultant routing congestion makes it harder to fit all the signal paths in, where a larger device allows a more favourable (simpler and more straightforward) and thus more efficient layout.
Or a larger device allows a larger but faster design (e.g. more multipliers instead of resource sharing, or larger memories, or more parallel execution units) but all of these mean you are comparing two different designs.
So, basically no but it depends.
(All bets are off if the FPGAs are from different FPGA families : newer families can usually clock at higher speeds. But then it's the newer family that makes the difference, larger size is just incidental)
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H: What are the M and N values when modulation formats (QPSK,8QAM) are polarization multiplexed?
I always get confused in the terminology of modulation level (M) and number of bits per symbol (N). Please correct me if I am wrong. Because with these values, my question extends to polarization multiplexed versions of the same.
For BPSK, N=1 and M=2
For QPSK, N=2 and M=4
For 8QAM, N=3 and M=8
For 64QAM, N=6 and M=64
Then, how the N and M values change if they all are polarization multiplexed? I.e. PM-BPSK,PM-QPSK,PM-8QAM,PM-64QAM? I think we can send more bits in PM format now but for will the N,M values change? I need to substitute these in some formula for my work and so I need clarity on this.
AI: 2^N = M
Example:
In an 8QAM constellations you got N = 3 and M = 8.
N = bits per symbol
M = symbols
Given a modulation scheme, there are many different constellations.
They all differ from the mutual distance or angles.
Once the media is assigned (fiber, copper, air) you can design the best constallation for that media that minimizes SNR.
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H: How does a doorbell work?
I'm trying to make my own smart doorbell with the same wiring of our current doorbell, so I'm investigating how the bell work snow. I know how part of the bell gong works, but how does the bell button itself work (with light inside of it.) The gong is the Honeywell D117 and is connected like the picture. The button of the doorbell is the Nico 12V~1A (include light).
Is it correct that the light is in parallel with the switch and when pressing the button of the doorbell it closes the switch and closes the system? Isn't this a short circuit when you do this without any resistor in the circuit?
My new smart doorbell will be made with a Raspberry Pi so I need DC voltage for it. Would it work to add a transformer in parallel with a switch to replace the current button to a new system?
AI: How does a doorbell work?
The bell transformer supplies AC voltage, typically 16V but ranging from 10 to 24V, which is wired in series through the doorbell coil and the push button switch. When you press the button its contacts close, completing the circuit. Current flows through the coil, which pulls in the bell striker and rings the first 'ding' bell tone. Release the switch, a spring pushes the bell striker back where it strikes the 'dong' tone.
How much current? The doorbell coil has some DC resistance as well as reactance, both of which limit the current when the switch is closed: it doesn’t ‘dead short’. The coil impedance is in the 100-200 ohm range, so when it's energized at 16V the current is in the 80-160mA range.
The pushbutton light is wired across the switch contacts. Without the button pressed the light draws a small current (about 10mA) through the bell coil, enough to light the light but not enough to pull in the bell striker. This is an important detail: the light is a small, high-resistance bulb, its current draw set up to give a dim illumination without triggering the bell. Of course the light goes off while you're pressing the button.
How do I replace the bell with an R.pi?
If your intention is to replace the bell itself with your R.pi, then you need to do two things:
Make the R.pi 5V DC from the bell transformer AC.
Such converters are available and inexpensive. Example: https://www.amazon.com/SMAKN%C2%AE-Converter-Voltage-Supply-Waterproof/dp/B00RE6QN4U
Provide enough voltage to the switch to light the light, while sensing its closure with the R.pi
You still need a high enough voltage to light the switch light, so running it directly with R.pi 5V won't work: it'll be way too dim.
Instead, get a 12V relay, run the 16VAC through the relay coil to the switch wire. (This relay would do nicely: https://www.grainger.com/product/OMRON-General-Purpose-Relay-6C874) The relay will stay normally open, and will close when the button is pressed. If the relay closes because of the lamp alone, add a shunt resistance across the coil.
Then, monitor the relay contacts with the R.pi: when the button is pressed the relay should close.
Here's the general scheme:
simulate this circuit – Schematic created using CircuitLab
You've stated your intention to replace the doorbell button with R.pi. Ok, let's talk about that.
How does a ‘Ring’ doorbell work?
To use the existing transformer and bell, with only the switch being changed out, requires some careful design. The 'Ring' doorbell unit satisfies this requirement, needing only the switch wire connections that come to the doorbell button + light to do its thing. How? tl; dr: It's a complicated beast with its own battery and very tight power management.
Like that switch light, Ring uses only a small amount of this through-the-bell current. It can do this because Ring spends most of its time asleep in a very low-power mode. During sleep time, the small standby current from the bell coil charges an internal battery inside the unit and illuminates the button light.
Ring wakes up when it detects motion from a passive IR sensor array on the front of the unit. Once awakened, its camera, main processor and wifi turn on and do their thing, drawing current from its battery.
When the Ring button is pressed, it shorts out the switch wires, ringing the physical bell, while it continues to supply its own power from its battery.
To do all this, the Ring includes a bridge rectifier and voltage / charge controller that not only maintains the battery, but also limits the current draw to a level below which the bell will strike, just like that dim bulb in the mechanical switch button.
That’s the key to how it works: low standby draw charges a battery while the Ring is asleep, and the battery supplies power when it wakes up.
How do I replace the doorbell button with R.pi?
If your intention is to use the existing bell, transformer and wire pair for your own R.pi project, you have two choices:
(1) Do the same low-standby magic as Ring, using a battery
- or -
(2) Run a separate power pair to the R.pi
If you choose option (1), and you have some design skills, that would be a really neat project (though I'd choose ESP32 rather than R.pi.) That said, note that even Ring draws too much standby current for some bells, enough current to pull in the bell striker. To overcome this, Ring sells an accessory that shunts some current around the bell coil to supply the extra current. You could use this technique also.
On the other hand, if you don't want to take on that battery-power design challenge, and instead power the R.pi all the time with up to 5W, then option (2), running a second low-voltage AC pair directly from the transformer to a low-voltage AC to 5VDC converter would be more doable. Then, use a small relay controlled by an R.pi GPIO to emulate the button press and ring the bell.
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H: What type of wire can I use to run 5V, 30A to my Arduino controlled relay module over a distance of 10-12m?
I'm building an Arduino-controlled Christmas light show. I power my 16-channel relay module with a 5V, 30A supply. It is placed outside the house and I want to place its power supply powering the relays inside.
I will have to run a wire from my workstation (where I set up my controlling PC and Arduino) outside to the spot where I placed my relay module (it needs a 10-12m long wire.)
I'm afraid that if I use an incorrect type of wire unsuitable to handle 5V, 30A, it would burn the wire.
Is there any thin wire that I could run for 10-12m carrying 5V, 30A power? Is there any type of wire that is thinner but still handles the power?
(Edited: I only need it to power the relay module, not the Christmas lights.)
AI: If you're using the usual cheap "arduino relay module" it uses 70mA per relay, so 1.1A for 16 relays. So that's the current you'll actually need.
Basically any zipcord/lampcord/whatever wires around 1mm2 or more will do. I'd recommend using the usual "5V 2A" cellphone charger as a power supply. If you really want to use the 30A power supply, then you need to add a fuse on the 5V output so it doesn't melt the wires in case of a short.
That's assuming you're using the 30A power supply because you got it lying around but you're just powering the relay board with it.
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H: Drive DC motor from higher than rated voltage
I am designing a DC motor driver circuit with an H-Bridge and capability for PWM speed control.
The input DC voltage is coming from rectifying the mains voltage (127 Vrms), which gives me about 178 DC Volts to play with.
This circuit should be able to drive various types of motors, including ones rated for 180 V, 150 V and 90 V.
My question is if I need to include a buck converter to supply the correct voltages for the lower voltage rated motors, or if I could get away with using the PWM capability to drive them without exceeding their power rating.
AI: The input DC voltage is coming from rectifying the mains voltage (127 Vrms), which gives me about 178 DC Volts to play with.
With full-bridge, you get about 127V DC equivalent, and the peak at about 178V, considering possible max loading.
My question is if I need to include a buck converter to supply the correct voltages for the lower voltage rated motors, or if I could get away with using the PWM capability to drive them without exceeding their power rating.
In short, you do not need a buck converter, normally. PWM is simpler, easier to control, more energy efficient, cost effective.
Snake lags (Redundant):
DC Linear motor model is a resistor in series with a Voltage source (BEMF). Power rating is from the design factors of the motor, electrical and mechanical. In order to meet the mechanical spec (speed, torque, operating temperature, etc.), electrical parts are designed to be capable of driving the mechanism sufficiently, both with margin. Most of the time, dielectric insulation capability far exceeds the voltage spec. What can break with the voltage is to heat up the internal impedance (and junctions) by the current flowing through (thus the power).
Edited.
I have used direct bridge rectified 120V line to control 68V DC motor with PWM, decades ago. The "thumper" is still regarded as professional, not gonna break easily. What prevents motor damage is the control circuitry.
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H: RL-circuit using Laplace
I have a series RL circuit (with zero initial conditions) and I want to find the voltage across the inductor. The formula I got is:
$$\text{V}_\text{L}\left(t\right)=\int_0^t\text{V}_\text{in}\left(\tau\right)\cdot\mathscr{L}_\text{s}^{-1}\left[\frac{\text{sL}}{\text{sL}+\text{R}}\right]_{\left(t-\tau\right)}\space\text{d}\tau\tag1$$
Question: is this formula correct?
AI: Yes, the equation you gave is correct.
Please note that the uppercase letters are usually reserved for frequency domain and/or DC values. For time-varying signals such as an inductor voltage, the lowercase notation \$v_L(t)\$ is far more common than the uppercase notation \$V_L(t)\$.
The impedance of the circuit is
$$Z(s) = R + sL$$
The voltage on the inductor is:
$$V_L(s) = V_{in}(s) \frac{Z_L(s)}{Z(s)} = V_{in}(s) \frac{sL}{R + sL}$$
The impulse response is:
$$G(s) = \frac{sL}{R + sL}, \quad V_{in}(s) = \mathcal{L}\left\{\delta(t)\right\} = 1$$
where \$\delta(t)\$ is the impulse (Dirac) function. The \$G(s)\$ is also known as the transfer function.
In the time domain the impulse response is
$$g(t) = \mathcal{L}^{-1} \left\{\frac{sL}{R + sL}\right\}$$
The response to any input in the time domain can be found by convolution:
$$v_L(t) = v_{in}(t) * g(t) = \int_{0}^{t}{v_{in}(\tau)g(t-\tau)d\tau}$$
The only catch is that the system must be linear and time-invariant (LTI). The convolution integral will not work if you have nonlinear elements in your circuit, eg a diode etc.
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H: How long does it take for energy to propagate in a circuit?
The premise
In a recent video by the pop-sci channel Veritasium, the concept of the flow of electricity and energy transmission in a circuit was discussed. In that video a thought experiment is presented, as seen below. The question is: after the circuit is complete, how long will it take for the lamp to turn on?
The video concludes that, after the switch is flipped, the lightbulb will turn on after 1/c seconds (1 meter divided by the speed of light), since the lamp and the battery are 1 meter apart. This is explained by showing that, in an electrical circuit, energy is transmitted through an EM field, which propagates at the speed of light, and not through movement of particles in a conductor.
This explanation did not sit right with me, for mainly two reasons:
Clearly, the conductor plays a role in the transmission of energy. This is actually pointed out in the video as well, by saying that after a connection in a circuit is made, the EM field will propagate along the conductor at the speed of light. To me, this would mean that the field would take 1s to propagate through the cables in the thought experiment, and the lamp will turn on after 1s.
For the lamp to turn on, current must flow through it, heating the filament. Simply being in an EM field generated by the battery would not work, there needs to be some potential difference at the lamp's terminals. The signal doesn't "know" what happens at the load until it reaches it. This is a big part of reflection in signal and transmission lines, yet seems to be ignored here. Therefore, the voltage will take 1s to arrive at the lamp in this case.
The question
Is the answer of 1 meter/c seconds correct, or should the answer be something else? If the answer is not 1 meter/c, where does the mistake in the video's reasoning lie?
AI: Veritasium hasn't gone into the vital detail. I'm not sure whether that was because he didn't want to complicate the answer, or because he didn't do enough research.
The important part is that the two 300 km loops of wire are transmission lines.
For the first second after closing the switch, before the reflection gets back from the far end, you could replace those lines in the circuit by resistors equal to their characteristic impedance.
The impedance of a line with two thin conductors 1 m apart will be quite high, many hundreds of ohms, perhaps 1 kohm. The two lines would therefore limit the current into the lamp to a few mA for the first second. If the lamp could operate with that low current, then it would turn on after 1 m/c following the switch closure.
Things get more interesting, and complicated, when a reflection arrives back from the short circuit at the far end. The detail of what happens rather depends on the impedance the lamp presents to the returning reflections. In the simplest case with the lamp matched to the line impedance, the reflection will be absorbed, and the lamp will now operate as if the lines are short-circuited. If the lamp isn't matched, then there will be a further reflection, and further changes of lamp brightness, until the waves propagating on these lines eventually die away.
The many problems this type of video has include:
One thing he says is true, energy 'flows' around the wires, not through them
but his demonstration doesn't show that
and his demonstration is not a real experiment, it's faked
He makes an assumption about zero resistance, which is not in itself a problem, but it does mean that any attempt to reproduce what he has done without superconductors is impossible
and it confounds the intuition of most non-technical viewers who insist the waves would die out on the long line, which they would on a resistive one
Why the lamp would light, a bit, immediately, is just straightforward transmission line theory
but he has the orders of magnitude all wrong
and the impedance to ground would be just as significant as the lines' impedance to each other, so trying to simulate exactly what he has there would be a) complicated and b) would not show what he's trying to demonstrate.
and without a definition of the lamp impedance, what happens when the reflection returns would be uncertain
The transmission lines he shows in the video demo area are better coupled to the ground than each other, which will further confuse how that area would react
but the lines in the diagram going out into space are clearly isolated from ground
Which assumption to make? I have chosen that the lines are isolated from ground, which makes for a simpler thought experiment, without changing the fundamentals. MathKeepsMeBusy makes the non-isolated assumption, which is why he gets such a different answer to me.
In the words of Wolfgang Pauli, Verisatium's demo is not even wrong, it's worse than that.
An experiment, a real physical demonstration, to show the delay of a transmission line would be better done with some well-defined commercial transmission line, ideally 50Ω coax, but some 300Ω open wire antenna wire would also serve and be far closer to the open wires he has used. With the length cut to a few metres or 10s of metres, the resistance would be small, small enough to ignore, but an oscilloscope would be needed to show the microseconds delay. With the line lofted to several metres, it would be sufficiently isolated from ground for my assumptions on isolation to hold and be shown.
I'm not sure I could think of an experiment to 'demonstrate' that energy flows outside of the wires, but it's fairly straightforward to argue that it either does, or that an assumption that it does is consistent with what we see. The Poynting Vector requires electric and magnetic field to create the energy flow. Considering two wires between a battery and a lamp, the battery provides the electric field between the conductors. Only when a current flows do we get the magnetic field between them. I referred to this phenomenon in another answer as a 'power guide' (cf wave guide), as the wires guide the current, and the magnetic field they produce cross the electric field transmits the energy.
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H: Average value and RMS value
I am trying to understand the concept of RMS value.
From whatever I have read and the tutorials I have seen, I have seen them derive the RMS value only considering the first positive half cycle of the periodic wave. Why is this?
Why don't they consider the second half cycle (which is either negative or decreasing to zero) while arriving at the RMS formula?
Second question, while considering the AC sine voltage , how does it effectively produce power when you have both positive and negative half cycles? Won't they cancel each other out?
AI: From whatever I have read and the tutorials I have seen, I have seen
them derive the RMS value only considering the first positive half
cycle of the periodic wave. Why is this?
Let's consider a few numbers such as {2,3,5}. Mean of these numbers (aka average) is:
(2+3+5)/3 =10/3
Now consider the average of {2,3,-5}. It would be (2+3+(-5))/3 = 0
Think of a periodic signal (e.g. sin wave) as a sequence of numbers.
If you were to sum these numbers for a half cycle and calculate the mean and it would be a positive number. But if you added these numbers for the full cycle, then it would be exactly zero. For the continuous case, you do an integration instead of a sum. The concept is the same though.
Why don't they consider the second half cycle (which is either
negative or decreasing to zero) while arriving at the RMS formula?
But what if a phenomenon (such as an ac voltage) was useful in both directions and we still wanted to find its effectiveness. Clearly a simple average won't do in the presence of negative quantities. So the points are squared to make them positive, mean is calculated, and then it is squared (and read backwards to give us rms).
rms of {2,3,5} would be Sqrt ( (2)^2 + (3)^2 + (5)^2 /3 ) = Sqrt[38/3]
What about rms of {2,3,-5}: The rms would still be Sqrt[38/3) since the negative quantity would be squared turning it into a positive quantity.
For a sin wave (for example) the following integral would integrate (or sum) from 0 to \$2\pi\$, find the mean by dividing by \$2\pi\$ and then get the square root to get \$\frac {1} {\sqrt {2}}\$:
$$\sqrt{\frac{\int_0^{2 \pi } \sin ^2(x) \, dx}{2 \pi }}$$
You can do this calc this for a half cycle (and divide by \$\pi\$) to get the same result as the two halves are identical, but you can't do it for an asymmetric shaped signal.
Second question, while considering the AC sine voltage , how does it
effectively produce power when you have both positive and negative
half cycles? Won't they cancel each other out?
Think of an AC voltage as a force that vibrates electrons (for instance) in either direction at 50 or 60 Hz (most common values). Energy is transferred through the wire and the electrons in the metal wire pretty much stay in the same place.
How much DC voltage would be required to get the same energy to transfer is going to be the rms value of the ac voltage.
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H: Suggestions to clarify comparator circuit
I'm confused with the next issue from school that I can't figure out and wasn't able to solve (this is homework already graded, but the teacher refused to explain me).
I was asked to design and implement a zero crossing detector using an op-amp (any op-amp, even the 741). I understand there are several ways to do this with opto, transformers,etc.
But the real issue was that this device must be able to detect the zero crossing and when the signal is at 90 degrees (in the positive and negative cycle).
So I made the circuits but separately. As in the next window detector:
(between 4.5 V and 5.5 V ) and
A non-zero level detector modified with the DC voltage source set to zero volts. If the sin-wave input voltage (Vin) is less than (Vref), the output remains at the maximum negative level. When Vin exceeds Vref, the output reaches its maximum positive value.
But if the output of the window is passed to the level detector it gets wrong result, since the level detector isn't a sinus signal but the square one, so how must they be wired together to make the 2 functions at the same time?
And is it valid to apply superposition to get the transfer function?
Thanks for your help.
AI: Homework guidance: If you cause 90 degrees phase lag to the sinusoidal input by feeding it through an integrator you can use another zero crossing detector to show when the input is on its plus or minus peak.
In theory a differentiator would also do the trick, but it amplifies easily noise; needs band limiting. But it doesn't need DC free input like an integrator which would get saturated if there's DC.
Integrator has a drawback, too: It in practice drifts even with no DC in the input signal. Opamp non-idealities are the main causes of the drifting. 741 is not the finest selection in this sense. Offset voltage error is the same as a DC component in the input. Input bias current is another cause for drifting. The capacitor needs a discharging resistor which hopefully can be big enough. Otherwise it causes phase error.
A multistage RC filter can be designed to cause 90 degrees phase shift, but that works only at a fixed and known frequency.
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H: What is the difference between making a resistor based keypad and not using a resistor on arduino?
I've seen videos on youtube about how to emulate a keypad on arduino. Some of them includes a resistor while others do not. What are the difference between them and are there advantages in doing one over another?
AI: Since the Atmega has internall pull-up resistor (50k) on Pins there's no need to use external resistors until you need to meet some special criteria. Just enable pull-up resistor on Pin you are going to use, connect button between this Pin and Gnd and look for signal Low in software.
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H: 3-phase star transformer connection with no neutral for wind turbine
I built a wind turbine a while back and have been using it to power lights in my house. It gives out 3-phase in star setup with no neutral. Neutral is buried in epoxy resin in the casting.
It feeds into a three phase rectifier down at the house and charges batteries. Generates 500 W peak.
I recently got my hands on a good number of single phase toroidal 400 W each transformers. I want to use them to step up the voltage at the base of the pole and step back down at the far side as it is a long distance (100 meters) and might give less voltage drop with higher voltage using these.
How can I connect these? Any diagrams I see online seem to require the neutral to be available.
AI: The transformers are to be 'star' connected using the 16 V secondaries.
Maximum transmission voltage would be about √3 times the transformer primary (mains) voltage.
It would be needless to connect the neutral points.
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H: 2-pin vs 3-pin plugs
Some basic questions around electricity to clarify some concepts
Why are some plugs have 2 pin while others have 3 pin? I know that 3rd pin is ground but I struggle to understand its purpose.
In a 2-pin, is one pin positive and other negative? I suppose not but just checking as at homes, we have AC power so positive/negative doesn't make sense (because the positive/negative continuously alternate I believe).
What type of devices use a 2-pin plug and what type use 3-pin plug? Could any device be connected with either of these without any issues?
AI: Ground pin, or earth, is used for safety. E.g. a computer has metal case and it is grounded via mains plug. If inside computer power supply some part malfunctions and mains live voltage gets in contact to computer case, then it will have a safe path to ground and it will blow a fuse. Without ground the metal case would be at live potential and it would be dangerous to touch it.
No, not positive and negative. There is neutral wire, which is at ground potential, and live wire, which has AC voltage.
Some devices are double insulated so they can use 2 pins safely. Some devices are not and they need 3 pins for safety. 2 pin devices can be connected to either socket, but it will be unsafe to connect 3 pin devices to 2 pin socket without ground.
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H: Not understanding how the output is forming because of the diode
I'm rather new to electronics and I don't understand how the output is formed in this question:
I'm providing an input (Vin) of 5V peak-to-peak sine wave with a 1kHz frequency.
I simulated this in LTspice but I did not expect the output to be anything like that (picture of waveform below.)
The thought process I used was: The diode will be forward biased whenever Vin is 0.6V with respect to ground and the output voltage will be 0.6V. When the input is below 0.6V and in its negative half cycle, the diode will be reverse biased and the current flows through the resistor and Vout is the same as Vin. However, once Vin reaches it's maximum negative value of -2.5V, the capacitor starts discharging and Vout becomes exponential in nature and this continues for each cycle.
The output I got was completely different:
Output waveform (green) imposed over Vin (blue)
Can someone please explain where I went wrong?
AI: It's true that the output can never exceed 0.6V, but you have neglected the action of the capacitor with that constraint.
Ignoring the resistor for now, whenever \$V_{IN}\$ rises above 0.6V, to its peak value of \$V_{IN(MAX)}\$, the capacitor will charge up very quickly to \$V_C = V_{IN(MAX)} - 0.6V\$.
That's a DC charge that remains there even when \$V_{IN}\$ drops back below its peak value.
Consequently, as \$V_{IN}\$ falls again, so that \$V_{IN} < V_{IN(MAX)}\$, the output potential \$V_{OUT}\$ is now lower than \$V_{IN}\$ by an amount equal to whatever voltage \$V_C\$ the capacitor initially charged to.
Also, when \$V_{IN} < V_{IN(MAX)}\$, the diode never again becomes strongly forward biased, and no longer plays a role.
Following that first excursion of \$V_{IN}\$ to its maximum \$V_{IN(MAX)}\$, which caused the capacitor to charge to \$V_C\$, the diode is mostly reverse biased, and the relationship between \$V_{IN}\$ and \$V_{OUT}\$ becomes:
$$
\begin{aligned}
V_{OUT} &= V_{IN} - V_C \\ \\
&= V_{IN} - (V_{IN(MAX)} - 0.6)
\end{aligned}
$$
If you examine that expression carefully, you'll see that this means the input signal is shifted down in potential exactly enough for its peaks to just touch +0.6V.
While that may not be what you intended, it is interesting to note that by flipping the diode polarity, you can shift an output to sit on top of -0.6V:
simulate this circuit – Schematic created using CircuitLab
This works because the capacitor is charged with the opposite polarity, when the input goes to its most negative potential. Now the capacitor becomes a permanent positive DC offset to the input.
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H: Is there an AC to DC converter in LED strings used in home
In this basic electric circuit, current from DC power source goes to positive leg of an LED and then back to the battery
So LED is working on DC current.
But homes have AC power. Then how do the following LED strings work? Do they convert AC to DC first?
AI: The LED string in your image should have some sort of power adaptor supplied with it. This will usually be in the form of a capacitor dropper followed by a rectifier. The circuit may show various degrees of refinement.
Input surge resistor to limit the inrush current.
Discharge resistor across the capacitor
Full wave bridge rectifier to increase the flicker frequency from 50 to 100Hz (or 60 to 120Hz)
A smoothing / reservoir capacitor to reduce flicker further.
If you look on YouTube for "Big Clive", he has published numerous videos where he tears down LED lighting and explains the power supply circuits in detail.
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H: 12V DC to DC converter used in place of solar charge controller
I bought this product to use as solar charge controller.
My circuit consists of:
12V solar panel (5A?) -> 12V (DC->DC) voltage converter -> 12V 35Ah SLA battery
The converter says its input is 20.9V from the panel, and its output is set to 13.7V, which is float voltage on the battery. That's all expected.
When I connect the converter output wires to the battery leads, the converter output voltage drops to 12.8V, and its input voltage 12.9V. This doesn't make sense to me.
The current on the converter goes from 0.00 to 0.08 when I connect to the battery, and I can't adjust the current. I would expect the current into the converter to be around 5A or more since my panel is at least 5A.
Can someone with electronics knowledge explain why:
converter shows input voltage drops from 20.9V -> 12.9V when I connect its output wires to battery?
converter shows only goes from 0.00A to 0.08A when I connect its output wires to the battery?
AI: A plain DCDC converter is neither suitable as a load for solar panels, nor should you charge a battery with it (fire hazzard). To sink current from solar cells, you should use a MPPT capable converter and you need a charge controller to charge batteries safely. There exist devices which have both features combined.
A "solar charger" is much more than a buck converter.
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H: LED indicator controlled by MOSFET
I was just looking at a reference design and I can't see how this simple circuit makes any sense:
It uses an EVERLIGHT LED and an NTZD3154N dual-transistor:
I couldn't find the operation point of the circuit.
Given that VGS = 1.8V, the VDS should be small enough not to burn the LED.
For VGS = 1.8, I see that for small VDS's, the current exceeds 1A which is a lot.
How can this make sense? The graph of the diode shows forward voltage in the range of [0mA - 50mA], and on the other side we have a transistor that passes a lot of current with such huge VGS.
What am I missing here?
Update:
Considering the answers I got, 20mA of current means the resistor has VR = 2V, the Anode gets 1.3V, and assuming VF=2V it means the cathode will be -0.7? how does it make sense that the cathode which is the VDS of the transistor is negative? did the source and drain here switch sides?
AI: Rds(on) with 1.8V drive is typically 0.7 ohm. So you have an LED with 100.7 ohms in series when the MOSFET is on.
Whether it's 0.7 or 0.9 or 0.5\$\Omega\$ the LED current and brightness will not vary significantly. So the MOSFET does the switching and the resistor controls the current.
To determine the current, draw the load-line of the 100 ohm resistor and 3.3V supply on the nonlinear LED curve and look for the intersection:
The load line goes from 3.3V with zero current to 3.3V/100\$\Omega\$ = 33mA with zero LED voltage.
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H: Why would you place a resistor in series before AND after a diode (see simple circuit)?
For an assignment we had to first simulate a circuit (first with a Schottky then with a rectifying diode) in LTSpice and then do measurements on an actual circuit before answering a few questions. Below are the schemes of the simulated and measured circuits:
To the questions
"How is the current limited?"
That seems pretty clear, Rg is acts as a ballast resistor to limit the current across the diode
"What is the purpose of R2?"
With this one I´m having troube... Rg ist already acting as a current limiter. I've read that it does not really matter whether you place your resistor before of after the diode, so I don't know why you whould do both... Also I suspect the purpose of Rg and R2 is different because R1 is noticeably larger in value than R2.
Am I missing some important detail?
AI: Your schematic suggests that you are being asked to apply an oscilloscope set into X-Y mode (one of the channels will have a large X written near it, for example.) This is where one of the input channels on your scope replaces the internal time-base section. (It's interesting to see a comparison of X-Y mode usage with analog vs digital scopes.)
If you are using an oscilloscope set into X-Y mode and assuming you've got the triggering working well enough, then you should observe a repeated curve that starts low (on the y-axis) at the left and shows a rising exponential curve of sorts heading towards the right side of the scope.
Rather than go to all the trouble of building it and taking a photo, I'll cheat a little and use LTspice in X-Y mode to show you what I mean using two different diodes:
I've overlapped two different diode curves onto one screen. You won't be able to do that with your setup. But LTspice lets me switch diodes quickly, so I can do it with that software program.
The reason for the \$1\:\Omega\$ resistor is that it makes it very easy to estimate the current in the diode for any voltage across it (because you just divide by 1.)
In case it matters, you can see how I approximated your schematic in LTspice:
|
H: Can I leave a throughole pad off one side of a machine-fabricated PCB?
So I'm designing a two-layer PCB and I'm very inexperienced. A third-party company will fabricate them.
Now, I have a PTH part with a number of closely spaced pins (and there is no SMD equivalent of this part). I can greatly simplify routing by running traces between certain pins. However, I can't do this unless I eliminate the pads for certain pins on one side of the board (to make clearance for the trace).
If I do this, that means that for those pins, only one side of the PCB can get solder even though the pin will stick through. So my question is: Given that this board's fabrication, population, and soldering is automated, can I leave pads off of one side of a PTH connection and run traces near it without issue? I guess I'm kind of imagining like, solder leaking through the holes or some weird mechanical issue with the partially-supported pins.
Or should I just come up with a more complex routing that doesn't pass in between closely spaced pins? Or ... maybe I can just eliminate like half the pad on one side of the board or something like that? Or, is there a different fabrication process that I could look for? I just don't really have any concept of the quirks that come up in fabrication, so I can't really make a good judgment call.
Unsure if relevant but expected operating temperature range is 0 - 40 °C, varying moisture (exposed to outdoor humidity but not rain water). No significant mechanical shocks or stresses expected (the board does have some jacks on it but they're all strain relieved with mounting points).
AI: I asked the inspection person here (I work for a contract manufacturer) and I was told that it will be flag as a defect if inspected by IPC-610 (Class 1,2 or 3). So what you're trying to do is not acceptable. Damage to one of the pads (top or bottom) is also a defect.
I have seen boards where the pad is not a perfect circle (like an ellipse) to make space for traces to go in between. This seems acceptable.
|
H: Does the 1x oscilloscope probe setting slow down MHz digital signals?
I was debugging what I thought was a weak LVDS driver fed with a 10MHz clock for hours when, out of other options, I've set my scope probes to x10 and although the signals were showing some ringing they looked fine otherwise.
Which should I trust, and if I should trust the x10 reading, why do the scope probes flatten the signal like that?
Here is what I am talking about:
With x1 setting:
With x10 setting:
Note1: The clock is active by groups of 8 cycles so the pause is normal.
Note2: Both probes are calibrated on the internal calibration signal of the scope.
Note3: As can be seen on the second snapshot, the coupling is DC and no bandwidth limiting is configured.
Note4: The signals are generated by the DS90LV027 and not connected to anything (not even a termination resistor). It's supposed to have less than 1ns rise time.
Note 5: Oscilloscope probes = PP510
AI: Not only does the probe have lower bandwidth when in 1:1 mode but there is much greater capacitance load on the source when in 1:1 mode.
That extra capacitance will significantly lengthen the rise and fall times.
I couldn't find the probe bandwidth in the Siglent documentation but the input capacitance is about 100pF in 1:1 mode compared with about 20pF in 10:1 mode.
This is because the 10:1 attenuator is in the probe head itself so the input signal does not have to drive the cable capacitance with the full signal. In the case of the 1:1 probe the input signal has to drive the cable capacitance (20-30pF/foot) plus the input capacitance of the scope itself (usually 15-20pF).
P5510 Brochure
This reseller of the Siglent product gives the bandwidth of the 1:1 position as 6MHz in the 1:1 setting.
P5510 bandwidth in 10:1 and 1:1 setting.
I only use the 1:1 setting with small signals that need the most sensitive capability of the scope. Even there I often use a direct wired coax rather than the scope probe as it is can give better signal integrity and reduce noise coupling from other sources.
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H: MOS Capacitor band diagram question
In a MOS system, is the energy offset between metal/oxide or semiconductor/oxide always the same regardless of the gate voltage applied? In other words, are A and B in the diagram above always the same? I think the offset must be always the same since it is determined by the material property (difference between work function of the material), but I see people draw this band diagram under bias as if these offsets change.
AI: A is always the same because it depends only on the metal..oxide work function.i B depends on the accumulation/depletion at the oxide..semconductor interface, so changes (until there is accumulation).
The slope through the oxide changes with applied V, so the amount by which B is above A changes.
In addition, as the V changes, the semiconductor part's depletion region widens, or thins to just an accumulation layer. The curved part in the semiconductor will change with those conditions.
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H: Uses of IC Logic Gates in Microelectronics
My question concerns the following ICs:
AND, OR, NAND, NOR, XOR, XNOR
Voltage Translating Gates
Buffers
Drivers
Translators
I understand what (1)s do, but what are simple uses for them? I have no idea what (2), (3), (4), and (5)s do. I have already researched a little but as for uses for them I'm not sure. Examples with microelectronics in mind would be helpful (imagine a student sitting at a table with an Arduino, breadboard, jumper wires, these ICs, resistors, and LEDs).
I got these from https://www.ti.com/logic-voltage-translation/overview.html
AI: The gates produce a logic state on their outputs according the inputs. They was used mainly in the past (1970, 1980), example in elevators where you control the floor number according button press but only after some condition is meet like closed door. Today's they are replaced with FPGA, microcontrollers.
Voltage Translating Gates are used to ensure voltage level compatibility between two circuits. Example: Control 5V device with 3v3, etc..
Buffer serves to decrease the impedance of a signal. Consider circuit gives you output with too high impedance to work/load in next circuit. Just place a buffer between them and you have "fresh"/strong signal on the input of second one.
Drivers are used to control high power devices like Power Mosfets/SCRs with low voltage logic like 3v3. The Mosfets needs about 15V to control the Mosfets gates what's makes an impossible with 3v3. The driver gives you a sufficient voltage and current level on it's output to control Mosfets properly.
The same as 2) , but this expression is sometimes used to ICs making a translation between protocols/communication interfaces, like I2C to SPI and so..
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H: What are technical challenges of implementing DRAM memory modules on SBC like Raspberry PI?
I'm surprised to see no Single-Board Computer including Raspberry PI has memory modules for allow for flexible amount of memory (e.g. this review). And I have not found such discussions via web search, for PI I've found only that post on PI site Improve RAM with a laptop's memory module:
No, not possible. The Pi does not have a memory socket of any
description - memory is soldered to the board.
No comments why, no comments whether it is in plans. I understand form factor is not large and it is densely packed already, but as amount of DRAM is important to many (IMO), why none of producers make at least one model with a removable SO-DIMM module? Any particular technical challenges?
AI: Largest technical challenge is the lack of infrastructure.
Many SoCs support only LPDDR memories and do not support standard DDR memories, so there are no existing sockets or memory modules you could use to add memory.
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H: Verilog code for adder shows unknown results (X) for some reason
I wrote this code, and it doesn't give a known value for the sum (S[15:0] in the waveforms). Why is that?
Design:
module fourBitAdder (input [3:0] A, B, input cin, output [3:0] S, output cout);
wire [4:0] c;
wire [4:0] S0;
assign c[0] = cin;
assign cout = c[4];
assign S0 = A + B + cin;
assign {cout, S} = (S0>9)? S0+6 : S0;
endmodule
module fourBitAdder11 (input [15:0] A, B, input cin, output [15:0] S, output cout);
wire [16:0] c;
fourBitAdder FB0 [3:0] (A[3:0], B[3:0], c[3:0], c[4:1], S[3:0]);
fourBitAdder FB1 [7:4] (A[7:4], B[7:4], c[7:4], c[8:5], S[7:4]);
fourBitAdder FB2 [11:8] (A[11:8], B[11:8], c[11:8], c[12:9], S[11:8]);
fourBitAdder FB3 [15:12] (A[15:12], B[15:12], c[15:12], c[16:13], S[15:12]);
endmodule
Testbench:
module Test_fourBitAdder;
reg [15:0] A, B;
reg cin;
wire [15:0] S;
wire cout;
wire [16:0] c;
fourBitAdder FB0 [3:0] (A[3:0], B[3:0], c[3:0], c[4:1], S[3:0]);
fourBitAdder FB1 [7:4] (A[7:4], B[7:4], c[7:4], c[8:5], S[7:4]);
fourBitAdder FB2 [11:8] (A[11:8], B[11:8], c[11:8], c[12:9], S[11:8]);
fourBitAdder FB3 [15:12] (A[15:12], B[15:12], c[15:12], c[16:13], S[15:12]);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
A = 16'h1234; B = 16'h4567; cin = 0;
#20 $finish;
end
endmodule
AI: You get X's because you have problems with your module instance port connections.
You are using connections-by-order, which can be error prone.
In your module definition, S is before cout, but in your instance lines,
cout is before S. You could switch the order, but it is better to use
connections-by-name to avoid this common Verilog error.
Another problem is that you use an array of 4 instances for a total of
16 instances of fourBitAdder; however, you only need a total of 4 instances.
You can omit the arrays.
You only need 5 carry bits, not 17, and you need to connect the cin signal. Here are the changes:
module Test_fourBitAdder;
reg [15:0] A, B;
reg cin;
wire [15:0] S;
wire [4:0] c;
assign c[0] = cin;
fourBitAdder FB0 (.A(A[ 3: 0]), .B(B[ 3: 0]), .cin(c[0]), .S(S[ 3: 0]), .cout(c[1]));
fourBitAdder FB1 (.A(A[ 7: 4]), .B(B[ 7: 4]), .cin(c[1]), .S(S[ 7: 4]), .cout(c[2]));
fourBitAdder FB2 (.A(A[11: 8]), .B(B[11: 8]), .cin(c[2]), .S(S[11: 8]), .cout(c[3]));
fourBitAdder FB3 (.A(A[15:12]), .B(B[15:12]), .cin(c[3]), .S(S[15:12]), .cout(c[4]));
initial begin
$dumpfile("dump.vcd");
$dumpvars;
A = 16'h1234; B = 16'h4567; cin = 0;
#20 $finish;
end
endmodule
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H: What are the caveats in this circuit design?
My question relates to the circuit in the image below. I have a non-inverting amplifier that generally will need to operate as a buffer (voltage follower) after a low pass filter to give a low impedance output that I can use elsewhere. In certain situations, the input to this op amp (U4) is low enough that it would be beneficial to amplify this signal (around x10 based on resistors chosen below). To accomplish this, I had the idea to put an N-channel MOSFET in the feedback loop that I can switch on and off with a digital control (from uC, button press, etc.). When switched on, the Rds is low (140 mOhms for the specific FET I'm looking at using) resulting in a gain of essentially 1. When switched off, the Rds is very high, making the feedback resistance nearly equal to R13 and changing the gain to approximately 10x.
Is this an acceptable way to accomplish this? Is there a better way to do it? Potentiometers or switches are out of the question as I need a way to control with a microcontroller output in some instances.
Then there's a follow up question to the circuit. What if instead of merely turning FET on and off, I sent a PWM signal into the gate? With a low pass filter after the output of the op amp, changing the duty cycle would give me a variable gain between 1 and 10. As simulated in LTspice, this seems to work, with a few caveats:
Cutoff frequency of the low pass filter after the output looks like it needs to be about 100 times lower than the PWM frequency in order to get a low-ripple output. PWM frequency is limited by my microcontroller speed. In my particular case, this isn't a problem at all. If I can pass through even 50 Hz, that's plenty.
The input signal can't be larger than 1/10 (less a bit) of the positive rail of the op amp to get consistent results.
I thought it was a kinda cool idea, and it simulates well enough in LTspice, but didn't know if there was maybe a better way to accomplish this, or maybe there's something I'm missing that would come back to get me later when I actually tried to implement it. I appreciate any and all feedback that you have.
AI: The best option to start is a decent transmission gate/analog switch IC. Barring that, the FET as proposed is theoretically workable but raises some concerns (some here, some in comments)
Switching the FET in and out seems plausible, as long as your control signal can reach to at least the negative rail and past the positive rail. As long as the gate voltage is well above the highest voltage expected on the op amp output, you have a nice comfortable triode operation where the FET is shorted.
However, if your output voltage reaches high enough to turn the FET off when it's meant to be on, your gain goes up as the FET resistance increases, so the gain increases and you lose control of your circuit. Even if it doesn't turn completely off, you've added a new behavior into the feedback loop which might lead to instability or poor performance, so it's best to keep the MOSFET firmly in triode with the gate well above the highest voltage you could see.
You'll also need to keep the body diode of the FET in mind, since you have a discrete FET with source and body bonded together. Because your output stays >= 0 V, this shouldn't be a major issue, but if you start working with signals that go negative you'll need to revise the design.
I'd budget at least one Vgson drop above the positive rail, which you could probably do with a 5 V square wave and a charge pump circuit consisting of a few diodes and ceramic capacitors. A second FET would then either pull the gate of M1 down or not, while a pullup resistor connects it to the charge pump.
An alternative approach would be a transmission gate, if you're able to create two complementary control signals that swing all the way to the positive and negative rails. An integrated transmission gate IC will also avoid the diode issue outlined above.
As for the PWM idea, I am skeptical of its accuracy but can't conclude that it's a poor idea for certain. Op amps have a limited and not-always-symmetric slew rate, which could compromise the accuracy of your result, especially as your PWM gets faster. If you do want to explore this further in simulation (rather than experimenting with a prototype) make sure your op amp model adequately models slew rate and other large-signal behaviors.
Finally, if a commercial off-the-shelf variable gain amplifier (either cascaded with your op amp, or replacing it altogether) can meet your specs, that's probably going to be a simpler idea to implement and qualify.
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H: Solution Verification: Thevenin Equivalent with Dependent Voltage Source
I am currently self-studying through MITs 6.002 Spring 2007 course. There are currently no solutions for the assignments afaik. Normally, this isn't an issue, but I am having some trouble with this Thevenin equivalent problem. I was hoping to get a pointer as to why and how my analysis is incorrect.
The question asks us to determine the Thevenin equivalent of the following circuit, where \$\alpha\$ has units of Ohms.
My solution attempt is as follows:
To find the Thevenin resistance \$R_{TH}\$, we treat the current source as an open circuit. Since the dependent voltage source has a voltage given by \$\alpha\$, we know that the resistance through the dependent voltage source is \$\alpha\$. Thus, calculating the resistance from the positive terminal, we see:
$$
R_{TH} = \frac{1}{\frac{1}{R_2} + \frac{1}{R_1 + \alpha}} = \frac{(R_1 + \alpha)R_2}{R_1 + R_2 + \alpha}
$$
Next, my intuition is to short the output terminals and determine the current between the terminals as \$I_N\$. We can then multiply by \$R_{TH}\$ to find the Thevenin voltage \$V_{TH}\$.
To do this, I treat the negative port as ground and apply KCL to the current flowing into the "ground node".
I need to determine the branch current through \$R_2\$ first. Considering the node where the dependent voltage source meets the positive output terminal, I believe that the following is true:
$$
i + I_{N} = i_2
$$
where \$i_2\$ is the current flowing through \$R_2\$.
So, putting together these 4 currents, I think we can correctly say the following about the ground node:
$$
-I_0 + i + (i + I_N) + I_N = 0 \\
\implies I_N = \frac{I_0 - 2i}{2}
$$
(At this point, I think something is wrong with my analysis...)
Thus,
$$
V_{TH} = I_NR_{TH} = \frac{I_0 - 2i}{2} \frac{(R_1 + \alpha)R_2}{R_1 + R_2 + \alpha}
$$
EDIT: I did not realize that a dependent voltage source also has no internal resistance (since it is an ideal), and thus the short circuit is obviously just \$I_N = I_0\$.
AI: First, I will present a method that uses Mathematica to solve this problem. I know that this approach is not 'smart' but this method will work all the time, even when the circuit is way complicated than this one. This makes my answer valuable in my opinion.
Well, we are trying to analyze the following circuit:
simulate this circuit – Schematic created using CircuitLab
When we use and apply KCL, we can write the following set of equations:
$$
\begin{cases}
\text{I}_0=\text{I}_1+\text{I}_4\\
\\
\text{I}_4=\text{I}_2+\text{I}_3\\
\\
\text{I}_5=\text{I}_2+\text{I}_3\\
\\
\text{I}_0=\text{I}_1+\text{I}_5
\end{cases}\tag1
$$
When we use and apply Ohm's law, we can write the following set of equations:
$$
\begin{cases}
\text{I}_1=\frac{\text{V}_1}{\text{R}_1}\\
\\
\text{I}_2=\frac{\text{V}_2}{\text{R}_2}\\
\\
\text{I}_3=\frac{\text{V}_2}{\text{R}_3}
\end{cases}\tag2
$$
And we also know that \$\text{V}_2-\text{V}_1=\text{n}\cdot\text{I}_1\$.
We can use \$(2)\$ and \$\text{V}_2-\text{V}_1=\text{n}\cdot\text{I}_1\$ in order to rewrite \$(1)\$:
$$
\begin{cases}
\text{I}_0=\frac{\text{V}_1}{\text{R}_1}+\text{I}_4\\
\\
\text{I}_4=\frac{\text{V}_2}{\text{R}_2}+\frac{\text{V}_2}{\text{R}_3}\\
\\
\text{I}_5=\frac{\text{V}_2}{\text{R}_2}+\frac{\text{V}_2}{\text{R}_3}\\
\\
\text{I}_0=\frac{\text{V}_1}{\text{R}_1}+\text{I}_5\\
\\
\text{V}_2-\text{V}_1=\text{n}\cdot\frac{\text{V}_1}{\text{R}_1}
\end{cases}\tag3
$$
Now, we can set up a Mathematica-code to solve for all the voltages and currents:
In[1]:=Clear["Global`*"];
FullSimplify[
Solve[{I0 == I1 + I4, I4 == I2 + I3, I5 == I2 + I3, I0 == I1 + I5,
I1 == V1/R1, I2 == V2/R2, I3 == V2/R3, V2 - V1 == n*I1}, {I1, I2,
I3, I4, I5, V1, V2}]]
Out[1]={{I1 -> (I0 R2 R3)/((n + R1) R2 + (n + R1 + R2) R3),
I2 -> (I0 (n + R1) R3)/((n + R1) R2 + (n + R1 + R2) R3),
I3 -> (I0 (n + R1) R2)/((n + R1) R2 + (n + R1 + R2) R3),
I4 -> (I0 (n + R1) (R2 + R3))/((n + R1) R2 + (n + R1 + R2) R3),
I5 -> (I0 (n + R1) (R2 + R3))/((n + R1) R2 + (n + R1 + R2) R3),
V1 -> (I0 R1 R2 R3)/((n + R1) R2 + (n + R1 + R2) R3),
V2 -> (I0 (n + R1) R2 R3)/((n + R1) R2 + (n + R1 + R2) R3)}}
Now, we can find:
\$\text{V}_\text{th}\$ we get by finding \$\text{V}_2\$ and letting \$\text{R}_3\to\infty\$:
$$\text{V}_\text{th}=\frac{\text{I}_0\text{R}_2\left(\text{n}+\text{R}_1\right)}{\text{R}_1+\text{R}_2+\text{n}}\tag4$$
\$\text{I}_\text{th}\$ we get by finding \$\text{I}_3\$ and letting \$\text{R}_3\to0\$:
$$\text{I}_\text{th}=\text{I}_0\tag5$$
\$\text{R}_\text{th}\$ we get by finding:
$$\text{R}_\text{th}=\frac{\text{V}_\text{th}}{\text{I}_\text{th}}=\frac{\text{R}_2\left(\text{R}_1+\text{n}\right)}{\text{R}_1+\text{R}_2+\text{n}}\tag6$$
Where I used the following Mathematica-codes:
In[2]:=FullSimplify[
Limit[(I0 (n + R1) R2 R3)/((n + R1) R2 + (n + R1 + R2) R3),
R3 -> Infinity]]
Out[2]=(I0 (n + R1) R2)/(n + R1 + R2)
In[3]:=FullSimplify[
Limit[(I0 (n + R1) R2)/((n + R1) R2 + (n + R1 + R2) R3), R3 -> 0]]
Out[3]=I0
In[4]:=FullSimplify[%2/%3]
Out[4]=((n + R1) R2)/(n + R1 + R2)
|
H: Where can I get +5VSB from a motherboard?
I have a computer I'm using as a server, I would want it to turn on on its own when power is cut off, and I figured the easiest way is to connect a micro, maybe an attiny85, that will short the power button pins with a transistor when it is reset (I've checked and the BIOS does not support automatic boot on power on).
However, for this I would need to access the +5VSB rail, is there a standard way to get it from an ATX motherboard? I was thinking about printing a PCB that plugs in one of the PCI-e x1 slots, but it looks like it doesn't have +5VSB, not even any +5V
AI: Apparently +5VSB is available from PS/2 mouse and keybaord ports. This is not true for every computer I've tested, but for some it is, for the one I'm working on luckily it is, so I can get it from this port.
|
H: Do boost converters have a minimum Vin/Vout difference?
Popular buck converter modules specify a minimum Vin/Vout difference, something like "Vin must be at least 1.5V higher than Vout". But I do not see such requirements for boost converter modules, other than a minimum Vin. Do they have no such requirements and can they convert any Vin, within the range of minimum Vin <= Vin <= Vout, to Vout, like converting 4.9V to 5V?
AI: If you look at the basic circuit of a boost converter, you'll see that the output connects to the incoming voltage via a diode so, if the MOSFET switch did nothing, the output would be roughly tied to the input voltage but about 0.7 volts lower. That sets the baseline for basic boost converters. If you need a slightly higher output voltage than input minus 0.7 volts then the MOSFET is called into action to store energy in the inductor that is cyclically transferred to the output. So, theoretically, with a very fine pulse on the MOSFET , you could start to raise the output to voltages slightly higher than input voltage minus 0.7 volts. Theoretically you could arrange for the output to equal the input voltage and be reasonably regulated but, it will be susceptible to input line noise. If you can live with that then, that's the lower limit.
Of course, the devil will be in the detail in many commercial offerings and some will just about regulate to equal input and output voltage and, some won't.
|
H: How often does one have to design low level adders or multipliers in digital hardware?
There are a few different techniques to implement adders like ripple adder, carry look ahead adder etc. Similarly there are different techniques to implement multipliers as well which include Booth multiplier etc. I am sure the same applies to other functions like divider and square root etc. There are certainly implementations for these functions that are at transistor level rather than at RTL level.
Digital hardware design is usually done via RTL coding nowadays. In RTL we would just write + or * for sum or product and leave the rest to the synthesis tool. Alternatively, we might instantiate vendor provided IP cores that implement such features so we can have finer control over the resulting design. However, such IP will be limited to features that are implemented by the vendor.
Now my question is, how often do we have to bother about low level details of adder, multiplier, divider etc? If I need finer control I will just use the IP provided by Intel or Microsemi.
Also, I find it strange that these things get asked in interviews when they rarely have real-world applications now.
AI: How often does one have to design low level adders or multipliers in digital hardware?
Rare; but happens. All HDLs I'm aware of will have primitives for addition, and even if they didn't, you'd just specify the math and let your synthesizer find an adequate implementation for your technology (i.e. the specific set of standard cells/logic cells in your ASIC, FPGA or whathaveyou).
Alternatively, we might instantiate vendor provided IP cores that implement such features so we can have finer control over the resulting design. However, such IP will be limited to features that are implemented by the vendor.
Well, if you want anything other than "standard" addition as defined by the language you're using, it's more likely some IP might have the special mode of operation you want...
But honestly, you implement the logic as HDL/RTL, and then come up with an optimized approach for the problem you're actually solving. If it's special, you probably need something special, and that's where you need to start thinking about clocking/space tradeoffs etc.
Now my question is, how often do we have to bother about low level details of adder, multiplier, divider e.t.c?
Define "we"! If you're doing something that demands specific non-standard additions all over the place, then often, else less often. Engineering is specifically not the discipline of solving the same problem that has been solved before with exactly the same tools over and over again, thus, such generalizations never work out.
The generalization that I'll allow myself is that understanding design choices and working principles in adders is certainly a positive indicator for skills in terms of thinking in digital logic. Rippling, clocking, pipelining, technology mapping are all principles that you need a problem of some complexity to understand, but you wouldn't start with something completely out of the world (say, a divider). You'd start looking at ways to implement a 4 bit adder.
If I need finer control I will just use the IP provided by Intel or Microsemi.
Sorry, I don't see how someone else's IP solves your "I need a special non-standard adder" problem.
Also:
Having a vague idea of the price of specialized IP cores if not "all inclusive" with your platform, you almost certainly would design that yourself, unless you've got more pots of gold at ends of rainbows than you have HDL engineers.
By the way, the "low level details" of a divider are... involved. Comparing that to implementing a single-clock adder is like comparing building an inkjet printer compared to knowing how to sharpen a quill for writing in ink. There's way more design options you have there. Very few dividers are implemented in a non-clocked single-stage manner. Most dividers are heavily pipelined beasts of complexity! But what you get when you write assign c = a + b; is a simplistic purely combinatorial adder. A single-cycle divider is a dangerous to clock high, space-hungry abomination, even if your operands are only 8 bit!
(PS:
Never heard of either companies selling IP / standard cell libraries for that purpose, got a source?)
|
H: How can I solve this opamp circuit?
I am designing an Analog Front-End circuit for an NTC Sensor which has 3 parts, the non inverting stage, the low pass filter, and goes to seeeduino.
Basically the input voltage is 5Vcc and I need to have a voltage output from 0 to 5V.
The NTC is the negative thermistor that changes according to temperature. R1 is there to act as a voltage divider that helps comparing the voltage entering the inverting side of the OA.
Both R1 and NTC are 10k ohm.
NTC is 10k at 25ºC (ambient temperature).
The opamp is an MCP6004.
The NTC range is: 27119 ohm at 5ºC, 10k for 25ºC and 4103 for 45ºC. I also have the Steinhart-Hart coefficients if necessary.
AI: Your input is a voltage divider consisting of R1 and the NTC thermistor and fed with a 5V supply.
You've specified that for the 5ºC to 45ºC temperature range you're interested in, the resistance of your thermistor changes from 27.119k to 4.103k.
So, simple voltage-divider math tells us that the output from your voltage divider to the the opamp will be 1.35V to 3.55V - a range of 2.2V.
So the function you need from your opamp circuit is (approximately):
\$ Vo = 2.25(Vi - 1.35) \$
I've taken some liberties with rounding because resistor tolerances will introduce far more error than the rounding
The 'ideal' circuit (if you had a fixed reference to use) would then simply be one with a gain of 2.25, using the reference to offset the value.
So the ratio of gain-setting resistors for a simple non-inverting configuration would be 1.25:1, since:
\$ Ao = 1 + (Rf / Ri) \$
\$ = 1 + (1.25 / 1) \$
\$ = 2.25 \$
and the reference you'd need would be:
\$ Vref = 1.35 + (\frac{1.35}{1.25k} \cdot\ 1k) \$
\$ = 2.43V\$
So your resulting circuit might look something like:
simulate this circuit – Schematic created using CircuitLab
However you don't have a 2.43V reference - all you have is your 5V supply.
So what you can do instead is combine the 2.43V reference with the R5 resistor to produce an equivalent using your 5V supply and a fixed voltage divider.
To get 2.43V from 5V using a voltage divider you need a ratio of 1.056:1.
And the parallel combination of resistors needs to be equal to 1k (or whatever value you end up choosing for R5).
For this 'ideal-ish' example, I'll choose resistor values of 1k94 and 2k06, which gives me 2.425V and 0.999k.
The circuit now looks like this:
simulate this circuit
and produces roughly the same result as the previous version using the reference voltage.
However, these are not realistic resistor values.
To produce a more realistic circuit, I now start working backwards from where we are.
A pair of 'realistic' resistor values to use in a voltage divider which will give us about 2.43V from a 5V supply could be 5k1 and 4k7. This combination will actually give us about 2.4V.
That pair of resistors in parallel is about 2.45k - so the feedback resistor for the opamp needs to be 3k06 (2.45k x 1.25), so we'll choose 3k as a realistic value.
So now we have a circuit which looks like this:
simulate this circuit
If you do the math or run the simulation, you'll find that this circuit now produces an output of approximately 0.06V to 4.95V for a temperature range of 5ºC to 45ºC.
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H: How to ensure supply voltage is not killed going into IC?
I'm working on a school project in a team where I'm in charge of the Power Management Unit to charge a small battery.
Although my part of project will take rectified DC from my team member (who's working on the rectification CRT), there's no guarantee that it will be a "clean" DC.
To charge the battery (GMB051215), I'm planning to use the MCP73831. Based on the MCP73831's datasheet, it should operate fine with a supply VDD within a range of 3.75V to 6V and a tiny supply current in the microamp range.
My partner says his design for the rectification CRT can supply 6V. Presumably, I would want that supply going into this IC to not have too many ripple so I'm thinking a voltage regular should take care of that.
I got a warning from my professor that whatever I do, I need to ensure that voltage going into my IC is not killed so that the whole thing does in fact work and I'm mainly considering the voltage regulator option right now for that reason. What could happen if I didn't use a regulator, what could happen if I did?
We're still in the design phase of things so I couldn't say what my partner's output actually looks like or anything like that.
AI: there's no guarantee that it will be a "clean" DC.
In a work situation, when different people are tasked with different modules of a design, you would expect that the level of quality of the DC is known. So, basically, there would be a guarantee, or at least a firm understanding, of what's coming out of that section of the overall circuit.
The downside of this in a student project is that you don't necessarily know what's practical until you've given it a try.
What would happen if I didn't use a regulator?
It depends on how the rectification stage is designed. A plain old diode bridge and capacitor stage will have a peak voltage that depends on the AC line, and a ripple that depends on the capacitor used. If you were designing a piece of consumer equipment, you'd want to know if you could use that and nothing more, so you'd look at whether you can find a combination that -- for expected AC line voltages -- never exceeds the voltage that'll break your chip, and never dips down far enough that your chip will stop working.
You have a pretty tight supply voltage range, so this may not be possible.
Note that if that stage is done with an off-line switching supply, then its output will be regulated, so you would have a guaranteed output voltage range.
what could happen if I did?
Basically, extra expense and complication, you'd need to choose your regulator carefully, and anything easy will suffer an efficiency hit.
Easiest would be to use something like a LM7805 regulator -- but if you use that specific part, read the datasheet carefully, particularly the part about "dropout voltage". The short story is that those old first-generation three-terminal regulators need about one and a half or two more volts on the input than they deliver on the output -- so if you use that part, then the troughs of your ripple need to be at around 6.5 to 7V.
The second easiest would be to find a truly low dropout regulator (LDO). Be careful -- for a while distributors were calling every three-terminal regulator a "low dropout" regulator. You want to look for a regulator that drops half a volt or less. With a good LDO your power rectifier student can hand you less voltage, and your circuit will still work. Choose carefully, and pay attention to getting the capacitors on the input and output right -- these vary by regulator, so you need to read the data sheet and do what it says.
The third easiest -- but cheapest -- would be to follow the circuit given in Figure 6.1 in the datasheet. They call out a zener diode across the input leads to the chip, to limit the voltage. This can cause problems -- it will only work if there's something to limit the current to the zener. In the days of old cheap unregulated wall-warts, you could count on the wall-wart transformer having enough leakage so that the voltage would drop with rising current. Using nice parts in the AC to DC converter actually causes problems -- in that case you may need to use a series resistor to limit current to the zener.
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H: Frequency response of a low-pass, band-pass, and high-pass adder circuit
I'm doing a project and one of the steps consists of filtering a signal through a low-pass, band-pass and high-pass filter.
All the filters are Sallen-Key with a passband gain of 1. The pass-band filter uses a Sallen-Key low-pass and high-pass circuit. The low-pass should ideally have a cut-off frequency of 100Hz, high-pass 4kHz, and the pass-band has a 100Hz high-pass filter and a 4kHz low pass. All the filter orders are 4 (n=4).
The output of these filters should be added in an adder circuit, with variable gain through a potentiometer. The problem I'm having is that I'm getting some flutuations of gain around the cuttoff frequencies, since for example if the cut-off frequencies are perfectly matched, the adder circuit adds 2 signals with 1/sqrt(2) of a specific gain, resulting in a gain of 3db.
Since my filters are not perfectly matched, the effect I'm having is getting some attenuation. Regardless of that, is there any method I can use to get rid of, or attenuate this problem?
Thanks!
AI: What you need is a Linkwitz-Riley filter, it's derived from the Butterworth. But, while the Butterworth has a corner frequency at \$\frac{1}{\sqrt{2}}\$, these have it at \$\frac12\$, which means that summing two filters, lowpass and highpass, with the same \$f_p\$, will result in a magnitude of \$2\cdot\frac{1}{\sqrt{2}}\$ for the Butterworth, and \$2\cdot\frac12\$ for the Linkwitz-Riley. Here's the barebones of it (\$j\$ just means a frequency of 1):
$$\begin{align}
B_{LP}(s)&=\dfrac{1}{s^2+\sqrt{2}s+1} \\
B_{HP}(s)&=\dfrac{s^2}{s^2+\sqrt{2}s+1} \\
|B_{LP}(j)|+|B_{HP}(j)|&=\dfrac{1}{\sqrt{2}}+\dfrac{1}{\sqrt{2}}=\sqrt{2} \tag{1} \\
LR_{LP}(s)&=\dfrac{1}{s^2+2s+1} \\
LR_{HP}(s)&=\dfrac{s^2}{s^2+2s+1} \\
|LR_{LP}(j)|+|LR_{HP}(j)|&=\dfrac12+\dfrac12=1 \tag{2}
\end{align}$$
As you can see, the Linkwitz-Riley filter is nothing but a critically damped case, and for the 4th order all you need is two, identical 2nd order Butterworth filters, cascaded.
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H: Why is the polarity of the \$3 \ \text{V}\$ source necessary to calculate the current flowing through the \$8 \ \Omega\$ resistor?
I'm currently studying the textbook Fundamentals of Electric Circuits, 7th edition, by Charles Alexander and Matthew Sadiku. Chapter 1.7 Problem Solving gives the following example:
Example 1.10
Solve for the current flowing through the \$8 \ \Omega\$ resistor in Fig. 1.19.
The authors begin by stating that a problem is that we do not know the polarity of the \$3 \ \text{V}\$ source, but I don't understand why the polarity of the \$3 \ \text{V}\$ source is even necessary to calculate the current flowing through the \$8 \ \Omega\$ resistor. Couldn't we just calculate the current flowing through the \$8 \ \Omega\$ resistor by using the other half of the circuit, where we have the \$5 \ \text{V}\$ source? Why is the polarity of the \$3 \ \text{V}\$ source necessary to calculate the current flowing through the \$8 \ \Omega\$ resistor?
AI: You absolutely need to know the polarity of the 3V source. The 3V source creates a potential that wants to make a current. This current has to go somewhere and that 8ohm resistor is a pretty good place for it to go.
See these two images.
If you flip the 3V source it will drive current the other way.
In the 2nd case: It doesn't mean that current is going through both ways at the same time. They will somewhat cancel out in the 8ohm resistor and flow in one direction, but less. (I didn't do the calculations, so I don't know which way is the final flow)
Anyway, there will be more current flowing through the 2 ohm and the 4ohm resistor as now the two supplies add together.
See this last image.
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H: Flash terminology and meaning
I am trying to choose an SPI flash device for my FPGA and I want to verify if I am understanding the terminology correctly.
Bitstream is the configuration data code used to implement the logic in the FPGA.
Flash density is the overall size of the Flash.
Sector is the partition in memory that holds the bitstream.
I might be way off but please help me understand the meaning of each.
Thank you
AI: "Sector" is the erase block size, so you cannot rewrite a block smaller than that, so you need to align the start of the image to an erase block boundary.
It also seems that an additional sector is required to note down which configuration is active (again, because overwriting that information is possible only by erasing an entire sector).
So, for 1.48 Mbit, which is a bit less than 192kB, you need 3*64k per image, plus one extra, so 7 sectors are used. The smallest available flash is 8 sectors, so one sector is unused. The rightmost two columns should add up to a power of two, because flash sizes will be a power of two.
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H: Theory vs practice in amplifier circuits with capacitors
Electrical Engineering student here! (AKA beginner)
Suppose we have a general circuit (ie bjt cascode amplifier, differential amplifier etc)
To perform theoretical DC analysis we treat capacitors as open circuits.
To take lab measurements we DO NOT add capacitors to our breadboard.
To perform theoretical AC analysis we treat capacitors as short circuits.
To take lab measurements we DO add capacitors to our breadboard.
Why this difference?
Thanks in advance.
AI: To perform theoretical DC analysis we treat capacitors as open
circuits. To take lab measurements we DO NOT add capacitors to our
breadboard.
To perform DC circuit analysis, it's true that you can simplify by treating the capacitor as an open circuit. This is because the effective resistance of a capacitor (i.e. its impedance) is 1/(2πfC). As f -> 0 the value of this expression goes to infinity (i.e. an open circuit).
If you have a breadboard of your circuit and are taking DC measurements you COULD leave the capacitors out and it would still perform the same way at DC. But I don't ever recall doing this in the real world.
To perform theoretical AC analysis we treat capacitors as short
circuits. To take lab measurements we DO add capacitors to our
breadboard
It's not clear where you got this idea but it's wrong. Capacitors only behave as short circuits when the frequency is high enough so that their impedance is much less than surrounding circuit elements. Again the formula for the impedance of the capacitor, 1/(2πfC), is used to calculate the effective resistance of a capacitor in the circuit at a particular frequency.
So whether or not you can treat the capacitor as a short circuit depends on the AC frequency you are using. There is no general rule that says you can always treat capacitors as short circuits under AC circuit analysis.
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H: What is the difference between LDA 210 and LDA 212?
Do you see any difference between LDA210 and LDA212?
Can it be that a factory produces the same product with different names?
LDA210 datasheet: link
LDA212 datasheet: link
Official comparison website: link
DigiKey comparison: link
Context:
I am trying to sense if lights are on or off with an ESP32. I am looking into an AC optocoupler with very high CTR ratio, so that I can reduce the current (Watts) as much as possible:
I tried with the HCPL-3700 (link to my project), but the resistors get very hot, since I am wasting almost 0.6W per channel
AI: The pins are wired differently on the units. This is common when you want your product to be compatible with existing products, to make it easy to use your product even if you originally designed it for the competitors or an older generation of optocouplers.
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H: Why does this circuit flash the two LEDs even without a 555 timer?
Can you please help understanding how this circuit is flashing the two LEDs? I know about transistors, capacitors, and resistors functionality, but can't get how this works without a 555 timer.
AI: The capacitors will alternate between being charged and discharged, thereby turning on and off the transistors making the LEDs blink alternately. This is a passive circuit, no need for a NE555.
More information on:
https://www.build-electronic-circuits.com/astable-multivibrator/
It is called an astable multivibrator circuit.
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H: Why MELF resistor for dc bus sensing
For sensing the DC bus voltage of SMPS, MELF resistors are usually chosen over typical chip resistors (as in this question).
Why is that?
AI: Directly from:
https://www.electronics-notes.com/articles/electronic_components/resistors/melf-smd-resistor.php
MELF resistors are used because of their long term stability, moisture resistance, reliability, and the resistance to the effects of temperature cycling experienced in
the soldering processes used today.
MELF (Metal Electrode Leadless Face resistors) are used where higher reliability and performance than that provided by normal SMT resistors are needed.
The MELF SMD resistors are used for a number of reasons:
MELF resistors provide a high level of reliability.
A MELF resistor has a more predictable pulse handling capacity than other SMD resistors.
MELF resistors can be manufactured with tolerances as tight as 0.1%.
They can be manufactured with very low levels of temperature coefficient, sometimes as low as 5 ppm/°C.
Overall the cylindrical construction of MELF resistors provides an optimal power rating and pulse load capability related to the mounting space.
Reflow oven's RoHS processes work at high temperature in the range 240°C to 260°C.
For sensing the DC bus voltage of SMPS, MELF resistors are usually chosen
I've seen many Switch Mode Power Supplies with bleeding resistors, between LINE and NEUTRAL, in 1206 pacakges. They had 2 resistors in series.
MMA 0204 HV and MMB 0207 HV Vishay's MELF resistors, for example, have a high operating voltage of 1000 V.
That's why MELF resistors provide a high level of reliability.
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H: Specification for RJ-14 connectors and 4-wire flat cable?
RJ-14 jack and plug should have some kind of standard to make sure that the parts from different manufacturers fit together, but I have not been able to find such information.
Can someone help to find that spec/drawing?
Same thing for 4-wire flat cable used with RJ-14. Where could I find the spec/drawing?
AI: The RJ-14 is the standard which defines how a 6p4c modular jack connector should be wired.
What you seek are the drawings for a 6p4c modular jack.
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H: Make a circuit to make sure a device only gets a maximum of 1A
I'm making my own smart home device with a Raspberry Pi. I will power the Pi on the same circuit as our bell. Now the bell transformer is 8V, 1A and the bell itself uses 0.5A.
I'm thinking to replace the bell transformer with a more powerful one, 12V, 2A or so. But is it possible to safely add the bell to the circuit without giving the device too high a current?
I know when I place two devices in parallel the current is lowered and when you place a resistor in series with the devices it will lower it, but is there not a better way to do this?
In the picture of the circuit the AM1 will be the bell and AM2 the circuit for powering the Pi. Is this safe so that AM1 will not be over 1A?
AI: without giving the device a too high current?
You misunderstand electricity.
Please understand that:
voltage is pushed, current is pulled
That is, each load takes as little or as much current as it wants. The transformer doesn't force current onto the loads. No. The loads set the current.
Your drawing shows a current source on the left. That is wrong. A transformer is a voltage source (or darn close to it) not a current source.
Is this safe so that AM1 will not be over 1A?
12 V / 200 Ohm = 60 mA. So, yes, the current will be less that 1 A. Way less.
Raspberry pi.
A Raspberry pi is not a resistor! You must add a 12 Vac to 5 Vdc power supply between the transformer and the Raspberry pi to power it.
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H: Are my capacitors working properly or not?
I've bought some capacitors because I needed to generate a current pulse into a coil. The idea was to charge a capacitor separately and then connect it to the coil to have a strong and brief magnetic field, but they don't discharge properly.
I've tried to charge them using batteries (9V), phone chargers (5V, 2A) and also a car charger (12V, 5A) and despite the capacitor's voltage being the same as the source's, it doesn't give any measurable power output, and even though there's no particular power output, the capacitor's voltage after the process is always 0.
I tried with a 16V, 47μF capacitor and it went as I described, after the fifth time it worked, but only once, and all the other tries were pretty useless. I also tried to change capacitors (I tried with a 16V, 220 μF, a 16V, 470μF and a 16V, 1000uF capacitor) and nothing changed.
I was expecting a surge in the current and therefore in the magnetic field, but it doesn't happen.
I didn't use any particular circuit to charge the capacitor; I've simply connected it to the power source (battery or charger) using wires, without any switch. Sometimes I included the amperometer to see when the current stopped flowing. The same goes for the discharge, I've simply connected the capacitor and the coil using wires.
To know when the capacitor is charged I put an amperometer in series, when the current reaches zero I disconnect the capacitor from the charger and then I measure the voltage and verify that is roughly the same as the source's voltage. After the "discharge" I measure the voltage of the capacitor again and verify that is zero.
To minimize the resistance of the circuit and also to know if there is a current flowing in it, I avoid using the multimeter and instead measure the magnetic field generated by the coil (but it remains practically zero, so I assume that there's something wrong). To measure the currents and the voltages I use a multimeter (which has a resolution of 10mV and an accuracy of +/-0.8% for the voltage and a resolution of 10mA and an accuracy of +/-2.0% for the currents.
I charged the capacitors connecting the negative wire of the source to the negative pole of the capacitor and the positive wire of the source to the positive pole of the capacitor.
My wires are taken from a scientific toy kit. I know they aren't the best, but I have only those.
If you have any idea about what could be the cause of the problem I'd be very happy to hear it. Thanks in advance.
AI: There is energy being stored in the capacitor and it is being discharged into the coil. I suspect if you used a more sensitive instrument on your coil you would see the effect. Try a compass and you will likely see the needle "wiggle".
The problem here is that you're failing to take into account how much energy must be dumped into this coil that you have built in order to get a large magnetic transient generated. Large magnetic transient requires a large electric current which means you have to have a large capacitor. None of the capacitors you mentioned qualify as "large".
I'm going to guess based on what I see in your photo that a capacitance of several thousand microFarads or more will be needed. You might look into one of those large capacitors that are used in automotive sound system installations. It's not uncommon to find those in values of 0.5 to 1.0 Farads or even more.
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H: Will mounting the hub of a fan directly above a heatsink have a big impact on thermal performance?
The 6 SMD MOSFETs in the center generate a total heat of about 80w. I was planning on using this heatsink (ATS-1106-C1-R0) with this fan (08025SS-24Q-AT-D0) mounted directly above it.
Looking at the PCB layout, the fan hub will take up a good amount of the heatsink area. I assume there will be very little airflow underneath it so I was wondering whether this will be an issue.
Do you think I should find a different place to mount it, or maybe leave a gap between the heatsink and the fan? I'm also unsure about whether to mount the fan blowing up or down.
Edit:
The rectangle in the center is the heatsink (the inner part is the footprint on the PCB, the outer part is the size at the top of the heatsink since the fins spread apart), the smaller circle is the fan hub, the bigger circle is the fan, the big rounded square is the fan housing.
Edit 2:
I swapped the 120mm fan for an 80mm one, which is the smallest size for which the screw holes will fit around the heatsink.
Some extra info:
I'm designing this as a prototype to be used without a case around it. If I ever end up putting this in a case, it will have enough airflow not to affect performance too much.
MOSFET's max channel temp is 150°C
MOSFET's channel-case Rth is 0.462°C/W
As I understand it:
This means that the max case temperature is 150°C - (80W/6 * 0.462°C/W) = 143.84°C
At 25°C ambient, the heatsink would need to have a Rth of (143.84°C-25°C) / 80W = 1.48°C/W or less.
The heatsink's Rth ranges from 1.3°C/W at 1m/s airflow to 0.6°C/W at 4m/s. The fan has an airflow of 1.55m³/min which equates to 4.04m/s over an area of 8cm*8cm.
I suspected that I shouldn't be expecting an actual Rth of 0.6°C/W with the fan mounted above the heatsink, but I was wondering how bad it would actually be. By 'an issue' I meant that the MOSFET's channel temperature would get close to or exceed the maximum of 150°C.
I mounted the fan on top of the heatsink in the first place since that seemed like the most obvious solution and because that takes up the least amount of PCB area. I'm not sure how I would mount it vertically.
AI: Will it cause an issue with your intended design?
Yes , several, but not unless you have specs or expectations.
Will it cool down? yes but sub-optimal in several aspects.
heat flux loss from coplanarity and mismatched apertures, and suboptimal velocity and heat extraction. More specs and geometry of enclosure are necessary.
You should start with specs for Tj max, Tamb max and thus Rth(cs,sa) max somewhere <<0.5 'C/W pref 0.2'C/W.
Air velocity up to 10m/s significantly lowers Rth(ca) while plenum area impedes velocity depending on 3D turbulence or 2D laminar flow exponentially. But you ought to achieve at least 2m/s over hotspot surface.
Recirculating the heat raises internal Ta.
High CFM or cu.m./s does not guarantee highest linear air speed over hotspots so is less important than air speed.
Thus max laminar velocity is best over many parallel fins used on CPU heat sinks and max turbulent flow over flat hot spots is best on PCB with a plenum cover works better. Quieter CPU heat sinks rely on optimizing velocity flow with minimum turbulence with load curves by choice of fin thickness and spacing with number of fins. Laminar requires great height or length, turbulence is synonymous with eddy currents in short path gradients so shape matters on the edges.
So for lowest cost and highest noise, directly over a CPU heatsink works well. But a rectangular plenum area of fan diameter reshaped to end geometry with laminar flow exhaust pulling turbulent air from heatsink achieves quiet removal of heat from enclosure. Dell did this with in inline fan plenum to case >20yrs ago for effective cooling and office quiet.
These could be small diameter thick blades but high RPM to match enclosure constraints. (e.g. 1U high) If not possible then a copper heat pipe to same is what is commonly used in laptops.
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H: How does one know that the current is flowing downwards through the \$8 \ \Omega\$ resistor?
I'm currently studying the textbook Fundamentals of Electric Circuits, 7th edition, by Charles Alexander and Matthew Sadiku. Chapter 1.7 Problem Solving gives the following example:
Example 1.10
Solve for the current flowing through the \$8 \ \Omega\$ resistor in Fig. 1.19.
Solution:
Carefully define the problem. This is only a simple example, but we can already see that we do not know the polarity on the 3-V source. We have the following options. We can ask the professor what the polarity should be. If we cannot ask, then we need to make a decision on what to do next. If we have time to work the problem both ways, we can solve for the current when the 3-V source is plus on top and then plus on the bottom. If we do not have the time to work it both ways, assume a polarity and then carefully document your decision. Let us assume that the professor tells us that the source is plus on the bottom as shown in Fig. 1.20.
Notice that the authors have claimed (without justification) that the current is flowing downwards through the \$8 \ \Omega\$ resistor. In SpiRail's answer here, they have also shown that, for the case where the polarity is + on the bottom, the current flows downwards through the \$8 \ \Omega\$ resistor (see the red arrow):
How does one know that the current is flowing downwards through the \$8 \ \Omega\$ resistor? This seems to be the immediate assumption, but there's no explanation from the authors as to why this is the case.
AI: No, the authors have not declared that the current \$i_8\$ is flowing downward. They have defined some current named \$i_8\$ that is flowing downward. Once the circuit is solved it may be found that the value of \$i_8\$ is negative. In that case, we know that there is actually a positive current flowing up.
We must label some assumed direction for all currents and some assumed polarity for voltages so we can write meaningful and consistent equations for the circuit. If the resulting values come out negative it just means that our assumptions were not correct, but it is a perfectly valid way to start a problem.
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H: Current mismatch in digital constant current source
For an electrochemical etching process I am trying to put together a battery powered, somewhat accurate current source able to provide 1mA to 5mA to a load with a varying resistance. (to be specific, it should be able to switch between 1mA, 2mA and 5mA to a load that is less than a few kΩ.)
The idea I had was to control the current through an NPN transistor using a low-pass filtered PWM signal from a microcontroller:
The values are chosen based on what I had lying around, making sure that the time constant of the low-pass filter is large enough to reduce the ripple somewhat, and R1 limits the output current to about 6mA. This results in the following simulated output current (red) when the duty cycle (blue) is swept from 0% to 100%:
I thought it would then be possible to use one of the analog inputs of the microcontroller to read out the voltage over the current limiting resistor R1 and use that to calculate the current through it according to Ohm's law. Then I could adjust the PWM duty cycle from the microcontroller using simple PI control.
The use of a microcontroller is convenient as I can show the measured current on a display without having to include a complete multimeter in the setup. Additionally it means I can switch between the target currents with a single button rather than having to use something like a potmeter to adjust the current with less precision.
After implementing this circuit though I ran into something unexpected. The PI control works well and quickly settles on the PWM where the calculated current through R1 is equal to the target current. If I use a multimeter to measure the current through R1 this also matches.
However, if I measure the current in series with the load I measure a current that is about 20% to 30% lower for all current settings. I am using a 220Ω load and the 5V microcontroller supply voltage as Vbat for testing. This supply should be sufficient to drive this load according to the previous plot which uses these parameters.
What could be the problem here? Did I overlook anything in the design? Is my multimeter at fault? :)
Thanks for any insights provided.
AI: Here's where the problem is. Your base current in driving the BJT transistor into saturation is going to be a significant part of the current flowing through the emitter resistor. So, what you measure across that emitter sense resistor is true load current plus base current. If you chose a linear circuit using an opamp, the base current would be much less (maybe 0.5% instead of 5%).
You mention a deficit of 20% to 30% and that doesn't surprise me either.
After discussion with the op on this and that, I suggested that emitter and collector pins of the transistor be rechecked because if he had placed the transistor incorrectly in the circuit, it would still work but with a significantly reduced beta value. This seems to be what actually happened.
So, when a person (like me) diagnoses a transistor saturation problem based on apparently poor beta (too much base current), it isn't wise to jump all over my answer and down-vote it because it might not appear to fit your limited scope of knowledge. In doing so you totally run the risk of the op not getting the help they truly deserve. Take note.
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