Split (1)

train · 1.46M rows

text stringlengths 83 79.5k
H: How to optimise a logic circuit? I have the following 15 sets of binary outputs: A B C D E b c d e f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I want to create a logic circuit that turns each 4-bit input value into a different 10-bit output row. (There will be one 4 bit value unused, whose output I do not care about, as there are only 15 rows.) The rows can be numbered in any order, provided there is an input that will generate each row. How can I go about finding the optimal logic circuit and numbering scheme for the rows, to use the least gates? AI: I will give you a couple of hints to get you started. By neglecting to show the four bit inputs to the left of each row you have made your question somewhat confusing. Since you have 10 outputs you will need to create 10 separate truth tables or Karnaugh maps. After you have found a set of mimimized logic equations for each of the 10 outputs it will likely be a manual process determine where there are common logic terms that can be shared. Trying to find the minimal overall logic solution will require iterative solving of the 10 truth tables with the different 4-bit input codes rotated among the rows. There are tools available for solving truth tables or Karnaugh maps. Some are online and some are downloadable apps such as one I have seen in the Microsoft store.
H: Evaluating a logic circuit expression My test says the answer is c) A OR B. To me it looks like: Q = AB + (A+B) What am I doing wrong? Which of the following is a logical expression that is equivalent to the logic circuit shown below? Answer is c. a) A AND B b) A AND (A OR B) c) A OR B d) B AND (A OR B) AI: Not doing the algebra, just looking at the diagram: The first OR gate will be true if A or B is true. The second OR gate will be true if the first OR gate is true. Therefore if A OR B is true, then the output is true. Continuing on with the diagram analysis: If A and B are true then the first OR gate will also be true. (goto 3) If A and B are true then the AND gate will be true (goto 3) If A and B are false then the first OR gate will be false and the AND gate will be false, therefore the second OR gate will be false.
H: Are input filters always required for switching power supplies? This is a follow up to the questions here and here I recently designed a PCB that contained a buck regulator (LM2576 5V). You can see the PCB layout in this question. After converting the input 12VDC to 5V, two linear regulators then bring that down to 3.3V (for a micro) and 4.1V (for a SIM800C GSM modem). When the board is connected to other boards in the system (which contains a speaker), a loud GSM buzz is heard when the modem transmits. Bringing a mobile phone close to the speaker board also caused the buzz but it was much much quieter, which implied to me that the noise was being conducted through the cables, rather than being radiated. In order to understand the noise, I did a simple conducted emissions test (using a spectrum analyzer and a Tekbox LISN). I captured the conducted emissions from 150kHz to 30Mhz (RBW 9kHz, step 5.4kHz dwell time 50ms) in a variety of different firmware configurations to try and understand where the problem originates from. Here are the scans: Scan 1 with GSM modem transmitting as frequently as possible (roughly once every 750ms) The large spikes spread throughout the spectrum are usually ~300kHz apart (closer peaks are about 90kHz apart - not sure how to interpret that. Could be multiples of the 52kHz switching frequency.) Scan 2 with GSM modem turned off So, looking at this, clearly turning the GSM modem off has reduced the conducted noise by a lot. However, I then decided to solder a 4.7R power resistor to the output of the 4.1V regulator to simulate the GSM modem load continuously. Scan 3 with GSM modem off and 4.7R load on 4.1V regulator The overall noise jumps back up again to similar levels to the spikes that were present in the first trace with the GSM modem on. If I were to join the peaks of the spikes on Scan 1, I'd end up with a trace similar to Scan 3. This made me think that the problem may actually be the SMPS generating more noise at higher loads rather than it be noise caused by the GSM signal itself, and that the GSM noise was actually due to the modem demanding sudden bursts of power from the SMPS which was then working harder to provide that and generating lots of switching noise. If this is true, it surprises me for the following reasons: I tried to follow the recommended layout for the LM2576 as specified in the datasheet to minimize switching noise. The 4.1V regulator has both large and small value capacitors on the input and output, which I would have thought should be sufficient to smooth out the current requirements of the GSM modem. The GSM modem has 100uF tantalum, 1uF, 33pF and 10pF caps positioned close to the power supply pins, as recommended in the datasheet, which should handle the high current requirements of the modem. Although there are layout issues with the board (especially underneath the micro in the center), the power supply traces seem OK in terms of current loops (see the layout here). The LM2576 datasheet makes no mention of any sort of input filter before the SMPS (only output filters). So the questions I'm asking are the following: Is my analysis of the source of this EMC problem correct? (SMPS generating input noise due to high load). Are input filters always necessary in order to reduce SMPS switching noise, or can this problem be solved just by improving the PCB layout? If so, where are the layout problems that are causing this issue? AI: Is my analysis of the source of this EMC problem correct? (SMPS generating input noise due to high load). I don't know if this is the cause of your 'loud GSM buzz' but it is above the compliance limit, and your tests indicate that it is coming from the SMPS. The peak conducted noise at 150kHz is ~90dBμV or ~30mV, which is about what I would expect from a switching regulator with no input filter. Are input filters always necessary in order to reduce SMPS switching noise Yes, if the noise is unacceptable. A buck switching regulator draws current in pulses, so it will always generate noise at the input. The 100μF electrolytic capacitor in your circuit must be providing some filtering, but apparently not enough. Using a larger capacitor probably won't help much because its inductance will likely be higher, which could make it even less effective. The usual way to tame EMI is to use an LC filter. Texas Instruments AN-2155 (Layout Tips for EMI Reduction in DC/DC Converters) includes this circuit:- As well the 'bulk' filter capacitor CIN6, several smaller capacitors are used to reduce impedance at increasingly higher frequencies. L2 and CIN7 form a low pass filter which reduces noise current conducted back into the power supply. Noise voltage may still be quite high at the SMPS, but the LC filter takes care of it. This filter should be dedicated to the SMPS, with other circuits fed from the supply side. LC filters will resonate if they have high Q, which may be a problem if the resonant frequency is close to the switching frequency. Therefore the capacitor values may need to be 'tuned' for best results. The bulk capacitor's ESR can also be utilized to reduce filter Q. or can this problem be solved just by improving the PCB layout? Probably not by itself, but a bad layout will exacerbate the problem. Your layout looks OK to me, except I would put a 1μF ceramic capacitor close to the VIN pin. I would also remove the copper pour from areas where it isn't doing any good (such as under the inductor) and put lots of vias through it where I want to augment the ground plane.
H: LiPo Shrinkwrapped components Besides over voltage protection, what other purposes are served by the shrink-wrapped (in yellow) components seen here? Do they have any effect on discharge, and will they discharge the battery other than parasitically in normal discharge use? AI: The protection circuits you find in these LiPos can also do over current protection, and under voltage protection so you don't take too much out of the cell and wreck it. Protection circuits do draw a little bit of power, but it is microscopically small, like micro or nano amps. Designers make sure the cell is big enough, and the lower voltage threshold is high enough, that it would take an extremely long time for that parasitic current to take the cell below a safe threshold. It could years or decades, much longer than it would take for the battery to die of self-discharge. Here's another great stack exchange post that goes into more detail: To protect a LiPO cell from undervoltage, how low current is low enough?
H: What is the effect of brown out detection on frequency? I want to use ATMega16 microcontroller to strobe a flash for an industrial camera. So timing is important. I enable BOD (brown out detection). Does BOD affect frequency or timing? If yes, is there any way or any micro or any external chip to avoid it? AI: Mostly all microcontrollers have built-in Brown-out detection (BOD) circuit, which monitors supply voltage level during operation. BOD circuit is nothing more than the comparator, which compares supply voltage to a fixed trigger level. If the supply voltage goes below that level the controller will be hold in reset. See Brown Out Info for details. To answer the question: No, a BOD circuit has no influence on frequency or timing.
H: Oscilloscope and Electrical Safety I was reading an article in a magazine in which the following sentence is written about a circuit that generates a certain waveform on a load R (in which one of its terminals is connected to the earth - not the circuital GND - ): "Never connect a normal oscilloscope probe to the ends of the load. In fact, the oscilloscope's GND terminal is connected directly to the earth conductor and therefore you could make a direct short circuit between the circuit phase and the earth, with relative risks of explosion, electrocution or fire. You need to use a differential probe." Can you explain me this on detail? I do not follow this reasoning. Why should the phase "touch" the earth voltage? To clarify the problem, here there is a picture of the schematic (the load is connected to CH1 or CH2, while the input AC 230V enters x1): AI: The article is cautioning you from connecting the scope probes - and especially the ground clip onto the mains voltage wiring at the bottom left of the schematic. The neutral can have a few volts on it due to voltage drop caused by current in other circuits in the building and, if the 'scope's ground is connected to mains earth, then clipping the scope ground onto neutral may cause mains return current to flow through the scope. There is also the danger that you clip the probe ground lead onto the live which would be much worse. A differential probe solves the problem because neither of the two probe wires are grounded. Notice that circuit, despite having an isolation transformer, PT1, has J1 and J2 to directly connect either to the mains. The control logic must therefore be treated as live and the same rules apply to connecting the scope probes to that also. Related: How to connect the oscilloscope to a circuit Help learning from a mistake connecting an oscilloscope
H: Why do we not get shocked by neutral wire and how can it behave as it does? I read some articles and watched videos regarding 1 phase and 3 phase AC. I later found out that for most home appliances we need 1 phase AC. Then I came to know about live and neutral wires. Few articles said neutral wire (blue) has 0 potential. And live wire (red) has high potential. Neutral wire is to return the current back to source. (I also read about earth wire. That was the thing that lead me to this question but I'll ask about that later) All these things gave me 3 doubts for now. If neutral wire returns the current, the same which was in live/red wire, why doesn't it give shock? Would it make any difference if you connect the bulb using 2 different methods as shown in image? (I have assumed a blub is connected this way. There are two points, one for in and one for out) If current keeps changing its direction many times a second, that means current should keep flowing from red to blue, blue to red and continuously. How is it even possible to flow current from blue/neutral wire? Where would current come in blue wire? From Earth? Okay these might seem too broad, but I believe these are very much related but I have separate doubts since I don't understand the concept fully. PS: Simple and not very scientific language would be appreciated :) AI: The neutral wire is tied to a potential of 0V in comparison to ground with a very low resistance. This means, that high currents can flow through the neutral wire without any noticable voltage appearing on the neutral wire (Ohms law: U = RI). Without any voltage on the neutral wire you can not get shocked (the high current can only flow through the neutral wire because of its low resistance. Your body has a pretty high resistance and needs some significant voltage to get a current flowing). Your first picture is the correct way to connect the light bulb. The live wire supplies the high voltage (110V or 230V) and current, the neutral wire is sinking the current. In your second picture both terminals of the light bulb are connected to the same potential - both to the live voltage. Without a potential difference between the terminals, there will be no flow of current through the light bulb (again: U = RI or I = U/R). At the same time you are connecting the live wire with neutral wire without a load in between - this will create a short circuit and a very high current. Hopefully the circuit breaker would trigger in this case ;) As I wrote above, the neutral wire has a potential of 0V and sinks the current back to the generator (or actually to the next transformer). It does not mattter whether the live voltage is positive oder negative. You are right, the polarity is changing rapidly with either 50Hz or 60Hz (depending on where you live). The only thing that changes is the direction of the current flow. In the case of a positive live voltage you have a positive current and in the case of a negative live voltage you have a negative current (minus sign just means, that the current flows in the other direction). Edit: See the picture below. The neutral wire is on 0V, which is represented by the black horizontal line in the middle. The live voltage follows the curve of a sine wave and is alternatingly positive and negative. When on positive potential, the potential is higher than neutral, but when the potential is negative, it is actually lower than 0V. The current is always flowing from the high potential to the negative one, so when the polarity of the live wire switches, so does the direction of current flow. Image from learn.sparkfun.com
H: What does the prefix "+/-" indicate before the data line names? At this link there are specs of a converter with the following excerpt: What does "+/-" sign indicate(mean) above before TxD or DATA? As far as I know TxD pin/line transmits and RxD receives the serial pulse train. But what does the extra prefix "+/-" indicate then? (And are these data lines always isolated from the ground of such converter? What is meant by Isolated RS-485 converter?) AI: The +/- means that the transmitted and received signals are 'bipolar' relative to ground. 1 / idle / spacing / logical 1 is usually negative relative to ground. 0 / active / logical 0 is usually positive relative to ground. Where a polarity is not specified (eg RS422) all signal levels are always positive relative to ground - but in a balanced signalling system such as RS422 the levels on the two data leads will be of opposite level t0 each other (1-0 or 0-1). . _____________________________________________________ TERMINOLOGY: Differential: Two signalling lines in a balanced pair. "One goes up and the other goes down." Both are usually within a single set of supply rails (eg V+ and ground BUT the signal is not ground referenced. The common mode voltage MAY need to remain within the rails or some limit BUT this is not part of the signalling system per se. Example - RS422 BIPOLAR: The signal is on a single line referenced to (usually) ground. It transitions above and below ground to signal (sending or receiving). It is not balanced, is not inherently noise immune. Example - R232.
H: Is shielding the entire circuit with a faraday cage a good idea? Let's suppose I have a circuit which contains a 3.3V MCU and a buck converter (let's think that its frequency is higher than 400 kHz). I'm wondering if shielding the entire circuit would not a good idea because I think that the shield may reflect the noise generated from buck converter to the MCU. Is this a valid concern? AI: The short answer is that you're right. It is possible (and i mean possible separately from likely) for the shielding of a circuit to cause a problem because a circuit is not self-immune to the quantity of EMI it is generating when not allowed to radiate to free space. The longer answer is that it's why you often see only select parts of circuits shielded. You might only shield the sensitive parts (like the MCU) to protect it from outside radiated EMI sources. You might equally shield things like switching power supplies to protect the rest of your circuit from them or to protect other circuits from the EMI generated by your supply. If you get problems from conducted EMI then shielding won't help you and conducted EMI may even get worse if you can no longer radiate the energy you're now containing.
H: How to control the output voltage of a solid state relay Considering this solid state relay: The output voltage can be from 24 to 380V. How can I control this voltage? Is it proportional to the input voltage? What I need is a voltage regulator that can be controlled from a Raspberry Pi in order to control the speed of a fan. Currently, I use something as below that works as expected. I am completely new in electrical engineering, so please be kind with me... AI: I think you've misunderstood how a solid-state relay works. The coil, or input, will work on 3 to 32 VDC. The contacts, or output, are rated for 24 to 380 VAC. When the "coil" receives its required voltage (SW1 closes below) it closes the internal "contact". In a normal relay, this is an electromechanical process. In an SSR it is an electronic process. Either way, this keeps both sides isolated from each other. General Relay Diagrams: simulate this circuit – Schematic created using CircuitLab The voltage that the coil operates on and the voltage at the output depend on what voltage you feed into either side. There is no conversion going on in a relay. It is just a switch. I wouldn't suggest using what you've displayed as the main component of a voltage regulator.
H: What causes a thorn like feeling when your put your hand in water in electronic appliances? I live in India, the voltage supply in houses is 220V. Sometimes, for example in my washing machine, when it is full of water and I put my hand in it, I get a feeling like a thorn/tiny nail is piercing my finger near nails. Same happens if some liquid is touch inside freezer. Sometimes it happens when I even touch the body of fridge. It doesn't give a shock, but I'm serious about it. Is it a low level of shock or is it something else? It happens when the appliances are plugged in. AI: Vikas, you didn't state your country or the voltage at the plug so I don't know if your washer is 240V or 230V or 120V but since you notice the problem with your fridge also (and it's not static discharge), then it seems to be a condition of your house wiring. Because your plug is 2 wire, you have no earth wire (also known as ground and protective earth). It seems to be leakage current from the appliance to the metal enclosure and your body becomes a path of this leakage when you touch it. The purpose of the earth wire is to provide a return path for leakage currents or in the event of a short to the metal enclosure. If your home does not have 3 wire receptacles then you will need an electrician to wire them in.
H: KiCad Saying Pins Not-connected So I am fairly new to using KiCad, and I have encountered a problem. I recently learned how to make hierarchical pins for bus assignments with the notation. NAME[start_index..end_index] Everything works fine when I use this notation to connect hierarchical sheets. It even goes by position from the start index of the output to the end index, when the names change between the hierarchical sheets. (I looked at the generated netlist to confirm this) When I bring the bus into its parent sheet and create bus entries and connections, it says the pins are not connected. Do I need to create another sub-sheet to complete, does it not let you use a bus in the parent sheet? Note: Error was confirmed in ERC to be unconnected pins, and pins are the only ones in their net. AI: So it seems you need to add labels to the actual bus in the format name[start..end] when transferring busses between parents and sub-sheets, which is not very consistent with the way it works between sub-sheets. Top Level Sheet Subsheet
H: PISO buffer for the MachXO2 I'm trying to design a "double-buffer" structure similar to that used in UARTs (for receiving). In my case, it is for samples from an ADC. I shift them in, and at some point my logic detects a condition that tells me that I want to "save" the block I currently have; thus, a second buffer of type PISO works (serial-out is fine, since the microprocessor can always read the samples from the FPGA sequentially). A pure HDL solution (using PFUs/LUTs) does not work, because the buffer is too large (I get the "Design does not fit in device selected" error at the mapping stage. Even with the XO2-7000, my required size is slightly larger). EDIT: I will need 512 elements × 16-bits per element (times two, if we're talking double-buffer). Notice that the ADC has parallel output; the analogy with the UART is not at the bit-level (in the analogy, each bit in a serial transmission would be like each sampled value of the ADC) END EDIT IPExpress only offers FIFO (including dual-clock) and RAMs (including dual-port). But ideally, I would need to copy in parallel to the second buffer. Any suggestions, or pointers to any additional IPs that could do the trick? (doesn't have to be free). The IPs I see through Lattice's website don't seem to match . AI: Double-buffering shouldn't require a parallel copy. The normal technique is to have two blocks of RAM, and when you get your "trigger" or whatever criteria you have to switch buffers, you simply switch which block you're writing to. simulate this circuit – Schematic created using CircuitLab The switches represent multiplexers. In the current state, U1 is being written and U2 is being read. When your trigger occurs, flip all of the switches, and now you're writing to U2 and reading from U1. If you're going to do this with FIFOs, the technique is similar, but there's a subtlety. Your problem description says that you essentially want to save the last 512 samples that were taken before the trigger, which implies that you will be throwing away data if the triggers are more than 512 samples apart. With FIFOs, you need to explicitly account for this, by removing data once they fill up. This is shown below with the addition of the AND gates. simulate this circuit
H: How to determine the length of the last data field in a SDO block transfer? I've got a problem with the implementation of the CANopen SDO Block Transfer. The transmission is ok except the last block: ... TX: " 618 [8] 5B 65 73 74 0A 44 69 65" TX: " 618 [8] 5C 73 20 69 73 74 20 65" TX: " 618 [8] 5D 69 6E 20 54 65 73 74" TX: " 618 [8] DE 0A 00 00 00 00 00 00" //last block (5E \| 80 = DE) RX: " 598 [8] A2 5E 00 00 00 00 00 00" //ACK from Server: last block 5E The data is a file which only contains Dies ist ein Test\n (engl: This is a test\n) several times. So the last byte that contains data is the 0A of the last block but an SDO has to be always 8-Byte, so the rest is filled up with zeros. On a SDO Block the first Byte counts the actual Block (max 7fh=127d). The MSB of the first Byte marks the end of a Block Download. In this example the SDO-Block sequence no is 5E and it is the last block so the MSB has to be marked as 5E OR 80 = DE. But the last block has to mark the size of non data bytes, see [1]. So I didn't find any documentation which describes how the first byte has to look on the last sequence in block mode. In a 'normal' SDO the 2nd and 3rd bit masks the data. A good explanation can be found in [2]. My Question is: Please, can someone explain how this first byte on the last sequence has to look like? Which bits must be set in this example? [1] CIA 301, Chap 7.2.4.2.11 Service SDO block download end [2] byteme, chap. Expedited Read Dictionary Object AI: TL;DR: The bits aren't set in the last segment of a sub-block. They are set in a separate message that follows the last sub-block. Unfortunately, the answer is a little bit more complicated. CiA 301 defines a SDO block download in three phases, see 7.2.4.3.8: SDO block download initiation (7.2.4.3.9) SDO block download sub-block (7.2.4.3.10) SDO block download end (7.2.4.3.11) As per 7.2.4.3.10, a block download ends when the MSB of the frame is set to 1 (called c in the documentation). That's where you apply 0x80. Your log and logic seems to follow the specification so far. However, there are no bits to set for the length. At least not in that frame. Instead, the server's acknowledgement must be followed by another frame that contains the following data: (1) (2) X C \| CRC \| Reserved 110 NNN 0 1 \| CCCCCCCC CCCCCCCC \| 00000000 00000000 00000000 00000000 00000000 0 1 2 3 4 5 6 7 (Byte) Here, (1) is the client command specifier and should be 6, due to the block download. C is the client subcommand and should be 1 (otherwise you would initiate another block download). X is not used and should be 0. The important bits are now NNN, which indicate the number of bytes that didn't contain any data in the last segment of the last block. As your last block only contained a single byte, NNN should be 110 (bytes [8-6,7]=[2,7] didn't contain valid data). So in your notation, the end of the block transfer should look like this: TX: " 618 [8] DE 0A 00 00 00 00 00 00" // your last message RX: " 598 [8] A2 5E 00 00 00 00 00 00" // Server ACK of block transfer TX: " 618 [8] DD ?? ?? 00 00 00 00 00" // Block End, 0xdd = 0xc1 + (n << 2) RX: " 598 [8] A1 00 00 00 00 00 00 00" // Server ACK of block end ?? indicate CRC bytes that depend on the transfer. Apparently, both sides of your CANopen implementation did not conform to the protocl as defined in 7.2.4.3.8 and ignored the missing download end; you should probably check both sides whether they follow CiA 301 in that regard.
H: Finding Charge of a battery without knowledge of prior charge We have a battery connected to some circuitry. Currently, we have all charging of the battery going through a LTC 2944 sensor, and all discharging going through another one of those sensors. We are trying to write software to read values from those sensors and get an idea as to the SOC of the battery. However, every method I am finding online (I.E. by voltage, Coulomb counting, etc) require you to know the previous state of charge of the battery. Does there exist a method of finding what state the battery is currently in, without any prior knowledge of the battery's charge level? I have found numerous other responses to this, but once again they all require some other knowledge of the battery's current state. Any explanation (or out right refusal) of this process would be much appreciated. (Edit): The battery is a Lithium Iron Phosphate battery. From data sheets from the manufacturer, it seems both the discharge rate and voltage stay constant until the battery is fully depleted. AI: I think this is a very tricky matter. A lot of effects within batteries contributing to their behavior dependent on charge and age are not very linear and come from complex chemistry inside. Think of memory effects in NiCd and also NiMH cells depending on the charge current of recent charging. Such effects might be difficult to separate from the effects of ageing and discharge. Analytical examination to get a model might grow rather complex. I think that this task may be solved with the help of a neural network or similar algorithms like HMM. You have to take care that the input delivers as much information as possible. E.g. by tests run like proposed by TimWescott's answer. Define a test set to be run on a battery, collect as much mesurement sets as possible on known battery states and feed it into a learning algorithm. I think the stimulation method is a good method which can be used even when the battery is powering a circuit, as it can be restricted to kind of a SOA wherin the power supply of your circuit is not put on risk. Stimulation results might be voltage during stress voltage recovery time after stress decrease rate of voltage after repeated stress (due to internal heating) change of the U/I-curve. If machine learning will be able to distill a useful result from that data is rather speculative and depends on the way different causes may generate similar effects. But I'd give it a try.
H: Creating a 5 volt (ish) power pack from 18650 batteries I want to create 5V power supply for a portable lighting project, using 18650 batteries. The power supply needs to provide power to an arduino (which can take 3.3V to 13V input) and some addressable LED strips, which would take 5 volts input ideally, but a somewhat lower voltage is acceptable. The project would draw a maximum of 2 Amps (10 watts) with all LEDs on. I’d like to use 18650 batteries as the power source, which are nominally 3.7V but which I believe would provide an actual voltage rannging between around 4.1V (when fully charged) down to maybe 2.5V (at which point they would be considered discharged). The options I’m considering are: 2 18650s in series, with a buck converter to step the voltage down to 5v. a single 18650, with a buck booster to bring the voltage up to 5v. EDIT I’m aiming for around 3 hours of battery life. I think the average draw of the project would be maybe 5 watts, so I need ~15Wh of capacity. A good quality panasonic 18650 provides around 12Wh, so if I went with the boost option I’d consider adding a second 18650 in parallel. Perhaps this means I’d also need a BMS? END EDIT I don’t believe that an LDO voltage regulator is a good approach - it would be pretty inefficient and would need a lot of heat dissapation support, given the wattage of the LEDs. Are there any majors pros or cons between these options? Are there other options I haven’t considered? My main decision factors are efficiency (for longer battery life) and cost. AI: 2 cells in series provide twice the energy of a single cell, and current is halved so capacity will be a bit higher. Buck converters are also usually more efficient than boost converters, so in practice it will probably be more than double. 2 cells in parallel will probably provide a bit less than 2 in series. One possible downside of cells in series is charging. If they are charged in situ then the charger must put out up to 8.4V, and a balancing circuit is required. This means you won't be able to use those cheap TP4056 modules, and the charger may need its own power supply rather than working off USB. Balancing is not required for cells in parallel. However 'BMS' functions to prevent over-charge and over-discharge are always required. For long cycle life the discharge voltage should not be allowed to go below 3.0V.
H: Calculating steady state output using Laplace transform I've tried to obtain the the steady state output with the help of final value theorem and multiplication properties of Laplace transform.But I'm not sure whether I've solved the problem correctly or not. Please let me know if any corrections are required. This is the question. This is the approach I've tried. The solution is 45. But I'm not sure whether I've made the correct assumption of input signal x(t) as a step signal with amplitude 5. AI: Yes, for these Laplace transform problems, "constant input" translates to "unit step". As a further check, you can reason through it -- while convolution is usually not something to try to do in your head, the convolution of a pulse with a constant is just the height of the pulse times the constant, integrated over the duration of the pulse. So, 3 * 3 * 5 = 45, which is not only the answer you got, but which follows the arithmetic in your final few lines fairly closely. (BTW: If I were a grad student grading your work you would have gotten full marks.)
H: PWM frequency and sine waveform generation I am trying to follow some guides (for instance this) to generate some analog signals (for instance a sine wave of 50 Hz) with Arduino (but my questions are general). But I have two basic questions: 1) The author of the guide chooses to generate that sine wave starting from a PWM signal of 31372Hz. As I understood, it is possible to choose an arbitrary frequency (with some limits obviously) since it is determined by some settings on the MCU internal timers. How do we choose it? Does its choice depend on the low - pass filter we decide to apply? 2) The guide shows the procedure for generating the first half wave on a pin, and the second half wave on another pin. Then, the voltage difference between them is taken, with a circuit called "H bridge". Is there any method to generate the full waveform directly on a single pin? AI: Secrets of Arduino PWM should answer most of your questions but you might need to read it a couple of times. It says: Each of the timers has a prescaler that generates the timer clock by dividing the system clock by a prescale factor such as 1, 8, 64, 256, or 1024. The Arduino has a system clock of 16 MHz and the timer clock frequency will be the system clock frequency divided by the prescale factor. Note that Timer 2 has a different set of prescale values from the other timers. That means that you are limited in the chosen value. You can get the PWM counters to reset at a value lower than 256 but then you lose PWM resolution. As I understood, it is possible to choose an arbitrary frequency (with some limits obviously) since it is determined by some settings on the MCU internal timers. How do we choose it? Does its choice depend on the low - pass filter we decide to apply? The first sentence is correct as discussed already. Figure 1. PWM for sinewave generation. Note that the PWM waveform is shown as a relatively low frequency for illustrative purposes. In practice it would need to be a couple of orders of magnitude of frequency higher than the sinewave to be produced. Source: How is a PWM signal converted to Sine using a transformer?. The second sentence is also correct. The filter on the PWM output has to filter out all the higher frequencies of the PWM if you hope to get a smooth sine. Is there any method to generate the full waveform directly on a single pin? Yes, but since the PWM is switching between 0 V and 5 V (or 3.3 V as the case may be) you have to bias the 'zero' of the sine to half supply or some other positive voltage.
H: Power supply circuit capacitor selection I'm planing to use this circuit for my op amp test but I don't understand capacitor selection Why C1 and C2 selected 2200 uF but C3 and C4 selected 1000 uF? (C3 is 1000 uF picture is wrong) I tried to use 220 uF and 100 uF and voltage levels were same. I think C3 and C4 for stabilizing the output but what's the purpose of C1 and C2? Also if capacitor selection only effects on output current, is there equation for it? AI: Why C1 and C2 selected 2200 uF but C3 and C4 selected 1000uF ? (C3 is 1000 uF picture is wrong) C1 and C2 are in series with the negative supply. The impedance is given as \$ Z_C = \frac {1}{2 \pi fC} \$ and for 2200 μF at 50 Hz that's just under 1.5 Ω each. (See Capacitor impedance calculator.) If you tried to pull 1 A from the negative supply you would drop 3 V across the capacitors so your supply would not be symmetrical. C3 and C4 are holding the voltage up between half-cycles of the supply. For modest levels of ripple the ripple will be given by \$ V_r = \frac {I_{load}}{2 f C} \$. See Electronics notes for more. I tried to use 220uF and 100uF and voltage levels were same I think C3 and C4 for stabilizing the output but what's the purpose of C1 and C2 ? C1 and C2 create an isolated supply for the negative rail since you haven't got a centre-tapped transformer. Also if capacitor selection only effects on output current , is there equation for it ? Given. simulate this circuit – Schematic created using CircuitLab Figure 1. A much simpler supply. You can make a much simpler supply as shown in Figure 1. This won't suffer the voltage drop in the negative rail that your circuit does and will give symmetrical voltages if the currents drawn are symmetrical.
H: What is the proper term for a board that replaces a chip? I've been working on some vintage electronics lately. In the course of this work, I've found that in some cases it is much easier to design a circuit to replace an old DIP chip that has failed than it is to locate the old part. (Actually, the bigger problem is that some of these parts are so old that the only replacements available are 30 years old and may not function at all) For example, I've replaced two socketed SRAM chips with a single modern SRAM on a daughter board with pin headers aligned so that the whole circuit plugs into the two DIP sockets on the original board. My question is, what is the actual name for this type of a board? Daughter board? Mezzanine board? I'm trying to figure out how to describe it in the tech notes. AI: It would be called a 'daughter board' if it was intended (usually as part of the original design) to extend the functionality of the main board, eg. Amiga 1000 WCS Daughter board A board which has similar chips to those it is replacing is commonly called a 'replacement module', particularly if it contains RAM. Example:- ZX Spectrum 4116 (lower RAM) replacement module If it uses eg. an MCU programed to replicate the functionality of a different type of chip it may be called an 'emulator'. Example:- SwinSID A board with no parts on it for using chips or modules with a different pinout is called an 'adapter'. Example:- Amiga 3000 SIMM ZIP Ram Adapter As always there are overlaps and exceptions to these definitions. The word 'module' is often used to describe small boards with various generic functions (CPU module, RAM module etc.), so 'replacement module' could just be a module to replace another one.
H: STM32: SPI hardware to implement custom serial interface I want to implement SDLC communication on an STM32 (assume I can pick any one up to M7) using the existing HW in it. SDLC is a full duplex synchronous serial interface. In my case, it uses differential signaling (RS-485), so I am using some MAX488 to convert the differential signals to single ended signals. So I have Tx Clock and Data, Rx Clock and Data. I was thinking about using one SPI as master for transmitting the data and one SPI as slave for receiving the data. A few questions: Is this possible? Is there any better way to achieve this with only an STM32? How can I generate 153.6 and 614.4 kHz clocks for SPI Tx? Can the SPI slave receive any clock? Like 614.4 kHz? AI: assume I can pick any one up to M7 Then pick one from STM32H7 series, it has direct hardware support for all the features you need for this, independent fractional PLL to generate arbitrary SPI clock rates, and variable frame length if you need bit stuffing, i.e. frame length is not necessarily a multiple of 8 bits. Any other STM32 can do it as well, even the smallest ones, but some tricks would be needed, like looping back a timer output externally to the SPI clock input, as they have only a simple power-of-two prescaler for SPI clock generation. Any better way to achieve this with only an STM32? I can't think of any. How can I generate 153.6 and 614.4 kHz clocks for SPI Tx? Experiment with the clock tree configurator in STM32CubeMX to understand how it works (faster than by reading the reference manual), get PLL2 or PLL3 to output 0.1536*256=39.3216 MHz and map it to the SPI clock. Then use the prescaler in the SPI peripheral to get 153.6 kHz (/256) or 614.4 kHz (/64). I'm quite certain that a better match is possible by fiddling with the divisor and multiplier values. Can the SPI slave receive any clock? Like 614.4 kHz? Any clock up to the limit in the datasheet, which is usually in the tens of MHz range. There is no low limit.
H: AC Simulation in Power supply simulators I would like to design a boost converter using LM3481 from texas instruments. To de the job, I have selected TINA TI circuit simulator, where the average model of LM3481 is given. So I have used this model to get the open loop bode plot of the power stage without the compensator.My objective is to get a plot that will help me to decide where to put poles and zeros of the compensator. The circuit is given bellow with (L=6uH, Rsense=20m, Fsw=227kHz) My probleme is that I do not know how to built a circuit for AC simulation, for exmample, I do not know how to isolate the COMPENSATION PIN or where to connect it. If I connect it the compensator circuit, I will not get the open loop graphs, but I will get the closed ones, am I right ? If I connect it to the ground, I get a strange graphs that are not convinient to me. What are the techniques that I should use to get the bode plot of the power stage without the compensator? AI: The circuit shown is ready for the open-loop analysis you want: \$L_1\$ and \$C_2\$ close the loop in dc and open it in ac analysis. This is an old trick and I traced it back to the Vince Bello times when he first published his average models. When you run the ac analysis, SPICE computes a bias point to know where all the elements operate. During this moment, inductors are shorted and capacitors are opened. The loop of your converter is thus physically closed by \$L_1\$ and the simulator calculates the correct operating point set by the resistive divider. When the ac analysis starts, the extremely-low cutoff frequency of \$L_1C_2\$ filter isolates/opens the return path and the converter runs in ac open-loop conditions. Should you change operating conditions (input voltage, load current...), the correct operating point will be computed each time you run the .AC analysis and parameter sweeping is easy. Now, if you want the power stage transfer function, probe the output voltage and the voltage at the COMP pin. When plotting the ratio of these two variables you'll obtain the control-to-output transfer function you want and decide what strategy to adopt with the compensation elements. Once compensation elements are calculated, probe \$V_{out}\$ only and you'll have the loop gain from which you can infer the 0-dB crossover and various margins. If you now want to test the transient response, reduce both \$L_1C_2\$ to a 1-p value and the loop is now closed in dc and ac. More information in this book.
H: Ultra Miniature Coaxial connector what does 50ohm stand for In my current project I designed a PCB board for the ESP8266EX chip. Instead of making an onboard antenna, like in the datasheet described, I have placed this connecter. The goal is to be able to choose a bigger antenna with higher dBi. Since the board will be placed inside an enclosure, I need to somehow connect the antenna with the connector via cable. The datasheet describes the antenna pin for 50 ohm impedance (when using the pi matching circuit). The connector on the lcsc page somehow says 50 ohm also. Does this mean, if I add a 50 ohm antenna, I'll have 100 ohm impedance on the pin that is meant to have 50 ohm on? Or does the 50 ohm impedance on the connector stand for the ability to connect a 50 ohm impedance antenna to it? Thus further I'm not quiet sure how to search for the coaxial cable... nor the antenna. Big websites like amazon don't seem to have anything when searching for "Ultra Miniature Coaxial (cable)". Is there a special website for these type of applications? AI: A 50 ohm connector is designed to be connected with 50 ohm cable, and 50 ohm track on the board. It's a description of the geometry and material of the dielectric used in the cable, connector and track. This controls their impedance, or the ratio of voltage to current of a signal that flows through them. You get best results when they are all the same impedance, so that a 50ohm signal launched into the track can continue with the same V/I ratio through the connector and into the cable. Small errors in impedance are usually negligible. Large errors can cause loss of signal, and so communication problems.
H: Is running two voltage regulators in parallel safe? Components Battery (7.5V 6A Max) D24V25F5 (5V 2.5A step down) U3V50F12 (12V 5A step up) Raspberry Pi 3 (5V 2.1A-2.5A) Motor (12V 3A stall) (Using H-Bridge) Would the setup be suitable? I much prefer to use one battery instead of two batteries in which one battery runs to each of the voltage regulators. Below I have included a drawing of how I'm going to solder them onto a prototyping PCB. AI: Do the math on your power budget: The Pi needs up to 2.5 A @ 5 V = 12.5 W The motor needs up to 3.0 A @ 12 V = 36 W That's a total of 48.5 W Taking the efficiency of the converters into account, which is going to be 90% or less, that becomes at least \$\frac{48.5 \text{ W}}{0.90} = 53.9 \text{ W}\$ that you need from the battery. But you say that the battery can only supply 6 A @ 7.5 V = 45 W. This will work only if you can tolerate overloading the battery each time the motor starts or stalls. (Motors generally pull their stall current when starting from a dead stop.) And just to clear up the misconception in the title, the regulators are in parallel, not in series.
H: What transistor setup to use for level shifting to create a logic ENABLE signal (for DC-DC converter module) I want to create an ENABLE signal driving a Murata OKI-T/3-W32P-C DC-DC converter, where the P stands for Positive Polarity of the On/Off Control line: the line has an internal pull-up, which means that the converter is on when the Control line is open or high, and off when pulled to GND. So what I have right now is a DISABLE signal, based on an N-channel enhancement-type MOSFET (2N7000). From what I read online, the easiest way to turn this setup into an ENABLE signal would be to use a depletion-type MOSFET, but I understand that these are rarely used? Or are there depletion-type MOSFETs that are generally recommended just like 2N7000 and other general-purpose transistors? If not, what would be the right way to go here? connecting the DISABLE signal to Vin using a pull-up resistor, and add another transistor at the low side to pull down the DISABLE signal when the ENABLE signal is activated? Follow-up: So here's the adjusted schema following @peufeu solution (thanks for providing a complete solution + explanation): Which leaves me with the question whether this is the general way to go, or whether the MOSFET-based solution can/should be used when Vin is not as high as 32V: In the datasheet for this OKI-T/3-W32P-C module I see that there is simply a switch symbol. But in the datasheet for the ABB ABXS002A3X41-SRZ module (fig. 27 on page 11), for example, there is a N-channel/enhanced MOSFET in the circuit. Is that because the max Vin in this case is only 16V? which means that a 2N7000 could be used directly here, as its max Vgs is 20V continuous? Similar thing in the datasheet for the Murata OKL-T/6-W12 module: Fig. 7 on page 15 shows the P-channel/depletion setup (for a module with negative logic) that I initially thought I could use. This module has a max Vin of 14V, so in this case a MOSFET would be able to handle it without level shifting? And if so, what transistor would be a good candidate? AI: Quick datasheet check... It does not use standard logic levels: "Low" is below 1.2V, and "High" is above Vin-2.5V. So, level shifting is required if you intend to use standard logic levels (like 3.3V CMOS) to control it. the easiest way to turn this setup into an ENABLE signal would be to use a depletion-type MOSFET A depletion N-Channel MOSFET has a negative threshold voltage, it is ON with Vgs=0V. However, it is still N-Channel, which means in order to turn it OFF, you need Vgs to be below the threshold, which means a negative Vgs. I don't think this is what you want, if your control signal is standard logic, it will be positive. So the simplest solution is to use 2 transistors to invert the signal twice and level-shift it. They can be bipolar or FET. Since the datasheet specifies an iternal pullup on your DC-DC it would be like this: simulate this circuit – Schematic created using CircuitLab I used BJTs because your 32V max input voltage will blow the gate of most FETs, so they would need extra components to limit Vgs. I added a pulldown on the input too. This is not necessary if the input is connected directly to a logic circuit, but if it is a connector it is better to have a pulldown to avoid spurious turn-on if a foreign object (ie, a finger) injects some tiny current into the base of the transistor... in the datasheet for the ABB ABXS002A3X41-SRZ module (fig. 27 on page 11), for example, there is a N-channel/enhanced MOSFET in the circuit. Is that because the max Vin in this case is only 16V? which means that a 2N7000 could be used directly here, as its max Vgs is 20V continuous? In the ABB case fig 27: FET gate is connected to ENABLE signal you provide -- thus you must pick a FET that is compatible with the logic levels of your ENABLE signal, it must fully turn ON on a logic high (5V or 3V3 etc). In this case it is up to the circuit that generates ENABLE signal to ensure Vgs will not exceed 20V. If it comes from a logic circuit, or a switch from the 16V supply, no problem. Similar thing in the datasheet for the Murata OKL-T/6-W12 module: Fig. 7 on page 15 shows the P-channel/depletion setup The schematic shows a weird MOSFET symbol with incorrect connections and a short between base and emitter of bipolar transistor Q3... ie, this schematic is most likely wrong, don't look at it, follow the instructions in the text instead!
H: Insight into cavity resonators Modes of a waveguide As shown in the link above, they show how these modes work for various values of m, n, and p. However, where is the antenna/ source of radiation placed within the cavity? From the picture I have shown the placement of 4 antennas refer to previous post here Visual understanding of EM fields within a rectangular metal container.. I'm am basically working backward in that I already have a cavity resonator and the frequency. I am simulating the modes in the container. However, as noted in the comments and answer there will exist different modes of operation and I think if I am correct these modes will be the same for each antenna. But does this mean that these will all have the same EM field pattern within the container or will each antenna have it's on EM field pattern? If there only existed one mode how will the EM field look inside the container for each of the 4 antennas? AI: Each antenna is able to excite almost any mode, and will. The only modes that won't be excited by an antenna are those for which the antenna is at a node of the mode, a point where the standing wave of the mode has no amplitude. Each antenna is at a different point in the cavity, so will excite different modes in different ratios. If there only existed one mode how will the em field look inside the container for each of the 4 antennas? The only way for there to be only one mode is if the cavity is much smaller, comparable to the half wavelength. I'm am basically working backward in that I already have a cavity resonator and the frequency. No, you don't have a cavity resonator, at least not what engineers would call a cavity resonator. You have a honking great box. A cavity resonator supports only one mode, it's built small enough or operated at the right frequency, to do that. You have a large box supporting many, many modes, most of which will be excited at essentially unpredictable levels by any radiation coming in from the antennae. There is no need for you to visualise the modes in your box, all you need to know is that there are a lot of them. There are so many that the pattern you actually get will be unpredictable, given the accuracy with which you can characterise the box and the antennae. A standard domestic microwave oven cavity is multimode. It will contain a number of high field and low field regions, which will result in over-cooked and cold food respectively. The three solutions to this are a) a turntable, to try to move the food through a variety of regions, b) a mode stirrer (very few have these) which is a metal vane rotating in the cavity to change the electrical geometry (roughly equivalent to your multiple antennae) and c) a single mode cavity with predictable power levels, these are only used in industrial applications where the cost of low frequency RF power generation is acceptable.
H: Repurposing PWM output for D- of USB I'm currently designing a self-powered PCB with a STM32L432KCU6 MCU on it. I want to use USB, but D- is already used for a different purpose. According to the datasheet, D- and D+ have to be connected to PA11 and PA12. For PA12, this is no problem as this pin is still free. However, I'm using PA11 to drive a small 8 mA LED that is controlled via PWM. There is no free pin to which I could assign this function instead. My question: Is it possible to repurpose PA11 from a PWM output to D- once VBUS is detected? Here the datasheet of the MCU: https://eu.mouser.com/datasheet/2/389/stm32l432kb-956275.pdf simulate this circuit – Schematic created using CircuitLab AI: Simply: No, you can not. A USB interface is a high speed serial interface with strict impedance rules. The tracks have to be routed side-by side having an impedance close to 90 ohm. You can not make a tap and route that somewhere else or connect other components to one (or both) of them. So you have to find a different solution.
H: Is this circuit for Piezo Transducer and corresponding resistor values correct? I want to drive this piezo transducer (https://www.mouser.com/datasheet/2/670/cpt-9019s-smt-1310960.pdf) at 3V and 4kHz with STM32F0 microcontroller. This is a follow-up to my previous question (Is this circuit for Piezo Transducer sufficient?). Since then, I've made some progress and come up with this circuit: simulate this circuit – Schematic created using CircuitLab R1 is to limit the amount of current the microcontroller pin draws and R2 is to discharge the speaker when there is no output to the speaker (since it acts like a capacitor). The MCU can draw a max of 25mA of current, but the speaker only uses a max of 5mA when driven at 3V and 4kHz. So I will limit the current draw from the MCU to 10mA. This gives i_c a value of 10mA and R1 a value of \$330\Omega\$. (R1 = \$\frac{3.3V}{10mA}\$). Since the speaker draws a max of 5mA, i_s = 5mA and i_b = 5mA. The schematic with the values plugged in is: simulate this circuit To determine R2, I know I want 3V to be applied to the speaker, so the voltage drop over R2 will be 3V. Using Ohm's Law, \$R2 = \frac{3V}{5mA} = 600\Omega\$. My two main questions are: Is this circuit fundamentally correct to drive the transducer? Do the values for resistors R1 and R2 make sense or am I overlooking something? AI: If the piezo speaker only draws 5 mA at 4 kHz when driven with a peak positive voltage of 3 volts then there is no need for a current limiting resistor if you are driving it with a peak voltage of 3 volts. On the other hand, it might be a good idea to have a series resistor to prevent the instantaneous current draw from the MCU pin exceeding limits stated in the data sheet so, focus on that and not the speaker. You don’t need a parallel resistor to discharge the piezo speaker capacitance because when the MCU pin cycles naturally through a low part of the waveform, it will discharge the piezo capacitance. Your calculation for R2 is fundamentally misplaced in theory.
H: Adapting two-way radio tactical throat mic (laryngophone) to cell phone or laptop I've ordered one of these: https://www.amazon.com/gp/product/B074Z1LDY2/, a tactical throat mic (and earpiece speaker) which is intended to be used with Kenwood two-way radios (and other compatible models). I'm interested in using this with conventional CTIA TRRS inputs/outputs as found on cell phone and laptops. I know the pin-outs are incompatible as they are so I know I need to re-wire at bare minimum. What I'm trying to discover is how to tell if I need some capacitors and resistors or a full, externally powered circuit to support the mic (my primary interest, the speaker is less interesting to me). I have a mid-level multi-meter and no oscilloscope. I know the pin-outs for these generally: Kenwood two-way pinouts: CTIA cell phone TRRS pinouts How can I best reverse engineer what the two-way radio mic is expecting and how to hook it up to what the cell phone is providing WRT to power? I've not been able to find any references on Kenwood two-way radio mics. Any tips for strategy to make this work, particularly not requiring more specialized testing equipment, would be very helpful. Also, any warnings and strategies for not damaging equipment would also be helpful. ;-) [Edit: I've come across this which is basically the opposite of what I'm interested in doing but may give helpful context to someone with more insight that I have. http://www.n1gy.com/headset-adaptor-for-kenwood--baofeng-and-wouxun-hts.html ] Follow-up: Works perfectly as described by @JRE below. The 3.5mm pin plugs directly into the breadboard jack on the right; the 2.5mm pin plugs into a 2.5->3.5mm adapter and then plugs into the jack on the left. The wiring specifics should be discernible via the photo. AI: Let's get a couple of things together here. First, a diagram of how to connect the Kenwood connector: That image came from here. Second is how to connect to an Android phone: Your throat microphone is most likely a two terminal electret microphone, so Note 2 from the Kenwood diagram should apply and there will not be a 10uF capacitor in the microphone line. All you should need to do is to connect the microphone line from the headseat to the Android microphone line. Then the microphone ground to the Android ground. The microphone ground is the ground connection on the smaller (2.5mm) plug. The Android diagram shows where to connect the microphone wires. Once the microphone is connected and plugged in to your phone, the phone should recognize the headset and switch to headset mode. That should do it. Connect the earphone to left or right and ground if you need the earphone. If you've never used a throat mic before, then you should be ready for a surprise. Throat mics don't sound like regular microphones. Throat mics pickup pretty much just the vibration from your larynx. All the aspirant sounds ("S" and "Sh" sounds and the like) will be very weak or not present at all. People may have a hard time understanding you.
H: What does the "capacitor into resistance" symbol mean? I can't understand the circled symbol and didn't manage to google it. It looks like a variable resistance and a capacitor. What does it mean? AI: It's not one symbol. It's just a capacitor connected to the wiper terminal of a potentiometer.
H: Time-invariant system question I seem to struggle with the notations and concepts used in signals & systems. The book states, given that x2(t) = x1(t-T), x2(2t-5) is equal to x1(2t-5-T). This might be a dumb question, but why wouldn't x2(2t-5) be x1(2t-5-2T)? AI: You were given $$ x_2(t) = x_1(t-T)$$ If you apply the transformation \$t\to t-T\$ to the expression \$2t-5\$, you get \$(2t-5)-T=2t-5-T\$, not \$2t-5-2T\$. Your expression for \$y(t)\$ involves multiplying the argument of \$x(t)\$ by 2, but that's irrelevant to the question of determining \$x_2(\cdot)\$ from \$x_1(\cdot)\$.
H: Hobby function generators I am a physicist with a limited knowledge of electronic. I usually study my problems extensively on Internet before asking for a help. This means that here I will present both the questions and probable solutions and I would like you to confirm or correct what I wrote. I would like to obtain a relatively cheap hobby signal generator up to cca. 10MHz. I have two requirements: It must give floating signal. It must be possible to ground the output within the aperture and still get a signal with no DC component. Ad 1: This condition can be fulfilled only if power and the signal generator are galvanically separated, which can be achieved by using a transformer. Therefore any signal generator that is DC powered (or has external DC power source) is out of the question. Ad 2: The reasonable way to fulfill this condition is that the signal generator uses transformer with two secondary windings, e.g. 12V-0V-12V. When the common wire of secondary windings is grounded, it is possible to get true negative and positive voltages. It seems that practically all cheap signal generators use DC power source (which automatically rules them out due to condition 1). One notably exception is model FY3200S. However, according to this video, signal generator FY3200 does not possess truly floated output (for 110V line voltage, 50V and 100 uA on the floating ground!). Fortunately, the secondary stage requires -12V, 5V, and +12V inputs, which probably means it should be able to make signals without DC component (condition 2). Author of the video suggests that the problem is that the device uses less appropriate switch mode power supply instead of better linear power supply and suggests replacing power supply. [I suspect that the less convinient switch mode power supply is used in order that the device could be used on both 220V and 110V power lines.] However, no information on the design of the linear power supply or the benefit of replacing power supply are provided. Since linear power supply should not be to hard to make, it seems to me that the best option would indeed be to replace original power supply with something like that: I could easily and cheaply produce something like that and also add a switch at the connection between the common wire of the secondary windings and the ground. And using second stage from FY3200S (as well as its box) I would avoid dealing with much more complex electronics of function generating. Does this seem to be a good idea? Would this at least reduce stray currents if not completely eliminating them? Is the power supply above appropriate for the application? AI: I actually own a FY3200S signal generator. When I bought it, I was already aware of the questionable quality of the switching power supply inside it, and the reported high earth leakage currents. For this reason, I replaced the built-in switch-mode power supply by a simple regulated linear power supply (a fairly common mod for these units). If you want to go this route, note that you'll need to provide +12V, -12V, and +5V. I managed to find the original switch-mode PSU for the signal generator, so I hooked it back up, and took several measurements with both the original switcher and the new linear supply. I probably should have done that when I built the linear supply, but hey ¯\_(ツ)_/¯ Power supply design The linear power supply is very straightforward: simulate this circuit – Schematic created using CircuitLab The LEDs aid debugging, and help ensure the rails are in regulation under no-load conditions. At the time I made this, I took measurements for the current requirements, but I forgot the results and can't find my notes on this project. The transformers are capable of 133mA (+12V and -12V each) and 425mA (+5V) respectively. I remember my design having not much headroom, so maybe these numbers help you. The power supply circuit in your question looks acceptable to me (though I haven't run the numbers). It's similar, except it uses a single transformer and derives the +5V from the +12V rail. I would expect it to work just fine, just ensure the transformer can deliver enough current to power both the +12V and +5V on one leg. Research how to size the transformer and capacitors; there should be plenty of information out there on that subject. These answers may be a good starting point. The implementation is messier than the schematic, because I had to make do with whatever parts I had laying around. In particular, the 5V rail is powered by two transformers that are paralleled after their bridges, and I had to use capacitors in series (with balancing resistors) on the ±12V rails to get the appropriate voltage rating (the rectified transformer output is like 24VDC to ground under no-load conditions). Test setup notes Please note that my test setup is probably terrible. None of my mains outlets have safety ground (I know ☹...), so my earth reference for these measurements was a wire hooked up to the central heating pipes (which are metal and grounded at the central heater). Also, there were longish wires all over the place picking up noise, etc... Waveforms were captured using a Rigol DS1104Z; multimeter measurements were performed using an EEVBlog 121GW (I tried my Fluke 17B+ first, but it's terrible at measuring >500Hz AC). For the tests, I only tested channel 1 of the FY3200S. Its output was set to a 10Vpp 1kHz sine wave. I also performed all tests with a 10Vpp 1kHz square wave, but that didn't yield any new information so those results have been omitted. I also used a 0V DC signal for the PSU noise measurements. Measurements In the results below, I'll always have the original switch-mode PSU at the left, and the replacement linear PSU at the right. Waveform First a capture of the test waveform. Looks clean, no difference between PSUs. PSU switching noise With the signal generator set to generate a 0V DC "signal", this is a capture of the signal (50mV/div, 5µs/div). The left image shows switching ripple at some 37kHz, which is absent on the right image: A close-up of the switching ripple (50mV/div, 50ns/div). The left image shows the switching ripple. The right image just appeared to have random noise (which sometimes the scope would trigger on, sometimes not): Waveform measurements The multimeter measured the sine wave as 3.515VAC RMS (works out for 10Vpp), at 999.9Hz. The square wave measured 4.933VAC RMS (close enough), at 999.9Hz. There was no significant difference between the two PSUs. DC offsets DC offset in the signal was measured with the multimeter in DC mode. Results: \| switching PSU \| linear PSU ------------+----------------+------------- sine wave \| 17.9 mV \| 20.7 mV square wave \| 19.1 mV \| 23.8 mV There's a small difference in favour of the switching PSU. I suspect this might be caused by asymmetry in the 7812/7912 linear regulators I used for the linear PSU, but I didn't investigate further. Earth leakage voltage This is the heart of the question, and the most common reason to replace the PSU in these signal generators. It was measured by hooking up the oscilloscope or multimeter between my earth reference (central heating pipes) and the ground of the signal generator. The signal generator output signal itself (10Vpp 1kHz sine) was left unconnected. Clearly, the linear PSU still has earth leakage due to capacitive coupling in the transformers and perhaps wiring, but it looks better than the switching PSU (both image 50V/div, 5ms/div): Multimeter measurements confirm that the open-circuit ground-to-earth voltage is indeed lower for the linear PSU (39VAC RMS) than the switching PSU (92VAC RMS): Earth leakage current But the real difference is in the earth leakage current; at 5.5µA, I'm slightly disappointed in the linear PSU performance here, but it's two orders of magnitude better than the switching PSU at 334µA! Conclusion of sorts So yeah. These things come with a crappy power supply. I have little faith in its safety, and ~0.3mA leakage current can ruin your day on sensitive circuits. And from what I've read online, some specimens exhibit >1mA leakage current. However, replacing the PSU with a linear power supply can improve this a lot, and it can be a fun little project. I used linear power supplies for every rail (which also makes it easy to get rid of switching ripple), but I've heard of others using DC-DC converters to derive the necessary rails from a single external 12VDC or 5VDC power supply. If you want to go this route, also consider what you'd like to do with the USB port, which is not isolated. In the end, with my replacement linear PSU, the results look acceptable. No switching ripple, 5µA leakage current, 30VAC open-circuit earth-to-ground (which is still something to be careful with). It's not perfect, but for < $100 it's okay at the hobby level. Signal quality at higher frequencies In your latest edit, you added "... up to cca. 10MHz." Beware that these cheap signal generators are not great at higher frequencies. If you need, say, good square waves at 10MHz, you'll probably have to spend more money. I added some captures of the FY3200S 10Vpp square wave at 10kHz, 1MHz, 6MHz, and 10MHz: I'm not even sure what's going on at 10MHz. Perhaps the synthesizer frequency isn't evenly divisible by 10MHz, so not all square pulses are of equal length, leading to the ghosting you can see there. Sine waves are easier, so they look considerably better, but at the higher frequencies they also show some small distortions.
H: Is it better to use a MOSFET with a gate driver IC or a MOSFET with a lower VGS,on? I am building an RGBW controller for my room. I will be using an ESP32 with four MOSFETs for each channel. I want to know which is best for fast switching. Do I need to use a MOSFET driver IC such as the ICL7667 with IRFZ44n or is it better to use a lower VGS MOSFET such as the AO3400, or something entirely different? I'm open for suggestions. What are the cons and pros for both, since it's only one time investment cost is not the issue? I will make the PCB, so I prefer SMD components. AI: which is best for fast switching do I need to use MOSFET driver IC such as ICL766 with IRFZ44n or is it better to use lower VGS MOSFET such as AO3400 You don't want fast switching to drive LED strips! If the FET switches in a couple tens of nanoseconds, you will send very high di/dt currents into your wires which will radiate electromagnetic interference and essentially act like a broadband radio jammer. Remember a signal with 10ns edges has bandwidth extending to hundreds of MHz... On the contrary, you want slow edges, like 0.5µs - 1µs. This increases switching losses, but your PWM frequency is going to be low anyway, so switching losses, which are proportional to frequency, will be low too. Let's check the math: Conduction losses = RdsON * I^2 * DutyCycle For 2 amps and a duty cycle of 1 (100%) a FET with RdsON of 40 mOhms dissipates 0.16W -- you can use a FET with lower RdsON if you want. Switching losses = V * I * SwitchingTime * Frequency For 12V, 2A, 500ns, 10kHz losses will be 0.12W. Note these losses are already a bit high for a SOT23 FET. I'd use a SO8 single or dual FET instead, they have better dissipation and they're pretty cheap. Say you want to switch an AO3400 in T=500ns, total gate charge is Qg=7nC so gate drive current will be roughly Qg/T = 14mA. For this you don't need a specialized gate drive IC. If you have 5V available, you can use a 74HCT logic gate as voltage translator between your 3V3 micro and a 5V "logic level" MOSFET. It's cheap and it'll work. If you only have 3V3 available and no 5V, and you don't want to bother with a separate 5V supply, then it makes sense to use a FET that is compatible with 3V3 drive. Depending on the gate drive current required, and the output drive capability of your micro, you might want to add a logic gate as a buffer too. 74LVC for example.
H: how to determine architecture core detail of ARM11 processor I'm cross-compiling for an embedded Linux board, based in BCM5892 ARM11 processor. I need to know about architecture detail of this processor(‘armv6’, ‘armv6j’, ‘armv6k’, ‘armv6kz’, ‘armv6t2’, ‘armv6z’, ‘armv6zk’) for feeding -mcpu flag for compiling my application, but there is no such information in Broadcom website and manufacturer does not provide any information too. then is there any way for determining this information from Processor or OS? AI: From this website, the answer is ARMv6TEJ: ~ $ cat /proc/cpuinfo Processor : ARMv6-compatible processor rev 5 (v6l) BogoMIPS : 398.13 Features : swp half thumb fastmult edsp java CPU implementer : 0x41 CPU architecture: 6TEJ CPU variant : 0x1 CPU part : 0xb36 CPU revision : 5 Hardware : Broadcom BCM5892 Chip Revision : 0000 Serial : 0000000000000000 Also confirmed from the Linux boot messages here: [ 0.000000] Linux version 2.6.32.9 ([email protected]) (gcc version 4.2.3) #72 PREEMPT Mon Mar 19 01:37:54 EDT 2012 [ 0.000000] CPU: ARMv6-compatible processor [4117b365] revision 5 (ARMv6TEJ), cr=00c5387d [ 0.000000] CPU: VIPT aliasing data cache, VIPT aliasing instruction cache [ 0.000000] Machine: Broadcom BCM5892 Chip
H: How could this circuit be reduced to first order low pass filter? I was told that the bottom half of the circuit wouldn't matter due to having a corner frequency being significantly higher compared to the top half, or due to time constant (somewhere along this line..). Can you please help me understand why? How would I go about reducing this to a first order low pass filter? (just one resister, one capacitor). Thanks in advance. AI: The simple answer is to recognise that C1/R1 and 1Meg/13pf is a special case, given the application : it is almost certainly a 10:1 oscilloscope probe. 1 Meg and some small C is a standard scope channel input : the precise value of C is undefined but happens to be 13 pF fro this scope. Then R1 is 9 Megohms to give the correct DC attenuation, and C1 is adjusted for a flat frequency response (actually, an accurate square wave response) each time you plug that particular 10:1 probe into that particular scope. (Calibrating the probes is just a routine part of using a scope. The scope will provide a "CAL" output for that purpose, and the correct plastic trimming tool lives in that pouch on top of the scope.) The probe output is then a perfectly scaled version of the probe input, with the same frequency response. Which means you can model the entire circled block as Cp in parallel with 1.3 pF and 10 megohms (followed by a perfect 20dB attenuator) Given the source impedance of 50R, you can for all practical purposes ignore the 10 megohm probe resistance, giving an attenuator composed of 50R and (Cp + 1.3 pF) to which you now have to add the impedance of the cable.
H: Is it acceptable to use decoupling capacitor ground pad as ground for oscilloscope probe? If one were to probe with an oscilloscope using the short ground spring clip attachment, and use the ground pad of a decoupling capacitor as the ground, would the measurement be thrown off at all by currents moving to ground through the capacitor? Or is something like a test point pad on the top layer ground pour required for peak accuracy? Say I'm probing a pin on an IC and using a local decoupling cap ground pad as the ground as shown in the pic, would this measurement be free of any noise from the cap? If not then what would be the best practice method to do this? Thanks. AI: In general you want to minimize the loop area when probing fast signals. So, as a rule of thumb, you should select the ground connection that minimizes the loop area. Now this is only in general. There may be good reasons to use the capacitor ground. This is due to the resonances in the ground plane. Your ground plane will not be zero volts everywhere for all frequencies. It will look something like this: source This shows the voltage of the ground plane at a specific frequency. What’s worse is that this can change dynamically depending on the power consumption of the ICs. If you select a ground reference near a resonant mode, high frequency noise can enter your probe, due to the fact that the ground plane reference will be oscillating at the resonant frequency. The thing about decoupling capacitors is that they suppress the resonances in the power planes. In fact this is how you prevent unwanted resonant modes near your frequency of operation. However this all depends on the geometry of the planes, the value of the capacitor (the smaller the better), power consumption of the ICs, frequency of the ICs etc. So it all depends on your specific situation. As I said, try to minimize the loop area as a general first approach.
H: Finding a current in a given circuit The problem has given the following circuit: And asked to find the value(s) of Ix if the elements absorb the power(s) given. I tired to set up KCL/KVL but I keep getting stuck. I first drew this: And set KVL1 = (Ra)(i1)-(Rb)(i2) KVL2 = (Rb)(i2)+(Rc)(i3) After that I am confused on how to continue without knowing the resistances. AI: You could use the fact that the power in a closed system is conserved. That is, the sum, $$\sum_i P_i = 0$$ Where, $$ 0=P_{V_0}+P_{R_1}+P_A+P_B+P_C.$$ So, $$ 0=-I_XV_0+R_1I_X^2+48-8+40.$$ Hence, $$ 0=-48I_X+4I_X^2+80.$$ This will give you two possible values for \$I_X\$. Maybe both results are ok, or there is a way to further determine which of the \$I_X\$ is the right one. If someone wants to further deduce it, please go-ahead.
H: What is the cause for a 180 phase shift between current and voltage in LT-spice simulation Just by clicking on the resistor, I got a display of the plot of current passing through it, marked with I(R3). In my opinion it must be in phase with the voltage across the resistor, but on the screenshot it seems to be different, could anyone help me to understand it? AI: Turn the resistor around. :) Electric current has a direction, it is not a scalar property of a resistor. And there is no a priori given "positive" direction neither. Spice simply assumes that the current flowing from one resistor terminal to another has positive sign and opposite direction is displayed as negative. Because terminal numbering is "hidden" and the visual symbol has both terminals indistinguishable, it can be a bit perplexing. LTspice will hint you what is the positive current direction by changing the cursor shape when you hover it over the component in "probe" mode.
H: What does D2 do in this schematic? Can somebody clarify what the purpose of D2 is in this schematic: I understand that we are taking a clock input from the Sync jack to the transistor. The reset pin (4) is pulled high to Vcc, until the NPN transistor is activated (pulled high) and it then drops the pin 4 to GND through the transistor. (Can somebody please clarify if my wording is correct with this description? How could I be more clear when speaking about transistors?) However, I do not understand what the D2 diode is supposed to do. Is it some sort of protection in the case of an incorrect input at the Sync jack? Isn't that what the de-coupling cap is for? AI: From the look of it D2 is to protect Q1's base emitter junction from excessive reverse voltages. The presence of C2 means the Sync input signal is AC coupled and it eliminates any DC bias, but now the Sync signal will attempt to drive base of Q1 equally positive and negative. In the positive direction the b-e junction will conduct in normal transistor operation, but on the negative excursion there would be nothing to limit the voltage if D1 were not in place. D1 also serves to clip any negative noise pulses if they are present in the environment.
H: Verilog -- how to assign mux/selector output to module's output Verilog beginner here. Working with Lattice Diamond for a design using the MachXO2. For context: I recently got this answer to a related question. See the second image in the answer. I want to implement a dblbuffer module that internally has the two FIFOs as shown in that diagram (FIFO_DC module from their IPExpress; module name is fifo_dc), and externally just has input data / write clock, and output data /read clock (plus some additional auxiliary signals, not relevant to this post/question). I can't seem to connect the output from the selector/multiplexer to the module's output: module dblbuffer (data_in, wr_clk, out, rd_clk, save_current); input wr_clk, rd_clk, save_current; input [15:0] data_in; output [15:0] out; reg selected; // a buffered/synchronized/edge-detection version of save_current // (details related to it omitted here for simplicity) always @(fifo0.Q, fifo1.Q, selected) begin out[15:0] <= (selected ? fifo1.Q[15:0] : fifo0.Q[15:0]); end fifo_dc fifo0 ( .Data(data_in), .WrClock(wr_clk), .RdClock(rd_clk), // ··· .Q(), // Should I leave Q unassigned, to be used as above? // ··· ); fifo_dc fifo1 .... The synthesizer gives me procedural assignment to a non-register out is not permitted. VERI-1100. So, I try adding: reg[15:0] out_wires; assign out_wires[15:0] = out[15:0]; And now it tells me concurrent assignment to a non-net out_wires is not permitted. VERI-1195. I thought it was related to the = vs. <=, but trying that with the <= gives me a plain syntax error (syntax error near <=. VERI-1137). If I simply try reg[15:0] out_wires = out[15:0] it tells me that out is not a constant. VERI-1188. I hope it's clear what I'm trying to do so that someone can point out the correct syntax (or the correct structure, if what I'm doing wrong goes beyond just syntax). Thanks! AI: It would be simpler to just declare the output port as reg (instead of the default, which is wire): output reg [15:0] out; But you don't really need the always block anyway, so just write: output [15:0] out; assign out[15:0] = (selected ? fifo1.Q[15:0] : fifo0.Q[15:0]);
H: 1602a LCD - Voltage drops to zero when both VSS and VDD are connected I'm currently trying to connect a 1602a LCD screen to an ATMega328P MCU: As you can see, I use an Arduino Uno for power supply and as ISP. However, when I connect both the first (VSS) and second (VDD) pin of the LCD screen, the voltage in the breadboard drops to zero (Arduino also stops blinking its leds). I was wondering what is causing this voltage drop? Is this possible because of bad soldering or a short circuit? When I connect VSS without VDD and vice versa the screen turns on. Here is closeup picture of the LCD holes: AI: You have errors in the wiring. Don't connect display VDD to ground, but to 5V. That error has caused excess current to flow out of AVR IO pins, via LCD input protection diodes to ground. Also, don't connect the contrast pin Vo directly to ground either - just via resistor to ground, or the display will be too dark, just black squares. And finally, there is no current limiting resistor on the backlight, most likely there is no internal resistor and it needs external one or it will draw too much current and might break something.
H: What is a good technique for a soldering novice to connect IC pins to female pin headers on a protoboard? I have protoboard, an 8 pin socket adapter and two sets of female header (4 pins). I want something a little more permanent than a bread board to use when programming ATTiny85s with my Arduino. I think being able to seat the ATTiny into the socket and then access all the pins directly on the female headers will be convenient. My issue is that I am a super novice at soldering. I seated the header pins right next to the pins for the socket adapter. Then soldered all the socket pins and the header pins. The issue is connecting the two. I read about people who connect solder directly to bridge the adjacent points. And also people who bend pins to make the connection. Both sounded like great options to me in theory. The problem was the pins are way too small for me to use the tools I have at my disposal to bend. They wouldn't reach anyways. I thought no problem, I'll just bridge solder from the Female header pin to the appropriate neighboring socket pin. But alas I suck at soldering so I ended up connecting it with the other adjacent solder as well so connecting 3 pins together when I wanted to connect two. I attempted to cut a little tiny piece of wire and place it in between the two pieces of solder but it wasn't very stable just sitting there so I didn't even try it. A complete solder fail. What technique should I be looking at to research to try and solder two adjacent pins together in a crowded area where I don't want to accidentally make a connection to other nearby pins? AI: Use a PC board that has connections laid out like a plastic breadboard - groups of 5 holes connected together.
H: An ideal op amp is given (with infinity gain), what is the current flowing through all the resistance for the given circuit? my problem is that do the output terminal of the op-amp behaves like short circuit of output terminal of the op-amp to its reference ground as shown in the ideal op-amp internal circuit? AI: It is unclear from those diagrams how current flows from the op amp output pin back to ground. Current must flow in a complete loop, which involves the +DC supply, and the -DC supply going to the op amp. So let's take your example 10 ohm circuit and see where current flows. There will be one amp of current flowing in this circuit. Your ideal op amp will maintain its output voltage at zero volts (because its two input pins will be at 0V). simulate this circuit – Schematic created using CircuitLab One amp flows through the 10V supply (V1), through R1 and into the op amp output pin. From there, it continues through the op amp to the -DC supply (which is grounded). That's a complete loop. No current flows through R2, and no current flows through R3. No current would flow through the +ve supply in this ideal case. In a real op amp, internal circuits draw a little extra current from its DC supplies.
H: Charging Li-Ion with BMS and CC-CV DC converter I'm currently building my own electric longboard and even though I looked through some resources considering this, I am not a 100% sure that I am on the right path. I want to use a 10S2P battery pack, consisting of Samsung's 30Q 18650 and I bought a 10S BMS with balancing capabilities. Now I need to charge the battery pack. Since it is 10S the charging in the first stage would be 42V for CV and below 6A for CC. I saw videos online where they simply use a Buck-Boost-Converter, which is capable of CC-CV. To my understanding, that would only cover the first stage of the charging process. Questions: What happens afterwards, if the CC-CV converter is still connected, even though first stage is over? I somewhere read, that CC-CV is from an electronics point of view simply CC, so the voltage might vary. Are there fatal consequences to be expected, if the converter is connected for too long? What happens in that case? If the first stage is over, there might be a chance that the CC-CV converter (which is really only a CC as I read, in case that's even correct) puts out more than 42V which is definitely a hazard for the Li-Ion cells. But since I am using a BMS (with overvoltage and balancing capabilities) I should be safe from this, right? Are BM systems in general capable of doing overcharge protection? voltage- and current-wise? So simply put: Can I connect the BMS to CV 42V and it will take care of everything? I could not really find specific answers to these questions, but hopefully you can enlighten me. Thanks in advance. AI: I somewhere read, that CC-CV is from an electronics point of view simply CC, so the voltage might vary. CC-CV stands for Constant Current and Constant Voltage, which means both voltage and current are regulated. If the battery does not accept the set current then the voltage will be held constant and the current must go down. This is the standard charge profile for Li-ion. Are there fatal consequences to be expected, if the converter is connected for too long? What happens in that case? The booster should continue to hold the battery voltage constant forever, and the battery should handle this. However at maximum voltage the battery's lifespan is reduced, particularly at high ambient temperature. An hour or two at full voltage is fine, a week is not. If you have to float continuously then reducing the voltage from 4.20V to 4.15V or 4.10V will increase lifespan with some reduction in capacity. To check that the booster maintains a safe voltage, simply set it to the correct voltage with no load. Then charge a battery with it and measure the voltage regularly as it gets close to the end. It should not go above 4.20V per cell. there might be a chance that the CC-CV converter... puts out more than 42V which is definitely a hazard for the Li-Ion cells. But since I am using a BMS (with overvoltage and balancing capabilities) I should be safe from this, right? Yes, in the unlikely event that the charger malfunctions the BMS should disconnect the battery before any serious harm occurs. However to avoid interfering with charging the BMS must cut off at a higher voltage than the normal peak voltage, so there is still a chance of cell damage occurring. Also some BMS circuits have an uncomfortably high cutoff voltage that may not be very accurate. Are BM systems in general capable of doing overcharge protection? voltage- and current-wise? So simply put: Can I connect the BMS to CV 42V and it will take care of everything? Most BMS circuits protect against over and under voltage and over-current. This should protect the battery from catastrophic failure of the charger or device being powered. It won't prevent long-term damage due to consistent floating at maximum voltage, drawing high current, discharging below the normal cutoff voltage or charging at a high rate when the battery is deeply discharged. If the BMS has balancing then it should be able to maintain balance provided that the cells are fairly well balanced to start with, and the charge current is not higher than the balancing current. For the first charge you should measure cell voltages regularly and reduce the charge current if they are not all within +-0.03V of each other. Balancing may take several hours if the imbalance is more than a few tenths of a volt.
H: Why do we need to use transistors when building an OR gate? Why do we need to use transistors when building an OR gate? Wouldn't we be able to achieve the same result without transistors at all, just by joining the two inputs and reading the output? AI: What you describe is called a wired OR connection. It is possible in some logic families, particularly ECL (emitter coupled logic), but not in the most common ones (TTL and CMOS). In CMOS it isn't possible because when a CMOS output is low, it creates a very near short from the output pin through the chip to ground. And when it is high, it creates a very near short from VDD through the chip to the the output pin. So if you tied two CMOS outputs together and one output high while the other output low, you'd have a very near short from VDD to ground, which would draw a large current and likely overheat one or the other of the two chips involved. For TTL, there's a similar issue, but the "shorts" from the output pin to VDD or ground aren't quite as near short as they are in CMOS. There's a variant output style, called open drain for CMOS or open collector for TTL, that allows wired AND connections rather than wired OR. These outputs are designed to only be able to sink current to ground, not to be able to produce any output current when they're nominally in the high state. These are normally used with an external pull-up resistor so that the output voltage will actually reach the "high" voltage level when required. Note: Open collector or open drain can be used for wired OR if you use active-low logic (low voltage represents logic 1, high voltage represents logic 0).
H: How to get right voltage output with Bts7960b H-Bridge? I am using a NodeMCU to control a BTS7960b motor driver. (datasheet of the BTS7960) This driver controls a 12v dc motor. This image shows my wiring (without the display and the buttons and with a NodeMCU instead of the Arduino nano). My problem is, when the driver is set to maximum speed (the pins L_EN and R_EN set to high, as well as either LPWM or RPWN to 255 [pin naming visible on this page]) the output voltage to the motor is consistently only 3v instead of 12v. Because of that my 180 RPM high torque motor just runs with about ~42 RPM. Decreasing the speed also decreases the output voltage. E.g. setting the speed to 150 decreases the voltage to ~1.8v. It doesn't matter in which direction the motor is turning. The motor, NodeMCU and driver are powered by the same power supply with a buck converter. I get the same behavior with 3.3v and 5v on the NodeMCU and the driver. What am I doing wrong? Thanks for the help! :) AI: Thanks to the hints of @Peter Karlsen I figured it out: I was used to the 8 bit resolution for PMW of the Arduino boards. But since my NodeMCU uses an ESP8266 Chip the PMW resolution is 10 bit [reference]. So the max value is not 255 but 1023. Changing the values in my code solved the problem.
H: Output capacitors placement in PCB Having a LDO output that is connected to digital circuitry, I would like to know the best way on how to place the bypass capacitors in this network. Is it better to place higher capacitance ones near the chip and low capacitance ones further away? AI: Considering capacitors having the same chip style, capacitors with higher capacitance have a lower resonance frequency, so the parasitic inductance will dominate at a (relative) lower frequency and therefore work worse for higher frequencies. Source: "parasitic inductance of multilayer ceramic capacitors" from AVX The parasitic inductance is dependent on chip size as is explained in referred document. Increasing capacitance sometimes requires a bigger chip size (due to availability/pricing), so a bigger capacitance might increase inductance as well, but not necessarily (compare Table 3 in refered document). In order to reduce EMI, current loop areas should be as small as possible, especially the high frequent current onces. Therefore, generally, you should place the capacitor with the lowest capacitance closest to an IC and capacitors with higher capacitance further away. UPDATE The explanation regarding smaller current loop areas above applies for input capacitors (C1 and C2 below) as well as for output capacitors (C3, C4 and C5 below). When placing a higher valued capacitor (C4) closest to the output of a device (and leaving out C3) and a smaller valued capacitor (C5) further away, the smaller capacitor (C5) hardly contributes with respect to the output of that device. Still there can be a smaller valued capacitor further away (shown as C6), but it is more likely that that capacitor serves as input capacitor for the electronics connected after it. simulate this circuit – Schematic created using CircuitLab In case of LDO's: a LDO may become unstable when placing too small valued capacitors at the output (due to low ESR). Moreover, a LDO is not a switching mode supply, so, there is no need to reduce high frequent current loop areas at its output. So, only a big capacitor at the output of the device will be sufficient.
H: How to draw ~1A from Li batteries without damaging/over-stressing them? I have designed a micropump driver powered by 2x AA (Li) batteries, the pump is piezoelectric and requires 27V. The pump requires a switching waveform, at the battery side this draws (including inefficiencies and driver consumption) 400mA and 900mA at the battery voltage which is nominal 3V (depending on the pressure being created by the pump), the batteries won't really see the switching because I am using a H-bridge and so there are two signals that are orthogonal to eachother and other than the small (ns) deadtime between them the boost converter will only see a DC drain (and even the deadtime will get lost in the feedback loop response time of the SMPS). Several problems have arisen: After a failed life-cycle test I measured the voltage across the batteries, one was sitting at 0.2V the other 1.47V, they are used in series, so why would one battery have such drastically different voltage? Does this suggest damage? or simply one is much more drained that the other? I'm using boost solution that can boost from ~1.5V up to the required 27V. I have noticed that the someway into a test the battery voltage drops off during a pump cycle, very quickly dropping below 1V and after the cycle ends quickly recovering to 2.8-2.9V, does this suggest I am drawing to much current out of the battery? or that the battery is damaged or simply running dry? I assume my design is damaging or stressing the batteries somehow, are there any standard practices to be used in this scenario? Based on a constant discharge test with reference to the battery manufacturer I estimate that the batteries that drop off in voltage drastically after a period of time being used are less than 1/3 discharged. I.e with a load drawing a defined constant current and measuring teh voltage across the terminals and comparign this with a the discharge curve (http://data.energizer.com/pdfs/l91.pdf) Unfortunately I can't upload schematics due to confidentiality agreements with the customer, however I'll provide whatever additional information I can. AI: Batteries have different capacities and the one with the lesser capacity will define how much capacity you get from a series connection of multiple cells. As you can see in the datasheet you linked, the cells will hold their voltage pretty constant until they drop off a cliff at the end. So I don't think you have a strange behaviour with one cell at 1.47 V and the other at 0.2 V. Both are actually discharged. Here is a relevant document explaining that cells which have an open circuit voltage of less than 1.7 V are to be considered discharged when they had the chance to rest (and recover their open circuit voltage) But there is a second effect happening which might be the troublesome part for you. As the cell gets discharged, the internal resistance rises. So if one cell is drained the internal resistance might be too high for you to draw all the current you need. Third thing is that your current requirement will rise during discharge. While it is 1 A at 3 V at the beginning it will be 2 A at 1.5 V when the batteries are almost dead which is overstressing them. The effect you see in 2. is the battery relaxation effect. I think that the batteries are running dry and you are in the region where the internal resistance is rising. In that state you can extract energy of the battery only with a smaller current. Depending on your SMPS design, it might draw peaks which are a lot higher than your average current, which will stress the batteries even more. You could try to reduce the problem with a really low ESR capacitor bank which provides the peak currents while the batteries then provide the average current.
H: Lumens specs when buying a flashlight/torch. Why maglite has only 680lm but cheap ones have 900,000? I am working as a night delivery driver and when its dark and/or rainy it's almost impossible to read many of the house numbers/names I am looking for. I've heard of Maglite and in fact my friend has a large Maglite which is 680lm and very powerful but it cost him a fair bit and uses huge batteries. I look on auction website and see ones boasting 900,000 lumen output! (for about £5 :D) I then google 'worlds most powerful flashlight' and it seems one made by 'Wicked Lasers' is considered one of the most powerful at 4,100 lumens. (https://www.wickedlasers.com/torch) So why on auction site are they allowed to state 900,000 lumens. And how can i trust the output specs on any advert? (is there any other spec I should be checking)? Really need it soon, and I need to be able to see stuff that is about 20-30 metres away in heavy rain at night. Any help would be greatly appreciated. Thanks (Ps. I could put links showing the adverts boasting 900,000lm but didnt want to put their links anywhere in case they are a scam) Additional Edit:- Well I have continued looking and the specs vary massively. This one I am thinking of buying boasts 20,000 lumens and 500m range. But it only takes 1x AAA battery ??!?!? - Surely this cannot be 20x more powerful than a top Maglite? https://www.ebay.co.uk/itm/Tactical-20000LM-L2-Zoomable-LED-Flashlight-Rechargeable-battery-Torch-with-BOX/322609536378?epid=16031184130&hash=item4b1d06dd7a:g:SwQAAOSwmcNdIJWc) Conclusion: For what it's worth I decided not to buy a 'No-name' brand. And after finding this one at Toolstation: https://www.toolstation.com/ledlenser-tt-police-tactical-torch/p41307 I realised their pricing is actually very competitive. It is a few quid cheaper in Toolstation than the same torch is on Amazon or ebay. I can just go into the shop and buy it today :D I am happy now, thanks again all you guys. PS. You have inspired me to begin learning electronics as a new hobby too AI: Well in your eBay-Link they are providing enough material to debunk themselves. They say they use a Cree XM L2 LED. So let's just look up what that thing can output. Datasheet XM L2 LED and we see: even if it is driven with 2000 mA - which is quite the stress on the battery - it outputs 600 lm. And they kindly provided a picture showing that they only use one LED and not multiple. So they are lying or they measures the first production batch in unison and forgot to say they used 400 of these things. Generally, you can expect around 100 lm / W and a handheld device is probably using 10 W maximum (okay might be 20 W or so with a good battery), so anything beyond 2000 lm is just unrealistic. If they tell you the 4000 mAh battery will last 6 hours, you can calculate the wattage: 4000 mAh / 1000mAh/Ah * 3.7 V / 6 h = 2.5 W. So 250 lm would be a realistic guess for the brightness. And yes, the 4000 mAh are faked as well - currently 18650 LiIon are around 3200 mAh maximum. Okay, so how does the "brightest torch" from wicked lasers hold up with these estimates? They claim 4100 lm using a 100 W OSRAM halogen bulb. The datasheet of that bulb tells us it emits 2800 lm. (Edit: the reflector does not affect the luminous flux, sorry about my mistake I often mix up the luminous units) I'm not really sure how they arrive at the 4100 lm figure - with 100 W it would be 41 lm / W, which is unrealistic high for a halogen bulb. So probably a bit of overadvertisement to stay with the claims of the cheap competition. What about the power of this thing? They claim 100 W which sounds ridiculous. But they use 4 18650 batteries in series and give a low estimate of 20 minutes lifetime. Sadly the capacity is not given, but this is a really high current application, so the capacity will be a bit smaller - I guess 2500 mAh for a high quality cell. 4 * 2.5 Ah * 3,7 V / 20min = 111 W So the math actually checks out and I think that it does what they say.
H: NVG compatibility LED Lights For an avionics application I need to make a keypanel which has NVG compatible LED lights behind its keys. I am trying to understand how does the NVG compatibility (Night vision Goggles) relates to the LED light? If I put a high-glow green color LED behind a keyboard button will it be enough for making it NVG compatible? Or do I need to apply any specific filter on top of the LED and that filter will make a normal LED into a NVG compatible LED light? AI: MIL-STD-3009 and MIL-L-85762 detail the spectrum requirements for NVIS compatible lighting, and include the sensitivity spectra for the for different classes of tubes. The aim is to minimize the output of light that is in the sensitive area of the NVGs. For incandescent lighting this was an issue since most of the output is in infrared, but LEDs generally have fairly sharply defined outputs. You'll need to look at the datasheets of the LEDs you intend to use, but the overlap looks to be pretty small for this random green LED I had a datasheet for. It's a pity that the lighting has to be green, blue LEDs centered at 480nm output have no overlap at all.
H: Circuit with dual power supply Doing some reverse engineering to a PCB, I drew this part of the circuit. Looking into the datasheets, I found out the comparator (LMC6772) is able to drive the SCR (S6S2) by itself. But the designer used a PNP transistor in between. I see that the comparator is fed with single power supply, so I assume the PNP is to do some kind of shift as the SCR is referenced to -13V. Why would the designer do this? It's like the current from the coil is sinking to -13V instead of the ground, but why? If you need more details about the circuit I can expand the drawing, but that's the basic concept of my question. Below there's a link which is a follow up of this thread. Some notes: TR1 in the old thread is U5 in this thread. V+ in this thread is the point between R2 and R3 in the old thread. L1 in this thread is the coil in parallel with D9 in the old thread. R20 in this thread is (R2 + Rds (FET)) in the old thread. In this thread, I just drew the circuit for simplicity, since in the old thread the path from R3 is bypassed when the SCR is fired. Understanding this power supply design AI: Looking into the datasheets, I found out the comparator (LMC6772) is able to drive the SCR (S6S2) by itself. You are mistaken about that. The LMC6772 has open-drain outputs, which means that they can only sink current, not source it. However, the SCR requires current to be driven into its gate terminal for triggering. Therefore, the PNP is required to convert a current sink into a current source. It really doesn't matter to the transistor whether the current is returned to ground or to the negative rail. Either way, the loop is completed through one or both power supplies.
H: Given a diode circuit and some of its values, how do I find the temperature? Let's say I am given the following circuit: along with $$dV_p/dT=0.139mV/K$$: Defining V1 the voltage above Diode D1 and V2 the voltage above diode D2 , we use the expression for the current of a diode for both diodes : $$I_{D1}=I_{S1}e^{\frac{V1}{V_T}}$$ $$I_{D2}=I_{S2}e^{\frac{V2}{V_T}}$$ If we solve with respect to the voltages, we get : $$V_1=V_T\ln{\frac{I_{D1}}{I_{S1}}}$$ $$V_2=V_T\ln{\frac{I_{D2}}{I_{S2}}}$$ Subtracting, we finally get Vp : $$Vp=V_T\ln{\frac{I_{D1}I_{S2}}{I_{D2}I_{S1}}}$$ What I know for sure, is that the thermal voltage VT depends on temperature and it is given by : $$V_T=\frac{kT}{q}$$ I think that the saturation currents depend on the temperature as well. However, will these currents be different? Or can I just cancel them out in the logarithm above? Cancelling them out, the result doesn't make sense: $$\frac{dV_p}{dT}=\frac{k}{q}\ln{\frac{I_{D1}}{I_{D2}}}$$ The result is different form the given value of 0.139 mV/K and does not depend on T so I get no information from here. So, it seems I can't cancel out the saturation currents . After looking it up, saturation currents seem to depend on : $$n_i^2=(5.2\times10^{15}T^{\frac{3}{2}}e^{\frac{-E_g}{2kT}})^2$$ However, even if I use the long expression for the saturation currents, ni1 and ni2 will still cancel out in the logarithm. Therefore the dependence of Vp on T vanishes even if the saturation currents depend on it. Long story short, this was my attempt at a solution. How do I find the temperature? AI: Obviously you can't ignore the Is temperature dependence or the diode temperature coefficient would be of the opposite sign (let alone the magnitude) of what we know it to be (~-2mV/K). But basically you have the answer. Vp = \$ \frac{n KT}{q} (\ln{(\frac {Id1}{Is}}) - \ln{(}{\frac{Id2}{Is}})) = \frac{n KT}{q} \ln{(\frac {Id1}{Id2}}) \$ dVp/dT = \$\frac{n K}{q} \ln(5) \$= 0.139mV/K so n = 1 (ideality factor) (if you got a different number, check your calculations here) So the temperature T = \$\frac{Vp}{0.139mV/K}\$ (it's simply proportional to absolute temperature of the junctions, assuming they're the same temperature, of course) eg, If Vp = 50mV then T = 56.6°C
H: Looking for gyroscope drift spec in datasheet The product page of the BMI088 IMU makes the very impressive claim The automotive-proven gyroscope of the BMI088 has an unmatched bias stability of less than 2°/h However, I can't find this claim anywhere in the datasheet. The datasheet does contain Zero-rate Offset, Zero-rate Offset Change over Temperature, and Zero-rate Offset Supply Voltage Drift, but not Zero-rate offset drift over time. What would zero-rate offset drift over time be called in the datasheet? If it isn't included, can it be derrived from other specifications in the datasheet? AI: BMI088 is offering a wide acceleration measurement range (up to 24 g), high vibration suppression ratio and vibration robustness, as well as high bias and temperature stability. The automotive-proven gyroscope of the BMI088 has an unmatched bias stability of less than 2°/h and a low temperature coefficient of offset (TCO) below 15 mdps/K. Source: https://ae-bst.resource.bosch.com/media/_tech/media/product_flyer/BST-BMI088-FL000.pdf I don't think I would believe that either unless listed in the datasheet. Only the temperature drift is listed in the datasheet. You would have to know the internal workings of their Kalman filter and how the errors of the gyroscope are being integrated to be able to calculate this yourself. The best course of action would be to contact Bosch and ask them about the drift rate and to put that figure in the datasheet.
H: Conversion from fixed point to IEEE 754 I am trying to design a simple processor (in VHDL) that takes in its input a real number coded in the fixed point representation in 2's complement (10 bits for the integer part, and 6 for the fractional part), and outputs its IEEE 754 single-precision format equivalent: I have been searching for a while now, and still couldn't find any resources on this type of conversion, at least some flow chart from which I could start. AI: Basically, you do four things: convert from 2’s complement to signed magnitude, save the sign count leading zeroes (find first ‘one’) add a bias to that to make the exponent shift the integer to normalize it as the mantissa. About four lines of code that synthesizes to some logic, an adder, and a shift mux. EDIT: As Tim said, before you do all that you also need to convert the 2’s complement integer to signed magnitude. So one more line.
H: Strange "step" in i2c plot I have some errors during debugging I2C chip. I took an oscilloscope and found some strange artifacts on the log: Maybe somebody has a suggestion about such questions? 1. What are these strange spikes at the beginning of each clock cycle? 2. Why SDA data ground level have different values? AI: SDA has different low levels depending on whether the master or slave is pulling it down. This is actually a useful debug tool because you can tell who is controlling the SDA at that moment. You will probably eventually wish to determine why they are pulling down to different grounds, though. The spikes are overshoot, caused by impedance mismatch.
H: Can I trust in visual inspection to identify LED terminals? In the figure above, LED A is a regular 5mm LED and the visual identification of its terminals polarity is well known. As you can see, on LED B the anode is identified by the longer leg, but the other rules for visual identification are inverted. I've confirmed the situation above with a multimeter. I have no datasheet or reference for LED B. I never saw an LED with these issues before. Is LED B the result of a manufacturing error? Thanks in advance. AI: Super-Red (AlGaAs) LED dice are mounted the opposite way of most others, so they appear backwards from the silhouette of the leadframe. The leadframe pin length should tell you the difference but there's been a case of one identified in another question here that's reversed even for that (presumably so they didn't have to buy two leadframe types or trim them differently- it's described in the datasheet so it's not an error). So, the bottom line is "no" you can't trust anything that's not specified in the datasheet (and even then, stuff happens, I've seen a 1N400x diode with reversed markings, presumably dropped and replaced on the line- post test, pre-marking by a worker in Taipei where the factory was at the time).
H: Read 8 serial ports at the same time with an Attiny I'm building a MIDI merger, based on a Attiny (either 84 or 85). How to read multiple serial ports at the same time (for example 8 RX inputs)? I can't find the blog article anymore, but I think I did read that it's not as easy as instancing multiple SoftwareSerial objects like this: #include <SoftwareSerial.h> SoftwareSerial Serial1(3, 4); SoftwareSerial Serial2(5, 6); void setup() { Serial1.begin(31250); Serial2.begin(31250); } void loop() { if (Serial1.available() > 0) { a = Serial1.read(); } if (Serial2.available() > 0) { b = Serial2.read(); } } What is the recommended way to do this? AI: This is possible... but hard. The idea is to sample all of the GPIO pins at least 2x the rate of the serial bitstream and use software to decode any data that comes in. You probably want to do the sampling in a timer-driver ISR and have it store the sampled level bytes into a circular buffer. Then the foreground process can pull sample bytes out of the buffer and decode the levels into data bits and bytes. If you can assign all the serial pins to the same port (like PORTA on the ATTINY84), then you can very efficiently grab all the levels at once with a single IN instruction and efficiently store them in the target buffer as a single byte. If you can sample at 16x the data rate then you can even do edge sync like a good hardware USART does.... Of course even at 20Mhz, this is a lot of work for a little ATTINY so you will be limited to the max baud, max duty cycle, and max processing you will be able to do before you run out of steam.
H: PCI-e jtag interface I am looking for information on JTAG interface on PCI-e 1x connector. Do anyone has an informaton how to program it? I would like to use it to program microcontrollers and FPGAs. AI: JTAG interface in PCIe connector is optional as per PCI-SIG. They won't define any specifications for these pins. They are defined as per 1149.1. You have not specified this question in the perspective of addin card or host. If you want to program devices on JTAG inside Add-in card from Host, then connect this pins to PCIe connector and see support in host side for programming this. Below is the snap from CEM
H: Buck Converter - Inductor CCM and DCM I have a doubt while selecting the inductor for a buck converter. TI App Note In This app note, in the abstract itself, they mention that this : This application report gives the formulas to calculate the power stage of a buck converter built with an integrated circuit having a integrated switch and operating in continuous conduction mode. This not mention anything about the DCM mode. So, does it mean that, if I follow the mentioned steps in the app note, for my Vin, Vout and Iout, I will not enter the DCM mode? I understand about the DCM mode. But in this case, what care should I take while designing such that my selected inductor does not enter DCM. Vin = 3.3V Vout = 1.8V Iout = 0.4A Selected Inductor = 22uH AI: what care should I take while designing such that my selected inductor does not enter DCM. If the chip itself can handle the transition from CCM to DCM then that should be OK. Changing from one mode to the other necessitates a change in how the control loop works and, if the chip is capable of handling this change automatically (many are of course) then there's usually no need to worry. On the other hand, if you designed the inductor for DCM mode and it entered CCM mode you might get problems but, this is not usually due to the chip. DCM requires an inductor of lower value and, as such never sees the same peak current as might happen in CCM mode so, under these circumstances, the inductor might saturate. Going from CCM to DCM usually isn't a problem and quite often happens when the load is very light because DCM can handle much lower energy transfers per switching cycle.
H: Using a CMOS 555 as a window comparator I've been working on a small project inspired by this question that uses a CMOS 555 timer as a power button controller (short press to turn on, 3s hold to turn off), the goal being to design a micropower circuit that can operate across a wide supply range. To do this, I use a CMOS 555 as a latching window comparator, and have separate RC networks connected to the THRES and TRIG inputs, as shown in the schematic. While researching different CMOS 555 timer options, I found the datasheet for the TLC555 has the following disclaimer about the quiescent current: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG. Does this imply that the TLC555 will draw an excessive amount of quiescent current if THRES is not connected directly to DISCH or TRIG? If so, why would this be the case? Note that in the "idle" state TRIG will be close to the supply voltage and THRES will be close to ground. AI: If we look at the TLC555's internal block diagram: We can see that the THRES input goes into a comparator which controls the Reset input of the flip-flop. So depending on how we connect THRES: THRES = VDD: the flip-flop will continuously reset THRES = GND: the flip-flop will never reset THRES = the voltage across the timing capacitor: reset when the capacitor is charged to 2/3 * VDD The most useful scenario is obviously the 3rd and that's also a typical usage case for this chip. Never leave the THRES input floating as that indeed can lead to unexpected results and high quiescent power consumption! This is a CMOS chip and the THRES input is a very high impedance CMOS input so it must be connected to some well defined voltage. In your application circuit, THRES is well defined by your RC circuit + MOSFET so in my opinion there should be no issue at all.
H: What happens if I connect computer to phone with aux connectors and just put music on each? If I connect an aux cable, like that one: https://5.imimg.com/data5/OG/IB/MY-9820141/aux-cord-for-audio-500x500.jpg Between my computer and phone, and start playing music on both of them, what will happen? Will there be current flowing back and forth, from either the computer or the phone? Can it be dangerous? Will the answer change if instead the cable above is connected to a computer on one side, but on the other side is connected to a USB-C to aux adapter, while the adapter is connected by USB-C to the phone? AI: Yes, there will be a flow of current between the two devices and it might or might not harm one or both devices. I would suppose that nothing breaks, but you can't be sure because this is not a specified use case. This does not change with the use of a USB-C to AUX adapter. It still depends on the roughness of both audio outputs. The resulting signal on the wire depends on the output impedance of both sound outputs. Probably one output has higher driving capabilites than the other one and saturates that one. The signal from this stronger output would be the signal remaining on the line, maybe a little bit attenuated. If the output on the computer has a headphone amplifier build in, it is probably going to "win" this fight. If it is the normal audio out jack there is no way to tell which one is stronger. You have to check the datasheets of the specific products. But for that you obviously have to know what audio driver the computer / smartphone / USB-adapter uses.
H: How are sampling frequency of an ADC and switching speed of a multiplexer synchronized? In a typical multiplexed system if we set the sampling frequency twice, does that mean the multiplexer switch loops faster like two times? And what controls the speed of multiplexer? (By speed of the MUX I mean the speed of the pivot like switch shown under the Multiplexer diagram below): AI: That is totally up to you, you have to somehow control and synchronize the tasks of sampling and multiplexing. You could use a µC, that triggers each conversion and switches the MUX to the next position after each finished conversion. OR you could measure multiple data points at one MUX position and only then switch the input of the MUX. It completly depends on your application. Let's assume two use cases: 1) You sample different audio channels, only one at a time: You sample with a typical audio sampling frequency of 44,1 kHz. You want to do this for a few seconds or minutes. After that you switch to the next audio input. If you double the sampling frequency you would probably not change the MUX speed, because these two parameters are independent (sampling frequency for your signal quality, MUX frequency for the time slots each input has). 2) You want to simultaneously capture different channels, e.g. in an oscilloscope: You always take one sample and immediately switch to the next input channel. Doubling the sampling frequency would require you to also double the MUX frequency, because both frequencies are synchronized.
H: Is it possible to combine multiple step up inverters in parallel? So my goal was to start the car off double layer capacitors, but the issue is, as any of the energy is used, the voltage drops according to the quantity of energy used. When only 20-30 percent of the total energy is used, the voltage already drops so low that the ecm\pcm starts turning on and off, turning off the starter relay. I saw "DC-DC Step-up Power Inverter Module 10V-32V to 12V-35V". However it's only for 10 amps, and no one makes 100 amp dc-dc adjustable step up inverters. I was wondering if you could put 10 or more of them in parallel. I was told there are issues balancing the load or something and that's why it can't be done? Can someone explain why this can't be done? AI: No, it is not a good idea to connect DCDC converters in parallel unless they're designed for that. If you used DCDC converters in parallel anyway then there is no way that you can make sure that all parallel converters share the load current equally. The converter which is set to the higest output voltage will take all the load and all the other converters will not do much or anything at all. If: converter A is set to 20.0 V converter B is set to 20.1 V converter C is set to 20.2 V And all their outputs are in parallel then converter C will "win", the combined output voltage will be 20.2 V. Converters A and B will not do anything as their feedback circuit will notice that the output voltage is too high (higher than what they are set to). Only when the voltage drops below 20.1 V or 20.0 V will they start to "work". So when the output is loaded converter C will do its utmost to keep the voltage at 20.2 V. So if the load is drawing more current than converter C can deliver, converter C will be overloaded. What then happens depends on how the converters handle an overload. The converter might "do its best", work at 100%, get hot, it might shut off if it has overtemperature protection. Only if the voltage drops below 20.1 V will converter B start helping. Even when it does, converter C still works at 100% while A does nothing. Even if you say: "But then I'll just set them all to 20.0 V exactly" that will not work because there will always be small differences which will result in the same behavior. Only if there's an additional circuit present which adjusts each converter such that they share the load equally, can this work properly.
H: MOSFET Symbol Confusion Hi i am a student & was hoping someone could please clarify on the below. In a section of learning materials for a module I am taking the symbol for the MOSFET is shown and referenced (FIG 11) with respect to a CMOS NAND gate: All other sources I have come across show the P channel MOSFET with the arrow pointing out on the source terminal & for an N channel MOSFET the arrow pointing into the gate on the source terminal(FIG a). If anyone could please advise if there is issue with the symbol for FIG 11 as these variants contradict one another. I have searched through other questions on a similar nature to this, but my understanding is that the symbols used in FIG 11 should have a T connector gate rather than L type connector gate in order to adhere to common practice? AI: Both kinds of symbols are commonly used. The second set is more detailed, showing the substrate connection explicitly, and the arrowhead indicates the polarity of the channel. Think of it as a diode, where the point of the arrow denotes where the N-type material is. Therefore, the N-channel device has the arrow pointing toward the channel, while the P-channel device has it pointing away. The first set is a simplified version that does away with the explicit substrate connection. Instead, the arrow shows the direction of conventional current flow, similar to how it is used on BJTs. Therefore, the N-channel device shows current flowing out of the source connection (analogous to the emitter on an NPN) and the P-channel device shows it flowing into the source connection. When you're drawing dozens or hundreds of devices for an IC schematic, this shorthand notation saves time and reduces clutter. You can generally assume that the substrates are connected to the most positive (P-channel) and most negative (N-channel) voltages available on the chip.
H: What are the bottom group of diodes for on BLDC motor control circuits? I'm studying the control circuit for a BLDC motor and I can't figure out what function the diodes serve that I point to in the basic diagram. What are they for? At what point in the basic operation of the motor would current need to pass through them and bypass the transistors they are bypassing? AI: Well, you don't seem to have the same problem with the upper diodes. After all, why would they conduct? For the same reason that the upper diodes conduct, the lower diodes are there for the return current path back to the motor and, the usual reason is when the transistors are off and the motor is freewheeling and generating voltage. Both upper and lower diodes protect the transistors from reverse current and dump the energy into the battery and bus capacitor.
H: Reduce Power of High frequency output signal (40khz) I want to try and make the output power of the following driver board adjustable. At full power it runs at 100watt I. The board itself does not have an option to reduce the power output. The output voltage is 220v (I think), output frequency is 40khz (most likely pwm square wave). Here is the driver circuit board I'd like to use: https://www.aliexpress.com/item/33001673042.html?spm=a2g0o.productlist.0.0.3d644912VCTYPe&algo_pvid=1c2f1089-3691-4e06-88a1-95689226a60f&algo_expid=1c2f1089-3691-4e06-88a1-95689226a60f-36&btsid=07fe0fa2-3398-48aa-a224-770f018b1ea3&ws_ab_test=searchweb0_0,searchweb201602_5,searchweb201603_52 Image: I don't think it can be done by placing another pwm signal generator (/"dimmer) on either the input or output side. I'm quite sure it would mess up the output frequency of the driver board. Perhaps I could use a lot of triacs in series to get the desired voltage drop and in this way reduce the power but this is probably a bad way of doing it. Variable resistor is not an option I think due to the high power draw (approx 100w). PS: I'd be using this driver/the high frequency transducer to try and build an ultrasonic cleaner. Any suggestions on how to solve this problem will be greatly appreciated. Thank you very much! AI: On the board, I see a "220V" input connector, rectifiers, and no smoothing caps. Thus I'm going to assume this runs directly from rectified mains. There doesn't seem to be any voltage regulation, and there are only two active devices. Also the board has "110V" and "220V" versions, which means it can't adjust its power output for lower voltage. So... if you want to reduce power, you could try powering it from an auto-transformer (variac) to reduce mains voltage. It probably needs some minimum volage value in order to run, though.
H: Is there any reason nowadays to use a neon indicator lamp instead of an LED? I have a bunch of old neon indicator lamps recovered from old AC devices and used to indicate power status. I wonder: is there any reason nowadays to use the neon lamps instead of LEDs? I see they are still widely available. LEDs are cheaper even after considering the need for a diode in AC applications. They blink half as often in AC applications, but emit much more light per watt. In what cases are neon indicator lamps still preferred? AI: Neon bulbs use microamps of current when fed through a dropping resistor directly from the AC line. LEDs need 10× to 100× the current and can't be fed AC directly.
H: Input impedance of High - Frequency Amplifiers I have a question about the choice of the input impedance of a high frequency amplifier. In general I know from elementary analog electronics courses that it is good for an amplifier (for instance an Op - Amp) or in general for a voltage meter, to have a very high input impedance. In this way, there would be only a negligible voltage drop on the parasitic resistance of the source, and so no signal loss. But this seems to me in contrast with the design of RF amplifiers input impedance. For instance, let's consider this circuit of a logarithmic amplifier which works at frequencies between 1 MHz and 8 GHz: The designer put at the input a parallel resistance (R3) of 51 Ohm in order to realize the impedance matching with the signal generator (which is supposed to have 50 Ohm output impedance) to avoid reflection. But it is completely in contrast with the previous criterion. I have a similar doubt about the output impedance of a device: in radiofrequency circuits I see that it is chosen to be equal to the input impedance of the following stage, while in analog electronics courses I learnt that it is important for it to be equal to 0 (or anyway it must be very low). AI: In the RF domain you already mention that what is important: impedance matching. Fact is that RF signals generally have such a high frequency that the wavelength of the signal can come close to the length of the tracks on a PCB and/or wires between PCBs and connectors. That then means that we cannot use "just a wire" the wire needs to be a transmission line. Note that a transmission line can be made using a Coaxial cable but also can be made by drawing a "controlled impedance" line on a PCB. Look on a PC motherboard PCB, the lines to the memory slots and high speed lines like SATA and USB connections are all controlled impedance lines. For a transmission line to work properly (transport the signal from A to B while not distorting it) the begin and end of the transmission line need to be terminated properly. This means that the input and output impedance of the circuits to which the transmission line connects must match impedance wise. The most commonly used impedance for RF transmission lines is 50 ohms. When a transmission line isn't properly terminated signal reflections will occur and these distort the signal. For low frequency signals these reflections aren't a real issue so we don't need the impedance matching and can choose the impedance that is most convenient.
H: Can I swap TX+ and TX- (and RX+ and RX- ) using ethernet magnetics? I am building ethernet connectors and a switch into a product. There is a requirement to include PoE which I haven't done before. This has required the use of a new magnetics chip to expose the two centre taps. The new magnetics chip has a different pin ordering to the one used previously, so as in the below image, there is a crossover introduced in the routing: I believe that the transformers in the magnetics are symmetric. I'm therefore hoping that I can simply swap the connections to the + / - (p/n) pins of the magnetics: (This would apply to both the TX and the RX pairs) This is what the datasheet for the magnetics (Bel Fuse S558-5500-25-F) shows: The centre tap is - I believe - genuinely in the centre and to my understanding the dots indicate that the coils are the same polarity. Does anyone have any reason not to make the swap I intend to improve my routing? The alternative would be to put the magnetics on the underside of the PCB, but this introduces unwanted layer changes, and potentially an interference issue. That or I find different magnetics. AI: As long as the RJ45 connector line pinout adheres to the standard, you shouldn't have any problems. The magnetics are a passive device, they don't care about RX + or RX-. You can even get away with RX/TX crossing on the connector side, as most modern NICs and switches have auto MDI/MDI-X capability. Some PHYs allow you to set the transmission polarity in their configuration, but I wouldn't rely on that capability.
H: What is the scope of semiconductor device fabrication compared to other fields? I am planning on applying to colleges for pursuing an MS degree. I would like to know the scope of semiconductor device modelling, both in terms of jobs as well as research. I also wish to know about any current trends, popular subfields in semiconductor device modelling. AI: First off, that is a very specialized field with probably not that many jobs globally. It's almost as specialized as, say, writing video chip graphics drivers. However, there are related fields which are very active at present, most notably in 2D physics eg graphene, molybdenum disulfide, topological conductors semiconductors insulators etc with an eye to future electonics devices ranging from transistor related, to sensors.
H: Do I need a protection diode to prevent reverse current flow into a voltage regulator? I have a 78L series voltage regulator that is used when a power supply is connected. When the power supply is absent, battery power is used. The battery will skip over the voltage regulator. The battery positive supplies power to the circuit at the same point as the voltage regulator output. Do I need a reverse protection diode on the voltage regulator output to prevent damage to it when battery power is active and the regulator is not providing the power? simulate this circuit – Schematic created using CircuitLab AI: The LM7805 is basically an NPN Emitter Follower with feedback so removing the input makes the regulator high impedance unless you wish to block the ~4mA bias current . You may verify my assumptions.
H: What are the calculations to do in practice to estimate beforehand the noise seen on the output of this op amp circuit? I would like help with understanding something better, but am not trained in electronics so please bear with me! I am trying to make a simple circuit to take a {-10V ... +10V} signal from a function generator, and to map it into the range {+1V ... +8V}. The circuit only needs to follow input signals up to a bandwidth of around 20 kHz. The arrangement I have so far is the following: The scaling and shifting aspect of the circuit works fine, as can be seen in the oscilloscope screenshot below (left). Now, I would like help understanding more the noise in the circuit. In the oscilloscope screenshot below (right), I have applied a much smaller, 2 mVp-p input signal, and observe the noise introduced on the output signal (with both channels on AC coupling). You can see that my circuit has added significant noise onto the input signal: In the previous images, I was almost at the noise floor limit of what my oscilloscope is able to discern, and so to get a better measure I have also measured the noise by feeding the signals first into the AD8428 instrumentation amplifier, which has gain x2000, via a 260 kHz low pass filter. The noise on the input and output for a 1 V DC input signal are shown below. At the moment, I am not able to provide a frequency spectrum of this noise, so apologies. From these data, I measure the input and output signals to have 53 µVrms and 357 µVrms of noise, respectively: I have measured both the +12V and -12V power supply rails, and they are both much lower noise than that seen on the output, and so are not responsible for it. All these measurements were done with a "pigtail" ground scope probe, to reduce the effect of any pick-up (indeed, the noise goes away when shorting the + and - of the probe together). Ideally, I would like the output noise to be limited by the noise on the input signal, and not add so much noise to it. Therefore I would like to understand exactly what is going on here. Specifically, my questions are: 1) Given the parts I have used, how would one go about calculating what the output noise is expected to be? I would like to learn what are the calculations and procedure I could go through in the future, and hopefully to predict the noise value seen on the output, without having to build it and measure it. I have access to a bunch of specifications in the parts' datasheets, including a voltage noise density of 8 nV/√Hz and current noise density of 0.2 pA/√Hz for the op amp OP1177 (at 1 kHz), and for the LM4040 a value of 180 µVrms from 10 Hz to 10 kHz. I understand the concept of spectral density and how to convert to rms using the desired bandwidth, but I don't understand how I can take these numbers (along with presumably the thermal noise of my resistors), and put them all together to predict the measured value of 357 µVrms. It would be great if someone could walk me through this as an example. It would also be a bonus if someone can illustrate how LTSpice could be used in a case like this to back up any hand calculations. 2) How can I reduce the noise down? Ideally, if I manage to learn more towards answers to the above questions, then I would hope to figure this one out on my own. --- EDIT -------------------------------------------------------------------- Following suggestions in the comments and answers, I have tried adding two additional capacitors, shown below: C7 is to limit the bandwidth of the op amp feedback, and therefore hopefully some of the noise. C6 is is an attempt to low pass filter the noise coming from the LM4040 +10V reference, which has the following noise specs from the datasheet: As pointed out by analogsystemsrf, the LM4040 has quite a lot of noise already. Using the tool https://apps.automeris.io/wpd/ I have extracted the noise spectral density from the picture in the datasheet, and then numerically integrated this spectrum over various bandwidths to get the expected rms noise cumulatively as a function of bandwidth. With a 10 kHz bandwidth, we can expect ~170 µVrms (as stated explicitly in the datasheet), and this increases to 350 µVrms for a 100 kHz bandwidth: With the addition of the two capacitors, the noise at the output is measured for both a shorted input, and with 1 VDC being sent from the function generator: When trying different values of C6 (always with the 100 pF feedback cap), the noise changes as follows: No capacitor: 217 µVrms 1 nF capacitor: 167 µVrms 10 nF capacitor: 123 µVrms 100 nF capacitor: 118 µVrms 1 µF capacitor: 117 µVrms 10 µF capacitor: 116 µVrms --- 2ND EDIT ---------------------------------------------------------------- As suggested by VoltageSpike, I have also done some tests with R2 disconnected and V_IN grounded, in order to remove the extra complication of noise from the LM4040 reference. The effective schematic is then simply the following: Then the output noise is measured using the AD8428 instrumentation amplifier, with two different bandwidths - the first is the standard bandwidth of the AD8428 amplifier of 3.5 MHz, and the second is with an additional 260 kHz low pass filter before the AD8428 amplifier. The following table shows the result of changing the value of C7: Then, after selecting the 56 pF capacitor based on the above data, I have also measured the effect of adding additional filtering capacitors to the power rails of the op amp - specifically, an extra 10 µF and a 100 µF were added to each of the positive and negative rails, changing the noise as follows: It seems now as if the output noise is coming down to the range of the power supply rails noise. Although, I don't understand why there is so much more noise on the output than the PSU rails when measuring over a 3.5 MHz bandwidth, given the fact that the op amp bandwidth should be limited to tens of kilohertz by the 56 pF capacitor C7. --- 3RD EDIT ---------------------------------------------------------------- I have managed to get around to taking a noise spectrum of my simplified op amp circuit shown above. There is no C7 capacitor fitted, and the noise was again measured using the AD8428 amplifier (gain x2000, bandwidth 3.5 MHz). Also, to remove the possibility of my power supply rails dominating the op amp output noise, I have been powering the circuit using dual ±9V batteries. Shown below is the oscilloscope trace, which indicates an RMS output noise of 196 µVrms. I have also then converted the time series data into a voltage spectral density, and the corresponding cumulative RMS noise curve (by integrating the spectral density over the relevant bandwith): From the data, I am able to read off a voltage noise of ~85 nV/√Hz. Following this TI Application Report, and the book Noise Reduction Techniques in Electronic Systems (Ott, H.), I made an attempt to learn how to arrive at this number. First, I associate noise sources with the various elements - namely, thermal noises of each resistor, and the input voltage noise and input current noise of the OP1177 op amp: After doing this, I calculate the following noise contributions: RESISTOR THERMAL NOISE ( using \$\sqrt{4k_BTRB}\$ ): For R1 - noise = 51 nV/√Hz * 1.35 = 68.9 nV/√Hz For R2 - noise = 31 nV/√Hz * 1 = 31 nV/√Hz For R3 - noise = 51 nV/√Hz * 0.35 = 17.9 nV/√Hz The factors of 1.35 and 0.35 are the gains due to the op amp, depending on whether it is applied in inverting or non-inverting configuration for the various noise sources. So, total resistor thermal noise is found by adding the noise sources by the sum of the squares to be 77 nV/√Hz. OP AMP INPUT VOLTAGE NOISE: This is given in the OP1177 datasheet to be 7.9 nV/√Hz (at 1 kHz), and is subject to a gain of x1.35. Therefore its contribution is 10.7 nV/√Hz. OP AMP INPUT CURRENT NOISE: From the datasheet, the input current noise is 0.2 pA/√Hz (at 1 kHz). This will develop into a voltage noise across R1, and then due to the gain will contribute of 0.2 pA/√Hz * 160 kΩ * 1.35 = 43.2 nV/√Hz on the output. Similarly, it will also produce a voltage across R2 and contribute an additional 0.2 pA/√Hz * 56 kΩ = 11.2 nV/√Hz. Adding these in quadrature gives 44.6 nV/√Hz coming from the input current noise. To get the total output voltage noise, we should simply have to add all three noise sources in quadrature, to arrive at: \$\sqrt{(77\;\;\textrm{nV}/\sqrt{\textrm{Hz}})^2 + (10.7\;\;\textrm{nV}/\sqrt{\textrm{Hz}})^2 + (44.6\;\;\textrm{nV}/\sqrt{\textrm{Hz}})^2}\$ \$\approx 90 \;\;\textrm{nV}/\sqrt{\textrm{Hz}}\$ This seems to agree reasonably well with my measurement above of 85 nV/√Hz, and so these calculations seem to work okay. However, I then obtained the SPICE model for the OP117 from the Analog Devices website here, and tried to reproduce this in LTSpice. The result is shown below: It can be seen that LTSpice predicts something like 207 nV/√Hz, which is very different to both the measured value and the value obtained from the simple hand calculations. Can anyone help to shed any light on what might have gone wrong here? Am I misunderstanding how to do the noise calculations, or did I make a mistake in LTSpice? Note that when configuring the OP1177 as a buffer without resistors, to measure its input voltage noise, LTSpice seems to give the correct value given in the datasheet of 7.9 nV/√Hz: --- 4th EDIT ---------------------------------------------------------------- It turns out that the SPICE model from the Analog Devices website for the OP1177 was WRONG. Although the input voltage noise was being modelled correctly at 7.9 nV/√Hz (as shown above), the input current noise was wrong in the SPICE model file. Instead of the value given in the datasheet of 0.2 pA/√Hz, the model was incorrectly producing 0.86 pA/√Hz input current noise. When going through the above "hand calculations" using 0.86 pA/√Hz instead, I arrive at the value simulated by LTSpice of 207 nV/√Hz. I am now happy that the hand calculations, the LTSpice result, and the measured value from lab are all consistent (provided your SPICE model is correct in the first place! Lesson - always compare SPICE model to datasheet values before continuing to model circuits). AI: Given you have "high value" resistors, you are not yet serious about the noise floor. A 1Kohm resistor produces 4.00 nanoVolts RMS noise /rootHertz, that is in 1Hz bandwidth. At 290 degree Kelvin. In 10Hz BW, 4sqrt(10). In 100Hz BW, 4sqrt(100). In 1,000Hz BW, 4nV * sqrt(1,000). Lets examine that 8nanoVolt/rtNz noise density. The equivalent resistor inside that opamp, to produce that 8nV, is 4,000 ohms. Vnoise is sqrt(4 * K * T * Bw * R). If you keep the resistors down to 1Kohm or so, requiring several milliAmps from the opamp, you can easily design a circuit with opamp-noise-density-limited total integrated random noise. With low Rvalue resistors, you can ignore the current-density. 1kohm * 0.2pA = 0.2nanoVolts, very small compared to 8nanoVolts. Thus in a 10,000 Hz bandwidth (including the pi/2 factor for 1-pole rolloff) you will have total input referred noise of 4nV * sqrt(10,000) = 400nV = 0.4 microvolt rms. Since your gain is about ONE, this will also be your output noise. Ignoring power supply trash, ground noise, magnetic field intrusion (20,000 Hz is not shielded or attenuated by standard copper foils), and electric field charge injection. If you use 20,000Hz bandwidth, 1-pole rolloff, you'll have 20,000 * pi/2 or or 31,000Hz equivalent bandwidth, with the noise voltage being integrated out to infinity as your 1-pole does the rolloff. The total integrated noise voltage is sqrt(31,000) * 4nanoVolts. Thus 1704 == 680nV == 0.68 microvolt RMS. ===================================================== After reading the LM4040 datasheet: The noise bandwidth of the LM4040 is about 40KHz. Thus the total integrated noise will be sqrt(40,000/ 10,000) 180uVrms, or 360uVrms. That is divided by R6 and R7. Their own contribution is about 10Kohm equivalent, or 4nV * sqrt(10,000 / 1,000) = 12 nanoVoltsrms/rtHz, with high bandwidth. Assume 1MHz, thus 12nV * sqrt(1,000,000) = 12 uVrms. The opamp buffer is 8nVrms. The voltage divider R1 and R2 is about 40,000 equivalent (those 2 in parallel); assume the same 1MHz bandwidth, so use the total integrated noise of R6/R7 and scale up; thus 12uVrms * sqrt(40,000 / 10,000) = 24 uVrms. The feedback network (gain slightly more than 1) has the same noise contribution, or 24uVrms. So you have a number of contributions. The largest is the reference diode. Lets filter that, with a 160Hz RC lowpass; we need 1milliSecond time constant TAU. The equivalent resistance on pin#3 of left-most opamp is about 10,000 ohms; install a capacitor in parallel, to ground, with R7, to get a 0.001 second (1e-3 second); a 0.1uF (or 1e-7 farad cap) does this. Filtering the Reference should be exciting. Now restrict the output bandwidth to 20KHz, or about 10 microseconds (about 8uS, actually, but lets do easy math). With R4 of 50Kohm, a 1pF cap in parallel causes tau of 50,000 picoSeconds, or 3MHz. Install 100pF and expect about 30,000Hz bandwidth. [wrong: not for non-inverting circuit use, because the Grounded resistor --- R3 --- prevents gain attenuation below Gain=1. So this 100pF is not a wise approach.] That should be exciting. [ wrong. The gain will only drop from 1.3 to 1.0 and then not attenuate any more. Thus is not a useful high-frequency lowpass.] Now use your instrumentation amplifier to examine the (zero output amplitude) of the Function Generator. That should be exciting. You may need to install 100 ohm resistors in each of the 4 VDD paths. And up the bypass caps to 10uF. This ensures higher frequency noise in the power supply regulator servo loop is filtered DOWN in amplitude. Let me know what works. =============================================== The righthand opamp U3 is an awkward circuit to convert to low-pass-filter. A capacitor across the Rfeedback merely ensures the high-frequency gain = 1.000, which lets all the opamp noise and the Vnoise of R3 160K to appear on the output. Assuming no noise entering the Vin-, nor the VDD pins, the opamp Rnoise of 4 Kohm can be added to the 160Kohm, thus predicting 164K ohm. Given 13*13 = 169, we'll scale up 4nV by 13, to 52 nanoVoltrms/rtHz, over 1MHz bandwidth. The total integrated noise should be 52 microVolts rms. [ error Initially said 52 milliVolts]
H: Looking for the part number of the button Installed in the Acer Aspire 2920 notebook. Does not work at all - pushing at any angle has no effect. Second button (left touchpad one) works properly. Circuit diagram lists SW-TACT-119-GP / 62.40009.671. Can not find anything using these numbers other than various Wistron circuit diagrams. Dimensions are (approximately) 6 * 6 * 3 (mm). Update: After taking the closeup pictures I thought that according to the construction the buttons seem to be maintainable. I disassembled all of them - without desoldering the device (only desoldering the top metallic cover's pin), cleaned, assembled back, and now all the buttons function properly. AI: https://www.digikey.com/product-detail/en/te-connectivity-alcoswitch-switches/FSM2JELGEATR/450-2153-2-ND/2400357 My guess is its a TE connectivity part, maybe one like the one shown above.
H: Increase in SMPS output voltage with RF amplifier as a load I am trying to use an SMPS of 50 V output ,16 A current capacity from meanwell make for powering one of the RF amplifier operating at 13.56 MHz. The amplifier is evaluation module of MRF300AN. The issue is that as soon as i increase the drive power to the amplifier, the voltage on the SMPS goes on increasing from 50 V to 100 V and more. ( for eg: When I give around 0 dBm , voltage is ok, but as we go more around 10 dBm,the voltage from the SMPS increases to 82 V and goes on increasing with more drive power) Have tried with a benctop switching power supply from APLAB too, here the issue is different. The output voltage goes down and that too without much current drawn, much lesser than the Cc limit set. I felt that could be an issue with RF superimposing on DC lines and creating some issue in control/sense circuitry in the power supply. But the same issue is not happening with MRF 101 eval board, even if the whole electrical environment is almost same. The power supply works fine in this case. Can anybody give a hint on what could cause such problems with switching power supplies. I would like to understand and resolve the issue. Thanks AI: In my experience, RF generally upsets power supplies (esp. SMPS) by getting on the feedback line. A pi filter very close to the feedback input (either CRC or CLC with a ferrite) will help. Choose values based on your RF frequency.
H: Successive Detection Logarithmic Amplifier let's consider this logarithmic Amplifier: I do not understand why at the terminal LOG OUTPUT there is a current which is proportional to log(Vinput). The current flowing on each diode is equal proportional to exp(-qVouti/KT), where Vouti is the output voltage of each stage. Each stage is a limiting amplifier: it has a transfer function like this one: References: https://www.analog.com/media/en/training-seminars/tutorials/MT-078.pdf AI: The text appears to indicate that current output is desired, so that summing is simpler. I believe based on the text that the diodes are added to indicate a conversion to current output for the summation. Note that it specifically states that "the detectors should be current outputs (not simple diodes)" indicating a linear voltage-to-current conversion. If I'm right, I agree that it could have been explained/drawn better.
H: Does a correctly sized resistor protect low voltage components from a high voltage source? Let's say that I have a 37v DC source that I would like to reduce to 12v so it can run a 12v light bar (a string of 6 leds and I assume a resistor to limit the current). I measure the resistance of the light bar at 35 Ohms, so using Ohm's law I calculate that putting a 70 ohm resistor before the light bar will safely reduce the voltage from 37v to 12v and run through the light bar at the expected 351 mA. Will this really protect the components of the light bar considering the fact that the inital voltage is 37v until the current starts flowing. If you measure the voltage of the 70 ohm resistor before the current starts flowing: it reads 37v. It's only after the current starts flowing: that the voltage is reduced to 12v. Is it possible for the 37v to damage a component that's not rated or such a high voltage? Initially I tried applying 29v directly to it (no initial resistor) and it instantly smoked and died without heating up first despite being supposedly rated for 12-30v so I'm wondering if some arcing will occur internally with 37v and a resistor. Diagram / Simulation AI: You can use a resistor to limit current, this is probably the worst way to do that. Why? Because the current will be consumed as power, in this case it will be roughly 9W that's a lot of power, and a large resistor will be needed. It's not the voltage that damages resistors it's power. (unless arcing occurs, you don't usually worry about arcing until after 60V) The other problem is the voltage will vary if the current varies, this could have consequences for your circuit. Use a linear regulator instead, or a few of them or a different power supply.
H: Specifying BOM substitutions / alternatives with Contract Manufacturer (CM) I fear this question may be opinion based but I think it has some value to the general community - because this falls into the end of the design phase. When working with a CM, they may have better pricing due their volume and as a design method, should you allow the CM to make changes to the BOM (provided you specify which components may be substituted) or is it industry practice to allow specify the components and alternatives and that's it ? AI: This is exactly why a BOM doesn't normally specify a manufacturer and part number directly. Instead, the BOM references in-house part numbers, and each in-house part number has an AVL (approved vendors list) associated with it. This level of indirection allows you to add (or remove, if necessary) manufacturers and their specific part numbers to the in-house number without having to update every BOM that uses that part. And it allows your purchasing department (or that of a CM) to pick the vendor that they prefer for whatever reason from that list. You asked about a sample of AVL data. This is a function that can be provided by any good MIS (Manufacturing Information System) or ERP (Enterprise Resource Planning) software. I'm a one-man consulting shop, so I don't use a commercial system; instead, I came up with my own tools that I use to support clients. They're based on a simple database. Here's a snippet of a dump of that database showing some relevant records: A: Enpoint 6001-0221 - "2x10 2mm female IDC" C: Enpoint 6001-0221 FCI 89947-720LF # (keyed, in tube) C: FCI 89947-720LF Digi-Key 609-2740 C: Enpoint 6001-0221 Sullins SFH21-PPPN-D10-ID-BK-M181 # (no key, bulk) C: Sullins SFH21-PPPN-D10-ID-BK-M181 Digi-Key S9078 An "A" record simply describes a part. The fields are: Manufacturer Part number Revision Description In this case, the "manufacturer" is a code for my client, and the part number is my internal house part number. A "C" record maps one part number to another. The fields are: Manufacturer Part number Manufacturer Part number (The # and anything after it are just comments.) In this case, there are two different mappings for "Enpoint 6001-0221" — one to "FCI 89947-720LF" and one to "Sullins SFH21-PPPN-D10-ID-BK-M181". Either of these parts would be acceptable wherever I use "6001-0221" in a design. As it happens, both of these are available from Digi-Key, so there's an additional record for each of those parts that maps it to the corresponding Digi-Key part number. This allows me to easily generate a Digi-Key order when I need to restock. The database has additional record types. "B" records describe the BOM itself, which is usually imported from schematic capture, and "G" records capture price data, including quantity price breaks. This allows me to then generate a "costed BOM" that looks like this: Hmm. I now see that there are errors in this BOM. But that's OK, since this is a prototype assembly that was long ago replaced by a custom flat-flex cable.
H: Logic level converter for NodeMCU (ESP8266): Input 24V/16V (Hi/Lo), 500 Baud I want to use a digital input pin of a NodeMCU board (ESP8266) to read a digital signal. The signal line idles at 24V DC. The logic levels are 24V and 16V. The signal speed is 500 Baud (each signal sample is approx. 2 ms long). How do I convert the signal for the NodeMCU board? EDIT: Unfortunately I do not have an oscilloscope. What I already did is: I connected the bus lines to the microphone port of an USB sound card using a voltage divider with 1MOhm and 1kOhm and used the software Soundcard Scope. Does this tell you something about how the bus works? 24V high, 16V low. No 24V supply available near the NodeMCU board. Not sure about the maximum transmitter load. It is the 2-wire communication bus of a door intercom system (TCS, https://www.tcsag.de/). BTW, in TCS:BUS documentation I found the hint that bus messages are either 16 or 32 bit long. EDIT: Soundcard Scope screenshot with Windows Automatic Gain Control (AGC) turned off for the microphone input: EDIT: This diagram is the result of capturing bus voltages with analogRead(): Any idea how this protocol could be working? AI: The simplest thing to do from a hardware perspective would be to use a pair of resistors to scale the voltage to a range acceptable to an analog input on the NodeMCU and do the rest in software. If you want to do more in hardware, add a voltage comparator that compares the scaled voltage to an appropriate threshold and then feed the output of the comparator to a digital input on the NodeMCU. For example, if you scale the 24V input down to 3.3V, the lower level will be at 2.2V. A threshold voltage of 2.75V would be appropriate. The following circuit made only with discrete transistors might do an adequate job. The input divider scales the 16V/24V input to 2.2V/3.3V. The B-E junction of the PNP creates a threshold at about 3.3V - 0.65V = 2.65V. When the input is at 16V (actually, anything less than about 19V), both transistors are switched on, and the digital output is pulled to ground. simulate this circuit – Schematic created using CircuitLab When the input is 16V, this is equivalent to connecting the base of Q1 to 2.2V through a 3700Ω resistor (Thévenin equivalent source). This puts about 0.45 volts across R5, allowing about 100 µA of current to flow out Q1's collector. Most of this current flows through Q2's base, driving it into saturation and sinking about 3 mA through R4. R3 prevents leakage current through Q1 from turning on Q2. It sinks about 30 µA @ 0.65 V, so anything less than that keeps Q2 cut off, while anything more than that switches it on.
H: Inductors short at DC or does it have a voltage drop? In previous courses, I remember we were told that capacitors act as an open circuit at DC and inductors act as a short circuit. I came across this video: https://www.youtube.com/watch?v=WR6qVvnDnI4 and in this, it has a DC source. Now with my previous understanding, does this mean that all the voltage is actually dropped by the non-ideal series resistance of the inductor? I'm just trying to make connections between different courses I took/am taking. AI: Yes, the ideal inductor has zero DC resistance. To model a real world inductor, we often add a series resistance, which may sustain a DC voltage drop. There is no way to measure this voltage drop independent of the inductor, however.
H: L-Pad Impedance Matching Equation I've been looking at impedance matching a circuit, but I'm struggling to find an equation for calculating the values of the resistors in the output network. Given this circuit: How are the values 475R and 56.2R calculated? AI: Say $$R1 = 475, R2= 56.2, Rload=50, Rsource=500$$ You simply want from the source side: $$ R1 + (R2Rload)/(R2+Rload) = Rsource $$ So lets try that: $$475 + (5056.5)/(50+56.5) = 501.5$$ So this shows that it works. But as you can see there are 2 unknowns, ie $$R1$$ and $$R2$$. So you need atleast two equations. The one I did above was looking in from the source side. You can form a similar equation from the load side and solve simultaneously: $$R2\|\|(R1+Rsource) = Rload $$
H: A/D conversion improvement through Arduino I have a certain analog signal v(t) which varies from 0 to 2V, which I want to be read by Arduino. I know that Arduino can read it through the function AnalogRead, and the result will be a sequence of numbers from 0 to 1023. Now, I have some doubts: The input range 0 - 5V is mapped to 0 - 1023. Therefore, if I get the result X and I want to find the original input voltage V, I have to apply the formula: V = X * 5 V /1023. Correct? The output range is 0 - 1023: this means that Arduino uses 10 bit for the A/D conversion. If I am correct, this means that the Arduino resolution is equal to 5V/1024 = 4.88 mV. But my signal varies from 0 to 2V, so there is a waste of bits. I think the conversion might be better. For instance, if all 10 bits were used for the range 0 - 2V, we would get a resolution of 2V/1024 = 2mV. Any solution? Moreover, what does it happen if I decide to amplify my voltage with a gain = 2.5? Is there a benefit? AI: As Tom Carpenter has already pointed out, you must divide by 2^N = 1024. You are correct with your second assumption. You always want to fit the ADC full scale voltage (the maximum voltage it can measure) with your maximum input amplitude. Typically there are two ways to do that: You can use an input amplifier to amplify/attenuate your signal to exactly match the FS voltage. You can set the reference voltage of the ADC to the desired value. While the controller used on the Arduino Uno (Atmega) offers in general the option to connect an analog reference voltage differing from general Vcc, this does not work for you, because the analog reference input is hardwired on the Arduino to 5V. So you are stuck with a reference voltage of 5V, which means your FS (full scale voltage) will always be 5V on the Arduino. What you CAN do, is to use an operational amplifier to increase your signal's amplitude by factor of 2.5 from 2V to 5V. That way, you get the full resolution of the 10 bit ADC.
H: Crystal Oscillators in MCU let's consider a MCU (for instance ATMEGA328) with a crystal. I know that the electrical model of a crystal is this one: My question is: which is the circuit that makes it oscillate? I do not see it because it is connected to two pins of the MCU. What is there between them? Power supply, a logic gate etc AI: Indeed as stated in the comments, a Pierce oscillator is most commonly used for a simple crystal oscillator circuit used in for example a MicroController. Here's a typical example of such a circuit: Source: this presentation. The top part (the NMOS, PMOS and both resistors) are on the IC. The crystal and both loading capacitors are on the PCB. What isn't shown is where the actual clock signal output is. I would simply use the output of the inverter, the node between Rf and R1. I would connect that point to an inverter so it is not loaded much. That extra inverter would then be suitable to use as a clock in the rest of the chip (on a real chip a clock distribution circuit would be used). Since I don't have schematics of the on-chip circuit of the ATMega328, there's no guarantee that the actual circuit on that IC is like this. However, since this circuit is quite commonly used since it is well known, chances are that it is exactly like this.
H: How to identify 422 or 485 bus from the PCB I have a very old CPU card, maybe 1980's. It has following chips on it and most probably these are used for communication with the rest of the system. SN55188 Quad Line Drivers SNJ55189 Quad Line Receivers I cannot power-up the board. But I need to figure out the communication bus type used in it. Looking at the above IC's can I safely say that: It's not using TTL signals on bus. It's not differential 485 bus. It's using differential 422 bus. AI: I need to figure out the communication bus type used in it. As commented, those ICs are only used for RS-232 (they cannot be used for RS-422 or RS-485). Your CPU card might have other interfaces too, of course, but RS-232 is the answer about what interface type those ICs are used for. Here is an example - an old IBM PC-compatible serial card, showing these ICs next to the RS-232 interface connector on the right-side of the board: RS-232 quad line driver (marked MC1488, equivalent to the TI SN55188) RS-232 quad line receiver (marked MC1489, equivalent to the TI SN55189) This specific board has two quad line receiver ICs (i.e. each containing 4 individual line receivers) so it has more than 4 incoming signals wired to the connector. If the "Ring Indicator" (RI) signal is supported, there are 5 typical input signals on an RS-232 interface. There are also empty sockets for an additional line driver & line receiver IC, if the second 8250 UART IC (U2) is populated, to provide a second RS-232 port via the pin header marked J2. (Image source - Wikipedia, photographer)
H: What does a comparator consume compared to an ADC Is there a way to calculate the power consumption of a comparator for one single measurement? I would like to compare the power consumption of a comparator with the power consumption of an ADC. I expect the comparator to be able to measure faster and consume less by doing so. However, I looked into multiple datasheets and could not find any data about power consumption. Why is that? How can I calculate it? // EDIT: In order to prevent myself of asking an A-B question here, I want to state my intent with this question: I want to show, that comparators are faster and less power consuming than ADCs while beeing cheaper overall. This is not about special chips but more a general thing I want to know. Therefore I just googled for datasheets instead of looking for specific ones because I am new to this area. Comparator Datasheets I found or were linked in the comments are: http://www.ti.com/lit/ds/symlink/tlv3501.pdf https://www.st.com/resource/en/datasheet/ts881.pdf AI: Tongue in cheek answer: An ADC has to include at least one comparator, or many comparators in the case of a Flash ADC. Here's a SAR ADC: Since the ADC has more circuitry than just a comparator, it will use more power! (all other things being equal, that is, if you could somehow buy the exact same comparator used in the ADC, which will never happen in practice...) Now, the power used by comparators and ADCs depends on many factors so it's impossible to answer the question. One very important factor is speed: faster comparators use more power, because the input stage is essentially an analog amplifier, and high-bandwidth low-noise analog amplifiers require more current. So you will find slow micropower comparators using fractions of a µA, and superfast ones using several mA or even tens of mA. ADC power use also depends on speed, bits, etc.
H: Sanity check: Routing high current traces (MOSFET relay circuit for 300W heater)? This is the first time I've ever designed a power PCB/ a PCB that needed to take a high current, I'm looking to check that I'm doing this right and for any advice on how to improve? details below. I'm using an arduino to control a 300W film heater in a PID loop kind of thing, and using a MOSFET to switch the high voltage which the arduino can't supply. Given that it's a 24V supply and the heater is 300W, this trace needs to support 12.5 amps of current. If I have a PCB with 1oz/ft^2 copper thickness, this means a pretty manageable 5mm ish trace width - I narrowed the trace going into the MOSFET terminals because otherwise it wouldn't fit - is this going to be a problem? Image below: Edit: The MOSFET I'm using is the IRLB8743PbF, and this is the circuit schematic: AI: If you can i'd move the input connector to next to the output one, since the input_1 trace can go directly between the two. That'll shorten the trace lengths between the connectors and to and from the MOSFET. I'd also copy the traces to the front and back of the PCB to maximise the copper carrying current and look at necking down the traces a little less (depending on what the board house can manage). If you're copying the traces to the front and back of the PCB then you don't really have to take any chances with minimising clearance. One final tip for this kind of situation is staggering the drain and source pins so they can be necked down less but this is trade off between between the gain and current loop area by having to stand the MOSFET further away form the PCB to do it.
H: Why are VHDL "external names" that are used to create alias to signal at another level of hierarchy, not synthesizeable? I am using Quartus 18.0 and have set the settings for VHDL-2008. However, when I try to compile a trivial project where one "external name" signal exists, I get this error: Error (10500): VHDL syntax error at LED.vhd(16) near text "<"; expecting an identifier, or a string literal This proves that "external name" which is declared using << and >> symbols, cannot be used in synthesizable code. I have confirmed that this fails in Microsemi Libero and also in Intel Quartus Prime Standard. My question is why? AI: Because hierarchical names do not use ports. You can refer to a signal in a different level/module, bypassing all I/O ports. To physical get to the signal the synthesis tool would have to auto generate additional I/O ports. It might be possible to implement this but I suspect that would open a whole can of worms. I maybe very old fashioned because I would not like a design to start routing signals between modules and hierarchies without me having very tight control over them.
H: What informations can we obtain with these voltage and current measurements of a little electronic device? I powered a little electronic device with 2 AA batteries and here are the results measured with a multimeter: When using a first set of 2 AA batteries: Voltage when device unplugged: 2.45 V Voltage when device plugged / ON: 2.10 V, consumption: 0.30 A When using a second set of 2 brand new AA batteries: Voltage when device unplugged: 3.10 V Voltage when device plugged / ON: 3.00 V, consumption: 0.20 A Just being curious: what informations can I deduce about the device or about the batteries with these measurements? AI: 2.1V * 0.3A = 0.63W 3.1V * 0.2A = 0.62W The device seems to use constant power no matter what the input voltage is, which most likely indicates it is internally powered by a switching DC-DC converter. It could also be a flashlight with a switching LED driver.
H: Part number suffix meaning (,135 ,115) When making a BOM I used a component which goes by part number BC847BW,135. It is available on Mouser and Digikey. An "alternative", is listed on Farnell: BC847BW,115 The datasheet doesn't seem to mention what ",135" or ",115" means. I've seen this suffix on other Nexperia parts but it never made a difference to me until today, when it caused me some inconveniences with an assembly house. So I'm curious as to what those numbers mean, and if the parts are different at all, or if its a packaging issue (reel size), etc. p.s.: the issue I had with the assembly house is unrelated to the question, I had to suggest the ,115 part as an alternative to the ,135 part because on their database BC847BW,135 is listed as SOT23, so I just had to suggest a different part number with SOT323 footprint - the W suffix clearly indicates SOT323 on the datasheet but anyway) update to the p.s.: they corrected their model on their database and will proceed with the ,135 part. AI: Those numbers are related to ordering and packaging, see https://www.nexperia.com/products/bipolar-transistors/general-purpose-bipolar-transistors/transistors-single-npn/BC847BW.html and scroll to the ordering section. The 115 is a 7" reel of 3k pieces, 135 is an 11 1/4" reel with 10k pieces.
H: Driving 5V mosfet with 5V tolerant pins on 3.3V dsPIC33F I need to drive a MOSFET (IRFZ44N) with a microcontroller (dsPIC33FJ64MC202). The problem is, the PIC runs at 3.3V and the FET's Vgs(th) lies between 2V and 4V, so there will be times my PIC won't turn it on. But, the PIC has some 5V tolerant pins. How can I use them? The datasheet says: Up to 5.5V output with open drain configuration on 5V tolerant pins with external pull-up. and 11.2 Open-Drain Configuration In addition to the PORT, LAT and TRIS registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired 5V tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. It seems so obvious but I still don't get it... How do I wire this circuit? What code do I need to make this work? Note: I can't change either of those components. That's what I've got to work with. AI: simulate this circuit – Schematic created using CircuitLab R1 is a pull up resistor which you provide. M1 is the transistor within the PIC and the drain is internally not connected (thus open drain). You need to choose R1 and the size will depend on how fast you need to switch your device on and off. A higher value resistor will lead to slower transition times (in particular output rise time). There will be a time constant formed by the resistor and the gate capacitance of your MOSFET. I suggest simulating as the choice of resistor is highly implementation dependent. A typical good start for R1 in general purpose switching control is 10k. To drive the pin high, set the pin to be an open drain output (as indicated in the text you have - the specifics will be in the reference manual) and write a '1' to that register bit. What voltages are permitted at the pin will be in the device data sheet; you could simply bring up the 5V behind the 3.3V. A 5V tolerant pin will be 5V tolerant for input or output. Most microcontrollers have the pins set to inputs at reset.
H: How to calculate primary, secondary, and auxiliary inductance of this transfromer? I am wondering how to calculate/find out the inductance values for primary, secondary, and auxiliary windings of a Würth Electronik 750310742 transformer. The main reason is so that I can attempt to model the transformer in LTspice. AI: The primary has an inductance of 38 uH and couples to the secondaries with a turns ratio of 2:1 and 2:1.1. The 2:1 coupling means that the secondary inductance is \$(1:2)^2\$ x 38 uH = 9.5 uH. The other secondary has a turns ratio slightly less (2:1.1) and therefore has an inductance of 11.5 uH. You use the square of the turns ratio to gather inductance values for unspecified windings. The leakage inductance for each secondary is specified as 0.47 uH.
H: Where Does VDD+0.3V Input Limit Come From on IC chips? There are a variety of integrated circuits that specify that their input voltage can span a fairly wide (absolute maximum) range, e.g. -0.3V to 6.0V (ref, pdf page 4), and then have a "Input Voltage at any pin" constrain that depends on the input voltage, e.g. -0.3V to VDD + 0.3V. That, in effect, makes the chip not be I/O tolerant to voltages that exceed the input voltage by more than 0.3V but are within the absolute maximum specs of what the input voltage allow, and forces me to apply some kind of external level shifting circuit to those inputs. So what is the practical reason for this kind of limitation in the specifications for integrated circuit I/O pins? AI: Most likely there is an ESD protection diode connected between the input pin and the VDD net on the chip, in such a way that it is normally reverse biased (A schematic showing the configuration is given in Peter Smith's answer). The idea is that when there is a positive ESD event, current will flow into the lower-impedance VDD net where it will do less damage than if it's all dumped on the one poor CMOS gate that's attached to the input pin. Because the limit is VDD + 0.3 V it's likely in your device the diode is a Schottky type instead of a PN junction. With a PN junction, you'll usually see a limit of VDD + 0.6 V or so. If you were to apply an input voltage above VDD (by more than 0.3 or 0.4 V) to this device, you'd forward bias this diode, and draw a high current from your source. This might damage your source or, if the source can supply enough current, heat up the chip to the point of damage. If you use a resistor to limit the current into the input pin under these conditions, you might find the circuit works fine. Or, particularly if the chip is a very low power one, you might find the whole chip (and maybe other things connected to the same VDD) are powered up through the input pin, which often leads to unintended behavior.
H: What is meaning of active low input in combinational logic circuits? I am currently doing self study on combinational logic circuits. I encountered few terms like active low output, active low input. I understood what active low output means (putting not gates at output side). I guess active low means putting not gate at input side. It will be very helpful if some one can explain this using an example (note that I have knowledge of encoders, decoders, Multiplexers so you can use these in your example). AI: It means the signal is inverted (like a NOT gate). Let's take this 555 timer below as an example Picture can be found here... Not my picture (and excuse the massive compression for this picture, hence the ugly pixels) Say that a signal that goes to this pin is a 1 or HIGH. Since Pin 4 is active low, it will end up being a 0 or LOW for this pin. The opposite is true: If the signal leading up to the pin is 0 or LOW, then Pin 4 will be 1 or HIGH. The purpose for a signal to be active low is to have some type of external logic device to turn off the signal. CPLDs are a good example of external logic that would shut off a device by sending a signal to an active low pin. You might thinking, "Why don't we just simply make it active high instead?" That's a valid question and I'm not really sure to be honest but if I had to guess, it could be to just simply save power.
H: MCU conneected to AC Mains I am developing a PCB which is having control MCU circuit, it will control the relays. Relays output are connected to 230V AC mains load (~100W load). This PCB is mounted on a cabin where people cant access, and the risk of electrical shock is nill. So is it a good idea to connect the mcu with non isolated power supply(capacitor based) which will reduce the overall cost? 1) Compare to the isolated version this topology having any prons & cons? 2) I am scaring about the high common mode voltage which demands more clearance and creepage in PCB? 3) What about surge/spike compatibility. I need to add any protective devices additionally AI: In short. An AC supply either needs to be double insulated, or have a transformer. Both need to be fused. Transformers isolate the supply from the grid. It would be difficult and costly to roll your own power supply. PCB mounted power supplies are available that convert AC to DC, they have been tested and conform to IEC and UL standards. The other option is to build your own which would probably need to be tested to conform to those standards (even if you aren't selling a product for safety's sake). I am scaring about the high common mode voltage which demands more clearance and creepage in PCB? If you are using a PCB mounted power supply (or run any AC mains on a PCB), the AC and DC sections need to be separated and the AC mains side will need proper creepage and clearance between traces. The AC side will also need creepage and clearance from the DC side of the supply (or any other traces). This prevents arcing. Source: http://www.ni.com/white-paper/2871/en/ Compare to the isolated version this topology having any prons & cons? I would say you need an isolating transformer minimum, I am not sure how you would design otherwise. What about surge/spike compatibility. I need to add any protective devices additionally Most of these are built into off the shelf power supplies, a line filter may be needed. You will need to fuse the device.
H: Can a bulged capacitor prevent a CPU from booting? I am trying to revive my old CPU. But it won't turn on. The fans don't turn ON, but they are working. PSU is also working. I have changed my CMOS battery. I found that one of the capacitors has bulged slightly. I want to know if this bulged capacitor is causing my CPU to not boot? The capacitor between DIMM2 and IDE2 has bulged. AI: I found that one of the capacitors has bulged slightly. I want to know if this bulged capacitor is causing my CPU to not boot? It sure can, even if the cap still retains its capacitance, the ESR is most likely too high. This will cause more ripple than normal and could interfere with digital signaling (the power supply needs to be clean). Pull the cap off the board. Check the cap with an ESR meter (should be under 1Ω or even lower) and replace. I would replace if it was bulging, make sure it has a higher voltage level than listed on the cap, and the same or more capacitance. This may or may not fix the problem. Check the power with a Digital Multi Meter and check the AC ripple in mV it should be lower than 25mV and hopefully in the 10-5mV range.
H: Circuit Diagrams - 2 Input/Output Current Source I have encountered a situation where I need to draw 1 controlled current source on a circuit diagram with 2 inputs and 2 outputs but I'm not sure what is the proper way to convey this idea. I can't seem to find anything online either. Here is what I came up with (doesn't seem proper to me): How can I draw a current source with two outputs? AI: There are two different kinds of controlled current sources, they are typically drawn as shown below: Source: https://www.electronics-tutorials.ws/dccircuits/current-source.html Usually a diamond indicates a controlled/dependent source, a circle indicates a independent source. If you want to draw two outputs, here are the options for drawing. A branched node shares the current with two nodes. Two separate sources keep the current the same (and can share the same input current node for dependence) simulate this circuit – Schematic created using CircuitLab
H: Passive switch that detects when a door is opened Background In my school, we are assigned lockers and I am trying my best to make mine as impressive as possible, at this point I've build a custom shelf for it and put up some LEDs. The problem is that I manually have to reach for the on/off-switch for the lights, and let us be honest, that is not really something you should have to do in 2019. Hence, I'm trying to figure out how to make the lights go on when I open the locker. Current progress Firstly I though about automating the process using an Arduino and motion sensor/distance sensor to see whether the door was open, but since the whole apparatus would have to be turned on 24/7, even the 50mW that I calculated that it would require was to much for two AA batteries in series. Then a friend suggested that I put in a button that would be pressed when the door was closed, opening the circuit with the LEDs, and closing the circuit when the door was opened. This would be very battery effective, but it is hard to place a button correctly, and it would propably come off if I accidentally closed the door with to much force. Today, I thought about using a LED as a "solarpanel", detecting that it was dark when the door was shut, and detecting increased luminosity when the door was opened, activating a transistor and closing the circuit. Problem is that a) I tried to build a prototype, but I didn't succed in powering the transistor using two different power sources, and b) the corridor that my locker is in is quite dark anyways, and would probably not be able to power the transistor. Question Is there some way I can detect if a door is opened or closed without using any power? I'd be grateful for all suggestions AI: Then a friend suggested that I put in a button that would be pressed when the door was closed, opening the circuit with the LEDs, and closing the circuit when the door was opened. This would be very battery effective, but it is hard to place a button correctly, and it would propably come off if I accidentally closed the door with to much force. I think you really should use a normally closed push button as your friend suggest and tackle the drawbacks mechanically: Use e.g. a guided rod in combination with a spring to press the button. The spring can solve the mounting misalignment issue to some extend as well as the slam-the-door issue. EDIT: Of course those have been invented already: search internet on "spring rod limit switch". Source (for as long as it exists there): www.alibaba.com Another option is using a roller lever switch like shown below: Source: Technical Guide of Basic Switches by Omron
H: I cannot find resistor in the market I'm trying to replicate this design and I cannot find the 6K/1% resistor in any online store (Digikey, Mouser). What can I do? the design I'm trying to replicate is this As per @Huisman request, all the resistors on the board are SMD, it also seems to be a 1005 package AI: You can use a resistor combination calculator to find possible combinations of E96 values. 6K is not an E96 value so it will not be that easy to find. The percentage indicates the nominal error. You can use 5900 1% in series with 100 ohms 5%, but generally both should be 1%. If you use a parallel combination, for one or two, you can stack the resistors manually. 5900 + 100 = 6000 (0 %) 4870 + 1130 = 6000 (0 %) 4530 + 1470 = 6000 (0 %) 4420 + 1580 = 6000 (0 %) 4220 + 1780 = 6000 (0 %) 3740 + 2260 = 6000 (0 %) 3570 + 2430 = 6000 (0 %) 10000 \|\| 15000 = 6000 (0 %) 10500 \|\| 14000 = 6000 (0 %)
H: What sensitivity of reed switch should I use? For my GCSE Engineering project, I am building a device which attaches to the frame of a bike, and uses a magnet (Attached to the wheel) to detect 1 turn of the wheel (I have also compensated for contact bounce etc.) The only problem I face is that I have never used reed switches before, and I don't know what sensitivity of reed switch to use. Assuming the bike wheel is 2150mm circumference, the max speed is 13 m/s, the magnet diameter is 50mm and it will be 180mm from the centre of the wheel, I calculated that (hopefully) the smallest amount of time the switch will be directly passing the magnet is 0.0037 seconds. I thought this seemed like a very small amount of time for a switch to close and open again before 1 rotation is over. A 1AT switch apparently closes at the north pole from the earth itself, so just to be safe i want to avoid disaster from it being too sensitive. Does anyone know what type/sensitivity of reed switch to use? AI: Somewhere around 25 AT will be more than enough to prevent accidental triggering from the earth's field, although you could go higher depending on your magnet and the proximity to the switch. The trick is to get the alignment right. You want to align the magnet and reed switch so that the reed switch is magnetized along its length. See https://standexelectronics.com/wp-content/uploads/Reed-Switch-And-Magnet-Interaction.pdf . If your magnet is 180 mm from the center (360 mm diameter), the magnet will pass in .0073 seconds, and a reed switch should be fine. They have operation times on the order of .0005 seconds. Good luck!
H: Diamond: Warning: logical net has no load I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesis) with the code as follows: module arrtest(clk, led); input clk; output reg led = 0; reg [3:0] arr_index = 0; reg [7:0] intervals [0:9] = {8'd125, 8'd128, 8'd200, 8'd210, 8'd192, 8'd192, 8'd185, 8'd100, 8'd255, 8'd80}; reg [7:0] countdown = 0; reg initialized = 0; always @(posedge clk) begin countdown <= countdown - 8'd1; if(countdown == 0) begin countdown <= intervals[arr_index]; arr_index <= (arr_index < 3'd10) ? arr_index + 4'd1 : 4'd0; led <= !led; end end endmodule And I've receiving the following warnings at the Translate Design stage: Running DRC... WARNING - logical net 'countdown_cry_0_S0[0]' has no load. WARNING - logical net 'countdown_s_0_S1[7]' has no load. WARNING - logical net 'countdown_s_0_COUT[7]' has no load. WARNING - DRC complete with 3 warnings. So I'm suspecting that something's wrong in the design and a part of the design doesn't get synthesized. On the other hand on the Map Trace stage it gives me the following: Top 10 highest fanout non-clock nets: Net arr_index[0]: 12 loads Net arr_index[1]: 12 loads Net arr_index[2]: 12 loads Net arr_index[3]: 8 loads Net countdown6_i: 8 loads Net countdown: 4 loads Net countdown[4]: 3 loads Net countdown[5]: 3 loads Net countdown6_3: 2 loads Net countdown6_4: 2 loads And I'm reading it as "the countdown net IS loaded". Why am I getting these "has no load" warnings and do they mean that a part of the design doesn't get synthesized? AI: This is a pet peeve of mine with synthesis tools in general — they tend to spew out a lot of irrelevant warning messages that make it very difficult to find the real errors in a design. In this case, it seems that the tool has recognized that your countdown variable is a counter, and used a general-purpose counter macro to implement it. However, this general-purpose macro has outputs that you don't need — and have no reason to know about in the first place. But the DRC cheerfully puts out warnings related to those outputs that mean nothing in the context of your actual design. Short answer: These particular warnings are safe to ignore, but you can't generalize from that.
H: How critical is the magnetics circuit diagram in a magjack RJ45? I'm looking at an example circuit diagram from ST, and it use sa 48F-01GYDXNL part that I can't find anywhere. It's a gigabit ethernet jack with magnetics, and the datasheet shows a circuit looking like: Link to the datasheet. I'd like to use a different part, but what I want to know is do I have to have the exact same circuit inside the magnetics ? Is any old RJ45 magjack going to work ? Or is it somewhere between the two ? The one I'd like to use is (datasheet here) which appears sufficiently different to cause me to worry they're not functionally the same. AI: You can use the 08621JX143-F just make sure the pins with TRD go toward the phy. The 08621JX143-F has one less center tap pin and some LED's. The frequency response might be a little different, but the overall functionality should comply with IEEE ethernet standards.

Subsets and Splits

No community queries yet

The top public SQL queries from the community will appear here once available.