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H: Can a vertical multiwatt package be bent to lie horizontal after it is installed?
I am working on a project with a multiwatt package audio amplifier IC.
Can this component be bent over to lie horizontal, flush with the PCB, after it is soldered into place?
AI: I’m going to assume you have a very tight space requirement that’s leading you to consider this, and somehow you’ve got a plan for the heatsink for this lay-flat orientation.
As for your question, it’s a bad idea. The lead frame or the encapsulation is likely to crack if you bend it over flat. This is due to the bend stress being concentrated at the lead-package interface.
Instead, consider a small PCB interposer to adapt the power package to horizontal.
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H: DHT22 issues at 3.3V - What else could I try?
I'm attempting to use an DHT22 at 3.3V for a very low power application - remote sensor unit with a very long battery life. Currently it's on a naked breadboard with a 328p.
At 5V in a spare arduino uno the DHT22 works fine. At 3.3V... it doesn't. Things I've tried:
Shorter cables (down to ~1 inch or less)
Multiple cables (drive the
overall resistance down further)
Longer waits (because I was being
hopeful)
More capacitors (because maybe the voltage is sagging on power up?)
Removing other, high power components that might somehow be interacting with it (xbee)
Varied pull up resistor values (3.3k, 5k-ish, 10k)
None of that has worked. I've ruled out wiring mistakes, faulty component, bad code.
What else can I try to resolve this? I've had a bad night, I'm not thinking clearly and all I can think of is throwing it all in the bin or buying a 3.6V regulator, in the hope that it's high enough to appease the DHT22 and not fry the xbee (limit 3.6V).
I'm also confused because on one hand, the datasheet says 3.3V is fine. On the other - the internet says that sometimes 3.3V isn't enough. Sometimes?!
Please give me more options.
DHT22 datasheet https://cdn-shop.adafruit.com/datasheets/Digital+humidity+and+temperature+sensor+AM2302.pdf
AI: Some sources that sell DHT22 mention in specifications that minimum supply voltage is 3.5V.
Depending on what voltages you have available in your system, you can easily level-shift the bidirectional data wire between a 3.3V MCU and e.g. 5V DHT22.
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H: Power converter: Why we always focus on loop gain involving control to output transfer function?
While measuring loop gain using AP300 frequency analyzer, why we always focus on loop gain involving control to output transfer function?
Is it because input to output transfer depends on power stage and not important for controller design?
(If there is a variation in input, it will result in variation at output and eventually variation in control parameter)
AI: A switching regulator can be described by the below block diagram. The input of this control system is the reference voltage, in the left side, while the output is \$V_{out}\$. The input voltage \$V_{in}\$ and the output current \$I_{out}\$ are perturbations the converter must fight. There is the audio-susceptibility (the ability to reject the perturbation coming from \$V_{in}\$) and the current absorbed by the load which reduces the output voltage because of the open-loop output impedance:
In a switching regulator, the reference voltage is fixed and sets the dc operating point. In small-signal analysis, because its level does not change while you ac-modulate the system, it does not play a role and it is 0 V in ac. You are left with a control system that we call a regulator: what the system does is deliver a constant output voltage (or current sometimes) permanently fighting the perturbations: if \$V_{in}\$ changes, you want \$V_{out}\$ to remain constant and if the load draws more current, you also want \$V_{out}\$ to remain unaffected.
For implementing this strategy, the system needs gain: no gain, no feedback. When I say "no gain" it means that the system, beyond crossover, runs ac open-loop: if you have a 10-kHz perturbation on the input voltage while crossover is 1 kHz, the system will do what it can to fight it but it virtually runs open-loop in ac.
The above expression describes how the output voltage is determined based on the perturbations inputs. You can see that the key to the rejection is the open-loop gain \$T\$. This gain involves the control variable, the duty ratio \$D\$ and that is the one the loop will act upon when correcting perturbations. The relationship linking a stimulus applied on the control input \$D\$ with the response observed on \$V_{out}\$ is the control-to-output transfer function you need to determine (bench measurement, simulation or analytical analysis) before thinking of a compensation strategy (poles and zeroes in the compensator). It is the one determining the way the control system will react to a change in the perturbation. Measuring the transfer function between \$V_{out}\$ and \$V_{in}\$ would certainly tell you how efficiently the system rejects incoming perturbation but it won't directly tell you about stability.
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H: How does the power transistor with antiparallel diode behave?
Let's say I have a transistor with an antiparallel diode in a circuit with inductance. Now suppose that the antiparallel diode conducts an intertial current of the inductance \$i_L\$.
During this time period a control signal to the transitor is send e.g. from the MCU. I would say that the transistor won't turn on due to the fact that it is reverse biased via the voltage drop across the antiparallel diode. Is my idea correct? Thanks in advance for clarification.
AI: Using the direction of \$i_L\$ as shown in your diagram then, the upper transistor's emitter will be raised approximately 0.7 volts above the positive rail.
Then, for the upper transistor conduct (in reverse mode), the base needs to be several hundred millivolts above the positive rail and, the roles of collector and emitter are swapped.
The transistor will of course be conducting some of \$i_L\$ towards the positive rail but, once that current has depleted, it will conduct in the normal direction.
If the drive voltage to the base of the upper transistor cannot rise above the positive rail then the diode in parallel with the upper transistor will continue to conduct \$i_L\$ until it is depleted.
It's a different story for the lower transistor of course.
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H: Opto / MOSFET switching question
UPDATE: To reflect evildemonic's comment.
ORIGINAL QUESTION:
I have this circuit.
The goal is to be able to put different high voltage rails into the circuit with this 3 pin screw down connector. For example I am going to put 12 V in on pin 1 on HV1. I am then going to be able to switch this load for this lamp using the opto-isolator and the MOSFET.
I think that pin 1 and 2 have to be connected together. If the MOSFET starts conducting there is not voltage on the load line to pull current through to the source. Is this right?
Thanks for any feedback.
AI: Keep everything how you have it, except disconnect Pin 3 from ground and instead attach it to the 12 V instead. You want the load to ground through the N-MOSFET.
How you have it now, when the MOSFET is conducting, both sides of the load are grounded.
If you connect pins 1 and 2 together, when you activate the MOSFET it will short the 12 V to ground. Don't do that.
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H: Laplace inverse transform of an exponential multiplying another function
I was trying to understand the inverse transform of \$Y(s)=F(s)e^{-as}\$, but on different sources I found three different answers (H being the step): \$f(t-a)\$, \$H(t)f(t-a)\$ and \$H(t-a)f(t-a)\$.
The first and the second I guess could be the same, given usually the analysis starts at t = 0, but which inverse transform is the right one?
AI: The Laplace Transform on the interval \$0<t<\infty\$ is common used in electronics.
Certainly causal signals \$u(t)=0; t<t_0\$.
We all get lazy when writing equations because often the context is understood.
For example: if the Laplace transform of \$f(t)=t\$, then all the values for t<0 get ignored. What we take the transform of is \$f(t)H(t)\$ where \$H(t)\$ is the unit step function (also called the switching function).
So then the inverse Laplace transform \$L^{-1}[G(s)] = g(t)H(t)\$. The multiplication by H(t) is often not written but understood to be there.
When a causal function is shifted to the right by \$t_0\$, the values of the function from 0 to \$t_0\$ is zero. So in this case the "switching" happens at \$t_0\$ instead of 0, so \$H(t-t_0)\$ is more descriptive but \$H(t)\$ will give the same result.$$L^-{1}[F(s)e^{-t_0 s}]=f(t-t_0)H(t-t_0)\tag{equ 1}$$is the correct and most descriptive form. However the other forms are correct if it is "understood that they mean equ 1
Solutions for the Laplace transform are valid for \$t \ge 0\$.
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H: How to calculate the voltage on this photodiode cathode?
Given these values, what steps to take to calculate the voltage present on the diode cathode?
V_bias = 100V
R_s = 700k
C_d = 1 uF
Diode dark current = 10 nA
Diode capacitance = 50 pF
AI: By "voltage" do you mean the operating point? Without knowing the time function of optical power absorbed by the diode and the diode's efficiency, DC is all we got.
So, since this looks like a DC analysis under dark conditions, the capacitors disappear, the op-amp disappears because it's not even connected to the diode now, and the diode is replaced by the dark current source.
So the problem is more or less trivial: there's a voltage source, an equivalent series resistor, and a current source. That's all. The diode drops some voltage by flowing 10nA of dark current across the 710kΩ of series resistance, and that adds up (with proper sign) with the bias voltage. Done.
Diode capacitance = 50 pF
One only hopes that's the capacitance at 100V of bias applied to the diode, but it doesn't matter in the problem anyway.
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H: AND gate output stuck at low
I am using a SN74HCS09 Schmitt-Trigger AND gate that has the output pins stuck at low. Despite trying different combinations of high and low channel inputs, the outputs remain stuck at 0V.
I am supplying 3.3V for VCC and have a capacitor at the supply. I have tried 10k pull-down resistors on the input signals and output signals without any success. Even connecting 3.3V directly to both inputs still leaves the output of the AND gate stuck at 0V. Should I be using 5V instead of 3.3V for the supply and signals? The datasheet says that 3.3V should be fine but there doesn't seem to be anything else that could be going wrong (https://www.ti.com/product/SN74HCS09)
Any help would be greatly appreciated.
AI: These gates have open-drain outputs, meaning that they will only either actively drive the output low, or let it float. Add a pullup resistor that pulls the output up to your supply voltage. Both 3.3 V and 5 V are within the allowable supply voltage range listed on the product brief.
While this seems annoying/tedious, open-drain outputs are actually useful in some scenarios - for example, you can easily AND the output of multiple of these chips together with a single pullup resistor and shared output line; if any of the outputs are 0 they will drive the shared output low, and if all outputs are floating the line will be pulled high.
Some chips with open-drain outputs also have modified output networks that allow you to use a higher voltage on the output as compared to input/supply - however that's not safe to do with this chip because of the clamping diodes on its output (which are used to protect against electrostatic damage to the chip)
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H: Help with voltage regulator
I’m very confused on how a voltage regulator is used. On this one that I found: Fasizi 3.3 DC Voltage Regulator 4.75V-12V to 3.3V 800mA, I have no clue where which cables should go where. If I use a USB cable, where do the data+ and data- wires go? There are only 3 pins on it. Or do I only connect the power and ground to the regulator?
Is it also possible to use this one: LM317T, without a PCB or whatever they’re called and just connect the cables?
AI: The voltage regulator regulates the supply voltage. As long as the webcam still uses the standard 3.3V USB signalling, the data wires connect directly, bypassing the voltage regulator.
The three pins on your first regulator are VIN, OUT, and GND; assuming this manufacturer has named these pins in the typical way, they would be wired as follows:
The ground of the USB supply, webcam, and regulator GND are all connected together
VIN connects to the +5V from the USB supply
OUT connects to the +3.3V line on the load.
However, there are some fishy specs with this regulator. It doesn't seem to have a consistent current rating, among other things. Prefer a trustworthy device or module with a clear datasheet if possible.
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H: Fundamental Question - how does magnetic permeability work for weak signals?
This is basically a physics question. If a sophisticated answer is needed, please go for it.
The standard explanation of magnetic permeability is something like this:
In a ferromagnetic material, there are many small regions of the material called domains, and each domain has its own magnetic field. When an external magnetic field is applied to the material, the magnetic moments of the domains tend to align in the direction of the applied field. However, in the absence of an external magnetic field, the magnetic moments of the domains tend to be randomly oriented, resulting in a net magnetic moment of zero.
So in other words, the domains are flipping to align with the external field, thus reinforcing it. Presumably, this has some quantum-mechanical-like behavior, because flipping each group of atoms will have a threshold energy. So they should flip in little groups of varying size and not in an orderly atom-by-atom manner (presumably).
This noisy domain flipping process is called the Barkhausen Effect.
So I have some questions:
I have used some very aggressive LC filters before, with moderately strong signals (perhaps up to 25% of the inductor saturation point). Why have I never seen a measurable increase in noise due to Barkhausen Effect?
For very weak signals, does the inductance of an inductor drop to a lower value since I'm not supplying a strong enough external field to flip the domains? If so, then is this a source of harmonic distortion in LC filters for example?
If the answer to #2 is NO - i.e. there is no lower limit that results in the collapse of permeability, then here's my followup question:
What is the physical mechanism that allows inductors to operate in a very stable and linear manner when the applied signal is very weak and far below the coercivity?
Thanks for your thoughts!
AI: The key here is to understand that domains do not flip. Domains shrink or grow as individual atoms at the edges of the domain flip.
The very wikipedia page you linked has a gif showing how the Barkhausen effect is not caused by domains flipping, but by domain walls getting "snagged" on crystal defects.
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H: What schematic symbol is used for a flex cable?
Generally asking, but primarily for KiCad, what is the schematic symbol typically used for FPC/FFC/flex cables?
That is to say, the flat end which is sometimes stiffened and does not have a connector like in the following image:
In KiCad, would the above cable be represented by Connector_Generic > Conn_01x14?
Or is this something that a Bus in KiCad can be used for? I doubt this because this appears to only be a way to make connections within a project, while in the use-case I'm asking about there is no further connection after this FFC (in the context of the project).
AI: That is essentially the same as an edge connector on a normal PC board, so I'd use a generic connector as the schematic symbol.
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H: Understanding voltage in simple electromagnet and DC motors
I made a simple electromagnet with enameled copper wire wrapped many times around a metal allen wrench. I attached the electromagnet to my PSU and it works great, but I do not understand the voltage output.
I understand that the magnetic flux is proportional to the ampere turns; more turns more current, more magnetism. The voltage does not go above 1.5 V regardless of the PSU setting (30 V/5 A) and draws the maximum current at 5 A; so I get roughly 7.5 W.
This amount of copper will roughly be the same for a single phase slot of a reluctance motor (high/low sides) design; about 6-8 feet of 20 AWG wire. I will be using a circuit to drive the motor with max 24 V and 5 A.
How can I increase the voltage across the inductor to achieve higher current? Thinner gauge wire and a significant amount of more turns for more resistance?
I am comparing this electromagnet to what will be the inductor in the stator (laminated) and it is not the ideal power. I thought the voltage would be that of the PSU setting for the electromagnet, then translate that to the stator slot to determine performance. Ideally a single phase can achieve 24 V 2-3 A.
Thank you.
AI: How can I increase the voltage across the inductor to achieve higher current? Thinner gauge wire and a significant amount of more turns for more resistance?
Yes, that's one way.
Not accounting for poor connections, your existing coil has a resistance of
$$ R = \frac{V}{I} = \frac{1.5V}{5A} = 0.3\Omega $$
In practice it will be less than this, because I imagine there's also some resistance in the interconnections and wiring between coil and supply.
If you wish to use this power supply, limited to 30V & 5A, you require a resistance which will pass exactly 5A when 30V is across it:
$$ R = \frac{30V}{5A} = 6\Omega $$
That's a factor of 20 times larger than the existing resistance, so you'll either need 20 times longer wire, or the same length of wire with \$\frac{1}{20}\$ of the cross sectional area.
Your PSU will output no more than 5A, and if the load tries to draw more than that, the PSU will simply drop its output voltage to whatever voltage is necessary across the load, to draw 5A.
As for the motor, if it has similar coil resistance, then initially it will cause the same 28.5V drop in PSU output, for the same reasons.
If that voltage/current is enough to cause the motor to start turning, then slowly it will accelerate, leaving the stall condition, requiring less and less current to run.
As it turns faster, the load it presents to the PSU falls. PSU output voltage can rise, and eventually motor current will reach a minimum (presumably less than 5A, with the motor unloaded), and then the PSU is able to output its "set" voltage.
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H: Regulator voltage drop upon connecting a relay
I have used an LM7805 as a voltage regulator from approx 36 V to 5 V. The regulator initially outputs 5 V perfectly but as I add up a single relay the voltage drops. And upon adding 2-3 relays in parallel the voltage further drops. Although for other types of load, the regulator works perfectly fine.
What is the reason behind this?
AI: Let's say your relay coil requires 5V at 100mA.
All three relays will draw 300mA in total from the 7805 output.
There is a potential difference across the 7805 (from input to output) of \$36V - 5V = 31V\$. There is 300mA flowing between those potentials, for a total power of \$P = I \times V = 300mA \times 31V = 9.3W\$, all dissipated within the 7805 regulator.
Unless you have some serious heatsink on the poor thing, and a fan, that 7805 is going to roast itself to oblivion if it doesn't protect itself first. My guess is that it is going into thermal shutdown, which it does by cutting off the current path from input to output. That results in the output voltage dropping to well under the 5V you expect.
This happens in spite of the datasheet's claim that the regulator can provide 1A or 1.5A. It can do that, but only while it isn't shutting itself down from excessive heating.
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H: How can I do immediate addition in the Atmel AVR instruction set?
I've been doing some AVR assembly programming for a university course, and I recently happened upon a situation where I would have wanted an "add immediate" instruction. However, no such instruction seems to exist within the Atmel AVR instruction set. I find this weird given that there are immediate variants of various other instructions, such as subtract, logical AND, compare, and even "add immediate to word" (ADIW), among others. What can I use in place of add immediate to perform immediate addition when doing AVR assembly programming?
AI: There is a subi instruction - "subtract immediate". You can easily do addition using this instruction, so one can speculate there isnt a need for a dedicated add immediate instruction.
For example, to add 2:
subi r16, 254
Alternatively, you can also express it like this using a negative number:
subi r16, -2
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H: Why does this datasheet report negative values for the gate threshold voltage?
I am a bit surprised to find negative values for the gate threshold voltage in the datasheet of an n-channel MOSFET, reference BSS159N from Infineon.
Since it is an n-channel, I would expect positive values instead. What am I missing?
AI: It's a depletion-mode FET, which means it's "on" at Vgs=0, and you can turn it off by driving Vgs negative (below the threshold voltage). However, it does conduct more when Vgs becomes positive.
Pay attention to datasheet figure 7 (which shows turnoff below -2.x Vgs) and figures 5 and 6 (which show the neat "constant current" characteristic over a range of Vgs values).
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H: Measuring resistance in corrosion removal electrolysis
I tried to measure the resistance of my electrolysis setup (rusty object on cathode, clean iron anode, electrolyte = 3l H2O + 1tb spoon baking soda). But the resistance fluctuated from 50 to 70 kΩ even when everything was still. During the reading it would usually climb up. Sometimes I even got a negative reading (when I added more baking soda). Could something about the way the multimeter measures resistance cause this? How can I measure the actual resistance and in what range should I expect it to be?
I want to know because I have a 12 V, max 12 A power supply + (16 A current limiting socket) and I worry that it is just too much power for some of the cables.
Note: The power supply is a 350 W ATX power supply with a selection of voltages from 3.3 V to 12 V.
AI: The electrolyte cathode and anode form an electrolytic cell. The voltages produced will influence the ohmmeter. The meter injects a current then measuring a voltage that calculates the resistance.
To measure the resistance, measure the voltage and current while operating. Apply Ohm’s Law.
The resistance is dependent on the evolution of the gases produced.
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H: Transimpedance Amplifier Not Outputting Voltage
I'm trying to build a transimpedance amplifier to convert the current from my photodiode to a voltage that can be read using an ESP32. The components I am using are:
OPA170AIDRLT Operational Amplifier (link)
QSB34CGR Onsemi Photodiode (link)
97.6kΩ Resistor
0.15uF Capacitor
I designed my circuit based on the Texas Instruments guide (link), and my circuit looks like the following schematic:
Like the title says, I am not measuring a voltage output from my circuit. More specifically, I am measuring 0V. I have checked the resistance over the photodiode to see whether it is in working order, and it is. Unfortunately, my circuit is soldered onto a PCB, so measuring the current output from the photodiode will not be very easy and I am leaving it as a last resort. Am I missing something obvious? What tests can I perform to find out what is wrong with my circuit? My lack of experience with this type of circuit is currently my downfall, so I would greatly appreciate any help or advice!
AI: Am I missing something obvious?
Yes, your photodiode is connected the wrong way round.
When light hits it, photocurrent will flow from 0 volts to the inverting input of the op-amp and, to maintain a virtual ground, the op-amp output would need to drop to a negative value on its output but, it can't do that because you have a single supply configuration.
Here's how it's normally done with a single rail op-amp and ground referenced photodiode: -
Image from Photodiode Amplifier Design using Photodiode Wizard - CN-0312 Spectroscopy Example supplied by Analog Devices (a very useful web page).
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H: Capacitor bursting
I attached a 0.1 uF capacitor at the input of a 5 V voltage regulator. It was rated 50 V and my input was 37 V.
After some time the capacitor burned out. I tried the same with another capacitor but it did the same. What could be the reason and how to solve it?
AI: You got fake capacitors most likely. The 50V rating on them is imaginary. Unfortunately, that's all too common. I got a whole "noname" capacitor kit, nicely packaged, that was supposed to be 50V rated. The capacitors look like they have a 16V rating and start failing a bit above 20V :( It's still useful, just not at 50V.
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H: Benefits of a differential PA in an RF power combiner design
Looking at the schematic for the Shure PA770 Antenna Combiner (found in their FCC listing) we can see the design is fairly straightforward, some amplification before combining via a typical Wilkinson divider.
What isn't immediately obvious to me is why the designer chose to use baluns/transformers to first convert the single-ended input to differential, amplify both signals independently, before converting the differential signal back to a single-ended output:
As can be seen in some internal photos on an FCC listing of their more modern combiners, these transformers aren't small (nor inexpensive), not to mention the duplication of the RF transistor and biasing circuitry:
What are the benefits to this design vs a more typical single-ended power amplifier architecture?
AI: One reason is that balanced amplifiers tend to suppress even harmonics, and reducing the 2nd harmonic means you don't need as much filtering.
In a broad band amplifier (an octave or more), filtering out the 2nd harmonics might be difficult since the second harmonic of the lowest frequency can fall within the upper end of the bandwidth you're trying to amplify, so having it suppressed by means of a balanced amplifier could be a big advantage.
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H: What does the root locus tell us exactly?
More specifically what information can one extract from a root locus drawing without calculating the transfer function and then using Routh Hurwitz or other techniques? Essentially, what information does the Root Locus alone give us?
AI: The Root Locus shows you how the zeros and the poles of your system change when you change a parameter. This is very useful to study and modify the behavior of your system by adjusting that parameter.
For example, converting a high order system to a lower order one by changing its gain.
Root locus, can help us in the design by selecting the operation point (that yield the required characteristics) on the root locus. If there will be more than two poles in the system, the dominant poles will be of interest.
In this example, you can see how for different values of gain K you can choose the behavior of the system from unstable to stable, looking only to the position of the poles in te RL. "Reference"
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H: Transistor Leg Orientation Question
I've ordered a PCB to be manufactured, I now need to solder some resistors and transistor to the board.
The transistor is a 2N3904 and it's place on the board is Q1. As can be seen the pins are aligned in triangular arrangement with the middle leg offset. Is this a special type of transistor because all of the components for this part which I have found online appear to have the legs in a straight line. Or is it simply a case of bending the legs to make them fit.
Apologies if this is a dumb newbie question :)
AI: The only dumb question is the unasked one
You just bend the pins to make them fit ;)
It's actually possible to get the transistors with the legs pre-bent, but if you're only making one or two boards, of course there's no point to bother with that.
It's actually going to be much easier to solder the pins with them spread out like this. While having a footprint with them 'straight', they end up very very close together and can be tricky for a rookie solderer to do w/o bridging solder between pins.
The "ideal" method of bending would be to grasp all 3 pins with tweezers at the point they enter the plastic body, and hold tight, then use your fingers to bend them to fit. The reason you would want to do this, if you don't hold the pin-to-plastic junction still, you can crack the plastic. Unlikely but does happen. Same goes for the resistors on your board too. Let the metal pin take all the bending stress, not the component body.
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H: Bias for single supply OA
simulate this circuit – Schematic created using CircuitLab
I am supplying an audio circuit with only a positive voltage of 12V. I have created a mid point (aka virtual ground, aka bias...) of VCC/2 like this in order to feed multiple OA.
Now howewer I am facing confusion on how to modify the filter schematic to accomodate the single supply.
How do I do it properly?
After the buffer my signal is already centered at 6v, do I have to reference the second order filter to the VCC/2 point somehow?
I am confused
AI: I would take C3 to the virtual ground to improve PSRR, but the unity gain Sallen and Key filter will work as is.
Note: I am not at all sure about the stability of the 5532/081 combo in the Baxandall volume control, a small cap across R5 will help here.
You probably want a cap and bleeder resistor at R3 wiper to prevent the wiper on the pot carrying the 5532 bias current (Or use a jfet opamp instead).
Note that the 07x series opamps all have a lovely trap if you exceed the common mode range in that they can undergo 'phase reversal' where the inverting and non inverting inputs flip, the resulting clipping is NASTY.
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H: 10-contact FPC socket has 12 PCB terminals
I have to place an FPC socket on my PCB. I selected 0.5 pitch and 10 contacts connector. Everyone has 12 PCB terminals instead of 10.
I am confused, what are those two extra pins for?
AI: To hold the connector in place. They are "anchors", though various companies call them with different names.
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H: Voltage regulator drop in voltage on load
1)I have been working on voltage regulators but they are not working correctly. I am using the LM7805 as the voltage regulator with 36V as input and 5V as output...It gave the 5V correctly without the load but as I added a 33ohm resistor the voltage dropped to zero...After that, I used an LM7812, and its output was given to a 5V regulator. The results were the same I am getting a drop...
2)Secondly I used a 10K resistors which gave the correct output but as I attached the 33ohm resistor the voltage dropped. Now even after removing the 33-ohm resistor, I could see the dropped voltage. I have to restart the circuit in order to get my output with 10k...what is the reason behind it as I am not able to understand.
AI: I am using the LM7805 as the voltage regulator with 36V as input and
5V as output...It gave the 5V correctly without the load but as I
added a 33ohm resistor the voltage dropped to zero
An LM7805 produces a 5 volt output and, when connected to a 33 Ω load will supply 151 mA. If the input supply is 36 volts, the 7805 has to drop 31 volts from input to output. That means the power dissipated by the 7805 is 31 volts × 151 mA = 4.7 watts and, due to that heat being produced, the 7805 will immediately shut-down because the internal temperature of the die has become dangerously close to frying the chip.
It's a protection measure employed by the chip. You are also exceeding the maximum voltage of the input by 1 volt. You need to downgrade your expectations of such a device: -
After that, I used an LM7812, and its output was given to a 5V
regulator
It's going to be a similar story; this time the 7812 will shut-down on a power waste of nearly 3.6 watts. Maybe this time you fit a heatsink to the 7812 and just about get away with it but, you are still over-volting the input and, that's bad design.
You should be considering a much more efficient and cooler-running buck regulator.
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H: LTspice 1000A simulation
I want to simulate a 1000A current flowing through a circuit in LTspice. The supply voltage is 230V AC @ 50Hz. This circuit will also have 0.05 milliohm in series with the load (this resistor acts as a shunt resistor.) The voltage drop across the resistor should be 50mV.
How do I go about simulating this in LTspice?
simulate this circuit – Schematic created using CircuitLab
AI: I believe this is what you want to do:
A couple notes here. First, you have to define your source in "peak" value and not RMS. For a sine wave, you just multiply the desired RMS value by 1.414 to get the peak value.
Second, the load here is just a basic current source that is the same frequency and is in phase with the voltage source. You also have to do the same thing with the RMS value as you do with the voltage source.
Third, your measured values are so small compared to your excitation values that you might want to force a smaller maxiumum timestep in the .tran command like I've done here:
Lastly, one way to get the RMS values back is to plot the waveform for an exact number of cycles and CTRL+leftclick the colored name of the trace. That's how I got those little boxes with Average and RMS values to pop up. You can't get two boxes up at the same time. I used some MSPaint magic for that.
|
H: Flyback Converter - Secondary Feedback
I am learning how to design a flyback converter power supply. I am using a reference design from TI PMP11047.
Detail schematic can be found here: https://www.ti.com/tool/PMP11047#description
I have a question on the feedback circuit. I understand that when the voltage increases above 24V, the reference voltage at TL431 is 2.5V, making it conduct and turn on the LED inside the opto-isolator. What is the purpose of D10, R28, D11, and C15?
AI: Looks like during startup D10 and C15 provide an initial path for LED current during the time when there's not yet enough voltage to activate the TL431. That probably prevents an odd spike in the output voltage, providing a smooth linear startup waveform.
C15 eventually charges up above the TL431 cathode, reverse biasing D10 so it no longer affects the circuit.
D11 and R28 discharge C15 on shutdown so that on the next startup the circuit operates as intended.
|
H: Should the sense pins be left floating on a DC-DC converter?
From this datasheet:
https://www.murata.com/products/productdata/8807040057374/uhe12-30w.pdf?1617679818000
"Note: The Sense and VOUT lines are internally connected through 10Ω resistors.
Nevertheless, if the sense function is not used for remote regulation the user
should connect the +Sense to +VOUT and –Sense to –VOUT at the DC/DC converter
pins."
Yet in the section about using the trim pin it says
"A resistor connected from the Trim (pin 9) to the –Output (pin 7),
or –Sense where applicable, will increase the output voltage for all models with the exception of the 1.2V models, which will decrease the output voltage in this configuration"
That "or" throws me off a little. Figure 8 shows a dotted line from -sense to -output. I've looked at some other datasheets and application notes for similar DC-DC converters and they all seem to say that the + and - outputs should be tied to their + and - sense pins.
One of the reasons I ask is that i've seen some applications of this converter where the sense pins are left floating. The converter seems to work but i'm curious what the drawbacks are (if any).
Edit: I'm gonna add this here from page 4 as an extra nail in the coffin.
Also, based on the ordering guide, there may be no sense pins at all! This explains the applications i've seen where they are not connected to the outputs.
AI: Yes, while they certainly can be left floating if unused, they really should not be floating when unused, as it will be better to not float them.
The drawback is that when left unconnected, it can work in some application and cause problems in some applications.
The second part of your question about TRIM pin is basically the same thing, do what is best. If you don't use sense wires, you should have output and sense connected together at the regulator, and so the regulator can sense only the voltage at regulator, and then the TRIM just trims the voltage at the regulator output. But if you do use the sense pins, you are measuring and regulating the voltage at load, not at the regulator, and so the TRIM input will affect the sensed voltage at load, not at the regulator output.
|
H: Altium: Fill, Solid Region, Rectangle and Polygon Pour
Altium designer provides capability to place these objects:
I have used Polygon pour a lot and it is used to create power and ground planes. The question is about the other options. These can also be used to create a region of copper but the design rules of planes do not apply to them e.g they do not repour and do not follow the clearance rules when they are created.
I can see that Fill and Solid Region, both can be used to create a region of copper. I can see what it does, but not why it would be needed. It is not clear why/when someone would need to use these and what design rules apply to them.
Besides this we have rectangle, is this to merely draw something (overlay layer or otherwise) and thus has no other function? It seems to be this way.
AI: A Rectangle is a non-filled set of connected tracks or lines limited to a rectangle shape (with corner options) which can be drawn on any layer.
A Fill or Solid Region is a solid region similar to a polygon pour except it does not have options for fill style (like hatched), pour sequence, or connection style to vias and pads. These are useful when designing footprints, PCB antennas, and other features for which design rules that would remove any portion of them are not desired. A fill is limited to a rectangular shape while a region is a polygon (but not a polygon pour).
A Polygon Pour is also a solid region that can have an arbitrary number of vertices, but is subject to design rules that remove copper in service of changing how it is filled, how it connects to vias and pads, and how it might have portions removed depending on polygon pour sequence (defined in the Polygon Manager).
Effectively, a rectangle is just a shorthand method for drawing four connected tracks or lines, which may be most useful on a silkscreen layer, but I use them also on assembly notes and drill guide layers to compartmentalize off-board information.
A fill or solid region is most useful when drawing some feature that needs to be exempt from any sort of design rule or automated process. I find this most useful with specific footprint pads, PCB antennas, and sometimes for silkscreen fills where I want a box for placing labels or writing something.
|
H: **FINAL UPDATE** I'm getting closer to a workable circuit for this device?
FINAL UPDATE
I think the power supply is squared away accept for some caps and resistors. Thank you for sticking with me. One question:
There are two thermistors (one for each battery pack) that are used to determine charge state via battery temperature. They can be found on the Charge Controller and Battery Packs schematic at location C5-C6. Problem is the datasheet example only uses a single battery stack and I have two. The way I wired it I'm sure will not work. What can be done to adapt this part of the sub-circuit to work with two thermistors?
UPDATED AGAIN
If only I had delayed that last update 10 min. Kuba solved my missing piece of the puzzle. I'm in the process of adding a 3.3V Micropower Regulator in place of the two linear regulators. I will update the schematics tomorrow.
UPDATED
After a few minutes of soul searching, a few hours of research and a few nudges from Justme and BeB00. I have changed the batteries to Low Self Discharge NiMH in order to keep the benefits of NiMH with greatly reduced self discharge. I have also dumped the linear regulators, but that leaves me with a hole in the circuit. What is the best way to get from 5V to 3.3V?
Introduction
I am a self-taught novice electrical engineer and a, wear all the hats, kind of entrepreneur. The device in question is a minimum viable product that is heading towards a Kickstarter campaign.
As a novice I have a limited understanding of EE and therefore my device. The design of the device has been through several revisions, right here in this forum. This is the first one that I think might work.
Theory of Operation
The device is a soil moisture sensing and analysis device that uses capacitance sensing technology to help manage soil moisture in your garden. One probe set at the bottom of the device and a second probe set just under the soil line, allow the device to measure soil moisture across the full vertical profile of the soil. Analysis of the data determines if the soil is over-saturated, optimally-saturated, wilting, or dry.
Green, yellow and red, instantly recognized symbols for good, bad and in-between serve as the interface of the device. These colors are used to indicate four discrete levels of soil moisture, and a low battery warning. The device is powered by six 1.2 V, 2300 mAh Low Self Discharge NiMH batteries for a maximum voltage of 8.4 V, which will power the device for the entire growing season.
System Overview
This block diagram presents the devices electric circuit broken out into six sub-circuits. Schematics for the sub-circuits follow the system specifications.
System Characteristics
Click on a device name below to get its datasheet. The purpose of this table is to confirm that all of the voltages, currents and impedances are properly matched and that there is enough current to go around. I scraped the datasheets pretty good but with my lack of experience, I'm sure I missed things.
#
Description
Input Voltage
Output Voltage
Input Current
Output Current
Min|Nom|Max
Unit
Min|Nom|Max
Unit
Min|Nom|Max
Unit
Min|Nom|Max
Unit
1
Charge Controller
4.5 | - | 16.5
V
- | - | -
-
- | 1.3 | 1.6
mA
- | - | -
-
2
2200mAh Battery
- | - | -
-
1 | 1.2 | 1.4
V
- | 210 | -
mA
- | 2100 | -
mAh
3
Power Receiver
4.0 | - | 10.0
V
- | - | -
-
- | - | 1
mA
- | - | 1
A
4
Receiver Coil
- | - | -
-
- | 5 | -
V
- | - | -
-
100 | - | 400
mA
5
5V Regulator
5.6 | 10.0 | 40
V
4.8 | 5 | 5.2
V
- | - | -
-
- | 50 | -
mA
6
Microcontroller
1.8 | - | 5.5
V
- | - | -
-
-40 | - | 40
mA
- | 50 | -
mA
7
Tri-Color LED
5.4 | - | 6.6
V
- | - | -
-
- | 20 | -
mA
- | - | -
-
8
3.3V Regulator
2.7 | - | 7.0
V
- | 3.3 | -
V
- | - | -
-
- | 10 | -
mA
9
C/D Converter
3.0 | 3.3 | 3.6
V
- | - | -
-
- | 750 | 950
µA
- | - | -
-
Wireless Power Receiver and Coil
The Texas Instruments bq51221, Dual Mode 5-W (WPC and PMA) Single Chip Wireless Power Receiver is a fully contained wireless power receiver capable of operating in both the WPC and PMA protocols. The bq51221 device provides a single device power conversion (rectification and regulation) as well as the digital control and communication for both standards. It also has autonomous detection of protocol and requires no additional active devices. The bq51221 device enables a complete wireless power transfer system for a wireless power supply solution.
Charge Controller and Battery Packs
The DS2715 from Maxim Integrated has been optimized for safe and reliable charging of 1 to 10 NiMH cells in series. It pre-conditions severely depleted cells before entering full charge mode. It terminates full charge using the dT/dt technique, which requires an external sensing thermistor. Over-temperature, under-temperature, and over-voltage detection prevents charging under unsafe conditions.
Power Distribution
Microcontroller
The Atmega4809 Microchip is an 8-bit AVR processor developed by Atmel that can run up to 20MHz. It comes with 6KB of SRAM, 48KB of flash, and 256 bytes of EEPROM. The chip features the latest technologies like flexible and efficient-power architecture, including Event System and Sleepwalking, precious analog features, and advanced peripherals.
Tri-Color LED
The four levels of moisture (over saturated, optimally saturated, wilting and dry) plus a low battery warning are communicated to the user through a single tri-color (green, yellow and red) LED. PWM, managed by the microprocessor, is used to control the LED’s color and the speed of fades.
Capacitance to Digital Converter and Sensors
Capacitive sensing is a technology, based on capacitive coupling, that can detect and measure anything that is conductive or has a dielectric constant different from air. Dielectric sensors measure the charge-storing capacity of the soil. This charge-storage approach is much more effective than a resistance approach.
The Texas Instruments FDC1004Q is a high-resolution, AEC-Q100 qualified, 4-channel capacitance-to-digital converter for implementing capacitive sensing solutions. Each channel has a full scale range of ±15 pF and can handle a sensor offset capacitance of up to 100 pF
The FDC1004’s basic operation of capacitive sensing implements a switched capacitor circuit to transfer charge from the sensor electrode to the sigma-delta analog to digital converter (ADC). A 25-kHz step waveform is driven on the sensor line for a particular duration of time to charge up the electrode. After a certain amount of time, the charge on the sensor is transferred to a sample-hold circuit. The sigma-delta ADC converts the analog voltage into a digital signal. Once the ADC completes its conversion, the result is digitally filtered and corrected depending on gain and offset calibrations.
An active shield coupling with the sensor helps mitigate interference and parasitic capacitances seen along the sensor signal path from the electrode to the input of the FDC1004. It also helps to focus the target direction in a specific area. Larger sensor size area increases sensitivity and dynamic range of the measurements.
AI: From comments:
Power Tree
Your device is battery powered, so power efficiency and quiescent current are vital - currently you have a 5V LDO, leading to a 3.3V LDO. There are two problems with this: first is that as justme points out, the input to it is 5V. Not only will it not help, it actively won't work - you need to put in more than 5V to get 5V out. Second is that it's hopelessly inefficient. Your 3.3V LDO has a quiescent current of 1.8uA (more on that in a moment) - your 5V LDO has a quiescent current of several mA - this is >1000x more. This will consume 99% of the energy in your design.
Another thing to consider is - why do you need 5V? The only thing in your system that you use it for is your MCU. Your MCU (along with almost all MCUs these days) can operate at 3.3V. If you use that, it will make your life much easier.
Battery Chemistry
you want this thing to run for an entire growing season. The length of a growing season varies, but say it's 6 months. NimH batteries apparently self discharge up to 20% in the first 24 hours after charging, and then up to 15% every month (nonwithstanding the fact that these cells probably will not be at room temperature). At that rate, after 6 months, all your energy has been used up by self discharge (i.e no matter what you do, they will be dead). If your growing season is 3 months, 65% of the energy has been used by self discharge. In that case, if the rest of your system lasts that long, it means your batteries are oversized by (1/0.45=)220%. If you had a less bad chemistry (like lithium ion), you could use batteries that were significantly smaller, lighter, and more efficient
|
H: What is the reason some microcontrollers are designed to be powered with 5V or 3.3V while the most common battery is 3.7V?
As we know, most batteries' voltage is rated 1.5V (alkaline) and 3.7V (Li-Ion). Indeed, alkaline battery will be 1.65V when it is new, while Li-Ion can reach 4.2V when it is fully charged. Most chargeable battery is Li-Ion. Why are microcontrollers (or most chips/ICs) voltage designation 5V? Why do they not put them 3.7V or just 4.2V? Is there any specific reason for that voltage designation? Some microcontrollers is designated 3.3V, the same voltage of two alkaline batteries when it just new put them in series, but as I have mentioned, the voltage rating is when the battery is new.
AI: I'm guessing you're young and weren't around while all this unfolded.
Lithium batteries are a very recent concept. The TTL voltage of 5 volts goes back to at least the 1960s. I recall 3.3 volts being common in the 1990s.
The lithium chemistry was starting to be discovered in 1965, but it took well into the 90s before they made any headway in improving the energy density enough to be competitive with nickel metal hydride (1.2 volts). So it didn't really "get legs" as a battery technology until the 2000s. Heck, my first few cell phones used NiMH packs.
Also, the idea of "everything being powered off batteries" is fairly novel. Early on, equipment was far too power-hungry to even conceive of running on batteries, noting that NiCd was the best battery energy density at the time, and it wasn't great. Two-hour run on a laptop was pretty good. The Mac Portable had a huge lead-acid battery. Electric vehicles of the time were a joke - here's the story of two electric cars attempting Nevada's Loneliest Road (US-50): In 1992 Noel Perrin tried to drive an EV conversion and didn't even get halfway over Donner Pass before energy density realities set in. In 2019 a Tesla made it no problem, but took a whole day*. So yeah. The idea of "run lots of stuff off batteries" is kinda new.
But the electronics industry is flexible, and certainly has a variety of options fit for powering off one lithium cell - e.g. anything with 3.3V voltage, as that is above the 'depleted' voltage of a lithium cell, and you can either buck, or use hardware tolerant of higher voltages.
* And Nevada DOT has since closed those DC fast charging "gaps", and the trip is easy today, with maybe 40 minutes spent charging from Reno to Deseret, time you'd spend eating and bathrooming anyway.
|
H: ESP-01 takes a long time and multiple resets to connect to Wi-Fi
I have a ESP-01 chip I'm trying to program using the Expressif C SDK. I'm using the ESP chip with a breakout board with a decoupling capacitor. I'm supplying power to it using the 3.3V pin on an Arduino Uno.
I flashed the Wi-Fi example from Expressif. For completeness, below is the exact code I'm flashing:
/* WiFi station Example
This example code is in the Public Domain (or CC0 licensed, at your option.)
Unless required by applicable law or agreed to in writing, this
software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied.
*/
#include <string.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/event_groups.h"
#include "esp_system.h"
#include "esp_log.h"
#include "esp_netif.h"
#include "esp_event.h"
#include "esp_wifi.h"
#include "nvs.h"
#include "nvs_flash.h"
#include "lwip/err.h"
#include "lwip/sys.h"
/* The examples use WiFi configuration that you can set via project configuration menu
If you'd rather not, just change the below entries to strings with
the config you want - ie #define EXAMPLE_WIFI_SSID "mywifissid"
*/
#define EXAMPLE_ESP_WIFI_SSID CONFIG_ESP_WIFI_SSID
#define EXAMPLE_ESP_WIFI_PASS CONFIG_ESP_WIFI_PASSWORD
#define EXAMPLE_ESP_MAXIMUM_RETRY CONFIG_ESP_MAXIMUM_RETRY
/* FreeRTOS event group to signal when we are connected*/
static EventGroupHandle_t s_wifi_event_group;
/* The event group allows multiple bits for each event, but we only care about two events:
* - we are connected to the AP with an IP
* - we failed to connect after the maximum amount of retries */
#define WIFI_CONNECTED_BIT BIT0
#define WIFI_FAIL_BIT BIT1
static const char *TAG = "wifi station";
static int s_retry_num = 0;
static void event_handler(void* arg, esp_event_base_t event_base,
int32_t event_id, void* event_data)
{
if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_START) {
esp_wifi_connect();
} else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_DISCONNECTED) {
if (s_retry_num < EXAMPLE_ESP_MAXIMUM_RETRY) {
esp_wifi_connect();
s_retry_num++;
ESP_LOGI(TAG, "retry to connect to the AP");
} else {
xEventGroupSetBits(s_wifi_event_group, WIFI_FAIL_BIT);
}
ESP_LOGI(TAG,"connect to the AP fail");
} else if (event_base == IP_EVENT && event_id == IP_EVENT_STA_GOT_IP) {
ip_event_got_ip_t* event = (ip_event_got_ip_t*) event_data;
ESP_LOGI(TAG, "got ip:%s",
ip4addr_ntoa(&event->ip_info.ip));
s_retry_num = 0;
xEventGroupSetBits(s_wifi_event_group, WIFI_CONNECTED_BIT);
}
}
void wifi_init_sta(void)
{
s_wifi_event_group = xEventGroupCreate();
tcpip_adapter_init();
ESP_ERROR_CHECK(esp_event_loop_create_default());
wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
ESP_ERROR_CHECK(esp_wifi_init(&cfg));
ESP_ERROR_CHECK(esp_event_handler_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &event_handler, NULL));
ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, IP_EVENT_STA_GOT_IP, &event_handler, NULL));
wifi_config_t wifi_config = {
.sta = {
.ssid = EXAMPLE_ESP_WIFI_SSID,
.password = EXAMPLE_ESP_WIFI_PASS
},
};
/* Setting a password implies station will connect to all security modes including WEP/WPA.
* However these modes are deprecated and not advisable to be used. Incase your Access point
* doesn't support WPA2, these mode can be enabled by commenting below line */
if (strlen((char *)wifi_config.sta.password)) {
wifi_config.sta.threshold.authmode = WIFI_AUTH_WPA2_PSK;
}
ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA) );
ESP_ERROR_CHECK(esp_wifi_set_config(ESP_IF_WIFI_STA, &wifi_config) );
ESP_ERROR_CHECK(esp_wifi_start() );
ESP_LOGI(TAG, "wifi_init_sta finished.");
/* Waiting until either the connection is established (WIFI_CONNECTED_BIT) or connection failed for the maximum
* number of re-tries (WIFI_FAIL_BIT). The bits are set by event_handler() (see above) */
EventBits_t bits = xEventGroupWaitBits(s_wifi_event_group,
WIFI_CONNECTED_BIT | WIFI_FAIL_BIT,
pdFALSE,
pdFALSE,
portMAX_DELAY);
/* xEventGroupWaitBits() returns the bits before the call returned, hence we can test which event actually
* happened. */
if (bits & WIFI_CONNECTED_BIT) {
ESP_LOGI(TAG, "connected to ap SSID:%s password:%s",
EXAMPLE_ESP_WIFI_SSID, EXAMPLE_ESP_WIFI_PASS);
} else if (bits & WIFI_FAIL_BIT) {
ESP_LOGI(TAG, "Failed to connect to SSID:%s, password:%s",
EXAMPLE_ESP_WIFI_SSID, EXAMPLE_ESP_WIFI_PASS);
} else {
ESP_LOGE(TAG, "UNEXPECTED EVENT");
}
ESP_ERROR_CHECK(esp_event_handler_unregister(IP_EVENT, IP_EVENT_STA_GOT_IP, &event_handler));
ESP_ERROR_CHECK(esp_event_handler_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, &event_handler));
vEventGroupDelete(s_wifi_event_group);
}
void app_main()
{
ESP_ERROR_CHECK(nvs_flash_init());
ESP_LOGI(TAG, "ESP_WIFI_MODE_STA");
wifi_init_sta();
}
The problem is this setup feels very fragile. When I monitor the serial output using make monitor, I see a lot of gibberish being printed. And it's really hard to get it to connect to Wi-Fi. After flashing the program, I have to reset the chip (RST pin to GND) multiple times to get it connected. When I make even a minor change (e.g., removing the comments), it stops working. I'm wondering if this is normal and what might be causing this. When I issue AT commands directly over serial, it connects to Wi-Fi fine. Following is what I almost always see on the first run after flashing the program:
EDIT:
I tried erasing the flash before before uploading the program using make erase_flash flash. Now, on top of everything else, I'm also getting the following warning message:
W (354) phy_init: failed to load RF calibration data (0x1102), falling back to full calibration
I used to get this warning before, but it disappeared after a few times of flashing the program.
AI: It seems like the issue was caused by the power supply. Instead of the 3.3V pin on Arduino Uno, I connected the VCC of the ESP-01 to 5V pin. Now it's working.
|
H: Resonant Frequency
simulate this circuit – Schematic created using CircuitLab
So, for series circuit to find resonance we have to have values of impedances (L and C) to be equal.
And then resonant frequency can be calculated wl and 1/wc but this is combination of elements how to find resonant frequency here. Is there any formula for this?
Zeq={(1*-jXc)/1-jXc} + jXl
AI: Well, notice that the input impedance of your circuit is given by:
\begin{equation}
\begin{split}
\underline{\text{Z}}_{\space\text{i}}\left(\omega\right)&=\underline{\text{Z}}_{\space\text{L}}+\underline{\text{Z}}_{\space\text{C}\space\text{||}\space\text{R}}\\
\\
&=\text{j}\omega\text{L}+\left(\frac{1}{\text{j}\omega\text{C}}\space\text{||}\space\text{R}\right)\\
\\
&=\text{j}\omega\text{L}+\frac{\displaystyle\frac{1}{\text{j}\omega\text{C}}\cdot\text{R}}{\displaystyle\frac{1}{\text{j}\omega\text{C}}+\text{R}}\\
\\
&=\text{j}\omega\text{L}+\frac{\displaystyle\frac{\text{j}\omega\text{C}}{\text{j}\omega\text{C}}\cdot\text{R}}{\displaystyle\frac{\text{j}\omega\text{C}}{\text{j}\omega\text{C}}+\text{j}\omega\text{C}\text{R}}\\
\\
&=\text{L}\omega\text{j}+\frac{\displaystyle\text{R}}{\displaystyle1+\text{CR}\omega\text{j}}\\
\\
&=\text{L}\omega\text{j}+\frac{\displaystyle\text{R}}{\displaystyle1+\text{CR}\omega\text{j}}\cdot\frac{\displaystyle1-\text{CR}\omega\text{j}}{\displaystyle1-\text{CR}\omega\text{j}}\\
\\
&=\text{L}\omega\text{j}+\frac{\displaystyle\text{R}\left(1-\text{CR}\omega\text{j}\right)}{\displaystyle1^2+\left(\text{CR}\omega\right)^2}\\
\\
&=\text{L}\omega\text{j}+\frac{\displaystyle\text{R}-\text{CR}^2\omega\text{j}}{\displaystyle1+\left(\text{CR}\omega\right)^2}\\
\\
&=\text{L}\omega\text{j}+\frac{\displaystyle\text{R}}{\displaystyle1+\left(\text{CR}\omega\right)^2}-\frac{\displaystyle\text{CR}^2\omega}{\displaystyle1+\left(\text{CR}\omega\right)^2}\cdot\text{j}\\
\\
&=\frac{\displaystyle\text{R}}{\displaystyle1+\left(\text{CR}\omega\right)^2}+\left(\text{L}\omega-\frac{\displaystyle\text{CR}^2\omega}{\displaystyle1+\left(\text{CR}\omega\right)^2}\right)\text{j}\\
\\
&=\frac{\displaystyle\text{R}}{\displaystyle1+\left(\text{CR}\omega\right)^2}+\omega\left(\text{L}-\frac{\displaystyle\text{CR}^2}{\displaystyle1+\left(\text{CR}\omega\right)^2}\right)\text{j}
\end{split}\tag1
\end{equation}
Where \$\alpha\space\text{||}\space\beta:=\frac{\displaystyle\alpha\beta}{\displaystyle\alpha+\beta}\$.
So, we can see that the amplitude of the input impedance is given by:
\begin{equation}
\begin{split}
\left|\underline{\text{Z}}_{\space\text{i}}\left(\omega\right)\right|&=\left|\frac{\displaystyle\text{R}}{\displaystyle1+\left(\text{CR}\omega\right)^2}+\omega\left(\text{L}-\frac{\displaystyle\text{CR}^2}{\displaystyle1+\left(\text{CR}\omega\right)^2}\right)\text{j}\right|\\
\\
&=\sqrt{\left(\frac{\displaystyle\text{R}}{\displaystyle1+\left(\text{CR}\omega\right)^2}\right)^2+\left(\omega\left(\text{L}-\frac{\displaystyle\text{CR}^2}{\displaystyle1+\left(\text{CR}\omega\right)^2}\right)\right)^2}
\end{split}\tag2
\end{equation}
Solving:
$$\frac{\displaystyle\partial\left|\underline{\text{Z}}_{\space\text{i}}\left(\omega\right)\right|}{\displaystyle\partial\omega}=0\space\Longrightarrow\space\omega_0=\dots\tag3$$
Gives:
$$\omega_0=\frac{\displaystyle1}{\displaystyle\text{C}^2\text{R}}\cdot\sqrt{\frac{\text{R}}{\text{L}}\cdot\sqrt{\text{C}^5\left(2\text{L}+\text{CR}^2\right)}-\text{C}^2}\tag4$$
Using your values, we find:
$$\omega_0=\sqrt{2\sqrt{30}-1}\approx3.15507\space\text{rad/sec}\tag5$$
And:
$$\left|\underline{\text{Z}}_{\space\text{i}}\left(\omega_0\right)\right|=\frac{\sqrt{4\sqrt{30}-21}}{10}\approx0.0953364\space\Omega\tag6$$
|
H: Derivative of a waveform
I am self studying linear circuits and I came to a very basic problem.
The problem:
$$y(t) = e^{-t} u(t)$$
where \$u(t)\$ is the step function.
Calculate the derivative of \$y(t)^{\prime}\$.
My take is:
$$ \begin{align}
y(t)^{\prime} & =\left( e^{-t} \right)^{\prime} u(t) + e^{-t} u(t)^{\prime} \\
& = e^{-t} (-t)^{\prime} u(t) + e^{-t} \left( u(t) \right)^{\prime} \\
& = -e^{-t} u(t) + e^{-t} \delta(t)
\end{align} $$
But this gives a solution, $$-e^{-t}u(t)+\delta(t)$$
Why?
AI: The Dirac function only has non-zero value at t=0, where your exponential has a value of 1. Therefore:
$$ −e^{−t}u(t)+e^{−t}δ(t) = −e^{−t}u(t)+δ(t) $$
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H: Molten plastic or resin over jumper terminals
I have a number of sensor boards on which I need to close two jumper connectors with solder. On the second board, my iron was not sufficiently hot and I made a mess of it. I've since replaced the iron. On the board, the solder did not adhere to the terminals and what looks like molten plastic is now covering them. Can anyone please suggest a good way forward to fix? Is it a matter of scratch away the plastic and trying again? The sensor is so tiny it's difficult. Will attach a photo of the GY-BNO055 board with the two open terminal pairs marked.
And this is how the the GY-BNO055 boards look normally with terminals open (image from Aliexpress):
AI: From your photo it is not clear how the "jumper" looks like. If it is like two pads to be shorted together, then they appear a little too far apart (they look like they are meant to host a resistor or other kind of component).
If my guess is correct it will be quite difficult to bridge the pads with a single solder joint, especially because there is solder mask between the pads.
If they are meant to be shorted at all, probably they are designed to be shorted using a 0Ω resistor during the pick and place phase of board manufacturing.
To join them manually without using a 0Ω resistor you could use a single strand of (very clean or maybe tinned) copper wire across them to act as a "guide" for the solder.
Pretinned wire-wrapping wire (AWG 30) is great for such things, once you remove its insulation. For example like this:
In this way you can help the solder to spread across the gap, otherwise surface tension will force the solder to split in two clumps, one on each pad.
Caveat: since the thing is so tiny you'll need a firm hand and some soldering skill (and a way to hold the board stuck to your workbench).
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H: TVS diodes clamping voltage against waveform and current
Having come across these two datasheets, two patterns might be inferred:
Clamping voltage increases with current: https://www.tme.eu/Document/edf5842caa2ca49fd1e87fde0a7b9438/sts32xxxxuxxx.pdf
Clamping voltage changes significantly with waveforms: https://pdf1.alldatasheet.com/datasheet-pdf/view/662439/STMICROELECTRONICS/SM6T12AY.html
Is it safe to infer these two patterns for most of TVS diodes or are these two cases outliers and nothing else?
AI: STS32:
Solid-state silicon-avalanche technology
ST doesn't actually say they're avalanche diodes, but there's very little else they could be.
A basic Thevenin diode model will suffice for this type; see Fig.3 from https://www.ti.com/lit/an/slvae37/slvae37.pdf:
That is, for applied voltage above breakdown, the diode acts as a voltage source plus resistance. The internal resistance is sometimes specified, or can be approximated from ratings. In general the resistance varies with current (this is a linearized approximation), but in general it will also tend to decrease (with rising current) towards an asymptotic minimum value, which can be understood as intrinsic internal resistances -- connecting leads and bulk silicon, those sorts of things.
You may find this and related documents informative:
https://www.st.com/resource/en/application_note/an1847-transient-protection-solutions-transil-diode-versus-varistor-stmicroelectronics.pdf
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H: Why this equation called as a plane wave equation?
I'm confused why this equation is called as plane wave equation. Is that because the direction is constant and indicates it to propagate in only one direction?
Thanks for any comment
AI: First of all, that is not an equation, but it is a way of expressing a plane wave in mathematical form.
In fact the equal sign there doesn't mean "equality", but "equal by definition". You don't solve it, it simply tells you that the lhs (a general expression for the electric field) is equal to the rhs in the case of a plane wave. In other words, that's the mathematical definition of a plane wave.
It is called "plane" because the value of \$ |E| \$ doesn't depend on R, but only on the phase, which is the same for all points in the same plane. That is the plane for which the scalar product \$ \hat k \cdot R \$ is constant, which is perpendicular to the vector \$\hat k\$ (which lies in the direction of propagation).
BTW, note that that expression technically is the phasor of the electric field, because there is no time dependency.
You may want to see, for example, this site.
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H: LED driver current consumption issue
I have an LED driver circuit that is not behaving the way I expect it to. More precisely, it’s not drawing as much current as I expect it to do. The design is not originally mine, so I don’t know the motivation behind all design choices, but I suspect the design was mostly copied from the evaluation board for the LED driver that is used in the design.
The schematic of the circuit is included below. It uses an NCL30160 LED driver to drive 4 different LEDs with wavelengths of 365, 400, 480 and 520 nm. The selection between the different LEDs is done with a BTS5200-4EKA high side switch, and the intensity of the LEDs is controlled by PWM (PC_PWM in the schematic)
The LEDs are from a company called Lumixtar with the following part numbers:
WL-5P5050EP120UV-365
WL-5P5050EP120UV-400
WL-5P5050EP120B-480
WL-5P5050EP120G-520
The 365, 400 and 480 nm LEDs have a listed forward voltage of 3.4V, while the 520 nm one has a listed forward voltage of 5.5V. All LEDs can handle a current of 700 mA.
The design choices made for the NCL30160 LED driver are the current sense resistor that controls the current (R12 in the schematic), the large inductor (L2), off-time setting resistor (R14), catch diode (D3) and input capacitor (C2).
The design seems to work fine, except for the issue that I’m not getting the current consumption that I thought I would. The selection of current sense resistor has been made to 0.27 Ohm, which according to the datasheet for the NCL30160 should result in an output current of 200 mV / 0.27 Ohm = 0.74A. However, I’m only getting a maximum of 233 mA of current. I’ve measured the current draw from a PSU at different PWM duty cycles and for the different LEDs and put it in the table below:
So I pulled out the oscilloscope to take a look at what’s going on. Below you can see in yellow the voltage of the LED- net label, between the inductor and the LEDs in the schematic above, and in blue the current measurement from the PSU, measured with a 100mV/A current clamp. These measurements are with 30%, 60% and 90% PWM duty cycles. I’m not entirely sure what’s going on, since I haven’t worked with LED drivers before, but from looking at that image and reading the datasheet I would guess that it does sort of what it’s supposed to do? The current ramps up until it hits a threshold, at which the FET starts rapidly switching on and off, depending on the tON and tOFF of the driver.
Figure 1 LED- voltage & overall current consumption, 30% duty cycle
Figure 2 LED- voltage & overall current consumption, 60% duty cycle
Figure 3 LED- voltage & overall current consumption, 90% duty cycle
My first theory was that the inductor selection was off, that with a larger inductor there would be less ripple and a higher average current, so I dug into the calculations for the inductor selection, which comes from the calculations for the tON and tOFF.
But these equations, nor the rest of the datasheet, doesn't give much recommendations on inductor sizing, beyond this bit of text:
After not being able to apply the equations properly I did what most engineers would probably have done, I simply swapped the inductor for something different to see what happened. I swapped the 100µH, 300mΩ inductor for a 15µH, 100mΩ one I had lying around, and then measured the current consumption again, with the results below.
Figure 4 LED- voltage & overall current consumption, 30% duty cycle, L = 15 uH
Figure 5 LED- voltage & overall current consumption, 60% duty cycle, L = 15 uH
Figure 6 LED- voltage & overall current consumption, 90% duty cycle, L = 15 uH
There’s some strange hysteresis effect going on between 90-100%. When I increase the duty cycle up from 90 -> 100% there’s a jump in current consumption and radical change in the switching frequency somewhere around 94-96%. Going back down it doesn’t “reset” until somewhere 92-94%.
The overall change in current consumption was negative, which I guess makes sense? The voltage regulation swings a lot more, which results in less overall current going through the LEDs. So, ignoring the consumption results ata 100% PWM the theory about larger inductor holds? So I then tried swapping the 100 µH inductor out for 2x 100µH inductors in series (I didn’t have any single SMD inductor at hand with a value larger than 100 µH, and stacking large components on PCBs is fun!) This didn’t have any impact on the current consumption at all pretty much unfortunately, the results were pretty much identical to the first table in this post.
Figure 7 Stacked inductors in series
Figure 8 LED- voltage & overall current consumption, 90% duty cycle, L = 200 uH
I then tested the swap the last component I could imagine would affect the current consumption, the off-time setting resistor. I didn’t expect this to have a large effect on the current consumption since the datasheet specifically states “The off-time setting resistor (ROT) programs the NCL30160 with the initial time duration that the MOSFET is turned off when the switching operation begins”, which I interpreted as that it shouldn’t have an effect on the continual switching, only the initial switch cycle. I changed it from 240k to 120k, and measured current consumption again, with the results below.
Figure 9 LED- voltage & overall current consumption, 30% duty cycle, L = 100 uH, Rot = 120k
This also didn’t change the overall current consumption, nor the shape of the wave forms, which I didn’t really expect it to.
So it’s at this point that I figured that I don’t really understand what’s going on here, and how the LED driver operates. I’m expecting the output current to be 0.74A continuously, based on the datasheet, but maybe that’s not the correct assumption? Maybe the LED driver is working exactly as it’s supposed to?
AI: I'm not sure where you're getting your numbers from (this is why you should link the datasheets you are using). I see typical Vf of the 480nm and 400nm LEDs as about 6.5V (6 to 7V). I only looked at those ones. They have two LEDs in series and two parallel strings.
So power consumption at 700mA would be around 4.5W. At 85% efficiency (Fig 10, two LEDs) the total consumption @24V would be around 220mA, plus a bit for the losses in the high-side switch and consumption of the chips themselves. That's pretty much what you are seeing. If I am interpreting your numbers correctly, the circuit is behaving as expected.
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H: Op Amp Precision Rectifier Question
I'm struggling a bit with op amps again! I'm trying to learn how to use an inverting precision amplifier, and I'm getting very confused about the operation of the op amp in a active rectifier configuration. I'm sure it's a simple answer and I'm overcomplicating it, so here goes.
With a unity gain inverting op amp as shown here, when Vin goes negative, Vout goes positive. Opamps will do whatever is necessary to keep the two inputs the same. Since our non-inverting terminal is connected to GND, the opamp will do whatever it can to keep the inverting terminal GND, giving us our virtual ground. So it raises Vout to match the inverse of Vin to keep our inverting terminal close to GND, yes? -1V(Vin) + 1V(Vout) = 0V. Okay sick.
Now here we have added two diodes to create an active half-wave inverting rectifier. D1 is the top diode.
When Vin is positive, we get the expected inverted output at Vout. However, when Vin is negative, the voltage gets locked at one forward diode drop. So I understand that Vout raises to + 0.7V (the diodes Vf), D1 is now forward biased and our inverting terminal is at GND. Now what happens when we lower Vin below -0.7V to say -5V? Why does the Vout not equally & inversely raise to keep the inverting terminal at ground? Vout right now is at +0.7V (or D1's Vf), but Vin is at -5V. Wouldn't the voltage at our inverting terminal be -5V? What am I missing?
Thanks!
AI: Assume op-amp and diode are ideal.
The output does everything to keep inverting input at 0V.
As the ideal diode has 0.7V drop for any amount of current such as 1mA or 10mA, all that matters is that output is at 0.7V for the inverting input to be 0V.
So, no matter how negative the input voltage is, and how much current flows in the input resistance, the op-amp output will go positive and will provide all the current it needs to keep inverting input at 0V.
But because there is a diode (instead of a simple resistor), the inverting input will stay at 0V, if output voltage stays at 0.7V.
That's because an ideal diode has always 0.7V in forward bias with any current, the voltage does not depend on current.
Compare that to the standard amplifier, where instead of diode, there is a resistor, and resistors have this linear relationship between voltage and current.
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H: Triridge reed relays data sheets/book? (for max current/voltage specs)
I have a 70s vintage circuit that uses a Triridge brand reed relay. It's marked with part number "220-100", and it's four pin, normally open. The operating voltage for the coil as seen in the circuit (and designed on the schematic) is 12V.
It's "sticking" closed when it's supposed to open sometimes (including with no power in the circuit at all), and I'm trying to determine why-- whether it's just old and been damaged from previous overcurrent excursions, whether it's under-rated for the current passing through it, some combination, etc.
I have been unable to find a scan of any data sheets or data books on eBay or whatever for this brand of relays. They seem to have made a ton of variants with often-confusing part numbers. I'd like to know what the voltage and current ratings actually are for the switching circuit.
Any pointers appreciated! Thanks.
AI: A quick web search finds a listing for a 220-100-24 that has a contact rating of 500mA resistive and 200V. Assuming they copied the numbers correctly, and assuming there is not some other additional designation for the reed capsule rating.
Reed relays are not famous for reliability when used to switch substantial current, especially if there's any inductance or surge current (or especially tiny currents, for that matter- my programmable ratio transformer warms up by clacking them all for several seconds). Sticking is a common failure mode.
If it's not a particularly picky circuit I would consider replacing it with a sealed telecom style relay. They're generally rated at 2A, which is far more than most small reeds can reliably switch. If it is a picky circuit, any similar size and rated reed will likely work.
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H: Lint tool is throwing an error about bit width when adding two 10-bit unsigned numbers and assigning to a 11-bit net
My code:
module adder(a,b,result);
input wire [9:0] a,b;
output wire [10:0] result;
assign result = a + b;
endmodule
My company recently changed policy to escalate the linting rule (W164a and W164b) mismatch of LHS and RHS bit widths from warnings to errors. Now I either have to waive these lines of code to tell the linting software not to freak out, or I have to prepend 1'b0 to both a & b.
What is the right approach here?
AI: The right approach is to discuss this situation with the people in your company who recently changed the policy. Your Verilog code is very clean, and it is a common way to add numbers together. Prepending 1'b0 to both a & b will result in code that is not commonly seen.
If you can not convince them to change this back to a warning, then you should waive these lines of code.
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H: Problem evaluating the current function over a time interval in circuit with inductance
The given expression describes a piecewise function of voltage u(t) across a circuit element with respect to time and is defined over four intervals:
$$
u(t)=
\begin{cases}
V_{0} \frac{t}{(2T)} &\text{for \(0 \leq t \leq 2T)\)}\\
V_{0} &\text{for \(2T \leq t \leq 3T)\)}\\
-V_{0} &\text{for \(3T \leq t \leq 4T)\)}\\
\frac{V_{0}}{2}(\frac{t}{T}-6) &\text{for \(4T \leq t \leq 8T)\)}
\end{cases}
$$
for $$0 < t \leq 2T$$
The expression $$i(t)=i(0)+\frac{1}{L} \int_{0}^{t} V_{0}\frac{t}{2T}dt$$ is a relationship between the current i(t) and the voltage V_0 over time for an inductor with inductance L.
Doing the math (if I am correct) I take:
\begin{align*}
\frac{1}{L} &* \int_{0}^{t} V_{0}\frac{t}{2T}dt\\
&=\frac{V_{0}}{L} \int_{0}^{t} \frac{t}{2T}dt\\
&=\frac{V_{0}}{L}\dfrac{t^2}{4T}\\
&=\frac{V_{0}}{L}(\dfrac{t}{2T})^2
\end{align*}
the book that I am reading gives the result $$i(t) =\frac{V_{0}T}{L}(\dfrac{t}{2T})^2 $$.
2 questions :
1) First of all the i(0) = ?
2) where the T in the numerator came from in the resulted expression ?
AI: Well, mathematically speaking let's define the voltage in a possible correct way:
$$\text{V}\left(t\right):=\begin{cases}
\displaystyle\text{V}_0\cdot\frac{t}{2\text{T}}&\text{if}\space0\leq t<2\text{T}\\
\\
\displaystyle\text{V}_0&\text{if}\space2\text{T}\leq t<3\text{T}\\
\\
\displaystyle-\text{V}_0&\text{if}\space3\text{T}\leq t<4\text{T}\\
\\
\displaystyle\frac{\text{V}_0}{2}\cdot\left(\frac{t}{\text{T}}-6\right)&\text{if}\space4\text{T}\leq t\leq8\text{T}
\end{cases}\tag1$$
Now, the relationship between the voltage across and the current through an inductor is given by:
$$\text{V}_\text{L}\left(t\right)=\text{I}_\text{L}'\left(t\right)\cdot\text{L}\space\Longleftrightarrow\space\text{I}_\text{L}\left(t\right)=\text{C}+\frac{1}{\text{L}}\int\text{V}_\text{L}\left(t\right)\space\text{d}t\tag2$$
So, we get:
\begin{equation}
\begin{split}
\text{I}_\text{L}\left(t\right)&=\text{C}+\frac{1}{\text{L}}\int\text{V}_\text{L}\left(t\right)\space\text{d}t\\
\\
&=\text{C}+\frac{1}{\text{L}}\int\text{V}\left(t\right)\space\text{d}t\\
\\
&=\text{C}+\frac{1}{\text{L}}\cdot\begin{cases}
\displaystyle\int\text{V}_0\cdot\frac{t}{2\text{T}}\space\text{d}t&\text{if}\space0\leq t<2\text{T}\\
\\
\displaystyle\int\text{V}_0\space\text{d}t&\text{if}\space2\text{T}\leq t<3\text{T}\\
\\
\displaystyle\int-\text{V}_0\space\text{d}t&\text{if}\space3\text{T}\leq t<4\text{T}\\
\\
\displaystyle\int\frac{\text{V}_0}{2}\cdot\left(\frac{t}{\text{T}}-6\right)\space\text{d}t&\text{if}\space4\text{T}\leq t\leq8\text{T}
\end{cases}\\
\\
&=\text{C}+\frac{1}{\text{L}}\cdot\begin{cases}
\displaystyle\frac{\text{V}_0}{2\text{T}}\int t\space\text{d}t&\text{if}\space0\leq t<2\text{T}\\
\\
\displaystyle\text{V}_0\int1\space\text{d}t&\text{if}\space2\text{T}\leq t<3\text{T}\\
\\
\displaystyle-\text{V}_0\int1\space\text{d}t&\text{if}\space3\text{T}\leq t<4\text{T}\\
\\
\displaystyle\frac{\text{V}_0}{2}\cdot\left(\frac{1}{\text{T}}\int t\space\text{d}t-6\int1\space\text{d}t\right)&\text{if}\space4\text{T}\leq t\leq8\text{T}
\end{cases}\\
\\
&=\text{C}+\frac{1}{\text{L}}\cdot\begin{cases}
\displaystyle\frac{\text{V}_0}{2\text{T}}\cdot\frac{t^2}{2}+\text{n}_1&\text{if}\space0\leq t<2\text{T}\\
\\
\displaystyle\text{V}_0t+\text{n}_2&\text{if}\space2\text{T}\leq t<3\text{T}\\
\\
\displaystyle\text{n}_3-\text{V}_0t&\text{if}\space3\text{T}\leq t<4\text{T}\\
\\
\displaystyle\frac{\text{V}_0}{2}\cdot\left(\frac{1}{\text{T}}\cdot\frac{t^2}{2}-6t\right)+\text{n}_4&\text{if}\space4\text{T}\leq t\leq8\text{T}
\end{cases}
\end{split}\tag3
\end{equation}
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H: Would this 3-phase sequence detector circuit work?
I was searching for a circuit that would detect 3 phase sequence and give dry contact output if the sequence is correct.
I have found the schematic below, from a Daikin compressor manual. I wonder if this will work if I assemble it?
As you can see all part of the elements value table given above. I have already checked this circuit at LTspice simulator and it seems it’s ok but im not sure yet. Because, I cannot see any voltage between relay coil on simulator also at 1C which sharing same nodes with relay coil. I can only see 24 V at when I attached probes between 1C (positive side) and 1ZD (anode side). This situation made me confused. What you are thinking, is that circuit can work at 400 V 50 Hz 3 phase lines? Otherwise which modifications needed?
Note: 1SA described at table as "Rheostat" . But im thinking of its a "SA" series TVS diode which manufactered by Littelfuse. If im wrong , correct me please.
AI: First, let's redraw the circuit diagram so it'll be more legible. Then we can simulate it and see what it does :)
CircuitLab is built into this website in both the question editor and in the answer editor - to use it, click the schematic icon:
And thus the schematic:
simulate this circuit – Schematic created using CircuitLab
The relay has a 0.1mH (guessed), 2.8kΩ (per the datasheet), 24V coil.
And the good news is:
It works! :)
When SW2 is as shown, the phase order is R-S-T, and the relay and the lamp turns on:
When SW2 is flipped, and the phase order is reversed to S-R-T, the relay stays off:
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H: Converting AGC Schematic from Single Sided to Dual Sided Supply
I am working with the attached circuit, sourced from here: Original
This circuit is designed for a single sided power supply and has worked very well for me in the past. For a new project, I would like to use it with a dual sided power supply, providing -6V, 0V, and +6V. Ignore the "precharge" section in the dotted box and R1, they will not be used.
I think I can remove R3, R4, R5, and C2 because they are just used to bias the op-amp for a single sided supply. Is this correct?
I don't understand the purpose of C4. Why is it there and is it required for a dual sided supply?
I don't understand the purpose of D2. Why is it there and is it required for a dual sided supply?
Would I be correct to connect each of the ground symbols, except for the U1 (-) power supply and the decoupling cap(s), to my 0V rail after removing the bias components I described in item 1?
Thanks!
UPDATE:
Breadboarded the circuit based on the feedback received.
All of the ground locations were connected to -6V except for R3 which was connected between U1 pin 3 and 0V.
R4, R5, and C2 were eliminated.
Initially I tried eliminating C4, but circuit oscillated badly. I replaced C4 and connected that between R6 and -6V. After that the circuit seems to be working well.
AI: Would I be correct to connect each of the ground symbols, except for the U1 (-) power supply and the decoupling cap(s), to my -6V rail after removing the bias components I described in item 1?
Why not connect U1's negative supply also to -6V? The op-amp's supplies will have to be +6V and -6V for your idea to work, but you are otherwise correct.
I don't understand the purpose of C4. Why is it there and is it required for a dual sided supply?
C4 has high impedance at DC, which is as if it's not there, for any DC component of the signal. C4, C7 and R6 can be disregarded at DC, leaving only R7, which makes U1 a voltage follower, with unity gain for any DC offset present at its non-inverting input. U1's output is therefore centered about whatever mean potential is established by the biasing network of C1, C2, R3, R4 and R5.
Another way of thinking about C4 is to consider its DC charge state. It will develop a mean DC voltage equal to the mean output potential, raising the op-amp's inverting input potential to equal the mean potential at the non-inverting input. In this way it becomes a kind of "ground" reference at about +6V, instead of 0V.
C4 will not be required if you have an actual 0V node, as indeed will be the case if you convert to supplies with +6V, 0V and -6V.
I don't understand the purpose of D2. Why is it there and is it required for a dual sided supply?
D2 prevents Q2's base from dropping below -0.7V, and Q2's base-emitter junction prevents that potential from rising above +0.7V. Between them Q2 and D2 constrain the signal at Q2's base to be within +0.7V and -0.7V.
There are two consequences that spring to mind, there may be others. Firstly, Q2's base-emitter junction will never be reverse biased to the point that it breaks down, which would seriously mess up the AGC's behaviour.
Secondly, the right side of C5 experiences similar loading during both negative and positive excursions of the op-amp's output. If D2 were not there, the resulting loading asymmetry would offset the mean potential at C5's right end, which should be 0V in the original, or -6V with your modifications.
You can't remove D2.
I think I can remove R3, R4, R5, and C2 because they are just used to bias the op-amp for a single sided supply. Is this correct?
You are almost correct. You will still need R3 to bias the non-inverting input at 0V, but the other three elements can be removed.
What you are left with is:
simulate this circuit – Schematic created using CircuitLab
All gain control elements, that I've omitted here, need to operate around -6V, their "grounds" must become -6V. All their +12V nodes become +6V.
Since your output is now ground referenced, and the AGC system requires a -6V baseline signal, C5 can no longer be used for DC blocking in both roles. It may no longer be required to block DC for the final output, but C5 is still necessary to allow the signal at Q2's base to be centered around -6V. Hence C5's change of position.
It's not clear to me without more thinking, whether it's safe to raise the input bias (via R1) to 0V, instead of -6V, so I've left it biased as it would have been in the original. Since the source is a microphone, that may be good enough, but if the source wasn't isolated, and shared a common 0V with this module, then additional AC coupling (a capacitor) at the input would probably be necessary.
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H: Why am I getting 5V at the hex inverter output?
Why am I getting 5V at point A?
The microcontroller IO is 3.3V.
AI: An open drain/collector inverter will not drive its outputs high and the pullups voltage will set Vout.
An inverter that is not open-drain will drive its outputs to near its V+ supply voltage - in this case = 5V.
The MC74ACT05DR2 open drain inverter will do what you want.
The 74AC05 also will. Datasheet for both here
It's intended to emulate an LS type open drain part.
An alternative is to use a 3V3 supply inverter and 5v to 3V3 input divider.
Q: Please specify the inverter type that you are using.
A: That's a possible but not certain solution. It will work IF the inverters are tolerant of 5V input.
As I said, ideally you need either open drain inverters or - not mentioned, inverters designed for level shifting.
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H: How does a current mirror work?
I'm trying to understand how current mirrors work.
In the text book Microelectronics by Jacob Millman, section 3-11, example 3-8, there is a picture of a current mirror:
They said if we consider \$V_{BE}\$ of these two transistors to be the same (0.7 V) then \$I_B\$ and \$I_C\$ of these 2 transistors are equal.
Question 1:
This statement confuse me. I think the correct statement should be "The maximum allowable \$I_C\$ of Q2 is equal to Q1's \$I_C\$", because the base current \$I_B\$ of a transistor is only a "valve" for the current, it decides the maximum current, but the actual current should be decided by the load. So when they said the two \$I_C\$s are the same, are they refering to the maximum of Q2's \$I_C\$?
Question 2:
When I simulate this circuit in LTspice, the result is strange:
The \$I_B\$ currents of the two transistors aren't the same. What am I doing wrong?
AI: Here is what you get ... as @periblepsis pointed out ...
You can see that "current mirror" if my R2 > 250 Ohms ...
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H: Why doesn't ESD cause a large amount of current?
It is agreed that ESD is caused by kV level large potential differences:
When we handle an ESD sensitive device such as a MOSFET or a type of diode etc., why doesn't it burn when it gets damaged by the ESD? If V = I * Z , wouldn't kV level of voltage cause a huge current through the device? I am looking for an answer as a simple circuit model or a model equation which shows why we don't experience a huge amount of current.
AI: The model most found to be useful is a 1.5kΩ resistor and a 100pF capacitor charged to a high voltage. It is described, for example, in MIL-STD 883:
A suggested schematic is provided in the linked standard.
Whether an ampere or so is a "huge" current is a matter of perspective. It's pretty large for a small structure on an IC to absorb, particularly if there is much voltage across the structure.
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H: PNP transistor symbols, pins and footprints
I am currently building a soft latch circuit in a CAD editor.
I want to use a PNP transistor, and have 2 choices for this component.
However, I am confused when comparing the datasheets of the components with the symbols and footprints in the CAD editor.
Part 1 looks like this. Pin 1 is base, pin 2 is emitter, pin 3 is collector. This lines up with it's data sheet. Also the footprint numbering lines up with the datasheet.
(Screenshot from EasyEDA)
(Image source: LCSC - Galaxy Microelectronics MMBT3904 datasheet)
For part 2, Pin 1 is base, pin 2 is collector, pin 3 is emitter in the CAD symbol. Ok, I understand that the pin numbering could be different. Looking at the datasheet, however, pin 1 should be emitter, pin 2 should be base, and pin 3 should be collector. Also, the footprint pin numbering is different then in the datasheet.
I tried to replace the symbol of part 1 in my schematic with part 2, but now I find out that the pins are swapped. Is it true that I can never just replace symbols in the schematic for transistors?
(Screenshot from EasyEDA)
(Image source: LCSC - Unisonic Technologies MMBT3906 datasheet)
I saw in a video that PNP/NPN transistor symbols are not unified. Does the empty/filled arrow in the symbol represent something different? Is the symbol and footprint for the second part plain wrong? Should I trust the datasheet of the second part, or not use it at all?
AI: You appear to have schnipped the datasheet image from the Unisonic (Taiwan) datasheet.
Their numbering of the pins is non-standard, IME. In any case, the transistors are physically interchangeable, only the pin numbering is wonky. I would ignore the Unisonic datasheet for the purposes of creating the symbol/footprint mapping. Use the Onsemi (nee Motorola) datasheet pin numbering.
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H: Good book on EMC and EMI
I'm looking for a good book about EMC and EMI.
There are plenty of books talking about norms and standards, but I'm looking for a book focusing on understanding the logic and physics behind it. And how to design filters and housings to reduce EMC and EMI issues.
Thanks.
AI: Fast Circuit Boards Energy Management
https://www.google.co.in/books/edition/Fast_Circuit_Boards/GIBDDwAAQBAJ?hl=en&gbpv=1&dq=high+energy+boards&printsec=frontcover
EMI Filter Design
https://www.google.co.in/books/edition/EMI_Filter_Design/H37y0HIyd4oC?hl=en&gbpv=1&printsec=frontcover
Introduction to electromagnetic compatibility
https://www.google.co.in/books/edition/Introduction_to_Electromagnetic_Compatib/GUjStAEACAAJ?hl=en
Electromagnetic Compatibility Engineering
https://www.google.co.in/books/edition/Electromagnetic_Compatibility_Engineerin/07rFwAEACAAJ?hl=en
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H: Current regulation compensation SG3524 and right place to place sense resistor
What is the right place to place current sense resistor? As in picture we get traingular wave n position 1, sine wave with highest amplitude on pos 2, smaller sine wave on pos 3 and nearly flat line but still there is sine wave on pos 4. There is DC Offset ofcourse and since its all symetrticaly moving around constant value its mean value is "same" for all positions.
I am able to stabilise control voltage part, but on current regulation, it just wont get stable.I guess pos 4 is the right one. Also worth mentioning SG3524 has transconductance error amplifiers. I am gonna use TL072 instead and its output connect to COMP pin. Thanks
AI: (1) so that the loop can be closed on current (average current mode control). Then add another error amp to regulate voltage.
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H: Please explain the highlighted part on the working of a D flip-flop
The section of the textbook Digital Design by Morris M. Mano and Michael D. Ciletti says the following about D flip-flops:
Another construction of an edge-triggered D flip-flop uses three SR latches as shown in Fig. 5.10. Two latches respond to the external D (data) and Clk (clock) inputs. The third latch provides the outputs for the flip-flop. The S and R inputs of the output latch are maintained at the logic-1 level when Clk = 0. This causes the output to remain in its present state. Input D may be equal to 0 or 1. If D = 0 when Clk becomes 1, R changes to 0. This causes the flip-flop to go to the reset state, making Q = 0. If there is a change in the D input while Clk = 1, terminal R remains at 0 because Q is 0."
How is the value at terminal R dependent on the output Q? Is it a logical fault in the explanation? If it isn't, please explain this part of the reasoning.
AI: But how is the value at terminal R dependent on the output Q? Is it a logical fault in the explanation? If it isn't, please explain this part of the reasoning.
The description is certainly misleading, and its correctness is debatable. Because \$R\$ and \$Q\$ go into a NAND gate, if \$Q = 0\$ the the output of the NAND is as if \$Q = 0\$; that holds \$Q'\$ high, so as long as the preceding circuitry is holding \$S\$ high, \$Q\$ stays at zero.
It is -- I hope! -- not how I'd have described it.
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H: Altium: Comment field of schematic symbols
Eagle does not contain a Value field for the schematic symbols. Rather, it contains a comment field. From what I know this field shall contain the resistance, capacitance and inductance value for resistor, capacitor and inductor component respectively. In these cases, the comment field must always be visible.
Now what is not clear is what to do with other components. These are diodes, transistor, connector and ICs. What is the comment field supposed to contain for these components? I mean, one can put anything, but what is the correct information to put into it? Someone will say put the part number. But if this is true then why don't we put part number of the resistors, capacitors and inductors and have a third field that shall contain their value since all components do not have a value field you see.
AI: There is no requirement for what goes there other than what others might ask you to do. (e.g. an organization requires specific formatting to ensure schematics produced by different engineers follow the same format, or a tool that parses schematics--such as a simulator plugin--may require specific fields to contain specific data.) Unless someone or something else requires something specific to be there, the field is just there for your reference, and you can put whatever you personally find most useful in it.
Below, I've written a bit about my personal practices. This should not be considered any sort of recognised standard; it's just what I do and what I've found useful.
What I do with the equivalent field in KiCad (called "Value") is put the value of resistors, capacitors, inductors, and the odd other component where a value makes sense (e.g. zener diodes' breakdown voltages, or battery pack voltages), and put the "reduced" part number (by which I mean, for instance, Si2318 instead of Si2318DS-T1-E3) for ICs, transistors, diodes, and connectors where a specific part number has been chosen and/or is important. For parts where any generic part meeting given specifications can be used and I want to leave that open, I'll put the requirements--e.g. "BNC", or "2 A Schottky", or what-have-you.
Passive parts with specific requirements may get additional annotations, such as "1 μF 50 V" to specify that the capacitor needs to be 50 V rated, or "51.1 kΩ ±0.1%" if a resistor needs to be more precise than standard (usually only where the requirement isn't obvious).
I then typically add additional "manufacturer" and "part number" fields where I put the manufacturer's name and the entire part number for each part that needs one. Sometimes passive components remain generic where any old 0402 package 1 kΩ resistor (for instance) will do. (I usually also put an additional "minimum voltage rating" field on capacitors for quick reference when choosing parts, so I can have that information in the BOM.)
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H: Does a MOSFET require a gate inline or pull up/down resistor when being driven from a NE555
I am trying to run some indicators/flashers on my own made bicycle. I have attempted ready-made automotive flashers but have found the lights don't draw enough current for the 2-wire ones and get weird behaviour. With the 3-wire relays types I have been unable to get them to stay in sync when the hazards are activated (both left and right activated at the same time)
I have attempted to make a circuit of my own using components I have to hand.
simulate this circuit – Schematic created using CircuitLab
Given the above circuit do my mosfets need any inline gate resistors or pull up/down resistors?
Is there anything else in the circuit I have overlooked or won't work as intended?
To further complicate things the switches are part of a switch cluster that shares a common positive and the lights are part of a light cluster that shares a common negative meaning I cannot alter the circuit outside of the switches and lights.
Update: Thank you for all the answers. Based on them I went with a simpler solution of using a DPDT relay driven by the 555 timer:
simulate this circuit
No need to worry about driving FETs or transistors, provides a satisfying click-click and I connected the indicators to the NC-connected pins so that the indicators come on as soon as they are switched.
AI: The MOSFETs need to be connected in common-source configuration. And you only need one of them. No need for a pull-down on the mosfet for basic functionality, since when the gate is not driven - when 555 is off - the lights have no power either. But to protect the MOSFET against electrostatic charge building up on the gate, a pull-down would be nice to have.
simulate this circuit – Schematic created using CircuitLab
C3 charges when the bulbs are in the dark part of the cycle, and then powers U1 when M1 conducts. That way you can still use just one MOSFET, and the circuit works pretty much like an old-style blinker would - it has only two external connections :)
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H: Second PCIe on KeyE M.2?
Based on this online resource, KeyE M.2 has
2x PCIe x1 / USB 2.0 / I2C / SDIO /
UART / PCM
Their pinout table shows these lanes (for E-key):
35 PETp0
37 PETn0
41 PERp0
43 PERn0
47 REFCLKp0
49 REFCLKn0
50 SUSCLK
52 PERST0
53 CLKREQ0
55 PEWAKE0
59 Reserved/PETp1
61 Reserved/PETn1
65 Reserved/PERp1
66 PERST1
67 Reserved/PERn1
68 CLKREQ1
70 PEWAKE1
71 Reserved/REFCLKp1
73 Reserved/REFCLKn1
I successfully managed to install an M2 (M-key) SSD into a keyE slot with an adapter, by interconnecting the above KeyE pins with the SSD (M-keying):
KeyE KeyM
-----------------------
35 PETp0 49 PETp0
37 PETn0 47 PETn0
41 PERp0 43 PERp0
43 PERn0 41 PERn0
47 REFCLKp0 55 REFCLKp
49 REFCLKn0 53 REFCLKn
53 CLKREQ0 52 CLKREQ
55 PEWAKE0 54 PEWAKE
50 SUSCLK 68 SUSCLK
52 PERST0 50 PERST
Now, the NVMe SSD is perfectly recognized by Linux, however, I just have realized that there is another PCIe on the KeyE slot.
Can I utilize this (pins above 58 on KeyE) other PCIe to make the NVMe SSD faster?
Currently it's downgraded (due to 1x PCIe) (lspci output):
LinkSta: Speed 5GT/s (downgraded), Width x1 (downgraded)
Can I interconnect KeyE's PCIe1 to KeyM's PCIe1?
I can only connect these:
KeyE KeyM
-----------------------
59 PETp1 37 PETp1
61 PETn1 35 PETn1
65 PERp1 31 PERp1
67 PERn1 29 PERn1
Or I have to somehow configure (synchronize) PCIe1's clocks and controls (REFCLKp1, REFCLKn1, CLKREQ1, PEWAKE1, PERST1) to control PCIe0's clocks and controls?
AI: As the secondary PCIe pins are optional, there is no guarantee that they are even wired up.
Even if they were, it is generally not possible to combine multiple PCIe links into a single one.
To be able to aggrigate the lanes from different links into a single link both the upstream port and BIOS/EFI/Firmware would have to support this, which would only be possible if the two links were bifurcated in the first place (i.e. they were originally a larger link split up into seperate links).
About the only reasonable thing you could do to speed things up in the highly likely case that aggregation is not supported, would be to use two SSDs, and form a striped RAID array. This would split accesses across the two drives to hopefully increase the overall transfer rate.
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H: How can I change the frequency of a sine wave from 5 MHz to several smaller ones, e.g. 1kHz, 100Hz and 1Hz?
5 MHz is the frequency of the quartz based oscillator. I get a clean, sine wave output. I would like to (divide) this signal into several, lower frequencies in steps, e.g. 1kHz, 100Hz and 1Hz. I don't want to use a microprocessor but an analog circuit instead.
AI: Do you want sine waves as the output? If so, there are several viable approaches:
Have voltage-controlled-frequency sinewave oscillators, and control their frequency using a PLL referenced to the 5MHz oscillator. E.g. a Wien bridge oscillator for each frequency, and use a vactrol and a PLL to keep its frequency and phase slaved to the 5MHz reference.
Divide the 5MHz down to desired frequencies using digital dividers, then low-pass the square waves to yield sine waves.
Use a counter, a bunch of magnitude comparators, and a wide-input XOR gate (parity generator) to make magic sine waves, then low-pass filter them using a low-order lowpass. The magic sinewave pulse trains only have the fundamental and very high harmonics, with nothing in-between, so should be easy to do.
Use a high frequency VCO and a PLL to generate 5MHz+Δf, then mix the two and low-pass the output.
Use a direct digital synthesis chip capable of low frequency output. The chip can be initialized using a long parallel-input, serial-output shift register with inputs set to configure the frequency as needed.
For #1, another approach might be to make a Bubba oscillator - four stages that shift 45° in phase in series - using an op-amp with current-controllable bandwidth. An LM146/LM346 would work well as an oscillator - it's a quad op-amp with bandwidth adjustable with a control current. A PLL's output would control the current source biasing the op-amp.
For #2, design 4th-order op-amp-based low-pass filters using a tool, then implement them, and you should get a reasonable-enough sine wave.
5 MHz is the frequency of the quartz based oscillator. I get a clean, sine wave output.
Just because you have a 5MHz sine wave doesn't mean it can be directly "converted" to a lower frequency. In almost all viable approaches, that sine wave will be either fed to a PLL as a reference input, or will have to be converted to a square wave to feed digital circuits.
And also there's no way to say how "clean" the output is unless you show spectrum analyzer plots.
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H: I am trying to figure out why npn does not work here... what assumptions should be made?
So I tried the calculation of
ic = (15-10)/2k = 2.5mA -> ib = 25uA, ie = 2.525mA
Vce = 15 - 2k*(2.5mA+2.525mA) = 4.95V
As Vbe = 0.5V, Vb = 5.55V required
voltage drop by 10k resistor = 250mV -> Vop,output = 5.8V
and I'm stuck from here.
Should I say this model would not work because Vop,output should be zero?
Also, I tried some simulations and found out that flipping inputs work, but I don't get why that would not work in real life. (according to my instructor)
AI: Not sure what "work" means in this context. The circuit you show has positive feedback so the op-amp output will rail (negative). That will likely cause the E-B junction of the transistor to break down in real life so the output voltage will be a volt or two below ground. The breakdown or may not be modeled in simulation. If it is not, the output voltage will be ~0V. Think about what a slight imbalance at the input does to the output. See if it will tend to compensate for the imbalance or if it will add more imbalance- if the latter, you've got positive feedback.
Flipping the inputs of the given circuit may or may not result in a stable output depending on the exact components. With the given resistor values and input voltage the gain is about -1 and there is a bit of phase shift so it may stabilize, likely with a somewhat degraded phase margin. If the gain of the transistor stage is too great or there is too much phase shift it may oscillate.
It's unclear what you are trying to accomplish here, so I suppose any of the above may be considered "working". Even if the circuits mentioned above are stable they are something like a ~2.5mA constant-current source into a 2kΩ resistor, so the voltage would change with any loading on Vout. In other words, not a constant voltage output. There are applications for such a circuit, for example if the bottom 2kΩ resistor was replaced with a capacitor it would generate a linear slope over some range of voltage.
If you are just trying to buffer the output of the op-amp and get a constant voltage output for a range of loads on Vout to ground, an emitter follower with feedback from the emitter to inverting input would be the way to do it. The base resistor would limit the op-amp output current and a collector resistor would similarly limit the output current. You can divide the input voltage to 5V if that is what you want at the output. Note that this circuit will likely be stable as described, but much capacitive loading (way less than a typical IC bypass capacitor) will cause oscillation so it's not a practical voltage regulator without additional work.
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H: Missing indicator in XL4016 buck converter module
I’ve bought below XL4016e1 buck module. There is an empty spot between the Indicator light and Input negative, between the left most capacitors.
What component is missing there? an LED/buzzer/adjustment POT?
What it supposed to do/indicate? Short circuit, No load, Over-under voltage, output lower than battery voltage, or some calibration?
From the backside it looks like one end is connected to Output negative
I couldn’t find a shop on the Internet providing this information. Some versions of this module seem to have left this spot blank on PCB.
AI: It’s just a spot for an LED with a series resistor (probably also not fitted, on the opposite side of the PCB and mostly obscured by the heat sink in your photo) connected across the output.
Not very vital. The bicolor LED already provides input power and overload indication. Unlike the latter, the brightness would vary with output voltage adjustment.
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H: Running multiple ICs with a single crystal
I need to run three AD7779 ADCs using the same clock signal for synchronization. I don't have access to an oscillator which I can use as a master clock, so I was wondering how I could use a single passive crystal to run all three ICs.
AI: The ADC you describe supports the use of a CMOS clock signal, as well as the use of a passive crystal. While you state that your selection of available components is limited, basic logic gates may be easier to source.
If you use a crystal alongside two inverter logic gates (one unbuffered, one Schmitt-triggered in the example below), you can then drive multiple chips from the output of the second logic gate.
simulate this circuit – Schematic created using CircuitLab
This diagram is based on TI Application Note SCEA099 (https://www.ti.com/lit/an/scea099/scea099.pdf)
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H: How to achieve the lowest noise configuration from a differential setup
I want to be able to capture a differential output from a shunt resistor. The shunt resistor differential voltage will range from 2.5mV to 50mV at 50Hz.
My initial idea was to send this signal through a unity gain differential amplifier and then send this output to a series of passive high-pass filters, active low-pass filters, and amplifier stages.
This will be done in order to apply a 40dB gain to the signal. Hence 50mV will be amplified to 5V. However, I want to have a resolution of around 5uV. I came across the AD8675 which has an input noise of 2.5nV/sqrt(Hz). Which looks like it will be good enough.
Can I just use the AD8675 for all stages of my design? (i.e. differential, active filters and amplification stages)
AI: My first thoughts are these; you ought to "draw" a signal that is typical in wave-shape but, towards the low end of the amplitude values you want to detect. Then, you should explain what it is about the signal that is important to maintain when amplified and filtered. I mention these things because I believe you may be misinterpreting what the input noise of the amplifier means.
It doesn't mean you can amplify a sinewave (low signal bandwidth) and get an improvement in noise compared to a signal of twice the bandwidth.
What it does mean is that if your amplifier channel has a noise-bandwidth of (say) 100 kHz, the equivalent input noise is 2.5 nV (RMS) × \$\sqrt{100000}\$ = 790 nV RMS and, the \$6\sigma\$ p-p value will be 4.7 μV p-p. That's the equivalent input noise.
I want to have a resolution of around 5uV
If that's an equivalent input resolution then you are close to the numbers I used above. You should make your own calculations based on the estimated noise-bandwidth of your amplifier.
Of course you may not understand noise-bandwidth so please ask if you need more detail.
Also, have you taken into account the low-frequency noise of the op-amp (100 nV p-p)? It's quite a good op-amp so maybe this won't be a showstopper.
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H: Parasitic oscillations for phase shift not equal to -180 degrees
From "Learning the Art of Electronics" by T. Hayes and P. Horowitz, Cambridge University Press (p. 360):
As per above figure, the LF411 op-amp imposes a -90 degree phase shift on output voltage. It is stated that to prevent parasitic oscillations, we must avoid including an RC circuit within the (negative) feedback loop, which induces an additional -90 degree phase shift at large frequencies, bringing the total phase shift to -180 degrees at some large frequency.
However, for a purely sinusoidal signal if the voltage fed back to the inverting input has any phase shift (except 0 degrees), it will violate the op-amp rule that for negative feedback, difference in voltages at the inverting and non-inverting inputs should be zero.
Why the emphasis on avoiding precisely -180 degree phase shift, vis-a-vis parasitic oscillations ?
AI: 180° of phase shift is true positive feedback and you get an oscillator. A bit less than 180° means that you see a lot of oscillatory ringing when you try and amplify step edges (such as a square wave) and, if you plotted the closed-loop frequency response you would see a big undesirable peak in the spectrum.
Around 120° of phase shift is about the point where most amplifiers would be acceptable in a lot of circuits but, it's still not ideal. 90° or less is pretty good and acceptable.
Op-amps are far from ideal. Here's a simulation of an op-amp that has a 1 MHz unity gain bandwidth and an open loop gain of 1,000,000. X1 is the diff input followed by an open loop gain of 1 million followed by an RC network that limits the BW to 1 MHz. A unity gain buffer follows it: -
Switch SW1 is open circuit hence, there is no feedback. When SW1 closes (later on), it becomes a 10 MΩ resistor. Notice that the phase shift is getting close to -90° by 100 Hz but, if I close the loop to make ×11 amplifier we see this significantly different result: -
Do you see any problems with this closed-loop amplifier given that the resulting output phase shift remains reasonable close to 0° well past 10 kHz? Here's what the input and output look like when driving a 100 Hz 1 volt p-p square wave: -
Do you see any ringing or overshoot on the output? Let's try a 100 kHz square wave: -
No overshoot problems here but, what if I added an extra pole (R3, C2): -
Above 100 kHz, the phase shift is marching towards -180° yet, the overshoot is only somewhat undesirable and, probably liveable-with in many applications. And, as a bonus waveform, here's the closed-loop spectral response for the above: -
And clearly, if you see a peak in the response then, there is bound to be some overshoot but, of course, the open loop response gave us that information.
So, in summary, op-amps with significant open-loop phase shift show very little phase change (input to output) when the loop is closed and, even if we really push things by adding an extra pole around 200 kHz, the overshoot is liveable-with for many applications.
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H: L298N as LiPo charger
The L298N motor driver contains a voltage regulator (lm317), so is it possible to adjust the output voltage beyond 5V and 12V to charge a 7.4V lithium polymer battery?
AI: That's an extremely bad idea. Even if the chip contained a voltage regulator like the LM317 (which it doesn't, BTW, see below), the charging process for a Lithium-based cell must be extremely controlled, unless you want to risk the destruction of the cell (and in case of naked cells, you could also risk "venting with flames" accidents).
A lithium cell needs to be charged in different phases. The two main phases are first a constant current (CC) phase, until the cells reaches the target voltage (a.k.a. float voltage: 4.200V±50mV for the most common Li-Mn chemistry), then there is a constant voltage (CV) phase, where current is monitored until it decreases to about a fraction of the C value of the cell (usually between C/10 and C/20). During the CV phase the voltage must remain constant with ±50mV tolerance or so.
Moreover, if the cell starts being charged when its voltage is below some minimum value (e.g. 3.5V) it needs to be "precharged" with a constant current that is much less than the normal charging current in the CC phase, until it reaches the threshold voltage.
On top of all that, the control logic of the charger must ensure that the cell voltage is not below some absolute minimum (e.g. 2V), under which the cell should be considered permanently damaged, because if you tried to charge a cell that has become so discharged its internal structure has changed so much that charging it becomes dangerous.
Any attempt to charge the cell outside all those limits will either result in an underperforming cell (less charge stored, much more energy wasted to charge it to a certain level), or in a damaged cell. A damaged cell could simply lose part of its capacity permanently or, in the worst case, become susceptible to leakage or venting during usage or charging, which is very dangerous for any lithium-based cell.
A quite old, but still meaningful, application note from Texas Instruments about battery charging is this. It's an application note for older charger chips, but the theory about charging is still relevant today and it is explained fairly well.
That's why even cheap-ass chargers use a dedicated chip that automates such procedures. An example is the ubiquitous and extremely cheap TP4056 from the Chinese Top Power ASIC Corporation. That's a chip suitable for single-cell Li-Mn (Lithium-Manganese, probably the most common chemistry today in consumer products) batteries.
There are even cheap charger modules sold on Amazon or other platforms based on that chip, for example this (the first I found on Amazon):
Moreover if a battery pack contains multiple cells in series it becomes necessary to charge the cells individually, to avoid unbalances in the charging status of the cells. This requires even more advanced chips to build a Battery Management System (BMS) circuit to be embedded in the battery pack.
As for the L298 containing an LM317 or any other kind or regulator like it, this is wrong. Here is the internal schematic of that chip, taken from its datasheet:
As you can see the chip contains two complete full H-bridges made up with BJTs and the relative control logic. The only thing that resembles a "regulator" is the block named Vref which is a low-power voltage reference used to power the internal logic circuit and set their logic thresholds (note that it is connected to the Vss pin, which is the Logic Supply Voltage according to the table at page 2).
So there is no way you can get from that chip a regulated DC output suitable to charge a single lithium cell, let alone to implement the complex algorithm needed for its safe charging.
BTW, as a side note, the L298 is an old dinosaur. It still uses BJTs to implement H-bridges instead of MOSFETs and it is hugely inefficient because of this. It's only advantage is it is ubiquitous in modules for hobby markets and that makes it dirty cheap (a marginal advantage is its moderately high limit for the motor voltage, i.e. 50V, which makes it quite robust for the price).
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H: NCP1654 current Mirror
Regarding the NCP1654, there is a circuit in the IC block diagram that I don't fully understand. Could you please take a look at the figure below and help me understand the blue and red lines?
below are my questions,
Is the blue line also referred to as the current mirror?
If both circuits are current mirrors, does the red line circuit resemble the blue line circuit?
If the red line circuit is different from the blue line circuit, could you please describe how the red line circuit is structured?
AI: Is [the circuit within] the blue line also referred to as the current mirror?
Assuming the circuit within the OP's blue lines is accurate, here is how it works.
simulate this circuit – Schematic created using CircuitLab
The voltage on the bases of the transistors may vary a little depending upon operating conditions, but the difference between Vdd and the voltage on the bases will relatively constant, say
$$Vbb = Vdd - 0.65V$$
So, the current through R1 will be approximately
$$I_{R1} = \frac{Vdd - 0.65}{R1}$$
If we assume there is no current out of the emitter of Q1, that is the CS pin is drawing no current, then all of the current through R1 will pass through the base of Q2. So, Iout will be approximately
$$I_{out0} = \beta I_{R1}$$
We will assume that the transistors are matched, and that \$\beta = \beta_{Q1} = \beta_{Q2}\$.
Now, if current is drawn out through the CS pin of the IC, (Iin in our diagram) current will be drawn through the base and collectors of Q1.
Ib(Q1) will be approximately
$$I_{b(Q1)} \approx \frac{I_{in}}{\beta}$$
This current is stolen from the base of Q2, so
$$I_{out} \approx I_{out0} - I_{in}$$
I wouldn't exactly call this a current mirror. Rather the input current is subtracted from a "quiescent" current to form the output.
If the red line circuit is different from the blue line circuit, could you please describe how the red line circuit is structured?
It probably looks something quite like this:
simulate this circuit
There may be additional resistors and transistors to improve accuracy, but that is the basic current mirror circuit. For a current mirror,
$$I_{out} \approx I_{in}$$
Note the absence of the "quiescent" current \$I_{out0}\$ found in the first circuit.
Edit:
Because the bases of Q1 and Q2 are tied together, if both transistors are conducting, their emitters will be at similar potentials within a few 10s of mV. That is, the emitter of Q1, when it is conducting, will be within a few 10s of mV from ground. From the point of view of the voltage across \$R_{cs}\$ (from the schematic in the datasheet), these few 10s of mV may not be that significant. However, when the two emitters are exactly at the same potential, given the assumption of matched transistors, then current \$I_{R1}\$ will be equally divided between the bases of Q1 and Q2. This will make the output current \$\frac{I_{out0}}{2}\$.
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H: Why am I getting clipping at the inputs and outputs?
I have designed the below circuit in LTspice. This is used to measure the voltage drop across the shunt. I know people on this platform have said I should use a current transformer, but they are not that accurate.
Simulation results:
Can someone explain to me why I am getting the clipping? The gain for the amp is 40dB.
EDIT 1
AI: Just take a look at the plot of "V(vscream)". The OpAmp's output is quite clearly saturating at its +/-5V supply voltages, which causes the differential amplifier you built from it to malfunction.
Note that, since the shunt is floating, the inputs to the difference amplifier float up to half of its output voltage due to the voltage divider chain R6-R5-R3-R4-R7. This is why you see a 2.5Vp waveform at the inputs of the OpAmp. (It's half of the 5Vp at the output.)
To fix the clipping, just lower the gain. Try 22k for R6 and R7.
Additionally, the circuit will explode dramatically if its ground is not floating with respect to the shunt. Try grounding the negative end of V4 (your simulated mains) in the simulation and you'll see what I mean. It's an instant electrical fire. The differential amplifier is also totally unnecessary, you could just as well ground one side of the shunt to simplify the circuit. It won't make a difference to the circuit's operation since you have no galvanic isolation anyway.
And last but not least, I hope you're aware that the entire circuit will be live at mains voltage.
If you need a high accuracy isolated current measurement, a sensor like this one is probably your best bet: https://www.mouser.de/datasheet/2/599/4640-X150_en-1516760.pdf (Accuracy better than 0.4%, linearity better than 0.1%, peak current >2000A)
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H: Laplace analysis of an unstable multivibrator based on an op-amp
I have tried to do a Laplace analysis of the following astable multivibrator circuit:
simulate this circuit – Schematic created using CircuitLab
I understand the principle of working. and although the component values were somewhat arbitratry, the circuit oscillates(provided i set the initial charge on the capacitor to some random, small, non-zero value, as is the case with a real circuit).
The next thing I tried to do was to do an analysis in the s-domain. I started with modeling with the following block diagram:
If we assume an input and set it to zero, I worked out out the total transfer function to be :
$$\frac{V_{out}}{V_{in}} \approx \frac{1}{-H_{1}(s) + H_{2}(s)}$$
I have simplified this assuming the open loop gain A is very large.
Now I have tried to plot the closed loop poles and zeros.
What i found is:
$$z = \frac{-1}{R_{1}C} \ \ \ \ ;\ \ p = \frac{R_3}{R_1 R_2 C}$$
both of which are REAL.
My quesetion is, how come the circuit is oscillating if the closed loop pole is real? I would expect the result of this analysis to be an exponentially growing signal until it hits the positive rail and settles.
Where did I go wrong or what am I missing? and does this have anything to do with the system having memory? How does that fit into the analysis?
Note this is not a homework or a school assignement, it is my own digging hence I can't seek help from a professor or check the solution somewhere. And upon searching the web I couldn't find someone who has done this type of analysis.
Thanks in advance.
AI: Obviously you assume an input to the summing junction and the opamp has proper plus and minus operating voltages.
Laplace analysis gave to you a pole which is real and positive. That's a perfect sign of an unstable circuit. It actually means an output which grows with no limit. But soon the output voltage meets the maximum which is set by the operating voltage and the opamp type. Your circuit is no more in the validity range of Laplace domain transfer function analysis. You clash to a wall, no way to continue with Laplace transfer functions. They are valid only to linear circuits. I must add that nonlinear circuits in some cases can be linearized for small signals around an operating point, but this is not such case, because there's no such thing as lasting operating point.
Hopefully you soon understand that this is a Schmitt-trigger which is connected to charge and discharge C1 through R1. The voltage of C1 swings between the two tresholds caused by the positive feedback. The oscillation period can be found by calculating with normal RC circuit charging equation how long it takes to change the voltage of C1 from the lower treshold to the upper treshold and back (after the Schmitt-trigged has flipped its state).
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H: Combining a mono signal with a stereo signal
I'm creating a stage sound system
I have already created a preamp for the microphone and led the connector through which I will feed the music. Now I need to mix music with a preamp. The problem is that the preamp works in mono and wants to keep the music in stereo.
I want to pass the sound from the microphone to the left and right channels. I need a diagram/advice on how to do this.
AI: This sounds like a simple summing problem, which can be solvedwith the classic opamp summing circuit. A summer is needed for each unique channel, so in a stereo configuration this needs two. The same mic preamp signal is fed to both summers, whilst the left and right channels are different for each summer. Note that the circuit schematic below expects a fairly low impedance source with the signal centred around 0V. A commercial implementation may include additional considerations like AC-coupling for inputs and outputs, protection, EMC filtering etc, but the basic idea is there.
simulate this circuit – Schematic created using CircuitLab
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H: How to measure table saw torque and horsepower?
I have a table saw that has the following rating:
120V at 60Hz
standard 5/8" arbor
I took the following measurements to see how they compared with the advertised specs. The below are the actual numbers measured.
RPM: 4,850.4
No load amp draw: 8.7A
No load voltage (taken at same time as amp draw): 114.0
This is a direct drive induction motor, so I'm assuming the efficiency is somewhere in the 95%+ range.
I can't seem to get a straight answer on other websites. Is there more information needed or can I get within a tenth or two of the actual horsepower rating with these numbers?
AI: Is there more information needed or can I get within a tenth or two of
the actual horsepower rating with these numbers?
You need to measure the supply voltage and current when the motor is on full-load and, you need to account for the power factor of the device. So, in a nutshell, you use a wattmeter and let it tell you the power input. Because you know the power output, you can calculate the efficiency but, it's likely to be significantly less than 95%.
No load figures of voltage and current tell you virtually nothing about full-load power or efficiency.
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H: Switching line between 5 V and ground using a 3.3 V signal
I am working with a PCB which looks like shown below. Switching the central line between 5 V and ground toggles the LEDs.
I had this PCB connected to a 5 V Arduino dev board where the switch line was connected to one of the GPIO pins; switching between high and low on that pin toggles the LEDs.
I have a requirement to get this working on a 3.3 V board so I need to amplify the 3.3 V GPIO pin to 5 V. I thought I could use a level shifter, I tried a TXB0104 with the 3 V signal connected to LV1 and the switch line connected to HV1 but when the pin is set to high, I only get ~3 V on the 5 V side.
Googling suggests I can achieve this using a MOSFET, but I'm very much a beginner and somewhat at a loss. What would be a simple solution to this?
Edit:
Thanks for the answers so far. I should have been clearer in my original post, the PCB in my example is an existing board which is part of a computer case IO and RGB controller. My circuit example is a smaller part of that board and the rest of the board requires 5V to operate correctly. I tried to find a schematic for the board (GYPCB-22105A-6) but couldn't find anything, I'm guessing its a proprietary board made specifically for the case. Added a picture for context.
AI: The hard way:
A single transistor can only pull that "central" node down to 0V, or pull up to +5V, not both. That's why a single transistor level translator can't work here. You will require a setup that can pull in both directions, which requires two transistors in a push-pull configuration:
simulate this circuit – Schematic created using CircuitLab
I'm sure you can see a potential problem here: if Q1 and Q2 are on simultaneously, this would be a direct short circuit between +5V and ground, and a lot of current will flow. Something will break unless you take great care to ensure that inputs A and B are never in a state where this condition to occur.
You could limit this so-called "shoot-through" current with resistors, further complicating the arrangement. Or you could build circuitry to control A and B independently, introducing a small delay between switching one transistor off and switching the other on. Also complicated.
Or, the easy way:
You require a digital gate that has a push-pull output stage, takes an input potential for which +3.3V is considered "high", and 0V is "low", and outputs either +5V or 0V in response. That's exactly what the 74HCT (note the "T", that's the important bit) range of logic devices do.
They have push-pull output stages, with all the problems I mentioned above already taken care of, and will translate from 3.3V logic levels to 5V. No resistors needed, no timing to take care of, no special power supply requirements.
They are available in single gate packages, such as the 74HCT1G08:
simulate this circuit
You could use any gate, from any 74HCT package, such as multiple-gate devices 74HCT08, 74HCT00, 74HCT04 etc.
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H: High power DC to AC inverters
I've looked around and found quite a few DC to AC inverter circuits; 12-24 V DC input and 120-240 V AC output.
None of them can support more than 400 W though, and they all use at least one big transformer. How do commercial inverters output enough power to drive up to 3500 W and still fit a compact chassis?
AI: The DC-AC inverters with schematics usually use a laminated iron transformer with a low voltage winding connected to a 50 or 60 Hz square wave circuit, and the output is from the 120 or 240 VAC winding. Because the transformer operates at such low frequency, it must be large and heavy. The advantage of such designs is their simplicity and low cost, especially if one uses a very common 12 V or 24 V center tapped transformer.
The compact automotive inverters rectify the 12 or 24 VDC input to get a nominal 15-30 VDC power bus, and a high frequency (20-50 KHz) switching circuit that uses a much smaller ferrite core step-up transformer, rectifiers, and capacitor, which produces a nominal 135 or 270 VDC bus. This is used with an H-bridge to get a "modified sine wave", consisting of rectangular pulses with an RMS value equivalent to 120 or 240 VAC mains. Waveform looks like this:
simulate this circuit – Schematic created using CircuitLab
The pure sine wave inverters use variable duty cycle PWM that produces the equivalent of a sine wave. This same principle is used for industrial 3 phase variable frequency drives (VFDs), mostly to drive induction motors, in a range from about 1/2 HP (375 watts), to 50 HP (37 kW) or more. VFDs usually are designed to use 240 or 480 V three phase, but some will also work on single phase.
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H: LT1389-5 voltage reference output is not as expected
I am using the LT1389-5 for one of my projects. My circuit is given below.
For 5 V output the maximum operating current is 10 mA. This is obtained from the maximum ratings.
I calculated the value of R1 based on a total current of 15 mA.
R1 = (12-5)/15 mA = 466 Ω.
When I simulated the circuit, I am getting an output voltage of 7.3 V.
Where did I go wrong?
My input varies from 8V to 14V and I need 5V at the output. I swept the Vin from 8V to 14V. What I can see is output is not a constant 5V.
Please see the waveform below.
AI: The 10mA is an absolute maximum limit and you should be operating nowhere near there. Proper operation is not implied or guaranteed.
The characteristics are only guaranteed up to 2mA for the 5V device. This is a nanopower part and not intended to sink large amounts of current, so not appropriate for a circuit such as yours. From the datasheet you linked:
If you do not require the high accuracy, fairly low drift (and low minimum operating current) of the rather excellent (at low currents) LT1389-5, a common TL431 and two resistors will function provided you give it a minimum of 1mA. It will sink 10mA or 15mA easily.
Here is the comparative behavior but with the currents in your circuit reduced by 10:1 (over an input range of 6 to 14V)
Now, include the trace for your circuit values:
According to the LTspice model it typically begins to lose regulation (with a typical sample, and at room temperature) at around 2.75mA.
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H: I'm trying to make a Zeta converter
I tried to design Zeta converter to be used in an MPPT charge controller.
VIN: 10-22 V
IIN: 3 A
Fs: 30 kHz
I have a problem.
With my design, the voltage is not coming out so well and nothing changes if I change the duty cycle (in real, not simulation, I have made a prototype.)
I tried simulating in software with Multisim 14.3 and it works. I found out that if I send PWM to the gate with high voltage is 23 V and a low voltage is -23 V, it will work like Zeta converter.
Is it possible to do that?
Here is a link to the simulation video:
Link to the video
Edited:
I have tried with isolated supply, but this was happend
Link to video
So, when i turn on my supply for the converter, the supply voltage become not stable as you can see in the video also 0 Vout from converter
AI: Please read the note I added to one of your pictures: -
With my design, the voltage is not coming out so well and nothing
changes if I change the duty cycle
Given Q1's source (output) is shorted to ground, that's all you can expect. U1 needs to run from a floating supply like from an isolated DC-to-DC converter.
Edited: I have tried with isolated supply, but this was happend
That won't work. In effect you are shorting the green node to the positive terminal of battery B2 and, you are shorting the orange node to +23 volts.
Just use a regular 0 volt / ground symbol connected to the negative terminal of B1 and ditch the 0 volt / ground symbol on the negative end of B2
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H: ATMega32U4 USB design considerations
I'm desigining a board with ATMega32U4 microcontroller.
The board will be minimal, and will feed the microcontroller from USB of an M.2 socket (E type) on a PC mainboard:
Now, checking Leonardo's schematic, they are using varistors to protect USB's D+ and D- pins:
This is perfectly understanable, as Leonardo can be plugged into any computer's USB port.
But in my case, this AVR will be powered from an internal M.2 socket soldered onto the PC's mainboard.
My assumption is that I can leave out these varistors, as when voltage on D+ and D- pins are above the varistors' limits (20V), my biggest problem probably will not be this AVR, but the whole computer.
Can you verify this assumption? Can I skip these varistors?
AI: It is likely that the TVS diodes can be omitted.
If you want, you could draw them in and choose at manufacturing stage to mount them or not.
But then the question is, if you need them because the board will be handled in an ESD environment, would all IO need protection. If you don't add protection to other pins, there is little reason to add protection to USB either.
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H: What are the possible implementations of LUT on silicon?
I'm looking for the possible ways to implement a LUT. The only way I know is to use Flip Flops to store the outputs and a MUX to select the output using the input as a select signal. Is there any other way to implement it?
AI: One alternative method to make a Look-Up Table is to use a parallel EEPROM chip. The address bus are your inputs, and the data bus are your outputs. The contents of the EEPROM are your logic output for the given "address" inputs. Some supporting circuitry would be required to get the method to work, such as clocking.
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H: What does this diagram with two opposing arrows depict?
I have an astronomical timer relay that controls lights. Its user manual shows this diagram:
What do the opposing fat arrows (vertically aligned) indicate? How would one read them? Also, it seems like there are three switches to the far right (within the load being controlled I presume). What do they signify?
While they may be good for professionals, for an end-user, such diagrams are somewhat meaningless, I feel.
PS: When I asked the manufacturer why output #1 was not used, they told me to ignore it, that it was 'normally open' and that they put it in because some customers wanted that option. How do those customers use the product?
AI: Also, it seems like there are three switches to the far right (within the load being controlled I presume.) What do they signify?
The small relay shown on the right side of the image - note the dark side is going to LINE and light side is going to NEUTRAL, to indicate polarity. Typically, this would be a three-phase contactor. When this timer activates, this contactor is switched on, supplying three-phase power to the designated load. It is small and nondescript because they are speculating about what you actually will have wired here.
What do the opposing fat arrows (vertically aligned) indicate?
The dark arrow on the A1-A2 side of the contact is indicating that it is the source of the action; the source of the magnetic field, pulling on the contact it points to.
The light arrow on the 1-2-3 contact indicates it is the target of the magnetic field. Normally 1-2 is connected, and when it is pulled towards the coil, 2-3 connect.
It looks like there is a C1 and C2 set of outputs. So could switch two independent contactors (say, one for 480VAC, and another for 240VAC power, simultaneously.)
When I asked the manufacturer why output #1 was not used, they told me to ignore it, that it was 'normally open' and that they put it in because some customers wanted that option. How do those customers use the product?
There are many possibilities. For a darkroom, consider if two contactors were connected to terminal 1 (timer off-state) and terminal 3 (timer on-state.) When the timer was off, regular room lighting was active. When the timer was activated, the regular room lights shut off, and instead a very low-power red light is activated, to not interfere with developing the photos. After a few hours (film is developed) regular lights come back on automatically.
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H: Need a way to decrease the current used by a stepper motor through a TMC2209 when it is idle
I am using an ESP8266 to control a stepper motor through TMC2209. In my use-case, the motor is idle 80% of the time. But i can't turn off the enable pin since i need the motor to still be fixed in its position. Is there a way to just decrease the current the motor is drawing while its idle?
AI: Look at page 50 and 51 of the DATASHEET.
The setting you are looking for is "IHOLD".
It can take values from 0 to 31. 31 being full current. You will have to test in your application for the minimum holding current that will work for you.
There is also an "automatic standstill current reduction" via pin 14.
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H: Is the emitter-base diode forward biased when an NPN transistor is used as an amplifier?
I came across a question asking about the state of both the emitter-base \$EB\$ and collector-base \$CB\$ diodes when an NPN transistor is used in amplification.
My understanding is that for amplification to happen, the \$EB\$ diode must be forward biased and the \$CB\$ must be reverse biased to cause the desired amplification, butI saw the question online on two separate platforms, with the complete opposite answer: the \$EB\$ is reverse biased and the \$CE\$ is forward biased. It got me very confused.
What is the correct configuration of diodes for the transistor to work as an amplifier, and what are the reasons behind it?
AI: When a BJT is used as an amplifier element, the emitter-base diode is forward biased. Because we are discussing an amplifier not a switch, we will assume the transistor does not go into saturation. With this assumption in place, the base collector junction is reverse biased. (Note, however, that not all BJT amplifiers avoid transistor saturation.)
Contrary to a comment, it makes no difference whether you call the diode consisting of emitter and base the emitter-base diode or base-emitter diode. Forward bias means the p-doped region is more positive than the n-doped region. How you refer to the diode doesn't change that.
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H: Tesla coil music
I want my solid state Tesla coil to play music. I built it to only accept square wave input. Does anyone know howI take a normal melody (no voice,) only keep the main soundtrack (no bass or anything else) and convert it into pure and simple square wave?
AI: The task you are after is easier to approach from the other end:
Get some sheet music. What you need is a single voice melody. An example.
1.1 A MIDI file of the song, if available, may save you a lot of manual work.
Convert pitches into frequencies. C (the note starting the example song) is 261 Hz, any half tone up is up by 12-th root of 2
Generate the square waves for each note by whatever means available (e.g. Arduino) and feed it into your Tesla coil setup. Take care to deal with different note durations. You may want to create 5% or 10% silence at the end of each note in order to distinguish the beat when some note repeat.
p.s. Also take care not to burn anything, yourself included.
p.s.2 You can get a lot of inspiration from what 1980s computers and game consoles did (see Retrocomputing.SE, a lot of 1980s hardware had only square waves available).
This is the same approach in modern hardware made for completely different purpose.
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H: Amplification of the oscillation of a signal without amplifying the offset
Knowing that I only have op-amps, comparators, resistors, capacitors, and simple diodes at my disposal, is there a simple way to amplify the small oscillation of such a signal without amplifying the mean of the oscillation? (I would like the curve that the oscillation follows to remain the same)
AI: It sounds like you are looking for a high pass filter, but more crucially, one that has a DC gain of unity to retain the input DC offset at the output.
A standard non inverting amplifier with an AC capacitor can achieve this with minimal parts. Resistor values can be tweaked to achieve the desired gain of the oscillation (passband signal) using the standard non inverting opamp equations. Gain at DC is always unity. The optimum capacitor value will depend on how quickly you want the circuit to be able to respond to the DC input (but ideally transitioned to acting as a short circuit by the oscillation frequency).
simulate this circuit – Schematic created using CircuitLab
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H: Is debouncing necessary for a power switch?
A few months ago I asked for help designing a circuit for powering on a microcontroller using a tact switch, and I finally just prototyped the circuit that @Jonathan-S. suggested. It works great. However, I neglected to consider any effects of contact bounce in the tact switch. I'm not seeing any ill effects, but I'm wondering if bouncing could cause glitching and I wonder if some sort of hardware debounce is necessary? If so, could someone suggest a simple circuit? My current schematic is below. "Boost EN" connects to a microcontroller output that is driven high out powerup to keep the boost converter operating, and "SW3" connect to an input on the uC.
AI: Short answer is maybe.
Longer answer, well it depends on everything else is your circuit. What frequency does the switch bounce at and how fast does everything else turn on/off, charge and discharge? What happens to the system if it gets rapidly power cycled a number of times? (assuming the bounce propogates through the power train fully)
How to deal with this varies, but a simple option is to pop a 200nF capacitor in parrallel with R5. When the switch is closed it will still rise quickly, but it will take 10ms for the capacitor to discharge when the switch is open. This 10ms is more than likely long enough for any bouncing to stop. This sort of simple capacitor debouncing is pretty common for switches, becuase they're human actuated there's rarely the need for them to be very fast, after all no real input to the switch is going to be 100Hz is it?
You can tweak the capacitor to change the time if you need something else from it.
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H: Op-amp high-pass filter and low open-loop gain at higher frequencies
How can a high-pass filter work when the open-loop gain of an op-amp completely attenuates from a certain frequency?
I understand that the open-loop gain of an op-amp is what limits every closed-loop gain. So if a high-pass filter is a closed-loop gain, how does a high-pass filter still work (at high frequencies)?
AI: Very true! All op-amp high pass filters are stopped by the open loop gain curve. They are actually band pass filters.
In actual applications, the "high-pass" bandwidth is does not need to be unlimited. In fact restricting the higher frequencies reduces noise and so is desireable.
So the trick is to trade gain for bandwidth. The gain-bandwidth product GBW is reported in op-amp datasheets.
How can a HPF work
The HP cutoff is the most important. Then you must choose the amplifier and closed loop gain to deliver the important frequencies in the application.
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H: How do reduce switching randomness from comparator without comprimising switching speed?
I'm working on a coil gun project and I've discovered an annoying problem involving a voltage comparator output which has lots of noise/ rapidly switching high and low before coming stable. Here's the circuit:
D4 projects light to R3 which gets disrupted when the projectile comes between them. Here's what I captured on the oscilloscope on the output pin of the comparator when doing a test shot.
And this causes my IGBT driving the coil to switch on and off rapidly when the current through the coil is highest which is scary. I used to have a 1uF bypass capacitor at the output of the comparator. But pair that with the 1k ohm pull up resistor and you see that the rise time is very slow.
So how can I elimate this noise without comprimising switching speed. I was thinking of something that triggers and stays on when the first high is detected and then stays on after that which would eliminate all the noise that would've procedded after the first high.
EDIT:
Using TI's hysteresis schematic recommended by Chris Knudsen I got this on the oscilloscope:
Looks great! The rise time is a little slow but it goes into an IGBT driver so it should be fine.
AI: Add positive feedback. eg, add a resistor from the output to the non-inverting input.
with about 5K on the input, about 100k of feedback is probably a good starting point. but try higher and lower also.
But first check that you have all the power supply bypass capacitors that the datasheets recommend installed.
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H: Why is the output of this class AB amplifier not equal to Vsine?
I'm simulating a class AB power amplifier.
According to the theory that I learned, the voltage at C8(2) should be equal to C10(1.) Why is there a huge gap between them (5.83 vs 1.89?)
The input impedance of this circuit is an approximation with R10 = R11. Is that correct?
AI: I see Q9's Vbe is reverse biased, the emitter is at a higher voltage than the base. It won't work.
You have to put some effort to bias the bases. I have no idea what your VCC value is, but the fact that D1 is reversed biased as well means this isn't properly biased. Perhaps you're not allowing enough current to flow through the diodes?
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H: Boost converter: using smaller inductance than "typical" application?
I need to boost 3.3V all the way up to 12.0V.
Current requirements are rather small, I only need to power an SSD1309 OLED driver (from pg7):
Common maximum sink current: 40mA
Almost all of the available high-quality boost converters are providing way more current than this, so I decided to use the smallest converter I can get: MP3438:
The MP3438 is a highly integrated boost
converter with a 1.2MHz fixed frequency and a
wide input voltage (VIN) range. The MP3438
starts up from a VIN as low as 2.7V, and can
support up to a 2A switching current limit with
integrated, low RDS(ON) power MOSFETs.
This is their recommended typical application converting 3.3V to 12V:
There is a section on pg16 "Selecting the Inductor":
An inductor is required to transfer the energy
between the input source and the output
capacitors. A larger-value inductor results in
less ripple current and a lower peak inductor
current, which reduces the stress on the power
MOSFET. However, a larger-value inductor is
physically larger, has a higher series resistance,
and has a lower saturation current.
For most designs, the inductance can be
estimated with Equation (6):
L = Vin*(Vout-Vin)/(Fsw*Vout*dIl)
Where dIl is the inductor ripple current.
Choose the inductor ripple current to be
approximately 20% to 50% of the maximum
inductor average current.
Question: what is "the maximum inductor average current"? Is it the 40mA? Or RMS Current (Irms) which is 4.4A for the recommended inductor?
Calculating the above formula with the recommended 3.3uH inductor:
dIL = Vin*(Vout-Vin)/(Fsw*Vout*L)
dIL = 3.3*(12-3.3)/(1200000*12*3.3/1000000)
dIL = 0.60417
This means ripple is 604mA?
AI: Question: what is "the maximum inductor average current"?
It is the average inductor current when the current loading on the 12 volt output is greatest. Maybe the boost calculator from my basic website might help a tad: -
I've set the load resistance to 300 Ω to match the 40 mA load current stated in the question.
So, it's running in DCM (discontinuous conduction mode) and, the average inductor current is 145 mA as expected for an ideal circuit. The calculator tells you that the ripple current is 419 mA p-p. The reason why the ripple current value disagrees with the data sheet guidance is because the data sheet assumed the chip would be used in CCM mode.
There's always a more ripply current in DCM because of the inductor current depleting to zero.
The calculator is for an ideal circuit; there will be switching losses, diode volt drops and inductor resistance losses.
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H: Filter phase shift and causality
A filter I have is showing to have a positive phase shift of ~30° at 1 kHz:
Also, it seems that the output signal is actually advanced by 30°.
But we all know that this is impossible because of causality. So what's really happening here, and how much degrees of phase shift should I consider?
AI: But we all know that this is impossible because of causality.
If I had a simple high-pass filter like this: -
I can do a spectral plot and see this: -
And, that spectral plot tells me that the output at 1 kHz is leading the input by about 30°. Yet, if I do a transient response for a newly applied sinewave of amplitude 0.5 volts p-p, I see this: -
The output doesn't begin before the input but, after a cycle it does end-up leading the input by 30°. However, causality isn't broken.
So what's really happening here, and how much degrees of phase shift should I consider?
It settles down to leading by approximately 30° but, in the wider scheme of things and, what you are trying to ultimately achieve, I can't answer because I don't know anything about these things.
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H: Total impedance in a circuit
To determine the current I have to calculate the total impedance, here named \$Z_{Ges}\$, in the circuit which can be seen in the first picture.
First I summed \$R_1 \$, \$C \$ and \$R_2 \$ as a parallel impedance \$Z_{1C2} = (Z_{R_1} || Z_C) || Z_{R_2} = (\frac{R_1 * \frac{1}{j\omega C}}{R_1 + \frac{1}{j \omega C}}) || R_2 = (\frac{R_1}{1+j \omega R_1 C})||R_2 = \frac{\frac{R_1}{1+j \omega R_1 C}R_2}{\frac{R_1}{1+j \omega R_1 C}+R_2} = ... = \frac{R_1^2 R_2 + R_1 R_2^2}{(R_1 + R_2)^2 + \omega^2 R_1^2 R_2^2 C^2} - j\frac{\omega R_1^2 R_2^2 C}{(R_1 + R_2)^2 + \omega^2 R_1^2 R_2^2 C^2}\$.
This leads to the simplified circuit with only \$Z_{1C2}\$, \$Z_{3}\$ and \$Z_{L}\$. Then I add this in a series and get
\$Z_{Ges} = Z_{1C2} + Z_{3} + Z_{L} = \frac{R_1^2 R_2 + R_1 R_2^2}{(R_1 + R_2)^2 + \omega^2 R_1^2 R_2^2 C^2} - j\frac{\omega R_1^2 R_2^2 C}{(R_1 + R_2)^2 + \omega^2 R_1^2 R_2^2 C^2} + R_3 + j\omega L = (\frac{R_1^2 R_2 + R_1 R_2^2}{(R_1 + R_2)^2 + \omega^2 R_1^2 R_2^2 C^2} + R_3)+ j(\omega L - \frac{\omega R_1^2 R_2^2 C}{(R_1 + R_2)^2 + \omega^2 R_1^2 R_2^2 C^2})\$.
After inserting the respective values I get \$ Z_{ges} = 0,6 * (3+j) [\Omega]\$
But when I want to write the calculated impedance in polar form (see picture 2) I get a somehow "strange" result in the exponent, namely \$ e^{j\frac{\pi}{540}} \$. I get this as follows:
\$ 3 + j = \sqrt{10}(\cos{x} + j\sin{x}) \$ and \$ x \$ evaluates to \$ \frac{1}{3} \$. Converting this to radians I get \$ \frac{\pi}{540} \$
Are the steps, particularly where I calculated the parallel impedance \$Z_{12C}\$, correct?
AI: Well, notice that the input impedance of your circuit is given by:
\begin{equation}
\begin{split}
\underline{\text{Z}}_{\space\text{i}}\left(\omega\right)&=\underline{\text{Z}}_{\space\text{R}_1}+\left[\left(\underline{\text{Z}}_{\space\text{C}}\space\text{||}\space\underline{\text{Z}}_{\space\text{R}_2}\right)\space\text{||}\space\left(\underline{\text{Z}}_{\space\text{R}_3}+\underline{\text{Z}}_{\space\text{L}}\right)\right]\\
\\
&=\text{R}_1+\frac{\displaystyle1}{\displaystyle\frac{\displaystyle1}{\displaystyle\frac{\displaystyle1}{\displaystyle\text{j}\omega\text{C}}}+\frac{\displaystyle1}{\displaystyle\text{R}_2}+\frac{\displaystyle1}{\displaystyle\text{R}_3+\text{j}\omega\text{L}}}\\
\\
&=\text{R}_1+\frac{\displaystyle1}{\displaystyle\text{j}\omega\text{C}+\frac{\displaystyle1}{\displaystyle\text{R}_2}+\frac{\displaystyle1}{\displaystyle\text{R}_3+\text{j}\omega\text{L}}}\\
\\
&=\text{R}_1+\frac{\displaystyle1}{\displaystyle\text{j}\omega\text{C}+\frac{\displaystyle1}{\displaystyle\text{R}_2}+\frac{\displaystyle1}{\displaystyle\text{R}_3+\text{j}\omega\text{L}}}\cdot\frac{\displaystyle\text{R}_3+\text{j}\omega\text{L}}{\displaystyle\text{R}_3+\text{j}\omega\text{L}}\\
\\
&=\text{R}_1+\frac{\displaystyle\text{R}_3+\text{j}\omega\text{L}}{\displaystyle\text{j}\omega\text{C}\left(\text{R}_3+\text{j}\omega\text{L}\right)+\frac{\displaystyle\text{R}_3+\text{j}\omega\text{L}}{\displaystyle\text{R}_2}+\frac{\displaystyle\text{R}_3+\text{j}\omega\text{L}}{\displaystyle\text{R}_3+\text{j}\omega\text{L}}}\\
\\
&=\text{R}_1+\frac{\displaystyle\text{R}_3+\text{j}\omega\text{L}}{\displaystyle\text{j}\omega\text{C}\left(\text{R}_3+\text{j}\omega\text{L}\right)+\frac{\displaystyle\text{R}_3+\text{j}\omega\text{L}}{\displaystyle\text{R}_2}+1}\\
\\
&=\text{R}_1+\frac{\displaystyle\text{R}_3+\text{j}\omega\text{L}}{\displaystyle\text{j}\omega\text{C}\left(\text{R}_3+\text{j}\omega\text{L}\right)+\frac{\displaystyle\text{R}_3+\text{j}\omega\text{L}}{\displaystyle\text{R}_2}+1}\cdot\frac{\displaystyle\text{R}_2}{\displaystyle\text{R}_2}\\
\\
&=\text{R}_1+\frac{\displaystyle\text{R}_2\left(\text{R}_3+\text{j}\omega\text{L}\right)}{\displaystyle\text{j}\omega\text{CR}_2\left(\text{R}_3+\text{j}\omega\text{L}\right)+\frac{\displaystyle\text{R}_2\left(\text{R}_3+\text{j}\omega\text{L}\right)}{\displaystyle\text{R}_2}+\text{R}_2}\\
\\
&=\text{R}_1+\frac{\displaystyle\text{R}_2\left(\text{R}_3+\text{j}\omega\text{L}\right)}{\displaystyle\text{j}\omega\text{CR}_2\left(\text{R}_3+\text{j}\omega\text{L}\right)+\text{R}_3+\text{j}\omega\text{L}+\text{R}_2}\\
\\
&=\text{R}_1+\frac{\displaystyle\text{R}_2\left(\text{R}_3+\text{j}\omega\text{L}\right)}{\displaystyle\text{R}_2+\text{R}_3+\text{j}\omega\text{CR}_2\text{R}_3+\text{j}\omega\text{CR}_2\text{j}\omega\text{L}+\text{j}\omega\text{L}}\\
\\
&=\text{R}_1+\frac{\displaystyle\text{R}_2\left(\text{R}_3+\text{j}\omega\text{L}\right)}{\displaystyle\text{R}_2+\text{R}_3-\text{CLR}_2\omega^2+\omega\left(\text{CR}_2\text{R}_3+\text{L}\right)\text{j}}\\
\\
&=\text{R}_1+\frac{\displaystyle\text{R}_2\left(\text{R}_3+\text{j}\omega\text{L}\right)}{\displaystyle\text{R}_2+\text{R}_3-\text{CLR}_2\omega^2+\omega\left(\text{CR}_2\text{R}_3+\text{L}\right)\text{j}}\cdot\frac{\displaystyle\text{R}_2+\text{R}_3-\text{CLR}_2\omega^2-\omega\left(\text{CR}_2\text{R}_3+\text{L}\right)\text{j}}{\displaystyle\text{R}_2+\text{R}_3-\text{CLR}_2\omega^2-\omega\left(\text{CR}_2\text{R}_3+\text{L}\right)\text{j}}\\
\\
&=\text{R}_1+\frac{\displaystyle\text{R}_2\left(\text{R}_3+\text{j}\omega\text{L}\right)\left(\text{R}_2+\text{R}_3-\text{CLR}_2\omega^2-\omega\left(\text{CR}_2\text{R}_3+\text{L}\right)\text{j}\right)}{\displaystyle\left(\text{R}_2+\text{R}_3-\text{CLR}_2\omega^2\right)^2+\left(\omega\left(\text{CR}_2\text{R}_3+\text{L}\right)\right)^2}
\end{split}\tag1
\end{equation}
Where \$\alpha\space\text{||}\space\beta:=\frac{\displaystyle\alpha\beta}{\displaystyle\alpha+\beta}\$.
Using your values, I found:
$$\underline{\text{Z}}_{\space\text{i}}\left(1\right)=3\space\Omega\tag2$$
So, we see that: \$\displaystyle\Im\left(\underline{\text{Z}}_{\space\text{i}}\left(1\right)\right)=0\space\Omega\$.
EDIT, the voltage across the inductor is given by:
$$\text{V}_\text{L}\left(t\right)=\hat{\text{u}}\cos\left(t+\varphi\right)\tag3$$
Where:
$$\hat{\text{u}}=\left|\text{j}\omega\text{L}\cdot\underbrace{\frac{\displaystyle\hat{\text{u}}_\text{i}\exp\left(\varphi_\text{i}\right)}{\displaystyle\underline{\text{Z}}_{\space\text{i}}\left(\omega\right)}\cdot\underbrace{\frac{\displaystyle\text{R}_2\space\text{||}\space\frac{1}{\text{j}\omega\text{C}}}{\displaystyle\text{R}_3+\text{j}\omega\text{L}+\left(\text{R}_2\space\text{||}\space\frac{1}{\text{j}\omega\text{C}}\right)}}_{=\space\text{current divider}}}_{=\space\text{current through inductor}}\right|\tag4$$
$$\varphi=\arg\left(\text{j}\omega\text{L}\cdot\frac{\displaystyle\hat{\text{u}}_\text{i}\exp\left(\varphi_\text{i}\right)}{\displaystyle\underline{\text{Z}}_{\space\text{i}}\left(\omega\right)}\cdot\frac{\displaystyle\text{R}_2\space\text{||}\space\frac{1}{\text{j}\omega\text{C}}}{\displaystyle\text{R}_3+\text{j}\omega\text{L}+\left(\text{R}_2\space\text{||}\space\frac{1}{\text{j}\omega\text{C}}\right)}\right)\tag5$$
Using your values, we find: trough
$$\hat{\text{u}}=\frac{4 \sqrt{2}}{3}\approx1.88562\space\text{V}\tag6$$
$$\varphi=\frac{\pi}{2}\tag7$$
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H: Change in switching frequency across gate source
I am working on a bidirectional half bridge DC-DC converter. The converter circuit is shown below.
I used a TLP250 IC for the driver circuit. A square wave with 20 kHz switching frequency was given as input to the driver circuit. The output from TLP250 is a square wave with 20 kHz switching frequency and 10 V peak to peak.
When I am applying this pulse across the MOSFET (IRF150) in the bidirectional DC-DC converter, the switching frequency of the pulse becomes more than 80 kHz. What might be the reason for this?
Edit:
The driver circuit is shown below
The output pulse from the TLP250(from pin 6)(before connecting the MOSFET) is
The pulse across gate source of the MOSFET is
AI: It looks like both signals have the same frequency, based on the images you added from your oscilloscope.
Both measurements have a scale of 10us/div and the period of both square waves is approximately 50us which corresponds to 20kHz
Perhaps the automatic measurement is set wrong and you obtained an erroneous measure.
|
H: Crystal oscillator construction
I am not sure about how the crystal oscillators are made. Some say it has a crystal but some says it has an LC combination which requires a parallel capacitor to resonate with the internal LC combination.What is the actual construction.
AI: A crystal oscillator has two things : the oscillator circuitry meant to be connected to a crystal, and the crystal itself.
The crystal is a suitably cut and polished piece of quartz crystal.
There are no LC circuits in it, but it can be modeled as such.
Crystals do need load capacitors of correct value to make the crystal oscilator to oscillate at the correct rate.
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H: How can I solve these two equations to determine resonant capacitors for a wireless charging coil?
My questions:
What are S, D, and the apostrophe above Inductance?
Is the equation looking for the inductance of the coil or the circuit?
Once I know what S and D stand for how can I determine their frequencies?
The following is an excerpt from the datasheet for Texas Instruments bq51221 Single Chip Wireless Power Receiver.
10.2.1.2.9 Series and Parallel Resonant Capacitors
Resonant capacitors C1 and C2 are set according to WPC specification. Although this is a dual mode solution, the PMA does not specify an exact resonance frequency for the resonant capacitors and in fact does not specify that resonant capacitors are indeed needed.
The equations for calculating the values of the resonant capacitors are shown:
AI: If you look at the main circuit on page 1 of the data sheet they show C1 and C2 in series: -
However, they forgot to indicate what \$L_S\$ is so, it's somewhat of a guess on my part. Firstly however, we have to think of pins AC1 and AC2 as current sources in opposition i.e. one is the inversion of the other.
This then permits us to be able to say that C1 and C2 are truly in series and, excitation from the AC pins to C2 is in the form of a current and, that current doesn't screw around with the impedances and formulas.
The resonant frequency of a parallel inductor and capacitor is this: -
$$F_R = \dfrac{1}{2\pi\sqrt{LC}}$$
And, it appears that C1 is the dominant reactance i.e. the highest reactance compared to C2 and, I suspect that this means you can rearrange the above formula to find C1: -
$$C_1 = \left(\dfrac{1}{2\pi F_R\sqrt{L}}\right)^2$$
Hopefully you can see that it is equivalent to your first formula (apart from the inductor being called \$L'_S\$). I think they are calling it \$L'_S\$ to fudge the math to make it work. So, I would call \$L'_S\$ the equivalent inductance that makes the circuit resonate at the correct frequency if we ignored C2.
Again, it seems an incompetent way of doing it but, TI no doubt have their reasons.
Then, for the 2nd formula TI are doing the right thing and solving my first formula where C is replaced with: -
$$C = \dfrac{1}{\frac{1}{C_1}+\frac{1}{C_2}}$$
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H: Placing feedback loop parts on PCB
I have one PCB for control circuitry and another for power parts (input caps, transformer, full bridge, output caps...).
I would like to ask if I can place some feedback parts (red square at picture) directly on "power board". Why I wanna do that? Since 10k resistor provides DC offset and there are 200V on the output and I don't want to use cables with higher dielectric insulation. Is that ok?
AI: Consider the effect of stray capacitance to the feedback (summing) node.
200V is hardly a burden (what, normal hookup wire is rated 300V?), and introducing noise to the summing node is probably a bad idea. The resistors could be divided up, but with the lead-lag network on there too, that's awkward.
(Is this for voltage or current mode? If you're changing to current mode, you should find the lead-lag network isn't necessary anymore.)
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H: Verilog - Unexpected behaviour on first clock cycle
I've done a bit of experimenting with Verilog recently, and I ran into a problem where it doesn't behave as I'd expect. In one of my modules, I have code like the following that is designed to simply track odd/even cycles, because I'm performing operations that take 2 cycles each:
reg even_cycle = 0;
always@(posedge clk)
begin
even_cycle <= ~even_cycle;
if(even_cycle)
//do something
end
The expected behaviour: On the first clock cycle, even_cycle is flipped, which, due to it being a register should see it continue to show zero until the next cycle, where its new value of 1 will be clocked.
What really happens: On the positive edge of the first clock cycle, even_cycle is already set to 1
I'm sure I'm missing something obvious, but could anyone please explain this behaviour? It seems to go against my understanding of registers. How can a reg's value appear to be updated on the same cycle it's assigned?
As a bonus question, if I have a clock signal that I want to pass to a module conditionally, is the following a bad way of doing it? If so, is there a recommended way?
input clk_in; //always running
wire cond_clk;
assign cond_clk = some_condition ? clk_in : 0
When run in the simulator and I stop the clock (i.e the condition becomes false), cond_clk shows as a vertical line in the simulator, as if it's high for a tiny period at the beginning of the cycle.
AI: The simulation behaves as it should. At the positive edge of clk, the nonblocking assignment is executed, updating the even_cycle signal with its new value, which is always the inverse of its previous value.
At time 0, you set even_cycle to 0 in the reg declaration line. It stays at 0 until the 1st positive edge of clk. At that time, even_cycle becomes 1.
Consider this simple code:
module tb;
reg clk = 0;
always #5 clk++;
reg even_cycle = 0;
always @(posedge clk)
begin
even_cycle <= ~even_cycle;
end
initial #500 $finish;
endmodule
Assuming clk is 0 at time 0 and goes to 1 at time 5, even_cycle goes high at time 5 as well. It then remains at 1 until the 2nd positive edge of clk at time 15. This code models a positive-edge triggered flip flop.
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H: What do the letters mean on this LiPo (or Li Ion) battery?
I’m trying to find a replacement battery for my Bluetooth earphone as they drain out very fast. It is a 3.7 V 55 mAh.
Looking through the options I see batteries with better capacity but the letters are different (the battery I have says AUN others have written PZY TX DX, etc.) what do these letters mean, and do I need to care about these?
AI: Some are probably date and lot codes. And maybe a hint as to the manufacturer or model.
It's really impossible to tell for sure without a specification (or a datasheet, but they are more rare in this space) from the manufacturer themselves. There isn't a standardized series or anything like that. And manufacturers may not choose to display their specifications in public, more like confidential info for their huge-quantity OEM buyers.
Aside from the voltage and rough mAh claim, you should probably concern yourself mainly with the physical size, whether the battery incorporates protection (and what kind) and maybe the connector and lead lengths.
If the supplier is on the dodgy side (and for replacement LiPo batteries they often are) the capacity (and other) claims may be exaggerated (or wildly exaugurated) so do your due diligence.
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H: MCP2515 and Crystal Error
I'm making a board with MCP2515T-I/ML due to space constraints and it won't start up.
(datasheet) https://ww1.microchip.com/downloads/en/DeviceDoc/MCP2515-Stand-Alone-CAN-Controller-with-SPI-20001801J.pdf
This is the pcb layout and schematic.
The top layer copper pour is 3.3V and the second layer is a solid ground plane.
I have checked for shorts, there are no shorts. I have checked the MISO, MOSI, CLK and CS lines and they all behave appropriately excluding MISO. It seems not only does the MCP2515 not want to turn on but the 8MHz external clock is not oscillating. I checked using a tiny SA and a H field probe (which correctly detects oscillations of other crystals).
I have conducted both manual hardware reset and SPI reset on the device and attempted to communicate with it, it still doesn't communicate.
After replacing the MCP2515T-I/ML multiple times on different boards I'm beginning to wonder if the issue isn't only that the crystal never starts up and the MCP2515 remains in "oscillator startup timer reset mode".
The crystal is ABM3B-8.000MHZ-10-D-1-G-T.
(datasheet) https://4donline.ihs.com/images/VipMasterIC/IC/ABRC/ABRC-S-A0001211322/ABRC-S-A0001211322-1.pdf?hkey=6D3A4C79FDBF58556ACFDE234799DDF0
The crystal load capacitor is 10p and I've replaced the crystal as well, no dice. I don't currently have 0402 capacitors to vary the load capacitance but am wondering if the 3.3V top layer copper pour could be providing so much parasitic capacitance that the board needs to be redesigned. According to C1,2 = 2(CL-Cstray), I should have used C1,2 = 14p if Cstray was 3p. Supposing Cstray is much higher I may not have needed to use any load capacitors. In desperation I've removed the load capacitors one at a time and attempted to see if the crystal would oscillate, in case the parasitics were in excess. That didn't work either.
I don't feel comfortable sending off a redesign until I know exactly what went wrong here, since it could be multiple things. I'm aware I should have had a keep out area and guard ring in the top layer around the crystal. Would that be the only issue though?
If possible I'd like to measure the actual load capacitance but my MM doesn't seem up to the job. The capacitance value measured across one load capacitor is either hovering around 12p or 2n.
Any ideas?
AI: In line with SpehroPefhany's answer, if you want to try connecting the ground pad you can do it as follows.
Using a small razor knife, make four cuts (as shown) to isolate the plane area under the chip from the 3.3V top side plane.
Scrape off the solder mask in the area shown, especially on the ground via.
Apply some solder paste to the newly exposed area (including the via)
Resolder the part. The ground pad should now be connected.
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H: Multiple feedback design methodology
I am having trouble finding a step by step approach to the MFB filter. I came across a tutorial from Analog Devices but I am struggling to find what is the reasoning behind their equations, and can't find any references about it. Their design goes as this:
Now I understand there are two conditions that need to be imposed and then the other three components are determined (knowing the coefficients of the transfer function). I can't figure out what their reasoning is for deriving each equation and been around it for hours. I did determine the equations of the parameters:
$$ H=\frac{R_4}{R_1} $$
$$ \omega_0 = \displaystyle \frac{1}{\displaystyle \sqrt{R_3R_4C_2C_5}} $$
$$ Q = \displaystyle \frac{\displaystyle \frac{1}{\displaystyle \sqrt{R_3R_4}}}{\displaystyle \frac{1}{R_1}+\frac{1}{R_3}+\frac{1}{R_4}} \times \sqrt{\frac{C_2}{C_5}} $$
AI: To begin
Two equivalent forms of the low-pass standard form term (three terms are possible for the full 2nd order TF):
$$\begin{align*}
\frac{V_{_\text{OUT}}}{V_{_\text{IN}}}&= A_0\cdot\left\{\begin{array}{l}
\frac1{
\left(\frac{s}{\omega_{_0}}\right)^2+\frac1{Q}
\left(\frac{s}{\omega_{_0}}\right)+1}
\\\\
\frac{\omega_{_0}^2}{s^2+2\zeta\:
\omega_{_0}s+\omega_{_0}^2}
\end{array}\right.
\end{align*}$$
(I use \$A_0\$ for the gain and not \$H\$, with the 0 implying the low-pass gain. A full 2nd order transfer function may also have \$A_2\$ and \$A_1\$ for the high-pass and band-pass terms.)
This configuration
The multifeedback solution for your schematic is:
$$\begin{align*}A_0&=-\frac{R_4}{R_1}\\\\\omega_{_0}&=\frac1{\sqrt{R_3\,R_4\,C_2\,C_5}}\\\\\zeta&=\frac12\cdot\sqrt{\frac{C_5}{C_2}}\cdot\frac{\sqrt{R_3\,R_4}}{R_1\,\mid\mid\, R_3\,\mid \mid\, R_4}, \text{ or:}&Q&=\sqrt{\frac{C_2}{C_5}}\cdot\frac{R_1\,\mid\mid\, R_3\,\mid \mid\, R_4}{\sqrt{R_3\,R_4}}\end{align*}$$
Sanity check
The form they used is closer to the \$\zeta\$-form, so I'd start with \$2\zeta\,\omega_{_0}=\frac1{C_2}\left(\frac1{R_1}+\frac1{R_3}+\frac1{R_4}\right)\$. Since \$2\pi \,f_{_0}=\omega_{_0}\$ then their \$k=\omega_{_0}\cdot C_5\$. Also, their \$\alpha=2\zeta\$.
So let's start at the beginning and just plug things in for a sanity test:
$$\begin{align*}
2\zeta\,\omega_{_0}&=\frac1{C_2}\left(\frac1{R_1}+\frac1{R_3}+\frac1{R_4}\right)
\\\\&=
\frac1{\frac4{\alpha^2}\left(1+H\right)C_5}\left(\frac1{\frac{\alpha}{2 \,H\, k}}+\frac1{\frac{\alpha}{2\,\left(1+H\right)\,k}}+\frac1{\frac{\alpha}{2\,k}}\right)
\\\\&=
\frac{\alpha^2}{4\left(1+H\right)C_5}\left(\vphantom{\frac1{\frac{\alpha}{2 \,H\, k}}}2 \,H+2\,\left(1+H\right)+2\right)\frac{k}{\alpha}
\\\\&=
\frac{\alpha^2}{4\left(1+H\right)C_5}\left(\vphantom{\frac1{\frac{\alpha}{2 \,H\, k}}}4 \,H+4\right)\frac{k}{\alpha}
\\\\&=
\frac{\alpha\,k}{C_5}
\\\\&=
\frac{\left(2\zeta\right)\,\left(\omega_{_0}\,C_5\right)}{C_5}
\\\\&=
2\zeta\,\omega_{_0}\end{align*}$$
So their algorithm checks out. Someone sane was involved. Good.
Understanding their algorithm
Now let's see how it might have been developed in the first place.
If we are given \$C_5\$, then it follows that \$\frac1{C_2}=R_3\,R_4\,C_5\,\omega_{_0}^2\$. So, using the definition for \$\omega_{_0}\$ we can find that:
$$\begin{align*}
2\zeta\,\omega_{_0}&= \frac1{C_2}\left(\frac1{R_1}+\frac1{R_3}+\frac1{R_4}\right)\\\\
2\zeta\,\omega_{_0}&=R_3\,R_4\,C_5\,\omega_{_0}^2\left(\frac1{R_1}+\frac1{R_3}+\frac1{R_4}\right)\\\\
2\zeta&=R_3\,R_4\,C_5\,\omega_{_0}\left(\frac1{R_1}+\frac1{R_3}+\frac1{R_4}\right)\\\\
\frac{2\zeta}{\omega_{_0}\,C_5}&=R_3\,R_4\left(\frac1{R_1}+\frac1{R_3}+\frac1{R_4}\right)\\\\
\frac{\zeta}{\omega_{_0}\,C_5}&=\frac12 R_3\,R_4\left(\frac1{R_1}+\frac1{R_3}+\frac1{R_4}\right) \\\\
\text{Clearly, }\frac{\zeta}{\omega_{_0}\,C_5}&\text{ is a resistance -- substitute in the gain, now}\\\\&=\frac12 R_3\left(\frac{R_4}{R_1}+\frac{R_4}{R_3}+1\right)\\\\
&=\frac12 R_3\left(H+1+\frac{R_4}{R_3}\right)\\\\\text{To resolve }&\frac{R_4}{R_3},\text{ assign }R_4=\frac{\zeta}{\omega_{_0}\,C_5}\text{ and place it on the left side}\\\\
R_4&=\frac12 R_3\left(H+1+\frac{R_4}{R_3}\right)\\\\
\frac{R_4}{R_3}&=\frac12 \left(H+1+\frac{R_4}{R_3}\right)\\\\
\text{Then assign }&u\text{ as the ratio }\frac{R_4}{R_3}\text{ and solve}\\\\
u &= \frac12 \left(H+1+u\right)\\\\
2 u &= H+1+u\\\\
u &= H+1
\end{align*}$$
Given the definition \$R_4=\frac{\zeta}{\omega_{_0}\,C_5}=\frac1{2 Q\,\omega_{_0}\,C_5}\$ and from the gain \$\mid A_{_0}\!\mid=H=\frac{R_4}{R_1}\$ requiring \$R_1=\frac1{H}R_4\$, it follows that remaining conditions then require \$R_3=\frac1{H+1}R_4\$.
So the resistors are done. (All this started out given \$Q\$, \$\omega_{_0}\$, and \$C_5\$. Nice.)
Now for \$C_2\$.
(I'm taking short-cuts, now, instead of writing out lists of tiny incremental steps I'm sure you can handle from here out.)
Return to \$2\zeta\,\omega_{_0}=\frac1{C_2}\left(\frac1{R_1}+\frac1{R_3}+\frac1{R_4}\right)\$. With the new resistor values, this becomes \$2\zeta\,\omega_{_0}=\frac1{C_2}\cdot 2\left(H+1\right)\cdot\frac{\omega_{_0}\,C_5}{\zeta}\$.
Solving, and canceling stuff out, find that \$C_2=\frac{H+1}{\zeta^2}C_5\$.
Substituting in \$\zeta=\frac1{2\,Q}\$, this works out to \$C_2=4 Q^2\left(H+1\right)\,C_5\$.
Summary
They chose to set up their own variables. For example, assigning \$\alpha=\frac1{Q}\$, which makes \$C_2=\frac{4}{\alpha^2} \left(H+1\right)\,C_5\$. Just as they wrote in your question. (I would not have bothered to define \$\alpha\$. It's not needed here and it is less confusing to just use \$Q\$.) But it will all work out the same, when all is said and done.
$$\begin{align*}
C_2&=4 Q^2\left(H+1\right)\,C_5\\\\
R_4&=\frac1{2 Q\,\omega_{_0}\,C_5}\\\\
R_1&=\frac1{H} \,R_4\\\\
R_3&=\frac1{H+1}\,R_4
\end{align*}$$
(Don't forget \$C_2\$ and \$R_4\$ may be multiplied together to get a \$\tau=C_2\,R_4=\frac{H+1}{\zeta\,\omega_{_0}}\$. So the new form of the denominator term, \$\frac1{C_2\,R_4}\left[2\left(H+1\right)\right]s\$, expands to \$2\zeta\,\omega_{_0}s\$. As must be.)
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H: Is it safe to run an instant power supply (IPS) with a flooded lead acid tubular battery (12V, 100 AH) in a small flat/apartment?
I live in a place where blackouts and power outages occur every hour. For backup power for two lights and two ceiling fans, I want to buy an IPS that runs on a flooded tubular acid battery, but I have recently read that they emit fumes and are not recommended for any indoor use. I am very concerned now. What should I do?
AI: For lights and a couple of fans, I would just use 12-volt-DC lights and fans, run them straight off the battery, and have the charger operate when able. It's fine to charge while discharging.
As to your question about off-gassing, that's all about the quality of the battery charger. I remember car alternators that had clacky-clack relay-based regulators. They were a complete disaster - constantly overcharged the battery, which creates hydrogen and oxygen and splatters acid out the tops. We had to add water every month to make up for the hydrolysis and splatters. But today, alternators are so good that they never overcharge, batteries never use up water, I haven't checked water in a battery for 20 years.
Charge control got so good that it actually became possible to have sealed lead-acid batteries, in which it is impossible to add water. They aren't magic; if they're overcharged they'll boil off their electrolyte and be destroyed since they can't be refilled. They just depend on the fact that most modern chargers are really good and tend not to overcharge them.
So yeah, if you use a quality 3-stage battery charger that is state of the art, you won't have much boiling off of hydrogen and oxygen, and so not much acid splatter. Still, would be wise to get a battery box for it. Don't put electronics in the battery box.
Of course you could also get a cheap battery charger and then have big and expensive problems. Your call.
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H: What is the purpose of chaining series of NOT gates?
I have seen these a few times, but I don't know what the purpose is. Clearly the purpose is something else than just to invert the signal. Otherwise just one or two would be enough for that. Also, does this configuration have a name?
simulate this circuit – Schematic created using CircuitLab
AI: It's an old trick to delay a pulse a certain amount of time, for ex. 100 nanoseconds. It's used to ensure that different circuits (or different parts of the same circuit) get the same digital logic signal in the wanted order. Let's assume the same pulse X is needed to start circuits A and B, but the right total effect needs that A starts before B. To guarantee it the designer lets B get X through a delay. The trick obviously was commonly seen in schematics say 50 years ago when complex systems were built of low integration level TTL or CMOS ICs. It's still used inside ICs.
The delay is not exactly known beforehand, because logic circuit manufacturers give "the propagation delay" in their datasheets with loose tolerances and the delay depends on operating voltage and temperature. But it can be good enough if certain minimum delay is a must, but tens of percents more is not harmful.
A transmission line based or an electroacoustic delay was used in cases where more accuracy was a must.
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H: Interconnecting two PCBs whose approximate distance is 2mm
I wish to design two separate PCBs (due to mechanical requirements), with 4 interconnections in between them.
Now, I could use standard pin header males and females for this task:
However, PCBs distance is less than 2mm (!).
I couldn't find shorter pin headers, are they existing at all?
I need only 4 pins, and it two PCBs must remain detachable (soldering them together is not an option).
Is there any option for this which I can finetune the 2 PCBs distance at least with 0.5mm precision (but 0.25 or 0.2mm would be even better)
Two boards are needed to be stacked i.e. like a sandwich, one is the bottom board, other is the top board:
---------------- TOP board
| | | |
---------------- BOTTOM board
4 connectors are used for USB (+5V, GND, D+, D-).
AI: Instead of using hard pin connections go flexible. Use a flat flexible cable (FFC) to interconnect the two boards. Two low profile flex cable connectors could be mounted near the edges of each board, then a short flexible cable would be used to connect the boards. With ever shrinking laptops, tablets and cell phones these types of connectors have been getting smaller. If the connector is low enough the bottom board might have it mounted on the same side as the top board. Here is an example of a flex cable connector with a 0.9mm height. Spacers or stand-offs mounted on the bottom board would determine the space between the two boards.
Connectors mounted on opposite sides:
Connectors mounted on same side:
If the two boards can be slightly different in size make the bottom board slightly wider. Then you could mount almost any connector type on the bottom board's edge that extends beyond the top board.
If the two boards must be the same overall size then consider designing a notch into the edge of the top board. The bottom board would then have a connector placed where the top board's notch is located.
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H: Why does a walkie talkie have TS for audio output and TRS for audio input?
Why does a walkie talkie have TS for audio output and TRS for audio input?
Is there any sense to have stereo for microphone and mono for speaker?
Why doesn't the manufacturer use TS for both audio input/output?
Please see walkie talkie audio jacks that I have:
AI: It isn't a stereo microphone. One of the pins is for the push-to-talk button, and the other is the microphone. The speaker doesn't have a button, so it doesn't need an extra pin.
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H: Can I do AC analysis of a transistor solely using the input/output impedances provided by the datasheet?
I learned to do AC small signal analysis of a BJT transistor with dV/dI ~ re = 26mV/Ie. But I don't understand why we take Vbe as 26mV here. Also, in the datasheets, I found graphs of input/output impedances for the transistor. Can't I just use them for a more precise calculation? If so, how to do it? I mean what would be the resulting equivalent circuit?
Let's assume Ic=10mA. Then it would follow that Zi=500 Ω and Zo=1/(65 μS) = 15,400 Ω = 15k4Ω.
Now that I have found these impedances, how should I place them in my equivalent circuit?
Re model was like this. But I don't know about what I should change.
AI: That 26 millivolts is not Vbe. It's a quantity seen in common basic nonlinear operating laws of diodes and transistors. Your formula 26mV/Ie is resistance Re in a linearized AC-only analysis model for transistors. Ie is the idle state (=operating point) value of the emitter current. The linearized model can be used properly for AC-signals which have peak values only few percents of the idle state DC values.
See for ex. this article of h-parameter AC model of a bipolar transistor.
https://bestengineeringprojects.com/h-parameter-model-for-transistor/
The parameters are different for all three basic amplifier configurations of BJT.
Using parameters is tricky and their actual values can vary wildly between the individuals of the same transistor type. The calculations must be done with complex number phasors in high frequencies. They are still useful when one tries to make statistical yield forecasts for a mass produced product or to see with calculations if his circuit idea has any chances to work. Without knowing the parameter values exactly (=measure them in the operating point) any accurate calculations are impossible. Taking the typical values from datasheets can easily cause large errors if you design a device which you are going to build just once. But as said, statistical analysis is possible if the distributions of the parameter values are known.
Circuits are generally designed so that the variations of the values of the h-parameters can be compensated to some degree. There are adjustments and preferably feedback which makes the actual h-parameter values less important as long as there's enough gain. Unfortunately the high frequency phase lag (=slowness) of transistors make feedback in radio frequencies less effective. But one can make the feedback to adjust the operating point to get the total gain right in a radio frequency amplifier.
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H: Capacitance for which the ratio of the input and output voltage is independent from the frequency
I have the following circuit with resistors and capacitors in parallel (see Picture 1):
I have to determine the capacitance \$ C_1 \$ in such way that \$\frac{u_e}{u_a} = 1 + \frac{Z_1}{Z_2} \$ is not dependent on the frequency \$ \omega \$.
I know that \$ Z_1 = Z_{R_1} || Z_{C_1} = \frac{R_1}{1+ j \omega R_1 C_1} \$ and \$ Z_2 = Z_{R_2} || Z_{C_2} = \frac{R_2}{1+ j \omega R_2 C_2} \$.
Then I get \$ \frac{Z_1}{Z_2} = \frac{\frac{R_1}{1+ j \omega R_1 C_1}}{\frac{R_2}{1+ j \omega R_2 C_2}} = \frac{R_1 + j \omega R_1 R_2 C_2}{R_2 + j \omega R_1 R_2 C_1} \$.
But from here on I fail to simplify this to calculate \$ C_1 \$. I tried to multiply this expression with the complex conjugate \$ \frac{R_1 - j \omega R_1 R_2 C_2}{R_2 - j \omega R_1 R_2 C_1} \$ but I just get a "mess" that I can't simplify
The solution should be \$ C_1 = 2,22 pF \$
Any help would be appreciated!
AI: Well, notice that the transfer function of this circuit is given by:
$$\underline{\mathscr{H}}\left(\text{j}\omega\right)=\frac{\displaystyle\text{R}_2\space\text{||}\space\frac{\displaystyle1}{\displaystyle\text{j}\omega\text{C}_2}}{\displaystyle\left(\text{R}_1\space\text{||}\space\frac{\displaystyle1}{\displaystyle\text{j}\omega\text{C}_1}\right)+\text{R}_2\space\text{||}\space\frac{\displaystyle1}{\displaystyle\text{j}\omega\text{C}_2}}=\frac{\displaystyle\text{R}_2\left(\text{C}_1\text{R}_1\omega-\text{j}\right)}{\displaystyle\text{R}_1\text{R}_2\left(\text{C}_1+\text{C}_2\right)\omega-\left(\text{R}_1+\text{R}_2\right)\text{j}}\tag1$$
Where \$\alpha\space\text{||}\space\beta:=\frac{\displaystyle\alpha\beta}{\displaystyle\alpha+\beta}\$.
Now, what happens when \$\text{C}_1=\frac{\displaystyle\text{C}_2\text{R}_2}{\displaystyle\text{R}_1}\$:
\begin{equation}
\begin{split}
\underline{\mathscr{H}}\left(\text{j}\omega\right)&=\frac{\displaystyle\text{R}_2\left(\frac{\displaystyle\text{C}_2\text{R}_2}{\displaystyle\text{R}_1}\cdot\text{R}_1\omega-\text{j}\right)}{\displaystyle\text{R}_1\text{R}_2\left(\frac{\displaystyle\text{C}_2\text{R}_2}{\displaystyle\text{R}_1}+\text{C}_2\right)\omega-\left(\text{R}_1+\text{R}_2\right)\text{j}}\\
\\
&=\frac{\displaystyle\text{R}_2\left(\text{C}_2\text{R}_2\omega-\text{j}\right)}{\displaystyle\text{R}_2\left(\frac{\displaystyle\text{C}_2\text{R}_1\text{R}_2}{\displaystyle\text{R}_1}+\text{C}_2\text{R}_1\right)\omega-\left(\text{R}_1+\text{R}_2\right)\text{j}}\\
\\
&=\frac{\displaystyle\text{R}_2\left(\text{C}_2\text{R}_2\omega-\text{j}\right)}{\displaystyle\text{R}_2\left(\text{C}_2\text{R}_2+\text{C}_2\text{R}_1\right)\omega-\left(\text{R}_1+\text{R}_2\right)\text{j}}\\
\\
&=\frac{\displaystyle\text{R}_2\left(\text{C}_2\text{R}_2\omega-\text{j}\right)}{\displaystyle\text{C}_2\text{R}_2\left(\text{R}_1+\text{R}_2\right)\omega-\left(\text{R}_1+\text{R}_2\right)\text{j}}\\
\\
&=\frac{\displaystyle\text{R}_2\left(\text{C}_2\text{R}_2\omega-\text{j}\right)}{\displaystyle\left(\text{R}_1+\text{R}_2\right)\left(\text{C}_2\text{R}_2\omega-\text{j}\right)}\\
\\
&=\frac{\displaystyle\text{R}_2}{\displaystyle\text{R}_1+\text{R}_2}\cdot\frac{\displaystyle\text{C}_2\text{R}_2\omega-\text{j}}{\displaystyle\text{C}_2\text{R}_2\omega-\text{j}}\\
\\
&=\frac{\displaystyle\text{R}_2}{\displaystyle\text{R}_1+\text{R}_2}
\end{split}\tag2
\end{equation}
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H: Shall I connect '-' terminal of power supply to earth GND (green terminal)?
Attached is the current lab setup for my chip testing. The green square represents the main PCB board, and little blue square represents the chip. The chip needs separate VDD voltage for its analog and digital circuits, but their ground is tied on the green PCB.
From here, I am seeking advice regarding the possible concerns about ground loop if '-' terminal of PSU is connected to the earth ground in the given situation.
I did some research on this matter and discovered that there are pros and cons to connecting the negative terminal of PSU to earth GND. On the one hand, shorting the '-' terminal of the PSU to earth ground can reduce common-mode noise caused by the parasitic cap b/w local GND and earth GND, but on the other hand, it may create a ground loop, which can possibly pick up 60Hz interferences.
Initially, I was of the opinion that connecting the '-' terminal to earth GND in my situation would not be advisable since the neutral pin for the PC power adapter is connected to earth GND, and this would create a GND loop if the PSU '-' terminal is shorted to the earth ground. However, other senior students in my lab have suggested that the PSU '-' terminal should always be connected to the earth GND unless a negative supply voltage is required. any feedback would be greatly appreciated.
AI: The PC is already earthed/grounded to mains PE wiring as you are using a 3-prong plug.
If it is a standard desktop PC, the PE earth/ground is already connected to PC metal chassis and to the common circuit ground inside the power supply.
The green terminal on lab power supply is also connected to mains PE via mains plug and lab supply voltage red and black output terminals are floating in respect to the green PE terminal.
In this case it would be best to not connect lab supply green terminals anywhere. The PCB is already earth-grounded through the PC.
If you connect the lab supply green terminal to PCB or to lab supply black terminal, that will create a DC path for a ground loop, through mains PE wiring inside the mains distribution network (either on your desk if devices are connected to same power strip, or via mains wiring inside walls).
And if you disconnect the lab supply black wire while black terminal is connected to green terminal, your device will be powered as the return path is via mains PE wiring of the power strip or room.
That's enough of a reason to prefer not using the green PE terminal on a lab PSU.
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H: Replacing 4pin USB with USB-C works only in one direction
I have an AR1100 with a usb mini-B female connector :
https://github.com/adafruit/Adafruit-AR1100-Resistive-Touch-Controller-PCB
Basically 4 usual USB pins : GND, D+, D-, +5V
I want to replace it with a usb-c connector.
At first I put a pull-down 5.1K resistor to GND on CC1 (A5) and CC2 (B5) pins. It didn't work at all.
I understood my mystake thanks to this topic, which explains if I want to make USB-C to USB-A device then I have to put a 5.1K pull-down resistor, but if I want to make a Type-A HOST (AR1100 IC : GND, +5V, D+ and D- signals) to Type-C device (my USB-C connector) I have to put a 56K pull-up resistor:
USB-A <-> USB-C adaptor
Then I replace the 5.1K pull down resistor with a 56K pull up to VBus and verified my schematic thanks to this topic: usbC_to_usbA. This time it works but only in on direction. Not the reverse.
After some thinking I came out with this :In one direction, D+ is gonna be connected to DP1 (A6) and D- to DN1 (A7).
But if I reverse my cable what's happen ? Then D+ is gonna be connected to DP2 (B6) and D- is gonna be connected to DN2 (B7) ? And because I left them unconnected that's why my signal doesn't work on reverse side ?
Here is my USB-C my board layout if needed:
EDIT:
See EDIT2, This assumption is probably wrong.
@Finbarr Vbus would be more correct if I'm doing something like this ?
Schema is coming from the official AR1100 schematic with original mini-b USB connector. If not would you please provide me correct layout for Vbus as I would like to use it in my project. I still have huge doubts as I'm still connecting Vbus to 5V here.
EDIT2:
This webpage Guide to USB-C Pinout and Features mention "The VBUS and GND pins are power and the return paths for the signals. The default VBUS voltage is 5 V but the standard allows the devices to negotiate and choose a VBUS voltage other than the default value. The Power Delivery allows VBUS to have a voltage up to 20 V. "
So I'm unsure how should I set up my VBUS pins.
This topic : Vbus line dfp clearly says "By Type-C specifications, a Type-C port should not supply any power until CC pins signal any connection, and power roles of connected partners are identified via Rp/Rd sense mechanism.You need a high-side power switch to turn VBUS on, which should be controlled by this "ID" pin".
So it seems the way, add a high-side power switch to turn VBUS on controlled by ID pin.
AI: Your first attempt was more correct.
The chip is not an USB host, your PC is.
The chip is an USB device, so you must have pull-downs.
Your board just connects to one set of USB data pins. Flipping the cable will make it work as cable has USB data pins on one side only.
The correct fix will be to put back the pull-downs and just connect chip to both sets of USB data pins.
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H: What is the rotatable switch used in smartwatches called?
Some smartwatches such as an apple watch and Samsung Gear use a rotatable switch for navigation that make a clicking sound when turned. The companies call it "crown" (some details - pdf). I'm trying to replicate the same for my arm computer more or less. I can't find it anywhere on the web.
The closest I got to was something called "selector switch" (images) but they seem way expensive to be the same. And also they seem to have very less divisions. The actual switch is a modified potentiometer with many divisions as far as I am guessing.
Video of crown of Apple
Similar thing, but it's a rotating bezel not crown, by Samsung
Few images:
AI: Typically this is just a particularly small mechanical rotary encoder. Similar to a large encoder with a 6mm or 6.35mm shaft, it will have a pair of contacts that operate in quadrature (from which rotation and direction can be determined by an MCU) and a SPST switching function if the crown is pressed.
One can find such things that are roughly cube-shaped and 3-5mm on a side. Any more and I'd have to link to actual products, and finding those is really your job.
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