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H: Equivalent diagram of a transistor using a Zener diode
In Horowitz The Art of Electronics on page 72 there is a schematic that provides an "ohmmeters view" of a transistor (see below.) In the description it says:
The base–emitter and base–collector circuits behave like diodes in which a small current applied to the base controls a much larger current flowing between the collector and emitter. Normally the base–emitter diode is conducting, whereas the base–collector diode is reverse-biased, i.e., the applied voltage is in the opposite direction to easy current flow.
Shouldn't the two diodes be switched? That is, shouldn't the B-C diode be the Zener one and the B-E diode the normal one? It says that the base-emitter diode is conducting and the base-collector diode is reverse-biased. Zener diodes are mostly used in reverse bias, right?
Sorry if this is obvious or something. I'm not studying electrical engineering, I am doing a physics lab and trying to understand transistors.
AI: The diagram is correct; the use of the Zener diode as the base-emitter connection is to remind the reader that the reverse breakdown voltage of the base-emitter region is much smaller than the reverse breakdown voltage of base-collector.
And, in relation to an explanation of how you might test a BJT using an ohmmeter, you have to be conscious that a fairly low voltage (usually less than 10 volts) can cause Zener breakdown when positive is applied to emitter and negative to base (NPN BJT).
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H: Trouble solving a specific KVL KCL question
Now I know this is newbie-ish kinda question but I was going over the basics of KCL and KVL, and encountered this problem:
For 1., I determine the drop using Ohm's law, ie. 2V
for 2-4 things get confusing. I apply KVL and KCL as follows:
For KVL1: I2R2+Vs1-I3R3=0
=> -2V+12V-2V should be 0 but it isn't!
For KVL2: I3R3-Vs2-I1R1=0
=> 2-10-8I1=0 => I1= -1A
For KCL1: I1+I2=-2
=> I2= -2+1= -1A
But all of those show up as wrong. What's wrong with my analysis? Any help would be appreciated.
AI: You are correct. The voltages around the upper loop should sum to zero. There is something wrong with the problem statement
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H: 2nd order high pass filter with two real poles
I want to implement an active analog high pass filter, which behaves as a high pass filter implemented by a capacitance, an inductance and a resistor in the following way:
simulate this circuit – Schematic created using CircuitLab
Which gives the follwing transfer function:
$$G_{hp} = \frac{CLs^2+RCs}{CLs^2+CRs+1}$$
Usually second order high pass filters are build up by Sallen-Key elements.
simulate this circuit
But the transfer function of these filters is given by
$$G_{hp2}=\frac{\frac{s}{\omega_g}^2}{\frac{s}{\omega_g}^2+s\cdot a\cdot\frac{s}{\omega_g}+1}$$
$$\omega_g=\frac{1}{RC}$$
In this transfer function there is only a conjugated complex zeros. But what I want to have is a zero at 0 and R/L.
Does some one know a circuit, which will give me an active filter, which is build up by an op-amp, capacitors and resistors, which behaves as the LCR filter?
AI: You could implement a grounded inductor with a GIC and add a resistor and capacitor (swapping the resistor and inductor will make no difference to the output in this case). The GIC takes two op-amps, a capacitor and several resistors (in this case).
GIC (image from Wikipedia):
Alternatively, a gyrator takes only one op-amp and two resistors to simulate a grounded inductor with a resistor in series. There are probably differences in the behavior between GIC and gyrator, especially near resonance if your op-amp(s) don't have a lot of GBW compared to the signal. Also if your resistor RL is relatively low value.
Gyrator (image from Wikipedia):
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H: Need a 110V switch that turns on with low current
I’m good with electronics, but bad with terminology. Basically, I need a switch of some sort that can pull regular power from my house (110V) to power a device that normally just plugs into the wall, except I need the switch to only close/turn on when low voltage (5V I believe, but I need to test) is applied through a positive and negative terminal.
I have an alarm clock that comes with a small disk with a vibration motor inside of it. When the alarm fires, it powers the vibration motor via a positive and negative wire connected to the clock. I’ve tried dozens of these, and none of them are powerful enough to work for me. I purchased a very large screen sifting vibration motor and I’m going to mount that to my bed frame. It is powered by a regular 110V outlet. I want to be able to signal a power on to the high powered motor via the old power source from the wires that used to go to the small alarm clock motor. I just don’t know what the name of such a switch might be.
AI: is there a specific kind that handles high voltage but switches for low voltage?
That is a relay. You need a relay whose contacts are rated for 110 V and whatever current that motor needs (plus some headroom, since a motor is an inductive device, and inductive devices tend to put more stress on relays). The coil voltage should be whatever voltage is applied to that vibration motor.
You're probably in luck since your alarm clock is designed to operate a motor, so its output is already suited toward operating something similar to a relay coil. You'll still need to carefully wire up the relay, taking extensive care to practice good electrical safety since you are dealing with mains voltage, and your device is going to be close to a bed (with a person as well as flammable bedding). This isn't simply a matter of connecting the right wires to the right places; you'll need to take care that your wiring and assembly workmanship is good enough to ensure no hotspots, shorts, etc even if the device is put under load, kicked around accidentally, etc.
An alternative would be an off-the-shelf device that integrates a relay, all the wiring, and safe construction all in one package. An example would be something like this - while I haven't used it and cannot personally endorse it, and I cannot find a UL listing or similar for it, this kind of off-the-shelf device is likely safer than DIY wiring without experience and suitable design review.
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H: LED drivers suitable for groups of LED lamps
Summary
Replacing MR16 SELV AC halogen spots with 12VDC LEDs. The halogens have individual drivers - need advice replacing these with (fewer) DC equivalents.
Setup
2 rooms with AC 240V supply, 6 lamp + 3 lamp
12VDC MR16 LED spots, 5W 660mA
These are smart - powered all the time and draw very low wattage when the light is off
Existing SELV AC drivers cause the DC LEDs to flicker inconsistently, and not turn on reliably
Constraints
Cost: Single driver for each room rather than 9 drivers
Question and Current Understanding
What drivers are suitable (+link to an example)?
Current Understanding:
DC driver to avoid flickering and damage to the smart components
Driver that supports a minimum wattage of close to zero, and a max of (5W*lamps_in_room)+20% headroom = ~36W and ~18W
Unclear on whether I need a constant current 660mA driver, or a constant voltage 12V driver, and whether to wire the lamps in series or parallel on each
Prior Research
I have asked lighting supply companies without success, and reviewed multiple StackExchange questions.
AI: The lamps you linked are 12V AC (not DC) lights. You should power them with a normal 12V AC transformer. They include their own internal drivers. They might also be ok with DC, but I don't see that in the datasheet and it's not a good idea to ignore specifications when wiring something in your home.
If you want to use DC lighting, you would buy DC lights, wire them in parallel and then use a constant voltage DC supply.
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H: System of linear equations for node voltage method
I have the following circuit (see Picture 1) on which I have to apply the node voltage method:
I have to use the steps which are described in the script that the prof. gave me.
The first step is to change the power supply with the series resistor \$R_2\$ into an current supply with the resistor connected parallel (see Picture 2) and to mark all currents in the circuit.
The second step is to define the linearly independent equations for the nodes \$1\$ and \$2\$. This can also be seen in Picture 2.
My question is: Are the equations that I wrote correct? Because later, when I have to write the resulting system of equations for all node voltages I get \$I_{q_1}\$ and \$I_{q_2}\$ in the same vector component.
AI: You haven't worked the circuit down to its basic form yet. Here's the next stage: -
So, you can combine R1 and R2 and, you can combine R4 and R5 to make life easier. The two current sources are now clearly in parallel too.
Get it to its basic form then use math; life's a lot easier this way.
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H: Case-less Power Triac Part Number Identification
I am trying to identify the part number of this high current (20A) triac. It was originally covered in potting, and it appears to have four pins (2 power, 2 control). It would appear to be something like this BCR30GM except that it does not have a case. The power triac circuit appears to follow Fig. 23 of this App Note
The PCB is ceramic and is bonded to a heatsink, to dissipate the heat. The part is driven by a IL420 optocoupler, triac driver. The entire module is used to control lighting. However, I have a number of them with failed triacs and would like to replace the part (or design a replacement PCB) since purchasing new modules is quite pricey.
Did they get the component manufacturer to produce these 'case-less' power triacs special for them or is there a place they can be purchased?
AI: The actual TRIAC looks to be a wafer here, apparently soldered underneath the copper prongs. Might be able to separate it with hot air, but the chip itself is unlikely to be a commercially-available part. The manufacturer likely orders them custom in ten-thousand quantity or more.
If these are failing prematurely, are they being overdriven, connected to inappropriate lamp type, or allowed to exceed temperature? Is there a cooling fan, and is it working?
If internal TRIAC replacement were attempted with a discrete (off-the-shelf, available) device in say a TO-3P or TO-247 package, how would you anchor the (now removed) prong? Also consider soldering the tab to the existing heat sink location. Low-temp solder may be needed, simply because it is going to be a challenge to get enough heat into it without cooking the TRIAC. And is that tab electrically isolated? The ceramic "board" may or may not electrically insulate it - hard to tell from the photo. If it does not, then my gut feeling is that the thermal conductivity (from chip, through ceramic, to heatsink) is not very good and the chip is getting too hot and failing. It really doesn't help that it is soldered and sandwiched between ceramic and copper - materials with different thermal expansion coefficients. And insertion and removal force is exerted directly on the chip (don't drop a module or slam it - it could readily stress-fracture the wafer.)
All-in-all, this seems like a lot of work for a very finnicky and no-guarantee repair. Might be easier to remove the whole module and permanently wire in a more robust solution (such as 30A TRIACs.) That would still need heatsink(s) and cooling though - quite a "retrofit" challenge.
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H: How to shift 3.3V to 5V with 3.3V provided only
I am trying to control 5V LED using ESP32's 3.3V GPIO. I researched voltage shifting using NMOS but could not get it to correctly output 5V when simulated in Tinkercad.
Is it possible to accomplish this without a 5V supply? What am I doing wrong here?
Edit:
LED I got is https://www.amazon.com/dp/B01LXZSV2N/ref=sspa_dk_detail_2?psc=1&pd_rd_i=B01LXZSV2N&pd_rd_w=hAXXr&content-id=amzn1.sym.89ee1d2e-380f-4a05-89e5-d22eb0a17762&pf_rd_p=89ee1d2e-380f-4a05-89e5-d22eb0a17762&pf_rd_r=JY1V7JDVYCG4V8GWN336&pd_rd_wg=qfdlZ&pd_rd_r=9d901bb4-46a0-46fe-b2f1-9c4b264b07c5&s=toys-and-games&sp_csd=d2lkZ2V0TmFtZT1zcF9kZXRhaWxfdGhlbWF0aWM&spLa=ZW5jcnlwdGVkUXVhbGlmaWVyPUExOTdHQThMNTZFOVJFJmVuY3J5cHRlZElkPUEwMzc0MzM1M1ZLTTJJM1FSS1REWCZlbmNyeXB0ZWRBZElkPUEwMDYxNzIxMjNYT1NKSkdaRjBMNCZ3aWRnZXROYW1lPXNwX2RldGFpbF90aGVtYXRpYyZhY3Rpb249Y2xpY2tSZWRpcmVjdCZkb05vdExvZ0NsaWNrPXRydWU=
AI: If you truly require 5v and only have a 3.3v supply, then you should generate a 5v supply using a boost converter.
However, many LEDs (even those whose datasheets specify 5v) can safely operate with a 3.3v supply. Perhaps your LED will work at 3.3v with no changes to the circuit.
You may need to reduce the resistor value to increase the LED brightness after reducing the supply voltage.
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H: Finding frequency response of inductive EMI sensor
I'm building an EMI sensor and trying to understand how it's done with the Elektrosluch. Here's the full schematic but this is the part I'm concerned about:
simulate this circuit – Schematic created using CircuitLab
I want to find the frequency response analytically. My understanding is that the inductor is the EMI sensor, and is our AC source Vin when finding our frequency response. Therefore, defining Vin on the left side of R1 and Vop as the output at the op amp:
$$Vin / R1 = -Vop(1 / R2 + jwC1) => H1(w) = -1/R1 * 1/(1/R2 + jwC1)$$
Therefore, defining Vout as the right side of C2, we have
$$jwC2(Vop - Vout) = Vin / R1 => $$
$$jwC2(H1(w)Vin - Vout) = Vin / R1 => $$
$$H2(w) = (H1(w) - 1/(jwR1C2))$$
When I plot this frequency response with Mathematica I get:
But with CircuitLab (I simulated by replacing the inductor with an AC source) I get something pretty different with two poles and max gain ~60dB instead of around ~145dB:
Where did my analysis go wrong? And does the inductance L1 not matter at all to the frequency response?
AI: The diagram below is the correct way to interpret the sensor. The frequency response can be calculated as the product of the op-amp stage and the output coupling stage.
\$C_2\$ does not interact with \$R_1\$ or any other of the components to the left of \$V_{OP}\$. It forms a high pass filter with \$R_L\$.
simulate this circuit – Schematic created using CircuitLab
$$H_1(j\omega)=\frac{-(\frac{1}{j\omega C_1})//R_2}{j\omega L_1+R_1}, H_2(j\omega)=\frac{R_L}{\frac{1}{j\omega C_2}+R_L}$$
The 100uF C2 should be large enough so that \$H_2=1\$
You should be able to take it from here.
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H: DC-DC Converter Remote ON/OFF logic levels
I'm trying to interpret the datasheet's description of the positive logic remote ON/OFF pin on this VQE50W-Q24-S5 DC to DC converter. It looks like it's ON when given 3.5 - 75V, or unconnected. Ok, that's pretty easy to understand.
But then it's OFF when... less than 1.2V. This seems to leave quite a bit of information out. If it's ON when unconnected (open) then it must be tied to ground in order to be considered 0 volts right? The datasheet also doesn't seem to define if a negative voltage would turn it off, or the input range. How would you interpret this?
I was able to find this technical document here from a different manufacturer of power modules and within that there is this explanation. I wonder if the same applies here?
https://flexpowermodules.com/resources/fpm-designnote021-enabling-with-rc-pin
"For both isolated and non-isolated converters with positive logic, the
converter operates normally if the RC pin is left open or connected
to a high level. The converter is turned off by connecting the
RC pin to a low level or to the negative input. The level definitions
vary from product to product and will be defined later in this
design note. The RC pin is referenced to the negative input."
AI: Not sure where your confusion is?
There's a positive logic input that looks like it's intended to (or at least could be) driven by an open collector, and is pulled up internally. It has to be pulled below 1.2 V to turn the module off.
Then there's a negative logic option that looks like it has an internal pull-down that has to be driven higher than 1.2 V to turn the module off.
Both of those are voltage levels with respect to the - input.
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H: Square wave generator without op-amp
I am trying to make a square wave generator but don't have an op-amp nor the PNP transistor to do it. Is there any way that works? I have tried using this one:
simulate this circuit – Schematic created using CircuitLab
but it is always on.
AI: It is already working and you can play with it.
simulate this circuit – Schematic created using CircuitLab
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H: Why is a LED with no resistor not a dead short?
From research you read on LEDs they need resistors to limit current.
But from experimenting, it seems to draw current given the correct voltage.
Even if I put a 5mm LED between 5 V and ground on an Arduino, it doesn't pull runaway current like a dead short. It just runs at 5 V and bright, then eventually burns out.
If that was a wire or a diode it would give high amounts of current causing power supply to cut out / Arduino to restart.
EDIT: The Voltage source was a USB port on a laptop.
The full circuit is
5V Laptop usb -> Arduino Nano -> 5v PIN -> multimeter -> White 5mm LED -> Nano Ground
With this I managed to keep the LED running solid at 150ma without a resistor. Overtime that current would go up a little, then drop a lot (assuming this is burning out), then would settle at 30ma, very dull, but not burn out.
Question 1)
Why does most of the internet say LEDs will pull too much current without a resistor, but it seems like the resistor is there to bring the voltage down, but the LED pulls the current it needs?
Or am I wrong in this thinking, and something else in the circuit (a circuit of Arduino, and LED between 5 V and ground, nothing else) limiting the current?
Question 2)
How would you drive an LED at more current than it pulls? If I wanted to pulse it at say 1 amp... how would that be done? Do I have to pulse at much higher voltage or is there a way to push current through the LED?
AI: When we call the LED a certain voltage, that's a simplification, or lie-to-children. Actually, you can look up the real current/voltage curve.
If you have a specific LED in mind you can look at its datasheet, but otherwise, here's some random chart for some random LEDs of different colours: (borrowed from another answer)
Your LED won't have the same curve as whatever random ones they used, so don't read the actual current and voltage off this chart. Just look at the shape. (I'd guess your ones have lower current than these ones.)
You can see the curves are kinda vertical, especially for the more red LEDs. So it's pretty reasonable to simplify the calculations by calling it a certain voltage. But it's not properly accurate.
If you feed the LED a certain voltage, it will stabilize at some current. If you put 5V across whatever UV LED they used to make the chart, it would draw about 78mA, as the chart says. If you put 5V across whatever red LED they used, the current would be off the chart. From the looks of it, about 350mA.
In most cases this current is way too high and the LED burns out. Hence the resistor is needed. You said this yourself - you said your LED runs bright and then burns out. So you have a problem, which you can fix by adding a resistor.
The I/V curve is maintained across the LED at all times (although it may shift depending on the temperature). If you want higher current you also need higher voltage. If you want higher voltage you also need higher current. They go together. This applies to almost all electronic components.
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H: In LTspice, how do I create a voltage source with a piecewise frequency dependence in an AC analysis?
I would like to run an AC analysis with a voltage source whose voltage varies with frequency according to the following piecewise plot:
I've heard it's impossible to have a frequency dependent voltage source in LTspice. I'm able to get around this for the first part of this curve using this technique:
Above, B1's voltage increases with frequency at 20dB/decade, just like the first part of the piecewise voltage function I'm going for. The second part is of course very simple - just a standard small signal AC voltage source.
I'm struggling with the third part of the piecewise, as there's no simple circuit I know of that creates a voltage that falls off at -10dB/decade. Furthermore, I'm not sure how to integrate these various sources into one piecewise source. I could brute force this by having three separate sims, one for each source, but I would prefer a more elegant solution. Any tips on these issues?
AI: I've heard it's impossible to have a frequency dependent voltage
source in LTspice.
I don't know where you heard this from. Anyway, I believe you just need to use a "FREQ table", which is simply a way to make a piecewise-linear source in the frequency domain. It's not in any of the official LTspice documentation, but LTspice can do it since it touts PSpice model compatibility and this feature is originally a PSpice feature.
Here is an example that plots your desired frequency response:
In this example consisting of only 4 points it's easy to define the FREQ table directly on the component within the schematic. If your target function requires a bunch more points, it might be easier to define the component as a SPICE directive and have it as a text block off to the side using the + symbol to allow you to continue a super long line horizontal line vertically (see the last entry of the first table here). If it's even BIGGER, then it's probably better throwing it into a subcircuit and .lib-ing it into the simulation. The answers to this previous question tackle some of that more nuanced stuff if you're interested:
LTspice: tables for parameterized passive components... why not?
It's worth noting that you can also define much smoother curves in the frequency domain using the Laplace feature. Both FREQ and Laplace suffer from artifacts when used in transient simulations because LTspice has to compute an IFFT to get the impulse response. However, Laplace is usually more well-behaved in that respect. If you're just doing .ac analysis, then you don't have to worry about that aspect, but if necessary more info can be found in the LTspice Help under "B. Arbitrary Behavioral Voltage or Current Sources" (duplicated below):
If an optional Laplace transform is defined, that transform is applied
to the result of the behavioral current or voltage. The Laplace
transform must be a function solely of s. The Boolean XOR operator, ^,
is understood to mean exponentiation, **, when used in a Laplace
expression. The frequency response at frequency f is found by
substituting s with sqrt(-1)2pi*f. The time domain behavior is found
from the sum of the instantaneous current(or voltage) with the
convolution of the history of this current(or voltage) with the
impulse response. Numerical inversion of a Laplace transfer function
to the time domain impulse response is a potentially compute-bound
process and a topic of current numerical research. In LTspice, the
impulse response is found from the FFT of a discrete set points in
frequency domain response. This process is prone to the usual
artifacts of FFT's such as spectral leakage and picket fencing that is
common to discrete FFT's. LTspice uses a proprietary algorithm that
exploits that it has an exact analytical expression for the frequency
domain response and chooses points and windows to cause such artifacts
to diffract precisely to zero. However, LTspice must guess an
appropriate frequency range and resolution. It is recommended that the
LTspice first be allowed to make a guess at this. The length of the
window and number of FFT data points used will be reported in the .log
file. You can then adjust the algorithm's choices by explicitly
setting nfft and window length. The reciprocal of the value of the
window is the frequency resolution. The value of nfft times this
resolution is the highest frequency considered. Note that the
convolution of the impulse response with the behavioral source is also
potentially a compute bound process.
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H: wGate driver working-Parallel NFET
Reference
With context to the following image.
From the input pin, which can be interfaced with CMOS logic. The highlighted enhancement type PMOS & NMOS pair acts as an inverter pair, right? (basically switching action, when PMOS is ON, the NMOS would be OFF & vice versa) this would be to prevent short of VS to the ground, I presume.
I didn't understand the connection between the PU and PD pins as well (the drain of the internal PMOS connected with the drain of the internal NMOS) is this correct to say?
Following this it is connected to the Gate of external FET Q1.
Are Q1 & Q2 acting as the load of the CMOS inverter?
I don't understand the connection of the BST to the SRC pin.
Although I'm new to this kinda circuit from the tutorials I referred the need of the Gate driver is based on the fact the FET (high side) needs VG > VS and hence the bootstrap power supply/capacitor is used to provide VSupply + VCBST to the gate of the external FETs.
The above is not the case here.
Just need help with the working; I'm clearly having problems understanding the same.
Basically the BST, PU, PD & SRC pins.
AI: You have correctly summarised the states of the two internal MOSFETS. One is off while the other is on, under control of the potential at INP. By joining PU to PD, this produces one of two conditions:
INP is high, the lower MOSFET is "on", and it pulls the potential at PU/PD down to 0V.
INP is low, the upper MOSFET is "on", which pulls PU/PD up in potential, to whatever potential is at its own source.
In this way gate potentials for Q1 and Q2 are raised and lowered under control of INP.
As for \$C_{BST}\$, its purpose is to raise potential at the gates of Q1 and Q2 beyond 48V (necessary to switch them fully on, in this source-follower configuration) during the period when the external MOSFETs Q1 and Q2 are supposed to be on.
Capacitor \$C_{BST}\$ needs to be charged ("topped up") only during the period when the MOSFETs are off. That's when Q1/Q2's source, node SRC, is at 0V potential. By connecting the bottom end of \$C_{BST}\$ to SRC, this allows \$C_{BST}\$ to charge up to whatever potential is at \$V_{AUX}\$ or the internal 12V source, during this off period.
Then, during the subsequent on period, SRC rises in potential, and the top of \$C_{BST}\$ (already at +12V) rises with it. Because the upper internal MOSFET is on at this point, it's the top of \$C_{BST}\$ which is effectively connected to Q1/Q2's gates, ultimately taking those gates to nearly \$48 + 12\$ volts.
In other words, the \$C_{BST}\$ is able to charge during the off period, and then "follow" the rise of SRC during the on period, due to being connected directly to SRC.
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H: Cut off frequency of a passive second order low pass filter
I was trying to do a simulation for second order low pass passive filter, and the equation of the cut off frequency is $$f_c=\frac{1}{2\pi\sqrt{R_1C_1R_2C_2}}$$
when I calculate it on the values of this circuit I get $$f_c=1591Hz$$
but when I use OrCad to approximate the value of it, I find that it's around $$f_c=608Hz$$
can any one explain how ?
AI: What the OP refers to as the corner/cutoff frequency is actually the natural frequrncy \$f_N=\frac{\omega_N}{2\pi}\$ of the system. The corner frequency \$f_c=\frac{\omega_c}{2\pi}\$ takes more work;
Using nodal analysis the transfer function can be derived:
$$H(s)=\frac{V_{C_{2}}(s)}{V_{1}(s)}=\frac{\frac{1}{R_{1}R_{2}C_{1}C_{2}}}{s^{2}+\left(\frac{1}{R_{1}C_{1}}+\frac{1}{R_{2}C_{1}}+\frac{1}{R_{2}C_{2}}\right)s+\frac{1}{R_{1}R_{2}C_{1}C_{2}}}$$
Comparing this to the standard 2nd order form:
$$H(s)=\frac{\omega_{N}^{2}}{s^{2}+2\zeta\omega_{N}s+\omega_{N}^{2}}\tag{equ 1}$$
reveals that
$$2\zeta\omega_{N}=\left(\frac{1}{R_{1}C_{1}}+\frac{1}{R_{2}C_{1}}+\frac{1}{R_{2}C_{2}}\right)\text{, and that }\omega_{N}=\frac{1}{\sqrt{R_{1}R_{2}C_{1}C_{2}}}$$
These two equations are used to solve for \$\zeta\$ and \$\omega_N\$
Then solve (equ 1) \$H(j\omega)=\frac{1}{\sqrt{2}}\$ for \$\omega=\omega_c\$
This then results in the -3dB corner frequency
$$f_c=f_N \sqrt{\left(1-2\zeta^{2}\right)+\sqrt{4\zeta^{4}-4\zeta^{2}+2}}$$
The confusion of the corner frequency with the natural frequency is the basic issue. The natural frequency is not a vibration or oscillation. It is a system parameter only.
You should work through the derivation steps that I have skipped.
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H: How to understand the DC-biasing and the HPF circuits in the top-left corner of OPA1671 datasheet's reference application schematic?
I'm looking to understand the chosen values in this reference design and whether they can be improved, particularly the biasing DC circuit and the high-pass filter for the electret microphone.
My understanding is that these two circuits can be analyzed via superposition.
Taking the DC biasing circuit first, we'd get something like this:
simulate this circuit – Schematic created using CircuitLab
I assume that R1 and C1 form a LPF, with a cutoff frequency of ~10 Hz; is that correct? If it is, then that would make sense, however, I'm not completely sure how to interpret C2 as a part of this circuit - in steady-state, this should be an open path (and then we can ignore C1 as well), which leads to 2 voltage dividers -> R1 || R2 and then ((R1 || R2) || (R3 || R4)). I can understand that R3 and R4 are chosen to be the same value to divide the supply voltage in half at the input of the op-amp, hence the DC biasing. I don't understand why R2 was put there or, at the very least, given a value of 10k, since that loads down the second divider and the DC voltage at the input of the op-amp is actually around ~2.15V. Would it make sense to increase R2 here to have a more equal biasing point?
With regards to the high-pass filter, my question is still the same - what's the point of R2 here? The C2 and R3||R4 form an HPF with a pole at 3.18 Hz, as described in this datasheet. This seems to form a pi-network, but I'm not sure why that'd be needed? Is it to limit the input current?
simulate this circuit
All help is appreciated, thanks in advance!
AI: For starters, there is not just one way of making a microphone amplifier, and this circuit is only an example, and while any circuit can be improved by changing component values to be more suitable for a specific case you might have, a different circuit might be better to begin with, so there is no point trying to optimize a generic example.
The R1 and C1 do form a 10 Hz low-pass filter, and the filtered output supply is used to power/bias the microphone capsule itself and the non-inverting input of the op-amp.
From then on, your analysis starts to go haywire.
The microphone can't be replaced by a short circuit to ground. At mininum, it should be replaced by a resistor to ground, or a constant current sink, to evaluate DC bias.
The microphone needs a bias supply, and it needs it via a resistor to a power supply, as the microphone has a JFET output stage built-in. So the resistor R2 is to give a bias supply to the microphone, from the filtered supply. The value of R2 is not very important here, and it is likely chosen at random, or just considered a roughly suitablr value for that specific microphone, or a wide range of different microphones. Usually the bias resistor is approximately 2 kohms to approximately 2 volts to provide some bias current at some bias voltage to the mic, but since the supply is almost 5V the resistor can be higher and it would cause relatively lower bias voltage to the mic but also mic output current chages would cause larger output voltage swings.
So, basically, R2 and mic provide you an audio signal with a DC bias.
Now, the DC bias out of the mic should be removed to let the resistor divider R3 and R4 to set the amplifier input bias to half supply. The bias is removed by C2. The value just needs to be good enough to pass audio. The input impedance to amplifier is 50 kohms. The 1uF cap with 50k impedance calculates to a roughly 3 Hz high pass - it will pass audio band just fine and removes DC bias. In reality you would need to calculate it with the mic output impedance which is max 10k, so it would not really change anything.
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H: Can someone give me an example of how a low or high pass filter is used in practice?
I understand the theory and math behind electric filtering systems but I don't understand how they can actually be used in circuits. Take an RC low pass filter as an example. For low frequencies, the input voltage will approximately appear over the output terminals but if this voltage is applied or connected to another circuit, then the current/voltage over the output terminals changes as it would if you were using a voltage divider as a voltage source for a circuit.
AI: An RC low pass filter passes low frequencies and does not pass high frequencies. It is basically a frequency dependent voltage divider, so it has input impedance and output impedance, so it is also sensitive to circuits that drive it or load it.
To have it work you can't put much load on the RC output or it will change the properties. Generally filters are loaded with things that have high impedance inputs so they don't load the filter.
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H: Using Timer Interrupts Instead Of Delays in PIC Microcontroller
I have this task where I have to use timer interrupts intead of delays (for efficiency purposes) in this 7 segment display circuit with PIC18F4620.
Here is the circuit:
Display is common anode.
I would normally write the code like this and the output on the display would be "32.10" but I have to eliminate all the delays:
int dgt[10] = {0x40, 0x79, 0x24, 0x30, 0x19, 0x12, 0x02, 0x78, 0x00, 0x10};
output_high(pin_d7);
output_c(dgt[0]);
output_high(pin_c7);
delay_ms(5);
output_low(pin_d7);
output_high(pin_d6);
output_c(dgt[1]);
output_high(pin_c7);
delay_ms(5);
output_low(pin_d6);
output_high(pin_d5);
output_c(dgt[2]);
output_low(pin_c7);
delay_ms(5);
output_low(pin_d5);
output_high(pin_d4);
output_c(dgt[3]);
output_high(pin_c7);
delay_ms(5);
output_low(pin_d4);
I started to experiment with replacing delays with timer1 interrupt with a LED blinking circuit and that code is something like this:
#define tmr 218
#use fast_io(b)
#int_timer1
void delayy(void)
{
output_toggle(pin_b0);
set_timer1(tmr);
clear_interrupt(INT_timer1);
}
void main()
{
set_tris_b(0x00);
enable_interrupts(INT_timer1);
enable_interrupts(GLOBAL);
setup_timer_1(T1_INTERNAL | T1_DIV_BY_1);
set_timer1(tmr);
while(TRUE);
}
My question is: How can I write that 7 segment display code without any delays and with only timers?
AI: You need to move your code from the main loop to interrupt handlers, doing small part of work on each interrupt.
Set timer to generate an interrupt every 5 ms. Then your code, rewritten as a finte-state machine, placed in the interrupt handler would look like this:
void timer_isr()
{
switch(state)
{
case 1:
output_high(pin_d7);
output_c(dgt[0]);
output_high(pin_c7);
state = 2;
break;
case 2:
output_low(pin_d7);
output_high(pin_d6);
output_c(dgt[1]);
output_high(pin_c7);
state = 3;
break;
case 3:
output_low(pin_d6);
output_high(pin_d5);
output_c(dgt[2]);
output_low(pin_c7);
state = 4;
break;
case 4:
output_low(pin_d5);
output_high(pin_d4);
output_c(dgt[3]);
output_high(pin_c7);
state = 5;
break;
case 5:
output_low(pin_d4);
state = 6;
break;
}
//clear interrupt/rearm timer
}
state is a global variable, declared as volatile, to prevent optimizing-out all code. Process is started by writing state = 1. By changing timer configuration on each state-change you can get different delays.
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H: A bit of confusion with DRV8210DRLR motor driver
I am working with DRV8210DRLR motor driver, mouser says it is a half bridge controller, texas instruments that it is a H-bridge. I require to spin motor and be able to change direction, so I assume I need full bridge controller. So first question is are there difference between H and Half bridges? Or are there 3 types of motor controllers: H bridge, half bridge and full bridge?
Second question is about the interface, I use DRL package, I am trying to control the direction and speed of a BDC motor using this table on page 14:
But it's a bit confusing, how to control speed and direction only using 2 pins? Or does my package is only able to spin motor in one direction, which would make this table useless and kind of misleading. I will include link to a datasheet here: https://www.ti.com/lit/ds/symlink/drv8210.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1682497944275&ref_url=https%253A%252F%252Feu.mouser.com%252F
AI: So first question is are there difference between H and Half bridges?
Or are there 3 types of motor controllers: H bridge, half bridge and
full bridge?
A H-bridge is also known as a full-bridge
A H-bridge is made from two half-bridges
The mouser site refers to half-bridges because the DRV8210 contains two half-bridges that can be (a) used independently, (b) used in parallel or (c) used together to form a "full" H-bridge.
how to control speed and direction only using 2 pins?
I've highlighted in your table where forward and reverse control takes place: -
The two input pins are IN1 and IN2 and you wire your motor in a H-bridge configuration: -
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H: Is it possible to produce 30W (5V 6A) using a flyback topology without opto-isolation?
The circuit steps the voltage down from POE (class 4) input to 5V 6A
The circuits I have found so far use opto-isolation to regulate the feedback voltage (for 5V 6A). I'm wondering is it feasible to use the Auxiliary to regulate the feedback circuit when the output 5V/6A? The manufacturers I have found all use opto-isolation for 5V and 6A. Is this because it is better to have opto-isolation for lower voltage and high current? Is there any other reason?
The following uses opto-isolation for 5V 6A:
Skywork
Texas Instruments
MPS
AI: The manufacturers I have found all use opto-isolation for 5V and 6A.
Is this because it is better to have opto-isolation for lower voltage
and high current? Is there any other reason?
Opto-isolation is used to feedback to the flyback controller when the output voltage is in regulation hence, it's regarded as the most satisfactory method of ensuring output voltage accuracy. It's got nothing to do with the output voltage level or the output current level.
Clearly, if you need galvanic isolation between output and input, an opto-isolator provides this with massive and obvious abundance.
Is it possible to produce 30W (5V 6A) using a flyback topology without
opto-isolation?
Other methods can be used that provide galvanic isolation AND accuracy but, why bother if an opto is good enough?
There are also less accurate methods such as using an auxiliary winding or measuring the back-emf on the primary side.
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H: What is the maximum reasonable cable length for a humidity sensor?
I have an ESP32, and use capacitive soil humidity sensors to check the humidity of my plants. They get shipped with about 15 cm of cable attached.
What is a reasonable/safe cable length I can use before it gives unrealistic readings? It is powered with 3.3 V.
AI: The longer you make your wire, the more voltage drop the analogue signal will suffer along the wire. This will show itself as decrease in the maximum value you can see appearing on your input pin, where a short wire may get up to 3.2v, but a long wire might only get up to 3.1v . Therefore for the most part you could fix this in software by re-scaling your readings as needed, and you can have pretty much as long a wire as you would like.
However, the longer the wire the more noise you will pick up, so you may need to do some software de-noising to fix this.
In general, you should be fine to make it up to a few meters long without any problems
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H: What is the design reason behind these components?
I have some questions regarding the comparison of these two circuits. Both produce current noise through the first reverse-biased transistor. That variable current enters through the base of the second transistor, affecting its collector's voltage.
What is the purpose of the components R1, R2, and C2 connected to the bases in the second schematic? How do they affect the noise production? What differs from the first schematic and why are the 1MR values for the resistors?
Why is the 680KR resistor in the emitter of the first transistor in the first schematic and not on the second one? It might be related to the first question.
AI: It's instructive to look at this circuit separately in terms of DC and AC. The DC signal is related to the biasing of each stage and is blocked by the series capacitors, while the AC signal flows through the capacitors from stage to stage, and is the signal being amplified. I'll walk through the circuit from left to right, discussing the DC and AC at each stage.
C1 provides AC coupling, meaning that the DC values of Q1 base and Q2 base can be different. R1 then provides a path to ground, reverse-biasing the Q1 base-emitter junction which causes it to produce AC flicker noise (ref).
Looking at C1 analytically, it produces a high-pass filter. Frequencies below a certain cutoff are not allowed through it; I'd estimate the cutoff on the order of 10-100 Hz, since the time constant is RC, where C is 100 nF and R is the effective impedance of Q1's junction, R1, and the input impedance of the amplifier based on Q2. I'd estimate this effective impedance to be on the order of 100k ish ohms, with 1 MOhm as an upper bound (because of R1). Note that this is a highly approximated and handwaved argument, and hand calculation or simulation will be required to get a more precise value.
R2 provides self-biasing as a form of feedback for the common-emitter amplifier based around Q2. When the output at the collector of Q2 rises, it increases the voltage on the base of Q2, which increases the current through Q2 and provides negative feedback by reducing the collector voltage of Q2 thanks to that higher current pulling the collector voltage down.
Because of C1, the DC voltage at the base of Q2 doesn't have to match the DC voltage at the base of Q1. This lets Q2 settle into a good operating point as a consequence of its own transfer characteristic (in purple) and the resistor feedback (in green). Note the slope of the transfer characteristic is very high - a small change in base voltage will produce a large change in collector voltage, meaning the gain is high, while the operating point is away from amplifier saturation (marked as 'Poor gain'):
The AC noise signal from Q1 enters the amplifier, and gets amplified by this high gain, producing a stronger AC signal at the collector.
Finally, C2 provides an additional level of AC coupling, keeping the DC bias of Q2's collector out of the output signal.
Compare this to the first circuit - the same DC bias is used for the base of Q1 and Q2; this bias is a consequence of base current in Q2 and reverse leakage in Q1, and chances are it could be a lousy bias for optimal performance of Q1, Q2, or both.
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H: Modelling a capacitor on a PCB
I want to design a "PCB capacitor". The goal is to detect the permittivity of the material surrounding the PCB. I am unsure how to design the electrodes of the capacitor in order to have the highest sensitivity. It will be a two layer PCB.
I basically have three designs in my mind, see attached image, but I have no idea which would be the best. I also dont know if I should use a ground plane, but I guess a ground plane would be contra productive, because it would block the field lines in the back, reducing the sensitivity.
AI: The first and most simple design is good. Two parallel areas with GND and the measuring-pin.
Look at the source of the Austrian "Giesomat", the ramser-elektro guy has created the Capacitive soil moisture sensor.
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H: How do I know how much a kWh costs me if I have my private generator
I have a 10 kVA generator and its efficiency is approx. 90%
How can I know the cost of a kWh?
Estimate the price of diesel as $2.5 a liter.
AI: I have a 10 kVA generator and its efficiency is approx. 90%.
That's impossible. No internal combustion engine can achieve that. The maximum theoretical value is 75%. (See Wikipedia.
For a small generator you'd be lucky to get 40%.
The 90% may refer to the alternator efficiency and this is in the realms of possibility (as is the likelihood that this number was advertised to mislead the buyer).
How can I know the cost of a kWh?
Estimate the price of diesel as $2.5 a liter.
Assuming a resistive load so that 10 kVA = 10 kW1 then the mechanical input will be given by $$ \frac {P_{out}}{e_{alt} \times e_{eng}} = \frac{10} {0.9 \times 0.4} = 28 \ \text {kW} $$
Diesel has an energy density close to 10 kWh/L so you will need 2.8 L/hour for 10 kW output.
2.8 L × $2.5 = $7 for 10 kWh.
1 kWh = $7 / 10 = $0.70.
1 Most generators are designed to run at a power factor less than unity - maybe 0.8 or so. As a result further derating may be required in your use case.
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H: Wrong frequency response of an active HPF filter
I am trying to simulate an active high pass filter on OrCad, but the frequency response of it looks like a band pass filter, does anyone know why ?
AI: Sure, the mystery part you used does not have the bandwidth or slew rate to be capable of 20V output amplitude at beyond about 100 kHz so it can't output 20V amplitude at higher frequencies it is capable of.
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H: Looking for a component that accepts a broad range of discrete values (e.g. 0 to 50 VDC) and outputs a LOGIC HIGH; otherwise output is LOGIC LOW
I am looking for a component that will accept multiple discrete values ranging from 0 to 50 VDC, but it doesn't have to be 50 VDC. I am looking for a broad range. This range could be 0 to 30 VDC or 0 to 60 VDC. Then, based on a set value of the discrete inputs (5 VDC or greater) will output a LOGIC HIGH and otherwise output is set to LOGIC LOW.
I could design a circuit easily for this purpose using a voltage divider and pulled down connected to a diode, but I am wanting a component that can accept multiple inputs and give multiple LOGIC outputs for each input. This will save room.
AI: Such component could be a plain comparator or an op-amp with a simple resistive voltage divider.
You need to have a minimum value above 0V at which it will trigger.
You could use a quad op-amp, so it's one IC with 4 circuits, giving you 4 inputs and outputs.
simulate this circuit – Schematic created using CircuitLab
Input voltage can go up to 60V easily, without damaging the comparator (LM339, for example).
The input voltage may need to reach 0.1V to give you a logic zero at output.
The voltage provided to the output pull-up resistor sets your logic high output voltage.
If you need to invert this and get logic high when input goes above 0.1V, you simply swap each inverting (-) and non-inverting (+) input with each other.
To make it more integrated and slim, you could use "integrated resistors" (multiple resistors in a single package/component).
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H: How to describe, in a schematic, grounding to the base/body of a potentiometer?
I am working on updating a guitar project I did many, many years ago. I mean, I could just do a 'symbolic' drawing of the wiring itself, but since I have more experience now, for my records I'd just like to draw up a formal schematic.
My question relates not so much to the context of my project per se, but more so, in general, how does one properly handle on a schematic any wiring or component use which is perhaps 'non-standard'?
e.g. In my case I have the three pins connected to the potentiometer, but also a ground wire going to the body/base of the pot itself. Mind you, not 'unheard of' in guitar work, but also (I think?) rather 'non-standard' on a schematic.
Question pertains to the potentiometer here, but also how to handle any other 'non-standard' wiring case. Don't know 'best practice'.
AI: You can put notes in the schematic as well as pictures of special assembly procedures. You could also draw a special symbol with a forth pin attached to a dashed box around the resistor symbol which is the body of the pot.
In a commercial environment, this is covered in special assembly instructions since schematics are not part of the assembly documentation.
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H: Voltage regulator LMR33630 doesn't work, asking for circuit review
I've put LMR33630ADDAR voltage regulator into a PCB with this circuit:
It's slightly different from the example from datasheet:
PG isn't connected, CFF capacitor absent and feedback resistors are 10k vs. 2.49k. I see no issues with these difference since resistor divider is the same for expected 5V output and PG pin may be not used according to datasheet:
Open drain power-good flag output. Connect to suitable voltage supply through a
current limiting resistor. High = power OK, low = power bad. Flag pulls low when EN =
Low. Can be left open when not used
And the same for CFF capacitor:
In some cases, a feedforward capacitor can be used across R FBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used
So, in result the circuit doesn't work - if I supply 12V input, I see 5.6V on BOOT and VCC pins (which is expected) but 0V on SW pin. I have no idea what's wrong. Furthermore, If I supply 5V, the LMR33630 starts heating to the burning point.
Here is also part of the PCB, probably the issue is in placement:
Would appreciate help of experts in this area since it's my first design of voltage regulation circuit
AI: The datasheet says that the exposed thermal pad is also analog ground.
The pad in the image appears to be floating.
The images are a bit confusing The top and bottom layers look identical with the parts on the bottom layer. This is unconventional and could lead to mirror image footprints. Note that red is considered the top layer and blue the bottom layer. While parts can be placed on the bottom layer, the footprints msut be placed as mirro image unless the view is inverted.
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H: Using clothesline steel core wire rope for AC and DC
As I am currently in a war zone, I don't have many options for cabling.
I found this clothesline (steel core plastic wire rope) that appears to be one mm of diameter (steel core diameter.) 13 meters of it measured 7 ohms resistance.
Edit: It is 3.8 Ω and not 7. The first multimeter test lead probes had 2-4 resistance when shorted. A slightly better multimeter had 0.5 Ω when shorted. Both multimeters gave 3.8 after subtracting multimeters own resistances and scratching the wire ends.
Can it carry AC 120 or 240 volts, and if so, for what distance?
How many of it (doubling it) can carry DC 18V and 15 A from a solar panel arrays 10 to 15 meters away from the inverter (charge controller)? (20 W panels with open circuit voltage of 21 V).
This is just temporary solution and I hope only for few days or weeks. Air strikes blew up some transformers and high voltage lines and our concrete homes are not designed to be habitable without AC power.
Edit:
Its now connected to a c32 breaker (the smallest I could find) and a breaker mounting brackets cut from a laptop battery cover. The wire is inserted in plastic bottle caps as wire wall clips and a tow heads plug is inserted to the other end (to be upgraded to three heads) because now polarity is important I think.
I will connect it to a manual changeover switch when adding the solar oart after finishing the battery but that is another longer story (Lithium battery without BMS) but I may be able to reuse old laptop batteries BMS (I have more than 20 batteries):
The solar system is only for a medium 100 W Samsung fridge and the mains are for the fridge plus two ceiling fan, one swamp cooler and three LED lights.
AI: Steel, having just around 10 times higher resistivity than copper means it will take ten times the conductor area to match copper. If you measured 13 meter of it to 3.8 Ω, the cross sectional area would be 2 mm^2, assuming 5.95*10^-7 Ωm of resistivity for "high alloy steel" (this varies greatly unfortunately so assume +100% -50% uncertainty for all values given).
To answer your questions:
How long = Time: probably many years. How long = Distance: Most devices will run happily with 10 % voltage drop. Anything universal input (100-240 V) could handle significant voltage drop due to the cable at which point it's the thermal capability of the cable which sets the limit as you don't want it to melt.
With 3.8 Ω for 13 meter, you have 0.29 Ω/m. At 1 A 230 V AC current, you can go 39.7 meter (round trip is double distance) before you have dropped 10 % of the voltage. If you halve the current, it's double the distance. Gut feeling + experience says it would get lukewarm at 2-3 A so I would not go much above it.
Could be lethal though, as the insulation is not mains voltage rated. I would be more afraid of anyone coming into contact with the end points and the cable termination than touching the outer shell of the clothesline and somehow get zapped by it as they tend to sit outside for decades without becoming brittle by the UV exposure.
As stated below by Martin McCormick, your best bet is to put the inverter as close to the panels as you can and run AC through the clothesline versus low voltage DC current through the clothesline.
With just one conductor, carrying 15 A via 3.8 Ω means a 57 V drop, so not possible with 18 V at all. It would also melt. To make it work at 18 V, perhaps 20 % drop (3.6 V) could be tolerated. To get down to 3.6 V drop, you would need 57/3.6 = 16 in parallel.
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H: IRLML9301PBF as high side switching for 5 V, 2 A load from a 3.3 V uC?
Circuit:
simulate this circuit – Schematic created using CircuitLab
I would like to cut off the power to my APA102-LED-strip during uC sleep -
as the standby current of these strips is relative high.
The strip is directly powered via the 5 V from the USB powerbank.
Theoretically it can draw up to 2.4 A@5 V = 12 W.
In normal usage it will be ~1 A (5 W)
The uC (ESP32-S3) is a 3.3 V type.
I think I need a high-side switch for the LED-power path.
So I need a P-channel MOSFET with 3.3 V logic level and ~3 A or similar.
For this I found at my available/favorite reseller (reichelt.de)
IRLML6402PBF datasheet
IRLML9301TRPBF datasheet
AO3413 datasheet
First two labeled as logic level - third just found by price sorting.
Am I correct with my assumptions that all of these would work?
Am I missing something?
Every time I have to select MOSFETs I have to relearn how to read these datasheets properly and find the correct VDSon information.
So I am looking forward to some educational answers ;-)
AI: I think I need a high-side switch for the LED-power path.
I agree with that. A low-side switch won't work because the clock and data lines would also need to be switched.
Am I correct with my assumptions that all of these would work? Am I
missing something?
The design you have proposed is flawed. The flaw lies in how you hope to drive the p-channel MOSFET. The problem I see is that the p-channel MOSFET's source is connected to 5 volts but, the gate can be driven no higher than 3.3 volts hence, the MOSFET will not deactivate fully.
There are ways around this by using an extra transistor of course.
So I need a P-channel MOSFET with 3.3 V logic level and ~3 A or
similar.
Not really; the source is tied to +5 volts and you can easily pull the gate down to 0 volts so, a 5 volt logic level would work. The problem you have is that your proposed design cannot properly deactivate the MOSFET.
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H: pulse generator MATLAB
How to create a rectangular waveform with amplitude 18 to -3 using pulse generator? If I put 18 as the amplitude then the wave is between 18 and 0. How do I change that to 18 to -3?
AI: Make the amplitude 21 volts and subtract 3 volts DC from the pulse output.
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H: How to define the input common-mode voltage in this circuit?
I am trying to simulate the circuit below (from this paper) at the transistor level using a 0.18um, 1.8V process. The circuit serves as an amplifier for recording neural activities, and uses 2 capacitors (C1) to block DC offset and set the gain.
The OTA is implemented as below:
However, C1 also blocks the DC bias voltage that I set in the signal source, and keeps the input common-mode voltage close to zero. This makes the two input PMOS (M1, M2) work in triode region in my case (Vs is about 750mV), and significantly reduces the Gm of the OTA. The voltage gain is even less than 1 in my simulation.
I'm wondering if this is a problem of the OTA. Should the OTA be designed to operate at fairly arbitrary input common-mode voltages?
Also, is there a way to define the input common-mode voltage as I want (around 350mV) if I keep this configuration?
By the way, I just connected VSS to ground and VDD to 1.8V in my simulation, while in that paper they used \$ \pm 2.5V \$ supply. Don't know if this causes the problem.
AI: The opamp structure works in the paper because they use +/-2.5V supply for the opamp. If VSS becomes -2.5V for the OTA, the drain of M1 and M2 will move lower compared to the case where VSS = 0V. This will bring M1 and M2 out of triode and opamp will start working.
Edit: If you want to use 1.8V/0V for the opamp, you can try the following
Note that I have added 700mV reference instead of the 350mV that you mentioned. Reason is that if Vout = 350mV, you may have trouble biasing the output cascode and M6 transistors in your opamp.
In the real world, the 700mV will be from a bandgap reference which will have noise and one needs to simulate and check how much noise it contributes at the output i.e., Vout.
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H: Working of analog current monitor
Reference
I couldn't understand the implementation of current monitoring for this IC.
"The current source at IMON terminal is configured to be proportional to the current flowing through the RSNS current sense resistor."
Per my observations, there is no current source at the IMON terminal.
VOS_SET input referred offset. What is the need for this & what does it mean?
VSNS to VIMON scaling. What is meant by scaling in this context?
Why is the clamp set to 6.5V? As per the given range VVS -0.5V (Upper bound). VVS can go up to 80V or close to it as per the datasheet.
A simplified breakdown of the working would help me immensely.
AI: Per my observations, there is no current source at the IMON terminal.
Actually there is but you didn't recognize it. You probably accept that CS- will be at a slightly lower voltage than the input side of the shunt resistor (\$R_{SNS}\$) due to load current. Does that make sense so far?
Well, in order to get the op-amp into stability (Cs- = CS+), the voltage at CS+ can be "dragged-down" to equal the voltage at CS- by activating the p-channel MOSFET and taking some current from \$R_{SET}\$, through the MOSFET and down to ground via \$R_{IMON}\$.
Does that make sense and, do you see that this all happens automatically within a negative feedback loop. Hence, the current source at IMON is the op-amp and MOSFET working together.
Of course, that current taken from the CS+ pin flows to ground through \$R_{IMON}\$ and, the voltage produced is proportional to the real load current through the shunt resistor \$R_{SNS}\$.
Scaling refers to the current through \$R_{IMON}\$ compared to the actual current through \$R_{SNS}\$.
The offset of the op-amp represents an error factor. Ideally it would be 0 μV but nothing ever is that good.
It might help if you concentrated on the crucial parts of the circuit that dictate performance and, put some example numbers on things: -
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H: Is this a possible Leakage current problem
I have a question about the connection circuit between µ-controller and KSZ8851SNL.
Are the CSN and SO pins of the KSZ8851SNL tolerant inputs?
When Q1 is off, LAN3.3V was 0.9V in actual measurement. I think this is due to the current flowing through the internal protection circuit of KSZ8851SNL from the pull-up resistors of CSN and SO. In this case, is there any problem with the design?
AI: Yes, there is a problem, as the circuit is doing exactly the thing that the datasheet warns about what should not be done.
The datasheet does not say what happens if you do against the suggestion.
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H: Need help understanding the basics of electronics
I would like to state that I'm a beginner in learning electronics by reading my first book on electronics I'm lost and would like some help. I even included an image that would hopefully help my case.
By learning series and parallel circuit. What confuses me if we have a battery plus terminal and minus and one light bulb wire coming from positive terminal of battery connects to positive terminal on light bulb and negative terminal of battery connects to negative terminal of light bulb.
Why does in series circuit if we have for example 3 lights bulbs and one battery wire connects from negative terminal of light bulb to positive terminal of another light bulb I don't get it. In parallel circuit wire coming from battery connects to positive terminal of battery and negative to negative even if we have 3 light bulbs. But in series circuit light bulbs are connected with wire from negative terminal of battery to positive terminal of battery. I found out its because of light bulbs have no polarity. But LED lights have polarity and they are still connected the same way. I don't get it. To makes things easier I put some markings on image.
tmR.png
AI: '+' and '-' are relative designations. In your picture with the LEDs, the '+' terminal of the red LED is at the same potential as the '+' terminal of the battery (because they are connected together.) The '-' terminal of the red LED and the '+' terminal of the amber LED are at a lower potential. The '-' terminal of the amber LED and the '+' terminal of the green LED are lower still, and so on until you get to the '-' terminal of the battery which is the lowest potential of all.
If we put a ground symbol anywhere in that circuit, then the circuit node with the ground symbol is arbitrarily designated as 0V, and we can assign voltage numbers to other nodes to show how many volts above (positive) or below (negative) the node is with respect to ground.
Often, when there is a ground symbol, it is attached to the lowest voltage in the circuit (the '-' terminal of the battery in this case) so that all of the other voltages will come out as positive numbers.
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H: Altium: What do the different options under Properties (panel) -> General (tab) -> Type, mean?
Here is the image of the drop down list:
The "standard" is the default option. But what does Mechanical, Graphical and other options do?
AI: I might introduce to you the F1 key on your keyboard. Highlight the offending menu-item/button/drop-down, then press the F1 key on your keyboard. You'll get this:
Type - Select one of the following component types for the component footprint here. The available types are:
Standard - components that possess standard electrical properties, are always synchronized between the schematic and PCB (the footprint, pins/pads, and net assignments must all match), and are included in the BOM. An example is a standard electrical component, such as a resistor.
Mechanical - components that do not have electrical properties, are not synchronized (you must manually place them in both editors), and are included in the BOM. An example is a heatsink.
Graphical - components that do not have electrical properties are not synchronized (you must manually place them in both editors), and are not included in the BOM. An example is a company logo.
Net Tie (In BOM) - components that are used to short two or more different nets together, are always synchronized between the schematic and PCB (the footprint, pins/pads, and net assignments must all match), and are included in the BOM. They differ from a Standard component in that connectivity created by copper within the footprint is not checked; it is this copper that allows the nets to be shorted. Note: enable the Verify Shorting Copper option in the Design Rule Checker dialog to verify that there is no unconnected copper within the component.
Net Tie (No BOM) - components that are used to short two or more different nets together, are always synchronized between the schematic and PCB (the footprint, pins/pads, and net assignments must all match), and are not included in the BOM. They differ from a Standard component in that connectivity created by copper within the footprint is not checked; it is this copper that allows the nets to be shorted. Note: enable the Verify Shorting Copper option in the Design Rule Checker dialog to verify that there is no unconnected copper in the component.
Standard (No BOM) - components that possess standard electrical properties, are always synchronized between the schematic and PCB (the footprint, pins/pads, and net assignments must all match), and are not included in the BOM. An example is a testpoint component that you want to exclude from the BOM.
Jumper - components that are used to include wire links in a PCB design, for example, on a single-sided PCB that cannot be fully routed on one layer. For this component type, the component footprint and pins are synchronized between the schematic and PCB but the net assignments are not, and the component is included in the BOM. As well as selecting this option at the component level, both of the pads in the component must have their JumperID set to the same non-zero value. Jumper type components do not need to be wired on the schematic; they only need to be included on the schematic if they are required in the BOM. If they are not required in the BOM, they can be placed directly in the PCB where the Component Type is set, the JumperIDs are set, and the Nets manually assigned for the pads.
Also found on:
https://www.altium.com/documentation/altium-designer/schematic-part-properties?version=21&help-data=InteractiveProperties.Dlg.Altium_Designer_InteractiveProperties_Views_View_MainView.SchComponent
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H: Can I use a power bank of 5 V/3 A to power an Orange Pi 5?
I'm trying to build a portable PC with the Orange Pi 5 16GB RAM model with a touch screen and powered by a solar power bank.
I saw that the Orange Pi 5 requires 5 V/4 A to be powered, but I can't find solar power banks with 5 V/4 A, only some with a max. of 5 V/3 A. Can I use that power bank to power the Orange Pi 5?
The Orange Pi 5 will be connected to a touch screen, keyboard, and mouse only, since the other functions I want to apply are software mostly.
AI: Reddit says the 4A number includes a lot of load from the add-on ports (like USB) and 2A is enough if you aren't using lots of power from those ports.
This review concurs that the Orange Pi 5 by itself only uses up to 10W (2A).
USB-C tops out at 5V 3A, or 9V 3A, or 15V 3A, or 20V 5A if you have a high-quality cable. 5V 4A is not a standard configuration which is why you have a hard time finding a charger that says it can do it. It carries a risk of overloading normal USB-C cables.
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H: Does the remote control we have at home work with infrared (IR) frequency?
Picture source.
I was told by my AC's technician who several times came to my house to fix my air conditioner, especially if it got problem with the remote control or the board on the AC equipment. Once he explained how to see the infrared light by using a smart phone's camera. He demonstrated how to see if the remote control is working or not by pressing any button on the remote control and pointing it to the smart phone's camera, and we will see a something like violet color blinking fast.
I tried to fix it my self after the same problem previously occurred, the remote control is not working, then I searched over the net, especially on YouTube, and I found that nothing to do with infrared frequency with the remote control. The remote control is using an LED which is called IR LED, while in the AC's board installed TSOP4838, which it works on 38KHz, not in the range of 300GHz-430THz (above microwave but below visible light), the infrared spectrum in the electromagnetic spectrum.
Does that remote control really work in IR spectrum? If not, then why is the LED installed on the remote control itself and the TSOP4838 IR receiver on the AC equipment are called IR LED and IR receiver respectively?
AI: The IR light emitted by the IR LED in the remote is a bunch of (incoherent) photons, each with frequency in the hundreds of THz (i.e. wavelength around 950 nm). The LED is turned on and off rapidly at 38 kHz, meaning that 38000 times per second, the stream of hundreds-of-THz photons starts and stops. Finally, that 38 kHz pattern is itself turned on and off with various rhythms to encode different messages from the remote (i.e. power, temperature up, fan on, ...).
The 38 kHz frequency has a practical purpose - it makes it easier to detect the remote's signal against the background of IR radiation from sunlight, reflection, and other background sources.
There is no contradiction to the content in your linked video, which is focused squarely on the practical aspects of IR remote controls that an electronics hobbyist would care about. The photodiode/phototransistor in the receiver detects the photons, and produces a current proportionalto how many photons are arriving (not a hundreds-of-THz current!)1. As a result, it produces a 38 kHz signal observed by the oscilloscope/microcontroller.
Here's another analogy: just like how we modulate 300 THz (IR) with 38 kHz, you can shine a green flashlight (600 THz) at me, while turning the switch on and off at 1 Hz.
Even though your nerves, muscles and fingers cannot operate at 600 THz, you are still modulating a 600 THz signal. On the other end, the retinas in my eyes contain a light-sensitive molecule called rhodopsin, which produces a nerve signal when it gets hit by light around 600 THz. My nerves also cannot carry 600 THz signals, but they detect the signal from my retinas getting stronger and weaker at 1 Hz.
This is just like the photodiode/phototransistor in the electronics example - it gives off a 38 kHz signal when 300-THz photons start and stop arriving 38000 times per second.
In regard to your confusion about the TSOP4838:
in the AC's board installed TSOP4838, which it is works on 38KHz, not in the range of 300GHz-430THz
Actually, it does work at around 300 THz according to this figure from the datasheet (it's just given as wavelength2 around 950 nm, which is equivalent):
This device has two frequencies in its datasheet specifications: The light frequencies that its light-sensitive component is physically sensitive to (in the THz range), and the modulation frequency that its electronic filter is most sensitive to (around 38 kHz).
1 In a photodiode, each photon produces an electron-hole pair (thus causing an electron to flow through the circuit), not a 300 THz wave. A 300 THz electronic signal cannot be practically measured or sustained on a circuit board or electronic chip, let alone a hobbyist grade breadboard. It cannot be directly measured by an oscilloscope either. The modulation is optoelectronic - a photon-producing device is turned on and off at a rate that a circuit can achieve, and the demodulation is likewise optoelectronic - a photon-detecting device produces current as a result of electromagnetic radiation, even though that electromagnetic radiation cannot directly be passed to electronic circuits.
2 Wavelength and frequency are related via the speed of light using the equation \$c = f\lambda\$. 950 nm light has a frequency of approximately 315 THz.
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H: LED PCB footprint with non-symmetrical pads
This question is related to the LED component HL-AM-2835H489W-S1-08HL-HR3 from HONGLITRONIC. The datasheet for this part can be found here.
This component has a SMD2835 SMD package that I have not used before. Please see the footprint drawing given in the datasheet page 2.
The LED itself is fairly symmetrical when viewed from the top. However, the pads are not symmetrical. The only question is, where exactly should the mid point be in the PCB footprint while taking the tolerance into consideration. It seems that the mid point won't be in the gap between the two pads but rather on the right side pad.
AI: Center of footprint. Does that help?
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H: For sufficiently low duty cycle, can you get away with driving SCR above rated current as long as A^2 * s are maintained?
I'm wondering if the A^2-s rating of an SCR is what ultimately decides whether a given current for a given time is okay, even if the data sheet does not list such a number.
For instance, right now I am looking at a device that accepts an RMS on state current of 30 A. This device can obviously accept (30 A)^2 * (1 s) = 900 A^2-s. So, can I most likely get away with higher currents so long as pulse width < (1 / (current^2))? In this case, if pulse width T = 1 us, that suggests that 8 kA is okay because (8 kA)^2 * 1E-6 = 64 A^2-s < 90. Is that how that works?
AI: There are approximately three limits you need to stay within:
Thermal -- junction temperature must remain within ratings. Note you can't measure Tj while operating (except as inferred from terminal voltage and current, which aren't well enough specified to do this, you'd need to calibrate per part first), and Tj is NOT case temperature so you can't measure it externally -- there is temperature drop and delay between them.
Physical -- you must avoid effects like electromigration, hotspot formation, etc. I'm not sure what all mechanisms apply to SCRs in pulsed operation, but likely there are some things like this. These may be one-shot (exceed it and it blows up then and there) or repetitive in nature (e.g. electromigration can be pushed if low lifetime is acceptable). These are rarely if ever specified, unfortunately.
Rate -- if nothing else, current can only increase at less than the maximum dI/dt. If other limits pull in during that rising edge, well, the edge needs to stop then and there. The ultimate ratings (defined by the other limits) could perhaps allow a much taller square pulse, but this limit prevents a pulse from being too "square". And at the time scales you're asking about, an exponential decay (with or without ringing) is about all you're going to do.
The first limit is more or less described by surge or fusing ratings, and directly by thermal impedance if given. Surge × number of cycles is more or less equivalent, as well (for the >8.3ms range). Note that these ratings only provide discrete points on the thermal response -- i.e. 8.3ms half-sine pulse, which doesn't tell you anything about what's happening on the say 10µs time scale.
The second limit is sometimes described by a short-term pulsed rating. I don't recall if I've ever seen this on an SCR, but it is occasionally provided on regular rectifiers (say for a 1ms square pulse, or 10µs, or whatever). Again, doesn't tell you anything about time scales far away from this, but is at least a point on a continuum, so tells you a little about nearby time scales.
Regarding scales: heat spreads by diffusion, giving a P ∼ 1/sqrt(t) and E ∼ sqrt(t) characteristic. Time scales of 10s µs involve heat flow through the die itself; up to some ms, heat flow from die into metal tab / substrate; and 10s ms to 1s+, heat flow into heatsink, PCB and eventually the ambient. Within each regime, it's reasonable to expect the diffusion scaling, but between regimes, the thermal impedance can be higher or lower than expected, which is to say, don't try too hard to extrapolate from any given point.
One might rightfully wonder whether the fusing rating should actually be more like I2√t. Well, fuses are closer to I2t in behavior, so they're specified that way; and they open within some ms, so the scaling error can be tolerated. Again, I wouldn't try to extrapolate from this rating, at least not very far.
Of course, say if you only need one pulse ever, you may well be satisfied that the device fails shorted (or maybe it arc-flashes internally, but is still conductive enough to do the job), having switched that one pulse exactly as commanded.
As mentioned in the comments, the datasheet only specifies what it specifies; anything beyond that, you're on your own.
To be clear, you're more or less on your own anyway; datasheets aren't legal documents, and at best you could make a case for, I suppose, something like implied sales contract, or maybe false advertising, and basically refund the cost of parts you paid for (or a bit more as a class action perhaps, but that would be really out there) -- not counting legal fees of course, which would make such a plan utterly ridiculous.
Your best recourse is simply to contact the manufacturer and ask them about what you want to do. They may have documentation available, whether public that you didn't locate yourself, or private (perhaps subject to an NDA?).
Or you can do qualification testing in-house, but this is labor intensive, and needs to be done at least on a statistical sampling basis, as the manufacturer may change their design from time to time and they are under no expectation / obligation to preserve parameters not on the datasheet.
Which is really what it comes down to: the further you stray from the datasheet, the less confidence you have in the ratings you've extrapolated, and the less reliability may be. Various effects have different scaling factors: some proportional, some quadratic, some exponential!
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H: How do you use an RC filter on an LNA output to reduce unwanted noise?
We designed two low noise amplifiers, one at 144 MHz and another at 440 MHz using this LNA; each design is tuned for the particular band. We noticed amplification at 440 MHz is clean and crisp, but amplification at 144 MHz is scratchy with FM audio signals. (The 144MHz LNA measures S21=+28dB and S11=-19dB with a VNA.)
Someone at a conference we went to recently told us that an RC filter is often used on an LNA output to reduce unwanted noise in the intended band. Later I wondered what type of filter to use and how it should be tuned, but the conversation was in passing I do not have access to the person to ask directly. He said that RC filters on LNA outputs have been used for years, so it sounds like this is a common thing to do.
Primary question:
What is the best practice for RC filters on an LNA output? HP, LP, or BP?
What dB drop across the filter is acceptable (or necessary) in the passband to operate as an appropriate filter? (We get 28dB gain at 144MHz so, if necessary, losing a few dB in the filter isn't that critical.)
More detail mixed with my speculation
Here they are, outputs are on the female SMA side (with the flat-side of the PCB down, output is on the right):
Below is the matching schematic, roughly oriented to the 2m picture above. Notice that S7 is disabled in the schematic (and bare pads/missing in the bottom-right of picture above), so we were thinking of adding a cap to pull down higher frequencies (in lieu of an RC filter?):
This is the output match by itself, that shows a highpass behavior on the 270pF output cap with S7 empty (bottom right of the 2m PCB picture):
This is a simulation with a 22pF shunt cap in S7 (hoping to avoid a board-redesign, but we can if necessary):
There is a big issue with this 22pF shunt: In S2P simulation (no EM), it kills the S11 input match, going from -27dB to -10dB. Smaller shunt caps affect the match less, but of course with less high-frequency attenuation. (Not sure how the real life match is affected without trying it, thought I'd ask the experts here, first.)
Suggestions?
AI: very often, you'll want to do both – filtering before and after the LNA. Yes, when filtering before insertion loss is a problem (because it effectively reduces the gain of the first active stage, and Friis' noise formula doesn't like that), but in the presence of blocking interference, you won't get around it. Filtering after the LNA is still a good idea – a bit of power loss doesn't matter that much anymore for overall noise figure, and:
Someone at a conference we went to recently told us that an RC filter is often used on an LNA output to reduce unwanted noise in the intended band.
Exactly, because if you happen to have a strong signal at your amplifier, be it in-band or out-of band, that makes your amplifier a bit less linear.
Let's think about a second amplifier stage after your LNA:
Any non-linear amplifier (and amplifiers, even without a narrowband interferer saturating it, are always a bit nonlinear) is effectively a mixer (if you take the output/input function and develop it into a Taylor series, you see a quadratic term appearing: that's your mixer right there).
That means that a tone at 190 MHz and a signal at 430 MHz yield an intermodulation product at at \$430 \pm 290\$ MHz, i.e. at 720 MHz and at 140 MHz. And the latter you really can't use. (So, you would filter as much of the non-140 MHz frequencies to begin with.)
Problematically, the same applies to harmonics of 140 MHz (which you are interested in) and receiver noise:
non-linearity in your LNA makes 0 Hz and 240 MHz, 420 MHz …; and as you always have receiver noise, further down the line you'll mix your wide band noise back down to 140 MHz.
So: get rid of these harmonics! A low-pass filter is almost always a good idea after a mixer.
Best practices are really hard to give. Of course, a band-pass makes the most sense here, practically: you want one band, and not the noise above or below, and if there's any interferer that made it through frontend filtering, you'll have to get rid of it anyway.
How that's implemented is a pretty different question – as a mater of fact, so good a question that the whole principle of the superheterodyne receiver is based on making that band-pass filter sharp: Buy / build / tune a filter that is really good, and move the signal of interest so that it fits that filter. (Intuitively, I'm always tempted to design a filter to "fit" the signal; superhet is the realization that good analog filters are hard, and if you need superb selectivity, moving the signal to the filter's passband is what wins.)
But: compared to a complex thing like a multi-stage analog filter for 144 MHz, be it implemented directly at 144 MHz or by means of mixing and filtering at a different frequency, an RC low pass is "nearly free"! Note how far the first relevant harmonic is from 140 MHz: this is a really easy filter to "get right enough" to have a benefit. It would be a shame if you didn't add that filter.
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H: PCB manufacturing process: covering holes with soldermask
The PCB manufacturer is asking
These highlighted green areas (they are openings on the bottom soldermask layer) will be exposed in the bottom layer and you required us to cover the bottom layer with solder resist in the notes.
We suggest to delete these openings of the bottom soldermask layer and cover with solder resist as your requirement.
Are they talking about deleting the holes and covering with solder mask?
The red is the bottom layer
The green is the bottom solder mask layer
AI: Covering small vias with soldermask is also known as tenting. In Altium, there is an option to specify whether you want tenting on the top or bottom of vias in the Solder Mask Expansion section of the via properties panel:
I recently reinstalled Altium so I can attest to the Tenting option being turned off by default for at least vias added through the via stitching option.
Consult your fabricator for what the minimum size is that will accommodate tenting without causing manufacturing issues or voids.
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H: LED PCB footprint with non-square pads
The question is related to the datasheet for LED part number MHT151WDT. It is manufactured by Lianyungang Meihua Electronics Technology Co. Ltd. The datasheet can be found here.
The pg. 2 in this datasheet gives this drawing as guide to create the PCB footprint:
There are two issues:
What is really point of having a pad size containing 4 decimal places? This is mind boggling.
Why is there a circle drawn in the drawing where the pad copper must be exlucded?
This leads to one question:
How does one design a PCB footprint for this package in Altium designer? It is not clear how to cut out copper as per the circle diagram shown.
Note (on page 2):
All dimensions are in millimeters. (inches)
Tolerance is ±0.10mm(0.004") unless otherwise specified.
AI: This is called a reverse entry type. The LED is designed to project through the PCB to the bottom side to allow viewing from the bottom. I would use a rectangular pad with a small clearance from the hole. The connections remain on the top side.
The part is still technically on the top side to keep assembly on one side only.
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H: Best Processor for WiFi to GbE Bridge
I’m looking to build a WiFi to Ethernet Bridge, and did an initial test with a Raspberry Pi 4B. I noticed the CPU was always using less than 10% processing power, which makes me question whether or not I need a full Linux computer for such a computationally simple task.
I realize there are many types of processors out there (FPGA, MCU, MPU, DSP, etc.) is there one best suited to handle the high data/low calculation process of a WiFi to Ethernet Bridge?
AI: Linux is actually a good choice. Consider that many routers and similar devices run some form of Linux or can be modified to run DD-WRT.
This is also not a "computationally simple task". To me that might mean something you could run on a 4 Mhz Z-80. The Raspberry Pi 4B has a 1.8 Ghz 64-bit processor - 10% of that is equivalent to a lot of Z-80s. Plus you would not want a system where you have to run at even 50% of CPU capacity. It might mean you could back down to a Raspberry Pi 1 or similar and run at perhaps 20% - 40%.
What you don't need are the "extras" that make the difference between a bare-bones system and a Raspberry Pi 4B. All you really need are:
CPU
RAM
ROM (of some sort - flash memory, etc.)
WiFi
Ethernet
Power Supply
Anything else is superfluous. So you don't need:
USB ports (except one can be a convenient way to supply power)
HDMI ports
Expansion bus
And if you then manufacture it in large quantities, you get a very low cost per unit. If you are only building a few, a Raspberry Pi that includes HDMI, USB, etc. may be worth the extra few $ as the extra hardware can make development a lot easier.
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H: Very low frequency counter
I currently teach an introductory course to electronics that is mostly analog, but can incorporate some digital circuits. On our function generators, we have an arbitrary heartbeat shaped waveform and I thought it would be nice to try to make a heartbeat counter.
Obviously, the easiest approach would be to feed the function generator to any microcontroller and do the calculation using an ADC and code, but I want to create a simple electronic solution.
My first design idea revolved around the way nurses manually calculate heart rate over 15 seconds.
simulate this circuit – Schematic created using CircuitLab
Essentially, you press or use a monostable to count the rising edges over 15 seconds and you are left with a binary representation of that particular 15 seconds. It doesn't have any problem digesting the painstakingly slow normal heartrate frequencies (1Hz to 3Hz.) I plan on using a 74LS393 to count the pulses. If needed be, it is straightforward to increase the maximum value to an 8 bit format. We might have 8 bit counters sleeping somewhere, too.
It will not, however, behave in such a way that you can modify the frequency on the fly and see the output value change accordingly on a ''real time basis.'' The user will need to run another 15 seconds sweep.
In code, I would simply create a threshold, monitor a moving average divided by time and call it a day, but I need some inspiration to translate that concept into a circuit that is simple enough for first year technicians.
It is a small proof of concept and it can be completely flawed.
The heart wave is ficticious and free of noise.
Any ideas?
Post-Mortem:
The digital version of it worked properly.
The accepted answer worked also properly.
Finally, we also tested this circuit which uses a 555 to generate a monostable wave and thus we get a duty cycle value at the output and it worked too.
AI: Since you already plan to use code, you can just run a timer to find the time between heartbeats, and take the reciprocal to get the frequency. Of course you also need to scale the result to get beats/minute.
You might also explore various tachometer circuits, like the one shown here, although you would need to change the components by a factor of about 30 for heartbeats. 6000 RPM / 30 = 200 b/m.
simulate this circuit – Schematic created using CircuitLab
This is a simple way to get a voltage that changes with frequency from 1 Hz to 3 Hz (60-180 beats/minute).
It might be a good idea to see how long it takes for those frequencies to produce a stable output for measurement:
simulate this circuit
The output filter capacitor had to be increased to 470 uF to get a well filtered DC level. For 1 Hz:
And for 3 Hz:
This works well for a sine wave, but the heartbeat signal is probably more like a series of short pulses, perhaps 100 mSec, spaced 1 second to 300 mSec apart. The same circuit should work, but would be based on the duty cycle.
(edit) A practical implementation might trigger a one-shot on a transition of the heartbeat signal, so that the pulse width is not dependent on amplitude or wave shape, and duty cycle will be proportional to frequency.
simulate this circuit
(edit) There is also another possible method for reading low frequency signals with greater precision. A CD4046 phase locked loop in conjunction with a CD4518 dual BCD counter may be able to produce a frequency 100 times the measured frequency, so for a 1 Hz to 3 Hz heartbeat, it would provide 100 to 300 Hz, and a frequency counter with a 1 second gate would read 1.00 to 3.00 Hz. A 0.6 second gate would read 60 to 180 beats/minute, and a 6 second gate would read 60.0 to 180.0. For an example of this circuit, see:
https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1018089/cd4046b-frequency-multiplication-circuit-with-at-least-100-times-magnification
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H: How does CANopen support many devices with limited PDO
I'm pretty new to canbus and CANopen and can't seem to wrap my head around PDOs. I understand that a PDO must be defined and agreed upon ahead of time, and that multiple OD entries can be packed into a single PDO. What I'm not understanding is how only 4 PDOs could possibly be useful when a node can presumably have dozens of unique data it wants to be able to send.
An example to illustrate what I'm struggling with:
Say I have a network with 4 nodes. Each node is an environmental sensor that wants to broadcast temperature, humidity, air pressure, and ambient light (all 32 bit values). I can pack this data into 2 PDOs (let's call them PDO1 and PDO2. From what I understand these devices could send this data using COB ID 0x181-0x184 and 0x281-0x284 for PDO1 and PDO2 respectively with the bottom 7 bits indicating which device sent the data. Anyone receiving this data could look up the PDO definition to understand how to interpret the data and use the 7 LSB to know who sent it.
Hopefully so far so good.
Now let's say I want to add 2 more, unique devices- call it a power management device and an IMU- each with their own two, unique PDOs. At this point I have a total of 6 unique PDOs I want to be able to send and from my understanding this is not possible.
Again I'm not experienced with can but this contrived network seems extremely basic to me, yet it cannot be supported. Is CANopen just not meant to support many different types of devices or unique data? I can easily imagine even a single device wanting to send more than 4 PDO worth of data.
Note: I have seen reference to being able to support up to 512 PDOs so I suspect I'm missing something fundamental but I'm not sure what it is.
AI: What I'm not understanding is how only 4 PDOs could possibly be useful when a node can presumably have dozens of unique data it wants to be able to send.
You're not limited to only 4 PDOs. The CANopen standard defines 4 default RPDOs and TPDOs.
The default PDO communication parameters are:
RPDO1: object 0x1400
default CAN-ID: 0x200 + NodeID
RPDO2: object 0x1401
default CAN-ID: 0x300 + NodeID
RPDO3: object 0x1402
default CAN-ID: 0x400 + NodeID
RPDO4: object 0x1403
default CAN-ID: 0x500 + NodeID
TPDO1: object 0x1800
default CAN-ID: 0x180 + NodeID
TPDO2: object 0x1801
default CAN-ID: 0x280 + NodeID
TPDO3: object 0x1802
default CAN-ID: 0x380 + NodeID
TPDO4: object 0x1803
default CAN-ID: 0x480 + NodeID
Apart from these default PDOs, you can implement up to 512 RPDOs and 512 TPDOs per device. The ranges 0x1404..0x15FF and 0x1804..0x19FF are reserved for manufacturer specific RPDOs and TPDOs, respectively.
From what I understand these devices could send this data using COB ID 0x181-0x184 and 0x281-0x284 for PDO1 and PDO2 respectively
The COB-IDs 0x181..0x184 are the default TPDO1 CAN-IDs for nodes 1 to 4. And COB-IDs 0x281..0x284 are the default TPDO2 CAN-IDs for nodes 1 to 4.
An important thing to note: you're not limited to use the default CAN-ID scheme (eg. 0x180 + NodeID for TPDO1, etc.). You may configure any CAN-ID in the range 0x180 .. 0x57F for any RPDO or TPDO.
Another thing to note: you can map any TPDO to any RPDO of multiple CANopen devices. If a device doesn't need all data mapped into the specific TPDO, it can configure RPDO dummy mappings to ignore certain parts of said TPDO.
EDIT 1
Going back to the environmental sensor. Let's say I've now defined two custom TPDOs for the data that I want these sensors to be able to share. How do I differentiate between PDOs I receive from different devices?
PDOs are differentiated by their CAN-ID. You can map a TPDO of one device to an RPDO of multiple other devices. You just have to make sure the RPDO COB-IDs match the TPDO COB-ID.
As an example, let's assume you've configured a TPDO with a COB-ID of 0x181. You can now configure multiple other CANopen devices to have an RPDO COB-ID of 0x181. This means said TPDO will be mapped to all other devices having an RPDO configured to have the same COB-ID as the TPDO.
Do I need to manually reserve N addresses between each PDO to allow for the node ID of each node to be added? In that case, the more nodes I have, the fewer PDOs I can represent? Is that correct? For example, with a full bus of 127 devices, only 8 PDOs (4 default + 4 custom) could be supported by all of them?
You have a total number of 512 RPDOs and 512 TPDOs per device. But overall the PDO COB-ID range spans 0x180..0x57F, which means there is a system-wide number of 1024 PDOs. These have to be shared among all 127 devices. Theoretically, if two devices use up 512 TPDOs each, there won't be any TPDOs left for subsequent devices.
If the 1024 TPDOs containing 8 bytes each isn't sufficient, you might want to consider upgrading your CAN bus to CAN FD.
EDIT 2
Just to be abundantly sure- if I have a device that I want to transmit 16 x 64-bit values using PDO, this would require 16 PDO addresses. Now if I wanted to deploy many of these devices on the same network, I would be limited to supporting (512/16=) 32 devices. Is that correct?
First of all, I had to correct a mistake above. Per device you can configure up to 512 TPDOs and 512 RPDOs. But system-wide you have 1024 TPDOs and 1024 RPDOs (range: 0x180..0x57F) available.
If each device uses 16 transmit PDOs (16 x 64-bit), you could support up to (1024/16=) 64 devices.
The question is, do you really need to transmit all 16x 64-bit values using PDO, or is it possible to partially use the SDO protocol?
It seems like a lot of careful planning is required to define the OD and PDO mapping for each device to ensure none overlap and that the host is mapping each to an RPDO. Can you recommend any resources to learn about how this is done?
If it's really this straightforward, so that each device uses 16 TPDOs, I'd keep it simple and assign COB-IDs 0x180..0x18F to node 1, 0x190..0x19F to node 2, ... 0x570..0x57F to node 64. The RPDOs have to be configured appropriately, to whichever devices needs the TPDOs.
For questions regarding the CANopen application layer and communication profile, I always consult CiA 301.
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H: 10/100 Ethernet Routing Review
I know it is a big favor to ask, but this is my first ethernet design, so could you provide input on the routing from connector to mag and from mag to PHY? Is it fine or how can I improve it?
Really appreciate it!
And this is the schematic for reference:
AI: 10/100 Ethernet is wonderfully forgiving. It's good to practice the best design you can though.
Something that justme has already noted, the magnetics has identical transformers in it that you can swap around, so you can do this in order to have to avoid jumping traces. I'm not sure I'd jump with resistors, if I had to I think I'd use Vias and go to another layer, the differential pair underneath is going to interfere even if there's no cross-talk. Check and be 100% sure first, but plenty of ethernet controllers can handle polarities and pairs being swapped, so sometimes you even have this flexibility.
Something you mentioned in a comment is trace length matching, and this is something you should do. Though I imagine on the scale you're using it's a bit irrelevant, but it's still good practice.
D1 and D2 look like ESD clamping diodes to me. While I can't imagine they'll cause issues, assuming you're using magnetics with isolation, there's really no need for them.
It does seem odd to me that you have series capacitors C9/10 on the RD+- pair, but not on the TD+-. Check this, if this is how the manufacturer of the W5500 tells you to do it then fine, I'm just checking this is deliberate. Similarly you've got pullups to 3v3 on the TX pair, but -VA on the RX pair, and again with the centre tap voltage. Do you have a reference design you're working from? Normally these are identical, in my experience.
[edit]
I've had a chance to look at the reference design (which you should edit your answer to include) and I can see the pullups/pull-downs match the reference, so that makes sense. I do also notice that you've used -VA and GND, instead of something like GND and CGND (like in the reference design), which I would recommend for readability, it makes it much clearer.
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H: Exposed pad and ground
I'm using this device - ATSAMD21G17A
While I measured the connection between the exposed pad and ground, they seem to be unconnected.
When I went and check on section 10, problem 20, on page 30 of this Checklist, I found the below:
Which effectively says us to connected the exposed pad to ground pins of the device and the PCB.
My question:
Should the exposed pad of a device always be connected to the ground? If so, why?
If the exposed pad should always be connected to the ground, then why do manufacturers, in this case, Microchip, do not connect the exposed pad and ground pins of the device together internally?
Like, is the exposed pad solely for thermal dissipation or does it serve as a ground pin as well?
Can the exposed pad be left floating in any case, if I am taking care of thermal dissipation?
AI: In general, the die is made of P-doped silicon, which forms diodes with the N-doped silicon of microelectronic components, so the substrate must have the most negative voltage in the device. Therefore, the substrate is usually connected to ground (or to the negative supply in op-amps).
The exposed pad is connected to the substrate with glue that might be electrically conductive. (The glue is chosen for its mechanical and thermal properties, not for its electrical ones.) So the pad could be left floating, but if it is connected to any voltage, it must be ground. So when you need a large amount of copper for thermal reasons, the ground plane is the obvious choice.
Creating an internal connection between pad and ground would make the packaging more expensive. (The pad is under the die; normal bond wires would not work.)
Other manufacturers like TI mention some of these considerations in a FAQ, but it is easier to simply say "connect it to ground".
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H: Connecting TTL-232R-5V-PCB to STM32F103C8T6A bluepill via OTG and installing boot to this STM32 microcontroller
I have TTL-232R-5V-PCB and STM32F103C8T6A bluepill board. I am working on installing bootloader to this bluepill board on that way, I have searched on the web about it but all people connected them via jumpers from TTL to some pins of STM32 bluepill board. Could it possible to connect in this way?
AI: No. It is unknown what that adapter of yours does, but you can't connect with an UART to the F103 USB pins for any useful purpose.
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H: Continuous current limiting with hot swap controller
I am using a brushless DC motor which has its own integrated controller (nominal current 4 A at 24 V). To protect the motor, I'm willing to implement some current limiting circuit (e.g. with maximum allowed current 5 A).
The TI LM5069 hot swap controller (link), looks interesting, and ticks some other of my requirements as well (under and over voltage protection, short protection). From what I understand, it is initially intended to perform current limiting for a set period of time, after which it will consider that a fault happened and will enter a restart procedure. However in my case I would like to stay in current limiting mode for as long as the current is too high, without stopping (say for example when my motor is running at its maximum allowed power).
On this chip, the fault timer is set by a capacitor, which gets charged when current limiting is occurring, and by monitoring the voltage on the TIMER pin. See extract from datasheet:
8.4.3 Fault Timer and Restart
When the current limit or power limit threshold is reached during turnon or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation. When either limiting function is activated, an 85-μA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 25 (fault timeout period). If the fault condition subsides during the fault timeout period before the TIMER pin reaches 4 V, the LM5069 returns to the normal operating mode and CT is discharged by the 2.5-μA current sink. If the TIMER pin reaches 4 V during the fault timeout period, Q1 is switched off by a 2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on which version of the LM5069 is in use.
Questions:
Instead of using a capacitor to set the fault period, would it be possible to pull the TIMER pin low (see image below) to prevent the chip from timing out when in current limiting mode?
If so, would it be safe for the main MOSFET Q1? I assume it could be selected to handle the maximum allowed current over a long period of time?
If not, is there an easy alternative to get the intended behavior, or would I need to design a dedicated circuit for it (e.g. something like these (Wikipedia), or as seen many times on this forum)?
Thanks in advance!
AI: Instead of using a capacitor to set the fault period, would it be possible to pull the TIMER pin low (see image below) to prevent the chip from timing out when in current limiting mode?
The timer pin is not really strictly an input. It's a current source used to charge a capacitor over a period of time to control the power on sequence (see 8.4.1 Power Up Sequence), fault timer and restart (see 8.4.3 Fault Timer and Restart), and timing for the power/current limiting functions (see 8.3.1 Current Limit and 8.3.3 Power Limit). The particularly challenging part would be to accommodate the power up sequence and handle the restart sequence.
For the power up sequence:
the TIMER pin
is initially held at ground. When the VIN voltage reaches the PORIT threshold (7.6 V) the insertion time begins.
During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 5.5-µA current source, and Q1 is
held off by a 2-mA pulldown current at the GATE pin regardless of the VIN voltage. The insertion time delay
allows ringing and transients at VIN to settle before Q1 can be enabled. The insertion time ends when the TIMER
pin voltage reaches 4 V. CT is then quickly discharged by an internal 1.5-mA pulldown current.
You could have a timer cap that is nominally connected to the timer pin and then use a controlled FET to short it to ground once the power up sequence has been completed. However, you would need a way of determining if/when that has happened an act appropriately.
The further trouble will be with the restart sequence as given by the below figure:
If using the timer capacitor bypass technique outlined above, you would need to re-connect it to allow the device to safely restart in the event of a fault. Faults like the "circuit breaker" and UVLO features would need to be recovered from with the restart sequence.
To answer the question directly: if you want to use this chip as you've described, it will take considerable effort using an MCU or other controller to bypass the timer capacitor only during the events you want. You'd need to track the states of the IC with a state machine and tightly control when the capacitor is bypassed and when it is connected. More effort than, in my engineering judgement, I think is warranted for the functionality.
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H: PCB fab questions: Surface finishes and reasonable source for a single board
I've designed a unique Stylophone-type keyboard. I've prototyped it on Masonite with copper foil tape. Now, I'd love to get a slick PCB fabricated. It's a large board, but I feel like, as a hobbyist, I'm just a complete annoyance to the places I've been contacting for quotes, because, well I don't know everything, and I've got questions.
My main question, at the moment, is about surface finishes. I plan to solder an array of tuning trim pots and fixed resistors to the board myself. But, the board has very large 'key' pads. It would be nice if the copper pads had a finish that prevented the copper from oxidizing. But, am I correct in thinking that "Lead-free HAL,' for instance is a solder finish that I would NOT want or need on those key pads?
Any suggestions for congenial, reasonable fab shops that have no board minimum would also be greatly appreciated.
AI: These days, the go-to places for prototype PCB fabrication are JLCPCB, PCBWAY, Rushpcb, Expresspcb, or similar online-process sites. If there's no way to quote and submit the job online, don't bother - it won't be cost effective for them to take your business.
Any online PCB fab shop will have an explanation of available surface finishes. You do not want bare copper - it will oxidate/corrode rather quickly and will look pretty bad, with fingerprints etched into the surface etc. ENIG (electroless nickel-under-gold) would be a nice finish - a bit more expensive than HA[S]L, but hey - shiny! :)
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H: I need to make a makeshift thermocouple given limited resources in the third world
I'm living in a part of the world where scrap electronics are hard to come by. Recycling these are big money in the impoverished SEA region I'm living in.
I have a Fluke 289 with a type K thermocouple that is reasonably precise. I really don't want to cut this and re-weld until I have to as the cable is really not very long to begin with.
Basically, I have access to a lot of aluminium wire, steel wire, some copper wire, some lead/tin alloy solder wire, and some very thin unknown alloy of nichrome I could take from inside a small power resistor. It's so thin though, like 44 AWG maybe.
I'm in need of a thermocouple that can give at least 10 mV of change in potential with only 1-2° C change at the welded junction. I can use my Fluke to calibrate this hackjob of a thermocouple.
Basically, I'm just asking if I can get anywhere near enough potential change using the materials at hand in order to trip a comparator to turn on a circuit.
The application is low temperature; I'd like to maintain 37-39° inside an insulated box at all times.
Some rudimentary experiments have yielded very poor results using copper and aluminum. Like 5-10 of millivolts across a 20° temperature change. I could get a lot of nuisance tripping with stray RF and parasitics at those low levels.
I haven't attempted to spot weld a junction yet but I can do so with the materials at hand.
AI: A thermocouple is an extraordinarily poor choice for measuring and maintaining a temperature in that range unless there is something very odd you are not divulging.
A thermocouple front end consists of the thermocouple itself, a “cold-junction” temperature sensor which generally measures the temperature where thermocouple materials transition to copper (eg. terminal block or connector) and some circuitry to amplify, combine and/or digitize the two inputs. The effect of the CJC sensor on the measured temperature is very close to 1:1 for most thermocouple types under typical conditions.
In your case you might be able to just use the CJC sensor to measure the chamber temperature and avoid the thermocouple entirely. A diode-connected transistor makes a reasonable to good temperature sensor in that range, depending on how you use it (~ -2mV/K to -200uV/K), and even a cheap 1% precision thermistor will outperform most thermocouple circuits. An RTD is more stable again. Both the latter can be had via mail for a few dollars.
If you would like to play with thermocouples for educational purposes, you can multiply the sensitivity by creating a “thermopile” with many junctions connected electrically in series. Type K is around 40uV per K so you would need many junctions to approach mV/K. You also need many “cold” junctions, so many pieces of wire thermally in parallel transmitting heat from hot to cold junctions- that’s the inescapable thermodynamics of the situation. You can make the wires as thin as you like to try to decrease errors due to heat transfer and the voltage won’t change, however the source resistance will increase. I would expect the materials you mention to be similar to worse to type K- iron is one additional material you could try. The traditional laboratory approach to the CJC is to immerse the cold junctions in an ice-water slurry, thus maintaining them near 0 degrees C. Not very convenient, but it can be relatively accurate with crude resources.
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H: What do dashed lines mean in the schematic?
This is a "6-pin self-locking push button", but I don't know what dashed lines mean (those that are in the schematic).
AI: It looks like the solid lines are the connections in the "normal" or unpressed state and the dashed lines are the connections in the pressed state. The datasheet may state this explicitly.
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H: Value of output capacitance via Miller approximation
There is an example in Razavi's textbook (Design of Analog CMOS Integrated Circuits 2nd edition) demonstrating the Miller effect/approximation, shown below.
As you can see the example claims that the Miller output capacitance is given by \$C=\frac{C_F}{A+1}\$. However, I think that the correct value for this capacitor should be \$C=C_F (1+A^{-1})\$, since the Miller approximation describes the output impedance as \$\frac{Z_0}{1-A^{-1}}\$, where \$Z_0\$ is the impedance before the transformation.
This isn't listed in the most current errata that I'm aware of. I'm also aware that part of the point of this particular example is to show that the Miller approximation can introduce errors like extra poles/fewer zeros, but either way I would just like to confirm if the capacitor value here is an error or not. (Contrary to the figure above, the rest of the example actually uses the value \$C=\frac{C_F}{1+A^{-1}}\$, which still seems incorrect.)
Update: Prof. Razavi has confirmed to me via email that these are typos. As of this update the errata haven't yet been updated.
AI: You're correct, it's a typo on his book. Which version do you have? he didn't correct it in the 2016 one?
We can prove it easily by writing a KCL equation on his simplified schematic (I used Vin instead of "X"):
$$
\frac{V_{out}-V_{in}}{Z_{C_f}} = I_{out}
$$
If we let \$V_{in}=-\frac{V_{out}}{A}\$ and \$Z_{C_f}=\frac{1}{sC_f}\$ and do some arithmetic manipulations, we arrive at:
$$
\frac{V_{out}}{I_{out}}=\frac{1}{sC_f(1+A^{-1})}
$$
In short, \$C_f\$ is scaled by a factor of \$\frac{A+1}{A}\$, or, in other words, its value remains almost the same when seen from the output at low frequencies and assuming \$A\$ is large.
EDIT:
2 Sanity checks.
With LTSpice
I setup the following schematic using an ideal gain of 100 and a coupling capacitor of 100pF.
These are the results I got:
The one with "V(out_1)/V(in1)" is the approximation I used with the formula I derived above.
I realized I used positive feedback in the examples above, but that's not important as the aim was to just only estimate the poles, not designing a proper amplifier.
Razavi himself writes this formula in one his video lectures (the second he does is already included in the link)
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H: How does MOSFET gate-drain capacitance behave?
When a voltage is applied to MOSFET drain, Cgd acts as closed switch and for a short moment raises the gate voltage to drain voltage. Is this statement true?
In Falstad circuit simulator (see simulation here), I added Cgd to simulate a real MOSFET and these short bursts of charging/discharging cause oscillation in the circuit.
Is this a real world issue or is it just the simulator?
simulate this circuit – Schematic created using CircuitLab
AI: It seems unrealistic to me that the Cgd would bring Vgs up to the full drain voltage (Vds) applied, simply because Vgd and Vgs would form a capacitive divider and there would have to be at least some reduction in voltage on the gate compared to drain voltage.
You didn't specify voltages, capacitances, any values in your simulation nor a screenshot so that we can better analyze your problem. I can only guess it has something to do with drain voltage being high, Cgd being large and maybe the Cgs being omitted.
The drain voltage influencing gate voltage through Cgd is realistic and possible if Cgd and Vd are large enough to charge the Cgs up to the Vgs threshold voltage and there is nothing loading or grounding the Vgs.
It is a real-world issue which can cause unwanted turn-ons, turn-offs and oscillations, and that's one of the reasons why there is at least a resistor between gate and source, and why it is recommended to have a low-impedance drive that brings the Vgs as low as possible and keeps it low when MOSFET is supposed to be off.
Even though Cgd is smaller than Cgs, the Vd typically being significantly higher than Vgs threshold voltage is what makes it more influential over Cgs, as you know from the formula Q=CV that a charge is a product of both capacitance and voltage applied, so even if Cgd is 10 times smaller than Cgs, a 10 times larger Vds than Vgs will give Cgd a charge equal to the charge on Cgs.
Let's assume 12V on drain, 0V on source.
Let's also assume a 4V Vgs threshold.
As the gate voltage rises from 0V to 4V, the capacitor Cgd discharges to about 8V. Vd will be 12V, Vg will be 4, meaning Vd is 8V more positive than Vg.
When MOSFET starts conducting, Vd starts going towards 0V, but since it is 8V more positive and the Vg is therefore 8V more negative compared to Vd, it will pull the Vg towards 0V, thus turning the MOSFET off.
In reality, Cgd is significantly smaller than Cgs, and any driver capable of turning a MOSFET on is also capable of overcoming this negative feedback and keeping the MOSFET on.
This interplay between Vg and Vd through Cgd in the real world can be seen in the gate voltage turn-on transition curve below:
(image linked from Analog Devices page: "Isolated Gate Drivers—What, Why, and How?")
You can see how the gate voltage rises until the MOSFET starts turning on, which drives the Vd down to Vs and which in turn takes away from the Vg by Cgd discharge, keeping the Vgs flat for a moment until Vd reaches Vs and then the Vg continues to rise further towards the gate driver's output voltage.
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H: Why do I need to ground GP0 to enter programming mode in ESP8266?
I have an ESP-01 chip. I found out that I need to ground the GP0 pin to enter the programming mode to flash a program to the chip. I can't find anything in the ESP8266 datasheet that documents this. I'm wondering how we know that we need to ground this pin to be able to program the ESP.
AI: Try pressing CTRL-F in the PDF reader and find for words "BOOT" or "GPIO0".
On page 11 it finds this:
GPIO2, GPIO0, and MTDO are used to select booting mode and the SDIO mode
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H: Correct orientation of EMI filter
The label of this EMI filter seems reversed to me because in the diagram there are three pins on the side of the line but the are two wires on that side of the device.
Is there a way to determine the correct orientation? I did some tests with a LCR meter but I measured around 100 nF on both sides trying different frequencies.
AI: The schematic on the label has the load on the two-wire side, so yes, somebody stuck the label on backwards.
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H: What happens if a dependent current source has a negative value?
When I try to solve some circuit exercises, I receive a negative number for the dependent current source (meaning the direction of the source is wrong, maybe).
Is this a wrong solution or is nothing wrong (meaning the direction of source draw in the exercise is not important -- if the value is negative, just redraw the direction of source)?
AI: When you don't know the direction of the current then you make an assumption. If it turns out to be negative then, yes, the current is going the wrong way. You don't have to fix it as long as the value shows that it is going the opposite direction.
simulate this circuit – Schematic created using CircuitLab
The circuits above are identical other than the direction and sign of their current sources.
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H: Are lithium-ion battery cells' maximum discharge ratings based on heat?
For any given lithium-ion battery cell, would I be able to discharge more than its rated maximum discharge value provided that it's for a brief time and/or the heat does not rise up and be sustained by a certain amount?
Like for instance if I discharge a 10 A battery at 10.1 A for just one second, and stop for 100 seconds, and do it again repeatedly, would there be any long-term chemical damage?
AI: In general (not just batteries), you cannot increase the current and reduce the time interval ad infinitum because material construction is imperfect and non-homogenous and it takes time for heat generated to to spread out and equilibriate. Heat is produced instantaneously and unevenly in the material due to these imperfections and it takes time for the heat to travel and equilibrate across the material; Time which component does not have if you keep shortening the time interval and this will generate hot spots which will fail and the dominoes start falling from there.
And 1 second is an eternity in electricity and heat generation, but not heat transfer.
Also note the way ratings work. It's not a hard universal physical limit. All ratings are obtained under some set of criteria. This criteria includes what the designers have deemed as an acceptable compromise between wear/degradation and performance for size or mass for the expected application and operating environment. So if the battery was expected to be used in a colder or or windier environment the same battery might be rated for higher current than if it were expected to be used in a warmer or more enclosed enclosed environment. Or if the battery was intended for an application where it needed to be much more reliable or last through many more charge cycles the battery might be rated for a much lower current than a less critical, more disposable application. Yet, the battery might not be physically changed at all.
There is also variance between individual components which produces variances between the component under test used to obtain the rating and the actual component you have in hand. So 10A vs 10.1A is probably meaningless, whereas 10A vs 100A is not.
So, to answer your question about whether it causes long term damage/wear: It depends on how how conservative the rating criteria is relative to your intended usage, your criteria for acceptable wear/damage, and how close you are to that thermal generation vs time threshold. So in some cases you can push it, and in other cases you can push it more if you are willing to accept the increased wear. Applications that are disposable or run for short-time can push batteries especially hard for their size (torpedoes, missiles, etc).
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H: Can you use a diode to cancel the body diode of a MOSFET?
From what I understand, MOSFETs inherently have a diode between the source and drain known as a body diode. If I were to use an nMOSFET as a low side switch, would it be bad to have a diode between the load and the drain of the MOSFET? What effect would it have?
Schematic is a representation only and is not intended to produce accurate simulation results
Edit to clarify comment:
The goal is to enable 2 low side switches (not at the same time) to switch between 2 rgb controllers. Originally I wanted to multiplex between the 2 controllers, but the couldn't find any with a large current rating. Without D1 and D2, the switching of controller 1 would affect current through controller 2 and vice versa. If there's a better way to switch between low side switches I am open to suggestions. (RGB Led should be LED Strip. Resistors are embedded)
AI: It would decrease the max voltage across the load by a voltage equal to the forward voltage (Vf) of D1. One reason I can think of to do this is if whatever the load is cannot handle the full Vdd across it.
I'm not sure what you mean by "cancel the body diode". When the FET is fully enhanced, it will effectively short out the diode and current can move through the FET in both directions. When the FET is off, the body diode is just like a power rectifier; it will pass current in one direction. In your circuit it will be reverse-biased by Vdd, so there will be no electron flow with or without D1.
If you have a situation where it is possible for both positive and negative current to appear across the FET, and you want to block both directions when the FET is off, such as reverse-polarity protection of a power supply input, then D1 will do this in the circuit as shown. There are two better ways to do this.
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H: Signal saturating after transistor amplifier
I'm trying to amplify this noise coming from Q1 but it looks like it's saturating at the collector of Q2 (as you can see in the image). How can I resize the resistor values such that the signal does not saturate?
I have 11.8V at the collector.
simulate this circuit – Schematic created using CircuitLab
AI: You have omitted some things in your original schematic.
Here is your schematic with my notes:
simulate this circuit – Schematic created using CircuitLab
I fail to see the reason for a voltage divider. You only have 24V but you want 12V?
You didn't connect the C2 and C3 with R2 and R3 to complete the voltage divider.
Is bottom, negative side of the 24V supply supposed to be ground or is it the lower end of R6?
R5 was 4.7Ω, but I'm sure that was a typo, should be 4.7kΩ.
Here is a better, working schematic:
simulate this circuit
The values for this circuit are from https://www.eeweb.com/simple-white-noise-generator/
Their schematic is the same:
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H: Spice transient vs AC models
In process of designing an electronic or a mechatronic system, we take into account AC analysis and Transient analysis of that system. In my case, I want to design a speed and position control system for a DC motor. I went through the theoretical analysis of my system by taking into account:
The electrical and mechanical characteristics of of the motor.
I have designed a theoretical controller for each: "Inner current control loop", "Inner speed control loop" and "Position control loop".
I have simulated my system using Matlab and I got a satisfactory result.
Now I want to simulate my system using component models, by using any well known electronic simulators like: LTSpice, Simetrix/Simplis. but when I come to component selection, specially Gate Driver ICs or Motor Driver ICs I do not find SPICE models of these components.
If I search on the internet, I am surprised to find that most companies provide transient rather than average models.
See the example in the following link:
https://www.ti.com/product/DRV8701#design-development
Texas instruments provides three different Transient models but no one AC model.
My questions:
Why it is easy to find a Transient SPICE model rather than AC model?
Why companies do not provide AC models of their components to allow designers to incorporate these components in AC analysis of the whole system?
How can I take advantage of the transient models to validate my simulation work for implementation?
AI: Consider what you are asking for: you desire an average AC model, but the device in question has 20-some pins on it. Which pins are you expecting a model through? Under what mode/condition (driver, PWM current limiter) shall it be linearized or averaged? How many combinations of pins should they model for reasonable completeness across all end users that desire this type of model? And how many people will actually make use of such models, when a reasonably complete* transient model is provided instead? (That is, even if such a model is reasonable and meaningful, it might still not be worth crafting because too few people will make use of it to justify the expense.)
*Assumption.
And, what are you really asking for? -- A PWM cycle-averaged model of a gate/motor driver is just a buffer, give or take some phase shift due to propagation delay, and some gain factor due to modulator gain (if applicable). Besides the current limiting function, these components are trivial in such a model; were you expecting more?
Also be careful about what kind of "AC" models you are asking for. SPICE does not require models specific to this, because it performs linearization on the system automatically, using a small-signal steady-state assumption. Note that a switching circuit has approximately zero gain under this method (i.e., consider the gain of a logic gate where its input voltage is below the logic threshold), so you will be disappointed with the results from this analysis, if you use device models. (So, you are correct, with respect to your assumption that transient models will not work as-is for AC/average purposes.)
AC Analysis is only applicable to passive and analog circuits, where bias (operating point) is easily calculated from the circuit as given, and the small-signal frequency response is desired.
In contrast, as you move from simplified average models towards a practical PCB design, you must consider transient conditions within a switching cycle (peak current flows and voltage drops due to stray inductance from the layout and other component strays), cycle-to-cycle variations (e.g. ripple current, for purposes of dimensioning supply components), and quasi-steady-state conditions (e.g. heat dissipation of devices, for component selection and thermal design purposes). Few things which your average or AC model
The only duty you have at this later [implementation] stage, with respect to the earlier (average) model, is to show that they still exhibit the same averaged dynamics. Which I think you will find is a much simpler task than all the other considerations the transient models bring, and ultimately the whole design.
I'm also assuming this is in academic context, or perhaps a high-reliability design context, given the emphasis on modeling. In contrast, much practical engineering is done on assumptions and testing. If you are in fact doing the latter, I would suggest not worrying about it, and concentrate on solving implementation issues (with or without simulation).
Finally, keep in mind what you stand to learn / develop from a given model. If I understand your meaning correctly, then about all you're going to find from your average model is just the compensation components for the respective control loops. That's, at most, 9 PID parameters total across your three loops (or equivalent R and C component values if analog, or perhaps more parameters if more complex controllers are chosen). Whereas the complete design might involve, what, 50 or 100 components, or more? So the average model can only helping you with say 10% of the overall design -- a small part of the whole. And, you can assume those values will have to be chosen somehow, and just leave them as placeholders -- deferring choice of values until final modeling, or even "tune" them in testing.
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H: TP4056 ON/OFF Switch not fully working
I was testing the PCB of an electronics design (attached) when I noticed that when I put SW1 into the "OFF" position, there was still a small voltage (~1V) on U37 (MT3608 boost converter) which was boosted to about ~3V and as such my microcontroller did not turn off (I disabled brownout detection).
I did a quick test with the multimeter and it seems that there was still a closed circuit (albeit with high resistance of 7M) between the legs of the switch. I desoldered the switch to test if the switch was faulty but it was not and the PCB pads themselves still show the same resistance (not fully open circuit).
The only chip that is in "contact" with SW1 is U5 (TP4056). As such I suspect that the TP4056 is providing some path for a small amount of current through GND or via LED1 and LED2. I desoldered both LEDs and the problem persists, leading me to suspect the former. Moreover, I tested a blank PCB with no components soldered on and there is an open circuit between the 2 legs, meaning that is most definitely a component that is causing this.
Has anyone experienced something similar with TP4056? How can I modify my circuit/placement of the switch such that the load is fully turned off when the switch is opened?
A potential workaround would be to set a higher brown-out detection on the ATMEGA328P so that even with this small voltage it would not turn on.
Thank you for any advice in advance! :)
AI: The battery positive is connected to MCU GPIO pin.
It will power up the MCU, via the MCU internal protection diode from that GPIO pin to VCC.
Also the USB connector ID pin is ìncorrectly connected to signal that this device is always the host.
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H: Virtual ground in non inverting op amp
Why is the voltage not equal in inverting and non-inverting terminals in a non-inverting opamp? During the derivation, we take two different V1 and V2. Why doesn't virtual ground apply here?
AI: In both of the circuits below, \$V_Q = V_P\$:
simulate this circuit – Schematic created using CircuitLab
In the left circuit (inverting) one of the inputs, P, is held explicitly at ground, 0V, but the other Q is maintained at the same potential by the op-amp with negative feedback, so \$V_Q = V_P = 0V\$. Hence the name "virtual ground" for node Q.
On the right (non-inverting), P and Q also have the same potential, for the same reasons, but because neither of them are connected to ground, we don't call node Q a virtual ground. In this case \$V_Q = V_P = V_{IN}\$.
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H: What MOSFETs should I use in this configuration?
Here is a configuration of MOSFETs which I believe allows for two different sources to supply power to the same load.
This diagram was originally found here.
The primary source is connected to the top pair of MOSFETs (labeled VCC_USB in the diagram.) The secondary source is connected to the bottom pair of MOSFETs (labeled VCC_USB_EDBG)
The source that is connected to the top pair of MOSFETs or the “primary” source, if it is connected, will supply the current for the load. The bottom pair of MOSFETs will act as diodes to prevent current from flowing from the primary source to the secondary source.
If the primary source is removed, because of their configuration, the bottom pair of MOSFETs will allow current to flow from the secondary source to the load and the top pair of MOSFETs will prevent current from flowing backwards.
Am I understanding this correctly?
This circuitry is for a lower voltage and amperage than what I want to use it for. I want to use it for 12VDC and 10-15 amperes of current. What MOSFETeds would be recommend to use for my configuration? I would prefer readily available low prices mosfets if possible. I was thinking that an FQP27P06would work. Could someone take a look and see if I am understanding it correctly and if those MOSFETs would work?
AI: If you use fqp27p06, when transistor is ON, you'll have VGS=-12V, ID=15A & RDS will be ~0.07 ohm as per the datasheet (https://www.sparkfun.com/datasheets/Components/General/FQP27P06.pdf)
So, VDS drop will be ~1.05*2V (since you have 2 PMOS in series) = 2.1V. So, if you feed 12V, you'll get only 9.9V at the output. If this is ok, you can use it.
Edit: Also, you'd need a heat sink.
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H: Easiest way for a beginner to design and make a custom printed circuit
I've used a prototyping board to successfully build an Arduino based system for a custom purpose
I would like to transfer this design to a custom PCB (using a service like PCBWay, for example,) so that I can have a smaller and neater circuit board to mount the components on.
When I went to PCBWay, I found the whole process overwhelming and didn't know what suitable software I (as a beginner) could use to design the board.
I only want to produce 1 or 2 small boards and it's only for my own usage.
AI: Download and use KiCad. It's open source. It's free. Available for Windows, macOS or Linux and It's more than enough for most hobbyists and many commercial users. You could also download a demo of a commercial program such as Altium but it won't be a much different experience, and the demo will time out leaving you without access to modifying your source files unless you fork over thousands of dollars. Follow some tutorials to get started (there will be a frustrating learning curve, expect and embrace it*, but follow the tutorials and you should be there in a few days). A two layer PCB will be fine for what you have. Try to do a ground pour. And consider Ki-cking them over few bucks if you're happy with the program.
When you have the PCB the way you like it on the screen you can output gerber files and NC drill file(s), zip them up and upload to your favorite online PCB vendor. These very inexpensive online vendors don't (can't) provide a whole lot of hands-on help, so you should read and understand their help files and take responsibility for what you get, because it's generally what you asked for (whether you wanted it or not). So you start with an EDA (Electronic Design Automation) program that is intended to produce the outputs that the industry uses, and then your interactions with them will be minimized.
* Someone once told me that when they got frustrated doing something, they got excited because it meant they were about to learn something new.
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H: Driving a 12-to-24 V P-channel MOSFET with TTL
I'd like to control up to 16 motorized valves with an ESP32. I'm using 74HCT595 shift registers (5 V outputs, 3.3 V input logic) to drive 12 V relays via NPN transistors. But the relays are pretty overkill and I'd like to replace them with MOSFETs. Since the motor valves need a switched +12V line, I need high side switching. In addition, I'd like to design the circuit so I can optionally switch to 24 V valves later without changing the circuit/PCB. I found this circuit on (https://forum.arduino.cc/t/protect-p-channel-mosfet-from-high-vgs-with-a-zener-diode/328512/6) which uses a 10 V Zener diode across gate-source and a 200 Ω resistor between the emitter and ground of the NPN BJT. Although it says 12 V VCC, the original author meant it to be for 24 V.
I have 2 problems with the circuit:
Shouldn’t the 200 Ω resistor be between collector and gate of the MOSFET, otherwise a 5 V voltage between GND and base won't turn on the BJT?
Isn’t the 200 Ω resistor smaller and will burn more energy than necessary? The Mosfet doesnt need much current, won't a 1k or even higher be fine too?
Will this circuit be fine, without changing values, for both 12 V and 24 V VCC?
I made a suggestion of my own: with R1 moved and larger - will this work as intended? Note I don't have a resistor across the Zener diode, do I need one with the LED there? I won't have any rapid switching so I don't mind if it takes a few ms for the MOSFET to turn off.
AI: Shouldnt the 200Ohm resistor be between collector and gate of the MOSFET, otherwise a 5V voltage between GND and base won't turn on the BJT?
R1, the 200Ω resistor is there to limit zener diode current while it is clamping \$V_{GS}\$. It does prevent Q1's collector from ever reaching all the way down to 0V, but it can still get far enough away from the positive supply to fully switch on Q2.
Your claim that this will require a higher base potential to turn Q1 on is correct, but emitter resistor R1 is modifying Q1's behaviour somewhat. It permits the emitter to rise in potential above 0V, which wouldn't be possible if the emitter were tied directly to ground.
Without going deep into the algebra, imagine that Q1 were saturated, and the emitter and collector were effectively connected together. Then R2 and R1 form a potential divider between +12V and ground, with \$12V \times \frac{200}{1000+200}=2V\$ in the middle (emitter & collector). To achieve that Q1 would require \$2V+V_{BE}=2.7V\$ at its base.
In other words, saturation occurs for inputs over +2.7V, which is fine. However, collector potential cannot ever drop below 2V, but that is still sufficiently low to turn on Q2.
For \$ V_{BASE}<+2.7V\$, base current will be very small, since the Q1 isn't saturated yet, and almost all current in R1 will come via the collector. Above +2.7V input, though, Q1 is saturated, and the base-emitter junction will tend to lift emitter potential with it. Extra current required to do this must come via the base; with a +5V input you can expect over 11mA to be drawn from the source, a digital output of the '595.
The '595 outputs are capable of sourcing 8mA maximum, each. Whatever design you settle on must not ask for more than this.
Isn't the 200Ohm resistor smaller and will burn more energy than necessary? The Mosfet doesnt need much current, won't a 1k or even higher be fine too?
Yes, that's correct. But driving a MOSFET is about more than just switching it on or off. It's also about doing it fast. Q2's gate is a capacitor that needs charging and discharging, and the smaller the resistors feeding the gate, the faster that happens. I think this is the primary motivation for the designer to have chosen such low values.
It doesn't sound like your application is particularly demanding in this respect, so I imagine you can get away with much larger resistances.
Will this circuit be fine, without changing values, for both 12V and 24V VCC?
I doubt it. Doubling the supply voltage from 12V to 24V will nearly double the base voltage required to saturate Q1, bringing it perilously close to the +5V available from your '595.
Your own design is nearly perfect. I have a few suggestions:
You really should include an additional resistor across the zener diode, to aid in switching the MOSFET off. Don't rely on the LED and its resistor to do this.
You don't need such a small resistor at Q1's base.
Your MOSFET is upside down. Connect source to +24V.
Include a diode to protect the transistor from inductive loads (Edit: I just noticed you already did this, sorry).
simulate this circuit – Schematic created using CircuitLab
Input current will be well under 1mA for each '595 output, which is perfectly acceptable.
This design will work well from a 12V or 24V supply, although current draw from the supply increases from 3mA @ 12V (no load) to 12mA @ 24V, due to zener diode D2 becoming conductive.
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H: Cannot stop Microcontroller's Hardware Timer from running
I'm using an Atmel ATMega8 microcontroller to control a stepper motor. (Datasheet).
Timer1 (a 16-bit hardware counter) is used in CTC mode to modulate an IO pin to provide the stepping signal to the motor controller. This part works fine and I'm able to adjust the frequency of stepping with decent granularity.
I've configured Timer1's Compare Match A interrupt (TIMER1_COMPA_vect below) to fire each time the IO pin toggles (both rising and falling edges). This also works correctly.
Timer1 has a minimum frequency that it will operate at, below this frequency I simply want to kill the timer altogether. For this purpose I am attempting to disable the Timer1 clock source. See the TIMER_1_HALT macro in the source code below.
According to the datasheet, setting TTCR1B bits CS12, CS11 and CS10 all to zero should completely disable the timer and thus prevent the stepping signal from reaching the motor driver.
Problem is that setting these clock selection bits to zero, as prescribed in the datasheet, does not appear to prevent Timer1 from running. I'm still seeing the blue LED flash at 600 Hz, and the motor keeps running at the original speed it started at, indicating that the hardware timer is still operating.
Below is a bare-bones version of the project that demonstrates the problem.
#define F_CPU (8000000)
#include <avr/io.h>
#include <avr/interrupt.h>
#define RED_LED_PB6 (1 << PB6)
#define GREEN_LED_PD6 (1 << PD6)
#define BLUE_LED_PB7 (1 << PB7)
#define MOTOR_ENABLE_PB2 (1 << PB2)
#define MOTOR_STEP_PB1 (1 << PB1)
#define MOTOR_MS1_PC0 (1 << PC0)
#define MOTOR_MS2_PC1 (1 << PC1)
#define MOTOR_DIR_PD7 (1 << PD7)
#define GLOBAL_INTERRUPTS_ON asm("sei\r\n");
#define GLOBAL_INTERRUPTS_OFF asm("cli\r\n");
volatile unsigned char forward_flag = 1;
float mapped_freq = 0;
const float MOTOR_MAX_FREQ = 30000.0f;
const float MOTOR_MIN_FREQ = 300.0f;
void Init_IO()
{
DDRB |= RED_LED_PB6
| BLUE_LED_PB7;
DDRD |= GREEN_LED_PD6;
DDRB |= MOTOR_ENABLE_PB2;
DDRD |= MOTOR_DIR_PD7;
DDRB |= MOTOR_STEP_PB1; //enable output for the step signal
}
#define TIMER_1_HALT TCCR1B &= ~(1 << CS12) | (1 << CS11) | (1 << CS10);
#define TIMER_1_RUN TCCR1B |= (0 << CS12) | (0 << CS11) | (1 << CS10);
void Init_Timer1()
{
TCCR1A = (0 << WGM11) | (0 << WGM10) //CTC mode
| (0 << COM1A1)| (1 << COM1A0); //toggle OC1A pin on compare match
TCCR1B = (0 << WGM13) |(1 << WGM12) //CTC mode
//| (0 << CS12) | (0 << CS11) | (1 << CS10) //clock div by 1 (e.g. no prescaler)
;
OCR1AH = 0xff; //16-bit register pair governs the output frequency
OCR1AL = 0xff;
//enable the Timer1 compare match A interrupt
TIMSK |= (1 << OCIE1A);
}
ISR(TIMER1_COMPA_vect)
{
PORTB |= BLUE_LED_PB7;
PORTB &= ~BLUE_LED_PB7;
}
void Init_Timer2()
{
//CTC mode, clock divided by 32
TCCR2 |= (1 << WGM21) | (0 << WGM20) | (0 << CS22) | (1 << CS21) | (1 << CS20);
OCR2 = 248; //the ISR will fire at about 1kHz
TIMSK |= (1 << OCIE2); //enable the compare interrupt
}
volatile unsigned char timer2_wait_milliseconds = 0;
ISR(TIMER2_COMP_vect)
{
if(timer2_wait_milliseconds) //if non-zero
timer2_wait_milliseconds--; //decrement (stops at zero and doesn't wrap around)
}
void Wait_ms(unsigned char ms)
{
//MAXIMUM wait is 255 milliseconds
timer2_wait_milliseconds = ms;
while(timer2_wait_milliseconds)
{}
}
void Set_Motor_Frequency(float hz)
{
if(hz >= 0.0f) //hz is positive
{
if(hz < MOTOR_MIN_FREQ)
{
//hold the motor
TIMER_1_HALT
}
else
{
//frequency is POSITIVE and within valid range, so update Timer1
mapped_freq = ((((float)F_CPU) / hz) / 2.0f) - 1; //scale the frequency to fit Timer1
OCR1AH = (signed int)mapped_freq >> 8;
OCR1AL = (signed int)mapped_freq & 0x00ff;
PORTD |= MOTOR_DIR_PD7; //set forward direction
forward_flag = 1;
TIMER_1_RUN
}
}
else //hz is negative
{
if(hz > -MOTOR_MIN_FREQ)
{
//hold the motor
TIMER_1_HALT
}
else
{
//frequency is NEGATIVE and within valid range, so update Timer1
mapped_freq = ((((float)F_CPU) / -hz) / 2.0f) - 1; //scale the frequency to fit Timer1
OCR1AH = (signed int)mapped_freq >> 8;
OCR1AL = (signed int)mapped_freq & 0x00ff;
PORTD &= ~MOTOR_DIR_PD7; //set reverse direction
forward_flag = 0;
TIMER_1_RUN
}
}
}
int main(void)
{
OSCCAL = 0xA4; //tuned for 8 MHz exactly
Init_IO();
Init_Timer1(); //stepper motor instantaneous frequency generator
Init_Timer2(); //simple millisecond delay timer for general use
GLOBAL_INTERRUPTS_ON
PORTB |= MOTOR_ENABLE_PB2;
Set_Motor_Frequency(300.0f); //set the motor going slowly (works fine)
Wait_ms(250);
Set_Motor_Frequency(0.0f); //SHOULD stop the motor but it doesn't
Wait_ms(250);
while(1)
{}
}
When the system powers up, the motor turns slowly but never stops, even though I'm setting the speed to zero 250 milliseconds later. I've tried other speeds too such as 600.0, but it seems that Timer1 doesn't want to stop, it just keeps going at whatever speed I start it at.
Why doesn't Timer1 stop triggering its interrupt when I set it's clock selection bits to 0?
I'm doing something boneheaded but I'm unable to fathom it.
AI: Looking into your code we can see that here:
#define TIMER_1_HALT TCCR1B &= ~(1 << CS12) | (1 << CS11) | (1 << CS10);
You forgot to add a bracket () into ~(1 << CS12) | (1 << CS11) | (1 << CS10)
Because now you are only clearing the CS12 bit in the TCCR1B register.
The correct way to do it looks like this:
~((1 << CS12) | (1 << CS11) | (1 << CS10));
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H: Why is this point giving me 8.3 V?
I am trying to find the voltage at V2 using the wire label in the Qucs-s simulator, powered by Ngspice. I have used Ohm’s law (V=IR) to work out the the voltage across R1 which was 1.66 volts;, but the simulator is claiming that there is around 8.3 volts at V2.
I also tried using the voltage divider equation, but where did the simulator get the 8.3 V?
AI: I redrew your circuit to make it easier to understand. Hope this helps visualize it:
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H: What is the ⎓ symbol (which looks similar to an equals sign) called?
What is the ⎓ symbol called, which looks similar to an equals sign with the bottom line broken into 3 dashes, and is used in consumer electronics?
AI: This is not an 'Equal' Sign in math-terms.
It's a sign used by convention to denote DC-systems.
In your screenshot it means:
Can draw/deliver upto 3A-DC at 5V-DC
Edit 3:
Removed previous edits.
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H: Universal AC Motor Brush Rotation Angle
Considering adding reversing capability to a Porter Cable 690LR (router) universal AC motor for use as a spindle motor. Yes, there are better alternatives but this is to finish someone else's wood-CNC project. 120 VAC, 60Hz, 11A, 27,500RPM, 1.75HP. Typical series-wound motor; reversing the field or brush wires is straightforward.
But upon inspecting the (rectangular) brushes, the holders are cylindrical and are retained with a hex lockscrew:
The brushes appear to be perfectly aligned to the center of the rotor axis. There is no visible offset or other adjustability. The only thing that can be adjusted is the brush angle:
One of the brushes is rotated more than the other, leading to uneven brush wear:
What effect does rotating the brush axially have on operation?
Should this angle be adjusted?
How will this affect forward and reverse operation?
Is it "bad" that one brush has more rotation angle than the other?
AI: What effect does rotating the brush axially have on operation?
It mostly depends on the wear of the brushes.
It shorts a part of the inductance armature of the motor, and is "commutating" it.
If it is "turned", it shorts too long which is a bad thing.
Should this angle be adjusted?
Yes, at the minimum angle.
Is it "bad" that one brush has more rotation angle than the other?
Well aligned, it doesn't matter.
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H: Solar charge controller for lithium batteries
My project is a solar powered RC car with the ESP32. Currently, I´m looking for a solar charge controller. I have two solar panels that deliver 3,5W at 6V. I want to charge Li-Ion or LiPo batterys. I need about 3A/ 5V for my project. My idea was to use the TP4056 charge controller. I tried to get information about it, but every site I visited said something different and I´m confused right now... Here are my questions:
Does the TP4056 come with battery protection? (Over charge, over discharge, short-circuit-protection, ...)
Can I charge multiple batteries with one TP4056? If I for example would use 18650 batterys, I would need three of those in parallel to give me the ammount of current I need. Can I charge them all with one TP4056? Or would I have to charge each battery with a seperate TP4056?
If I would have to use three charge controllers: How would I wire them, so all batteries can be used in parallel (to give me the amount of current I need) as a power source and can all be charged at the same time?
Is the TP4056 even the right charge controller for my project? If no, is there another one, that you would recommend?
Thanks for your help!
AI: No. Protection needs to be separate, unless the cells or pack already has built in protection.
Multiple cells in parallel is just one large cell. You can use a single TP4056 but it would just take very long to charge with 1A.
If the pack already has multiple cells in parallel, it is just one large cell. Not possible to charge each separately with TP4056 for each cell. You also can't use multiple TP4056s in parallel for increased current.
No it does not seem like suitable, but suggesting a product or what to buy is off-topic.
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H: How can I control PNP and NPN transistors together from one pin?
I'm trying to understand how it is possible to control a PNP and a NPN transistor simultaneously from one controlling pin.
My issue is that when the INPUT pin is left floating, the transistors drive each other and both go into conducting mode. When I try to pull the input pin up or down for those floating situations, the pull-up (or down) must be so powerful (few hundred ohms) that it causes high drain in the input pin, otherwise the transistors won't listen to this pulling of input pin.
simulate this circuit – Schematic created using CircuitLab
Please help me understand what I am doing wrong.
AI: Have the input drive one transistor/LED with weakly set default state, and use the output of the first transistor to drive the second.
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H: LTspice simulation for an inductor doesn't output the correct current value
I have a very simple circuit in LTspice for an inductor. The power is an AC voltage source with 50Hz and peak voltage is 640V. The inductor is 0.1H. According to the inductive impedance equation X = 2fL, the impedance is 31.415Ω and the maximum current is therefore 20.371A.
According to my simulation result, the maximum current is 18.3738A. Although in LTspice, the inductor has 1mΩ series resistance, it doesn't have significant influence on the final current. What's wrong with my experiment?
AI: Problem is the waveform gets less accurate as the total time increases, due to the limited number of steps (you can see it by zooming into the current waveform).
To fix this you can either reduce the simulation time or reduce the 'Maximum Timestep'.
With Timestep set to 1 μs I get 20.3718 A.
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H: Altium: Deleting the "room" object in the PCB view
When I carried out "Import changes from ..." into my PCB view, the components from the only schematic were all imported into it. However, it also created a box that has same name as the schematic file itself. Please see this image below:
I am not completely sure why this has been created. Is it safe to delete this? I believe that a room is used to group components that must all be placed within it. I could be wrong since I have never used it so far.
AI: Yes it's completely safe to delete the room. You can also set some preferences to keep them from being created in the first place.
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H: ATtiny85: Accidentally applied reverse voltage
Now it happened. It was dark and while I was coding I accidentally put the ATtiny85 inverted into the breadboard, so I applied +5 VDC to GND instead to VCC.
The power came from an UNO R3 which was powered by USB. Immediately after that I heard the Windows USB sound so I assume that this has caused a over-current protection to become active. I removed the cable after one or two seconds.
However, the ATtiny85 still runs fine. Can I assume from that fact it wasn't damaged and that it will still run fine even in two months? Or is it better drop it? Once the project is finished it would be not easy to replace it, but I also don't want to trash it if I can safely assume that it is fine.
AI: I think if you put a DIP part into a socket wrong you actually applied +5 to GND and 0V to Vdd.
This is bad for the part and can damage or destroy it. There's no way to tell if it has been damaged in some way (say from overheating of the die). It's a cheap part, you shouldn't hesitate to bin it if failure could have any ill effects.
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H: Diode configuration of BJT
I came across this configuration while trying to understand the remote temp sensing ability of the TPS4811.
It seems as if the diode pin voltage is responsible for turning on the BJT. V(BE) being >= 0.7V. The same is also controlling the Collector current & Base current.
How exactly is this working to enable remote temperature sensing ability of this IC?
Or rather how is it able to sense temperature?
AI: The terminal behaviour of a diode can be approximately represented by the equation
$$I_\mathrm{D} \approx I_\mathrm{S}\mathrm{e}^{V_\mathrm{D}/V_T},\tag{1}$$
where \$I_\mathrm{D}\$ is the diode current, \$I_\mathrm{S}\$ is the reverse saturation current and \$V_T = k_\mathrm{B}T/e\$ is the thermal voltage, being \$k_\mathrm{B}\$ the Boltzmann constant, \$e\$ the elementary charge, and \$T\$ the thermodynamic temperature. The above relationship holds for \$I_\mathrm{D}\gg I_\mathrm{S}\$.
If we periodically switch the current \$I_\mathrm{D}\$ between two values \$I_1\$ and \$I_2\$, we obtain
$$\frac{I_2}{I_1} \approx \mathrm{e}^\frac{V_2-V_1}{V_T},$$
where \$V_1\$ and \$V_2\$ are the diode voltages measured with the two currents. From the above equation, solving for \$T\$,
$$T \approx \frac{e(V_2-V_1)}{k_\mathrm{B}\ln(I_2/I_1)}.$$
The main idea of this arrangement is that it allows to measure the temperature \$T\$ cancelling the dependence on the diode parameter \$I_\mathrm{S}\$, which is difficult to characterise and is also temperature-dependent. Note that the diode is not used as an ON/OFF device.
Now, why using a diode-connected BJT instead of a proper diode? The reason is that the characteristic of a diode-connected BJT follows the model (1) much better than a diode. Hence, the temperature measurement is more accurate.
In the TPS4811x, \$I_1\approx 10\,\mu\mathrm{A}\$ and \$I_2\approx 160\,\mu\mathrm{A}\$.
Other details on this type of measurement can be found in the following document:
Texas Instruments, Optimizing Remote Temperature Sensor Design, SBOA173A Application Report, 2019.
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H: Which reverse polarity protection is better and why?
You can find two such circuits using a diode that protects against reverse polarity, i.e. against wrong power connection.
I wonder what is the point of using the D2 diode, since the current flowing through it will damage it - at least that's what the simulation shows. Diode D1 will not allow current to flow through it if we do not exceed the maximum voltage value. Am I right? Please explain.
AI: Every circuit might need a different form of protection. In your particular circuit (a linear 5 volt regulator) D1 is the preferable choice because it also helps reduce the power dissipation in the linear regulator by dropping voltage. Clearly if you have a strong voltage source, the D2 implementation needs some type of fuse but, you wouldn't use a BAT54.
In different regulator circuits where the input voltage runs much closer to the drop-out voltage of the linear regulator, D1 would prove problematic and the D2 circuit (with a fuse) would be used.
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H: Using BS270 MOSFET as Temperature Sensor
I have previously asked a question about using thermocouples to maintain a temperature range of 36-39° inside an insulated and dry environment.
The more enlightened engineers advised I look into using either a semiconductor device or an RTD instead.
Parts availability is limited where I'm currently located in the third world and mail order is unreliable at best.
I have a lot of bipolar transistors as well as MOSFETs at my disposal.
I've seen some examples of using 2N3904/3906 as thermal sensors.
The BS270 looks a bit more appealing to me because of the positive temperature coefficient and lower currents required.
My one concern is the inherent D-S resistance warming the device. But if the current is low enough I think the resistance curve with respect to junction temperature looks easier to calibrate than something based on bipolar transistors.
Am I travelling down the wrong path here? Bipolars seem to be more popular for this sort of hack job sensor.
The alternative is for me to manufacture an RTD which is indeed a possibility if that's a better option.
AI: Vbe of a diode-connected transistor is a fairly predictable and stable characteristic of a BJT. It is quite linear and yields a large signal (-2mV/K, approximately). It would probably require at least single point calibration in your application, since variability is of the order of +/-10°C without calibration. I expect you will use this because it is very, very simple (resistor + transistor -> ADC) and "good enough" for your application. Now, for general interest--
Better is difference in Vbe of two matched BJT devices at exactly the same temperature (i.e. on the same die) at two currents differing by a large factor such as 10:1. Or Vbe of a single device at two currents, switched fast enough that the temperature does not vary between measurements. For a device with low base spreading resistance such as an BC547 it is almost independent of individual device characteristics. Diode-connected transistors have an ideality factor close to one and varying little from that (perhaps 1.008 or so) This yields a smaller signal (order of 200uV/K) but more than 10x more accurate without calibration (proportional to absolute temperature) - typically better than +/-1°C.
Almost every characteristic of every component has some temperature dependence so one can't say that any given idea is unsuitable, however some are definitely better than others, and I would say the Vbe of a diode-connected transistor or delta-Vbe is very good. The two-current method is the same principle used to measure the die temperature in your computer CPU, for example, and the PTAT voltage is used in band-gap voltage references.
If r is the ratio between currents, the voltage difference is
\$\Delta V_{BE} = \frac{nkT}{q}
\ln(r)\$
where n is the ideality factor, k is Boltzman's constant, T is temperature (Kelvin) and q is the charge on an electron.
Note that, except for n (which is very close to 1.00 for a diode-connected transistor, and does not vary much with a given type of transistor), there are only fundamental constants in the equation plus the current ratio (which you control).
(there are a few other sources of error but that's a very good first approximation)
The key thing is that Is (saturation current) in the Ebers-Moll equation is eliminated. Is varies widely and is not constant with temperature.
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H: Why is DutyCycle not respected in code? Where I am wrong?
I have a PIC12F1572 and a push button (not exist in schematic). I want to get PWM on RA4 when the button is activated. The button is connected to RA2.
I set 50% PWM (13333 from 26667.) When the button is activated I get small PWM (under 1%). When the button is released I reach 0%. What have I done wrong?
Link to code:
https://pastebin.com/jKPUztm0
/*
* PIC12F1572 PWM example.
*
* Pins:
* +----+
* Vdd -|1 8|- Vss
* PWM1 RA5 -|2 7|- RA0/ICSPDAT
* PWM2 RA4 -|3 6|- RA1/ICSPLCK
* RA3/MCLR -|4 5|- RA2 PWM3
* +----+
*/
#include <xc.h>
#define _XTAL_FREQ 16000000 // Oscillator frequency.
#pragma config FOSC = INTOSC // INTOSC oscillator: I/O function on CLKIN pin.
#pragma config WDTE = OFF // Watchdog Timer disable.
#pragma config PWRTE = OFF // Power-up Timer enbable.
#pragma config MCLRE = ON // MCLR/VPP pin function is MCLR.
#pragma config CP = OFF // Program memory code protection disabled.
#pragma config BOREN = ON // Brown-out Reset enabled.
#pragma config CLKOUTEN = OFF // CLKOUT function is disabled; I/O or oscillator function on the CLKOUT pin.
#pragma config WRT = OFF // Flash Memory Write protection off.
#pragma config STVREN = ON // Stack Overflow or Underflow will cause a Reset.
#pragma config BORV = LO // Brown-out Reset Voltage (Vbor), low trip point selected.
#pragma config LVP = OFF // High-voltage on MCLR/VPP must be used for programming.
#define pwm_1 PORTAbits.RA5
#define pwm_2 PORTAbits.RA4
#define frana PORTAbits.RA3
#define semnalizare PORTAbits.RA2
#define pozitie PORTAbits.RA1
#include <stdio.h>R
#include <stdlib.h>
void init_pic() {
OSCCON = 0b01111010; // 16 Mhz oscillator.
ANSELA = 0b00000000;// 0b-prefix pentru binar bit:0b76543210
//bit7=RA5(0 digital input, 1= analog input) PWM_1
//bit6=RA4(0 digital input, 1= analog input) PWM_2
//bit5=RA3(0 digital input, 1= analog input) Frana
//bit4=RA2(0 digital input, 1= analog input) Semnalizare
//bit3=RA1(0 digital input, 1= analog input) Pozitie
//bit2=RA0(0 digital input, 1= analog input)
//bit1- nefolosit (set to 0)
//bit0- nefolosit (set to 0)
LATA = 0; // Zero all port bits.
}
void init_pwm() {
// Pin selection.
APFCONbits.P1SEL = 1; // PWM1 on RA5.
APFCONbits.P2SEL = 1; // PWM2 on RA4.
// Set PWM pins to be outputs.
TRISAbits.TRISA5 = 0; //RA5 = PWM_1 = OUTPUT
TRISAbits.TRISA4 = 0; //RA4 = PWM_1 = OUTPUT
// Set input pins.
TRISAbits.TRISA3 = 1; //RA3 = frana = INPUT
TRISAbits.TRISA2 = 1; //RA2 = semnalizare = INPUT
TRISAbits.TRISA1 = 1; //RA1 = pozitie = INPUT
// Set HFINTOSC clock, no prescaler.
PWM1CLKCON = 0b00000001;
PWM2CLKCON = 0b00000001;
// PWM control (standard mode).
PWM1CON = 0b11000000;
PWM2CON = 0b11000000;
// Phase.
PWM1PH = 0;
PWM2PH = 0;
// Duty cycle.
//PWM1 =RA5 PWM2=RA4 PWM3=RA2
PWM1DC = 13333; //= duty_cycle * (PERIOD/100); //RA5
PWM2DC = 24000; //RA4
// Period.
PWM1PR = 26667; //PERIOD
PWM2PR = 26667;
//On
PWM1LD= 0;
PWM2LD= 0;
}
//RA5= frana cerc mic (PWM1)
//RA4= semnalizare cerc mic (PWM2)
int main()
{
PWM1LD=0;
PWM2LD=0;
init_pic();
init_pwm();
while (1)
{
if (semnalizare == 1)
{
PWM2LD = 1;
PWM2DC = 13333; // PWM=50%
}
else
{
PWM2LD = 0;
PWM2DC = 0;
}
return (EXIT_SUCCESS);
}
}
AI: The problem likely is not how the PWM is setup, the problem is a mistake in the main loop returning.
The main loop that is supposed to run forever is not an infinite loop.
The loop runs exactly only once because the return statement is inside the infinite while loop.
The code then returns to the startup library and it likely just starts executing the code from start as if the MCU was reset. The exact behaviour can be seen by looking at the MCU startup code, linker map file, code outpt listing, or disassembled binary.
So it's the main program that will be periodically run, and there is likely nothing wrong with your PWM duty setting code.
Move the return out of the main loop, it does not belong there, but outside it.
|
H: Discrete OPAMP problem
I designed an opamp using discrete components (no specific purpose).
This is my circuit:
Real circuit:
I test the opamp by simple voltage follower circuit. Everything seems right.
Yellow: input signal. Blue: output signal. They are almost identical. Therefore, they look like single sine wave.
However, when I connected a large resistor (470kohm) between non-inverting input and my signal source, the output amplitude decreased (reasonable behavior due to not-large-enough input impedance) and considerable phase shift happened (this is what I am curious about).
Yellow: input. Blue: output.
XY mode view. About 26 degrees of phase shift.
Could anyone explain to me what cause the phase shift? According to discrete transistors pico-farad level junction capacitance, this should not be the main reason for the phase shift?
By the way, is there any recommended book to read if I want to learn how to design opamp in transistor level?
AI: Around 10pF of capacitance would cause that amount of phase shift with a 470kΩ resistor @16kHz, which is not implausible when you include the breadboard capacitance.
There's also Miller capacitance since the collector voltages are changing. You could reduce that with a cascode configuration.
|
H: Computing the value of the quiescent operating point
Сan you help please with solving this problem?
The circuit shown below is used as an amplifier
The value of the componets are Rb=470 kΩ om RC = 4.7 kΩ
Power supply Vcc = 12V
The transistor has Vbe = 0.6V β(Beta) = 80
Compute the value of the quiescent operating point:
Ib = ? μA
Vc = ? V
The transistor is working in ____________ region.
simulate this circuit – Schematic created using CircuitLab
So this my doubts and calculations, are they correct?
Base current (Ib):
Ib = (12V - 0.6V) / 470 kΩ
Ib = 11.4V / 470 kΩ
Ib ≈ 24.26 μA
Collector-emitter voltage (Vc):
Vc ≈ Vcc / 2
Vc = 12V / 2
Vc = 6V
Therefore, the quiescent operating point of the amplifier is:
Ib ≈ 24.26 μA
Vc = 6 V
The transistor is working in the active region (as an amplifier) because the collector-emitter voltage (Vc) is not saturated (close to Vcc) or cut-off (close to 0 V).
AI: This is what I teach my students when they deal with such a circuit. It is a 3 steps algorithm:
is the transistor cut-off? For it to be cut-off, the voltage on the base needs to be lower than the Base-Emitter diode voltage (noted Vbe or VD0). In your case, the Vbe is 0.6 and the VB is 12V
is the transistor saturated?
2-1) Calculate satuartion current Ic(sat)
2-2) Calculate the minimum base current to achieve the saturation point Ib(min)
2-3) Calculate the real base current Ib (you got that part correctly in your question)
If it is not in saturation or in cut-off, then it is simply in active/linear region and is neither fully closed or fully open.
In your question, you did not provide a value for Vce(sat) which is the voltage between the collector and emitter, but you can fairly assume values between 0v and 0.2.
Calculation become Ic(sat) = (Vcc- Vce(sat)) / Rc
Ib(min) = Ic(sat)/beta
Ib is what you previously calculated.
If the transistor was saturated, Vc would be equal to Vce(sat) or nearly 0V.
I am pretty sure that the transistor is in the linear/active region since the Rb resistor is pretty big.
In that case, the real Ic is obtained by multiplying Ib and beta together.
so 24.26 uA * 80 yield 1.94mA for Ic.
You can then apply Ohm's law accordingly: Vcc - Ic*Rc = Vc
12V - 1.94mA* 4.7k = 2.88V
Vc is then 2.88V
In this answer, when I refer to open and close it means that the transistor is free to let current through like a valve (open) or restrict it completely (closed). An open transistor (Saturated) yield a closed circuit and a cut-off transistor yield an open circuit.
As a side note, I was puzzled with your approximation that Vc is Vcc / 2. I never saw that before and I don't think it is a thing. Vc is equal to the voltage Vce and that voltage can take any value from Vcc when the transistor is full closed to Vce(Sat) when the transistor is fully open.
The more open the transistor is, the lower Vc will become. This is because the ground is slowly being exposed to the Vc point through the transistor. If the transistor was completely ideal, Vc would be able to reach 0V. However, it will never be the case in practice.
I hope this helped you a bit.
|
H: PI Controller or Type 2 compensator using SIMetrix/SIMPLIS
I have PI controller build around one OPAM (link:https://www.researchgate.net/figure/Schematic-diagram-for-PI-controller-using-operational-amplifier_fig2_338104251) and I want to simulate it in SIMetrix/SIMPLIS simulator.Knowing that SIMPLIS simulator does not need an average model for AC simulation, the circuit is redrawn as follows:
I have used an error amplifier with 100k open loop gain, V3 (AC Source) as a perturbation signal that is need by SIMPLIS for AC analysis and the DC point of my system is expected to be 2.5v
When I simulate the circuit, I expect the bode plot to be shaped as of that of PI controller as given bellow:
But what I got is totally different, whiche means that my simulation model is incorrect
In the internet I have found a simulation model that uses a different approach:
I am not at the level of evaluating the work of the author, but I think this is a classical approach by using 1k capacitor and 1k inductor, that could work on any SPICE simulator and does not take advantage of SIMPLIS method of simulation.
Could anyone explain to me why my model did not work even though SIMPLIS does not need an average model, and how can I simulate a PI controller around one OPAMP?
AI: The cited automated type 2 compensator in SIMPLIS is part of the ready-made templates you can freely download from my web page. As with any op-amp-based circuit, you need to make sure the device operates in its linear range, away from ground and the supply rail. Here, as the maximum output of the op-amp model is 5 V, I force its output to be around 2.5 V via the extra E1 component.
It is an old SPICE trick to auto-bias an averaged model regardless of the operating conditions. When SPICE starts simulating, whether this is an ac or transient exercise, a bias point needs to be determined. By doing so, SPICE opens all the capacitors and short circuits all inductors. In the given circuit, LOL is shorted and the solver determines the exact bias to apply at \$R_{upper}\$ for having the op-amp output set to 2.5 V roughly (the 100 gain is weak so don't expect a precise output but the exact value is irrelevant here as long as the op-amp does not rail up or down). Then, when the ac simulation starts, capacitor COL injects the ac and, together with LOL, form a low-pass filter which blocks any modulation from E1 and effectively opens the loop in ac.
Why is this useful? Because if your error circuit uses an op-amp featuring a 90-dB open-loop gain, to force its output to be between 1-3 V, you will have to tweak the input dc bias at the µV level which is extremely tedious. With the proposed circuit, it is done immediately in one shot.
Of course, as shown below, you could get rid of the COL/LOL network and insert the ac source in series, nothing mysterious here but you still need the auto-bias circuit:
As with any simulation, particularly ac, always check the dc operating point before considering the simulated data. Here it is 2.6 V as expected and the ac response is what we want.
If you want the PI response, disable \$C_2\$ and push the op-amp low-frequency pole to 30 MHz or so (infinite bandwidth) and you will see the response you want:
Make sure the Bode box receives the output from the op-amp as the phase margin should be -270° or 90° at dc (the op-amp reverses by -180° and the pole at the origin adds another 90° lag).
|
H: IPC 4671 Via Types
In Altium designer the via type can be declared as one of the follows:
I know about tenting. This is where a via is covered. This way it won't cut through the silk screen or solder mask. But why would a person ever need the other options tenting and covering, plugging, plugging and covering? Surely, just tenting should be enough. It will hide the via and prevent something from going it into.
AI: Tenting (Type I and II):
Tenting is the simplest of all via covering options. All tenting options have the major downside of possible entrapment of chemicals that may create long-term reliability issues. Also entrapped gas can burst open the tent due to expansion during the soldering process (can be avoided by tenting only one side of the via).
Depending on the type of solder mask used other problems may occur: The tent can collapse when the via hole is too big for the applied solder mask type. Or a very fluid solder mask can cause ugly "pimples" around the via hole.
The difference between Type I and II is that with Type II two (different type) solder mask layers are used to cover the hole for increased robustness.
Via plugging (Type III and IV):
Via plugging overcomes some of the downsides of via tenting: The hole openings are plugged with a non-conductive paste that is more robust than solder mask. But the issues of trapped chemicals and gas are still there. At least the problem of vias bursting open due to gas expansion can be avoided, if just one side of the via is plugged (as with tenting).
Also plugging is usually more suitable for bigger via holes compared to tenting. However, there is usually a minimum diameter requirement for plugging as opposed to tenting which can be applied to arbitrarily small via holes.
The difference between Type III and IV is that with Type IV there is solder mask applied on top of the plugged via.
Via Filling (Type V, VI and VII):
With via filling the via is completely filled with non-conductive paste. This avoids all entrapment issues. The filled via may then be covered with solder mask (Type VI) or a flush and solderable surface finish (Type VII or "capped"). The main advantage of capped vias is their use as "Via-in-Pad": You can place a via directly in a pad without worrying about solder flowing through. This saves a lot of space in very dense designs or might even be a necessity to be able to fan-out packages like narrow pitch BGAs.
Cost:
Tenting is the cheapest type, as it causes practically no additional cost. I personally never used plugging, because if I already need to pay additional money I might as well go for the "best" option (filling). Also the PCB shops I'm usually working with are more used to via filling and have much more experience and process knowledge compared to plugging. So all things considered, filling might even be cheaper than plugging.
But all cost aspects may depend very heavily on the specific PCB shop you are using.
For further reading Multi-CB has a convenient overview on via types:
https://www.multi-circuit-boards.eu/en/pcb-design-aid/surface/via-covering.html
|
H: Why can't USART in synchronous mode be full duplex?
I have read in many websites (for example Difference between USART and UART and Difference between USART and UART) that USART operates in half-duplex mode and UART operates in full-duplex, but they never explain why.
I don't understand what makes it not possible for USART in synchronous mode to operate in full-duplex, given that there two pins available for data, just like in UART or SPI and they can operate in full-duplex.
AI: The terms USART and UART are very broad and can mean different things to different applications.
Generally speaking the "synchronous" part ('S') means that a clock signal is sent along with the data to keep everything synchronised.
Whereas the "asynchronous" operation means the far end has to recover the clock from the data signal, for UART by guessing based on knowing the approximate baud rate.
Now if we are talking simple 8N1 or similar serial interfaces such as underly RS232 etc, then you may only have two wires available for data transfer.
For synchronous operation, requiring sending the clock uses up one of these wires. The other is then used for data. This means you cannot both transmit and receive at the same time in synchronous mode hence half-duplex. For example the Rx wire could be used to send the clock, and the Tx wire used bidirectionally for sending and receiving data.
For asynchronous mode, you don't need the clock so one wire can be used for transmit, the other for receive allowing full duplex.
In other applications you can have a different number of wires. For example ATMega MCUs provide a third wire for clock in syncronous mode. This means that full duplex synchronous operation is perfectly possible in such an application because we now have an extra wire to carry the clock.
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H: How can I stop a comparator from oscillating in a relaxation oscillator configuration?
I have a dual supply comparator and I want it to stop oscillating and output +12V with a single switch. I tried to connect R3 to +12V but it still oscillate with low frequency and like 95% duty cycle.
As the tile goes: How can I stop the comparator from oscillating with a single switch?
simulate this circuit – Schematic created using CircuitLab
AI: simulate this circuit – Schematic created using CircuitLab
Something like this will do.
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H: Output impedance of the crystal driver
My question is regarding the answers, one and two.
Both answers talk about the impedance of the crystal driver output.
I'm trying to understand how the crystal driver output impedance will be related to the load capacitors of the crystal.
The first answer has this, "The impedance of 6 pF at 32.8 kHz is 810 kΩ. Now the impedance of the crystal driver is certainly not zero, but quite likely significant relative to 810 kΩ."
Can someone tell me how this impedance of 810k is relevant or how to understand this with the remaining part of the answer.
Basically, I want to understand the relation between the crystal drive impedance and the load capacitance of crystal.
AI: Basically, I want to understand the relation between the crystal drive
impedance and the load capacitance of crystal.
The phrase "crystal drive impedance" is a bit ambiguous so, I'll define it as the output resistance of the inverting gate used in the Pierce oscillator. I mention Pierce oscillator because that's pretty much what all MCU/logic chips use. Pierce oscillator circuit diagram: -
Image from here.
So, "crystal drive impedance" is the resistance above shown as \$R_S\$. Resistor \$R_F\$ turns the unbuffered logic gate into a linear amplifier (due to negative feedback). I believe you know what \$C_a\$ and \$C_b\$ are i.e. they are the so-called crystal loading capacitors.
Now, where you might be getting confused is in the terminology. For instance, the term loading capacitance is badly named because in fact, they are part of a phase shifting network. The "true" (as in actual) loading capacitor for the crystal is \$C_a\$. Capacitor \$C_b\$ does not "load" the crystal; it loads the output of the inverting gate via its output resistor \$R_S\$.
So, there are in fact two phase shifting networks: -
\$R_S\$ and \$C_b\$
The crystal's reactance and \$C_a\$
Together they produce 180° of phase shift at one particular frequency. This produces oscillation and all is good. The crystal's reactance is inductive (at oscillation frequencies) and, along with \$C_a\$ shift the phase by nearly 180° (not enough on its own for oscillation to occur). \$R_S\$ and \$C_b\$ shift the phase by a few degrees more and hence, you get oscillation.
So, to answer your question, the relationship between \$R_S\$ and \$C_b\$ (half the so-called loading capacitance) is to produce a few degrees of phase shift and allow the circuit to oscillate.
Maybe you should read what I put on my basic website about crystal oscillators.
Can someone tell me how this impedance of 810k is relevant or how to
understand this with the remaining part of the answer.
The 810 kΩ is the impedance of \$C_b\$ (above) at 32.768 kHz and it will form a phase shift network with \$R_S\$ as explained earlier.
|
H: Impact of crystal's ESR on the working of a crystal
I'd like to know how important the value of a crystal's ESR is for the working of the crystal at the right operating frequency.
I went through this question which asks for the priority between the crystal's ESR and stability, but I couldn't get clarity from the answers.
One of the answers states, "ESR has an effect on the pullability of the crystal and the power dissipation and probably jitter."
My question:
What does the pullability of the crystal mean in simple terms and why does it matter for ESR?
Also, why does ESR matter? How important is the value of ESR for the right oscillation of the crystal? Does higher ESR imply good oscillation, or does lower ESR?
AI: I'd like to know how important the value of a crystal's ESR is for the
working of the crystal at the right operating frequency.
It affects the oscillator operating frequency a little bit. Consider a simulation of a "10 MHz" crystal that I evolved some time ago. Here's the circuit: -
\$V_{IN}\$ would be the raw logic gate driver voltage
\$V_{OUT}\$ would feed the input of the logic gate in a Pierce oscillator
Rs, Ls and Cs are the equivalent motional components of the crystal
Cp is the electrical parallel capacitance of the crystal
If we plot the phase of \$V_{OUT}\$ we can see at what frequency we get 180° phase shift for various values of ESR (Rs): -
Summarising, for an ESR of 20 Ω we get an oscillation frequency of 10.001370 MHz. For an ESR of 80 Ω we get an oscillation frequency that is slightly higher at 10.001509 MHz (139 Hz higher).
What does the pullability of the crystal mean in simple terms and why
does it matter for ESR?
Pullability means how much we can make the oscillator run at a different frequency. For the graphs and simulation above, when ESR changes from 20 Ω to 80 Ω we can "pull" the oscillator frequency by 139 Hz.
But, remember, for a given crystal, we can't alter the internal ESR so this is not of any importance. We could add an external resistor of a few ohms but, this is missing the point; we use the "so-called" loading capacitors if we wish to "pull" the oscillation frequency. This is much more effective.
Also, why does ESR matter? How important is the value of ESR for the
right oscillation of the crystal? Does higher ESR imply good
oscillation, or does lower ESR?
It doesn't matter in the bigger scheme of things because, for a given crystal, we "tune" the oscillator to where we want it (if we are concerned about having a very accurate frequency) by using the loading capacitors.
Also, as Rohat mentions in his answer (now deleted), the higher the value of ESR the more loop gain is needed by the logic gate (running linearly) to get successful oscillation. However, the loop gain is usually high enough to cope with large variations in ESR.
|
H: Inside a 2N3904 transistor TO-92 package
I cracked open this 2N3904 transistor. I lack the means to test its function until tomorrow.
The die doesn't look like anything I've ever seen before. I'm not quite sure where the silicon is.
In your opinion, does the back half of the transistor contain silicon required to function,or is the die contained behind the leads?
The reason for cracking this open was to find whether the construction allows for good thermal conductivity to the leads. The answer to that question is an obvious yes, as there are no bottlenecks inside the transistor package.
I'm curious now about the actual function. I'm about to pry the leads off to see what is underneath.
AI: From National Semiconductor "Discrete Semiconductor Products" Databook 1989. The chip itself seems to be missing from OP's photos.
These chips were something like 0.01" thick (if memory serves):
Two flying bonding wires were attached to emitter (E) and base
(B). No bonding wire was needed for collector, since it was electrically attached to the lead frame underneath. The lead frame mostly appears in the top photo. Silicon chip remnants may be in both photos, shattered and split. The top-surface of the chip shown in the schematic above would be facing down along with bonding wires, in the bottom photo.
The package epoxy conducts much heat to the ambient environment. However, the thermal path to the collector lead is favoured over the emitter and the base leads.
|
H: Why does this show as a syntax error on Verilog?
I'm a newbie to Verilog, and I'm trying to follow the few youtube videos I've seen that use vscode as text editor for Verilog.
However, I get an error in the Verilog file itself. Here's my code:
module test(A, B, C)
input A;
output B;
output C;
assign B = A;
assign C = !A;
endmodule
And here's the error I get, with line 3 being the input A; line:
./test.v:3: syntax error
I give up.
AI: It's not easy to get a helpful error message with any simulator in this case. The module line needs to end with a semicolon.
Change:
module test(A, B, C)
to:
module test(A, B, C);
Unrelated to your error, here is the recommended way to declare module ports. It uses the ANSI-style, which simplifies the code and avoids common Verilog errors associated with having duplicate port lists:
module test (
input A,
output B,
output C
);
assign B = A;
assign C = !A;
endmodule
|
H: Linear solenoid specifications
I want to buy a linear solenoid that has the following specifications in the Datasheet:
24 VDC
9W 100% Duty Cycle
18W 50% Duty Cycle
36W 25% Duty Cycle
90W 10% Duty Cycle
And the following force-stroke curves:
I have a power supply of 24VDC and 10A. Since I don't know the coil resistance (at 20 °C), how can I know the current that would go through the coil?
In other words, do I have to assume that at 24V the curve that represents the behaviour of the solenoid corresponds to 100% duty cycle and 9W? And the other curves are only for higher voltages than the rated voltage of 24 V?
AI: I have a power supply of 24VDC and 10A. Since I don't know the coil
resistance (at 20 °C), how can I know the current that would go
through the coil?
From the information you state....
24 VDC
9W 100% Duty Cycle
It's a fair assumption that the current from a 24 volt supply would be 375 mA or thereabouts. The solenoid would have a DC resistance of 64 Ω.
90W 10% Duty Cycle
That's basically an average of 9 watts i.e. 90 watts for 10 percent of the time. That puts an upper limit on the pulsed voltage of 75.89 volts because: -
$$\text{Voltage}_{MAX} = \sqrt{Power\times Resistance}$$
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H: Inductance of Two Primaries in Parallel
I need to verify the design of a prototype SMPS transformer. The transformer has two primary windings driven in parallel specced at the same inductance value (the transformer manufacturer suggested this, our initial handwound design used a single primary). When I measure each primary separately, I read a value of 5 mH for both but when I connect the two in parallel, I still read 5 mH when I expect to read 2.5 mH. I measure the inductance with the secondary open circuit.
Is this expected, does the inductance not change because the windings share the same core?
This is the schematic for the design.
AI: does the inductance not change because the windings share the same
core?
Correct, two identical coils wound on the same core, when paralleled exhibit the same inductance as one coil. Think about winding an inductor with Litz wire. Litz wire is tens to thousands of very thin individually insulated wires that behave like a single fat wire (but better): -
Image from here
But, if the two coils did not share the same magnetic core then sure, the inductance would halve.
Maybe think about half the current going down one side of the wire in the coil and, the other half of the current going down the other side. Then, as brain experiment consider that the two sides of the wire are magically insulated from each other by a very thin gap running the length of the wire. That's the same as two wires.
Another way of looking at it is this: when two electrically connected 5 mH inductors get magnetically close to each other, both inductances rise towards 10 mH hence, their parallel arrangement becomes 5 mH.
This is based on the definition of inductance; the inductance is the amount of magnetic flux produced per amp.
So, both are producing an amount of flux when separated but, when together, not only is there the flux from each other but also the individual fluxes to consider hence, either coil appears to produce twice the flux for the same current therefore, inductance appears to double.
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H: Variable output voltage regulation - does this solution make sense?
I want to use a switching power supply that has a fixed 24VDC output. I want to add a simple circuit that will give me an adjustable voltage between 0-24VDC. The power supply allows the consumption of about 2A and I would like to have such a current in the entire adjustment range. I thought about such a circuit based on a darlington transistor, which is controlled by a potentiometer (divider R5/R6). Overcurrent protection is still missing. Does this arrangement make sense?
AI: Does this arrangement make sense?
Does and doesn't.
Does, because the arrangement is basically a linear regulator with local feedback. You apply a voltage to the base and expect two VBE drop less at the output.
Doesn't, because the output voltage depends on the VBE of the transistors, and VBE of the output transistor changes with collector (load) current as well as with temperature. There's no compensation network implemented in your circuit. So it won't work as a voltage regulator i.e. the output voltage will drop as the load draws more current.
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H: FR4/PCB electrical permitivity varing over temperature and effects on trace matching, how much does it change?
I have a high speed design that runs at 1.6GHz, there are also matched traces on a 12 layer board. Now I would like to know if the design will function over temperature of a -10C to 50C range and if the electrical permittivity and Dk will change and by how much.
How much does electrical permittivity or Dk change with PCB materials, is it a few percent?
I am using this material for my design...
TU-768
which the datasheet isn't really useful when it comes to temperature change.
AI: I found this reference in Microwave Journal:
To evaluate performance variations with temperature, circuit-board materials are characterized by the thermal coefficient of dielectric constant (TCDk). It is simply a measure of how much the dielectric constant changes over a defined temperature range. For FR-4, it is typically 200 parts per million (ppm) per degree Celsius (°C) change in temperature.
200 ppm/K over a 60 K variation in temperature would give about 1.2% variation for your use case.
On the other hand, iPCB, a PCB vendor, suggests it could be much worse:
The fr4 dielectric constant changes with temperature, and the maximum change range can reach 20% in the temperature range of 0-70 degrees.
"Improved FR-4" products like N6000 can be better, here(slide 11) we have a measurement of less than 0.3% variation between 0 and 60 C.
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H: Altium: Unable to select component that ended up outside of the schematic sheet area
So I use "Smart paste" to create array of copies, then I selected the whole block and moved it to the side. Altium correctly moved the block and placed some components outside the sheet area. No error message was given.
Now I am unable to move these components back into the sheet and am unable to select them by clicking on them. What do I do? Please see the components in that are outside the sheet in the diagram below:
AI: Temporarily make the sheet size larger, move parts, then make sheet size smaller.
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H: High voltage MOSFET linear regulator failure
I designed the circuit below for an FSAE electric vehicle, for which the rules require an HV-powered LED to be lit when the HV bus is above 60 V. In simulation, the circuit works very well.
In real life, when 400 V was applied (smoothly thru a precharge circuit), it blew a fuse, the MOSFET failed (post-mortem RGS = 39 Ω, RDS = 4.1 kΩ), the 10 V Zener diode exploded, and its negative trace burned to death.
Is there a fundamental problem with this circuit that I haven't caught on?
My hypothesis is that the gate somehow broke down and it must have sank current straight from the drain. Would such a Zener arrangement be too slow to kick in, thus causing VGS to go beyond absolute maximum?
What could I do to fix the issue? If the problem is the Zener being too slow to kick in, I was thinking about adding 1 MΩ and 0.1 uF both in parallel with the Zener to better protect VGS.
MOSFET datasheet
Circuit simulation
(HV and LV grounds are separate in real life)
AI: There is a lot of capacitance from Drain to Source because that is a beefy MOSFET.
When the voltage is applied with a fast ramp, that capacitance will raise up the Source voltage well above Vgs(max). The gate is constrained to be 10V above ground so you get a huge negative voltage on the gate relative to the source. The zener should be be from gate to source to protect it and you may also need some series resistance (in series with the input, not the zener) that is resistant to failure from massive (but brief) power dissipation during the start-up pulses. Your LED and Optocoupler LEDs may be seeing potentially destructive peak currents as well as stressing the 1.5kΩ and 10kΩ resistors.
Since failure of the LED or the resistors would result in a false "safe" indication, I would expect you would want to do a very careful analysis and ensure that none of the parts are particularly stressed (and even that may not be sufficient).
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H: Altium: Place components along circular path
There are basically two pairs of 10 LEDs, each in 0603 package. I need to place both of them in a circular path at 36 degree apart. I need to try a few different circle radius before I finally how I want the end product to be.
In Eagle PCB, I could just run a ULP script that would place the parts. How do I place parts along a circle or any other uniform path (that can be defined using formula) in the Altium designer PCB editor?
AI: One option is to place a local polar grid. If the "Comp" check box is checked, parts will automatically rotate when placed on the polar grid. This requires manual placement of the parts.
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H: How to achieve coherent sampling in practice
In the context of measuring a sinusoidal source with an ADC, coherent sampling (i.e. capturing an integer number of periods) allows the use of a rectangular window without spectral leakage.
How does one actually do this in practice?
I am testing a 16 bit ADC that is sampling at 5 MSPS. I set my source to 97.75 Hz to get 41 periods in \$2^{21}\$ samples. Looking at the result, I am missing about 1/8th of a period, and there is spectral leakage. Using a flattop window, the spectral leakage will be at about -95 dB, which is pretty close to where a 16 bit ADC performs. I don't think it would be good enough for something like a 20 bit ADC.
What is a practical bench setup to measure a sine source with an ADC and sample coherently?
AI: You can use a PLL (phase-locked loop) to lock the ADC sampling frequency to the input sine signal.
The bandwidth of the PLL has to be chosen to minimize the overall system's phase jitter and drift - if the input signal changes in frequency quickly, the PLL has to have high bandwidth so it can follow these changes properly, and if the input signal is very stable, the PLL should have low bandwidth to minimize its output jitter.
With a good enough PLL (and zero-crossing detector), you can make the ADC start and stop sampling exactly during the zero-crossing of your waveform while still capturing an exact power of two of samples. The PLL will tune the phase and frequency of the ADC's clock signal accordingly.
When designing your own PLL circuitry to generate an appropriate ADC clock, you might want to consider a multi-stage approach: First a low-frequency PLL that multiplies the signal frequency with a factor of (for example) 256 to get it from the 100Hz range into the 20kHz range, then by another 256 or so to get it into the MHz range. If those multiplication factors are still too large, you could use a three-stage design instead: Three cascaded 64x stages will get you to about 26MHz, which is ideal for many ADCs.
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H: Altium: Pour small ground plane inside PWR plane
I have a layer with a full copper pour connected to 5V. I need to have a small section inside of this that is connected to ground. Is this possible in Altium Designer?
AI: Multiple areas with different nets a plane layer are common in PCBs, and possible in Altium.
There are two (2) general options to create that, depending on how the layer is set up in Altium.
The layer is defined as a plane layer in the PCB stack-up. In layers like that Altium renders traces as negative - traces are gaps in copper. If you draw a closed-loop trace, you'll create an island in a plane with a gap around it. You can assign a net to the island, and it will behave like a plane with that net (vias will connect to it).
The layer is defined as a routing layer in the PCB stack-up. Use polygons to create islands. If you draw a polygon which covers the entire PCB, then it will be a de facto plane. If you draw a polygon B in the middle of another polygon A with a different net, then Altium will add clearance around polygon B, and it will be an island.
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H: Unbalanced Wheatstone bridge with a capacitor in the middle
I have to find the amount of charge stored in a capacitor after a significant amount of time when $$ R_{1}=1 k \Omega, R_{2}=8 k \Omega, R_{3}=4 k \Omega, R_{4}=2 k \Omega,C=1\mu F,V=10V$$ There is no charge stored in the capacitor.
I found that this circuit is unbalanced
$$\frac{R_{1}}{R_{4}}\neq\frac{R_{2}}{R_{3}}$$
which means that at least initially there's current flowing through the capacitor. However, I'm having trouble figuring out what's the voltage across the capacitor. There is no angular frequency given, so I can't get the reactance, which means I can't get the total resistance.
I did a quick simulation and found out that the voltage drop across the capacitor is 6V. Am I missing something obvious?
AI: This is a question about DC, since \$V\$ is constant. The phrase "after a significant amount of time" should make you think of "DC operating point", or "quiescent state", in which all capacitors have charged to some steady voltage, and all inductors' magnetic fields have settled also. In that state, capacitors are passing no current, and can be removed from the circuit without changing any currents or potentials anywhere, and inductors are passing a steady maximum current, have no voltage across them, and can be replaced with short-circuits (0Ω resistors).
Therefore, your circuit becomes:
simulate this circuit – Schematic created using CircuitLab
No need to consider reactance of the capacitor, since the question is dealing with DC. The potentials at A and B are:
$$
\begin{aligned}
V_A &= V \frac{R_3}{R_1+R_3} = 10\frac{4k}{1k+4k} = 8V \\ \\
V_B &= V \frac{R_4}{R_2+R_4} = 10\frac{2k}{2k+8k} = 2V \\ \\
\end{aligned}
$$
The capacitor will evetually charge to \$V_A-V_B = 6V\$.
It may help to replace the potential dividers of R1 & R3, and R2 & R4 with their Thevenin equivalents, to see why this is true. The system of source V, R1 and R3 have the Thevenin equivalent in the blue box, and the red box is the equivalent of the system V, R2 and R4:
simulate this circuit
The bottom circuit is the entire system reduced to a single source, resistance and capacitance, and I hope now it's "obvious" why C will charge to 6V after a "significant amount of time".
Also, given that we can now clearly see the time constant is \$2.4k\Omega \times 1\mu F\$, you even have an idea of what amount of time is "significant" in this case!
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