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H: LTspice simulation of LM311 comparator with hysteresis not behaving as expected
I am trying to simulate the following comparator circuit with LTspice:
The LM311 comparator was intended to be used with hysteresis, same as the circuit shown in this graph (designators are the same):
The high threshold should be 3.1V and lower threshold 1.9V, centered around 2.5V. I used the following website to calculate the resistor ratios. The pull-up resistor R3 is set to be 1K so that it is much smaller than feedback resistor R4 according to this post.
The simulate results give strange waveforms:
At VIN (the previous stage is a current sense amplifier with 2.5V offset, and at this point there is no current so this voltage is 2.5V):
At the output (COL_OUT) there is unexpected oscillation:
At REF, there is oscillation as well:
What could be the cause of this behavior?
AI: What could be the cause of this behaviour? Thanks in advance!
The emitter should be connected (via a resistor or not) to ground and not 5 volts: -
And, the collector normally has a pull-up resistor to 5 volts and not the complex arrangement you have shown (that doesn't match your other schematic).
So, forget about the emitter resistor and connect "E" to ground/0 volts. Use a simple 1 kΩ pull-up resistor from "C" to 5 volts and, feedback to "REF" with a high value resistor such as 100 kΩ or greater.
Here's an example from the data sheet that shows how E and C pins are used (my bits in red): -
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H: Gate resistors on the MOSFET
I was working on the breadboard on this simple circuit to do some testing and noticed that sometimes it would not turn on as expected . Somewhat abnormal operation.
I always knew to connect a resistor (say 330 ohms) to limit the current that can damage the output of a microcontroller and a 1k resistor to make sure a pull-down such that the mosfet does not turn on for some reason.
Just by simulating, however, I noticed that this resitive divider provides on the gate of the mosfet a focus no longer [0..5]V coming from an Arduino.. but [0..3.7]V
This may not completely turn the mosfet on, and in any case, it is not what I want.
To "solve" this problem I replaced 1k with 10k:
Is this okay?
Am I doing something wrong?
If I remember correctly .. the resistor toward gnd (10k) might alter something inherent in the Cgs of the mosfet, but it is not clear to me what ... if you can explain this concept a little better and the consequences I have in using 1k or 10k .. thank you very much!
AI: The pull-down resistor is only to set the default state while the MCU is waking up (most go tri-state after reset). It can (indeed, should, for this reason) be placed before the series resistor, thus losing no voltage at the gate.
The series resistor serves to slow the gate risetime, against gate capacitance; this can be harmful as it increases switching losses, but also helpful as it slows switching in general, so can avoid problems like generating radio interference or needing protective circuitry to address transient currents or voltages. The value or range required, depends on the application.
Note that the MCU's pins have an approx. 20-50 ohm source resistance themselves. This isn't documented directly, but can be inferred from the VOH and VOL parameters, and what currents they are tested at. This resistance limits current some already. When driving small capacitors (other CMOS pins, trace impedance, and small MOSFETs too), this resistance alone is sufficient -- the current is not continuous so it doesn't heat up the device or cause damage. An external gate resistor is still recommended, particularly if there is a long distance between MCU and MOSFET, as the MOSFET can oscillate as it switches (another source of radio interference), and a resistor placed at the MOSFET gate prevents oscillation.
There are less common reasons you might want a gate resistor, too. For example, if you want to prevent damage to the MCU in event the MOSFET fails catastrophically. (Typically when a transistor fails, it becomes a three-way short, at least momentarily; drain supply voltage can thus flow into the gate circuit.) A series resistor, with a clamping TVS from source to gate, can be used to shunt this energy to ground, away from the MCU. (This isn't very important most times, as any electrical failure means board replacement, and survival of the MCU is irrelevant; but it can be handy while prototyping, when transistor failures are likely.)
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H: LVDS to Singled-Ended - Transmission Line Balun Matching
I need to convert a LVDS clock into a single-ended signal. In the past I've used a voltage balun with a center tap on the secondary but I haven't found any good past 1GHz. I need to get to 2GHz in this application and found transmission line baluns good from 4.5-3000 MHz like the TC-1-13M+ from Mini-Circuits.
Analog Devices shows an implementation of it on an eval board schematic in their datasheet for the ADL5391 (page 13). It looks like R4 is the matching for the output impedance of the IC but what is unclear is why they added R5/R6. Is this to present a 150 ohm differential impedance (R4+R5+R6) to the balun? The balun is 1:1 so doesn't that mean the single-ended output impedance is 150 ohm? The datasheet mentions the balun is 50 ohm. I feel like I'm missing something here.
I'd appreciate any clarification you can offer.
AI: Notice page 3, "Differential Output Impedance", which rises with frequency; and Fig.16. Most likely they wanted a load resistor to dampen this, and then series resistors to match to 50/100 ohm outputs. Put another way, it acts as an R-pad or attenuator, which reduces signal level but stabilizes impedance.
Note that many resistors (and capacitors) are provided so the user can add/remove parts and pick whatever balance, impedance, and filtering to a certain extent, they require.
Generally speaking, transformers aren't too picky about the impedances they are used at; you simply get proportionally more loss, less amplitude, or less frequency range.
From such meager data, it's not clear how exactly the TC-1-13M+ would behave at 100 or 150 ohms.
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H: Flip Flop as frequency divider precision
I am using a couple of CD4013BC as frequency dividers as per schematic :
I am checking from a data logger that they are losing some cycles, or not dividing the frequency properly from time to time. The unused IC pins are grounded.
Did anyone experience the same and know the possible reasons why flip flops are not accurate in the 24hours run?
Accurate means if I divide a frequency let's say 100 Hz and I obtain another one of 50Hz for example, sometime I notice the output frequency as logged is higher or lower (75Hz or24 Hz resulting in my datalogger as negative or positive spikes.
I am clocking them with a square wave DC 5v 100Hz
Is this a standard behavior?
As requested, I am feeding this frequency from an optocoupler that is taking the square wave from a zero cross circuit. The optocoupler is feed with 5V, a 4N25.
This is the input, and doesn't looks noisy to me at all :
for proving that, I measured the input from the source before it arrives to the IC and I don't have any frequency changes.
@Simonb
here is an example of the output recorded from the datalogger , directly after the optocoupler. Consequently, when the frequency changes of little variations OR there are these glitches, the flip flop seems to amplify them even more , even with delays before counting back correctly
-- EDIT
Looks like I solved partially just adding a capacitor to the AC output at the very initial stage of the circuit.
@SteveSh
EDIT --
Alright, I will post this to further confirm the GLITCHES theory. I am not saying that a ST is not necessary, just that the CAUSE are the GLITCHES, the EFFECT is then reflected on the IC itself from the noise of the modulated AC source.
So I decided to add a monitor and sync it with my datalogger to see it clearer. It's evident from the below images there are some amplitude modulated signals in the AC Power supply, probably coming from the grid or local switches that are creating these alteration. As the clock below are sync with multiple Chrony instances the signal in time corresponds to the perturbations created by AM modulation.
Hence the erratic EFFECTS are reaching the IC with relative consequences.
Image 1 source : AC power supply monitored with a spectrum
[![enter image description here][7]][7]
Image 2 : The not yet cleaned by software frequency coming out from the Flip Flop to the datalogger, with full bandwidth scale (note the timings) :
Image 3 : the frequency from the Flip Flop cleaned with a custom software using FBMWA algorithm (same data from figure 1, just cleaned from the Glitches and focused in bandwidth .
Conclusion my side and correct answer remains for glitches cause first.
AI: The chances are that the flipflop is responding to very short glitches on your power supply. Modern ICs can respond to clock inputs measured in nanoseconds. A momentary spike on your supply could be enough to trigger an extra clock cycle.
You may need to look more carefully at your input circuit to try to filter out such glitches.
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H: How does ESC differ PWM and UART signals?
Many electronic speed controls provide the same hardware interface to manage them. It's +5 V, GND, PWM wires.
But I have noticed an interesting feature, which is provided by BLHeli based ESC. You can program it with BLHeli suite software. For example, Arduino Nano is programmed to be bootloader, then it will use GND, PWM wires in order to program ESC. I suppose that some kind of UART protocol is used. The most obscure thing for me is possible implementation from ESC's side. How does ESC understand that "PWM" pin should be treated as UART signal? I guess that we can detect some "preamble" signal at the start of ESC, if it's not matched then pin is assumed to receive PWM signal. But it's only my guess-work.
AI: The source code may reveal how it's done.
There's plenty of ways to implement it even without looking at the source code.
First option is to just have it as a PWM receive pin as usual, and send UART data in such a way that it looks like pulses of PWM signal.
The PWM pin could also be used as UART receive pin if there is no valid PWM. For example waiting a few seconds for any pulses if it is UART data and if nothing happens or it is not valid UART data then start normal PWM reception.
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H: From breadboard to PCB, MOSFET not able to control load
I designed a simple circuit like the one in picture to control a load:
Basically, if I'm viewing this the right way, I have a GPIO from an Arduino on the D6 point to control a MOSFET (it's actually a 30N06L one, not the 1N4007) to decide if on the load (PUMP2) I have a flow of current (the difference between the PUMP source -- 24V -- and the ground, which is on the source of the MOSFET).
This works great, when I set the GPIO to high, the load starts, when I set it to low it stops. I correctly read the value of desired voltage on the load accordingly.
It works very well when I implemented this circuit on a breadboard. Then I made a PCB out of it and this screenshot is directly from Fusion360. I populated the PCB and tested without the load, and it works. Again, GPIO to high, I do see 24V-0V on the two pins of the J2 component (a connector for the load); GPIO to low, I do see 24V-24V on the same two pins.
However, once I connect the load (an electrovalve, just two wires, nothing fancy), once I set the pin to high I read a delta voltage of about 6V (one pin stays to 24Vish, the other goes to 18Vish). Why is that? What is wrong with the PCB? What I forgot to consider? Again on the breadboard, same scheme, same load, same components, everything works just fine.
Following, the full schematic of the pcb (the breadboard has the same circuit).
AI: I found the issue. There was a pin on the Arduino headers on the PCB that was not welded correctly (The GND was not GND...). Re-welded and now everything works as supposed to.
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H: Voltage Drops to 0 When Load is Connected
I have put together a simple voltage regulator that uses an LM338 IC and a potentiometer to adjust the voltage. On the output, I also put an inline 3A fuse to protect it from overloading.
(the diagram shows a different IC although I did use the LM338)
I am trying to power a light bulb using this power supply rated at 4V and 3A.
When measuring the voltage without load it shows 3.9V, but when I connect it to the light bulb it then drops to 0V. Also connecting an ammeter shows that it is only drawing 0.1A which seems too low.
I am not sure why this is the case and would appreciate any suggestions.
AI: With a 5V input, the highest possible "official" output from that voltage regulator is 1.2V (\$V_{REF}=1.2V\$) lower than this, which is 3.8V.
Under load, this value decreases rapidly. At 3A of load, the drop-out voltage exceeds 2V, and you cannot expect more than 3V output, with a 5V input.
You've overestimated this regulator's ability to provide 4V, both in terms of drop-out and its internal reference. The only way you can guarantee 4V out from this thing (under load) is if you increase input voltage to 7V or more.
The only reasons (I can think of) that it outputs 3.9V at all, with no load, is because it's operating way outside of its specified limits, or it's broken. I don't think it's broken.
You need to study the datasheet, and learn what this thing can and can't do. In particular, learn how to calculate exactly what resistance RP1 should be, to obtain the exact output you require.
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H: How can I decrease the update rate of the analog conversion?
I'm working on this analog converter circuit. The potentiometer is connected to pin AN0. The resistance value is shown on a 7 segment display. The circuit works fine but the ADC's update rate is too fast. I want to decrease the update rate of the ADC converter (I want the value to slowly change if that makes sense.) I have some ideas about how to solve the issue:
Getting the average of every 10 or so resistance values and show that on the display.
Slowing down the convertion process by changing the prescaler value of the ADC (but it can't be set more that 1/64.)
If you have any other ideas or know how I can actually apply my solutions I would appreciate it.
Details about the project:
Microcontroller: PIC18F4620
Potentiometer: 2k Ohm
ADC code (the rest of the code is about the 7 segment display):
setup_timer_0(RTCC_INTERNAL | RTCC_DIV_16 | RTCC_8_BIT);
set_timer0(160);
setup_adc(ADC_CLOCK_DIV_64);
setup_adc_ports(AN0);
Schematic:
AI: It's usually desirable to not update the display too frequently, say more than 3x per second. Around 2x-3x per second is good. Too low an update rate and the lag is irritating to the user. Too fast and you could get numbers flipping back and forth between two values leading to a confusing display.
If your reading rate is, say 100x per second you could simply add every 32 values then arithmetic right-shift 5 bits (divide by 32) and display. That's effectively a boxcar FIR (Finite Impulse Response) filter. That would give you a display update rate of about 3x/second. You just have to ensure that the sum does not overflow. If you add up enough readings and there is enough of the right kind of noise in the reading you may be able to effectively increase the resolution of the ADC by as much as \$\log_2(\sqrt{\text n})\$ bits, where n is the number of readings.
If you want filtering beyond reducing the update rate, one easy approach is to insert an IIR (infinite impulse response) filter. That's very simple if you have periodic ADC reads (fixed period). The concept is to pick some number \$\alpha\$ < 1 and each time you do an ADC conversion you update the value v with reading r as follows:
v = v(1-\$\alpha\$) + r(\$\alpha\$), and then display v
If \$\alpha\$ = 1 you have instant updates and the history does not matter. As \$\alpha\$ approaches zero the display takes longer and longer (in terms of sample times) to approach the ADC reading. Mathematically, it never quite gets there, but it gets close enough. If you don't have floating point available you would have to do some scaling to use integer math. You can also find approximate formulas for the -3dB cutoff frequency of the IIR filter, but if you're not thinking in those terms I doubt it will be helpful.
The two approaches can be combined, and you can certainly use more sophisticated filtering techniques but the above may be enough. Here is a paper that describes moving average filters, for example. The rabbit hole is deep on signal processing.
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H: Altium count number of selected vias
Is there a way in Altium to count the number of selected vias? For example, the below figure shows 9 vias, which are manually countable. In some layouts where I have a lot more than that, how should I keep track of the number of vias?
AI: In the PCB panel (View > PCB), you can select "Pad & Via Templates" from the menu at top and are presented with a list of every via type (template) used in the PCB, which includes the counts for each:
Selecting any of the listed templates will select/highlight those vias for you to verify.
Alternatively, if you select only the objects you are interested in, there is a count for the number of selected objects at the bottom of the Properties panel:
Finally, if your reason for counting vias is for drilling purposes or cost estimation, know that there is a drill table which your PCB fabricator will usually request. The drill table lists all drill hits (holes) with their dimensions. You can place a drill table (usually somewhere off-board, and usually on a mechanical or "drill guide" layer) by selecting Place > Drill Table from the menu. Here is an example:
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H: Why are via stubs not avoided?
Via stubs are defined as the part of a via that is not used for signal transmission. Via stubs cause all sorts of problems, but I just don't understand why they happen in the first place.
Can't you just not make a via stub and keep only the part of the via used for signal transmission?
I can see two explanations for this:
The via stub serves a purpose
The via stub does not serve a purpose, but it's easier for the electronics design automation (EDA) software to just place it there, or it facilitates manufacturing in some way
AI: It is to avoid blind and/or buried vias. These are much more expensive to produce compared to a through via.
To avoid stubs you need to use either a blind or buried vias:
The Through-hole via is very cheap and easy to manufacture since it can be done after laminating. The blind and buried vias are much trickier to assemble and require more steps.
In most cases this is not a problem and through hole vias can be used. When working with very high frequencies, the stubs may become a problem and the more expensive process must be used.
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H: Should I protect against collapsing field effects of a microcontroller-driven small-signal relay coil?
I am building a simple engage/bypass switch for musical (e.g. electric guitar) effects. The signal switching will be done by a single coil (bistable) latching relay, such as the Panasonic TQ2-L-5V. The user interface is a momentary SPST footswitch. Between the footswitch and the relay is small microcontroller (e.g. ATtiny13), which is responsible for recognizing the switch press, and in turn toggling the relay state (and a status indicator LED).
The single coil (bistable) latching relay works by applying a short current pulse (e.g. 3ms) at a specified voltage (e.g. 5v in the case of the TQ2-L-5V). The direction of the pulse is used to distinguish desired relay state (i.e. if the relay is "on" or "off").
There are examples of this available on the web, e.g:
Amplified Parts: Relay True Bypass Switching
mas-effects relay bypass
My concern with these kinds of circuits is that the microcontroller's IO pins are direct-connected to the relay coil. Here is a simplified schematic:
+------------------+
| microcontroller |
+------------------+
| |
gpio-1 gpio-2
| |
| |
+--[relay coil]--+
Basically, to set the relay to one state, gpio-1 goes high, and gpio-2 goes low for a short duration. And vice-versa to set the other state.
The question is, should additional circuitry be added to protect the MCU from effects of the relay coil's collapsing field? For example, an H-Bridge?
This circuit certainly works. I have successfully implemented it for several microcontrollers; not to mention the examples above and countless others. But I am concerned about long-term reliability/longevity. Might the (theoretical) infinite voltage temporarily seen by the MCU pins after relay state change (due to the coil's collapsing field) shorten the lifespan of the MCU?
AI: There is much room for improvement in your design. It may appear to work with some MCUs but it might really not. Loads that are this heavy and inductive should really not be driven directly from IO pins even if you add protection.
The 5V coil is said to have a 250 ohm coil resistance, so it is a 20mA inductive load.
And data sheet recommends a 10ms pulse at rated coil voltage, so in your case of driving a 3ms pulse with weak IO pins that can't reach rated voltage under 20mA load may not always work.
For your example of ATTiny13, while the absolute maximum IO pin current is 40mA, it means a fault state such as short circuit. The rated current is 20mA, where voltage may be as low as 4.2V instead of 5V on the high side, and what's worse there can be as high as 0.7V on the low side instead of 0V.
So there will not be 20mA over the coil as the IO pins can't provide 5V to that load. Fortunately the relay is rated to only need 3.75V to successfully work, and it only needs about 15mA for that. The ATTiny13 pins are barely rated to provide 15mA at 3.75V to coil under varying temperature conditions, so it may work at room temperatures but not at elevated temperatures. And does not assume any tolerance or deviation down on the 5V supply voltage.
And in fact the IO pins are push-pull outputs, and so they already do count as a H-bridge that drives the coil. It's just that those IO pins are quite a weak as a H-bridge so they can barely drive the coil.
And when you asked if IO pin protection is needed, well, the IO pins of the ATTiny13 already have internal clamping diodes as protection. They just are not meant to be used on purpose for that job so every circuit that relies on them by design is a bad circuit. As there is no other mention how much clamping current they tolerate, likely they can handle the absolute maximum of 40mA, and they withstand voltages up to 0.5V above supply and 0.5V below ground.
So actually, when current flows in the coil, and you set both IO pins low to stop driving the coil, the 20mA still needs to decay down, and while one IO pin sinks it to ground or almost down to 0V through NFET, the other IO pin must source current and it will be clamped to -0.5V by the coil pulling 20mA through protection diode from the other IO pin.
The other option to stop driving the coil is to set both IO pins into high impedance mode. In this case, the coil current needs to decay from the initial value, and so the rated 20mA must flow through IO pins. It will be limited by the internal clamping diodes to about 6V, because one IO pin can be pushed up to 5.5V and the other pushed down to -0.5V by the coil and the current might end up out of the MCU supply pins and it will try to push the supply voltage higher. This must be catched by capacitors or zeners or something before supply rises too much to damage the MCU, limit being 6V for ATTiny13.
So in reality, you should add four schottky diodes to clamp voltages to about 0.3V above supply and 0.3V below ground. And preferably use external FETs or some IC to drive the relays instead of using the IO pins directly.
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H: Generating a solid 5V output from a buck converter whose output varies from 4.8V to 5.2V
I have a buck converter whose output varies from 4.8V to 5.2V. This buck converter is present in my VCU. Input for the buck converter can vary from 8V to 14V.
The 5 volt rail is powering many IC's present on the board, and for those IC's, this 4.8V to 5.2V is fine and there are no issues.
The same output from this buck converter is provided as a reference voltage for the vehicle's throttle.
Since the output of the buck converter is varying, the throttle output also varies, which is not acceptable.
What circuit can I use to generate a constant 5V from this varying 4.8V to 5.2V buck output?
Inviting your thoughts/suggestions.
AI: Design away the problem. Measure both the reference voltage (that is, your 5V) for the throttle and the throttle output itself and compute a ratio to determine throttle position. Then you can reject variances in the reference.
Otherwise, create local, stable reference at a lower voltage to use for your throttle voltage reference. You'd still want to measure it as a ratio regardless.
Also consider redundancy for your throttle sensor. In FuSa (functional safety) -speak, it would be an ASIL-D (highest level) component since its failure would lead to an uncontrollable condition resulting in a possibly fatal crash.
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H: Green vs black capacitor (aluminum)
I seem to have defective capacitors on a board and I am looking at buying new one to change them.
The actual capacitors are green. I noticed that the green ones are more expensive than the black ones (same voltage same capacitance) so I was wondering if there was a difference between them.
AI: There is no correlation between the color of the shrink wrap insulation and the performance of the capacitor across manufacturers. Some may like green with gold printing, others black and white. Some may use different colors for different model lines. You need to look at model numbers and specifications as well as the voltage and temperature rating on the capacitor. And some manufacturers are thought to be better than others.
Key specifications:
Capacitance (same or a little bit higher is fine) generally marked clearly
Voltage rating (same or a bit higher is fine) generally marked clearly
Temperature rating (this translates to life span in most cases) generally marked clearly
Low impedance vs. standard (if they're bulging caps on a mombo they likely need to be low impedance) usually not marked
Size (if you want it to fit an existing board)
There are other things like bipolar vs. non-polar vs. standard (rare for the former two types to be in an application where they fail in bunches), polymer electrolytic types etc.
If you can't find any specifications for the part in the board (there are a great many makers of electrolytic capacitors and only a handful have good datasheets in English easily available) post some clear photos of the caps and a wider angle shot of the application (and a description) and we can probably provide some advice, maybe even good advice.
If the device is very old (20-30 years, say) even good quality replacement parts may be surprisingly small by comparison with the originals.
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H: High gain low current amp
I'm trying to design high gain, low collector current Common Emitter amplifier.
As far as I know, this is well known CE amp for high gain.
Is there anything I can do for low-current consumption? And I would really appreciate it if you let me know the methods to decide resistor values for high-gain, low-current
AI: One way to reduce current consumption in a CE amp is to use self-biasing instead of voltage divider biasing.
Basically you remove R2, and connect R1 to the collector instead of the positive supply. Now all of the bias current goes into the base instead of some being shunted to ground. It also makes biasing pretty easy, since it adjusts itself to some degree it's rather forgiving of resistor values.
Something like this for instance will give you around 45 dB of gain at around 500 uA current draw. Note that it needs to be followed by a stage with high input impedance, typically at least 10 times the collector resistance (indicated by the 100k load here), the following stage can be something like an emitter follower as it only needs current gain.
simulate this circuit – Schematic created using CircuitLab
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H: What causes LED1 to light up slightly when powered?
The main goal of this circuit is to limit the current if the output side is shorted. LED1 Lights up when output is shorted. LED2 lights up with output isnt shorted. U1 is a 12V regulator with current limiting features.
Problem: Why does LED1 light up when I apply 13.91V input voltage, even though it should not? Is this because the excess voltage is being dropped over LED1, given that the Vdrop is 12?
Can I added a resistor in parallel to the LED to bleed it out? Is that the best solution?
AI: According to the LED's datasheet, its typical forward voltage at rated current (20mA) is 1.95V. When you apply 13.91V to the input, 13.91V - 12V = 1.91V drop across the LED (and series resistor). I'd be surprised if the LED didn't light up under these conditions.
Adding a resistor in parallel to the LED will work. It will form a voltage divider together with R1 to lower the voltage across the LED while the circuit is in operation. As a rough guesstimate, you could use 220 Ohms to raise the voltage differential at which the LED begins to light roughly threefold. If that prevents the LED from lighting when you want it to, increase the value.
Note that the resistor has to go directly across the LED's pins.
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H: How do I calculate the RPM and torque of a 12 V DC motor that gets 5 V?
I have a PCB that outputs 5 V to each of the two motors. It was part of a robotics kit that included two 12 V 360 RPM motors.
I want to attach a 12 V DC motor with 3500 RPM. How do I calculate how much RPM or torque I can expect to see?
AI: The torque you see depends on how much load you actually apply to the motor. I think what you're asking is how much torque it is safe for the motor to produce.
But you can't calculate anything unless you know the stall torque of the motor at some voltage and the no-load RPM at that same voltage.
Stall torque and no-load RPM approximately scale with the voltage. So double the voltage, you double the no-load RPM and double the stall torque.
DC motors produce zero torque at no-load RPM and stall torque at zero RPM, with a straight line running between the two. In other words the torque vs RPM curve is linear.
As a rule of thumb for DC motors, maximum efficiency happens at about 1/7th of stall torque or or 6/7ths of no-load RPM (these correspond to the same point on the curve). Maximum power output happens at 1/2 of no-load RPM and 1/2 of stall torque (again, these correspond to the same point on the curve). You want to run the motor at one of these points if possible based on your priorities, or at least in between these two points.
It is better to load the motor a bit more than the torque required for maximum efficiency than to underload it since the efficiency drops off much more as you load it below this point than if you overload it.
Note that rated RPM and rated torque are different numbers. These are numbers the designers think you would probably want to run the motor at for a good compromise between efficiency and power output for the weight of the motor (as well as other usage considerations).
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H: Delaying falling edge, and faster rising edge for output signal
I'm trying to take an incoming signal to use as an output, but that output (active low) needs to be enabled about 20ns after the incoming signal goes low, and then go high again about 20ns before the incoming signal goes high. I'm using a 50MHz clock, so just one cycle is needed on either end.
What I've tried:
input signal_in; //incoming signal, active low
input clk; //50MHz clock, 20ns cycles
output signal_out_n; //output, active low
reg delay_sig;
always @ (posedge clk)
begin
delay_sig <= signal_in;
end
wire fallingEdge <= delay_sig & !signal_in; //if delay is 1, and signal is 0, we have incoming falling edge
wire risingEdge <= !delay_sig & signal_in; //if delay is 0, and signal is 1, we have incoming rising edge
assign signal_out_n = ??
How do I assign this output so that falling, rising and incoming signals are accounted for? I've tried:
signal_out_n = {fallingEdge,risingEdge,signal_in}==3'b000 ? 1'b0 : 1'b1;
... where fallingEdge and risingEdge would both be a 0 when neither is upcoming, so we'd go low when signal_in goes low. But I'm sure this needs to be done differently...
Any help would be appreciated.
AI: I assume your input is asynchronous to the clk. The following circuit can generate a delay on the falling edge and almost no delay on the rising edge.
The falling edge delay can vary between 1-2 clk cycles because the input is asynchronous to the clk. The delay won't be fixed.
You cannot generate an output that goes high before the input goes high. At best, you can make the output go almost when input goes high (after some combo delay) like in the circuit above. If you do need to generate an output which rises before the input, you can delay the input signal like in the picture below. The rising edge output is early w.r.t the delayed input and falling edge is delayed w.r.t the delayed input. The above circuit needs some modifications to achieve this.
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H: Transformer design problem
I will try my best because my English is not the best. Thanks!
I'm designing a transformer for a PCB that I made. The circuit in the PCB accepts 5 V to 20 V in.
So the transformer that I made is for 220 VAC 50 Hz but you can put 380 VAC, because (this is the part when I don't know if it's okay). I will have in the output of the transformer this:
220VAC-10VAC and 380VAC -> (380 VAC × 10 VAC) / 220 VAC = 17.27 V.
And yes, I did it and it functions perfectly, but it gets hot when I apply 380 VAC. This is the data of the transformer I made:
Vout: 8 V . Vrms: 8 V / (root 2) = 5.65 + 2.3 V for losses and diodes. = 8 V
I Secondary max: 0.25 A
I Primary max : 2 W / 220 V = 0.009 A = 9 mA
Potency: 0.25 A × 8 V = 2W
Core: 2 cm × 1 cm = 2 cm2
Pmax Core: 2 cm2 × 2 cm22 = 4 W
V1/V2= 220 / 8 V = 27.5
Turns = 42 / (2 cm2) = 21 Turns x volt
Pturns= 21 × 220 V = 4620 Turns
Sturns = 21 × 8 V = 168 Turns
Diameter of primary: 0.09 mm
Diameter of secondary: 0.25 mm
I used copper non-oriented grain silicon steel, thickness: 0.5 mm, losses: 1.8 - 2.2 W/kg
The circuit doesn't consume more than 100 mA when it gets hot, I think that the primary more. The transformer also vibrates more than normal, so I suppose that it's overloaded. Should I add more turns? Should I add more thickness to the copper?
AI: I'm guessing that you are running in to core saturation issues.
The minimum number of turns to prevent saturation is given by
$$ N = {E_{pk} \over {\omega \cdot B_{pk} \cdot A_e}} $$
Where:
\$ E_{pk}\$ = peak sine wave voltage. Multiply by 1.57 for a symmetrical square wave.
\$\omega\$ = radian frequency = \$2\pi f\$
\$A_e\$ = effective area of the core [\$m^2\$] (refer to the core data sheet)
\$B_{pk}\$ = peak flux density when the core saturates [\$T\$] (refer to the core data sheet)
Silicon steels generally saturate in the 1.1 to 1.5 Tesla region.
When designing transformers, I like to keep the magnetizing inductive reactance >5x higher than the load (or reflected load) impedance so the magnetizing current isn't significant compared to the load current.
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H: How does this current sink work (Figure 15 LM675)
Here is figure 15 of the LM675 datasheet. I was interested in it because it shows an opamp voltage-controlled current device that doesn't include a FET. The LM675 is a power opamp that can source and sink 3A.
I've been trying to figure out how to derive the figures in the bottom right (I_out = 2.5 Amp/Volt * V_in), and how to select the potentiometer value for R_out.
I tried to do some nodal analysis:
Shortcut constants:
R_out is the resistance between the opamp output and GND.
It is equal to 4 + [(10k + 200 potentiometer + 1k) || R_load]
k is the ratio between V+ and V_out, since is being connected through a voltage divider.
V_out (the output of the opamp) = A(V+ - V-)
V+ = k * V_out
KCL: (V_in (the input) - V-) / 1k = (V_out - V-) / (10.1k).
I isolated V- to be equal to (10.1 / 9.1) V_in - V_out
After solving and taking the limit of A to infinity, I got:
V_in = ( (1k / 10.1k)(1-k) + k ) V_out
Here's where I got stuck. This is supposed to be a constant current device, but the output
voltage depends on k, which in turn depends on R_load. I can't find a way to make R_load disappear, and I don't know whether it's supposed to since there's a potentiometer to tune it.
How can I derive / modify the current to input voltage ratio?
AI: I don't fancy doing a complete precise-to-the-ohm analysis of this, and it's not really necessary. Instead, we can make some observations which will really simplify things. Start with a suitably labelled schematic:
simulate this circuit – Schematic created using CircuitLab
For example, we can say that negative feedback will cause the op-amp to adjust its output \$V_X\$ to whatever potential is necessary to equalise the potentials of its two inputs, \$V_P\$ and \$V_Q\$. That fact would eventually emerge from a complete analysis, as a consequence of taking the limit as \$A\rightarrow \infty\$, but it's much easier to start with this equality:
$$ V_P = V_Q $$
A second observation is that current in \$R_4\$ and \$R_3\$ is three orders of magnitude smaller than load current in \$R_L\$. I'll make the statement that:
$$ I_L = I_S $$
This allows us to avoid the ugly arithmetic associated with the parallel combination of \$(R_3+R_4) \parallel R_L\$. Then we have this simple expression for \$V_Y\$:
$$
\begin{aligned}
V_Y &= V_X - I_SR_S \\ \\
&= V_X - I_LR_S
\end{aligned}
$$
Perhaps you already see the implication that any algebra from this point on is independent of \$R_L\$. Perhaps, also, you begin to see the role that \$R_S\$ is playing here, somehow involved in setting transconductance, the ratio \$\frac{I_L}{V_{IN}}\$.
Let's continue, though:
$$
\begin{aligned}
V_P &= V_Y \frac{R_3}{R_3+R_4} \\ \\
&= \frac{10}{111}V_Y \\ \\
&= \frac{10}{111}(V_X - I_LR_S) \\ \\
\end{aligned}
$$
Also:
$$
\begin{aligned}
V_Q &= V_{IN} + (V_X-V_{IN})\frac{R_1}{R_1+R_2} \\ \\
&= V_{IN} + (V_X-V_{IN}) \frac{10}{111} \\ \\
&= \left(1 - \frac{10}{111}\right)V_{IN} + \frac{10}{111} V_X \\ \\
&= \frac{101}{111} V_{IN} + \frac{10}{111} V_X \\ \\
\end{aligned}
$$
Since \$V_P=V_Q\$, we can equate these two expressions, and rearrange to find \$I_L\$ as the subject:
$$
\begin{aligned}
\frac{101}{111} V_{IN} + \frac{10}{111} V_X &= \frac{10}{111}(V_X - I_LR_S) \\ \\
10.1V_{IN} + V_X &= V_X - I_LR_S \\ \\
I_L &= -10.1\frac{V_{IN}}{R_S}
\end{aligned}
$$
It seems that you must adjust \$R_S\$ to set your desired relationship between \$I_L\$ and \$V_{IN}\$. Also, as long as \$R_3\$ and \$R_4\$ are large compared to \$R_S\$. this relationship is independent of load resistance \$R_L\$.
The last thing to address is the role of the potentiometer in the original circuit. It allows you to change the transconductance (closed-loop gain) very slightly, above and below the center value of −10.1 calculated above.
Essentially, it makes \$R_4\$ variable between 10.0kΩ and 10.2kΩ, permitting transconductance to be adjusted to exactly \$-2.5AV^{-1}\$. Other than this "trimming" role, it has no significant influence over transconductance, which is squarely in the hands of \$R_S\$.
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H: MOSFET between LED and driver for PWM dimming?
So I found a lot of cheap nice LED lamps with some generic cheap non dimmable LED driver. I like dimming.
The LED is something like 18 V, 250 mA.
Could I stick something like an ESP32 with a MOSFET between the driver and the LED, and do PWM dimming?
My doubt is if the PWM will confuse the cheap driver somehow, because it assumes that the LED is a constant (current?) load.
AI: You guessed right: the constant current driver regulates its output voltage to keep average load current constant.
If you add a PWM on the LED at the output, and you reduce the PWM value to dim the LED, it will reduce average current, and the driver will respond by increasing voltage until average current returns to the set value.
From others who have tried it on this forum, the result is constant brightness no matter what the PWM value is in a rather wide range, then at low PWM values the driver hits its maximum output voltage. When that happens it may shut down or go to a powersave mode that will blink because it thinks the LED is disconnected.
In other words, it's not going to work at all.
Also you can't power the ESP32 from the driver's output because ESP32 draws variable current. So every time it does something with WiFi it will draw a spike of supply current, and with a constant current driver this means the LED current will decrease, causing dips in brightness.
You'd need a constant voltage supply, a buck converter to supply the ESP32, and a separate DC-DC driver for the LED.
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H: STM32F407VE Change/Update IP Address Issue
I have a big problem to change IP Address without restart STM32F407VE.
I'm working on STM32F407VE TCP/IP ethernet protocol (IAR9.30.1).
I am able to transmit data to arm and receive to pc terminal (putty, teraterm).
I'm using project lwipWebserver.ewp .eww copied from
c:\ARM_ST_9.30.1_50027_Downloadly.ir\ST\STM32F4xx\IAR-STM32F407ZG-SK\WebServer
I copied from Examples:
from ARM_ST_9.30.1_50027_Downloadly.ir\ST\STM32F4xx 3 folders:
IAR-STM32F407VE (previous IAR-STM32F407ZG-SK)
Libraries
STM32F4xx_DSP_StdPeriph_Lib
Everything works fine if I set the IP Address 192.168.1.114 only once:
main.c:
u32_t ip_addr_arr[4];
ip_addr_arr[0] = 192;
ip_addr_arr[1] = 168;
ip_addr_arr[2] = 1;
ip_addr_arr[3] = 114;
LwIP_Init_New(&ip_addr_arr[0]); // &ip_addr_arr[0] or ip_addr_arr
Windows10: cmd:
ping 192.168.1.114
OK
But if I try to change the IP Address from 192.168.1.114 to 192.168.1.113 while the program is running, then problems start:
it works for a few seconds, then it stops working: main.c:
ip_addr_arr[0] = 192;
ip_addr_arr[1] = 168;
ip_addr_arr[2] = 1;
ip_addr_arr[3] = 113;
LwIP_Init_New(ip_addr_arr); // &ip_addr_arr[0] or ip_addr_arr
Windows10: cmd:
ping 192.168.1.113
Not OK
I changed LwIP_Init to LwIP_Init_New:
C:\ARM_STM32F407_PRJ\IAR-STM32F407VE\WebServer\app\httpserver\netconf.c
void LwIP_Init_New(u32_t* ip_addr_array) // minem
{
struct ip_addr ipaddr;
struct ip_addr netmask;
struct ip_addr gw;
/* Initializes the dynamic memory heap defined by MEM_SIZE.*/
mem_init();
/* Initializes the memory pools defined by MEMP_NUM_x.*/
memp_init();
#ifdef USE_DHCP
ipaddr.addr = 0;
netmask.addr = 0;
gw.addr = 0;
#else
// IP4_ADDR(&ipaddr, IP_ADDR0, IP_ADDR1, IP_ADDR2, IP_ADDR3);
// IP4_ADDR(&ipaddr, *ip_addr0, *ip_addr1, *ip_addr2, *ip_addr3);
IP4_ADDR(&ipaddr, ip_addr_array[0], ip_addr_array[1], ip_addr_array[2], ip_addr_array[3]);
IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1 , NETMASK_ADDR2, NETMASK_ADDR3);
IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3);
#endif
/* - netif_add(struct netif *netif, struct ip_addr *ipaddr,
struct ip_addr *netmask, struct ip_addr *gw,
void *state, err_t (* init)(struct netif *netif),
err_t (* input)(struct pbuf *p, struct netif *netif))
Adds your network interface to the netif_list. Allocate a struct
netif and pass a pointer to this structure as the first argument.
Give pointers to cleared ip_addr structures when using DHCP,
or fill them with sane numbers otherwise. The state pointer may be NULL.
The init function pointer must point to a initialization function for
your ethernet netif interface. The following code illustrates it's use.*/
netif_add(&netif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, ðernet_input);
/* Registers the default network interface.*/
netif_set_default(&netif);
/* When the netif is fully configured this function must be called.*/
netif_set_up(&netif);
}
Would you tell me how to change the IP address to the second, third and fourth, etc. without restarting STM32F407VE?
AI: If you want to change the IP address during runtime (while using static IP addressing), you need to call netif_set_addr followed by netif_set_up.
An example taken from TivaWare:
//*****************************************************************************
//
// Completes the network configuration change. This is directly called when
// not using a RTOS and provided as a callback to the TCP/IP thread when using
// a RTOS.
//
//*****************************************************************************
static void
lwIPPrivateNetworkConfigChange(void *pvArg)
{
uint32_t ui32IPMode;
struct ip_addr ip_addr;
struct ip_addr net_mask;
struct ip_addr gw_addr;
//
// Get the new address mode.
//
ui32IPMode = (uint32_t)pvArg;
//
// Setup the network address values.
//
if(ui32IPMode == IPADDR_USE_STATIC)
{
ip_addr.addr = htonl(g_ui32IPAddr);
net_mask.addr = htonl(g_ui32NetMask);
gw_addr.addr = htonl(g_ui32GWAddr);
}
#if LWIP_DHCP || LWIP_AUTOIP
else
{
ip_addr.addr = 0;
net_mask.addr = 0;
gw_addr.addr = 0;
}
#endif
//
// Switch on the current IP Address Aquisition mode.
//
switch(g_ui32IPMode)
{
//
// Static IP
//
case IPADDR_USE_STATIC:
{
//
// Set the new address parameters. This will change the address
// configuration in lwIP, and if necessary, will reset any links
// that are active. This is valid for all three modes.
//
netif_set_addr(&g_sNetIF, &ip_addr, &net_mask, &gw_addr);
//
// If we are going to DHCP mode, then start the DHCP server now.
//
#if LWIP_DHCP
if((ui32IPMode == IPADDR_USE_DHCP) && g_bLinkActive)
{
dhcp_start(&g_sNetIF);
}
#endif
//
// If we are going to AutoIP mode, then start the AutoIP process
// now.
//
#if LWIP_AUTOIP
if((ui32IPMode == IPADDR_USE_AUTOIP) && g_bLinkActive)
{
autoip_start(&g_sNetIF);
}
#endif
//
// And we're done.
//
break;
}
//
// DHCP (with AutoIP fallback).
//
#if LWIP_DHCP
case IPADDR_USE_DHCP:
{
//
// If we are going to static IP addressing, then disable DHCP and
// force the new static IP address.
//
if(ui32IPMode == IPADDR_USE_STATIC)
{
dhcp_stop(&g_sNetIF);
netif_set_addr(&g_sNetIF, &ip_addr, &net_mask, &gw_addr);
}
//
// If we are going to AUTO IP addressing, then disable DHCP, set
// the default addresses, and start AutoIP.
//
#if LWIP_AUTOIP
else if(ui32IPMode == IPADDR_USE_AUTOIP)
{
dhcp_stop(&g_sNetIF);
netif_set_addr(&g_sNetIF, &ip_addr, &net_mask, &gw_addr);
if(g_bLinkActive)
{
autoip_start(&g_sNetIF);
}
}
#endif
break;
}
#endif
//
// AUTOIP
//
#if LWIP_AUTOIP
case IPADDR_USE_AUTOIP:
{
//
// If we are going to static IP addressing, then disable AutoIP and
// force the new static IP address.
//
if(ui32IPMode == IPADDR_USE_STATIC)
{
autoip_stop(&g_sNetIF);
netif_set_addr(&g_sNetIF, &ip_addr, &net_mask, &gw_addr);
}
//
// If we are going to DHCP addressing, then disable AutoIP, set the
// default addresses, and start dhcp.
//
#if LWIP_DHCP
else if(ui32IPMode == IPADDR_USE_DHCP)
{
autoip_stop(&g_sNetIF);
netif_set_addr(&g_sNetIF, &ip_addr, &net_mask, &gw_addr);
if(g_bLinkActive)
{
dhcp_start(&g_sNetIF);
}
}
#endif
break;
}
#endif
}
//
// Bring the interface up.
//
netif_set_up(&g_sNetIF);
//
// Save the new mode.
//
g_ui32IPMode = ui32IPMode;
}
EDIT
u32_t ip_addr_arr[4];
ip_addr_arr[0] = 192;
ip_addr_arr[1] = 168;
ip_addr_arr[2] = 1;
ip_addr_arr[3] = 114;
LwIP_Init_New(&ip_addr_arr[0]); // :This is OK in main.c
********* We do some work then *********
// Then without restarting:
u32_t ip_addr_arr[4];
ip_addr_arr[0] = 192;
ip_addr_arr[1] = 168;
ip_addr_arr[2] = 1;
ip_addr_arr[3] = 109;
LwIP_Init_New(&ip_addr_arr[0]); // :This is no OK in the same session in the same main.c:
You shouldn't call LwIP_Init_New when the lwIP stack is already up and running. Instead, replace it with the following:
void LwIP_change_ip_cfg(u32_t* ip_addr_array)
{
struct ip_addr ipaddr;
struct ip_addr netmask;
struct ip_addr gw;
#ifdef USE_DHCP
ipaddr.addr = 0;
netmask.addr = 0;
gw.addr = 0;
#else
IP4_ADDR(&ipaddr, ip_addr_array[0], ip_addr_array[1], ip_addr_array[2], ip_addr_array[3]);
IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1 , NETMASK_ADDR2, NETMASK_ADDR3);
IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3);
#endif
/* Set the new address parameters.*/
netif_set_addr(&netif, &ipaddr, &netmask, &gw);
/* When the netif is fully configured this function must be called.*/
netif_set_up(&netif);
}
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H: Identify and replace capacitor "FP12K 79AJ 271 16"
Unfortunately a capacitor got knocked off from a mainboard. The mainboard is an AsRock Z370 Extreme4 (see here).
The capacitor is labelled as:
FP12K
79AJ
271
16
I want to replace it, but I am not sure what capacitor would be equivalent. What I found out is that it must be a "Nichicon 12K Black Cap". I think the "16" means 16 Volt, but I don't know what "79AJ" and "271" means.
AI: I couldn't find the datasheet for this exact capacitor from Nichicon, maybe these FP12K are ASRock specific, but one for the RHT series which has similar markings.
This means the capacitor in question is rated for 16V and has a capacity of 270uF.
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H: Salvage Motor From HDD Without Screws
I’ve searched everywhere and can’t seem to find how to salvage this motor from my wd10ears HDD. It seems most other HDDs have screws to take it out, but this one doesn’t. The centre screw is just round so that doesn’t get it out. If someone could let me know how to approach this, that would be great.
Thanks!
AI: A vise might have more chance of success than a hammer. If you have (or can make) a cylinder to press in the proper spot. Image from here
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H: Lithium Battery Protection DW01
I'm using DW01 to protect LiPo batteries. But since there are more than one source of voltage in the circuit, I need to add a diode to DW01's VCC pin for the situations that battery is removed and reverse voltage across battery protection circuit causes unwanted behavior.
The best schottky diode with least forward voltage drop that I have access to is BAT54C. Voltage difference across R1 (100 ohms) is measured 0.15V that indicates 1.5mA through it. Using BAT54C datasheet charts, if I replace R1 resistor with BAT54C I'll have almost 250mV voltage drop across it (@25'C).
I do not know the function of R1 in the circuit, so I can not tell if replacing it with a schottky diode that has almost same voltage drop will interfere with its functionalities or not.
Please guide me through this. Is R1 replaceable with a schottky diode? Or should I simply add the diode in series with it? Or this theory of mine is impossible all together!
AI: Normally you shouldn't need any series diode.
Also the IC monitors the battery voltage through its Vcc pin and stops charging/discharging based on the measured voltage. So, putting a series diode will cause the IC to measure a wrong voltage and therefore to change the behaviour of protections.
Instead, you can implement a very simple reverse polarity protection with a MOSFET (a.k.a. MOSFET ideal diode):
simulate this circuit – Schematic created using CircuitLab
NOTE: M1 can be 2N700x (7000 or 7002).
When the battery first applied with correct polarity, current will flow through M1's body diode first, so the M1's source voltage will be one diode drop above BAT- level. This makes the Vgs of M1 positive and turns it on. The voltage drop will be minimal. If the battery is applied with reverse polarity then the body diode of M1 will be reverse biased so no current (except a leakage of a few nA or pA) will flow.
I do not know the function of R1 in the circuit ...
R1-C1 pair is there to filter out any potential noise/ripple coming from the supply line to VCC pin.
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H: What is the difference between a hex inverting buffer and hex inverting Schmitt trigger?
What is the difference between an hex inverting buffer (e.g. TC74HC4049AP) and hex inverting Schmitt trigger (e.g. 74HCT14N)?
How can hysteresis be added to a CMOS hex inverting buffer to make it act like a Schmitt trigger, if they differ?
AI: The dfference is that the standard inverting buffers don't have hysteresis and the Schmitt trigger inverting buffer have hysteresis.
Hysteresis just means you have different levels for low going threshold and high going threshold, to have a margin for noise. Without hysteresis there is only one threshold to determine if a signal is high or low, so noisy signal right at the threshold level will just amplify the noise to output and noisy slowly changing signals have multiple noisy output transitions. Hysteresis can remove all that.
The hysteresis is added similar to how you would add feedback to an analog comparator to change the threshold of change.
As an internal block diagram it just has feedback from output back to input which will change the level where the input threshold is.
Instead of resistors the feedback can be done with weak PMOS and NMOS transistors in a CMOS chip.
In logic gate level, there is no difference except the standard inverter symbol has added the symbol to mean it's a Schmitt trigger inverter.
|
H: Is there a something similar to DSLR batteries to power up PCBs?
I'm working on a project that requires the user to regularly swap battery packs to keep an esp32 board running. For the prototype we are using one of these batteries that seem to be quite common to find:
Swapping this kind of battery is not a smooth process, and I think the connector might not be meant for regular mating.
Are there any batteries similar to those of DSLRs? or any other good alternatives?
I recently came across Duracell selling battery replacements for common DSLRs, the problem is that I'm finding it hard to find the terminals for these batteries so that we can add them to the final design of the PCB.
I'm aware that voltage and power wise these will vary a lot. I'm primarily asking for PCB components similar to those found in DSLR that can be bought commercially.
AI: the problem is that I'm finding it hard to find the terminals for these batteries so that we can add them to the final design of the PCB.
Consider instead batteries that have flush target pads, such as the ones used in cell phones, for example these.
Then, use spring-loaded contacts to mate to the battery (my site):
Pogo PCB pins
Pogo PCB header
Spring leaf PCB terminals
Spring leaf PCB header
{This is my picture}
|
H: Why do I a get different cut-off frequency in LTspice?
I have built a low-pass filter circuit according to the multifeedback topology using the values for the resistors and capacitors calculated with the help of this website.
According to the website, the cutoff frequency should be about 95 Hz.
I built the same circuit, with the corresponding values for the resistors and capacitors in LTspice. The simulation gives a different cutoff frequency.
The supply voltage U+ and U- are at +2.5V and -2.5V.
My guess is that the simulations use different op-amps to calculate the frequency response, but I'm not sure.
AI: The op-amp characteristics are not considered in the web page calculator.
If you change the Q to 0.707 (or the damping ratio to 0.707, this is the point where the two are equal) you'll get much closer to -3dB at the characteristic frequency using that calculator. That should be Butterworth response.
You can also pick E96 series resistors to get closer, but that's not the main issue here.
|
H: Crystal oscillator input power
I have seen many circuits in which they have connected the crystal oscillator with two capacitors as a clock for the microcontroller like atmega 16A. The first question I want to ask is whether the crystal oscillator with two capacitors provide any frequency or not..If it doesn't then why don't we connect a power to the oscillator before giving it to the microcontroller?
AI: Previous answers to your previous questions should already explain this.
What is connected to the MCU is just the crystal, not a crystal oscillator.
The oscillator circuitry for the crystal is in the MCU and is powered along the MCU.
The crystal, and the caps, they do nothing until connected to an active oscillator circuit that drives the crystal into oscillation.
Only when you combine the crystal, and an oscillation circuit for the crystal, you make a crystal oscillator.
Just like you don't have an RC or LC oscillator without the RC or LC components in a suitable oscillator circuit.
|
H: Do I have to use pull up/down resistor with switch with common terminal?
I have seen some examples why we need to use pull up/down resistors, but do I need to use it if I use switch with common terminal?
If I have the schema like so, do I need to use the pull up/down resistor anyway?
The input should either read high or low right?
AI: Typically switches are non-shorting (just as well, or you'd short out your power supply). The switch contact thus spends some finite time "open" each time it is switched. During that time (which might be some milliseconds) the MCU input could drift around or pick up noise. If that's not an issue you don't need the pullup or pull down.
Generally though it's inconvenient to use SPDT switches because of cost and availability of switch designs (SPST N.O. are much more common and cheaper- tact switches and membrane, for example) and extra wiring and typically there are internal pullups and/or pulldowns (though perhaps of too high value to be optimal for noise considerations) so the pullup/pulldown is most often used, either internal or external.
There may also be situations where you want a defined state even if the switch fails or is partially or completely disconnected. Or maybe the 'switch' is a jumper block and you can't count on the user to place it correctly and don't want to deal with the consequences of a floating input.
There is one clear advantage of your circuit, and that is that there is only leakage current drawn in either position, which could be a consideration for battery power. That's also a subtle issue in that most switches require a minimum "wetting" current to be guaranteed to work, and your circuit will conduct only nA typically. Here, for example, is a tact switch from a reliable manufacturer:
If the minimum current is not stated by the manufacturer, you should assume it's in the mA, especially if the part does not have precious metal contact materials.
|
H: Behavioral Sigma-Delta simulation error
I am trying to simulate a behavioral sigma delta modulator as shown in the circuit below. Basically, I am trying to sense the current through I1 by measuring the ratio of the number of times the voltage across the capacitor dips below some value relative to the number of measurements (number of clock cycles).
Here's the netlist for convenience.
C1 cap 0 10p
B1 comp 0 V=V(clk) > 0.5 ? (V(cap) < 5 ? 1 : 0) : 0
I1 cap 0 10µ
B2 vdd cap I=V(comp) > 0.5 ? 50u : 0
V1 vdd 0 1
V2 clk 0 PULSE(0 1 5n 100p 100p 5n 10n)
R1 cap 0 10Meg
.IC V(cap)=5
.tran 100n
Simulating the above circuit produces the following error with LtSpice. Any idea how it can be resolved?
AI: Adding GMIN across current sources solves your "time-step-too-small" problem.
Tools=>Control Panel=>Hacks!=>Set "Add GMIN across current sources" option.
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H: CAN Bus transceiver \$V_{RXD}\$/\$V_{IO}\$ pin confusion
I am looking for a widely available CAN Bus transceiver for a project. I have sorted by availability and found two options that seem to satisfy my criteria. However, they both have an extra pin that I do not completely understand the function of, so to my question:
For the SN65HVD266, what is the deal with the VRXD pin? It seems to me like it is some sort of level-shifting pin, but I am confused as it is described as a "Supply pin". In the typical application schematics, the VRXD pin is connected to the 3V voltage regulator, and also the VCC of the MCU, why is this?
The other transceiver is the MCP2562FD, which has a VIO pin, that seems to function in a similar way to VRXD, but here I am also confused by the description.
Could someone please clarify the function of these pins, and how I should connect them when using this transceiver with an ESP32-S3 MCU?
AI: "Vrxd" is the logic level supply. I guess they named it that way since it only powers the RX pin (the TX signal is driven by the MCU).
The CAN signals require 2.5V +/- 1V so at least 3.5V. This is no problem to achieve if the part is supplied with 5V. Classic CAN transceivers work with 5V logic levels on RX and TX and 5V supply. One example of this would be the MCP2551.
When there is only 3.3V supply available and the MCU requires 3.3V levels, one option is to use 3.3V supply on the transceiver and then tweak the CAN logic levels to 2.5V +/- 0.8V. On example of this would be the SN65HVD230 family.
Yet another option is to provide 5V supply to the transceiver but a variable supply to the logic levels. That's how both the parts you link work. The advantage of this is that you don't have to tweak the CAN logic levels in questionable ways, while at the same time allowing a 3.3V MCU to communicate directly with the transceiver. Most modern transceivers seem to have picked this option.
As for choosing between SN65HVD266 and MCP2562FD, that should be easy. SN65HVD266 is an older part with overall worse protection. Also Microchip is a well-known vendor, while TI is... not recommended for new design, by yours sincerely at least.
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H: How do I select whether the LSM6DSOX IMU Sensor uses it's SPI or I2C Interface
I am trying to use the LSM6DSOX IMU sensor which has both an SPI and an I2C interface which are mapped to the same pins. I want to address the IC using its SPI interface
(Datasheet for reference)
In the datasheet the following is said:
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied
high (i.e connected to Vdd_IO).
Wouldn't that mean that while the this IC is not selected that it is in I2C mode. Couldn't this result in this IC being accidentally addressed due to another IC being addressed on the same SPI BUS which happens to be receiving a command which corresponds to the LSM6DSOXs I2C address?
AI: The chip will start up with all interfaces enabled and listen to I2C bus protocol when SPI chip select is high and will listen to SPI bus protocol when SPI chip select is low.
When the chip has been powered up, you can configure it via SPI to not to listen to I2C protocol when SPI chip select is high.
That way any SPI transactions to other chips will not be interpreted falsely as I2C transactions.
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H: LTspice Half bridge current spikes
I simulated a half bridge with two NMOS and at every switching event a current spike up to 1.2 A in the voltage source V4 occurs. I used a resistor as load because with any inductive or capacitive load I would expect a spike because of the dead time between the MOSFETs.
Can the parastitic capacitance between Gate-Drain and Gate-Source be the reason or did I do something wrong in the simulation?
I know that the selected FETs are oversized but properly I need them for a higher load.
Schematic:
M1 Vsource Vg_HS Vnode Vnode IXFX90N30
M2 Vnode Vg_LS 0 0 IXFX90N30
V4 Vsource 0 100
R3 0 Vnode 1k
V1 Vg_HS Vnode PWL REPEAT FOREVER (0 5 0.00159999 5 0.0016 0 0.0033 0 0.0033000001 5) ENDREPEAT
V2 Vg_LS 0 PWL REPEAT FOREVER (0 0 0.001649999 0 0.00165 5 0.003249999 5 0.00325 0 0.0033 0) ENDREPEAT
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\hamsn\Documents\LTspiceXVII\lib\cmp\standard.mos
.tran 7m
.backanno
.end
AI: Can the parasitic capacitance between Gate-Drain and Gate-Source be the reason
Not quite. It's the Drain-Source capacitance.
If you check the spec sheet, Coss is 1 nF at 100 V.
I eyeballed the switching time to be 0.1 ms. The supply voltage is 100 V.
I = CV / T = 1 nF * 100 V / 0.1 ms = 1 A
That is darn close to the 1.2 A that you see reported.
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H: RISC-V byte load and store
I have the confusion in the following RISC V programming statements. Can someone explain that why does the contents of s0 in the last comment shown. shouldn't it be 0x00000180 the same as we are not messing up contents of s0. Also the contents of s2 would be 0x00000080? since the 24 bits should be ignored. Kindly explain this as I am confused.
AI: According to instruction set manual, the comment is correct.
The byte from lowest byte of register s2 (0x80) is stored to byte pointed by register (s0), but the offset in the opcode is 2.
Thus the result is written to byte offset s0+2, so the result will be 0x00800180.
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H: Why is my LC oscillator PCB design not working?
I'm building a simple FM transmitter to learn more about LC oscillators. I've successfully designed and built the following transmitter on a bread-board and perf-board using standard through hole components. For the 100 nH, I used this through-hole component.
It works adequately, not great quality, but sound comes through none the less. As an experiment, I designed a PCB using the same schematic.
Crucially, the conductor that I've used for my PCB is the TDK NLV25T-047J-EF. It has a Q value of 20 at 100 MHz and self resonant frequency at 1.2 GHz. I also used this 68 pF capacitor.
I should expect an oscillation around 89 MHz, however, I'm getting nothing near that on my oscilloscope.
Any tips on what I could change? I'm wondering if the traces are causing a lot of extra capacitance. Or perhaps, this is just the wrong type of inductor.
AI: A couple of things:
First, if you haven't already done so verify your board layout, you may have missed something, so go over it carefully and make sure all the connections are correct.
Second, you prototyped it with one value inductor and then used one with half that value in your finished design, meaning that you had to double the capacitance. The difference in the L/C ratio could be part of the problem.
Third, not absolutely necessary, but you have no means of tuning it. Usually there's a variable capacitor so you can adjust it to an unused frequency in the FM band. A good quality ceramic trimmer cap is recommended for this, cheap plastic ones will mostly just frustrate you.
I built some transmitters like this many years ago, I tried surface mount inductors similar to what you're using and for some reason had no luck at all with them. What I ended up using was a hand wound toroidal coil, it was something like 10 turns on a very small core and you have to get the right material mix for the frequency you're using. The advantages were that I could tweak the value by adding or removing a turn, and a toroid is self shielding so the frequency was barely affected by nearby fingers or metal objects the way a solenoid coil is. I think I have an image of it, will post it if I can find it.
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H: CAN Bus Inter Frame Spacing (IFS) -- Three Bits or Seven?
If you google around for the length of the CAN Bus Inter Frame Spacing (IFS), you can find some references that say it's 3 bits and others that say it's 7 bits.
Google Link for 3-bit search
Google Link for 7-bit search
Why is there this discrepancy? Did the minimum IFS get changed to 3 bits at at some point in the history of CAN Bus?
AI: The early CAN 2.0 specification, published in 1991, already specified an IFS field length of 3 bits.
An excerpt from chapter 3.2.5 on page 53:
3.2.5 INTERFRAME SPACING
DATA FRAMEs and REMOTE FRAMEs are separated from preceding frames whatever type they are [..] by a bit field called INTERFRAME SPACE. [..]
INTERFRAME SPACE
contains the bit fields INTERMISSION and BUS IDLE [..].
[..]
INTERMISSION
consists of three 'recessive' bits.
[..]
BUS IDLE
The period of BUS IDLE may be of arbitrary length.
I believe sources specifying a 7-bit IFS simply contain a typo or copy/paste error (which could be plausible, since the preceding EOF field is 7 bits in length).
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H: One FTDI Programmer, many Arduino
I have been playing with an idea of having multiple Arduino (e.g. ATmega328) with different purposes running on a circuit.
The intention would be to enable the FTDI programmer such as the FT232RL or FT231X chip to communicate to a specific circuit by switching these digital pins to one Arduino at a time to accomplish this programming.
The FT232RL or FT231X chip would be routed to a USB host whilst the programming pins would only be enabled on the selected Arduino.
My initial design idea was AND gates before I truly understood that Arduino Programming is a bi-directional communication process -- this would never work.
My next logical step is working with relays, this seems overkill for what I am attempting to accomplish considering cost and space on a board alone.
My specific implementation of this doesn't require any special considerations such as signal noise or loss. The Arduinos could be assumed to be on the same PCB operating over traces.
Does anyone have any other component suggestions that could accomplish this direct bidirectional connection whilst being switched on and off using a 5 V pin?
AI: Sounds like you need a tri-state buffer for each of the lines between the Arduino and the FTDI FT232RL or FT231X, such as the 74LS244 Octal Tri-state Buffer
You would have one of these for each Arduino, and connect the relevant IO pins to each of the buffers in the appropriate direction:
Arduino outputs to the An inputs of the buffer
Arduino inputs to the Qn outputs of the buffer
The same would apply to the IO pins of the FTDI IC
Assuming that there are a maximum of four lines in each direction between the Arduino and the FTDI IC (which I believe to be the case), then only one buffer IC would be needed per Arduino.
The fact that the buffer is tri-state means that you can isolate the Arduinos that are not needing to communicate with the FTDI IC, by disabling their buffers via the CA and CB inputs. Then enable the CA and CB inputs only on the buffer(s) connected to the Arduino that needs to communicate with the FTDI IC.
Clearly, only one set of buffers should be enabled at any one time.
You would also need to consider to enable and disable the buffers. That is to say, consider how these CA and CB pins, for each buffer, are managed. You could either manually control each one with a switch or, automatically, with an additional µController, with the appropriate glue logic. You could also have each Arduino manage their own buffers, but that would require some negotiation between the Arduinos to ensure that no conflict occurs - however, this seems to be adding unnecessary complexity.
Note that, if you have any bi-directional lines (although the FTDI ICs don't have any of those), then a bus transceiver, such as the TTL 74LS245, should be used.
Note that the term Arduino usually refers to the Arduino boards (such as the Uno, Nano, etc.). These boards already have a FTDI IC on them, so this would complicate matters.
However, if by Arduino, you actually mean an actual ATmega328P µController IC, then this method, as described above, should work.
Useful References
Bus Transceiver
74LS244
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H: frequency-dependent network equivalent in time domain simulations
I have this question that has been haunting me for a while now. We all know that the first solution we think of when willing to account for frequency-dependent behavior in time-domain simulations, is the usage of equivalent networks deduced from fittings reproducing the same frequency-behavior.
My question is the following: why is it that running the equivalent circuit in transient simulations (I use LTspice) we do not get Gibbs phenomenon? The frequency-behavior is fitted up to a certain maximum frequency, right? Hence, a truncation of the frequency behavior.
AI: You get the Gibbs phenomenom when you truncate the frequency domain behaviour. If we do an FFT and ignore all frequencies above Fmax, that's effectively setting all response above Fmax to zero.
When we fit models of real component networks to a small number of frequencies up to Fmax, the network response doesn't 'stop' at Fmax, it carries on, being steadily attenuated, being defined by those components to as high a frequency as the time domain simulation handles. It's this steady attenuation that prevents Gibbs ripples from being seen.
Because we don't fit the network above Fmax, the response up there might be incorrect. However, if it's a low pass response (as it would be if we feel it's useful to stop fitting at high frequencies), the response will carry on dropping more or less smoothly, and will not exhibit the Gibbs phenomenom. It may be wrong, but it won't show Gibbs. You can make an estimate of the unfitted energy above Fmax, and use that to bound your expected error when you simulate the model.
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H: Is it possible to connect 5v and Ground to opposite ends of ws2812b LED strip to prevent voltage drop?
I'm currently working on a LED project with WS2812B LED strips with 30LEDs/m. After a couple meters at full brightness the color gets red because of the voltage drops.
Is it possible to connect 5v to the start of the LED strip and Ground to the opposite end of the LED strip to save wires (as in the sketch below)? When testing it that way it worked great, I just want to make sure it's safe and doesn't have any drawbacks.
Whenever I Google this topic people suggest to connect ground and 5v to both ends of the strip which is why I'm unsure.
Thanks in advance!
AI: Connecting 5 V at one end and GND at the other will dramatically reduce the differential between different LEDs, and improve the voltage at the lowest voltage LED ...
...assuming all the loads are drawing maximum current.
The resistance of the supply remains quite high though, and as the LED current drops, the voltage will rise. You will therefore still get a significant change in voltage and hence colour as you change the programmed brightness of the LEDs.
If you do have access to both ends, it's far better to supply 5 V and GND to both ends. This reduces the supply impedance and so the voltage swing with brightness significantly.
Here is a simple simulation of a power supply along a string of 4 loads drawing, in this example, 100 mA each. The supply has a 1Ω resistance wires between each load. The schematic shows the circuit in the 'alternate ends' configuration, drawing maximum current. With a very low programmed brightness, the voltage on all the loads will rise to 5 V.
Load
Single endR1 5 V, R6 GND
Alternate endsR5 5 V, R6 GND
Both endsR1+5 5 V, R6+10 GND
5 V one endGround both endsR1 5 V, R6+10 GND
I1
4.2 V
3.6 V
4.6 V
4.4 V
I2
3.6 V
3.4 V
4.4 V
4.0 V
I3
3.2 V
3.4 V
4.4 V
3.8 V
I4
3.0 V
3.6 V
4.6 V
3.8 V
Re-reading your question, it appears your diagram shows supply at one end, but ground connected to both ends. I've added this to the simulation. It's rather better than one end, and a bit better than alternate ends, but still not as good as using both ends.
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H: How do I get Kp?
How do you get the equation for Kp? I know where R2/R1 comes from, but no idea about + Cd/Ci.
AI: The transfer function \$G_c(s)\$ for this inverting op-amp compensator is:
$$G_c(s)=-\frac{Z_f(s)}{Z_i(s)}$$
The transfer function for a PID compensator is:
$$G_{PID}=\frac{k_D s^2+k_Ps+k_I}{s}$$
Solve for \$G_c(s)\$. Manipulate and compare.
You should be able to take it from here
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H: Why is my op-amp getting hot?
I am using a LM4562 dual op-amp (in SOIC-8) as a level-shift and attenuation stage between an audio amplifier and an ADC. The circuit works fine, with the expected gain and shift, but the op-amp gets hot (68°C). The board is sitting on the bench in free air with no enclosure.
The amplifier isn't oscillating, and is at the same temperature with or without a 1kHz 1Vpp input signal.
The datasheet states a maximum "Total quiescent current", (which I guess means both amps summed together), of 12mA. 12mA * 30V = 360mW. The thermal resistance junction-case is 35°C/W. With Ta=25°C, that would put the case temperature at 25 + (35*0.36) = 38°C.
Are my thermal assumptions invalid?
AI: Junction-to-ambient (JA), not junction-to-case (JC) because the heat is being sinked to ambient, not the case.
Junction-to-case is used when you are connecting a heatsink directly to the case, and when you do that you the need to also account for the heatsink's thermal resistance.
Image source: TI LM4562 datasheet
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H: Voltage drop across TPS259631DDAR when drawing current
I'm building a powerbank and I'm using an E-Fuse IC for the battery protection (specifically, the TPS259631DDAR). As soon as I start drawing any current the voltage drops from 4.1v to 3.4v. The more current I draw, the more the voltage drops. I'm not sure what I'm doing wrong. I've gone through the datasheet multiple times but nothing makes sense at this point. I'll provide my schematic and PCB design for you to have a more detailed look at.
I'll be more than happy to provide anything else that you may require to help me out, here.
Thank you so much!
AI: The efuse on resistance is 89 mOhm. Your traces look pretty small. If they were 10 mil traces on 0.5 oz copper, and a total of 3" long that would add an additional 0.26 ohms, for about 0.35 ohms total. That would give you your 0.7 V drop at a current of 2 A. However, you have to figure out your actual trace resistance and load current to see if it makes sense. There's a trace resistance calculator here.
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H: Can a bistatic receiving radar get an echo on different axis?
I’m a bit confused about bistatic radar. I understand the case when the Tx(transmitter) antenna and Rx(receiver) antenna are separated and and the target (such as a plane) approaches to both of them and they are in alignment of each other.
However, just basic assumption, assume that a ground based transmitter radar antenna (Tx in image) aligned with target’s pitch axis and the airborne receiver radar antenna (on another plane) aligned with target’s roll axis. So, the transmitter antenna hits on the pitch axis of the plane whereas receiving antenna is aligned with roll axis of the plane.
In this case, Can the receiving radar get the echo despite the different axis of the echo?
Thanks for any comment.
AI: understand the case when the Tx(transmitter) antenna and Rx(receiver) antenna are separated
Indeed! Correct.
and the target (such as a plane) approaches to both of them and they are in alignment of each other.
There's no requirement on geometry given by the term "bistatic" other than that the receiver and the emitter of the reflected signal are not in the same place.
Can the receiving radar get the echo despite the different axis of the echo?
Radar targets in general are not corner reflectors, and typically scatter the signal. So, most likely, yes, though the effective radar cross section might be severely reduced.
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H: Calculate current flowing through each of the resistors in the following circuit:
I'm not sure how to go about this, but the answers are below
AI: Here's a hint that simplifies your circuit in order to find the current through the 20 Ω resistor: -
Do you understand the source transformation that I made?
Do you know how to calculate the net value of parallel resistors?
Can you then solve for \$I_{20}\$?
Of course you could solve it with superposition but it's easier this way IMHO.
Once you have \$I_{20}\$ you can then reapply that current to your original circuit
And calculate the voltage at the common node of the three resistors
That then gives you \$I_{40}\$ quite automatically
Once you have \$I_{20}\$ and \$I_{40}\$, and \$I_{10}\$ is easily revealed
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H: Why is my transistor is letting through current?
I'm working my way through the Arduino starter kit project book and am doing the first project involving a transistor (MOSFET). As far as I understand, what I've done is wired up a 9V battery, a resistor and LED, and the source/drain pins of the MOSFET in series. Since there's no voltage on the gate pin, I expect the LED to be dead, but it's shining. I'm not 100% sure which pin on the MOSFET is the gate (the book says it's the one I'm not using), but only this combination of pins produces light from the LED.
Here are some photos of my circuit, and here's what I think is happening diagrammatically:
AI: There's multiple options.
First of all, the transistor drawn is not a FET but a BJT.
Either you have drain and source swapped, so current flows through the intrinsic body diode.
Or, the drain and source are the correct way around, and there is voltage on gate so transistor is on.
Having a gate disconnected does not mean there is no voltage.
It is possible that leakage current or you touching the gate with fingers has caused charge to flow to gate and accumumate voltage.
Or, the FET is damaged by ESD.
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H: I Need help to find what smd component is this?
This component is found on an electronic board of a Siemens Simatic S7-400 device.
The printed nomenclature on the electronic board reads '6C F
AI: Possibly a common BC817-40 or similar https://assets.nexperia.com/documents/data-sheet/BC817_SER.pdf
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H: How to apply KVL to MOSFET circuits?
I'm a little bit confused about applying KVL to circuits containing MOSFETs. I hope someone can provide some clarity. I'll be using the figure below to ask my questions.
First Question
If we want M1 to be ON, we need \$V_{\text{in}, \min} > V_{\text{TH}1}\$.
For M2 to be ON, we need \$V_{b, \min} > V_{\text{GS}2} +
V_{X}\$. This is shown in the figure with red arrows.
In the case of \$V_{b, \min}\$, it was straight-forward to write the KVL.
However in the case of Vin,min, I had to use my knowledge of transistors to
write the condition.
Let's say I want to write KVL for M1. I'll get \$V_{\text{in},
\min} > V_{\text{GS}1} + 0\$. This makes no sense since
\$V_{\text{GS}1}\$ is \$V_{\text{in}}\$. Why was I able to
derive the condition for M2 using KVL, whereas I wasn't able to do the same
for M1?
Second Question
For M2 to be in saturation, we need \$V_{b, \max} <
V_{\text{TH}2} + V_{\text{out}}\$. Again, I used my knowledge
of transistors to get this condition. How can we get this condition from KVL?
If I use the same technique that I used to derive \$V_{b, \min}\$, I'll get
\$V_{b, \max} < V_{\text{GD}2} + V_{\text{out}}\$. But
\$V_{\text{GD}2}\$ is not \$V_{\text{TH}2}\$.
AI: First, KVL does not involve inequalities. It says that the sum of the voltages around a closed pathequals zero.
First Question
If we want M1 to be ON, we need \$V_{in,min}>V_{TH1}\$
This is correct but not KVL. It is a requirement of the FET.
For M2 to be ON, we need \$V_{b,min}>V_{GS2}+V_X\$
This is incorrect:
KVL says \$V_{b,min}=V_{GS2}+V_X\$. This is always true no matter what is going on.
\$V_{GS2}\$ is not the same as \$V_{TH2}\$.
\$V_{TH2}\$ is a particular value of \$V_{GS2}\$. So, from transistor theory, \$V_{GS2}>V_{TH2}\$ for M2 to conduct.
So then: \$V_{b,min}=V_{GS2}+V_X>V_{TH2}+V_X\$ for M2 to conduct.
I want to write KVL for M1. I'll get \$V_{in,min}>V_{GS1}+0\$
This is also incorrect. By KVL, \$V_{in}=V_{GS1}\$ always, whether M1 is on or off. Applying transistor theory, \$V_{in,min}>V_{TH1}\$ for M1 to turn on.
Second Question
For M2 to be in saturation, we need \$V_{b,max}<V_{TH2}+V_{out}\$
This is correct.
Again, I used my knowledge of transistors to get this condition. How can we get this condition from KVL?
You can't get device defining relations usising KVL.
transistor theory
According to the Wikipedia article on MOSFETs. the condition for saturation is
$$V_{GS2}>V_{TH2}\text{ and }V_{DS2}>V_{GS2}-V_{TH2}$$
Combining these shows that:
$$V_{TH2}<V_{GS2}<V_{DS2}+V_{TH2}\tag{Equ 1}$$
revealing that
$$V_{GS2min}=V_{TH2}\text{ and }V_{GS2max}=V_{DS2}+V_{TH2}$$
Applying KVL:
$$V_{DS2}=V_{OUT}-V_{X}$$
and:$$V_{GS2}=V_b-V_{X}$$
Substituting into (Equ 1) and rearranging reveals:$$V_{X}+V_{TH2}<V_{b}<V_{out}+V_{TH2}$$
So: $$V_{b,min}=V_X+V_{TH2}\text{ and }V_{b,max}=V_{out}+V_{TH2}$$
But \$V_{GD2}\$ is not \$V_{TH2}\$.
Of course it is not. Proper application of KVL and substitution reveals that $$V_{X}+V_{TH2}-V_{out}<V_{GD}<V_{TH2}$$
There are two issues with your analysis:
Incorrect application of KVL. KVL is a moment captured in time of the voltages in a closed path. There are no inequalities or maximums or minimums or threshholds.
Confusion among variable names. \$V_{GS}\$ is not \$V_{TH}\$.
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H: Simulating a tuning circuit in LTspice
This is the tuning circuit that I'm trying to simulate in LTspice:
My input signal is the sum of a 500 kHz, 1 MHz, and 1.5 MHz sine wave, all modulated at 5 kHz. The 5 kHz waves carried by each of the frequencies are 90 degress apart from each other, as demonstrated in the equation of my input signal below:
\begin{align}
f_\text{1 MHz}(t) &= \cos(2\pi.10^6t).[1+\cos(2\pi.5000t)] \\
f_\text{500 kHz}(t) &= \cos(2\pi.500{\times}10^3t).\left[1+\cos\left(2\pi.5000t+\frac{\pi}{2}\right)\right] \\
f_{1\cdot5\text{ MHz}}(t) &= \cos(2\pi.1{\cdot}5{\times}10^6t).\left[1+\cos\left(2\pi.5000t-\frac{\pi}{2}\right)\right] \\
f_\text{signal}(t)&=f_\text{1 MHz}(t)+f_\text{500 kHz}(t)+f_{1\cdot5\text{ MHz}}(t)
\end{align}
From what I understand, L1 and C1 should short the 500 kHz and 1.5 MHz signal respectively and only the 1 MHz signal would be present across the output load R2, but when I simulate my circuit using the input signal I described above and have a look at the output signal in both the time and frequency domains, that doesn't seem to be the case:
For reference, here's what the input signal looks like the the time and frequency domains:
Does anyone know why the 500 kHz and 1.5 MHz signals aren't getting filtered?
AI: You have made a low Q or wideband filter. Increase R1 to sharpen it up. Try 10K then 100K.
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H: Which impedance matters?
In USB2.0 specification, there is a requirement of desigining its data traces to be around 90Ohms +/- 15%.
Using this calculator, with these below data:
I got these results:
Now, question is, which value shall I make 90Ohms?
Differential? Common?
Common seems much easier to reach.
I know these calculators are far from exact and also I know impedance can't be really calculated with simple calculators like this.
Still, I wish to know which impedance of this calculator must I design to be 90Ohms in case of desigining a USB2.0 communication.
AI: USB has 90 ohms differential impedance.
Differential means impedance seen by a differential signal where one wire goes positive and the other wire goes negative.
Common means impedance seen by a signal where both wires have the same signal.
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H: Differential impedance calculation - which way to go width vs spacing?
In USB2.0 specification, there is a requirement of desigining its data traces to be around 90Ohms +/- 15%.
Using this calculator, based on my earlier question I'll need to make sure to approach 90Ohms with the "Impedance (differential)".
To reach 90Ohms, there are 2 ways (or there is another, please advise!):
1.) Increasing the trace width crazily:
Or
2.) Dramatically decrease the spacing in between differential pairs:
I know:
This calculator is not exact and precise
Answer can depend on actual goals
I wish to know in general, is it better practice to increase the data trace widths or decrease the spacing, or 3rd option? (putting "something" in between d+ / d- traces?)
AI: Those two are not the only options. They are the only two options if you have already chosen a PCB structure and material with height between copper planes and dielectric constant Er you can't change, and then that's the problem.
The formulas used by calculators are not valid for any arbitrary parameters, usually the ratio between W and S or maybe even their ratio between H is limited to certain range to give out meaningful results. Which means, the calculators may allow you to input any values, but it does not warn you if the values exceed sensible input range and you get a result you can't trust.
If it is hard to achieve sensible track widths with the H you have, then it means the choice of PCB structure is poor.
The real way to make differential pairs with controlled impedance is to have more than 2 layer PCB which allows you to select a suitable distance H between data wires and ground plane to have sensible track width and spacing, so that tolerances in any of them won't change the impedance too much.
So in general case, you likely need to go to 4 layer board, with a suitable layer structure that allows impedance control.
Even if you calculate and draw the track width and spacing properly to your design, you might not get it properly manufactured due to PCB fab house not knowing what limitations there are to select the PCB material and structure of stack up they happen to have in use. That's why you need to define them when ordering PCBs, sometimes you don't care and sometimes you care how they will manufacture it.
If you give the PCB house instructions that you need impedance control on your USB tracks, then they can fine tune the track width and spacing of impedance controlled lines according to their experience how it will end up in the final PCB, given the properties of PCB material and layer structure. They can also give you feedback if they can't manufacture your PCB with the impedances you request and so they can suggest what to change to make it possible.
So what you must decide, do you really want to pay for that if doing a simple one-off hobbyist product for yourself where the USB traces between connector and MCU are few centimeters and running only at 12 MBps, or should you do it properly if you have a commercial product with long PCB traces running at 480 Mbps.
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H: SystemVerilog error: Can't unroll generate for; Unable to unroll loop
I am trying to write a code that converts binary to thermometer code. Thermometer (a.k.a. unary) coding is frequently used in digital systems applications to represent a natural number.
In a thermometer code, an N-bit binary number is represented by a (2 ** N)-bit digital word, which has m zeros followed by (N - m) ones or vice-versa. Basically, if you have a 4-bit binary number say 0110 (decimal is 6), the equivalent thermometer code will be of width 2^4 (=16), and its value will be 6 ones following 10 zeroes (0000000000111111).
module model (
input [7:0] din,
output reg [255:0] dout
);
logic [255:0] tempout;
int count;
always @ (*) begin
count <= din;
tempout<= '0;
end
generate
for (genvar i=0; i <= count; i++) begin
tempout[i] = 1;
end
endgenerate
assign dout = tempout;
endmodule
I am getting the following error for this code:
%Error: Loop unrolling failed.
%Error-UNSUPPORTED: Unsupported: Can't unroll generate for; Unable to unroll loop
For error description see https://verilator.org/warn/UNSUPPORTED?v=4.228
What is wrong with my code?
I have a working code also, but it goes through the loop 2^N number of times, and I want to reduce that.
localparam LP_DATA_SIZE = 8;
generate
for (genvar i = 0; i < 2**LP_DATA_SIZE; i++) begin
assign dout[i] = (i <= din);
end
endgenerate
AI: What is wrong with my code?
You get the Verilator error message because the generate for loop needs a constant for the end condition, not a variable. You can't use count for the end condition because it is a variable (int). Your "working code" correctly uses a constant (localparam) for the end condition.
Another problem with the code is that the following assignment to tempout either needs the assign keyword, or it must be inside an always block inside the generate construct:
tempout[i] = 1;
Also, you would be making assignments to tempout from multiple places (the 1st always block and the generate) which would cause contention.
it goes through the loop 2^N number of times, and I want to reduce
that.
There is no concern for your working code. That is the proper way to describe the hardware you want. The for loop simply creates 256 parallel assignments (one for each bit of dout), which is what you are trying to achieve.
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H: Changing the pre-amplifier gain
I want to change the gain of this pre-ampilifier I assemvled from a kit. If change the value of resistor R1 or R4, should I then change the values of other elements?
I'm thinking about changing R1 from 330R to 220R:
AI: The gain of an inverting op-amp amplifer is given by \$A = -\frac {R_f}{R_i} = \frac {P_1}{R1} = \frac {10k}{330} = 30\$ maximum when the wiper is all the way to the left.
The second stage has a maximum gain of -10. The combined circuit has a maximum gain of -30 × -10 = +300.
Changing R1 to 220 Ω would increase the gain but would increase the loading on the signal source and this may reduce the gain somewhat. Since R4 is driven by the low output impedance of IC1A you wouldn't have that problem there.
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H: Frequency of PCIe differential pairs (RX, TX, CLOCK)
I'm planning to design a board for PCIe (v2).
For all impedance matching considerations, there is rule-of-thumb: if you can decrease the trace lengths below 1/10 of the wavelength, you're probably good to go even without serious impedance matching.
Now looking at those amazing great GT/s values for PCIe versions (5GT/s for v2), I was thinking on how is this really utilized? 5GHz? No CPU is out there which is clocked to this high frequency. And PCIe v4 is even higher (16 GT/s). Is it clocked for 16GHz?
Are these valid states?
PCIe v2's differential pairs (RX, TX) is clocked for 500MHz?
PCIe v2's differential pair (REFCLK) is clocked for 100MHz? (x1 lane)
PCIe v4's differential pairs (RX, TX) is clocked for 123.1MHz?
AI: The trace width being less than tenth of wavelength has nothing to do with the decision if you need impedance matching or not. The rule of thumb applies to length of traces, not width.
And the rule of thumb is not really defined by the wavelength of the signal either, but the rise/fall times of the signal edges, and the allowed impedance mismatches that cause signal reflections.
PCIe V2 is 5 Gbps, so there definitely is a 5 GHz bit clock that clocks bits out at 5 Gbps. It does not require a CPU to run at that speed, the link does. So in theory, there can be signal edges happening at 5 GHz rate even with the 8b10b line encoding. And yes, PCIe V4 is 16 Gbps with 16 GHz bit clock.
Both PCIe V2 and V4 use 100 MHz reference clock, no matter how many lanes are used.
So yes, this is PCIe, you need extremely serious impedance matching, not just for the PCB traces, but for everything, and for the transition areas between everything. This includes even vias, connector pin pads, and pads for any other components there might be on the PCB traces.
And for further understanding, a digital signal is basically a square wave, and you want that square wave to pass through your board with little degradation. The problem is, for any square wave with some bit rate, there is a rule of thumb that you need at least 5 times the bandwidth for the square wave to pass through a system and stay as a square wave. So a 5 Gbps PCIe needs to have a PCB design that can pass 25 GHz without too much degradation in the signal.
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H: Current through combination of parallel and series resistors
I have created a simple example in order to understand what is going on with the current through combination of resistors (parallel and in series) in a electrical circuit. I ask my self to calculate the current through resistor R3.
R1 is in parallel with R2 (R1||R2) and R2 in series with R3.So $$R_{eq} = \frac{5*4}{5+4}+R3 = \frac{20}{9}+8=\frac{92}{9} \approx 10.222$$.
Now the current that flows through R1 is (I use the current division here):
$$ i_{1} = \frac{i}{R_1}\left(\frac{R1*R2}{R1+R2}\right) = i\left(\frac{R2}{R1+R2}\right) =\frac{16}{3}=5.333 $$
for i_2
$$ i_{2} = \frac{i}{R_2}\left(\frac{R1*R2}{R1+R2}\right) = i\left(\frac{R1}{R1+R2}\right) =\frac{60}{9}=6.666 $$
Both currents i_1 and i_2 add up to the current that the source is giving to the circuit.And now because R3 is in series with R2 the current is the same for R3. Am I correct here? Or I am missing something?
Edit
AI: R1 is in parallel with R2 (R1||R2) and R2 in series with R3
No, that is incorrect; all three are in parallel.
Am I correct here? Or I am missing something?
The latter.
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H: Altium: Correct way to handle multiple variants of the same IC
The component AMS1117 comes in three packages. Then each package has a part that gives different fixed output voltage. Here is the table:
When creating the library for this in Altium designer, I shall have one footprint for each of the packages TO-252, SOT-223 and 8L SOIC. Then, I shall have a single schematic symbol for all the different variants for the different voltages. However, since each of these is actually a different part, this means that there will be 7*3=21 parts in schematic library that look identical but represent each of the different 21 parts. And, there will be 3 parts in the PCB library since there are three footprints. Is this correct?
This means that, it is not possible to create a single solitary alone schematic symbol called AMS1117 that when put the into the schematic, we choose the specific part (out of the 21 parts) using something in a drop down box in the properties. Is this the correct way?
AI: Just create the parts you need for the design. If you're undecided on package type, you can create the schematic symbols for the three different packages.
Altium has a feature similar to Orcad's "include" feature which allows you to stuff parameters from an Excel database file in to the schematic layout. Do a search for "Database Link File" to see how to use this.
Example, I have a few schematic symbols for resistors based on footprint style such as R0402 for a 0402 resistor. I will add the value to the schematic during the design phase. Before I commit to layout I will run Tools → Update Parameters From Database which will stuff parameters like manufacturer, manufacturers part number, footprint, description, and company part number. This is matched against "Library_Reference", "Value", "Spare1", & "Spare2" which are part of the schematic symbol. Normally Spare1 & Spare2 are loaded with "." (period) to appease limitations in Altium's search engine, but sometimes I'll have special information in Spare1 and Spare2 to make similar parts unique. For resistors & capacitors, Value is left blank in the library symbol since I fill it in during the design phase. For voltage regulators, Value will contain most of the part number except the output voltage in the library symbol. The output voltage is filled in during the design phase.
The include file technique works well for solo operators and is a bit cumbersome to do in a work environment with multiple seats.
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H: Identify Specific PCB Component
I have identified and tested all the components on this board apart from one. Can someone identify the component please?
I believe it may be faulty as all the other components seem to test ok.
AI: If it's connected between positive and negative supply it could be a gas discharge tube (GDT).
If it's in series with a supply line, it's probably a fuse.
If I would have to take a guess, it's the latter, since that would be an odd place for a GDT. GDTs are intended to protect against heavy surge voltages and are usually accompanied with other protection devices and located more "upstream" near cables that enter a product from the outside world (mains, communication lines, ...).
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H: What sets a proper grid-forming inverter apart from a regular power station?
I have been told here that disconnecting solar panels with micro-inverters (like Enphase, APsystems or NEP) from the grid, and connecting a power station to the group using a suicide cable will probably not trick them into feeding power to the system. In order to do that I would need a so called grid-forming inverter (like Victron MultiPlus, Schneider Conext, or Outback Radian).
A search on "grid-forming" leads to allot of webinars about energy companies concerned with keeping the frequency of the entire grid synchronised, and does not answer the question why a simple power station cannot provide a good enough sine wave for the microinverters to follow.
Is it just that the power station would not be expecting any help from other inverters and malfunction when they start contributing?
Or are there standardized power-line signals or protocols that allow communication instructing inverters to switch on or off at certain times? I know that some city street lights work with such signals, and that the utility company can read out my usage from my meter remotely via the grid-lines, but cannot find any detailed info on it.
So what does an expensive grid-forming inverter have to do extra compared to what a cheap power station already does?
AI: I'll attempt an answer here but hopefully others can fill in some of the gaps in my own knowledge.
Grid following inverters are current sources and depend on the inertia of the grid for a stable voltage reference
The gist of it is that grid-following inverters act as current sources to maximize power output and rely on the inertia of the grid to maintain proper voltage and frequency. When the grid voltage and frequency deviate from accepted limits (per IEEE 1547), they disconnect from the grid.
If you were to try and "trick" the grid-following inverter with a simple ac power supply, it would not have the inertia necessary to provide a stable voltage and frequency, and the inverter would disconnect. Basically, the grid-following inverter would attempt to increase the current output to maximize power transfer, causing a rise in the system voltage which would exceed the capacity of your power supply's regulator. The rising voltage would trip the inverter offline (if it didn't fry the power supply first). The power supply would stabilize, the inverter would reconnect, and the process would start again.
In contrast, grid-forming inverters create their own reference
Grid forming inverters create their own reference voltage and current. They also attempt to maximize power transfer by increasing current output, but when the voltage rises near the limit they are designed to back off the current in order to maintain stable voltage and frequency.
Putting a grid-following inverter and a power supply back-to-back doesn't work because they aren't designed to operate together.
What is grid inertia?
The article "Inertia and the Power Grid:
A Guide Without the Spin" (pdf) from the U.S. National Renewable Energy Lab gives a great explanation:
Inertia in power systems refers to the energy stored in large rotating generators and some industrial motors, which gives them the tendency to remain rotating. This stored energy can be particularly valuable when a large power plant fails, as it can temporarily make up for the power lost from the failed generator. This temporary response—which is typically available for a few seconds—allows the mechanical systems that control most power plants time to detect and respond to the failure.
The Wikipedia article on inertial response also gives a good overview, and goes on to discuss the decline in grid inertia as the penetration of inverter-based resources increases.
Some other references.
From the U.S. National Renewable Energy Lab, "Grid-Forming Inverter Controls"
Most inverter controllers today are grid-following and built on the assumption that system voltage and frequency are regulated by inertial sources
From Du, Wei, Schneider, Kevin P., Tuffner, Francis K., Chen, Zhe, and Lasseter, Robert H.. 2019. "Modeling of Grid-Forming Inverters for Transient Stability Simulations of an all Inverter-based Distribution System"
A. Grid-Following Concept. Currently, most grid-connected, inverter-based DERs use grid-following control, which typically uses a phase-lock-loop (PLL) and a current control loop to achieve fast control of the inverter’s output currents. Grid-following control makes the voltage source inverter behave approximately like a
current source, as shown in Fig. 4 (a). The advantage of this control is that the currents can be quickly regulated. However, because grid-following control does not control the voltage and frequency, it relies on an external voltage source to provide the voltage and frequency references. During load disturbances, grid-following inverters maintain their output power approximately constant.
B. Grid-Forming Concept. In contrast, grid-forming control controls the voltage and frequency of the inverter, making the voltage source inverter behave approximately like a voltage source, as shown in Fig. 4 (b). Because the voltage and frequency remain constant, the grid-forming inverters can work in stand-alone modes and track the loads. To achieve parallel operation of multiple grid-forming inverters, different control strategies have been proposed, including droop control, virtual oscillator control, and virtual synchronous machines, etc.
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H: How are layers kept parallel in multi-layer PCBs?
If I understand correctly the process to assemble multi-layer PCBs, two-sided boards are made, with separators intertwined, and they are then pressed together. The two-sided boards have already been etched, which in theory leaves an uneven surface. When pressed together, it then appears to me that one of two things should happen:
a) The thickness of the separating layers is preserved but they suffer deformation, in which case the PCB would end up looking uneven at the end (probably not what happens?)
b) The parts of the separators above copper are pressed more than those above etched areas, thus yielding even surfaces, but with higher densities of separating material. This in turn probably changes the dielectric constant which might cause some (probably tiny) signal integrity issues (I believe?)
Is one of the above two variants correct?
AI: The separating layers (normally called "pre-pregs") are fiberglass layers, but the crucial difference is that their resin is uncured when they are pressed together in the lamination process. This means that the resin component can deform and even flow fairly readily.
As they are compressed between two core layers, the resin flows to fill the gaps between the copper areas on the facing surfaces of the cores.
This does cause some variation in the dielectric constant because the resin and the glass have different dielectric constants, so that regions with more resin and less glass have lower effective dielectric constant, and vice versa.
If I have understood your question correctly, I believe this means that both of your "variants" are at least partly correct.
How are layers kept parallel in multi-layer PCBs?
I haven't observed the process myself, but I expect a solid surface is used on either side of the board to apply pressure during the lamination, and this ensures that the board remains flat and the cores remain parallel.
In olden times, it was recommended to maintain roughly equal copper coverage across the board, and between symmetrically opposed layers of the board. Meaning, in a 4-layer stack-up if layer 1 has 70% copper coverage (and 30% of the copper etched away) then layer 4 should also have 70% coverage. Furthermore, any given square cm of the board should have roughly 70% coverage (not 100% coverage on the right 2/3 of the board and 0% on the left 1/3). This was meant to prevent warping of the board as it cooled after the lamination and curing of the pre-preg.
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H: LTSpice multiple input source noise analysis
In my schematic, I have two input differential current source and I want to simulate the output noise of the system. However, the LTSpice noise simulation only allows me to put one input source in the simulation command. Is there any way to simulate noise with multiple input source?
AI: You could modify your testbench to the following
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H: Help with (very) odd single phase motor wiring
I think this is my first post here.
I have little knowledge on AC motors, and this machine I am servicing (an old Balltrap/Clay target shooting machine) left me baffled. The below diagram is a simplification of the wiring for the motor that arms the next clay target to be thrown. It has 3 wires that come from the driving board, and to my knowledge, no centrifugal switch (although not quite sure how to check this without disassembling). The driving board is an analog board with relay logic for the start and stop conditions (a button and a limit switch respectively).
For extra context, the motor goes through a gearbox and it's used to reduce speed/increase torque to compress a spring (which then shoots the clay target), so the run time each time is short, no more than 10-20 seconds each time.
Has anyone encountered this type of single phase motor, and if that's the case, can you give me some insight into how it is driven? The drive board is on its last legs and I'm attempting to make a homebrew drive board to keep the machine in service. The literature I find online for single phase motors only shows a secondary starting winding with a starting cap in series for all cases, but I have yet to come across this configuration.
I will take some measurements of the motor running during the week to provide more information.
simulate this circuit – Schematic created using CircuitLab
Thank you very much in advance.
UPDATE:
Modified the schematics to provide measurements taken during running. The driving board has some type of voltage increasing circuit as you can see. Sadly I cannot tell the timing of each voltage value, since I have to probe each pair individually, and I only have a simple multimeter.
Answers below indicate a reversible wiring, yet this motor only runs in one direction.
Video of the machine running: Youtube Link
The three black cables assemblies coming out of the green connector are 3, 1 and 2 from the left, respectively. There are some unused traces that can throw off since the board seems to be used for 3 phase motors as well.
The grey transformer is a stepdown to 15V for another signal unrelated to the motor itself.
AI: If the two windings have the same resistance, it is very likely that they function alternately as main and run (phase shifted) windings for reversing the direction of rotation. So you would connect one line (L1) to the common tap (terminal 3), and connect L2 to either terminal 1 or 2 for forward or reverse. According to the following, this is usually found in small fractional HP motors.
https://www.woodgears.ca/motors/reversing.html
They show this crude diagram:
Terminals A and B correspond to your terminals 1 and 2.
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H: NMOS current is negative for a very short time when turning off
I am designing a circuit that uses the 2n7000 NMOS as a switch, controlled by a digital I/O pin from an Arduino Micro.
I made a simulation in LTspice, and I notice that when the NMOS is turning off the drain-source current becomes negative for a very short time: -
Why does this happen? Is it unwanted? Can this be avoided?
The netlist is here. The model for the 2n7000 is not available in LTspice by default, by the way.
XM1 Vin N001 N002 2N7000
V1 Vin 0 3
R_load N002 0 220
V2 Vgate 0 PULSE(0 5 1m 10n 10n 1 2)
R_pulldown 0 Vgate 10k
R_gate Vgate N001 1k
* fetched 2015/3/15 from http://www.onsemi.com/pub_link/Collateral/2N7000.REV0.LIB
.SUBCKT 2N7000 1 2 3
**************************************
* Model Generated by MODPEX *
*Copyright(c) Symmetry Design Systems*
* All Rights Reserved *
* UNPUBLISHED LICENSED SOFTWARE *
* Contains Proprietary Information *
* Which is The Property of *
* SYMMETRY OR ITS LICENSORS *
*Commercial Use or Resale Restricted *
* by Symmetry License Agreement *
**************************************
* Model generated on Mar 31, 04
* MODEL FORMAT: PSpice
* Symmetry POWER MOS Model (Version 1.0)
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
* Default values used in MM:
* The voltage-dependent capacitances are
* not included. Other default values are:
* RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
.MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=2.236 LAMBDA=0 KP=0.0932174
+CGSO=1.79115e-07 CGDO=1.0724e-11
RS 8 3 1.10523
D1 3 1 MD
.MODEL MD D IS=2.71011e-10 RS=0.0140826 N=1.5 BV=60
+IBV=1e-05 EG=1.16084 XTI=3.00131 TT=0
+CJO=3.41211e-11 VJ=4.67429 M=0.899864 FC=0.1
RDS 3 1 2.4e+11
RD 9 1 0.0001
RG 2 7 2.18034
D2 4 5 MD1
* Default values used in MD1:
* RS=0 EG=1.11 XTI=3.0 TT=0
* BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=7.93181e-11 VJ=0.643298 M=0.9 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.400165 RS=3.00002e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 1.58786e-10
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.400165
.ENDS 2n7000
.tran 0 10 0 1m
.backanno
.end
EDIT
Using the NMOS as a low side switch yields the same results, except now the current is negative when the NMOS turns on:
AI: These transient current spikes are usually not an issue because it exists only for a few ns.
In your circuit where the switch is used in the low side, this is happening due to capacitive coupling from gate to drain of the transistor. When gate goes high sharply, there will be some coupling to the drain which will increase the drain voltage beyond 3V and hence there will be a reverse current through the load for a very short period.
In your simulation, if you make the rise time and fall time slower, this negative current will reduce. This is just for your understanding.
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H: Sharing 5V and GND between peripheral connector(molex connector) and USB 2.0
I have external devices connected to PC which require USB 2.0 connection and a peripheral connector (Molex connector) power connection.
Since those devices are installed several meters(<3m) away from the PC, very long cables are used to connect the PC and the devices.
I want to clean up all the messy cable connections.
My plan is to unify two kinds of connections into single circular connector such as GX16 or GX20.
Now, I have to know how many pins I will need.
At first, I thought I need 8 pins for 4 lines from the peripheral connector and 4 lines from USB 2.0.
However, I notice that some lines are duplicated.
peripheral connector consists of one 12V, one 5V, and two GND.
USB 2.0 consists of one 5V, two data, and one GND.
If I can share all duplicated lines, I will need only 5pins:
one 5V, one 12V, one GND, two USB data
Is this idea safe? If it's bad idea, how many pins do I need here at least?
P.S.
The circular connector idea is a passthrough connector for power and signals in order to convenient cable management.
Each end of the cable is split into USB and molex connectors anyway.
AI: That "IDE connector" wording initially confused me.
Actually that connector is called "Peripheral Connector" in ATX12V specification, but often called "molex connector".
I can't say connecting two grounds is dangerous for sure.
But connecting 5V from USB(Vusb) and +5VDC power rail is terrible idea because:
USB controller can be powered from +5VSB(stand-by 5V, always present), so when system is stopped, +5VDC can be powered from USB port.
Vusb and +5VDC can have different actual voltage, thus when they are connected causing current to flow between them. As a result current can exceed 0.5A threshold and hopefully will trip over-current protection.
What I would recommend to use 5V only from molex connector.
1 - GND
2 - USB_DP
3 - USB_DN
4 - +5VDC
5 - +12VDC
6 - Vusb(optionally), should not be connected to +5VDC
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H: Setting up an EMI test bench: Attenuator
I am in the midst of setting up an EMC test bench for Conducted Emissions testing. This question goes out to the EMC experts regarding the essential equipment needed for the same.
Currently available:
Spectrum Analyzer;
Ground plane;
LISN;
Question:
Several sources suggest connecting the LISN through an attenuator (10dB is what I came across the most) to the spectrum analyzer. How do we choose the attenuation level as there are several available in the market?
Note: The CE test is for a power electronics application board so the possible standards would be considered as for commercial/industrial applications.
Apart from the above-mentioned equipment what other equipment would be essential in order to set up the test bench?
AI: It's always a good idea to have external attenuation in emission testing.
10 dB external attenuation should be a good starting point. You might also consider getting an attenuator with integrated transient protection. Some LISNs also have an internal attenuator that you can turn on and off.
But it's hard too tell how much attenuation is reasonable in your case. With significantly more attenuation than 10 dB the noise floor of the setup could prevent you from getting useful results.
What I always do is to start with the highest attenuation possible and then reduce the attenuation until I get useful results. But I always try to have at least 10 dB of external attenuation with a dedicated attenuator that you can't accidentally turn off.
Apart from that, I guess you are good to go. Just don't forget the little stuff like cables, gender-changers and adapters (e. g. BNC to N-Type).
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H: Exceeding max RPM of wind turbine
I have a wind turbine that reaches its max output power at 1000 RPM, and I want to know if there's any problem if I make it go faster than that (e.g. around 1250 RPM).
I have a TESUP Yuzo. You can find its manual here
I will not be using the blades. Just the shaft.
AI: You probably shouldn't plan to exceed the maximum RPM as stated in the datasheet of 1000RPM. What will happen if you do is pretty much guesswork, but I would guess that you'd see a decreased lifetime. The Overspeed would likely cause excessive heating and cause the turbine to fail sooner, how much sooner depends on how much overspeed, how well-built the device is, and possibly other factors I don't know about.
You could also find that if the device generates more power than it is designed to, this causes extra heating in the wiring/windings and causes a failure in these, or possibly even a fire in a worst case scenario.
Driving the turbine from something other than the blades might have an effect. You might find that without the blades, there's less wear on the shaft from other forces, such as less vibration. Particularly if there's play in the shaft, you might reduce wear from that. Of course, if you're coupling doesn't have good concentricity, you might wear something out sooner. If you drive the turbine from a belt, for example, the belt will apply some lateral force to the shaft from its tension, that if not properly supported could weaken/wear it. I presume there's a mechanical engineering SE that you could go to for further input on the mechanical coupling to your turbine.
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H: Duty Cycle and Filtering in Switching Power Supplies
I have a few confusions to clear up. The first one is about the switching power supply.
Does the power supply simply work on the bases of the duty cycle? Like If I have a pulsating signal of 50% duty cycle and I filter that out using a capacitor so the output should be 2.5V in case of giving a 5V.
Is the reason the fact that the capacitor charges and discharges according to the duty cycle?
And is the same thing used in the switching power supply?
AI: It's not quite that simple, but for a buck converter it is almost that simple.
The key parts you are correct about is that, yes, there are switches, and yes, the PWM duty cycle goes a long way to determining the ratio of the input and output voltages. What you're leaving out is that the switches feed an inductor, which smooth out the current from the switching before feeding the capacitor.
this question has some answers for what happens next.
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H: buck/boost converters currents
I have seen that the buck and the boost converters have capacitors in them and a switching circuit that switches the circuit on/off. I want to ask whether the buck and boost converters increase the current since due to switching the current is very high. This will help me reduce the coil thickness since the current at input could be low and after switching it could be made high. Am I right or wrong??
AI: A buck converter will have greater average output current than average input current. A boost converter will have less average output current than average input current.
The extra output current in the buck converter is drawn from the ground through the switching diode or synchronous transistor.
The peak current through the coil will be greater than the average current because of the switching. Peak current matters for things like saturation of the inductor coil. However, heating of the coil wire does not depend on the peak current, but the average.
The difference between peak current and average current depends upon the design of the converter and the operating conditions. This ripple current may be large or small. When a converter is operated in CCM, the ratio of peak to average current will be smaller than if the converter is operated in DCM.
So whats the reason behind this increase in the current in the buck converter. Like if I am using a voltage regulator I won't be able to use the relation that as the voltage decreases the current increases.
The output current of a "linear" voltage regulator cannot be greater than the input current. This is because a linear regulator simply passes (most of) the input current to the output while dropping the voltage. The voltage voltage drop in such a regulator is due to the resistance of the pass transistor. In a switching buck converter, on the other hand, current passes through the switching transistor into the inductor for part of the cycle, and then current passes from ground through the diode and through the inductor for the rest (or a part of the rest) of the cycle. The inductor does not want to see a change in current, so when the switching transistor turns off, the inductor, figuratively "sucks" current from the ground through the diode, in order to maintain the current in the inductor.
simulate this circuit – Schematic created using CircuitLab
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H: ESP32 program completely halts when serial terminal is disconnected
My platform is ESP32-wroom (Devkit v1 board). ESP-IDF 5.0 on Win10.
I've been using PuTTY to monitor the ESP32's serial log and output (the main serial where all the diagnostic info goes, not the optional ones). It worked just fine.
However, today I've noticed that upon closing PuTTY's terminal window (and clicking "ok" when it asks "Are you sure you want to close the session?") the ESP32 comes to a complete halt. The program running on it stops. Power, however, is still on.
Using ESP-IDF's VSCode extension "monitor" function does not cause this effect, however.
I've tried flashing the official blink example to see if the problem was in my code. But nope, the LED stops blinking the moment I disconnect the PuTTY terminal session. What may be the reason?
P.S: I'm aware that ESP32 may use RTS/DTR pins of the serial for some internal controls, i.e. every time serial connection is established, ESP32 soft-resets. Is that the case here too? I.e. maybe PuTTY sends some signal over serial that ESP32 interprets as "halt"?
Steps to recreate this:
1.Flash official blink example, connect an LED to a chosen pin.Confirm that the led blinks.
2. Connect to ESP32 with PuTTY (115200baud serial)
3. Close the PuTTY terminal window by clicking on the X then "Ok"
4. LED will stop blinking.
AI: Using a terminal program to access a serial port will generally control DTR.
Closing a serial port will bring DTR to inactive level, and opening a serial port will bring DTR to active level.
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H: LC-converter non sinosoidal currents and voltages
I simulated a LC-converter with a verly low static switching frequency of 300 Hz. I expected the current in C1 and L2 in a sinosoidal shape but instead it is almost a square wave. Also there is a oscillation on the voltage Vnode of 75 kHz.
In the FFT of I(C1) it can be seen that the fundamental frequency is at the resonant frequency of C1/L2 of 300 Hz.
Like in LC or LLC converters I expected a sinosoidal current shape. Is my expectation wrong or did I do something wrong with the simulation?
LTspice Netlist:
C1 N002 Vnode 1.41m
D2 N003 Vout+ 1SR154-600
D4 N001 Vout+ 1SR154-600
C2 Vout+ 0 3000µ
R1 Vout+ 0 200
L2 N002 0 0.2m
L3 0 N003 0.1m
L4 N001 0 0.1m
V3 Vsource 0 100
V4 Vg_HS Vnode PWL REPEAT FOREVER (0 5 0.00157 5 0.0016 0 0.00327 0 0.0033 5) ENDREPEAT
V5 Vg_LS 0 PWL REPEAT FOREVER (0 0 0.00163 0 0.00165 5 0.003247 5 0.00325 0 0.0033 0) ENDREPEAT
M1 Vsource Vg_HS Vnode Vnode IRFH5020
M2 Vnode Vg_LS 0 0 IRFH5020
.model D D
.lib C:\Users\hamsn\Documents\LTspiceXVII\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\hamsn\Documents\LTspiceXVII\lib\cmp\standard.mos
.tran 75m startup uic
K1 L2 L3 L4 1
.backanno
.end
AI: 2 bad errors.
Your transformer has far too low primary coil inductance. The primary current grows with an incredible rate to the max which the mosfet allows with the given Vgs drive. That happens even with nothing connected to the secondary and that's what you see.
You charge (or actually try to charge) the output capacitor C2 with no series inductor. It's a short circuit which would in practice easily blow the fets or the rectifier or both at the startup (assuming the transformer was functional). Simulated parts generally do not burn, so you do not smell anything when you run the simulation.
My suggestion: Learn the design principles of forward DC to DC converters and restart from the beginning. Now you are drifting totally offroad.
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H: Current measurement with LT6015, simulation doesn't work
I'm trying to simulate high side shunt resistor current measurement using LT6015 op amp, but the simulation doesn't work I'm always having the same output even if I change the current. Can somebody tell me why?
lt6015 datasheet
AI: You have two problems. As Spehro notes, the 3.3V power supply is connected backwards. You will also clip the output with a 0.2V input. Either change the gain, the current sense resistor, or the 3.3V power supply to 5V.
If you simulate your circuit with a sine wave input, you can see the part saturating.
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H: Mistake in calculation of RMS current flyback primary switch node
I'm trying to calculate the RMS current of a flyback converters primary switch node. The Waveform is shown below:
I'm okay with assuming it is a triangle wave with a duty cycle of 50%. The peak value is 1.25A and the Period time is 4u seconds.
I can calculate it using the following formula I found on the internet:
And I will find a RMS current of 0.51A what is right.
But my problem is when I try to calculate it with another method i believe is right I get a different answer. I hope someone can point out me where I'm wrong. See my calculation below:
$$
I_{RMS} = \sqrt{\frac{1}{T}\cdot\int_{0}^{T}I^2(t)dt}
$$
I then simplify the integral to an easy area calculation
$$\int_{0}^{T}I^2(t)dt = (0.5 \cdot 0.5T \cdot I_{PK})^2$$
I work this all out to the following:
$$I_{RMS} = \sqrt{\frac{1}{T}(0.5 \cdot 0.5T \cdot I_{PK})^2}$$
When i fill everything in:
$$I_{RMS} = \sqrt{\frac{1}{4\mu}(0.5 \cdot 0.5 \cdot 2\mu \cdot 1.25)^2} $$
$$I_{RMS} = 3.125\cdot10^{-4} A $$
I end up wrong. I think my problem is with the simplification. But it doesn't make sense to me why it should be wrong.
AI: Apply dimensional analysis to see your error. In the third step, you have:
$$ (A) \equiv \sqrt{(s^{-1}) \left[ (A) (s) \right]^2} = \sqrt{ A^2 s} = A \sqrt{ s} $$
which fails the equivalence on the left.
The curve you need to integrate is a quadratic, from 0 to DT, and the remainder (from DT to T) is zero. The antiderivative of the square is 1/3 of the cube, which lies is under the radical, hence where the \$\sqrt{3}\$ fraction comes from.
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H: How does the thermistor activate/not activate a circuit?
I have this schematic which is temperature-dependent and would only make a sound once the heat detected is above the threshold of the NTC thermistor.
Can I get some help with circuit analysis?
How does the thermistor in this schematic stop/not make the buzzer buzz when the heat is below its threshold? Does the Zener diode have a play in this or is it just simply about the op-amp in terms of turning on?
My take is that it when the resistance is high (the threshold heat is not achieved) there will be less current passing through so it won't be enough to conduct the diode. I am unsure with these so please correct me.
AI: The IC U2 is an op-amp used to compare two voltages.
One voltage depends on thermistor resistance (i.e. temperature) and the other voltage depends on the potentiometer resistance (i.e. setpoint).
The comparator will output high or low depending on which input voltage is higher, and this in turn controls the NE555 to stop or start running the tone to speaker.
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H: What type of connector is this one?
What is the name of this connector?
It´s about 4mm x 8.5mm x 6.5mm
This is the counterpart:
AI: It is a JST PH type connector (not necessarily JST brand) with 4 pins.
Here is the JST datasheet, which gives part numbers for various members of the PH family.
Here is an image of PH family parts that I obtained from here
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H: What am I supposed to do with the Backplanes for the PCA85276?
I am trying to use eight 14-segment display with this driver but I can't figure out what the backplanes would be for and what I should connect them to. It gives me this table with the possible configuration
It then says that "The possible display configurations of the PCA85276 depend on the number of active backplane outputs required".
Would that mean that I would leave the pins floating/unconnected?
Here are the links to the data sheets:
https://media.digikey.com/pdf/Data%20Sheets/Varitronix%20PDFs/VIM-878.pdf
https://www.nxp.com/docs/en/data-sheet/PCA85276.pdf
AI: Your display has a total of 128 segments (14 plus 2 per digit, 8 digits) so you'll need to have all four backplane outputs active as per the table:
The diagram just below that table in the datasheet shows you how to connect the display to the driver:
Your four backplane outputs (BP0 to BP3) should be connected to the four common pins of the display (COM0 to COM3) and 32 of the 40 segment outputs should be connected to the 32 remaining segment pins.
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H: PIC16F54 I/P PDIP-18 8-Bit microcontroller: self-made PIC programmer with USB serial communication
The PIC programmer circuit below is from the PIC16F54 datasheet.
The programming stage can be reached when the pins RB6 and RB7 are set low and the VPP pin gets more voltage than the power supply in this controller. The idea is about making out a PIC programmer with these given conditions. Normally, a USB cable should be enough to code this PIC. USB cable has four pins. Pinout of USB plug is the following one; pin-1 power, pin-2 data (-), pin-3 data (+) and pin-4 GND.
When I would try to get a connection between microcontroller and computer then I would solder pin-1 (+5V) with VDD and pin-4 with VSS (0V). VPP will be supported by an external power supply with 13.5V. The pins of clock signal and data signal of controller can be with either pin-2 (data -) or pin-3 (data +) on USB soldered, I think so.
My question is about this. Which pin of USB cable does transfer the clock signal? I have already a programming IDE for this code transfer. All I need is the right pinout.
AI: USB uses a differential transmission format on the two data lines. It cannot be used to send a clock on one line and data on the other.
You may be able to use a USB to serial/uart interface to do what you want.
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H: Value of series resistor for crystal oscillation
In this device, this is the Hardware Design Checklist.
On page 8 of this checklist, section 4.2., it recommends adding a series resistor at the clock out pin, but they have not specified any values of the series resistor. On page 192 of the datasheet, reference crystal characteristics, the ESR recommended is 50 ohms. I also understand that this does not require placing a 1Mohm resistor across the crystal terminals.
What resistor value should I place at the clock out pin? Is 510 ohms Ok, or any specific range?
Any guidance on how to arrive at a value of the series resistor?
AI: There are two distinct situations.
The resistor is recommended if you are using an external clock oscillator. It should be near the oscillator module clock output pin rather than the chip and you could try a value such as 22Ω or 50Ω and fiddle with it a bit until the waveform looks good on your oscilloscope. After that, the value should be good enough for multiple units of production unless the layout or something else major changes. In this case, you leave X0 open (and you'll need one capacitor across the oscillator supply).
No resistor is recommended if you are using the internal clock oscillator with an external crystal. The 50Ω maximum ESR is a recommended characteristic of that crystal, it's not a discrete resistor. Along with the other values in the table. So if you can find a crystal with a maximum ESR of 30Ω you should be fine since 30Ω \$\le\$ 50Ω. The maximum ESR value should be shown in the crystal datasheet- if it isn't, don't buy it. If you want to use a crystal that does not meet those specifications, it gets a bit more complex, so it's best to stick to what is recommended. You'll need to calculate the two load capacitor values from the crystal load capacitance and stray/input capacitances (it is not taken directly from any datasheet).
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H: What's the difference between Texas Instruments V62/06623-01XE and MAX3232MDBREP?
I'm using a MAX3232 but given different production codes with the same package (V62/06623-01XE, MAX3232MDBREP), is there any difference between them?
Can the two be used as substitutes for each other?
Datasheet check out page 8
www.ti.com/product/MAX3232-EP
AI: These two parts are the same.
As it seems, you can't order V62/06623-01XE any longer. TI probably updated the part identifier at some point.
Source: https://www.ti.com/product/MAX3232-EP/part-details/MAX3232MDBREP
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H: Zener diode wrong gate voltage regulation for battery reverse protection
I have the following circuit meant for reverse polarity battery protection.
The battery is a 2s li-ion (8.4 V to 7.0 V), but it could also be a 12 V max PSU.
I'm not sure what's wrong on the PMOS gate, why is it only getting 3.1 V from the Zener?
My expectation was to have a gate voltage increasing together with the battery voltage, until it reaches the Zener voltage. Then the Zener would regulate it and keep it at about 7.4 V.
The Zener is the MM5Z7V5T1G. The MOSFET is the YJQ1216A.
Link for the circuit simulation: Falstad simulation.
AI: Your zener is in the wrong place. When reverse-biased, the zener will initially block like a normal diode, but eventually break down at it's zener voltage and begin conducting.
For this zener (in your simulation), that's around 5V. If 5V were to drop across the zener that would leave 3V across the resistor,
3V / 10k Ohm = 50uA
This small current isn't actually enough to open the zener, which needs around 1mA to operate.
So what you're seeing is the zener isn't operating properly, and is in the region before it breaks down, and hence passes 307.2uA, and drops 4.9V
You need to swap the resistor and zener around so that the regulation from the zener is between the gate and ground, rather than between the gate and Vin like current. You should also decrease the resistor to allow enough current for the zener to operate.
I've used values for the diode in your simulation, so I could adjust the simulation. The diode you linked has 7.5V breakdown voltage, but the math is much the same
You could also do away with the zener and just drop a resistor divider in. The Gate threshold voltage is -1V, so even a pair of 10k's to make a divider would be enough. You could also increase the value in order to waste less power.
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H: Is a 1 Hz signal the same as 1 PPS one?
Is a 1 Hz signal output from a ripple counter or divider the same as a formal "1 PPS" signal? If no, what is the difference in the time domain?
AI: Both signals will have a rising edge, and a falling edge, every second.
However, their name tends to imply different things about the duty cycle.
1 PPS implies 'pulses', with likely a low duty cycle.
The GPS '1 PPS' signal is a 20 us, with the leading edge coincident with the whole second mark. The GNSS '1 PPS' is 36 us, similarly aligned. There are quite a few other applications that specify 1 PPS with other parameters.
A '1 Hz', depending on how it has been made, could be 50% duty cycle, if the last divider in the chain is a /2. If it's the carry-out from a /10 stage, it may have a 10% duty cycle. If it's the 'D' output (23 weight) from a /10, then it would be 20%. There's no limit (beyond the period of the divider input clock) to the duty cycle that ingenuity could create.
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H: Why do I still hear audio plugging only signal pins of jacks
I am debugging some audio project I am currently having fun with. I came down to the following (minimal ?) example I don't understand. The setup is as follows.
I have an audio stereo jack that comes out of my phone. It splits into 2 mono jacks.
A male-male mono jack is connected to a speaker. If I make contact with only the signal pin of the jack plugged in the phone and the signal pin of the jack that goes into the speaker I can hear the sound.
Phone is working on battery and speakers on AC. Speakers also have balanced inputs. The other mono jack coming from my phone goes nowhere.
AI: If your source is battery powered and your receiver is AC-powered, I can see a few explanations:
You’re inadvertently touching for example both left and right, producing the difference between left and right, played in mono. Fun experiment when intended to hear what’s going on in the mix, for example dry lead vocals panned straight to middle but stereo reverb on the same. If you’re playing a stereo mix, this should be almost as loud as when fully plugged in.
You’re actually only touching one single terminal, “breaking” KVL as there is no closed path for current to flow. The closed loop is formed by an air gap and therefore a capacitor between device chassis or plug, via either air to the cable and/or via you to cable and/or ground. This will have a distinct LF roll-off sound and lower amplitude.
Rough schematic:
simulate this circuit – Schematic created using CircuitLab
If you’re touching both chassis, you will form a resistive return path between the devices. Depending on how hydrated you are, this will sound as an attenuation of sound but flat frequency characteristic.
Also, the higher your receiver input impedance, the easier it is to hear the capacitive coupling and lower frequency for the -3 dB crossover point.
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H: LED strip 12V powered from powerbank
I have LED strip 12V.
https://hadex.cz/k043a-led-pasek-12mm-hlinikovy-bily-teply-72x-led5730m-ip20-delka-1m/.
I tried power from this powerbank (USB cabel cut, black - and red + wire), but nothing.
https://www.planeo.cz/katalog/1277989-yenkee-ypb-1030-power-bank.html
I wanna buy/try this powerbank?
https://www.datart.cz/powerbanka-emos-alphaq-10-10000-mah-cerna-1613052400.html#moreDescription
Question 1
Am I understanding will, that problem is that Yankee powerbank have output only 5V?
Question 2
If I will try Emos powerbank, will it work with LED? Have it 12V output?
AI: 1.The issue is that the Yankee power bank you mentioned has an output of 5V, which is not sufficient to power your LED strip that requires 12V.
2.The Emos Alphaq 10 with a capacity of 10,000mAh, does not have a specified 12V output. It typically provides the standard USB output of 5V. Therefore, it may not be suitable for powering your 12V LED strip. You would need a power bank with a 12V output or use a different power source capable of supplying the required 12V for your LED strip.
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H: Freely rotating part that conducts electricity to fixed part - does this exist?
Planning a design that has a 12V voltage source connected to a physical part that rotates.
I need to conduct electricity from the rotating part to a fixed part which is connected (electrically isolated) to free-standing structure like a pole or a tower.
I'm imagining the matching 'rotating' and 'fixed' conductive parts to be anywhere from a few centimetres across to maybe 20-30cm and spinning at maybe 500rpm max.
Does a solution for this challenge - or some sort of conductive, [edit: reasonably] frictionless, easily machinable material - already exist in general population?
Thanks.
AI: The term you are searching for is Slip Ring Connectors.
A slip ring is an essential component and parts that can solve the 360
degrees of continuous rotating, and get electricity to a continuously
rotating part of the assembly, rotating without limits.
Read more
See on Amazon (available for way less on other websites though)
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H: FSM derivation for a digital Manchester encoder
I am looking at an FSM example in a digital design literature book where the idea is to create a simple FSM using a Moore machine for a Manchester encoder.
The FSM takes two inputs. d is the data signal, and v is the data valid signal. d is the signal to be encoded. The output of the FSM is y, the encoded result. The book doesn't specify any relationship between the clock generating the input signal d and the one clk driving the FSM. But, it mentions that the max speed that can be achieved is half the speed of the clock driving d, which is expected. It takes a transition from one level to another (d0 -> d1) to generate one output data (y0).
The state diagram suggested by the book is the following.
Notations: d' <=> (d = '0') and d <=> (d = '1'). Same for v.
The book doesn't explain how the states were derived and what they represent. This is an extract of the text.
I don't understand why the output y is asserted in the s0b state. If d is initially low, the FSM goes to s0a state. At that point, the next state is set to s0b regardless of the input, and the output y is asserted (y <= '1'). But, is this correct? The output should be 0 since we start from d=0 (a transition from low to high). (Update The reason of my confusion here, is that I was trying to solve a different problem. I was making a state diagram for a Decoder.)
I simulated the code implementing this state diagram and I see a strange behaviour in the output y.
library ieee;
use ieee.std_logic_1164.all;
entity manchester_encoder is
port (
clk, reset : in std_logic;
v, d : in std_logic;
y : out std_logic
);
end manchester_encoder;
architecture moore_arch of manchester_encoder is
type state_type is (idle, s0a, s0b, s1a, s1b);
signal state_reg, state_next : state_type;
begin
-- state register
process (clk, reset)
begin
if (reset = '0') then
state_reg <= idle;
elsif (clk'event and clk = '1') then
state_reg <= state_next;
end if;
end process;
-- next-state logic
process (state_reg, v, d)
begin
case state_reg is
when idle =>
if v = '0' then
state_next <= idle;
else
if d = '0' then
state_next <= s0a;
else
state_next <= s1a;
end if;
end if;
when s0a =>
state_next <= s0b;
when s1a =>
state_next <= s1b;
when s0b =>
if v = '0' then
state_next <= idle;
else
if d = '0' then
state_next <= s0a;
else
state_next <= s1a;
end if;
end if;
when s1b =>
if v = '0' then
state_next <= idle;
else
if d = '0' then
state_next <= s0a;
else
state_next <= s1a;
end if;
end if;
end case;
end process;
-- Moore output logic
y <= '1' when state_reg = s1a or state_reg = s0b else
'0';
end moore_arch;
As expected, the waveforms show that y is asserted erroneously following a transition from 0 to 1 in the input signal d. I am starting to believe that this state diagram is incorrect. Can someone help me figure this out?
Another concern is how to define an FSM clock that allows to sample the transitions of the d correctly as they come.
Update
I re-simulated the DUT using the suggested tips. The waveforms behaves correctly.
AI: You must stimulate the design in a way, that each bit at d, that shall be transfered, is active for 2 clock cycles. So if you want to transfer a 1 you need d=1 for 2 clock cylces, if you want to transfer a 0 you need d=0 for 2 clock cycles.
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H: PCIe "RefClk" impedance requirements?
I'm designing a very heavy impedance-requiremented PCB, with PCIe v2.
I know TX and RX diffpairs have strict differential impedance requirements of 100Ohms.
But I couldn't really find impedance requirements for RefClk diffpairs. Are there any?
AI: PCIe electrical specs between data and clock lanes are slightly different. All lanes still have the same differential impedance requirement.
So you can't skimp on routing clock lane without proper differential impedance.
If you are not aware, even if specs say 100 ohm differential terminations, routing the tracks with 100 ohms may not be the best option, and many design guides say 85 ohms as the best practice - but it depends very much on if you are making the motherboard or the card or some adapter that sits between motherboard and card.
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H: Isolation on RS232 bus
Is there any "simple" way to get (1500V) galvanic isolation on RS232 (just RX and TX)? By isolating, I mean than I have 2 different grounds on each side of the insulation barrier.
On side A, I have 1.8V, 3.3V, 4.5V, and 5V rails, and can accept voltage ranges between (-4, +4) and (-15, +15). On side B, I only have 5V rail, and it should be something rather standard (the equipment on side B is for future use).
For logic level signals, it's quite easy to use a digital isolator (or even an opto-coupler).
However, I'm quite stuck with RS232, which goes bellow 0V.
The solution I found so far is convert RS232 to TTL, then pass the isolation, and convert back to RS232 : nothing difficult, but that makes 3 ICs and lots of PCB space. I even found some ICs doing RS232 to TTL and isolation in one step.
But for now, I haven't found a nice way to directly isolate RS232 signals.
Any idea?
AI: I haven't seen any solution simpler than RS232 chips to TTL, I think that is the way you'll have to go with an isolation design.
|
H: How does the KLJ-5030 buzzer work?
I need a small package buzzer to replace the regular piezo buzzer which is too big for my design, so I tried the KLJ-5030.
I tested by applying 3V to positive pin and GND to negative pin and heard a small crackling but not really sound (beep).
The datasheet does not explain well how this works. I am wondering, does this require other components in order to work?
Update:
I tested with Arduino at 4000 Hz and got 46db on my decibel meter placed at 30cm: not good enough for my need.
AI: You need an external 4kHz square wave source and driver.
You may be able to generate the 4kHz with an Arduino, but it's better not to try to drive this directly with the Arduino pin- DC resistance is only 12Ω so you'd be basically short-circuiting the GPIO and the sound won't be that large.
If you have a 5V Arduino you can drive it like this:
simulate this circuit – Schematic created using CircuitLab
For 3.3V:
simulate this circuit
The diode is optional according to the transducer datasheet recommendations, but I'd put it in just for luck unless you 'scope the voltage at the collector and find it will within limits. If you leave it out, a 2N4401 would be safer.
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H: Is it feasible to put solder mask cured on the top of tinned pads?
I made a batch of PCBs with a QFN package IC. I accidentally connected the pad to GND even though it should be either left floating or connected to some signals else. I am glad that I have requested a few samples before I made the PCB fab house assemble all of them.
It would be very expensive to re-order the boards, and there are vias-in-pad connected to internal layers. So I think that disconnected the IC's exposed pad from the PCB's pad with additional solder mask should be a viable solution.
As long as I know that the pads are tinned with HASL. Would you suggest whether my next few actions are feasible or not:
I request the fab house to mask the pads and assemble the boards.
For my received sample boards:
I desolder all the affected QFN chips
remove all the solder with the copper braid
clean with isotropic alcohol.
Then either apply solder mask paint cured by UV light or stick Kapton tapes to cover the pad.
Finally re-solder the parts with heat gun.
AI: The fab house is unlikely to be able to mask the exposed pad. You could ask but prepare to be disappointed.
If this is a small run, have the boards assembled, but leave the QFN unpopulated (change the BoM to mark it as DNI). If the fab is purchasing the parts for you, have them ship the unassembled QFNs to you with the board. Make sure also to send an updated Gerber file for the solder paste stencil to remove the openings for the QFN so that the pads don't end up with reflowed solder on them. This will avoid the unnecessary desoldering and cleanup.
For manually assembling the QFN, you'll want to cover the exposed pad in a heat resistant lacquer that is as thin as possible so as to avoid raising the QFN pads off the copper too far. Ideally something as thin as the existing solder mask. You could use Kapton tape (polyimide) but that may be too thick (though would be a better choice than Teflon tape), there are places that will sell 25 micron thick stuff (including adhesive) which might be ok.
Once covered, you could then use some low temperature solder paste (optionally applied with a tiny stencil just the size of the QFN if there is enough space around it) and either a hot plate or air or IR heater or reflow oven. The lower temperature paste avoids risking desoldering the existing joints.
For larger runs, it is probably more economical to simply respin the boards. Doing anything nonstandard like asking the assembly house to start covering pads is probably going to cost more than remaking the boards.
|
H: Have I made this XNOR gate right?
enter image description here
I tried to make a circuit implementing the XNOR logic by using the identity XNOR (A,B) = OR ( NOR(A,B) , AND(A,B) ). The circuit works in breadboard (1st pic), it produces the 1001 truth table associated with XNOR gate. Is the drawing of the circuit alright?
Transistors 1, 2 and 3 make the AND gate (three transistors on the top middle in the breadboard), transistors 4 and 5 make the NOR gate (two transistors on the top right in the breadboard) and transistors 6, 7 and 8 make the OR gate (three transistors on the bottom left in the breadboard).
I needed 8 transistors and 7 resistors to make this circuit. Are there better ways of making XNOR gate using BJTs that requires less components?
AI: If your circuit works then it works. However, it's a bad idea to share the same resistor with the base of multiple transistors, because they could use different voltages to turn on (due to manufacturing variations, or different voltages at the collector/emitter) and when the bases are directly connected it forces them to be the same. Each one should have its own resistor.
Also, transistors 1 and 8 are forming two NOT gates in sequence, and could be eliminated.
I suppose if you want to calculate OR ( NOR(A,B) , AND(A,B) ) you won't be able to do it with less transistors.
You can cheat a little. If you remove the last transistor 6, you can have an XOR gate, and reverse when the LED is on, by wiring it from 5V to the output, instead of from the output to ground.
But watch this magic: (click to simulate)
This is an XNOR with only 4 transistors - and 2 of them are NOT gates that are only needed because of the type of input you are using. If you use different inputs, 2 is enough:
I'm not sure where I found this circuit. You can play with it in the simulator. If one of the inputs is low and one is high, one of the transistors discharges the output to 0V; if they are both the same voltage then neither one turns on.
|
H: A fully clamped sinusoidal wave has its RMS multiplied by the square root of 3. Is my textbook mistaken?
A fully clamped sinusoidal wave has its RMS multiplied by the square root of 3: Vo = 1.73Vi
My textbook says that clamper circuits don't affect the Vpp and Vrms of an AC signal.
Obviously, Vpp didn't change, but Vrms must certainly change according to this calculation. Is my textbook mistaken? Does this magnification have any practical uses?
AI: If you have a sine wave with a peak-to-peak value of 2P volts, its RMS value is the peak (which is P) divided by √2 or P/√2 and its DC value is 0. When the sine wave is clamped to 0 volts, its peak-to-peak value is still 2P but it is now has a DC value of P volts. Therefore, its RMS value is now given by √(DC^2 + RMS^2) or √(P^2 + (P/√2)^2) which reduces to √(P^2 + P^2/2) = √(3(P^2)/2) = √3(P/√2) = √3RMS value. So your textbook is correct. The extra value is supplied by the clamping circuit.
|
H: VHDL : how to write data in FIFO (first in first out) and read data with diffrent clocks for the writing and reading?
So I have this problem . I need data to be saved in a FIFO . but the problem is that the I need different clock for the writing and the reading . for exmaple I need that MY FIFO will write the data in frequency 50 M Hz ,and after the FIFO is full to read this data but with frequency of 960 Hz . I know that in point of hardware it is not possible because in FIFO you have the same clock for writing and reading . But is there any other way to save data in some sort of memory and then read this data from the memory in different frequency ?
I drew simple pic of my meaning
AI: It seems like you're thinking of the FIFO as a shift register. It isn't; it's more efficiently implemented as a circular buffer. Keep your data in a memory location, and use two independent pointers for read and write. Those pointers can be updated in different processes.
As others have said, use vendor IP where applicable, especially for synthesis. If you're looking for a behavioural model, or for some other reason can't use the vendor-supplied model, the circular buffer is the way to go.
|
H: Is there a "repeater" logic gate?
What I want to create is a simple logic gate that doesn't actually perform any logic, but instead simply repeats the given signal. I want to do this so that I can have a one-way wire.
Some ideas that I've thought of, but I'm not sure if they're efficient, or which one is more efficient:
A NOT gate plugged into a NOT gate.
An AND gate with both of the inputs as the same wire
An OR gate with both of the inputs as the same wire.
AI: What you're looking for is commonly known as a "buffer". Any of your proposed constructions would work to form one; I believe the two-cascaded-NOT-gates is common in CMOS logic.
|
H: Verilog: Posedge sensitivity vs. If statement in Always block
I have recently completed a design that had run into timing issues (negative slack). The modules that were found to be troublesome, from the timing reports generated in Vivado 2017.4, are these modules that are used to calculate some synchronous outputs. A clock, reset, and enable (en) signal are provided as inputs. The modules that had these issues were previously implemented as shown below:
always @ (clk, rst) begin
if (rst) begin
...
...
end
else if (clk & en) begin
...
...
end
end
A coworker suggested that the "code is creating latches for the pipeline segments, instead of clocked flip flops". Following his suggestions I changed the modules to what is shown below.
always @ (posedge clk, posedge rst) begin
if (rst) begin
...
...
end
else if (en) begin
...
...
end
end
This seems to have resolved the negative slack coming from these modules, but I am curious to know why this is the case.
AI: A coworker suggested that the "code is creating latches for the pipeline segments, instead of clocked flip flops".
The two code segments are totally different.
The first is combinatorial logic, the second is a register.
The behavior of the two is also total different.
In the first what you call a 'clk' is not giving you the behavior of a real clock at all, it is just a signal*.
From the first code you can get gates or latches, but not registers.
In the code section you should use blocking = assignments.
The second format should produce registers with an asynchronous positive reset.
In the code section you should use non-blocking <= assignments.
*(That was so unusual that it caused my first, wrong, answer)
I'm just having a hard time seeing why this would be the root of a timing issue.
As you are saying you get negative slack, I assume some other parts of the circuit does have registers in them.
The logic from the first parts of the code has NO registers. It is just one huge combinatorial 'blob'.
my original thinking was that the if-statements would help implement the sequential behavior
No, an if statement produces only multiplexers which are combinatorial again.
|
H: AC coupled sinewave
How can I see in this picture that the signals are AC coupled?
Does not AC coupled means that the DC offset is 0 and the sine is centered to the origin?
Both signals have an offset from what I can see here.
AI: How can I see in this picture that the signals are AC coupled?
You can't. We can see that both signals have zero mean, but we can't tell why that might be. AC coupling could explain it.
Does not AC coupled means that the DC offset is 0 and the sine is centered to the origin?
Yes, the peaks of a sine wave would be centered on the origin.
Both signals have an offset from what I can see here.
These are obviously not sine waves. But they do appear to be exact complements of each other, and they cross each other exactly at zero on the vertical axis. Therefore, there is no common-mode signal. This means either of two things:
Neither signal has a DC offset. (the simplest case)
Both signals have a DC offset, and the offsets exactly cancel each other. (unlikely)
|
H: Counting the number of button presses in ATMEGA16A
I am looking forward to counting the number of presses of a button in a 2 seconds interval in ATMEGA16A. I have prepared some code below. Is there another way around? My first solution was to perform polling inside the while() loop, but I think that would be imprecise.
Problem description: Two buttons, START and PV are given and two internal states: IDLE and COUNTING. Once START is pressed the state changes to COUNTING and the timer starts to count up. During this time, the number of PV presses is recorded by incrementing a variable 'na'. One the timer reaches 2 seconds, no further presses are recorded. The output is represented by 12-LEDs, 3 of them for the tens, named LZ1-LZ3 and 9 LEDs for the units, named LU1-LU9, for a maximum count of 39.
My second solution used interrupts for the 2 buttons and the timer overflow. Initially, the clock for the timer was set to 0, so the timer won't start. I would only enable an interrupt for the START(INT0) button. It would enable the interrupt for the PV (INT1). When a low signal is detected on START (button pressed), it would change the state to COUNTING and it would enable interrupts for PV. When PV is pressed, na is incremented. When the timer overflows (i.e. it reaches 2 seconds), the interrupts for PV would be disabled, the timer would be stopped and reset and the program would go into state IDLE to output the last 'na'.
I used timer 1 in CTC mode with N = 46875 and a clock of 256.
Now, for some code:
#include <avr/io.h>
#include <avr/interrupt.h>
#define N 46875 //TOP value for the timer 1
#define IDLE 0 //in this state we print the last number of presses
#define COUNTING 1 //we do nothing here, only used as intermediary state
#define LZ1 PD4
#define LZ2 PD5
#define LZ3 PD6
#define LU9 PD7
volatile unsigned char na = 0; //number of presses shared between main and ISRs
volatile unsigned char state = IDLE; //initial state shared between main and ISRs
/************************************************************************/
/*
PA0-PA9: LEDs which display units 0-8
PD0-1: unused
PD1-2: START button(INT0) and PV button(INT1)
PD4-6: tenths LEDs
PD7: LED for unit 9
ex: 35 presses of PV
LU - LED for units
LZ - LED for tenths
PD4 PD5 PD6 PA 0 1 2 3 4 5 6 7 PD7
LZ1 LZ2 LZ3 (PD4-6) LU 1 2 3 4 5 6 7 8 9
1 1 1 0 0 0 0 1 1 1 1 1
*/
/************************************************************************/
int main(void)
{
//setup ports
DDRA = 0xff; //whole PORTA as output
DDRD = 0b111100--; //buttons PS and PV on PD2 and PD3
//setup timer 1
TCCR1B = 0b---10000; //CTC mode 4 and CLOCk = '0' -> timer 1 not counting yet
TCCR1A = 0b------00; //CTC mode 4
OCR1A = N - 1; //setup TOP for CTC mode
//setup interrupts
TIMSK |= (1<<OCIE1A); //enable interrupt for ISR
GIFR |= (1<<INT1); //enable interrupts from INT1 (PV)
MCUCR = 0b----0000; //INT 0 and INT1 are active on low
sei(); //enable global interrupts
//declarations
unsigned char lut_units[] = {
0b00000000, // 0
0b00000001, // 1
0b00000011, // 2
0b00000111, // 3
0b00001111, // 4
0b00011111, // 5
0b00111111, // 6
0b01111111, // 7
0b1111111 // 8
};//lookup table used to store the LED configurations for units 0-9
unsigned char units = 0, tens = 0; //used as temporary variables
while (1)
{
switch(state):{
//used to print out the number of presses
case IDLE:{
units = na % 10; //extract the units from the number of presses ex. 23 -> 3
tens = na / 10; //extract the tenths from the number of presses ex. 23 -> 2
//write the units to the LEDS
PORTA = lut_units[units]; //write the appropriate lookup table value to PORTD
if(units < 9){
PORTD &= ~(1<<LU9); //the LEd for 9 units is placed on PD7, turn it OFF
}else{
PORTD |= (1<<LU9); //the LEd for 9 units is placed on PD7, turn it ON
}
//write the tenths to the 3 LEDs on PORTD
if(tens & (1<<0)){
PORTD |= (1<<LZ1); //only LZ1 on for 1 tenth
}
if(tens & (1<<2)){
PORTD |= (1<<LZ1) | (1<<LZ2); //LZ1 and LZ2 for 2 tenths
}
if(tens > 2){
PORTD |= (1<<LZ1) | (1<<LZ2) | (1<<LZ3); //LZ1, LZ2 and LZ3 for more tenths
}
}
case COUNTING:{
//do nothing, the interrupts will handle everything
}
}
}
}
/************************************************************************/
/*
ISR for the START button on PD2 (INT0). Once this is pressed the
program switches its state to counting
*/
/************************************************************************/
ISR(INT0_vect)
{
state = COUNTING; //switch state to counting
GICR = (1<<INT1); //allow interrupts from PV
TCCR1B |= (1<<CS12); //set the clock to 256
na = 0;
}
/************************************************************************/
/*
ISR for the PV button which is pressed and counted.
*/
/************************************************************************/
ISR(INT1_vect)
{
na++; //simply increment the number of presses
}
/************************************************************************/
/*
ISR for the compare match with OCR1A. When this ISR is triggered it
means 2 seconds have passed and that the program should no longer
count any presses from PV. The timer should be reset and put in
stand-by.
*/
/************************************************************************/
ISR(TIMER1_COMPA_vect)
{
GICR &= ~(1<<INT1); //disable interrupts coming from PV
TCCR1B &= 0b11111000; //set the clock to '0'
TCNT1 = 0; //reset the timer 1 state to BOTTOM
state = IDLE; //switch the state to IDLE
}
AI: Is there another way around?
The T0 or T1 pin configured as a clock source for Timer/Counter0 or Timer/Counter1 respectively is intended exactly for the purpose of counting total number of external impulses in hardware without need for code to do busy-loop waiting and/or react on each single event.
Nevertheless, the input signal needs to be clean without bounces as there is no option for filtering in the MCU, so you need external debouncing (simple RC filter will do in many situations).
|
H: How would you design a clock in order to play triplets?
If you take a master clock (e.g. 1 Hz) it is easy to get the quarter notes (every pulse), the half notes (every two pulses), and the whole notes (every four pulses) to build a simple drum machine.
What would I need to do in order to create a steady stream of triplets1 from a master clock?
1 A triplet is when three notes of a type take up the same duration as two regular notes of the same type. E.g. three triplet quarter notes are the same 'length' as two quarter notes.
AI: 6 has factors 2 and 3. So if you start with a clock that is 6× your quarter note rate, you can divide by 2 to get eighth-note triplets and by 3 to get eighth notes.
The MIDI system clock messages are transmitted at a rate of 24 per quarter note (2×2×2×3), which allows 64th-note triplets to be generated directly.
Every clock → 64th triplets
Every 2nd clock → 32nd triplets
Every 3rd clock → 32nd notes
Every 4th clock → 16th triplets
Every 6th clock → 16th notes
Every 8th clock → 8th triplets
Every 12th clock → 8th notes
Every 16th clock → quarter triplets
Every 24th clock → quarter notes
... and so on.
|
H: Measuring Current by rectifying or voltage-doubling a Current Transformer
Originally, my plan was to just get the voltage output of a current transformer (obviously with the burden resistor circuit stuff and DC biasing circuit stuff) before ADC'ing it, averaging it’s output per second to get the average current per second. However, I will be using all 6 analog pins in the uC to get 6 outputs from a 60hz current transformer, and the uC only has one ADC, which will make my readings kind of inaccurate. Or is it really inaccurate? Please enlighten me.
https://openenergymonitor.org/forum-archive/node/156.html
I was thinking of rectifying the output of the transformer first and using a capacitor to smooth out the output to get a more stable reading, but since I will be dealing with small voltages, I don’t think that's a viable option. Is there some kind of trick in rectifying small signals with as little drop out as possible?
Source: https://www.electronics-notes.com/articles/analogue_circuits/diode-rectifiers/full-wave-bridge-rectifier.php
Also, I was wondering if it is possible to use a voltage doubler circuit to boost the voltage output of this transformer, since the highest voltage that can be attained by this circuit is 2Vp, but is this really 2Vp? Or is there also a voltage drop from the diodes that needs to be taken into consideration?
https://www.electronics-tutorials.ws/blog/voltage-multiplier-circuit.html
AI: A CT can be generally regarded as having a current output that is proportional to the current flowing through the primary. This is converted to a voltage by the burden resistor. So, if you apply a bridge rectifier between CT secondary winding and burden resistor you get a pretty good approximation to a full-wave precision rectifier: -
A word of warning; don't push it too far - you should be able to get a few volts peak-to-peak but don't aim to get a peak voltage higher than what would be obtainable with the burden placed conventionally because you might suffer a little bit of inaccuracy and, if you take it too far, you might start to overly saturate the CT's core. In other words, don't choose a burden resistor value that is significantly higher than that recommended by the data sheet.
|
H: Function Generator amplifier to drive resonance circuit help
I have a model resonance circuit that is excited with an auxiliary winding and I need to build an amplifier to be able to amplify the current from the function generator in order to drive the auxiliary winding. I have used an OPA548 in Multisim in order to amplify the generators signal by a factor of 3 and it is current limited to an amp. However when simulating I am getting unexpected outputs across the auxiliary winding (7mH inductor) and I do not know how to resolve this or if this is just a multisim error.
Here is the resonance circuit.
Any help would be appreciated, I've never had to make an amplifier for an inductive load before so i'm not sure what I have to account for.
AI: You've made an error here: -
The inverting input should go to the junction of R2 and R3.
Also, driving an inductor directly is somewhat frowned upon given that the likely offset DC voltage from the OPAMP is going to be in the realm of 20 mV and this might be trying to force several amps of DC through the 7 mH inductor.
|
H: TPA3118: coils and op-amp getting warm
I designed a simple board based upon the ds of the TPA3118.
Here the actual schematic:
When I power the device, even with no input signals, coils (L1..L4) and op-amps (IC1..IC2) reach a quite warm temperature:
I understand it's not such an high temperature, but I would like to understand if it's normal. Especially for op-amp I don't understand what they are doing. With no input signals there's only a DC offset (provided by R4 and R6).
The coils are NRS8040T100MJGJ (10 uH, 3.1A, 34 mOhm, 22 MHz).
I checked with the oscilloscope and there are no oscillations in the input pins.
Of course I have the high-frequency "PWM" on the coils - here I can understand the heat.
I measure 135 mA at 24V in this condition.
The board is working. But I want to be sure this is its correct behavior or I missed something in my design.
AI: Just as an example, if you are seeing 49.3 degC in an ambient of 25 degC, the op-amps are warming up 24.3 degC. The thermal resistance of the dual op-amp (NE5532) is circa 90 degC/watt so that would imply the dual op-amps are dissipating about 270 mW each.
The op-amp spec implies a total (both in a dual package) no load current of around 8 mA and, on a supply voltage of 24 volts, that's a power dissipation of 192 mW. Given that you are outputting a midrail of 12 volts (op-amp output) into possibly (say) a 5 kohm pot, that's an extra power of about 30 mW per channel. You have two channels and this takes the quiescent power from 192 mW to about 250 mW and you are almost at the 270 mW dissipation implied from the measured temperature, assumed ambient temperature and details in the data sheet.
By no means is my analysis precise. I've just thrown a few numbers at things and bounced them off the wall to get a ball-park estimate but, it looks believable.
|
H: Input range for TPA311x
I'm reading through the datasheet of the TPA311x family.
I'm looking for the input range for pins INPR and INPL but I cannot find this information. I see the absolute maximum ratings, but it's not what I need. I'm interested in the maximum recommended input range for the audio signal.
I also measure an offset of about 2.90V on those pins, but in the ds I can't find this value neither.
If it's not declared, is it safe to use all the available swing, i.e. 2.90V ±2.90V? It means the input signal might swing from 0.00V to 5.80V.
AI: I also measure an offset of about 2.90V on those pins, but in the ds I
can't find this value neither.
The DS states the pins are biased at 3 volts (page 2).
I'm looking for the input range for pins INPR and INPL but I cannot
find this information.
You take the gain value (programmed at power up) and reverse back from the preferred maximum peak-to-peak output voltage (supply dependent and dictated by your preferred worst case distortion levels) to get the required peak-to-peak input signal.
|
H: Can/will the Qi charging system damage LF (125-133kHz) RFID tags?
In the Qi standard, frequency is listed as 80-300kHz for the higher power application which is within the target(resonance?) frequency of LF RFID tags. So power transmission should be quite high for the tags. Will this damage the tags or can they just ignore the induced current?
AI: Qi chargers do not continuously transmit power. There is a communication and negotiation sequence that occurs to establish what the receiving device requires before the power transmission is started.
The communication will happen at much lower TX power levels to ensure this kind of a problem doesn't occur and when power transmission is in progress the transmitter performs foreign object detection (in case something conductive like an RFID tag gets in the way) and infers the efficacy of the coupling between TX and RX coils to make sure it should continue transmitting power.
|
H: Vivado:Error-Ambiguous clk in event control
Ambiguous clk in event control error and is pointed to always block.
//fpga4student.com
module PWM_Signals
(
input sysclk_p, // 100mhz
input sysclk_n,
input reset_n,
input cpu_restn,
input increase_duty,
input decrease_duty,
output PWM_OUT );
wire clk; //100mhz
wire locked;
wire slow_clk_enable; // slow clock enable signal for debouncing FFs
reg[31:0] counter_debounce=0;// counter for creating slow clock enable signals
wire tmp1,tmp2,duty_inc;// temporary flip-flop signals for debouncing the increasing button
wire tmp3,tmp4,duty_dec;// temporary flip-flop signals for debouncing the decreasing button
reg[7:0] counter_PWM=0;// counter for creating 10Mhz PWM signal
reg[7:0] DUTY_CYCLE=128; // initial duty cycle is 50%
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_debounce <= 0;
else
counter_debounce <= counter_debounce + 1;
if (counter_debounce>=100000000)
counter_debounce <= 0;
end
AI: Your second if statement isn't controlled by reset_n, which makes it non-synthesizable. You probably meant something more like:
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
counter_debounce <= 0;
end else begin
if (counter_debounce>=100000000) begin
counter_debounce <= 0;
end else begin
counter_debounce <= counter_debounce + 1;
end
end
end
|
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