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H: Program FPGA without JTAG? I write embedded software that runs on a single board computer running Linux and talking to FPGAs. I do not do FPGA design, so I'm at the edge of my knowledge with this question: how do I program an FPGA without JTAG? Background At my previous employer, we had what folks called "chain flashable firmware" which meant once we had programmed it via JTAG one time, we could then forever after use software to update the FPGA's code, and next time it booted it would be running the new FPGA version. It took a couple minutes, but worked without issues (unless the power went down while you were running the update... then you were back to JTAG the next time around). At my current employer, this "sounds crazy" to those who write FPGA code. Every time we have to update the firmware, we have to tear everything apart, connect to the JTAG headers, and burn the firmware. (Yes, I understand if we routed the JTAG headers to the outside we would have a much easier time... that's not what I'm asking here.) I want to be able to do this via software, but don't know enough, and every time I search the web for "update FPGA without JTAG" or something like it, I get answers about consumer electronics devices and how to update them. Just not what I'm looking for. To the best of my understanding, the FPGA code is simply loaded into flash or an EPROM or a CPLD of some sort via the JTAG header. What is the mechanism folks use to update firmware without JTAG? Is it just a matter of writing to flash? Do we have to include some IP Core into the firmware that allows it to write back out to the place it reads its program from? Is it a good idea to allow updating firmware without JTAG headers? I don't have any issue with it, but some express reluctance. My view is if we can do it in software and save ourselves a ton of time and effort, let's do it. Is there a MicroSemi version of Xilinx's SelectMAP? I think this might be what I'm looking for. What am I not asking that I should have? Note: according to this guys answer, this is totally doable, BUT in my case I must have the firmware up and running well before the software comes up, so I can't be dynamically loading the FPGA code from the software each time the FPGA boots. It needs to be stored in some memory the FPGA uses upon its boot up, not coming from software. The only time I want it to come from software is when I attempt to change what the FPGA sees upon it's next boot up. Thanks! AI: If you want to program the FPGA directly, such as when you are doing development work, you will use JTAG. If you want to program an FPGA that uses external memory (which was the norm until recently) then you need only program the external memory device (which generally have their own programming protocols not using JTAG) and then reset the FPGA so that it does a load from memory. I suppose it possible, though I have never done it myself, to allocate part of the FPGA to implement a loader so that you can load it (partially at least) using a different protocol than JTAG and go from there but that would be entirely up to the developer of the system.
H: Full-Bridge Mosfet Vds Waveform Problem I'm trying to build a full-bridge dc-dc converter, PWM signals are ok but drain-source waveform has some problems. Here is drain-source waveform with a proper pwm signal on gate. Then I decided to add a C snubber(100nF) across drain-source and waveform turned into this: Is the voltage waveform in 2.pic is acceptable? or do I need to make changes? I'm very weak about snubbers, even I don't know which snubber to use or should I use a snubber? Or is there any other way to make this better? AI: A snubber is designed to suppress voltage spikes. In your first photo, you don't really show any spiking, so a snubber is not what you need. It looks like the problem is insufficient gate current. There is a drain-gate capacitance in a MOSFET that is likely causing your problem. When you switch "on" and the gate threshold is reached, the drain voltage drops from a high voltage to the source voltage at a high rate of dV/dT. If your gate drive has a high output impedance, this change of drain voltage tends to drive your gate more negative through the drain-gate capacitance. Since the gate has just passed the threshold , it is driven back below the threshold and turns the MOSFET "off," as shown in your first photo. The drain voltage rises and the gate voltage continues to increase and then the MOSFET turns back "on." The same thing happens on the falling edge, except the polarities are reversed. In you first photo, this happens once on the rising edge and two or three times on the falling edge. When you put a capacitance across the drain to source, the rise and fall times are slowed so that the coupling from through the drain-gate capacitance is reduced. However, your capacitor combined with your circuit's inductance forms a "tank" circuit with the characteristic decaying sinusoidal waveform on every edge, shown perfectly in the second photo. To solve your problem you can put in a gate driver with high current capability that will override the coupling effect. Or you can try a FET with lower gate-drain capacitance (which usually means a higher "on" resistance). Or you could have a layout problem - make sure your traces between the gate driver and gate are short and fat. When done right your switching time will go down and your "on-off-on" issue will be solved. A capacitor across the drain-source is not usually a good idea; it just causes higher peak currents. When you get this fixed, your switching time will decrease and your efficiency will go up. If you have inductance in the layout, and this causes voltage spiking, then you can consider a snubber. Good luck!
H: How to match two impedances which both have an imaginary component? I am designing a matching network for an inverted F antenna, the source RF pin impedance is 30 Ω + j10 Ω (source IC is an ESP32-D0WDQ6, datasheet here, RF pin impedance in section 2.5 on page 7). I will be designing the antenna using the openEMS simulator software. The datasheet calls for a pi-network close to the IC and a 50 ohm transmission line (datasheet in section 3.1.5 on page 16) the antenna will be as close to 50 ohms as possible, frequency is 2.4 GHz. The PCB layout is very similar to what is shown in the image below, I have the output capacitor of the pi-filter connected directly to the antenna input with no transmission line, and the transmission line coming from the IC is only 1 mm in length. I asked a similar previous question to which someone offered a solution on how to match the source impedance to 50 ohms using this method: If your antenna is 50 Ω and your source is 30 Ω + j10 Ω then, add a series capacitor of -j10 Ω to cancel out the +j10 Ω effect of the inductor. This now means you are trying to match 30 Ω resistive to an antenna of 50 Ω resistive. Then use an L-pad calculator like this: - You can double check the formula derivation on that site. Series inductance needs to be about 1.6 nH Parallel capacitance needs to be about 1.1 pF Then, if you went back to the start of the problem and analysed what value of inductance is needed to produce the j10 Ω in your driver output impedance, you'd calculate it to be 0.663 nH at 2.4 GHz. This means that you can actually dispense with the added series capacitor of -j10 Ω (as originally proposed) because you need 1.624 nH from the above calculator. The upshot of this is that 1.624 nH might as well be 1.663 nH so, the external series inductor you need to add is 1 nH. But an antenna is rarely ever purely 50 ohms resistive once it is on the board, and will involve some imaginary component. My question is, how will I match the source impedance to the antenna impedance if the antenna impedance also has an imaginary component, say it ends up being 55 Ω + j 15 Ω. HERE IS MY 2 PART QUESTION: How would I match 30 Ω + j 10 Ω to 55 Ω + j 15 Ω using a pi-filter? Or any other filter topology if another would be any advantage? The datasheet says the pi-filter should be placed close to the IC and the output transmission line should be 50 ohms to the 50 ohm antenna, but I essentially do not have a transmission line, only the 1 mm trace leading to the pi-filter. Since the source is not 50 ohms, would there be a more ideal impedance to set the transmission line at which leads to the pi-filter from the IC? Such as 30 or 40 ohms? Here is an image of the layout they use on the ESP32 module: AI: For question 1: the previous answer suggested putting a capacitor (negative reactance) in series with the load to make the load entirely real. Then you can match the real source to a real load. If both the source and load are inductive, then place one capacitor in series with the load to cancel out the reactance, then put another capacitor in series with the source to cancel out the source reactance. When you do that, you can match a real source to a real load. For question 2: your transmission line impedance should match both the load and the source impedances in order to deliver maximum power to the load. So if your source is 30 ohms, and you impedance transformed the load to be 30 ohms, then you should use a 30 ohms transmission line. That said, the impedance mismatch between 30 and 50 ohms isn't that much \$\Gamma=\frac{50-30}{50+30}=1/4\$ so the power delivered is \$1-\|\Gamma\|^2=94\%\$. So if you just made you load 50 ohms, used a 50 ohm transmission line, and had a 30 ohm source, you'd still deliver 94% of the power to the load.
H: Phase shift in AC Circuit power calculation I have the below question. I am not trying to ask the answer for the problem. But my question is that, we can see that 60deg is the phase shift. But both the voltage and current across the passive element is 60deg. With respect to what is the phase shift 60deg. Is the phase shift 60deg is with respect to AC Voltage source? Or is it with respect to what? And for the power calculation, I should just multiply the values of V and I. AI: If I said that the voltage was \$10\cos(100t)\$ and the current was \$5\sin(100t)\$, would you be asking about the phase angle? I mean; the phase angle (when not mentioned) is implicitly assumed to be 0° so there wouldn't be any worry there if it wasn't mentioned. Are you OK with that? So, if both voltage and current are shifted by 60° (or any phase angle), does it really affect how you would answer the question? No, because both are time shifted by the same amount and, the load that converted the cosine voltage waveform into a sinusoidal current is still exactly the same. With respect to what is the phase shift 60deg. To answer your question; it matters not one bit what the 60° is relative to. And, it's exactly the same when phase angle is not mentioned (assumed to be 0°). Other (different) problems involving phase angle might require us to validly ask what it is respect to but not in this example. And for the power calculation, I should just multiply the values of V and I Unfortunately, the answers given are probably all wrong. When we talk about voltages or currents and mention the "sin" or "cos" parts we are implying that the voltage or current is a peak value (not an RMS value). To calculate VI or watts we have to use RMS voltage and current values and, the apparent power for a 10 volt peak amplitude voltage and a 5 amp peak amplitude current is 25 VA. So, if the answers to the question are all using phasor notation (\$X\angle\$ for instance), \$X\$ should be an RMS value.
H: Calculate the finger position on a Capacitive touch slider When building a Capacitive touch slider like the picture shows, I know when finger tip touches the metal slider it would create a apparent sensor capacitance is increased by the introduction of a parallel path to earth through human body. But how could the exact position of the finger tip on the plate be calculated? AI: The capacitive sliders are usually done using two capacitive plates, both referred to ground (not in mutual capacitance). The trick is drawing them sloped (triangular, not rectangular). When you touch the slider, in that position there will be usually one bigger and one smaller plate (except right on the middle), so you'll have two capacitance values. Some math will give you the estimated position.
H: Is my battery really fully charged? Should I use the "pulse repair" button of my charger? I have a 12V lead-acid battery that is detected at 0.8V when I use a multimeter: When I plug my charger it says "fully charged": Should I use the "repair" button of my charger (I don't know what it does)? Is my battery dead? How can I charge it with the charger I have? I have no knowledge about this kind of things. AI: I would defenetly look at the multimeter readout. It looks like the battery is dead. When the voltage on 12V battery falls <9V it get's permanently damaged. You can attempt to charge the battery using bench PSU, with low current at the start, however the capacity will be signifficantly lower forever. I used to repair those batteries with charging them on bench PSU, adding distilled water, charging, adding few drops of water, discharging, charging, water and so on. But this is probably not worth it.
H: +-33V Overvoltage and reverse polarity protection I found on this forum a schematic (Zener + MOSFET overvoltage protection). But It does not work and I can't figure out why. this is the schematic: I want to protect the power supply of an opAmp form voltage above 33V (and symetric -33V). It's maximum votlage is +-45V. For some reason M3 is always conducting and doesn't deactivate when M1 is conducting.. Which should bring M3s gate to the same voltage than M3s source, thus deactivating M3. I know there are many other circuit possible do achieve what I want to do. But I'm wondering why this doesn't work because thoereticly it seems ok to me. For my academic knowledge ^^. Thanks for your help. AI: I can't reproduce your problem, it works for me. The green graph is the voltage over the load with increasing input voltage. And for the negative side with the corresponding n-channel (and rotated diode):
H: Connecting analog GND and power GND I need to connect a power ground and an analog ground. The power ground is a SMPS output. The analog side consists of 8 opamps and their resistors and capacitors. What's the best way to connect these two ground? With some ferrite beads? Resistors? Or directly connect them without any components between them? AI: This answer is valid if you have 1 power supply for both analog and digital parts. The picture comes from this Analaog Devices' tutorial: https://www.analog.com/media/en/training-seminars/tutorials/MT-031.pdf?doc=CN0156.pdf CASE 1: Double layer PCB Route all AGND signals to the GND pole of the connector. Alternatively, route all AGND signals to one point of the board, and then route that point to the GND pole of the connector. CASE 2: Multi layer PCB (This is my way of routing) Split the GND layer in 2 parts: AGND and DGND. Route AGND to the GND pole of the connector without crossing DGND (). Route all AGND signals to AGND. Usually, AGND split plane (that's the technical name) are small areas. () This is what I do usually unless the manufacturer of that particular integrated circuit gives me specific instructions about routing. TI and ST, for example, write application notes that tell people how to route AGND and DGND and all the critical signals.
H: What is this electrical component on a Time Crisis II I/O PCB? I have a Nanco Time Crisis II That has a bad I/O board. Power is getting to the board, but not making it to the chip on the board (activity LEDs not flashing). I’m trying to trace where there may be a problem but there are components on the board I don’t recognize. What is component FL1 & FL2? They have 3 legs and the only other marking on it is 222. How do I test it? Can I test this in-circuit? AI: FL is usually the designator for a FiLter, I believe. Most likely, they're a simple filter network of some sort, probably either to filter noisy input power or to filter noisy signal lines.
H: Adding harmonics to the square wave means I have generated two imperfect square waves by: Adding fundamental frequency with 10 odd harmonics. Adding fundamental with 20 odd harmonics. What difference should I observe between two imperfect square waves by increasing the number of harmonics? AI: A practical answer The -3dB BW is defined by the 10% to 90% rise time $$f_{-3dB}=0.35/Tr$$ which is an approximation for a 1st order filter response. Yet a square wave BW limited is not a 1st order signal, so this is just a -3dB approximation of BW not a -20 dB BW which would include your 1st 10 odd harmonics while all the even f’s are zero or - infinity dB. All spectral components are odd and cos(-90 deg) and successively smaller with higher order such that the 11th harmonic is down ~ 20 dB from the fundamental. So your -20dB BW is 11 x fo and fo is not 0dB but rather ~2dB. Since the risetime is created only by the -3dB BW, each odd harmonic has only a smaller impact on the risetime until the Tr reaches 0, but rather more visibly contribute to the <10% and >90% with ringing and over/undershoot like any underdamped filter greater than a 1st order filter. The ringing in the square wave will be at the last odd harmonic included. Each subsequent odd harmonic will reduce the overshoot and ringing at that harmonic until infinity when the overshoot and risetime is zero. Each subsequent harmonic contributes less overshoot at that frequency and even though the 41st harmonic (1+20f * 2) is only 10 dB lower than the 21st harmonic, with 20 odd harmonics added the overshoot is still about 10% of the 0 to peak amplitude in the time domain. 10% time domain overshoot is almost 1dB of overshoot. Integrating a square wave into a triangle wave results in all spectral components now at cos(0 deg) and down 6 dB per octave or -12 dB per odd harmonic. So what’s the difference between 10 odd harmonics and 20 odd harmonics? about 1dB of residual overshoot after 20 harmonics (41st) and about -30 dB of the 41st harmonic. An interesting feature of a square wave is you can compute and measure the asymmetry easily on a spectrum analyzer for very small errors much easier than using an old CRT as the even harmonic 2f rises with a predictable nonlinear curve in dB with asymmetry. I found this very useful for designing a perfect RF limiter on an RF sinewave. << 0.1% square wave = ?? -dB on 2f (quiz) then 1% asymmetry = (?) To understand intuitively more about Fourier Transforms or rather spectral density waveforms, try Falstad’s Fourier site http://www.falstad.com/fourier/ And choose log display with phase then experiment with different periodic signals and then modify time domain or f domain response with a iOS pen or Windows mouse. If you want to design a filter with constant group delay or steep skirts or zero overshoot in the time domain go to his filter site, http://www.falstad.com/afilter or his time domain site and copy paste your filter to analyze it. The more you seek, the more you will find, the smarter you become. Feel free to edit oops by adding or subtracting to this answer.
H: Help with LTSpice full-wave rectifier simulation I'm fairly new to LTSpice and its function. Our professor asked us to construct this specific circuit (in the photo). I tried doing it on my own, but I am not that confident if my LTSpice circuit is the same as the one that is instructed. Note: Our professor only taught us the basics of LTSpice, like how to put different components etc. The photo below is my attempt: May I ask if I should change anything in my LTspice simulation or is it already correct? I also do not know anything about potentiometer or even oscilloscope. Those two terms are fairly new to me. AI: Your voltages are wrong. 24VAC is the RMS voltage, and LTspice uses peak. LTspice has a pot component that allows you to set the shaft rotation from 0..1 And you have a short. Either flip one voltage source or (better IMHO) add a phase shift phi of 180° to one of them).
H: What have I done wrong in determining the transfer function for this RCL circuit What have I done wrong in determining the transfer function for this RCL circuit? (1) $$\dfrac{Eo(s)}{Ei(s)}=\dfrac{s^2R_2CL+sL}{s^2CL(R_1+R_2)+s(R_1R_2C+L)+R_1} $$ Regardless, of how many times that I try, I get the same result. However, my TF response doesn't match the circuit response, as can be seen. Using complex impedance method Defining $$z_1 = R1 $$ $$z_s=\dfrac{1}{sC} + R_2 = \dfrac{1+sR_2C}{sC} $$ $$z_p = \dfrac{z_sz_L}{z_s+z_L}=\dfrac{\dfrac{1+sR_2C}{sC}sL}{\dfrac{1+sR_2C}{sC}+sL} =\dfrac{\dfrac{s^2R_2CL+sL}{sC}}{\dfrac{1+sR_2C}{sC}+sL}$$ Multiplying numerator and deniminator through by sC $$z_p=z_2=\dfrac{s^2R_2CL+sL}{s^2CL+sR_2C+1} $$ Therefore, we have that $$\dfrac{Eo(s)}{Ei(s)}=\dfrac{z_2}{z_1+z_2}= \dfrac{\dfrac{s^2R_2CL+sL}{s^2CL+sR2C+1}}{{R1}+\dfrac{s^2R_2CL+sL}{s^2CL+sR2C+1}}$$ Simplifying $$\dfrac{Eo(s)}{Ei(s)}=\dfrac{s^2R_2CL+sL}{{R_1(s^2CL+sR_2C+1)}+{s^2R_2CL+sL}}$$ $$\dfrac{Eo(s)}{Ei(s)}=\dfrac{s^2R_2CL+sL}{s^2CL(R_1+R_2)+s(R_1R_2C+L)+R1}$$ AI: Well, we are trying to analyze the circuit. When we use and apply KCL, we can write the following set of equations: $$\text{I}_{\text{R}_1}=\text{I}_\text{L}+\text{I}_{\text{R}_2}\tag1$$ When we use and apply Ohm's law, we can write the following set of equations: $$ \begin{cases} \text{I}_{\text{R}_1}=\frac{\text{V}_\text{i}-\text{V}_1}{\text{R}_1}\\ \\ \text{I}_\text{L}=\frac{\text{V}_1}{\text{sL}}\\ \\ \text{I}_{\text{R}_2}=\frac{\text{V}_1-\text{V}_2}{\text{R}_2}\\ \\ \text{I}_{\text{R}_2}=\text{sC}\text{V}_2 \end{cases}\tag2 $$ Substitute \$(2)\$ into \$(1)\$, in order to get: $$ \begin{cases} \frac{\text{V}_\text{i}-\text{V}_1}{\text{R}_1}=\frac{\text{V}_1}{\text{sL}}+\frac{\text{V}_1-\text{V}_2}{\text{R}_2}\\ \\ \frac{\text{V}_\text{i}-\text{V}_1}{\text{R}_1}=\frac{\text{V}_1}{\text{sL}}+\text{sC}\text{V}_2 \end{cases}\tag3 $$ Now, the transfer function is given by: $$\frac{\text{V}_2}{\text{V}_\text{i}}=\frac{\text{sL}}{\text{CL}\left(\text{R}_1+\text{R}_2\right)\text{s}^2+\left(\text{L}+\text{CR}_1\text{R}_2\right)\text{s}+\text{R}_1}\tag4$$ Where I used the following Mathematica-codes: In[1]:=Clear["Global`"]; FullSimplify[ Solve[{IR1 == IL + IR2, IR1 == (Vi - V1)/R1, IL == V1/(sL), IR2 == (V1 - V2)/R2, IR2 == scV2}, {IR1, IR2, IL, V1, V2}]] Out[1]={{IR1 -> (Vi + c s (R2 + L s) Vi)/( R1 + (L + c R1 R2) s + c L (R1 + R2) s^2), IR2 -> (c L s^2 Vi)/(R1 + (L + c R1 R2) s + c L (R1 + R2) s^2), IL -> (Vi + c R2 s Vi)/(R1 + (L + c R1 R2) s + c L (R1 + R2) s^2), V1 -> (L s (1 + c R2 s) Vi)/( R1 + (L + c R1 R2) s + c L (R1 + R2) s^2), V2 -> (L s Vi)/(R1 + (L + c R1 R2) s + c L (R1 + R2) s^2)}}
H: Asynchronous FIFO design with PULSE synchronizer I'm trying to understand various implementations of asynchronous FIFO from the following link https://inst.eecs.berkeley.edu/~cs150/sp10/Collections/Discussion/Honors/Honors14_1PP.pdf In the slide 7 there's a proposal where pulse synchronizers are used for read and write signals which are the. This design doesn't work because if the reads and writes are high in successive cycles(burst transfer), pulse synchronizer output will only output one pulse in destination clock domain. Am I correct? Suppose if I have a case where writes and reads are not continuous but are separated by fixed 2-3 cycles will this design work? Will it have any further issues? AI: This design doesn't work because if the reads and writes are high in successive cycles(burst transfer), pulse synchronizer output will only output one pulse in destination clock domain. Am I correct? If you want to use pulse synchronizers to keep read-write pointer/counters synchronized to the respective clock domains, there are overheads to keep in mind. Normally you want to continuously enqueue/dequeue data to/from a FIFO every clock cycle. Suppose you keep write signal high for say 2 clock cycles, you have to get 2 synchronized pulses or a two-cycle long pulse at the read-clock domain, which will then update the pointers and the FIFO works flawlessly. BUT unfortunately pulse synchronizers don't work like that. Pulse/Toggle Synchronizer Consider a simple toggle/pulse synchronizer like this: (credits: edn.com) For this pulse synchronizer to work correctly, the output signal from flop-A has to be stable for a minimum time period such that there is at least one clock edge at destination clock that will sample the data correctly without metastability. This is because it's possible that the signal causes metastability in the first clock edge at flop-B1. After metastability, flop-B1 may settle to a wrong value, which is then propagated by rest of the flops. However if flop-A output signal remains stable until the next destination-clock edge, it is sure that the correct value is sampled at the second clock edge. Scenario Suppose write-clock is very faster than read-clock. Say, you keep write signal asserted high for 2 successive clock cycles (as we discussed at the beginning). What happens is that flop-A output toggles for a single write-clock cycle, and it is never sure that this single-cycle pulse at flop-A is correctly synchronized to the read-clock because of metastability. May be this transition gets completely missed before any sampling clock edge arrives at read-clock. It is also possible that the '1' from flop-A was sampled so close to the read-clock edge and it settled to '0' after metastability. Then the sampled signal remains '0' in remaining read-clock cycles as well, because the flop-A's output signal has already de-asserted after one write-clock cycle. The result is that the you missed the pulse completely. So the write pointer/counter will not be updated at the read-clock domain, and thus the pointers goes out of sync at the two clock domains, and the functionality of the FIFO flaws. Thus you can't really get full throughput if you design an Asynchronous FIFO using pulse synchronizers. You have to pulse write and read properly for successive data transfer with enough time-period between the pulses for the destination clock domain to correctly sample and update the pointers. Suppose if I have a case where writes and reads are not continuous but are separated by fixed 2-3 cycles will this design work From above discussion I guess it's already clear that there is a dependency on clock periods of read and write. Suppose read-clock is at 10 MHz and write-clock is 100 MHz, pulsing write every 2-3 clock cycles is not going to guarantee synchronization with read-clock domain. Pulsing write for one cycle generates an active-high strobe signal (at Flop-A) internally which has to be sampled and converted to pulse at read-clock. You need longer wait duration before you can pulse the next write and be absolutely sure that synchronization happened; in this it would be greater than the period of read-clock ie., \$> 10\$ write-clock cycles.
H: Question about PID control loop timing For my project I am creating a RISC processing architecture on an FPGA that can perform various basic instructions like adding, multiplying, subtracting, storing and fetching from memory etc. To prove my architecture I am using these instructions to control the speed of a motor using a PID control loop. So the system has a potentiometer to set a speed setpoint, a direction and start/stop inputs, a motor driver to drive the motor with PWM, and an encoder to read the speed back. Its pretty simple. I at the stage where everything has been tested individually and can now start controlling the motor speed with the PID loop. I am new to PID loops but have been reading up on them. I read the speed setpoint from potentiometer and rotational speed from the encoder every 1ms. However in my program that I write with instructions that is ran at 100MHz, I keep calculating the speeds as they are refreshed every 1ms. So I calculate the same answer a lot of times before it is refreshed. This is no problem currently as it is only for display on 7 segments. From my PID loop understanding, you need a fixed scan time as the integral and derivative accumulations will be skewed. Currently I have no means to do this as my processor will be calculating at 100MHz but the variables are only refreshing at 1ms. I have two questions: Should I add an interrupt capability to my processor to only run the PID code every 1ms as the speeds are refreshed? Also in your opinions, is every 1ms too fast or too slow to refresh the values? This is a motor and encoder on a bench with no load so it probably doesn't even matter, I am just unsure. If there is anything unclear, please ask :) EDIT Some additional process information: Motor speed: Approx 1000 to 4000 rpm max Motor no load, full speed current: 200mA Motor load: Virtually nothing, just an encoder Motor driver: L298n (PWM is created in FPGA logic) Encoder type: Rotary incremental encoder, 2 12V channels 90 degree phase shifted, 1000ppr (doubled to 2000ppr) AI: 1st write a spec with the Current vs acceleration vs RPM then repeat with an inertial load as the optimal PID parameters will change especially with reverse. Create an algorithm for it. Also determine the power dissipation for such duty cycles of acceleration and create an algorithm for that. You ought to know that no-load = kV or RPM/V is a constant and current is proportional to force of acceleration which depends on load and there is a stall stiction start current. You those two feedbacks with your encoder velocity and current feedback to create two loops and determine the error with your target profile and use PID feedback to optimize stability and minimize 1 or more parameter choices. Eg. Max/rated current, seek time, etc. So the signal bandwidth changes and the error tolerance on each control variable including overshoot and settling time are your specs. The lighter the load, the more bandwidth from faster response and samples per second you will need to support the dynamic range of speed control and tolerance error. BW=0.35/Tr 10~90z handles only 3dB of BW but your step changes might span from 3 dB to 20 dB or more, thus depending on your goal to make the fastest settling (Tbd BW) time with minimal TBD overshoot determines your sampling rate. car wheel magnetic speed sensors for example using Infineon IC measures velocity from 0.5 to over 150 kph for smart cornering and braking with something like 100 magnets per rev as the wheel encoder which is excessive at high RPM but this is how it measure speed. So the LSB’s are truncated at low speed and DSP interpolates with a Biphase digital output in addition with the ~ 100ish pulses per rev. the ECU handles all the PID etc. You might want to be more ambitious in Your project. p.. don’t use a BJT driver, use a Full bridge NCh driver that can handle your motor. Like an Arduino CNC shield. Look for PMIC software.
H: Why is the arrow on this MOS transistor IC common? The schematic below is of a CD4007 MOS transistor chip. From the schematic it can be seen that on either side, PMOS or NMOS, the arrows indicating what type of MOS transistor it is are all connected to a single pin - pin 7 for the NMOS side, and pin 14 on the PMOS side. In this case, pin 7 is a source and pin 14 is a drain. Why is that? Does anything need to be connected to those pins to use the other transistor in the chip? AI: That is the body connection. All MOSFETs have a fourth connection to the substrate, but for discrete MOSFETs this is normally connected internally to the source which results in a parasitic body diode anti-parallel to the source-drain. So in a typical discrete MOSFET you see the body connection tied to the source terminal and you get the MOSFET symbol which you are used to see which looks like this: simulate this circuit – Schematic created using CircuitLab But if you are designing on silicon wafer you get to do whatever you want with the body connection. On a very few discrete transistors, the body connection is run out so you can use it however you want. One such application is a CMOS transmission gate. Taken from: https://learnabout-electronics.org/Digital/dig55.php The NMOS body is connected to the most negative rail in the system and the PMOS connects to the most positive rail in the system (much like in your schematic). Doing this allow the MOSFET to block current in both directions which is something it cannot do when a body diode is present. As a result, you can't make a CMOS transmission gate if the transistor body connection is fixed to the source terminal. I wish more MOSFETs did run the body connection out. There might be other ways or reasons to connect the body, but I don't know them.
H: How can a diode parallel to the source can't take the source value but take about 0.7V? I was practicing diode circuits and this question stucked in my mind. When a diode connected parallel to a DC voltage source, doesn't it have to take the value of the source rather than 0.7V according to Kirchoff laws ? ( the diode is forward-biased ) AI: In an ideal circuit with a ideal voltage source with a perfectly constant voltage output and no output resistance, and ideal diode with no resistance and a constant voltage drop, there is no answer. It is a contradiction, which is why it is ideal and doesn't actually exist. It is basically unstoppable force (the voltage source) versus immovable object (the diode voltage drop). In general, this is why ideal things are ideal. They are simple to work with, but there's a logical contradiction lurking in there somewhere that doesn't allow it to actually exist. But in reality: the voltage source has output resistance which causes the voltage output to decrease as the current supplied increases the diode's voltage does change very slightly as current increases as the current running through it increases This means that as the current increases the source voltage output and the diode voltage drop approach each other. However, good voltage sources have low output resistance, and diodes take a lot of current to change their forward voltage drop by a little bit so the practical result is usually that the voltage source has to output so much current that it explodes before the equilibrium can be reached.
H: Oscilloscope bandwidth and PWM pulse width I've been working on a project which involves a PWM signal that operates at 30khz with a 10 bit resolution. I am generating the signal with a Teensy 4.0, which has a 600mhz processor, well above the ~31mhz required to generate the PWM frequency and resolution I need. I was measuring this signal with my oscilloscope, just to verify that everything was working, and I noticed that as soon as the PWM pulse width drops below 200ns, I stop seeing well-formed pulses. 200ns corresponds to ~5mhz, and my scope has a 100mhz bandwidth, so my sense is that is should be able to display the minimum pulse width of a 30mhz signal. Am I wrong about this, or is it possible that something else is affecting the my ability to either emit or measure pulse widths below 200ns (as far as I can tell—the actual point where it stops providing clear measurements might be lower). I checked my probe and it was set to 10x, as was the oscilloscope, so I don't think that's a factor. Here's a 300ns pulse. I was actually able to measure a 200ns pulse by increasing the PWM frequency to 48khz (sorry about my fingers, but you can see the important bits) This is the minimum pulse width, which should be about 32ns AI: The small B in the CH1 label below indicates that the BW limit is on. click on CH1 knob and select Bandwidth Limit Off The real signal will look more rectangular most likely. The bandwidth limit is offered by these scopes so you are not overly confused by the oscillations when not doing a proper differential measurement with low loop impedance return cable. It also helps to see mVs of ripple in the kHz range that can be buried in 10s of mV rms wideband noise.
H: What kind of gps battery can I use for uBlox NEO-M8N GPS module? What kind of gps battery can I use for uBlox NEO-M8N GPS module? Would you please recommend gps battery? and Which can I use 5.5mAh or 11mAh?For example; MS621FE-FL11E - BATTERY LITTIUM 3V 5.5MAH (https://ozdisan.com/bataryalar/sarj-edilebilir-piller/lityum-piller/MS621FE-FL11E) Seiko MS920SE-FL27E Lithium ion Şarjlı Pil / 3.0V 11 Mah (https://birikimpilleri.net/endustriyel-piller/lithium-ion-buton/920/prd-seiko-ms920se-fl27e-lithium-pil) If you know better please recommend to me..thanks AI: Question What kind of power source should I use for the uBlox NEO-M8N GPS module? Answer uBlox NEO-6/7/8M GPS Module has a small button battery on board to hold the config/fix data. You need an external power source for the module. Neo-6/7/8M GPS Module Setup Example 1 I am using bench top 220VAC to 12VDC and a LM2956 12VDC to 5VDC step down 2A PSU to power the GPS module. I also tried Lipo 18650 batteries but found them not necessary to improve any performance. The GPS module has a small on board button battery at the top left corner of the module. Neo-6/7/8M GPS Module Setup Example 2 The photo shows the small button battery at the bottom left corner. See the reference below for more details / to continue, ... References (1) Rpi Neo-6M / Neo-8M GPS Module Setup / Fix / Update Problems (2) How can Rpi listen to a GPS module? - RpiSE 2020jun02 (3) GPS taking long time to fix out in the open - EESE 2020sep03 / to continue, ... Appendices / to continue, ...
H: Is this diagram wrong as the congruent circuit? Given the below diagram. The 2 identities are given. $$ V_{1}=AV_{2}+BI_{2} $$ $$ I_{1}=CV_{2}+DI_{2} $$ $$ A,B,C,D~\text{are constant coefficients.} $$ As \$V_{2}=0~\$ \$V_{1}=BI_{2}\$ \$I_{1}=DI_{2}\$ the above circuit is congruent with the below diagram. Hence, \$V_1=r_3I_2\$ \$V_1=r_1(I_1-I_2)\$ These statements are given from the textbook. The problem for me is that why the pre position of \$r_2\$ was shortened in the second diagram. I think that as \$V_2=0\$ then any current doesn't flow between the endpoints of \$r_2\$ so this part must be opened,not be shortened. Is the second diagram incorrect? AI: The second diagram is correct, because imposing \$V_2=0\$ means that no voltage drops across that portion of the circuit and such a condition is obtained indeed by short-circuiting \$r_2\$. This condition does not imply no current flow, and in fact \$I_2\$ flows through \$r_3\$, down into the shorted branch (by-passing \$r_2\$ and thus avoiding any voltage drop across it) and back towards the negative "side" of \$V_1\$, where it is combined with \$I_1-I_2\$ correctly yielding \$I_1\$. Put it another way, if you actually opened your rightmost branch, then no current would flow through neither \$r_2\$ or \$r_3\$, but \$V_2=V_1\neq0\$ would hold and contradict your starting \$V_2=0\$ assumption. Summarizing: \$I=0\$ --> open circuit \$V=0\$ --> short circuit
H: Decay Modes - Stepper Motor related Query I'm trying to understand something fundamental about Decay Modes.It is widely accepted on the internet that a slow decay mode shorts the Back-EMF of the motor and in essence stops the motor instantaneously. Hence the torque generated is higher when slow decay mode is used in comparison with Fast Decay Mode. I have a few queries regarding this When slow decay mode is used, the motor is shorted to ground through the Rds of the of lower MOSFETs, this doesn't imply that the voltage across the coil has to become zero, a high enough current can flow to maintain a high Back-EMF. When the Back-EMF is zero the current through the coil is still present, doesn't the coil current dictate the torque generated? Why does the Back-EMF have precedence over the coil current when it comes to the torque. Please help me clear any misconception I have regarding this Thank you AI: Remember that current and voltage are always tied unless there is an impedance in between. That impedance could be (and often just is) the wiring but usually we think at components as 'directly connected'. In the same way 'instantaneously' doesn't exist, otherwise mechanically the motor would rip itself from the bearing from the inertia and torque. Decay modes in stepper are mostly related to how current is regulated in the winding. Do not confuse steppers with brushed DC: a supplied DC motor runs, a supplied stepper motor just holds position with some torque. You need to commutate the phases to do this. Also back-EMF is way less relevant in stepper unless at high speeds (it's used for stall detection, for example, but it doesn't work at slow speed). Since current regulation in the winding is done following the current ramp of the winding decay modes changes indirectly the control profile: the driver can only make the current rise (with the time constant of the windings) or let the current decay (either shorting or leaving open the bridge). The resulting current ripple is actually torque ripple (holding torque or running torque depending on the mechanical alignment). The issue arises especially with microstepping when the current controlled is different from the current one: it can only rise at one speed but can decay at two different speeds. It gets even more complex since the drive can use fast decay for one part of the cycle and slow decay for the rest of the cycle. Like for PWM the net result is any decay speed in between (this is called mixed decay). Each controller does it in its own way: I used the DRV8885 and there are more than 4 pages in the datasheet explaining pros and cons of each decay modes.
H: Help in assessing the input mains circuit integrity I've been working on designing a (220-380 VAC) 3/4 wire phase energy meter and in terms of metrology operation, things were working very well quite similar in terms of metrology if compared to a commercial unit. Now I'm no expert in mains power electronics circuit design so I opted to integrate an off the shelf AC/DC flyback power supply, which when integrated in the meter worked well in lab conditions. I've followed and implemented the mains Input protection circuit going into PSU which is specified by the PSU manufacturer but to be honest I feel helpless as I have no idea how to calculate/know how and why the values are specified in this stage, I need to be able to know how much energy/ voltage and the where bouts of the circuit operates in a surge, fast transient and ESD situation since I plan on doing a pre-compliance test and one of the tests I'm concerned with is if the input protection fails then I have not backup plan so I would really appreciate if someone would kindly share his insights and knowledge on how to pre-simulate or calculate the values of the input circuit below in order to pass the following test conditions below as well. Schematic of the mains input circuitry with the power Supply Test 1 Test 2 Test 3 Some information on the MOV used on each line (230 VAC My questions : How do you calculate/simulate or choose the correct MOV model/value for the above application to pass the test conditions mentioned above? Will the current input stage of the power supply survive the tests mentioned above? Final Note: I come from an Electronics and Communications background and i have done a reasonable amount of work in low voltage (analog, digital) board designs but I'm no expert in this subject but I'm willing to learn. I know how to simulate how an AC signal going in to a bridge rectifier and analyse the output; you know basic stuff that most of us learned during undergrad, but the (fast transients, etc) on an AC mains situation, I've never worked with such case. I'm having a hard time on how to figure out how to model and simulate the MOV in the simulation programs (LTSpice, Proteus ISIS & TI TINA). AI: I need to be able to know how much energy/ voltage and the where bouts of the circuit operates in a surge , fast transient and ESD situation and How do you calculate/simulate or choose the correct MOV model/value for the above application to pass the test conditions mentioned above ? You need to model the way in which the surges, bursts and ESD are applied to your live and neutral connections. There will be an interface circuit for all three and, these circuits should be locatable on-line. For instance, indirect lightning surge testing is available because I've researched it myself to uncover whether some TVS diodes (that I was planning on using for a particular job) were man-enough to withstand the surges. So, do some digging and uncover those circuits - they won't be too tricky - you can easily model the waveforms with straight lines ramps of voltage; it doesn't need to be exact - reasonable approximations to the waveforms are good enough but, the important thing to model is the surge/burst/discharge source impedance because this tells you how much current is fed to the protection device when it is protecting. In my surge example above, I had to deal with surge voltages at a peak of 4,000 volts sourced through a 2 Ω series resistor. In other words, the peak current could be up to 2,000 amps. So, I modelled it and simulated the surge protection circuit and determined how much peak energy I might subject my TVS to. Then I looked at the data sheet for the TVS and worked out whether I had a comfortable enough margin. if the input protection fails then I have not backup plan Your only back-up plan is diligence - have you got a comfortable enough margin. I mean; if you don't simulate and get a feel for things then you have no idea whether the protection you fit is anything like suitable so, do the right thing and model each threat in terms of voltage waveform and output impedance and model each protection device to see that you don't exceed the peak energy handling in the data sheet (and add a comfort margin of 1.5). Will the current Input stage of the Power Supply survive the Tests mentioned above ? You can be sure if your modelling and simulation suggest not, then you need to improve things. But, of course, the real test is the lab test. My surge test (EN 61000-4-5) was a pass if that gives you any confidence in things but, I probably spent two solid weeks with a simulator.
H: Components in the circuit based on admittance (in complex form) My Question I have an admittance in complex form for a circuit. Is it possible to know what components are in the circuit based on the admittance? How do I calculate it? AI: Is it possible to know what components are in the circuit based on the admittance? Unfortunately not because a single spectral point admittance value tells you nothing about what that admittance changes to at other frequencies AND you need a full spectrum of admittance (or impedance) values to make that determination. Even then, it won't tell you what the exact "black-box" circuit is; it only gives you an equivalent model.
H: Can USB 3.0 tracks be closer together than 5W if they're quite short? I am currently laying out a space constrained PCB which contains some USB 3.0 Superspeed differential pairs. These USB signals are confined to the PCB, going from a Cypress CX3 chip to a USB 3.0 Hub chip. They do not go to or come from a connector. The signals are approximately 30mm long from start to end. According to the advice, the Superspeed pairs should be separated from each other by at least 5x the differential pair spacing. (This is known as the 5W rule) Since the signals are fairly short, and do not go through a connector or cable, would it be possible to push them a little closer than 5W? Say, 4W or 3W? AI: The document you linked says this: - Does that help you? Can you place ground between or can you route on different layers separated by a ground plane? See also section 7.2 of that document.
H: How do I know which is the correct AI to connect to a system's "Synch Out" pin? I am trying to measure a square signal that I should be obtaining from the "Trigger In" (Trigger Input) and the "Ground" pins being connected to the oscilloscope. The signal we ought to be getting is not the one shown, so I was advised to connect the "Synch Out" pin (Frame Synchronisation Output) to the DAQ* AI (Analog Input). How do I know which is the correct AI "socket" to connect the "Synch Out" to? Is it as simple as just connecting a cable to this "socket"? I leave this link which might help better understand the system. *Data Acquisition System that, once the correct signal is obtained, must be connected to the 3 pins above mentioned. I have only ever studied theoretical physics before so this is a completely new field for me, if my explanation was not good enough, I can try to further explain it. AI: It's up to the computer software. A DAQ is just a way to get signals into a computer. It doesn't care what the signals are. If you are looking at a signal as a graph on your screen for example, and you look at AI 2, but your signal is hooked up to AI 1, you won't see it - for obvious reasons. If you moved the signal to AI 2 or switched the graph to display AI 1, you'd see it. So it depends on what the computer is doing. This can't be answered based on only the electronics side.
H: Is it possible to generate light with an antenna? An antenna (e.g. a dipole) is able to radiate at a certain frequency thanks to the EM field generated by a current provided by a signal generator at such a frequency. So, for instance: Voltage source at frequency f (representing an amplifier) + Antenna made of conductors = Radiation at frequency f My question is: is it possible (or, maybe will it be possible) to generate light by using a voltage source at frequency of light (480-750THz)? All light sources I've seen are realized by using mechanisms different from EM radiation, like LEDs, LASER etc. AI: Photonics is a thing, and it very much treats light as electromagnetic waves in waveguides on silicon, with mixers, delay lines, matching circuits, amplifiers etc as you'd do for a RFIC. Just as an antenna doesn't generate the signal to be transmitted, an oscillator is used to generate a carrier wave – just that the oscillator happens to be a laser diode, sometimes on the same substrate, instead of a discrete transistor, an L and a C. An antenna is just an impedance matcher between transmission line and free-space, and that's what you find on every laser diode die, standard LED die at the point where you try to convert the surface-bound or substrate-travelling lightwave into something emitted into the fiber or a lens or free space. What you definitely don't find is the classical dipole being fed with a current coming from an oscillator. That doesn't work, as most such components are comparable in size as the antenna. But, there are photonic antennas. These convert a free-space EM wave to a guided wave, just as your phone's antenna converts free-space waves to waves in a coax cable (and vice versa), while simulataneously mixing things with a lightwave. This is not an antenna in the sense of a \$\lambda/4\$-monopole or something. They are fiddly: THz Antenna coupled to a high-speed silicon plasmonic photodetector enabling opto-electronic generation and detection of waves by photomixing within a THz-bandwidth. Source: Institute of Photonics and Quantum Electronics (IPQ), Karlsruhe Institute of Technology
H: LED driver operation vs boost converter operation I am having this A80604 - LED Driver IC for driving a string of 9 LEDs. Each LED has a forward voltage drop of 3.1V and a forward current of 300mA through each LED. So, I need to generate a maximum of 30V for this LED string with forward current of 300mA. My input voltage range is 10V to 16V I tried to search in google but unable to find. I want to understand - What is the operational difference between this LED driver and a general boost converter? How does this LED driver help to output the 30V for the LED string when my input is 12V? Is its operation similar to a boost converter? I have read that for LEDs, we drive the required current through it, and then the appropriate forward voltage appears across the LED. So, does this LED driver work by producing the 300mA and the output voltage of 30V would increase/decrease according to the LED forward voltage drop? Please let me know on how an LED driver operates and how is it different and advantageous from a normal boost converter IC. AI: What is the operational difference between this LED driver and a general boost converter? There isn't much of a difference but to get a blow-by-blow absolute definitive list of differences is not going to happen because Allegro will protect their IP and they won't disclose what the bottom end of the LED string truly connects to. But, you can make certain inroads into a comparison providing you understand that IP is usually a guarded secret. Consider a fairly conventional boost converter like this one: - The important pin to fixate on is FBX (red-lined). That pin "wants" to be at 1.6 volts and so it will adjust the duty cycle of the converter so that 1.6 volts appears on FBX. This means that the current through the 15.8 kΩ resistor MUST BE 101.27 μA. And this means that the voltage across the 226 kΩ resistor is 22.89 volts. And, it therefore follows that the voltage from the top of the 226 kΩ resistor to 0 volts is 22.89 volts + 1.6 volts = 24.49 volts. And, give or take a little bit of handwaving over resistor tolerances and the tolerance on the FBX "must-be" voltage, the output is pretty much 24 volts as stated on the schematic. The important thing to note here is that whatever value the 226 kΩ resistor is, the output voltage will be manipulated (via PWM) to force a current of 101.27 μA through the lower resistor (15.8 kΩ). So, now replace the 15.8 kΩ with a 15.8 Ω resistor and the current that the chip wants to take into that resistor needs to be 1.6 volts ÷ 15.8 Ω = 101.27 mA. Now, if you replace the 226 kΩ resistor with a string of LEDs you get this schematic: - And that current that flows down those LEDs is determined by the FBX "must-be" voltage of 1.6 volts and the lower resistor (now at 15.8 Ω). So, to get 300 mA, just make the lower resistor 5.333 Ω and what you basically have achieved is a constant current LED driver. Of course, the Allegro chip has the 5.333 Ω embedded inside it and it probably isn't that value but something a lot smaller and there'll be an amplifier behind it to make the voltage up to whatever is the internal equivalent of the LT3957's FBX voltage but, essentially, it's the same bar a few bells and whistles. Also note that this analysis can apply to a buck converter too.
H: Add downloaded components to existing library in Altium? I have just started using Altium as a student after using Eagle for a lot of years. I download part libraries from sites like Ultra Librarian and can use the supplied script to generate a library with symbol, footprint and 3D body, I can then compile so I can use it in a design. But this is going to end up with me having hundreds and libraries with just one part in each. How can I create one library and import the downloaded files from Ultra Libary (and others) into that library? Bearing in mind that I have no scripting experience. Basically, I want to end up with one library for say one brand of MCUs, comm transceivers, connectors etc much like in eagle. AI: Open the various individual libraries in Altium. Open the your new target library. Right-click on the component, in the component panel list, that you want to include in your new library, and select 'Copy'. Right-click in your new library and select 'Paste' in the component list. This works for both Schematic and PCB libraries. Going from Eagle to fAultium is a big jump. Read the docs. Join the Official Altium forum ( https://forum.live.altium.com ).
H: Not visualizing signal in oscilloscope when a speaker is connected Hope you can help me with this, because I really don't understand what is happening. I have the following electronic circuit. The Arduino is generating a tone and I am changing the volume with a digital potentiometer. The problem I found is when I connect an oscilloscope to point A and GND I am able to visualize the signal 720mV with the oscilloscope. However, when I connect an 8 ohm speaker to the output I have 50mV. I can hear it though, but I would like to know what could be happening and how to solve it. Shouldn't I have the same voltage value at point A? AI: Your drawing does not show a signal ground connection back to the Arduino? Is there one? Also, an 8 ohm speaker forms the shunt leg of an attenuator. The series leg is the 100 ohm resistor plus the equivalent resistance of the digital pot. The signal might be attenuated so much that it is below the quantizing level of the scope. Can you increase the scope's vertical channel gain? Starting with the signal level at the Arduino output pin, you can calculate the Thevenin equivalent voltage and impedance at the wiper of the digital pot. This now is the signal source going into the 100 ohm resistor. With Ohm's Law you can calculate the voltage across the 8 ohm speaker. Note - the Thevenin equivalent values will change depending on the wiper position in the digital pot. To see the full effect of this, run the calculations three times, with wiper positions of 10%, 50%, and 80%.
H: Why is this buffered rail splitter oscillating and how can I compensate it? Inspired by the question Op amp Power supply splitter with totem pole I played with the buffered rail splitter in LTspice. I placed a current sink as load on the output to simulate the current sourcing and sinking of a connected amplifier with 100mA amplitude and 50Hz. The output is stable to 20µV, so everything is fine (Fig 1). But when I increase the size from the bypass caps C1 and C2 at output (as one would do to bypass the supply on succeeding amplifier stages) the whole circuit starts to oscillate (Fig 2). For the screenshot I used values of 100u for C1 and C2, but even with 100n the circuit is already oscillating. What is the reason for this oscillation with some capacitance between the new ground and the symmetrical supply rails? I would have assumed these caps would even increase the stability, as the feedback to U1 is now somewhat low pass filtered. Can I compensate for that behaviour? How? Fig. 1: Stable buffered rail splitter Fig. 2: Oscillating rail splitter with bypass capacitors AI: What is the reason for this oscillation with some capacitance between the new ground and the symmetrical supply rails? I would have assumed these caps would even increase the stability, as the feedback to U1 is now somewhat low pass filtered. Just because you have buffered the op-amp with an emitter follower push-pull circuit does not mean you have somehow isolated the op-amp from oscillating when you close the feedback loop. Pretty much any op-amp will sing its little heart out when the loading capacitance rises to a certain value and might only stop singing when the capacitance has risen to an unfeasibly and not useful large value of thousands of micro farads. Can I compensate for that behaviour? How? You can stop it by slugging the op-amp response with a local integration capacitor from op-amp output to inverting input but, make sure you use a 1 kΩ to 10 kΩ resistor to connect the inverting input to the emitter follower output. My answer to this question contains a detailed breakdown of why an op-amp (buffered or not) will sing when capacitance rises to a certain small value and why it won't stop oscillating until the loading capacitance reaches a much, much higher value.
H: Decoupling caps not near IC pins - global decoupling It is common wisdom that decoupling caps should be near the IC drawing power, minimizing loop inductance. For some time, I have seen that Todd Hubing advocates what he calls global decoupling in some of the youtube examples they have for LearnEMC, if the board has a tightly spaced power and ground plane pair. The rationale is, that - with tightly spaced power and ground planes - the inductance of the plane pair is anyway smaller then interconnect traces. So if the decoupling caps lowest impedance path is through the plane pair anyway, then it doesn't matter that much where on the plane the decoupling cap is placed. Here is one example screenshot from that video which illustrates the placement of the global decoupling caps. As a result they advocate, just sprinkling the board with a sufficient number of decoupling caps. Yesterday, Altium posted a new youtube video with Todd Hubing where he also explains this approach. It sounds quite plausible. However, I do not recall seeing this school of thought anywhere else and most designs do have the decoupling caps very close to ICs, although I suppose most designs on 4+ layer board do have tightly spaced power and ground areas. As Todd Hubing mentions, caps near the ICs can actually make the situation worse because routing can be more congested when caps are very close to ICs. So I was interested if there are problems with global decoupling unmentioned by Todd Hunting, that explain why it is not used more often. AI: This is true IF the power and ground planes are tightly coupled. What do you get with two copper planes very close together but not touching? A capacitor. And yes, since the power/ground vias can drop right from the pins to the respective plane, the inductive loop is much smaller making that capacitance much more effective at higher frequencies where small capacitors have trouble. You will however still need larger “bulk” capacitors (typically 10uF) around the ICs. These capacitors offset the resistance of the switching current path back to the power supply. They can already tolerate a bit more inductance as they target the lower switching frequency currents of the IC and don’t need to be right on the pins and can me optimized with lower priority than the signal trace fan-out from the IC. Why isn’t this used more often? It requires significant space on two PCB layers that cannot be split with a routing trace through them. Splitting the trace will result in loop currents again introducing inductance again and radiated emissions. It requires two planes of the board around the IC. Not a problem if you have an expensive 8 or 12 layer PCB design. Go nuts :) Many complex ICs require multiple power supplies. Each supply will require its own power/ground plane around the IC which eats up more valuable routing planes around the IC. Again, not an issue on designs with large number of PCB layers. To keep costs down, the goal is often to reduce the number of layers in the PCB. If this can be done with optimized placement of decoupling capacitors, the cost will be less than introducing more layers into the board. It all really comes down to trading off design time, complexity, and cost. The main point is that you need to evaluate your PCB power and ground along with your decoupling capacitors to effectively determine the impedance of the power distribution network. From there you can determine if it meets the requirements for the switching current frequencies of that particular IC.
H: Why does the current enter the negative terminal of this element and it is still absorbing power? Hi there, I am learning the kirchhoffs-laws, according to the passive sign convention if a positive current enter through the positive terminal of an element and exits out of its negative terminal, then the element is dissipating power. So, in this diagram the current enter through the negative terminal element with 3 ohms resistance. The calculation shows that the voltage across it is the same sign as the voltage across the 2 ohms resistor. Why do they have the same voltage sign although the current enter through different polarity of terminal, is there any element that has such properties in real life? AI: Resistors aren't polarised. The positive and negative are simply labels, and someone has written the v2 labels the wrong way up. Alternatively, this is a homework question asking for a negative value for v2. If you put the negative lead of a voltmeter to the -v2 and the positive lead to +v2, you will read a negative vale on the voltmeter. If you swap the leads you read a positive value.
H: Dithering Modulation Frequency and Dithering Rate I have a question regarding dithering. I was reading this Application note and under section 4.1 page 5,they have given below, I understand that we perform dithering in the DC-DC Switching converters to reduce the emission magnitude at the switching frequency and spread it across different harmonics. In doing so, we would get a maximum switching frequency and a minimum switching frequency. In the above case, they have mentioned as 72kHz and 58kHz. But what is the meaning of dithering rate of 2kHz? Can someone explain me what is the meaning of dithering rate and how that value would impact or be helpful in this scenario? AI: This is basically FM modulation of the carrier PWM frequency. The usefulness is not so much in performance with crosstalk to other tuned circuits but rather to reduce the quasi-peak amplitude of unintended radiation. Here they chose an FM BW of 10% pp approx and 2% modulation rate or an FM ratio = 10/2=5 to reduce the quasi-peak EMI possibly radiated or conduction on the AC grid. Let me see if I can simulate this from FCC or EU EMI setups for quasi-peak BW which were derived from old days of AM radio interference with an RC filter on the peak detector. It might not make much difference since 10% here is still audible if converted from FM to AM to baseband audible noise for this LF radio band which might only be 4kHz. In PC BIOS setups some have spread-spectrum options to do the same on bus clocks used for CPU clock for the same reason but in higher Radio bands.
H: Device RF input calibration setup A device requires RF input calibration. The input signal specification is: CW, 60MHz, 0.0 dBm. The user manual recommends setup 1 (fig below). Provided that the Signal Generator is capable of outputting the specified signal, what would be the advantage of using setup 1 instead of 2? Edit #1 Calibration The calibration rational is to insert a known signal into the device (inputPOW), read the input level (readPOW) and evaluate an offset as follows: inputPOW == readPOW + offset. AI: Usually they insert RF attenuators in the signal chain to avoid issues with reflected signal from the DUT. In the second case the generator outputs 0dBm straights to the device, in the first one it only needs -10dBm (and maybe with better signal quality) with the attenuators to isolate the stages. Other than that if it's only to evaluate signal strength I don't see advantages in the first setup other than better reflection protection.
H: No response from 2 working spi devices when they are stacked I have two identical SPI devices but each off them is on a separate board, they are connected via a header that allows the board to be "stacked" on top of the master controller. the signal will pass through two ICs before it reaches the slave device, a signal mux SN74CBTLV3257 and a digital isolator ISO7741. Here is the schematic. I have already confirmed that each of the circuit works perfectly fine when it is alone. The problem lies when both of them are stacked, i can confirm that each slave device has received my spi transaction as i can visually see that it is doing what im telling it to. Supposedly the slave will send a response back but i am not getting any. With a bit of tinkering around the circuit i have concluded that the signal from the slave device is not making it back to the controller. In the schematic above i tried probing testpoint A and testpoint B with my logic analyzer and this is what i got. at point B the correct signal is still there ( i checked that it is indeed the correct response to what i sent), at point A the signal seems very noisy, an lastly at MISO (directly on the master controller pin) it doesnt see anything. The only explination i can think of is something between the two ICs are interfering with each other preventing the signal to be pulled high/low. But i could not make out why it is interfering with each other. The mux is able to handle bi directional signal so it should be it, It might be the isolator, when the other isolator pulls low the two muxes somewhat forms a voltage divider with isolator 1 Dout outputing 3.3v and isolator 2 Dout trying to pull it to 0v, and assuming both muxes has same resistance the controller would essentially be seeing 1/2 of 3.3v. I have no idea if that sounds correct though but it would be hard to test without an oscilloscope. Can anybody help me with what might be happening and how to resolve it? AI: Both muxes and isolators are always enabled. So the isolator data out to MCU MISO are both enabled and driving the same node. Neither the mux or the isolator are controlled to avoid this.
H: Optocoupler design - why does this circuit work? I am busy with some calculations regarding the components around the optocoupler and I am now finding myself in a bit of a mental struggle. I have done quite a lot of reading (at least here, here, here, this Vishay guide, this Toshiba guide and this Avago guide to name a few) and I still find myself unable to answer a few questions. The more I try to figure out the correct math, I just end up with more questions that need answers. The application for this circuit is to isolate signals from mechanical switches on one power network (supply voltage of 5 V) to the inputs of a port expander IC on another power network. The optocoupler used in the design is the TLP621-4. This is the circuit in question: Firstly, there is the input stage of the optocoupler. Designing for that seems to be rather straight forward – choose a suitable current to drive the LED at in order to switch on the phototransistor so that the correct logic voltage can appear at the pins of the port expander. The port expander runs at a supply voltage of 3.3 V, so the switch signals will also be translated/shifted to 3.3 V signals. Choosing a forward current of 5 mA corresponds to a \$V_f\$ of approx. 1.2 V at 25 °C, according to the datasheet. For the LED this yields: \$R_{LED} = \frac{V_{supply} – V_f}{I_f} = \frac{5 – 1.2}{0.005} = 760 \Omega\$. According to the optocoupler datasheet, \$I_f\$ = 5 mA corresponds to a CTR of 120%. Thus, the collector current \$I_C\$ = 5 mA \$\times\$ 120% = 6 mA. Now here comes my question – how do I design for the output stage of the optocoupler? If I want to convert the collector current to a voltage at the emitter so that the port expander can detect a logic HIGH/LOW, for what collector current and pull-down resistor values do I design? Below follows the circuit as I have built it for testing purposes - it works. However, it is all nice that it works perfectly for this application so far, but it bothers me WHY it works: The LED current limiting resistor value is 10 kΩ, which yields a forward current of only \$I_f\$ = (5 – 1.2) / 10000 = 380 \$\mu\$A. The CTR curve in the optocoupler datasheet starts at approx. 75% at 1 mA, so the true CTR is probably below 70%. This yields a theoretical collector current of approx. \$I_C\$ = 380 \$\mu\$A x 70% = 266 \$\mu\$A. Furthermore, the pull-down resistor value at the output stage of the optocoupler is also 10 kΩ. Where does the collector-emitter voltage \$V_{CE}\$ come into play? If the output stage supply voltage is 3.3 V and the desired logic HIGH at the emitter is also 3.3 V, then this means that \$V_{CE}\$ must be 0 V - is this possible? If so, what do the various \$V_{CE}\$ - \$I_f\$ and \$I_C\$ - \$V_{CE}\$ curves in the datasheet mean? I would appreciate it if someone could shed light on why the above circuit works and what the corresponding parameters are. Also, if the above design is not optimal, what would the correct approach be to designing the circuit for the mentioned desired specifications? AI: A few notes: CTR is only rarely a guaranteed value that you can use for accurate linear isolated measurements. In the case of the TLP621-4, the datasheet only guarantees that it's somewhere between 50% and 600%. I'm not sure where your 120% number came from. Even the graph on page 8 doesn't show 120% at 5 mA, and it has multiple very different lines from different sample devices besides. That CTR curve (page 8) also shows CTRs down to 300 μA, so I'm not sure what datasheet you're looking at but it's not the one on the page you linked to. This optocoupler is specifically marketed, and thus probably designed, as a solid-state relay, only intended to be used as a switch and not as an amplifier or analog isolator. You won't be able to achieve a \$V_{CE}\$ of zero, as the output transistor still has a \$V_{CE,sat}\$ like any bipolar transistor. This doesn't matter, however, because there's a fair margin on what most logic chips and microcontroller inputs will accept as a logical high. It should say in the datasheet what that is, likely labelled as \$V_{IH}\$ (for voltage, input high). What value you use for the output resistance also shouldn't matter, as long as it's high enough to allow the transistor to fully saturate, and low enough to reliably act as a pull-down on the logic input. When the transistor is saturated, CTR goes out the window, just like how β is useless in a standard BJT in saturation. The way I would design this circuit is to have the LED run at a reasonable middle-of-the-range current, to ensure that the output transistor saturates regardless of what the CTR is. Since they guarantee the CTR to be at least 50% with a forward current of 5 mA, that's the condition I'd design for: 5 mA input, and 2.5 mA output. So choose your input resistor to give 5 mA through the LED. Then, you need to select your output resistor. You are guaranteed that the output current will be at least 2.5 mA if you have no resistance in there at all. But we don't want that--we want to ensure that the transistor is saturated. So we use a resistance that, in combination with the transistor's \$V_{CE,sat}\$ (max 0.4 volts according to the datasheet), results in, let's say 2 mA current on the output. Now, regardless of what the device's actual CTR is, you'll see an output current of approximately 2 mA through the resistor, and an output voltage of between 2.9 and 3.3 volts (depending on what the device's actual \$V_{CE,sat}\$ is). This is a voltage high enough for any 3.3 volt logic input I've ever worked with (and many, if not most, 5 V logic inputs too) to read it as a reliable high. To answer your questions in the comments: If the saturation voltage is a fixed value, then how does increasing (or decreasing) the resistor value not have an influence on \$V_O\$? Does the collector current compensate for the change in resistance, or am I missing something? Yes, the collector current will reduce. One (oversimplified!) way to think of it is that (for complicated reasons relating to the way transistors work), it's not possible for there to be current through the transistor with \$V_{CE} < V_{CE,sat}\$. Another intuition is to think of it this way: With the transistor powered from a 3.3 volt supply, with a 1 kΩ resistor in series with it, could that transistor possibly drive 10 mA through that resistor? That would make 10 volts across the resistor--but you only have 3.3 volts to work with! Clearly, it can't drive that much current, even if the CTR or β says that it should--this is when the transistor saturates. Perhaps a follow-up question - what design condition drives the phototransistor into saturation in the first place? In other words, what are the design parameters to ensure that the phototransistor is in saturation? An easy way to do it is as follows: Either in a real circuit or in simulation (including manual circuit-solving as simulation, here), connect the collector to your supply voltage, and the emitter to ground. No resistors or anything. Apply your designed current through the optocoupler's LED. Measure or compute the current through the transistor. Figure out a resistance that would produce that same current given that same supply voltage across it. That resistance is (slightly higher than; we didn't account for saturation voltage) the minimum resistance required such that your transistor is in saturation. If you use a larger resistance, you will have less current, but still the same output voltage. If you choose a lower resistance, you will have the same current, and a lower output voltage.
H: PNP and NPN H-Bridge - Drive PNP from opposite output To drive the PNP transistors on an H-bridge circuit, the control voltage needs to be at least the input voltage, or a secondary stage is driving the high-side PNPs. I have come across a circuit that uses the output of the opposite switch to drive the PNP transistors. This circuit exists, and I measured it, and it behaves well. In this case, VDC=30V and Vctl=5V. Vctl is a square wave (approx. 300Hz with a short dead-time between "on" ~100us), like so: Component values are measured; but transistors are unmarked, so I used generic ones. The circuit works well with clean switching at Aout and Bout. So far so good. I've tried to make such a circuit in LTspice, but it isn't so well behaved. During the dead-time at the input, both Aout and Bout should be 32V, meaning 0V difference from how I see it. However, LTspice shows me a voltage dip during the dead-time and a current spike on the input line: Indeed, building this circuit results in comparable behavior (a dip on both sides), and the transistors get warm (input in this case is current limited), meaning they don't fully turn off. Now, clearly I'm making wrong assumptions, so why does this not work and what is the trick to making this work? AI: Consider this as the starting scenario: - Q2 is on and Q4 was off, Q3 would be activated (due to Q2) and this forces Q1 to be off. It remains like this for some time. Then, just imagine Q2 was turned off - ask yourself what will cause Q3 to turn off. With Q2 off, Q3's miller capacitance would remain charged and keep Q3 on for some length of time. How long might that length of time be you might ask. Well, the 10 kΩ resistor feeding Q3 (R8) is not being pulled low by Q2 any more; its kind of floating on the non-base side of Q3. This creates a long and hard to define CR time with the miller capacitance of Q3; in effect, the base of Q3 is now open circuit because R8 isn't connecting to anything substantial. You might put some number on what that leakage impedance is and, you might choose to look at the 2N2222 data sheet to see if there are any clues. You'd find that in this data sheet the collector leakage current is 10 nA on a 50 volt supply. That pull-down current will be pulled-up by the leakage current of Q1 (the 2N2907) - it has a collector leakage current of 50 nA. So the net pull-up current is about 40 nA and it is that current that is attempting to discharge the miller capacitance of Q3 and drag Q3's base up towards 30 volts. So, using this well-known formula for a capacitor: - $$I = C\dfrac{dv}{dt}$$ We can calculate dv/dt based on the 40 nA and the miller capacitance for Q3 of 8 pF but, that transistor also has a base-emitter capacitance that needs to be discharged of 30 pF. In effect we might be looking at trying to discharge about 40 pF with 40 nA and that means a dv/dt of 1000 volts per second or 1 volt per millisecond. So, once Q2 turns off it's collector voltage will rise (with a bit of hand-waving) at a rate of 1 volt per millisecond and it will take probably another 29 milliseconds for it to rise enough (from 0 volts to 29 volts) for Q3 to show signs of being deprived of significant base current. Until this happens you will get a significant shoot-through current should Q4 be activated. a short dead-time between "on" ~100us That's a lot shorter than my analysis requires it to be so... Solution: add base-to-30V-rail resistors on the two PNP transistors - maybe 10k will do but, the lower the better really. 10k implies a discharge current of a few tens of microamp and that's a helluva lot better than 40 nA.
H: Dithering Circuit using an Op-amp I am reading and trying to understand this Application note from TI on how the dithering circuit works. I can deduce that the Op-amp acts as a schmitt trigger but there's no details on how the frequency change is effected. Can someone help me with the working of the circuit on how the frequency change is effected with the schmitt trigger? And also, can someone explain how is the calculation obtained? Why is the 7kHz/65kH multiplied with the 45uA current? AI: What they are saying is that to make the UC28180 dither its operating frequency there is an external 2 kHz triangle wave generator (below) that is attached to the FREQ pin: - And, because the operating frequency is set by the current out of the FREQ pin, the dithering oscillator can modulate this by taking, in effect an AC current from the FREQ pin. The main central oscillation frequency (65 kHz) is set by RT but, if a little current is taken and put back through the 100 kΩ resistor then the main chip's oscillation frequency will "dither". To set the basic 65 kHz operating frequency, RT must draw 45.87 μA and, to make this 7 kHz higher or lower, a current of plus or minus 4.94 μA must be taken through the 100 kΩ resistor. That current is: - $$ \pm 45.87\text{ } \mu A \times\dfrac{7}{65} = \pm 4.9398\text{ } \mu A$$
H: What is the difference between "Storage Temp", "Ambient Temp" and "Operating Temp" mean? To my understanding, ambient temperature is the temperature of the surrounding area while the unit being worked on is powered. While operating temperature is the temperature of the unit itself under heat and power. I have seen many different explanations online, and most seem to contradict themselves. If the operating temperature of a unit has a maximum of 100°C, then does that mean the chip/components inside the unit can only operate at a max of 100°C? So that should be taken into consideration when adjusting the temperature of the oven. If so, is the only difference between ambient temperature and storage temperature that there is power being delivered to the unit? AI: Generally the "Operating Temperature" is listed as a MAXIMUM or a range. That means you should not operate the equipment or device outside those bounds or you risk damage or the device not performing according to specs. In my opinion "Ambient" is the same although different manufacturers may have different definitions for this. Here it pays to read their documentation carefully if you are going to be approaching these limits. "Storage Temp." is also often given as a range and states the limits at which the device or equipment should be stored. Outside that range may cause damage.
H: Connecting a single end stop to two circuits I currently have a garage door opener that has its own controller. One of its inputs supports a mechanical end stop, so it can know when it's done opening. I'm in the process of adding a very simple circuit (based on a Sonoff, en ESP8266) to be able to control the garage door opener using WiFi. As it's now, I'm triggering the manual "open button" using the relay in the sonoff. It works great, but I'd like to also connect the endstop, so my controller also knows when the door finished opening. As I understand it, I can't directly plug both circuits to the same endstop, as they use different voltage sources. So my question is: How can I easily "mirror" the endstop, or isolate it somehow, so both circuits can use it? (adding a secondary endstop is not an option right now, nor is it replacing the main garage door circuit). AI: Probably the simplest practical way is to use a relay that has isolated output contacts for circuit A and circuit B. Use the original end-stop switch to activate the relay from a simple power supply such as 12 volts DC. This would need a 12 volt relay.
H: Does different bulbs in one circuit lead to shorter lifespan? I had a conversation with my family regarding lifespans of bulbs. They claimed that they had observed that when different wattage bulbs are plugged in the same hanging light, the bulbs would die sooner. Specifically, they noticed that in a 3-way arrangement with one bulb of different wattage, that one lamp would be the first to die. That could also be the case in different arrangements. I didn't believe them and I put it down to the quality of the lamps tested, since none of the physics or maths I know would explain it. However, I cannot test the theory because it would take too much time and (electrical) energy. Am I missing something? Is it possible that the bulbs would die sooner if connected in the fashion described? Could some malfunction of the hanging light be the cause? Necessary info: I live in Europe so the mains voltage is 230V/50Hz AC and, given that the rest of the bulbs would stay on, the lamps are wired in parallel. The bulbs were probably incandescent bulbs. I am asking because I am going to change some dead bulbs so hopefully the answers will help me on whether I have to make sure that the new LED lamps have the same wattage as the old or the other ones. If I don't have to, I might as well use some bulbs I have lying around. I know those are a lot of questions so Thanks a lot! P.S.: I did search the web and only found this but it doesn't cover anything about the lifespan of the bulbs. Also, if this is not the correct site, notify me of the right one. AI: All three lamps will have identical supply voltage as they are in the one fixture. They don't know about each other and each will draw the current they require based on their individual resistances. Their lifespan will be the same as if they were in separate rooms of the house unless there is an additional factor such as excessive temperature due to the three bulbs being in the one enclosure, etc.
H: Are fluorescent tubes dangerous? I'm disassembling a Sega GameGear. The capacitors inside are all rated 50v or lower, so it shouldn't be hazardous in that regard (I will discharge them anyway just to be sure). However, the metal plate that covers the fluorescent tube of the screen, has a big "CAUTION: HIGH VOLTAGE" on it. Does it refer to the voltage of the capacitors nearby just to be precautios? Or is the actual tube under the plate dangerous? Does it store high voltage like a capacitor? Should it be discharged in some way before being touched? AI: You can safely disassemble the unit without risk of shock, so long as the power supply is disabled or removed. The shield is there to isolate the CCFL operating voltage while the CCFL is on (it's also the backlight reflector / baffle.) The CCFL voltage can be quite high - hundreds of volts - so safety rules mandate that separation from the low-voltage parts of your system. When the CCFL is off, both ends are essentially ground (one end actual ground, the other the inverter's transformer secondary coil, then to ground), so the CCFL would not tend to store charge by itself.
H: Problem or misunderstand of ADATE bit on ATTiny45 I have 2 buttons connected to pulled-down ADC input. I want to trigger ISR(SIG_ADC) when ADC finishes conversion - this is working. If I start ADC using ADCSRA \|= _BV(ADSC), this works OK; I want ADC to start conversion automatically when there is HIGH edge on PB3. I suppose ADCSRA[ADATE] bit is responsible for this, but I can not make it work. Buttons are connected this way (buttons can not be mechanically pressed simultaneously, so, R3 = 0 is OK) Chip is ATTiny45. # # # # # # # # # # # # # # # # # # # # # # # # # 20kΩ # # GND >---------------- R1 --------> PB3 # # \| # # \| # # (S1) 10KΩ \| # # ----.\_---- R2 ----* # # \| \| # # \| \| # # \| (S2) 0Ω \| # # ----.\_---- R3 ---- # # \| # # Vcc >----* # # # # # # # # # # # # # # # # # # # # # # # # # I assume that ADATE should trigger conversion start when it's +2v on PB3, because ADCSRB \|= _BV(ADTS1) \| _BV(ADTS2); is set to Pin Change Interrupt Request value. And after conversion complete, ISR(SIG_ADC) will be triggered. When I run ADCSRA \|= _BV(ADSC) in main() loop, everything works as expected: PWM signal represents ADC value. When I comment this line, everything doesnt work, but I expect HIGH edge should trigger ADC and ADC should start conversion, and after some time it will fire ISR(SIG_ADC). I can override this behavior attaching pin change interrupt to PB3 and running ADCSRA \|= _BV(ADSC) from this interrupt, but I think that's wrong to attach both pin change interrupt and ADC to the same pin, I'd like ADC to auto-trigger on pin change. Where is my mistake? inline void setupPwm() { // Enable PLL _SFR_BYTE(PLLCSR) \|= _BV(PLLE); // Wait for PLL to lock _delay_us(100); while (!(PLLCSR & _BV(PLOCK))); // Enable PCK clock on Timer1 _SFR_BYTE(PLLCSR) \|= _BV(PCKE); // Enable PWM _SFR_BYTE(TCCR1) = _BV(COM1A0) \| _BV(COM1A1) \| _BV(PWM1A) \| MOTOR_SPEED_SLOW; _SFR_BYTE(OCR1A) = 0x00; _SFR_BYTE(OCR1C) = 0xFF; _SFR_BYTE(TCNT1) = 0x00; _SFR_BYTE(DDRB) \|= _BV(PINB1); } inline void SetupAdc() { // Disable unnecessary data inputs // REF: 17.13.5 DIDR0 – Digital Input Disable Register 0 // [5:2] = 1101 (ADC0D and ADC2D and ADC1D) => Disable ADC0, ADC1, ADC2. // NOTE: Bit order is irregular _SFR_BYTE(DIDR0) \|= _BV(ADC0D) \| _BV(ADC1D) \| _BV(ADC2D); // Set ADC for PB3 (ADC3) button input. // REF: 17.13.1 ADMUX – ADC Multiplexer Selection Register // [7:6],4 = 0 (REFS0..3) => VCC used as Voltage Reference, disconnected from PB0 (AREF). // [5] = 1 (ADLAR) => Right\Left Adjust (1 = Left, means ADCH contains [10:2] of ADC value and ADCL contains [7:8] as [1:0] of ADC value) // [3:0] = 0011 (MUX0..3) => ADC3 (PB3) _SFR_BYTE(ADMUX) \|= _BV(MUX0) \| _BV(MUX1) \| _BV(ADLAR); // Setup ADC // REF: 17.13.2 ADCSRA – ADC Control and Status Register A // [7] = 1 (ADEN) => Enable ADC // [6] = 0 (ADSC) => ADC Start Conversion // [5] = 1 (ADATE) => ADC Auto Trigger Enable // [4] = 0 (ADIF) => ADC Interrupt Flag // Set by HW // [3] = 1 (ADIE) => ADC Interrupt Enable // [2:0] = 0b111 (ADPS0..3) => ADC Prescaler Select Bits (0b111 => 1/128) _SFR_BYTE(ADCSRA) \|= _BV(ADEN) \| _BV(ADATE) \| _BV(ADIE) \| _BV(ADPS0) \| _BV(ADPS1) \| _BV(ADPS2); //REF: 17.13.4 ADCSRB – ADC Control and Status Register B // [7] = 0 (BIN) => Bipolar Input Mode (0 = disabled) // [5] = 0 (IPR) => Input Polarity Reversal (0 = disabled) // [2:0] = 0b000 (ADTS0..2) => ADC Auto Trigger Source _SFR_BYTE(ADCSRB) \|= _BV(ADTS1) \| _BV(ADTS2); // Enable external interrupts // REF: 9.3.2 GIMSK – General Interrupt Mask Register // [6] = 0 (INT0) => External Interrupt Request 0 Enable (0 = disable) // [5] = 1 (PCIE) => Pin Change Interrupt Enable (1 = enable) _SFR_BYTE(GIMSK) \|= _BV(PCIE); // Globally enable interrupts // REF: 4.4.1 SREG – AVR Status Register // [7] = 1 (I) => Global Interrupt Enable _SFR_BYTE(SREG) \|= _BV(SREG_I); } ISR(SIG_ADC) { _SFR_BYTE(OCR1A) = _SFR_BYTE(ADCH); } int main() { setupPwm(); SetupAdc(); _SFR_BYTE(OCR1A) = 0x7F; while(true){ _SFR_BYTE(ADCSRA) \|= _BV(ADSC); // THIS LINE }; } AI: You have selected the pin change interrupt as the ADC trigger source, but there is no code to configure pin change interrupts. So since nothing can trigger pin change interrupts, the ADC never triggers.
H: Using VBUS instead of the USB port to power a MCU I'm using an EK-TMC123GXL, for now powering it from the PC. I have found some problems with some pins (ADC, PWM) that doesn't arise if I power it up applying 3.3V to its VBUS pin instead of connecting it to my PC. However, in its user manual (part 1.5) I have read that apparently the only way to power it up is through either of the two USB ports it has, specifically 4.75 to 5.25 V. As explained above, I have been using it by aplying 3.3V to the VBUS pin, can this damage the board? How can it work with only 3.3V if the minimum stated is 4.75? What I have investigated I have seen the schematics and the VBUS pin is connected to a 3.3V regulator. The name of the regulator, according to the schematics, is TPS73633DRB, which I haven't found. I have found this one though TPS763, which matches the beginning of the reference in the schematics. Below in the datasheet, I have found that the model TPS76333 has an output of 3.3V, so I suspect this is the regultor my board is using. Don't understand very well the schematics reference. The thing is that this voltage regulator, according to the datasheet, admits a maximum input voltage of 10V (part 7, Absolute Maximum Ratings). Then, can I power up my board with a 9V battery safely? AI: Applying 3.3V to the regulator input will likely result in an unregulated output of <3.3V (3.1 to 2.7V based on power draw up to 150 mA) Its not a perfect pass through. And while the regulator accepts up to 10V, you need to consider the voltage rating for anything else in the path, mainly capacitors, or in this case other ICs, or the LEDs. And voltage drop in heat across the linear regulator. A higher VIN leads to a higher wasted heat. If you want to use a 9V then you'll need an additional regulator for 9V to 5V. If you skip 5V/VBus and apply a regulated 3.3V at the 3.3V input then the device side would be fine, the debug side unused and the 3 leds will not be powered. Specifically though, you can apply 5V through the USB port without using a computer. It can be with an adapter cable, a USB power supply, or a USB power bank (some have auto-shutdown features which make them annoying to use with low current applications). The USB VBUS connects to the VBUS pin via the power switch. No real electrical difference there.
H: Do pads 6,7,8 have to be connected with pad 12 in this layout? In eagle there is a line that says these have to be connected but the data sheet doesn't mention it. Here is the data sheet in case it helps https://www.mouser.com/datasheet/2/468/RPX_1_0-1903909.pdf AI: 12 is electrically connected to 6 7 8 internally. If you look at the recommended pcb layout on page 10, it has a pad but its not even connected to anything. Neither are 6 7 8. Its just for heat sinking. Eagle is showing them as connected because they are the same net. It can be ignored, once you take into account the information from the datasheet.
H: Calculating BJT Base Resistor Value The circuit below supplies 3.3V to an antenna (3.3VGreen), which then gives GNSS info to a control module (ANT_GNSS). The attached antenna is datasheet and only consumes about 10mA I'd like to be able to switch the antenna on and off to preserve power, as this application uses a battery. So I thought the circuit below would accomplish this. But I am wondering what resistor value I need at the BJT's base to bring the transistor to saturation? The transistor's datasheet is linked here datasheet. I am thinking that if h_fe is 100 @10mA (collector current) then base current needs to be at least 10mA/100 or 0.1mA to drive to saturation? Following this BJT Tutorial, but I have no practical experience. AI: Somewhere around 0.5 to 1mA is fine, forced beta of 10-20. The transistor is specified at a Ic/Ib = 10, but 20 will be fine too, especially at only 1mA Ic. So the resistor would be about (3.3V - 0.7V)/0.75mA or about 3.3K\$\Omega\$. The hFE is specified at Vce = 1.0V and you would like it to be more like 0.1V to minimize the losses in the transistor. You could also use an inexpensive logic-level p-channel MOSFET such as AO3401A which will have negligible voltage drop.
H: Why have both a Schottky Diode and a MOSFET for reverse voltage protection? I was looking at this open-source power supply circuit for an automotive CANBus device. I am wondering it would include both a Schottky Diode (D1) and a MOSFET (Q1) on the power supply line. My understanding is that both of these are to provide reverse-voltage protection. Is redundancy of two reverse-voltage devices just that, to have a failsafe? Or do these two devices have different characteristics that make it desirable to have both? Edit: Here is a link to the schematic: https://github.com/macchina/m2-hardware/blob/master/M2/Interface%20Board/Interface%20Board%20Schematic.pdf It is from the open-source Macchina M2 CAN Bus network analyzer. AI: The MOSFET/PNP circuit looks to me more like load-dump over-voltage protection, rather than reverse-polarity protection. If the input voltage rises much above the D3 zener voltage then Q2 begins to conduct, pulling the PMOS gate up towards its source and switching it off, which cuts off the output. simulate this circuit – Schematic created using CircuitLab An automotive electrical environment can be really nasty, and 'load-dump' (if you're not familiar with the term) refers to a situation where you may have a heavy load on the electrical system drawing a large current from the alternator, and then this load is suddenly switched off. The alternator takes a finite time to react, so for some period it's trying to push the same amount of power into the vehicle's electrical system as it was before - but since there's no longer that load drawing a lot of current, the voltage rises - and this voltage rise can be quite significant.
H: Full bridge rectifier - in depth explanation Most explanations of full wave bridge rectifiers start off with a diagram like the one below, and then go on about what will happen on the positive and negative cycle of the AC input voltage. This is all fine and well, but I would like to understand what goes on at a deeper level. During the positive cycle, diodes D2 and D3 will conduct, but let's stop right here: the depletion region of D2 will only be forward-biased (start to conduct) if its anode is more positive than its cathode. But for this to work, terminal 'a' would have to be at a lower voltage than D2's anode initially. I don't see any defined potential for terminal 'a' in the beginning, but with 'a' floating, how can the bridge begin to rectify? Clearly, some of my assumptions must be faulty, but I don't see it. AI: 'a' is not floating, it is connected through the load to 'b', which in turn is connected through D3 to the negative terminal of the supply. When the upper AC terminal is positive, there will be a conducting path through D2, 'a', Rl, 'b', and D3 to the lower AC (negative) terminal.
H: Why place a "Polygon Pour Cutout" area in PCB? This is a front end circuit for capture signal. The signal's highest frenquency is 20 MHz. Why place a "Polygon Pour Cutout" area in PCB? AI: Less capacitance. A ground plane underneath traces adds capacitance to those traces. It can mess with sensitive circuits. Note C58 and C56 are very low capacitance and any added capacitance along the traces they are on will throw things off.
H: Why does two-BJT transistor-based capacitance multiplier show bad performance I'm trying to understand why two-BJT transistor-based capacitance multiplier shows bad performance. The circuit (note that capacitance multipliers are bi-polar): Below are time output for usual RC circuit (in green), same RC parameters powered by BJT multiplier (in blue), same powered by op amp multiplier (in red): Basic RC elements in all above circuits are 10μF capacitor and 10k resistor. Red graph was taken from the top pin of R6, blue one from that of R32, green one from that of R1, respectively. Please ignore the circuit in the bottom left corner, it's unrelated. Emulated capacitor in op amp curcuit discharged from 10V to 1V over ~2200 secs (36 min), emulated capacitor in BJT circuit did so over ~11 secs, natural one did so over 0.22 secs. Emulation is apparently correct both in BJT and op amp performance (discharge slopes are exponential in their visible shapes). Leverages in both emulations are resistor pairs of 10 and 100k Ohms (R3-R4 with R2-R5, R24-R30 with R23-R31 respectively). Modifying hFE values of the transistors and their emitter resistors gives little effect. Note that one can enlarge emulated capacitor in both cases by decreasing R3-R4 (R24-R30) and by increasing R2-R5 (R23-R31). But why do hFE values matter so little here (200 times worse than op amp in any way)? Did I miss anything? AI: To start with, op amp U1 does nothing. Its output is coupled to the input via R3, which is useless because V4 overrides it. So the circuit devolves into this:- simulate this circuit – Schematic created using CircuitLab U2 maintains its output voltage equal to the voltage at the top of R5 without drawing significant current at its input. This 'bootstraps' the bottom of R5, reducing the voltage across it so C3 charges slower. Since R2 is connected to R5 it also gets the same voltage, causing C2 to also charge slower. Now consider what happens when you replace U2 with Q1. This has 3 undesirable characteristics that the op amp doesn't:- The Base requires significant current to produce the required Emitter current. It has an offset voltage of ~0.6V between Base and Emitter. The gain is less than 1. These flaws make it a poor substitute for the op amp. The Base current causes the capacitor to charge faster. The offset voltage and reduced gain cause the 'bootstrap' to be less effective, so the voltage at the bottom of R5 and R2 is lower causing the capacitors to charge faster.
H: Help! Why don't my connections show up on my pcb gerber files? But they show up on the Eagle layout? Below is a screenshot of my Eagle pcb layout. and below that is a screenshot of my gerber file extracted from pcbway.com As you can see none of the connections show up but they do show up if I take off the red polygon layer. But I need that layer for gnd. Is there a way to fix this? Am I exporting my gerber files wrong? AI: Most likely you have set the "Isolate" option on you ground plane to "0". Instead you should pick something larger like "0.3mm". With the isolate setting of 0, Eagle will still show the ground pour as cut away based on the DRC settings, however the Gerber files have this habit of exporting with the ground pour having no isolation.
H: Is there a way to increase space between connections and ground planes in eagle? The below picture is a screen shot from eagle. The red shade means gnd. Is there a way to increase the space between where the connection goes and the red, gnd, plane? I'm paranoid I'm going to solder over the small gaps shown and cause a short to gnd. Is it possible to increase that space? AI: This is done using the "Isolate" setting of the plane (right-click -> properties -> Isolate). The setting specifies the minimum distance from the plane fill to any other copper. Making this value larger will increase the spacing.
H: Cleaning a PCB w/ w/ Isopropyl Alcohol - What Type of Deionized Water Should I Use? I read a post on this sub-stack from seven years ago, which detailed exactly what I need to do. I will be soldering some components on a laptop PCB, and I'll be using rosin flux. Therefore, I'll be cleaning it w/ 99 percent isopropyl alcohol, which apparently, when it dries, leaves a residue behind. Thus, I'll be using the DI water to remove that residue. The only thing the post didn't mention was the type of DI water. I looked elsewhere online, and remarkably, I couldn't find an answer. I'm assuming that I'll need to use either Type I or Type II DI water, but I thought it wise to inquire. Does the type make a difference, and is there a specific brand anyone recommends for this type of work? Any help would be greatly appreciated. Thank you. AI: There is no need to wipe/clean the residue of the isopropyl alcohol. Its residue is a white-like stain, mainly around components. Maybe that is why you cannot find any references. Many times you might as well see in other products this white stain, like here, where someone asks what are those white stains: And the accepter answer: It looks like residue from cleaning more than corrosion so gently cleaning with some isopropyl alcohol should remove it, use a coffe filter but not a tissue as that can leave fibers in the board. If it is only a leftover residue it should not impact the performance of the card. Is it working as expected? Being an older GPU corrosion is possible if it was in a humid enviorment for a time but as it is a used card it is a case of you pay your money and take your chance. Make sure though it is DRY after cleaning before you power it up !!! Hope it works out for you Cheers He recommends re-cleaning the board with isopropanol, but there is no need, since the white stains will be created once again. EDIT: Ok I just read here That the white stain is not a product from isopropanol, but flux residue as you mentioned. I guess you learn things everyday. So yes, try to remove it again with isopropanol. White residue is generally a symptom of ineffective PCB cleaning. Common conductive flux residues from the soldering process can include various unreacted activators, binders, rheology components, and saponifiers. Among these are numerous iterations of acids (abietic, adipic, succinic among others), highly basic ingredients (amino compounds), and even constituents found in “soaps” such as phosphate and sulfate ions. When a cleaner does not fully dissolve all the constituents, or the cleaner is not allowed to flow off the PCB, the remaining solvent can evaporate off and leave behind residue that is either white or like water spots.
H: How to control the output current in when using a transistor as a switch? Assuming that I have the following circuit where I use a transistor as a switch: When the transistor is not active Vout will be equal to the Vcc and the current will become very high right? So if I want to add a combinatorial circuit or any other IC what should I do about that? edit: The circuit that lead me to this question: S1 simulates what happens if the IR gate is blocked, and U1 is a quadruple NAND gate IC wired to form a NOT gate. I posted this question because XMM2 is measuring extremely high currents. Is that because the simulator is ignoring the saturation limit of the phototransistor? AI: When the transistor is not active Vout will be equal to the Vcc and the current will become very high right? No, the current through the transistor and RLwill be zero. (Look at your switch equivalent. Where could the current flow to?) So if I want to add a combinatorial circuit or any other IC what should I do about that? Adding a second switch in parallel with the existing one will create OR logic. Switching on either one will power the load, RL. In the transistor circuit that means adding a second Rin and transistor.
H: Boost converter inductor selection - inductor ripple current calculation based on input current or output current? I've a question regarding the inductor selection in a boost converter. In this TI App note under Inductor Selection on page 3, it is asking to assume the inductor ripple current as a percentage of OUTPUT CURRENT. This is a general circuit of a boost converter below, In the above circuit, we can see the inductor is connected to the input voltage. So, should the inductor ripple current be calculated as a percentage of input current? Below, I have attached a snap shot from the TI App note. In the datasheet of the A80604 LED driver, on page 36, step 4c, they have calculated the inductor ripple as a percentage of the input current. Below, I have attached the snapshot from the A80604 LED Driver Datasheet. So, which one should be followed? Inductor ripple current based on input current or output current? Similarly, for the boost converter forward diode (shown in the above image,) the forward current (need to calculate for the diode power dissipation) would be the output current of the boost converter only, right? It cannot be the input current, right? AI: The inductor value when we talk about a switching cell affects numerous parameters in the converter. Among those that I think of, we have: the input current ripple: in a boost converter, the input current is that of the inductor. We say it is a smooth non-pulsating current while the output current is highly pulsating. The higher the inductor, and the smaller the input ac ripple will be. The lower the ac ripple, the best iron losses in the core as the BH minor loop dynamics is reduced (unlike in discontinuous conduction mode where it is the highest). a small input ripple obviously helps for designing the front-end filter and the burden on the filtering capacitor will be less with a boost than with a buck converter for instance (highly-pulsating input current, like a buck-boost). unfortunately, if shooting for a low input ripple is a possible choice, having a large inductor clearly hampers the converter's reaction time. An inductor naturally opposes current variation so do not expect a fast converter if you have a large inductor, pushing operations in deep continuous conduction mode (CCM). The boost converter being an indirect-energy-transfer type of converter, the delay in the conversion process is modeled as a right-half-plane zero (RHPZ). And you can't reasonably select a crossover frequency higher than 30% of the lowest RHPZ position. finally, a low ac ripple implies smaller circulating rms current and less stress on the filtering capacitors. This is true for the input caps in a boost structure and for a buck output capacitor. In both cases, the inductor smooths the circulating input (boost) and output (buck) currents. All the ohmic paths benefit from this lower ripple such as the power MOSFET for instance. As a preliminary conclusion, designing the inductor goes through an iterative process building on the above remarks. But as you have to start from somewhere, I have given a design formula in my book on switching power supplies based on the following inductor waveforms: The formula is here: \$L=\frac{\eta V_{in}^2D}{\delta I_rF_{sw}P_{out}}\$ So if you start with a ripple percentage (it peaks at \$\frac{V_{in}}{2}\$), think about the points I highlighted. When I started looking at designs 35 years ago, people were suggesting 10% of the output current for the design of the inductor in a buck for instance. Considering the progress in core materials, the ripple selection nowadays is more between 30-40% of the output current: the inductor is smaller, it has less dc losses, the ac core losses are less of a problem. Good luck with your design!
H: Constant Gain-Bandwidth product in amplifiers Can somebody explain to me how the gain-bandwidth product is constant in an amplifier or op-amp? I want to know the mathematical expression behind it if possible. As said here: https://en.wikipedia.org/wiki/Gain%E2%80%93bandwidth_product AI: can somebody explain to me how the gain and bandwidth product is constant in an amplifier or OP AMP ? Just look at the open loop gain of a typical op-amp: - Mathematically this happens because an op-amp internally is equivalent to a DC gain stage with high gain followed by a single order low pass filter and, as we know with a single order low pass filter, the amplitude reduces above the 3 dB point at a rate proportional to frequency i.e. ten times the frequency means one-tenth the amplitude. It's all embodied in a simple RC low-pass filter when we move beyond the cut-off frequency. An RC low pass filter has a transfer function of: - $$\dfrac{1}{1+j\omega RC}$$ And, when you get beyond the cut-off frequency the transfer function becomes asymptotic with \$\dfrac{1}{j\omega RC}\$ hence, gain is inversely proportional to frequency. That slope has a constant gain-bandwidth product.
H: Voltage ramp with split power supply I want to create an controllable output voltage from -2.5 to +2.5 on the R8 resistor. My circuit is: simulate this circuit – Schematic created using CircuitLab So my microcontroller controls the DAC, which outputs from 5V to 0V. This output goes to Differential amplifier (AMP2), which should give me max: 2.5V-0 = +2.5V and min: 2.5V-5V = -2.5V Across the R8 Did I use the reference voltages (VGND and GND) correct? I have a slight confusion: Will the AMP2 see the 5V from the DAC as 5V and subtract it? Or it will see the 5V from DAC as 2.5V? I think, because DAC is connected to GND (and not VGND) , the AMP2 will see the 5V from the DAC AI: I simulated my circuit, and even though I did not put a DAC, I think its pretty accurate simulation: My output (on R8) goes to -2.5V as I wanted it to be. And on +2.5V as I want it to be. I also figured out I do not need the AMP2 (The differencial op amp). I can have +2.5 and -2.5 directly from DAC:
H: What is the "collector light current" of a phototransistor and how does it relate to the collector current? I found the "collector light current" term in this datasheet (Vishay TEFT4300) but I can't find a definition for it on the internet nor figure out how it relates to the collector current. I am particularly interested in this graph below: AI: "I'm interested in estimating Ic based on the Irradiance I calculated (~0.5mW/cm^2)" Ic mainly depends on: How precise is the estimated value (mW/cm^2) or what is expected range The value of the resistor connected to the collector (Rc) The DC voltage source connected to the collector resistor (Vcc) Assuming Vcc is given by your circuit, by increasing the Rc the operating point will move towards the origin (lower Ic and Vce), eventually leaving the active region and entering the saturation. You could use the current for the active region on the graph as a lower estimate for saturation: Example 1: Vcc = 5V, Ic (graph) = 130uA -> Rc = 38.4kOhm This resistor would result in Vce = 0V (if that was possible), so you know the transistor left the active region and entered the saturation. The larger the resistor, the more you force it into saturation but the "dark current" would also limit this increase (since it would avoid the transistor turning off: Vce ~= Vcc). Conversely, lower values will move the transistor into the active region, but this operating point would vary with temperature, for each different device you use and the real mW/cm^2. Example 2: Vce = 2.5V (Vcc/2), Ic (graph) = 130uA -> Rc = 19.2kOhm E.g., if the real mW/cm^2 is 1.0 instead of 0.5, the transistor saturates.
H: CCM, DCM and BCM - Inductor In a boost converter, what is the factor that determines whether the power supply (dc-dc converter) will be in the CCM, BCM or DCM mode? Because, I have an LED Driver A80604. And I am trying to calculate the inductor value for it. Input Voltage = 9.5V to 16V LED string = 9 LEDs (each Vf of 3.1V and If=0.3A) Output voltage = 30V Output Current = 300mA In this case, I have been following the design example from page 35. I have got to this point : Vout_typ = 30.64V & Vf_schottky=0.52V. Vbat = 9.5V, 13.5V & 16V (Min, typ and Max) Are my above calculations, right? My questions: What is the factor that determines whether the power supply (dc-dc converter) will be in the CCM, BCM or DCM mode? What is the required inductor value that I need to choose for this application which requires constant current for the LEDs? AI: What is the factor that determines whether the power supply (dc-dc converter) will be in the CCM, BCM or DCM mode? The dominant factor is load current. If the load current goes beyond a certain value the boost converter will operate in continuous conduction mode: - On lighter loads the boost converter will operate in discontinuous conduction mode: - And, at exactly one point, DCM and CCM look the same - this is called boundary conduction mode. What is the required inductor value that I need to choose for this application which requires constant current for the LEDs? If you want to run in CCM (probably the likely choice) then if the input voltage is 12 volts, the output voltage is 30 volts, the output current is 300 mA and the operating frequency is 455 kHz then, the minimum inductance value is around 12 μH: - Note that I set the output voltage to be 30.7 volts to accommodate the forward drop of a real diode. The dotted lines in the above graph show the BCM point. If the converter current waveform fell below that BCM line, you'd be in DCM. However, that gives over 1.3 amps of input supply ripple current and you may choose to make the inductor a lot bigger such as 100 μH: - Now, the ripple current is 0.847 amps minus 0.686 amps = 161 mA I expect somewhere between the two will be the right answer but, you can use the interactive boost tool to try out different scenarios. Your value range from 39 μH to 91 μH is going to be about right. My low end value of 12 μH might cause the boost circuit to drop into DCM mode on a lower load current and sometimes, that can cause stability problems.
H: EV controller output signals I am designing an electric vehicle controller for a university project. The motor driver varies the speed according to an analog voltage (0V-12V). My queston is, should I use a digital potentiometer followed by a buffer or a DAC to change the digital signal output from the microcontroller to an analog voltage for the motor driver, I found both close in terms of cost and complexity, and the resolution of the digital potentiometer is good for my requirements. So which would be better? Did I miss an important point of comparison? Thanks AI: Pretty much the same really as you can see: You will be able to find higher res DACs but if a digipot is OK for you then fine. You can look here to see if there is any more information which is useful: https://www.maximintegrated.com/en/design/technical-documents/tutorials/4/4025.html Check if you have a DAC embedded in the uController which could save design time.
H: Does a radio antenna need to form a closed loop to function? In either a radio transmitter or antenna, is the antenna and open end or a closed loop? In electrical theory it seems that no open loop could achieve anything. But in physics a piece of metal exposed to radio frequencies might be expected to vary in electrical potential in a way that a sensing system (tuner) could be sensitive to. Similarly with a radio tower, is the tower an open-ended conductor whose electrical potential is rapidly varied, or does the tower only emit radio waves when it conducts a current along its length? AI: An antenna of the classical type (such as a quarter wave monopole) appears to have an open end and therefore, current flowing in the monopole must become zero at that open end. This kind of implies that no current can flow but that isn't the case. A monopole requires the presence of ground/earth to work effectively and, it is the capacitance to ground that allows current to flow in a seemingly open-wire. Of course that current has to be AC just as a capacitor requires an AC voltage across it for current to pass through it. It also needs to be roughly the right sort of frequency compared to the physical size of the antenna to transmit or receive radio waves effectively. Yet real current (electrons) do not pass from one capacitor plate to the other; the action of charge building up on one plate ejects charge from the other plate and current is "seen" to flow through the wires of a capacitor. What flows between the plates is called "displacement current". Displacement current has all the same hallmarks as a real flow of electrons without electrons being harmed in any way. That displacement current produces a magnetic field just as a real flow of current does. So, when we have a monopole excited with an AC source, there are magnetic and electric fields produced that surround the antenna. Those fields can be quite complex close to the antenna but, at some small distance from the antenna can resolve into values that match the impedance of free space (approximately 377 Ω). That creates a radio (EM) wave that propagates at the speed of light. In fact light is an electromagnetic wave and it propagates through space using the same medium as radio. A dipole antenna is two quarter wave monopoles and doesn't require an earth/ground because it is driven differentially and, it is the capacitance from one end to the other that is important: - Picture from here And, when receiving: - Picture from here With both dipole and monopole antennas, if you match the applied frequency to the length of the antenna you can efficiently convert electrical power in the feed wires to radiated power in free-space (vacuum or air for instance). See also Why does 1/4 wavelength have a ground plane and 1/2 wavelength needs none?.
H: Convert 15 minute kW readings to a monthly kWh total I have metering data (kW) in 15 minute intervals that I am trying to get a monthly kWh total for... I simply summed the entire kW range, then multiplied it by hours in the month 745 (total number of readings 2,981/4). This seemed too simple though and now I'm just confused after looking at it for so long. Is this correct? Or is there more to it? AI: Assuming the power is constant for every 15 minute interval. You get $$E[n] = P[n] * 0.25~\text{h}$$ where \$ P[n] \$ is in kW and \$ E[n] \$ in kWh $$Total Energy = \sum_{i=1}^n {E[n]} $$ Where n is the number of 15-minute readings in a month (n will vary from month to month)
H: Piezoelectricity question If I have a piezoelectric crystal and apply pressure to it , it will be deformed and a voltage between its 2 ends will be generated. Is the voltage generated due to its deformation or due to the pressure? If I continue to apply the same pressure and it doesn't get anymore deformed will there still be voltage? If I stop applying pressure, it will return back to its initial position. Will voltage be generated? AI: If I have a piezoelectric crystal and apply pressure to it , it will be deformed and a voltage between its 2 ends will be generated. Nope. When you apply pressure, which deforms and this causes the crystal to gain charge. So, basically, a piezo acts as a current source, and the current it generates is proportional to the rate of change of deformation. In fact, in actual circuits you have to use charge amplifier (or integrator) to measure the force/pressure/displacement. Is the voltage generated due to its deformation or due to the pressure? Suppose the piezo crystal has a surface area \$A\$. For the pressure you apply, there will be a force that will be acting on the crystal which will deform that in a particular direction and so it will generate current in that direction. If I continue to apply the same pressure and it doesn't get anymore deformed will there still be voltage? No, because at some time the force that you applied will be balanced by the force which is generated by the stiffness of the crystal. So, your crystal will stop deforming and hence, there will be generation of current, so you cannot get any voltage. If I stop applying pressure, it will return back to its initial position. Will voltage be generated? Yes!
H: Vestax PMC-07 Mixer PSU I'm trying to fix a Vestax PMC-07 Mixer and I'm puzzled by the schematics. It is fed by a single +12V wall-wart switching adapter through a DC Jack. Can this configuration really produce a negative 10V rail using this combination of a NJM-7910 for the negative and a NJM-7810 for the positive? The full service manual can be found here: VSS-PMC-07PRO.pdf AI: The picture you took from the service manual clearly says the power supply input is 15 VAC, right next to the connector. It can't work with a DC supply.
H: Right way of wiring discrete LEDs to make a high power LED panel I want to make an LED panel as shown below: I need some help understanding the wiring of discrete LEDs. Typically discrete LEDs are rated for 185 mA at 2.7 V. Calculated wattage will be roughly 0.5 watts. I want to make a 100 W panel which means 200 LEDs. I understand that LEDs should be driven by a constant current source but it will be highly impractical to put the entire set of LEDs in series and drive using a CC power supply. The voltage requirement will be roughly 540 V. The second option is to connect the LEDs in a series-parallel network that looks like this: 8 LEDs in series and 15 such series networks in parallel. In an ideal case, this setup can be powered up by a constant current source of 4.625 amps (assuming equal current distribution in the parallel networks). I guess they use a very similar circuit in the chip on board LED lights (shown below): My questions are as follows: Can I just connect a 4.625 amp constant current source on red and black wires and expect the setup to work correctly? Should I regulate the current in the individual series group network to 185 mA and feed the whole setup with a constant voltage power supply? How do COB lights distribute the current so uniformly that they do not need current regulation in individual series group? AI: There is a resistive component to the LED I-V curve, which is especially significant at higher currents. This helps in making the current distribution more even. The Vf of the LEDs will vary with temperature so you might want to connect them in a way that the inevitable higher spot temperature in the center of the plate does not unduly influence any one string. This may not be so easy (or even possible) on a single-layer aluminum core PCB. Without an aluminum core PCB and ~75W of dissipation (the remainder leaves as visible light), your PCB may tend to self-immolate. Chances are your LEDs will mostly be very close to each other in Vf at a given current because the dice are taken from a wafer in a very organized fashion in most cases. A constant current to the series-parallel array makes the most sense to me. You could also consider adding to the series resistance of the strings by inserting 25 physical resistors, one in each string (still driven with a constant-current source), but that would add to the power dissipation and you might want to figure out what the intrinsic resistive component is to estimate the improvement.
H: Bandwidth and frequency confusion This picture is taken from this answer. As far as I know, the bandwidth is the range of frequencies at which the gain does not go below 70.7% of its maximum gain. As we can see the author said when gain is 100 the "bandwidth" is 10,000. How? the graph simply says at frequency 10,000 Hz the gain would be 100, that's all. It does not mean from 0-10,000 Hz the amplifier is going to attain at least 70.7% of it's maximum gain (that flat line gain). So does it mean the the author want to mean "frequency" instead of BW? If no, then what is the actual definition of BW? AI: If you have an amplifier that has maximum open-loop gain at DC up to some frequency (call it the 3 dB point or cut-off point) then, at any spectral point on that gain curve, the bandwidth equals frequency. If you had an amplifier that didn't have gain at DC, rather like this confusing diagram on a certain Wikipedia page that attempts to explain GBW product: - Then, the waters are considerably muddied by the high pass nature in the lower frequencies and, this would not apply to common op-amps at all because clearly, the open-loop bandwidth at any particular gain has to take into account limitations at DC and, there isn't an op-amp that I know of that behaves this way (despite the wiki article and the picture showing an op-amp circuit in the diagram). In other words: - Those low frequency cut-offs don't happen with an op-amp and gain extends all the way to DC. So, my advice to you is forget that wiki page and that confusing diagram.
H: Controlling MG946R servo with 3.3v PWM signal For a project we're building a robot arm, using three MG946R servos and one MG90S servo. Now I was wondering how to control those since I've been tasked with acquiring the hardware. I think the MG90S takes a 3.3v PWM signal since I've worked with its 'brother', the SG90, before. Can we use a 3.3v PWM signal for the MG946R servos too? Seeing that they use 6V for power. Also, what micro controller would you recommend? I assume it would need four pins with PWM to control the four servos Thanks for any help! AI: I think you would need a 5V PWM signal to use the full range of speeds/torques of the motor for both types of servos. This components101.com link talks about your motor some and how to control it. An Arduino with 4 independent PWM outputs should work, like the Uno or Atmega2560 version. It looks like you will have to power the servos with a 5V/GND pair that can supply up to 1.2A for the MG946R servo if it stalls. If you try to power it with the wrong pins from, say, an Arduino board you could trip the board or blow a fuse, so make sure whatever pins you use can handle the current max that could be drawn. IIRC the Uno has 6 PWMS and a 5V output pin that can provide enough current for you.
H: DSLR Hotshoe wiring to Arduino revisited - I'm getting false triggering. How can I overcome that? I read this post of 7 years ago:DLSR Hotshoe wiring to Arduino I built the exact circuit described in the answer, shown below, to detect when my canon DLSR hotshoe would send a "trigger" order to the flash. This trigger signal could then be dealt with by an Arduino. This is the hotshoe of the Canon camera below: My Arduino detects when I fire the flash (pull trigger to GND,) but the weird thing is that it also detects when I half-press the shooting button, and sometimes keeps detecting if I keep the button half pressed for some time. When I do shoot it always detects normally, so it works, but something is false triggering when I half press the button - and it's random. If the camera is on and I don't press the shooting button, it works normally as it should, never detects any false "triggering". What could I do to fix it? Is the Canon hotshoe trigger different from others? AI: After seeing with the scope that the camera keeps sending fast pulses from time to time while the button is half-pressed, and a longer pulse when the button is fully pressed, I implemented the debounce function to only allow pulses that are longer than 5ms. That seemed to have solved the problem and the false triggerings!
H: Switch negative pulse The following image shows a switch that, when activated, feeds a load with -10 volts. I have a microcontroller and I need to switch this, what can I use instead of the key? Npn transistor already tried but I couldn't, how to do it?! (https://i.stack.imgur.com/q3dTK.png) AI: Based on very little information, here is something I did 5 years ago on another forum. There is another way to do that that uses only one NPN transistor and a zener diode.
H: Why is the voltage drop over my MOSFET so large? I am trying to use an NCV8403B N-channel power MOSFET to control the power for my circuit. The schematic itself is quite simple: The MOSFET is controlled by an SPST switch. When in the ON position, Vds and Vgs will be between 7V and 8.4V, depending on how charged the batteries are. The Vgd is well above the Vgs(th)(gate threshold) of 1.0V-2.2V. A Vgd of 7V - 8.4V should also give a Rds(on) value of about 40mOhms. With a current, Id, of 3A, that should equal a voltage drop of 0.12V, but when I test the circuit I get a voltage drop of 1.8V over the MOSFET. Why is this happening, and what can I do to stop it? AI: You have a source follower, not high-side switch. MOSFETs are NOT controlled by the gate voltage. They are controlled by the voltage DIFFERENCE between gate and source. How is your MOSFET supposed to know what the voltage at GND is when none of its pins are connected to GND? Yet, you are applying a gate voltage relative to GND. What happens to the voltage at source node when current tries to flow through the load? What does this do to Vgs? To use an NMOS in this situtation, you need what is called a "high-side gate drive" that drives the gate voltage relative to the source voltage, rather than relative to GND. But not just any high-side gate drive. Since yours is a switch, you require a high-side gate drive capable of 100% duty cycle which most high-side gate drives cannot do (motor and inverter commutation, for example alternates frequently between switches and does not need 100% duty cycle). Expect a lot of work providing 100% duty capable high-side drive for an NMOS. Bootstrap cap drive won't provide 100% duty. PMOS is easier in this respect. For PMOS it is simplest to +V (high-side). For an NMOS, it is simplest to connect closest to GND (low-side). But interrupting the GND can cause noise issues in some circuits so is not generally desirable but not a deal breaker either Works fine for simple things like heaters, LEDs, relays and sometimes motors but could run into issues with more sensitive or complex loads. Recommend you use PMOS on high-side instead unless your current demands are so high you are forced to go with an NMOS. NMOS on the high-side is not necessarily worse than PMOS; NMOS is more efficient after all, but it will definitely add complexity.
H: Why should BJTs be saturated in switching circuits? Assume that I'm going to drive an LED with a bipolar transistor as a switch. According to books, when the LED is on, the transistor should be saturated, i.e. V_CE should be close to zero. But why do authors emphasize on saturation? I mean, in plots of collector current (I_C) as a function of V_CE, we can see that for a wide range of V_CE values, I_C is almost constant. I can think of two possible motivations for using saturation: When a BJT is saturated, the calculations are simpler: no need to calculate V_CE and insert it in Kirchhoff's voltage law. When a BJT is saturated, all voltage provided by power supply can be given to the load (with no V_CE voltage drop) AI: Reason 2 is the answer. Since P = VI we have two switch states: Transistor off: I = 0 so P = 0. There is no power dissipated in the transistor. Transistor on: I is high but V is low - typically 0.2 V or so for a BJT. That means that P = 0.2 × I. This may be as low as we can get with a BJT but will be a lot better than V/2 × I/2 which would be the half-way point on an analog arrangement. Note that with high powered loads that this reduced power can still be high enough that serious looking heatsinks are required.
H: As a general rule, should input pins be protected with a series resistor? I have read this article about why and how protect input pins. The article mentions the specific scenario of industrial electronics, with the input pin conneted to a long wire. However, if the input pin is connected through a short wire to a sensor or a pot. do the rules in the above article be applied as well? AI: The simple rule is that if the input pin is going to something that's 100% under your control and guaranteed not to misbehave, then no, you don't need protection. If you can't guarantee that, then yes, you need protection. The only time I'd advocate violating that principle is if, for some reason, you're designing an instrument whose measurements won't work right if you use protection (i.e., if you're building a $100 4-1/2-digit voltmeter, then it should be designed so that nothing can break it. But if you're building a $100,000 10-digit voltmeter, then it can break if a grad student sneezes three feet away from it, as long as it says so in the manual). Generally, "under your control" means that said input pin is inside the box, and it's going to something that you put in the box. So if your pot or sensor are inside the product, and you can guarantee that they won't apply a voltage/current combination that exceeds the input pin's parameters, then you're fine. If the input pin goes to something outside the box -- for example, if you're building a multimeter, or even a box that uses your bespoke cable with a sensor at the end of it -- then you should protect the input pins.
H: What are the final steps to arrive at the transfer function for this RCL circuit? What are the final steps to arrive at the transfer function for this RCL circuit? I am attempting to arrive at this transfer function $$\dfrac{V_o(s)}{V_i(s)}=\dfrac{sL}{CL(R_1+R_2)s^2+(R_1R_2C+L)s+R_1}$$ for the following RCL circuit. My initial problem was not knowing the correct steps to take to get from the circuit to the final TF, using the complex impedance method. So, I have now used the KVL method, which has got me to a final transfer function. But, not the one that I desire. $$\dfrac{I_2(s)}{V_1(s)}=\dfrac{s^2CL}{CL(R_1+R_2)s^2+(R_1R_2C+L)s+R_1}$$ Therefore, I would just like to know whether or not the last remaining step is to take \$V_o = I_2(s)Z_c\$, where \$Z_c = \frac{1}{sC}\$ and therefore multiply \$I_2(s)\$ by \$\frac{1}{sC}\$ and thus reduce the numerator from \$s^2CL\$ to \$sL\$ So, these are the steps taken using KVL: Loop 1: $$V_1(s) - I_1(s)R_1 - L(sI_1(s)-sI_2(s)) = 0$$ $$I_1(s)(R_1 + sL)- sLI_2(s) = V_1(s)\tag{1}$$ Loop 2: $$I_2(s)R_2 + \frac{I_2(s)}{sC} + L(sI_2(s)-sI_1(s)) = 0$$ $$-sLI_1(s)+I_2(s)(sL+R_2+\frac{1}{sC}) = 0\tag{2}$$ From (2) I get that \$I_1\$ $$I_1=I_2(s)(sL+R_2+\frac{1}{sC})\frac{1}{sL}$$ $$I_1=I_2(s)(1+\frac{R_2}{sL}+\frac{1}{s^2CL})\tag{3}$$ which, when substituted into (1), gives $$I_2(s)(1+\frac{R_2}{sL}+\frac{1}{s^2CL})(sL+R_1) - sLI_2(s) = V_1(s)\tag{4}$$ Multiplying through by \$(sL+R_1)\$ $$I_2(s)(sL+\frac{sLR_2}{sL}+\frac{sL}{s^2CL}+R_1+\frac{R_1R_2}{sL}+\frac{R_1}{s^2CL})-sLI_2(s)= V_1(s)\tag{5}$$ Multiplying through by \$I_2(s)\$ $$sLI_2(s)+\frac{sLR_2}{sL}I_2(s)+\frac{sL}{s^2CL}I_2(s)+R_1I_2(s)+\frac{R_1R_2}{sL}I_2(s)+\frac{R_1}{s^2CL}I_2(s)-sLI_2(s)= V_1(s)\tag{6}$$ cancelling out like terms, I get $$\frac{sLR_2}{sL}I_2(s)+\frac{sL}{s^2CL}I_2(s)+R_1I_2(s)+\frac{R_1R_2}{sL}I_2(s)+\frac{R_1}{s^2CL}I_2(s)= V_1(s)$$ factoring out \$I_2(s)\$, I get $$I_2(s)(\frac{R_1}{s^2CL}+\frac{R_1R_2}{sL}+\frac{1}{sC}+R_1+R_2)= V_1(s)\tag{7}$$ obtaining a common denominator, I get the following $$I_2(s)(\frac{R_1}{s^2CL}+\frac{sR_1R_2C+sL}{s^2CL}+R_1+R_2)= V_1(s)\tag{8}$$ $$I_2(s)(\frac{R_1}{s^2CL}+\frac{sR_1R_2C+sL+s^2CL(R_1+R_2)}{s^2CL})= V_1(s)\tag{9}$$ factoring out the \$1/s^2CL\$, I get $$\frac{I_2(s)}{s^2CL}(R_1+sR_1R_2C+sL+s^2CL(R_1+R_2)= V_1(s)\tag{10}$$ Rearranging in terms of \$I_2(s)\$ and \$V_1(s)\$, I get $$\dfrac{I_2(s)}{V_1(s)}=\dfrac{s^2CL}{CL(R_1+R_2)s^2+(R_1R_2C+L)s+R_1}\tag{11}$$ So, is the last step to take \$V_o = I_2(s)Z_c\$, where \$Z_c = \frac{1}{sC}\$ and therefore multiply \$I_2(s)\$ by \$\frac{1}{sC}\$ whereby reducing the numerator from \$s^2CL\$ to \$sL\$? AI: Your schematic is as follows: simulate this circuit – Schematic created using CircuitLab Above, you can see that \$R_2\$ and \$Z_2\$ form a voltage divider that divides \$V_Y\$ into \$V_\text{OUT}\$. It follows that: $$\begin{align} \text{Each Stage} \left\{ \begin{array}{rl} V_\text{OUT} = V_Y\,\frac{1}{1+\frac{R_2}{Z_2}}&&Z_2 = \left(Z_{C_1}\mid\mid \infty\right)=Z_{C_1}\\\\ V_Y = V_\text{IN}\,\frac{1}{1+\frac{R_1}{Z_1}}&&Z_1 = Z_{L_1}\mid\mid \left(Z_2 + R_2\right) \end{array} \right. \end{align}$$ $$\therefore \frac{V_\text{OUT}}{V_\text{IN}}=\frac{1}{1+\frac{R_1}{Z_1}}\cdot\frac{1}{1+\frac{R_2}{Z_2}}$$ From that, I get: $$H\left(s\right)=\frac{L_1\,s}{L_1\,C_1\left(R_1+R_2\right)s^2+\left(R_1\,R_2\,C_1+L_1\right)s+R_1}$$ That is not in standard form, though. To get started, you want to divide through so that you isolate \$s^2\$ in the denominator. So, something like this to start: $$H\left(s\right)=\frac{\frac{1}{C_1\left(R_1+R_2\right)}\,s}{s^2+\frac{R_2\,C_1+\frac{L_1}{R_1}}{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}\,s+\frac{1}{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}}$$ Set \$\alpha=\frac12\cdot \frac{R_2\,C_1+\frac{L_1}{R_1}}{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}\$, \$\omega_{_0}=\frac{1}{\sqrt{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}}\$, and create the unitless damping factor of \$\zeta=\frac{\alpha}{\omega_{_0}}\$. The standard form for a 2nd order bandpass is: $$H\left(s\right)=K\cdot \frac{2\zeta\,\omega_{_0}\,s}{s^2+2\zeta\,\omega_{_0}\,s+\omega_{_0}^2}$$ Where \$K\$ is the voltage gain. You can now solve for \$K\$. It may be convenient to set \$\tau_{_1}=\frac{L_1}{R_1}\$ and \$\tau_{_2}=R_2\,C_1\$. Then you should find: $$K=\frac{1}{1+\frac{\tau_{_2}}{\tau_{_1}}}$$ With all values set to 1, as you show, this means \$K=\frac12\$ or \$-6\;\text{dB}\$. Let's re-examine \$H\left(s\right)\$ with some light from above. We know that \$\omega_{_0}\cdot \tau_{_0}=1\$, so it follows that: \$\tau_{_0}=\sqrt{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}\$ Let's follow through with some algebra and replacements: $$\begin{align} H\left(s\right)&=\frac{\frac{1}{C_1\left(R_1+R_2\right)}\,s}{s^2+\frac{R_2\,C_1+\frac{L_1}{R_1}}{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}\,s+\frac{1}{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}}\\\\ &=\frac{\frac{\frac{L_1}{R_1}}{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}\,s}{s^2+\frac{R_2\,C_1+\frac{L_1}{R_1}}{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}\,s+\frac{1}{L_1\,C_1\left(1+\frac{R_2}{R_1}\right)}}\\\\ &=\frac{\tau_{_1}\,\omega_{_0}^2\,s}{s^2+\left(\tau_{_1}+\tau_{_2}\right)\omega_{_0}^2\,s+\omega_{_0}^2} \end{align}$$ From this, we can fathom that the damping factor is \$\zeta=\frac12\,\left(\tau_{_1}+\tau_{_2}\right)\omega_{_0}\$. (Look back at the definitions for \$\alpha\$, \$\omega_{_0}\$, and \$\zeta\$ earlier above.) Looking only at the numerator now, we know that \$K\,2\zeta\,\omega_{_0}=K\,2\left(\frac12\,\left(\tau_{_1}+\tau_{_2}\right)\omega_{_0}\right)\,\omega_{_0}=\tau_{_1}\,\omega_{_0}^2\$ or that \$K\left(\tau_{_1}+\tau_{_2}\right)=\tau_{_1}\therefore K=\frac{\tau_{_1}}{\tau_{_1}+\tau_{_2}}=\frac{1}{1+\frac{\tau_{_2}}{\tau_{_1}}}\$ Q.E.D. I hadn't realized you wanted the branch current through \$R_2\$ and \$C_1\$ divided by \$V_\text{IN}\$, before. But everything is present above to develop it. Take the equation for \$V_Y\$ from above and divide it by the branch impedance, \$R_2+Z_{C_1}\$: $$\begin{align} I&=\frac{V_Y}{R_2+Z_{C_1}} = V_\text{IN}\,\frac{1}{1+\frac{R_1}{Z_1}}\,\frac{1}{R_2+Z_{C_1}}\\\\&\therefore\\\\ \frac{I}{V_\text{IN}}&=\frac{L_1\,C_1\,s^2}{L_1\,C_1\left(R_1+R_2\right)s^2+\left(R_1\,R_2\,C_1+L_1\right)s+R_1} \end{align}$$ But the easier way to see the above result is to just go back to your \$\frac{V_\text{OUT}}{V_\text{IN}}\$ transfer function. \$V_\text{OUT}\$ is riding on top of \$C_1\$. So the branch current is \$I=\frac{V_\text{OUT}}{Z_2}\$. All you have to do is: $$\frac{I}{V_\text{IN}}=\frac{V_\text{OUT}}{V_\text{IN}}\cdot \frac{I}{V_\text{OUT}}=\frac{V_\text{OUT}}{V_\text{IN}}\cdot\frac1{Z_2}=\frac{V_\text{OUT}}{V_\text{IN}}\cdot \bigg[C_1\, s\bigg]$$ Nothing at all difficult to see. Final note to OP on using sympy for problems such as the above Since you expressed an interest in sympy (which I most certainly recommend to you), I'll disclose below what I did to save myself time (and mindless mistakes) when creating the equations I used above. (I also recommend including a numeric solver, SageMath. I use Sage with sympy, myself. Be sure to google around to see how others have installed both on your operating system of choice.) I entered the following, to get started: var('vin vout vy l1 c1 r1 r2 s') z2=1/s/c1 z1=(sl1)(z2+r2)/(sl1+z2+r2) hs=simplify(1/(1+r1/z1)/(1+r2/z2)) Then I write the first line below, which printed out the second line: hs l1s/(l1s(c1r2s + 1) + r1(c1s(l1s + r2) + 1)) Well, sympy has its own style of generating "best output" by factoring things. I didn't like it much, so I wrote something to just grab the denominator, expand it (un-factor it) out, and then factor it back over 's', instead. The first line is what I wrote; the second line is what it gave back: factor(expand(fraction(hs)[1]),s) r1 + s*2(c1l1r1 + c1l1r2) + s(c1r1r2 + l1) Now, that looks a lot better. Pretty easy, right?? But then I wanted "standard form." So now the following (a is \$\alpha\$, w0 is \$\omega_{_0}\$, etc): a=(r1r2c1+l1)/2/l1/c1/(r1+r2) w0=sqrt(r1/l1/c1/(r1+r2)) zeta=a/w0 I knew that \$K=\frac{H\left(s\right)}{\left[\frac{2\zeta\,\omega_{_0}\,s}{s^2+2\zeta\,\omega_{_0}\,s+\omega_{_0}^2}\right]}\$, so I added: K=simplify(hs/((2zetaw0s)/(s*2+2zetaw0s+w0w0))) To see what that was: K l1/(c1r1r2 + l1) Well, this immediately told me something important. Divide top and bottom by \$L_1\$ and I get: \$\frac{1}{1+\frac{R_2\,C_1}{\frac{L_1}{R_1}}}\$. (The denominator is unitless, as it must be. And so I kept both factors in terms of time so that the unit cancellation was obvious. ) That's probably enough for now. You get the idea. It's really easy! Sage, if you use it, has its own "shell variable" called "SAGE_STARTUP_FILE" which you can set to some file. When you start Sage from a shell command, it will load that file and execute the lines as if you typed them. Saves time. In my case, to get the bits of sympy I often use, my file starts this way: %colors linux from sympy import from sympy.solvers import solve from sympy import radsimp, signsimp from sympy.simplify.radsimp import collect_sqrt Because it's easy to do and because I sometimes want to look at different Butterworth filters without having to go find a manual on it, I add these lines, as well: def Butterworth(n): r = solve( 1+(-1)*nx*(2n), x ) t = [] for a in r: if real( a ) < 0: t.append( a ) t.sort( key = lambda tup: real( tup ) ) u = [] var( 's' ) if ( len( t ) - 2int( len( t ) / 2 ) ) == 1: u.append( s + 1 ) t.pop( 0 ) for i in range( len( t ) / 2 ): scnd = collect(expand((s - t[2i])(s - t[2i+1])), I, evaluate=False)[1] n, d = fraction( scnd ) co = [collect_sqrt( simplify( r ) ) for r in Poly( n, s ).all_coeffs()] spwr = simplify( s*(len( co )-1) ) ufactor = 0 for j in co: ufactor = ufactor + spwr factor( j/d ) spwr = simplify( spwr/s ) u.append( ufactor ) return u This allows me to write: for x in Butterworth(2): simplify(x) s*2 + sqrt(2)s + 1 If I want the numbers, instead, then: for x in Butterworth(2): simplify(x.n()) s*2 + 1.4142135623731s + 1.0 Let's try something a little higher order, done both with irrationals as well as just approximate real numbers: for x in Butterworth(4): simplify(x) s*2 + s(sqrt(4 - 2sqrt(2)) + sqrt(2sqrt(2) + 4) + 2sqrt(sqrt(2) + 2))/4 + 1 s2 + s(-sqrt(4 - 2sqrt(2)) + 2sqrt(2 - sqrt(2)) + sqrt(2sqrt(2) + 4))/4 + 1 for x in Butterworth(4): simplify(x.n()) s2 + 1.84775906502257s + 1.0 s*2 + 0.765366864730179s + 1.0 Ah! But I wanted a 12th order Butterworth: for x in Butterworth(12): simplify(x.n()) s*2 + 1.98288972274762s + 1.0 s*2 + 1.84775906502257s + 1.0 s*2 + 1.58670668058247s + 1.0 s*2 + 1.21752285801744s + 1.0 s*2 + 0.765366864730179s + 1.0 s*2 + 0.261052384440103s + 1.0 Well, I'm insane now. I'm going to design myself a 23rd order Butterworth filter because... well because I can: for x in Butterworth(23): simplify(x.n()) s + 1.0 s*2 + 1.98137189207266s + 1.0 s*2 + 1.9258345746956s + 1.0 s*2 + 1.83442260301091s + 1.0 s*2 + 1.70883880909298s + 1.0 s*2 + 1.55142258140884s + 1.0 s*2 + 1.36510628643731s + 1.0 s*2 + 1.15336064422973s + 1.0 s*2 + 0.920130075462304s + 1.0 s*2 + 0.669759224341972s + 1.0 s*2 + 0.406912026105268s + 1.0 s*2 + 0.136484826729342s + 1.0 Now, do you know where I can find the constants for a 23rd order Butterworth? (If so, I'll just use this: "for x in Butterworth(100): simplify(x.n())" and push up the ante a bit.) In short, you can develop your own functions and solutions for a variety of electronic needs. I have. Pretty much anything is at your fingertips. I sometimes want to develop my own diode equations for various LED devices. I grab a bunch of random devices from the bag and make three measurements on each one. (I do have to use a 5-digit multimeter, or better, to get necessary precision and reasonable accuracy. I have a 6.5 digit one from HP.) In this way, I can collect up the LED parameters and examine their distributions. This tells me a lot about their manufacturer and their strategies in selling them through the supplier I bought from. So I wrote this: def diode(): print( "This program uses 3 diode measurements to extract parameters." ) print( "You will need to have taken these measurements beforehand." ) print( "Enter each point as [ <diode current>, <diode voltage> ]." ) print( "" ) TA= int( input( "Enter the ambient temperature in Celsius (default is 27 C): " ) or "27" ) print( "" ) VT= 8.61733034e-5 * ( 273.15 + TA ) POINTS= [] vd, id, N, ISAT, RS= symbols( "vd id N ISAT RS" ) for i in range(3): pid, pvd= input( "Enter point " + str(i) + ": " ).split() POINTS.append( { vd: pvd, id: pid } ) EQS= [] for i in range(3): EQS.append( Eq( POINTS[i][vd], RSPOINTS[i][id] + NVTln(POINTS[i][id]) - NVTISAT ) ) print( POINTS ) print( EQS ) ANS= solve( EQS, [ RS, N, ISAT ] )[0] print( "RS = " + str(ANS[0]) ) print( "N = " + str(ANS[1]) ) print( "ISAT = " + str(exp(ANS[2])) ) This program generates the model parameters I want for any LED I have in my hand from just three distinct measurement points, \$\left(V_i, I_i\right)\$. By the way, if you think I'm joking about 100th order Butterworth? Here it is: for x in Butterworth(100): simplify(x.n()) s2 + 1.99975326496332s + 1.0 s*2 + 1.99777974992394s + 1.0 s*2 + 1.99383466746626s + 1.0 s*2 + 1.98792191091036s + 1.0 s*2 + 1.98004731543312s + 1.0 s*2 + 1.97021865230955s + 1.0 s*2 + 1.95844562124353s + 1.0 s*2 + 1.94473984079535s + 1.0 s*2 + 1.9291148369156s + 1.0 s*2 + 1.91158602959666s + 1.0 s*2 + 1.89217071765509s + 1.0 s*2 + 1.87088806165973s + 1.0 s*2 + 1.84775906502257s + 1.0 s*2 + 1.82280655327089s + 1.0 s*2 + 1.79605515152123s + 1.0 s*2 + 1.76753126017739s + 1.0 s*2 + 1.73726302887638s + 1.0 s*2 + 1.70528032870818s + 1.0 s*2 + 1.67161472273654s + 1.0 s*2 + 1.63629943485005s + 1.0 s*2 + 1.59936931697418s + 1.0 s*2 + 1.56086081467666s + 1.0 s*2 + 1.52081193120006s + 1.0 s*2 + 1.47926218995722s + 1.0 s*2 + 1.43625259552638s + 1.0 s*2 + 1.39182559318463s + 1.0 s*2 + 1.34602502701955s + 1.0 s*2 + 1.29889609666037s + 1.0 s*2 + 1.25048531267141s + 1.0 s*2 + 1.20084045065177s + 1.0 s*2 + 1.15001050408656s + 1.0 s*2 + 1.09804563599626s + 1.0 s*2 + 1.0449971294319s + 1.0 s*2 + 0.990917336864815s + 1.0 s*2 + 0.935859628521147s + 1.0 s*2 + 0.87987833971183s + 1.0 s*2 + 0.823028717210218s + 1.0 s*2 + 0.765366864730179s + 1.0 s*2 + 0.706949687558514s + 1.0 s*2 + 0.647834836396299s + 1.0 s*2 + 0.588080650464608s + 1.0 s*2 + 0.527746099930746s + 1.0 s*2 + 0.466890727711811s + 1.0 s*2 + 0.405574590713025s + 1.0 s*2 + 0.343858200558819s + 1.0 s*2 + 0.281802463875165s + 1.0 s*2 + 0.219468622182091s + 1.0 s*2 + 0.15691819145569s + 1.0 s*2 + 0.0942129014192853s + 1.0 s*2 + 0.0314146346236414s + 1.0 Of course, that's all theoretical! Assuming a sufficiently precise VNA even existed, you might be sitting around for a long time tweaking it using its time domain function.
H: Friendly target identification in radar Crossposted from Signal Processing stack exchange, How do radar systems identify friendly targets to avoid AA locks during combat scenarios? Do friendly planes broadcast a known signal or is something else going on? AI: They use IFF (Identification Friend or Foe) for the Radar version of friendly target identification. I'm afraid it's becoming a bit more complicated than that. Being developed currently at the complete force organization level you have CJADC2 (Combined Joint All Domain Command and Control), the air force's contribution to which is the ABMS (Advanced Battle Management System) The new tech for the Anti Aircraft part of this system is an evolving fully integrated air defense network which integrates all available sensors and effectors in the field and intelligently coordinates responses to threats (fire control decisions are made by a human). It can be fed GPS positioning, signals from radars, radio signals, laser painted targets, whatever. They've built the system with a flexible architecture so if they want to add a sensor type, they just need to write code to interface it. For really complicated sensors like a camera, data interpretation can be done by a separate computer to generate the actual data fed to the system. A single potential target could be observed at the same time by several radar systems, a friendly GPS signal and or transponder code from a BTID (Battlefield Target Identification Device) or GPS radio system, satellite camera or triangulation data from a sensor like a jet in flight or a robot dog. Based on the article it appears they are designing it to be fairly intelligent, able to differentiate between actual targets and electronically spoofed targets, likely also disguised targets. It can reroute the sensor data "tracks" it finds valid between units (presumably so non-automated parts of units can see the correct data and respond) and provide alternatives in the case an effector fails. As far as what it can control, pretty much any modernized automated weapon system (not necessarily automatic like a CIWS (Close In Weapons System), but capable of being computer controlled. As another option, software can be written to interface with humans controlling non-automated systems by whatever form of messaging. Aside from physical weaponry or deployment orders, it can advise for and control electronic warfare options, say, to hack a drone or missile in flight. That said, part of the reason that parts of this system are being brought into existence is that friendly fire is still a problem. In terms of things that have already been used, I found this article from 2007 about preventing friendly fire that seems to indicate that air to ground combat information was fed to pilots by control centers staffed by humans and a recent improvement made was to stream video from the aircraft so the person in the control center isn't working off of verbal description of the pilot of all things. They mention that the BTID devices mentioned above are currently under evaluation and another option being evaluated was to use the GPS radio systems already integrated into some countries' machinery. The precise state of military technology is often kept under wraps to some degree (a fair bit is obfuscated in these articles) but it's 2021 and 14 is a lot of years in technology time, so by now I would expect all the high end militaries to have fully integrated GPS at the vehicle level at the very least, likely GPS equipment at some squad level and possibly capability for individual soldiers. Good old fashioned knowing where your stuff is can't really be completely replaced (true in the article if you read it), but as parts of it are enhanced and automated, friendly fire risk probably goes down. With the right programming, based on all of it's sensor data and information about who or what should be where, the system would have a much better chance of identifying by inference a friendly target whose IFF transponder had failed.
H: Will the Boolean equation change when we reduce the CMOS transistors in a static CMOS logic? We are doing a project about a multiplier. Two of my teammates are assigned to make the transistor level designs of the adders, subtractors and few barrel shifters. My prof has told me to make a structural level Verilog modelling of the same multiplier. He then instructed " When your teammates reduce the number of transistors for the adders and subtractors, the boolean equation changes. Put those boolean equations in the Verilog Code and we'll have the optimized multiplier". Our team is slightly confused, since the Boolean equation has nothing to do with the transistors but just the logic to be implemented. So TLDR ; If the number of transistors in a Static CMOS logic design are reduced, will the Boolean equation change significantly? AI: Sure it does. An unsimplified boolean expression has redundant operations hidden inside it. If you implement that unsimplified boolean expression, then you will have extra logic gates/transistors implementing those redundant operations. If you did things correctly, the end result doesn't change, but the path to get there does. the Boolean equation has nothing to do with the transistors but just the logic to be implemented. The boolean equation is used to pick the logic gates, and the logic gates are made of transistors.
H: Help decode/identify/guess this blown ceramic capacitor? My monitor's backlight died (can still see screen with torch). Found a blown ceramic disc capacitor. The problem is it's partly exploded over the values. I'm hoping people here might have a better guess. The monitor is the Philips BDM4065UC. The capacitor is off the power board. And for reference here are pictures of the board. Can't upload them here due to 2MB filesize. The capacitor is C9818 it's in the middle top of the top of the board picture and the middle right of the bottom of the board. AI: That part appears to be a 220pF 1kV capacitor1. These are readily available (e.g. from here2). These don't typically burn up on their own3 though so there's likely an additional fault on the board that caused this cap to fail. You should also take a look at this question which is very similar to yours. 1 22 is the multiplier, 1 is the number of zeroes after it, K is usually the tolerance (probably ±10%), value is in pF. Thus 221K == 220pF ±10%. 2 The part links go to Mouser (my preferred distributor) but Digikey, Newark, or RS are also reputable suppliers. I'd avoid purchasing any parts from the likes of ebay, Amazon, or Ali Express. 3 Edit: Having taken another look at the photos you provided it looks like that the failed cap is part of an overvoltage protection circuit. I can't read the markings on the diode on the bottom of the board to determine precisely what it is (type, voltage, etc.)3. Suffice to say it looks to me like a voltage spike came in and (based on the lack of obvious damage elsewhere on the board) the protection circuit did its job and cut power to the board (using the MOSFET Q98014). The spike, however, exceeded the voltage rating of the bypass capacitor and caused it to burn up. My guess is the rest of the components are fine though Q9801 may also have been damaged. Cleaning both sides of the board around where it failed6 and replacing the capacitor and maybe the MOSFET should get things working again. One thing that you should probably do is choose a replacement capacitor with a higher voltage rating7 such as one of these. If you're not already doing so make sure your equipment is plugged into a power strip with transient voltage surge protection; that'll prevent a lot of damaging spikes from getting through. 3 Based on the questioner's comment, the diode is marked A27 which may be a DAM1MA27 or DAM3MA27 27V zener. That voltage seems odd though given that it's on the mains (high-voltage) side of the circuit. I've probably misidentified it. 4 Per the questioner's comment, Q9801 is a Toshiba K13A65U which has been discontinued by the manufacturer. It's hard to choose a suitable replacement without doing a detailed analysis of the circuit. The manufacturer recommends either the TK11A65W (datasheet, Mouser) or the TK380A65Y (datasheet, Mouser) as possible replacements. Of the two, the TK11A65W would be my choice given its lower on resistance and higher current rating. When choosing a replacement, the main parameters to try to match are probably the pinout, Vdss, Vgss, Id, V(br)dss, Vth, and Rds(on) with Qq being less important. The part found by the questioner (TK155A65Z, datasheet) also looks like a decent option. Honestly, choosing an appropriate replacement is a whole question unto itself5. 5 I'd encourage you to post such a question. 6 90% denatured or isopropyl alcohol should do fine for cleaning. 7 In my experience, monitor manufacturers are notorious for combining the lowest-speced parts possible with poor thermal design. Top of board Bottom of board
H: Offsetting Op-Amp output offset in combination with charge pump I want to have a +-12.0V square wave output from an opamp fed from a 3.3 and 5V power supply. The signal is 2.5kHz with a low duty cycle of 3-10% generated by an MCU. Peak voltage at both ends need to be within 0.1V from +-12V. The load I am driving is 1kOhm so max 12mA. The slew rate requirement is 20V/us. I have have tried a 5V to +-12V DC/DC converter as well as chargepump a. Given the low load I would think a chargepump is the most econimical. Using rail to rail opamps gave me 11.9V but I have never found an opamp with high enough slew rate. Meaning the rail to rail opamps seemed to0 slow. Then I have searched for ‘trimmable’ charge pumps at say +-12.5V that would drive a faster opamp with a 0.5V output drop but have just not found it. Was just wondering if you guys could help me with this. My situation is just easier with a more accurate 12V output. Even 11.9 has some downsides. Thanks EDIT: Built the circuit per first answer. It works great!. Albeit the output is inverted. I solved this by modifying the circuit. Removed the inverting transistor for the +12V and added a second inverting transistor for the -12V side. But other than what I had expected, the circuit became clearly 'slower' in the second, non-inverting case than it was in the inverting case per the first answer. I learned (by doing) that switching at 3.3V is slow and at 12V it is fast. What I do not understand is why the transistor M22 that I added makes the circuit slower. It is switched at 12V. What can I do to make my signal faster? (note that I simulate at 1Mhz and will build at 2.5kHz). Top schematic: inverting, bottom: non-inverting: Response graphs of OUTPUT (inverting schema) and OUTPUT2 (non-inverting schema). Clear that OUTPUT2 is 'slowish'. Probably better way to switch a -12V signal with at the inverse of a 3.3V signal than what I have done. Help appreciated!! AI: You can use transistors as so.. assuming you have solid +/-12V rails available (you could use a +/-15V DC-DC converter and linear regulators): This circuit uses 5 inexpensive MOSFETs and one 4-resistor resistor network to shift the MCU signals to +/-12V. The necessity to keep \|Vgs\| < 20V adds a bit to the complexity. This will give rise/fall times in the 100ns range and voltage drop typically < 50mV.
H: Choosing the right voltage regulation - 12/24V to 5V for my projects I always come across the power part which kinda bugs me. Usually i just open the TI webbench, put my parameters into and take whatever he gives me. But is that the right/good way? Why and where do I choose linear vs step regulation? low heat low noise? Example : Input Voltage 12/24VDC, Output Voltage = 5VDC/3A max - pref. low noise > low temp TI now gives me multiple choices: TPS56339 - buck, seems good to me or the LM604x0 - synchron step down - LMR33630 - synchron step down dont really seem to see a difference between these 2 Because all of theese are via switching I have to reduce the output noise, I didnt choose yet so I cant say how. Is there any way to choose the "best" one ? Another questions about voltage regulation - is there a way to always get the desired output voltage even with 2 different input ? Same parameters as before, but I "dont know" which one is it, so I cant make a switch/jumper, but I always need a stable 5V output. ideas? Thanks and greetings! AI: Why and where do I choose linear vs step regulation? low heat low noise? A linear regulator is typically used when a low noise output is desired and/or when the PSU is required to not emit a lot of EMI. A linear regulator is a very simple type of regulator which works by dropping excess input voltage to maintain a constant output voltage. Linear regulators are easy to use and only need a few complimentary components. However, they can be extremely inefficient, especially when there is a large voltage difference between the input and the output. Let us take your example specs - Input Voltage: 12/24VDC, Output Voltage: 5VDC/3A max The power dissipated in a linear regulator is (Vin - Vout) * Iout. If the input voltage is 24V, then the power dissipated is (24 - 5) * 3 = 57W. This requires some serious amount of heatsinking and is generally not a feasible idea. A buck converter is a switch-mode DC-DC converter which is a much more efficient solution to step down 24V to 5V at 3A. Assuming an efficiency of 90%, the power dissipated in the buck converter circuit will be around 1.5W, which is reasonable. However, buck converters usually have more complimentary components than a linear regulator, and the complimentary components must be carefully chosen (like you must only use low ESR capacitors) and they do feature a noisy output. But if you want low noise and low power dissipation, you must use both types of regulators in a cascade configuration. It looks like you are a beginner, so this might not be the best solution for you as it is a complex one. So I suggest using a simple buck converter to efficiently step down 24/12V to 5V and not worry too much about the output noise. Another questions about voltage regulation - is there a way to always get the desired output voltage even with 2 different input ? Same parameters as before, but I "dont know" which one is it, so I cant make a switch/jumper, but I always need a stable 5V output. ideas? The simplest solution is to use two diodes as shown: Use Schottky diodes that have an appropriate current rating. There are other methods, but this is the simplest one.
H: How can I carry DC component to negative side? I made a sine wave with stm32f407VG DAC periphal. But my sine wave has DC component 1.32V. I designed high pass filter but DC component was gone. But I don't want it to be gone. How can I carry it to negative side? AI: How can I carry it to negative side? Assuming that you mean 'How can I add a negative offset to the sine wave', this is my solution: The 100n capacitor is use for DC blocking and the two 10k resistors are used to bias the signal to -2.5V, so it will swing around that point. You can change the DC offset by changing the resistor values.
H: Dc to DC converter: "split" one power supply (24V, 5A) into four power sources 5V, max 3A I have one DC input 24V, 5A. I have designed a 4 channel led driver using the PAM2804 for Cree RGBW leds. I am using 3 of them. So, 3 Rgbw leds, and 3 led drivers. I need to be able to control individual r,g,b,w channels, and select if I want to use 1,2 o 3 leds. An arduino supplies the control signal to the PAMs. My question, is how to convert the 24V, 5A into four 5V, 3A(max) sources. I hav been using LM2596, or XL6009E1, to convert 24V into one 5V, 3A source. But connecting several LM2596s in series to a 24v power supply seems not to work, one of them gets almost all the voltage. I have used them both in adjustable and fixed output. What can I use instead? EDIT the picture shows 12V 5A; that is not correct, it is 24V 5A; as described in the text description. Thanks for pointing it out. AI: Your LED drivers are controlled by the same micro, so everything must have a common ground. I don't understand the "series" confusion, there is nothing to be wired in series here. What you need is a 5V power supply for 4x 3A loads, so a 5V 12A load. You can replace your 24V power supply with a 5V 15A mains power supply, or use a sufficient number of step-down DC-DCs to get 5V at the required current. For example if you get 5V 3A DC-DCs you need four, one per LED board. Please do not buy the famous cheap counterfeit LM2596 modules from the internet, every component is fake, starting with the LM2596 obviously, but the caps are also garbage and they will die.
H: What is this yellow component in my Samsung mains charger and what is its purpose? What is this yellow component in my Samsung mains charger? On the top is written "DT0506C" and on the side is written "ETAOU81EBE BE 1218". Similar looking components I've found were transformers. In my opinion it is way too far away from the rectifier and the mains connection. Its traces point me nearer to the USB port. In the third picture is the bottom perspective with the component (yellow), mains connection (red), and probably rectifier (green). AI: It's the transformer. But in my opinion its way too far away from the rectifier and the mains connection That's because it's a switching supply. Mains is rectified first, resulting in about 320V DC in the two blue CrapXon caps, then this is chopped into a square wave, fed into the transformer, and rectified in the other side. The frequency is much higher than 50Hz mains, which allows a much smaller transformer and secondary smoothing caps, and lower weight and cost. Here's a bit more detail about how a flyback power supply works.
H: BJT in saturation mode equations Suppose we have this circuit: simulate this circuit – Schematic created using CircuitLab The BJT transistor is in saturation mode.Which are the equations which help us find the different currents(Emitter , Base and Collector current)? I only know how to solve BJT transistors in forward active mode and I couldn't find anything online.Help really appreciated AI: Help really appreciated I'm going to trust you on that point Miss Mulan. Your circuit won't be behaving like an active (and saturated) BJT any more - there is too much forward bias between base and collector for this to happen and, all rules about transistor amplification are laid-to-rest and, the BJT behaves like two forward biased diodes: - Compare voltages and currents side-by-side and you'll see that they are virtually identical. The main point to note is this: - the collector current is flowing from the collector to the 1 volt power supply rail via the 100 Ω collector resistor. That means all bets are off when trying to analyse this circuit as a bona fide BJT problem because collector current is flowing the wrong way. BTW the diodes simulated above are 1N4148 devices. So analyse it as two diodes instead of a regular transistor.
H: Why does this transistor limit the current so much? I have been trying to understand how a transistor works. I bought a simulator to be able to understand it better. Below is a small circuit I designed. The load is a lamp. The characteristics of the lamp are 5 V, 50 W, so it should draw 10 A. When I design the schematic without the transistor etc, it does draw 10 A. However when I use the transistor weather I put on the lamp 50 W or 20 W etc it will not draw a "big" current. Of course this is a "generic" transistor from the sim. The sim gives me the following settings to configure the transistor (please check the bottom left of the picture) I do not understand how to configure this transistor since those settings do not match with the datasheet information at all. EDIT: Without Resistor at all on the base Ib is too high but still Ic is "too low" AI: Your lamp needs 10 A to be fully on. So your transistor then needs to be able to conduct at least 10 A. If the transistor wants to conduct more, that's OK, only 10 A will flow as the lamp will prevent more current from flowing. So the collector current of the NPN transistor needs to be 10 A. All bipolar transistors have a certain amount of current amplification which is called \$h_{FE}\$ or \$\beta\$. This \$\beta\$ is the ratio between collector and base current: \$\beta = \frac{I_C}{I_B}\$ When you want a collector current of 10 A then your base current will be about \$\beta\$ times smaller. Transistors for small currents (much less than 1 A) often have a \$\beta\$ of around 100. Transistors for large currents usually have a smaller \$\beta\$ of maybe 30 (it depends on the actual transistor). But you're in a simulator so we can do anything we like. So let's assume that \$\beta\$ = 100 that means that your base current would need to be: 10 A / 100 = 100 mA. I see that your base current is only 516 uA so it needs to be about 200x higher! If you want to be able to switch on/off a 10 A lamp with a small current (smaller than 1 mA) then I would recommend using an N-channel MOSFET. MOSFETs do not need a high current at their input. Do realize that MOSFETs do need a high voltage at their gate, it depends on the MOSFET how much that needs to be. Some MOSFETs can work with the 3.3 V you're using in your schematic.
H: Matched pair PNP usage I am asking help to understand the circuit in the black rectangle below. It’s using a matched pair of PNP, with common Base. I was thinking to a kind of current mirror, but R2 and R3 are different. I have looked in usage of matched pairs and I understand its main properties are equally matched gain. Any ideas AI: As Andy stated in his answer, the main purpose of the whole circuit is to provide reverse-polarity protection by using the PMOS as an ideal diode. Normally, you can get rid of the transistor pair at the bottom, and leave only the R3 (47k) connected to the gate. The circuit can still work and provide reverse-polarity protection: simulate this circuit – Schematic created using CircuitLab The downside of the circuit above is that it does not protect either side when you apply a positive voltage on both sides. For example, when you apply a positive voltage from the right-hand side instead of the left-hand side, the MOSFET will turn on and provide voltage to the left-hand side. Think about what happens if the VIN is connected to the USB power and you accidentally applied a positive voltage to the VOUT-side. That is the case the transistor pair's crucial role comes in. The pair ensures that the MOSFET remains off when the voltage is applied to the right-hand side instead of the left-hand side. Or generally, when there is a greater voltage on the right-hand side than that on the left-hand side. Assume you applied a positive voltage to the right-hand side and left the left-hand side unconnected. The right part of the pair will turn on (because its base is connected to GND through R2) and connect the gate of Q3 to the source. So Q3 will be off. The same things apply when the voltage on the right-hand side is greater than that on the left-hand side. So we can say that the pair prevents the MOSFET to work as a bidirectional switch. It does not provide protection when VOUT is lesser than VIN, though.
H: ESP32/ESP8266 external programmer two way design question When I design a PCB that has a ESP32/ESP8266, I usually integrate a USB-UART bridge in the design as well. However, I am now working on a board that will likely have more than just a few copies. The USB-UART bridge isn't necessary in this particular application as we are unlikely to edit the code once it is uploaded. It adds up to part cost and my time soldering the boards together. I want to use one of those cheap USB TTL boards to program the boards. There is a slight inconvenience. The standard ESP32 auto program circuit uses the "Request to Send" (RTS) line, and the FTDI programmer that I want to use doesn't have that as a standard output as seen below. It has an RTS pin on the side, so I could butcher the board and make an adapter on a breadboard but I am very sure my superiors won't accept such a put together solution. Is there a possible hardware solution I could implement on the main board that would allow me to use one of these FTDI boards to program the ESP32 automatically? Pressing a button isn't an acceptable solution either. It has to be a plug in solution. If there isn't any then I will have to design a separate programmer board that fits the requirements. AI: You could use ESP-Prog which is built specifically for this job. Comes with both UART and JTAG as well, so it give's you more options. Comes with IDC cables so all you need is to add a small IDC connector to your board (similar to the ones on the ESP-PROG PCB) It is not as cheap as those eBay FTDI clones but it still very cheap (~12$) and reliable.
H: Expected behavior for damaged transistor The generic question I have is what's the "expected" behavior for a damaged BJT. Let me add more color.. I was trying to fix my kid's toy where a motor would run even when it wasn't supposed to (no matter if the switch was on or off, it would always run). I tried to reverse-engineer the schematic driving the motor and here's what I think they had on the PCB: The motor is represented by an inductor (ignore its value). What I think is damaged is the transistor Q3 because when the motor was running there were ~8V at the base of Q3 (so it should have been off) and yet I could measure ~1V at the gate of Q4, enough to keep it on. Q4 didn't seem to be broken because if I drove 0V to its gate, the motor would stop running. Is my analysis correct or the problem of them motor always on could be elsewhere? I guess my question is: is this an expected behavior for a damaged PNP? If not, what is? I'm asking because I'd rather expect a burned BJT not to conduct when it's on, not the other way around (i.e. conduct even when it's off). And if that's the case, what might have caused it? Some specific incident (spikes in current or similar) or do transistor wear out over time anyway? Thanks EDIT So I opened it up again and there was indeed a diode across the motor as Spehro suggested (just not on the PCB). And as andre314 suggested, I measured the voltage across R4: it was 0V. So it looks like Spehro was right: the transistor that's damaged is Q4, not Q3. Now I need to learn how to replace it... Thanks everyone for your help and suggestions AI: Remove R4 and confirm that the motor remains off. Shorting R5 is not sufficient to be sure, there could be D-G leakage on Q4 for example. I would suspect Q4 first, damage to Q3 would likely be more of a random failure (toys are not known for using the finest space-qualified components). Semiconductors do tend to fail "on" unless they've been abused to the point where the case is blown apart or wirebonds are vaporized. It would be better if there was a diode across the motor unless there is some reason that is not shown in this schematic that would make that a terrible idea (possibly damaging other components).
H: ESP12F (ESP8266): every program runs okay but it's warm/hot I have an ESP12F that I programmed with USB-TTL from the Arduino IDE. The wire setup when a program is running: USB->ESP12F RX->TX TX->RX 3V3->VCC GND->GND While on GPIOs of ESP12F: RST->VCC CH_PD->VCC GPIO 0->VCC GPIO 15->GND When I touch the ESP12F, I feel my thumb gets warm and it feels like ironing temperature. I dont have a thermometer, so I just tell what I feel. What I'm afraid of is that this hot state is indicating a short circuit, but I'm sure there's no short there. If shorted, the blink program wouldn't blink, and it's blinking. I'm not using any resistor for it, I'm just connecting directly using a cable jumper. Or should I think that hot is normal? Due to current that stuff needs? Also I wonder if the GPIOs on the ESP12F are 5V tolerant. I have read many articles, they have different questions that make me confused. AI: It's absolutely normal for an ESP to become warm a little bit, especially when WiFi is active. If the metal shielding gets up to 30° or maybe 40°C I wouldn't worry too much. I suggest you measure the current/power consumption. From my experience, an ESP in a typical application (WiFi enabled, some peripherals like LEDs or transistors attached) draws around half a watt. When I power my ESP-based boards for the first time, that's what I measure to have an idea if there's something wrong. And no, the IOs are not 5 V tolerant.
H: Why there was no power to an electric cloth dryer? The other day I stumbled on something very puzzling to me. I installed a 3 prong dryer cord on a previously working dryer and as I plugged it in the wall outlet the dryer would not turn on. I was aware that the outlet was good. I unplugged the cord and checked it for continuity on all three pins. The continuity was perfect. The fellow that I was doing this for said that the cord was bad and I assured him the cord was good based on the ohmmeter. I had tossed that bad cord in my truck and was forgotten. Months passed. One fine day I checked the cord again when I found out that when it is bent just the right way, the return wire would show discontinuity. Except the heating element, the rest of the dryer runs on 120V. AI: The continuity was perfect. What, exactly, does this mean? If you used a meter with a continuity function, it only means that the resistance on each line was less than some preset limit - and this limit may have been well above what the dryer (which is a very high-current device) could allow. Go back to your cable, and set your meter to Ohms on the lowest resistance scale. Touch the two probes together and record the resistance. Now check the resistance of each line in the suspect cable. It should be very, very close to zero. The fellow that I was doing this for said that the cord was bad So, of course, when you told him it was good, you then asked him why he thought it was bad, right? No? Why not? If he thought it was bad because he had tried it before, or on another piece of gear, and it didn't work then, why did you think it would work this time?
H: Resonance Frequency of system with two inductors I am trying to derive a formula for the resonance frequency of the following circuit: The piece that is giving me trouble are the two inductors, that (although I might be wrong) cannot be further simplified. Therefore, it is not possible to use the known/basic formulas for RLC circuits which either are completely in parallel, or in series (https://en.wikipedia.org/wiki/RLC_circuit). I hope that one of you will be able to get me going by providing some hints, or pointing me to a source where I can look up the answer. In any case, thank you for your trouble. AI: The impedance of the parallel RLC is known, and it is obtained by putting together the three admittances and then reciprocating: z1 = 1/(1/R + jwC + 1/jwL2) The you add the inductor L1 in series z2 = z1 + jwL1 This is the total impedance. Then the resonance frequencies correspond to the poles of the circuit (Note: if the poles are real, ok , no resonance; if they are complex, you consider the imaginary part). Now, it's easier to take the zeros of the admittance: y2 = 1/z2 These zeros are the indication of the resonance frequencies of the circuit.
H: Is this a Depletion MOSFET? I am confused on whether this is a depletion or enchantment MOSFET and I am wondering if anyone could figure it out. I need a depletion MOSFET for my circuit and can't figure out if this MOSFET is one. Here is the link to the MOSFET: https://lcsc.com/product-detail/MOSFET_ROHM-Semicon-RTQ025P02TR_C79602.html AI: No. It is P-channel enhancement MOSFET, not depletion. You will probably not find one as depletion mode MOSFETs are exceedingly rare and I have never seen a P-channel one. You would be recommended to not require them in your design. I agree it can be confusing with a P-channel as the voltages are negative and datasheets are not consistent in the way they present the negative gate voltage. You can see from the datasheet that the drain current at zero Vgs is about zero so it is not a depletion mode.
H: Changing board shape in Altium: sliding the edge does not work How can I slide this edge? According to Altium documentation, I should:"Click anywhere along an edge, away from editing handles, and drag to slide that edge" but it does not work for me. What am I missing? AI: To change board shape in Altium, Go to your PCBDoc Press 'P', then 'L' (Short for place line) Press TAB to enter properties Set width and layer (mechanical for example at 10 mil width). Press OK Draw the boundary of your board with these settings Once you are done, select this boundary Go to Design >> Board Shape >> Define from selected objects. Done!!
H: Connect load cell to hx711 I have a 50 kg load cell and an HX711 sensor (as in the image below), my problem is that in all the tutorials I've seen people use load cells with 4 output wires or 2 cells with 3 output cables, I just need to connect only one, so I can weigh objects. I do not know if I really need 2 load cells for what I want, but I mainly want to weigh food. I have been testing with this tutorial as a base since it works for many people https://tutorials-raspberrypi.com/digital-raspberry-pi-scale-weight-sensor-hx711/ I'm learning, thank you. AI: To use a single load cell, you make the '4th wire' like this simulate this circuit – Schematic created using CircuitLab Check with your datasheet for the values of R1 and R2. They need to be low enough to power A- properly, but high enough to not load the E terminals too much. 1k will be a good default if they're not specified. Mount R1 and R2 such that they share the same temperature. You won't need much tempco, and much temperature difference, to get a significant reading. To use a second load cell, place it in the circuit where the 'ref wire' block is, but invert the red and black wires. This will make its output in antiphase to the first, so the differential input will add them with the same gain.
H: Increase number of practical microcontroller outputs (x when pin 1 is powered, y when pin 2 is powered, and z when both are)? Is there any way to make a circuit that powers (only) x part of it when pin 1 is powered, (only) y part of it when pin 2 is powered, and only z part of it when both are? I am new at electronics...i do not know. AI: Hi there are lots of GPIO EXPANDER ICs available in market which can be used for this purpose.
H: LED and the resistors I am a beginner in Electronics. I would like to clarify if my understanding regarding LEDs is correct. Suppose that we have an imaginary battery with no internal resistor that provides 2 volts. Assuming that we have a LED with forward voltage and current 2 volts and 10mA respectively. The question is can we simply light the led without a resistor? My assumption is yes, since the LED will have a voltage drop of 2 volts, and the current will be 20mA. My questions stems from the fact that there are many many sources out there, mentioning that a LED will try to gather as much current as possible and burn out in the end. This is wrong i feel or at least not very accurate. In general, the current that a LED will try to obtain is not the maximum available by the battery, but the current as specified in the i-v curves of the LED. Also, just to note, I am not asking if a resistor is required or not in case of a battery that provides enough voltage. Its more than clear to me that it is required. Is my understanding correct? AI: Assuming that we have a LED with forward voltage and current 2 volts and 10mA respectively. Yes that is true but this is only a theoretical thruth. In the real world a 2 V, 10 mA LED does not exist, at least not for long. Measure it later and the current will be different. LEDs have an exponential relation between Voltage and current. Only a small voltage change will cause a huge current change. Adding to this, the behavior of a LED is very temperature dependent. A small change in temperature will also result in a huge current change. Also not all LEDs are physically equal. Even a number of LEDs made at the same time in the same machine will be somewhat different. One will draw 20 mA at 2 V but another one 15 mA, 115 mA, 130 mA and 1 mA. All very unpredictable. So this means that when kept as 2 V the current through the LED is highly unpredictable. It can be much lower and the LED would produce less light but the current will often be much higher as well. When too much current flows the LED will be damaged. The solution is not to let the LED control the current but to use a resistor. There will still be some dependency on temperature etc. but the resulting current variations will be kept within safe limits. A resistor or some other form of current limiting is required. In some designs the resistor might not be present but might be there in a hidden form like a small battery which has a high build-in series resistance.
H: Is this negative regulator really meant to be an inverted positive regulator? Project: make a power supply that can replace the 240V AC supply shown, so that I don't die when messing with the board that this connects to. I'm only interested in the part inside the yellow box; the +40V output goes to the power amp section which I'm not working with. So I went out and bought a 7812 and 7815, but then I got confused because of the general consensus that you shouldn't use a 7815 with inverted output pins as a negative voltage regulator, but it seems like that's what they're doing here. I've ordered a 7915, but my question: (a) Is this circuit doing something smart by connecting the 7815's positive output to ground and using its output as -15V? (b) Is this circuit doing something weird, and I should use the 7915 to source -15V as the gods intended (c) it's impossible to tell, needs more info Note that I'm sourcing ±30V DC from a preamp circuit in this project, which is higher than what would be at the input in this schematic but well within tolerance for the 7812/7815/7915. My schematic, using a 7915: simulate this circuit – Schematic created using CircuitLab Version with 'reversed' 7815: simulate this circuit AI: What you have shown in the yellow box is OK, because the 18 V secondary that's sourcing the 7815 is fully isolated from the other rails. This means the 15 V output is fully floating, and any terminal can be grounded. If you want to use a centre-tapped transformer (with some slight savings in hardware and diode drops) which produces non-isolated rails, or the non-isolated rails from another piece of equipment, then you need to use 79xx series regulators for the negative rails. The reversed 7815 you've drawn will not provide the -15 V you want.
H: No PSB pin on LCD? I bought a Winstar 144x32 LCD (WG14432D) because it was cheap and it would be nice to do some experiments with it. The main problem with this LCD is that it has no (working) library for it. I already searched the whole Internet with Google, but my results were unimpressive: https://forum.crystalfontz.com/showthread.php/7410-Tutorial-ST7920-Seeeduino-v4-2-Arduino-Sample-Sketch-Driving-a-144x32-Graphic-LCD (A huge example code which doesn't work. I set SCK, MISO and CS correctly and nothing happens.) Knowing it has the ST7920 chip, I found a library for screens that use this same chip: https://github.com/olikraus/u8glib/wiki/device#st7920-192x32 (The library supports only other resolutions, such as 128x64, but I think as it's the same chip, it should work too. I also tried other screen variants of this same chip.) On some portuguese site I found how to initialize and use the library properly: http://www.arduinoecia.com.br/2013/09/display-grafico-lcd-128x64-st7920.html (No problem for me, as I speak portuguese too) They use: U8GLIB_ST7920_128X64_1X u8g(6, 5, 4 ,7); to set the software SPI pins for the LCD. On mine (Arduino Mega) it would be: U8GLIB_ST7920_128X64_1X u8g(52, 51, 53); //Enable, RW, RS [,RESET] (known also as) SCK, MOSI, CS The result: The display stayed blank. Then I tried to use the hardware SPI initialization, which according to this site is: U8GLIB_ST7920_128X64_1X u8g(53); // RS (known also as) CS pin needed only Even so, the display won't do anything. It stayed light gray (Contrast adjusted) and that's it. No blinking, no switching on/off, nothing... Finally, I was reading on this datasheet that the PSB pin must be set to 0 (ground) in order to enable SPI mode. Other variants of those screen had jumpers or pins on the back, which you can jump to ground, but this one has none. A high resolution image of the back of the LCD I captured (or atleast tried) and attached below (the front has nothing but the LCD), because I could find nothing about anything of this board. No schematic, nothing. I couldn't find any PSB pin (which is identified as it), jumper ("JP") or similar on this board. The pins to interface the LCD had no unusual pins which are identified as "PSB" or similar too: Any suggestion or answer is much appreciated. AI: Many LCD controllers (including the ST7920) can support a variety of interface types, of which you can use one at a time. Sometimes the interface type is fixed on a given LCD display module; sometimes the interface can be selected. The exact PCB markings for selecting between interfaces (when possible) does not always match the signal names you are expecting. Since the interface is not always able to be selected, then the answer from Finbarr is sometimes correct - you might find that the interface is absolutely fixed (e.g. parallel-only, SPI-only etc.) on a given LCD module. However in your case, I think you might be lucky. I noticed a similarity between your LCD module, and the one used in the first tutorial which you linked. Notice how your LCD module has the part number 14432D on the back, and we see 2 component locations - R11 and R12. R11 is missing and R12 is fitted: Now look at this image from the first tutorial that you linked, showing the back of that LCD module (which is different to your LCD module, and hence there is no guarantee that the first tutorial you linked would apply to your LCD module anyway). See that it has the same component arrangement as your LCD module and also has an R11 and R12. Except on that module, R11 is fitted and R12 is missing: I cannot guarantee that this next part applies to your LCD module - you need its datasheet with the relevant details to be completely sure. However it is possible that the answer is contained in this document: Notice how for their model number ending 14432D (similar to your model number), the resistors R11 and R12 are used to select between parallel and SPI interfaces. On the LCD module in your first tutorial link, see how only R11 is fitted, and they are using the SPI interface. On your LCD module, see how only R12 is fitted and you are unable to use the SPI interface pinout as shown in that tutorial. So perhaps your LCD module is configured for a parallel interface? That would be consistent with the fact that R12 is fitted on your LCD module. Therefore perhaps by desoldering R12 from your board and resoldering it in the R11 position, you may be able to use the SPI interface and pinout shown in that first tutorial. Update: Here is the PCB after Fusseldieb made the modification (the resistor was moved from the R12 position, to the R11 position): That modification was confirmed to successfully enable the SPI interface, using the following connector pins: LCD Pin SPI signal (Original) ------- ---------- ---------- 1 Vdd (Vdd) 2 Vss (Vss) 3 Vo (Vo) 4 CS (SS) (RS) 5 MOSI (R/W) 6 SCLK (E) FYI, looking at the other tutorial: http://www.arduinoecia.com.br/2013/09/display-grafico-lcd-128x64-st7920.html That uses an LCD module with a completely different interface pinout, which includes the CS1 and CS2 signals (pins 15 & 16 on its 20-pin connector). This allows the interface to be switched between parallel and SPI without needing to solder/desolder components on the PCB. You don't have that 20-pin connector with those signals on your LCD module. That is why that tutorial does not directly apply to your module (although the ST7920 commands will likely apply, once you can get an SPI interface working on your specific LCD module).
H: IR Barrier with a 555 I'm trying to build an IR Barrier with an 555, a sfh4547 and a tssp58038. Here are the datasheets: http://www.ti.com/lit/ds/symlink/ne555.pdf https://www.osram-os.com/Graphics/XPic0/00209793_0.pdf/SFH%204547.pdf http://www.vishay.com/docs/82479/tssp58038.pdf This is the schematic of the emitter: An this is the schematic of the receiver: I have tested that the emitter has a frequency near 38khz but always have a 5v output in pin 1 of the tssp58038. I don't know how to make it work. Update: Osciloscope at 1v and 5us. This is the NE555 output: This is the base of the Q1: This is between Q1 and D1: This is between D1 and R5: AI: Мost infrared sensors, do not respond very well to a continuous incidence of infrared light. Switching the IR source off, even for a small period, allows IR detectors to ‘recuperate’, and so optimise their ability to minimize the response to ambient light. Try to use a modulated signal. Example.
H: Can single-sideband (SSB) be used with PSK, QAM or APSK? I got this question while considering the Nyquist no-ISI criterion, the consequence of which is that if we send one baseband symbol every T (time) then unless the bandwidth B of the channel is at least 1/2T it is inevitable that there will be inter-symbol interference. That is to say, the highest possible ISI-free symbol-rate in a baseband channel of bandwidth B is 2B. Then, if we multiply this baseband signal with a carrier frequency f, then the spectrum of the resulting signal is shifted right by f, but since the 'negative frequency' portion of the baseband signal also shifts right, it results in a signal that spans from f-B to f+B, and thus has a bandwidth of 2B. Which seems to indicate that in case of a bandpass channel of bandwidth B the highest possible ISI-free symbol rate is B. My question is, what compels us to transmit the frequency-shifted version of the negative frequency part? In amplitude modulation we can have SSB (single sideband) transmission, where either the upper or the lower sideband is not transmitted: why isn't this done for digital modulation methods like PSK, QAM or APSK? If it could be done, the maximum possible symbol rate in a bandpass channel of bandwidth B would have been 2B which is a good thing, so I assume there are sound mathematical reasons as to why suppressing either one of the sidebands would stop us from successfully demodulating the signal. Any pointers as to what they may be? AI: My question is, what compels us to transmit the frequency-shifted version of the negative frequency part? Indeed, nothing compels us to do so. Transmitting the same (baseband) signal twice is inefficient, it unnecessarily doubles the use of frequency space. why isn't this done for digital modulation methods like PSK, QAM or APSK? What makes you think it is not done ? The modulation does not matter so you can add OFDM to the list. Actually SSB is a bit "old hat". What is done with modern modulation techniques like OFDM, OFDMA is that a baseband signal is created using digital signal processing. This digital signal is then converted into an analog signal by an AD converter (ADC). OK, I lied, two of those actually. That gives us two analog signals. These are called quadrature signals. The essence of this signal (consisting of an I and a Q component) is that it has negative and positive frequencies ! Negative frequencies ? Huh, you must be joking ! No I'm not, a negative frequency simply relates to the phase of a signal. If you have only one signal, you cannot determine the phase because a phase is always relative. Now I hope you see why we need two signals because then I can "play" with the phase and make negative frequencies ! This quadrature signal can then be mixed (in a quadrature mixer !) with an RF carrier and transmitted. If we would start with a baseband signal of 10 MHz wide it would exist between -5 MHz and + 5 MHz and after mixing it with a carrier of 1000 MHz it would occupy 995 MHz to 1005 MHz. That's what is used in GSM, UMTS, CDMA, Wifi, nearly all modern digital communication standards use this.
H: Using triac as a tripping device Can i use DC Voltage (5DCV or more?) to trip the Gate of a Triac BTA series Transistor to connect Terminal 1 and Terminal 2 completing the circuit? AI: Yes, but you need a resistor in series with the gate to limit the current. Read the data sheet to find the gate voltage at the desired trigger current. Make sure to give it enough current for all the applicable quadrants and for low temperature and worst-case sensitivity. Usually negative current is better, or necessary in cases where quadrant III operation (positive gate current, negative MT2 bias) is not guaranteed. That will turn the triac on. It will not shut off until current drops to below the holding current and the gate current is removed.
H: Dual Feedback Transistor Biasing a Common Emitter Amplifier I was reviewing/following a tutorial describing the pros/cons of various transistor base biasing configurations. Configuration #4 is shown above. Resistor Rb2 was added to what was previously Configuration #3. The circuit with the text is shown below (in quotes).... Why does adding Rb2 increase stability with respect to variations in Beta, ( β ) by increasing the current flowing through the base biasing resistors? The unclear (to me) original text is below. Thanks "Adding an additional resistor to the base bias network of the previous configuration improves stability even more with respect to variations in Beta, ( β ) by increasing the current flowing through the base biasing resistors. The current flowing through RB1 is generally set at a value equal to about 10% of collector current, IC. Obviously it must also be greater than the base current required for the minimum value of Beta, β. One of the advantages of this type of self biasing configuration is that the resistors provide both automatic biasing and Rf feedback at the same time." AI: Why does adding Rb2 increase stability with respect to variations in Beta That's not difficult to see. Adding Rb2 would "steal" some current from the base of the NPN, so to prevent that we decrease the value of Rb1 such that it provides extra current. Now if the base current is 1 uA and we make 100 uA flow through Rb1 that leaves 99 uA for Rb2. If now for some reason beta is halved, the base current would become 2 uA. So now 98 uA flows through Rb2. Thatś not much of a difference now is it ? Compare that to the situation where Ib = 1 uA but Rb1 provides only 2 uA so for Rb2 thereś only 1 uA left. Now if beta halves there would be zero current left for Rb2. That would not actually happen of course, it would settle somewhere in the middle. But notice how by "wasting" current through Rb1, Rb2 I can basically ignore what happens to the base current and therefore beta as well. For small signals adding Rb2 also has an advantage as Rb2 with Rb1 forms a voltage divider controlling how much of the output signal is fed-back. Without Rb2 there will only be the internal small signal input resistance of the NPN, it has value beta/gm. Note how beta is in there again ! By adding Rb2 and making it much lower value than beta/gm Rb2 "takes over" and allows us to have more control and also making the influence of beta smaller.
H: Can a vacuum tube Triode increase the voltage in a circuit above the voltage rating of the batteries in the circuit? I guess this will take a little explanation. I have not mastered the "sketching" used on this website yet. The triode in question has one plate circuit connected to a 90 volt battery and the filament voltage creating the space charge is 1.5 volts. This tube is not using the third connection of the triode. In essence the batteries are in series. In this simple connection is there any conceivable way that the total voltage can exceed the sum of the two batteries in the circuit. I believe the schematic I am viewing has a mistake. Thank you. AI: Funnily enough, the total voltage range can slightly exceed the battery voltages. Firstly the space charge is negative, so that unused third connection may float to a few volts negative with respect to the cathode. In early battery operated vacuum tube circuits, this voltage (which tends to reduce the anode current) is controlled by providing a conducting path to ground with a "grid leak" resistance - usually in the megohm range, since grid current is in the microamp range. Secondly, in an RF circuit, the load is often an inductor, either the primary of a transformer or an RF choke. Then the mean anode (plate) voltage is the battery voltage, but there is AC superimposed on that, so the peak voltage exceeds the battery voltage. This is essentially, as @pjc50 says, happens in a boost converter (which then rectifies those peaks). Whether these apply to your schematic ... well, show us the schematic!

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