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# -------------------------------------------------------------------------
# Copyright (c) Microsoft Corporation. All rights reserved.
# --------------------------------------------------------------------------
import sys
from .trace import EventTypes
from .. import utils
logger = utils.get_logger()
class BaseNode:
def __init__(self):
self.name = None
self.start_time = None
self.end_time = None
self.type = None
self.external_id = None # For consistency check.
class HostNode(BaseNode):
def __init__(self):
super(HostNode, self).__init__()
self.device_duration = 0 # Total time of Kernel, GPU Memcpy, GPU Memset. TODO: parallel multi-stream?
class OperatorNode(HostNode):
def __init__(self):
super(OperatorNode, self).__init__()
self.children = [] # OperatorNode and ProfilerStepNode.
self.runtimes = [] # RuntimeNode
self.input_shape = None
self.self_host_duration = 0
self.self_device_duration = 0
def fill_stats(self):
self.self_host_duration = self.end_time - self.start_time
for child in self.children:
self.device_duration += child.device_duration
# To be consistent with pytorch autograd profiler.Include child Runtime time as self time.
self.self_host_duration -= (child.end_time - child.start_time)
for rt in self.runtimes:
self.device_duration += rt.device_duration
self.self_device_duration += rt.device_duration
class ProfilerStepNode(OperatorNode):
def __init__(self):
super(ProfilerStepNode, self).__init__()
class RuntimeNode(HostNode):
def __init__(self):
super(RuntimeNode, self).__init__()
# One runtime could trigger more than one kernel, such as cudaLaunchCooperativeKernelMultiDevice.
self.device_nodes = None
def fill_stats(self):
if self.device_nodes is None:
return
for device_node in self.device_nodes:
self.device_duration += device_node.end_time - device_node.start_time
class DeviceNode(BaseNode):
def __init__(self):
super(DeviceNode, self).__init__()
self.op_node = None # The cpu operator that launched it.
class OperatorAgg:
def __init__(self):
self.name = None
self.input_shape = None # Optional
self.calls = 0
self.host_duration = 0
self.device_duration = 0
self.self_host_duration = 0
self.self_device_duration = 0
# TODO: Think about adding these avgs to UI.
self.avg_host_duration = 0
self.avg_device_duration = 0
def average(self):
self.avg_host_duration = self.host_duration / self.calls
self.avg_device_duration = self.device_duration / self.calls
class KernelAggByNameOp:
def __init__(self):
self.name = None
self.op_name = None
self.calls = 0
self.total_duration = 0
self.avg_duration = 0
self.min_duration = sys.maxsize
self.max_duration = 0
def average(self):
self.avg_duration = self.total_duration / self.calls
class ModuleParser:
def __init__(self):
self.tid2tree = {}
self.cpp_op_list = [] # For Operator-view.
self.kernel_list = [] # For Kernel-view.
self.op_list_groupby_name = [] # For Operator-view.
self.op_list_groupby_name_input = [] # For Operator-view.
self.kernel_list_groupby_name_op = {} # For Kernel-view.
# host_node_list: list of OperatorNode and ProfilerStepNode.
# zero_rt_list: list of RuntimeNode with external_id=0.
def _build_tree(self, host_node_list, zero_rt_list):
def build_tree_relationship(host_node_list, zero_rt_list):
node_stack = []
root_node = OperatorNode()
root_node.start_time = -sys.maxsize - 1
root_node.end_time = sys.maxsize
root_node.runtimes = zero_rt_list # Give the list of RuntimeNode with external_id=0 to root node.
node_stack.append(root_node)
for node in host_node_list:
while True: # break loop when the node is inserted.
tail_node = node_stack[-1]
if node.start_time < tail_node.end_time:
if node.end_time <= tail_node.end_time:
tail_node.children.append(node)
node_stack.append(node)
else:
logger.error("Error in input data: ranges on the same thread should not intersect!"
"Father:({},{},{}) Child:({},{},{})".format(
tail_node.name, tail_node.start_time, tail_node.end_time,
node.name, node.start_time, node.end_time
))
break
else:
node_stack.pop()
root_node.name = "CallTreeRoot"
root_node.type = EventTypes.PYTHON
return root_node
# Merge the consecutive calls to same function into one.
# Just follow the same pattern in torch/autograd/profiler.py,
# EventList._remove_dup_nodes
# TODO: Replace recursive by for loop, in case of too deep callstack.
def remove_dup_nodes(node):
if node.type == EventTypes.RUNTIME:
return
if len(node.children) == 1:
child = node.children[0]
if node.name == child.name and node.type == EventTypes.OPERATOR and child.type == EventTypes.OPERATOR:
node.children = child.children
node.runtimes = child.runtimes # Keep consistent with autograd profiler.
remove_dup_nodes(node) # This node may have to merge with child's child.
for child in node.children:
remove_dup_nodes(child)
# TODO: Replace recursive by using a stack, in case of too deep callstack.
def fill_stats(node):
if node.type != EventTypes.RUNTIME:
for child in node.children:
fill_stats(child)
for rt in node.runtimes:
fill_stats(rt)
if rt.device_nodes is not None:
for device_node in rt.device_nodes:
device_node.op_node = node
if node.name == "CallTreeRoot":
node.start_time = node.end_time = None
for i in range(len(node.children)):
if node.children[i].start_time is not None:
node.start_time = node.children[i].start_time
break
for i in range(len(node.children) - 1, -1, -1):
if node.children[i].end_time is not None:
node.end_time = node.children[i].end_time
break
node.fill_stats()
if type(node) is OperatorNode and node.type == EventTypes.OPERATOR \
and not (node.name.startswith("enumerate(DataLoader)#") and node.name.endswith(".__next__")) \
and not node.name.startswith("Optimizer."):
self.cpp_op_list.append(node)
if node.type == EventTypes.RUNTIME and node.device_nodes is not None:
self.kernel_list.extend([n for n in node.device_nodes if n.type == EventTypes.KERNEL])
root_node = build_tree_relationship(host_node_list, zero_rt_list)
remove_dup_nodes(root_node)
fill_stats(root_node)
return root_node
def parse_events(self, events):
def parse_event(event, corrid_to_device, corrid_to_runtime, externalid_to_runtime, tid2list, tid2zero_rt_list):
def build_node(node, event):
node.name = event.name
node.start_time = event.ts
node.end_time = event.ts + event.duration
node.type = event.type
if "external id" in event.args:
node.external_id = event.args["external id"]
elif "External id" in event.args:
node.external_id = event.args["External id"]
corrid = event.args["correlation"] if "correlation" in event.args else None
input_shape = event.args["Input dims"] if "Input dims" in event.args else None
tid = event.tid
if event.type in [EventTypes.KERNEL, EventTypes.MEMCPY, EventTypes.MEMSET]:
device_node = DeviceNode()
build_node(device_node, event)
if corrid in corrid_to_runtime:
rt_node = corrid_to_runtime[corrid] # Don't pop it because it may be used by next kernel.
if rt_node.device_nodes is None:
rt_node.device_nodes = [device_node]
else:
rt_node.device_nodes.append(device_node)
if rt_node.external_id != device_node.external_id:
logger.warning(
"Runtime and Device-op have same correlation id but with different external id!"
)
else:
if corrid not in corrid_to_device:
corrid_to_device[corrid] = [device_node]
else:
corrid_to_device[corrid].append(device_node)
elif event.type == EventTypes.RUNTIME:
rt_node = RuntimeNode()
build_node(rt_node, event)
corrid_to_runtime[corrid] = rt_node
if corrid in corrid_to_device:
rt_node.device_nodes = []
rt_node.device_nodes.extend(corrid_to_device[corrid])
for device_node in corrid_to_device[corrid]:
if rt_node.external_id != device_node.external_id:
logger.warning(
"Runtime and Device-op have same correlation id but with different external id!"
)
if rt_node.external_id in externalid_to_runtime:
externalid_to_runtime[rt_node.external_id].append(rt_node)
else:
externalid_to_runtime[rt_node.external_id] = [rt_node]
# Some runtimes has external_id 0, which will not be correlated to any operator.
# So get them and attach them to root node.
if rt_node.external_id == 0:
if tid not in tid2zero_rt_list:
tid2zero_rt_list[tid] = []
tid2zero_rt_list[tid].append(rt_node)
elif event.type in [EventTypes.PYTHON, EventTypes.OPERATOR, EventTypes.PROFILER_STEP]:
if event.type == EventTypes.PROFILER_STEP:
op_node = ProfilerStepNode()
else:
op_node = OperatorNode()
build_node(op_node, event)
op_node.input_shape = input_shape
if tid not in tid2list:
tid2list[tid] = []
tid2list[tid].append(op_node)
def parse_ops(cpp_op_list):
def aggregate(key_to_agg, key, op):
if key not in key_to_agg:
key_to_agg[key] = OperatorAgg()
agg = key_to_agg[key]
agg.name = op.name
agg.input_shape = str(op.input_shape)
agg.calls += 1
agg.host_duration += op.end_time - op.start_time
agg.device_duration += op.device_duration
agg.self_host_duration += op.self_host_duration
agg.self_device_duration += op.self_device_duration
return agg
name_to_agg = {}
for op in cpp_op_list:
agg = aggregate(name_to_agg, op.name, op)
for _, agg in name_to_agg.items():
agg.average()
op_list_groupby_name = list(name_to_agg.values())
name_input_to_agg = {}
for op in cpp_op_list:
name_input = op.name + "###" + str(op.input_shape)
agg = aggregate(name_input_to_agg, name_input, op)
for _, agg in name_input_to_agg.items():
agg.average()
op_list_groupby_name_input = list(name_input_to_agg.values())
return op_list_groupby_name, op_list_groupby_name_input
def parse_kernels(kernel_list):
name_op_to_agg = {}
for kernel in kernel_list:
key = kernel.name + "###" + kernel.op_node.name
if key not in name_op_to_agg:
name_op_to_agg[key] = KernelAggByNameOp()
agg = name_op_to_agg[key]
agg.name = kernel.name
agg.op_name = kernel.op_node.name
agg.calls += 1
dur = kernel.end_time - kernel.start_time
agg.total_duration += dur
agg.min_duration = min(agg.min_duration, dur)
agg.max_duration = max(agg.max_duration, dur)
for _, agg in name_op_to_agg.items():
agg.average()
kernel_list_groupby_name_op = list(name_op_to_agg.values())
return kernel_list_groupby_name_op
# For OperatorNode and ProfilerStepNode:
# Use time interval containing relationship to build father-child correlation,
# which is consistent with autograd profiler.
# For RuntimeNode:
# Use external_id to build correlation with its father OperatorNode or ProfilerStepNode.
# Because in the case when RuntimeNode has duration 0 and starts at same time as a OperatorNode,
# just use interval containing relationship can't tell it is child or brother of the OperatorNode.
tid2list = {} # value is a list of OperatorNode and ProfilerStepNode. Do not include RuntimeNode
tid2zero_rt_list = {} # value is a list of RuntimeNode with external_id=0. They will be attached to root nodes.
corrid_to_device = {} # value is a list of DeviceNode
corrid_to_runtime = {} # value is a RuntimeNode
externalid_to_runtime = {} # value is a list of RuntimeNode
for event in events:
parse_event(event, corrid_to_device, corrid_to_runtime, externalid_to_runtime, tid2list, tid2zero_rt_list)
# associate CUDA Runtimes with CPU events
for _, op_list in tid2list.items():
for op in op_list:
if op.external_id in externalid_to_runtime:
op.runtimes.extend(externalid_to_runtime[op.external_id])
del externalid_to_runtime[op.external_id]
for ext_id in externalid_to_runtime:
if ext_id != 0:
logger.warning("{} Runtime with external id {} don't correlate to any operator!".format(
len(externalid_to_runtime[ext_id]), ext_id))
for tid, op_list in tid2list.items():
zero_rt_list = tid2zero_rt_list[tid] if tid in tid2zero_rt_list else []
# Note that when 2 start_time are equal, the one with bigger end_time should be ahead of the other.
op_list.sort(key=lambda x: (x.start_time, -x.end_time))
root_node = self._build_tree(op_list, zero_rt_list)
self.tid2tree[tid] = root_node
self.op_list_groupby_name, self.op_list_groupby_name_input = parse_ops(self.cpp_op_list)
self.kernel_list_groupby_name_op = parse_kernels(self.kernel_list)
|
#!/usr/bin/env python
import distutils.log
from distutils.command.build import build
from setuptools.command.develop import develop
from distutils.cmd import Command
from setuptools import setup
def read_text_file(path):
import os
with open(os.path.join(os.path.dirname(__file__), path)) as f:
return f.read()
class BuildGenerateInstructions(build):
def run(self):
self.run_command("generate")
build.run(self)
class DevelopGenerateInstructions(develop):
def run(self):
self.run_command("generate")
develop.run(self)
class GenerateInstructions(Command):
description = "Generate PeachPy instructions from Opcodes DB"
user_options = []
def initialize_options(self):
pass
def finalize_options(self):
pass
def run(self):
# package_dir may be None, in that case use the current directory.
import os
if not self.distribution.package_dir:
src_dir = os.getcwd()
else:
src_dir = os.path.abspath(self.distribution.package_dir[""])
# Run code-generation script
import opcodes
self.announce("Generating x86-64 instruction classes from opcodes %s" % opcodes.__version__,
level=distutils.log.INFO)
import codegen.x86_64
codegen.x86_64.main(src_dir)
setup(
name="PeachPy",
version="0.2.0",
description="Portable Efficient Assembly Codegen in Higher-level Python",
author="Marat Dukhan",
author_email="[email protected]",
url="https://github.com/Maratyszcza/PeachPy/",
packages=["peachpy", "peachpy.c",
"peachpy.common", "peachpy.x86_64", "peachpy.arm",
"peachpy.formats", "peachpy.formats.elf", "peachpy.formats.macho", "peachpy.formats.mscoff"],
keywords=["assembly", "codegen", "x86-64"],
long_description=read_text_file("README.rst"),
classifiers=[
"Development Status :: 3 - Alpha",
"Intended Audience :: Developers",
"Intended Audience :: Science/Research",
"License :: OSI Approved :: BSD License",
"Operating System :: OS Independent",
"Operating System :: Microsoft :: Windows",
"Operating System :: POSIX :: Linux",
"Operating System :: POSIX :: FreeBSD",
"Operating System :: MacOS :: MacOS X",
"Programming Language :: Assembly",
"Programming Language :: Python",
"Programming Language :: Python :: 2",
"Programming Language :: Python :: 2.7",
"Programming Langauge :: Python :: 3",
"Programming Language :: Python :: 3.2",
"Programming Language :: Python :: 3.3",
"Programming Language :: Python :: 3.4",
"Programming Language :: Python :: 3.5",
"Programming Language :: Python :: Implementation :: CPython",
"Programming Language :: Python :: Implementation :: PyPy",
"Natural Language :: English",
"Topic :: Scientific/Engineering",
"Topic :: Software Development",
"Topic :: Software Development :: Assemblers",
"Topic :: Software Development :: Code Generators",
"Topic :: Software Development :: Compilers",
"Topic :: Software Development :: Libraries"
],
setup_requires=["Opcodes>=0.3.13", "six"],
install_requires=["six", 'enum34;python_version<"3.4"'],
cmdclass={
"build": BuildGenerateInstructions,
"develop": DevelopGenerateInstructions,
"generate": GenerateInstructions,
})
|
import six
from peachpy.c.types import Type, \
int8_t, int16_t, int32_t, int64_t, \
uint8_t, uint16_t, uint32_t, uint64_t, \
float_, double_
from peachpy.parse import parse_assigned_variable_name
from peachpy.name import Name
class Constant:
_supported_sizes = [1, 2, 4, 8, 16, 32, 64]
_supported_types = [uint8_t, uint16_t, uint32_t, uint64_t,
int8_t, int16_t, int32_t, int64_t,
float_, double_]
def __init__(self, size, repeats, data, element_ctype, name):
assert isinstance(size, six.integer_types), "Constant size must be an integer"
assert size in Constant._supported_sizes, "Unsupported size %s: the only supported sizes are %s" \
% (str(size), ", ".join(map(str, sorted(Constant._supported_sizes))))
assert isinstance(repeats, six.integer_types), "The number of contant repeats must be an integer"
assert size % repeats == 0, "The number of constant repeats must divide constant size without remainder"
assert isinstance(element_ctype, Type), "Element type must be an instance of peachpy.c.Type"
assert element_ctype in Constant._supported_types, "The only supported types are %s" \
% ", ".join(Constant._supported_types)
assert isinstance(name, Name)
self.size = size
self.repeats = repeats
self.element_ctype = element_ctype
self.data = data
self.name = (name,)
self.label = None
self.prefix = None
def __str__(self):
format_spec = "%%0%dX" % (self.size / self.repeats * 2)
return "<" + ", ".join(format_spec % data for data in self.data) + ">"
def __hash__(self):
return hash(self.data) ^ hash(self.size) ^ hash(self.repeats)
def __eq__(self, other):
return isinstance(other, Constant) and self.data == other.data and self.element_ctype == other.element_ctype
def encode(self, encoder):
from peachpy.encoder import Encoder
assert isinstance(encoder, Encoder)
encode_function = {
1: encoder.uint8,
2: encoder.uint16,
4: encoder.uint32,
8: encoder.uint64
}[self.size / self.repeats]
return bytearray().join([encode_function(data) for data in self.data])
@property
def alignment(self):
if self.size == 10:
return 16
else:
return self.size
@property
def as_hex(self):
from peachpy.encoder import Encoder, Endianness
bytestring = self.encode(Encoder(Endianness.Little))
return "".join("%02X" % byte for byte in bytestring)
def format(self, assembly_format):
if assembly_format == "go":
return "const0x" + self.as_hex + "(SB)"
else:
return str(self)
@staticmethod
def _uint64xN(name, n, *args):
from peachpy.util import is_int, is_int64
assert is_int(n)
args = [arg for arg in args if arg is not None]
if len(args) == 0:
raise ValueError("At least one constant value must be specified")
if len(args) != 1 and len(args) != n:
raise ValueError("Either 1 or %d values must be specified" % n)
for i, number in enumerate(args):
if not is_int(number):
raise TypeError("The value %s is not an integer" % str(number))
if not is_int64(number):
raise ValueError("The number %d is not a 64-bit integer" % number)
if number < 0:
args[i] += 0x10000000000000000
if len(args) == 1:
args = [args[0]] * n
return Constant(8 * n, n, tuple(args), uint64_t, name)
@staticmethod
def _uint32xN(name, n, *args):
from peachpy.util import is_int, is_int32
assert is_int(n)
args = [arg for arg in args if arg is not None]
if len(args) == 0:
raise ValueError("At least one constant value must be specified")
if len(args) != 1 and len(args) != n:
raise ValueError("Either 1 or %d values must be specified" % n)
for i, number in enumerate(args):
if not is_int(number):
raise TypeError("The value %s is not an integer" % str(number))
if not is_int32(number):
raise ValueError("The number %d is not a 32-bit integer" % number)
if number < 0:
args[i] += 0x100000000
if len(args) == 1:
args = [args[0]] * n
return Constant(4 * n, n, tuple(args), uint32_t, name)
@staticmethod
def _uint16xN(name, n, *args):
from peachpy.util import is_int, is_int32
assert is_int(n)
args = [arg for arg in args if arg is not None]
if len(args) == 0:
raise ValueError("At least one constant value must be specified")
if len(args) != 1 and len(args) != n:
raise ValueError("Either 1 or %d values must be specified" % n)
for i, number in enumerate(args):
if not is_int(number):
raise TypeError("The value %s is not an integer" % str(number))
if not is_int32(number):
raise ValueError("The number %d is not a 16-bit integer" % number)
if number < 0:
args[i] += 0x100000000
if len(args) == 1:
args = [args[0]] * n
return Constant(2 * n, n, tuple(args), uint32_t, name)
@staticmethod
def _float64xN(name, n, *args):
args = [arg for arg in args if arg is not None]
if len(args) == 0:
raise ValueError("At least one constant value must be specified")
if len(args) != 1 and len(args) != n:
raise ValueError("Either 1 or %d values must be specified" % n)
args = [Constant._parse_float64(arg) for arg in args]
if len(args) == 1:
args = [args[0]] * n
return Constant(8 * n, n, tuple(args), double_, name)
@staticmethod
def _float32xN(name, n, *args):
args = [arg for arg in args if arg is not None]
if len(args) == 0:
raise ValueError("At least one constant value must be specified")
if len(args) != 1 and len(args) != n:
raise ValueError("Either 1 or %d values must be specified" % n)
args = [Constant._parse_float32(arg) for arg in args]
if len(args) == 1:
args = [args[0]] * n
return Constant(4 * n, n, tuple(args), double_, name)
@staticmethod
def uint64(number, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint64"))
return Constant._uint64xN(name, 1, number)
@staticmethod
def uint64x2(number1, number2=None, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint64x2"))
return Constant._uint64xN(name, 2, number1, number2)
@staticmethod
def uint64x4(number1, number2=None, number3=None, number4=None, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint64x4"))
return Constant._uint64xN(name, 4, number1, number2, number3, number4)
@staticmethod
def uint64x8(number1, number2=None, number3=None, number4=None,
number5=None, number6=None, number7=None, number8=None,
name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint64x8"))
return Constant._uint64xN(name, 8,
number1, number2, number3, number4, number5, number6, number7, number8)
@staticmethod
def uint32(number, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint32"))
return Constant._uint32xN(name, 1, number)
@staticmethod
def uint32x2(number1, number2=None, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint32x2"))
return Constant._uint32xN(name, 2, number1, number2)
@staticmethod
def uint32x4(number1, number2=None, number3=None, number4=None, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint32x4"))
return Constant._uint32xN(name, 4, number1, number2, number3, number4)
@staticmethod
def uint32x8(number1, number2=None, number3=None, number4=None,
number5=None, number6=None, number7=None, number8=None,
name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint32x8"))
return Constant._uint32xN(name, 8,
number1, number2, number3, number4, number5, number6, number7, number8)
@staticmethod
def uint32x16(number1, number2=None, number3=None, number4=None,
number5=None, number6=None, number7=None, number8=None,
number9=None, number10=None, number11=None, number12=None,
number13=None, number14=None, number15=None, number16=None,
name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint32x16"))
return Constant._uint32xN(name, 16,
number1, number2, number3, number4, number5, number6, number7, number8,
number9, number10, number11, number12, number13, number14, number15, number16)
@staticmethod
def uint16x8(number1, number2=None, number3=None, number4=None,
number5=None, number6=None, number7=None, number8=None,
name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint16x8"))
return Constant._uint16xN(name, 8,
number1, number2, number3, number4, number5, number6, number7, number8)
@staticmethod
def uint16x16(number1, number2=None, number3=None, number4=None,
number5=None, number6=None, number7=None, number8=None,
number9=None, number10=None, number11=None, number12=None,
number13=None, number14=None, number15=None, number16=None,
name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.uint16x16"))
return Constant._uint16xN(name, 16,
number1, number2, number3, number4, number5, number6, number7, number8,
number9, number10, number11, number12, number13, number14, number15, number16)
@staticmethod
def float64(number, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.float64"))
return Constant._float64xN(name, 1, number)
@staticmethod
def float64x2(number1, number2=None, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.float64x2"))
return Constant._float64xN(name, 2, number1, number2)
@staticmethod
def float64x4(number1, number2=None, number3=None, number4=None, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.float64x4"))
return Constant._float64xN(name, 4, number1, number2, number3, number4)
@staticmethod
def float32(number, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.float32"))
return Constant._float32xN(name, 1, number)
@staticmethod
def float32x2(number1, number2=None, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.float32x2"))
return Constant._float32xN(name, 2, number1, number2)
@staticmethod
def float32x4(number1, number2=None, number3=None, number4=None, name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.float32x4"))
return Constant._float32xN(name, 4, number1, number2, number3, number4)
@staticmethod
def float32x8(number1, number2=None, number3=None, number4=None,
number5=None, number6=None, number7=None, number8=None,
name=None):
if name is not None:
Name.check_name(name)
name = Name(name=name)
else:
import inspect
name = Name(prename=parse_assigned_variable_name(inspect.stack(), "Constant.float32x8"))
return Constant._float32xN(name, 8,
number1, number2, number3, number4, number5, number6, number7, number8)
@staticmethod
def _convert_to_float32(number):
import array
float_array = array.array('f', [number])
return float_array[0]
@staticmethod
def _parse_float32(number):
if isinstance(number, float):
number = float.hex(Constant._convert_to_float32(number))
elif isinstance(number, str):
# Validity check
try:
number = float.hex(Constant._convert_to_float32(float.fromhex(number)))
except ValueError:
raise ValueError("The string %s is not a hexadecimal floating-point number" % number)
else:
raise TypeError("Unsupported type of constant number %s" % str(number))
if number == "inf" or number == "+inf":
return 0x7F800000
elif number == "-inf":
return 0xFF800000
elif number == "nan":
return 0x7FC00000
is_negative = number.startswith("-")
point_position = number.index('.')
exp_position = number.rindex('p')
number_prefix = number[int(is_negative):point_position]
assert number_prefix == '0x0' or number_prefix == '0x1'
mantissa = number[point_position + 1:exp_position]
if number_prefix == '0x0' and int(mantissa) == 0:
# Zero
return int(is_negative) << 31
else:
exponent = number[exp_position + 1:]
mantissa_bits = len(mantissa) * 4
if mantissa_bits == 23:
mantissa = int(mantissa, 16)
elif mantissa_bits < 23:
mantissa = int(mantissa, 16) << (23 - mantissa_bits)
else:
mantissa = int(mantissa, 16) >> (mantissa_bits - 23)
exponent = int(exponent)
if exponent <= -127:
# Denormals
mantissa = (mantissa + (1 << 23)) >> -(exponent + 126)
exponent = -127
return mantissa + (int(exponent + 127) << 23) + (int(is_negative) << 31)
@staticmethod
def _parse_float64(number):
if isinstance(number, float):
number = float.hex(number)
elif isinstance(number, str):
# Validity check
try:
number = float.hex(float.fromhex(number))
except ValueError:
raise ValueError("The string %s is not a hexadecimal floating-point number" % number)
else:
raise TypeError("Unsupported type of constant number %s" % str(number))
if number == "inf" or number == "+inf":
return 0x7FF0000000000000
if number == "-inf":
return 0xFFF0000000000000
if number == "nan":
return 0x7FF8000000000000
is_negative = number.startswith("-")
point_position = number.index('.')
exp_position = number.rindex('p')
number_prefix = number[int(is_negative):point_position]
assert number_prefix == '0x0' or number_prefix == '0x1'
mantissa = number[point_position + 1:exp_position]
if number_prefix == '0x0':
# Zero
assert int(mantissa) == 0
return int(is_negative) << 63
else:
exponent = number[exp_position + 1:]
mantissa_bits = len(mantissa) * 4
if mantissa_bits == 52:
mantissa = int(mantissa, 16)
elif mantissa_bits < 52:
mantissa = int(mantissa, 16) << (52 - mantissa_bits)
else:
mantissa = int(mantissa, 16) >> (mantissa_bits - 52)
exponent = int(exponent)
if exponent <= -1023:
# Denormals
mantissa = (mantissa + (1 << 52)) >> -(exponent + 1022)
exponent = -1023
elif exponent > 1023:
# Infinity
mantissa = 0
exponent = 1023
return mantissa + (int(exponent + 1023) << 52) + (int(is_negative) << 63)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import six
def int_size(n):
assert is_int64(n)
if is_int8(n):
return 1
elif is_int16(n):
return 2
elif is_int32(n):
return 4
else:
return 8
def is_int(n):
return isinstance(n, six.integer_types)
def is_int64(n):
return isinstance(n, six.integer_types) and -9223372036854775808 <= n <= 18446744073709551615
def is_sint64(n):
return isinstance(n, six.integer_types) and -9223372036854775808 <= n <= 9223372036854775807
def is_uint64(n):
return isinstance(n, six.integer_types) and 0 <= n <= 18446744073709551615
def is_int32(n):
return isinstance(n, six.integer_types) and -2147483648 <= n <= 4294967295
def is_sint32(n):
return isinstance(n, six.integer_types) and -2147483648 <= n <= 2147483647
def is_uint32(n):
return isinstance(n, six.integer_types) and 0 <= n <= 4294967295
def is_int16(n):
return isinstance(n, six.integer_types) and -32768 <= n <= 65535
def is_sint16(n):
return isinstance(n, six.integer_types) and -32768 <= n <= 32767
def is_uint16(n):
return isinstance(n, six.integer_types) and 0 <= n <= 65535
def is_int8(n):
return isinstance(n, six.integer_types) and -128 <= n <= 255
def is_uint8(n):
return isinstance(n, six.integer_types) and 0 <= n <= 255
def is_sint8(n):
return isinstance(n, six.integer_types) and -128 <= n <= 127
def roundup(n, q):
import math
return int(math.ceil(float(n) / float(q)) * q)
def ilog2(n):
if n & (n - 1) != 0:
raise ValueError("%u is not an power of 2" % n)
if n == 0:
return 0
else:
l = 0
while n != 1:
l += 1
n >>= 1
return l
def unique(seq):
seq_values = set()
unique_seq = []
for value in seq:
if value not in seq_values:
seq_values.add(value)
unique_seq.append(value)
return unique_seq
def append_unique(value, sequence=None):
if sequence is None:
return [value]
else:
if value not in sequence:
sequence.append(value)
return sequence
def pairwise(iterable):
import itertools
a, b = itertools.tee(iterable)
next(b, None)
return itertools.izip(a, b)
def diff(sequence):
import operator
return map(operator.__sub__, pairwise(sequence))
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
__version_info__ = (0, 2, 0)
__version__ = '.'.join(map(str, __version_info__))
from peachpy.stream import InstructionStream
from peachpy.c.types import Type, \
uint8_t, uint16_t, uint32_t, uint64_t, uintptr_t, \
int8_t, int16_t, int32_t, int64_t, intptr_t, \
size_t, ptrdiff_t, \
Float16, Float32, Float64, \
const_uint8_t, const_uint16_t, const_uint32_t, const_uint64_t, const_uintptr_t, \
const_int8_t, const_int16_t, const_int32_t, const_int64_t, const_intptr_t, \
const_size_t, const_ptrdiff_t, \
const_Float16, const_Float32, const_Float64, \
Yep8u, Yep16u, Yep32u, Yep64u, \
Yep8s, Yep16s, Yep32s, Yep64s, \
Yep16f, Yep32f, Yep64f, YepSize, \
const_Yep8u, const_Yep16u, const_Yep32u, const_Yep64u, \
const_Yep8s, const_Yep16s, const_Yep32s, const_Yep64s, \
const_Yep16f, const_Yep32f, const_Yep64f, \
const_YepSize, \
char, wchar_t, \
signed_char, unsigned_char, \
signed_short, unsigned_short, \
signed_int, unsigned_int, \
signed_long, unsigned_long, \
signed_long_long, unsigned_long_long, \
float_, double_, \
const_char, const_wchar_t, \
const_signed_char, const_unsigned_char, \
const_signed_short, const_unsigned_short, \
const_signed_int, const_unsigned_int, \
const_signed_long, const_unsigned_long, \
const_signed_long_long, const_unsigned_long_long, \
const_float_, const_double_, \
ptr, const_ptr
from peachpy.literal import Constant
from peachpy.function import Argument
class RegisterAllocationError(Exception):
pass
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import six
from peachpy.abi import Endianness
class Encoder:
def __init__(self, endianness, bitness=None):
assert endianness in {Endianness.Little, Endianness.Big}
if endianness == Endianness.Little:
self.int16 = Encoder.int16le
self.uint16 = Encoder.uint16le
self.int32 = Encoder.int32le
self.uint32 = Encoder.uint32le
self.int64 = Encoder.int64le
self.uint64 = Encoder.uint64le
else:
self.int16 = Encoder.int16be
self.uint16 = Encoder.uint16be
self.int32 = Encoder.int32be
self.uint32 = Encoder.uint32be
self.int64 = Encoder.int64be
self.uint64 = Encoder.uint64be
self.bitness = bitness
if bitness is not None:
assert bitness in {32, 64}, "Only 32-bit and 64-bit encoders are supported"
if bitness == 32:
self.signed_offset = self.int32
self.unsigned_offset = self.uint32
else:
self.signed_offset = self.int64
self.unsigned_offset = self.uint64
@staticmethod
def int8(n):
"""Converts signed 8-bit integer to bytearray representation"""
assert -128 <= n <= 127, "%u can not be represented as an 8-bit signed integer" % n
return bytearray([n & 0xFF])
@staticmethod
def uint8(n):
"""Converts unsigned 8-bit integer to bytearray representation"""
assert 0 <= n <= 255, "%u can not be represented as an 8-bit unsigned integer" % n
return bytearray([n])
@staticmethod
def int16le(n):
"""Converts signed 16-bit integer to little-endian bytearray representation"""
assert -32768 <= n <= 32767, "%u can not be represented as a 16-bit signed integer" % n
return bytearray([n & 0xFF, (n >> 8) & 0xFF])
@staticmethod
def int16be(n):
"""Converts signed 16-bit integer to big-endian bytearray representation"""
assert -32768 <= n <= 32767, "%u can not be represented as a 16-bit signed integer" % n
return bytearray([n >> 8, (n & 0xFF) & 0xFF])
@staticmethod
def uint16le(n):
"""Converts unsigned 16-bit integer to little-endian bytearray representation"""
assert 0 <= n <= 65535, "%u can not be represented as a 16-bit unsigned integer" % n
return bytearray([n & 0xFF, n >> 8])
@staticmethod
def uint16be(n):
"""Converts unsigned 16-bit integer to big-endian bytearray representation"""
assert 0 <= n <= 65535, "%u can not be represented as a 16-bit unsigned integer" % n
return bytearray([n >> 8, n & 0xFF])
@staticmethod
def int32le(n):
"""Converts signed 32-bit integer to little-endian bytearray representation"""
assert -2147483648 <= n <= 2147483647, "%u can not be represented as a 32-bit signed integer" % n
return bytearray([n & 0xFF, (n >> 8) & 0xFF, (n >> 16) & 0xFF, (n >> 24) & 0xFF])
@staticmethod
def int32be(n):
"""Converts signed 32-bit integer to big-endian bytearray representation"""
assert -2147483648 <= n <= 2147483647, "%u can not be represented as a 32-bit signed integer" % n
return bytearray([(n >> 24) & 0xFF, (n >> 16) & 0xFF, (n >> 8) & 0xFF, n & 0xFF])
@staticmethod
def uint32le(n):
"""Converts unsigned 32-bit integer to little-endian bytearray representation"""
assert 0 <= n <= 4294967295, "%u can not be represented as a 32-bit unsigned integer" % n
return bytearray([n & 0xFF, (n >> 8) & 0xFF, (n >> 16) & 0xFF, n >> 24])
@staticmethod
def uint32be(n):
"""Converts unsigned 32-bit integer to big-endian bytearray representation"""
assert 0 <= n <= 4294967295, "%u can not be represented as a 32-bit unsigned integer" % n
return bytearray([n >> 24, (n >> 16) & 0xFF, (n >> 8) & 0xFF, n & 0xFF])
@staticmethod
def int64le(n):
"""Converts signed 64-bit integer to little-endian bytearray representation"""
assert -9223372036854775808 <= n <= 9223372036854775807, \
"%u can not be represented as a 64-bit signed integer" % n
return bytearray([n & 0xFF, (n >> 8) & 0xFF, (n >> 16) & 0xFF, (n >> 24) & 0xFF,
(n >> 32) & 0xFF, (n >> 40) & 0xFF, (n >> 48) & 0xFF, (n >> 56) & 0xFF])
@staticmethod
def int64be(n):
"""Converts signed 64-bit integer to big-endian bytearray representation"""
assert -9223372036854775808 <= n <= 9223372036854775807, \
"%u can not be represented as a 64-bit signed integer" % n
return bytearray([(n >> 56) & 0xFF, (n >> 48) & 0xFF, (n >> 40) & 0xFF, (n >> 32) & 0xFF,
(n >> 24) & 0xFF, (n >> 16) & 0xFF, (n >> 8) & 0xFF, n & 0xFF])
@staticmethod
def uint64le(n):
"""Converts unsigned 64-bit integer to little-endian bytearray representation"""
assert 0 <= n <= 18446744073709551615, "%u can not be represented as a 64-bit unsigned integer" % n
return bytearray([n & 0xFF, (n >> 8) & 0xFF, (n >> 16) & 0xFF, (n >> 24) & 0xFF,
(n >> 32) & 0xFF, (n >> 40) & 0xFF, (n >> 48) & 0xFF, (n >> 56) & 0xFF])
@staticmethod
def uint64be(n):
"""Converts unsigned 64-bit integer to big-endian bytearray representation"""
assert 0 <= n <= 18446744073709551615, "%u can not be represented as a 64-bit unsigned integer" % n
return bytearray([(n >> 56) & 0xFF, (n >> 48) & 0xFF, (n >> 40) & 0xFF, (n >> 32) & 0xFF,
(n >> 24) & 0xFF, (n >> 16) & 0xFF, (n >> 8) & 0xFF, n & 0xFF])
def int16(self, n):
"""Converts signed 16-bit integer to bytearray representation according to encoder endianness"""
pass
def uint16(self, n):
"""Converts unsigned 16-bit integer to bytearray representation according to encoder endianness"""
pass
def int32(self, n):
"""Converts signed 32-bit integer to bytearray representation according to encoder endianness"""
pass
def uint32(self, n):
"""Converts unsigned 32-bit integer to bytearray representation according to encoder endianness"""
pass
def int64(self, n):
"""Converts signed 64-bit integer to bytearray representation according to encoder endianness"""
pass
def uint64(self, n):
"""Converts unsigned 64-bit integer to bytearray representation according to encoder endianness"""
pass
@staticmethod
def fixed_string(string, size):
"""Converts string to fixed-length bytearray representation"""
assert isinstance(size, six.integer_types) and size > 0, "size %u is not a positive integer" % size
if string is None:
return bytearray(size)
import codecs
byte_string = codecs.encode(string, "utf8")
if len(byte_string) > size:
raise ValueError("The length of %s exceeds the target %d" % (string, size))
elif len(byte_string) == size:
return byte_string
else:
return byte_string + bytearray(size - len(byte_string))
def signed_offset(self, n):
"""Converts signed integer offset to bytearray representation according to encoder bitness and endianness"""
raise ValueError("Can not encode signed offset: encoder bitness not specified")
def unsigned_offset(self, n):
"""Converts unsigned integer offset to bytearray representation according to encoder bitness and endianness"""
raise ValueError("Can not encode unsigned offset: encoder bitness not specified")
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
active_stream = None
class InstructionStream(object):
def __init__(self):
self.instructions = list()
self.previous_stream = None
def __enter__(self):
global active_stream
self.previous_stream = active_stream
active_stream = self
return self
def __exit__(self, exc_type, exc_value, traceback):
global active_stream
active_stream = self.previous_stream
self.previous_stream = None
def __iter__(self):
return iter(self.instructions)
def __len__(self):
return len(self.instructions)
def __getitem__(self, i):
try:
return self.instructions[i]
except IndexError:
return None
def add_instruction(self, instruction):
if instruction is not None:
self.instructions.append(instruction)
def issue(self, count=1):
for i in range(count):
if self.instructions:
active_stream.add_instruction(self.instructions.pop(0))
class NullStream:
def __init__(self):
self.previous_stream = None
def __enter__(self):
global active_stream
self.previous_stream = active_stream
active_stream = None
return self
def __exit__(self, exc_type, exc_value, traceback):
global active_stream
active_stream = self.previous_stream
self.previous_stream = None
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy import Constant, ConstantBucket, RegisterAllocationError
import peachpy.codegen
import peachpy.c
import string
import inspect
import time
active_function = None
active_stream = None
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import sys
class Loader:
def __init__(self, code_size, data_size=0):
from peachpy.util import is_int
if not is_int(code_size):
raise TypeError("code size must be an integer")
if not is_int(data_size):
raise TypeError("data size must be an integer")
if code_size <= 0:
raise ValueError("code size must be positive")
if data_size < 0:
raise ValueError("data size must be non-negative")
import mmap
self.allocation_granularity = max(mmap.ALLOCATIONGRANULARITY, mmap.PAGESIZE)
self.code_address = None
self.code_size = self.allocation_size(code_size)
self.data_address = None
self.data_size = self.allocation_size(data_size)
self._release_memory = None
osname = sys.platform.lower()
if osname == "darwin" or osname.startswith("linux") or osname.startswith("freebsd"):
import ctypes
if osname == "darwin":
libc = ctypes.cdll.LoadLibrary("libc.dylib")
elif osname.startswith("freebsd"):
libc = ctypes.cdll.LoadLibrary("libc.so.7")
else:
libc = ctypes.cdll.LoadLibrary("libc.so.6")
# void* mmap(void* addr, size_t len, int prot, int flags, int fd, off_t offset)
mmap_function = libc.mmap
mmap_function.restype = ctypes.c_void_p
mmap_function.argtype = [ctypes.c_void_p, ctypes.c_size_t,
ctypes.c_int, ctypes.c_int,
ctypes.c_int, ctypes.c_size_t]
# int munmap(void* addr, size_t len)
munmap_function = libc.munmap
munmap_function.restype = ctypes.c_int
munmap_function.argtype = [ctypes.c_void_p, ctypes.c_size_t]
def munmap(address, size):
munmap_result = munmap_function(ctypes.c_void_p(address), size)
assert munmap_result == 0
self._release_memory = lambda address_size: munmap(address_size[0], address_size[1])
# Allocate code segment
code_address = mmap_function(None, self.code_size,
mmap.PROT_READ | mmap.PROT_WRITE | mmap.PROT_EXEC,
mmap.MAP_ANON | mmap.MAP_PRIVATE,
-1, 0)
if code_address == -1:
raise OSError("Failed to allocate memory for code segment")
self.code_address = code_address
if self.data_size > 0:
# Allocate data segment
data_address = mmap_function(None, self.data_size,
mmap.PROT_READ | mmap.PROT_WRITE,
mmap.MAP_ANON | mmap.MAP_PRIVATE,
-1, 0)
if data_address == -1:
raise OSError("Failed to allocate memory for data segment")
self.data_address = data_address
elif osname == "win32":
import ctypes
# From WinNT.h
PAGE_READWRITE = 0x04
PAGE_EXECUTE_READWRITE = 0x40
MEM_COMMIT = 0x1000
MEM_RESERVE = 0x2000
MEM_RELEASE = 0x8000
# LPVOID WINAPI VirtualAlloc(LPVOID address, SIZE_T size, DWORD allocationType, DWORD protect)
VirtualAlloc_function = ctypes.windll.kernel32.VirtualAlloc
VirtualAlloc_function.restype = ctypes.c_void_p
VirtualAlloc_function.argtypes = [ctypes.c_void_p, ctypes.c_size_t, ctypes.c_ulong, ctypes.c_ulong]
# BOOL WINAPI VirtualFree(LPVOID lpAddress, SIZE_T dwSize, DWORD dwFreeType)
VirtualFree_function = ctypes.windll.kernel32.VirtualFree
VirtualFree_function.restype = ctypes.c_int
VirtualFree_function.argtypes = [ctypes.c_void_p, ctypes.c_size_t, ctypes.c_ulong]
def VirtualFree(address, size):
VirtualFree_result = VirtualFree_function(address, 0, MEM_RELEASE)
assert VirtualFree_result != 0
self._release_memory = lambda address_size: VirtualFree(address_size[0], address_size[1])
# Allocate code segment
code_address = VirtualAlloc_function(None, self.code_size,
MEM_RESERVE | MEM_COMMIT,
PAGE_EXECUTE_READWRITE)
if not code_address:
raise OSError("Failed to allocate memory for code segment")
self.code_address = code_address
if self.data_size > 0:
# Allocate data segment
data_address = VirtualAlloc_function(None, self.data_size,
MEM_RESERVE | MEM_COMMIT,
PAGE_READWRITE)
if not data_address:
raise OSError("Failed to allocate memory for data segment")
self.data_address = data_address
elif osname == "nacl":
import dynacl
# Allocate code segment
self.allocation = dynacl.allocate(self.code_size, self.data_size)
self.code_address = self.allocation.code_address
self.data_address = self.allocation.data_address
self.copy_code = self._nacl_copy_code
else:
raise ValueError("Unknown host OS: " + osname)
def allocation_size(self, segment_size):
import peachpy.util
return peachpy.util.roundup(segment_size, self.allocation_granularity)
def copy_code(self, code_segment):
import ctypes
ctypes.memmove(self.code_address,
ctypes.c_char_p(bytes(code_segment)),
len(code_segment))
def _nacl_copy_code(self, code_segment):
code_offset = 0
self.allocation.dyncode_create(code_segment, code_offset)
def copy_data(self, data_segment):
import ctypes
ctypes.memmove(self.data_address,
ctypes.c_char_p(bytes(data_segment)),
len(data_segment))
def __del__(self):
if self._release_memory is not None:
if self.code_address is not None:
self._release_memory((self.code_address, self.code_size))
self.code_address = None
if self.data_address is not None:
self._release_memory((self.data_address, self.data_size))
self.data_address = None
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
class Endianness:
Big, Little = "Big-Endian", "Little-Endian"
class ABI(object):
def __init__(self, name, endianness,
bool_size, wchar_size, short_size, int_size, long_size, longlong_size,
pointer_size, index_size,
stack_alignment, red_zone,
callee_save_registers, argument_registers, volatile_registers, restricted_registers=[],
elf_class=None, elf_data_encoding=None, elf_machine_type=None,
mscoff_machine_type=None):
super(ABI, self).__init__()
self.name = name
self.endianness = endianness
self.bool_size = bool_size
self.wchar_size = wchar_size
self.short_size = short_size
self.int_size = int_size
self.long_size = long_size
self.longlong_size = longlong_size
self.pointer_size = pointer_size
self.index_size = index_size
self.stack_alignment = stack_alignment
self.red_zone = red_zone
self.callee_save_registers = callee_save_registers
self.argument_registers = argument_registers
self.volatile_registers = volatile_registers
self.restricted_registers = restricted_registers
self.elf_class = elf_class
self.elf_data_encoding = elf_data_encoding
self.elf_machine_type = elf_machine_type
self.mscoff_machine_type = mscoff_machine_type
def __eq__(self, other):
return isinstance(other, ABI) and self.name == other.name
def __ne__(self, other):
return not isinstance(other, ABI) or self.name != other.name
def __hash__(self):
return hash(self.name)
def __str__(self):
return self.name
def __repr__(self):
return str(self)
@property
def is_elf_compatible(self):
return self.elf_class is not None and self.elf_data_encoding is not None and self.elf_machine_type is not None
@property
def is_mscoff_compatible(self):
return self.mscoff_machine_type is not None
@property
def is_macho_compatible(self):
return False
@property
def elf_bitness(self):
if self.elf_class is not None:
from peachpy.formats.elf.file import ElfClass
return {ElfClass.class32: 32, ElfClass.class64: 64}[self.elf_class]
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
active_writers = []
class TextWriter(object):
def __init__(self, output_path):
super(TextWriter, self).__init__()
self.output_path = output_path
self.prologue = []
self.content = []
self.epilogue = []
def __enter__(self):
global active_writers
active_writers.append(self)
self.output_file = open(self.output_path, "w")
return self
def __exit__(self, exc_type, exc_value, traceback):
global active_writers
active_writers.remove(self)
if exc_type is None:
self.output_file.write(self.serialize())
self.output_file.close()
self.output_file = None
else:
import os
os.unlink(self.output_file.name)
self.output_file = None
raise
def serialize(self):
import os
prologue = self.prologue
if not isinstance(prologue, str):
prologue = os.linesep.join(map(str, prologue))
if prologue:
prologue += os.linesep * 3
content = self.content
if not isinstance(content, str):
content = os.linesep.join(map(str, content))
epilogue = self.epilogue
if not isinstance(epilogue, str):
epilogue = os.linesep.join(map(str, epilogue))
if epilogue:
epilogue = os.linesep * 3 + epilogue
return prologue + content + epilogue
class AssemblyWriter(TextWriter):
def __init__(self, output_path, assembly_format, input_path=None):
super(AssemblyWriter, self).__init__(output_path)
if assembly_format not in {"go", "nasm", "masm", "gas"}:
raise ValueError("Unknown assembly format: %s" % assembly_format)
self.assembly_format = assembly_format
self.comment_prefix = {
"go": "//",
"nasm": ";",
"masm": ";",
"gas": "#"
}[assembly_format]
if assembly_format == "go":
from os import linesep
self.prologue = "// +build !noasm" + linesep
else:
self.prologue = ""
import peachpy
if input_path is not None:
self.prologue += "{escape} Generated by PeachPy {version} from {filename}".format(
escape=self.comment_prefix, version=peachpy.__version__, filename=input_path)
else:
self.prologue += "{escape} Generated by PeachPy {version}".format(
escape=self.comment_prefix, version=peachpy.__version__)
self.prologue_lines = len(self.prologue.splitlines()) + 3
def add_function(self, function):
import peachpy.x86_64.function
assert isinstance(function, peachpy.x86_64.function.ABIFunction), \
"Function must be finalized with an ABI before its assembly can be used"
function_lines = function.format(self.assembly_format, line_separator=None, line_number=self.prologue_lines + len(self.content))
self.content += function_lines
class ImageWriter(object):
def __init__(self, output_path):
super(ImageWriter, self).__init__()
self.output_path = output_path
def __enter__(self):
global active_writers
active_writers.append(self)
self.output_file = open(self.output_path, "wb", buffering=0)
return self
def __exit__(self, exc_type, exc_value, traceback):
global active_writers
active_writers.remove(self)
if exc_type is None:
self.output_file.write(self.encode())
self.output_file.close()
self.output_file = None
else:
import os
os.unlink(self.output_file.name)
self.output_file = None
raise
def encode(self):
return bytearray()
class ELFWriter(ImageWriter):
def __init__(self, output_path, abi, input_path=None):
super(ELFWriter, self).__init__(output_path)
from peachpy.formats.elf.image import Image
from peachpy.formats.elf.section import TextSection, ProgramBitsSection
self.abi = abi
self.image = Image(abi, input_path)
self.text_section = TextSection()
self.image.add_section(self.text_section)
self.gnu_stack_section = ProgramBitsSection(".note.GNU-stack", allocate=False)
self.image.add_section(self.gnu_stack_section)
self.text_rela_section = None
self.rodata_section = None
def encode(self):
return self.image.as_bytearray
def add_function(self, function):
import peachpy.x86_64.function
from peachpy.util import roundup
assert isinstance(function, peachpy.x86_64.function.ABIFunction), \
"Function must be finalized with an ABI before its assembly can be used"
encoded_function = function.encode()
code_offset = len(self.text_section.content)
code_padding = bytearray([encoded_function.code_section.alignment_byte] *
(roundup(code_offset, encoded_function.code_section.alignment) - code_offset))
self.text_section.content += code_padding
code_offset += len(code_padding)
self.text_section.content += encoded_function.code_section.content
self.text_section.alignment = max(self.text_section.alignment, encoded_function.code_section.alignment)
const_offset = 0
if encoded_function.const_section.content:
if self.rodata_section is None:
from peachpy.formats.elf.section import ReadOnlyDataSection
self.rodata_section = ReadOnlyDataSection()
self.image.add_section(self.rodata_section)
const_offset = self.rodata_section.get_content_size(self.abi)
const_padding = bytearray([encoded_function.const_section.alignment_byte] *
(roundup(const_offset, encoded_function.const_section.alignment) - const_offset))
self.rodata_section.content += const_padding
const_offset += len(const_padding)
self.rodata_section.content += encoded_function.const_section.content
self.rodata_section.alignment = max(self.rodata_section.alignment, encoded_function.const_section.alignment)
# Map from symbol name to symbol index
from peachpy.formats.elf.symbol import Symbol, SymbolBinding, SymbolType
symbol_map = dict()
for symbol in encoded_function.const_section.symbols:
const_symbol = Symbol()
const_symbol.name = function.mangled_name + "." + symbol.name
const_symbol.value = const_offset + symbol.offset
const_symbol.size = symbol.size
const_symbol.section = self.rodata_section
const_symbol.binding = SymbolBinding.local
const_symbol.type = SymbolType.data_object
self.image.symtab.add(const_symbol)
symbol_map[symbol] = const_symbol
if encoded_function.code_section.relocations:
if self.text_rela_section is None:
from peachpy.formats.elf.section import RelocationsWithAddendSection
self.text_rela_section = RelocationsWithAddendSection(self.text_section, self.image.symtab)
self.image.add_section(self.text_rela_section)
from peachpy.formats.elf.symbol import RelocationWithAddend, RelocationType
for relocation in encoded_function.code_section.relocations:
elf_relocation = RelocationWithAddend(RelocationType.x86_64_pc32,
code_offset + relocation.offset,
symbol_map[relocation.symbol],
relocation.offset - relocation.program_counter)
self.text_rela_section.add(elf_relocation)
function_symbol = Symbol()
function_symbol.name = function.mangled_name
function_symbol.value = code_offset
function_symbol.content_size = len(encoded_function.code_section)
function_symbol.section = self.text_section
function_symbol.binding = SymbolBinding.global_
function_symbol.type = SymbolType.function
self.image.symtab.add(function_symbol)
class MachOWriter(ImageWriter):
def __init__(self, output_path, abi):
super(MachOWriter, self).__init__(output_path)
from peachpy.formats.macho.image import Image
self.abi = abi
self.image = Image(abi)
def encode(self):
return self.image.encode()
def add_function(self, function):
import peachpy.x86_64.function
assert isinstance(function, peachpy.x86_64.function.ABIFunction), \
"Function must be finalized with an ABI before its assembly can be used"
from peachpy.formats.macho.symbol import Symbol, SymbolType, SymbolDescription, SymbolVisibility, \
Relocation, RelocationType
from peachpy.util import roundup
encoded_function = function.encode()
code_offset = len(self.image.text_section.content)
code_padding = bytearray([encoded_function.code_section.alignment_byte] *
(roundup(code_offset, encoded_function.code_section.alignment) - code_offset))
self.image.text_section.content += code_padding
code_offset += len(code_padding)
self.image.text_section.content += encoded_function.code_section.content
self.image.text_section.alignment = \
max(self.image.text_section.alignment, encoded_function.code_section.alignment)
const_offset = self.image.const_section.content_size
const_padding = bytearray([encoded_function.const_section.alignment_byte] *
(roundup(const_offset, encoded_function.const_section.alignment) - const_offset))
self.image.const_section.content += const_padding
const_offset += len(const_padding)
self.image.const_section.content += encoded_function.const_section.content
self.image.const_section.alignment = \
max(self.image.const_section.alignment, encoded_function.const_section.alignment)
# Map from PeachPy symbol to Mach-O symbol
symbol_map = dict()
for symbol in encoded_function.const_section.symbols:
macho_symbol = Symbol("_" + function.mangled_name + "." + symbol.name,
SymbolType.section_relative, self.image.const_section,
const_offset + symbol.offset)
macho_symbol.description = SymbolDescription.defined
self.image.symbol_table.add_symbol(macho_symbol)
symbol_map[symbol] = macho_symbol
for relocation in encoded_function.code_section.relocations:
macho_relocation = Relocation(RelocationType.x86_64_signed, code_offset + relocation.offset, 4,
symbol_map[relocation.symbol], is_pc_relative=True)
relocation_addend = relocation.offset + 4 - relocation.program_counter
if relocation_addend != 0:
self.image.text_section.content[code_offset + relocation.offset] = relocation_addend & 0xFF
self.image.text_section.content[code_offset + relocation.offset + 1] = (relocation_addend >> 8) & 0xFF
self.image.text_section.content[code_offset + relocation.offset + 2] = (relocation_addend >> 16) & 0xFF
self.image.text_section.content[code_offset + relocation.offset + 3] = (relocation_addend >> 24) & 0xFF
self.image.text_section.relocations.append(macho_relocation)
function_symbol = Symbol("_" + function.mangled_name, SymbolType.section_relative, self.image.text_section,
value=code_offset)
function_symbol.description = SymbolDescription.defined
function_symbol.visibility = SymbolVisibility.external
self.image.symbol_table.add_symbol(function_symbol)
class MSCOFFWriter(ImageWriter):
def __init__(self, output_path, abi, input_path=None):
super(MSCOFFWriter, self).__init__(output_path)
from peachpy.formats.mscoff import Image, TextSection, ReadOnlyDataSection
self.output_path = output_path
self.abi = abi
self.image = Image(abi, input_path)
self.text_section = TextSection()
self.image.add_section(self.text_section)
self.rdata_section = ReadOnlyDataSection()
self.image.add_section(self.rdata_section)
def encode(self):
return self.image.encode()
def add_function(self, function):
import peachpy.x86_64.function
assert isinstance(function, peachpy.x86_64.function.ABIFunction), \
"Function must be finalized with an ABI before its assembly can be used"
from peachpy.util import roundup
from peachpy.formats.mscoff import Symbol, SymbolType, StorageClass, Relocation, RelocationType
encoded_function = function.encode()
code_offset = len(self.text_section.content)
code_padding = bytearray([encoded_function.code_section.alignment_byte] *
(roundup(code_offset, encoded_function.code_section.alignment) - code_offset))
self.text_section.content += code_padding
code_offset += len(code_padding)
self.text_section.content += encoded_function.code_section.content
self.text_section.alignment = \
max(self.text_section.alignment, encoded_function.code_section.alignment)
rdata_offset = self.rdata_section.content_size
rdata_padding = bytearray([encoded_function.const_section.alignment_byte] *
(roundup(rdata_offset, encoded_function.const_section.alignment) - rdata_offset))
self.rdata_section.content += rdata_padding
rdata_offset += len(rdata_padding)
self.rdata_section.content += encoded_function.const_section.content
self.rdata_section.alignment = \
max(self.rdata_section.alignment, encoded_function.const_section.alignment)
# Map from PeachPy symbol to Mach-O symbol
symbol_map = dict()
for symbol in encoded_function.const_section.symbols:
mscoff_symbol = Symbol()
mscoff_symbol.name = symbol.name
mscoff_symbol.value = rdata_offset + symbol.offset
mscoff_symbol.section = self.rdata_section
mscoff_symbol.symbol_type = SymbolType.non_function
mscoff_symbol.storage_class = StorageClass.static
self.image.add_symbol(mscoff_symbol)
symbol_map[symbol] = mscoff_symbol
for relocation in encoded_function.code_section.relocations:
relocation_type_map = {
4: RelocationType.x86_64_relocation_offset32,
5: RelocationType.x86_64_relocation_plus_1_offset32,
6: RelocationType.x86_64_relocation_plus_2_offset32,
7: RelocationType.x86_64_relocation_plus_3_offset32,
8: RelocationType.x86_64_relocation_plus_4_offset32,
9: RelocationType.x86_64_relocation_plus_5_offset32
}
relocation_type = relocation_type_map[relocation.program_counter - relocation.offset]
mscoff_relocation = Relocation(relocation_type,
code_offset + relocation.offset,
symbol_map[relocation.symbol])
self.text_section.relocations.append(mscoff_relocation)
function_symbol = Symbol()
function_symbol.name = function.mangled_name
function_symbol.value = code_offset
function_symbol.section = self.text_section
function_symbol.symbol_type = SymbolType.function
function_symbol.storage_class = StorageClass.external
self.image.add_symbol(function_symbol)
class MetadataWriter(TextWriter):
def __init__(self, output_path):
super(MetadataWriter, self).__init__(output_path)
self.metadata = []
def add_function(self, function):
import peachpy.x86_64.function
assert isinstance(function, peachpy.x86_64.function.ABIFunction), \
"Function must be finalized with an ABI before its assembly can be used"
self.metadata.append(function.metadata)
class JSONMetadataWriter(MetadataWriter):
def __init__(self, output_path):
super(JSONMetadataWriter, self).__init__(output_path)
def serialize(self):
import json
return json.dumps(self.metadata)
class CHeaderWriter(TextWriter):
def __init__(self, output_path, input_path=None):
super(CHeaderWriter, self).__init__(output_path)
import peachpy
if input_path is not None:
self.prologue = ["/* Generated by PeachPy %s from %s */" % (peachpy.__version__, input_path)]
else:
self.prologue = ["/* Generated by PeachPy %s */" % peachpy.__version__]
self.prologue += [
"",
"#pragma once",
"",
"#ifdef __cplusplus",
"extern \"C\" {",
"#endif"
]
self.epilogue = [
"#ifdef __cplusplus",
"} /* extern \"C\" */",
"#endif",
""
]
def add_function(self, function):
import peachpy.x86_64.function
assert isinstance(function, peachpy.x86_64.function.ABIFunction), \
"Function must be finalized with an ABI before its assembly can be used"
return_type = "void" if function.result_type is None else str(function.result_type)
arguments = [str(arg.c_type) + " " + arg.name for arg in function.arguments]
self.content.append(return_type + " " + function.mangled_name + "(" + ", ".join(arguments) + ");")
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
def parse_assigned_variable_name(stack_frames, constructor_name):
"""Analyses the provided stack frames and parses Python assignment expressions like
some.namespace.variable_name = some.module.name.`constructor_name`(...)
from the caller's call site and returns the name of the variable being assigned as a string.
If the assignment expression is not found, returns None.
"""
if isinstance(stack_frames, list) and len(stack_frames) > 1:
parent_stack_frame = stack_frames[1]
if isinstance(parent_stack_frame, tuple) and len(parent_stack_frame) == 6:
(_, _, _, _, source_lines, _) = parent_stack_frame
if isinstance(source_lines, list) and source_lines:
source_line = source_lines[0]
if source_line:
import re
assignment_regexp = r"(?:\w+\.)*(\w+)\s*=\s*(?:\w+\.)*" + re.escape(constructor_name) + r"\(.*\)"
match = re.match(assignment_regexp, source_line.strip())
if match:
return match.group(1)
def parse_with_variable_name(stack_frames, constructor_name):
"""Analyses the provided stack frames and parses Python with expressions like
with `constructor_name`(...) as variable_name:
from the caller's call site and returns the name of the variable named in the statement as a string.
If a with statement is not found, returns None.
"""
if isinstance(stack_frames, list) and len(stack_frames) > 1:
parent_stack_frame = stack_frames[1]
if isinstance(parent_stack_frame, tuple) and len(parent_stack_frame) == 6:
(_, _, _, _, source_lines, _) = parent_stack_frame
if isinstance(source_lines, list) and source_lines:
source_line = source_lines[0]
if source_line:
import re
with_regexp = r"with\s+(?:\w+\.)*" + re.escape(constructor_name) + "\(.*\)\s+as\s+([_a-zA-Z]\w*)\s*:"
match = re.match(with_regexp, source_line.strip())
if match:
return match.group(1)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import six
class Name:
def __init__(self, name=None, prename=None):
assert name is None or isinstance(name, str)
assert prename is None or isinstance(prename, str)
assert name is None or prename is None, \
"Either name or prename, but not both, can be specified"
self.name = name
self.prename = prename
def __str__(self):
if self.name is not None:
return self.name
elif self.prename is not None:
return "<" + self.prename + ">"
else:
return "<?>"
def __repr__(self):
return str(self)
def __hash__(self):
return hash(self.name) ^ id(self)
def __eq__(self, other):
return isinstance(other, Name) and (self is other or self.name == other.name)
def __ne__(self, other):
return not isinstance(other, Name) or (self is not other and self.name != other.name)
@staticmethod
def check_name(name):
"""Verifies that the name is appropriate for a symbol"""
if not isinstance(name, str):
raise TypeError("Invalid name %s: string required" % str(name))
import re
if not re.match("^[_a-zA-Z]\\w*$", name):
raise ValueError("Invalid name: " + name)
if name.startswith("__"):
raise ValueError("Invalid name %s: names starting with __ are reserved for PeachPy purposes" % name)
class Namespace:
def __init__(self, scope_name):
assert scope_name is None or isinstance(scope_name, Name)
# Name of the namespace.
self.scope_name = scope_name
# Map from name string to either Name or Namespace object
self.names = dict()
# Map from prename string to a set of Name and Namespace objects
self.prenames = dict()
def __str__(self):
return str(self.scope_name)
def __hash__(self):
return hash(self.scope_name)
def __eq__(self, other):
return isinstance(other, Namespace) and self.scope_name == other.scope_name
def __ne__(self, other):
return not isinstance(other, Namespace) or self.scope_name != other.scope_name
def add_scoped_name(self, scoped_name):
assert isinstance(scoped_name, tuple)
scope_name, subscoped_name = scoped_name[0], scoped_name[1:]
assert isinstance(scope_name, Name)
scope = scope_name
if subscoped_name:
scope = Namespace(scope_name)
scope.add_scoped_name(subscoped_name)
if scope_name.name:
assert scope_name.prename is None
if scope_name.name in self.names:
if subscoped_name and isinstance(self.names[scope_name.name], Namespace):
self.names[scope_name.name].add_scoped_name(subscoped_name)
else:
raise ValueError("Name %s already exists" % scope_name.name)
else:
self.names[scope_name.name] = scope
else:
assert scope_name.name is None
self.prenames.setdefault(scope_name.prename, set())
if subscoped_name:
for subscope in iter(self.prenames[scope_name.prename]):
if isinstance(subscope, Namespace) and subscope.scope_name is scope_name:
subscope.add_scoped_name(subscoped_name)
return
self.prenames[scope_name.prename].add(scope)
def assign_names(self):
# Step 1: assign names to symbols with prenames with no conflicts
for prename in six.iterkeys(self.prenames):
if prename is not None:
if len(self.prenames[prename]) == 1 and prename not in self.names:
name_object = next(iter(self.prenames[prename]))
self.names[prename] = name_object
if isinstance(name_object, Namespace):
name_object = name_object.scope_name
name_object.name = prename
# Step 2: assign names to symbols with conflicting prenames
for prename, prename_objects in six.iteritems(self.prenames):
if prename is not None:
suffix = 0
suffixed_name = prename + str(suffix)
for name_object in iter(prename_objects):
# Check that the name wasn't already assigned at Step 1
if name_object.name is None:
# Generate a non-conflicting name by appending a suffix
while suffixed_name in self.names:
suffix += 1
suffixed_name = prename + str(suffix)
self.names[suffixed_name] = name_object
if isinstance(name_object, Namespace):
name_object = name_object.scope_name
name_object.name = suffixed_name
# Step 3: assign names to symbols without prenames
if None in self.prenames:
unnamed_objects = self.prenames[None]
suffix = 0
suffixed_name = "__local" + str(suffix)
for name_object in iter(unnamed_objects):
# Generate a non-conflicting name by appending a suffix
while suffixed_name in self.names:
suffix += 1
suffixed_name = "__local" + str(suffix)
self.names[suffixed_name] = name_object
if isinstance(name_object, Namespace):
name_object = name_object.scope_name
name_object.name = suffixed_name
pass
@property
def name(self):
return self.scope_name.name
@property
def prename(self):
return self.scope_name.prename
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
class CodeGenerator(object):
def __init__(self, use_tabs=True):
self.indentationLevel = 0
self.use_tabs = use_tabs
self.code = []
def indent(self):
self.indentationLevel += 1
return self
def dedent(self):
self.indentationLevel -= 1
return self
def add_line(self, string='', indent=None):
if indent == None:
indent = self.indentationLevel
elif indent < 0:
indent += self.indentationLevel
if string == '':
self.code.append(string)
else:
if self.use_tabs:
self.code.append("\t" * indent + string)
else:
self.code.append(" " * indent + string)
return self
def add_lines(self, lines, indent=None):
for line in lines:
self.add_line(line, indent)
def add_empty_lines(self, count):
for i in range(count):
self.add_line()
return self
def add_c_comment(self, lines, doxygen=False):
if isinstance(lines, str) and lines.find("\n") != -1:
lines = lines.split("\n")
if isinstance(lines, list) and len(lines) > 1:
if doxygen:
self.add_line("/**")
else:
self.add_line("/*")
for line in lines:
self.add_line(" * " + line)
self.add_line(" */")
else:
line = lines[0] if isinstance(lines, list) else str(lines)
if doxygen:
self.add_line("/** " + line + "*/")
else:
self.add_line("/* " + line + "*/")
def add_assembly_comment(self, lines, indent=None):
for line in lines:
self.add_line("; " + line, indent)
def add_fortran90_comment(self, lines, doxygen=False):
if isinstance(lines, str) and lines.find("\n") != -1:
lines = lines.split("\n")
elif isinstance(lines, str):
lines = [lines]
for index, line in enumerate(lines):
if doxygen:
if index == 0:
self.add_line("!> " + line)
else:
self.add_line("!! " + line)
else:
self.add_line("! " + line)
def add_csharp_comment(self, lines, doxygen=False):
if isinstance(lines, str) and lines.find("\n") != -1:
lines = lines.split("\n")
if isinstance(lines, list) and len(lines) > 1:
if not doxygen:
self.add_line("/*")
for line in lines:
if doxygen:
self.add_line("/// " + line)
else:
self.add_line(" * " + line)
if not doxygen:
self.add_line(" */")
else:
line = lines[0] if isinstance(lines, list) else str(lines)
if doxygen:
self.add_line("/// " + line)
else:
self.add_line("// " + line)
def get_code(self):
return "\n".join(self.code)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
class Argument(object):
"""
Function argument.
An argument must have a C type and a name.
:ivar c_type: the type of the argument in C
:type c_type: :class:`peachpy.c.types.Type`
:ivar name: the name of the argument
:type name: str
"""
def __init__(self, c_type, name=None):
"""
:param peachpy.c.types.Type c_type: the type of the argument in C.
When Go function is generated, the type is automatically converted to similar Go type.
Note that the ``short``, ``int``, ``long``, and ``long long`` types do not have an equivalents in Go.
In particular, C's ``int`` type is not an equivalent of Go's ``int`` type. To get Go's ``int`` and ``uint``
types use ``ptrdiff_t`` and ``size_t`` correspondingly.
:param str name: the name of the argument. If the name is not provided explicitly, PeachPy tries to parse it
from the caller code. The name must follow the C rules for identifiers:
- It can contain only Latin letters, digits, and underscore symbol
- It can not start with a digit
- It can not start with double underscore (these names are reserved for PeachPy)
- Name must be unique among the function arguments
"""
from peachpy.c.types import Type
if not isinstance(c_type, Type):
raise TypeError("%s is not a C type" % str(c_type))
self.c_type = c_type
if name is None:
import inspect
import re
_, _, _, _, caller_lines, _ = inspect.stack()[1]
if caller_lines is None:
raise ValueError("Argument name is not specified and the caller context is not available")
source_line = caller_lines[0].strip()
match = re.match("(?:\\w+\\.)*(\\w+)\\s*=\\s*(?:\\w+\\.)*Argument\\(.+\\)", source_line)
if match:
name = match.group(1)
while name.startswith("_"):
name = name[1:]
if name.endswith("argument") or name.endswith("Argument"):
name = name[:-len("argument")]
if name.endswith("arg") or name.endswith("Arg"):
name = name[:-len("arg")]
while name.endswith("_"):
name = name[:-1]
if not name:
raise ValueError("Argument name is not specified and can not be parsed from the code")
from peachpy.name import Name
Name.check_name(name)
self.name = name
def __str__(self):
return str(self.c_type) + " " + self.name
def __repr__(self):
return str(self)
def __eq__(self, other):
return isinstance(other, Argument) and self.c_type == other.c_type and self.name == other.name
def __ne__(self, other):
return not isinstance(other, Argument) or self.c_type != other.c_type or self.name != other.name
@property
def is_floating_point(self):
return self.c_type.is_floating_point
@property
def is_codeunit(self):
return self.c_type.is_codeunit
@property
def is_integer(self):
return self.c_type.is_integer
@property
def is_unsigned_integer(self):
return self.c_type.is_unsigned_integer
@property
def is_signed_integer(self):
return self.c_type.is_signed_integer
@property
def is_size_integer(self):
return self.c_type.is_size_integer
@property
def is_pointer_integer(self):
return self.c_type.is_pointer_integer
@property
def is_pointer(self):
return self.c_type.is_pointer
@property
def is_vector(self):
return self.c_type.is_vector
@property
def is_mask(self):
return self.c_type.is_mask
@property
def size(self):
return self.c_type.size
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from enum import IntEnum
class SymbolVisibility(IntEnum):
external = 0x01
private_external = 0x10
class SymbolType(IntEnum):
undefined = 0x00
prebound_undefined = 0x0C
absolute = 0x02
section_relative = 0x0E
indirect = 0x0A
class SymbolDescription(IntEnum):
undefined_lazy = 0x00
undefined_non_lazy = 0x01
defined = 0x02
private_defined = 0x03
private_undefined_lazy = 0x05
private_undefined_non_lazy = 0x04
class SymbolFlags(IntEnum):
referenced_dynamically = 0x10
no_dead_strip = 0x20
weak_reference = 0x40
weak_definition = 0x80
class Symbol:
def __init__(self, name, type, section, value=None):
self.name = name
self.visibility = 0
self.type = type
self.section = section
self.description = 0
self.flags = 0
self.value = value
@staticmethod
def get_entry_size(abi):
from peachpy.abi import ABI
assert isinstance(abi, ABI)
assert abi.pointer_size in [4, 8]
return {4: 12, 8: 16}[abi.pointer_size]
def encode(self, encoder, name_index_map, section_index_map, section_address_map):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
assert self.name in name_index_map
assert self.section is None or self.section in section_index_map
name_index = name_index_map[self.name]
section_index = 0
if self.section is not None:
section_index = section_index_map[self.section]
if encoder.bitness == 32:
return encoder.uint32(name_index) + \
encoder.uint8(self.type | self.visibility) + \
encoder.uint8(section_index) + \
encoder.uint16(self.description | self.flags) + \
encoder.uint32(self.value)
else:
return encoder.uint32(name_index) + \
encoder.uint8(self.type | self.visibility) + \
encoder.uint8(section_index) + \
encoder.uint16(self.description | self.flags) + \
encoder.uint64(self.value + section_address_map[self.section])
class RelocationType(IntEnum):
x86_64_unsigned = 0
x86_64_signed = 1
# CALL or JMP instruction with 32-bit displacement.
x86_64_branch = 2
# Load (MOVQ) of a 64-bit Global Offset Table entry
x86_64_got_load = 3
x86_64_got = 4
x86_64_subtractor = 5
# Signed 32-bit displacement with a -1 addend
x86_64_signed_minus_1 = 6
# Signed 32-bit displacement with a -2 addend
x86_64_signed_minus_2 = 7
# Signed 32-bit displacement with a -4 addend
x86_64_signed_minus_4 = 8
arm_vanilla = 0
arm_pair = 1
arm_sectdiff = 2
arm_local_sectdiff = 3
arm_pb_la_ptr = 4
arm_br_24 = 5
arm_half = 6
arm_half_sectdiff = 7
arm64_unsigned = 0
arm64_subtractor = 1
arm64_branch26 = 2
arm64_page21 = 3
arm64_pageoff12 = 4
arm64_got_load_page21 = 5
arm64_got_load_pageoff12 = 6
arm64_pointer_to_got = 7
arm64_tlvp_load_page21 = 8
arm64_tlvp_load_pageoff12 = 9
arm64_reloc_addend = 10
class Relocation:
size = 8
def __init__(self, type, offset, size, symbol, is_pc_relative=False):
from peachpy.util import is_sint32
assert is_sint32(offset)
assert offset >= 0
assert size in [1, 2, 4, 8]
from peachpy.formats.macho.section import Section
assert symbol is None or isinstance(symbol, (Section, Symbol))
self.type = type
self.offset = offset
self.size = size
self.symbol = symbol
self.is_pc_relative = is_pc_relative
def encode(self, encoder, section_index_map, symbol_index_map):
from peachpy.formats.macho.section import Section
from peachpy.util import ilog2
symbol = 0
if isinstance(self.symbol, Symbol):
# Set "external" bit (bit 27) if referencing an external symbol
symbol = symbol_index_map[self.symbol] | 0x8000000
elif isinstance(self.symbol, Section):
symbol = section_index_map[self.symbol]
if self.is_pc_relative:
# Set "pc_relative" bit (bit 24) if the relocation is relative to the program counter
symbol |= 0x1000000
log2_size = ilog2(self.size)
symbol |= log2_size << 25
symbol |= self.type << 28
return encoder.uint32(self.offset) + encoder.uint32(symbol)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from enum import IntEnum
class MemoryProtection(IntEnum):
read = 0x01
write = 0x02
execute = 0x04
default = 0x07
class Segment:
def __init__(self, name):
self.name = name
self.sections = list()
self.flags = 0
def add_section(self, section):
assert isinstance(section, Section)
assert section.segment_name == self.name
self.sections.append(section)
def get_command_size(self, abi):
from peachpy.abi import ABI
assert isinstance(abi, ABI)
assert abi.pointer_size in [4, 8]
return {4: 56, 8: 72}[abi.pointer_size] + \
sum(section.get_command_size(abi) for section in self.sections)
def encode_command(self, encoder, section_offset_map, section_address_map, section_relocations_map):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
offset = section_offset_map[self.sections[0]]
memory_size = section_address_map[self.sections[-1]] + self.sections[-1].content_size
file_size = sum(section.content_size for section in self.sections)
address = 0
if self.sections:
address = section_address_map[self.sections[0]]
# TODO: combine the two cases
if encoder.bitness == 32:
command_id = 0x1
command_size = 56 + len(self.sections) * 68
command = encoder.uint32(command_id) + \
encoder.uint32(command_size) + \
encoder.fixed_string(self.name, 16) + \
encoder.uint32(address) + \
encoder.uint32(memory_size) + \
encoder.uint32(offset) + \
encoder.uint32(file_size) + \
encoder.uint32(MemoryProtection.default) + \
encoder.uint32(MemoryProtection.default) + \
encoder.uint32(len(self.sections)) + \
encoder.uint32(self.flags)
else:
command_id = 0x19
command_size = 72 + len(self.sections) * 80
command = encoder.uint32(command_id) + \
encoder.uint32(command_size) + \
encoder.fixed_string(self.name, 16) + \
encoder.uint64(address) + \
encoder.uint64(memory_size) + \
encoder.uint64(offset) + \
encoder.uint64(file_size) + \
encoder.uint32(MemoryProtection.default) + \
encoder.uint32(MemoryProtection.default) + \
encoder.uint32(len(self.sections)) + \
encoder.uint32(self.flags)
for section in self.sections:
command += section.encode_command(encoder,
section_offset_map[section],
section_address_map[section],
section_relocations_map.get(section))
from peachpy.x86_64.abi import system_v_x86_64_abi
return command
class SectionIndex(IntEnum):
no_section = 0
class SectionType(IntEnum):
regular = 0x00
zero_fill = 0x01
gb_zero_fill = 0x0C
cstring_literals = 0x02
four_byte_literals = 0x03
eight_byte_literals = 0x04
sixteen_byte_literals = 0x0E
literal_pointers = 0x05
non_lazy_symbol_pointers = 0x06
lazy_symbol_pointers = 0x07
symbol_stubs = 0x08
module_init_function_pointers = 0x09
module_terminate_function_pointers = 0x0A
coalesced_symbols = 0x0B
interposing = 0x0D
dtrace_object_format = 0x0F
lazy_dylib_symbol_pointers = 0x10
thread_local_regular = 0x11
thread_local_zero_fill = 0x12
thread_local_variable_descriptors = 0x13
thread_local_variable_pointers = 0x14
thread_local_function_pointers = 0x15
class SectionAttributes(IntEnum):
only_instructions = 0x80000000
coalesced_symbols = 0x40000000
strip_static_symbols = 0x20000000
no_dead_stripping = 0x10000000
live_support = 0x08000000
self_modifying_code = 0x04000000
debug = 0x02000000
some_instructions = 0x00000400
external_relocations = 0x00000200
local_relocations = 0x00000100
class Section(object):
def __init__(self, type, segment_name, section_name):
self.type = type
self.segment_name = segment_name
self.section_name = section_name
self.attributes = 0
self._alignment = 1
self.relocations = []
self.content = bytearray()
@property
def alignment(self):
return self._alignment
@alignment.setter
def alignment(self, alignment):
from peachpy.util import is_uint32
if not is_uint32(alignment):
raise TypeError("Section alignment %s is not representable as a 32-bit unsigned integer" % str(alignment))
if alignment & (alignment - 1) != 0:
raise ValueError("Section alignment %d is not a power of 2" % alignment)
if alignment == 0:
alignment = 1
self._alignment = alignment
@property
def log2_alignment(self):
from peachpy.util import ilog2
return ilog2(self._alignment)
@property
def relocations_count(self):
return len(self.relocations)
@property
def content_size(self):
return len(self.content)
@staticmethod
def get_command_size(abi):
from peachpy.abi import ABI
assert isinstance(abi, ABI)
assert abi.pointer_size in [4, 8]
return {4: 68, 8: 80}[abi.pointer_size]
def encode_command(self, encoder, offset, address, relocations_offset):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
if len(self.relocations) == 0:
relocations_offset = 0
if encoder.bitness == 32:
return encoder.fixed_string(self.section_name, 16) + \
encoder.fixed_string(self.segment_name, 16) + \
encoder.uint32(address) + \
encoder.uint32(self.content_size) + \
encoder.uint32(offset) + \
encoder.uint32(self.log2_alignment) + \
encoder.uint32(relocations_offset) + \
encoder.uint32(self.relocations_count) + \
encoder.uint32(self.type | self.attributes) + \
bytearray(8)
else:
return encoder.fixed_string(self.section_name, 16) + \
encoder.fixed_string(self.segment_name, 16) + \
encoder.uint64(address) + \
encoder.uint64(self.content_size) + \
encoder.uint32(offset) + \
encoder.uint32(self.log2_alignment) + \
encoder.uint32(relocations_offset) + \
encoder.uint32(self.relocations_count) + \
encoder.uint32(self.type | self.attributes) + \
bytearray(12)
class RegularSection(Section):
def __init__(self, segment_name, section_name):
super(RegularSection, self).__init__(SectionType.regular, segment_name, section_name)
def align(self, alignment):
import peachpy.util
ilog2_alignment = peachpy.util.ilog2(alignment)
self.alignment = max(self.alignment, ilog2_alignment)
if len(self.content) % alignment != 0:
padding_length = alignment - len(self.content) % alignment
self.content += bytearray(padding_length)
class TextSection(RegularSection):
def __init__(self):
super(TextSection, self).__init__("__TEXT", "__text")
self.attributes = SectionAttributes.only_instructions | SectionAttributes.some_instructions
class ConstSection(RegularSection):
def __init__(self):
super(ConstSection, self).__init__("__TEXT", "__const")
class SymbolTable:
command_size = 24
def __init__(self, string_table):
assert isinstance(string_table, StringTable)
self.symbols = list()
self.string_table = string_table
def add_symbol(self, symbol):
from peachpy.formats.macho.symbol import Symbol
assert isinstance(symbol, Symbol)
self.symbols.append(symbol)
self.string_table.add(symbol.name)
def encode_command(self, encoder, symbol_offset_map, string_offset):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
command_id = 0x2
symbols_offset = 0
if self.symbols:
symbols_offset = symbol_offset_map[self.symbols[0]]
return encoder.uint32(command_id) + \
encoder.uint32(SymbolTable.command_size) + \
encoder.uint32(symbols_offset) + \
encoder.uint32(len(self.symbols)) + \
encoder.uint32(string_offset) + \
encoder.uint32(self.string_table.size)
class StringTable:
def __init__(self):
self.string_index_map = dict()
self.size = 0
def add(self, string):
import codecs
if string is None or len(string) == 0:
return 0
if string in self.string_index_map:
return self.string_index_map[string]
else:
content_size = self.size
if content_size == 0:
content_size = 1
string_index = content_size
self.string_index_map[string] = string_index
bytestring = codecs.encode(string, "utf-8")
content_size += len(bytestring) + 1
self.size = content_size
def encode(self):
import codecs
if self.size != 0:
bytestring = b"\x00"
for string in sorted(self.string_index_map, key=self.string_index_map.get):
bytestring += codecs.encode(string, "utf8") + b"\x00"
return bytestring
else:
return bytearray()
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from enum import IntEnum
class FileType(IntEnum):
# No file type
null = 0
# Relocatable file
object = 1
# Executable file
executable = 2
# Fixed VM shared library (?)
fixed_vm_library = 3
# Core dump file
core_dump = 4
# Preloaded executable file
preloaded_executable = 5
# Dynamically bound shared library
dynamic_library = 6
# Dynamic linker (dyld)
dynamic_linker = 7
# Dynamically bound bundle file
dynamic_bundle = 8
# Shared library stub for build-time linking (no section content)
dynamic_library_stub = 9
# Companion file with debug sections only
debug_symbols = 10
# Kernel-mode driver
kext_bundle = 11
class CpuType(IntEnum):
x86 = 0x00000007
x86_64 = 0x01000007
arm = 0x0000000C
arm64 = 0x0100000C
ppc = 0x00000012
ppc64 = 0x01000012
abi64 = 0x01000000
class PPCCpuSubType(IntEnum):
all = 0
# PowerPC G3
powerpc750 = 9
# PowerPC G4
powerpc7400 = 10
# PowerPC G4+
powerpc7450 = 11
# PowerPC G5
powerpc970 = 100
class X86CpuSubType(IntEnum):
all = 3
class ARMCpuSubType(IntEnum):
all = 0
# ARM 1176
v6 = 6
# ARM Cortex-A8
v7 = 9
# Cortex-A9 (ARMv7 + MP extension + NEON-HP, de-facto useless, removed from Clang)
v7f = 10
# Swift (ARMv7 + MP extension + VFPv4/NEONv2 + DIV)
v7s = 11
# Marvell Kirkwood (ARMv7 + XScale extension + WMMXv2 + Armada extension, no NEON)
v7k = 12
# Cyclone
v8 = 13
class ARM64CpuSubType(IntEnum):
all = 0
# Cyclone
v8 = 1
class MachHeader:
def __init__(self, abi):
import peachpy.x86_64
import peachpy.arm
self.abi = abi
self.size = {4: 28, 8: 32}[abi.pointer_size]
if abi == peachpy.x86_64.abi.system_v_x86_64_abi:
# 64-bit
self.magic = 0xFEEDFACF
self.cpu_type = CpuType.x86_64
self.cpu_subtype = X86CpuSubType.all
else:
raise ValueError("Unsupported ABI: %s" % str(abi))
self.file_type = FileType.object
self.commands_count = 0
self.commands_size = 0
self.flags = 0
@staticmethod
def get_size(abi):
from peachpy.abi import ABI
assert isinstance(abi, ABI)
assert abi.pointer_size in [4, 8]
return {4: 24, 8: 32}[abi.pointer_size]
def encode(self, encoder):
bytes = encoder.uint32(self.magic) + \
encoder.uint32(self.cpu_type) + \
encoder.uint32(self.cpu_subtype) + \
encoder.uint32(self.file_type) + \
encoder.uint32(self.commands_count) + \
encoder.uint32(self.commands_size) + \
encoder.uint32(self.flags)
if self.abi.pointer_size == 8:
bytes += bytearray(4)
return bytes
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
class Image:
def __init__(self, abi):
from peachpy.formats.macho.section import Segment, TextSection, ConstSection, StringTable, SymbolTable
self.abi = abi
self.segments = list()
self.text_segment = Segment("__TEXT")
self.add_segment(self.text_segment)
self.text_section = TextSection()
self.text_segment.add_section(self.text_section)
self.const_section = ConstSection()
self.text_segment.add_section(self.const_section)
self.string_table = StringTable()
self.symbol_table = SymbolTable(self.string_table)
def add_segment(self, segment):
from peachpy.formats.macho.section import Segment
assert isinstance(segment, Segment)
self.segments.append(segment)
def encode(self):
from peachpy.formats.macho.file import MachHeader
from peachpy.formats.macho.symbol import Relocation
from peachpy.util import roundup
from peachpy.encoder import Encoder
bitness = {4: 32, 8: 64}[self.abi.pointer_size]
encoder = Encoder(self.abi.endianness, bitness)
mach_header = MachHeader(self.abi)
mach_header.commands_size = self.symbol_table.command_size
mach_header.commands_count = 1
for segment in self.segments:
mach_header.commands_size += segment.get_command_size(self.abi)
mach_header.commands_count += 1
symbol_offset_map = dict()
section_offset_map = dict()
section_address_map = dict()
section_relocations_map = dict()
# Layout the commands
data_offset = mach_header.get_size(self.abi)
for segment in self.segments:
data_offset += segment.get_command_size(self.abi)
data_offset += self.symbol_table.command_size
# Layout section data
data_address = 0
for segment in self.segments:
for section in segment.sections:
data_offset = roundup(data_offset, section.alignment)
data_address = roundup(data_address, section.alignment)
section_offset_map[section] = data_offset
section_address_map[section] = data_address
data_offset += section.content_size
data_address += section.content_size
data_offset = roundup(data_offset, self.abi.pointer_size)
# Layout the relocations
for segment in self.segments:
for section in segment.sections:
if section.relocations:
section_relocations_map[section] = data_offset
data_offset += Relocation.size * len(section.relocations)
# Layout the symbols
for symbol in self.symbol_table.symbols:
symbol_offset_map[symbol] = data_offset
data_offset += symbol.get_entry_size(self.abi)
# Layout the strings
string_table_offset = data_offset
# Create map: section->index
section_index = 1
section_index_map = dict()
for segment in self.segments:
for section in segment.sections:
section_index_map[section] = section_index
section_index += 1
# Create map: symbol->index
symbol_index_map = {symbol: index for index, symbol in enumerate(self.symbol_table.symbols)}
# Write Mach-O header
data = mach_header.encode(encoder)
# Write commands
for segment in self.segments:
data += segment.encode_command(encoder, section_offset_map, section_address_map, section_relocations_map)
data += self.symbol_table.encode_command(encoder, symbol_offset_map, string_table_offset)
# Write section data
for segment in self.segments:
for section in segment.sections:
padding = bytearray(roundup(len(data), section.alignment) - len(data))
data += padding + section.content
padding = bytearray(roundup(len(data), self.abi.pointer_size) - len(data))
data += padding
# Write relocations
for segment in self.segments:
for section in segment.sections:
for relocation in section.relocations:
data += relocation.encode(encoder, section_index_map, symbol_index_map)
# Write symbols
for symbol in self.symbol_table.symbols:
data += symbol.encode(encoder, self.string_table.string_index_map, section_index_map, section_address_map)
# Write string table
data += self.string_table.encode()
return data
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy.formats.mscoff.image import MachineType, Image
from peachpy.formats.mscoff.section import Section, TextSection, ReadOnlyDataSection
from peachpy.formats.mscoff.symbol import Symbol, SymbolType, StorageClass, Relocation, RelocationType
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from enum import IntEnum
class StorageClass(IntEnum):
"""
External symbol. If section number is undefined (0), value specifies symbol size. Otherwise value specifies offset
within section.
"""
external = 2
"""Static symbol. value specifies offset within section. value of 0 means that symbol represents section name."""
static = 3
"""A function .bf (beginning of function), .ef (end of function) or .lf (lines in function record) """
function = 101
"""Source-file symbol record. Followed by auxiliary records that name the file"""
file = 103
class SymbolType(IntEnum):
non_function = 0
function = 0x20
class Symbol:
entry_size = 18
def __init__(self):
# Name of the symbol
self.name = None
# Value of the symbol. Interpretation depends on section_index and storage_class
self.value = None
# Relevant section
self.section = None
# Symbol type. Microsoft tools use only 0x20 (function) or 0x0 (not a function)
self.symbol_type = None
# Storage class
self.storage_class = None
def encode_entry(self, encoder, name_index_map, section_index_map):
from peachpy.encoder import Encoder
assert isinstance(encoder, Encoder)
try:
name_8_bytes = encoder.fixed_string(self.name, 8)
except ValueError:
name_index = name_index_map[self.name]
name_8_bytes = encoder.uint32(0) + encoder.uint32(name_index)
section_index = section_index_map[self.section]
auxiliary_entries = 0
return name_8_bytes + \
encoder.uint32(self.value) + \
encoder.uint16(section_index) + \
encoder.uint16(self.symbol_type) + \
encoder.uint8(self.storage_class) + \
encoder.uint8(auxiliary_entries)
class RelocationType(IntEnum):
# Relocation is ignored
absolute = 0
# 32-bit address
x86_address32 = 6
# 32-bit offset relative to image base
x86_imagebase_offset32 = 7
# 16-bit section index
x86_section_index = 10
# 32-bit offset relative to the section
x86_section_offset32 = 11
# CLR token
x86_clr_token = 12
# Unsigned 7-bit offset relative to the section
x86_section_offset7 = 13
# 32-bit offset relative to the end of relocation
x86_relocation_offset32 = 14
# 64-bit address
x86_64_address64 = 1
# 32-bit address
x86_64_address32 = 2
# 32-bit offset relative to image base
x86_64_imagebase_offset32 = 3
# 32-bit offset relative to the end of relocation
x86_64_relocation_offset32 = 4
# 32-bit offset relative to the end of relocation + 1 byte
x86_64_relocation_plus_1_offset32 = 5
# 32-bit offset relative to the end of relocation + 2 bytes
x86_64_relocation_plus_2_offset32 = 6
# 32-bit offset relative to the end of relocation + 3 bytes
x86_64_relocation_plus_3_offset32 = 7
# 32-bit offset relative to the end of relocation + 4 bytes
x86_64_relocation_plus_4_offset32 = 8
# 32-bit offset relative to the end of relocation + 5 bytes
x86_64_relocation_plus_5_offset32 = 9
# 16-bit section index
x86_64_section_index = 10
# 32-bit offset relative to the section
x86_64_section_offset32 = 11
# Unsigned 7-bit offset relative to the section
x86_64_section_offset7 = 12
# CLR token
x86_64_clr_token = 13
class Relocation:
entry_size = 10
def __init__(self, type, offset, symbol):
from peachpy.util import is_int, is_uint32
if not isinstance(type, RelocationType):
raise TypeError("Relocation type %s is not in RelocationType enumeration" % str(type))
if not is_int(offset):
raise TypeError("Offset %s is not an integer" % str(offset))
if not is_uint32(offset):
raise ValueError("Offset %d can not be represented as a 32-bit unsigned integer" % offset)
if not isinstance(symbol, Symbol):
raise TypeError("Symbol %s is not an instance of Symbol type" % str(symbol))
self.type = type
self.offset = offset
self.symbol = symbol
def encode_entry(self, encoder, symbol_index_map, section_address=0):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
assert self.symbol in symbol_index_map
symbol_index = symbol_index_map[self.symbol]
return encoder.uint32(section_address + self.offset) + \
encoder.uint32(symbol_index) + \
encoder.uint16(self.type)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import six
class SectionFlags:
# Section contains executable code
code = 0x00000020
# Section contains initialized data
initialized_data = 0x00000040
# Section contains uninitialized data
uninitialized_data = 0x00000080
# Section contains extended relocations
extended_relocations = 0x01000000
# Section can be discarded as needed
discardable = 0x02000000
# Section can not be cached
uncached = 0x04000000
# Section can not be pageable
unpaged = 0x08000000
# Section data can be shared between process instances
shared = 0x10000000
# Section contains executable data during process execution
executable = 0x20000000
# Section contains readable data during process execution
readable = 0x40000000
# Section contains writable data during process execution
writable = 0x80000000
class Section(object):
header_size = 40
_alignment_flag_map = {
1: 0x00100000,
2: 0x00200000,
4: 0x00300000,
8: 0x00400000,
16: 0x00500000,
32: 0x00600000,
64: 0x00700000,
128: 0x00800000,
256: 0x00900000,
512: 0x00A00000,
1024: 0x00B00000,
2048: 0x00C00000,
4096: 0x00D00000,
8192: 0x00E00000
}
_flag_alignment_map = {flag: alignment for (alignment, flag) in six.iteritems(_alignment_flag_map)}
_alignment_mask = 0x00F00000
def __init__(self, name, flags, alignment=None):
from peachpy.util import is_uint32
if not isinstance(name, str):
raise TypeError("Section name %s is not a string" % str(name))
if not is_uint32(flags):
raise TypeError("Flags %s are not representable as a 32-bit unsigned integer" % str(flags))
super(Section, self).__init__()
# Section name
self.name = name
# Flags for the section
self.flags = (flags & ~Section._alignment_mask) | Section._alignment_flag_map[1]
if alignment is not None:
self.alignment = alignment
self.relocations = list()
self.content = bytearray()
@property
def content_size(self):
return len(self.content)
@property
def alignment(self):
return Section._flag_alignment_map.get(self.flags & Section._alignment_mask, 1)
@alignment.setter
def alignment(self, alignment):
from peachpy.util import is_int
if not is_int(alignment):
raise TypeError("Alignment %s is not an integer" % str(alignment))
if alignment < 0:
raise ValueError("Alignment %d is not a positive integer" % alignment)
if alignment & (alignment - 1) != 0:
raise ValueError("Alignment %d is not a power of 2" % alignment)
if alignment not in Section._alignment_flag_map:
raise ValueError("Alignment %d exceeds maximum alignment (8192)" % alignment)
self.flags = (self.flags & ~Section._alignment_mask) | Section._alignment_flag_map[alignment]
def encode_header(self, encoder, name_index_map, offset, relocations_offset=None, address=None):
from peachpy.encoder import Encoder
assert isinstance(encoder, Encoder)
assert isinstance(name_index_map, dict)
if address is None:
address = 0
if relocations_offset is None:
relocations_offset = 0
line_numbers_offset = 0
line_numbers_count = 0
try:
name_8_bytes = encoder.fixed_string(self.name, 8)
except ValueError:
name_index = name_index_map[self.name]
name_8_bytes = encoder.fixed_string("/" + str(name_index), 8)
return name_8_bytes + \
encoder.uint32(self.content_size) + \
encoder.uint32(address) + \
encoder.uint32(self.content_size) + \
encoder.uint32(offset) + \
encoder.uint32(relocations_offset) + \
encoder.uint32(line_numbers_offset) + \
encoder.uint16(len(self.relocations)) + \
encoder.uint16(line_numbers_count) + \
encoder.uint32(self.flags)
class TextSection(Section):
def __init__(self, name=".text", alignment=None):
super(TextSection, self).__init__(name,
SectionFlags.code | SectionFlags.readable | SectionFlags.executable,
alignment)
class ReadOnlyDataSection(Section):
def __init__(self, name=".rdata", alignment=None):
super(ReadOnlyDataSection, self).__init__(name,
SectionFlags.initialized_data | SectionFlags.readable,
alignment)
class StringTable:
def __init__(self):
self._strings = dict()
self.size = 4
def add(self, string):
import codecs
if string in self._strings:
return self._strings[string]
else:
string_index = self.size
self._strings[string] = string_index
bytestring = codecs.encode(string, "utf-8")
self.size += len(bytestring) + 1
return string_index
def encode(self):
import codecs
import peachpy.encoder
bytestring = peachpy.encoder.Encoder.uint32le(self.size)
for string in sorted(self._strings, key=self._strings.get):
bytestring += codecs.encode(string, "utf8") + b"\x00"
return bytestring
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from enum import IntEnum
class MachineType(IntEnum):
# Machine-independent
unknown = 0
# IA32 (x86)
x86 = 0x14C
# x86-64 (AMD64, Intel64, x64)
x86_64 = 0x8664
# IA64 (Itanium)
ia64 = 0x200
# ARM
arm = 0x1C0
# ARMv7 (Thumb mode only)
armnt = 0x1C4
# ARMv8 AArch64
arm64 = 0xAA64
# EFI bytecode
efi_bytecode = 0xEBC
class Image:
file_header_size = 20
def __init__(self, abi, source=None):
from peachpy.formats.mscoff.section import StringTable
self.abi = abi
self.sections = list()
self.symbols = list()
self.string_table = StringTable()
def add_section(self, section):
from peachpy.formats.mscoff.section import Section
assert isinstance(section, Section)
self.sections.append(section)
def add_symbol(self, symbol):
from peachpy.formats.mscoff.symbol import Symbol
assert isinstance(symbol, Symbol)
self.symbols.append(symbol)
def encode(self):
from peachpy.encoder import Encoder
encoder = Encoder(self.abi.endianness)
# Collect names that need to be encoded in the string table
import codecs
for section in self.sections:
if len(codecs.encode(section.name, "utf8")) > 8:
self.string_table.add(section.name)
for symbol in self.symbols:
if len(codecs.encode(symbol.name, "utf8")) > 8:
self.string_table.add(symbol.name)
# Layout sections offsets
from peachpy.formats.mscoff.section import Section
section_offset_map = dict()
symbol_table_offset = Image.file_header_size + len(self.sections) * Section.header_size
data_offset = symbol_table_offset + self.string_table.size
for symbol in self.symbols:
data_offset += symbol.entry_size
for section in self.sections:
section_offset_map[section] = data_offset
data_offset += section.content_size
# Layout section relocations
from peachpy.formats.mscoff.symbol import Relocation
section_relocations_map = dict()
for section in self.sections:
if section.relocations:
section_relocations_map[section] = data_offset
data_offset += Relocation.entry_size * len(section.relocations)
section_index_map = {section: index + 1 for index, section in enumerate(self.sections)}
symbol_index_map = {symbol: index for index, symbol in enumerate(self.symbols)}
# Write file header
timestamp = 0
file_flags = 0
data = encoder.uint16(self.abi.mscoff_machine_type) + \
encoder.uint16(len(self.sections)) + \
encoder.uint32(timestamp) + \
encoder.uint32(symbol_table_offset) + \
encoder.uint32(len(self.symbols)) + \
encoder.uint16(0) + \
encoder.uint16(file_flags)
# Write section headers
for section in self.sections:
data += section.encode_header(encoder, self.string_table._strings,
section_offset_map[section],
section_relocations_map.get(section))
# Write symbol table and string table (immediately follows symbols table)
for symbol in self.symbols:
data += symbol.encode_entry(encoder, self.string_table._strings, section_index_map)
data += self.string_table.encode()
# Write section content
for section in self.sections:
data += section.content
# Write section relocations
for section in self.sections:
for relocation in section.relocations:
data += relocation.encode_entry(encoder, symbol_index_map)
return data
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy.formats.elf.section import DataSection, TextSection
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from enum import IntEnum
class SymbolBinding(IntEnum):
local = 0
global_ = 1
weak = 2
class SymbolType:
# No type specified (e.g. an absolute symbol)
unspecified = 0
# Data object
data_object = 1
# Function entry point
function = 2
# Symbol associated with a section
section = 3
# Source file associated with the object file
file = 4
class Symbol:
def __init__(self):
# Symbol name
self.name = None
# Value of the symbol (typically offset from the section)
self.value = None
# Size of the data object (0 if size is unknown or meaningless)
self.size = 0
# Binding attribute
self.binding = 0
# Type attribute
self.type = 0
# The relevant section in the section header table
self.section = None
@staticmethod
def get_entry_size(abi):
from peachpy.abi import ABI
assert isinstance(abi, ABI)
assert abi.elf_bitness in [32, 64]
return {32: 16, 64: 24}[abi.elf_bitness]
def encode(self, encoder, name_index_map, section_index_map):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
assert encoder.bitness in [32, 64]
assert self.name in name_index_map
from peachpy.formats.elf.section import SectionIndex
assert self.section is None or isinstance(self.section, SectionIndex) or self.section in section_index_map
name_index = name_index_map[self.name]
section_index = SectionIndex.absolute
if self.section is not None:
if isinstance(self.section, SectionIndex):
section_index = self.section
else:
section_index = section_index_map[self.section]
if encoder.bitness == 32:
return encoder.uint32(name_index) + \
encoder.uint32(self.value) + \
encoder.uint32(self.size) + \
encoder.uint8((self.binding << 4) | (self.type & 0xF)) + \
encoder.uint8(0) + \
encoder.uint16(section_index)
else:
return encoder.uint32(name_index) + \
encoder.uint8((self.binding << 4) | (self.type & 0xF)) + \
encoder.uint8(0) + \
encoder.uint16(section_index) + \
encoder.uint64(self.value) + \
encoder.uint64(self.size)
class RelocationType(IntEnum):
x86_32 = 1
x86_pc32 = 2
x86_got32 = 3
x86_plt32 = 4
x86_copy = 5
x86_glob_dat = 6
x86_jmp_slot = 7
x86_relative = 8
x86_gotoff = 9
x86_gotpc = 10
x86_64_64 = 1
x86_64_pc32 = 2
x86_64_got32 = 3
x86_64_plt32 = 4
x86_64_copy = 5
x86_64_glob_dat = 6
x86_64_jump_slot = 7
x86_64_relative = 8
x86_64_gotpcrel = 9
x86_64_32 = 10
x86_64_32s = 11
x86_64_16 = 12
x86_64_pc16 = 13
x86_64_8 = 14
x86_64_pc8 = 15
x86_64_dtpmod64 = 16
x86_64_dtpoff64 = 17
x86_64_tpoff64 = 18
x86_64_tlsgd = 19
x86_64_tlsld = 20
x86_64_dtpoff32 = 21
x86_64_gottpoff = 22
x86_64_tpoff32 = 23
x86_64_pc64 = 24
x86_64_gotoff64 = 25
x86_64_gotpc32 = 26
x86_64_got64 = 27
x86_64_gotpcrel64 = 28
x86_64_gotpc64 = 29
x86_64_gotplt64 = 30
x86_64_pltoff64 = 31
x86_64_size32 = 32
x86_64_size64 = 33
x86_64_gotpc32_tlsdesc = 34
x86_64_tlsdesc_call = 35
x86_64_tlsdesc = 36
x86_64_irelative = 37
arm_abs32 = 2
arm_rel32 = 3
arm_ldr_pc_g0 = 4
arm_abs16 = 5
arm_abs12 = 6
arm_thm_abs5 = 7
arm_abs8 = 8
arm_sbrel32 = 9
arm_thm_call = 10
arm_thm_pc8 = 11
arm_brel_adj = 12
arm_tls_desc = 13
arm_tls_dtpmod32 = 17
arm_tls_dtpoff32 = 18
arm_tls_tpoff32 = 19
arm_copy = 20
arm_glob_dat = 21
arm_jump_slot = 22
arm_relative = 23
arm_gotoff32 = 24
arm_base_prel = 25
arm_got_brel = 26
arm_plt32 = 27
arm_call = 28
arm_jump24 = 29
arm_thm_jump24 = 30
arm_base_abs = 31
arm_target1 = 38
arm_v4bx = 40
arm_target2 = 41
arm_prel31 = 42
arm_movw_abs_nc = 43
arm_movt_abs = 44
arm_movw_prel_nc = 45
arm_movt_prel = 46
arm_thm_movw_abs_nc = 47
arm_thm_movt_abs = 48
arm_thm_movw_prel_nc = 49
arm_thm_movt_prel = 50
arm_thm_jump19 = 51
arm_thm_jump6 = 52
arm_thm_alu_prel_11_0 = 53
arm_thm_pc12 = 54
arm_abs32_noi = 55
arm_rel32_noi = 56
arm_alu_pc_g0_nc = 57
arm_alu_pc_g0 = 58
arm_alu_pc_g1_nc = 59
arm_alu_pc_g1 = 60
arm_alu_pc_g2 = 61
arm_ldr_pc_g1 = 62
arm_ldr_pc_g2 = 63
arm_ldrs_pc_g0 = 64
arm_ldrs_pc_g1 = 65
arm_ldrs_pc_g2 = 66
arm_ldc_pc_g0 = 67
arm_ldc_pc_g1 = 68
arm_ldc_pc_g2 = 69
arm_alu_sb_g0_nc = 70
arm_alu_sb_g0 = 71
arm_alu_sb_g1_nc = 72
arm_alu_sb_g1 = 73
arm_alu_sb_g2 = 74
arm_ldr_sb_g0 = 75
arm_ldr_sb_g1 = 76
arm_ldr_sb_g2 = 77
arm_ldrs_sb_g0 = 78
arm_ldrs_sb_g1 = 79
arm_ldrs_sb_g2 = 80
arm_ldc_sb_g0 = 81
arm_ldc_sb_g1 = 82
arm_ldc_sb_g2 = 83
arm_movw_brel_nc = 84
arm_movt_brel = 85
arm_movw_brel = 86
arm_thm_movw_brel_nc = 87
arm_thm_movt_brel = 88
arm_thm_movw_brel = 89
arm_tls_gotdesc = 90
arm_tls_call = 91
arm_tls_descseq = 92
arm_thm_tls_call = 93
arm_plt32_abs = 94
arm_got_abs = 95
arm_got_prel = 96
arm_got_brel12 = 97
arm_gotoff12 = 98
arm_gotrelax = 99
arm_thm_jump11 = 102
arm_thm_jump8 = 103
arm_tls_gd32 = 104
arm_tls_ldm32 = 105
arm_tls_ldo32 = 106
arm_tls_ie32 = 107
arm_tls_le32 = 108
arm_tls_ldo12 = 109
arm_tls_le12 = 110
arm_tls_ie12gp = 111
arm_thm_tls_descseq16 = 129
arm_thm_tls_descseq32 = 130
arm_thm_got_brel12 = 131
class RelocationWithAddend:
def __init__(self, type, offset, symbol, addend):
from peachpy.util import is_uint64, is_sint64
assert isinstance(type, RelocationType)
assert is_uint64(offset)
assert isinstance(symbol, Symbol)
assert is_sint64(addend)
self.type = type
self.offset = offset
self.symbol = symbol
self.addend = addend
@staticmethod
def get_entry_size(abi):
from peachpy.abi import ABI
assert isinstance(abi, ABI)
assert abi.elf_bitness in [32, 64]
return {32: 12, 64: 24}[abi.elf_bitness]
def encode(self, encoder, symbol_index_map):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
assert encoder.bitness in [32, 64]
assert self.symbol in symbol_index_map
symbol_index = symbol_index_map[self.symbol]
info = (symbol_index << 32) | self.type
return encoder.unsigned_offset(self.offset) + \
encoder.unsigned_offset(info) + \
encoder.signed_offset(self.addend)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from enum import IntEnum
class SectionFlags(IntEnum):
# Section contains writable data during process execution
writable = 0x1
# Section occupies memory during process execution
allocate = 0x2
# Section contains executable data machine instructions
executable = 0x4
class SectionType(IntEnum):
# Nil section
null = 0
# Program-specific content
program_bits = 1
# Symbol table
symbol_table = 2
# String table
string_table = 3
# Relocations with explicit addend
relocations_with_addend = 4
# Hash table for symbols used in dynamic linking
symbol_hash_table = 5
# Information for dynamic linking
dynamic_linking_info = 6
# Free-form note
note = 7
# Program-specific zero-initialized content
no_bits = 8
# Relocations without explicit addends
relocations = 9
# Minimal symbol table for dynamic linking
dynamic_symbol_table = 11
class SectionIndex(IntEnum):
absolute = 0xFFF1
common = 0xFFF2
undefined = 0x0000
class Section(object):
def __init__(self, name, type, allocate=False, writable=False, executable=False):
# Section name
self.name = name
# Type of the section content
self._type = SectionType.null
self.type = type # Check the type object in property setter
# Properties of section content
self.flags = 0
if allocate:
self.flags |= SectionFlags.allocate
if writable:
self.flags |= SectionFlags.writable
if executable:
self.flags |= SectionFlags.executable
# Section address alignment. Only powers of 2 are allowed. Value 0 or 1 mean no alignment restrictions.
self._alignment = 1
@property
def type(self):
return self._type
@type.setter
def type(self, type):
if not isinstance(type, SectionType):
raise TypeError("Section type %s is not a SectionType enum" % str(type))
self._type = type
@property
def alignment(self):
return self._alignment
@alignment.setter
def alignment(self, alignment):
from peachpy.util import is_uint32
if not is_uint32(alignment):
raise TypeError("Section alignment %s is not representable as a 32-bit unsigned integer" % str(alignment))
if alignment & (alignment - 1) != 0:
raise ValueError("Section alignment %d is not a power of 2" % alignment)
if alignment == 0:
alignment = 1
self._alignment = alignment
@staticmethod
def get_header_size(abi):
from peachpy.abi import ABI
assert isinstance(abi, ABI)
assert abi.elf_bitness in [32, 64]
return {32: 40, 64: 64}[abi.elf_bitness]
def get_content_size(self, abi):
return 0
def encode_header(self, encoder, name_index_map, section_index_map, offset,
address=None, link_section=None, info=None,
content_size=0, entry_size=0):
import peachpy.encoder
from peachpy.util import is_uint64, is_uint32
assert isinstance(encoder, peachpy.encoder.Encoder)
assert isinstance(name_index_map, dict)
assert section_index_map is None or isinstance(section_index_map, dict)
assert offset is None or is_uint64(offset)
assert address is None or is_uint64(address)
assert link_section is None or isinstance(link_section, Section)
assert info is None or is_uint64(info)
assert is_uint64(content_size)
assert is_uint32(entry_size)
assert encoder.bitness in [32, 64]
if encoder.bitness == 32:
assert offset is None or is_uint32(offset)
assert address is None or is_uint32(address)
assert self.name is None or self.name in name_index_map
assert section_index_map is not None or link_section is None
name_index = name_index_map.get(self.name, 0)
if address is None:
address = 0
if offset is None:
offset = 0
link = 0
if link_section is not None:
link = section_index_map[link_section]
if info is None:
info = 0
return encoder.uint32(name_index) + \
encoder.uint32(self.type) + \
encoder.unsigned_offset(self.flags) + \
encoder.unsigned_offset(address) + \
encoder.unsigned_offset(offset) + \
encoder.unsigned_offset(content_size) + \
encoder.uint32(link) + \
encoder.uint32(info) + \
encoder.unsigned_offset(self.alignment) + \
encoder.unsigned_offset(entry_size)
def encode_content(self, encoder, name_index_map, section_index_map, symbol_index_map):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
assert isinstance(name_index_map, dict)
assert section_index_map is None or isinstance(section_index_map, dict)
assert symbol_index_map is None or isinstance(symbol_index_map, dict)
assert encoder.bitness in [32, 64]
return bytearray()
null_section = Section(None, SectionType.null)
class ProgramBitsSection(Section):
def __init__(self, name, allocate=True, writable=False, executable=False):
super(ProgramBitsSection, self).__init__(name, SectionType.program_bits, allocate, writable, executable)
self.content = bytearray()
def get_content_size(self, abi):
return len(self.content)
def encode_header(self, encoder, name_index_map, section_index_map, offset, address=None):
return super(ProgramBitsSection, self).encode_header(encoder, name_index_map, section_index_map, offset,
address=address, content_size=len(self.content))
def encode_content(self, encoder, name_index_map, section_index_map, symbol_index_map):
super(ProgramBitsSection, self).encode_content(encoder, name_index_map, section_index_map, symbol_index_map)
return self.content
class TextSection(ProgramBitsSection):
def __init__(self, name=".text"):
super(TextSection, self).__init__(name, executable=True)
class DataSection(ProgramBitsSection):
def __init__(self, name=".data"):
super(DataSection, self).__init__(name, writable=True)
class ReadOnlyDataSection(ProgramBitsSection):
def __init__(self, name=".rodata"):
super(ReadOnlyDataSection, self).__init__(name)
class StringSection(Section):
def __init__(self, name=".strtab"):
super(StringSection, self).__init__(name, SectionType.string_table)
self._string_index_map = dict()
self.content_size = 0
def add(self, string):
if not string:
return 0
elif string in self._string_index_map:
return self._string_index_map[string]
else:
import codecs
if self.content_size == 0:
self.content_size = 1
string_index = self.content_size
self._string_index_map[string] = string_index
string_bytes = codecs.encode(string, "utf-8")
self.content_size += len(string_bytes) + 1
return string_index
def get_content_size(self, abi):
return self.content_size
def encode_header(self, encoder, name_index_map, section_index_map, offset):
return super(StringSection, self).encode_header(encoder, name_index_map, section_index_map, offset,
content_size=self.content_size)
def encode_content(self, encoder, name_index_map, section_index_map, symbol_index_map):
super(StringSection, self).encode_content(encoder, name_index_map, section_index_map, symbol_index_map)
if self.content_size != 0:
import codecs
bytes = b"\x00"
for string in sorted(self._string_index_map, key=self._string_index_map.get):
bytes += codecs.encode(string, "utf8") + b"\x00"
return bytes
else:
return bytearray()
class SymbolSection(Section):
def __init__(self, name=".symtab", string_table=None):
super(SymbolSection, self).__init__(name, SectionType.symbol_table)
self._symbols_set = set()
self._local_symbols = list()
self._nonlocal_symbols = list()
self._string_table = string_table
@property
def symbol_index_map(self):
symbol_index_map = {symbol: index for index, symbol in enumerate(self._local_symbols)}
local_symbols_count = len(self._local_symbols)
symbol_index_map.update(
{symbol: local_symbols_count + index for index, symbol in enumerate(self._nonlocal_symbols)})
return symbol_index_map
def add(self, symbol):
from peachpy.formats.elf.symbol import Symbol, SymbolBinding
assert isinstance(symbol, Symbol)
if symbol in self._symbols_set:
raise ValueError("Symbol %s is already present in the section %s" % (str(symbol), self.name))
self._symbols_set.add(symbol)
if symbol.binding == SymbolBinding.local:
self._local_symbols.append(symbol)
else:
self._nonlocal_symbols.append(symbol)
def get_content_size(self, abi):
from peachpy.formats.elf.symbol import Symbol
from peachpy.abi import ABI
assert isinstance(abi, ABI)
assert abi.elf_bitness in [32, 64]
entry_size = Symbol.get_entry_size(abi)
return entry_size * (len(self._local_symbols) + len(self._nonlocal_symbols))
def encode_header(self, encoder, name_index_map, section_index_map, offset):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
assert encoder.bitness in [32, 64]
entry_size = {32: 16, 64: 24}[encoder.bitness]
symbols_count = len(self._local_symbols) + len(self._nonlocal_symbols)
return super(SymbolSection, self).encode_header(encoder, name_index_map, section_index_map, offset,
link_section=self._string_table,
info=len(self._local_symbols),
content_size=symbols_count * entry_size,
entry_size=entry_size)
def encode_content(self, encoder, name_index_map, section_index_map, symbol_index_map):
super(SymbolSection, self).encode_content(encoder, name_index_map, section_index_map, symbol_index_map)
# Local symbols must be encoded before non-local symbols. Thus, need to separate the two classes
content = bytearray()
# Step 1: encode local symbols
for symbol in self._local_symbols:
content += symbol.encode(encoder, name_index_map, section_index_map)
# Step 2: encode non-local symbols
for symbol in self._nonlocal_symbols:
content += symbol.encode(encoder, name_index_map, section_index_map)
return content
class RelocationsWithAddendSection(Section):
def __init__(self, reference_section, symbol_table):
super(RelocationsWithAddendSection, self).__init__(".rela" + reference_section.name,
SectionType.relocations_with_addend)
self.reference_section = reference_section
self.symbol_table = symbol_table
self.relocations = list()
def add(self, relocation):
from peachpy.formats.elf.symbol import RelocationWithAddend
assert isinstance(relocation, RelocationWithAddend)
self.relocations.append(relocation)
def get_content_size(self, abi):
from peachpy.abi import ABI
assert isinstance(abi, ABI)
assert abi.elf_bitness in [32, 64]
entry_size = {32: 12, 64: 24}[abi.elf_bitness]
return entry_size * len(self.relocations)
def encode_header(self, encoder, name_index_map, section_index_map, offset):
import peachpy.encoder
assert isinstance(encoder, peachpy.encoder.Encoder)
assert encoder.bitness in [32, 64]
entry_size = {32: 16, 64: 24}[encoder.bitness]
relocations_count = len(self.relocations)
reference_section_index = section_index_map[self.reference_section]
return super(RelocationsWithAddendSection, self).\
encode_header(encoder, name_index_map, section_index_map, offset,
link_section=self.symbol_table,
info=reference_section_index,
content_size=relocations_count * entry_size,
entry_size=entry_size)
def encode_content(self, encoder, name_index_map, section_index_map, symbol_index_map):
super(RelocationsWithAddendSection, self).\
encode_content(encoder, name_index_map, section_index_map, symbol_index_map)
content = bytearray()
for relocation in self.relocations:
content += relocation.encode(encoder, symbol_index_map)
return content
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from enum import IntEnum
class FileType(IntEnum):
# No file type
null = 0
# Relocatable file
object = 1
# Executable file
executable = 2
# Shared object file
dynamic_shared_object = 3
# Core dump file
core_dump = 4
class MachineType(IntEnum):
# Not specified
unspecified = 0
# SPARC
sparc = 2
# IA32 (x86)
x86 = 3
# MIPS
mips = 8
# 32-bit subset of SPARC V9
sparc32plus = 18
# IBM POWER and PowerPC
ppc = 20
# IBM PowerPC 64
ppc64 = 21
# ARM
arm = 40
# SPARC V9 (64-bit)
sparc64 = 43
# IA64 (Itanium)
ia64 = 50
# x86-64 (AMD64, Intel64, x64)
x86_64 = 62
# Intel Knights Ferry
l1om = 180
# Intel Knights Corner
k1om = 181
# ARMv8 AArch64
arm64 = 183
# ATI/AMD GPU code (for any GPU arch)
cal = 125
# nVidia CUDA GPU code (for any GPU arch)
cuda = 190
# HSAIL code (32-bit ELF)
hsail32 = 0xAF5A
# HSAIL code (64-bit ELF)
hsail64 = 0xAF5B
class FormatVersion(IntEnum):
# Invalid version
invalid = 0
# Current version
current = 1
class ElfClass(IntEnum):
# Invalid class
invalid = 0
# 32-bit ELF
class32 = 1
# 64-bit ELF
class64 = 2
class DataEncoding(IntEnum):
# Invalid data encoding
invalid = 0
# Least significant byte first (Little-Endian)
little_endian = 1
# Most significant byte first (Big-Endian)
big_endian = 2
class OSABI(IntEnum):
# No extensions or unspecified
none = 0
# GNU Linux
gnu = 3
# FreeBSD
freebsd = 9
# ATI/AMD GPU ABI
cal = 100
class FileIdentification:
def __init__(self, abi):
self.abi = abi
self.file_version = FormatVersion.current
@property
def as_bytearray(self):
identification = bytearray(16)
identification[0] = 0x7F
identification[1] = ord('E')
identification[2] = ord('L')
identification[3] = ord('F')
identification[4] = self.abi.elf_class
identification[5] = self.abi.elf_data_encoding
identification[6] = self.file_version
return identification
class FileHeader:
def __init__(self, abi):
import peachpy.formats.elf.section
import peachpy.abi
if not isinstance(abi, peachpy.abi.ABI):
raise TypeError("ABI %s must be represented by an ABI object" % str(abi))
if not abi.is_elf_compatible:
raise ValueError("ABI %s is not compatible with ELF" % str(abi))
self.abi = abi
self.identification = FileIdentification(self.abi)
if self.abi.elf_class == ElfClass.class32:
# Size of ELF32 file header, in bytes
self.file_header_size = 52
# Size of program header, in bytes. All program headers have the same size.
self.program_header_entry_size = 32
# Size of a section header, in bytes. All sections have the same size.
self.section_header_entry_size = 40
else:
# Size of ELF64 file header, in bytes
self.file_header_size = 64
# Size of program header, in bytes. All program headers have the same size.
self.program_header_entry_size = 56
# Size of a section header, in bytes. All sections have the same size.
self.section_header_entry_size = 64
self.size = self.file_header_size
self.file_type = FileType.object
self.file_version = FormatVersion.current
self.entry_address = None
self.program_header_table_offset = None
self.section_header_table_offset = None
self.flags = 0
# Number of program headers in the program header table.
self.program_header_entries_count = 0
# Number of section headers in the section header table.
self.section_header_entries_count = 0
# Index of the section header for a section which contains section name string table.
# Usually this section is called ".shstrtab"
self.section_name_string_table_index = peachpy.formats.elf.section.SectionIndex.undefined
@property
def as_bytearray(self):
import peachpy.encoder
encoder = peachpy.encoder.Encoder(self.abi.endianness, self.abi.elf_bitness)
return self.identification.as_bytearray + \
encoder.uint16(self.file_type) + \
encoder.uint16(self.abi.elf_machine_type) + \
encoder.uint32(self.file_version) + \
encoder.unsigned_offset(self.entry_address or 0) + \
encoder.unsigned_offset(self.program_header_table_offset or 0) + \
encoder.unsigned_offset(self.section_header_table_offset or 0) + \
encoder.uint32(self.flags) + \
encoder.uint16(self.file_header_size) + \
encoder.uint16(self.program_header_entry_size) + \
encoder.uint16(self.program_header_entries_count) + \
encoder.uint16(self.section_header_entry_size) + \
encoder.uint16(self.section_header_entries_count) + \
encoder.uint16(self.section_name_string_table_index)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
class Image:
def __init__(self, abi, source=None):
from peachpy.formats.elf.section import null_section, StringSection, SymbolSection, SectionIndex
from peachpy.formats.elf.symbol import Symbol, SymbolBinding, SymbolType
self.abi = abi
self.shstrtab = StringSection(".shstrtab")
self.strtab = StringSection(".strtab")
self.symtab = SymbolSection(string_table=self.strtab)
self.sections = [null_section, self.shstrtab, self.strtab, self.symtab]
self._section_names = set([self.shstrtab.name, self.strtab.name, self.symtab.name])
if source:
source_symbol = Symbol()
source_symbol.value = 0
source_symbol.binding = SymbolBinding.local
source_symbol.type = SymbolType.file
source_symbol.name = source
source_symbol.size = 0
source_symbol.section = SectionIndex.absolute
self.symtab.add(source_symbol)
def add_section(self, section):
from peachpy.formats.elf.section import Section
if not isinstance(section, Section):
raise TypeError("%s is not a Section object" % str(section))
if section.name is not None and section.name in self._section_names:
raise ValueError("Section %s is already present in the image" % section.name)
self.sections.append(section)
self._section_names.add(section.name)
def find_section(self, section_name):
for section in self.sections:
if section.name == section_name:
return section
@property
def as_bytearray(self):
import six
from peachpy.formats.elf.file import FileHeader
from peachpy.formats.elf.section import Section, StringSection, SymbolSection
from peachpy.util import roundup
file_header = FileHeader(self.abi)
file_header.section_header_table_offset = file_header.size
file_header.section_header_entries_count = len(self.sections)
file_header.section_name_string_table_index = 1
data = file_header.as_bytearray
# Collect strings from sections
for section in self.sections:
self.shstrtab.add(section.name)
if isinstance(section, StringSection):
pass
elif isinstance(section, SymbolSection):
for symbol in six.iterkeys(section.symbol_index_map):
self.strtab.add(symbol.name)
# Layout sections
data_offset = file_header.size + Section.get_header_size(self.abi) * len(self.sections)
section_offsets = []
for section in self.sections:
if section.alignment != 0:
data_offset = roundup(data_offset, section.alignment)
section_offsets.append(data_offset)
data_offset += section.get_content_size(self.abi)
from peachpy.encoder import Encoder
encoder = Encoder(self.abi.endianness, self.abi.elf_bitness)
section_index_map = {section: index for index, section in enumerate(self.sections)}
# Write section headers
for section, offset in zip(self.sections, section_offsets):
data += section.encode_header(encoder, self.shstrtab._string_index_map, section_index_map, offset)
# Write section content
for section in self.sections:
padding = bytearray(roundup(len(data), section.alignment) - len(data))
data += padding
data += section.encode_content(encoder,
self.strtab._string_index_map, section_index_map,
self.symtab.symbol_index_map)
return data
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import six
class RegisterAllocator:
def __init__(self):
# Map from virtual register id to internal id of conflicting registers (both virtual and physical)
self.conflicting_registers = dict()
# Map from virtual register id to physical register id
self.register_allocations = dict()
# Map from virtual register id to a list of available physical ids for the allocation
self.allocation_options = dict()
def add_conflicts(self, virtual_id, conflict_internal_ids):
self.conflicting_registers.setdefault(virtual_id, set())
self.conflicting_registers[virtual_id].update(conflict_internal_ids)
for conflict_internal_id in conflict_internal_ids:
if conflict_internal_id < 0:
conflict_virtual_id = -conflict_internal_id
self.conflicting_registers.setdefault(conflict_virtual_id, set())
self.conflicting_registers[conflict_virtual_id].add(-virtual_id)
def set_allocation_options(self, abi, register_kind):
physical_ids = \
[reg.physical_id for reg in abi.volatile_registers if reg.kind == register_kind] + \
[reg.physical_id for reg in abi.argument_registers if reg.kind == register_kind][::-1] + \
[reg.physical_id for reg in abi.callee_save_registers if reg.kind == register_kind]
for reg in abi.restricted_registers:
if reg.kind == register_kind and reg.physical_id in physical_ids:
physical_ids.remove(reg.physical_id)
# TODO: account the pre-allocated registers in allocation options
for virtual_id, conflict_internal_ids in six.iteritems(self.conflicting_registers):
self.allocation_options[virtual_id] = \
[physical_id for physical_id in physical_ids if physical_id not in conflict_internal_ids]
def _bind_register(self, virtual_id, physical_id):
assert virtual_id > 0
assert physical_id >= 0
# TODO: handle situation before allocation options are initialized
for conflict_internal_id in self.conflicting_registers[virtual_id]:
if conflict_internal_id < 0:
conflict_virtual_id = -conflict_internal_id
try:
self.allocation_options[conflict_virtual_id].remove(physical_id)
except ValueError:
pass
self.allocation_options[virtual_id] = [physical_id]
self.register_allocations[virtual_id] = physical_id
def try_allocate_register(self, virtual_id, physical_id):
assert virtual_id > 0
if physical_id in self.allocation_options[virtual_id]:
self._bind_register(virtual_id, physical_id)
return True
else:
return False
def _allocation_alternatives(self, virtual_id, physical_id):
return sum(1 for reg in self.allocation_options[virtual_id] if reg != physical_id)
def _min_conflict_allocation_alternatives(self, virtual_id, physical_id):
try:
return min(self._allocation_alternatives(-conflict_internal_id, physical_id)
for conflict_internal_id in self.conflicting_registers[virtual_id]
if conflict_internal_id < 0)
except ValueError:
return 0
def allocate_registers(self):
unallocated_registers = [reg for reg in six.iterkeys(self.allocation_options)
if reg not in self.register_allocations]
while unallocated_registers:
# Choose the virtual register for which there are the least allocation options
virtual_id = min(unallocated_registers, key=lambda reg: len(self.allocation_options[reg]))
if not self.allocation_options[virtual_id]:
raise Exception("No physical registers for virtual register %d" % virtual_id)
if self.conflicting_registers[virtual_id]:
# Choose the physical register for which there are most alternatives
physical_id = max(self.allocation_options[virtual_id],
key=lambda reg: self._min_conflict_allocation_alternatives(virtual_id, reg))
else:
# Choose the first available physical register
physical_id = self.allocation_options[virtual_id].pop()
self._bind_register(virtual_id, physical_id)
unallocated_registers.remove(virtual_id)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy.common.regalloc import RegisterAllocator
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
active_function = None
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import six
class Register(object):
GPType = 1
WMMXType = 2
VFPType = 3
def __init__(self):
super(Register, self).__init__()
self.number = None
self.size = None
def __lt__(self, other):
return self.number < other.number
def __le__(self, other):
return self.number <= other.number
def __eq__(self, other):
return isinstance(other, Register) and self.number == other.number
def __ne__(self, other):
return not isinstance(other, Register) or self.number != other.number
def __gt__(self, other):
return self.number > other.number
def __ge__(self, other):
return self.number >= other.number
def __contains__(self, register):
if self.id == register.id:
register_mask = register.get_mask()
return (self.mask & register_mask) == register_mask
else:
return False
def __hash__(self):
return self.number
@property
def id(self):
return self.number >> 12
@property
def mask(self):
return self.number & 0xFFF
@property
def bitboard(self):
assert not self.is_virtual
if isinstance(self, GeneralPurposeRegister) or isinstance(self, WMMXRegister) or isinstance(self, SRegister):
return 0x1 << self.get_physical_number()
elif isinstance(self, DRegister):
return 0x3 << (self.get_physical_number() * 2)
elif isinstance(self, QRegister):
return 0xF << (self.get_physical_number() * 4)
@staticmethod
def from_parts(id, mask, expand=False):
if mask == 0x001:
# General-purpose register
return GeneralPurposeRegister((id << 12) | mask)
elif mask == 0x002:
# WMMX register
return WMMXRegister((id << 12) | 0x002)
elif (mask & ~0x7F0) == 0x000:
# VFP or NEON register
if (mask & 0x7F0) == 0x0F0:
return QRegister((id << 12) | mask)
elif ((mask & 0x7F0) == 0x030) or ((mask & 0x7F0) == 0x0C0) or ((mask & 0x7F0) == 0x300):
return DRegister((id << 12) | mask)
elif (mask & (mask - 1)) == 0:
return SRegister((id << 12) | mask)
else:
if expand and ((mask & ~0x0F0) == 0):
return QRegister((id << 12) | 0x0F0)
else:
raise ValueError("Invalid register mask %s" % hex(mask))
else:
raise ValueError("Invalid register mask %s" % hex(mask))
@staticmethod
def from_bitboard(bitboard, regtype):
if regtype == Register.GPType:
return {0x0001: r0,
0x0002: r1,
0x0004: r2,
0x0008: r3,
0x0010: r4,
0x0020: r5,
0x0040: r6,
0x0080: r7,
0x0100: r8,
0x0200: r9,
0x0400: r10,
0x0800: r11,
0x1000: r12,
0x2000: sp,
0x4000: lr,
0x8000: pc}[bitboard]
elif regtype == Register.WMMXType:
return {0x0001: wr0,
0x0002: wr1,
0x0004: wr2,
0x0008: wr3,
0x0010: wr4,
0x0020: wr5,
0x0040: wr6,
0x0080: wr7,
0x0100: wr8,
0x0200: wr9,
0x0400: wr10,
0x0800: wr11,
0x1000: wr12,
0x2000: wr13,
0x4000: wr14,
0x8000: wr15}[bitboard]
elif regtype == Register.VFPType:
return {0x00000001: s0,
0x00000002: s1,
0x00000004: s2,
0x00000008: s3,
0x00000010: s4,
0x00000020: s5,
0x00000040: s6,
0x00000080: s7,
0x00000100: s8,
0x00000200: s9,
0x00000400: s10,
0x00000800: s11,
0x00001000: s12,
0x00002000: s13,
0x00004000: s14,
0x00008000: s15,
0x00010000: s16,
0x00020000: s17,
0x00040000: s18,
0x00080000: s19,
0x00100000: s20,
0x00200000: s21,
0x00400000: s22,
0x00800000: s23,
0x01000000: s24,
0x02000000: s25,
0x04000000: s26,
0x08000000: s27,
0x10000000: s28,
0x20000000: s29,
0x40000000: s30,
0x80000000: s31,
0x0000000000000003: d0,
0x000000000000000C: d1,
0x0000000000000030: d2,
0x00000000000000C0: d3,
0x0000000000000300: d4,
0x0000000000000C00: d5,
0x0000000000003000: d6,
0x000000000000C000: d7,
0x0000000000030000: d8,
0x00000000000C0000: d9,
0x0000000000300000: d10,
0x0000000000C00000: d11,
0x0000000003000000: d12,
0x000000000C000000: d13,
0x0000000030000000: d14,
0x00000000C0000000: d15,
0x0000000300000000: d16,
0x0000000C00000000: d17,
0x0000003000000000: d18,
0x000000C000000000: d19,
0x0000030000000000: d20,
0x00000C0000000000: d21,
0x0000300000000000: d22,
0x0000C00000000000: d23,
0x0003000000000000: d24,
0x000C000000000000: d25,
0x0030000000000000: d26,
0x00C0000000000000: d27,
0x0300000000000000: d28,
0x0C00000000000000: d29,
0x3000000000000000: d30,
0xC000000000000000: d31,
0x000000000000000F: q0,
0x00000000000000F0: q1,
0x0000000000000F00: q2,
0x000000000000F000: q3,
0x00000000000F0000: q4,
0x0000000000F00000: q5,
0x000000000F000000: q6,
0x00000000F0000000: q7,
0x0000000F00000000: q8,
0x000000F000000000: q9,
0x00000F0000000000: q10,
0x0000F00000000000: q11,
0x000F000000000000: q12,
0x00F0000000000000: q13,
0x0F00000000000000: q14,
0xF000000000000000: q15}[bitboard]
def extend_bitboard(self, bitboard):
physical_register = Register.from_bitboard(bitboard, self.type)
if isinstance(self, SRegister) and self.parent and self.parent.parent:
physical_register = physical_register.get_parent().get_parent()
elif (isinstance(self, SRegister) or isinstance(self, DRegister)) and self.parent:
physical_register = physical_register.get_parent()
return physical_register.get_bitboard()
@property
def is_virtual(self):
return self.number >= 0x40000
def bind(self, register):
assert self.is_virtual
assert not register.is_virtual
if isinstance(register, GeneralPurposeRegister) or isinstance(register, WMMXRegister):
self.number = (self.number & 0xFFF) | (register.id << 12)
elif isinstance(register, SRegister):
self.number = register.number
elif isinstance(register, DRegister):
if isinstance(self, DRegister):
self.number = register.number
elif isinstance(self, SRegister):
if register.mask == 0x030 and self.mask == 0x100:
self.number = (register.id << 12) | 0x010
elif register.mask == 0x030 and self.mask == 0x200:
self.number = (register.id << 12) | 0x020
elif register.mask == 0x0C0 and self.mask == 0x100:
self.number = (register.id << 12) | 0x040
elif register.mask == 0x0C0 and self.mask == 0x200:
self.number = (register.id << 12) | 0x080
else:
assert False
else:
assert False
elif isinstance(register, QRegister):
if isinstance(self, QRegister):
self.number = register.number
elif isinstance(self, DRegister):
self.number = (register.id << 12) | self.mask
elif isinstance(self, SRegister):
self.number = (register.id << 12) | self.mask
else:
assert False
assert not self.is_virtual
class GeneralPurposeRegister(Register):
_name_to_number_map = {'r0': 0x20001,
'r1': 0x21001,
'r2': 0x22001,
'r3': 0x23001,
'r4': 0x24001,
'r5': 0x25001,
'r6': 0x26001,
'r7': 0x27001,
'r8': 0x28001,
'r9': 0x29001,
'r10': 0x2A001,
'r11': 0x2B001,
'r12': 0x2C001,
'sp': 0x2D001,
'lr': 0x2E001,
'pc': 0x2F001}
_number_to_name_map = {0x20001: 'r0',
0x21001: 'r1',
0x22001: 'r2',
0x23001: 'r3',
0x24001: 'r4',
0x25001: 'r5',
0x26001: 'r6',
0x27001: 'r7',
0x28001: 'r8',
0x29001: 'r9',
0x2A001: 'r10',
0x2B001: 'r11',
0x2C001: 'r12',
0x2D001: 'sp',
0x2E001: 'lr',
0x2F001: 'pc'}
def __init__(self, id=None):
super(GeneralPurposeRegister, self).__init__()
if id is None:
from peachpy.arm.function import active_function
self.number = active_function.allocate_general_purpose_register()
self.type = Register.GPType
self.size = 4
elif isinstance(id, int):
self.number = id
self.type = Register.GPType
self.size = 4
elif isinstance(id, str):
if id in GeneralPurposeRegister._name_to_number_map:
self.number = GeneralPurposeRegister._name_to_number_map[id]
self.type = Register.GPType
self.size = 4
else:
raise ValueError('Unknown register name: {0}'.format(id))
elif isinstance(id, GeneralPurposeRegister):
self.number = id.number
self.type = id.type
self.size = id.size
else:
raise TypeError('Invalid register id')
def get_physical_number(self):
return {0x20001: 0,
0x21001: 1,
0x22001: 2,
0x23001: 3,
0x24001: 4,
0x25001: 5,
0x26001: 6,
0x27001: 7,
0x28001: 8,
0x29001: 9,
0x2A001: 10,
0x2B001: 11,
0x2C001: 12,
0x2D001: 13,
0x2E001: 14,
0x2F001: 15}[self.number]
@staticmethod
def is_compatible_bitboard(bitboard):
return bitboard in {0x0001, 0x0002, 0x0004, 0x0008,
0x0010, 0x0020, 0x0040, 0x0080,
0x0100, 0x0200, 0x0400, 0x0800,
0x1000, 0x2000, 0x4000, 0x8000}
def __str__(self):
if self.is_virtual:
return 'gp-vreg<{0}>'.format((self.number - 0x40000) >> 12)
else:
return GeneralPurposeRegister._number_to_name_map[self.number]
def __neg__(self):
return NegatedGeneralPurposeRegister(self)
def wb(self):
return GeneralPurposeRegisterWriteback(self)
def LSL(self, shift):
return ShiftedGeneralPurposeRegister(self, "LSL", shift)
def LSR(self, shift):
return ShiftedGeneralPurposeRegister(self, "LSR", shift)
def ASR(self, shift):
return ShiftedGeneralPurposeRegister(self, "ASR", shift)
def ROR(self, shift):
return ShiftedGeneralPurposeRegister(self, "ROR", shift)
def RRX(self):
return ShiftedGeneralPurposeRegister(self, "RRX")
r0 = GeneralPurposeRegister('r0')
r1 = GeneralPurposeRegister('r1')
r2 = GeneralPurposeRegister('r2')
r3 = GeneralPurposeRegister('r3')
r4 = GeneralPurposeRegister('r4')
r5 = GeneralPurposeRegister('r5')
r6 = GeneralPurposeRegister('r6')
r7 = GeneralPurposeRegister('r7')
r8 = GeneralPurposeRegister('r8')
r9 = GeneralPurposeRegister('r9')
r10 = GeneralPurposeRegister('r10')
r11 = GeneralPurposeRegister('r11')
r12 = GeneralPurposeRegister('r12')
sp = GeneralPurposeRegister('sp')
lr = GeneralPurposeRegister('lr')
pc = GeneralPurposeRegister('pc')
class GeneralPurposeRegisterWriteback(GeneralPurposeRegister):
def __init__(self, register):
if isinstance(register, GeneralPurposeRegister):
super(GeneralPurposeRegisterWriteback, self).__init__(register)
self.register = register
else:
raise TypeError('Register parameter is not an instance of GeneralPurposeRegister')
def __str__(self):
return str(self.register) + "!"
class NegatedGeneralPurposeRegister:
def __init__(self, register):
if isinstance(register, GeneralPurposeRegister):
self.register = register
else:
raise TypeError('Register parameter is not an instance of GeneralPurposeRegister')
def __str__(self):
return "-" + str(self.register)
class ShiftedGeneralPurposeRegister:
def __init__(self, register, kind, shift=None):
if isinstance(register, GeneralPurposeRegister):
self.register = register
if kind in {'LSR', 'ASR'}:
if 1 <= shift <= 32:
self.shift = int(shift)
self.type = kind
else:
raise ValueError("Shift is beyond the allowed range (1 to 32)")
elif kind in {'LSL', 'ROR'}:
if 1 <= shift <= 31:
self.shift = int(shift)
self.type = kind
else:
raise ValueError("Shift is beyond the allowed range (1 to 31)")
elif kind == 'RRX':
if shift is None:
self.shift = shift
self.type = kind
else:
raise ValueError("Shift parameter is not allowed for RRX modificator")
else:
raise ValueError("Illegal shift kind %s" % kind)
else:
raise TypeError("Register parameter must be a general-purpose register")
def __str__(self):
if self.type != 'RRX':
return str(self.register) + ", " + self.type + " #" + str(self.shift)
else:
return str(self.register) + ", " + self.type
class WMMXRegister(Register):
_name_to_number_map = {'wr0': 0x10002,
'wr1': 0x11002,
'wr2': 0x12002,
'wr3': 0x13002,
'wr4': 0x14002,
'wr5': 0x15002,
'wr6': 0x16002,
'wr7': 0x17002,
'wr8': 0x18002,
'wr9': 0x19002,
'wr10': 0x1A002,
'wr11': 0x1B002,
'wr12': 0x1C002,
'wr13': 0x1D002,
'wr14': 0x1E002,
'wr15': 0x1F002}
_number_to_name_map = {0x10002: 'wr0',
0x11002: 'wr1',
0x12002: 'wr2',
0x13002: 'wr3',
0x14002: 'wr4',
0x15002: 'wr5',
0x16002: 'wr6',
0x17002: 'wr7',
0x18002: 'wr8',
0x19002: 'wr9',
0x1A002: 'wr10',
0x1B002: 'wr11',
0x1C002: 'wr12',
0x1D002: 'wr13',
0x1E002: 'wr14',
0x1F002: 'wr15'}
def __init__(self, id=None):
super(WMMXRegister, self).__init__()
if id is None:
from peachpy.arm.function import active_function
self.number = active_function.allocate_wmmx_register()
self.regtype = Register.WMMXType
self.size = 8
elif isinstance(id, int):
self.number = id
self.regtype = Register.WMMXType
self.size = 8
elif isinstance(id, str):
if id in WMMXRegister._name_to_number_map:
self.number = WMMXRegister._name_to_number_map[id]
self.regtype = Register.WMMXType
self.size = 8
else:
raise ValueError('Unknown register name: {0}'.format(id))
elif isinstance(id, WMMXRegister):
self.number = id.number
self.regtype = id.regtype
self.size = id.size
else:
raise TypeError(
'Register id is neither a name of an architectural mmx register, nor an id of a virtual register')
@staticmethod
def is_compatible_bitboard(bitboard):
return bitboard in {0x0001, 0x0002, 0x0004, 0x0008,
0x0010, 0x0020, 0x0040, 0x0080,
0x0100, 0x0200, 0x0400, 0x0800,
0x1000, 0x2000, 0x4000, 0x8000}
def __str__(self):
if self.is_virtual:
return 'wmmx-vreg<{0}>'.format((self.number - 0x40000) >> 12)
else:
return WMMXRegister._number_to_name_map[self.number]
wr0 = WMMXRegister('wr0')
wr1 = WMMXRegister('wr1')
wr2 = WMMXRegister('wr2')
wr3 = WMMXRegister('wr3')
wr4 = WMMXRegister('wr4')
wr5 = WMMXRegister('wr5')
wr6 = WMMXRegister('wr6')
wr7 = WMMXRegister('wr7')
wr8 = WMMXRegister('wr8')
wr9 = WMMXRegister('wr9')
wr10 = WMMXRegister('wr10')
wr11 = WMMXRegister('wr11')
wr12 = WMMXRegister('wr12')
wr13 = WMMXRegister('wr13')
wr14 = WMMXRegister('wr14')
wr15 = WMMXRegister('wr15')
class SRegister(Register):
_name_to_number_map = {'s0': 0x00010,
's1': 0x00020,
's2': 0x00040,
's3': 0x00080,
's4': 0x01010,
's5': 0x01020,
's6': 0x01040,
's7': 0x01080,
's8': 0x02010,
's9': 0x02020,
's10': 0x02040,
's11': 0x02080,
's12': 0x03010,
's13': 0x03020,
's14': 0x03040,
's15': 0x03080,
's16': 0x04010,
's17': 0x04020,
's18': 0x04040,
's19': 0x04080,
's20': 0x05010,
's21': 0x05020,
's22': 0x05040,
's23': 0x05080,
's24': 0x06010,
's25': 0x06020,
's26': 0x06040,
's27': 0x06080,
's28': 0x07010,
's29': 0x07020,
's30': 0x07040,
's31': 0x07080}
_number_to_name_map = {0x00010: 's0',
0x00020: 's1',
0x00040: 's2',
0x00080: 's3',
0x01010: 's4',
0x01020: 's5',
0x01040: 's6',
0x01080: 's7',
0x02010: 's8',
0x02020: 's9',
0x02040: 's10',
0x02080: 's11',
0x03010: 's12',
0x03020: 's13',
0x03040: 's14',
0x03080: 's15',
0x04010: 's16',
0x04020: 's17',
0x04040: 's18',
0x04080: 's19',
0x05010: 's20',
0x05020: 's21',
0x05040: 's22',
0x05080: 's23',
0x06010: 's24',
0x06020: 's25',
0x06040: 's26',
0x06080: 's27',
0x07010: 's28',
0x07020: 's29',
0x07040: 's30',
0x07080: 's31'}
def __init__(self, id=None):
super(SRegister, self).__init__()
if id is None:
from peachpy.arm.function import active_function
self.number = active_function.allocate_s_register()
self.type = Register.VFPType
self.size = 4
elif isinstance(id, int):
self.number = id
self.type = Register.VFPType
self.size = 4
elif isinstance(id, str):
if id in SRegister._name_to_number_map:
self.number = SRegister._name_to_number_map[id]
self.type = Register.VFPType
self.size = 4
else:
raise ValueError('Unknown register name: {0}'.format(id))
elif isinstance(id, SRegister):
self.number = id.number
self.type = id.type
self.size = id.size
else:
raise TypeError(
'Register id is neither a name of an architectural S register, nor an id of a virtual register')
def get_physical_number(self):
assert not self.is_virtual
return {0x00010: 0,
0x00020: 1,
0x00040: 2,
0x00080: 3,
0x01010: 4,
0x01020: 5,
0x01040: 6,
0x01080: 7,
0x02010: 8,
0x02020: 9,
0x02040: 10,
0x02080: 11,
0x03010: 12,
0x03020: 13,
0x03040: 14,
0x03080: 15,
0x04010: 16,
0x04020: 17,
0x04040: 18,
0x04080: 19,
0x05010: 20,
0x05020: 21,
0x05040: 22,
0x05080: 23,
0x06010: 24,
0x06020: 25,
0x06040: 26,
0x06080: 27,
0x07010: 28,
0x07020: 29,
0x07040: 30,
0x07080: 31}[self.number]
def is_compatible_bitboard(self, bitboard):
if self.mask == 0x400:
return bitboard in {0x00000001, 0x00000002, 0x00000004, 0x00000008,
0x00000010, 0x00000020, 0x00000040, 0x00000080,
0x00000100, 0x00000200, 0x00000400, 0x00000800,
0x00001000, 0x00002000, 0x00004000, 0x00008000,
0x00010000, 0x00020000, 0x00040000, 0x00080000,
0x00100000, 0x00200000, 0x00400000, 0x00800000,
0x01000000, 0x02000000, 0x04000000, 0x08000000,
0x10000000, 0x20000000, 0x40000000, 0x80000000}
elif self.mask == 0x200:
return bitboard in {0x00000002, 0x00000008,
0x00000020, 0x00000080,
0x00000200, 0x00000800,
0x00002000, 0x00008000,
0x00020000, 0x00080000,
0x00200000, 0x00800000,
0x02000000, 0x08000000,
0x20000000, 0x80000000}
elif self.mask == 0x100:
return bitboard in {0x00000001, 0x00000004,
0x00000010, 0x00000040,
0x00000100, 0x00000400,
0x00001000, 0x00004000,
0x00010000, 0x00040000,
0x00100000, 0x00400000,
0x01000000, 0x04000000,
0x10000000, 0x40000000}
elif self.mask == 0x080:
return bitboard in {0x00000008, 0x00000080, 0x00000800, 0x00008000,
0x00080000, 0x00800000, 0x08000000, 0x80000000}
elif self.mask == 0x040:
return bitboard in {0x00000004, 0x00000040, 0x00000400, 0x00004000,
0x00040000, 0x00400000, 0x04000000, 0x40000000}
elif self.mask == 0x020:
return bitboard in {0x00000002, 0x00000020, 0x00000200, 0x00002000,
0x00020000, 0x00200000, 0x02000000, 0x20000000}
elif self.mask == 0x010:
return bitboard in {0x00000001, 0x00000010, 0x00000100, 0x00001000,
0x00010000, 0x00100000, 0x01000000, 0x10000000}
else:
assert False
def __str__(self):
if self.is_virtual:
return 's-vreg<{0}>'.format((self.number - 0x40000) >> 12)
else:
return SRegister._number_to_name_map[self.number]
@property
def parent(self):
mask = self.mask
parent_mask = {0x400: None,
0x200: 0x300,
0x100: 0x300,
0x080: 0x0C0,
0x040: 0x0C0,
0x020: 0x030,
0x010: 0x030}[mask]
if parent_mask:
return DRegister(self.number | parent_mask)
s0 = SRegister('s0')
s1 = SRegister('s1')
s2 = SRegister('s2')
s3 = SRegister('s3')
s4 = SRegister('s4')
s5 = SRegister('s5')
s6 = SRegister('s6')
s7 = SRegister('s7')
s8 = SRegister('s8')
s9 = SRegister('s9')
s10 = SRegister('s10')
s11 = SRegister('s11')
s12 = SRegister('s12')
s13 = SRegister('s13')
s14 = SRegister('s14')
s15 = SRegister('s15')
s16 = SRegister('s16')
s17 = SRegister('s17')
s18 = SRegister('s18')
s19 = SRegister('s19')
s20 = SRegister('s20')
s21 = SRegister('s21')
s22 = SRegister('s22')
s23 = SRegister('s23')
s24 = SRegister('s24')
s25 = SRegister('s25')
s26 = SRegister('s26')
s27 = SRegister('s27')
s28 = SRegister('s28')
s29 = SRegister('s29')
s30 = SRegister('s30')
s31 = SRegister('s31')
class DRegister(Register):
_name_to_number_map = {'d0': 0x00030,
'd1': 0x000C0,
'd2': 0x01030,
'd3': 0x010C0,
'd4': 0x02030,
'd5': 0x020C0,
'd6': 0x03030,
'd7': 0x030C0,
'd8': 0x04030,
'd9': 0x040C0,
'd10': 0x05030,
'd11': 0x050C0,
'd12': 0x06030,
'd13': 0x060C0,
'd14': 0x07030,
'd15': 0x070C0,
'd16': 0x08030,
'd17': 0x080C0,
'd18': 0x09030,
'd19': 0x090C0,
'd20': 0x0A030,
'd21': 0x0A0C0,
'd22': 0x0B030,
'd23': 0x0B0C0,
'd24': 0x0C030,
'd25': 0x0C0C0,
'd26': 0x0D030,
'd27': 0x0D0C0,
'd28': 0x0E030,
'd29': 0x0E0C0,
'd30': 0x0F030,
'd31': 0x0F0C0}
_number_to_name_map = {0x00030: 'd0',
0x000C0: 'd1',
0x01030: 'd2',
0x010C0: 'd3',
0x02030: 'd4',
0x020C0: 'd5',
0x03030: 'd6',
0x030C0: 'd7',
0x04030: 'd8',
0x040C0: 'd9',
0x05030: 'd10',
0x050C0: 'd11',
0x06030: 'd12',
0x060C0: 'd13',
0x07030: 'd14',
0x070C0: 'd15',
0x08030: 'd16',
0x080C0: 'd17',
0x09030: 'd18',
0x090C0: 'd19',
0x0A030: 'd20',
0x0A0C0: 'd21',
0x0B030: 'd22',
0x0B0C0: 'd23',
0x0C030: 'd24',
0x0C0C0: 'd25',
0x0D030: 'd26',
0x0D0C0: 'd27',
0x0E030: 'd28',
0x0E0C0: 'd29',
0x0F030: 'd30',
0x0F0C0: 'd31'}
def __init__(self, id=None):
super(DRegister, self).__init__()
if id is None:
from peachpy.arm.function import active_function
self.number = active_function.allocate_d_register()
self.type = Register.VFPType
self.size = 8
elif isinstance(id, int):
self.number = id
self.type = Register.VFPType
self.size = 8
elif isinstance(id, str):
if id in DRegister._name_to_number_map:
self.number = DRegister._name_to_number_map[id]
self.type = Register.VFPType
self.size = 8
else:
raise ValueError('Unknown register name: {0}'.format(id))
elif isinstance(id, DRegister):
self.number = id.number
self.type = id.type
self.size = id.size
else:
raise TypeError(
'Register id is neither a name of an architectural D register, nor an id of a virtual register')
def get_physical_number(self):
assert not self.is_virtual
return {0x00030: 0,
0x000C0: 1,
0x01030: 2,
0x010C0: 3,
0x02030: 4,
0x020C0: 5,
0x03030: 6,
0x030C0: 7,
0x04030: 8,
0x040C0: 9,
0x05030: 10,
0x050C0: 11,
0x06030: 12,
0x060C0: 13,
0x07030: 14,
0x070C0: 15,
0x08030: 16,
0x080C0: 17,
0x09030: 18,
0x090C0: 19,
0x0A030: 20,
0x0A0C0: 21,
0x0B030: 22,
0x0B0C0: 23,
0x0C030: 24,
0x0C0C0: 25,
0x0D030: 26,
0x0D0C0: 27,
0x0E030: 28,
0x0E0C0: 29,
0x0F030: 30,
0x0F0C0: 31}[self.number]
@property
def is_extended(self):
return self.number >= 0x08000
def is_compatible_bitboard(self, bitboard):
if self.mask == 0x300:
return bitboard in {0x0000000000000003, 0x000000000000000C,
0x0000000000000030, 0x00000000000000C0,
0x0000000000000300, 0x0000000000000C00,
0x0000000000003000, 0x000000000000C000,
0x0000000000030000, 0x00000000000C0000,
0x0000000000300000, 0x0000000000C00000,
0x0000000003000000, 0x000000000C000000,
0x0000000030000000, 0x00000000C0000000,
0x0000000300000000, 0x0000000C00000000,
0x0000003000000000, 0x000000C000000000,
0x0000030000000000, 0x00000C0000000000,
0x0000300000000000, 0x0000C00000000000,
0x0003000000000000, 0x000C000000000000,
0x0030000000000000, 0x00C0000000000000,
0x0300000000000000, 0x0C00000000000000,
0x3000000000000000, 0xC000000000000000}
elif self.mask == 0x0C0:
return bitboard in {0x000000000000000C,
0x00000000000000C0,
0x0000000000000C00,
0x000000000000C000,
0x00000000000C0000,
0x0000000000C00000,
0x000000000C000000,
0x00000000C0000000,
0x0000000C00000000,
0x000000C000000000,
0x00000C0000000000,
0x0000C00000000000,
0x000C000000000000,
0x00C0000000000000,
0x0C00000000000000,
0xC000000000000000}
elif self.mask == 0x030:
return bitboard in {0x0000000000000003,
0x0000000000000030,
0x0000000000000300,
0x0000000000003000,
0x0000000000030000,
0x0000000000300000,
0x0000000003000000,
0x0000000030000000,
0x0000000300000000,
0x0000003000000000,
0x0000030000000000,
0x0000300000000000,
0x0003000000000000,
0x0030000000000000,
0x0300000000000000,
0x3000000000000000}
else:
assert False
def __str__(self):
if self.is_virtual:
return 'd-vreg<{0}>'.format((self.number - 0x40000) >> 12)
else:
return DRegister._number_to_name_map[self.number]
def __getitem__(self, key):
if isinstance(key, slice) and key.start is None and key.stop is None and key.step is None:
return DRegisterLanes(self)
else:
raise ValueError("Illegal subscript value %s" % key)
@property
def parent(self):
if self.mask != 0x300:
return QRegister(self.number | 0x0F0)
@property
def low_part(self):
if (self.number & ~0xFFF) == 0x300:
return SRegister((self.number & ~0xFFF) | 0x100)
elif (self.number & ~0xFFF) == 0x0C0:
return SRegister((self.number & ~0xFFF) | 0x040)
else:
return SRegister((self.number & ~0xFFF) | 0x010)
@property
def high_part(self):
if (self.number & ~0xFFF) == 0x300:
return SRegister((self.number & ~0xFFF) | 0x200)
elif (self.number & ~0xFFF) == 0x0C0:
return SRegister((self.number & ~0xFFF) | 0x080)
else:
return SRegister((self.number & ~0xFFF) | 0x020)
d0 = DRegister('d0')
d1 = DRegister('d1')
d2 = DRegister('d2')
d3 = DRegister('d3')
d4 = DRegister('d4')
d5 = DRegister('d5')
d6 = DRegister('d6')
d7 = DRegister('d7')
d8 = DRegister('d8')
d9 = DRegister('d9')
d10 = DRegister('d10')
d11 = DRegister('d11')
d12 = DRegister('d12')
d13 = DRegister('d13')
d14 = DRegister('d14')
d15 = DRegister('d15')
d16 = DRegister('d16')
d17 = DRegister('d17')
d18 = DRegister('d18')
d19 = DRegister('d19')
d20 = DRegister('d20')
d21 = DRegister('d21')
d22 = DRegister('d22')
d23 = DRegister('d23')
d24 = DRegister('d24')
d25 = DRegister('d25')
d26 = DRegister('d26')
d27 = DRegister('d27')
d28 = DRegister('d28')
d29 = DRegister('d29')
d30 = DRegister('d30')
d31 = DRegister('d31')
class DRegisterLanes:
def __init__(self, register):
if isinstance(register, DRegister):
self.register = register
else:
raise TypeError('Register parameter is not an instance of DRegister')
def __str__(self):
return str(self.register) + "[]"
class QRegister(Register):
name_to_number_map = {'q0': 0x000F0,
'q1': 0x010F0,
'q2': 0x020F0,
'q3': 0x030F0,
'q4': 0x040F0,
'q5': 0x050F0,
'q6': 0x060F0,
'q7': 0x070F0,
'q8': 0x080F0,
'q9': 0x090F0,
'q10': 0x0A0F0,
'q11': 0x0B0F0,
'q12': 0x0C0F0,
'q13': 0x0D0F0,
'q14': 0x0E0F0,
'q15': 0x0F0F0}
number_to_name_map = {0x000F0: 'q0',
0x010F0: 'q1',
0x020F0: 'q2',
0x030F0: 'q3',
0x040F0: 'q4',
0x050F0: 'q5',
0x060F0: 'q6',
0x070F0: 'q7',
0x080F0: 'q8',
0x090F0: 'q9',
0x0A0F0: 'q10',
0x0B0F0: 'q11',
0x0C0F0: 'q12',
0x0D0F0: 'q13',
0x0E0F0: 'q14',
0x0F0F0: 'q15'}
def __init__(self, id=None):
super(QRegister, self).__init__()
if id is None:
from peachpy.arm.function import active_function
self.number = active_function.allocate_q_register()
self.type = Register.VFPType
self.size = 16
elif isinstance(id, int):
self.number = id
self.type = Register.VFPType
self.size = 16
elif isinstance(id, str):
if id in QRegister.name_to_number_map:
self.number = QRegister.name_to_number_map[id]
self.type = Register.VFPType
self.size = 16
else:
raise ValueError('Unknown register name: {0}'.format(id))
elif isinstance(id, QRegister):
self.number = id.number
self.type = id.type
self.size = id.size
else:
raise TypeError(
'Register id is neither a name of an architectural Q register, nor an id of a virtual register')
def get_physical_number(self):
assert not self.is_virtual
return {0x000F0: 0,
0x010F0: 1,
0x020F0: 2,
0x030F0: 3,
0x040F0: 4,
0x050F0: 5,
0x060F0: 6,
0x070F0: 7,
0x080F0: 8,
0x090F0: 9,
0x0A0F0: 10,
0x0B0F0: 11,
0x0C0F0: 12,
0x0D0F0: 13,
0x0E0F0: 14,
0x0F0F0: 15}[self.number]
def is_compatible_bitboard(self, bitboard):
if self.mask == 0x0F0:
return bitboard in {0x000000000000000F,
0x00000000000000F0,
0x0000000000000F00,
0x000000000000F000,
0x00000000000F0000,
0x0000000000F00000,
0x000000000F000000,
0x00000000F0000000,
0x0000000F00000000,
0x000000F000000000,
0x00000F0000000000,
0x0000F00000000000,
0x000F000000000000,
0x00F0000000000000,
0x0F00000000000000,
0xF000000000000000}
else:
assert False
@property
def is_extended(self):
return self.number >= 0x08000
def __str__(self):
if self.is_virtual:
return 'q-vreg<{0}>'.format((self.number - 0x40000) >> 12)
else:
return QRegister.number_to_name_map[self.number]
@property
def low_part(self):
return DRegister((self.number & ~0xFFF) | 0x030)
@property
def high_part(self):
return DRegister((self.number & ~0xFFF) | 0x0C0)
q0 = QRegister('q0')
q1 = QRegister('q1')
q2 = QRegister('q2')
q3 = QRegister('q3')
q4 = QRegister('q4')
q5 = QRegister('q5')
q6 = QRegister('q6')
q7 = QRegister('q7')
q8 = QRegister('q8')
q9 = QRegister('q9')
q10 = QRegister('q10')
q11 = QRegister('q11')
q12 = QRegister('q12')
q13 = QRegister('q13')
q14 = QRegister('q14')
q15 = QRegister('q15')
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy.arm.isa import Extension, Extensions
class Microarchitecture:
def __init__(self, name, extensions):
self.name = name
self.extensions = Extensions(*[prerequisite for extension in extensions
for prerequisite in extension.prerequisites])
def is_supported(self, extension):
return extension in self.extensions
@property
def id(self):
return self.name.replace(" ", "")
def __add__(self, extension):
return Microarchitecture(self.name, self.extensions + extension)
def __sub__(self, extension):
return Microarchitecture(self.name, self.extensions - extension)
def __str__(self):
return self.name
Default = None
XScale = None
ARM9, ARM11 = None, None
CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15 = None, None, None, None, None, None
Scorpion, Krait = None, None
PJ4 = None
Microarchitecture.Default = Microarchitecture('Default', Extension.All)
Microarchitecture.XScale = Microarchitecture('XScale', [Extension.V5E, Extension.Thumb,
Extension.XScale, Extension.WMMX2])
Microarchitecture.ARM9 = Microarchitecture('ARM9', [Extension.V5E, Extension.Thumb])
Microarchitecture.ARM11 = Microarchitecture('ARM11', [Extension.V6K, Extension.Thumb,
Extension.VFP2, Extension.VFPVectorMode])
Microarchitecture.CortexA5 = Microarchitecture('Cortex A5', [Extension.V7MP, Extension.Thumb2,
Extension.VFP4, Extension.VFPd32, Extension.NEON2])
Microarchitecture.CortexA7 = Microarchitecture('Cortex A7', [Extension.V7MP, Extension.Thumb2, Extension.Div,
Extension.VFP4, Extension.VFPd32, Extension.NEON2])
Microarchitecture.CortexA8 = Microarchitecture('Cortex A8', [Extension.V7, Extension.Thumb2,
Extension.VFP3, Extension.VFPd32, Extension.NEON])
Microarchitecture.CortexA9 = Microarchitecture('Cortex A9', [Extension.V7MP, Extension.Thumb2,
Extension.VFP3, Extension.VFPHP])
Microarchitecture.CortexA12 = Microarchitecture('Cortex A12', [Extension.V7MP, Extension.Thumb2, Extension.Div,
Extension.VFP4, Extension.VFPd32, Extension.NEON2])
Microarchitecture.CortexA15 = Microarchitecture('Cortex A15', [Extension.V7MP, Extension.Thumb2, Extension.Div,
Extension.VFP4, Extension.VFPd32, Extension.NEON2])
Microarchitecture.Scorpion = Microarchitecture('Scorpion', [Extension.V7MP, Extension.Thumb2,
Extension.VFP3, Extension.VFPd32, Extension.VFPHP,
Extension.NEON, Extension.NEONHP])
Microarchitecture.Krait = Microarchitecture('Krait', [Extension.V7MP, Extension.Thumb2, Extension.Div,
Extension.VFP4, Extension.VFPd32, Extension.NEON2])
Microarchitecture.PJ4 = Microarchitecture('PJ4', [Extension.V7, Extension.Thumb2,
Extension.VFP3, Extension.WMMX2])
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
class QuasiInstruction(object):
def __init__(self, name, origin=None):
super(QuasiInstruction, self).__init__()
self.name = name
self.line_number = origin[1][2] if origin else None
self.source_file = origin[1][1] if origin else None
self.source_code = origin[1][4][0].strip() if origin else None
class Instruction(QuasiInstruction):
def __init__(self, name, operands, isa_extensions=None, origin=None):
import peachpy.x86_64.isa
super(Instruction, self).__init__(name, origin=origin)
self.operands = operands
self.isa_extensions = peachpy.x86_64.isa.Extensions(isa_extensions)
self.available_registers = set()
self.live_registers = set()
def __len__(self):
return self.size
def __str__(self):
return self.name + " " + ", ".join(map(str, self.operands))
def get_registers_list(self):
return [register for operand in self.operands for register in operand.get_registers_list()]
def get_local_variable(self):
for operand in self.operands:
if isinstance(operand, Operand) and operand.is_local_variable():
return operand.variable
def get_constant(self):
for operand in self.operands:
if isinstance(operand, Operand) and operand.is_constant():
return operand.constant
class Operand(object):
RegisterType = 1
RegisterListType = 2
RegisterLanesType = 3
RegisterLanesListType = 4
ShiftedRegisterType = 5
AddressRegisterType = 6
ImmediateType = 7
MemoryType = 8
ConstantType = 9
VariableType = 10
LabelType = 11
NoneType = 12
def __init__(self, operand):
super(Operand, self).__init__()
import copy
from peachpy import Constant
from peachpy.arm.registers import Register, GeneralPurposeRegister, \
GeneralPurposeRegisterWriteback, ShiftedGeneralPurposeRegister, DRegisterLanes
from peachpy.arm.function import LocalVariable
from peachpy.arm.pseudo import Label
from peachpy.util import is_int
if isinstance(operand, GeneralPurposeRegisterWriteback):
self.type = Operand.AddressRegisterType
self.register = copy.deepcopy(operand.register)
elif isinstance(operand, Register):
self.type = Operand.RegisterType
self.register = copy.deepcopy(operand)
elif isinstance(operand, DRegisterLanes):
self.type = Operand.RegisterLanesType
self.lanes = copy.deepcopy(operand)
elif isinstance(operand, ShiftedGeneralPurposeRegister):
self.type = Operand.ShiftedRegisterType
self.register = copy.deepcopy(operand)
elif isinstance(operand, tuple):
if all(isinstance(element, Register) for element in operand):
if len(set((register.type, register.size) for register in operand)) == 1:
self.type = Operand.RegisterListType
self.register_list = copy.deepcopy(operand)
else:
raise TypeError('Register in the list {0} have different types'.format(", ".join(operand)))
elif all(isinstance(element, DRegisterLanes) for element in operand):
self.type = Operand.RegisterLanesListType
self.register_list = copy.deepcopy(operand)
else:
raise TypeError('Unknown tuple elements {0}'.format(operand))
elif is_int(operand):
if -9223372036854775808 <= operand <= 18446744073709551615:
self.type = Operand.ImmediateType
self.immediate = operand
else:
raise ValueError('The immediate operand {0} is not a 64-bit value'.format(operand))
elif isinstance(operand, list):
if len(operand) == 1 and (isinstance(operand[0], GeneralPurposeRegister) or isinstance(operand[0],
GeneralPurposeRegisterWriteback)):
self.type = Operand.MemoryType
self.base = copy.deepcopy(operand[0])
self.offset = None
elif len(operand) == 2 and isinstance(operand[0], GeneralPurposeRegister) and (
isinstance(operand[1], int) or isinstance(operand[1], ShiftedGeneralPurposeRegister)):
self.type = Operand.MemoryType
self.base = copy.deepcopy(operand[0])
self.offset = operand[1]
else:
raise ValueError('Memory operand must be a list with only one or two elements')
elif isinstance(operand, Constant):
self.type = Operand.ConstantType
self.constant = operand
self.size = operand.size * operand.repeats
elif isinstance(operand, LocalVariable):
self.type = Operand.VariableType
self.variable = operand
self.size = operand.size * 8
elif isinstance(operand, str):
self.type = Operand.LabelType
self.label = operand
elif isinstance(operand, Label):
self.type = Operand.LabelType
self.label = operand.name
elif operand is None:
self.type = Operand.NoneType
else:
raise TypeError('The operand {0} is not a valid assembly instruction operand'.format(operand))
def __str__(self):
if self.is_constant():
if self.constant.prefix is None:
return "[rel {0}]".format(self.constant.label)
else:
return "[rel {1}.{0}]".format(self.constant.label, self.constant.prefix)
elif self.is_local_variable():
return str(self.variable)
elif self.is_memory_address():
from peachpy.arm.registers import GeneralPurposeRegisterWriteback
if self.offset is None:
if isinstance(self.base, GeneralPurposeRegisterWriteback):
return "[" + str(self.base.register) + "]!"
else:
return "[" + str(self.base) + "]"
else:
if isinstance(self.base, GeneralPurposeRegisterWriteback):
return "[" + str(self.base.register) + ", #" + str(self.offset) + "]!"
else:
if isinstance(self.offset, int):
return "[" + str(self.base) + ", #" + str(self.offset) + "]"
else:
return "[" + str(self.base) + ", " + str(self.offset) + "]"
elif self.is_register() or self.is_shifted_general_purpose_register():
return str(self.register)
elif self.is_register_lanes():
return str(self.register)
elif self.is_address_register():
return str(self.register) + "!"
elif self.is_register_list() or self.is_register_lanes_list():
return "{" + ", ".join(map(str, self.register_list)) + "}"
elif self.is_label():
return self.label
elif self.is_immediate():
return "#" + str(self.immediate)
elif self.is_none():
return ""
else:
raise TypeError('Unsupported operand type')
def __eq__(self, other):
if isinstance(other, Operand) and self.type == other.type:
if self.is_immediate():
return self.immediate == other.immediate
elif self.is_register():
return self.register == other.register
elif self.is_memory_address():
return self.base == other.base and self.offset == other.offset
elif self.is_label():
return self.label == other.label
else:
return False
else:
return False
def __ne__(self, other):
return not self == other
def is_none(self):
return self.type == Operand.NoneType
def is_immediate(self):
return self.type == Operand.ImmediateType
def is_immediate5(self):
return self.is_immediate and 0 <= self.immediate <= 31
def is_modified_immediate12(self):
def rotate32(x, n):
return ((x >> n) | (x << (32 - n))) & 0xFFFFFFFF
if self.type == Operand.ImmediateType:
if -2147483648 <= self.immediate <= 4294967295:
dword = self.immediate & 0xFFFFFFFF
ndword = (~self.immediate) & 0xFFFFFFFF
return any(
[(rotate32(dword, n) & 0xFFFFFF00) == 0x00000000 or (rotate32(ndword, n) & 0xFFFFFF00) == 0x00000000
for n in range(0, 32, 2)])
else:
return False
else:
return False
def is_neon_modified_immediate8(self):
return self.type == Operand.ImmediateType and -128 <= self.immediate <= 255
def is_neon_modified_immediate16(self):
if self.type == Operand.ImmediateType and -32768 <= self.immediate <= 65535:
hword = self.immediate & 0xFFFF
return (hword & 0xFF00) == 0 or (hword & 0x00FF) == 0
else:
return False
def is_neon_modified_immediate32(self):
if self.type == Operand.ImmediateType and -2147483648 <= self.immediate <= 4294967295:
word = self.immediate & 0xFFFFFFFF
return (word & 0x00FFFFFF) == 0x00000000 or \
(word & 0xFF00FFFF) == 0x00000000 or \
(word & 0xFFFF00FF) == 0x00000000 or \
(word & 0xFFFFFF00) == 0x00000000 or \
(word & 0xFF00FFFF) == 0x0000FFFF or \
(word & 0xFFFF00FF) == 0x000000FF
else:
return False
def is_neon_modified_immediate64(self):
if self.type == Operand.ImmediateType and -2147483648 <= self.immediate <= 4294967295:
dword = self.immediate & 0xFFFFFFFFFFFFFFFF
byte = dword & 0xFF
return all([(dword >> n) & 0xFF == byte for n in range(8, 64, 8)])
else:
return False
def is_preindexed_memory_address(self):
from peachpy.arm.registers import GeneralPurposeRegisterWriteback
return self.type == Operand.MemoryType and \
self.offset is not None and \
isinstance(self.base, GeneralPurposeRegisterWriteback)
def is_memory_address(self, offset_bits=None, allow_writeback=True):
from peachpy.arm.registers import GeneralPurposeRegisterWriteback, ShiftedGeneralPurposeRegister
if self.type == Operand.MemoryType:
if not allow_writeback and isinstance(self.base, GeneralPurposeRegisterWriteback):
return False
else:
if self.offset is None or offset_bits is None:
return True
elif isinstance(self.offset, ShiftedGeneralPurposeRegister):
return True
else:
bound = (1 << offset_bits) - 1
return -bound <= self.offset <= bound
else:
return False
def is_writeback_memory_address(self):
from peachpy.arm.registers import GeneralPurposeRegisterWriteback
return self.type == Operand.MemoryType and isinstance(self.base, GeneralPurposeRegisterWriteback)
def is_memory_address_offset8_mod4(self):
return self.type == Operand.MemoryType and \
(self.offset is None or -1020 <= self.offset <= 1020 and self.offset % 4 == 0)
def is_offset8(self):
return self.type == Operand.ImmediateType and -255 <= self.immediate <= 255
def is_offset12(self):
return self.type == Operand.ImmediateType and -4095 <= self.immediate <= 4095
def is_label(self):
return self.type == Operand.LabelType
def is_constant(self):
return self.type == Operand.ConstantType
def is_local_variable(self):
return self.type == Operand.VariableType
def is_register(self):
return self.type == Operand.RegisterType
def is_register_lanes(self):
return self.type == Operand.RegisterLanesType
def is_register_list(self):
return self.is_register() or self.type == Operand.RegisterListType
def is_register_lanes_list(self):
return self.type == Operand.RegisterLanesListType
def is_general_purpose_register(self):
from peachpy.arm.registers import GeneralPurposeRegister
return self.type == Operand.RegisterType and \
isinstance(self.register, GeneralPurposeRegister)
def is_shifted_general_purpose_register(self):
from peachpy.arm.registers import ShiftedGeneralPurposeRegister
return self.is_general_purpose_register() or self.type == Operand.ShiftedRegisterType and \
isinstance(self.register, ShiftedGeneralPurposeRegister)
def is_general_purpose_register_list(self):
from peachpy.arm.registers import GeneralPurposeRegister
return self.is_general_purpose_register() or self.type == Operand.RegisterListType and \
isinstance(self.register_list[0], GeneralPurposeRegister)
def is_address_register(self):
return self.is_general_purpose_register() or self.type == Operand.AddressRegisterType
def is_wmmx_register(self):
from peachpy.arm.registers import WMMXRegister
return self.type == Operand.RegisterType and isinstance(self.register, WMMXRegister)
def is_s_register(self):
from peachpy.arm.registers import SRegister
return self.type == Operand.RegisterType and isinstance(self.register, SRegister)
def is_s_register_list(self):
from peachpy.arm.registers import SRegister
return self.is_s_register() or \
self.type == Operand.RegisterListType and isinstance(self.register_list[0], SRegister)
def is_d_register(self):
from peachpy.arm.registers import DRegister
return self.type == Operand.RegisterType and isinstance(self.register, DRegister)
def is_d_register_list(self):
from peachpy.arm.registers import DRegister
return self.is_d_register() or \
self.type == Operand.RegisterListType and isinstance(self.register_list[0], DRegister)
def is_q_register(self):
from peachpy.arm.registers import QRegister
return self.type == Operand.RegisterType and isinstance(self.register, QRegister)
def is_vldst1_register_list(self):
from peachpy.arm.registers import DRegister
return self.is_d_register() or \
self.type == Operand.RegisterListType and \
isinstance(self.register_list[0], DRegister) and \
len(self.register_list) <= 4
def is_vldst1_register_lanes_list(self):
from peachpy.arm.registers import DRegisterLanes
return self.type == Operand.RegisterLanesType and \
isinstance(self.register, DRegisterLanes) or \
self.type == Operand.RegisterLanesListType and \
all(isinstance(register, DRegisterLanes) for register in self.register_list)
def is_general_purpose_memory_address(self):
return self.type == Operand.MemoryType and -4095 <= self.offset <= 4095
def get_registers_list(self):
from peachpy.arm.registers import sp, GeneralPurposeRegisterWriteback, ShiftedGeneralPurposeRegister
if self.is_address_register() or self.is_register() or self.is_register_lanes():
return [self.register]
elif self.is_shifted_general_purpose_register():
return [self.register.register]
elif self.is_constant():
return list()
elif self.is_local_variable():
return [sp]
elif self.is_register_list():
return list(self.register_list)
elif self.is_register_lanes_list():
return [register_lanes.register for register_lanes in self.register_list]
elif self.is_memory_address():
if isinstance(self.base, GeneralPurposeRegisterWriteback):
return [self.base.register]
else:
if isinstance(self.offset, ShiftedGeneralPurposeRegister):
return [self.base, self.offset.register]
else:
return [self.base]
else:
return list()
def get_writeback_registers_list(self):
if self.is_memory_address():
from peachpy.arm.registers import GeneralPurposeRegisterWriteback
if isinstance(self.base, GeneralPurposeRegisterWriteback):
return [self.base.register]
else:
return [self.base]
else:
return list()
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import inspect
import peachpy.stream
from peachpy.arm.instructions import QuasiInstruction, Instruction, Operand
class Label(object):
def __init__(self, name):
super(Label, self).__init__()
self.name = name
def __str__(self):
return "<LABEL:" + self.name + '>'
class LabelQuasiInstruction(QuasiInstruction):
def __init__(self, name, origin=None):
super(LabelQuasiInstruction, self).__init__('<LABEL>', origin=origin)
if name.is_label():
self.name = name.label
else:
raise TypeError("Name must be an Label or string")
self.input_branches = set()
def __str__(self):
return "L" + self.name + ':'
class AlignQuasiInstruction(QuasiInstruction):
supported_alignments = [2, 4, 8, 16, 32]
def __init__(self, alignment, origin=None):
super(AlignQuasiInstruction, self).__init__('<ALIGN>', origin=origin)
if isinstance(alignment, int):
if alignment in AlignQuasiInstruction.supported_alignments:
self.alignment = alignment
else:
raise ValueError("The alignment value {0} is not in the list of supported alignments ({1})"
.format(alignment, ", ".join(AlignQuasiInstruction.supported_alignments)))
else:
raise TypeError("The alignment value must be an integer")
def __str__(self):
return "align {0}".format(self.alignment)
class LoadConstantPseudoInstruction(Instruction):
def __init__(self, destination, source, origin=None):
super(LoadConstantPseudoInstruction, self).__init__('<LOAD-CONSTANT>', origin=origin)
if destination.is_register():
self.destination = destination
else:
raise ValueError('Load constant pseudo-instruction expects a register as a destination')
if source.is_constant():
if destination.register.size * 8 == source.constant.size * source.constant.repeats:
self.source = source
elif destination.register.size == 16 and \
source.constant.size == 64 and \
source.constant.repeats == 1 and \
source.constant.basic_type == 'float64':
self.source = source
elif destination.register.size == 16 and \
source.constant.size == 32 and \
source.constant.repeats == 1 and \
source.constant.basic_type == 'float32':
self.source = source
else:
raise ValueError('The size of constant should be the same as the size of register')
else:
raise ValueError('Load constant pseudo-instruction expects a Constant instance as a source')
self.size = 4 + 4
def __str__(self):
return "LOAD.CONSTANT {0} = {1}".format(self.destination, self.source)
def get_input_registers_list(self):
return list()
def get_output_registers_list(self):
return [self.destination.register]
def get_constant(self):
return self.source.constant
def get_local_variable(self):
return None
class LoadArgumentPseudoInstruction(Instruction):
def __init__(self, destination, source, origin=None):
from peachpy.arm.function import active_function
from peachpy import Argument, Yep32f, Yep64f
super(LoadArgumentPseudoInstruction, self).__init__('<LOAD-PARAMETER>', [destination, source], origin=origin)
if isinstance(source, Argument):
argument = active_function.find_argument(source)
if argument is not None:
self.argument = argument
else:
raise ValueError('{0} is not an argument of the active function'.format(source))
else:
raise TypeError('LOAD.ARGUMENT expects an Argument object as a source')
if destination.is_general_purpose_register() and \
(argument.is_integer or argument.is_pointer or argument.is_codeunit):
if destination.register.size >= argument.size:
self.destination = destination
else:
raise ValueError('Destination register %s is too narrow for the argument %s' % (destination, argument))
elif destination.is_s_register() and source.ctype == Yep32f:
self.destination = destination
elif destination.is_d_register() and source.ctype == Yep64f:
self.destination = destination
else:
raise ValueError('Unsupported combination of instruction operands')
def __str__(self):
return "LOAD.ARGUMENT {0} = {1}".format(self.destination, self.argument)
def get_input_registers_list(self):
from peachpy.arm.registers import sp
if self.argument.register:
return [self.argument.register]
else:
return [sp]
def get_output_registers_list(self):
return [self.destination.register]
class ReturnInstruction(QuasiInstruction):
def __init__(self, return_value=None, origin=None):
super(ReturnInstruction, self).__init__('RETURN', origin=origin)
if return_value.is_none():
self.return_value = None
elif return_value.is_modified_immediate12():
self.return_value = return_value.immediate
else:
raise ValueError('Return value is not representable as a 12-bit modified immediate integer')
def to_instruction_list(self):
from peachpy.stream import InstructionStream
from peachpy.arm.registers import r0, lr
from peachpy.arm.generic import MOV, BX
return_instructions = InstructionStream()
with return_instructions:
if self.return_value is None:
pass
else:
MOV(r0, self.return_value)
BX(lr)
return list(iter(return_instructions))
def __str__(self):
return "RETURN {0}".format(self.return_value)
def get_input_registers_list(self):
from peachpy.arm.registers import sp
return [sp]
def get_output_registers_list(self):
from peachpy.arm.registers import sp
return [sp]
def get_constant(self):
return None
def get_local_variable(self):
return None
class AssumeInitializedPseudoInstruction(Instruction):
def __init__(self, destination, origin=None):
super(AssumeInitializedPseudoInstruction, self).__init__('<ASSUME-INITIALIZED>', origin=origin)
if destination.is_register():
self.destination = destination
else:
raise ValueError('Assume initialized pseudo-instruction expects a register as a destination')
self.size = 0
def __str__(self):
return "ASSUME.INITIALIZED {0}".format(self.destination)
def get_input_registers_list(self):
return list()
def get_output_registers_list(self):
return [self.destination.register]
def get_constant(self):
return None
def get_local_variable(self):
return None
def LABEL(name):
instruction = LabelQuasiInstruction(Operand(name))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class Loop:
def __init__(self, name=None):
if name is None:
import inspect
import re
source_line = inspect.stack()[1][4][0].strip()
match = re.match("(?:\\w+\\.)*(\\w+)\\s*=\\s*(?:\\w+\\.)*Loop\\(.*\\)", source_line)
if match:
name = match.group(1)
else:
match = re.match("\\s*with\\s+(?:\\w+\\.)*Loop\\(.*\\)\\s+as\\s+(\\w+)\\s*:\\s*", source_line)
if match:
name = match.group(1)
else:
raise ValueError('Loop name is unspecified')
self.name = name
self.begin = Label(self.name + ".begin")
self.end = Label(self.name + ".end")
def __enter__(self):
LABEL(self.begin)
return self
def __exit__(self, type, value, traceback):
if type is None:
LABEL(self.end)
def ALIGN(alignment):
instruction = AlignQuasiInstruction(alignment)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RETURN(return_value=None):
instruction = ReturnInstruction(Operand(return_value))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class LOAD:
@staticmethod
def CONSTANT(destination, source):
from peachpy.arm.function import active_function
origin = inspect.stack() if active_function.collect_origin else None
instruction = LoadConstantPseudoInstruction(Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def ARGUMENT(destination, source):
from peachpy.arm.function import active_function
origin = inspect.stack() if active_function.collect_origin else None
instruction = LoadArgumentPseudoInstruction(Operand(destination), source, origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def ARGUMENTS():
from peachpy.arm.function import active_function
from peachpy.arm.registers import GeneralPurposeRegister, SRegister, DRegister
from peachpy import Yep32f, Yep64f
registers = list()
for argument in active_function.arguments:
if argument.is_pointer or argument.is_integer or argument.is_codeunit:
if argument.size <= 4:
register = GeneralPurposeRegister()
LOAD.ARGUMENT(register, argument)
else:
raise NotImplementedError("TODO: Handle 8-byte integers")
elif argument.is_floating_point:
if argument.ctype == Yep32f:
register = SRegister()
LOAD.ARGUMENT(register, argument)
elif argument.ctype == Yep64f:
register = DRegister()
LOAD.ARGUMENT(register, argument)
else:
raise TypeError("Unknown floating-point type %s" % argument.ctype)
else:
raise TypeError("Unknown argument type %s" % argument.ctype)
registers.append(register)
return tuple(registers)
@staticmethod
def ZERO(destination, ctype):
if isinstance(ctype, peachpy.c.Type):
# if isinstance(destination, SRegister):
# PXOR( destination, destination )
# elif isinstance(destination, DRegister):
# if ctype.is_floating_point():
# if Target.has_avx():
# SIMD_XOR = {4: VXORPS, 8: VXORPD }[ctype.get_size()]
# else:
# SIMD_XOR = {4: XORPS, 8: XORPD}[ctype.get_size()]
# else:
# SIMD_XOR = VPXOR if Target.has_avx() else PXOR
# SIMD_XOR( destination, destination )
# elif isinstance(destination, QRegister):
# LOAD.ZERO( destination.get_oword(), ctype )
# else:
raise TypeError("Unsupported type of destination register")
else:
raise TypeError("Type must be a C type")
@staticmethod
def ELEMENT(destination, source, ctype, increment_pointer=False):
from peachpy.arm.function import active_function
from peachpy.arm.instructions import Operand
from peachpy.arm.registers import Register, GeneralPurposeRegister, SRegister, DRegister
from peachpy.arm.generic import LDR, LDRH, LDRSH, LDRB, LDRSB, ADD
from peachpy.arm.vfpneon import VLDR
from peachpy import Type
if not isinstance(ctype, Type):
raise TypeError("Type must be a C type")
if isinstance(destination, Register):
raise TypeError("Destination must be a register")
if not Operand(source).is_memory_address():
raise TypeError("Source must be a memory operand")
memory_size = ctype.get_size(active_function.abi)
if isinstance(destination, GeneralPurposeRegister):
if ctype.is_unsigned_integer:
if memory_size == 4:
if increment_pointer:
LDR(destination, source, memory_size)
else:
LDR(destination, source)
elif memory_size == 2:
if increment_pointer:
LDRH(destination, source, memory_size)
else:
LDRH(destination, source)
elif memory_size == 1:
if increment_pointer:
LDRB(destination, source, memory_size)
else:
LDRB(destination, source)
else:
raise ValueError("Invalid memory operand size {0}".format(memory_size))
elif ctype.is_signed_integer:
if memory_size == 4:
if increment_pointer:
LDR(destination, source, memory_size)
else:
LDR(destination, source)
elif memory_size == 2:
if increment_pointer:
LDRSH(destination, source, memory_size)
else:
LDRSH(destination, source)
elif memory_size == 1:
if increment_pointer:
LDRSB(destination, source, memory_size)
else:
LDRSB(destination, source)
else:
raise ValueError("Invalid memory operand size {0}".format(memory_size))
else:
raise TypeError("Invalid memory operand type")
elif isinstance(destination, SRegister):
if ctype.is_floating_point:
if memory_size == 4:
VLDR(destination, source)
if increment_pointer:
address_register = Operand(source).get_registers_list()[0]
ADD(address_register, memory_size)
else:
raise ValueError("Invalid memory operand size {0}".format(memory_size))
else:
raise TypeError("Invalid memory operand type")
elif isinstance(destination, DRegister):
if ctype.is_floating_point:
if memory_size == 8:
VLDR(destination, source)
if increment_pointer:
address_register = Operand(source).get_registers_list()[0]
ADD(address_register, memory_size)
else:
raise ValueError("Invalid memory operand size {0}".format(memory_size))
else:
raise TypeError("Invalid memory operand type")
else:
raise TypeError("Unsupported destination type")
class STORE:
@staticmethod
def ELEMENT(destination, source, ctype, increment_pointer=False):
from peachpy.arm.function import active_function
from peachpy.arm.instructions import Operand
from peachpy.arm.registers import GeneralPurposeRegister, SRegister, DRegister
from peachpy.arm.generic import STR, STRH, STRB, ADD
from peachpy.arm.vfpneon import VSTR
if isinstance(ctype, peachpy.c.Type):
if Operand(destination).is_memory_address():
if Operand(source).is_register():
memory_size = ctype.get_size(active_function.abi)
if isinstance(source, GeneralPurposeRegister):
if ctype.is_integer():
if memory_size == 4:
if increment_pointer:
STR(source, destination, memory_size)
else:
STR(source, destination)
elif memory_size == 2:
if increment_pointer:
STRH(source, destination, memory_size)
else:
STRH(source, destination)
elif memory_size == 1:
if increment_pointer:
STRB(source, destination, memory_size)
else:
STRB(source, destination)
else:
raise ValueError("Invalid memory operand size {0}".format(memory_size))
else:
raise TypeError("Invalid memory operand type")
elif isinstance(source, SRegister):
if ctype.is_floating_point():
if memory_size == 4:
VSTR(source, destination)
if increment_pointer:
address_register = Operand(destination).get_registers_list()[0]
ADD(address_register, memory_size)
else:
raise ValueError("Invalid memory operand size {0}".format(memory_size))
else:
raise TypeError("Invalid memory operand type")
elif isinstance(source, DRegister):
if ctype.is_floating_point():
if memory_size == 8:
VSTR(source, destination)
if increment_pointer:
address_register = Operand(destination).get_registers_list()[0]
ADD(address_register, memory_size)
else:
raise ValueError("Invalid memory operand size {0}".format(memory_size))
else:
raise TypeError("Invalid memory operand type")
else:
raise TypeError("Source must be a general-purpose register")
else:
raise TypeError("Source must be a register")
else:
raise TypeError("Destination must be a memory operand")
else:
raise TypeError("Type must be a C type")
class ASSUME:
@staticmethod
def INITIALIZED(destination):
from peachpy.arm.function import active_function
origin = inspect.stack() if active_function.collect_origin else None
instruction = AssumeInitializedPseudoInstruction(Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class INIT:
@staticmethod
def ONCE(register_class, constant, register=None):
if register is None:
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
register = register_class()
instruction = LoadConstantPseudoInstruction(Operand(register), Operand(constant), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return register
else:
return register
class REDUCE:
@staticmethod
def SUM(acc, input_type, output_type):
raise NotImplementedError("Needs ARM implementation")
@staticmethod
def MAX(acc, input_type, output_type):
raise NotImplementedError("Needs ARM implementation")
@staticmethod
def MIN(acc, input_type, output_type):
raise NotImplementedError("Needs ARM implementation")
class SWAP:
@staticmethod
def REGISTERS(register_x, register_y):
from peachpy.arm.registers import Register
if isinstance(register_x, Register) and isinstance(register_y, Register):
if register_x.type == register_y.type and register_x.size == register_y.size:
register_x.number, register_y.number = register_y.number, register_x.number
else:
raise ValueError(
"Registers {0} and {1} have incompatible register types".format(register_x, register_y))
else:
raise TypeError("Arguments must be of register type")
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import inspect
import peachpy.stream
import peachpy.arm.function
from peachpy.arm.instructions import QuasiInstruction, Instruction, Operand
from peachpy.arm.isa import Extension
class ArithmeticInstruction(Instruction):
def __init__(self, name, destination, source_x, source_y, origin=None):
allowed_instructions = ['ADD', 'ADDEQ', 'ADDNE', 'ADDCS', 'ADDHS', 'ADDCC', 'ADDLO', 'ADDMI', 'ADDPL', 'ADDVS',
'ADDVC', 'ADDHI', 'ADDLS', 'ADDGE', 'ADDLT', 'ADDGT', 'ADDLE',
'ADDS', 'ADDSEQ', 'ADDSNE', 'ADDSCS', 'ADDSHS', 'ADDSCC', 'ADDSLO', 'ADDSMI', 'ADDSPL',
'ADDSVS', 'ADDSVC', 'ADDSHI', 'ADDSLS', 'ADDSGE', 'ADDSLT', 'ADDSGT', 'ADDSLE',
'ADC', 'ADCEQ', 'ADCNE', 'ADCCS', 'ADCHS', 'ADCCC', 'ADCLO', 'ADCMI', 'ADCPL', 'ADCVS',
'ADCVC', 'ADCHI', 'ADCLS', 'ADCGE', 'ADCLT', 'ADCGT', 'ADCLE',
'ADCS', 'ADCSEQ', 'ADCSNE', 'ADCSCS', 'ADCSHS', 'ADCSCC', 'ADCSLO', 'ADCSMI', 'ADCSPL',
'ADCSVS', 'ADCSVC', 'ADCSHI', 'ADCSLS', 'ADCSGE', 'ADCSLT', 'ADCSGT', 'ADCSLE',
'SUB', 'SUBEQ', 'SUBNE', 'SUBCS', 'SUBHS', 'SUBCC', 'SUBLO', 'SUBMI', 'SUBPL', 'SUBVS',
'SUBVC', 'SUBHI', 'SUBLS', 'SUBGE', 'SUBLT', 'SUBGT', 'SUBLE',
'SUBS', 'SUBSEQ', 'SUBSNE', 'SUBSCS', 'SUBSHS', 'SUBSCC', 'SUBSLO', 'SUBSMI', 'SUBSPL',
'SUBSVS', 'SUBSVC', 'SUBSHI', 'SUBSLS', 'SUBSGE', 'SUBSLT', 'SUBSGT', 'SUBSLE',
'SBC', 'SBCEQ', 'SBCNE', 'SBCCS', 'SBCHS', 'SBCCC', 'SBCLO', 'SBCMI', 'SBCPL', 'SBCVS',
'SBCVC', 'SBCHI', 'SBCLS', 'SBCGE', 'SBCLT', 'SBCGT', 'SBCLE',
'SBCS', 'SBCSEQ', 'SBCSNE', 'SBCSCS', 'SBCSHS', 'SBCSCC', 'SBCSLO', 'SBCSMI', 'SBCSPL',
'SBCSVS', 'SBCSVC', 'SBCSHI', 'SBCSLS', 'SBCSGE', 'SBCSLT', 'SBCSGT', 'SBCSLE',
'RSB', 'RSBEQ', 'RSBNE', 'RSBCS', 'RSBHS', 'RSBCC', 'RSBLO', 'RSBMI', 'RSBPL', 'RSBVS',
'RSBVC', 'RSBHI', 'RSBLS', 'RSBGE', 'RSBLT', 'RSBGT', 'RSBLE',
'RSBS', 'RSBSEQ', 'RSBSNE', 'RSBSCS', 'RSBSHS', 'RSBSCC', 'RSBSLO', 'RSBSMI', 'RSBSPL',
'RSBSVS', 'RSBSVC', 'RSBSHI', 'RSBSLS', 'RSBSGE', 'RSBSLT', 'RSBSGT', 'RSBSLE',
'RSC', 'RSCEQ', 'RSCNE', 'RSCCS', 'RSCHS', 'RSCCC', 'RSCLO', 'RSCMI', 'RSCPL', 'RSCVS',
'RSCVC', 'RSCHI', 'RSCLS', 'RSCGE', 'RSCLT', 'RSCGT', 'RSCLE',
'RSCS', 'RSCSEQ', 'RSCSNE', 'RSCSCS', 'RSCSHS', 'RSCSCC', 'RSCSLO', 'RSCSMI', 'RSCSPL',
'RSCSVS', 'RSCSVC', 'RSCSHI', 'RSCSLS', 'RSCSGE', 'RSCSLT', 'RSCSGT', 'RSCSLE',
'AND', 'ANDEQ', 'ANDNE', 'ANDCS', 'ANDHS', 'ANDCC', 'ANDLO', 'ANDMI', 'ANDPL', 'ANDVS',
'ANDVC', 'ANDHI', 'ANDLS', 'ANDGE', 'ANDLT', 'ANDGT', 'ANDLE',
'ANDS', 'ANDSEQ', 'ANDSNE', 'ANDSCS', 'ANDSHS', 'ANDSCC', 'ANDSLO', 'ANDSMI', 'ANDSPL',
'ANDSVS', 'ANDSVC', 'ANDSHI', 'ANDSLS', 'ANDSGE', 'ANDSLT', 'ANDSGT', 'ANDSLE',
'BIC', 'BICEQ', 'BICNE', 'BICCS', 'BICHS', 'BICCC', 'BICLO', 'BICMI', 'BICPL', 'BICVS',
'BICVC', 'BICHI', 'BICLS', 'BICGE', 'BICLT', 'BICGT', 'BICLE',
'BICS', 'BICSEQ', 'BICSNE', 'BICSCS', 'BICSHS', 'BICSCC', 'BICSLO', 'BICSMI', 'BICSPL',
'BICSVS', 'BICSVC', 'BICSHI', 'BICSLS', 'BICSGE', 'BICSLT', 'BICSGT', 'BICSLE',
'ORR', 'ORREQ', 'ORRNE', 'ORRCS', 'ORRHS', 'ORRCC', 'ORRLO', 'ORRMI', 'ORRPL', 'ORRVS',
'ORRVC', 'ORRHI', 'ORRLS', 'ORRGE', 'ORRLT', 'ORRGT', 'ORRLE',
'ORRS', 'ORRSEQ', 'ORRSNE', 'ORRSCS', 'ORRSHS', 'ORRSCC', 'ORRSLO', 'ORRSMI', 'ORRSPL',
'ORRSVS', 'ORRSVC', 'ORRSHI', 'ORRSLS', 'ORRSGE', 'ORRSLT', 'ORRSGT', 'ORRSLE',
'EOR', 'EOREQ', 'EORNE', 'EORCS', 'EORHS', 'EORCC', 'EORLO', 'EORMI', 'EORPL', 'EORVS',
'EORVC', 'EORHI', 'EORLS', 'EORGE', 'EORLT', 'EORGT', 'EORLE',
'EORS', 'EORSEQ', 'EORSNE', 'EORSCS', 'EORSHS', 'EORSCC', 'EORSLO', 'EORSMI', 'EORSPL',
'EORSVS', 'EORSVC', 'EORSHI', 'EORSLS', 'EORSGE', 'EORSLT', 'EORSGT', 'EORSLE']
super(ArithmeticInstruction, self).__init__(name, [destination, source_x, source_y], origin=origin)
if name not in allowed_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if destination.is_general_purpose_register() and source_x.is_general_purpose_register() and source_y.is_modified_immediate12():
pass
elif destination.is_general_purpose_register() and source_x.is_general_purpose_register() and source_y.is_shifted_general_purpose_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, destination, source_x, source_y))
def is_conditional(self):
return self.name[-2:] in {"EQ", "NE", "CS", "CC", "LO", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT",
"LE"}
def get_input_registers_list(self):
if self.is_conditional():
return self.operands[0].get_registers_list() + self.operands[1].get_registers_list() + self.operands[
2].get_registers_list()
else:
return self.operands[1].get_registers_list() + self.operands[2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class ShiftInstruction(Instruction):
def __init__(self, name, destination, source_x, source_y, origin=None):
allowed_instructions = ['LSL', 'LSR', 'ASR']
super(ShiftInstruction, self).__init__(name, [destination, source_x, source_y], origin=origin)
if name not in allowed_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if destination.is_general_purpose_register() and source_x.is_general_purpose_register() and source_y.is_immediate5():
pass
elif destination.is_general_purpose_register() and source_x.is_general_purpose_register() and source_y.is_general_purpose_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, destination, source_x, source_y))
def get_input_registers_list(self):
return self.operands[1].get_registers_list() + self.operands[2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class CompareInstruction(Instruction):
def __init__(self, name, source_x, source_y, origin=None):
allowed_instructions = ['CMP', 'CMPEQ', 'CMPNE', 'CMPCS', 'CMPHS', 'CMPCC', 'CMPLO', 'CMPMI', 'CMPPL', 'CMPVS',
'CMPVC', 'CMPHI', 'CMPLS', 'CMPGE', 'CMPLT', 'CMPGT', 'CMPLE',
'TEQ', 'TEQEQ', 'TEQNE', 'TEQCS', 'TEQHS', 'TEQCC', 'TEQLO', 'TEQMI', 'TEQPL', 'TEQVS',
'TEQVC', 'TEQHI', 'TEQLS', 'TEQGE', 'TEQLT', 'TEQGT', 'TEQLE',
'TST', 'TSTEQ', 'TSTNE', 'TSTCS', 'TSTHS', 'TSTCC', 'TSTLO', 'TSTMI', 'TSTPL', 'TSTVS',
'TSTVC', 'TSTHI', 'TSTLS', 'TSTGE', 'TSTLT', 'TSTGT', 'TSTLE',
'TEQ', 'TEQEQ', 'TEQNE', 'TEQCS', 'TEQHS', 'TEQCC', 'TEQLO', 'TEQMI', 'TEQPL', 'TEQVS',
'TEQVC', 'TEQHI', 'TEQLS', 'TEQGE', 'TEQLT', 'TEQGT', 'TEQLE']
if name in allowed_instructions:
super(CompareInstruction, self).__init__(name, [source_x, source_y], origin=origin)
else:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if source_x.is_general_purpose_register() and source_y.is_modified_immediate12():
pass
elif source_x.is_general_purpose_register() and source_y.is_general_purpose_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}'.format(name, source_x, source_y))
def get_input_registers_list(self):
return self.operands[0].get_registers_list() + self.operands[1].get_registers_list()
def get_output_registers_list(self):
return list()
class MovInstruction(Instruction):
def __init__(self, name, destination, source, origin=None):
allowed_instructions = ['MOV', 'MOVEQ', 'MOVNE', 'MOVCS', 'MOVHS', 'MOVCC', 'MOVLO', 'MOVMI', 'MOVPL', 'MOVVS',
'MOVVC', 'MOVHI', 'MOVLS', 'MOVGE', 'MOVLT', 'MOVGT', 'MOVLE',
'MOVS', 'MOVSEQ', 'MOVSNE', 'MOVSCS', 'MOVSHS', 'MOVSCC', 'MOVSLO', 'MOVSMI', 'MOVSPL',
'MOVSVS', 'MOVSVC', 'MOVSHI', 'MOVSLS', 'MOVSGE', 'MOVSLT', 'MOVSGT', 'MOVSLE']
if name in allowed_instructions:
super(MovInstruction, self).__init__(name, [destination, source], origin=origin)
else:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if destination.is_general_purpose_register() and source.is_modified_immediate12():
pass
elif destination.is_general_purpose_register() and source.is_general_purpose_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}'.format(name, destination, source))
def is_conditional(self):
return self.name[-2:] in {"EQ", "NE", "CS", "CC", "LO", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT",
"LE"}
def get_input_registers_list(self):
if self.is_conditional():
return self.operands[0].get_registers_list() + self.operands[1].get_registers_list()
else:
return self.operands[1].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class LoadStoreInstruction(Instruction):
load_instructions = ['LDR', 'LDRH', 'LDRSH', 'LDRB', 'LDRSB']
store_instructions = ['STR', 'STRB', 'STRH']
def __init__(self, name, register, address, increment, origin=None):
allowed_instructions = LoadStoreInstruction.load_instructions + LoadStoreInstruction.store_instructions
if name not in allowed_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'.format(name, ", ".join(
allowed_instructions)))
if register.is_general_purpose_register() and address.is_memory_address(offset_bits=8) and increment.is_none():
super(LoadStoreInstruction, self).__init__(name, [register, address], origin=origin)
elif name in {'STR', 'LDR', 'LDRB',
'STRB'} and register.is_general_purpose_register() and address.is_memory_address(
offset_bits=12) and increment.is_none():
super(LoadStoreInstruction, self).__init__(name, [register, address], origin=origin)
elif register.is_general_purpose_register() and address.is_memory_address(offset_bits=0,
allow_writeback=False) and increment.is_offset8():
super(LoadStoreInstruction, self).__init__(name, [register, address, increment], origin=origin)
elif register.is_general_purpose_register() and address.is_memory_address(offset_bits=0,
allow_writeback=False) and increment.is_offset12():
super(LoadStoreInstruction, self).__init__(name, [register, address, increment], origin=origin)
else:
if increment.is_none():
raise ValueError('Invalid operands in instruction {0} {1}, {2}'.format(name, register, address))
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, register, address, increment))
def get_input_registers_list(self):
input_registers_list = self.operands[
0].get_registers_list() if self.name in LoadStoreInstruction.store_instructions else list()
for operand in self.operands[1:]:
input_registers_list += operand.get_registers_list()
return input_registers_list
def get_output_registers_list(self):
output_registers_list = self.operands[
0].get_registers_list() if self.name in LoadStoreInstruction.load_instructions else list()
if len(self.operands) > 2 or self.operands[1].is_preindexed_memory_address():
output_registers_list.append(self.operands[1].base)
return output_registers_list
class PushPopInstruction(Instruction):
def __init__(self, name, register_list, origin=None):
allowed_instructions = {'PUSH', 'POP'}
if name in allowed_instructions:
super(PushPopInstruction, self).__init__(name, [register_list], origin=origin)
else:
raise ValueError('Instruction {0} is not one of the allowed instructions'.format(name))
if register_list.is_general_purpose_register_list():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}'.format(name, register_list))
def get_input_registers_list(self):
if self.name == 'PUSH':
return self.operands[0].get_registers_list()
else:
return list()
def get_output_registers_list(self):
if self.name == 'POP':
return self.operands[0].get_registers_list()
else:
return list()
class BranchInstruction(Instruction):
def __init__(self, name, destination, origin=None):
allowed_instructions = {'B', 'BEQ', 'BNE', 'BCS', 'BHS', 'BCC', 'BLO', 'BMI', 'BPL', 'BVS', 'BVC', 'BHI', 'BLS',
'BGE', 'BLT', 'BGT', 'BLE'}
if name in allowed_instructions:
super(BranchInstruction, self).__init__(name, [destination], origin=origin)
self.is_visited = False
else:
raise ValueError('Instruction {0} is not one of the allowed instructions'.format(name))
if destination.is_label():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}'.format('BX', destination))
def get_input_registers_list(self):
return self.operands[0].get_registers_list()
def get_output_registers_list(self):
return list()
def is_conditional(self):
return not self.name == 'B'
def __str__(self):
return self.name + " L" + str(self.operands[0])
class BranchExchangeInstruction(Instruction):
def __init__(self, destination, origin=None):
from peachpy.arm.registers import lr
super(BranchExchangeInstruction, self).__init__('BX', [destination], origin=origin)
if destination.is_general_purpose_register() and destination.register == lr:
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}'.format('BX', destination))
def get_input_registers_list(self):
return self.operands[0].get_registers_list()
def get_output_registers_list(self):
return list()
class BreakInstruction(Instruction):
def __init__(self, origin=None):
super(BreakInstruction, self).__init__('BKPT', (), origin=origin)
def __str__(self):
return "BKPT"
def get_input_registers_list(self):
return []
def get_output_registers_list(self):
return []
def get_constant(self):
return None
def get_local_variable(self):
return None
def BX(destination):
instruction = BranchExchangeInstruction(Operand(destination))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BKPT():
instruction = BreakInstruction()
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADD(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADD', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADDSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADDSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ADCSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ADCSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUB(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUB', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SUBSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SUBSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def SBCSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('SBCSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSB(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSB', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSBSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSBSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def RSCSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('RSCSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def AND(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('AND', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ANDSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ANDSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BIC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BIC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BICSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('BICSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORR(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORR', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORREQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORREQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ORRSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('ORRSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EOR(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EOR', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EOREQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EOREQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSEQ(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSEQ', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSNE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSNE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSCS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSCS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSHS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSHS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSCC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSCC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSLO(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSLO', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSMI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSMI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSPL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSPL', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSVS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSVS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSVC(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSVC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSHI(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSHI', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSLS(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSLS', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSGE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSGE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSLT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSLT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSGT(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSGT', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def EORSLE(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ArithmeticInstruction('EORSLE', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def LSL(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ShiftInstruction('LSL', Operand(destination), Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def LSR(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ShiftInstruction('LSR', Operand(destination), Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def ASR(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = ShiftInstruction('ASR', Operand(destination), Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMP(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMP', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPEQ(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPEQ', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPNE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPNE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPCS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPCS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPHS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPHS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPCC(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPCC', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPLO(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPLO', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPMI(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPMI', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPPL(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPPL', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPVS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPVS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPVC(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPVC', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPHI(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPHI', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPLS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPLS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPGE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPGE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPLT(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPLT', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPGT(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPGT', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMPLE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMPLE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMN(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMN', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNEQ(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNEQ', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNNE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNNE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNCS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNCS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNHS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNHS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNCC(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNCC', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNLO(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNLO', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNMI(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNMI', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNPL(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNPL', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNVS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNVS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNVC(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNVC', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNHI(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNHI', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNLS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNLS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNGE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNGE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNLT(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNLT', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNGT(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNGT', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def CMNLE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('CMNLE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TST(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TST', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTEQ(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTEQ', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTNE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTNE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTCS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTCS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTHS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTHS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTCC(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTCC', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTLO(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTLO', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTMI(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTMI', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTPL(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTPL', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTVS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTVS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTVC(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTVC', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTHI(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTHI', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTLS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTLS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTGE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTGE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTLT(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTLT', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTGT(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTGT', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TSTLE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TSTLE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQ(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQ', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQEQ(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQEQ', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQNE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQNE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQCS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQCS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQHS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQHS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQCC(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQCC', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQLO(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQLO', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQMI(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQMI', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQPL(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQPL', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQVS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQVS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQVC(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQVC', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQHI(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQHI', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQLS(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQLS', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQGE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQGE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQLT(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQLT', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQGT(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQGT', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def TEQLE(source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = CompareInstruction('TEQLE', Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOV(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOV', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVEQ(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVEQ', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVNE(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVNE', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVCS(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVCS', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVHS(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVHS', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVCC(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVCC', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVLO(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVLO', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVMI(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVMI', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVPL(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVPL', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVVS(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVVS', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVVC(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVVC', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVHI(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVHI', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVLS(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVLS', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVGE(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVGE', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVLT(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVLT', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVGT(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVGT', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVLE(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVLE', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVS(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVS', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSEQ(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSEQ', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSNE(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSNE', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSCS(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSCS', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSHS(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSHS', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSCC(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSCC', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSLO(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSLO', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSMI(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSMI', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSPL(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSPL', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSVS(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSVS', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSVC(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSVC', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSHI(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSHI', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSLS(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSLS', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSGE(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSGE', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSLT(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSLT', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSGT(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSGT', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def MOVSLE(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = MovInstruction('MOVSLE', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def PUSH(register_list):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = PushPopInstruction('PUSH', Operand(register_list), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def POP(register_list):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = PushPopInstruction('POP', Operand(register_list), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def LDR(register, address, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = LoadStoreInstruction('LDR', Operand(register), Operand(address), Operand(increment), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def STR(register, address, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = LoadStoreInstruction('STR', Operand(register), Operand(address), Operand(increment), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def LDRH(register, address, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = LoadStoreInstruction('LDRH', Operand(register), Operand(address), Operand(increment), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def LDRSH(register, address, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = LoadStoreInstruction('LDRSH', Operand(register), Operand(address), Operand(increment), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def STRH(register, address, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = LoadStoreInstruction('STRH', Operand(register), Operand(address), Operand(increment), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def LDRB(register, address, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = LoadStoreInstruction('LDRB', Operand(register), Operand(address), Operand(increment), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def LDRSB(register, address, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = LoadStoreInstruction('LDRSB', Operand(register), Operand(address), Operand(increment), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def STRB(register, address, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = LoadStoreInstruction('STRB', Operand(register), Operand(address), Operand(increment), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def B(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('B', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BEQ(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BEQ', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BNE(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BNE', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BCS(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BCS', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BHS(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BHS', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BCC(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BCC', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BLO(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BLO', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BMI(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BMI', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BPL(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BPL', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BVS(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BVS', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BVC(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BVC', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BHI(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BHI', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BLS(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BLS', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BGE(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BGE', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BLT(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BLT', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BGT(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BGT', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def BLE(destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = BranchInstruction('BLE', Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import peachpy
import peachpy.arm.abi
import peachpy.arm.isa
from peachpy.arm.microarchitecture import Microarchitecture
from peachpy.arm.registers import GeneralPurposeRegister, SRegister, DRegister, QRegister, WMMXRegister, \
r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, pc, \
s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, \
s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, \
d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, \
q0, q1, q2, q3, q4, q5, q6, q7, \
wr0, wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9, wr10, wr11, wr12, wr13, wr14, wr15
from peachpy.arm.function import Function
from peachpy.arm.pseudo import Label, Loop, \
LABEL, ALIGN, RETURN, LOAD, STORE, ASSUME, INIT, REDUCE, SWAP
from peachpy.arm.generic import \
ADD, ADDEQ, ADDNE, ADDCS, ADDHS, ADDCC, ADDLO, ADDMI, ADDPL, ADDVS, \
ADDVC, ADDHI, ADDLS, ADDGE, ADDLT, ADDGT, ADDLE, \
ADDS, ADDSEQ, ADDSNE, ADDSCS, ADDSHS, ADDSCC, ADDSLO, ADDSMI, ADDSPL, \
ADDSVS, ADDSVC, ADDSHI, ADDSLS, ADDSGE, ADDSLT, ADDSGT, ADDSLE, \
ADC, ADCEQ, ADCNE, ADCCS, ADCHS, ADCCC, ADCLO, ADCMI, ADCPL, ADCVS, \
ADCVC, ADCHI, ADCLS, ADCGE, ADCLT, ADCGT, ADCLE, \
ADCS, ADCSEQ, ADCSNE, ADCSCS, ADCSHS, ADCSCC, ADCSLO, ADCSMI, ADCSPL, \
ADCSVS, ADCSVC, ADCSHI, ADCSLS, ADCSGE, ADCSLT, ADCSGT, ADCSLE, \
SUB, SUBEQ, SUBNE, SUBCS, SUBHS, SUBCC, SUBLO, SUBMI, SUBPL, SUBVS, \
SUBVC, SUBHI, SUBLS, SUBGE, SUBLT, SUBGT, SUBLE, \
SUBS, SUBSEQ, SUBSNE, SUBSCS, SUBSHS, SUBSCC, SUBSLO, SUBSMI, SUBSPL, \
SUBSVS, SUBSVC, SUBSHI, SUBSLS, SUBSGE, SUBSLT, SUBSGT, SUBSLE, \
SBC, SBCEQ, SBCNE, SBCCS, SBCHS, SBCCC, SBCLO, SBCMI, SBCPL, SBCVS, \
SBCVC, SBCHI, SBCLS, SBCGE, SBCLT, SBCGT, SBCLE, \
SBCS, SBCSEQ, SBCSNE, SBCSCS, SBCSHS, SBCSCC, SBCSLO, SBCSMI, SBCSPL, \
SBCSVS, SBCSVC, SBCSHI, SBCSLS, SBCSGE, SBCSLT, SBCSGT, SBCSLE, \
RSB, RSBEQ, RSBNE, RSBCS, RSBHS, RSBCC, RSBLO, RSBMI, RSBPL, RSBVS, \
RSBVC, RSBHI, RSBLS, RSBGE, RSBLT, RSBGT, RSBLE, \
RSBS, RSBSEQ, RSBSNE, RSBSCS, RSBSHS, RSBSCC, RSBSLO, RSBSMI, RSBSPL, \
RSBSVS, RSBSVC, RSBSHI, RSBSLS, RSBSGE, RSBSLT, RSBSGT, RSBSLE, \
RSC, RSCEQ, RSCNE, RSCCS, RSCHS, RSCCC, RSCLO, RSCMI, RSCPL, RSCVS, \
RSCVC, RSCHI, RSCLS, RSCGE, RSCLT, RSCGT, RSCLE, \
RSCS, RSCSEQ, RSCSNE, RSCSCS, RSCSHS, RSCSCC, RSCSLO, RSCSMI, RSCSPL, \
RSCSVS, RSCSVC, RSCSHI, RSCSLS, RSCSGE, RSCSLT, RSCSGT, RSCSLE, \
AND, ANDEQ, ANDNE, ANDCS, ANDHS, ANDCC, ANDLO, ANDMI, ANDPL, ANDVS, \
ANDVC, ANDHI, ANDLS, ANDGE, ANDLT, ANDGT, ANDLE, \
ANDS, ANDSEQ, ANDSNE, ANDSCS, ANDSHS, ANDSCC, ANDSLO, ANDSMI, ANDSPL, \
ANDSVS, ANDSVC, ANDSHI, ANDSLS, ANDSGE, ANDSLT, ANDSGT, ANDSLE, \
BIC, BICEQ, BICNE, BICCS, BICHS, BICCC, BICLO, BICMI, BICPL, BICVS, \
BICVC, BICHI, BICLS, BICGE, BICLT, BICGT, BICLE, \
BICS, BICSEQ, BICSNE, BICSCS, BICSHS, BICSCC, BICSLO, BICSMI, BICSPL, \
BICSVS, BICSVC, BICSHI, BICSLS, BICSGE, BICSLT, BICSGT, BICSLE, \
ORR, ORREQ, ORRNE, ORRCS, ORRHS, ORRCC, ORRLO, ORRMI, ORRPL, ORRVS, \
ORRVC, ORRHI, ORRLS, ORRGE, ORRLT, ORRGT, ORRLE, \
ORRS, ORRSEQ, ORRSNE, ORRSCS, ORRSHS, ORRSCC, ORRSLO, ORRSMI, ORRSPL, \
ORRSVS, ORRSVC, ORRSHI, ORRSLS, ORRSGE, ORRSLT, ORRSGT, ORRSLE, \
EOR, EOREQ, EORNE, EORCS, EORHS, EORCC, EORLO, EORMI, EORPL, EORVS, \
EORVC, EORHI, EORLS, EORGE, EORLT, EORGT, EORLE, \
EORS, EORSEQ, EORSNE, EORSCS, EORSHS, EORSCC, EORSLO, EORSMI, EORSPL, \
EORSVS, EORSVC, EORSHI, EORSLS, EORSGE, EORSLT, EORSGT, EORSLE, \
LSL, LSR, ASR, \
CMP, CMPEQ, CMPNE, CMPCS, CMPHS, CMPCC, CMPLO, CMPMI, CMPPL, CMPVS, \
CMPVC, CMPHI, CMPLS, CMPGE, CMPLT, CMPGT, CMPLE, \
TEQ, TEQEQ, TEQNE, TEQCS, TEQHS, TEQCC, TEQLO, TEQMI, TEQPL, TEQVS, \
TEQVC, TEQHI, TEQLS, TEQGE, TEQLT, TEQGT, TEQLE, \
TST, TSTEQ, TSTNE, TSTCS, TSTHS, TSTCC, TSTLO, TSTMI, TSTPL, TSTVS, \
TSTVC, TSTHI, TSTLS, TSTGE, TSTLT, TSTGT, TSTLE, \
TEQ, TEQEQ, TEQNE, TEQCS, TEQHS, TEQCC, TEQLO, TEQMI, TEQPL, TEQVS, \
TEQVC, TEQHI, TEQLS, TEQGE, TEQLT, TEQGT, TEQLE, \
MOV, MOVEQ, MOVNE, MOVCS, MOVHS, MOVCC, MOVLO, MOVMI, MOVPL, MOVVS, \
MOVVC, MOVHI, MOVLS, MOVGE, MOVLT, MOVGT, MOVLE, \
MOVS, MOVSEQ, MOVSNE, MOVSCS, MOVSHS, MOVSCC, MOVSLO, MOVSMI, MOVSPL, \
MOVSVS, MOVSVC, MOVSHI, MOVSLS, MOVSGE, MOVSLT, MOVSGT, MOVSLE, \
LDR, LDRH, LDRSH, LDRB, LDRSB, \
STR, STRB, STRH, \
B, BEQ, BNE, BCS, BHS, BCC, BLO, BMI, BPL, BVS, BVC, BHI, BLS, BGE, BLT, BGT, BLE, \
BKPT
from peachpy.arm.vfpneon import VADD, VADDL, VSUB, VSUBL, VMUL, VMULL, VMIN, VMAX, \
VABD, VABS, VACGE, VACGT, VACLE, VACLT, \
VAND, VBIC, VORR, VORN, VEOR, \
VPADD, VPMIN, VPMAX, VQADD, VQSUB, VHADD, VHSUB, VRHADD, \
VRECPS, VRSQRTS, \
VTST, VNMUL, VDIV, VSQRT, VNEG, \
VMLA, VMLS, VNMLA, VNMLS, VFMA, VFMS, VFNMA, VFNMS, \
VLDR, VSTR, VLDM, VLDMIA, VLDMDB, VSTM, VSTMIA, VSTMDB, VLD1, VST1, VMOV
__m64 = peachpy.Type("__m64", size=8, is_vector=True, header="mmintrin.h")
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import inspect
import peachpy.stream
import peachpy.arm.function
from peachpy.arm.instructions import Instruction, Operand
from peachpy.arm.isa import Extension
class VFPLoadStoreInstruction(Instruction):
def __init__(self, name, register, address, origin=None):
allowed_instructions = {'VLDR', 'VSTR'}
if name in allowed_instructions:
super(VFPLoadStoreInstruction, self).__init__(name, [register, address],
isa_extensions=Extension.VFP2, origin=origin)
else:
raise ValueError('Instruction {0} is not one of the allowed instructions'.format(name))
if (register.is_d_register() or register.is_s_register()) and address.is_memory_address_offset8_mod4():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}'.format(name, register, address))
def get_input_registers_list(self):
input_registers_list = self.operands[1].get_registers_list()
if self.name == 'VSTR':
input_registers_list += self.operands[0].get_registers_list()
return input_registers_list
def get_output_registers_list(self):
if self.name == 'VLDR':
return self.operands[0].get_registers_list()
else:
return list()
class VFPLoadStoreMultipleInstruction(Instruction):
load_instructions = {"VLDM", "VLDMIA", "VLDMDB"}
store_instructions = {"VSTM", "VSTMIA", "VSTMDB"}
def __init__(self, name, address, register_list, origin=None):
if name in VFPLoadStoreMultipleInstruction.load_instructions or \
name in VFPLoadStoreMultipleInstruction.store_instructions:
super(VFPLoadStoreMultipleInstruction, self).__init__(name, [address, register_list],
isa_extensions=Extension.VFP2, origin=origin)
else:
raise ValueError('Instruction {0} is not one of the allowed instructions'.format(name))
if address.is_address_register() and register_list.is_d_register_list():
pass
elif address.is_address_register() and register_list.is_s_register_list():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}'.format(name, register_list, address))
def get_input_registers_list(self):
if self.name in VFPLoadStoreMultipleInstruction.store_instructions:
return self.operands[0].get_registers_list() + self.operands[1].get_registers_list()
else:
return self.operands[0].get_registers_list()
def get_output_registers_list(self):
if self.name in VFPLoadStoreMultipleInstruction.load_instructions:
return self.operands[1].get_registers_list()
else:
return list()
class NeonLoadStoreInstruction(Instruction):
load_instructions = {"VLD1.8", "VLD1.16", "VLD1.32", "VLD1.64"}
store_instructions = {"VST1.8", "VST1.16", "VST1.32", "VST1.64"}
def __init__(self, name, register_list, address, increment, origin=None):
if name not in NeonLoadStoreInstruction.load_instructions and \
name not in NeonLoadStoreInstruction.store_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions'.format(name))
if register_list.is_vldst1_register_list() and \
address.is_memory_address(offset_bits=0) and \
increment.is_none():
super(NeonLoadStoreInstruction, self).__init__(name, [register_list, address],
isa_extensions=Extension.NEON, origin=origin)
elif register_list.is_vldst1_register_list() and \
address.is_memory_address(offset_bits=0, allow_writeback=False) and \
increment.is_general_purpose_register():
super(NeonLoadStoreInstruction, self).__init__(name, [register_list, address, increment],
isa_extensions=Extension.NEON, origin=origin)
elif register_list.is_vldst1_register_lanes_list() and \
address.is_memory_address(offset_bits=0) and \
increment.is_none():
super(NeonLoadStoreInstruction, self).__init__(name, [register_list, address],
isa_extensions=Extension.NEON, origin=origin)
elif register_list.is_vldst1_register_lanes_list() and \
address.is_memory_address(offset_bits=0, allow_writeback=False) and \
increment.is_general_purpose_register():
super(NeonLoadStoreInstruction, self).__init__(name, [register_list, address, increment],
isa_extensions=Extension.NEON, origin=origin)
else:
if increment.is_none():
raise ValueError('Invalid operands in instruction {0} {1}, {2}'.format(name, register_list, address))
else:
raise ValueError(
'Invalid operands in instruction {0} {1}, {2}, {3}'.format(name, register_list, address, increment))
def get_input_registers_list(self):
input_registers_list = self.operands[1].get_registers_list()
if self.name in NeonLoadStoreInstruction.store_instructions:
input_registers_list += self.operands[0].get_registers_list()
if len(self.operands) == 3:
input_registers_list += self.operands[2].get_registers_list()
return input_registers_list
def get_output_registers_list(self):
output_registers_list = list()
if self.name in NeonLoadStoreInstruction.load_instructions:
output_registers_list += self.operands[0].get_registers_list()
if len(self.operands) == 3 or self.operands[1].is_writeback_memory_address():
output_registers_list += self.operands[1].get_writeback_registers_list()
return output_registers_list
class VFPPushPopInstruction(Instruction):
def __init__(self, name, register_list, origin=None):
allowed_instructions = {'VPUSH', 'VPOP'}
if name in allowed_instructions:
super(VFPPushPopInstruction, self).__init__(name, [register_list],
isa_extensions=Extension.VFP2, origin=origin)
else:
raise ValueError('Instruction {0} is not one of the allowed instructions'.format(name))
if register_list.is_d_register_list():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}'.format(name, register_list))
def get_input_registers_list(self):
if self.name == 'VPUSH':
return self.operands[0].get_registers_list()
else:
return list()
def get_output_registers_list(self):
if self.name == 'VPOP':
return self.operands[0].get_registers_list()
else:
return list()
class VFPDoublePrecisionMultiplyAddInstruction(Instruction):
def __init__(self, name, destination, source_x, source_y, origin=None):
mla_instructions = ['VMLA.F64', 'VMLS.F64', 'VNMLA.F64', 'VNMLS.F64']
fma_instructions = ['VFMA.F64', 'VFMS.F64', 'VFNMA.F64', 'VFNMS.F64']
if name in mla_instructions:
super(VFPDoublePrecisionMultiplyAddInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.VFP2, origin=origin)
elif name in fma_instructions:
super(VFPDoublePrecisionMultiplyAddInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.VFP4, origin=origin)
else:
raise ValueError('Instruction {0} is not one of the allowed instructions'.format(name))
if destination.is_d_register() and source_x.is_d_register() and source_y.is_d_register():
pass
else:
raise ValueError(
'Invalid operands in instruction {0} {1}, {2}, {3}'.format(name, destination, source_x, source_y))
def get_input_registers_list(self):
return self.operands[0].get_registers_list() + self.operands[1].get_registers_list() + self.operands[
2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class VFPSinglePrecisionMultiplyAddInstruction(Instruction):
def __init__(self, name, destination, source_x, source_y, origin=None):
mla_instructions = ['VNMLA.F32', 'VNMLS.F32']
fma_instructions = ['VFNMA.F32', 'VFNMS.F32']
if name in mla_instructions:
super(VFPSinglePrecisionMultiplyAddInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.VFP2, origin=origin)
elif name in fma_instructions:
super(VFPSinglePrecisionMultiplyAddInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.VFP4, origin=origin)
else:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(mla_instructions + fma_instructions)))
if destination.is_s_register() and source_x.is_s_register() and source_y.is_s_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, destination, source_x, source_y))
def get_input_registers_list(self):
return self.operands[0].get_registers_list() + self.operands[1].get_registers_list() + self.operands[
2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class VFPNeonBinaryArithmeticInstruction(Instruction):
def __init__(self, name, destination, source_x, source_y, origin=None):
allowed_instructions = ['VADD.F32', 'VSUB.F32', 'VMUL.F32']
if name not in allowed_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if destination.is_s_register() and source_x.is_s_register() and source_y.is_s_register():
super(VFPNeonBinaryArithmeticInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.VFP2, origin=origin)
elif destination.is_d_register() and source_x.is_d_register() and source_y.is_d_register():
super(VFPNeonBinaryArithmeticInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.NEON, origin=origin)
elif destination.is_q_register() and source_x.is_q_register() and source_y.is_q_register():
super(VFPNeonBinaryArithmeticInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.NEON, origin=origin)
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, destination, source_x, source_y))
def get_input_registers_list(self):
return self.operands[1].get_registers_list() + self.operands[2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class VFPNeonMultiplyAddInstruction(Instruction):
def __init__(self, name, accumulator, factor_x, factor_y, origin=None):
mla_instructions = ['VMLA.F32', 'VMLS.F32']
fma_instructions = ['VFMA.F32', 'VFMS.F32']
if name not in mla_instructions and name not in fma_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions'.format(name))
if name in mla_instructions and \
accumulator.is_s_register() and \
factor_x.is_s_register() and \
factor_y.is_s_register():
super(VFPNeonMultiplyAddInstruction, self).__init__(name, [accumulator, factor_x, factor_y],
isa_extensions=Extension.VFP2, origin=origin)
elif name in fma_instructions and \
accumulator.is_s_register() and \
factor_x.is_s_register() and \
factor_y.is_s_register():
super(VFPNeonMultiplyAddInstruction, self).__init__(name, [accumulator, factor_x, factor_y],
isa_extensions=Extension.VFP4, origin=origin)
elif name in mla_instructions and \
accumulator.is_d_register() and \
factor_x.is_d_register() and \
factor_y.is_d_register():
super(VFPNeonMultiplyAddInstruction, self).__init__(name, [accumulator, factor_x, factor_y],
isa_extensions=Extension.NEON, origin=origin)
elif name in mla_instructions and \
accumulator.is_q_register() and \
factor_x.is_q_register() and \
factor_y.is_q_register():
super(VFPNeonMultiplyAddInstruction, self).__init__(name, [accumulator, factor_x, factor_y],
isa_extensions=Extension.NEON, origin=origin)
elif name in fma_instructions and \
accumulator.is_d_register() and \
factor_x.is_d_register() and \
factor_y.is_d_register():
super(VFPNeonMultiplyAddInstruction, self).__init__(name, [accumulator, factor_x, factor_y],
isa_extensions=Extension.NEON2, origin=origin)
elif name in fma_instructions and \
accumulator.is_q_register() and \
factor_x.is_q_register() and \
factor_y.is_q_register():
super(VFPNeonMultiplyAddInstruction, self).__init__(name, [accumulator, factor_x, factor_y],
isa_extensions=Extension.NEON2, origin=origin)
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, accumulator, factor_x, factor_y))
def get_input_registers_list(self):
return self.operands[0].get_registers_list() + \
self.operands[1].get_registers_list() + \
self.operands[2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class VFPSinglePrecisionBinaryArithmeticInstruction(Instruction):
def __init__(self, name, destination, source_x, source_y, origin=None):
allowed_instructions = ['VNMUL.F32', 'VDIV.F32']
super(VFPSinglePrecisionBinaryArithmeticInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.VFP2,
origin=origin)
if name not in allowed_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if destination.is_d_register() and source_x.is_s_register() and source_y.is_s_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, destination, source_x, source_y))
def get_input_registers_list(self):
return self.operands[1].get_registers_list() + self.operands[2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class VFPDoublePrecisionBinaryArithmeticInstruction(Instruction):
def __init__(self, name, destination, source_x, source_y, origin=None):
allowed_instructions = ['VADD.F64', 'VSUB.F64', 'VMUL.F64', 'VNMUL.F32', 'VNMUL.F64', 'VDIV.F32', 'VDIV.F64']
super(VFPDoublePrecisionBinaryArithmeticInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.VFP2,
origin=origin)
if name not in allowed_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if destination.is_d_register() and source_x.is_d_register() and source_y.is_d_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, destination, source_x, source_y))
def get_input_registers_list(self):
return self.operands[1].get_registers_list() + self.operands[2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class VFPDoublePrecisionUnaryArithmeticInstruction(Instruction):
def __init__(self, name, destination, source, origin=None):
allowed_instructions = ['VABS.F64', 'VNEG.F64', 'VSQRT.F64']
super(VFPDoublePrecisionUnaryArithmeticInstruction, self).__init__(name, [destination, source],
isa_extensions=Extension.VFP2, origin=origin)
if name not in allowed_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if destination.is_d_register() and source.is_d_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}'.format(name, destination, source))
def get_input_registers_list(self):
return self.operands[1].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class NeonArithmeticInstruction(Instruction):
def __init__(self, name, destination, source_x, source_y, origin=None):
allowed_instructions = ['VADD.I8', 'VADD.I16', 'VADD.I32', 'VADD.I64',
'VSUB.I8', 'VSUB.I16', 'VSUB.I32', 'VSUB.I64',
'VMUL.I8', 'VMUL.I16', 'VMUL.I32',
'VMIN.S8', 'VMIN.S16', 'VMIN.S32', 'VMIN.U8', 'VMIN.U16', 'VMIN.U32', 'VMIN.F32',
'VMAX.S8', 'VMAX.S16', 'VMAX.S32', 'VMAX.U8', 'VMAX.U16', 'VMAX.U32', 'VMAX.F32',
'VABD.S8', 'VABD.S16', 'VABD.S32', 'VABD.U8', 'VABD.U16', 'VABD.U32', 'VABD.F32',
'VACGE.F32', 'VACGT.F32', 'VACLE.F32', 'VACLT.F32',
'VEOR', 'VORR', 'VORN', 'VAND', 'VBIC',
'VPADD.I8', 'VPADD.I16', 'VPADD.I32', 'VPADD.F32',
'VPMIN.S8', 'VPMIN.S16', 'VPMIN.S32', 'VPMIN.U8', 'VPMIN.U16', 'VPMIN.U32', 'VPMIN.F32',
'VPMAX.S8', 'VPMAX.S16', 'VPMAX.S32', 'VPMAX.U8', 'VPMAX.U16', 'VPMAX.U32', 'VPMAX.F32',
'VQADD.S8', 'VQADD.S16', 'VQADD.S32', 'VQADD.S64', 'VQADD.U8', 'VQADD.U16', 'VQADD.U32',
'VQADD.U64',
'VQSUB.S8', 'VQSUB.S16', 'VQSUB.S32', 'VQSUB.S64', 'VQSUB.U8', 'VQSUB.U16', 'VQSUB.U32',
'VQSUB.U64',
'VHADD.S8', 'VHADD.S16', 'VHADD.S32', 'VHADD.U8', 'VHADD.U16', 'VHADD.U32',
'VHSUB.S8', 'VHSUB.S16', 'VHSUB.S32', 'VHSUB.U8', 'VHSUB.U16', 'VHSUB.U32',
'VRHADD.S8', 'VRHADD.S16', 'VRHADD.S32', 'VRHADD.U8', 'VRHADD.U16', 'VRHADD.U32',
'VRECPS.F32', 'VRSQRTS.F32',
'VTST.8', 'VTST.16', 'VTST.32']
super(NeonArithmeticInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.NEON, origin=origin)
if name not in allowed_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if destination.is_d_register() and source_x.is_d_register() and source_y.is_d_register():
pass
elif destination.is_q_register() and source_x.is_q_register() and source_y.is_q_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, destination, source_x, source_y))
def get_input_registers_list(self):
return self.operands[1].get_registers_list() + self.operands[2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class NeonWideArithmeticInstruction(Instruction):
def __init__(self, name, destination, source_x, source_y, origin=None):
allowed_instructions = ['VADDL.S8', 'VADDL.S16', 'VADDL.S32',
'VADDL.U8', 'VADDL.U16', 'VADDL.U32',
'VSUBL.S8', 'VSUBL.S16', 'VSUBL.S32',
'VSUBL.U8', 'VSUBL.U16', 'VSUBL.U32',
'VMULL.S8', 'VMULL.S16', 'VMULL.S32',
'VMULL.U8', 'VMULL.U16', 'VMULL.U32',
'VMULL.P8']
super(NeonWideArithmeticInstruction, self).__init__(name, [destination, source_x, source_y],
isa_extensions=Extension.NEON, origin=origin)
if name not in allowed_instructions:
raise ValueError('Instruction {0} is not one of the allowed instructions ({1})'
.format(name, ", ".join(allowed_instructions)))
if destination.is_q_register() and source_x.is_d_register() and source_y.is_d_register():
pass
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}, {3}'
.format(name, destination, source_x, source_y))
def get_input_registers_list(self):
return self.operands[1].get_registers_list() + self.operands[2].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class VfpNeonMovInstruction(Instruction):
def __init__(self, name, destination, source, origin=None):
if name == 'VMOV' and destination.is_q_register() and source.is_q_register():
super(VfpNeonMovInstruction, self).__init__(name, [destination, source],
isa_extensions=Extension.NEON, origin=origin)
elif name == 'VMOV' and destination.is_d_register() and source.is_d_register():
super(VfpNeonMovInstruction, self).__init__(name, [destination, source],
isa_extensions=Extension.NEON, origin=origin)
elif name == 'VMOV.F32' and destination.is_s_register() and source.is_s_register():
super(VfpNeonMovInstruction, self).__init__(name, [destination, source],
isa_extensions=Extension.VFP2, origin=origin)
elif name == 'VMOV.F64' and destination.is_d_register() and source.is_d_register():
super(VfpNeonMovInstruction, self).__init__(name, [destination, source],
isa_extensions=Extension.VFP2, origin=origin)
else:
raise ValueError('Invalid operands in instruction {0} {1}, {2}'.format(name, destination, source))
def get_input_registers_list(self):
return self.operands[1].get_registers_list()
def get_output_registers_list(self):
return self.operands[0].get_registers_list()
class VADD:
@staticmethod
def I8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VADD.I8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VADD.I16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VADD.I32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VADD.I64', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPNeonBinaryArithmeticInstruction('VADD.F32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPDoublePrecisionBinaryArithmeticInstruction('VADD.F64', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VADDL:
@staticmethod
def S8(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VADDL.S8', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VADDL.S16', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VADDL.S32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VADDL.U8', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VADDL.U16', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VADDL.U32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VSUB:
@staticmethod
def I8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VSUB.I8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VSUB.I16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VSUB.I32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VSUB.I64', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPNeonBinaryArithmeticInstruction('VSUB.F32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPDoublePrecisionBinaryArithmeticInstruction('VSUB.F64', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VSUBL:
@staticmethod
def S8(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VSUBL.S8', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VSUBL.S16', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VSUBL.S32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VSUBL.U8', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VSUBL.U16', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VSUBL.U32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VMUL:
@staticmethod
def I8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMUL.I8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMUL.I16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMUL.I32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPNeonBinaryArithmeticInstruction('VMUL.F32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPDoublePrecisionBinaryArithmeticInstruction('VMUL.F64', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VMULL:
@staticmethod
def S8(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VMULL.S8', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VMULL.S16', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VMULL.S32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VMULL.U8', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VMULL.U16', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VMULL.U32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def P8(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonWideArithmeticInstruction('VMULL.P8', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VMIN:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMIN.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMIN.S16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMIN.S32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMIN.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMIN.U16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMIN.U32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMIN.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VMAX:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMAX.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMAX.S16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMAX.S32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMAX.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMAX.U16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMAX.U32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VMAX.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VABD:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VABD.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VABD.S16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VABD.S32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VABD.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VABD.U16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VABD.U32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VABD.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VACGE:
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VACGE.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VACGT:
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VACGT.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VACLE:
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VACLE.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VACLT:
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VACLT.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VAND(object):
@staticmethod
def __new__(cls, destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VAND', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VBIC(object):
@staticmethod
def __new__(cls, destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VBIC', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VORR(object):
@staticmethod
def __new__(cls, destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VORR', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VORN(object):
@staticmethod
def __new__(cls, destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VORN', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VEOR(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VEOR', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VPADD:
@staticmethod
def I8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPADD.I8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPADD.I16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPADD.I32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPADD.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VPMIN:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMIN.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMIN.S16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMIN.S32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMIN.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMIN.U16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMIN.U32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMIN.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VPMAX:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMAX.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMAX.S16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMAX.S32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMAX.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMAX.U16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMAX.U32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VPMAX.F32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VQADD:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQADD.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQADD.S16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQADD.S32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQADD.S64', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQADD.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQADD.U16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQADD.U32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQADD.U64', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VQSUB:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQSUB.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQSUB.S16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQSUB.S32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQSUB.S64', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQSUB.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQSUB.U16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQSUB.U32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VQSUB.U64', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VHADD:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHADD.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHADD.S16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHADD.S32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHADD.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHADD.U16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHADD.U32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VHSUB:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHSUB.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHSUB.S16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHSUB.S32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHSUB.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHSUB.U16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VHSUB.U32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VRHADD:
@staticmethod
def S8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VRHADD.S8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VRHADD.S16', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def S32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VRHADD.S32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U8(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VRHADD.U8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U16(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VRHADD.U16', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def U32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VRHADD.U32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VRECPS:
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VRECPS.F32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VRSQRTS:
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = NeonArithmeticInstruction('VRSQRTS.F32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VTST:
@staticmethod
def I8(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonArithmeticInstruction('VTST.8', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I16(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonArithmeticInstruction('VTST.16', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I32(destination, source_x, source_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonArithmeticInstruction('VTST.32', Operand(destination), Operand(source_x), Operand(source_y),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VNMUL:
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPSinglePrecisionMultiplyAddInstruction('VNMUL.F32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPDoublePrecisionBinaryArithmeticInstruction('VNMUL.F64', Operand(destination),
Operand(source_x), Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VDIV:
@staticmethod
def F32(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPSinglePrecisionMultiplyAddInstruction('VDIV.F32', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPDoublePrecisionBinaryArithmeticInstruction('VDIV.F64', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VSQRT:
@staticmethod
def F64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPDoublePrecisionUnaryArithmeticInstruction('VSQRT.F64', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VABS:
@staticmethod
def F64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPDoublePrecisionUnaryArithmeticInstruction('VABS.F64', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VNEG:
@staticmethod
def F64(destination, source_x, source_y=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
if source_y is None:
(destination, source_x, source_y) = (destination, destination, source_x)
instruction = VFPDoublePrecisionUnaryArithmeticInstruction('VNEG.F64', Operand(destination), Operand(source_x),
Operand(source_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VMLA:
@staticmethod
def F32(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPNeonMultiplyAddInstruction('VMLA.F32', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPDoublePrecisionMultiplyAddInstruction('VMLA.F64', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VMLS:
@staticmethod
def F32(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPNeonMultiplyAddInstruction('VMLS.F32', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPDoublePrecisionMultiplyAddInstruction('VMLS.F64', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VNMLA:
@staticmethod
def F32(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPSinglePrecisionMultiplyAddInstruction('VNMLA.F32', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPDoublePrecisionMultiplyAddInstruction('VNMLA.F64', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VNMLS:
@staticmethod
def F32(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPSinglePrecisionMultiplyAddInstruction('VNMLS.F32', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPDoublePrecisionMultiplyAddInstruction('VNMLS.F64', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VFMA:
@staticmethod
def F32(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPNeonMultiplyAddInstruction('VFMA.F32', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPDoublePrecisionMultiplyAddInstruction('VFMA.F64', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VFMS:
@staticmethod
def F32(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPNeonMultiplyAddInstruction('VFMS.F32', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPDoublePrecisionMultiplyAddInstruction('VFMS.F64', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VFNMA:
@staticmethod
def F32(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPSinglePrecisionMultiplyAddInstruction('VFNMA.F32', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPDoublePrecisionMultiplyAddInstruction('VFNMA.F64', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VFNMS:
@staticmethod
def F32(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPSinglePrecisionMultiplyAddInstruction('VFNMS.F32', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(accumulator, factor_x, factor_y):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPDoublePrecisionMultiplyAddInstruction('VFNMS.F64', Operand(accumulator), Operand(factor_x),
Operand(factor_y), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VLDR(register, address):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPLoadStoreInstruction("VLDR", Operand(register), Operand(address), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VSTR(register, address):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPLoadStoreInstruction("VSTR", Operand(register), Operand(address), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VLDM(source, destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPLoadStoreMultipleInstruction("VLDM", Operand(source), Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VLDMIA(source, destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPLoadStoreMultipleInstruction("VLDMIA", Operand(source), Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VLDMDB(source, destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPLoadStoreMultipleInstruction("VLDMDB", Operand(source), Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VSTM(source, destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPLoadStoreMultipleInstruction("VSTM", Operand(source), Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VSTMIA(source, destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPLoadStoreMultipleInstruction("VSTMIA", Operand(source), Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VSTMDB(source, destination):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPLoadStoreMultipleInstruction("VSTMDB", Operand(source), Operand(destination), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VPUSH(register_list):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPPushPopInstruction("VPUSH", Operand(register_list), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
def VPOP(register_list):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VFPPushPopInstruction("VPOP", Operand(register_list), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VLD1:
@staticmethod
def I8(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VLD1.8", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I16(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VLD1.16", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I32(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VLD1.32", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I64(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VLD1.64", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VLD1.32", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VST1:
@staticmethod
def I8(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VST1.8", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I16(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VST1.16", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I32(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VST1.32", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def I64(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VST1.64", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(address, register_list, increment=None):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = NeonLoadStoreInstruction("VST1.32", Operand(address), Operand(register_list), Operand(increment),
origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
class VMOV(object):
@staticmethod
def __new__(cls, destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VfpNeonMovInstruction('VMOV', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F32(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VfpNeonMovInstruction('VMOV.F32', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
@staticmethod
def F64(destination, source):
origin = inspect.stack() if peachpy.arm.function.active_function.collect_origin else None
instruction = VfpNeonMovInstruction('VMOV.F64', Operand(destination), Operand(source), origin=origin)
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(instruction)
return instruction
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
class Extension:
def __init__(self, name):
if name in {'V4', 'V5', 'V5E', 'V6', 'V6K', 'V7', 'V7MP', 'Div', 'Thumb', 'Thumb2',
'VFP', 'VFP2', 'VFP3', 'VFPd32', 'VFPHP', 'VFP4', 'VFPVectorMode',
'XScale', 'WMMX', 'WMMX2', 'NEON', 'NEONHP', 'NEON2'}:
self.name = name
else:
raise ValueError('Invalid ISA extension: {0} is not supported on this architecture'.format(name))
def __eq__(self, other):
return self.name == other.name
def __ne__(self, other):
return self.name != other.name
def __gt__(self, other):
return other in self.prerequisites
def __lt__(self, other):
return self in other.prerequisites
@property
def prerequisites(self):
return {
'V4': [Extension.V4],
'V5': [Extension.V4, Extension.V5],
'V5E': [Extension.V4, Extension.V5, Extension.V5E],
'V6': [Extension.V4, Extension.V5, Extension.V5E, Extension.V6],
'V6K': [Extension.V4, Extension.V5, Extension.V5E, Extension.V6, Extension.V6K],
'V7': [Extension.V4, Extension.V5, Extension.V5E, Extension.V6, Extension.V6K, Extension.V7],
'V7MP': [Extension.V4, Extension.V5, Extension.V5E, Extension.V6, Extension.V6K, Extension.V7,
Extension.V7MP],
'Div': [Extension.V4, Extension.V5, Extension.V5E, Extension.V6, Extension.V6K, Extension.V7,
Extension.V7MP, Extension.Div],
'Thumb': [Extension.Thumb],
'Thumb2': [Extension.Thumb, Extension.Thumb2],
'VFP': [Extension.VFP],
'VFP2': [Extension.VFP, Extension.VFP2],
'VFP3': [Extension.VFP, Extension.VFP2, Extension.VFP3],
'VFPd32': [Extension.VFP, Extension.VFP2, Extension.VFP3, Extension.VFPd32],
'VFPHP': [Extension.VFP, Extension.VFP2, Extension.VFP3, Extension.VFPHP],
'VFP4': [Extension.VFP, Extension.VFP2, Extension.VFP3, Extension.VFPHP, Extension.VFP4],
'VFPVectorMode': [Extension.VFP, Extension.VFP2, Extension.VFPVectorMode],
'XScale': [Extension.XScale],
'WMMX': [Extension.WMMX],
'WMMX2': [Extension.WMMX, Extension.WMMX2],
'NEON': [Extension.VFP, Extension.VFP2, Extension.VFP3, Extension.VFPd32, Extension.NEON],
'NEONHP': [Extension.VFP, Extension.VFP2, Extension.VFP3, Extension.VFPd32, Extension.NEON,
Extension.NEONHP],
'NEON2': [Extension.VFP, Extension.VFP2, Extension.VFP3, Extension.VFPd32, Extension.NEON,
Extension.NEONHP, Extension.NEON2],
}[self.name]
@property
def ancestors(self):
return {
'V4': [Extension.V4],
'V5': [Extension.V4, Extension.V5],
'V5E': [Extension.V4, Extension.V5. Extension.V5E],
'V6': [Extension.V4, Extension.V5, Extension.V5E, Extension.V6],
'V6K': [Extension.V4, Extension.V5, Extension.V5E, Extension.V6, Extension.V6K],
'V7': [Extension.V4, Extension.V5, Extension.V5E, Extension.V6, Extension.V6K, Extension.V7],
'V7MP': [Extension.V4, Extension.V5, Extension.V5E, Extension.V6, Extension.V6K, Extension.V7,
Extension.V7MP],
'Div': [Extension.Div],
'Thumb': [Extension.Thumb],
'Thumb2': [Extension.Thumb, Extension.Thumb2],
'VFP': [Extension.VFP],
'VFP2': [Extension.VFP, Extension.VFP2],
'VFP3': [Extension.VFP, Extension.VFP2, Extension.VFP3],
'VFPd32': [Extension.VFPd32],
'VFPHP': [Extension.VFPHP],
'VFP4': [Extension.VFP, Extension.VFP2, Extension.VFP3, Extension.VFPHP, Extension.VFP4],
'VFPVectorMode': [Extension.VFPVectorMode],
'XScale': [Extension.XScale],
'WMMX': [Extension.WMMX],
'WMMX2': [Extension.WMMX, Extension.WMMX2],
'NEON': [Extension.NEON],
'NEONHP': [Extension.NEON, Extension.NEONHP],
'NEON2': [Extension.NEON, Extension.NEONHP, Extension.NEON2],
}[self.name]
def __add__(self, extension):
return Extensions(self, extension)
def __hash__(self):
return hash(self.name)
def __str__(self):
return self.name
V4, V5, V5E, V6, V6K, V7, V7MP = None, None, None, None, None, None, None
Div = None
Thumb, Thumb2 = None, None
VFP, VFP2, VFP3, VFP4 = None, None, None, None
VFPVectorMode, VFPd32, VFPHP = None, None, None
XScale, WMMX, WMMX2 = None, None, None
NEON, NEONHP, NEON2 = None, None, None
All = None
Extension.V4 = Extension('V4')
Extension.V5 = Extension('V5')
Extension.V5E = Extension('V5E')
Extension.V6 = Extension('V6')
Extension.V6K = Extension('V6K')
Extension.V7 = Extension('V7')
Extension.V7MP = Extension('V7MP')
Extension.Div = Extension('Div')
Extension.Thumb = Extension('Thumb')
Extension.Thumb2 = Extension('Thumb2')
Extension.VFP = Extension('VFP')
Extension.VFP2 = Extension('VFP2')
Extension.VFP3 = Extension('VFP3')
Extension.VFP4 = Extension('VFP4')
Extension.VFPd32 = Extension('VFPd32')
Extension.VFPHP = Extension('VFPHP')
Extension.VFPVectorMode = Extension('VFPVectorMode')
Extension.XScale = Extension('XScale')
Extension.WMMX = Extension('WMMX')
Extension.WMMX2 = Extension('WMMX2')
Extension.NEON = Extension('NEON')
Extension.NEONHP = Extension('NEONHP')
Extension.NEON2 = Extension('NEON2')
Extension.All = [Extension.V4, Extension.V5, Extension.V5E, Extension.V6, Extension.V6K, Extension.V7, Extension.V7MP,
Extension.Div, Extension.Thumb, Extension.Thumb2,
Extension.VFP, Extension.VFP2, Extension.VFP3, Extension.VFP4, Extension.VFPd32, Extension.VFPHP,
Extension.VFPVectorMode, Extension.XScale, Extension.WMMX, Extension.WMMX2,
Extension.NEON, Extension.NEONHP, Extension.NEON2]
class Extensions:
def __init__(self, *args):
self.extensions = set()
for extension in args:
if extension is None:
pass
elif isinstance(extension, Extensions):
self.extensions.add(extension.extensions)
elif isinstance(extension, Extension):
self.extensions.add(extension)
else:
self.extensions.add(Extension(extension))
def __add__(self, extension):
extensions = set(self.extensions)
if isinstance(extension, Extension):
extensions.add(extension)
else:
extensions.add(Extension(extension))
return Extensions(*extensions)
def __sub__(self, extension):
extensions = set(self.extensions)
if extension in extensions:
del extensions[extension]
else:
raise KeyError('Extension set does not contain {0}'.format(extension))
return Extensions(*extensions)
def __str__(self):
extensions = list(reversed(sorted(self.extensions)))
for extension in extensions:
for ancestor in extension.ancestors:
if ancestor != extension and ancestor in extensions:
extensions.remove(ancestor)
return ", ".join(sorted(map(str, extensions)))
def __contains__(self, item):
return item in self.extensions
def __len__(self):
return len(self.extensions)
def __not__(self):
return not self.extensions
def __iter__(self):
return iter(self.extensions)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy.abi import ABI
from peachpy.abi import Endianness
from peachpy.formats.elf.file import ElfClass, MachineType, DataEncoding
from peachpy.arm.registers import r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, \
d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, \
d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31
arm_gnueabi = ABI("GNU Soft-Float ARM EABI", endianness=Endianness.Little,
bool_size=1, wchar_size=2, short_size=2, int_size=4, long_size=4, longlong_size=8,
pointer_size=4, index_size=4,
stack_alignment=8, red_zone=0,
callee_save_registers=[r4, r5, r6, r7, r8, r9, r10, r11,
d8, d9, d10, d11, d12, d13, d14, d15],
argument_registers=[r0, r1, r2, r3],
volatile_registers=[r12,
d0, d1, d2, d3, d4, d5, d6, d7,
d16, d17, d18, d19, d20, d21, d22, d23,
d24, d25, d26, d27, d28, d29, d30, d31],
elf_class=ElfClass.class32,
elf_data_encoding=DataEncoding.little_endian,
elf_machine_type=MachineType.arm)
arm_gnueabihf = ABI("GNU Hard-Float ARM EABI", endianness=Endianness.Little,
bool_size=1, wchar_size=2, short_size=2, int_size=4, long_size=4, longlong_size=8,
pointer_size=4, index_size=4,
stack_alignment=8, red_zone=0,
callee_save_registers=[r4, r5, r6, r7, r8, r9, r10, r11,
d8, d9, d10, d11, d12, d13, d14, d15],
argument_registers=[r0, r1, r2, r3],
volatile_registers=[r12,
d0, d1, d2, d3, d4, d5, d6, d7,
d16, d17, d18, d19, d20, d21, d22, d23,
d24, d25, d26, d27, d28, d29, d30, d31],
elf_class=ElfClass.class32,
elf_data_encoding=DataEncoding.little_endian,
elf_machine_type=MachineType.arm)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from __future__ import print_function
import time
import peachpy.arm.instructions
import peachpy.arm.registers
from peachpy.arm.microarchitecture import Microarchitecture
active_function = None
class Function(object):
def __init__(self, name, arguments, return_type=None,
target=Microarchitecture.Default,
abi=None,
collect_origin=False, dump_intermediate_assembly=False,
report_generation=True, report_live_registers=False):
self.name = name
self.arguments = arguments
self.return_type = return_type
for argument in self.arguments:
argument.stack_offset = None
argument.register = None
if argument.is_size_integer or argument.is_pointer_integer or argument.is_pointer:
argument.ctype.size = abi.pointer_size
assert argument.size
self.target = target
self.abi = abi
self.collect_origin = collect_origin
self.dump_intermediate_assembly = dump_intermediate_assembly
self.report_generation = report_generation
self.report_live_registers = report_live_registers
self.ticks = None
# Assign argument locations
from peachpy.arm.abi import ABI
from peachpy.arm.registers import r0, r1, r2, r3
if abi == ABI.GnuEABI or abi == ABI.GnuEABIHF:
# Up to 4 first arguments are passed in registers, others passed through stack
# Arguments smaller than 4 bytes are extended to 4 bytes (both when passed on stack or in a register).
# 8-byte arguments occupy 2 general-purpose registers or 8 bytes on stack. When they are passed in
# registers, the index of the first register must be even (i.e. they are passed in (r0, r1) or (r2, r3),
# but not in (r1, r2). When 8-byte arguments are passed on stack, their location is aligned on 8 bytes,
# skipping 4 bytes if necessary.
argument_registers = (r0, r1, r2, r3)
register_offset = 0
stack_offset = 0
for argument in self.arguments:
if argument.size <= 4:
if register_offset < 4:
argument.register = argument_registers[register_offset]
register_offset += 1
else:
argument.stack_offset = stack_offset
stack_offset += 4
elif argument.size == 8:
# First register index must be even
if register_offset % 2 == 1:
register_offset += 1
if register_offset < 4:
argument.register = (argument_registers[register_offset], argument_registers[register_offset+1])
register_offset += 2
else:
if stack_offset % 8 == 4:
stack_offset += 4
argument.stack_offset = stack_offset
stack_offset += 8
else:
raise ValueError("Unsupported argument size {0}".format(argument.size))
else:
raise ValueError("Unsupported assembler ABI %s" % abi)
self.instructions = list()
self.constants = list()
self.stack_frame = StackFrame(self.abi)
self.local_variables_count = 0
self.virtual_registers_count = 0x40
self.conflicting_registers = dict()
self.allocation_options = dict()
self.unallocated_registers = list()
def __enter__(self):
import peachpy.stream
global active_function
if active_function is not None:
raise ValueError('Function {0} was not detached'.format(active_function.name))
if peachpy.stream.active_stream is not None:
raise ValueError('Alternative instruction stream is active')
active_function = self
peachpy.stream.active_stream = self
if self.report_generation:
print("Generating function {Function} for microarchitecture {Microarchitecture} and ABI {ABI}"
.format(Function=self.name, Microarchitecture=self.target, ABI=self.abi))
print("\tParsing source", end="")
self.ticks = time.time()
return self
def __exit__(self, exc_type, exc_value, traceback):
import peachpy.stream
from peachpy.arm.instructions import Instruction
peachpy.stream.active_stream = None
if exc_type is None:
try:
self.generate_labels()
self.decompose_instructions()
self.reserve_registers()
if self.report_generation:
elapsed = time.time() - self.ticks
print(" (%2.2f secs)" % elapsed)
print("\tRunning liveness analysis", end="")
self.ticks = time.time()
self.determine_available_registers()
self.determine_live_registers(exclude_parameter_loads=True)
if self.dump_intermediate_assembly:
with open('%s.S' % self.symbol_name, "w") as intermediate_assembly_file:
for instruction in self.instructions:
if isinstance(instruction, Instruction):
consumed_registers = ", ".join(sorted(map(str, list(instruction.get_input_registers_list()))))
produced_registers = ", ".join(sorted(map(str, list(instruction.get_output_registers_list()))))
available_registers = ", ".join(sorted(map(str, list(instruction.available_registers))))
live_registers = ", ".join(sorted(map(str, list(instruction.live_registers))))
intermediate_assembly_file.write(str(instruction) + "\n")
intermediate_assembly_file.write("\tConsumed registers: " + consumed_registers + "\n")
intermediate_assembly_file.write(
"\tProduced registers: " + produced_registers + "\n")
intermediate_assembly_file.write("\tLive registers: " + live_registers + "\n")
if instruction.line_number:
intermediate_assembly_file.write(
"\tLine: " + str(instruction.line_number) + "\n")
if instruction.source_code:
intermediate_assembly_file.write("\tCode: " + instruction.source_code + "\n")
else:
intermediate_assembly_file.write(str(instruction) + "\n")
if self.report_generation:
elapsed = time.time() - self.ticks
print(" (%2.2f secs)" % elapsed)
print("\tRunning register allocation", end="")
self.ticks = time.time()
self.check_live_registers()
self.determine_register_relations()
self.allocate_registers()
if self.report_generation:
elapsed = time.time() - self.ticks
print(" (%2.2f secs)" % elapsed)
print("\tGenerating code", end="")
self.ticks = time.time()
self.remove_assume_statements()
self.update_stack_frame()
self.generate_parameter_loads()
if self.report_live_registers:
self.determine_live_registers()
self.generate_prolog_and_epilog()
self.generate_constant_loads()
self.optimize_instructions()
if self.report_generation:
elapsed = time.time() - self.ticks
print(" (%2.2f secs)" % elapsed)
self.ticks = time.time()
finally:
self.detach()
else:
self.detach()
def detach(self):
import peachpy.stream
global active_function
if active_function is None:
raise ValueError('Trying to detach a function while no function is active')
active_function = None
peachpy.stream.active_stream = None
return self
@property
def assembly(self):
from peachpy.arm.instructions import Instruction
from peachpy.arm.generic import BranchInstruction
from peachpy.arm.pseudo import LabelQuasiInstruction
import os
function_label = self.name
constants_label = self.name + "_constants"
assembly = ""
if len(self.constants) > 0:
assembly += 'section .rodata.{Microarchitecture} progbits alloc noexec nowrite align={Alignment}'\
.format(Microarchitecture=self.target.id, Alignment=32) + os.linesep
assembly += constants_label + ':' + os.linesep
data_declaration_map = {8: "DB", 16: "DW", 32: "DD", 64: "DQ", 128: "DO"}
need_alignment = False
for constant_bucket in self.constants:
if need_alignment:
assembly += "\tALIGN {Alignment}".format(Alignment=constant_bucket.capacity) + os.linesep
for constant in constant_bucket.constants:
assembly += "\t.{Label}: {Declaration} {Value}"\
.format(Label=constant.label,
Declaration=data_declaration_map[constant.size],
Value=", ".join([str(constant)] * constant.repeats)) + os.linesep
need_alignment = not constant_bucket.is_full()
assembly += os.linesep
assembly += '.section .text.{Microarchitecture},"ax",%progbits'\
.format(Microarchitecture=self.target.id) + os.linesep
assembly += "BEGIN_ARM_FUNCTION " + function_label + os.linesep
assembly += "\t" + self.gnu_arch_spec + os.linesep
if self.gnu_fpu_spec:
assembly += "\t" + self.gnu_fpu_spec + os.linesep
for instruction in self.instructions:
if isinstance(instruction, BranchInstruction):
assembly += "\t" + "{0} L{1}.{2}"\
.format(instruction.name, self.name, instruction.operands[0].label) + os.linesep
elif isinstance(instruction, Instruction):
constant = instruction.get_constant()
if constant is not None:
constant.prefix = constants_label
assembly += "\t" + str(instruction) + os.linesep
elif isinstance(instruction, LabelQuasiInstruction):
assembly += "L{0}.{1}:".format(self.name, instruction.name) + os.linesep
else:
assembly += "\t" + str(instruction) + os.linesep
assembly += "END_ARM_FUNCTION " + function_label + os.linesep
assembly += os.linesep
return assembly
@property
def gnu_arch_spec(self):
from peachpy.arm.isa import Extension
isa_extensions = self.isa_extensions
if Extension.Div in isa_extensions:
return ".cpu cortex-a15"
elif Extension.V7MP in isa_extensions:
return ".cpu cortex-a9"
elif Extension.V7 in isa_extensions:
return ".arch armv7-a"
elif Extension.V6K in isa_extensions:
return ".arch armv6zk"
elif Extension.V6 in isa_extensions:
return ".arch armv6"
elif Extension.V5E in isa_extensions:
return ".arch armv5te"
else:
return ".arch armv5t"
@property
def gnu_fpu_spec(self):
from peachpy.arm.isa import Extension
isa_extensions = self.isa_extensions
if Extension.NEON2 in isa_extensions or Extension.VFP4 in isa_extensions:
return ".fpu neon-vfpv4"
elif Extension.NEONHP in isa_extensions or \
Extension.VFPHP in isa_extensions and Extension.NEON in isa_extensions:
return ".fpu neon-fp16"
elif Extension.NEON in isa_extensions:
return ".fpu neon"
elif Extension.VFPHP in isa_extensions:
if Extension.VFPd32 in isa_extensions:
return ".fpu vfpv3-fp16"
else:
return ".fpu vfpv3-d16-fp16"
elif Extension.VFP3 in isa_extensions:
if Extension.VFPd32 in isa_extensions:
return ".fpu vfpv3"
else:
return ".fpu vfpv3-d16"
elif Extension.VFP in isa_extensions or Extension.VFP2 in isa_extensions:
return
elif Extension.VFP3 in isa_extensions:
return ".fpu vfp"
else:
return None
def add_instruction(self, instruction):
from peachpy.arm.instructions import Instruction
if instruction is None:
return
if isinstance(instruction, Instruction):
for extension in instruction.isa_extensions:
if extension not in self.target.extensions:
raise ValueError("{0} is not supported on the target microarchitecture".format(extension))
local_variable = instruction.get_local_variable()
if local_variable is not None:
self.stack_frame.add_variable(local_variable.get_root())
self.stack_frame.preserve_registers(instruction.get_output_registers_list())
self.instructions.append(instruction)
def add_instructions(self, instructions):
for instruction in instructions:
self.add_instruction(instruction)
def decompose_instructions(self):
from peachpy.arm.pseudo import ReturnInstruction
new_instructions = list()
for instruction in self.instructions:
if isinstance(instruction, ReturnInstruction):
new_instructions.extend(instruction.to_instruction_list())
else:
new_instructions.append(instruction)
self.instructions = new_instructions
def generate_prolog_and_epilog(self):
from peachpy.arm.generic import BranchExchangeInstruction
from peachpy.arm.pseudo import LabelQuasiInstruction
prologue_instructions = self.stack_frame.generate_prologue()
epilogue_instructions = self.stack_frame.generate_epilogue()
new_instructions = list()
for instruction in self.instructions:
if isinstance(instruction, LabelQuasiInstruction):
new_instructions.append(instruction)
if instruction.name == 'ENTRY':
new_instructions.extend(prologue_instructions)
elif isinstance(instruction, BranchExchangeInstruction):
new_instructions.extend(epilogue_instructions)
new_instructions.append(instruction)
else:
new_instructions.append(instruction)
self.instructions = new_instructions
def generate_labels(self):
from peachpy.arm.pseudo import LabelQuasiInstruction
from peachpy.arm.instructions import Operand
for instruction in self.instructions:
if isinstance(instruction, LabelQuasiInstruction):
if instruction.name == 'ENTRY':
break
else:
self.instructions.insert(0, LabelQuasiInstruction(Operand("ENTRY")))
def get_label_table(self):
from peachpy.arm.pseudo import LabelQuasiInstruction
label_table = dict()
for index, instruction in enumerate(self.instructions):
if isinstance(instruction, LabelQuasiInstruction):
label_table[instruction.name] = index
return label_table
def find_entry_label(self):
from peachpy.arm.pseudo import LabelQuasiInstruction
for index, instruction in enumerate(self.instructions):
if isinstance(instruction, LabelQuasiInstruction):
if instruction.name == 'ENTRY':
return index
raise ValueError('Instruction stream does not contain the ENTRY label')
def find_exit_points(self):
from peachpy.arm.generic import BranchExchangeInstruction
ret_instructions = list()
for index, instruction in enumerate(self.instructions):
if isinstance(instruction, BranchExchangeInstruction):
ret_instructions.append(index)
return ret_instructions
def determine_branches(self):
from peachpy.arm.generic import BranchInstruction
from peachpy.arm.pseudo import LabelQuasiInstruction
label_table = self.get_label_table()
for instruction in self.instructions:
if isinstance(instruction, LabelQuasiInstruction):
instruction.input_branches = set()
for i, instruction in enumerate(self.instructions):
if isinstance(instruction, BranchInstruction):
target_label = instruction.operands[0].label
target_index = label_table[target_label]
self.instructions[target_index].input_branches.add(i)
def reserve_registers(self):
pass
def determine_available_registers(self):
from peachpy.arm.instructions import Instruction
from peachpy.arm.generic import BranchInstruction
processed_branches = set()
label_table = self.get_label_table()
def mark_available_registers(instructions, start, initial_available_registers):
available_registers = set(initial_available_registers)
for i in range(start, len(instructions)):
instruction = instructions[i]
if isinstance(instruction, Instruction):
instruction.available_registers = set(available_registers)
if isinstance(instruction, BranchInstruction):
if i not in processed_branches:
target_label = instruction.operands[0].label
target_index = label_table[target_label]
processed_branches.add(i)
mark_available_registers(instructions, target_index, available_registers)
if not instruction.is_conditional():
return
else:
available_registers |= set(instruction.get_output_registers_list())
current_index = self.find_entry_label()
mark_available_registers(self.instructions, current_index, set())
def determine_live_registers(self, exclude_parameter_loads=False):
from peachpy.arm.instructions import Instruction
from peachpy.arm.generic import BranchInstruction
from peachpy.arm.pseudo import LoadArgumentPseudoInstruction, LabelQuasiInstruction
from peachpy.arm.registers import Register
self.determine_branches()
for instruction in self.instructions:
if isinstance(instruction, Instruction):
live_registers = set()
if isinstance(instruction, BranchInstruction):
instruction.is_visited = False
def mark_live_registers(instructions, exit_point, initial_live_registers):
live_registers = dict(initial_live_registers)
# Walk from the bottom to top of the linear block
for i in range(exit_point, -1, -1):
instruction = instructions[i]
if isinstance(instruction, BranchInstruction) and not instruction.is_conditional and i != exit_point:
return
elif isinstance(instruction, Instruction):
# First mark registers which are written to by this instruction as non-live
# Then mark registers which are read by this instruction as live
for output_register in instruction.get_output_registers_list():
register_id = output_register.id
register_mask = output_register.mask
if register_id in live_registers:
live_registers[register_id] &= ~register_mask
if live_registers[register_id] == 0:
del live_registers[register_id]
if not (exclude_parameter_loads and isinstance(instruction, LoadArgumentPseudoInstruction)):
for input_register in instruction.get_input_registers_list():
register_id = input_register.id
register_mask = input_register.mask
if register_id in live_registers:
live_registers[register_id] |= register_mask
else:
live_registers[register_id] = register_mask
# Merge with previously determined as live registers
for instruction_live_register in instruction.live_registers:
if instruction_live_register.id in live_registers:
live_registers[instruction_live_register.id] |= instruction_live_register.mask
else:
live_registers[instruction_live_register.id] = instruction_live_register.mask
instruction.live_registers = set([Register.from_parts(id, mask, expand=True)
for (id, mask) in live_registers.iteritems()])
elif isinstance(instruction, LabelQuasiInstruction):
for entry_point in instruction.input_branches:
if not instructions[entry_point].is_visited:
instructions[entry_point].is_visited = True
mark_live_registers(instructions, entry_point, live_registers)
exit_points = self.find_exit_points()
for exit_point in exit_points:
mark_live_registers(self.instructions, exit_point, set())
def check_live_registers(self):
pass
# all_registers = self.abi.volatile_registers + list(reversed(self.abi.argument_registers)) + self.abi.callee_save_registers
# available_registers = { Register.GPType: list(), Register.WMMXType: list(), Register.VFPType: list() }
# for register in all_registers:
# if register not in available_registers[register.regtype]:
# available_registers[register.regtype].append(register)
# for instruction in self.instructions:
# live_registers = { Register.GPType: set(), Register.WMMXType: set(), Register.VFPType: set() }
# if isinstance(instruction, Instruction):
# for live_register in instruction.live_registers:
# live_registers[live_register.regtype].add(live_register)
# for register_type in live_registers.iterkeys():
# if len(live_registers[register_type]) > len(available_registers[register_type]):
# raise ValueError("Not enough available registers to allocate live registers at instruction {0}".format(instruction))
def determine_register_relations(self):
from peachpy import RegisterAllocationError
from peachpy.arm.registers import Register, SRegister, DRegister, QRegister
from peachpy.arm.instructions import Instruction
from peachpy.arm.vfpneon import NeonLoadStoreInstruction, VFPLoadStoreMultipleInstruction
all_registers = self.abi.volatile_registers + list(
reversed(self.abi.argument_registers)) + self.abi.callee_save_registers
available_registers = {Register.GPType: list(), Register.WMMXType: list(), Register.VFPType: list()}
for register in all_registers:
if register.type == Register.GPType or register.type == Register.WMMXType:
register_bitboard = 0x1 << register.get_physical_number()
if register_bitboard not in available_registers[register.type]:
available_registers[register.type].append(register_bitboard)
for instruction in self.instructions:
if isinstance(instruction, Instruction):
virtual_live_registers = [register for register in instruction.live_registers if register.is_virtual]
for registerX in virtual_live_registers:
if registerX.type == Register.VFPType:
if isinstance(registerX, SRegister) and registerX.parent:
registerX = registerX.parent
if isinstance(registerX, DRegister) and registerX.parent:
registerX = registerX.parent
if registerX.get_id() not in self.allocation_options:
if isinstance(registerX, SRegister):
self.allocation_options[registerX.id] = [(0x1 << n) for n in range(32)]
elif isinstance(registerX, DRegister):
if self.target.has_vfpd32:
self.allocation_options[registerX.id] = [(0x3 << n) for n in range(0, 64, 2)]
else:
self.allocation_options[registerX.id] = [(0x3 << n) for n in range(0, 32, 2)]
else:
self.allocation_options[registerX.id] = [(0xF << n) for n in range(0, 64, 4)]
else:
if registerX.id not in self.allocation_options:
self.allocation_options[registerX.id] = list(available_registers[registerX.type])
self.unallocated_registers.append((registerX.id, registerX.type))
# Setup the list of conflicting registers for each virtual register
if registerX.id not in self.conflicting_registers:
self.conflicting_registers[registerX.id] = set()
for registerY in virtual_live_registers:
# VFP registers have a conflict even they are of different size
if registerX.id != registerY.id and registerX.type == registerY.type:
self.conflicting_registers[registerX.id].add(registerY.id)
# Mark available physical registers for each virtual register
for instruction in self.instructions:
if isinstance(instruction, Instruction):
virtual_live_registers = [register for register in instruction.live_registers if register.is_virtual]
# If a physical register is live at some point, it can not be allocated for a virtual register
physical_live_registers = [register for register in instruction.live_registers if
not register.is_virtual]
for virtual_register in virtual_live_registers:
for physical_register in physical_live_registers:
if virtual_register.type == physical_register.type:
virtual_register_id = virtual_register.id
physical_register_bitboard = physical_register.bitboard
self.allocation_options[virtual_register_id][:] = \
[possible_register_bitboard for possible_register_bitboard in
self.allocation_options[virtual_register_id]
if (possible_register_bitboard & physical_register_bitboard) == 0]
# Detect group constraints
constraints = dict()
for instruction in self.instructions:
if isinstance(instruction, NeonLoadStoreInstruction) or isinstance(instruction,
VFPLoadStoreMultipleInstruction):
if isinstance(instruction, NeonLoadStoreInstruction):
register_list = instruction.operands[0].get_registers_list()
physical_registers_count = 32
else:
register_list = instruction.operands[1].get_registers_list()
physical_registers_count = 32 if self.target.has_vfpd32 else 16
if len(register_list) > 1:
if all(isinstance(register, DRegister) for register in register_list):
register_id_list = list()
for register in register_list:
register_id = register.get_id()
if register_id not in register_id_list:
register_id_list.append(register_id)
register_id_list = tuple(register_id_list)
# Iterate possible allocations for this register list
# For VLD1/VST1 instructions all registers must be allocated to sequential physical registers
options = list()
for sequence_bitboard_position in range(0, 2 * physical_registers_count - 2 * len(
register_list) + 2, 2):
register_bitboards = [0x3 << (sequence_bitboard_position + 2 * i) for i in
range(len(register_list))]
for i, (bitboard, register) in enumerate(zip(register_bitboards, register_list)):
register_bitboards[i] = register.extend_bitboard(bitboard)
# Check that bitboard is available for allocation
for register, bitboard in zip(register_list, register_bitboards):
if bitboard not in self.allocation_options[register.get_id()]:
break
else:
# Check that if registers with the same id use the same bitboard in this allocation
register_id_map = dict()
for register, bitboard in zip(register_list, register_bitboards):
register_id = register.get_id()
if register_id in register_id_map:
if register_id_map[register_id] != bitboard:
break
else:
register_id_map[register_id] = bitboard
else:
# Check that allocation bitboards do not overlap:
allocation_bitboard = 0
for bitboard in register_id_map.itervalues():
if (allocation_bitboard & bitboard) == 0:
allocation_bitboard |= bitboard
else:
break
else:
ordered_bitboard_list = [register_id_map[register_id] for register_id in
register_id_list]
options.append(tuple(ordered_bitboard_list))
if options:
if len(register_id_list) > 1:
if register_id_list in constraints:
constraints[register_id_list] = tuple(
[option for option in constraints[register_id_list] if option in options])
else:
constraints[register_id_list] = tuple(options)
else:
raise RegisterAllocationError("Imposible virtual register combination in instruction %s"
% instruction)
elif all(isinstance(register, SRegister) for register in register_list) and \
isinstance(instruction, VFPLoadStoreMultipleInstruction):
register_id_list = list()
for register in register_list:
register_id = register.id
if register_id not in register_id_list:
register_id_list.append(register_id)
register_id_list = tuple(register_id_list)
# Iterate possible allocations for this register list
# For VLDM/VSTM instructions all registers must be allocated to sequential physical registers
options = list()
for sequence_bitboard_position in range(0, 32 - len(register_list) + 1):
register_bitboards = [0x1 << (sequence_bitboard_position + i) for i in
range(len(register_list))]
for i, (bitboard, register) in enumerate(zip(register_bitboards, register_list)):
register_bitboards[i] = register.extend_bitboard(bitboard)
# Check that bitboard is available for allocation
for register, bitboard in zip(register_list, register_bitboards):
if bitboard not in self.allocation_options[register.id]:
break
else:
# Check that if registers with the same id use the same bitboard in this allocation
register_id_map = dict()
for register, bitboard in zip(register_list, register_bitboards):
register_id = register.id
if register_id in register_id_map:
if register_id_map[register_id] != bitboard:
break
else:
register_id_map[register_id] = bitboard
else:
# Check that allocation bitboards do not overlap:
allocation_bitboard = 0
for bitboard in register_id_map.itervalues():
if (allocation_bitboard & bitboard) == 0:
allocation_bitboard |= bitboard
else:
break
else:
ordered_bitboard_list = [register_id_map[register_id] for register_id in
register_id_list]
options.append(tuple(ordered_bitboard_list))
if options:
if len(register_id_list) > 1:
if register_id_list in constraints:
constraints[register_id_list] = tuple(
[option for option in constraints[register_id_list] if option in options])
else:
constraints[register_id_list] = tuple(options)
else:
raise RegisterAllocationError(
"Imposible virtual register combination in instruction %s" % instruction)
else:
assert False
report_register_constraints = False
if report_register_constraints:
for (register_list, options) in constraints.iteritems():
print("REGISTER CONSTRAINTS: ", map(str, register_list))
for option in options:
print("\t", map(lambda t: "%016X" % t, option))
# Merging of different groups sharing a register will be implemented here sometime
# Check that each register id appears only once
constrained_register_id_list = [register_id for register_id_list in constraints.iterkeys() for register_id in
register_id_list]
assert (len(constrained_register_id_list) == len(set(constrained_register_id_list)))
constrained_register_id_set = set(constrained_register_id_list)
# Create a map from constrained register to constrained register group
# constrained_register_map = dict()
# for register_id_list in constraints.iterkeys():
# for register_id in register_id_list:
# constrained_register_map[register_id] = register_id_list
# Remove individual registers from the set of unallocated registers and add the register group instead
for constrained_register_id in constrained_register_id_list:
while (constrained_register_id, Register.VFPType) in self.unallocated_registers:
self.unallocated_registers.remove((constrained_register_id, Register.VFPType))
for register_id_list in constraints.iterkeys():
self.unallocated_registers.append((register_id_list, Register.VFPType))
# print "UNALLOCATED REGISTERS:"
# print "\t", self.unallocated_registers
# Remove individual registers from the sets of conflicting registers and add the register group instead
# for register_id_list in constraints.iterkeys():
# self.conflicting_registers[register_id_list] = set()
# for constrained_register_id in constrained_register_id_list:
# self.conflicting_registers[constrained_register_map[constrained_register_id]].update(self.conflicting_registers[constrained_register_id])
# del self.conflicting_registers[constrained_register_id]
# for conflicting_registers_set in self.conflicting_registers.itervalues():
# for constrained_register_id in constrained_register_id_list:
# if constrained_register_id in conflicting_registers_set:
# conflicting_registers_set.remove(constrained_register_id)
# conflicting_registers_set.add(constrained_register_map[constrained_register_id])
# Remove individual registers from the lists of allocation options and add the register group instead
for constrained_register_id in constrained_register_id_list:
del self.allocation_options[constrained_register_id]
for register_id_list, constrained_options in constraints.iteritems():
self.allocation_options[register_id_list] = list(options)
def allocate_registers(self):
from peachpy.arm.registers import Register
from peachpy.arm.instructions import Instruction
from peachpy.arm.pseudo import LoadArgumentPseudoInstruction
# Map from virtual register id to physical register
register_allocation = dict()
for (virtual_register_id, virtual_register_type) in self.unallocated_registers:
register_allocation[virtual_register_id] = None
def bind_register(virtual_register_id, physical_register):
# Remove option to allocate any conflicting virtual register to the same physical register or its enclosing register
physical_register_bitboard = physical_register.bitboard
for conflicting_register_id in self.conflicting_registers[virtual_register_id]:
if conflicting_register_id in self.allocation_options:
for allocation_bitboard in self.allocation_options[conflicting_register_id]:
if (allocation_bitboard & physical_register_bitboard) != 0:
self.allocation_options[conflicting_register_id].remove(allocation_bitboard)
register_allocation[virtual_register_id] = physical_register
def bind_registers(virtual_register_id_list, physical_register_id_list):
# Remove option to allocate any conflicting virtual register to the same physical register or its enclosing register
physical_register_bitboard_list = [physical_register.get_bitboard() for physical_register in
physical_register_id_list]
for virtual_register_id, physical_register_bitboard in zip(virtual_register_id_list,
physical_register_bitboard_list):
for conflicting_register_id in self.conflicting_registers[virtual_register_id]:
for allocation_key, allocation_option in self.allocation_options.iteritems():
if isinstance(allocation_key, tuple):
if conflicting_register_id in allocation_key:
conflicting_register_index = allocation_key.index(conflicting_register_id)
for bitboard_list in allocation_option:
if (bitboard_list[conflicting_register_index] & physical_register_bitboard) != 0:
allocation_option.remove(bitboard_list)
else:
if conflicting_register_id == allocation_key:
for bitboard in allocation_option:
if (bitboard & physical_register_bitboard) != 0:
allocation_option.remove(bitboard)
for virtual_register_id, physical_register_id in zip(virtual_register_id_list, physical_register_id_list):
register_allocation[virtual_register_id] = physical_register_id
def is_allocated(virtual_register_id):
return bool(register_allocation[virtual_register_id])
# First allocate parameters
for instruction in self.instructions:
if isinstance(instruction, LoadArgumentPseudoInstruction):
if instruction.argument.register:
if instruction.destination.register.is_virtual:
if not is_allocated(instruction.destination.register.id):
if instruction.argument.register.bitboard in self.allocation_options[
instruction.destination.register.id]:
bind_register(instruction.destination.register.id, instruction.argument.register)
# Now allocate registers with special restrictions
for virtual_register_id_list, virtual_register_type in self.unallocated_registers:
if isinstance(virtual_register_id_list, tuple):
# print "REGLIST: ", map(str, virtual_register_id_list)
assert self.allocation_options[virtual_register_id_list]
physical_register_bitboard_list = self.allocation_options[virtual_register_id_list][0]
physcial_registers_list = [Register.from_bitboard(physical_register_bitboard, virtual_register_type) for
physical_register_bitboard in physical_register_bitboard_list]
bind_registers(virtual_register_id_list, physcial_registers_list)
# Now allocate all other registers
while self.unallocated_registers:
virtual_register_id, virtual_register_type = self.unallocated_registers.pop(0)
if not isinstance(virtual_register_id, tuple):
if not is_allocated(virtual_register_id):
assert self.allocation_options[virtual_register_id]
physical_register_bitboard = self.allocation_options[virtual_register_id][0]
physical_register = Register.from_bitboard(physical_register_bitboard, virtual_register_type)
bind_register(virtual_register_id, physical_register)
for instruction in self.instructions:
if isinstance(instruction, Instruction):
for input_register in instruction.get_input_registers_list():
if input_register.is_virtual:
input_register.bind(register_allocation[input_register.id])
for output_register in instruction.get_output_registers_list():
if output_register.is_virtual:
if output_register.id in register_allocation:
output_register.bind(register_allocation[output_register.id])
# Updates information about registers to be saved/restored in the function prologue/epilogue
def update_stack_frame(self):
from peachpy.arm.instructions import Instruction
for instruction in self.instructions:
if isinstance(instruction, Instruction):
self.stack_frame.preserve_registers(instruction.get_output_registers_list())
def remove_assume_statements(self):
from peachpy.arm.pseudo import AssumeInitializedPseudoInstruction
new_instructions = list()
for instruction in self.instructions:
if isinstance(instruction, AssumeInitializedPseudoInstruction):
continue
else:
new_instructions.append(instruction)
self.instructions = new_instructions
def generate_parameter_loads(self):
from peachpy.arm.registers import sp
from peachpy.arm.generic import MOV, LDR
from peachpy.arm.pseudo import LoadArgumentPseudoInstruction
new_instructions = list()
for instruction in self.instructions:
if isinstance(instruction, LoadArgumentPseudoInstruction):
parameter = instruction.argument
if parameter.register:
# If parameter is in a register, use register-register move:
if instruction.destination.register != parameter.register:
# Parameter is in a different register than instruction destination, generate move:
new_instruction = MOV(instruction.destination.register, parameter.register)
new_instruction.live_registers = instruction.live_registers
new_instruction.available_registers = instruction.available_registers
new_instructions.append(new_instruction)
# If parameter is in the same register as instruction destination, no instruction needed:
# MOV( instruction.destination == parameter.register_location, parameter.register_location )
# is a no-op
else:
parameter_address = self.stack_frame.get_parameters_offset() + parameter.stack_offset
new_instruction = LDR(instruction.destination.register, [sp, parameter_address])
new_instruction.live_registers = instruction.live_registers
new_instruction.available_registers = instruction.available_registers
new_instructions.append(new_instruction)
else:
new_instructions.append(instruction)
self.instructions = new_instructions
def generate_constant_loads(self):
from peachpy.arm.instructions import Instruction
from peachpy.arm.pseudo import LoadConstantPseudoInstruction
from peachpy import ConstantBucket
max_alignment = 0
for instruction in self.instructions:
if isinstance(instruction, Instruction):
constant = instruction.get_constant()
if constant is not None:
constant_alignment = constant.get_alignment()
constant_size = constant.size * constant.repeats
max_alignment = max(max_alignment, constant_alignment)
constant_id = 0
constant_label_map = dict()
constant_buckets = dict()
for instruction in self.instructions:
if isinstance(instruction, Instruction):
constant = instruction.get_constant()
if constant is not None:
if constant in constant_label_map:
constant.label = constant_label_map[constant]
else:
constant.label = "c" + str(constant_id)
constant_id += 1
constant_label_map[constant] = constant.label
constant_alignment = constant.get_alignment()
constant_size = constant.size * constant.repeats
if constant_alignment in constant_buckets:
constant_buckets[constant_alignment].add(constant)
if constant_buckets[constant_alignment].is_full():
del constant_buckets[constant_alignment]
else:
constant_bucket = ConstantBucket(max_alignment / 8)
constant_bucket.add(constant)
self.constants.append(constant_bucket)
if not constant_bucket.is_full():
constant_buckets[constant_alignment] = constant_bucket
new_instructions = list()
for instruction in self.instructions:
if isinstance(instruction, LoadConstantPseudoInstruction):
raise NotImplementedError()
else:
new_instructions.append(instruction)
self.instructions = new_instructions
def optimize_instructions(self):
from peachpy.arm.generic import MovInstruction
from peachpy.arm.vfpneon import VfpNeonMovInstruction
new_instructions = list()
for instruction in self.instructions:
# Remove moves where source and destination are the same
if isinstance(instruction, MovInstruction):
if len(instruction.operands) != 2 or instruction.operands[0] != instruction.operands[1]:
new_instructions.append(instruction)
elif isinstance(instruction, VfpNeonMovInstruction):
if instruction.operands[0] != instruction.operands[1]:
new_instructions.append(instruction)
else:
new_instructions.append(instruction)
self.instructions = new_instructions
def get_target(self):
return self.target
@property
def isa_extensions(self):
from peachpy.arm.instructions import Instruction
from peachpy.arm.registers import QRegister, DRegister
from peachpy.arm.isa import Extension, Extensions
isa_extensions = Extensions()
for instruction in self.instructions:
if isinstance(instruction, Instruction):
for extension in instruction.isa_extensions:
isa_extensions += extension
if any(isinstance(register, QRegister) or
isinstance(register, DRegister) and register.is_extended for
register in instruction.get_registers_list()):
isa_extensions += Extension.VFPd32
return isa_extensions
def get_yeppp_isa_extensions(self):
isa_extensions_map = {'V4': ('V4', None, None),
'V5': ( 'V5', None, None),
'V5E': ( 'V5E', None, None),
'V6': ( 'V6', None, None),
'V6K': ( 'V6K', None, None),
'V7': ( 'V7', None, None),
'V7MP': ( 'V7MP', None, None),
'Div': ( 'Div', None, None),
'Thumb': ( 'Thumb', None, None),
'Thumb2': ( 'Thumb2', None, None),
'VFP': ( 'VFP', None, None),
'VFP2': ( 'VFP2', None, None),
'VFP3': ( 'VFP3', None, None),
'VFPd32': ( 'VFPd32', None, None),
'VFP3HP': ( 'VFP3HP', None, None),
'VFP4': ( 'VFP4', None, None),
'VFPVectorMode': ( None, None, 'VFPVectorMode'),
'XScale': ( None, 'XScale', None),
'WMMX': ( None, 'WMMX', None),
'WMMX2': ( None, 'WMMX2', None),
'NEON': ( None, 'NEON', None),
'NEONHP': ( None, 'NEONHP', None),
'NEON2': ( None, 'NEON2', None)}
(isa_extensions, simd_extensions, system_extensions) = (set(), set(), set())
for isa_extension in self.get_isa_extensions():
if isa_extension is not None:
(isa_extension, simd_extension, system_extension) = isa_extensions_map[isa_extension]
if isa_extension is not None:
isa_extensions.add(isa_extension)
if simd_extension is not None:
simd_extensions.add(simd_extension)
if system_extension is not None:
system_extensions.add(system_extension)
isa_extensions = map(lambda id: "YepARMIsaFeature" + id, isa_extensions)
if not isa_extensions:
isa_extensions = ["YepIsaFeaturesDefault"]
simd_extensions = map(lambda id: "YepARMSimdFeature" + id, simd_extensions)
if not simd_extensions:
simd_extensions = ["YepSimdFeaturesDefault"]
system_extensions = map(lambda id: "YepARMSystemFeature" + id, system_extensions)
if not system_extensions:
system_extensions = ["YepSystemFeaturesDefault"]
return (isa_extensions, simd_extensions, system_extensions)
def allocate_local_variable(self):
self.local_variables_count += 1
return self.local_variables_count
def allocate_q_register(self):
self.virtual_registers_count += 1
return (self.virtual_registers_count << 12) | 0x0F0
def allocate_d_register(self):
self.virtual_registers_count += 1
return (self.virtual_registers_count << 12) | 0x300
def allocate_s_register(self):
self.virtual_registers_count += 1
return (self.virtual_registers_count << 12) | 0x400
def allocate_wmmx_register(self):
self.virtual_registers_count += 1
return (self.virtual_registers_count << 12) | 0x002
def allocate_general_purpose_register(self):
self.virtual_registers_count += 1
return (self.virtual_registers_count << 12) | 0x001
class LocalVariable(object):
def __init__(self, register_type):
from peachpy.arm.registers import GeneralPurposeRegister, WMMXRegister, SRegister, DRegister, QRegister
super(LocalVariable, self).__init__()
if isinstance(register_type, int):
self.size = register_type
elif register_type == GeneralPurposeRegister:
self.size = 4
elif register_type == WMMXRegister:
self.size = 8
elif register_type == SRegister:
self.size = 4
elif register_type == DRegister:
self.size = 8
elif register_type == QRegister:
self.size = 16
else:
raise ValueError('Unsupported register type {0}'.format(register_type))
self.id = active_function.allocate_local_variable()
self.address = None
self.offset = 0
self.parent = None
def __eq__(self, other):
return self.id == other.id
def __hash__(self):
return hash(self.id)
def __str__(self):
if self.is_subvariable():
address = self.parent.get_address()
if address is not None:
address += self.offset
else:
address = self.address
if address is not None:
return "[{0}]".format(address)
else:
return "local-variable<{0}>".format(self.id)
def is_subvariable(self):
return self.parent is not None
def get_parent(self):
return self.parent
def get_root(self):
if self.is_subvariable():
return self.get_parent().get_root()
else:
return self
def get_address(self):
if self.is_subvariable():
return self.parent.get_address() + self.offset
else:
return self.address
def get_size(self):
return self.size
def get_low(self):
assert self.get_size() % 2 == 0
child = LocalVariable(self.get_size() / 2)
child.parent = self
child.offset = 0
return child
def get_high(self):
assert self.get_size() % 2 == 0
child = LocalVariable(self.get_size() / 2)
child.parent = self
child.offset = self.get_size() / 2
return child
class StackFrame(object):
def __init__(self, abi):
super(StackFrame, self).__init__()
self.abi = abi
self.general_purpose_registers = list()
self.d_registers = list()
self.s_variables = list()
self.d_variables = list()
self.q_variables = list()
def preserve_registers(self, registers):
for register in registers:
self.preserve_register(register)
def preserve_register(self, register):
from peachpy.arm.registers import GeneralPurposeRegister, SRegister, DRegister, QRegister
if isinstance(register, GeneralPurposeRegister):
if not register in self.general_purpose_registers:
if register in self.abi.callee_save_registers:
self.general_purpose_registers.append(register)
elif isinstance(register, SRegister):
if not register.is_virtual():
register = register.get_parent()
if not register in self.d_registers:
if register in self.abi.callee_save_registers:
self.d_registers.append(register)
elif isinstance(register, DRegister):
if not register in self.d_registers:
if register in self.abi.callee_save_registers:
self.d_registers.append(register)
elif isinstance(register, QRegister):
d_low = register.get_low_part()
d_high = register.get_high_part()
if d_low not in self.d_registers:
if register in self.abi.callee_save_registers:
self.d_registers.append(d_low)
if d_high not in self.d_registers:
if register in self.abi.callee_save_registers:
self.d_registers.append(d_high)
else:
raise TypeError("Unsupported register type {0}".format(type(register)))
def add_variable(self, variable):
if variable.get_size() == 16:
if variable not in self.sse_variables:
self.sse_variables.append(variable)
elif variable.get_size() == 32:
if variable not in self.avx_variables:
self.avx_variables.append(variable)
else:
raise TypeError("Unsupported variable type {0}".format(type(variable)))
def get_parameters_offset(self):
parameters_offset = len(self.general_purpose_registers) * 4
if parameters_offset % 8 == 4:
parameters_offset += 4
return parameters_offset + len(self.d_registers) * 8
def generate_prologue(self):
from peachpy.stream import InstructionStream
from peachpy.arm.registers import r3
from peachpy.arm.generic import PUSH
from peachpy.arm.vfpneon import VPUSH
with InstructionStream() as instructions:
if self.general_purpose_registers:
general_purpose_registers = list(self.general_purpose_registers)
if len(general_purpose_registers) % 2 == 1:
general_purpose_registers.append(r3)
PUSH(tuple(sorted(general_purpose_registers, key=lambda reg: reg.get_physical_number())))
if self.d_registers:
VPUSH(tuple(sorted(self.d_registers, key=lambda reg: reg.get_physical_number())))
return list(iter(instructions))
def generate_epilogue(self):
from peachpy.stream import InstructionStream
from peachpy.arm.registers import r3
from peachpy.arm.generic import POP
from peachpy.arm.vfpneon import VPOP
with InstructionStream() as instructions:
if self.d_registers:
VPOP(tuple(sorted(self.d_registers, key=lambda reg: reg.get_physical_number())))
if self.general_purpose_registers:
general_purpose_registers = list(self.general_purpose_registers)
if len(general_purpose_registers) % 2 == 1:
general_purpose_registers.append(r3)
POP(tuple(sorted(general_purpose_registers, key=lambda reg: reg.get_physical_number())))
return list(iter(instructions))
|
__author__ = 'marat'
|
class Type:
def __init__(self, base, size=None, is_const=False,
is_floating_point=False, is_signed_integer=False, is_unsigned_integer=False,
is_pointer_integer=False, is_size_integer=False, is_vector=False, is_mask=False,
is_char=False, is_wchar=False, is_bool=False,
is_short=False, is_int=False, is_long=False, is_longlong=False,
header=None):
self.size = size
self.is_const = is_const
self.is_floating_point = is_floating_point
self.is_signed_integer = is_signed_integer
self.is_unsigned_integer = is_unsigned_integer
self.is_pointer_integer = is_pointer_integer
self.is_size_integer = is_size_integer
self.is_vector = is_vector
self.is_mask = is_mask
self.is_short = is_short
self.is_char = is_char
self.is_wchar = is_wchar
self.is_bool = is_bool
self.is_int = is_int
self.is_long = is_long
self.is_longlong = is_longlong
self.header = header
if base is None or isinstance(base, Type):
self.base = base
self.name = None
self.is_pointer = True
elif isinstance(base, str):
self.base = None
self.name = base
self.is_pointer = False
else:
raise TypeError("%s must be either a type name or a type" % base)
def __str__(self):
if self.is_pointer:
if self.base is None:
text = "void*"
else:
text = str(self.base) + "*"
if self.is_const:
text += " const"
else:
text = self.name
if self.is_const:
text = "const " + text
return text
def __hash__(self):
if self.is_pointer:
h = hash(self.base)
return (h >> 5) | ((h & 0x07FFFFFF) << 27)
else:
h = 0
if self.is_fixed_size:
h = hash(self.size)
if self.is_floating_point:
h ^= 0x00000003
if self.is_signed_integer:
h ^= 0x0000000C
if self.is_unsigned_integer:
h ^= 0x00000030
if self.is_pointer_integer:
h ^= 0x000000C0
if self.is_size_integer:
h ^= 0x00000300
if self.is_vector:
h ^= 0x00000C00
h ^= hash(self.name)
if self.is_mask:
h ^= 0x00003000
if self.is_short:
h ^= 0x0000C000
if self.is_char:
h ^= 0x00030000
if self.is_wchar:
h ^= 0x000C0000
if self.is_bool:
h ^= 0x00300000
if self.is_int:
h ^= 0x00C00000
if self.is_long:
h ^= 0x03000000
if self.is_longlong:
h ^= 0x0C000000
return h
def __eq__(self, other):
if not isinstance(other, Type):
return False
elif self.is_pointer:
return other.is_pointer and self.base == other.base
else:
if self.name == other.name:
return True
else:
if self.is_vector and other.is_vector:
return self.name == other.name
else:
# If both types have size, check it. If any doesn't have type, ignore size altogether.
# This is important because the size of ABI-specific types (size_t, etc) is updated after binding
# to ABI and it is important to ensure that e.g. size_t == size_t after ABI binding too
if self.size is not None and other.size is not None and self.size != other.size:
return False
else:
return self.is_floating_point == other.is_floating_point and \
self.is_signed_integer == other.is_signed_integer and \
self.is_unsigned_integer == other.is_unsigned_integer and \
self.is_pointer_integer == other.is_pointer_integer and \
self.is_size_integer == other.is_size_integer and \
self.is_vector == other.is_vector and \
self.is_mask == other.is_mask and \
self.is_short == other.is_short and \
self.is_char == other.is_char and \
self.is_wchar == other.is_wchar and \
self.is_bool == other.is_bool and \
self.is_int == other.is_int and \
self.is_long == other.is_long and \
self.is_longlong == other.is_longlong
def __ne__(self, other):
return not self == other
def get_size(self, abi):
if self.size is None:
if self.is_pointer or self.is_pointer_integer:
return abi.pointer_size
elif self.is_size_integer:
return abi.index_size
elif self.is_short:
return abi.short_size
elif self.is_int:
return abi.int_size
elif self.is_long:
return abi.long_size
elif self.is_longlong:
return abi.longlong_size
elif self.is_wchar:
return abi.wchar_size
elif self.is_bool:
return abi.bool_size
else:
assert False
else:
return self.size
@property
def is_fixed_size(self):
return not (self.is_pointer or self.is_size_integer or self.is_wchar or self.is_bool or
self.is_short or self.is_int or self.is_long or self.is_longlong)
@property
def is_integer(self):
return self.is_unsigned_integer or self.is_signed_integer
@property
def is_codeunit(self):
return self.is_char or self.is_wchar
@property
def primitive_type(self):
t = self
while t.is_pointer:
t = t.base
return t
@property
def as_ctypes_type(self):
import ctypes
if self.is_pointer:
if self.base is None:
return ctypes.c_void_p
else:
return ctypes.POINTER(self.base.as_ctypes_type)
else:
types_map = {
uint8_t: ctypes.c_uint8,
uint16_t: ctypes.c_uint16,
uint32_t: ctypes.c_uint32,
uint64_t: ctypes.c_uint64,
int8_t: ctypes.c_int8,
int16_t: ctypes.c_int16,
int32_t: ctypes.c_int32,
int64_t: ctypes.c_int64,
size_t: ctypes.c_size_t,
# Not exactly the same, but seems to match on all supported platforms
ptrdiff_t: ctypes.c_ssize_t,
char: ctypes.c_char,
signed_char: ctypes.c_byte,
unsigned_char: ctypes.c_ubyte,
signed_short: ctypes.c_short,
unsigned_short: ctypes.c_ushort,
signed_int: ctypes.c_int,
unsigned_int: ctypes.c_uint,
signed_long: ctypes.c_long,
unsigned_long: ctypes.c_ulong,
signed_long_long: ctypes.c_longlong,
unsigned_long_long: ctypes.c_ulonglong,
float_: ctypes.c_float,
double_: ctypes.c_double
}
ctype = types_map.get(self)
if ctype is None:
raise ValueError("Type %s has no analog in ctypes module" % str(self))
return ctype
# Fixed-width C types
uint8_t = Type("uint8_t", size=1, is_unsigned_integer=True, header="stdint.h")
uint16_t = Type("uint16_t", size=2, is_unsigned_integer=True, header="stdint.h")
uint32_t = Type("uint32_t", size=4, is_unsigned_integer=True, header="stdint.h")
uint64_t = Type("uint64_t", size=8, is_unsigned_integer=True, header="stdint.h")
uintptr_t = Type("uintptr_t", is_unsigned_integer=True, is_pointer_integer=True, header="stdint.h")
int8_t = Type("int8_t", size=1, is_signed_integer=True, header="stdint.h")
int16_t = Type("int16_t", size=2, is_signed_integer=True, header="stdint.h")
int32_t = Type("int32_t", size=4, is_signed_integer=True, header="stdint.h")
int64_t = Type("int64_t", size=8, is_signed_integer=True, header="stdint.h")
intptr_t = Type("intptr_t", is_signed_integer=True, is_pointer_integer=True, header="stdint.h")
size_t = Type("size_t", is_unsigned_integer=True, is_size_integer=True, header="stddef.h")
ptrdiff_t = Type("ptrdiff_t", is_signed_integer=True, is_size_integer=True, header="stddef.h")
Float16 = Type("_Float16", is_floating_point=True, size=2)
Float32 = Type("_Float32", is_floating_point=True, size=4)
Float64 = Type("_Float64", is_floating_point=True, size=8)
const_uint8_t = Type("uint8_t", size=1, is_const=True, is_unsigned_integer=True, header="stdint.h")
const_uint16_t = Type("uint16_t", size=2, is_const=True, is_unsigned_integer=True, header="stdint.h")
const_uint32_t = Type("uint32_t", size=4, is_const=True, is_unsigned_integer=True, header="stdint.h")
const_uint64_t = Type("uint64_t", size=8, is_const=True, is_unsigned_integer=True, header="stdint.h")
const_uintptr_t = Type("uintptr_t", is_const=True, is_unsigned_integer=True, is_pointer_integer=True, header="stdint.h")
const_int8_t = Type("int8_t", size=1, is_const=True, is_signed_integer=True, header="stdint.h")
const_int16_t = Type("int16_t", size=2, is_const=True, is_signed_integer=True, header="stdint.h")
const_int32_t = Type("int32_t", size=4, is_const=True, is_signed_integer=True, header="stdint.h")
const_int64_t = Type("int64_t", size=8, is_const=True, is_signed_integer=True, header="stdint.h")
const_intptr_t = Type("intptr_t", is_const=True, is_signed_integer=True, is_pointer_integer=True, header="stdint.h")
const_size_t = Type("size_t", is_const=True, is_unsigned_integer=True, is_size_integer=True, header="stddef.h")
const_ptrdiff_t = Type("ptrdiff_t", is_const=True, is_signed_integer=True, is_size_integer=True, header="stddef.h")
const_Float16 = Type("_Float16", is_const=True, is_floating_point=True, size=2)
const_Float32 = Type("_Float32", is_const=True, is_floating_point=True, size=4)
const_Float64 = Type("_Float64", is_const=True, is_floating_point=True, size=8)
# Yeppp! types
Yep8u = Type("Yep8u", size=1, is_unsigned_integer=True, header="yepTypes.h")
Yep16u = Type("Yep16u", size=2, is_unsigned_integer=True, header="yepTypes.h")
Yep32u = Type("Yep32u", size=4, is_unsigned_integer=True, header="yepTypes.h")
Yep64u = Type("Yep64u", size=8, is_unsigned_integer=True, header="yepTypes.h")
Yep8s = Type("Yep8s", size=1, is_signed_integer=True, header="yepTypes.h")
Yep16s = Type("Yep16s", size=2, is_signed_integer=True, header="yepTypes.h")
Yep32s = Type("Yep32s", size=4, is_signed_integer=True, header="yepTypes.h")
Yep64s = Type("Yep64s", size=8, is_signed_integer=True, header="yepTypes.h")
Yep16f = Type("Yep16f", size=2, is_floating_point=True, header="yepTypes.h")
Yep32f = Type("Yep32f", size=4, is_floating_point=True, header="yepTypes.h")
Yep64f = Type("Yep64f", size=8, is_floating_point=True, header="yepTypes.h")
YepSize = Type("YepSize", is_unsigned_integer=True, is_size_integer=True, header="yepTypes.h")
const_Yep8u = Type("Yep8u", size=1, is_const=True, is_unsigned_integer=True, header="yepTypes.h")
const_Yep16u = Type("Yep16u", size=2, is_const=True, is_unsigned_integer=True, header="yepTypes.h")
const_Yep32u = Type("Yep32u", size=4, is_const=True, is_unsigned_integer=True, header="yepTypes.h")
const_Yep64u = Type("Yep64u", size=8, is_const=True, is_unsigned_integer=True, header="yepTypes.h")
const_Yep8s = Type("Yep8s", size=1, is_const=True, is_signed_integer=True, header="yepTypes.h")
const_Yep16s = Type("Yep16s", size=2, is_const=True, is_signed_integer=True, header="yepTypes.h")
const_Yep32s = Type("Yep32s", size=4, is_const=True, is_signed_integer=True, header="yepTypes.h")
const_Yep64s = Type("Yep64s", size=8, is_const=True, is_signed_integer=True, header="yepTypes.h")
const_Yep16f = Type("Yep16f", size=2, is_const=True, is_floating_point=True, header="yepTypes.h")
const_Yep32f = Type("Yep32f", size=4, is_const=True, is_floating_point=True, header="yepTypes.h")
const_Yep64f = Type("Yep64f", size=8, is_const=True, is_floating_point=True, header="yepTypes.h")
const_YepSize = Type("YepSize", is_const=True, is_unsigned_integer=True, is_size_integer=True, header="yepTypes.h")
# Basic C types
char = Type("char", size=1, is_char=True)
wchar_t = Type("wchar_t", is_wchar=True)
signed_char = Type("signed char", size=1, is_signed_integer=True)
unsigned_char = Type("unsigned char", size=1, is_unsigned_integer=True)
signed_short = Type("short", is_signed_integer=True, is_short=True)
unsigned_short = Type("unsigned short", is_unsigned_integer=True, is_short=True)
signed_int = Type("int", is_signed_integer=True, is_int=True)
unsigned_int = Type("unsigned int", is_unsigned_integer=True, is_int=True)
signed_long = Type("long", is_signed_integer=True, is_long=True)
unsigned_long = Type("unsigned long", is_unsigned_integer=True, is_long=True)
signed_long_long = Type("long long", is_signed_integer=True, is_longlong=True)
unsigned_long_long = Type("unsigned long long", is_unsigned_integer=True, is_longlong=True)
float_ = Type("float", is_floating_point=True, size=4)
double_ = Type("double", is_floating_point=True, size=8)
const_char = Type("char", size=1, is_const=True, is_char=True)
const_wchar_t = Type("wchar_t", is_const=True, is_wchar=True)
const_signed_char = Type("signed char", size=1, is_const=True, is_signed_integer=True)
const_unsigned_char = Type("unsigned char", size=1, is_const=True, is_unsigned_integer=True)
const_signed_short = Type("short", is_const=True, is_signed_integer=True, is_short=True)
const_unsigned_short = Type("unsigned short", is_const=True, is_unsigned_integer=True, is_short=True)
const_signed_int = Type("int", is_const=True, is_signed_integer=True, is_int=True)
const_unsigned_int = Type("unsigned int", is_const=True, is_unsigned_integer=True, is_int=True)
const_signed_long = Type("long", is_const=True, is_signed_integer=True, is_long=True)
const_unsigned_long = Type("unsigned long", is_const=True, is_unsigned_integer=True, is_long=True)
const_signed_long_long = Type("long long", is_const=True, is_signed_integer=True, is_longlong=True)
const_unsigned_long_long = Type("unsigned long long", is_const=True, is_unsigned_integer=True, is_longlong=True)
const_float_ = Type("float", is_const=True, is_floating_point=True, size=4)
const_double_ = Type("double", is_const=True, is_floating_point=True, size=8)
def ptr(t=None):
if t is None or isinstance(t, Type):
return Type(base=t)
else:
raise TypeError("%s must be a type, e.g. uint32_t, size_t, or Yep64f" % type)
def const_ptr(t=None):
if t is None or isinstance(t, Type):
return Type(base=t, is_const=True)
else:
raise TypeError("%s must be a type, e.g. uint32_t, size_t, or Yep64f" % type)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
abi = None
target = None
debug_level = 0
package = None
assembly_format = "go"
generate_assembly = None
rtl_dump_file = None
name_mangling = "${Name}"
def get_debug_level():
from peachpy.common.function import active_function
if active_function is None:
return debug_level
else:
return active_function.debug_level
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import six
class Register(object):
"""A base class for all encodable registers (rip is not encodable)"""
_mask_size_map = {
0x1: 1,
0x2: 1,
0x3: 2,
0x7: 4,
0xF: 8,
0x10: 8,
0x40: 8,
0x100: 16,
0x300: 32,
0x700: 64
}
size = None
def __init__(self, mask, virtual_id=None, physical_id=None):
super(Register, self).__init__()
from peachpy.util import is_int
assert is_int(mask), \
"Mask must be an integer"
assert mask in Register._mask_size_map, \
"Unknown mask value: %X" % mask
self.mask = int(mask)
assert virtual_id is not None or physical_id is not None, \
"Virtual or physical ID must be specified"
assert virtual_id is None or is_int(virtual_id) and virtual_id > 0,\
"Virtual ID must be a positive integer"
assert physical_id is None or is_int(physical_id) and physical_id >= 0,\
"Physical ID must be a non-negative integer"
self.virtual_id = None if virtual_id is None else int(virtual_id)
self.physical_id = None if physical_id is None else int(physical_id)
def __eq__(self, other):
return isinstance(other, Register) and self.mask == other.mask and self._internal_id == other._internal_id
def __ne__(self, other):
return not isinstance(other, Register) or self.mask != other.mask or self._internal_id != other._internal_id
def __lt__(self, other):
return isinstance(other, Register) and (self.mask, -self._internal_id) < (other.mask, -other._internal_id)
def __le__(self, other):
return isinstance(other, Register) and (self.mask, -self._internal_id) <= (other.mask, -other._internal_id)
def __hash__(self):
h = hash(self.mask)
if self.physical_id is not None:
return hash(self.physical_id) ^ h
else:
return hash(self.virtual_id) ^ h
def __repr__(self):
return str(self)
@property
def _internal_id(self):
if self.is_virtual:
return -self.virtual_id
else:
return self.physical_id
@staticmethod
def _reconstruct(internal_id, mask):
registers = set()
if internal_id >= 0:
# Physical register
if mask & 0x400 != 0:
mask &= ~0x700
registers.add(ZMMRegister(physical_id=internal_id))
elif mask & 0x200 != 0:
mask &= ~0x300
registers.add(YMMRegister(physical_id=internal_id))
elif mask & 0x100 != 0:
mask &= ~0x100
registers.add(XMMRegister(physical_id=internal_id))
if mask & 0x10 != 0:
mask &= ~0x10
registers.add(MMXRegister(physical_id=internal_id))
if mask & 0x8 != 0:
mask &= ~0xF
registers.add(GeneralPurposeRegister64(physical_id=internal_id))
elif mask & 0x4 != 0:
mask &= ~0x7
registers.add(GeneralPurposeRegister32(physical_id=internal_id))
elif mask & 0x2 != 0:
mask &= ~0x3
registers.add(GeneralPurposeRegister16(physical_id=internal_id))
elif mask & 0x1 != 0:
mask &= ~0x1
registers.add(GeneralPurposeRegister8(physical_id=internal_id))
assert mask == 0, "Unknown register mask component: %X" % mask
else:
# Virtual register
# Physical register
if mask & 0x400 != 0:
mask &= ~0x700
registers.add(ZMMRegister(virtual_id=-internal_id))
elif mask & 0x200 != 0:
mask &= ~0x300
registers.add(YMMRegister(virtual_id=-internal_id))
elif mask & 0x100 != 0:
mask &= ~0x100
registers.add(XMMRegister(virtual_id=-internal_id))
if mask & 0x10 != 0:
mask &= ~0x10
registers.add(MMXRegister(virtual_id=-internal_id))
if mask & 0x40 != 0:
mask &= ~0x40
registers.add(KRegister(virtual_id=-internal_id))
if mask & 0x8 != 0:
mask &= ~0xF
registers.add(GeneralPurposeRegister64(virtual_id=-internal_id))
elif mask & 0x4 != 0:
mask &= ~0x7
registers.add(GeneralPurposeRegister32(virtual_id=-internal_id))
elif mask & 0x2 != 0:
mask &= ~0x3
registers.add(GeneralPurposeRegister16(virtual_id=-internal_id))
elif mask & 0x1 != 0:
mask &= ~0x1
registers.add(GeneralPurposeRegister8(virtual_id=-internal_id))
assert mask == 0, "Unknown register mask component: %X" % mask
return registers
@staticmethod
def _reconstruct_multiple(reg_dict):
reg_set = set()
for (reg_id, reg_mask) in six.iteritems(reg_dict):
reg_set.update(Register._reconstruct(reg_id, reg_mask))
return reg_set
@property
def kind(self):
if self.mask & GeneralPurposeRegister64._mask != 0:
return GeneralPurposeRegister._kind
elif self.mask & MMXRegister._mask != 0:
return MMXRegister._kind
elif self.mask & XMMRegister._mask != 0:
return XMMRegister._kind
elif self.mask & KRegister._mask != 0:
return KRegister._kind
else:
assert False, "Unknown register mask: %X" % self.mask
@property
def is_virtual(self):
"""Indicated if a register is virtual, i.e. not bounded to a physical register"""
return self.physical_id is None
@property
def lcode(self):
"""Returns the bits 0-2 of register encoding"""
assert self.physical_id is not None, \
"The method returns encoding detail for a physical register"
if self.mask == GeneralPurposeRegister8._high_mask:
assert self.physical_id & ~0x3 == 0, \
"Only ah, bh, ch, dh can be the high 8-bit registers"
return 0x4 | self.physical_id
else:
return self.physical_id & 0x7
@property
def hcode(self):
"""Returns the bit 3 of register encoding"""
assert self.physical_id is not None, \
"The method returns encoding detail for a physical register"
return (self.physical_id >> 3) & 1
@property
def ecode(self):
"""Returns the bit 4 of register encoding"""
assert self.physical_id is not None, \
"The method returns encoding detail for a physical register"
return (self.physical_id >> 4) & 1
@property
def hlcode(self):
"""Returns the bits 0-3 of register encoding"""
assert self.physical_id is not None, \
"The method returns encoding detail for a physical register"
assert self.mask != GeneralPurposeRegister8._high_mask, \
"ah/bh/ch/dh registers never use 4-bit encoding"
return self.physical_id & 0xF
@property
def ehcode(self):
"""Returns the bits 3-4 of register encoding"""
assert self.physical_id is not None, \
"The method returns encoding detail for a physical register"
return (self.physical_id >> 3) & 0b11
class GeneralPurposeRegister(Register):
"""A base class for general-purpose registers"""
_go_physical_id_map = {0x0: 'AX', 0x1: 'CX', 0x2: 'DX', 0x3: 'BX',
0x4: 'SP', 0x5: 'BP', 0x6: 'SI', 0x7: 'DI',
0x8: 'R8', 0x9: 'R9', 0xA: 'R10', 0xB: 'R11',
0xC: 'R12', 0xD: 'R13', 0xE: 'R14', 0xF: 'R15'}
_kind = 1
def __init__(self, mask, virtual_id=None, physical_id=None):
super(GeneralPurposeRegister, self).__init__(mask, virtual_id, physical_id)
@property
def as_low_byte(self):
return GeneralPurposeRegister8(self.physical_id, self.virtual_id)
@property
def as_word(self):
return GeneralPurposeRegister16(self.physical_id, self.virtual_id)
@property
def as_dword(self):
return GeneralPurposeRegister32(self.physical_id, self.virtual_id)
@property
def as_qword(self):
return GeneralPurposeRegister64(self.physical_id, self.virtual_id)
def format(self, assembly_format):
assert assembly_format in {"peachpy", "gas", "nasm", "go"}, \
"Supported assembly formats are 'peachpy', 'gas', 'nasm', 'go'"
if assembly_format == "go":
assert not self.is_virtual, \
"Go assembler does not support virtual registers"
return GeneralPurposeRegister._go_physical_id_map[self.physical_id]
elif assembly_format == "gas":
return "%" + str(self)
else:
return str(self)
class GeneralPurposeRegister64(GeneralPurposeRegister):
"""64-bit general-purpose register"""
size = 8
_physical_id_map = {0x0: 'rax', 0x1: 'rcx', 0x2: 'rdx', 0x3: 'rbx',
0x4: 'rsp', 0x5: 'rbp', 0x6: 'rsi', 0x7: 'rdi',
0x8: 'r8', 0x9: 'r9', 0xA: 'r10', 0xB: 'r11',
0xC: 'r12', 0xD: 'r13', 0xE: 'r14', 0xF: 'r15'}
_mask = 0xF
def __init__(self, physical_id=None, virtual_id=None):
if virtual_id is None and physical_id is None:
from peachpy.common.function import active_function
super(GeneralPurposeRegister64, self).__init__(GeneralPurposeRegister64._mask,
active_function._allocate_general_purpose_register_id())
else:
super(GeneralPurposeRegister64, self).__init__(GeneralPurposeRegister64._mask, virtual_id, physical_id)
def __str__(self):
if self.is_virtual:
return "gp64-vreg<%d>" % self.virtual_id
else:
return GeneralPurposeRegister64._physical_id_map[self.physical_id]
def __add__(self, offset):
from peachpy.x86_64.operand import MemoryAddress
return MemoryAddress(self) + offset
def __sub__(self, offset):
from peachpy.x86_64.operand import MemoryAddress
return MemoryAddress(self) - offset
def __mul__(self, scale):
from peachpy.x86_64.operand import MemoryAddress
from peachpy.util import is_int
if not is_int(scale):
raise TypeError("Register can be scaled only by an integer number")
if int(scale) not in {1, 2, 4, 8}:
raise ValueError("Invalid scale value (%d): only scaling by 1, 2, 4, or 8 is supported" % scale)
return MemoryAddress(index=self, scale=scale)
rax = GeneralPurposeRegister64(0)
rcx = GeneralPurposeRegister64(1)
rdx = GeneralPurposeRegister64(2)
rbx = GeneralPurposeRegister64(3)
rsp = GeneralPurposeRegister64(4)
rbp = GeneralPurposeRegister64(5)
rsi = GeneralPurposeRegister64(6)
rdi = GeneralPurposeRegister64(7)
r8 = GeneralPurposeRegister64(8)
r9 = GeneralPurposeRegister64(9)
r10 = GeneralPurposeRegister64(10)
r11 = GeneralPurposeRegister64(11)
r12 = GeneralPurposeRegister64(12)
r13 = GeneralPurposeRegister64(13)
r14 = GeneralPurposeRegister64(14)
r15 = GeneralPurposeRegister64(15)
class GeneralPurposeRegister32(GeneralPurposeRegister):
"""32-bit general-purpose register"""
size = 4
_physical_id_map = {0x0: 'eax', 0x1: 'ecx', 0x2: 'edx', 0x3: 'ebx',
0x4: 'esp', 0x5: 'ebp', 0x6: 'esi', 0x7: 'edi',
0x8: 'r8d', 0x9: 'r9d', 0xA: 'r10d', 0xB: 'r11d',
0xC: 'r12d', 0xD: 'r13d', 0xE: 'r14d', 0xF: 'r15d'}
_mask = 0x7
def __init__(self, physical_id=None, virtual_id=None):
if virtual_id is None and physical_id is None:
from peachpy.common.function import active_function
super(GeneralPurposeRegister32, self).__init__(GeneralPurposeRegister32._mask,
active_function._allocate_general_purpose_register_id())
else:
super(GeneralPurposeRegister32, self).__init__(GeneralPurposeRegister32._mask, virtual_id, physical_id)
def __str__(self):
if self.is_virtual:
return "gp32-vreg<%d>" % self.virtual_id
else:
return GeneralPurposeRegister32._physical_id_map[self.physical_id]
def __add__(self, offset):
from peachpy.x86_64.operand import MemoryAddress
return MemoryAddress(self) + offset
def __sub__(self, offset):
from peachpy.x86_64.operand import MemoryAddress
return MemoryAddress(self) - offset
def __mul__(self, scale):
from peachpy.x86_64.operand import MemoryAddress
from peachpy.util import is_int
if not is_int(scale):
raise TypeError("Register can be scaled only by an integer number")
if int(scale) not in {1, 2, 4, 8}:
raise ValueError("Invalid scale value (%d): only scaling by 1, 2, 4, or 8 is supported" % scale)
return MemoryAddress(index=self, scale=scale)
eax = GeneralPurposeRegister32(0)
ecx = GeneralPurposeRegister32(1)
edx = GeneralPurposeRegister32(2)
ebx = GeneralPurposeRegister32(3)
esp = GeneralPurposeRegister32(4)
ebp = GeneralPurposeRegister32(5)
esi = GeneralPurposeRegister32(6)
edi = GeneralPurposeRegister32(7)
r8d = GeneralPurposeRegister32(8)
r9d = GeneralPurposeRegister32(9)
r10d = GeneralPurposeRegister32(10)
r11d = GeneralPurposeRegister32(11)
r12d = GeneralPurposeRegister32(12)
r13d = GeneralPurposeRegister32(13)
r14d = GeneralPurposeRegister32(14)
r15d = GeneralPurposeRegister32(15)
class GeneralPurposeRegister16(GeneralPurposeRegister):
"""16-bit general-purpose register"""
size = 2
_physical_id_map = {0x0: 'ax', 0x1: 'cx', 0x2: 'dx', 0x3: 'bx',
0x4: 'sp', 0x5: 'bp', 0x6: 'si', 0x7: 'di',
0x8: 'r8w', 0x9: 'r9w', 0xA: 'r10w', 0xB: 'r11w',
0xC: 'r12w', 0xD: 'r13w', 0xE: 'r14w', 0xF: 'r15w'}
_mask = 0x3
def __init__(self, physical_id=None, virtual_id=None):
if virtual_id is None and physical_id is None:
from peachpy.common.function import active_function
super(GeneralPurposeRegister16, self).__init__(GeneralPurposeRegister16._mask,
active_function._allocate_general_purpose_register_id())
else:
super(GeneralPurposeRegister16, self).__init__(GeneralPurposeRegister16._mask, virtual_id, physical_id)
def __str__(self):
if self.is_virtual:
return "gp16-vreg<%d>" % self.virtual_id
else:
return GeneralPurposeRegister16._physical_id_map[self.physical_id]
ax = GeneralPurposeRegister16(0)
cx = GeneralPurposeRegister16(1)
dx = GeneralPurposeRegister16(2)
bx = GeneralPurposeRegister16(3)
sp = GeneralPurposeRegister16(4)
bp = GeneralPurposeRegister16(5)
si = GeneralPurposeRegister16(6)
di = GeneralPurposeRegister16(7)
r8w = GeneralPurposeRegister16(8)
r9w = GeneralPurposeRegister16(9)
r10w = GeneralPurposeRegister16(10)
r11w = GeneralPurposeRegister16(11)
r12w = GeneralPurposeRegister16(12)
r13w = GeneralPurposeRegister16(13)
r14w = GeneralPurposeRegister16(14)
r15w = GeneralPurposeRegister16(15)
class GeneralPurposeRegister8(GeneralPurposeRegister):
"""8-bit general-purpose register"""
size = 1
_physical_id_map = {(0x0, 0x1): 'al', (0x1, 0x1): 'cl', (0x2, 0x1): 'dl', (0x3, 0x1): 'bl',
(0x0, 0x2): 'ah', (0x1, 0x2): 'ch', (0x2, 0x2): 'dh', (0x3, 0x2): 'bh',
(0x4, 0x1): 'spl', (0x5, 0x1): 'bpl', (0x6, 0x1): 'sil', (0x7, 0x1): 'dil',
(0x8, 0x1): 'r8b', (0x9, 0x1): 'r9b', (0xA, 0x1): 'r10b', (0xB, 0x1): 'r11b',
(0xC, 0x1): 'r12b', (0xD, 0x1): 'r13b', (0xE, 0x1): 'r14b', (0xF, 0x1): 'r15b'}
_go_physical_id_map = {(0x0, 0x1): 'AX', (0x1, 0x1): 'CX', (0x2, 0x1): 'DX', (0x3, 0x1): 'BX',
(0x0, 0x2): 'AH', (0x1, 0x2): 'CH', (0x2, 0x2): 'DH', (0x3, 0x2): 'BH',
(0x4, 0x1): 'SP', (0x5, 0x1): 'BP', (0x6, 0x1): 'SI', (0x7, 0x1): 'DI',
(0x8, 0x1): 'R8', (0x9, 0x1): 'R9', (0xA, 0x1): 'R10', (0xB, 0x1): 'R11',
(0xC, 0x1): 'R12', (0xD, 0x1): 'R13', (0xE, 0x1): 'R14', (0xF, 0x1): 'R15'}
_mask = 0x1
_high_mask = 0x2
def __init__(self, physical_id=None, virtual_id=None, is_high=False):
mask = GeneralPurposeRegister8._high_mask if is_high else GeneralPurposeRegister8._mask
if virtual_id is None and physical_id is None:
from peachpy.common.function import active_function
super(GeneralPurposeRegister8, self).__init__(mask, active_function._allocate_general_purpose_register_id())
else:
super(GeneralPurposeRegister8, self).__init__(mask, virtual_id, physical_id)
def __str__(self):
if self.is_virtual:
return "gp8-vreg<%d>" % self.virtual_id
else:
return GeneralPurposeRegister8._physical_id_map[(self.physical_id, self.mask)]
def format(self, assembly_format):
assert assembly_format in {"peachpy", "gas", "nasm", "go"}, \
"Supported assembly formats are 'peachpy', 'gas', 'nasm', 'go'"
if assembly_format == "go":
assert not self.is_virtual, \
"Go assembler does not support virtual registers"
return GeneralPurposeRegister8._go_physical_id_map[(self.physical_id, self.mask)]
else:
return super(GeneralPurposeRegister8, self).format(assembly_format)
al = GeneralPurposeRegister8(0)
cl = GeneralPurposeRegister8(1)
dl = GeneralPurposeRegister8(2)
bl = GeneralPurposeRegister8(3)
ah = GeneralPurposeRegister8(0, is_high=True)
ch = GeneralPurposeRegister8(1, is_high=True)
dh = GeneralPurposeRegister8(2, is_high=True)
bh = GeneralPurposeRegister8(3, is_high=True)
spl = GeneralPurposeRegister8(4)
bpl = GeneralPurposeRegister8(5)
sil = GeneralPurposeRegister8(6)
dil = GeneralPurposeRegister8(7)
r8b = GeneralPurposeRegister8(8)
r9b = GeneralPurposeRegister8(9)
r10b = GeneralPurposeRegister8(10)
r11b = GeneralPurposeRegister8(11)
r12b = GeneralPurposeRegister8(12)
r13b = GeneralPurposeRegister8(13)
r14b = GeneralPurposeRegister8(14)
r15b = GeneralPurposeRegister8(15)
class MMXRegister(Register):
"""64-bit MMX technology register"""
size = 8
_physical_id_map = {n: "mm" + str(n) for n in range(8)}
_go_physical_id_map = {n: "M" + str(n) for n in range(8)}
_kind = 2
_mask = 0x10
def __init__(self, physical_id=None, virtual_id=None):
if virtual_id is None and physical_id is None:
from peachpy.common.function import active_function
super(MMXRegister, self).__init__(MMXRegister._mask,
active_function._allocate_mmx_register_id())
else:
super(MMXRegister, self).__init__(MMXRegister._mask, virtual_id, physical_id)
def __str__(self):
if self.is_virtual:
return "mm-vreg<%d>" % self.virtual_id
else:
return MMXRegister._physical_id_map[self.physical_id]
def format(self, assembly_format):
assert assembly_format in {"peachpy", "gas", "nasm", "go"}, \
"Supported assembly formats are 'peachpy', 'gas', 'nasm', 'go'"
if assembly_format == "go":
assert not self.is_virtual, \
"Go assembler does not support virtual registers"
return MMXRegister._go_physical_id_map[self.physical_id]
elif assembly_format == "gas":
return "%" + str(self)
else:
return str(self)
mm0 = MMXRegister(0)
mm1 = MMXRegister(1)
mm2 = MMXRegister(2)
mm3 = MMXRegister(3)
mm4 = MMXRegister(4)
mm5 = MMXRegister(5)
mm6 = MMXRegister(6)
mm7 = MMXRegister(7)
class XMMRegister(Register):
"""128-bit xmm (SSE) register"""
size = 16
_physical_id_map = {n: "xmm" + str(n) for n in range(32)}
_go_physical_id_map = {n: "X" + str(n) for n in range(16)}
_kind = 3
_mask = 0x100
def __init__(self, physical_id=None, virtual_id=None):
if virtual_id is None and physical_id is None:
from peachpy.common.function import active_function
super(XMMRegister, self).__init__(XMMRegister._mask,
active_function._allocate_xmm_register_id())
else:
super(XMMRegister, self).__init__(XMMRegister._mask, virtual_id, physical_id)
def __str__(self):
if self.is_virtual:
return "xmm-vreg<%d>" % self.virtual_id
else:
return XMMRegister._physical_id_map[self.physical_id]
def format(self, assembly_format):
assert assembly_format in {"peachpy", "gas", "nasm", "go"}, \
"Supported assembly formats are 'peachpy', 'gas', 'nasm', 'go'"
if assembly_format == "go":
assert not self.is_virtual, \
"Go assembler does not support virtual registers"
return XMMRegister._go_physical_id_map[self.physical_id]
elif assembly_format == "gas":
return "%" + str(self)
else:
return str(self)
@property
def as_xmm(self):
return XMMRegister(self.physical_id, self.virtual_id)
@property
def as_ymm(self):
return YMMRegister(self.physical_id, self.virtual_id)
@property
def as_zmm(self):
return ZMMRegister(self.physical_id, self.virtual_id)
@property
def code(self):
"""Returns 5-bit encoding of the register"""
assert self.physical_id is not None, \
"The method returns encoding detail for a physical register"
return self.physical_id
@property
def kcode(self):
"""Returns encoding of mask register"""
return 0
@property
def zcode(self):
"""Returns encoding of zeroing/merging flag of mask register"""
return 0
def __call__(self, mask):
if not isinstance(mask, (KRegister, RegisterMask)):
raise SyntaxError("xmm(mask) syntax requires mask to be a KRegister or KRegister.z")
return MaskedRegister(self, mask)
def __mul__(self, scale):
from peachpy.x86_64.operand import MemoryAddress
from peachpy.util import is_int
if not is_int(scale):
raise TypeError("Register can be scaled only by an integer number")
if int(scale) not in {1, 2, 4, 8}:
raise ValueError("Invalid scale value (%d): only scaling by 1, 2, 4, or 8 is supported" % scale)
return MemoryAddress(index=self, scale=scale)
xmm0 = XMMRegister(0)
xmm1 = XMMRegister(1)
xmm2 = XMMRegister(2)
xmm3 = XMMRegister(3)
xmm4 = XMMRegister(4)
xmm5 = XMMRegister(5)
xmm6 = XMMRegister(6)
xmm7 = XMMRegister(7)
xmm8 = XMMRegister(8)
xmm9 = XMMRegister(9)
xmm10 = XMMRegister(10)
xmm11 = XMMRegister(11)
xmm12 = XMMRegister(12)
xmm13 = XMMRegister(13)
xmm14 = XMMRegister(14)
xmm15 = XMMRegister(15)
xmm16 = XMMRegister(16)
xmm17 = XMMRegister(17)
xmm18 = XMMRegister(18)
xmm19 = XMMRegister(19)
xmm20 = XMMRegister(20)
xmm21 = XMMRegister(21)
xmm22 = XMMRegister(22)
xmm23 = XMMRegister(23)
xmm24 = XMMRegister(24)
xmm25 = XMMRegister(25)
xmm26 = XMMRegister(26)
xmm27 = XMMRegister(27)
xmm28 = XMMRegister(28)
xmm29 = XMMRegister(29)
xmm30 = XMMRegister(30)
xmm31 = XMMRegister(31)
class YMMRegister(Register):
"""256-bit ymm (AVX) register"""
size = 32
_physical_id_map = {n: "ymm" + str(n) for n in range(32)}
_kind = 3
_mask = 0x300
def __init__(self, physical_id=None, virtual_id=None):
if virtual_id is None and physical_id is None:
from peachpy.common.function import active_function
super(YMMRegister, self).__init__(YMMRegister._mask,
active_function._allocate_xmm_register_id())
else:
super(YMMRegister, self).__init__(YMMRegister._mask, virtual_id, physical_id)
def __str__(self):
if self.is_virtual:
return "ymm-vreg<%d>" % self.virtual_id
else:
return YMMRegister._physical_id_map[self.physical_id]
def format(self, assembly_format):
assert assembly_format in {"peachpy", "gas", "nasm", "go"}, \
"Supported assembly formats are 'peachpy', 'gas', 'nasm', 'go'"
if assembly_format == "go":
assert not self.is_virtual, \
"Go assembler does not support virtual registers"
return XMMRegister._go_physical_id_map[self.physical_id]
elif assembly_format == "gas":
return "%" + str(self)
else:
return str(self)
@property
def as_xmm(self):
return XMMRegister(self.physical_id, self.virtual_id)
@property
def as_ymm(self):
return YMMRegister(self.physical_id, self.virtual_id)
@property
def as_zmm(self):
return ZMMRegister(self.physical_id, self.virtual_id)
@property
def code(self):
"""Returns 5-bit encoding of the register"""
assert self.physical_id is not None, \
"The method returns encoding detail for a physical register"
return self.physical_id
@property
def kcode(self):
"""Returns encoding of mask register"""
return 0
@property
def zcode(self):
"""Returns encoding of zeroing/merging flag of mask register"""
return 0
def __call__(self, mask):
if not isinstance(mask, (KRegister, RegisterMask)):
raise SyntaxError("ymm(mask) syntax requires mask to be a KRegister or KRegister.z")
return MaskedRegister(self, mask)
def __mul__(self, scale):
from peachpy.x86_64.operand import MemoryAddress
from peachpy.util import is_int
if not is_int(scale):
raise TypeError("Register can be scaled only by an integer number")
if int(scale) not in {1, 2, 4, 8}:
raise ValueError("Invalid scale value (%d): only scaling by 1, 2, 4, or 8 is supported" % scale)
return MemoryAddress(index=self, scale=scale)
ymm0 = YMMRegister(0)
ymm1 = YMMRegister(1)
ymm2 = YMMRegister(2)
ymm3 = YMMRegister(3)
ymm4 = YMMRegister(4)
ymm5 = YMMRegister(5)
ymm6 = YMMRegister(6)
ymm7 = YMMRegister(7)
ymm8 = YMMRegister(8)
ymm9 = YMMRegister(9)
ymm10 = YMMRegister(10)
ymm11 = YMMRegister(11)
ymm12 = YMMRegister(12)
ymm13 = YMMRegister(13)
ymm14 = YMMRegister(14)
ymm15 = YMMRegister(15)
ymm16 = YMMRegister(16)
ymm17 = YMMRegister(17)
ymm18 = YMMRegister(18)
ymm19 = YMMRegister(19)
ymm20 = YMMRegister(20)
ymm21 = YMMRegister(21)
ymm22 = YMMRegister(22)
ymm23 = YMMRegister(23)
ymm24 = YMMRegister(24)
ymm25 = YMMRegister(25)
ymm26 = YMMRegister(26)
ymm27 = YMMRegister(27)
ymm28 = YMMRegister(28)
ymm29 = YMMRegister(29)
ymm30 = YMMRegister(30)
ymm31 = YMMRegister(31)
class ZMMRegister(Register):
"""512-bit zmm (AVX-512) register"""
size = 64
_physical_id_map = {n: "zmm" + str(n) for n in range(32)}
_kind = 3
_mask = 0x700
def __init__(self, physical_id=None, virtual_id=None):
if virtual_id is None and physical_id is None:
from peachpy.common.function import active_function
super(ZMMRegister, self).__init__(ZMMRegister._mask,
active_function._allocate_xmm_register_id())
else:
super(ZMMRegister, self).__init__(ZMMRegister._mask, virtual_id, physical_id)
def __str__(self):
if self.is_virtual:
return "zmm-vreg<%d>" % self.virtual_id
else:
return ZMMRegister._physical_id_map[self.physical_id]
@property
def as_xmm(self):
return XMMRegister(self.physical_id, self.virtual_id)
@property
def as_ymm(self):
return YMMRegister(self.physical_id, self.virtual_id)
@property
def as_zmm(self):
return ZMMRegister(self.physical_id, self.virtual_id)
@property
def code(self):
"""Returns 5-bit encoding of the register"""
assert self.physical_id is not None, \
"The method returns encoding detail for a physical register"
return self.physical_id
@property
def kcode(self):
"""Returns encoding of mask register"""
return 0
@property
def zcode(self):
"""Returns encoding of zeroing/merging flag of mask register"""
return 0
def __call__(self, mask):
if not isinstance(mask, (KRegister, RegisterMask)):
raise SyntaxError("zmm(mask) syntax requires mask to be a KRegister or KRegister.z")
return MaskedRegister(self, mask)
def __mul__(self, scale):
from peachpy.x86_64.operand import MemoryAddress
from peachpy.util import is_int
if not is_int(scale):
raise TypeError("Register can be scaled only by an integer number")
if int(scale) not in {1, 2, 4, 8}:
raise ValueError("Invalid scale value (%d): only scaling by 1, 2, 4, or 8 is supported" % scale)
return MemoryAddress(index=self, scale=scale)
zmm0 = ZMMRegister(0)
zmm1 = ZMMRegister(1)
zmm2 = ZMMRegister(2)
zmm3 = ZMMRegister(3)
zmm4 = ZMMRegister(4)
zmm5 = ZMMRegister(5)
zmm6 = ZMMRegister(6)
zmm7 = ZMMRegister(7)
zmm8 = ZMMRegister(8)
zmm9 = ZMMRegister(9)
zmm10 = ZMMRegister(10)
zmm11 = ZMMRegister(11)
zmm12 = ZMMRegister(12)
zmm13 = ZMMRegister(13)
zmm14 = ZMMRegister(14)
zmm15 = ZMMRegister(15)
zmm16 = ZMMRegister(16)
zmm17 = ZMMRegister(17)
zmm18 = ZMMRegister(18)
zmm19 = ZMMRegister(19)
zmm20 = ZMMRegister(20)
zmm21 = ZMMRegister(21)
zmm22 = ZMMRegister(22)
zmm23 = ZMMRegister(23)
zmm24 = ZMMRegister(24)
zmm25 = ZMMRegister(25)
zmm26 = ZMMRegister(26)
zmm27 = ZMMRegister(27)
zmm28 = ZMMRegister(28)
zmm29 = ZMMRegister(29)
zmm30 = ZMMRegister(30)
zmm31 = ZMMRegister(31)
class KRegister(Register):
"""AVX-512 mask register"""
size = 8
_physical_id_map = {n: "k" + str(n) for n in range(8)}
_kind = 4
_mask = 0x40
def __init__(self, physical_id=None, virtual_id=None):
if virtual_id is None and physical_id is None:
from peachpy.common.function import active_function
super(KRegister, self).__init__(KRegister._mask,
active_function._allocate_mask_register_id())
else:
super(KRegister, self).__init__(KRegister._mask, virtual_id, physical_id)
def __str__(self):
if self.is_virtual:
return "k-vreg<%d>" % self.virtual_id
else:
return KRegister._physical_id_map[self.physical_id]
@property
def z(self):
return RegisterMask(self, is_zeroing=True)
@property
def kcode(self):
"""Returns the register encoding"""
assert self.physical_id is not None, \
"The method returns encoding detail for a physical register"
return self.physical_id
@property
def zcode(self):
"""Returns encoding of the merge/zero flags"""
return 0
def __call__(self, mask):
if not isinstance(mask, KRegister):
raise SyntaxError("k(mask) syntax requires mask to be a KRegister")
return MaskedRegister(self, mask)
class RegisterMask:
def __init__(self, mask_register, is_zeroing=False):
self.mask_register = mask_register
self.is_zeroing = is_zeroing
@property
def kcode(self):
"""Returns encoding of the mask register"""
return self.mask_register.kcode
@property
def zcode(self):
"""Returns encoding of the merge/zero flags"""
return int(self.is_zeroing)
k0 = KRegister(0)
k1 = KRegister(1)
k2 = KRegister(2)
k3 = KRegister(3)
k4 = KRegister(4)
k5 = KRegister(5)
k6 = KRegister(6)
k7 = KRegister(7)
class MaskedRegister:
def __init__(self, register, mask):
assert isinstance(register, (XMMRegister, YMMRegister, ZMMRegister, KRegister))
assert isinstance(mask, (KRegister, RegisterMask))
self.register = register
if isinstance(mask, KRegister):
self.mask = RegisterMask(mask)
else:
self.mask = mask
@property
def code(self):
"""Returns the 5-bit register encoding"""
return self.register.code
@property
def lcode(self):
"""Returns the bits 0-2 of register encoding"""
return self.register.lcode
@property
def hcode(self):
"""Returns the bit 3 of register encoding"""
return self.register.hcode
@property
def ecode(self):
"""Returns the bit 4 of register encoding"""
return self.register.ecode
@property
def hlcode(self):
"""Returns the bits 0-3 of register encoding"""
return self.register.hlcode
@property
def ehcode(self):
"""Returns the bits 3-4 of register encoding"""
return self.register.ehcode
@property
def kcode(self):
"""Returns encoding of mask register"""
return self.mask.kcode
@property
def zcode(self):
"""Returns encoding of zeroing/merging flag of mask register"""
return self.mask.zcode
def __mul__(self, scale):
from peachpy.x86_64.operand import MemoryAddress
from peachpy.util import is_int
if not is_int(scale):
raise TypeError("Register can be scaled only by an integer number")
if int(scale) not in {1, 2, 4, 8}:
raise ValueError("Invalid scale value (%d): only scaling by 1, 2, 4, or 8 is supported" % scale)
return MemoryAddress(index=self, scale=scale)
class RIPRegister:
def __init__(self):
pass
def __str__(self):
return "rip"
def __add__(self, offset):
from peachpy.x86_64.operand import RIPRelativeOffset
return RIPRelativeOffset(offset)
def __sub__(self, offset):
from peachpy.x86_64.operand import RIPRelativeOffset
return RIPRelativeOffset(-offset)
rip = RIPRegister()
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
def optional_rex(r, rm, force_rex=False):
assert r in {0, 1}, "REX.R must be 0 or 1"
from peachpy.x86_64.operand import MemoryAddress, RIPRelativeOffset
from peachpy.x86_64.registers import Register
assert isinstance(rm, (Register, MemoryAddress, RIPRelativeOffset)), \
"rm is expected to be a register or a memory address"
b = 0
x = 0
if isinstance(rm, Register):
b = rm.hcode
elif isinstance(rm, MemoryAddress):
if rm.base is not None:
b = rm.base.hcode
if rm.index is not None:
x = rm.index.hcode
# If REX.R, REX.X, and REX.B are all zeroes, REX prefix can be omitted
if (r | x | b) == 0 and not force_rex:
return bytearray()
else:
return bytearray([0x40 | (r << 2) | (x << 1) | b])
def rex(w, r, rm):
assert w in {0, 1}, "REX.W must be 0 or 1"
assert r in {0, 1}, "REX.R must be 0 or 1"
from peachpy.x86_64.operand import MemoryAddress, RIPRelativeOffset
assert isinstance(rm, (MemoryAddress, RIPRelativeOffset)), \
"rm is expected to be a memory address"
b = 0
x = 0
if isinstance(rm, MemoryAddress):
if rm.base is not None:
b = rm.base.hcode
if rm.index is not None:
x = rm.index.hcode
return bytearray([0x40 | (w << 3) | (r << 2) | (x << 1) | b])
def vex2(lpp, r, rm, vvvv=0, force_vex3=False):
# 2-byte VEX prefix:
# Requires: VEX.W = 0, VEX.mmmmm = 0b00001 and VEX.B = VEX.X = 0
# +----------------+
# Byte 0: | Bits 0-7: 0xC5 |
# +----------------+
#
# +-----------+----------------+----------+--------------+
# Byte 1: | Bit 7: ~R | Bits 3-6 ~vvvv | Bit 2: L | Bits 0-1: pp |
# +-----------+----------------+----------+--------------+
#
#
# 3-byte VEX prefix:
# +----------------+
# Byte 0: | Bits 0-7: 0xC4 |
# +----------------+
#
# +-----------+-----------+-----------+-------------------+
# Byte 1: | Bit 7: ~R | Bit 6: ~X | Bit 5: ~B | Bits 0-4: 0b00001 |
# +-----------+-----------+-----------+-------------------+
#
# +----------+-----------------+----------+--------------+
# Byte 2: | Bit 7: 0 | Bits 3-6: ~vvvv | Bit 2: L | Bits 0-1: pp |
# +----------+-----------------+----------+--------------+
assert lpp & ~0b111 == 0, "VEX.Lpp must be a 3-bit mask"
assert r & ~0b1 == 0, "VEX.R must be a single-bit mask"
assert vvvv & ~0b1111 == 0, "VEX.vvvv must be a 4-bit mask"
from peachpy.x86_64.operand import MemoryAddress, RIPRelativeOffset
from peachpy.x86_64.registers import Register
assert rm is None or isinstance(rm, (Register, MemoryAddress, RIPRelativeOffset)), \
"rm is expected to be a register, a memory address, a rip-relative offset, or None"
b = 0
x = 0
if rm is not None:
if isinstance(rm, Register):
b = rm.hcode
elif isinstance(rm, MemoryAddress):
if rm.base is not None:
b = rm.base.hcode
if rm.index is not None:
x = rm.index.hcode
# If VEX.B and VEX.X are zeroes, 2-byte VEX prefix can be used
if (x | b) == 0 and not force_vex3:
return bytearray([0xC5, 0xF8 ^ (r << 7) ^ (vvvv << 3) ^ lpp])
else:
return bytearray([0xC4, 0xE1 ^ (r << 7) ^ (x << 6) ^ (b << 5), 0x78 ^ (vvvv << 3) ^ lpp])
def vex3(escape, mmmmm, w____lpp, r, rm, vvvv=0):
# 3-byte VEX/XOP prefix
# +-----------------------------------+
# Byte 0: | Bits 0-7: 0xC4 (VEX) / 0x8F (XOP) |
# +-----------------------------------+
#
# +-----------+-----------+-----------+-----------------+
# Byte 1: | Bit 7: ~R | Bit 6: ~X | Bit 5: ~B | Bits 0-4: mmmmm |
# +-----------+-----------+-----------+-----------------+
#
# +----------+-----------------+----------+--------------+
# Byte 2: | Bit 7: W | Bits 3-6: ~vvvv | Bit 2: L | Bits 0-1: pp |
# +----------+-----------------+----------+--------------+
assert escape in {0xC4, 0x8F}, "escape must be a 3-byte VEX (0xC4) or XOP (0x8F) prefix"
assert w____lpp & ~0b10000111 == 0, "VEX.W____Lpp is expected to have no bits set except 0, 1, 2 and 7"
assert mmmmm & ~0b11111 == 0, "VEX.m-mmmm is expected to be a 5-bit mask"
assert r & ~0b1 == 0, "VEX.R must be a single-bit mask"
assert vvvv & ~0b1111 == 0, "VEX.vvvv must be a 4-bit mask"
from peachpy.x86_64.operand import MemoryAddress, RIPRelativeOffset
assert isinstance(rm, (MemoryAddress, RIPRelativeOffset)), \
"rm is expected to be a memory address or a rip-relative offset"
b = 0
x = 0
if isinstance(rm, MemoryAddress):
if rm.base is not None:
b = rm.base.hcode
if rm.index is not None:
x = rm.index.hcode
return bytearray([escape, 0xE0 ^ (r << 7) ^ (x << 6) ^ (b << 5) ^ mmmmm, 0x78 ^ (vvvv << 3) ^ w____lpp])
def evex(mm, w____1pp, ll, rr, rm, Vvvvv=0, aaa=0, z=0, b=0):
assert mm & ~0b11 == 0, "EVEX.mm must be a 2-bit mask"
assert w____1pp & ~0b10000011 == 0b100, "EVEX.W____1pp is expected to have no bits set except 0, 1, 2, and 7"
assert ll & ~0b11 == 0, "EVEX.L'L must be a 2-bit mask"
assert rr & ~0b11 == 0, "EVEX.R'R must be a 2-bit mask"
assert Vvvvv & ~0b11111 == 0, "EVEX.v'vvvv must be a 5-bit mask"
assert aaa & ~0b111 == 0, "EVEX.aaa must be a 3-bit mask"
assert z & ~0b1 == 0, "EVEX.z must be a single-bit mask"
from peachpy.x86_64.operand import MemoryAddress, RIPRelativeOffset
from peachpy.x86_64.registers import Register, XMMRegister, YMMRegister, ZMMRegister
assert rm is None or isinstance(rm, (Register, MemoryAddress, RIPRelativeOffset)), \
"rm is expected to be a register, a memory address, or None"
r_, r = rr >> 1, rr & 1
v_, vvvv = Vvvvv >> 4, Vvvvv & 0b1111
b_ = 0
x = 0
if rm is not None:
if isinstance(rm, Register):
b_ = rm.hcode
x = rm.ecode
elif isinstance(rm, MemoryAddress):
if rm.base is not None:
b_ = rm.base.hcode
if rm.index is not None:
x = rm.index.hcode
if isinstance(rm.index, (XMMRegister, YMMRegister, ZMMRegister)):
v_ = rm.index.ecode
p0 = (r << 7) | (x << 6) | (b_ << 5) | (r_ << 4) | mm
p1 = w____1pp | (vvvv << 3)
p2 = (z << 7) | (ll << 5) | (b << 4) | (v_ << 3) | aaa
# p0: invert RXBR' (bits 4-7)
# p1: invert vvvv (bits 3-6)
# p2: invert V' (bit 3)
return bytearray([0x62, p0 ^ 0xF0, p1 ^ 0x78, p2 ^ 0x08])
def modrm_sib_disp(reg, rm, force_sib=False, min_disp=0, disp8xN=None):
from peachpy.x86_64.operand import MemoryAddress, RIPRelativeOffset
from peachpy.x86_64.registers import rsp, rbp, r13
from peachpy.util import is_int, is_sint8, ilog2
assert is_int(reg) and 0 <= reg <= 7, \
"Constant reg value expected, got " + str(reg)
assert isinstance(rm, (MemoryAddress, RIPRelativeOffset))
if disp8xN is None:
disp8xN = 1
assert disp8xN in [1, 2, 4, 8, 16, 32, 64]
# ModR/M byte
# +----------------+---------------+--------------+
# | Bits 6-7: mode | Bits 3-5: reg | Bits 0-2: rm |
# +----------------+---------------+--------------+
#
# SIB byte
# +-----------------+-----------------+----------------+
# | Bits 6-7: scale | Bits 3-5: index | Bits 0-2: base |
# +-----------------+-----------------+----------------+
if isinstance(rm, MemoryAddress):
# TODO: support global addresses, including rip-relative addresses
assert rm.base is not None or rm.index is not None, \
"Global addressing is not yet supported"
if not force_sib and rm.index is None and rm.base.lcode != 0b100:
# No SIB byte
if rm.displacement == 0 and rm.base != rbp and rm.base != r13 and min_disp <= 0:
# ModRM.mode = 0 (no displacement)
assert rm.base.lcode != 0b100, \
"rsp/r12 are not encodable as a base register (interpreted as SIB indicator)"
assert rm.base.lcode != 0b101, \
"rbp/r13 is not encodable as a base register (interpreted as disp32 address)"
return bytearray([(reg << 3) | rm.base.lcode])
elif (rm.displacement % disp8xN == 0) and is_sint8(rm.displacement // disp8xN) and min_disp <= 1:
# ModRM.mode = 1 (8-bit displacement)
assert rm.base.lcode != 0b100, \
"rsp/r12 are not encodable as a base register (interpreted as SIB indicator)"
return bytearray([0x40 | (reg << 3) | rm.base.lcode, (rm.displacement // disp8xN) & 0xFF])
else:
# ModRM.mode == 2 (32-bit displacement)
assert rm.base.lcode != 0b100, \
"rsp/r12 are not encodable as a base register (interpreted as SIB indicator)"
return bytearray([0x80 | (reg << 3) | rm.base.lcode,
rm.displacement & 0xFF, (rm.displacement >> 8) & 0xFF,
(rm.displacement >> 16) & 0xFF, (rm.displacement >> 24) & 0xFF])
else:
# All encodings below use ModRM.rm = 4 (0b100) to indicate the presence of SIB
assert rsp != rm.index, "rsp is not encodable as an index register (interpreted as no index)"
# Index = 4 (0b100) denotes no-index encoding
index = 0x4 if rm.index is None else rm.index.lcode
scale = 0 if rm.scale is None else ilog2(rm.scale)
if rm.base is None:
# SIB.base = 5 (0b101) and ModRM.mode = 0 indicates no-base encoding with disp32
return bytearray([(reg << 3) | 0x4, (scale << 6) | (index << 3) | 0x5,
rm.displacement & 0xFF, (rm.displacement >> 8) & 0xFF,
(rm.displacement >> 16) & 0xFF, (rm.displacement >> 24) & 0xFF])
else:
if rm.displacement == 0 and rm.base.lcode != 0b101 and min_disp <= 0:
# ModRM.mode == 0 (no displacement)
assert rm.base.lcode != 0b101, \
"rbp/r13 is not encodable as a base register (interpreted as disp32 address)"
return bytearray([(reg << 3) | 0x4, (scale << 6) | (index << 3) | rm.base.lcode])
elif (rm.displacement % disp8xN == 0) and is_sint8(rm.displacement // disp8xN) and min_disp <= 1:
# ModRM.mode == 1 (8-bit displacement)
return bytearray([(reg << 3) | 0x44, (scale << 6) | (index << 3) | rm.base.lcode,
(rm.displacement // disp8xN) & 0xFF])
else:
# ModRM.mode == 2 (32-bit displacement)
return bytearray([(reg << 3) | 0x84, (scale << 6) | (index << 3) | rm.base.lcode,
rm.displacement & 0xFF, (rm.displacement >> 8) & 0xFF,
(rm.displacement >> 16) & 0xFF, (rm.displacement >> 24) & 0xFF])
elif isinstance(rm, RIPRelativeOffset):
# ModRM.mode == 0 and ModeRM.rm == 5 (0b101) indicates (rip + disp32) addressing
return bytearray([0b00000101 | (reg << 3),
rm.offset & 0xFF, (rm.offset >> 8) & 0xFF,
(rm.offset >> 16) & 0xFF, (rm.offset >> 24) & 0xFF])
def nop(length):
assert 1 <= length <= 15
# Note: the generated NOPs must be allowed by NaCl validator, see
# https://src.chromium.org/viewvc/native_client/trunk/src/native_client/src/trusted/validator_ragel/instruction_definitions/general_purpose_instructions.def
# https://src.chromium.org/viewvc/native_client/trunk/src/native_client/src/trusted/validator_ragel/instruction_definitions/nops.def
return {
1: bytearray([0x90]),
2: bytearray([0x40, 0x90]),
3: bytearray([0x0F, 0x1F, 0x00]),
4: bytearray([0x0F, 0x1F, 0x40, 0x00]),
5: bytearray([0x0F, 0x1F, 0x44, 0x00, 0x00]),
6: bytearray([0x66, 0x0F, 0x1F, 0x44, 0x00, 0x00]),
7: bytearray([0x0F, 0x1F, 0x80, 0x00, 0x00, 0x00, 0x00]),
8: bytearray([0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00]),
9: bytearray([0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00]),
10: bytearray([0x66, 0x2E, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00]),
11: bytearray([0x66, 0x66, 0x2E, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00]),
12: bytearray([0x66, 0x66, 0x66, 0x2E, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00]),
13: bytearray([0x66, 0x66, 0x66, 0x66, 0x2E, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00]),
14: bytearray([0x66, 0x66, 0x66, 0x66, 0x66, 0x2E, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00]),
15: bytearray([0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x2E, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00])
}[length]
class Flags:
AccumulatorOp0 = 0x01
AccumulatorOp1 = 0x02
Rel8Label = 0x04
Rel32Label = 0x08
ModRMSIBDisp = 0x10
OptionalREX = 0x20
VEX2 = 0x40
class Options:
Disp8 = 0x01
Disp32 = 0x02
SIB = 0x04
REX = 0x08
VEX3 = 0x10 |
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
def check_operand(operand):
"""Validates operand object as an instruction operand and converts it to a standard form"""
from peachpy.x86_64.registers import Register, MaskedRegister
from peachpy.x86_64.pseudo import Label
from peachpy.x86_64.function import LocalVariable
from peachpy.literal import Constant
from peachpy import Argument
from peachpy.util import is_int, is_int64
from copy import copy, deepcopy
if isinstance(operand, Register):
return copy(operand)
elif isinstance(operand, (MaskedRegister, MemoryOperand)):
return deepcopy(operand)
elif isinstance(operand, (Argument, RIPRelativeOffset, Label)):
return operand
elif is_int(operand):
if not is_int64(operand):
raise ValueError("The immediate operand %d is not representable as a 64-bit value")
return operand
elif isinstance(operand, list):
if len(operand) != 1:
raise ValueError("Memory operands must be represented by a list with only one element")
return MemoryOperand(operand[0])
elif isinstance(operand, Constant):
from copy import copy, deepcopy
operand = copy(operand)
import peachpy.common.function
if peachpy.common.function.active_function:
operand.name = deepcopy(operand.name, peachpy.common.function.active_function._names_memo)
return MemoryOperand(operand)
elif isinstance(operand, LocalVariable):
return MemoryOperand(operand)
elif isinstance(operand, set):
if len(operand) != 1:
raise ValueError("Rounding control & suppress-all-errors operands must be represented by a set "
"with only one element")
return next(iter(operand))
else:
raise TypeError("Unsupported operand: %s" % str(operand))
def get_operand_registers(operand):
"""Returns a set of registers that comprise the operand"""
from peachpy.x86_64.registers import Register, MaskedRegister
if isinstance(operand, Register):
return [operand]
elif isinstance(operand, MaskedRegister):
return [operand.register, operand.mask.mask_register]
elif isinstance(operand, MemoryOperand) and isinstance(operand.address, MemoryAddress):
registers = list()
if operand.address.base is not None:
registers.append(operand.address.base)
if operand.address.index is not None:
registers.append(operand.address.index)
return registers
else:
return list()
def format_operand(operand, assembly_format):
assert assembly_format in {"peachpy", "gas", "nasm", "go"}, \
"Supported assembly formats are 'peachpy', 'gas', 'nasm', 'go'"
immediate_prefix_map = {
"peachpy": "",
"gas": "$",
"nasm": "",
"go": "$"
}
from peachpy.util import is_int64
if is_int64(operand):
return immediate_prefix_map[assembly_format] + str(operand)
else:
return operand.format(assembly_format)
def format_operand_type(operand):
"""Returns string representation of the operand type in assembly language"""
from peachpy.x86_64.registers import GeneralPurposeRegister64, GeneralPurposeRegister32, GeneralPurposeRegister16,\
GeneralPurposeRegister8, MMXRegister, XMMRegister, YMMRegister, ZMMRegister, MaskedRegister, \
al, ax, eax, rax, cl, xmm0
from peachpy.x86_64.pseudo import Label
from peachpy.util import is_int64, is_int32, is_int16, is_int8
if is_int8(operand):
return "imm8"
elif is_int16(operand):
return "imm16"
elif is_int32(operand):
return "imm32"
elif is_int64(operand):
return "imm64"
elif al == operand:
return "al"
elif ax == operand:
return "ax"
elif eax == operand:
return "eax"
elif rax == operand:
return "rax"
elif cl == operand:
return "cl"
elif xmm0 == operand:
return "xmm0"
elif isinstance(operand, GeneralPurposeRegister64):
return "r64"
elif isinstance(operand, GeneralPurposeRegister32):
return "r32"
elif isinstance(operand, GeneralPurposeRegister16):
return "r16"
elif isinstance(operand, GeneralPurposeRegister8):
return "r8"
elif isinstance(operand, MMXRegister):
return "mm"
elif isinstance(operand, XMMRegister):
return "xmm"
elif isinstance(operand, YMMRegister):
return "ymm"
elif isinstance(operand, ZMMRegister):
return "zmm"
elif isinstance(operand, MaskedRegister):
if operand.mask.is_zeroing:
return format_operand_type(operand.register) + "{k}{z}"
else:
return format_operand_type(operand.register) + "{k}"
elif isinstance(operand, MemoryOperand):
if operand.size is None:
return "m"
else:
if operand.mask is None:
return "m" + str(operand.size * 8)
elif operand.mask.is_zeroing:
return "m" + str(operand.size * 8) + "{k}{z}"
else:
return "m" + str(operand.size * 8) + "{k}"
elif isinstance(operand, RoundingControl):
return "{er}"
elif isinstance(operand, SuppressAllExceptions):
return "{sae}"
elif isinstance(operand, Label):
return "rel"
else:
return operand.__class__.__name__
class MemoryAddress:
"""An address expression involving a register, e.g. rax - 10, r8d * 4."""
def __init__(self, base=None, index=None, scale=None, displacement=0):
from peachpy.x86_64.registers import GeneralPurposeRegister64, \
XMMRegister, YMMRegister, ZMMRegister, MaskedRegister
from peachpy.util import is_int, is_sint32
# Check individual arguments
if base is not None and not isinstance(base, GeneralPurposeRegister64):
raise TypeError("Base register must be a 64-bit general-purpose register")
if index is not None and \
not isinstance(index, (GeneralPurposeRegister64, XMMRegister, YMMRegister, ZMMRegister)) and not \
(isinstance(index, MaskedRegister) and
isinstance(index.register, (XMMRegister, YMMRegister, ZMMRegister)) and
not index.mask.is_zeroing):
raise TypeError("Index register must be a 64-bit general-purpose register or an XMM/YMM/ZMM register")
if scale is not None and not is_int(scale):
raise TypeError("Scale must be an integer")
if scale is not None and int(scale) not in {1, 2, 4, 8}:
raise TypeError("Scale must be 1, 2, 4, or 8")
if not is_sint32(displacement):
raise ValueError("Displacement value (%s) is not representable as a signed 32-bit integer" %
str(displacement))
# Check relations of arguments
if scale is not None and index is None or scale is None and index is not None:
raise ValueError("Either both of neither of scale and index must be defined")
if index is None and base is None:
raise ValueError("Either base or index * scale must be specified")
self.base = base
self.index = index
self.scale = None if scale is None else int(scale)
self.displacement = int(displacement)
def __add__(self, addend):
from peachpy.x86_64.registers import GeneralPurposeRegister64
from peachpy.util import is_int, is_sint32
if is_int(addend):
if not is_sint32(addend):
raise ValueError("The addend value (%d) is not representable as a signed 32-bit integer" % addend)
return MemoryAddress(self.base, self.index, self.scale, self.displacement + addend)
elif isinstance(addend, GeneralPurposeRegister64):
if self.base is not None:
raise TypeError("Can not add a general-purpose register to a memory operand with existing base")
if self.index.size != addend.size:
raise TypeError("Index (%s) and addend (%s) registers have different size" %
(str(self.index), str(addend)))
return MemoryAddress(addend, self.index, self.scale, self.displacement)
elif isinstance(addend, MemoryAddress):
if self.base is not None and addend.base is not None:
raise ValueError("Can not add memory address: both address expressions use base registers")
if self.index is not None and addend.index is not None:
raise ValueError("Can not add memory address: both address expressions use index registers")
sum_base = self.base if self.base is not None else addend.base
(sum_index, sum_scale) = (self.index, self.scale) \
if self.index is not None else (addend.index, addend.scale)
return MemoryAddress(sum_base, sum_index, sum_scale, self.displacement + addend.displacement)
else:
raise TypeError("Can not add %s: unsupported addend type" % str(addend))
def __sub__(self, minuend):
from peachpy.util import is_int, is_sint32
if is_int(minuend):
if not is_sint32(-minuend):
raise ValueError("The addend value (%d) is not representable as a signed 32-bit integer" % minuend)
return MemoryAddress(self.base, self.index, self.scale, self.displacement - minuend)
else:
raise TypeError("Can not add %s: unsupported addend type" % str(minuend))
def __str__(self):
parts = []
if self.base is not None:
parts.append(str(self.base))
if self.index is not None:
parts.append(str(self.index) + "*" + str(self.scale))
if self.displacement >= 0:
if self.displacement > 0:
parts.append(str(self.displacement))
return " + ".join(parts)
else:
return " + ".join(parts) + " - " + str(-self.displacement)
def __repr__(self):
return str(self)
class MemoryOperand:
def __init__(self, address, size=None, mask=None, broadcast=None):
from peachpy.x86_64.registers import GeneralPurposeRegister64, \
XMMRegister, YMMRegister, ZMMRegister, MaskedRegister
from peachpy.x86_64.function import LocalVariable
from peachpy.literal import Constant
assert isinstance(address, (GeneralPurposeRegister64, XMMRegister, YMMRegister, ZMMRegister,
MemoryAddress, Constant, LocalVariable, RIPRelativeOffset)) or \
isinstance(address, MaskedRegister) and \
isinstance(address.register, (XMMRegister, YMMRegister, ZMMRegister)) and \
not address.mask.is_zeroing, \
"Only MemoryAddress, 64-bit general-purpose registers, RIP-Relative addresses, XMM/YMM/ZMM registers, " \
"and merge-masked XMM/YMM/ZMM registers may be specified as an address"
from peachpy.util import is_int
assert size is None or is_int(size) and int(size) in SizeSpecification._size_name_map, \
"Unsupported size: %d" % size
self.symbol = None
self.size = size
self.mask = mask
self.broadcast = broadcast
if isinstance(address, MemoryAddress):
if isinstance(address.index, MaskedRegister):
self.address = MemoryAddress(address.base, address.index.register, address.scale, address.displacement)
assert mask is None, "Mask argument can't be used when address index is a masked XMM/YMM/ZMM register"
self.mask = address.index.mask
else:
self.address = address
elif isinstance(address, MaskedRegister):
self.address = MemoryAddress(index=address.register, scale=1)
assert mask is None, "Mask argument can't be used when address is a masked XMM/YMM/ZMM register"
self.mask = address.mask
elif isinstance(address, Constant):
self.address = RIPRelativeOffset(0)
self.symbol = address
self.size = address.size
elif isinstance(address, LocalVariable):
from peachpy.x86_64.registers import rsp
self.address = MemoryAddress(rsp, displacement=address.offset)
self.symbol = address
self.size = address.size
elif isinstance(address, RIPRelativeOffset):
self.address = address
else:
# Convert register to memory address expression
self.address = MemoryAddress(address)
def __str__(self):
if self.size is None:
return "[" + str(self.address) + "]"
else:
return SizeSpecification._size_name_map[self.size] + " [" + str(self.address) + "]"
def __repr__(self):
return str(self)
def __call__(self, mask):
from peachpy.x86_64.registers import KRegister, RegisterMask
if not isinstance(mask, (KRegister, RegisterMask)):
raise SyntaxError("zmm(mask) syntax requires mask to be a KRegister or KRegister.z")
if self.broadcast:
raise ValueError("mask can not be applied to memory operands with broadcasting")
if isinstance(mask, KRegister):
mask = RegisterMask(mask)
return MemoryOperand(self.address, self.size, mask)
def format(self, assembly_format):
assert assembly_format in {"peachpy", "gas", "nasm", "go"}, \
"Supported assembly formats are 'peachpy', 'gas', 'nasm', 'go'"
if assembly_format == "go":
text = str(self.address.displacement)
if self.address.base is not None:
text += "(" + self.address.base.format(assembly_format) + ")"
if self.address.index is not None:
text += "(%s*%d)" % (self.address.index.format(assembly_format), self.address.scale)
return text
elif assembly_format == "gas":
if isinstance(self.address, RIPRelativeOffset):
return str(self.address.offset) + "(%rip)"
else:
base = self.address.base
if self.address.index is None:
return "{displacement}({base})".format(
displacement=self.address.displacement,
base=base.format(assembly_format))
else:
return "{displacement}({base},{index},{scale})".format(
displacement=self.address.displacement,
base="" if base is None else base.format(assembly_format),
index=self.address.index.format(assembly_format),
scale=self.address.scale)
else:
return str(self)
@property
def bcode(self):
return int(self.broadcast is not None)
@property
def kcode(self):
if self.mask is None:
return 0
else:
return self.mask.kcode
@property
def zcode(self):
if self.mask is None:
return 0
else:
return self.mask.zcode
class SizeSpecification:
_size_name_map = {
1: "byte",
2: "word",
4: "dword",
8: "qword",
10: "tword",
16: "oword",
32: "hword",
64: "zword"
}
def __init__(self, size):
from peachpy.util import is_int
assert is_int(size) and int(size) in SizeSpecification._size_name_map, \
"Unsupported size: %d" % size
self.size = size
def __str__(self):
return SizeSpecification._size_name_map[self.size]
def __getitem__(self, address):
return MemoryOperand(address, self.size)
@property
def to2(self):
if self.size not in [4, 8]:
raise ValueError("{1to2} broadcasting is only supported for dword and qword memory locations")
return BroadcastSpecification(self.size, 2)
@property
def to4(self):
if self.size not in [4, 8]:
raise ValueError("{1to4} broadcasting is only supported for dword and qword memory locations")
return BroadcastSpecification(self.size, 4)
@property
def to8(self):
if self.size not in [4, 8]:
raise ValueError("{1to8} broadcasting is only supported for dword and qword memory locations")
return BroadcastSpecification(self.size, 8)
@property
def to16(self):
if self.size != 4:
raise ValueError("{1to16} broadcasting is only supported for dword memory locations")
return BroadcastSpecification(self.size, 16)
class BroadcastSpecification:
def __init__(self, size, broadcast):
assert size in [4, 8]
assert broadcast in [2, 4, 8, 16]
assert size * broadcast in [16, 32, 64]
self.size = size
self.broadcast = broadcast
def __str__(self):
return SizeSpecification._size_name_map[self.size] + "{1to%d}" % self.broadcast
def __getitem__(self, address):
return MemoryOperand(address, self.size, broadcast=self.broadcast)
class RIPRelativeOffset:
def __init__(self, offset):
import peachpy.util
if not peachpy.util.is_sint32(offset):
raise ValueError("RIP-relative offset must be a 32-bit signed integer")
self.offset = offset
def __add__(self, extra_offset):
return RIPRelativeOffset(self.offset + extra_offset)
def __sub__(self, extra_offset):
return RIPRelativeOffset(self.offset - extra_offset)
def __str__(self):
return self.format("peachpy")
def format(self, assembly_format):
if assembly_format == "gas":
return "%d(%rip)" % self.offset
elif assembly_format == "go":
return "%d(IP)" % self.offset
else:
return "rip%+d" % self.offset
def is_al(operand):
from peachpy.x86_64.registers import GeneralPurposeRegister8, al
return isinstance(operand, GeneralPurposeRegister8) and (operand.is_virtual or operand == al)
def is_cl(operand):
from peachpy.x86_64.registers import GeneralPurposeRegister8, cl
return isinstance(operand, GeneralPurposeRegister8) and (operand.is_virtual or operand == cl)
def is_ax(operand):
from peachpy.x86_64.registers import GeneralPurposeRegister16, ax
return isinstance(operand, GeneralPurposeRegister16) and (operand.is_virtual or operand == ax)
def is_eax(operand):
from peachpy.x86_64.registers import GeneralPurposeRegister32, eax
return isinstance(operand, GeneralPurposeRegister32) and (operand.is_virtual or operand == eax)
def is_rax(operand):
from peachpy.x86_64.registers import GeneralPurposeRegister64, rax
return isinstance(operand, GeneralPurposeRegister64) and (operand.is_virtual or operand == rax)
def is_xmm0(operand):
from peachpy.x86_64.registers import XMMRegister, xmm0
return isinstance(operand, XMMRegister) and (operand.is_virtual or operand == xmm0)
def is_r8(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.GeneralPurposeRegister8)
def is_r8rex(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.GeneralPurposeRegister8) and \
operand.physical_id >= 4
def is_r8h(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.GeneralPurposeRegister8) and \
operand.mask == peachpy.x86_64.registers.GeneralPurposeRegister8._high_mask
def is_r16(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.GeneralPurposeRegister16)
def is_r32(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.GeneralPurposeRegister32)
def is_r64(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.GeneralPurposeRegister64)
def is_mm(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.MMXRegister)
def is_xmm(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.XMMRegister) and \
(operand.physical_id is None or operand.physical_id < 16)
def is_evex_xmm(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.XMMRegister)
def is_xmmk(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.XMMRegister) or \
isinstance(operand, peachpy.x86_64.registers.MaskedRegister) and \
isinstance(operand.register, peachpy.x86_64.registers.XMMRegister) and \
not operand.mask.is_zeroing
def is_xmmkz(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.XMMRegister) or \
isinstance(operand, peachpy.x86_64.registers.MaskedRegister) and \
isinstance(operand.register, peachpy.x86_64.registers.XMMRegister)
def is_ymm(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.YMMRegister) and \
(operand.physical_id is None or operand.physical_id < 16)
def is_evex_ymm(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.YMMRegister)
def is_ymmk(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.YMMRegister) or \
isinstance(operand, peachpy.x86_64.registers.MaskedRegister) and \
isinstance(operand.register, peachpy.x86_64.registers.YMMRegister) and \
not operand.mask.is_zeroing
def is_ymmkz(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.YMMRegister) or \
isinstance(operand, peachpy.x86_64.registers.MaskedRegister) and \
isinstance(operand.register, peachpy.x86_64.registers.YMMRegister)
def is_zmm(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.ZMMRegister)
def is_zmmk(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.ZMMRegister) or \
isinstance(operand, peachpy.x86_64.registers.MaskedRegister) and \
isinstance(operand.register, peachpy.x86_64.registers.ZMMRegister) and \
not operand.mask.is_zeroing
def is_zmmkz(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.ZMMRegister) or \
isinstance(operand, peachpy.x86_64.registers.MaskedRegister) and \
isinstance(operand.register, peachpy.x86_64.registers.ZMMRegister)
def is_k(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.KRegister)
def is_kk(operand):
import peachpy.x86_64.registers
return isinstance(operand, peachpy.x86_64.registers.KRegister) or \
isinstance(operand, peachpy.x86_64.registers.MaskedRegister) and \
isinstance(operand.register, peachpy.x86_64.registers.KRegister) and \
not operand.mask.is_zeroing
def is_m(operand):
if not isinstance(operand, MemoryOperand) or operand.mask is not None or operand.broadcast is not None:
return False
# Check that the operand does not use vector index
from peachpy.x86_64.registers import GeneralPurposeRegister
return isinstance(operand.address, RIPRelativeOffset) or \
operand.address.index is None or isinstance(operand.address.index, GeneralPurposeRegister)
def is_mk(operand):
if not isinstance(operand, MemoryOperand) or operand.broadcast is not None:
return False
# Check that the no zero-masking applied to the operand
if operand.mask is not None and operand.mask.is_zeroing:
return False
# Check that the operand does not use vector index
from peachpy.x86_64.registers import GeneralPurposeRegister
return operand.address.index is None or isinstance(operand.address.index, GeneralPurposeRegister)
def is_mkz(operand):
if not isinstance(operand, MemoryOperand) or operand.broadcast is not None:
return False
# Check that the operand does not use vector index
from peachpy.x86_64.registers import GeneralPurposeRegister
return operand.address.index is None or isinstance(operand.address.index, GeneralPurposeRegister)
def is_vmx(operand):
from peachpy.x86_64.registers import XMMRegister
return isinstance(operand, MemoryOperand) and isinstance(operand.address.index, XMMRegister) and \
(operand.address.index is None or operand.address.index.physical_id < 16) and \
operand.mask is None
def is_evex_vmx(operand):
from peachpy.x86_64.registers import XMMRegister
return isinstance(operand, MemoryOperand) and isinstance(operand.address.index, XMMRegister) and \
operand.mask is None
def is_vmxk(operand):
from peachpy.x86_64.registers import XMMRegister
return isinstance(operand, MemoryOperand) and isinstance(operand.address.index, XMMRegister)
def is_vmy(operand):
from peachpy.x86_64.registers import YMMRegister
return isinstance(operand, MemoryOperand) and isinstance(operand.address.index, YMMRegister) and \
(operand.address.index is None or operand.address.index.physical_id < 16) and \
operand.mask is None
def is_evex_vmy(operand):
from peachpy.x86_64.registers import YMMRegister
return isinstance(operand, MemoryOperand) and isinstance(operand.address.index, YMMRegister) and \
operand.mask is None
def is_vmyk(operand):
from peachpy.x86_64.registers import YMMRegister
return isinstance(operand, MemoryOperand) and isinstance(operand.address.index, YMMRegister)
def is_vmz(operand):
from peachpy.x86_64.registers import ZMMRegister
return isinstance(operand, MemoryOperand) and isinstance(operand.address.index, ZMMRegister) and \
operand.mask is None
def is_vmzk(operand):
from peachpy.x86_64.registers import ZMMRegister
return isinstance(operand, MemoryOperand) and isinstance(operand.address.index, ZMMRegister)
def is_m8(operand, strict=False):
return is_m(operand) and (operand.size is None and not strict or operand.size == 1)
def is_m16(operand, strict=False):
import peachpy.literal
return is_m(operand) and (operand.size is None and not strict or operand.size == 2) or \
isinstance(operand, peachpy.literal.Constant) and operand.size == 2
def is_m16kz(operand):
return is_mkz(operand) and (operand.size is None or operand.size == 2)
def is_m32(operand, strict=False):
import peachpy.literal
return is_m(operand) and (operand.size is None and not strict or operand.size == 4) or \
isinstance(operand, peachpy.literal.Constant) and operand.size == 4
def is_m32k(operand):
return is_mk(operand) and (operand.size is None or operand.size == 4)
def is_m32kz(operand):
return is_mkz(operand) and (operand.size is None or operand.size == 4)
def is_m64(operand, strict=False):
import peachpy.literal
return is_m(operand) and (operand.size is None and not strict or operand.size == 8) or \
isinstance(operand, peachpy.literal.Constant) and operand.size == 8
def is_m64k(operand):
return is_mk(operand) and (operand.size is None or operand.size == 8)
def is_m64kz(operand):
return is_mkz(operand) and (operand.size is None or operand.size == 8)
def is_m80(operand, strict=False):
return is_m(operand) and (operand.size is None and not strict or operand.size == 10)
def is_m128(operand, strict=False):
import peachpy.literal
return is_m(operand) and (operand.size is None and not strict or operand.size == 16) or \
isinstance(operand, peachpy.literal.Constant) and operand.size == 16
def is_m128kz(operand):
return is_mkz(operand) and (operand.size is None or operand.size == 16)
def is_m256(operand, strict=False):
import peachpy.literal
return is_m(operand) and (operand.size is None and not strict or operand.size == 32) or \
isinstance(operand, peachpy.literal.Constant) and operand.size == 32
def is_m256kz(operand):
return is_mkz(operand) and (operand.size is None or operand.size == 32)
def is_m512(operand, strict=False):
import peachpy.literal
return is_m(operand) and (operand.size is None and not strict or operand.size == 64) or \
isinstance(operand, peachpy.literal.Constant) and operand.size == 64
def is_m512kz(operand):
return is_mkz(operand) and (operand.size is None or operand.size == 64)
def is_m64_m32bcst(operand):
return is_m64(operand) or isinstance(operand, MemoryOperand) and operand.size == 4 and operand.broadcast == 2
def is_m128_m32bcst(operand):
return is_m128(operand) or isinstance(operand, MemoryOperand) and operand.size == 4 and operand.broadcast == 4
def is_m256_m32bcst(operand):
return is_m256(operand) or isinstance(operand, MemoryOperand) and operand.size == 4 and operand.broadcast == 8
def is_m512_m32bcst(operand):
return is_m512(operand) or isinstance(operand, MemoryOperand) and operand.size == 4 and operand.broadcast == 16
def is_m128_m64bcst(operand):
return is_m128(operand) or isinstance(operand, MemoryOperand) and operand.size == 8 and operand.broadcast == 2
def is_m256_m64bcst(operand):
return is_m256(operand) or isinstance(operand, MemoryOperand) and operand.size == 8 and operand.broadcast == 4
def is_m512_m64bcst(operand):
return is_m512(operand) or isinstance(operand, MemoryOperand) and operand.size == 8 and operand.broadcast == 8
def is_m32bcst(operand):
return False
def is_m64bcst(operand):
return False
def is_imm(operand):
import peachpy.util
return peachpy.util.is_int(operand)
def is_imm4(operand):
import peachpy.util
return peachpy.util.is_int(operand) and 0 <= operand <= 15
def is_imm8(operand, ext_size=None):
import peachpy.util
if ext_size is None:
return peachpy.util.is_int8(operand)
else:
sup = 2**(8*ext_size)
return peachpy.util.is_int(operand) and \
(-128 <= operand <= 127 or sup - 128 <= operand < sup)
def is_imm16(operand, ext_size=None):
import peachpy.util
if ext_size is None:
return peachpy.util.is_int16(operand)
else:
sup = 2**(8*ext_size)
return peachpy.util.is_int(operand) and \
(-32768 <= operand <= 32767 or sup - 32768 <= operand < sup)
def is_imm32(operand, ext_size=None):
import peachpy.util
if ext_size is None:
return peachpy.util.is_int32(operand)
else:
sup = 2**(8*ext_size)
return peachpy.util.is_int(operand) and \
(-2147483648 <= operand <= 2147483647 or sup - 2147483648 <= operand < sup)
def is_imm64(operand):
import peachpy.util
return peachpy.util.is_int64(operand)
def is_rel8(operand):
from peachpy.util import is_sint8
return isinstance(operand, RIPRelativeOffset) and is_sint8(operand.offset)
def is_rel32(operand):
from peachpy.util import is_sint32
return isinstance(operand, RIPRelativeOffset) and is_sint32(operand.offset)
def is_label(operand):
import peachpy.x86_64.pseudo
return isinstance(operand, peachpy.x86_64.pseudo.Label)
def is_er(operand):
return isinstance(operand, RoundingControl)
def is_sae(operand):
return isinstance(operand, SuppressAllExceptions)
byte = SizeSpecification(1)
word = SizeSpecification(2)
dword = SizeSpecification(4)
qword = SizeSpecification(8)
tword = SizeSpecification(10)
oword = SizeSpecification(16)
hword = SizeSpecification(32)
yword = SizeSpecification(32)
zword = SizeSpecification(64)
class RoundingControl:
def __init__(self, name, code):
self.name = name
self.code = code
def __hash__(self):
return hash(self.name)
def __eq__(self, other):
return isinstance(other, RoundingControl) and other.name == self.name and other.code == self.code
def __ne__(self, other):
return not isinstance(other, RoundingControl) or other.name != self.name or other.code != self.code
def __str__(self):
return "{" + self.name + "}"
class SuppressAllExceptions:
def __init__(self, name):
self.name = name
def __hash__(self):
return hash(self.name)
def __eq__(self, other):
return isinstance(other, SuppressAllExceptions) and other.name == self.name
def __ne__(self, other):
return not isinstance(other, SuppressAllExceptions) or other.name != self.name
def __str__(self):
return "{" + self.name + "}"
rn_sae = RoundingControl("rn-sae", 0b00)
rz_sae = RoundingControl("rz-sae", 0b11)
ru_sae = RoundingControl("ru-sae", 0b10)
rd_sae = RoundingControl("rd-sae", 0b01)
sae = SuppressAllExceptions("sae")
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
class Instruction(object):
def __init__(self, name, origin=None, prototype=None):
super(Instruction, self).__init__()
self.name = name
self.line_number = None
self.source_file = None
self.source_code = None
if origin is not None:
self.line_number = origin[1][2]
self.source_file = origin[1][1]
self.source_code = origin[1][4][0].strip()
elif prototype is not None:
self.line_number = prototype.line_number
self.source_file = prototype.source_file
self.source_code = prototype.source_code
self.operands = ()
self._implicit_in_regs = dict()
self._implicit_out_regs = dict()
self.in_regs = ()
self.out_regs = ()
self.out_operands = ()
self.encodings = []
self.bytecode = None
self._gas_name = None
self.go_name = None
self.isa_extensions = frozenset()
self.mmx_mode = None
self.avx_mode = None
self._cancelling_inputs = False
if prototype is None:
self._available_registers = dict()
self._live_registers = dict()
self._indent_level = 0
else:
self._available_registers = prototype._available_registers.copy()
self._live_registers = prototype._available_registers.copy()
self._indent_level = prototype._indent_level
def __str__(self):
if self.operands:
return str(self.name) + " " + ", ".join(map(str, self.operands))
else:
return str(self.name)
@property
def gas_name(self):
if self._gas_name is None:
return self.name.lower()
else:
return self._gas_name
def format(self, assembly_format, indent=False, line_number=None):
from peachpy.x86_64.operand import format_operand
text = "\t" * self._indent_level if indent else ""
if assembly_format == "peachpy":
return text + str(self)
elif assembly_format == "nasm":
return text + str(self)
elif assembly_format == "gas":
if self.operands:
from peachpy.x86_64.pseudo import Label
if line_number is not None and len(self.operands) == 1 and isinstance(self.operands[0], Label) and self.operands[0].line_number is not None:
label = self.operands[0]
return "{indent}{mnemonic} {label_line}{direction} # {label_name}".format(
indent=text,
mnemonic=self.gas_name,
label_line=self.operands[0].line_number,
label_name=str(self.operands[0]),
direction="b" if self.operands[0].line_number < line_number else "f")
else:
return text + self.gas_name + " " + ", ".join(format_operand(op, assembly_format) for op in reversed(self.operands))
else:
return text + self.gas_name
elif assembly_format == "go":
if self.go_name:
from peachpy.util import is_int
if self.name == "CMP" and is_int(self.operands[1]):
# CMP instruction with an immediate operand has operands in normal (non-reversed) order
return text + str(self.go_name) + " " + \
", ".join(format_operand(op, assembly_format) for op in self.operands)
elif self.operands:
return text + str(self.go_name) + " " + \
", ".join(format_operand(op, assembly_format) for op in reversed(self.operands))
else:
return text + str(self.go_name)
else:
return text + "; ".join(map(lambda b: "BYTE $0x%02X" % b, self.encode())) + " // " + str(self)
def format_encoding(self, indent):
if self.bytecode:
text = "\t" * self._indent_level if indent else ""
return text + "# " + " ".join("%02X" % byte for byte in self.bytecode)
@property
def registers(self):
from peachpy.x86_64.operand import get_operand_registers
registers = set()
for operand in self.operands:
registers.update(get_operand_registers(operand))
return registers
@property
def register_objects(self):
from peachpy.x86_64.operand import get_operand_registers
return sum(map(get_operand_registers, self.operands), [])
@property
def available_registers(self):
from peachpy.x86_64.registers import Register
return Register._reconstruct_multiple(self._available_registers)
@property
def live_registers(self):
from peachpy.x86_64.registers import Register
return Register._reconstruct_multiple(self._live_registers)
@property
def input_registers(self):
from peachpy.x86_64.registers import Register
return Register._reconstruct_multiple(self.input_registers_masks)
@property
def input_registers_masks(self):
from peachpy.x86_64.operand import get_operand_registers
if self._cancelling_inputs:
from peachpy.x86_64.registers import Register
input_operands = [operand for (is_input_reg, operand) in zip(self.in_regs, self.operands) if is_input_reg]
assert len(input_operands) == 2, "Instruction forms with cancelling inputs must have two inputs"
assert all(map(lambda op: isinstance(op, Register), input_operands)), \
"Both inputs of instruction form with cancelling inputs must be registers"
if input_operands[0] == input_operands[1]:
return dict()
else:
return {reg._internal_id: reg.mask for reg in input_operands}
else:
registers_masks = self._implicit_in_regs.copy()
for (has_input_registers, operand) in zip(self.in_regs, self.operands):
if has_input_registers:
for register in get_operand_registers(operand):
register_id = register._internal_id
registers_masks[register_id] = \
registers_masks.get(register_id, 0) | register.mask
return registers_masks
@property
def output_registers(self):
from peachpy.x86_64.registers import Register
return Register._reconstruct_multiple(self.output_registers_masks)
@property
def output_registers_masks(self):
from peachpy.x86_64.operand import get_operand_registers
from peachpy.x86_64.registers import GeneralPurposeRegister32, GeneralPurposeRegister64, \
XMMRegister, YMMRegister
registers_masks = self._implicit_out_regs.copy()
for (is_output_register, operand) in zip(self.out_regs, self.operands):
if is_output_register:
for register in get_operand_registers(operand):
register_id = register._internal_id
register_mask = register.mask
if register_mask == GeneralPurposeRegister32._mask:
register_mask = GeneralPurposeRegister64._mask
elif bool(self.avx_mode) and register_mask == XMMRegister._mask:
register_mask = YMMRegister._mask
registers_masks[register_id] = \
registers_masks.get(register_id, 0) | register_mask
return registers_masks
@property
def constant(self):
from peachpy.x86_64.operand import MemoryOperand
from peachpy.literal import Constant
return next(iter(operand.symbol for operand in self.operands if
isinstance(operand, MemoryOperand) and isinstance(operand.symbol, Constant)), None)
@property
def local_variable(self):
from peachpy.x86_64.operand import MemoryOperand
from peachpy.x86_64.function import LocalVariable
return next(iter(operand.symbol for operand in self.operands if
isinstance(operand, MemoryOperand) and isinstance(operand.symbol, LocalVariable)), None)
@property
def memory_address(self):
from peachpy.x86_64.operand import MemoryOperand
memory_operands = [operand for operand in self.operands if isinstance(operand, MemoryOperand)]
if memory_operands:
assert len(memory_operands) == 1, \
"x86-64 instructions can not have more than 1 explicit memory operand"
return memory_operands[0].address
def encode(self):
encodings = self._filter_encodings()
if encodings:
bytecodes = [encoding(self.operands) for (_, encoding) in encodings]
return min(bytecodes, key=len)
else:
return bytearray()
def encode_options(self):
if self.encodings:
bytecodes = [encoding(self.operands) for (_, encoding) in self._filter_encodings()]
min_length = min(map(len, bytecodes))
return filter(lambda b: len(b) == min_length, bytecodes)
else:
return bytearray()
def encode_length_options(self):
from peachpy.x86_64.encoding import Flags, Options
length_encoding_map = {}
encode_options = []
for (flags, encode) in self._filter_encodings():
options = 0
baseline = encode(self.operands)
if flags & Flags.ModRMSIBDisp != 0:
if len(encode(self.operands, sib=True)) != len(baseline):
options |= Options.SIB
if len(encode(self.operands, min_disp=1)) != len(baseline):
options |= Options.Disp8
if len(encode(self.operands, min_disp=4)) != len(baseline):
options |= Options.Disp32
if flags & Flags.OptionalREX != 0:
if len(encode(self.operands, rex=True)) != len(baseline):
options |= Options.REX
if flags & Flags.VEX2 != 0:
if len(encode(self.operands, vex3=True)) != len(baseline):
options |= Options.VEX3
length_encoding_map.setdefault(len(baseline), baseline)
encode_options.append((options, encode))
# Try disp8/disp32 options as they never involve any decoding overhead
for (options, encode) in encode_options:
if options & Options.Disp8:
bytecode = encode(self.operands, min_disp=1)
length_encoding_map.setdefault(len(bytecode), bytecode)
if options & Options.Disp32:
bytecode = encode(self.operands, min_disp=4)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Try to use SIB byte as well (may cause spilling into multiple uops)
for (options, encode) in encode_options:
if options & Options.SIB:
bytecode = encode(self.operands, sib=True)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Or try to combine SIB with disp8/disp32
if options & Options.Disp8:
bytecode = encode(self.operands, min_disp=1)
length_encoding_map.setdefault(len(bytecode), bytecode)
if options & Options.Disp32:
bytecode = encode(self.operands, min_disp=4)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Try to use VEX3
for (options, encode) in encode_options:
if options & Options.VEX3:
bytecode = encode(self.operands, vex3=True)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Combinations of VEX3 with disp8/disp32
if options & Options.Disp8:
bytecode = encode(self.operands, vex3=True, min_disp=1)
length_encoding_map.setdefault(len(bytecode), bytecode)
if options & Options.Disp32:
bytecode = encode(self.operands, vex3=True, min_disp=4)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Try to use VEX3 + SIB
for (options, encode) in encode_options:
if options & Options.VEX3 and options & Options.SIB:
bytecode = encode(self.operands, vex3=True, sib=True)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Combinations of VEX3, SIB, disp8/disp32
if options & Options.Disp8:
bytecode = encode(self.operands, vex3=True, sib=True, min_disp=1)
length_encoding_map.setdefault(len(bytecode), bytecode)
if options & Options.Disp32:
bytecode = encode(self.operands, vex3=True, sib=True, min_disp=4)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Try to use REX
for (options, encode) in encode_options:
if options & Options.REX:
bytecode = encode(self.operands, rex=True)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Combinations of REX with disp8/disp32
if options & Options.Disp8:
bytecode = encode(self.operands, rex=True, min_disp=1)
length_encoding_map.setdefault(len(bytecode), bytecode)
if options & Options.Disp32:
bytecode = encode(self.operands, rex=True, min_disp=4)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Try to use REX + SIB
for (options, encode) in encode_options:
if options & Options.REX and options & Options.SIB:
bytecode = encode(self.operands, rex=True, sib=True)
length_encoding_map.setdefault(len(bytecode), bytecode)
# Combinations of REX, SIB, disp8/disp32
if options & Options.Disp8:
bytecode = encode(self.operands, rex=True, sib=True, min_disp=1)
length_encoding_map.setdefault(len(bytecode), bytecode)
if options & Options.Disp32:
bytecode = encode(self.operands, rex=True, sib=True, min_disp=4)
length_encoding_map.setdefault(len(bytecode), bytecode)
return length_encoding_map
def _filter_encodings(self):
encodings = []
from peachpy.x86_64.encoding import Flags
for (flags, encoding) in self.encodings:
if flags & Flags.AccumulatorOp0 != 0:
if self.operands[0].physical_id == 0:
encodings.append((flags, encoding))
elif flags & Flags.AccumulatorOp1 != 0:
if self.operands[1].physical_id == 0:
encodings.append((flags, encoding))
else:
encodings.append((flags, encoding))
return encodings
@property
def relocation(self):
"""Returns relocation corresponding to encoding of this instruction of None if no relocation needed.
Relocation offset and type variables are initialized, symbol variable needs to be initialized by the caller.
Relocation offset specifies offset relative to the start of instruction encoding.
"""
from peachpy.x86_64.meta import Relocation, RelocationType
if self.bytecode:
from peachpy.literal import Constant
if self.constant is not None:
# Mini-disassembler for instruction encoding.
# Possible encoding sequences:
# | [66, F2, or F3 prefix] | [REX] | [66, F2, or F3 prefix] | ...
# ... [0F, 0F 38, or 0F 3A opcode extension] | Opcode | Mod R/M | disp32 | [imm] |
# | C5 ... 2-byte VEX | Opcode | Mod R/M | disp32 | [imm] |
# | C4 ... 3-byte VEX | Opcode | Mod R/M | disp32 | [imm] |
# | 8F ... 3-byte XOP | Opcode | Mod R/M | disp32 | [imm] |
# | 62 ... 4-byte EVEX | Opcode | Mod R/M | disp32 | [imm] |
prefix_lengths = {
0xC5: 2,
0xC4: 3,
0x8F: 3,
0x62: 4
}
if self.bytecode[0] in prefix_lengths:
mod_rm_position = prefix_lengths[self.bytecode[0]] + 1
else:
decode_position = 0
if self.bytecode[0] in [0x66, 0xF2, 0xF3]:
# Legacy prefix
decode_position += 1
if self.bytecode[decode_position] & 0xF0 == 0x40:
# REX prefix
decode_position += 1
if self.bytecode[decode_position] in [0x66, 0xF2, 0xF3]:
# Legacy prefix += 1
decode_position += 1
if self.bytecode[decode_position] == 0x0F:
# Opcode extension
decode_position += 1
if self.bytecode[decode_position] in [0x38, 0x3A]:
# 2-byte 0F 38 or 0F 3A opcode extension
decode_position += 1
# Opcode
mod_rm_position = decode_position + 1
mod_rm = self.bytecode[mod_rm_position]
rm = mod_rm & 0b111
mode = mod_rm >> 6
assert rm == 0b101 and mode == 0b00, \
"Encoding must use rip-relative disp32 addressing, can't have SIB byte"
return Relocation(mod_rm_position + 1, RelocationType.rip_disp32, program_counter=len(self.bytecode))
class BranchInstruction(Instruction):
def __init__(self, name, origin=None, prototype=None):
super(BranchInstruction, self).__init__(name, origin=origin, prototype=prototype)
self.is_conditional = name != "JMP"
def _encode_label_branch(self, address, label_address=None, long_encoding=False):
if label_address is None:
encodings = [encode(0) for (_, encode) in self.encodings]
else:
encodings = []
from peachpy.x86_64.encoding import Flags
from peachpy.util import is_sint8, is_sint32
for (flags, encode) in self.encodings:
offset = label_address - (address + len(encode(0)))
if flags & Flags.Rel8Label != 0 and is_sint8(offset) or \
flags & Flags.Rel32Label != 0 and is_sint32(offset):
encodings.append(encode(offset))
if not encodings:
raise ValueError("Can not encode offset to label %s" % self.label_name)
assert len(encodings) <= 2, "At most 2 encodings expected for branch instructions with immediate code offset"
if len(encodings) == 1:
return True, encodings[0]
else:
if long_encoding:
return True, max(encodings, key=len)
else:
return False, min(encodings, key=len)
@property
def label_name(self):
from peachpy.x86_64.pseudo import Label
if isinstance(self.operands[0], Label):
return self.operands[0].name
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import inspect
import peachpy.stream
import peachpy.x86_64.options
import peachpy.x86_64.isa
from peachpy.x86_64.instructions import Instruction
from peachpy.x86_64.operand import check_operand, format_operand_type
from peachpy.parse import parse_assigned_variable_name, parse_with_variable_name
class Label:
def __init__(self, name=None):
from peachpy.name import Name
if name is None:
import inspect
self.name = (Name(prename=parse_assigned_variable_name(inspect.stack(), "Label")),)
elif isinstance(name, tuple):
assert all(isinstance(part, Name) for part in name), \
"Name must a string or a tuple or Name objects"
self.name = name
else:
Name.check_name(name)
self.name = (Name(name=name),)
self.line_number = None
def __str__(self):
"""Returns a string representation of the name"""
return ".".join(map(str, self.name))
def format(self, assembly_format):
assert assembly_format in {"peachpy", "gas", "nasm", "go"}, \
"Supported assembly formats are 'peachpy', 'gas', 'nasm', 'go'"
if assembly_format == "go":
# Go assembler rejects label names with a dot, so we replace it with underscore symbol
return str(self).replace(".", "_")
else:
return str(self)
@property
def is_named(self):
return not any(part.name is None for part in self.name)
class LABEL(Instruction):
def __init__(self, label, origin=None):
label = check_operand(label)
super(LABEL, self).__init__("LABEL", origin=origin)
self.operands = (label,)
if not isinstance(label, Label):
raise SyntaxError("Invalid operand for LABEL statement: Label object expected")
self.identifier = label.name
self.input_branches = set()
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def __str__(self):
return ".".join(map(str, self.identifier)) + ":"
def format(self, assembly_format, indent=False, line_number=None):
assert assembly_format in {"peachpy", "gas", "nasm", "go"}, \
"Supported assembly formats are 'peachpy', 'gas', 'nasm', 'go'"
if assembly_format == "go":
# Go assembler rejects label names with a dot, so we replace it with underscore symbol
return "_".join(map(str, self.identifier)) + ":"
elif assembly_format == "gas":
# GAS doesn't support named non-local labels
if self.operands[0].line_number is None:
return "." + str(self) + ":"
else:
return str(self.operands[0].line_number) + ": # " + str(self)
else:
return str(self)
def __enter__(self):
return self
def __exit__(self, exc_type, exc_value, traceback):
if exc_type is not None:
raise
class Loop:
def __init__(self, name=None):
from peachpy.name import Name
if name is None:
import inspect
prename = parse_assigned_variable_name(inspect.stack(), "Loop")
if prename is None:
prename = parse_with_variable_name(inspect.stack(), "Loop")
self.name = (Name(prename=prename),)
elif isinstance(name, tuple):
assert all(isinstance(part, Name) for part in name), \
"Name must a string or a tuple or Name objects"
self.name = name
else:
Name.check_name(name)
self.name = (Name(name=name),)
self.begin = Label(self.name + (Name(name="begin"),))
self.end = Label(self.name + (Name(name="end"),))
def __enter__(self):
LABEL(self.begin)
from peachpy.common.function import active_function
if active_function is not None:
active_function._indent_level += 1
return self
def __exit__(self, exc_type, exc_value, exc_traceback):
from peachpy.common.function import active_function
if active_function is not None:
active_function._indent_level -= 1
if exc_type is None:
LABEL(self.end)
else:
raise
class Block:
def __init__(self, name=None):
from peachpy.name import Name
if name is None:
import inspect
prename = parse_assigned_variable_name(inspect.stack(), "Block")
if prename is None:
prename = parse_with_variable_name(inspect.stack(), "Block")
self.name = (Name(prename=prename),)
elif isinstance(name, tuple):
assert all(isinstance(part, Name) for part in name), \
"Name must a string or a tuple or Name objects"
self.name = name
else:
Name.check_name(name)
self.name = (Name(name=name),)
self.begin = Label(self.name + (Name(name="begin"),))
self.end = Label(self.name + (Name(name="end"),))
def __enter__(self):
LABEL(self.begin)
from peachpy.common.function import active_function
if active_function is not None:
active_function._indent_level += 1
return self
def __exit__(self, exc_type, exc_value, exc_traceback):
from peachpy.common.function import active_function
if active_function is not None:
active_function._indent_level -= 1
if exc_type is None:
LABEL(self.end)
else:
raise
class ALIGN(Instruction):
supported_alignments = (2, 4, 8, 16, 32)
def __init__(self, alignment, origin=None):
super(ALIGN, self).__init__('ALIGN', origin=origin)
if not isinstance(alignment, int):
raise TypeError("The alignment value must be an integer")
if alignment not in ALIGN.supported_alignments:
raise ValueError("The alignment value {0} is not in the list of supported alignments ({1})"
.format(alignment, ", ".join(ALIGN.supported_alignments)))
self.alignment = alignment
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def __str__(self):
return "align {0}".format(self.alignment)
class RETURN(Instruction):
def __init__(self, *args, **kwargs):
from peachpy.common.function import active_function
from peachpy.x86_64.registers import GeneralPurposeRegister, MMXRegister, XMMRegister, YMMRegister
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(RETURN, self).__init__("RETURN", origin=origin)
self.operands = tuple(map(check_operand, args))
if len(self.operands) == 0:
# It is not an error to return nothing from a function with a return type
self.in_regs = tuple()
self.out_regs = tuple()
self.out_operands = tuple()
elif len(self.operands) == 1:
# It is an error to return something from a void function
from peachpy.util import is_int64, int_size
if active_function.result_type is None:
raise ValueError("Void function should not return a value")
if active_function.result_type.is_integer or active_function.result_type.is_pointer:
if is_int64(self.operands[0]):
if active_function.result_type.size is None and int_size(self.operands[0]) > 4 or\
active_function.result_type.size is not None and \
active_function.result_type.size < int_size(self.operands[0]):
raise ValueError("Value {0} can not be represented with return type {1}".
format(str(self.operands[0]), str(active_function.result_type)))
self.in_regs = (False,)
self.out_regs = (False,)
self.out_operands = (False,)
elif isinstance(self.operands[0], GeneralPurposeRegister):
if active_function.result_type.size < self.operands[0].size:
raise ValueError("Register {0} can not be converted to return type {1}".
format(str(self.operands[0]), str(active_function.result_type)))
self.in_regs = (True,)
self.out_regs = (False,)
self.out_operands = (False,)
else:
raise TypeError("Invalid operand type: RETURN {0} for {1} function".
format(str(self.operands[0]), str(active_function.result_type)))
elif active_function.result_type.is_floating_point:
if isinstance(self.operands[0], XMMRegister):
self.in_regs = (True,)
self.out_regs = (False,)
self.out_operands = (False,)
else:
raise TypeError("Invalid operand type: RETURN {0} for {1} function".
format(str(self.operands[0]), str(active_function.result_type)))
elif active_function.result_type.is_vector:
if isinstance(self.operands[0], (MMXRegister, XMMRegister, YMMRegister)) and \
active_function.result_type.size == self.operands[0].size:
self.in_regs = (True,)
self.out_regs = (False,)
self.out_operands = (False,)
else:
raise TypeError("Invalid operand type: RETURN {0} for {1} function".
format(str(self.operands[0]), str(active_function.result_type)))
else:
raise SyntaxError("Invalid operand type: RETURN " + ", ".join(map(format_operand_type, self.operands)))
else:
raise SyntaxError("Pseudo-instruction \"RETURN\" requires 0 or 1 operands")
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def __str__(self):
if len(self.operands) == 0:
return "RETURN"
else:
return "RETURN " + ", ".join(map(str, self.operands))
def format(self, assembly_format, indent=False, line_number=None):
text = "\t" if indent else ""
if assembly_format == "peachpy":
return text + str(self)
else:
raise SyntaxError("Invalid assembly format \"%s\"" % assembly_format)
class LOAD:
class ARGUMENT(Instruction):
def __init__(self, *args, **kwargs):
from peachpy.common.function import active_function
from peachpy.x86_64.registers import GeneralPurposeRegister, XMMRegister, YMMRegister
from peachpy.x86_64 import m64
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(LOAD.ARGUMENT, self).__init__("LOAD.ARGUMENT", origin=origin)
self.operands = tuple(map(check_operand, args))
self.out_regs = (True, False)
self.in_regs = (False, False)
if len(self.operands) != 2:
raise SyntaxError("Instruction \"LOAD.ARGUMENT\" requires 2 operands")
# Check source (second) operand
if not isinstance(self.operands[1], peachpy.Argument):
raise TypeError('The source operand to LOAD.ARGUMENT must be of Argument type')
argument = active_function._find_argument(self.operands[1])
if argument is None:
raise ValueError('%s is not an argument of the active function' % str(self.operands[1]))
# Check destination (first) operand
if isinstance(self.operands[0], GeneralPurposeRegister) and (argument.is_integer or argument.is_pointer):
if argument.size is not None and self.operands[0].size < argument.size:
raise ValueError("Destination register %s is too narrow for the argument %s"
% (self.operands[0], argument))
elif isinstance(self.operands[0], (XMMRegister, YMMRegister)) and argument.is_floating_point:
pass
elif isinstance(self.operands[0], (XMMRegister, YMMRegister)) and \
(argument.is_vector and argument.c_type != m64):
pass
else:
raise ValueError("Unsupported combination of instruction operands")
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def format(self, assembly_format, indent=False, line_number=None):
assert assembly_format in {"peachpy", "go"}, \
"Supported assembly formats are 'peachpy' and 'go'"
text = "\t" if indent else ""
if assembly_format == "go":
from peachpy.x86_64.registers import GeneralPurposeRegister64, GeneralPurposeRegister32, \
GeneralPurposeRegister16, GeneralPurposeRegister8, GeneralPurposeRegister, \
MMXRegister, XMMRegister, YMMRegister
assert isinstance(self.operands[0], (GeneralPurposeRegister, MMXRegister, XMMRegister)), \
"LOAD.ARGUMENT must load into a general-purpose, mmx, or xmm register"
if isinstance(self.operands[0], GeneralPurposeRegister8):
return text + "MOVB %s+%d(FP), %s" % \
(self.operands[1].name, self.operands[1].stack_offset, self.operands[0].format("go"))
elif isinstance(self.operands[0], GeneralPurposeRegister16):
mov_name = {
(True, 1): "MOVWLSX",
(True, 2): "MOVW",
(False, 1): "MOVWLZX",
(False, 2): "MOVW"
}[(self.operands[1].is_signed_integer, self.operands[1].size)]
return text + "%s %s+%d(FP), %s" % \
(mov_name, self.operands[1].name, self.operands[1].stack_offset, self.operands[0].format("go"))
elif isinstance(self.operands[0], GeneralPurposeRegister32):
mov_name = {
(True, 1): "MOVBLSX",
(True, 2): "MOVWLSX",
(True, 4): "MOVL",
(False, 1): "MOVBLZX",
(False, 2): "MOVWLZX",
(False, 4): "MOVL"
}[(self.operands[1].is_signed_integer, self.operands[1].size)]
return text + "%s %s+%d(FP), %s" % \
(mov_name, self.operands[1].name, self.operands[1].stack_offset, self.operands[0].format("go"))
elif isinstance(self.operands[0], GeneralPurposeRegister64):
mov_name = {
(True, 1): "MOVBQSX",
(True, 2): "MOVWQSX",
(True, 4): "MOVLQSX",
(True, 8): "MOVQ",
(False, 1): "MOVBQZX",
(False, 2): "MOVWQZX",
(False, 4): "MOVLQZX",
(False, 8): "MOVQ"
}[(self.operands[1].is_signed_integer, self.operands[1].size)]
return text + "%s %s+%d(FP), %s" % \
(mov_name, self.operands[1].name, self.operands[1].stack_offset, self.operands[0].format("go"))
elif isinstance(self.operands[0], MMXRegister):
mov_name = {
4: "MOVD",
8: "MOVQ"
}[self.operands[1].size]
return text + "%s %s+%d(FP), %s" % \
(mov_name, self.operands[1].name, self.operands[1].stack_offset, self.operands[0].format("go"))
elif isinstance(self.operands[0], XMMRegister):
mov_name = {
4: "MOVD",
8: "MOVQ"
}[self.operands[1].size]
return text + "%s %s+%d(FP), %s" % \
(mov_name, self.operands[1].name, self.operands[1].stack_offset, self.operands[0].format("go"))
else:
return text + str(self)
class STORE:
class RESULT(Instruction):
def __init__(self, *args, **kwargs):
from peachpy.common.function import active_function
from peachpy.x86_64.registers import GeneralPurposeRegister, MMXRegister, XMMRegister, YMMRegister
from peachpy.util import is_int16, is_int32
from peachpy.x86_64.abi import goasm_amd64_abi, goasm_amd64p32_abi
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(STORE.RESULT, self).__init__("STORE.RESULT", origin=origin)
self.operands = tuple(map(check_operand, args))
self.out_regs = (False,)
self.in_regs = (True,)
if len(self.operands) != 1:
raise SyntaxError("Instruction \"STORE.RESULT\" requires 1 operand")
target_function = active_function
destination_offset = None
if target_function is None:
target_function = kwargs.get("target_function")
assert target_function.abi in {goasm_amd64_abi, goasm_amd64p32_abi}
destination_offset = target_function.result_offset
if target_function.result_type is None:
raise ValueError("STORE.RESULT can't be used with void functions")
self.destination_type = target_function.result_type
self.destination_size = self.destination_type.size
# Will be updated during ABI binding (ABIFunction._lower_pseudoinstructions)
self.destination_offset = destination_offset
if isinstance(self.operands[0], GeneralPurposeRegister):
if self.operands[0].size != self.destination_size:
raise ValueError("Can not store result in register %s: size mismatch with return type %s"
% (str(self.operands[0]), str(self.destination_type)))
elif isinstance(self.operands[0], MMXRegister):
if self.destination_size not in {4, 8}:
raise ValueError("Can not store result in register %s: size mismatch with return type %s"
% (str(self.operands[0]), str(self.destination_type)))
elif isinstance(self.operands[0], XMMRegister):
if self.destination_size not in {4, 8}:
raise ValueError("Can not store result in register %s: size mismatch with return type %s"
% (str(self.operands[0]), str(self.destination_type)))
elif isinstance(self.operands[0], YMMRegister):
raise ValueError("Can not store result in register %s: unsupported register type")
elif is_int32(self.operands[0]):
if not self.destination_type.is_integer:
raise ValueError("Can not store integer result %d: type mismatch with result type %s"
% (self.operands[0], str(self.destination_type)))
if is_int16(self.operands[0]) and self.destination_size < 2:
raise ValueError("Can not store integer result %d: size mismatch with result type %s"
% (self.operands[0], str(self.destination_type)))
if is_int32(self.operands[0]) and self.destination_size < 4:
raise ValueError("Can not store integer result %d: size mismatch with result type %s"
% (self.operands[0], str(self.destination_type)))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def format(self, assembly_format, indent=False, line_number=None):
assert assembly_format in {"peachpy", "go"}, \
"Supported assembly formats are 'peachpy' and 'go'"
text = "\t" if indent else ""
if assembly_format == "go":
from peachpy.x86_64.registers import MMXRegister, XMMRegister
from peachpy.x86_64.operand import format_operand
if isinstance(self.operands[0], MMXRegister):
mov_name = {
4: "MOVD",
8: "MOVQ"
}[self.destination_size]
elif isinstance(self.operands[0], XMMRegister):
if self.destination_type.is_floating_point:
mov_name = {
4: "MOVSS",
8: "MOVSD"
}[self.destination_size]
else:
mov_name = {
4: "MOVD",
8: "MOVQ"
}[self.destination_size]
else:
mov_name = {
1: "MOVB",
2: "MOVW",
4: "MOVL",
8: "MOVQ"
}[self.destination_size]
return text + "%s %s, ret+%d(FP)" % \
(mov_name, format_operand(self.operands[0], "go"), self.destination_offset)
else:
return text + str(self)
class SWAP:
@staticmethod
def REGISTERS(register_x, register_y):
from peachpy.x86_64.registers import Register
if isinstance(register_x, Register) and isinstance(register_y, Register):
if register_x.kind == register_y.kind and register_x.size == register_y.size:
register_x.virtual_id, register_y.virtual_id = register_y.virtual_id, register_x.virtual_id
register_x.physical_id, register_y.physical_id = register_y.physical_id, register_x.physical_id
else:
raise ValueError("Registers {0} and {1} have incompatible register types"
.format(register_x, register_y))
else:
raise TypeError("Arguments must be of register regtype")
def REDUCE(reduction_instruction, registers):
if not isinstance(registers, (tuple, list)):
raise ValueError("List or tuple of registers expected")
offset = 1
while offset < len(registers):
for i in range(offset, len(registers), 2 * offset):
reduction_instruction(registers[i - offset], registers[i])
offset *= 2
return registers[0]
class IACA:
class START(Instruction):
def __init__(self, *args, **kwargs):
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(IACA.START, self).__init__("IACA.START", origin=origin)
self.operands = tuple(map(check_operand, args))
if len(self.operands) == 0:
# It is not an error to return nothing from a function with a return type
self.in_regs = tuple()
self.out_regs = tuple()
self.out_operands = tuple()
self.encodings.append((0x0, lambda op: bytearray([0x0F, 0x0B, 0xBB, 0x6F, 0x00, 0x00, 0x00, 0x64, 0x67, 0x90])))
else:
raise SyntaxError("Pseudo-instruction \"IACA.START\" requires 0 operands")
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
class END(Instruction):
def __init__(self, *args, **kwargs):
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(IACA.END, self).__init__("IACA.END", origin=origin)
self.operands = tuple(map(check_operand, args))
if len(self.operands) == 0:
self.in_regs = tuple()
self.out_regs = tuple()
self.out_operands = tuple()
self.encodings.append((0x0, lambda op: bytearray([0xBB, 0xDE, 0x00, 0x00, 0x00, 0x64, 0x67, 0x90, 0x0F, 0x0B])))
else:
raise SyntaxError("Pseudo-instruction \"IACA.END\" requires 0 operands")
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import peachpy.x86_64.abi
import peachpy.x86_64.uarch
import peachpy.x86_64.isa
from peachpy.x86_64.registers import GeneralPurposeRegister, \
GeneralPurposeRegister8, GeneralPurposeRegister16, GeneralPurposeRegister32, GeneralPurposeRegister64, \
MMXRegister, XMMRegister, YMMRegister, ZMMRegister, KRegister, \
rax, rbx, rcx, rdx, rsi, rdi, rbp, r8, r9, r10, r11, r12, r13, r14, r15, \
eax, ebx, ecx, edx, esi, edi, ebp, r8d, r9d, r10d, r11d, r12d, r13d, r14d, r15d, \
ax, bx, cx, dx, si, di, bp, r8w, r9w, r10w, r11w, r12w, r13w, r14w, r15w, \
al, ah, bl, bh, cl, ch, dl, dh, sil, dil, bpl, r8b, r9b, r10b, r11b, r12b, r13b, r14b, r15b, \
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7, \
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15, \
xmm16, xmm17, xmm18, xmm19, xmm20, xmm21, xmm22, xmm23, xmm24, xmm25, xmm26, xmm27, xmm28, xmm29, xmm30, xmm31, \
ymm0, ymm1, ymm2, ymm3, ymm4, ymm5, ymm6, ymm7, ymm8, ymm9, ymm10, ymm11, ymm12, ymm13, ymm14, ymm15, \
ymm16, ymm17, ymm18, ymm19, ymm20, ymm21, ymm22, ymm23, ymm24, ymm25, ymm26, ymm27, ymm28, ymm29, ymm30, ymm31, \
zmm0, zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, zmm7, zmm8, zmm9, zmm10, zmm11, zmm12, zmm13, zmm14, zmm15, \
zmm16, zmm17, zmm18, zmm19, zmm20, zmm21, zmm22, zmm23, zmm24, zmm25, zmm26, zmm27, zmm28, zmm29, zmm30, zmm31, \
k0, k1, k2, k3, k4, k5, k6, k7
from peachpy.x86_64.function import Function, LocalVariable
from peachpy.x86_64.operand import byte, word, dword, qword, oword, hword, yword, zword, \
rn_sae, rz_sae, ru_sae, rd_sae, sae
from peachpy.x86_64.pseudo import Label, Loop, Block, \
LABEL, ALIGN, IACA, RETURN, LOAD, STORE, SWAP, REDUCE
from peachpy.x86_64.nacl import NACLJMP
from peachpy.x86_64.generic import \
ADD, SUB, ADC, SBB, ADCX, ADOX, \
AND, OR, XOR, ANDN, \
NOT, NEG, INC, DEC, \
TEST, CMP, \
MOV, MOVZX, MOVSX, MOVSXD, MOVBE, MOVNTI, \
BT, BTS, BTR, BTC, POPCNT, BSWAP, \
BSF, BSR, LZCNT, TZCNT, \
SHR, SAR, SHL, SAL, SHRX, SARX, SHLX, \
SHRD, SHLD, \
ROR, ROL, RORX, \
RCR, RCL, \
IMUL, MUL, MULX, \
IDIV, DIV, \
LEA, PUSH, POP, \
POPCNT, LZCNT, TZCNT, \
BEXTR, PDEP, PEXT, \
BZHI, \
BLCFILL, BLCI, BLCIC, BLCMSK, BLCS, \
BLSFILL, BLSI, BLSIC, BLSMSK, BLSR, \
T1MSKC, TZMSK, \
CRC32, \
CBW, CDQ, CQO, \
CWD, CWDE, CDQE, \
CMOVA, CMOVNA, CMOVAE, CMOVNAE, \
CMOVB, CMOVNB, CMOVBE, CMOVNBE, \
CMOVC, CMOVNC, CMOVE, CMOVNE, \
CMOVG, CMOVNG, CMOVGE, CMOVNGE, \
CMOVL, CMOVNL, CMOVLE, CMOVNLE, \
CMOVO, CMOVNO, CMOVP, CMOVNP, \
CMOVS, CMOVNS, CMOVZ, CMOVNZ, \
CMOVPE, CMOVPO, \
SETA, SETNA, SETAE, SETNAE, \
SETB, SETNB, SETBE, SETNBE, \
SETC, SETNC, SETE, SETNE, \
SETG, SETNG, SETGE, SETNGE, \
SETL, SETNL, SETLE, SETNLE, \
SETO, SETNO, SETP, SETNP, \
SETS, SETNS, SETZ, SETNZ, \
SETPE, SETPO, \
JA, JNA, JAE, JNAE, \
JB, JNB, JBE, JNBE, \
JC, JNC, JE, JNE, \
JG, JNG, JGE, JNGE, \
JL, JNL, JLE, JNLE, \
JO, JNO, JP, JNP, \
JS, JNS, JZ, JNZ, \
JPE, JPO, JMP, \
JRCXZ, JECXZ, \
RET, CALL, \
PAUSE, NOP, \
INT, UD2, \
CPUID, RDTSC, RDTSCP, XGETBV, \
SYSCALL, \
STC, CLC, CMC, \
STD, CLD, \
XADD, XCHG, \
CMPXCHG, CMPXCHG8B, CMPXCHG16B, \
SFENCE, MFENCE, LFENCE, \
PREFETCHNTA, PREFETCHT0, PREFETCHT1, PREFETCHT2, PREFETCH, PREFETCHW, PREFETCHWT1, \
CLFLUSH, CLFLUSHOPT, CLWB, CLZERO
from peachpy.x86_64.mmxsse import \
MOVSS, EXTRACTPS, INSERTPS, \
ADDSS, SUBSS, MULSS, DIVSS, SQRTSS, \
ROUNDSS, MINSS, MAXSS, RCPSS, RSQRTSS, \
CMPSS, COMISS, UCOMISS, \
MOVSD, ADDSD, SUBSD, MULSD, DIVSD, SQRTSD, \
ROUNDSD, MINSD, MAXSD, \
CMPSD, COMISD, UCOMISD, \
MOVAPS, MOVUPS, MOVLPS, MOVNTPS, \
MOVHPS, MOVSLDUP, MOVSHDUP, \
MOVAPD, MOVUPD, MOVLPD, MOVNTPD, \
MOVHPD, MOVDDUP, \
ADDPS, HADDPS, SUBPS, HSUBPS, ADDSUBPS, MULPS, DIVPS, SQRTPS, \
ADDPD, HADDPD, SUBPD, HSUBPD, ADDSUBPD, MULPD, DIVPD, SQRTPD, \
ROUNDPS, MINPS, MAXPS, RCPPS, RSQRTPS, DPPS, \
CMPPS, MOVMSKPS, \
ROUNDPD, MINPD, MAXPD, DPPD, \
CMPPD, MOVMSKPD, \
ANDPS, ANDNPS, ORPS, XORPS, BLENDPS, BLENDVPS, \
ANDPD, ANDNPD, ORPD, XORPD, BLENDPD, BLENDVPD, \
UNPCKLPS, UNPCKHPS, MOVLHPS, MOVHLPS, SHUFPS, \
UNPCKLPD, UNPCKHPD, SHUFPD, \
MOVD, MOVQ, MOVDQ2Q, MOVQ2DQ, MOVDQA, MOVDQU, LDDQU, \
MASKMOVQ, MASKMOVDQU, \
MOVNTQ, MOVNTDQ, MOVNTDQA, \
PMOVSXBW, PMOVSXBD, PMOVSXBQ, PMOVSXWD, PMOVSXWQ, PMOVSXDQ, \
PMOVZXBW, PMOVZXBD, PMOVZXBQ, PMOVZXWD, PMOVZXWQ, PMOVZXDQ, \
PEXTRB, PEXTRW, PEXTRD, PEXTRQ, \
PINSRB, PINSRW, PINSRD, PINSRQ, \
PMOVMSKB, PTEST, \
PADDB, PADDW, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW, \
PHADDW, PHADDD, PHADDSW, \
PSUBB, PSUBW, PSUBD, PSUBQ, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, \
PHSUBW, PHSUBD, PHSUBSW, \
PMAXSB, PMAXSW, PMAXSD, PMAXUB, PMAXUW, PMAXUD, \
PMINSB, PMINSW, PMINSD, PMINUB, PMINUW, PMINUD, \
PSLLW, PSLLD, PSLLQ, PSRLW, PSRLD, PSRLQ, PSRAW, PSRAD, \
PMULLW, PMULHW, PMULHUW, PMULLD, PMULDQ, PMULUDQ, \
PMULHRSW, PMADDWD, PMADDUBSW, \
PAVGB, PAVGW, \
PSADBW, MPSADBW, PHMINPOSUW, \
PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, \
PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, \
PABSB, PABSW, PABSD, PSIGNB, PSIGNW, PSIGND, \
PAND, PANDN, POR, PXOR, PBLENDW, PBLENDVB, \
PUNPCKLBW, PUNPCKLWD, PUNPCKLDQ, PUNPCKLQDQ, \
PUNPCKHBW, PUNPCKHWD, PUNPCKHDQ, PUNPCKHQDQ, \
PACKSSWB, PACKSSDW, PACKUSWB, PACKUSDW, \
PSHUFB, PSHUFW, PSHUFLW, PSHUFHW, PSHUFD, \
PSLLDQ, PSRLDQ, PALIGNR, \
PCMPESTRI, PCMPESTRM, PCMPISTRI, PCMPISTRM, \
CVTSS2SI, CVTTSS2SI, CVTSI2SS, \
CVTSD2SI, CVTTSD2SI, CVTSI2SD, \
CVTPS2DQ, CVTTPS2DQ, CVTDQ2PS, \
CVTPD2DQ, CVTTPD2DQ, CVTDQ2PD, \
CVTPS2PI, CVTTPS2PI, CVTPI2PS, \
CVTPD2PI, CVTTPD2PI, CVTPI2PD, \
CVTSD2SS, CVTSS2SD, \
CVTPD2PS, CVTPS2PD, \
LDMXCSR, STMXCSR, \
EMMS
from peachpy.x86_64.avx import \
VMOVSS, VEXTRACTPS, VINSERTPS, \
VADDSS, VSUBSS, VMULSS, VDIVSS, VSQRTSS, \
VROUNDSS, VRNDSCALESS, VRANGESS, \
VMINSS, VMAXSS, VREDUCESS, \
VGETMANTSS, VGETEXPSS, VSCALEFSS, VFIXUPIMMSS, VFPCLASSSS, \
VRCPSS, VRSQRTSS, VRCP14SS, VRSQRT14SS, VRCP28SS, VRSQRT28SS, \
VCMPSS, VCOMISS, VUCOMISS, \
VMOVSD, VADDSD, VSUBSD, VMULSD, VDIVSD, VSQRTSD, \
VROUNDSD, VRNDSCALESD, VRANGESD, \
VMINSD, VMAXSD, VREDUCESD, \
VGETMANTSD, VGETEXPSD, VSCALEFSD, VFIXUPIMMSD, VFPCLASSSD, \
VRCP14SD, VRSQRT14SD, VRCP28SD, VRSQRT28SD, \
VCMPSD, VCOMISD, VUCOMISD, \
VMOVAPS, VMOVUPS, VMOVLPS, VMOVHPS, \
VMASKMOVPS, VMOVMSKPS, VMOVNTPS, \
VBROADCASTSS, VMOVSLDUP, VMOVSHDUP, \
VEXPANDPS, VCOMPRESSPS, \
VGATHERDPS, VGATHERQPS, \
VGATHERPF0DPS, VGATHERPF0QPS, \
VGATHERPF1DPS, VGATHERPF1QPS, \
VSCATTERDPS, VSCATTERQPS, \
VSCATTERPF0DPS, VSCATTERPF0QPS, \
VSCATTERPF1DPS, VSCATTERPF1QPS, \
VMOVAPD, VMOVUPD, VMOVLPD, VMOVHPD, \
VMASKMOVPD, VMOVMSKPD, VMOVNTPD, \
VBROADCASTSD, VMOVDDUP, \
VEXPANDPD, VCOMPRESSPD, \
VGATHERDPD, VGATHERQPD, \
VGATHERPF0DPD, VGATHERPF0QPD, \
VGATHERPF1DPD, VGATHERPF1QPD, \
VSCATTERDPD, VSCATTERQPD, \
VSCATTERPF0DPD, VSCATTERPF0QPD, \
VSCATTERPF1DPD, VSCATTERPF1QPD, \
VADDPS, VHADDPS, VSUBPS, VHSUBPS, VADDSUBPS, VMULPS, VDIVPS, VSQRTPS, \
VADDPD, VHADDPD, VSUBPD, VHSUBPD, VADDSUBPD, VMULPD, VDIVPD, VSQRTPD, \
VROUNDPS, VRNDSCALEPS, VRANGEPS, \
VMINPS, VMAXPS, VREDUCEPS, VDPPS, \
VGETMANTPS, VGETEXPPS, VSCALEFPS, VFIXUPIMMPS, VFPCLASSPS, \
VRCPPS, VRSQRTPS, VRCP14PS, VRSQRT14PS, VRCP28PS, VRSQRT28PS, VEXP2PS, \
VCMPPS, VTESTPS, \
VROUNDPD, VRNDSCALEPD, VRANGEPD, \
VMINPD, VMAXPD, VREDUCEPD, VDPPD, \
VGETMANTPD, VGETEXPPD, VSCALEFPD, VFIXUPIMMPD, VFPCLASSPD, \
VRCP14PD, VRSQRT14PD, VRCP28PD, VRSQRT28PD, VEXP2PD, \
VCMPPD, VTESTPD, \
VANDPS, VANDNPS, VORPS, VXORPS, VBLENDPS, VBLENDVPS, VBLENDMPS, \
VANDPD, VANDNPD, VORPD, VXORPD, VBLENDPD, VBLENDVPD, VBLENDMPD, \
VUNPCKLPS, VUNPCKHPS, VMOVLHPS, VMOVHLPS, VSHUFPS, \
VUNPCKLPD, VUNPCKHPD, VSHUFPD, \
VPERMPS, VPERMILPS, VPERMT2PS, VPERMI2PS, \
VPERMPD, VPERMILPD, VPERMT2PD, VPERMI2PD, \
VMOVD, VMOVQ, VMOVDQA, VMOVDQA32, VMOVDQA64, \
VMOVDQU, VMOVDQU8, VMOVDQU16, VMOVDQU32, VMOVDQU64, VLDDQU, \
VPBROADCASTB, VPBROADCASTW, VPBROADCASTD, VPBROADCASTQ, \
VPEXPANDD, VPEXPANDQ, \
VPCOMPRESSD, VPCOMPRESSQ, \
VPMASKMOVD, VPMASKMOVQ, VMASKMOVDQU, VMOVNTDQ, VMOVNTDQA, \
VPMOVSXBW, VPMOVSXBD, VPMOVSXBQ, VPMOVSXWD, VPMOVSXWQ, VPMOVSXDQ, \
VPMOVZXBW, VPMOVZXBD, VPMOVZXBQ, VPMOVZXWD, VPMOVZXWQ, VPMOVZXDQ, \
VPMOVWB, VPMOVDB, VPMOVDW, VPMOVQB, VPMOVQW, VPMOVQD, \
VPMOVSWB, VPMOVSDB, VPMOVSDW, VPMOVSQB, VPMOVSQW, VPMOVSQD, \
VPMOVUSWB, VPMOVUSDB, VPMOVUSDW, VPMOVUSQB, VPMOVUSQW, VPMOVUSQD, \
VPEXTRB, VPEXTRW, VPEXTRD, VPEXTRQ, \
VPINSRB, VPINSRW, VPINSRD, VPINSRQ, \
VPGATHERDD, VPGATHERDQ, VPGATHERQD, VPGATHERQQ, \
VPSCATTERDD, VPSCATTERDQ, VPSCATTERQD, VPSCATTERQQ, \
VPCONFLICTD, VPCONFLICTQ, \
VPLZCNTD, VPLZCNTQ, \
VPTEST, VPMOVMSKB, \
VPADDB, VPADDW, VPADDD, VPADDQ, VPADDSB, VPADDSW, VPADDUSB, VPADDUSW, \
VPHADDW, VPHADDD, VPHADDSW, \
VPSUBB, VPSUBW, VPSUBD, VPSUBQ, VPSUBSB, VPSUBSW, VPSUBUSB, VPSUBUSW, \
VPHSUBW, VPHSUBD, VPHSUBSW, \
VPMAXSB, VPMAXSW, VPMAXSD, VPMAXSQ, VPMAXUB, VPMAXUW, VPMAXUD, VPMAXUQ, \
VPMINSB, VPMINSW, VPMINSD, VPMINSQ, VPMINUB, VPMINUW, VPMINUD, VPMINUQ, \
VPSLLW, VPSLLD, VPSLLQ, VPSRLW, VPSRLD, VPSRLQ, VPSRAW, VPSRAD, VPSRAQ, \
VPROLD, VPROLQ, VPRORD, VPRORQ, \
VPSLLVW, VPSLLVD, VPSLLVQ, VPSRLVW, VPSRLVD, VPSRLVQ, VPSRAVW, VPSRAVD, VPSRAVQ, \
VPROLVD, VPROLVQ, VPRORVD, VPRORVQ, \
VPMULLW, VPMULHW, VPMULHUW, VPMULLD, VPMULLQ, VPMULDQ, VPMULUDQ, \
VPMULHRSW, VPMADDWD, VPMADDUBSW, \
VPMADD52LUQ, VPMADD52HUQ, \
VPAVGB, VPAVGW, \
VPSADBW, VMPSADBW, VDBPSADBW, VPHMINPOSUW, \
VPCMPEQB, VPCMPEQW, VPCMPEQD, VPCMPEQQ, \
VPCMPGTB, VPCMPGTW, VPCMPGTD, VPCMPGTQ, \
VPCMPB, VPCMPW, VPCMPD, VPCMPQ, \
VPCMPUB, VPCMPUW, VPCMPUD, VPCMPUQ, \
VPABSB, VPABSW, VPABSD, VPABSQ, VPSIGNB, VPSIGNW, VPSIGND, \
VPAND, VPANDD, VPANDQ, VPANDN, VPANDND, VPANDNQ, \
VPOR, VPORD, VPORQ, VPXOR, VPXORD, VPXORQ, \
VPTERNLOGD, VPTERNLOGQ, \
VPBLENDW, VPBLENDVB, VPBLENDD, \
VPBLENDMB, VPBLENDMW, VPBLENDMD, VPBLENDMQ, \
VPUNPCKLBW, VPUNPCKLWD, VPUNPCKLDQ, VPUNPCKLQDQ, \
VPUNPCKHBW, VPUNPCKHWD, VPUNPCKHDQ, VPUNPCKHQDQ, \
VPACKSSWB, VPACKSSDW, VPACKUSWB, VPACKUSDW, \
VPSHUFB, VPSHUFLW, VPSHUFHW, VPSHUFD, \
VPERMB, VPERMW, VPERMD, VPERMQ, \
VPERMT2B, VPERMT2W, VPERMT2D, VPERMT2Q, \
VPERMI2B, VPERMI2W, VPERMI2D, VPERMI2Q, \
VPSLLDQ, VPSRLDQ, VPALIGNR, VALIGND, VALIGNQ, VPMULTISHIFTQB, \
VPOPCNTD, VPOPCNTQ, \
VPCMPESTRI, VPCMPESTRM, VPCMPISTRI, VPCMPISTRM, \
VCVTSS2SI, VCVTSS2USI, VCVTTSS2SI, VCVTTSS2USI, VCVTSI2SS, VCVTUSI2SS, \
VCVTSD2SI, VCVTSD2USI, VCVTTSD2SI, VCVTTSD2USI, VCVTSI2SD, VCVTUSI2SD, \
VCVTPS2DQ, VCVTPS2UDQ, VCVTTPS2DQ, VCVTTPS2UDQ, VCVTDQ2PS, VCVTUDQ2PS, \
VCVTPS2QQ, VCVTPS2UQQ, VCVTTPS2QQ, VCVTTPS2UQQ, VCVTQQ2PS, VCVTUQQ2PS, \
VCVTPD2DQ, VCVTPD2UDQ, VCVTTPD2DQ, VCVTTPD2UDQ, VCVTDQ2PD, VCVTUDQ2PD, \
VCVTPD2QQ, VCVTPD2UQQ, VCVTTPD2QQ, VCVTTPD2UQQ, VCVTQQ2PD, VCVTUQQ2PD, \
VCVTSD2SS, VCVTSS2SD, \
VCVTPD2PS, VCVTPS2PD, \
VCVTPS2PH, VCVTPH2PS, \
VBROADCASTF128, VBROADCASTI128, \
VBROADCASTF32X2, VBROADCASTI32X2, \
VBROADCASTF32X4, VBROADCASTI32X4, \
VBROADCASTF32X8, VBROADCASTI32X8, \
VBROADCASTF64X2, VBROADCASTI64X2, \
VBROADCASTF64X4, VBROADCASTI64X4, \
VEXTRACTF128, VEXTRACTI128, \
VEXTRACTF32X4, VEXTRACTI32X4, \
VEXTRACTF32X8, VEXTRACTI32X8, \
VEXTRACTF64X2, VEXTRACTI64X2, \
VEXTRACTF64X4, VEXTRACTI64X4, \
VINSERTF128, VINSERTI128, \
VINSERTF32X4, VINSERTI32X4, \
VINSERTF32X8, VINSERTI32X8, \
VINSERTF64X2, VINSERTI64X2, \
VINSERTF64X4, VINSERTI64X4, \
VPERM2F128, VPERM2I128, \
VSHUFF32X4, VSHUFI32X4, \
VSHUFF64X2, VSHUFI64X2, \
VPTESTMB, VPTESTMW, VPTESTMD, VPTESTMQ, \
VPTESTNMB, VPTESTNMW, VPTESTNMD, VPTESTNMQ, \
VPMOVB2M, VPMOVW2M, VPMOVD2M, VPMOVQ2M, \
VPMOVM2B, VPMOVM2W, VPMOVM2D, VPMOVM2Q, \
VPBROADCASTMB2Q, VPBROADCASTMW2D, \
VPTESTMB, VPTESTMW, VPTESTMD, VPTESTMQ, \
VPTESTNMB, VPTESTNMW, VPTESTNMD, VPTESTNMQ, \
VLDMXCSR, VSTMXCSR, \
VZEROUPPER, VZEROALL
from peachpy.x86_64.fma import \
VFMADD132SS, VFMADD213SS, VFMADD231SS, VFMADDSS, \
VFMSUB132SS, VFMSUB213SS, VFMSUB231SS, VFMSUBSS, \
VFNMADD132SS, VFNMADD213SS, VFNMADD231SS, VFNMADDSS, \
VFNMSUB132SS, VFNMSUB213SS, VFNMSUB231SS, VFNMSUBSS, \
VFMADD132SD, VFMADD213SD, VFMADD231SD, VFMADDSD, \
VFMSUB132SD, VFMSUB213SD, VFMSUB231SD, VFMSUBSD, \
VFNMADD132SD, VFNMADD213SD, VFNMADD231SD, VFNMADDSD, \
VFNMSUB132SD, VFNMSUB213SD, VFNMSUB231SD, VFNMSUBSD, \
VFMADD132PS, VFMADD213PS, VFMADD231PS, VFMADDPS, \
VFMSUB132PS, VFMSUB213PS, VFMSUB231PS, VFMSUBPS, \
VFNMADD132PS, VFNMADD213PS, VFNMADD231PS, VFNMADDPS, \
VFNMSUB132PS, VFNMSUB213PS, VFNMSUB231PS, VFNMSUBPS, \
VFMADD132PD, VFMADD213PD, VFMADD231PD, VFMADDPD, \
VFMSUB132PD, VFMSUB213PD, VFMSUB231PD, VFMSUBPD, \
VFNMADD132PD, VFNMADD213PD, VFNMADD231PD, VFNMADDPD, \
VFNMSUB132PD, VFNMSUB213PD, VFNMSUB231PD, VFNMSUBPD, \
VFMADDSUB132PS, VFMADDSUB213PS, VFMADDSUB231PS, VFMADDSUBPS, \
VFMSUBADD132PS, VFMSUBADD213PS, VFMSUBADD231PS, VFMSUBADDPS, \
VFMADDSUB132PD, VFMADDSUB213PD, VFMADDSUB231PD, VFMADDSUBPD, \
VFMSUBADD132PD, VFMSUBADD213PD, VFMSUBADD231PD, VFMSUBADDPD
from peachpy.x86_64.mask import \
KADDB, KADDW, KADDD, KADDQ, \
KANDB, KANDW, KANDD, KANDQ, \
KANDNB, KANDNW, KANDND, KANDNQ, \
KORB, KORW, KORD, KORQ, \
KXNORB, KXNORW, KXNORD, KXNORQ, \
KXORB, KXORW, KXORD, KXORQ, \
KMOVB, KMOVW, KMOVD, KMOVQ, \
KNOTB, KNOTW, KNOTD, KNOTQ, \
KUNPCKBW, KUNPCKWD, KUNPCKDQ, \
KTESTB, KTESTW, KTESTD, KTESTQ, \
KORTESTB, KORTESTW, KORTESTD, KORTESTQ, \
KSHIFTLB, KSHIFTLW, KSHIFTLD, KSHIFTLQ, \
KSHIFTRB, KSHIFTRW, KSHIFTRD, KSHIFTRQ
from peachpy.x86_64.crypto import \
AESDEC, AESDECLAST, AESENC, AESENCLAST, AESIMC, AESKEYGENASSIST, \
VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VAESIMC, VAESKEYGENASSIST, \
SHA1MSG1, SHA1MSG2, SHA1NEXTE, SHA1RNDS4, SHA256MSG1, SHA256MSG2, SHA256RNDS2, \
PCLMULQDQ, VPCLMULQDQ, \
RDRAND, RDSEED
from peachpy.x86_64.amd import \
PAVGUSB, PMULHRW, \
PF2ID, PF2IW, PI2FW, PI2FD, \
PFADD, PFSUB, PFSUBR, PFMUL, PFMAX, PFMIN, \
PFACC, PFNACC, PFPNACC, PSWAPD, \
PFCMPEQ, PFCMPGT, PFCMPGE, \
PFRCP, PFRCPIT1, PFRCPIT2, PFRSQRT, PFRSQIT1, \
FEMMS, \
MOVNTSS, MOVNTSD, \
INSERTQ, EXTRQ, \
VPPERM, VPCMOV, \
VPROTB, VPROTW, VPROTD, VPROTQ, \
VPSHAB, VPSHAW, VPSHAD, VPSHAQ, \
VPSHLB, VPSHLW, VPSHLD, VPSHLQ, \
VPCOMB, VPCOMW, VPCOMD, VPCOMQ, \
VPCOMUB, VPCOMUW, VPCOMUD, VPCOMUQ, \
VPHADDBW, VPHADDBD, VPHADDBQ, VPHADDWD, VPHADDWQ, VPHADDDQ, \
VPHADDUBW, VPHADDUBD, VPHADDUBQ, VPHADDUWD, VPHADDUWQ, VPHADDUDQ, \
VPHSUBBW, VPHSUBWD, VPHSUBDQ, \
VPMACSDQH, VPMACSDQL, VPMACSDD, VPMACSWD, VPMACSWW, VPMADCSWD, \
VPMACSSDD, VPMACSSDQH, VPMACSSDQL, VPMACSSWD, VPMACSSWW, VPMADCSSWD, \
VFRCZSS, VFRCZSD, VFRCZPS, VFRCZPD, \
VPERMIL2PD, VPERMIL2PS
from peachpy.x86_64.types import \
m64, m128, m128d, m128i, m256, m256d, m256i, m512, m512d, m512i, mmask8, mmask16
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy import Type
m64 = Type("__m64", size=8, is_vector=True, header="mmintrin.h")
m128 = Type("__m128", size=16, is_vector=True, header="xmmintrin.h")
m128d = Type("__m128d", size=16, is_vector=True, header="emmintrin.h")
m128i = Type("__m128i", size=16, is_vector=True, header="emmintrin.h")
m256 = Type("__m256", size=32, is_vector=True, header="immintrin.h")
m256d = Type("__m256d", size=32, is_vector=True, header="immintrin.h")
m256i = Type("__m256i", size=32, is_vector=True, header="immintrin.h")
m512 = Type("__m512", size=64, is_vector=True, header="immintrin.h")
m512d = Type("__m512d", size=64, is_vector=True, header="immintrin.h")
m512i = Type("__m512i", size=64, is_vector=True, header="immintrin.h")
mmask8 = Type("__mmask8", size=1, is_mask=True, header="immintrin.h")
mmask16 = Type("__mmask16", size=2, is_mask=True, header="immintrin.h")
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
class Extension:
def __init__(self, name, safe_name=None):
assert isinstance(name, str), "name must be a string"
self.name = name
if safe_name is None:
self.safe_name = self.name
else:
self.safe_name = safe_name
def __hash__(self):
return hash(self.name)
def __eq__(self, other):
return self.name == other.name
def __ne__(self, other):
return self.name != other.name
def __gt__(self, other):
return other in self.prerequisites
def __lt__(self, other):
return self in other.prerequisites
@property
def prerequisites(self):
return {
"RDTSC": (rdtsc,),
"RDTSCP": (rdtsc, rdtscp),
"CPUID": (cpuid,),
"MMX": (mmx,),
"MMX+": (mmx, mmx_plus),
"3dnow!": (mmx, three_d_now, prefetch, prefetchw),
"3dnow!+": (mmx, three_d_now, three_d_now_plus, prefetch, prefetchw),
"FEMMS": (mmx, femms),
"SSE": (mmx, mmx_plus, sse),
"SSE2": (mmx, mmx_plus, sse, sse2),
"SSE3": (mmx, mmx_plus, sse, sse2, sse3),
"SSSE3": (mmx, mmx_plus, sse, sse2, sse3, ssse3),
"SSE4A": (mmx, mmx_plus, sse, sse2, sse3, sse4a),
"SSE4.1": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1),
"SSE4.2": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2),
"AES": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, aes),
"PCLMULQDQ": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, pclmulqdq),
"RDRAND": (rdrand,),
"RDSEED": (rdrand, rdseed),
'SHA': (sha,),
"AVX": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, avx),
"F16C": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, avx, f16c),
"AVX2": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2),
"XOP": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, avx, xop),
"FMA3": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, avx, fma3),
"FMA4": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, avx, fma4),
"AVX512F": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2, avx512f),
"AVX512BW": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512bw),
"AVX512DQ": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512dq),
"AVX512VL": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512vl),
"AVX512CD": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512cd),
"AVX512PF": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512pf),
"AVX512ER": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512er),
"AVX512VBMI": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512vbmi),
"AVX512IFMA": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512ifma),
"AVX512VPOPCNTDQ": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512vpopcntdq),
"AVX512_4VNNIW": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512_4vnniw),
"AVX512_4FMAPS": (mmx, mmx_plus, sse, sse2, sse3, ssse3, sse4_1, sse4_2, sse4_2, avx, f16c, fma3, avx2,
avx512f, avx512_4fmaps),
"PREFETCH": (prefetch,),
"PREFETCHW": (prefetchw,),
"PREFETCHWT1": (prefetchwt1,),
"CLFLUSH": (clflush,),
"CLFLUSHOPT": (clflush, clflushopt,),
"CLWB": (clwb,),
"CLZERO": (clzero,),
"CMOV": (cmov,),
"POPCNT": (popcnt,),
"LZCNT": (lzcnt,),
"MOVBE": (movbe,),
"BMI": (bmi,),
"BMI2": (bmi, bmi2),
"TBM": (tbm,),
"ADX": (adx,)
}[self.name]
@property
def ancestors(self):
return {
"RDTSC": (rdtsc,),
"RDTSCP": (rdtsc, rdtscp),
"CPUID": (cpuid,),
"MMX": (mmx,),
"MMX+": (mmx, mmx_plus),
"3dnow!": (mmx, three_d_now),
"3dnow!+": (mmx, three_d_now, three_d_now_plus),
"FEMMS": (femms,),
"SSE": (sse,),
"SSE2": (sse, sse2),
"SSE3": (sse, sse2, sse3),
"SSSE3": (sse, sse2, sse3, ssse3),
"SSE4A": (sse, sse2, sse3, sse4a),
"SSE4.1": (sse, sse2, sse3, ssse3, sse4_1),
"SSE4.2": (sse, sse2, sse3, ssse3, sse4_1, sse4_2),
"AES": (aes,),
"PCLMULQDQ": (pclmulqdq,),
"RDRAND": (rdrand,),
"RDSEED": (rdrand, rdseed),
"SHA": (sha,),
"AVX": (avx,),
"F16C": (f16c,),
"AVX2": (avx, avx2),
"XOP": (xop,),
"FMA3": (fma3,),
"FMA4": (fma4,),
"AVX512F": (avx, fma3, f16c, avx2, avx512f),
"AVX512BW": (avx, fma3, f16c, avx2, avx512f, avx512bw),
"AVX512DQ": (avx, fma3, f16c, avx2, avx512f, avx512dq),
"AVX512VL": (avx, fma3, f16c, avx2, avx512f, avx512vl),
"AVX512ER": (avx, fma3, f16c, avx2, avx512f, avx512er),
"AVX512PF": (avx, fma3, f16c, avx2, avx512f, avx512pf),
"AVX512CD": (avx, fma3, f16c, avx2, avx512f, avx512cd),
"AVX512VBMI": (avx, fma3, f16c, avx2, avx512f, avx512vbmi),
"AVX512IFMA": (avx, fma3, f16c, avx2, avx512f, avx512ifma),
"AVX512VPOPCNTDQ": (avx, f16c, fma3, avx2, avx512f, avx512vpopcntdq),
"AVX512_4VNNIW": (avx, f16c, fma3, avx2, avx512f, avx512_4vnniw),
"AVX512_4FMAPS": (avx, f16c, fma3, avx2, avx512f, avx512_4fmaps),
"PREFETCH": (prefetch,),
"PREFETCHW": (prefetchw,),
"PREFETCHWT1": (prefetchwt1,),
"CLFLUSH": (clflush,),
"CLFLUSHOPT": (clflush, clflushopt,),
"CLWB": (clwb,),
"CLZERO": (clzero,),
"CMOV": (cmov,),
"POPCNT": (popcnt,),
"LZCNT": (lzcnt,),
"MOVBE": (movbe,),
"BMI": (bmi,),
"BMI2": (bmi, bmi2),
"TBM": (tbm,),
"ADX": (adx,)
}[self.name]
def __add__(self, extension):
return Extensions(self, extension)
def __str__(self):
return self.name
def __repr__(self):
return str(self)
rdtsc = Extension("RDTSC")
rdtscp = Extension("RDTSCP")
cpuid = Extension("CPUID")
mmx = Extension("MMX")
mmx_plus = Extension("MMX+", safe_name="MMXPlus")
three_d_now = Extension("3dnow!", safe_name="3dnow")
three_d_now_plus = Extension("3dnow!+", safe_name="3dnowPlus")
femms = Extension("FEMMS")
sse = Extension("SSE")
sse2 = Extension("SSE2")
sse3 = Extension("SSE3")
ssse3 = Extension("SSSE3")
sse4a = Extension("SSE4A")
sse4_1 = Extension("SSE4.1", safe_name="SSE4_1")
sse4_2 = Extension("SSE4.2", safe_name="SSE4_2")
aes = Extension("AES")
pclmulqdq = Extension("PCLMULQDQ")
rdrand = Extension("RDRAND")
rdseed = Extension("RDSEED")
sha = Extension("SHA")
avx = Extension("AVX")
avx2 = Extension("AVX2")
avx512f = Extension("AVX512F")
avx512pf = Extension("AVX512PF")
avx512cd = Extension("AVX512CD")
avx512er = Extension("AVX512ER")
avx512dq = Extension("AVX512DQ")
avx512bw = Extension("AVX512BW")
avx512vl = Extension("AVX512VL")
avx512ifma = Extension("AVX512IFMA")
avx512vbmi = Extension("AVX512VBMI")
avx512vpopcntdq = Extension("AVX512VPOPCNTDQ")
avx512_4vnniw = Extension("AVX512_4VNNIW")
avx512_4fmaps = Extension("AVX512_4FMAPS")
prefetch = Extension("PREFETCH")
prefetchw = Extension("PREFETCHW")
prefetchwt1 = Extension("PREFETCHWT1")
clflush = Extension("CLFLUSH")
clflushopt = Extension("CLFLUSHOPT")
clwb = Extension("CLWB")
clzero = Extension("CLZERO")
xop = Extension("XOP")
f16c = Extension("F16C")
fma3 = Extension("FMA3")
fma4 = Extension("FMA4")
cmov = Extension("CMOV")
popcnt = Extension("POPCNT")
lzcnt = Extension("LZCNT")
movbe = Extension("MOVBE")
bmi = Extension("BMI")
bmi2 = Extension("BMI2")
tbm = Extension("TBM")
adx = Extension("ADX")
default = (cpuid, rdtsc, cmov, mmx, mmx_plus, sse, sse2)
class Extensions:
def __init__(self, *args):
self.extensions = set()
for extension in args:
assert extension is None or isinstance(extension, (Extension, Extensions)), \
"Each argument must be an Extension or Extensions object"
if isinstance(extension, Extensions):
self.extensions.add(extension.extensions)
elif isinstance(extension, Extension):
self.extensions.add(extension)
def minify(self):
extensions = list(reversed(sorted(self.extensions)))
for extension in extensions:
for ancestor in extension.ancestors:
if ancestor != extension and ancestor in extensions:
extensions.remove(ancestor)
return extensions
def __add__(self, extension):
return Extensions(extension, *self.extensions)
def __sub__(self, extension):
extensions = set(self.extensions)
if extension in extensions:
del extensions[extension]
else:
raise KeyError("Extension set does not contain {0}".format(extension))
return Extensions(*extensions)
def __str__(self):
return ", ".join(sorted(map(str, self.minify())))
def __contains__(self, extension):
return extension in self.extensions
def __len__(self):
return len(self.extensions)
def __not__(self):
return not self.extensions
def __iter__(self):
return iter(self.extensions)
|
from peachpy.x86_64.registers import GeneralPurposeRegister, MMXRegister, XMMRegister, YMMRegister
from peachpy.x86_64.generic import MOV, MOVZX, MOVSX, MOVSXD
from peachpy.x86_64.mmxsse import MOVQ, MOVAPS, MOVAPD, MOVSS, MOVSD, MOVDQA
from peachpy.x86_64.avx import VMOVAPS, VMOVAPD, VMOVSS, VMOVSD, VMOVDQA
from peachpy.x86_64.operand import dword, word, byte
from peachpy.stream import NullStream
from peachpy.x86_64 import m128, m128d, m128i, m256, m256d, m256i
from peachpy import Type
def load_register(dst_reg, src_reg, data_type, prototype):
assert dst_reg.size >= src_reg.size
assert isinstance(data_type, Type)
with NullStream():
if isinstance(dst_reg, GeneralPurposeRegister):
if dst_reg.size == src_reg.size:
if dst_reg != src_reg or dst_reg.size == 4:
return MOV(dst_reg, src_reg, prototype=prototype)
elif (dst_reg.size, src_reg.size) == (8, 4):
if data_type.is_signed_integer:
return MOVSXD(dst_reg, src_reg, prototype=prototype)
else:
return MOV(dst_reg.as_dword, src_reg, prototype=prototype)
else:
if data_type.is_signed_integer:
return MOVSX(dst_reg, src_reg, prototype=prototype)
else:
if dst_reg.size == 8:
return MOVZX(dst_reg.as_dword, src_reg, prototype=prototype)
else:
return MOVZX(dst_reg, src_reg, prototype=prototype)
elif isinstance(dst_reg, MMXRegister):
if dst_reg != src_reg:
return MOVQ(dst_reg, src_reg, prototype=prototype)
elif isinstance(dst_reg, XMMRegister):
if dst_reg != src_reg:
if data_type.is_floating_point:
assert data_type.size in [4, 8]
xmm_fp_mov = {
(4, True): VMOVAPS,
(4, False): MOVSS,
(8, True): VMOVAPD,
(8, False): MOVSD
}[(data_type.size, bool(prototype.avx_mode))]
return xmm_fp_mov(dst_reg, src_reg, prototype=prototype)
else:
assert data_type in [m128, m128d, m128i]
xmm_mov = {
(m128, True): VMOVAPS,
(m128, False): MOVAPS,
(m128d, True): VMOVAPD,
(m128d, False): MOVAPD,
(m128i, True): VMOVDQA,
(m128i, False): MOVDQA
}[(data_type, bool(prototype.avx_mode))]
return xmm_mov(dst_reg, src_reg, prototype=prototype)
elif isinstance(dst_reg, YMMRegister):
if dst_reg != src_reg:
ymm_mov = {
m256: VMOVAPS,
m256d: VMOVAPD,
m256i: VMOVDQA
}[data_type]
return ymm_mov(dst_reg, src_reg, prototype=prototype)
else:
assert False, "Unexpected type: " + dst_reg.__class__
def load_memory(dst_reg, src_address, src_type, prototype):
assert dst_reg.size >= src_type.size
assert isinstance(src_type, Type)
with NullStream():
if isinstance(dst_reg, GeneralPurposeRegister):
if dst_reg.size == src_type.size:
return MOV(dst_reg, [src_address], prototype=prototype)
elif (dst_reg.size, src_type.size) == (8, 4):
if src_type.is_signed_integer:
return MOVSXD(dst_reg, dword[src_address], prototype=prototype)
else:
return MOV(dst_reg.as_dword, dword[src_address], prototype=prototype)
else:
size_spec = {
1: byte,
2: word,
4: dword
}[src_type.size]
if src_type.is_signed_integer:
return MOVSX(dst_reg, size_spec[src_address], prototype=prototype)
else:
if dst_reg.size == 8:
return MOVZX(dst_reg.as_dword, size_spec[src_address], prototype=prototype)
else:
return MOVZX(dst_reg, size_spec[src_address], prototype=prototype)
elif isinstance(dst_reg, MMXRegister):
return MOVQ(dst_reg, [src_address], prototype)
elif isinstance(dst_reg, XMMRegister):
if src_type.is_floating_point:
assert src_type.size in [4, 8]
if src_type.size == 4:
if prototype.avx_mode:
return VMOVSS(dst_reg, [src_address], prototype=prototype)
else:
return MOVSS(dst_reg, [src_address], prototype=prototype)
else:
if prototype.avx_mode:
return VMOVSD(dst_reg, [src_address], prototype=prototype)
else:
return MOVSD(dst_reg, [src_address], prototype=prototype)
else:
assert src_type in [m128, m128d, m128i]
if src_type == m128:
if prototype.avx_mode:
return VMOVAPS(dst_reg, [src_address], prototype=prototype)
else:
return MOVAPS(dst_reg, [src_address], prototype=prototype)
elif src_type == m128d:
if prototype.avx_mode:
return VMOVAPD(dst_reg, [src_address], prototype=prototype)
else:
return MOVAPD(dst_reg, [src_address], prototype=prototype)
else:
if prototype.avx_mode:
return VMOVDQA(dst_reg, [src_address], prototype=prototype)
else:
return MOVDQA(dst_reg, [src_address], prototype=prototype)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
import inspect
import peachpy.stream
from peachpy.x86_64.instructions import Instruction
from peachpy.x86_64.operand import check_operand, format_operand_type, is_r32, is_imm32
# Permitted pseudo-instructions:
#
# - [rep] cmps %nacl:(%rsi),%nacl:(%rdi),%rZP (sandboxed cmps)
# mov %esi,%esi
# lea (%rZP,%rsi,1),%rsi
# mov %edi,%edi
# lea (%rZP,%rdi,1),%rdi
# [rep] cmps (%rsi),(%rdi)
#
# - [rep] movs %nacl:(%rsi),%nacl:(%rdi),%rZP (sandboxed movs)
# mov %esi,%esi
# lea (%rZP,%rsi,1),%rsi
# mov %edi,%edi
# lea (%rZP,%rdi,1),%rdi
# [rep] movs (%rsi),(%rdi)
#
# - naclasp ...,%rZP (sandboxed stack increment)
# add ...,%esp
# add %rZP,%rsp
#
# - naclcall %eXX,%rZP (sandboxed indirect call)
# and $-32, %eXX
# add %rZP, %rXX
# call *%rXX
# Note: the assembler ensures all calls (including naclcall) will end at the bundle boundary.
#
# - nacljmp %eXX,%rZP (sandboxed indirect jump)
# and $-32,%eXX
# add %rZP,%rXX
# jmp *%rXX
#
# - naclrestbp ...,%rZP (sandboxed %ebp/rbp restore)
# mov ...,%ebp
# add %rZP,%rbp
#
# - naclrestsp ...,%rZP (sandboxed %esp/rsp restore)
# mov ...,%esp
# add %rZP,%rsp
#
# - naclrestsp_noflags ...,%rZP (sandboxed %esp/rsp restore)
# mov ...,%esp
# lea (%rsp,%rZP,1),%rsp
#
# - naclspadj $N,%rZP (sandboxed %esp/rsp restore from %rbp; incudes $N offset)
# lea N(%rbp),%esp
# add %rZP,%rsp
#
# - naclssp ...,%rZP (sandboxed stack decrement)
# SUB(esp, ...)
# ADD(rZP, rsp)
#
# - [rep] scas %nacl:(%rdi),%?ax,%rZP (sandboxed stos)
# mov %edi,%edi
# lea (%rZP,%rdi,1),%rdi
# [rep] scas (%rdi),%?ax
# [rep] stos %?ax,%nacl:(%rdi),%rZP
#
# - (sandboxed stos) mov %edi,%edi
# LEA(rdi, [rZP + rdi*1])
# REP.STOS([rdi], al/ax/eax/rax)
class NACLJMP(Instruction):
"""Sandboxed Indirect Jump"""
def __init__(self, *args, **kwargs):
"""Supported forms:
* NACLJMP(r32)
"""
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(NACLJMP, self).__init__("NACLJMP", origin=origin, prototype=prototype)
self.operands = tuple(map(check_operand, args))
if len(self.operands) != 1:
raise SyntaxError("Instruction \"NACLJMP\" requires 1 operand")
self.in_regs = (True,)
self.out_regs = (False,)
self.out_operands = (True,)
self._gas_name = "nacljmp"
if not is_r32(self.operands[0]):
raise SyntaxError("Invalid operand types: NACLJMP " + ", ".join(map(format_operand_type, self.operands)))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def _lower(self):
from peachpy.stream import InstructionStream
from peachpy.x86_64.generic import AND, ADD, JMP
from peachpy.x86_64.registers import r15
with InstructionStream() as stream:
AND(self.operands[0], -32)
ADD(self.operands[0].as_qword, r15)
JMP(self.operands[0].as_qword)
return stream.instructions
def encode(self):
import operator
return bytearray().join(map(operator.methodcaller("encode"), self._lower()))
class NACLASP(Instruction):
"""Sandboxed RSP Increment (Addition)"""
def __init__(self, *args, **kwargs):
"""Supported forms:
* NACLASP(r32)
* NACLASP(imm32)
"""
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(NACLASP, self).__init__("NACLASP", origin=origin, prototype=prototype)
self.operands = tuple(map(check_operand, args))
if len(self.operands) != 1:
raise SyntaxError("Instruction \"NACLASP\" requires 1 operand")
self.in_regs = (True,)
self.out_regs = (False,)
self.out_operands = (True,)
self._gas_name = "naclasp"
if not is_r32(self.operands[0]) and not is_imm32(self.operands[0]):
raise SyntaxError("Invalid operand types: NACLASP" + ", ".join(map(format_operand_type, self.operands)))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def _lower(self):
from peachpy.stream import InstructionStream
from peachpy.x86_64.generic import ADD
from peachpy.x86_64.registers import esp, rsp, r15
with InstructionStream() as stream:
ADD(esp, self.operands[0])
ADD(rsp, r15)
return stream.instructions
def encode(self):
import operator
return bytearray().join(map(operator.methodcaller("encode"), self._lower()))
class NACLSSP(Instruction):
"""Sandboxed RSP Decrement (Subtraction)"""
def __init__(self, *args, **kwargs):
"""Supported forms:
* NACLSSP(r32)
* NACLSSP(imm32)
"""
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(NACLSSP, self).__init__("NACLSSP", origin=origin, prototype=prototype)
self.operands = tuple(map(check_operand, args))
if len(self.operands) != 1:
raise SyntaxError("Instruction \"NACLSSP\" requires 1 operand")
self.in_regs = (True,)
self.out_regs = (False,)
self.out_operands = (True,)
self._gas_name = "naclssp"
if not is_r32(self.operands[0]) and not is_imm32(self.operands[0]):
raise SyntaxError("Invalid operand types: NACLSSP" + ", ".join(map(format_operand_type, self.operands)))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def _lower(self):
from peachpy.stream import InstructionStream
from peachpy.x86_64.generic import SUB, ADD
from peachpy.x86_64.registers import esp, rsp, r15
with InstructionStream() as stream:
SUB(esp, self.operands[0])
ADD(rsp, r15)
return stream.instructions
def encode(self):
import operator
return bytearray().join(map(operator.methodcaller("encode"), self._lower()))
class NACLRESTSP(Instruction):
"""Sandboxed RSP Restore"""
def __init__(self, *args, **kwargs):
"""Supported forms:
* NACLRESTSP(r32)
"""
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(NACLRESTSP, self).__init__("NACLRESTSP", origin=origin, prototype=prototype)
self.operands = tuple(map(check_operand, args))
if len(self.operands) != 1:
raise SyntaxError("Instruction \"NACLRESTSP\" requires 1 operand")
self.in_regs = (True,)
self.out_regs = (False,)
self.out_operands = (True,)
self._gas_name = "naclrestsp"
if is_r32(self.operands[0]):
pass
else:
raise SyntaxError("Invalid operand types: NACLRESTSP " + ", ".join(map(format_operand_type, self.operands)))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def _lower(self):
from peachpy.stream import InstructionStream
from peachpy.x86_64.generic import MOV, ADD
from peachpy.x86_64.registers import esp, rsp, r15
with InstructionStream() as stream:
MOV(esp, self.operands[0])
ADD(rsp, r15)
return stream.instructions
def encode(self):
import operator
return bytearray().join(map(operator.methodcaller("encode"), self._lower()))
class NACLRESTBP(Instruction):
"""Sandboxed RBP Restore"""
def __init__(self, *args, **kwargs):
"""Supported forms:
* NACLRESTBP(r32)
"""
origin = kwargs.get("origin")
prototype = kwargs.get("prototype")
if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:
origin = inspect.stack()
super(NACLRESTBP, self).__init__("NACLRESTBP", origin=origin, prototype=prototype)
self.operands = tuple(map(check_operand, args))
if len(self.operands) != 1:
raise SyntaxError("Instruction \"NACLRESTBP\" requires 1 operand")
self.in_regs = (True,)
self.out_regs = (False,)
self.out_operands = (True,)
self._gas_name = "naclrestbp"
if is_r32(self.operands[0]):
pass
else:
raise SyntaxError("Invalid operand types: NACLRESTBP " + ", ".join(map(format_operand_type, self.operands)))
if peachpy.stream.active_stream is not None:
peachpy.stream.active_stream.add_instruction(self)
def _lower(self):
from peachpy.stream import InstructionStream
from peachpy.x86_64.generic import MOV, ADD
from peachpy.x86_64.registers import ebp, rbp, r15
with InstructionStream() as stream:
MOV(ebp, self.operands[0])
ADD(rbp, r15)
return stream.instructions
def encode(self):
import operator
return bytearray().join(map(operator.methodcaller("encode"), self._lower()))
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy.x86_64 import isa
class Microarchitecture:
def __init__(self, name, extensions, alu_width, fpu_width, load_with, store_width):
self.name = name
self.extensions = isa.Extensions(*[prerequisite for extension in extensions
for prerequisite in extension.prerequisites])
self.alu_width = alu_width
self.fpu_width = fpu_width
self.load_width = load_with
self.store_width = store_width
def is_supported(self, extension):
return extension in self.extensions
@property
def id(self):
return self.name.replace(" ", "")
@property
def has_sse3(self):
return isa.sse3 in self.extensions
@property
def has_ssse3(self):
return isa.ssse3 in self.extensions
@property
def has_sse4_1(self):
return isa.sse4_1 in self.extensions
@property
def has_sse4_2(self):
return isa.sse4_2 in self.extensions
@property
def has_avx(self):
return isa.avx in self.extensions
@property
def has_avx2(self):
return isa.avx2 in self.extensions
@property
def has_fma3(self):
return isa.fma3 in self.extensions
@property
def has_fma4(self):
return isa.fma4 in self.extensions
@property
def has_fma(self):
return self.has_fma3 or self.has_fma4
@property
def has_avx512f(self):
return isa.avx512f in self.extensions
def __add__(self, extension):
return Microarchitecture(self.name, self.extensions + extension,
self.alu_width, self.fpu_width, self.load_width, self.store_width)
def __sub__(self, extension):
return Microarchitecture(self.name, self.extensions - extension,
self.alu_width, self.fpu_width, self.load_width, self.store_width)
def __hash__(self):
return hash(self.name)
def __eq__(self, other):
return isinstance(other, Microarchitecture) and self.name == other.name
def __ne__(self, other):
return not isinstance(other, Microarchitecture) or self.name != other.name
def __str__(self):
return self.name
def __repr__(self):
return str(self)
default = Microarchitecture('Default', isa.default,
alu_width=128, fpu_width=128, load_with=128, store_width=128)
prescott = Microarchitecture('Prescott', (isa.cmov, isa.sse3, isa.clflush),
alu_width=64, fpu_width=64, load_with=64, store_width=64)
conroe = Microarchitecture('Conroe', (isa.cmov, isa.mmx_plus, isa.ssse3, isa.clflush),
alu_width=128, fpu_width=128, load_with=128, store_width=128)
penryn = Microarchitecture('Penryn', (isa.cmov, isa.mmx_plus, isa.sse4_1, isa.clflush),
alu_width=128, fpu_width=128, load_with=128, store_width=128)
nehalem = Microarchitecture('Nehalem', (isa.cmov, isa.mmx_plus, isa.sse4_2, isa.popcnt, isa.clflush),
alu_width=128, fpu_width=128, load_with=128, store_width=128)
sandy_bridge = Microarchitecture('Sandy Bridge', (isa.cmov, isa.mmx_plus, isa.sse4_2, isa.popcnt, isa.avx),
alu_width=128, fpu_width=256, load_with=256, store_width=128)
ivy_bridge = Microarchitecture('Ivy Bridge', (isa.cmov, isa.mmx_plus, isa.sse4_2, isa.popcnt, isa.avx, isa.f16c),
alu_width=128, fpu_width=256, load_with=256, store_width=128)
haswell = Microarchitecture('Haswell', (isa.cmov, isa.mmx_plus, isa.sse4_2, isa.popcnt, isa.avx, isa.f16c, isa.fma3,
isa.avx2, isa.lzcnt, isa.prefetchw, isa.movbe, isa.bmi2),
alu_width=256, fpu_width=256, load_with=256, store_width=256)
broadwell = Microarchitecture('Broadwell', (isa.cmov, isa.mmx_plus, isa.sse4_2, isa.popcnt, isa.f16c, isa.fma3, isa.avx2,
isa.lzcnt, isa.prefetchw, isa.movbe, isa.bmi2, isa.adx, isa.rdseed),
alu_width=256, fpu_width=256, load_with=256, store_width=256)
skylake = Microarchitecture('Skylake', (isa.cmov, isa.mmx_plus, isa.sse4_2, isa.popcnt, isa.f16c, isa.fma3, isa.avx2,
isa.lzcnt, isa.prefetchw, isa.clflushopt, isa.movbe, isa.bmi2, isa.adx, isa.rdseed),
alu_width=256, fpu_width=256, load_with=256, store_width=256)
skylake_xeon = Microarchitecture('Skylake Xeon', (isa.cmov, isa.mmx_plus, isa.sse4_2, isa.popcnt, isa.f16c, isa.fma3,
isa.lzcnt, isa.prefetchw, isa.clflushopt, isa.movbe, isa.bmi2, isa.adx,
isa.avx512bw, isa.avx512dq, isa.avx512vl, isa.avx512cd, isa.rdseed),
alu_width=512, fpu_width=512, load_with=512, store_width=512)
cannonlake = Microarchitecture('Cannonlake', (isa.cmov, isa.mmx_plus, isa.sse4_2, isa.popcnt, isa.f16c, isa.fma3,
isa.lzcnt, isa.prefetchw, isa.clflushopt, isa.movbe, isa.bmi2, isa.adx,
isa.avx512bw, isa.avx512dq, isa.avx512vl, isa.avx512cd,
isa.avx512ifma, isa.avx512vbmi, isa.rdseed),
# TODO: update EU width when CNL is out
alu_width=512, fpu_width=512, load_with=512, store_width=512)
knights_landing = Microarchitecture('Knights Landing',
(isa.cmov, isa.mmx_plus, isa.sse4_2, isa.popcnt, isa.f16c, isa.fma3,
isa.lzcnt, isa.prefetchw, isa.movbe, isa.bmi2, isa.adx,
isa.avx512cd, isa.avx512cd, isa.avx512er),
alu_width=512, fpu_width=512, load_with=512, store_width=512)
k8 = Microarchitecture('K8', (isa.cmov, isa.mmx_plus, isa.three_d_now_plus, isa.sse2,
isa.prefetch, isa.prefetchw, isa.clflush),
alu_width=64, fpu_width=64, load_with=64, store_width=64)
k10 = Microarchitecture('K10', (isa.cmov, isa.mmx_plus, isa.three_d_now_plus, isa.sse4a,
isa.prefetch, isa.prefetchw, isa.clflush, isa.popcnt, isa.lzcnt),
alu_width=128, fpu_width=128, load_with=128, store_width=64)
bulldozer = Microarchitecture('Bulldozer', (isa.cmov, isa.mmx_plus, isa.sse4a, isa.avx, isa.xop, isa.fma4,
isa.prefetch, isa.prefetchw, isa.clflush,
isa.aes, isa.pclmulqdq, isa.lzcnt, isa.popcnt),
alu_width=128, fpu_width=128, load_with=128, store_width=128)
piledriver = Microarchitecture('Piledriver', (isa.cmov, isa.mmx_plus, isa.sse4a, isa.sse4_2,
isa.avx, isa.xop, isa.fma4, isa.fma3, isa.f16c, isa.aes, isa.pclmulqdq,
isa.prefetch, isa.prefetchw, isa.clflush,
isa.lzcnt, isa.popcnt, isa.bmi, isa.tbm),
alu_width=128, fpu_width=128, load_with=128, store_width=128)
steamroller = Microarchitecture('Steamroller', (isa.cmov, isa.mmx_plus, isa.sse4a, isa.sse4_2,
isa.avx, isa.xop, isa.fma4, isa.fma3, isa.f16c, isa.aes, isa.pclmulqdq,
isa.prefetch, isa.prefetchw, isa.clflush,
isa.lzcnt, isa.popcnt, isa.bmi, isa.tbm),
alu_width=128, fpu_width=256, load_with=256, store_width=128)
excavator = Microarchitecture('Excavator', (isa.cmov, isa.mmx_plus, isa.sse4a, isa.xop, isa.fma4, isa.fma3, isa.f16c,
isa.avx2, isa.aes, isa.pclmulqdq, isa.rdrand,
isa.prefetch, isa.prefetchw, isa.clflush,
isa.lzcnt, isa.popcnt, isa.bmi2, isa.tbm),
alu_width=256, fpu_width=256, load_with=256, store_width=128)
zen = Microarchitecture('Zen', (isa.cmov, isa.mmx_plus, isa.fma4, isa.fma3, isa.f16c, isa.avx2,
isa.aes, isa.pclmulqdq, isa.rdseed, isa.sha,
isa.prefetch, isa.prefetchw, isa.clflushopt, isa.clzero,
isa.lzcnt, isa.popcnt, isa.bmi2, isa.adx, isa.rdseed),
alu_width=256, fpu_width=256, load_with=256, store_width=256)
bonnell = Microarchitecture('Bonnell', (isa.cmov, isa.movbe, isa.mmx_plus, isa.ssse3, isa.clflush),
alu_width=128, fpu_width=64, load_with=128, store_width=128)
saltwell = Microarchitecture('Saltwell', (isa.cmov, isa.movbe, isa.mmx_plus, isa.ssse3, isa.clflush),
alu_width=128, fpu_width=64, load_with=128, store_width=128)
silvermont = Microarchitecture('Silvermont', (isa.cmov, isa.movbe, isa.popcnt, isa.clflush,
isa.mmx_plus, isa.sse4_2, isa.aes, isa.pclmulqdq),
alu_width=128, fpu_width=64, load_with=128, store_width=128)
airmont = Microarchitecture('Airmont', (isa.cmov, isa.movbe, isa.popcnt,
isa.mmx_plus, isa.sse4_2,
isa.aes, isa.pclmulqdq, isa.rdrand,
isa.prefetchw, isa.clflush, isa.rdtscp),
alu_width=128, fpu_width=64, load_with=128, store_width=128)
goldmont = Microarchitecture('Goldmont', (isa.cmov, isa.movbe, isa.popcnt, isa.adx,
isa.mmx_plus, isa.sse4_2, isa.prefetchw, isa.clflushopt,
isa.aes, isa.pclmulqdq, isa.rdseed, isa.sha,
isa.rdtscp),
alu_width=128, fpu_width=64, load_with=128, store_width=128)
bobcat = Microarchitecture('Bobcat', (isa.cmov, isa.mmx_plus, isa.ssse3, isa.sse4a,
isa.prefetch, isa.prefetchw, isa.clflush, isa.lzcnt, isa.popcnt),
alu_width=64, fpu_width=64, load_with=64, store_width=64)
jaguar = Microarchitecture('Jaguar', (isa.cmov, isa.mmx_plus, isa.sse4_2, isa.sse4a, isa.avx, isa.f16c,
isa.prefetch, isa.prefetchw, isa.clflush, isa.lzcnt, isa.popcnt, isa.movbe,
isa.aes, isa.pclmulqdq),
alu_width=128, fpu_width=128, load_with=128, store_width=128)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy.abi import ABI
from peachpy.abi import Endianness
from peachpy.x86_64.registers import rax, rbx, rcx, rdx, rsi, rdi, rbp, r8, r9, r10, r11, r12, r13, r14, r15, \
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15, \
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7
import peachpy.formats.elf.file
import peachpy.formats.mscoff
microsoft_x64_abi = ABI("Microsoft x64 ABI", endianness=Endianness.Little,
bool_size=1, wchar_size=2, short_size=2, int_size=4, long_size=4, longlong_size=8,
pointer_size=8, index_size=8,
stack_alignment=16, red_zone=0,
callee_save_registers=[rbx, rsi, rdi, rbp,
r12, r13, r14, r15,
xmm6, xmm7, xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15],
argument_registers=[rcx, rdx, r8, r9,
xmm0, xmm1, xmm2, xmm3],
volatile_registers=[rax, r10, r11,
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
xmm4, xmm5],
mscoff_machine_type=peachpy.formats.mscoff.MachineType.x86_64)
system_v_x86_64_abi = ABI("SystemV x86-64 ABI", endianness=Endianness.Little,
bool_size=1, wchar_size=4, short_size=2, int_size=4, long_size=8, longlong_size=8,
pointer_size=8, index_size=8,
stack_alignment=16, red_zone=128,
callee_save_registers=[rbx, rbp, r12, r13, r14, r15],
argument_registers=[rdi, rsi, rdx, rcx, r8, r9, xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7],
volatile_registers=[rax, r10, r11,
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15],
elf_class=peachpy.formats.elf.file.ElfClass.class64,
elf_data_encoding=peachpy.formats.elf.file.DataEncoding.little_endian,
elf_machine_type=peachpy.formats.elf.file.MachineType.x86_64)
linux_x32_abi = ABI("Linux X32 ABI", endianness=Endianness.Little,
bool_size=1, wchar_size=4, short_size=2, int_size=4, long_size=4, longlong_size=8,
pointer_size=4, index_size=4,
stack_alignment=16, red_zone=128,
callee_save_registers=[rbx, rbp, r12, r13, r14, r15],
argument_registers=[rdi, rsi, rdx, rcx, r8, r9,
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7],
volatile_registers=[rax, r10, r11,
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15],
elf_class=peachpy.formats.elf.file.ElfClass.class32,
elf_data_encoding=peachpy.formats.elf.file.DataEncoding.little_endian,
elf_machine_type=peachpy.formats.elf.file.MachineType.x86_64)
native_client_x86_64_abi = ABI("Native Client x86-64 ABI", endianness=Endianness.Little,
bool_size=1, wchar_size=4, short_size=2, int_size=4, long_size=4, longlong_size=8,
pointer_size=4, index_size=4,
stack_alignment=16, red_zone=0,
callee_save_registers=[rbx, rbp, r12, r13, r14, r15],
argument_registers=[rdi, rsi, rdx, rcx, r8, r9,
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7],
volatile_registers=[rax, r10, r11,
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15],
restricted_registers=[rbp],
elf_class=peachpy.formats.elf.file.ElfClass.class64,
elf_data_encoding=peachpy.formats.elf.file.DataEncoding.little_endian,
elf_machine_type=peachpy.formats.elf.file.MachineType.x86_64)
gosyso_amd64_abi = ABI("Go/SysO x86-64 ABI", endianness=Endianness.Little,
bool_size=1, wchar_size=4, short_size=2, int_size=4, long_size=8, longlong_size=8,
pointer_size=8, index_size=8,
stack_alignment=8, red_zone=0,
callee_save_registers=[],
argument_registers=[],
volatile_registers=[rax, rbx, rcx, rdx, rdi, rsi, rbp, r8, r9, r10, r11, r12, r13, r14, r15,
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8,
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15],
elf_class=peachpy.formats.elf.file.ElfClass.class64,
elf_data_encoding=peachpy.formats.elf.file.DataEncoding.little_endian,
elf_machine_type=peachpy.formats.elf.file.MachineType.x86_64,
mscoff_machine_type=peachpy.formats.mscoff.MachineType.x86_64)
goasm_amd64_abi = ABI("Go/Asm x86-64 ABI", endianness=Endianness.Little,
bool_size=1, wchar_size=4, short_size=2, int_size=4, long_size=8, longlong_size=8,
pointer_size=8, index_size=8,
stack_alignment=8, red_zone=0,
callee_save_registers=[],
argument_registers=[],
volatile_registers=[rax, rbx, rcx, rdx, rdi, rsi, rbp, r8, r9, r10, r11, r12, r13, r14, r15,
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8,
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15])
gosyso_amd64p32_abi = ABI("Go/SysO x32 ABI", endianness=Endianness.Little,
bool_size=1, wchar_size=4, short_size=2, int_size=4, long_size=8, longlong_size=8,
pointer_size=4, index_size=4,
stack_alignment=4, red_zone=0,
callee_save_registers=[],
argument_registers=[],
volatile_registers=[rax, rbx, rcx, rdx, rdi, rsi, rbp, r8, r9, r10, r11, r12, r13, r14, r15,
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8,
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15],
elf_class=peachpy.formats.elf.file.ElfClass.class32,
elf_data_encoding=peachpy.formats.elf.file.DataEncoding.little_endian,
elf_machine_type=peachpy.formats.elf.file.MachineType.x86_64,
mscoff_machine_type=peachpy.formats.mscoff.MachineType.x86_64)
goasm_amd64p32_abi = ABI("Go/Asm x32 ABI", endianness=Endianness.Little,
bool_size=1, wchar_size=4, short_size=2, int_size=4, long_size=8, longlong_size=8,
pointer_size=4, index_size=4,
stack_alignment=4, red_zone=0,
callee_save_registers=[],
argument_registers=[],
volatile_registers=[rax, rbx, rcx, rdx, rdi, rsi, rbp, r8, r9, r10, r11, r12, r13, r14, r15,
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8,
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15])
def detect(system_abi=False):
"""Detects host ABI (either process ABI or system ABI, depending on parameters)
:param bool system_abi: specified whether system ABI or process ABI should be detected. The two may differ, e.g.
when a 64-bit system runs 32-bit Python interpreter.
:returns: the host ABI or None if the host is not recognized or is not x86-64.
:rtype: ABI or None
"""
import platform
import os
import struct
(osname, node, release, version, machine, processor) = platform.uname() # pylint:disable=unpacking-non-sequence
pointer_size = struct.calcsize("P")
if osname == "Darwin" and machine == "x86_64" and (system_abi or pointer_size == 8):
return system_v_x86_64_abi
elif osname == "FreeBSD" and machine == "amd64" and (system_abi or pointer_size == 8):
return system_v_x86_64_abi
elif osname == "Linux" and machine == "x86_64":
if system_abi or pointer_size == 8:
return system_v_x86_64_abi
else:
return linux_x32_abi
elif osname == "Windows" and machine == "AMD64" and (system_abi or pointer_size == 8):
return microsoft_x64_abi
elif osname == "NaCl" and os.environ.get("NACL_ARCH") == "x86_64" and (system_abi or pointer_size == 4):
return native_client_x86_64_abi
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from __future__ import absolute_import
from peachpy import *
from peachpy.x86_64 import *
import sys
import argparse
import six
parser = argparse.ArgumentParser(
description="PeachPy: Portable Efficient Assembly Code-generation in High-level Python")
parser.add_argument("-g", dest="debug_level", type=int, default=0,
help="Debug information level")
parser.add_argument("-S", dest="generate_assembly", action="store_true",
help="Generate assembly listing on output")
parser.add_argument("-MMD", dest="generate_dependencies_makefile", action="store_true",
help="Generate Makefile describing the dependencies")
parser.add_argument("-MF", dest="dependencies_makefile_path",
help="Path to output Makefile with dependencies")
parser.add_argument("-I", dest="include", action="append", default=list(),
help="Add directory to module search path")
parser.add_argument("-fdump-rtl", dest="rtl_dump",
help="Path to output file for RTL dump")
parser.add_argument("-emit-json-metadata", dest="json_metadata_file",
help="Path to output file for JSON metadata")
parser.add_argument("-emit-c-header", dest="c_header_file",
help="Path to output file for C/C++ header")
parser.add_argument("-fname-mangling", dest="name_mangling",
help="Mangling of function names")
abi_map = {
"ms": (peachpy.x86_64.abi.microsoft_x64_abi, ["masm", "nasm"], ["ms-coff"]),
"sysv": (peachpy.x86_64.abi.system_v_x86_64_abi, ["gas", "nasm"], ["elf", "mach-o"]),
"x32": (peachpy.x86_64.abi.linux_x32_abi, ["gas"], ["elf"]),
"nacl": (peachpy.x86_64.abi.native_client_x86_64_abi, ["gas"], ["elf"]),
"gosyso": (peachpy.x86_64.abi.gosyso_amd64_abi, ["gas"], ["elf", "mach-o", "ms-coff"]),
"goasm": (peachpy.x86_64.abi.goasm_amd64_abi, ["go"], []),
"gosyso-p32": (peachpy.x86_64.abi.gosyso_amd64p32_abi, ["gas"], ["elf", "mach-o", "ms-coff"]),
"goasm-p32": (peachpy.x86_64.abi.goasm_amd64p32_abi, ["go"], [])
}
parser.add_argument("-mabi", dest="abi", default="native",
choices=("native", "ms", "sysv", "x32", "nacl", "gosyso", "gosyso-p32", "goasm", "goasm-p32"),
help="Generate code for specified ABI")
cpu_map = {
"default": peachpy.x86_64.uarch.default,
"prescott": peachpy.x86_64.uarch.prescott,
"conroe": peachpy.x86_64.uarch.conroe,
"penryn": peachpy.x86_64.uarch.penryn,
"nehalem": peachpy.x86_64.uarch.nehalem,
"sandybridge": peachpy.x86_64.uarch.sandy_bridge,
"ivybridge": peachpy.x86_64.uarch.ivy_bridge,
"haswell": peachpy.x86_64.uarch.haswell,
"broadwell": peachpy.x86_64.uarch.broadwell,
"skylake": peachpy.x86_64.uarch.skylake,
"skylake-xeon": peachpy.x86_64.uarch.skylake_xeon,
"cannonlake": peachpy.x86_64.uarch.cannonlake,
"k8": peachpy.x86_64.uarch.k8,
"k10": peachpy.x86_64.uarch.k10,
"bulldozer": peachpy.x86_64.uarch.bulldozer,
"piledriver": peachpy.x86_64.uarch.piledriver,
"steamroller": peachpy.x86_64.uarch.steamroller,
"excavator": peachpy.x86_64.uarch.excavator,
"zen": peachpy.x86_64.uarch.zen,
"bonnell": peachpy.x86_64.uarch.bonnell,
"saltwell": peachpy.x86_64.uarch.saltwell,
"silvermont": peachpy.x86_64.uarch.silvermont,
"airmont": peachpy.x86_64.uarch.airmont,
"goldmont": peachpy.x86_64.uarch.goldmont,
"bobcat": peachpy.x86_64.uarch.bobcat,
"jaguar": peachpy.x86_64.uarch.jaguar,
"knightslanding": peachpy.x86_64.uarch.knights_landing
}
parser.add_argument("-mcpu", dest="cpu", default="default",
choices=("default", "prescott", "conroe", "penryn", "nehalem", "sandybridge", "ivybridge",
"haswell", "broadwell", "skylake", "skylake-xeon", "cannonlake",
"k8", "k10", "bulldozer", "piledriver", "steamroller", "excavator", "zen",
"bonnell", "saltwell", "silvermont", "airmont", "goldmont",
"bobcat", "jaguar",
"knightslanding"),
help="Target specified microarchitecture")
parser.add_argument("-mimage-format", dest="image_format", default="native",
choices=("native", "elf", "mach-o", "ms-coff"),
help="Target binary image format")
parser.add_argument("-massembly-format", dest="assembly_format",
choices=("golang", "nasm", "gas", "masm"),
help="Target assembly format")
parser.add_argument("-fpackage", dest="package", default="",
help="Use specified Go package name in generated Plan 9 assembly listings")
avx_group = parser.add_mutually_exclusive_group()
avx_group.add_argument("-mavx", dest="avx", action="store_true",
help="Enable AVX extension")
avx_group.add_argument("-mno-avx", dest="avx", action="store_false",
help="Disable AVX extension")
xop_group = parser.add_mutually_exclusive_group()
xop_group.add_argument("-mxop", dest="xop", action="store_true",
help="Enable XOP extension")
xop_group.add_argument("-mno-xop", dest="xop", action="store_false",
help="Disable XOP extension")
fma4_group = parser.add_mutually_exclusive_group()
fma4_group.add_argument("-mfma4", dest="fma4", action="store_true",
help="Enable FMA4 extension")
fma4_group.add_argument("-mno-fma4", dest="fma4", action="store_false",
help="Disable FMA4 extension")
fma3_group = parser.add_mutually_exclusive_group()
fma3_group.add_argument("-mfma3", dest="fma3", action="store_true",
help="Enable FMA3 extension")
fma3_group.add_argument("-mno-fma3", dest="fma3", action="store_false",
help="Disable FMA3 extension")
f16c_group = parser.add_mutually_exclusive_group()
f16c_group.add_argument("-mf16c", dest="f16c", action="store_true",
help="Enable F16C extension")
f16c_group.add_argument("-mno-f16c", dest="f16c", action="store_false",
help="Disable F16C extension")
avx2_group = parser.add_mutually_exclusive_group()
avx2_group.add_argument("-mavx2", dest="avx2", action="store_true",
help="Enable AVX2 extension")
avx2_group.add_argument("-mno-avx2", dest="avx2", action="store_false",
help="Disable AVX2 extension")
parser.add_argument("-o", dest="output", required=True,
help="Output file name (ELF/Mach-O/COFF image or Go assembly source)")
parser.add_argument("input", nargs=1,
help="Input file name (must be a PeachPy Python script)")
def guess_assembly_format_from_abi(abi):
_, supported_assembly_formats, _ = abi_map[abi]
return supported_assembly_formats[0]
def check_abi_assembly_format_combination(abi, assembly_format):
_, supported_assembly_formats, _ = abi_map[abi]
if assembly_format not in supported_assembly_formats:
raise ValueError("Assembly format %s is not supported for %s" % (assembly_format, str(abi)))
def check_abi_image_format_combination(image_format, abi):
_, _, supported_image_formats = abi_map[abi]
if image_format not in supported_image_formats:
raise ValueError("Image format %s is not supported for %s" % (image_format, str(abi)))
def detect_native_image_format():
import platform
osname = platform.system()
if osname == "Darwin":
return "mach-o"
elif osname in ["Linux", "NaCl", "FreeBSD"]:
return "elf"
elif osname == "Windows":
return "ms-coff"
def add_module_files(module_files, module, roots):
"""Recursively adds Python source files for module and its submodules inside the roots directories"""
if not hasattr(module, "__file__"):
return
module_file = module.__file__
if module_file is None:
return
import os
if not any(module_file.startswith(root + os.sep) for root in roots):
# The file is not inside any of the monitored roots
# This is typical for system modules
return
if module_file.endswith(".pyc") or module_file.endswith(".pyo"):
module_source_file = module_file[:-4] + ".py"
if os.path.isfile(module_source_file):
module_file = module_source_file
if module_file in module_files:
# This module was already added under a different name
return
module_files.add(module_file)
from types import ModuleType
for variable_name in dir(module):
if variable_name.startswith("__"):
continue
variable = getattr(module, variable_name)
if isinstance(variable, ModuleType):
add_module_files(module_files, variable, roots)
def execute_script(writers, source_filename):
if writers:
writer = writers.pop()
with writer:
execute_script(writers, source_filename)
else:
with open(source_filename) as input_file:
code = compile(input_file.read(), source_filename, 'exec')
exec(code, globals())
def main():
options = parser.parse_args()
import peachpy.x86_64.options
peachpy.x86_64.options.debug_level = options.debug_level
if options.abi == "native":
abi = peachpy.x86_64.abi.detect(system_abi=True)
if abi is None:
raise ValueError("Could not auto-detect ABI: specify it with -mabi option")
# Set options.abi to the corresponding string value because it is used later on
options.abi = {abi: name for name, (abi, _, _) in six.iteritems(abi_map)}[abi]
else:
abi, _, _ = abi_map[options.abi]
peachpy.x86_64.options.abi = abi
peachpy.x86_64.options.target = cpu_map[options.cpu]
peachpy.x86_64.options.package = options.package
peachpy.x86_64.options.generate_assembly = options.generate_assembly
if options.name_mangling:
peachpy.x86_64.options.name_mangling = options.name_mangling
from peachpy.writer import ELFWriter, MachOWriter, MSCOFFWriter, AssemblyWriter, JSONMetadataWriter, CHeaderWriter
writers = []
if peachpy.x86_64.options.generate_assembly:
assembly_format = options.assembly_format
if assembly_format is None:
assembly_format = guess_assembly_format_from_abi(options.abi)
else:
check_abi_assembly_format_combination(options.abi, assembly_format)
writers.append(AssemblyWriter(options.output, assembly_format, options.input[0]))
else:
image_format = options.image_format
if image_format == "native":
image_format = detect_native_image_format()
if image_format is None:
raise ValueError("Could not auto-detect image format: specify it with -mimage-format option")
check_abi_image_format_combination(image_format, options.abi)
if image_format == "elf":
writers.append(ELFWriter(options.output, abi, options.input[0]))
elif image_format == "mach-o":
writers.append(MachOWriter(options.output, abi))
elif image_format == "ms-coff":
writers.append(MSCOFFWriter(options.output, abi, options.input[0]))
else:
raise ValueError("Image format %s is not supported" % image_format)
dependencies_makefile_path = options.output + ".d"
if options.dependencies_makefile_path:
dependencies_makefile_path = options.dependencies_makefile_path
if options.rtl_dump:
peachpy.x86_64.options.rtl_dump_file = open(options.rtl_dump, "w")
if options.c_header_file:
writers.append(CHeaderWriter(options.c_header_file, options.input[0]))
if options.json_metadata_file:
writers.append(JSONMetadataWriter(options.json_metadata_file))
# PeachPy sources can import other modules or files from the same directory
import os
include_directories = [os.path.abspath(include_dir) for include_dir in options.include]
include_directories.insert(0, os.path.abspath(os.path.dirname(options.input[0])))
sys.path.extend(include_directories)
# We would like to avoid situations where source file has changed, but Python uses its old precompiled version
sys.dont_write_bytecode = True
execute_script(writers, options.input[0])
if options.generate_dependencies_makefile:
module_files = set()
for module in sys.modules.values():
add_module_files(module_files, module, include_directories)
dependencies = list(sorted(module_files))
dependencies.insert(0, options.input[0])
with open(dependencies_makefile_path, "w") as dependencies_makefile:
dependencies_makefile.write(options.output + ": \\\n " + " \\\n ".join(dependencies) + "\n")
if __name__ == "__main__":
main()
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from __future__ import print_function
import os
import operator
import bisect
import collections
import six
import peachpy
import peachpy.writer
import peachpy.name
import peachpy.x86_64.instructions
import peachpy.x86_64.registers
import peachpy.x86_64.avx
import peachpy.x86_64.options
import peachpy.x86_64.meta
class Function:
"""Generalized x86-64 assembly function.
A function consists of C signature and a list of instructions.
On this level the function is supposed to be compatible with multiple ABIs. In particular, instructions may have
virtual registers, and instruction stream may contain pseudo-instructions, such as LOAD.ARGUMENT or RETURN.
"""
def __init__(self, name, arguments, result_type=None,
package=None,
target=None,
debug_level=None):
"""
:param str name: name of the function without mangling (as in C language).
:param tuple arguments: a tuple of :class:`peachpy.Argument` objects.
:param Type result_type: the return type of the function. None if the function returns no value (void function).
:param str package: the name of the Go package containing this function.
:param Microarchitecture target: the target microarchitecture for this function.
:param int debug_level: the verbosity level for debug information collected for instructions. 0 means no
debug information, 1 and above enables information about the lines of Python code that originated an
instruction. Collecting debug information increases processing time by several times.
:ivar Label entry: a label that marks the entry point of the function. A user can place the entry point in any
place in the function by defining this label with LABEL pseudo-instruction. If this label is not defined
by the user, it will be placed automatically before the first instruction of the function.
:ivar int _indent_level: the level of indentation for this instruction in assembly listings. Indentation level
is changed by Loop statements.
:ivar list _instructions: the list of :class:`Instruction` objects that comprise the function code.
:ivar set _label_names: a set of string names of LABEL quasi-instructions in the function. The set is populated
as instructions are added and is intended to track duplicate labels.
:ivar dict _named_constants: a dictionary that maps names of literal constants to Constant objects.
As instructions are added the dictionary is used to track constants with same names, but different content.
"""
self.name = name
self.arguments = arguments
self.result_type = result_type
if package is None:
self.package = peachpy.x86_64.options.package
self.package = package
if target is None:
target = peachpy.x86_64.options.target
if target is None:
target = peachpy.x86_64.uarch.default
if not isinstance(target, peachpy.x86_64.uarch.Microarchitecture):
raise TypeError("%s is not an valid CPU target" % str(target))
self.target = target
if debug_level is None:
self.debug_level = peachpy.x86_64.options.debug_level
else:
self.debug_level = int(debug_level)
from peachpy.x86_64.pseudo import Label
from peachpy.name import Name
self.entry = Label((Name("__entry__", None),))
self._indent_level = 1
self._instructions = list()
# This set is only used to ensure that all labels references in branches are defined
self._label_names = set()
# Map from id of Name objects to their copies.
# This ensures that Name objects without name can be compared for equality using id
self._names_memo = dict()
self._scope = peachpy.name.Namespace(None)
self._local_variables_count = 0
self._virtual_general_purpose_registers_count = 0
self._virtual_mmx_registers_count = 0
self._virtual_xmm_registers_count = 0
self._virtual_mask_registers_count = 0
from peachpy.x86_64 import m256, m256d, m256i
avx_types = [m256, m256d, m256i]
self.avx_environment = any([arg.c_type in avx_types for arg in self.arguments]) or self.result_type in avx_types
self._avx_prolog = None
from peachpy.x86_64.registers import GeneralPurposeRegister, MMXRegister, XMMRegister, KRegister
from peachpy.common import RegisterAllocator
self._register_allocators = {
GeneralPurposeRegister._kind: RegisterAllocator(),
MMXRegister._kind: RegisterAllocator(),
XMMRegister._kind: RegisterAllocator(),
KRegister._kind: RegisterAllocator()
}
@property
def c_signature(self):
"""C signature (including parameter names) for the function"""
signature = "void" if self.result_type is None else str(self.result_type)
signature = signature + " " + self.name
signature = signature + "(" + ", ".join(map(str, self.arguments)) + ")"
return signature
@property
def go_signature(self):
"""Go signature (including parameter names) for the function.
None if the function argument or return type is incompatible with Go"""
def c_to_go_type(c_type):
assert isinstance(c_type, peachpy.Type)
if c_type.is_pointer:
if c_type.base is not None:
return "*" + c_to_go_type(c_type.base)
else:
return "uintptr"
elif c_type.is_bool:
return "boolean"
elif c_type.is_size_integer:
return "int" if c_type.is_signed_integer else "uint"
elif c_type.is_signed_integer:
return {
1: "int8",
2: "int16",
4: "int32",
8: "int64"
}[c_type.size]
elif c_type.is_unsigned_integer:
return {
1: "uint8",
2: "uint16",
4: "uint32",
8: "uint64"
}[c_type.size]
elif c_type.is_floating_point:
return {
4: "float32",
8: "float64"
}[c_type.size]
else:
return None
go_argument_types = list(map(c_to_go_type, map(operator.attrgetter("c_type"), self.arguments)))
# Some of the C types doesn't have a Go analog
if not(all(map(bool, go_argument_types))):
return None
go_arguments = map(lambda name_gotype: " ".join(name_gotype),
zip(map(operator.attrgetter("name"), self.arguments), go_argument_types))
if self.result_type is None:
return "func %s(%s)" % (self.name, ", ".join(go_arguments))
else:
go_result_type = c_to_go_type(self.result_type)
if go_result_type is None:
return None
else:
return "func %s(%s) %s" % (self.name, ", ".join(go_arguments), go_result_type)
@property
def isa_extensions(self):
from peachpy.x86_64.isa import Extensions
extensions = set()
for instruction in self._instructions:
extensions.update(instruction.isa_extensions)
return Extensions(*extensions)
def __enter__(self):
self.attach()
return self
def __exit__(self, exc_type, exc_value, traceback):
self.detach()
if exc_type is None:
self._add_default_labels()
self._check_undefined_labels()
self._remove_unused_labels()
self._analize()
if peachpy.x86_64.options.rtl_dump_file:
peachpy.x86_64.options.rtl_dump_file.write(self.format_instructions())
self._check_live_registers()
self._preallocate_registers()
self._bind_registers()
self._scope.assign_names()
if peachpy.x86_64.options.abi is not None:
abi_function = self.finalize(peachpy.x86_64.options.abi)
for writer in peachpy.writer.active_writers:
writer.add_function(abi_function)
else:
raise
def attach(self):
"""Makes active the function and its associated instruction stream.
While the instruction stream is active, generated instructions are added to this function.
While the function is active, generated instructions are checked for compatibility with the function target.
"""
import peachpy.stream
import peachpy.common.function
if peachpy.common.function.active_function is not None:
raise ValueError("Can not attach the function: alternative function %s is active" %
peachpy.common.function.active_function.name)
if peachpy.stream.active_stream is not None:
raise ValueError("Can not attach the function instruction stream: alternative instruction stream is active")
peachpy.common.function.active_function = self
peachpy.stream.active_stream = self
return self
def detach(self):
"""Make the function and its associated instruction stream no longer active.
The function and its instruction stream must be active before calling the method.
"""
import peachpy.stream
import peachpy.common.function
if peachpy.common.function.active_function is None:
raise ValueError("Can not detach the function: no function is active")
if peachpy.common.function.active_function is not self:
raise ValueError("Can not detach the function: a different function is active")
peachpy.common.function.active_function = None
peachpy.stream.active_stream = None
return self
@staticmethod
def _check_arguments(args):
# Check types
if not isinstance(args, (list, tuple)):
raise TypeError("Invalid arguments types (%s): a tuple or list of function arguments expected" % str(args))
for i, arg in enumerate(args):
if not isinstance(arg, Argument):
raise TypeError("Invalid argument object for argument #%d (%s): peachpy.Argument expected" %
(i, str(arg)))
# mapping from argument name to argument number
names = dict()
# First check argument names for arguments with explicit names
for i, arg in enumerate(args):
if arg.name:
if arg.name in names:
raise ValueError("Argument #%d (%s) has the same name as argument #%d (%s)" %
(i, str(arg), names[arg.name], args[names[arg.name]]))
names[arg.name] = i
def _find_argument(self, argument_target):
from peachpy import Argument
assert isinstance(argument_target, (Argument, str)), \
"Either Argument object or argument name expected"
if isinstance(argument_target, Argument):
if argument_target in self.arguments:
return argument_target
else:
return None
else:
return next((argument for argument in self.arguments if argument.name == argument_target), None)
def add_instruction(self, instruction):
# If instruction is None, do nothing
if instruction is None:
return
from peachpy.x86_64.instructions import Instruction
if not isinstance(instruction, Instruction):
raise TypeError("Instruction object expected")
from peachpy.x86_64.pseudo import LABEL
# Check that label with the same name is not added twice
if isinstance(instruction, LABEL):
self._scope.add_scoped_name(instruction.identifier)
self._label_names.add(instruction.identifier)
constant = instruction.constant
if constant is not None:
self._scope.add_scoped_name(constant.name)
# Check that the instruction is supported by the target ISA
for extension in instruction.isa_extensions:
if self.target is not None and extension not in self.target.extensions:
raise ValueError("{0} is not supported on the target microarchitecture".format(extension))
instruction._indent_level = self._indent_level
self._instructions.append(instruction)
def add_instructions(self, instructions):
for instruction in instructions:
self.add_instruction(instruction)
def finalize(self, abi):
from peachpy.x86_64.abi import ABI
if not isinstance(abi, ABI):
raise TypeError("%s is not an ABI object" % str(abi))
return ABIFunction(self, abi)
def _add_default_labels(self):
"""Adds default labels if they are not defined"""
from peachpy.x86_64.pseudo import LABEL
if self.entry.name not in self._scope.names:
self._instructions.insert(0, LABEL(self.entry))
self._scope.add_scoped_name(self.entry.name)
self._label_names.add(self.entry.name)
def _check_undefined_labels(self):
"""Verifies that all labels referenced by branch instructions are defined"""
from peachpy.x86_64.instructions import BranchInstruction
referenced_label_names = set()
for instruction in self._instructions:
if isinstance(instruction, BranchInstruction) and instruction.label_name:
referenced_label_names.add(instruction.label_name)
if not referenced_label_names.issubset(self._label_names):
undefined_label_names = referenced_label_names.difference(self._label_names)
raise ValueError("Undefined labels found: " +
", ".join(map(lambda name: ".".join(map(str, name)), undefined_label_names)))
def _remove_unused_labels(self):
"""Removes labels that are not referenced by any instruction"""
from peachpy.x86_64.instructions import BranchInstruction
from peachpy.x86_64.pseudo import LABEL
referenced_label_names = set()
for instruction in self._instructions:
if isinstance(instruction, BranchInstruction) and instruction.label_name:
referenced_label_names.add(instruction.label_name)
unreferenced_label_names = self._label_names.difference(referenced_label_names)
# Do not remove entry label if it is in the middle of the function
if self.entry.name in unreferenced_label_names:
if not isinstance(self._instructions[0], LABEL) or self._instructions[0].identifier != self.entry.name:
unreferenced_label_names.remove(self.entry.name)
# Remove LABEL pseudo-instructions with unreferenced label names
self._instructions = [instruction for instruction in self._instructions
if not isinstance(instruction, LABEL) or
instruction.identifier not in unreferenced_label_names]
self._label_names.difference_update(unreferenced_label_names)
def _analize(self):
from peachpy.x86_64.instructions import BranchInstruction
from peachpy.x86_64.pseudo import LABEL, RETURN
from peachpy.x86_64.generic import RET
# Query input/output registers for each instruction
input_registers = []
output_registers = []
for instruction in self._instructions:
input_registers.append(instruction.input_registers_masks)
output_registers.append(instruction.output_registers_masks)
# Map from label name to its quasi-instruction number in the stream
labels = {instruction.identifier: i for (i, instruction)
in enumerate(self._instructions) if isinstance(instruction, LABEL)}
entry_position = 0
if self.entry.name in self._label_names:
entry_position = labels[self.entry.name]
branch_instructions = [(i, instruction) for (i, instruction) in enumerate(self._instructions) if
isinstance(instruction, BranchInstruction) and instruction.label_name]
# Basic blocks start at function entry position or on branch target
basic_block_starts = {entry_position}
for (i, branch_instruction) in branch_instructions:
basic_block_starts.add(labels[branch_instruction.label_name])
if branch_instruction.is_conditional:
basic_block_starts.add(i+1)
basic_block_starts = sorted(basic_block_starts)
# Basic block ends on a referenced label instruction or right after return/branch instructions
basic_block_ends = [i + int(not isinstance(instruction, LABEL)) for (i, instruction)
in enumerate(self._instructions) if
isinstance(instruction, (BranchInstruction, RETURN, RET, LABEL))]
# TODO: check that the last block with an unconditional branch/return instruction
basic_block_bounds = [(start, basic_block_ends[bisect.bisect_right(basic_block_ends, start)])
for start in basic_block_starts]
class BasicBlock:
def __init__(self, start_position, end_position, input_registers_list, output_registers_list):
self.start_position = start_position
self.end_position = end_position
self.input_registers_list = input_registers_list
self.output_registers_list = output_registers_list
self.consumed_register_masks = collections.defaultdict(int)
self.produced_register_masks = collections.defaultdict(int)
self.live_register_masks = collections.defaultdict(int)
self.available_register_masks = collections.defaultdict(int)
self.is_reachable = False
self.liveness_analysis_passes = 0
self.availability_analysis_passes = 0
self.input_blocks = list()
self.output_blocks = list()
self.processed_input_blocks = set()
self.processed_output_blocks = set()
# Mark available and consumed registers:
# - If a register is consumed by an instruction but not produced by preceding instructions of the basic
# block, the register is consumed by the basic block
# - If a register is produced by an instruction, it becomes available for the subsequent instructions
# of the basic block and counts as produced by the basic block
for (input_registers, output_registers) in zip(input_registers_list, output_registers_list):
for (input_register_id, input_register_mask) in six.iteritems(input_registers):
consumed_mask = input_register_mask & ~self.produced_register_masks[input_register_id]
if consumed_mask != 0:
self.consumed_register_masks[input_register_id] |= consumed_mask
for (output_register_id, output_register_mask) in six.iteritems(output_registers):
self.produced_register_masks[output_register_id] |= output_register_mask
def reset_processed_blocks(self):
self.processed_input_blocks = set()
self.processed_output_blocks = set()
@property
def available_registers_list(self):
from peachpy.x86_64.registers import Register
available_registers_list = []
available_registers_masks = self.available_register_masks.copy()
for output_registers in self.output_registers_list:
# Record available registers for current instruction
available_registers_list.append(available_registers_masks.copy())
# Update with output registers for current instruction
for (output_register_id, output_register_mask) in six.iteritems(output_registers):
available_registers_masks[output_register_id] = \
available_registers_masks.get(output_register_id, 0) | output_register_mask
return available_registers_list
@property
def live_registers_list(self):
from peachpy.x86_64.registers import Register
live_registers_list = []
live_registers_masks = self.live_register_masks.copy()
for (input_registers, output_registers) in \
reversed(list(zip(self.input_registers_list, self.output_registers_list))):
# Mark register written by the instruction as non-live
for (output_register_id, output_register_mask) in six.iteritems(output_registers):
if output_register_id in live_registers_masks:
new_live_register_mask = live_registers_masks[output_register_id] & ~output_register_mask
if new_live_register_mask != 0:
live_registers_masks[output_register_id] = new_live_register_mask
else:
del live_registers_masks[output_register_id]
# Mark registers read by the instruction as live
for (input_register_id, input_register_mask) in six.iteritems(input_registers):
live_registers_masks[input_register_id] = \
live_registers_masks.get(input_register_id, 0) | input_register_mask
# Record available registers for current instruction
live_registers_list.append(live_registers_masks.copy())
live_registers_list.reverse()
return live_registers_list
def __str__(self):
return "[%d, %d)" % (self.start_position, self.end_position)
def __repr__(self):
return str(self)
def analyze_availability(self, extra_available_registers):
self.availability_analysis_passes += 1
if self.availability_analysis_passes == 1:
# First pass: add registers produced by the block and propagate further
self.available_register_masks.update(extra_available_registers)
if self.output_blocks:
# Add registers produced by this block
for (produced_reg_id, produced_reg_mask) in six.iteritems(self.produced_register_masks):
extra_available_registers[produced_reg_id] =\
extra_available_registers.get(produced_reg_id, 0) | produced_reg_mask
else:
# Subsequent passes: compute and propagate only the input registers that were not processed before
for (reg_id, extra_reg_mask) in list(six.iteritems(extra_available_registers)):
old_reg_mask = self.available_register_masks[reg_id]
update_reg_mask = extra_reg_mask & ~old_reg_mask
if update_reg_mask != 0:
self.available_register_masks[reg_id] |= extra_reg_mask
if self.output_blocks:
if update_reg_mask != 0:
extra_available_registers[reg_id] = update_reg_mask
else:
del extra_available_registers[reg_id]
if self.output_blocks and (extra_available_registers or self.availability_analysis_passes == 1):
for output_block in self.output_blocks[1:]:
# The dict needs to be copied because output blocks can change it
output_block.analyze_availability(extra_available_registers.copy())
# Optimization: do not create a copy of the dict
self.output_blocks[0].analyze_availability(extra_available_registers)
def analyze_liveness(self, extra_live_registers):
# Update in liveness analysis consists of three steps:
# 1. Update live registers for this basic block.
# 2. Mark registers which are produced to by the basic block as non-live.
# 3. Mark registers which are consumed by the basic block as live (only on first pass).
self.liveness_analysis_passes += 1
# Steps 1 and 2
for (reg_id, extra_reg_mask) in list(six.iteritems(extra_live_registers)):
old_reg_mask = self.live_register_masks[reg_id]
update_reg_mask = extra_reg_mask & ~old_reg_mask
if update_reg_mask != 0:
self.live_register_masks[reg_id] |= extra_reg_mask
if self.input_blocks:
# On the first pass do not modify the extra live registers masks that are passed to input blocks
# On subsequent passes only the novel live registers need to be passed further
if self.liveness_analysis_passes == 1:
update_reg_mask = extra_reg_mask
update_reg_mask &= ~self.produced_register_masks.get(reg_id, 0)
if update_reg_mask != 0:
extra_live_registers[reg_id] = update_reg_mask
else:
del extra_live_registers[reg_id]
# Step 3
if self.input_blocks:
if self.liveness_analysis_passes == 1:
for (consumed_reg_id, consumed_reg_mask) in six.iteritems(self.consumed_register_masks):
extra_live_registers[consumed_reg_id] =\
extra_live_registers.get(consumed_reg_id, 0) | consumed_reg_mask
if self.input_blocks and (extra_live_registers or self.liveness_analysis_passes == 1):
for input_block in self.input_blocks[1:]:
# The dict needs to be copied because input blocks can change it
input_block.analyze_liveness(extra_live_registers.copy())
# Optimization: do not create a copy of the dict
self.input_blocks[0].analyze_liveness(extra_live_registers)
def analyze_reachability(self):
if not self.is_reachable:
self.is_reachable = True
for output_block in self.output_blocks:
output_block.analyze_reachability()
def forward_pass(self, processing_function, instructions, input_state):
output_state = processing_function(self, instructions, input_state)
for output_block in self.output_blocks:
if output_block.start_position not in self.processed_output_blocks:
self.processed_output_blocks.add(output_block.start_position)
output_block.forward_pass(processing_function, instructions, output_state)
def backward_pass(self, processing_function, instructions, input_state):
output_state = processing_function(self, instructions, input_state)
for input_block in self.input_blocks:
if input_block.start_position not in self.processed_input_blocks:
self.processed_input_blocks.add(input_block.start_position)
input_block.backward_pass(processing_function, instructions, output_state)
def propogate_sse_avx_state_forward(self, instructions, is_avx_environment):
from peachpy.x86_64.avx import VZEROALL, VZEROUPPER
from peachpy.x86_64.pseudo import LOAD, STORE
avx_state = True if is_avx_environment else None
def propogate_forward(block, instructions, avx_state):
for instruction in instructions[block.start_position:block.end_position]:
if isinstance(instruction, (VZEROUPPER, VZEROALL)):
avx_state = None
elif instruction.avx_mode is None:
# Instruction without a mode
if isinstance(instruction, (LOAD.ARGUMENT, STORE.RESULT, RETURN, RET, LABEL)):
# Some pseudo-instructions need AVX/SSE mode for lowering
instruction.avx_mode = avx_state
elif instruction.avx_mode:
# AVX-mode instruction
avx_state = True
else:
# SSE-mode instruction
if avx_state:
raise TypeError("AVX-mode instruction {0} follows an SSE-mode instruction".
format(instruction))
avx_state = False
return avx_state
self.forward_pass(propogate_forward, instructions, avx_state)
def propogate_sse_state_backward(self, instructions, is_avx_environment):
from peachpy.x86_64.pseudo import LOAD, STORE
avx_state = True if is_avx_environment else None
def propogate_sse_backward(block, instructions, avx_state):
for instruction in reversed(instructions[block.start_position:block.end_position]):
if instruction.avx_mode is not None:
avx_state = instruction.avx_mode
elif avx_state is not None and not avx_state:
if isinstance(instruction, (LOAD.ARGUMENT, STORE.RESULT, RETURN, RET, LABEL)):
instruction.avx_mode = avx_state
return avx_state
self.backward_pass(propogate_sse_backward, instructions, avx_state)
def propogate_avx_state_backward(self, instructions, is_avx_environment):
from peachpy.x86_64.pseudo import LOAD, STORE
avx_state = True if is_avx_environment else None
def propogate_avx_backward(block, instructions, avx_state):
for instruction in reversed(instructions[block.start_position:block.end_position]):
if instruction.avx_mode is not None:
avx_state = instruction.avx_mode
elif avx_state:
if isinstance(instruction, (LOAD.ARGUMENT, STORE.RESULT, RETURN, RET, LABEL)):
instruction.avx_mode = avx_state
self.backward_pass(propogate_avx_backward, instructions, avx_state)
basic_blocks = list(map(lambda start_end:
BasicBlock(start_end[0], start_end[1],
input_registers[start_end[0]:start_end[1]],
output_registers[start_end[0]:start_end[1]]),
basic_block_bounds))
# Map from block start position to BasicBlock object
basic_blocks_map = {basic_block_start: basic_block
for (basic_block_start, basic_block) in zip(basic_block_starts, basic_blocks)}
# Set output basic blocks for each basic block object
for (i, basic_block) in enumerate(basic_blocks):
# Consider last instruction of the basic block
last_instruction = self._instructions[basic_block.end_position - 1]
if isinstance(last_instruction, (RET, RETURN)):
# Basic block that ends with a return instruction has no output blocks
pass
elif isinstance(last_instruction, BranchInstruction) and last_instruction.label_name:
# Basic block that ends with a branch instruction can jump to the block at branch label
target_position = labels[last_instruction.label_name]
basic_block.output_blocks = [basic_blocks_map[target_position]]
if last_instruction.is_conditional:
# Basic blocks that end with a conditional branch instruction can fall through to the next block
basic_block.output_blocks.append(basic_blocks[i+1])
else:
# Basic block ends before a label and continues to the next basic block
basic_block.output_blocks = [basic_blocks[i+1]]
# Set input basic blocks for each basic block object
for basic_block in basic_blocks:
basic_block.input_blocks = list(filter(lambda bb: basic_block in bb.output_blocks, basic_blocks))
# Analyze which blocks can be reached from the entry point
basic_blocks_map[entry_position].analyze_reachability()
exit_positions = [block.start_position for block in basic_blocks if not block.output_blocks]
# Analyze register lifetime
basic_blocks_map[entry_position].analyze_availability(dict())
for exit_position in exit_positions:
basic_blocks_map[exit_position].analyze_liveness(dict())
# Analyze SSE/AVX mode
basic_blocks_map[entry_position].propogate_sse_avx_state_forward(self._instructions, self.avx_environment)
for exit_position in exit_positions:
basic_blocks_map[exit_position].propogate_sse_state_backward(self._instructions, self.avx_environment)
for basic_block in basic_blocks:
basic_block.reset_processed_blocks()
for exit_position in exit_positions:
basic_blocks_map[exit_position].propogate_avx_state_backward(self._instructions, self.avx_environment)
self._avx_prolog = self._instructions[entry_position].avx_mode
# Reconstruct live and available registers for the whole instruction sequence
for basic_block in basic_blocks:
for (instruction, available_registers, live_registers) in \
zip(self._instructions[basic_block.start_position:basic_block.end_position],
basic_block.available_registers_list, basic_block.live_registers_list):
instruction._live_registers = live_registers
instruction._available_registers = available_registers
# Remove referenced to input/output blocks to avoid memory leaks due to cycles in ref graph
basic_block.input_blocks = None
basic_block.output_blocks = None
# Analyze conflicting registers
output_registers = set()
for instruction in self._instructions:
instruction_registers = instruction.input_registers
instruction_registers.update(output_registers)
for instruction_register in instruction_registers:
if instruction_register.is_virtual:
conflict_internal_ids = [reg_id for (reg_id, reg_mask)
in six.iteritems(instruction._live_registers)
if reg_mask & instruction_register.mask != 0]
self._register_allocators[instruction_register.kind].add_conflicts(
instruction_register.virtual_id, conflict_internal_ids)
physical_registers = [r for r in instruction_registers
if not r.is_virtual]
if physical_registers:
from peachpy.x86_64.registers import Register
live_virtual_registers = \
Register._reconstruct_multiple({reg_id: reg_mask for (reg_id, reg_mask)
in six.iteritems(instruction._live_registers)
if reg_id < 0})
for live_virtual_register in live_virtual_registers:
conflict_internal_ids = [reg._internal_id for reg in physical_registers
if reg.mask & live_virtual_register.mask != 0]
self._register_allocators[live_virtual_register.kind].add_conflicts(
live_virtual_register.virtual_id, conflict_internal_ids)
output_registers = instruction.output_registers
def _check_live_registers(self):
"""Checks that the number of live registers does not exceed the number of physical registers for each insruction
"""
from peachpy.x86_64.registers import GeneralPurposeRegister, MMXRegister, XMMRegister, KRegister
max_live_registers = {
GeneralPurposeRegister._kind: 15,
MMXRegister._kind: 8,
XMMRegister._kind: 16,
KRegister._kind: 8
}
for instruction in self._instructions:
live_registers = max_live_registers.copy()
for reg in instruction.live_registers:
live_registers[reg.kind] -= 1
if any(surplus_count < 0 for surplus_count in six.itervalues(live_registers)):
if instruction.source_file is not None and instruction.line_number is not None:
raise peachpy.RegisterAllocationError(
"The number of live virtual registers exceeds physical constaints %s at %s:%d" %
(str(instruction), instruction.source_file, instruction.line_number))
else:
raise peachpy.RegisterAllocationError(
"The number of live virtual registers exceeds physical constaints %s" % str(instruction))
def _preallocate_registers(self):
"""Allocates registers that can be binded only to a single virtual register.
Several instructions accept only a fixed a register as their operand. If a virtual register is supplied as such
operand, it must be binded to the fixed register accepted by instruction encoding.
These instructions are:
- BLENDVPS xmm, xmm/m128, xmm0
- BLENDVPD xmm, xmm/m128, xmm0
- PBLENDVB xmm, xmm/m128, xmm0
- SHA256RNDS2 xmm, xmm/m128, xmm0
- SHR r/m, cl
- SAR r/m, cl
- SAL r/m, cl
- SHL r/m, cl
- ROR r/m, cl
- ROL r/m, cl
- SHRD r/m, r, cl
- SHLD r/m, r, cl
"""
from peachpy.x86_64.registers import GeneralPurposeRegister, XMMRegister, GeneralPurposeRegister8, xmm0, cl
from peachpy import RegisterAllocationError
cl_binded_registers = set()
xmm0_binded_registers = set()
for instruction in self._instructions:
if instruction.name in {"BLENDVPD", "BLENDVPS", "PBLENDVB", "SHA256RNDS2"}:
assert len(instruction.operands) == 3, \
"expected 3 operands, got %d (%s)" % \
(len(instruction.operands), ", ".join(map(str, instruction.operands)))
xmm0_operand = instruction.operands[2]
assert isinstance(xmm0_operand, XMMRegister), \
"expected xmm registers in the 3rd operand, got %s" % str(xmm0_operand)
if xmm0_operand.is_virtual:
# Check that xmm0 is not live at this instruction
if instruction._live_registers.get(xmm0._internal_id, 0) & XMMRegister._mask != 0:
raise RegisterAllocationError(
("Instruction %s requires operand 3 to be allocated to xmm0 register, " +
"but xmm0 is a live register") % str(instruction.name))
xmm0_binded_registers.add(xmm0_operand._internal_id)
elif instruction.name in {"SAL", "SAR", "SHL", "SHR", "ROL", "ROR", "RCL", "RCR"}:
assert len(instruction.operands) == 2, \
"expected 2 operands, got %d (%s)" % \
(len(instruction.operands), ", ".join(map(str, instruction.operands)))
count_operand = instruction.operands[1]
# The count operand can be cl or imm8
if isinstance(count_operand, GeneralPurposeRegister8) and count_operand.is_virtual:
# Check that cl is not live at this instruction
if instruction._live_registers.get(cl._internal_id, 0) & GeneralPurposeRegister8._mask != 0:
raise RegisterAllocationError(
"Instruction %s requires operand 2 to be allocated to cl register, " +
"but cl is a live register" % instruction.name)
cl_binded_registers.add(count_operand._internal_id)
elif instruction.name in {"SHLD", "SHRD"}:
assert len(instruction.operands) == 3, \
"expected 3 operands, got %d (%s)" % \
(len(instruction.operands), ", ".join(map(str, instruction.operands)))
count_operand = instruction.operands[2]
# The count operand can be cl or imm8
if isinstance(count_operand, GeneralPurposeRegister8) and count_operand.is_virtual:
# Check that cl is not live at this instruction
if instruction._live_registers.get(cl._internal_id, 0) & GeneralPurposeRegister8._mask != 0:
raise RegisterAllocationError(
"Instruction %s requires operand 3 to be allocated to cl register, " +
"but cl is a live register" % instruction.name)
cl_binded_registers.add(count_operand._internal_id)
# Check that cl-binded registers are not mutually conflicting
for cl_register in cl_binded_registers:
other_cl_registers = filter(operator.methodcaller("__ne__", cl_register), cl_binded_registers)
conflicting_registers = self._conflicting_registers[1][cl_register]
if any([other_register in conflicting_registers for other_register in other_cl_registers]):
raise RegisterAllocationError("Two conflicting virtual registers are requred to bind to cl")
# Check that xmm0-binded registers are not mutually conflicting
for xmm0_register in xmm0_binded_registers:
other_xmm0_registers = filter(operator.methodcaller("__ne__", xmm0_register), xmm0_binded_registers)
conflicting_registers = self._conflicting_registers[3][xmm0_register]
if any([other_register in conflicting_registers for other_register in other_xmm0_registers]):
raise RegisterAllocationError("Two conflicting virtual registers are requred to bind to xmm0")
# Commit register allocations
for cl_register in cl_binded_registers:
self._register_allocations[GeneralPurposeRegister._kind][cl_register] = cl.physical_id
for xmm0_register in xmm0_binded_registers:
self._register_allocations[XMMRegister._kind][xmm0_register] = xmm0.physical_id
def _bind_registers(self):
"""Iterates through the list of instructions and assigns physical IDs to allocated registers"""
for instruction in self._instructions:
for register in instruction.register_objects:
if register.is_virtual:
register.physical_id = \
self._register_allocators[register.kind].register_allocations.get(
register._internal_id, register.physical_id)
def _allocate_local_variable(self):
"""Returns a new unique ID for a local variable"""
self._local_variables_count += 1
return self._local_variables_count
def _allocate_mask_register_id(self):
"""Returns a new unique ID for a virtual mask (k) register"""
self._virtual_mask_registers_count += 1
return self._virtual_mask_registers_count
def _allocate_xmm_register_id(self):
"""Returns a new unique ID for a virtual SSE/AVX/AVX-512 (xmm/ymm/zmm) register"""
self._virtual_xmm_registers_count += 1
return self._virtual_xmm_registers_count
def _allocate_mmx_register_id(self):
"""Returns a new unique ID for a virtual MMX (mm) register"""
self._virtual_mmx_registers_count += 1
return self._virtual_mmx_registers_count
def _allocate_general_purpose_register_id(self):
"""Returns a new unique ID for a virtual general-purpose register"""
self._virtual_general_purpose_registers_count += 1
return self._virtual_general_purpose_registers_count
def __str__(self):
"""Returns string representation of the function signature and instructions"""
return self.format()
def format_instructions(self, line_separator=os.linesep):
"""Formats instruction listing including data on input, output, available and live registers"""
from peachpy.x86_64.pseudo import LABEL, ALIGN
code = []
tab = " " * 4
for instruction in self._instructions:
code.append(instruction.format("peachpy", indent=False))
if not isinstance(instruction, (LABEL, ALIGN)):
code.append(tab + "In regs: " + ", ".join(sorted(map(str, instruction.input_registers))))
code.append(tab + "Out regs: " + ", ".join(sorted(map(str, instruction.output_registers))))
code.append(tab + "Live regs: " + ", ".join(sorted(map(str, instruction.live_registers))))
code.append(tab + "Avail regs: " + ", ".join(sorted(map(str, instruction.available_registers))))
code.append("")
if line_separator is None:
return code
else:
return str(line_separator).join(code)
def format(self, line_separator=os.linesep):
"""Formats assembly listing of the function according to specified parameters"""
code = [self.c_signature]
for instruction in self._instructions:
code.append(instruction.format("peachpy", indent=True))
if line_separator is None:
return code
else:
return str(line_separator).join(code)
class Argument(peachpy.Argument):
def __init__(self, argument, abi):
"""Extends generic Argument object with x86-64 specific attributes required for stack frame construction
:ivar peachpy.x86_64.registers.Register register: the register in which the argument is passed to the function
or None if the argument is passed on stack.
:ivar int stack_offset: offset from the end of return address on the stack to the location of the argument on
stack or None if the argument is passed in a register and has no stack location. Note that in Microsoft X64
ABI the first four arguments are passed in registers but have stack space reserved for their storage.
For these arguments both register and stack_offset are non-null.
:ivar peachpy.x86_64.operand.MemoryAddress address: address of the argument on stack, relative to rsp or rbp.
The value of this attribute is None until after register allocation. In Golang ABIs this attribute is never
initialized because to load arguments from stack Golang uses its own pseudo-register FP, which is not
representable in PeachPy (LOAD.ARGUMENT pseudo-instructions use stack_offset instead when formatted as
Golang assembly).
"""
assert isinstance(argument, peachpy.Argument), \
"Architecture-specific argument must be constructed from generic Argument object"
from peachpy.x86_64.abi import ABI
assert isinstance(abi, ABI), "ABI object expected"
from copy import deepcopy
super(Argument, self).__init__(deepcopy(argument.c_type), argument.name)
if self.c_type.size is None:
self.c_type.size = self.c_type.get_size(abi)
self.abi = abi
self.register = None
self.address = None
self.stack_offset = None
self.save_on_stack = False
@property
def passed_on_stack(self):
return self.register is None
class ABIFunction:
"""ABI-specific x86-64 assembly function.
A function consists of C signature, ABI, and a list of instructions without virtual registers.
"""
def __init__(self, function, abi):
from peachpy.x86_64.abi import ABI, \
microsoft_x64_abi, system_v_x86_64_abi, linux_x32_abi, native_client_x86_64_abi, \
gosyso_amd64_abi, gosyso_amd64p32_abi, goasm_amd64_abi, goasm_amd64p32_abi
from copy import deepcopy
assert isinstance(function, Function), "Function object expected"
assert isinstance(abi, ABI), "ABI object expected"
self.name = function.name
self.arguments = [Argument(argument, abi) for argument in function.arguments]
self.result_type = function.result_type
self.result_offset = None
self.package = function.package
self.target = function.target
self.isa_extensions = function.isa_extensions
self.abi = abi
self.c_signature = function.c_signature
self.go_signature = function.go_signature
self.avx_environment = function.avx_environment
self._avx_prolog = function._avx_prolog
from peachpy.x86_64.registers import rsp
self._stack_base = rsp
self._stack_frame_size = 0
self._stack_frame_alignment = self.abi.stack_alignment
self._local_variables_size = 0
self._instructions = deepcopy(function._instructions)
self._register_allocators = deepcopy(function._register_allocators)
if abi == microsoft_x64_abi:
self._setup_windows_arguments()
elif abi in {system_v_x86_64_abi, linux_x32_abi, native_client_x86_64_abi}:
self._setup_unix_arguments()
elif abi in {gosyso_amd64_abi, gosyso_amd64p32_abi, goasm_amd64_abi, goasm_amd64p32_abi}:
self._setup_golang_arguments()
else:
raise ValueError("Unsupported ABI: %s" % str(abi))
self._update_argument_loads(function.arguments)
self._layout_local_variables()
self._allocate_registers()
self._bind_registers()
self._clobbered_registers = self._analyze_clobbered_registers()
self._update_stack_frame()
self._update_argument_addresses()
self._lower_argument_loads()
self._lower_pseudoinstructions()
self._filter_instruction_encodings()
self.mangled_name = self.mangle_name()
def _update_argument_loads(self, arguments):
from peachpy.x86_64.pseudo import LOAD
for instruction in self._instructions:
if isinstance(instruction, LOAD.ARGUMENT):
instruction.operands = \
(instruction.operands[0], self.arguments[arguments.index(instruction.operands[1])])
if instruction.operands[1].register in instruction.available_registers:
instruction.operands[1].save_on_stack = True
def _setup_windows_arguments(self):
from peachpy.x86_64.abi import microsoft_x64_abi
assert self.abi == microsoft_x64_abi, \
"This function must only be used with Microsoft x64 ABI"
# The first 4 arguments are passed in registers, others are on stack.
# 8 bytes on stack is reserved for each parameter (regardless of their size).
# On-stack space is also reserved, but not initialized, for parameters passed in registers.
# Arguments are NOT extended to 8 bytes, and high bytes of registers/stack cells may contain garbage.
from peachpy.x86_64 import m64
from peachpy.x86_64.registers import rcx, rdx, r8, r9, xmm0, xmm1, xmm2, xmm3
floating_point_argument_registers = (xmm0, xmm1, xmm2, xmm3)
integer_argument_registers = (rcx, rdx, r8, r9)
for (index, argument) in enumerate(self.arguments):
argument.passed_by_reference = argument.is_vector and argument != m64
if index < 4:
if argument.is_floating_point:
argument.register = floating_point_argument_registers[index]
elif argument.is_integer or \
argument.is_pointer or \
argument.is_codeunit or \
argument.is_mask or \
argument.c_type == m64:
argument_register = integer_argument_registers[index]
argument.register = {
1: argument_register.as_low_byte,
2: argument_register.as_word,
4: argument_register.as_dword,
8: argument_register
}[argument.size]
elif argument.is_vector:
argument.register = integer_argument_registers[index]
else:
assert False
# Stack offset does not include return address
argument.stack_offset = index * 8
def _setup_unix_arguments(self):
from peachpy.x86_64.abi import system_v_x86_64_abi, linux_x32_abi, native_client_x86_64_abi
assert self.abi in {system_v_x86_64_abi, linux_x32_abi, native_client_x86_64_abi}, \
"This function must only be used with System V x86-64, Linux x32 or Native Client x86-64 SFI ABI"
from peachpy.x86_64.registers import rdi, rsi, rdx, rcx, r8, r9, \
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
# The first 6 integer/pointer arguments are passed in general-purpose registers.
# The first 8 floating-point arguments are passed in SSE registers.
# For all integer arguments in excess of 6 and floating-point arguments in excess the caller reserves
# 8 bytes on stack.
# Arguments smaller than 4 bytes are extended (with sign-extension, if needed) to 4 bytes.
# For 4-byte and smaller arguments passed on stack the high 4 bytes are not initialized.
# For 4-byte and smaller arguments passed in registers the high 4 bytes are zero-initialized.
# X32 and Native Client ABIs were not much tested, but they seem similar
available_floating_point_registers = [xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7]
available_integer_registers = [rdi, rsi, rdx, rcx, r8, r9]
# Stack offset does not include return address
stack_offset = 0
for argument in self.arguments:
if (argument.is_floating_point or argument.is_vector) and len(available_floating_point_registers) > 0:
argument.register = available_floating_point_registers.pop(0)
if argument.size in {4, 8, 16}:
pass
elif argument.size == 32:
argument.register = argument.register.as_ymm
elif argument.size == 64:
argument.register = argument.register.as_zmm
else:
assert False
elif (argument.is_integer or argument.is_pointer or argument.is_codeunit) \
and len(available_integer_registers) > 0:
argument_register = available_integer_registers.pop(0)
argument.register = {
1: argument_register.as_dword,
2: argument_register.as_dword,
4: argument_register.as_dword,
8: argument_register
}[argument.size]
elif argument.is_vector or argument.is_mask:
assert False
else:
argument.stack_offset = stack_offset
stack_offset += 8
def _setup_golang_arguments(self):
from peachpy.x86_64.abi import gosyso_amd64_abi, gosyso_amd64p32_abi, goasm_amd64_abi, goasm_amd64p32_abi
assert self.abi in {gosyso_amd64_abi, gosyso_amd64p32_abi, goasm_amd64_abi, goasm_amd64p32_abi}, \
"This function must only be used with Golang AMD64 or AMD64p32 ABI"
from peachpy.util import roundup
# All arguments are passed on stack
# Stack offset does not include the return address
stack_offset = 0
for index, argument in enumerate(self.arguments):
# Arguments are aligned on stack
stack_offset = roundup(stack_offset, argument.size)
argument.stack_offset = stack_offset
stack_offset += argument.size
if self.result_type is not None:
self.result_offset = roundup(stack_offset, self.result_type.size)
def _layout_local_variables(self):
from peachpy.x86_64.registers import rsp
local_variables_set = set()
local_variables_list = list()
for instruction in self._instructions:
local_variable = instruction.local_variable
if local_variable is not None:
local_variable = local_variable.root
if local_variable not in local_variables_set:
local_variables_set.add(local_variable)
local_variables_list.append(local_variable)
if local_variables_list:
local_variables_list = list(sorted(local_variables_list, key=lambda var: var.size))
self._stack_frame_alignment = max(var.alignment for var in local_variables_list)
local_variable_address = 0
from peachpy.util import roundup
for local_variable in local_variables_list:
local_variable_address = roundup(local_variable_address, local_variable.alignment)
local_variable._address = local_variable_address
local_variable_address += local_variable.size
self._local_variables_size = local_variable_address
for instruction in self._instructions:
local_variable = instruction.local_variable
if local_variable is not None:
assert local_variable.address is not None
memory_address = instruction.memory_address
assert memory_address is not None
assert memory_address.base == rsp
instruction.memory_address.displacement = local_variable.address
def _allocate_registers(self):
for register_kind, register_allocator in six.iteritems(self._register_allocators):
register_allocator.set_allocation_options(self.abi, register_kind)
from peachpy.x86_64.pseudo import LOAD
from peachpy.x86_64.registers import Register, GeneralPurposeRegister, MMXRegister, XMMRegister, KRegister
for instruction in self._instructions:
if isinstance(instruction, LOAD.ARGUMENT):
dst_reg = instruction.operands[0]
src_arg = instruction.operands[1]
assert isinstance(dst_reg, Register)
assert isinstance(src_arg, Argument)
if dst_reg.is_virtual and src_arg.register is not None:
self._register_allocators[dst_reg.kind]\
.try_allocate_register(dst_reg.virtual_id, src_arg.register.physical_id)
for register_allocator in six.itervalues(self._register_allocators):
register_allocator.allocate_registers()
def _lower_argument_loads(self):
from peachpy.x86_64.pseudo import LOAD
from peachpy.x86_64.abi import goasm_amd64_abi, goasm_amd64p32_abi
from peachpy.x86_64.registers import GeneralPurposeRegister, MMXRegister, XMMRegister, YMMRegister
from peachpy.x86_64.lower import load_register, load_memory
if self.abi == goasm_amd64_abi or self.abi == goasm_amd64p32_abi:
# Like PeachPy, Go assembler uses pseudo-instructions for argument loads
return
lowered_instructions = []
for (i, instruction) in enumerate(self._instructions):
if isinstance(instruction, LOAD.ARGUMENT):
assert isinstance(instruction.operands[0],
(GeneralPurposeRegister, MMXRegister, XMMRegister, YMMRegister)), \
"Lowering LOAD.ARGUMENT is supported only for general-purpose, mmx, xmm, and ymm target registers"
if instruction.operands[1].register is not None:
# The argument is passed to function in a register
ld_reg = load_register(instruction.operands[0],
instruction.operands[1].register,
instruction.operands[1].c_type,
prototype=instruction)
if ld_reg is not None:
lowered_instructions.append(ld_reg)
else:
# The argument is passed to function on stack
ld_mem = load_memory(instruction.operands[0],
instruction.operands[1].address,
instruction.operands[1].c_type,
prototype=instruction)
lowered_instructions.append(ld_mem)
else:
lowered_instructions.append(instruction)
self._instructions = lowered_instructions
def _lower_pseudoinstructions(self):
from peachpy.x86_64.pseudo import RETURN, STORE
from peachpy.x86_64.mmxsse import MOVAPS
from peachpy.x86_64.avx import VMOVAPS, VZEROUPPER
from peachpy.x86_64.generic import PUSH, SUB, ADD, XOR, MOV, POP, RET, AND, LEA
from peachpy.x86_64.nacl import NACLJMP, NACLRESTBP, NACLRESTSP, NACLASP, NACLSSP
from peachpy.x86_64.lower import load_register
from peachpy.x86_64.abi import native_client_x86_64_abi, \
gosyso_amd64_abi, gosyso_amd64p32_abi, goasm_amd64_abi, goasm_amd64p32_abi
from peachpy.x86_64.registers import GeneralPurposeRegister64, XMMRegister, rsp, rbp, eax
from peachpy.util import is_uint32, is_sint32, is_int
from peachpy.stream import InstructionStream
# The new list with lowered instructions
instructions = list()
# Generate prologue
cloberred_xmm_registers = list()
cloberred_general_purpose_registers = list()
with InstructionStream() as prolog_stream:
# 1. Save clobbered general-purpose registers with PUSH instruction
# 2. If there are clobbered XMM registers, allocate space for them on stack (subtract stack pointer)
# 3. Save clobbered XMM registers on stack with (V)MOVAPS instruction
for reg in self._clobbered_registers:
assert isinstance(reg, (GeneralPurposeRegister64, XMMRegister)), \
"Internal error: unexpected register %s in clobber list" % str(reg)
if isinstance(reg, GeneralPurposeRegister64):
cloberred_general_purpose_registers.append(reg)
PUSH(reg)
else:
cloberred_xmm_registers.append(reg)
# If stack needs to be realigned
if self._stack_frame_alignment > self.abi.stack_alignment:
cloberred_general_purpose_registers.append(rbp)
PUSH(rbp)
MOV(rbp, rsp)
if cloberred_xmm_registers or self._local_variables_size != 0:
# Total size of the stack frame less what is already adjusted with PUSH instructions
stack_adjustment = \
self._stack_frame_size - len(cloberred_general_purpose_registers) * GeneralPurposeRegister64.size
if self.abi != native_client_x86_64_abi:
SUB(rsp, stack_adjustment + self._local_variables_size)
if self._stack_frame_alignment > self.abi.stack_alignment:
AND(rsp, -self._stack_frame_alignment)
else:
if self._stack_frame_alignment > self.abi.stack_alignment:
# Note: do not modify rcx/rdx/r8/r9 as they may contain function arguments
LEA(eax, [rsp - (stack_adjustment + self._local_variables_size)])
AND(eax, -self._stack_frame_alignment)
NACLRESTSP(eax)
else:
NACLSSP(stack_adjustment + self._local_variables_size)
for i, xmm_reg in enumerate(cloberred_xmm_registers):
movaps = VMOVAPS if self._avx_prolog else MOVAPS
movaps([rsp + self._local_variables_size + i * XMMRegister.size], xmm_reg)
# TODO: handle situations when entry point is in the middle of a function
instructions.extend(prolog_stream.instructions)
for instruction in self._instructions:
if isinstance(instruction, RETURN):
from peachpy.x86_64.registers import GeneralPurposeRegister, MMXRegister, XMMRegister, YMMRegister, \
rax, eax, ax, al, rcx, ecx, mm0, xmm0, ymm0
is_goasm_abi = self.abi in {goasm_amd64_abi, goasm_amd64p32_abi}
is_gosyso_abi = self.abi in {gosyso_amd64_abi, gosyso_amd64p32_abi}
with InstructionStream() as epilog_stream:
# Save return value
if instruction.operands:
assert len(instruction.operands) == 1
if is_int(instruction.operands[0]):
assert self.result_type.is_integer or self.result_type.is_pointer
# Return immediate constant
if is_goasm_abi:
# Return value must be saved on stack with STORE.RESULT pseudo-instruction
if self.result_type.size <= 4 or is_sint32(instruction.operands[0]):
# STORE.RESULT will assemble to one of the forms:
# - MOV m8, imm8
# - MOV m16, imm16
# - MOV m32, imm32
# - MOV m64, imm32
STORE.RESULT(instruction.operands[0], prototype=instruction, target_function=self)
else:
# STORE.RESULT can't be used directly (MOV m64, imm64 doesn't exist), instead use
# MOV rax, imm64 + MOV m64, rax (STORE.RESULT)
MOV(eax, instruction.operands[0], prototype=instruction)
STORE.RESULT(eax, prototype=instruction, target_function=self)
else:
# Return value is returned in:
# - eax register if result type is not greater than 4 bytes
# - rax register if result type is greater than 8 bytes
if instruction.operands[0] == 0:
# - Zero eax register (high 32 bits of rax register clear automatically)
XOR(eax, eax, prototype=instruction)
elif self.result_type.size <= 4 or is_uint32(instruction.operands[0]):
# - If the result type is not greater than 4 bytes, directly mov it to eax register
# - If the result type is greater than 4 bytes, but the result value is
# representable as unsigned 32-bit literal, mov it to eax register and the high
# 32 bits of rax will be cleared automatically
MOV(eax, instruction.operands[0], prototype=instruction)
else:
# - Either negative 32-bit constant (would use MOV rax, imm32 form)
# - Or large 64-bit constant (would use MOV rax, imm64 form)
MOV(rax, instruction.operands[0], prototype=instruction)
elif isinstance(instruction.operands[0], GeneralPurposeRegister):
if is_goasm_abi and instruction.operands[0].size == self.result_type.size:
STORE.RESULT(instruction.operands[0], prototype=instruction, target_function=self)
else:
result_reg = eax if self.result_type.size <= 4 else rax
epilog_stream.add_instruction(load_register(result_reg,
instruction.operands[0],
self.result_type,
prototype=instruction))
if is_goasm_abi:
result_subreg = {
1: al,
2: ax,
4: eax,
8: rax
}[self.result_type.size]
STORE.RESULT(result_subreg, prototype=instruction, target_function=self)
elif isinstance(instruction.operands[0], MMXRegister):
epilog_stream.add_instruction(load_register(mm0,
instruction.operands[0],
self.result_type,
prototype=instruction))
elif isinstance(instruction.operands[0], XMMRegister):
if self.result_type.is_floating_point and is_goasm_abi:
assert self.result_type.size in {4, 8}
STORE.RESULT(instruction.operands[0], prototype=instruction, target_function=self)
else:
epilog_stream.add_instruction(load_register(xmm0,
instruction.operands[0],
self.result_type,
prototype=instruction))
elif isinstance(instruction.operands[0], YMMRegister):
epilog_stream.add_instruction(load_register(ymm0,
instruction.operands[0],
self.result_type,
prototype=instruction))
else:
assert False
if instruction.avx_mode and not self.avx_environment:
VZEROUPPER(prototype=instruction)
# Generate epilog
# 1. Restore clobbered XMM registers on stack with (V)MOVAPS instruction
# 2. If there are clobbered XMM registers, release their space on stack (increment stack pointer)
# 3. Restore clobbered general-purpose registers with PUSH instruction
for i, xmm_reg in enumerate(cloberred_xmm_registers):
movaps = VMOVAPS if self.avx_environment else MOVAPS
movaps(xmm_reg, [rsp + self._local_variables_size + i * XMMRegister.size])
if self._stack_frame_alignment > self.abi.stack_alignment:
# Restore rsp value from rbp
MOV(rsp, rbp)
elif cloberred_xmm_registers or self._local_variables_size != 0:
# Total size of the stack frame less what will be adjusted with POP instructions
stack_adjustment = self._stack_frame_size - \
len(cloberred_general_purpose_registers) * GeneralPurposeRegister64.size
if self.abi != native_client_x86_64_abi:
ADD(rsp, stack_adjustment + self._local_variables_size)
else:
NACLASP(stack_adjustment + self._local_variables_size)
# Important: registers must be POPed in reverse order
for reg in reversed(cloberred_general_purpose_registers):
if reg == rbp and self.abi == native_client_x86_64_abi:
POP(rcx)
NACLRESTBP(ecx)
else:
POP(reg)
# Return from the function
if self.abi == native_client_x86_64_abi:
POP(rcx, prototype=instruction)
NACLJMP(ecx)
else:
RET(prototype=instruction)
instructions.extend(epilog_stream.instructions)
elif isinstance(instruction, STORE.RESULT):
instruction.destination_offset = self.result_offset
instructions.append(instruction)
else:
if self.abi == native_client_x86_64_abi and instruction.name != "LEA":
from peachpy.x86_64.operand import is_m
memory_operands = list(filter(lambda op: is_m(op), instruction.operands))
if memory_operands:
assert len(memory_operands) == 1, \
"x86-64 instructions can not have more than 1 explicit memory operand"
memory_address = memory_operands[0].address
from peachpy.x86_64.operand import MemoryAddress
if isinstance(memory_address, MemoryAddress):
if memory_address.index is not None:
raise ValueError("NaCl does not allow index addressing")
from peachpy.x86_64.registers import rbp, rsp, r15
if memory_address.base is not None and memory_address.base not in {rbp, rsp, r15}:
# Base register is not a restricted register: needs transformation
memory_address.index = memory_address.base
memory_address.scale = 1
memory_address.base = r15
instructions.append(instruction)
self._instructions = instructions
def _filter_instruction_encodings(self):
for instruction in self._instructions:
instruction.encodings = instruction._filter_encodings()
def _update_argument_addresses(self):
for argument in self.arguments:
if argument.stack_offset is not None:
argument.address = self._argument_stack_base + argument.stack_offset
def _analyze_clobbered_registers(self):
from peachpy.x86_64.registers import GeneralPurposeRegister, XMMRegister, YMMRegister, ZMMRegister
output_subregisters = set()
for instruction in self._instructions:
output_subregisters.update(instruction.output_registers)
output_registers = set()
for subreg in output_subregisters:
if isinstance(subreg, GeneralPurposeRegister):
output_registers.add(subreg.as_qword)
elif isinstance(subreg, (XMMRegister, YMMRegister, ZMMRegister)):
output_registers.add(subreg.as_xmm)
# Other register types are volatile registers for all x86-64 ABIs
return list(sorted(filter(lambda reg: reg in self.abi.callee_save_registers, output_registers)))
def _update_stack_frame(self):
from peachpy.x86_64.registers import GeneralPurposeRegister64, XMMRegister, rbp, rsp
clobbered_general_purpose_registers = 0
clobbered_xmm_registers = 0
for reg in self._clobbered_registers:
assert isinstance(reg, (GeneralPurposeRegister64, XMMRegister)), \
"Internal error: unexpected register %s in clobber list" % str(reg)
if isinstance(reg, GeneralPurposeRegister64):
clobbered_general_purpose_registers += 1
else:
clobbered_xmm_registers += 1
# If the stack needs to be aligned, rbp register needs to be preserved too
if self._stack_frame_alignment > self.abi.stack_alignment:
clobbered_general_purpose_registers += 1
self._stack_frame_size = \
clobbered_general_purpose_registers * GeneralPurposeRegister64.size + \
clobbered_xmm_registers * XMMRegister.size
# 1. On function entry stack is misaligned by 8
# 2. Each clobbered general-purpose register is pushed as 8 bytes
# 3. If the number of clobbered general-purpose registers is odd, the stack will be misaligned by 8 after they
# are pushed on stack
# 4. If additionally there are clobbered XMM registers, we need to subtract 8 from stack to make it aligned
# by 16 after the general-purpose registers are pushed
if (clobbered_xmm_registers != 0 or self._local_variables_size != 0) and clobbered_general_purpose_registers % 2 == 0:
self._stack_frame_size += 8
# Set stack_argument_base
return_address_size = 8
if self._stack_frame_alignment > self.abi.stack_alignment:
# rsp is realigned, argument addressing uses rbp
saved_rbp_size = 8
self._argument_stack_base = rbp + return_address_size + saved_rbp_size
else:
# argument addressing uses rsp
self._argument_stack_base = rsp + return_address_size + self._stack_frame_size + self._local_variables_size
def _bind_registers(self):
"""Iterates through the list of instructions and assigns physical IDs to allocated registers"""
for instruction in self._instructions:
for register in instruction.register_objects:
if register.is_virtual:
register.physical_id = \
self._register_allocators[register.kind].register_allocations[register.virtual_id]
def format_code(self, assembly_format="peachpy", line_separator=os.linesep, indent=True, line_number=1):
"""Returns code of assembly instructions comprising the function"""
code = []
if assembly_format == "gas":
# Pre-assign line number to labels
from peachpy.x86_64.pseudo import LABEL
for i, instruction in enumerate(self._instructions):
if isinstance(instruction, LABEL):
instruction.operands[0].line_number = line_number + i
for i, instruction in enumerate(self._instructions):
from peachpy.x86_64.instructions import Instruction
# if isinstance(instruction, Instruction):
# try:
# hex_string = " ".join("%02X" % byte for byte in instruction.encode())
# code.append(" " + "# " + hex_string)
# except Exception as e:
# import sys
# code.append(e.message)
# # raise
code.append(instruction.format(assembly_format=assembly_format, indent=indent, line_number=line_number + i))
if line_separator is None:
return code
else:
return str(line_separator).join(code)
def format(self, assembly_format="peachpy", line_separator=os.linesep, line_number=1):
"""Formats assembly listing of the function according to specified parameters"""
if assembly_format == "go":
# Arguments for TEXT directive in Go assembler
package_string = self.package
if package_string is None:
package_string = ""
if six.PY2:
text_arguments = [package_string + "\xC2\xB7" + self.mangled_name + "(SB)"]
else:
text_arguments = [package_string + "\u00B7" + self.mangled_name + "(SB)"]
text_arguments.append("4")
stack_size = sum(map(operator.attrgetter("size"), self.arguments))
if self.result_offset is not None:
stack_size = self.result_offset + self.result_type.size
if stack_size == 0:
text_arguments.append("$0")
else:
text_arguments.append("$0-%d" % stack_size)
code = ["TEXT " + ",".join(text_arguments)]
if self.go_signature is not None:
code.insert(0, "// " + self.go_signature)
elif assembly_format == "gas":
from peachpy.util import ilog2
code_alignment = 16
code = [
"#ifdef __APPLE__",
".section __TEXT,__text,regular,pure_instructions",
".globl _{name}".format(name=self.mangled_name),
".p2align {ilog2alignment}, 0x90".format(
ilog2alignment=ilog2(code_alignment)),
"_{name}:".format(name=self.mangled_name),
"#else /* !__APPLE__ */",
".text",
".p2align {ilog2alignment},,{max_alignment_bytes}".format(
ilog2alignment=ilog2(code_alignment),
max_alignment_bytes=code_alignment - 1),
".globl " + self.mangled_name,
".type {name}, @function".format(name=self.mangled_name),
"{name}:".format(name=self.mangled_name),
"#endif /* !__APPLE */",
]
else:
code = []
code += self.format_code(assembly_format, line_separator=None, indent=True, line_number=line_number + len(code))
if assembly_format == "gas":
code += [
"#ifndef __APPLE__",
".size {name}, .-{name}".format(name=self.mangled_name),
"#endif /* !__APPLE__ */",
]
if assembly_format in ["go", "gas"]:
# Add trailing line or assembler will refuse to compile
code.append("")
if line_separator is None:
return code
else:
return str(line_separator).join(code)
def encode(self):
return EncodedFunction(self)
@property
def metadata(self):
metadata = collections.OrderedDict([
("entry", "function"),
("name", self.name),
("symbol", self.mangled_name),
("return", "void" if self.result_type is None else str(self.result_type)),
("arguments", [collections.OrderedDict([
("name", argument.name),
("type", str(argument.c_type))]) for argument in self.arguments]),
("arch", "x86-64"),
("abi", str(self.abi)),
("uarch", self.target.name),
("isa", [str(extension) for extension in self.isa_extensions.minify()])
])
return metadata
def mangle_name(self):
import peachpy.x86_64.options
import string
name = peachpy.x86_64.options.name_mangling \
.replace("${Name}", self.name) \
.replace("${name}", self.name.lower()) \
.replace("${NAME}", self.name.upper()) \
.replace("${uArch}", self.target.id) \
.replace("${uarch}", self.target.id.lower()) \
.replace("${UARCH}", self.target.id.upper()) \
.replace("${ISA}", "_".join([extension.safe_name for extension in self.isa_extensions.minify()])) \
.replace("${isa}", "_".join([extension.safe_name.lower() for extension in self.isa_extensions.minify()]))
return name
class InstructionBundle:
def __init__(self, capacity, address):
if capacity not in {16, 32, 64}:
raise ValueError("Bundle capacity must be 16, 32, or 64")
self.capacity = capacity
self.address = address
self.size = 0
self._instructions = []
# Map from instruction position to tuple (label address, long encoding, short range)
self.branch_info_map = dict()
@property
def padding(self):
return self.capacity - self.size
def add(self, instructions):
from peachpy.x86_64.instructions import Instruction
assert isinstance(instructions, list)
assert all(isinstance(instruction, Instruction) for instruction in instructions), \
"Instruction instance expected"
bytecode = bytearray().join([instruction.encode() for instruction in instructions])
if self.size + len(bytecode) <= self.capacity:
self.size += len(bytecode)
for instruction in instructions:
instruction.bytecode = instruction.encode()
self._instructions.append(instruction)
else:
raise BufferError()
def add_label_branch(self, instruction, label_address=None, long_encoding=False):
from peachpy.x86_64.instructions import BranchInstruction
assert isinstance(instruction, BranchInstruction), \
"BranchInstruction instance expected"
long_encoding, bytecode = instruction._encode_label_branch(self.address + self.size, label_address, long_encoding)
if self.capacity - self.size > len(bytecode):
self.size += len(bytecode)
if not long_encoding and label_address is not None:
# offset = label_address - self.end_address
# -> self.end_address = label_address - offset
# -> branch_address = label_address - len(bytecode) - offset
# -> branch_position = label_address - self.start_address - len(bytecode) - offset
#
# -> branch_pos >= label_address - self.start_address - len(bytecode) - 127
# -> branch_pos <= label_address - self.start_address - len(bytecode) + 128
branch_pos = label_address - self.address - len(bytecode)
branch_pos_max = min(branch_pos + 128, self.capacity)
else:
branch_pos_max = self.capacity
instruction.bytecode = bytecode
self.branch_info_map[len(self._instructions)] = (label_address, long_encoding, branch_pos_max)
self._instructions.append(instruction)
else:
raise BufferError()
def optimize(self):
from peachpy.x86_64.instructions import BranchInstruction
from peachpy.x86_64.pseudo import LABEL
if any(isinstance(instruction, (BranchInstruction, LABEL)) for instruction in self._instructions):
return
def suitable_encodings(instruction):
return [(encoding, length) for (length, encoding) in six.iteritems(instruction.encode_length_options())
if 0 < length - len(instruction.bytecode) <= self.padding]
while self.size < self.capacity:
suitable_instructions = [instr for instr in self._instructions if any(suitable_encodings(instr))]
if not suitable_instructions:
break
shortest_suitable_instruction = min(suitable_instructions, key=lambda instr: len(instr.bytecode))
new_encoding, new_length = min(suitable_encodings(shortest_suitable_instruction),
key=operator.itemgetter(1))
self.size += new_length - len(shortest_suitable_instruction.bytecode)
assert self.size <= self.capacity
shortest_suitable_instruction.bytecode = new_encoding
def finalize(self):
from peachpy.x86_64.generic import NOP
while self.capacity > self.size:
self.add([NOP()])
self.size = self.capacity
@property
def label_address_map(self):
from peachpy.x86_64.pseudo import LABEL
label_address_map = dict()
code_address = self.address
for instruction in self._instructions:
if isinstance(instruction, LABEL):
label_address_map[instruction.identifier] = code_address
else:
code_address += len(instruction.bytecode)
return label_address_map
def __len__(self):
return self.size
class EncodedFunction:
"""ABI-specific x86-64 assembly function.
A function consists of C signature, ABI, and a list of instructions without virtual registers.
"""
def __init__(self, function):
from copy import copy, deepcopy
assert isinstance(function, ABIFunction), "ABIFunction object expected"
self.name = function.name
self.mangled_name = function.mangled_name
self.arguments = list(map(copy, function.arguments))
self.result_type = function.result_type
self.target = function.target
self.abi = function.abi
from peachpy.x86_64.meta import Section, SectionType
from peachpy.x86_64.abi import native_client_x86_64_abi
if self.abi == native_client_x86_64_abi:
# Align with HLT instruction
self.code_section = Section(SectionType.code, alignment_byte=0xF4)
self.code_section.alignment = 32
else:
# Align with INT 3 instruction
self.code_section = Section(SectionType.code, alignment_byte=0xCC)
self.code_section.alignment = 16
self.const_section = Section(SectionType.const_data)
self._instructions = deepcopy(function._instructions)
self._constant_symbol_map = dict()
self._layout_literal_constants()
self._encode()
def _layout_literal_constants(self):
from peachpy.encoder import Encoder
from peachpy.x86_64.meta import Symbol, SymbolType
encoder = Encoder(self.abi.endianness)
constants = list()
for instruction in self._instructions:
constant = instruction.constant
if constant is not None:
constants.append(constant)
max_constant_size = 0
max_constant_alignment = 0
if constants:
max_constant_size = max(constant.size for constant in constants)
max_constant_alignment = max(constant.alignment for constant in constants)
self.const_section.alignment = max_constant_alignment
# Unsorted list of Symbol objects for constants
constant_symbols = list()
# This set is used to ensure that each constant is added only once
constant_names_set = set()
if max_constant_size != 0:
# Map from constant value (as bytes) to address in the const data section
constants_address_map = dict()
for instruction in self._instructions:
constant = instruction.constant
if constant is not None:
constant_value = bytes(constant.encode(encoder))
if constant_value not in constants_address_map:
# Add the new constant to the section
assert constant.size == max_constant_size, \
"Handling of functions with constant literals of different size is not implemented"
assert constant.alignment == max_constant_alignment, \
"Handling of functions with constant literals of different alignment is not implemented"
constants_address_map[constant_value] = len(self.const_section)
self.const_section.content += constant_value
if constant.name not in constant_names_set:
constant_names_set.add(constant.name)
const_symbol = Symbol(constants_address_map[constant_value],
SymbolType.literal_constant,
name=constant.name,
size=constant.size)
constant_symbols.append(const_symbol)
self._constant_symbol_map[constant.name] = const_symbol
for constant_symbol in sorted(constant_symbols, key=lambda sym: (sym.offset, -sym.size)):
self.const_section.add_symbol(constant_symbol)
def _encode(self):
from peachpy.x86_64.pseudo import LABEL
from peachpy.x86_64.instructions import BranchInstruction
label_address_map = dict()
long_branches = set()
# Special post-processing for Native Client SFI
from peachpy.x86_64.abi import native_client_x86_64_abi
if self.abi == native_client_x86_64_abi:
has_updated_branches = True
has_unresolved_labels = True
bundles = list()
while has_updated_branches or has_unresolved_labels:
code_address = 0
has_updated_branches = False
has_unresolved_labels = False
bundles = list()
current_bundle = InstructionBundle(32, code_address)
for (i, instruction) in enumerate(self._instructions):
if isinstance(instruction, LABEL):
label_address_map[instruction.identifier] = code_address
current_bundle.add([instruction])
elif isinstance(instruction, BranchInstruction) and instruction.label_name:
label_address = label_address_map.get(instruction.label_name)
if label_address is None:
has_unresolved_labels = True
was_long = i in long_branches
is_long, instruction.bytecode = instruction._encode_label_branch(code_address, label_address,
long_encoding=was_long)
if is_long and not was_long:
long_branches.add(i)
has_updated_branches = True
try:
current_bundle.add_label_branch(instruction, label_address, is_long)
except BufferError:
bundles.append(current_bundle)
current_bundle = InstructionBundle(32, current_bundle.address + current_bundle.capacity)
current_bundle.add_label_branch(instruction, label_address, is_long)
else:
instruction_group = [instruction]
memory_address = instruction.memory_address
from peachpy.x86_64.operand import MemoryAddress
if isinstance(memory_address, MemoryAddress) and memory_address.index is not None:
from peachpy.stream import NullStream
with NullStream():
from peachpy.x86_64.generic import MOV
instruction_group.insert(0,
MOV(memory_address.index.as_dword, memory_address.index.as_dword)
)
try:
current_bundle.add(instruction_group)
except BufferError:
bundles.append(current_bundle)
current_bundle = InstructionBundle(32, current_bundle.address + current_bundle.capacity)
current_bundle.add(instruction_group)
code_address = current_bundle.address + current_bundle.size
bundles.append(current_bundle)
self._instructions = list()
for bundle in bundles:
bundle.optimize()
for instruction in bundle._instructions:
constant = instruction.constant
if constant:
relocation = instruction.relocation
for index in range(relocation.offset, relocation.offset + 4):
instruction.bytecode[index] = 0
relocation.offset += len(self.code_section)
relocation.program_counter += len(self.code_section)
relocation.symbol = self._constant_symbol_map[instruction.constant.name]
self.code_section.add_relocation(relocation)
if instruction.bytecode:
self.code_section.content += instruction.bytecode
if bundle.size < bundle.capacity:
if bundle is not bundles[-1]:
self.code_section.content += self._encode_nops(bundle.capacity - bundle.size)
else:
self.code_section.content += self._encode_abort(bundle.capacity - bundle.size)
else:
has_updated_branches = True
has_unresolved_labels = True
while has_updated_branches or has_unresolved_labels:
code_address = 0
has_updated_branches = False
has_unresolved_labels = False
for (i, instruction) in enumerate(self._instructions):
if isinstance(instruction, LABEL):
label_address_map[instruction.identifier] = code_address
elif isinstance(instruction, BranchInstruction) and instruction.label_name:
label_address = label_address_map.get(instruction.label_name)
if label_address is None:
has_unresolved_labels = True
was_long = i in long_branches
is_long, instruction.bytecode = instruction._encode_label_branch(code_address, label_address,
long_encoding=was_long)
if is_long and not was_long:
long_branches.add(i)
has_updated_branches = True
else:
instruction.bytecode = instruction.encode()
if instruction.bytecode:
code_address += len(instruction.bytecode)
for instruction in self._instructions:
constant = instruction.constant
if constant:
relocation = instruction.relocation
for index in range(relocation.offset, relocation.offset + 4):
instruction.bytecode[index] = 0
relocation.offset += len(self.code_section)
relocation.program_counter += len(self.code_section)
relocation.symbol = self._constant_symbol_map[instruction.constant.name]
self.code_section.add_relocation(relocation)
if instruction.bytecode:
self.code_section.content += instruction.bytecode
def _encode_nops(self, length):
assert 1 <= length <= 31
from peachpy.x86_64.encoding import nop
if length <= 15:
return nop(length)
elif length <= 30:
return nop(length // 2) + nop(length - length // 2)
else:
return nop(8) + nop(8) + nop(15)
def _encode_abort(self, length):
from peachpy.x86_64.abi import native_client_x86_64_abi, goasm_amd64_abi, goasm_amd64p32_abi
if self.abi == native_client_x86_64_abi:
# Use HLT instructions
return bytearray([0xF4] * length)
elif self.abi in {goasm_amd64_abi, goasm_amd64p32_abi}:
# Use a single INT 3 instruction as alignment is not supported anyway
return bytearray([0xCD])
else:
# Use INT 3 instructions
return bytearray([0xCD] * length)
def format_code(self, assembly_format="peachpy", line_separator=os.linesep, indent=True):
"""Returns code of assembly instructions comprising the function"""
code = []
for instruction in self._instructions:
code.append(instruction.format_encoding(indent=indent))
code.append(instruction.format(assembly_format=assembly_format, indent=indent))
if line_separator is None:
return code
else:
return str(line_separator).join(filter(lambda line: line is not None, code))
def format(self, assembly_format="peachpy", line_separator=os.linesep):
"""Formats assembly listing of the function according to specified parameters"""
if assembly_format == "go":
# Arguments for TEXT directive in Go assembler
text_arguments = ["%s\xC2\xB7%s(SB)" % (self.package_name, self.name)]
text_arguments.append("4")
text_arguments.append("$0")
code = ["TEXT " + ",".join(text_arguments)]
else:
code = []
code.extend(self.format_code(assembly_format, line_separator=None, indent=True))
if assembly_format == "go":
# Add trailing line or assembler will refuse to compile
code.append("")
if line_separator is None:
return code
else:
return str(line_separator).join(filter(bool, code))
def load(self):
return ExecutableFuntion(self)
class ExecutableFuntion:
def __init__(self, function):
assert isinstance(function, EncodedFunction), "EncodedFunction object expected"
import peachpy.x86_64.abi
process_abi = peachpy.x86_64.abi.detect()
if process_abi != function.abi:
raise ValueError("Function ABI (%s) does not match process ABI (%s)" %
(str(function.abi), str(process_abi)))
self.code_segment = bytearray(function.code_section.content)
self.const_segment = bytearray(function.const_section.content)
import peachpy.loader
self.loader = peachpy.loader.Loader(len(self.code_segment), len(self.const_segment))
# Apply relocations
from peachpy.x86_64.meta import RelocationType
from peachpy.util import is_sint32
for relocation in function.code_section.relocations:
assert relocation.type == RelocationType.rip_disp32
assert relocation.symbol in function.const_section.symbols
old_value = self.code_segment[relocation.offset] | \
(self.code_segment[relocation.offset + 1] << 8) | \
(self.code_segment[relocation.offset + 2] << 16) | \
(self.code_segment[relocation.offset + 3] << 24)
new_value = old_value + \
(self.loader.data_address + relocation.symbol.offset) - \
(self.loader.code_address + relocation.program_counter)
assert is_sint32(new_value)
self.code_segment[relocation.offset] = new_value & 0xFF
self.code_segment[relocation.offset + 1] = (new_value >> 8) & 0xFF
self.code_segment[relocation.offset + 2] = (new_value >> 16) & 0xFF
self.code_segment[relocation.offset + 3] = (new_value >> 24) & 0xFF
assert not function.const_section.relocations
self.loader.copy_code(self.code_segment)
self.loader.copy_data(self.const_segment)
import ctypes
result_type = None if function.result_type is None else function.result_type.as_ctypes_type
argument_types = [arg.c_type.as_ctypes_type for arg in function.arguments]
self.function_type = ctypes.CFUNCTYPE(result_type, *argument_types)
self.function_pointer = self.function_type(self.loader.code_address)
def __call__(self, *args):
return self.function_pointer(*args)
def __del__(self):
del self.loader
self.loader = None
self.function_pointer = None
class LocalVariable:
def __init__(self, size_option, alignment=None):
from peachpy.util import is_int
if alignment is not None and not is_int(alignment):
raise TypeError("alignment %s is not an integer" % str(alignment))
if alignment is not None and alignment <= 0:
raise ValueError("alignment %d is not a positive integer" % alignment)
self.alignment = alignment
if is_int(size_option):
if size_option <= 0:
raise ValueError("size %d is not a positive integer" % size_option)
self.size = size_option
elif isinstance(size_option, peachpy.x86_64.registers.Register):
self.size = size_option.size
else:
raise TypeError('Unsupported size specification %s: register or integer expected' % size_option)
if self.alignment is None:
self.alignment = self.size
self._address = None
self._offset = 0
self.parent = None
def __eq__(self, other):
return isinstance(other, LocalVariable) and self.root is other.root and \
self.size == other.size and self.offset == other.offset
def __ne__(self, other):
return not isinstance(other, LocalVariable) or self.root is not other.root or \
self.size != other.size or self.offset != other.offset
def __hash__(self):
return id(self.root) ^ hash(self.size) ^ hash(self.offset)
def __str__(self):
if self.address is not None:
return "[" + str(self.address) + "]"
else:
return "local-variable<%d[%d:%d]>" % (id(self.root), self.offset, self.offset + self.size)
def __repr__(self):
return str(self)
@property
def is_subvariable(self):
return self.parent is not None
@property
def root(self):
root = self
while root.parent is not None:
root = root.parent
return root
@property
def offset(self):
node = self
offset = 0
while node.parent is not None:
offset += node._offset
node = node.parent
return offset
@property
def address(self):
if self.is_subvariable:
base_address = self.root.address
if base_address is not None:
return base_address + self.offset
else:
return self._address
@property
def lo(self):
assert self.size % 2 == 0
child = LocalVariable(self.size // 2, min(self.size // 2, self.alignment))
child.parent = self
child._offset = 0
return child
@property
def hi(self):
assert self.size % 2 == 0
child = LocalVariable(self.size // 2, min(self.size // 2, self.alignment))
child.parent = self
child._offset = self.size // 2
return child
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from enum import Enum
class SectionType(Enum):
code = 0
const_data = 1
class Section(object):
max_alignment = 4096
def __init__(self, type, alignment_byte=None):
from peachpy.util import is_uint8
if not isinstance(type, SectionType):
raise TypeError("Type %s is not in SectionType enumeration" % str(type))
if alignment_byte is None:
alignment_byte = 0
elif not is_uint8(alignment_byte):
raise TypeError("Alignment byte %s is not an 8-bit unsigned integer" % str(alignment_byte))
self.type = type
self.alignment_byte = alignment_byte
self.content = bytearray()
self.symbols = list()
self.relocations = list()
self._alignment = 1
def __len__(self):
return len(self.content)
@property
def alignment(self):
return self._alignment
@alignment.setter
def alignment(self, alignment):
from peachpy.util import is_int
if not is_int(alignment):
raise TypeError("Alignment %s is not an integer" % str(alignment))
if alignment < 0:
raise ValueError("Alignment %d is not a positive integer" % alignment)
if alignment & (alignment - 1) != 0:
raise ValueError("Alignment %d is not a power of 2" % alignment)
if alignment > Section.max_alignment:
raise ValueError("Alignment %d exceeds maximum alignment (%d)" % (alignment, Section.max_alignment))
if alignment == 0:
alignment = 1
self._alignment = alignment
def add_symbol(self, symbol):
if not isinstance(symbol, Symbol):
raise TypeError("Symbol %s is not an instance of Symbol type" % str(symbol))
self.symbols.append(symbol)
def add_relocation(self, relocation):
if not isinstance(relocation, Relocation):
raise TypeError("Relocation %s is not an instance of Relocation type" % str(relocation))
self.relocations.append(relocation)
class RelocationType(Enum):
"""Relocation for RIP-relative disp32 offset"""
rip_disp32 = 0
class Relocation:
def __init__(self, offset, type, symbol=None, program_counter=None):
from peachpy.util import is_int
if not is_int(offset):
raise TypeError("Offset %s is not an integer" % str(offset))
if offset < 0:
raise ValueError("Offset %d is negative" % offset)
if not isinstance(type, RelocationType):
raise TypeError("Relocation type %s is not in RelocationType enumeration" % str(type))
if symbol is not None and not isinstance(symbol, Symbol):
raise TypeError("Symbol %s is not an instance of Symbol type" % str(symbol))
if program_counter is not None:
if not is_int(program_counter):
raise TypeError("Program counter %s is not an integer" % str(program_counter))
if program_counter < 0:
raise TypeError("Program counter %d is negative" % program_counter)
self.offset = offset
self.type = type
self.symbol = symbol
self.program_counter = program_counter
class SymbolType(Enum):
"""Literal constant"""
literal_constant = 0
"""Label"""
label = 1
class Symbol:
def __init__(self, offset, type, name=None, size=None):
from peachpy.util import is_int
if not is_int(offset):
raise TypeError("Offset %s is not an integer" % str(offset))
if offset < 0:
raise ValueError("Offset %d is negative" % offset)
if not isinstance(type, SymbolType):
raise TypeError("Symbol type %s is not in SymbolType enumeration" % str(type))
from peachpy.name import Name
if name is not None and not (isinstance(name, tuple) and all(isinstance(part, Name) for part in name)):
raise TypeError("Name %s must be a tuple of Name objects" % str(name))
if size is not None:
if not is_int(size):
raise TypeError("Size %s is not an integer" % str(size))
if size < 0:
raise ValueError("Size %d is negative" % size)
self.offset = offset
self.type = type
self.name = ".".join(map(str, name))
self.size = size
|
import unittest
from peachpy import *
class UInt32(unittest.TestCase):
def runTest(self):
Constant.uint32(-2147483648)
Constant.uint32(0)
Constant.uint32(2147483647)
Constant.uint32(2147483648)
Constant.uint32(4294967295)
class UInt32x2(unittest.TestCase):
def runTest(self):
Constant.uint32x2(1)
Constant.uint32x2(-1, 2)
class UInt32x4(unittest.TestCase):
def runTest(self):
Constant.uint32x4(1)
Constant.uint32x4(-1, 2, -3, 4)
class UInt32x8(unittest.TestCase):
def runTest(self):
Constant.uint32x8(1)
Constant.uint32x8(-1, 2, -3, 4, -5, 6, -7, 8)
class UInt32x16(unittest.TestCase):
def runTest(self):
Constant.uint32x16(1)
Constant.uint32x16(-1, 2, -3, 4, -5, 6, -7, 8, -9, 10, -11, 12, -13, 14, -15, 16)
class UInt64(unittest.TestCase):
def runTest(self):
Constant.uint64(-9223372036854775808)
Constant.uint64(0)
Constant.uint64(9223372036854775807)
Constant.uint64(9223372036854775808)
Constant.uint64(18446744073709551615)
class UInt64x2(unittest.TestCase):
def runTest(self):
Constant.uint64x2(1)
Constant.uint64x2(-1, 2)
class UInt64x4(unittest.TestCase):
def runTest(self):
Constant.uint64x4(1)
Constant.uint64x4(-1, 2, -3, 4)
class UInt64x8(unittest.TestCase):
def runTest(self):
Constant.uint64x8(1)
Constant.uint64x8(-1, 2, -3, 4, -5, 6, -7, 8)
class Float64(unittest.TestCase):
def runTest(self):
self.assertEqual(Constant.float64(0.0).data, (0x0000000000000000,))
self.assertEqual(Constant.float64(1.0).data, (0x3FF0000000000000,))
self.assertEqual(Constant.float64(0.5).data, (0x3FE0000000000000,))
self.assertEqual(Constant.float64(0.75).data, (0x3FE8000000000000,))
self.assertEqual(Constant.float64(2.0).data, (0x4000000000000000,))
self.assertEqual(Constant.float64(float("inf")).data, (0x7FF0000000000000,))
self.assertEqual(Constant.float64(-0.0).data, (0x8000000000000000,))
self.assertEqual(Constant.float64(-1.0).data, (0xBFF0000000000000,))
self.assertEqual(Constant.float64(-0.5).data, (0xBFE0000000000000,))
self.assertEqual(Constant.float64(-0.75).data, (0xBFE8000000000000,))
self.assertEqual(Constant.float64(-2.0).data, (0xC000000000000000,))
self.assertEqual(Constant.float64(-float("inf")).data, (0xFFF0000000000000,))
self.assertEqual(Constant.float64("0x1.6A09E667F3BCDp+0").data, (0x3FF6A09E667F3BCD,))
self.assertEqual(Constant.float64("0x1.BB67AE8584CAAp+0").data, (0x3FFBB67AE8584CAA,))
self.assertEqual(Constant.float64("0x1.921fb54442d18p+1").data, (0x400921FB54442D18,))
self.assertEqual(Constant.float64("0x1.5bf0a8b145769p+1").data, (0x4005BF0A8B145769,))
class Float32(unittest.TestCase):
def runTest(self):
self.assertEqual(Constant.float32(0.0).data, (0x00000000,))
self.assertEqual(Constant.float32(1.0).data, (0x3F800000,))
self.assertEqual(Constant.float32(0.5).data, (0x3F000000,))
self.assertEqual(Constant.float32(0.75).data, (0x3F400000,))
self.assertEqual(Constant.float32(2.0).data, (0x40000000,))
self.assertEqual(Constant.float32(float("inf")).data, (0x7F800000,))
self.assertEqual(Constant.float32(-0.0).data, (0x80000000,))
self.assertEqual(Constant.float32(-1.0).data, (0xBF800000,))
self.assertEqual(Constant.float32(-0.5).data, (0xBF000000,))
self.assertEqual(Constant.float32(-0.75).data, (0xBF400000,))
self.assertEqual(Constant.float32(-2.0).data, (0xC0000000,))
self.assertEqual(Constant.float32(-float("inf")).data, (0xFF800000,))
self.assertEqual(Constant.float32("0x1.6A09E6p+0").data, (0x3FB504F3,))
self.assertEqual(Constant.float32("0x1.BB67AEp+0").data, (0x3FDDB3D7,))
self.assertEqual(Constant.float32("0x1.921FB6p+1").data, (0x40490FDB,))
self.assertEqual(Constant.float32("0x1.5BF0A8p+1").data, (0x402DF854,))
|
import six
def equal_codes(code, ref_code):
assert isinstance(code, list) or isinstance(code, six.string_types)
assert isinstance(ref_code, list) or isinstance(code, six.string_types)
if isinstance(code, six.string_types):
code = code.splitlines()
if isinstance(ref_code, six.string_types):
ref_code = ref_code.splitlines()
code = [line.strip() for line in code if len(line)]
ref_code = [line.strip() for line in ref_code if len(line)]
if six.PY3:
ref_code = [line.replace("\xC2\xB7", "\u00B7") for line in ref_code]
return code == ref_code
|
import unittest
class FileHeaderSize(unittest.TestCase):
def runTest(self):
from peachpy.formats.elf.file import FileHeader
import peachpy.arm.abi
file_header = FileHeader(peachpy.arm.abi.arm_gnueabi)
file_header_bytes = file_header.as_bytearray
self.assertEqual(len(file_header_bytes), file_header.file_header_size,
"ELF header size must match the value specified in the ELF header")
|
import unittest
from peachpy import *
from peachpy.arm import *
class TestARM(unittest.TestCase):
def runTest(self):
# Implement function void add_1(const uint32_t *src, uint32_t *dst, size_t length)
source_arg = Argument(ptr(const_uint32_t))
destination_arg = Argument(ptr(uint32_t))
length_arg = Argument(size_t)
# This optimized kernel will target Intel Nehalem processors. Any instructions which are not
# supported on Intel Nehalem (e.g. AVX instructions) will generate an error. If you don't have
# a particular target in mind, use "Unknown"
with Function("add_1", (source_arg, destination_arg, length_arg), abi=ABI.GnuEABIHF, report_generation=False) as add_function:
# Load arguments into registers
(source, destination, length) = LOAD.ARGUMENTS()
# Main processing loop. Length must be a multiple of 4.
with Loop() as loop:
x = GeneralPurposeRegister()
LDR(x, [source], 4)
# Add 1 to x
ADD(x, x, 1)
STR(x, [destination], 4)
SUBS(length, 4)
BNE(loop.begin)
RETURN()
print add_function.assembly
|
import unittest
from test import equal_codes
from peachpy import *
from peachpy.x86_64 import *
class Empty(unittest.TestCase):
def runTest(self):
with Function("empty", tuple()) as function:
RETURN()
code = function.finalize(abi.goasm_amd64_abi).format("go")
ref_code = """
// func empty()
TEXT \xc2\xB7empty(SB),4,$0
RET
"""
assert equal_codes(code, ref_code), "Unexpected Golang code:\n" + code
class ReturnIntegerArgument(unittest.TestCase):
def runTest(self):
n_arg = Argument(uint32_t)
with Function("return_int_arg", (n_arg,), uint32_t) as function:
n = ebx
LOAD.ARGUMENT(n, n_arg)
STORE.RESULT(n)
RETURN()
code = function.finalize(abi.goasm_amd64_abi).format("go")
ref_code = """
// func return_int_arg(n uint32) uint32
TEXT \xc2\xB7return_int_arg(SB),4,$0-8
MOVL n+0(FP), BX
MOVL BX, ret+4(FP)
RET
"""
assert equal_codes(code, ref_code), "Unexpected Golang code:\n" + code
class ComputeIntegerSum(unittest.TestCase):
def runTest(self):
x_arg = Argument(uint32_t)
y_arg = Argument(uint32_t)
with Function("integer_sum", (x_arg, y_arg), uint32_t) as function:
x = ecx
LOAD.ARGUMENT(x, x_arg)
y = r8d
LOAD.ARGUMENT(y, y_arg)
ADD(x, y)
STORE.RESULT(x)
RETURN()
code = function.finalize(abi.goasm_amd64_abi).format("go")
ref_code = """
// func integer_sum(x uint32, y uint32) uint32
TEXT \xc2\xB7integer_sum(SB),4,$0-12
MOVL x+0(FP), CX
MOVL y+4(FP), R8
ADDL R8, CX
MOVL CX, ret+8(FP)
RET
"""
assert equal_codes(code, ref_code), "Unexpected Golang code:\n" + code
|
import unittest
from test import equal_codes
from peachpy import *
from peachpy.x86_64 import *
class TestExplicitRegisterInputConflict(unittest.TestCase):
def runTest(self):
with Function("explicit_reg_input", (), uint64_t) as function:
reg_tmp = GeneralPurposeRegister64()
MOV(reg_tmp, 42)
MOV([reg_tmp], rax)
RETURN(reg_tmp)
listing = function.finalize(abi.goasm_amd64_abi).format("go")
ref_listing = """
// func explicit_reg_input() uint64
TEXT \xc2\xB7explicit_reg_input(SB),4,$0-8
MOVQ $42, BX
MOVQ AX, 0(BX)
MOVQ BX, ret+0(FP)
RET
"""
assert equal_codes(listing, ref_listing), "Unexpected PeachPy listing:\n" + listing
class TestExplicitRegisterConflict2(unittest.TestCase):
def runTest(self):
with Function("explicit_reg_input_2", ()) as function:
g1 = GeneralPurposeRegister64()
g2 = GeneralPurposeRegister64()
MOV(g1, 0)
MOV(g2, 0)
MOV(rax, 0)
MOV([g1], 0)
MOV([g2], 0)
RET()
listing = function.finalize(abi.goasm_amd64_abi).format("go")
ref_listing = """
// func explicit_reg_input_2()
TEXT \xc2\xB7explicit_reg_input_2(SB),4,$0
MOVQ $0, BX
MOVQ $0, CX
MOVQ $0, AX
MOVB $0, 0(BX)
MOVB $0, 0(CX)
RET
"""
assert equal_codes(listing, ref_listing), "Unexpected PeachPy listing:\n" + listing
class TestExplicitRegisterOutputConflict(unittest.TestCase):
def runTest(self):
with Function("explicit_reg_output", (), uint64_t) as function:
reg_tmp = GeneralPurposeRegister64()
MOV(reg_tmp, 1)
MOV(rax, 2)
RETURN(reg_tmp)
listing = function.finalize(abi.goasm_amd64_abi).format("go")
ref_listing = """
// func explicit_reg_output() uint64
TEXT \xc2\xB7explicit_reg_output(SB),4,$0-8
MOVQ $1, BX
MOVQ $2, AX
MOVQ BX, ret+0(FP)
RET
"""
assert equal_codes(listing, ref_listing), "Unexpected PeachPy listing:\n" + listing
class TestImplicitRegisterConflict(unittest.TestCase):
def runTest(self):
with Function("implicit_reg", (), uint64_t) as function:
reg_tmp = GeneralPurposeRegister64()
MOV(reg_tmp, 42)
CPUID()
RETURN(reg_tmp)
listing = function.finalize(abi.goasm_amd64_abi).format("go")
ref_listing = """
// func implicit_reg() uint64
TEXT \xc2\xB7implicit_reg(SB),4,$0-8
MOVQ $42, DI
CPUID
MOVQ DI, ret+0(FP)
RET
"""
assert equal_codes(listing, ref_listing), "Unexpected PeachPy listing:\n" + listing
class TestIssue65(unittest.TestCase):
def runTest(self):
with Function("crash", (), int64_t) as function:
r = GeneralPurposeRegister64()
MOV(r, 999)
RETURN(rax)
listing = function.finalize(abi.goasm_amd64_abi).format("go")
ref_listing = """
// func crash() int64
TEXT \xc2\xB7crash(SB),4,$0-8
MOVQ $999, BX
MOVQ AX, ret+0(FP)
RET
"""
assert equal_codes(listing, ref_listing), "Unexpected PeachPy listing:\n" + listing
class TestIssue65SecondComment(unittest.TestCase):
def runTest(self):
with Function("crash", (), int64_t) as function:
r = GeneralPurposeRegister64()
MOV(r, 1)
MOV(r, [rax])
RET()
listing = function.finalize(abi.goasm_amd64_abi).format("go")
ref_listing = """
// func crash() int64
TEXT \xc2\xB7crash(SB),4,$0-8
MOVQ $1, BX
MOVQ 0(AX), BX
RET
"""
assert equal_codes(listing, ref_listing), "Unexpected PeachPy listing:\n" + listing
|
import unittest
from peachpy import *
from peachpy.x86_64 import *
abi_list = [abi.microsoft_x64_abi, abi.system_v_x86_64_abi, abi.linux_x32_abi, abi.native_client_x86_64_abi]
class Return0(unittest.TestCase):
def runTest(self):
for abi in abi_list:
for return_type in [int8_t, int16_t, int32_t, int64_t, uint8_t, uint16_t, uint32_t, uint64_t]:
with Function("return_0", tuple(), return_type) as function:
RETURN(0)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "XOR eax, eax", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnOne(unittest.TestCase):
def runTest(self):
for abi in abi_list:
for return_type in [int8_t, int16_t, int32_t, int64_t, uint8_t, uint16_t, uint32_t, uint64_t]:
with Function("return_1", tuple(), return_type) as function:
RETURN(1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOV eax, 1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnMinusOne(unittest.TestCase):
def runTest(self):
for abi in abi_list:
for return_type in [int8_t, int16_t, int32_t]:
with Function("return_minus_one", tuple(), return_type) as function:
RETURN(-1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOV eax, -1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
with Function("return_minus_one", tuple(), int64_t) as function:
RETURN(-1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOV rax, -1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class Return0xFFFFFFFF(unittest.TestCase):
def runTest(self):
for abi in abi_list:
for return_type in [int64_t, uint64_t]:
with Function("return_0xFFFFFFFF", tuple(), return_type) as function:
RETURN(0xFFFFFFFF)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOV eax, 4294967295", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnGeneralPurposeRegister(unittest.TestCase):
def runTest(self):
for abi in abi_list:
for return_type in [int8_t, int16_t, int32_t]:
with Function("return_r8_intX", tuple(), return_type) as function:
RETURN(dl)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVSX eax, dl", \
"Unexpected PeachPy code:\n" + "\n".join(code)
for return_type in [int16_t, int32_t]:
with Function("return_r16_intX", tuple(), return_type) as function:
RETURN(dx)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVSX eax, dx", \
"Unexpected PeachPy code:\n" + "\n".join(code)
for return_type in [uint8_t, uint16_t, uint32_t, uint64_t]:
with Function("return_r8_uintX", tuple(), return_type) as function:
RETURN(dl)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVZX eax, dl", \
"Unexpected PeachPy code:\n" + "\n".join(code)
for return_type in [uint16_t, uint32_t, uint64_t]:
with Function("return_r16_uintX", tuple(), return_type) as function:
RETURN(dx)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVZX eax, dx", \
"Unexpected PeachPy code:\n" + "\n".join(code)
for return_type in [int32_t, uint32_t, uint64_t]:
with Function("return_r32", tuple(), return_type) as function:
RETURN(edx)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOV eax, edx", \
"Unexpected PeachPy code:\n" + "\n".join(code)
for return_type in [int64_t, uint64_t]:
with Function("return_r64", tuple(), return_type) as function:
RETURN(rdx)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOV rax, rdx", \
"Unexpected PeachPy code:\n" + "\n".join(code)
with Function("return_r8_int64", tuple(), int64_t) as function:
RETURN(dl)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVSX rax, dl", \
"Unexpected PeachPy code:\n" + "\n".join(code)
with Function("return_r16_int64", tuple(), int64_t) as function:
RETURN(dx)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVSX rax, dx", \
"Unexpected PeachPy code:\n" + "\n".join(code)
with Function("return_r32_int64", tuple(), int64_t) as function:
RETURN(edx)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVSXD rax, edx", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnFloat(unittest.TestCase):
def runTest(self):
for abi in abi_list:
with Function("return_float", tuple(), float_) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] in ["MOVSS xmm0, xmm1", "MOVAPS xmm0, xmm1"], \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnDouble(unittest.TestCase):
def runTest(self):
for abi in abi_list:
with Function("return_double", tuple(), double_) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] in ["MOVSD xmm0, xmm1", "MOVAPD xmm0, xmm1"], \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnFloatAVX(unittest.TestCase):
def runTest(self):
for abi in abi_list:
v = Argument(m256)
with Function("return_float_avx_arg", (v,), float_) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] in ["VMOVSS xmm0, xmm1", "VMOVAPS xmm0, xmm1"], \
"Unexpected PeachPy code:\n" + "\n".join(code)
assert "VZEROUPPER" not in code
assert "VZEROALL" not in code
class ReturnDoubleAVX(unittest.TestCase):
def runTest(self):
for abi in abi_list:
v = Argument(m256d)
with Function("return_double_avx_arg", (v,), double_) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] in ["VMOVSD xmm0, xmm1", "VMOVAPD xmm0, xmm1"], \
"Unexpected PeachPy code:\n" + "\n".join(code)
assert "VZEROUPPER" not in code
assert "VZEROALL" not in code
class ReturnM64(unittest.TestCase):
def runTest(self):
for abi in abi_list:
with Function("return_m64", tuple(), m64) as function:
RETURN(mm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVQ mm0, mm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
assert "EMMS" not in code
assert "FEMMS" not in code
class ReturnM128(unittest.TestCase):
def runTest(self):
for abi in abi_list:
with Function("return_m128", tuple(), m128) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVAPS xmm0, xmm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnM128D(unittest.TestCase):
def runTest(self):
for abi in abi_list:
with Function("return_m128d", tuple(), m128d) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVAPD xmm0, xmm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnM128I(unittest.TestCase):
def runTest(self):
for abi in abi_list:
with Function("return_m128i", tuple(), m128i) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "MOVDQA xmm0, xmm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnM128AVX(unittest.TestCase):
def runTest(self):
for abi in abi_list:
v = Argument(m256)
with Function("return_m128_avx", (v,), m128) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "VMOVAPS xmm0, xmm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
assert "VZEROUPPER" not in code
assert "VZEROALL" not in code
class ReturnM128DAVX(unittest.TestCase):
def runTest(self):
for abi in abi_list:
v = Argument(m256d)
with Function("return_m128d_avx", (v,), m128d) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "VMOVAPD xmm0, xmm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
assert "VZEROUPPER" not in code
assert "VZEROALL" not in code
class ReturnM128IAVX(unittest.TestCase):
def runTest(self):
for abi in abi_list:
v = Argument(m256i)
with Function("return_m128i_avx", (v,), m128i) as function:
RETURN(xmm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "VMOVDQA xmm0, xmm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
assert "VZEROUPPER" not in code
assert "VZEROALL" not in code
class ReturnM256(unittest.TestCase):
def runTest(self):
for abi in abi_list:
with Function("return_m256", tuple(), m256) as function:
RETURN(ymm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "VMOVAPS ymm0, ymm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnM256D(unittest.TestCase):
def runTest(self):
for abi in abi_list:
with Function("return_m256d", tuple(), m256d) as function:
RETURN(ymm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "VMOVAPD ymm0, ymm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
class ReturnM256I(unittest.TestCase):
def runTest(self):
for abi in abi_list:
with Function("return_m256i", tuple(), m256i) as function:
RETURN(ymm1)
code = function.finalize(abi).format_code(line_separator=None, indent=False)
assert code[0] == "VMOVDQA ymm0, ymm1", \
"Unexpected PeachPy code:\n" + "\n".join(code)
|
import unittest
from test import equal_codes
from peachpy import *
from peachpy.x86_64 import *
class TestBasicBlockAnalysis(unittest.TestCase):
def runTest(self):
x = Argument(uint32_t)
y = Argument(uint32_t)
with Function("integer_sum", (x, y), uint32_t) as function:
reg_x = GeneralPurposeRegister32()
reg_y = GeneralPurposeRegister32()
LOAD.ARGUMENT(reg_x, x)
LOAD.ARGUMENT(reg_y, y)
ADD(reg_x, reg_y)
MOV(eax, reg_x)
RETURN()
listing = function.format_instructions()
ref_listing = """
LOAD.ARGUMENT gp32-vreg<1>, uint32_t x
In regs:
Out regs: gp64-vreg<1>
Live regs:
Avail regs:
LOAD.ARGUMENT gp32-vreg<2>, uint32_t y
In regs:
Out regs: gp64-vreg<2>
Live regs: gp32-vreg<1>
Avail regs: gp64-vreg<1>
ADD gp32-vreg<1>, gp32-vreg<2>
In regs: gp32-vreg<1>, gp32-vreg<2>
Out regs: gp64-vreg<1>
Live regs: gp32-vreg<1>, gp32-vreg<2>
Avail regs: gp64-vreg<1>, gp64-vreg<2>
MOV eax, gp32-vreg<1>
In regs: gp32-vreg<1>
Out regs: rax
Live regs: gp32-vreg<1>
Avail regs: gp64-vreg<1>, gp64-vreg<2>
RETURN
In regs:
Out regs:
Live regs:
Avail regs: gp64-vreg<1>, gp64-vreg<2>, rax
"""
assert equal_codes(listing, ref_listing), "Unexpected PeachPy listing:\n" + listing
class TestSimpleLoopAnalysis(unittest.TestCase):
def runTest(self):
x = Argument(ptr(const_float_))
y = Argument(ptr(float_))
length = Argument(size_t)
with Function("square", (x, y, length)) as function:
r_x = GeneralPurposeRegister64()
r_y = GeneralPurposeRegister64()
r_length = GeneralPurposeRegister64()
LOAD.ARGUMENT(r_x, x)
LOAD.ARGUMENT(r_y, y)
LOAD.ARGUMENT(r_length, length)
with Loop() as loop:
xmm_value = XMMRegister()
MOVSS(xmm_value, [r_x])
MULSS(xmm_value, xmm_value)
MOVSS([r_y], xmm_value)
SUB(r_length, 1)
JNZ(loop.begin)
RETURN()
listing = function.format_instructions()
ref_listing = """
LOAD.ARGUMENT gp64-vreg<1>, const float* x
In regs:
Out regs: gp64-vreg<1>
Live regs:
Avail regs:
LOAD.ARGUMENT gp64-vreg<2>, float* y
In regs:
Out regs: gp64-vreg<2>
Live regs: gp64-vreg<1>
Avail regs: gp64-vreg<1>
LOAD.ARGUMENT gp64-vreg<3>, size_t length
In regs:
Out regs: gp64-vreg<3>
Live regs: gp64-vreg<1>, gp64-vreg<2>
Avail regs: gp64-vreg<1>, gp64-vreg<2>
loop.begin:
MOVSS xmm-vreg<1>, [gp64-vreg<1>]
In regs: gp64-vreg<1>
Out regs: xmm-vreg<1>
Live regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, xmm-vreg<1>
MULSS xmm-vreg<1>, xmm-vreg<1>
In regs: xmm-vreg<1>
Out regs: xmm-vreg<1>
Live regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, xmm-vreg<1>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, xmm-vreg<1>
MOVSS [gp64-vreg<2>], xmm-vreg<1>
In regs: gp64-vreg<2>, xmm-vreg<1>
Out regs:
Live regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, xmm-vreg<1>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, xmm-vreg<1>
SUB gp64-vreg<3>, 1
In regs: gp64-vreg<3>
Out regs: gp64-vreg<3>
Live regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, xmm-vreg<1>
JNZ loop.begin
In regs:
Out regs:
Live regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, xmm-vreg<1>
RETURN
In regs:
Out regs:
Live regs:
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, xmm-vreg<1>
"""
assert equal_codes(listing, ref_listing), "Unexpected PeachPy code:\n" + listing
class TestBFSAnalysis(unittest.TestCase):
def runTest(self):
vertex_edges = Argument(ptr(const_uint32_t))
neighbors = Argument(ptr(const_uint32_t))
input_queue = Argument(ptr(const_uint32_t))
input_vertices = Argument(uint32_t)
output_queue = Argument(ptr(uint32_t))
levels = Argument(ptr(uint32_t))
current_level = Argument(uint32_t)
with Function("bfs",
(vertex_edges, neighbors, input_queue, input_vertices,
output_queue, levels, current_level)) as function:
reg_vertex_edges = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_vertex_edges, vertex_edges)
reg_neighbors = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_neighbors, neighbors)
reg_input_queue = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_input_queue, input_queue)
reg_input_vertices = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_input_vertices, input_vertices)
reg_output_queue = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_output_queue, output_queue)
reg_levels = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_levels, levels)
reg_current_level = GeneralPurposeRegister32()
LOAD.ARGUMENT(reg_current_level, current_level)
reg_output_queue_start = GeneralPurposeRegister64()
MOV(reg_output_queue_start, reg_output_queue)
skip_neighbor = Label("skip_neighbor")
per_edge_loop = Loop("per_edge_loop")
with Loop() as per_vertex_loop:
reg_current_vertex = GeneralPurposeRegister64()
MOV(reg_current_vertex.as_dword, [reg_input_queue])
ADD(reg_input_queue, 4)
reg_start_edge = GeneralPurposeRegister64()
MOV(reg_start_edge.as_dword, [reg_vertex_edges + reg_current_vertex * 4])
reg_end_edge = GeneralPurposeRegister64()
MOV(reg_end_edge.as_dword, [reg_vertex_edges + reg_current_vertex * 4 + 4])
CMP(reg_start_edge, reg_end_edge)
JE(per_edge_loop.end)
reg_current_neighbor_pointer = GeneralPurposeRegister64()
LEA(reg_current_neighbor_pointer, [reg_neighbors + reg_start_edge * 4])
reg_end_neighbor_pointer = GeneralPurposeRegister64()
LEA(reg_end_neighbor_pointer, [reg_neighbors + reg_end_edge * 4])
with per_edge_loop:
reg_neighbor_vertex = GeneralPurposeRegister64()
MOV(reg_neighbor_vertex.as_dword, [reg_current_neighbor_pointer])
ADD(reg_current_neighbor_pointer, 4)
reg_neighbor_level = GeneralPurposeRegister32()
MOV(reg_neighbor_level, [reg_levels + reg_neighbor_vertex * 4])
CMP(reg_neighbor_level, reg_current_level)
JBE(skip_neighbor)
MOV([reg_output_queue], reg_neighbor_vertex.as_dword)
ADD(reg_output_queue, 4)
MOV([reg_levels + reg_neighbor_vertex * 4], reg_current_level)
LABEL(skip_neighbor)
CMP(reg_current_neighbor_pointer, reg_end_neighbor_pointer)
JNE(per_edge_loop.begin)
SUB(reg_input_vertices, 1)
JNE(per_vertex_loop.begin)
SUB(reg_output_queue, reg_output_queue_start)
SHR(reg_output_queue, 2)
MOV(rax, reg_output_queue)
RETURN()
listing = function.format_instructions()
ref_listing = """
LOAD.ARGUMENT gp64-vreg<1>, const uint32_t* vertex_edges
In regs:
Out regs: gp64-vreg<1>
Live regs:
Avail regs:
LOAD.ARGUMENT gp64-vreg<2>, const uint32_t* neighbors
In regs:
Out regs: gp64-vreg<2>
Live regs: gp64-vreg<1>
Avail regs: gp64-vreg<1>
LOAD.ARGUMENT gp64-vreg<3>, const uint32_t* input_queue
In regs:
Out regs: gp64-vreg<3>
Live regs: gp64-vreg<1>, gp64-vreg<2>
Avail regs: gp64-vreg<1>, gp64-vreg<2>
LOAD.ARGUMENT gp64-vreg<4>, uint32_t input_vertices
In regs:
Out regs: gp64-vreg<4>
Live regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>
LOAD.ARGUMENT gp64-vreg<5>, uint32_t* output_queue
In regs:
Out regs: gp64-vreg<5>
Live regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>
LOAD.ARGUMENT gp64-vreg<6>, uint32_t* levels
In regs:
Out regs: gp64-vreg<6>
Live regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>
LOAD.ARGUMENT gp32-vreg<7>, uint32_t current_level
In regs:
Out regs: gp64-vreg<7>
Live regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>
MOV gp64-vreg<8>, gp64-vreg<5>
In regs: gp64-vreg<5>
Out regs: gp64-vreg<8>
Live regs: gp32-vreg<7>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>
Avail regs: gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>
per_vertex_loop.begin:
MOV gp32-vreg<9>, [gp64-vreg<3>]
In regs: gp64-vreg<3>
Out regs: gp64-vreg<9>
Live regs: gp32-vreg<7>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
ADD gp64-vreg<3>, 4
In regs: gp64-vreg<3>
Out regs: gp64-vreg<3>
Live regs: gp32-vreg<7>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>, gp64-vreg<9>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
MOV gp32-vreg<10>, [gp64-vreg<1> + gp64-vreg<9>*4]
In regs: gp64-vreg<1>, gp64-vreg<9>
Out regs: gp64-vreg<10>
Live regs: gp32-vreg<7>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>, gp64-vreg<9>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
MOV gp32-vreg<11>, [gp64-vreg<1> + gp64-vreg<9>*4 + 4]
In regs: gp64-vreg<1>, gp64-vreg<9>
Out regs: gp64-vreg<11>
Live regs: gp32-vreg<7>, gp64-vreg<10>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>, gp64-vreg<9>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
CMP gp64-vreg<10>, gp64-vreg<11>
In regs: gp64-vreg<10>, gp64-vreg<11>
Out regs:
Live regs: gp32-vreg<7>, gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
JE per_edge_loop.end
In regs:
Out regs:
Live regs: gp32-vreg<7>, gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
LEA gp64-vreg<12>, [gp64-vreg<2> + gp64-vreg<10>*4]
In regs: gp64-vreg<10>, gp64-vreg<2>
Out regs: gp64-vreg<12>
Live regs: gp32-vreg<7>, gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
LEA gp64-vreg<13>, [gp64-vreg<2> + gp64-vreg<11>*4]
In regs: gp64-vreg<11>, gp64-vreg<2>
Out regs: gp64-vreg<13>
Live regs: gp32-vreg<7>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
per_edge_loop.begin:
MOV gp32-vreg<14>, [gp64-vreg<12>]
In regs: gp64-vreg<12>
Out regs: gp64-vreg<14>
Live regs: gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
ADD gp64-vreg<12>, 4
In regs: gp64-vreg<12>
Out regs: gp64-vreg<12>
Live regs: gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
MOV gp32-vreg<15>, [gp64-vreg<6> + gp64-vreg<14>*4]
In regs: gp64-vreg<14>, gp64-vreg<6>
Out regs: gp64-vreg<15>
Live regs: gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
CMP gp32-vreg<15>, gp32-vreg<7>
In regs: gp32-vreg<15>, gp32-vreg<7>
Out regs:
Live regs: gp32-vreg<15>, gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
JBE skip_neighbor
In regs:
Out regs:
Live regs: gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
MOV [gp64-vreg<5>], gp32-vreg<14>
In regs: gp32-vreg<14>, gp64-vreg<5>
Out regs:
Live regs: gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
ADD gp64-vreg<5>, 4
In regs: gp64-vreg<5>
Out regs: gp64-vreg<5>
Live regs: gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
MOV [gp64-vreg<6> + gp64-vreg<14>*4], gp32-vreg<7>
In regs: gp32-vreg<7>, gp64-vreg<14>, gp64-vreg<6>
Out regs:
Live regs: gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
skip_neighbor:
CMP gp64-vreg<12>, gp64-vreg<13>
In regs: gp64-vreg<12>, gp64-vreg<13>
Out regs:
Live regs: gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
JNE per_edge_loop.begin
In regs:
Out regs:
Live regs: gp32-vreg<7>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
per_edge_loop.end:
SUB gp64-vreg<4>, 1
In regs: gp64-vreg<4>
Out regs: gp64-vreg<4>
Live regs: gp32-vreg<7>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
JNE per_vertex_loop.begin
In regs:
Out regs:
Live regs: gp32-vreg<7>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
SUB gp64-vreg<5>, gp64-vreg<8>
In regs: gp64-vreg<5>, gp64-vreg<8>
Out regs: gp64-vreg<5>
Live regs: gp64-vreg<5>, gp64-vreg<8>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
SHR gp64-vreg<5>, 2
In regs: gp64-vreg<5>
Out regs: gp64-vreg<5>
Live regs: gp64-vreg<5>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
MOV rax, gp64-vreg<5>
In regs: gp64-vreg<5>
Out regs: rax
Live regs: gp64-vreg<5>
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>
RETURN
In regs:
Out regs:
Live regs:
Avail regs: gp64-vreg<10>, gp64-vreg<11>, gp64-vreg<12>, gp64-vreg<13>, gp64-vreg<14>, gp64-vreg<15>, gp64-vreg<1>, gp64-vreg<2>, gp64-vreg<3>, gp64-vreg<4>, gp64-vreg<5>, gp64-vreg<6>, gp64-vreg<7>, gp64-vreg<8>, gp64-vreg<9>, rax
"""
assert equal_codes(listing, ref_listing), "Unexpected PeachPy code:\n" + listing
|
import unittest
from test import equal_codes
from peachpy.x86_64 import *
class TestInvalidLabelName(unittest.TestCase):
"""Test that Label constructor rejects invalid names"""
def runTest(self):
with self.assertRaises(TypeError):
Label(1)
with self.assertRaises(ValueError):
Label("1")
with self.assertRaises(ValueError):
Label("lbl:")
with self.assertRaises(ValueError):
Label(".lbl")
with self.assertRaises(ValueError):
Label("__lbl")
class TestAutonamedLabel(unittest.TestCase):
"""Test that Label name is parsed from Python code whenever possible"""
def runTest(self):
with Function("autonamed_label", tuple()) as function:
skip_nop = Label()
JMP(skip_nop)
NOP()
LABEL(skip_nop)
RETURN()
code = function.format()
ref_code = """
void autonamed_label()
JMP skip_nop
NOP
skip_nop:
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
class TestDuplicateNamedLabels(unittest.TestCase):
"""Test that defining an already defined label immediately produces an error"""
def runTest(self):
with Function("duplicate_labels", tuple()):
label1 = Label("lbl")
label2 = Label("lbl")
LABEL(label1)
with self.assertRaises(ValueError):
LABEL(label2)
RETURN()
class TestDuplicateAutonamedLabels(unittest.TestCase):
"""Test that conflicts in parsed label names resolve automatically"""
def runTest(self):
with Function("duplicate_autonamed_labels", tuple()) as function:
# One "skip" label
skip = Label()
JMP(skip)
INT(3)
LABEL(skip)
# Another "skip" label
skip = Label()
JMP(skip)
NOP()
LABEL(skip)
RETURN()
code = function.format()
ref_code0 = """
void duplicate_autonamed_labels()
JMP skip0
INT 3
skip0:
JMP skip1
NOP
skip1:
RETURN
"""
ref_code1 = """
void duplicate_autonamed_labels()
JMP skip1
INT 3
skip1:
JMP skip0
NOP
skip0:
RETURN
"""
assert equal_codes(code, ref_code0) or equal_codes(code, ref_code1), \
"Unexpected PeachPy code:\n" + code
class TestUndefinedLabels(unittest.TestCase):
"""Test that referencing undefined labels produces an error"""
def runTest(self):
with self.assertRaises(ValueError):
with Function("undefined_label", tuple()):
label = Label("lbl")
JMP(label)
RETURN()
class TestDefaultLabels(unittest.TestCase):
"""Test that entry label can be referenced even if it is not defined"""
def runTest(self):
with Function("jump_to_entry", tuple()) as function:
JMP(function.entry)
RETURN()
class TestUnreferencedLabels(unittest.TestCase):
"""Test that unreferenced labels are removed from the function"""
def runTest(self):
with Function("unreferenced_labels", tuple()) as function:
used_label = Label("used")
unused_label = Label("unused")
LABEL(unused_label)
JMP(used_label)
LABEL(used_label)
RETURN()
code = function.format()
ref_code = """
void unreferenced_labels()
JMP used
used:
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
|
import unittest
from test import equal_codes
from peachpy import *
from peachpy.x86_64 import *
class Empty(unittest.TestCase):
def runTest(self):
with Function("empty", tuple()) as function:
RETURN()
code = function.format()
ref_code = """
void empty()
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
class ReturnIntegerArgument(unittest.TestCase):
def runTest(self):
n = Argument(uint32_t)
with Function("return_int_arg", (n,), uint32_t) as function:
r_n = GeneralPurposeRegister32()
LOAD.ARGUMENT(r_n, n)
MOV(eax, r_n)
RETURN()
code = function.format()
ref_code = """
uint32_t return_int_arg(uint32_t n)
LOAD.ARGUMENT gp32-vreg<1>, uint32_t n
MOV eax, gp32-vreg<1>
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
class ReturnFloatArgument(unittest.TestCase):
def runTest(self):
x = Argument(float_)
with Function("return_float_arg", (x,), float_) as function:
xmm_x = XMMRegister()
LOAD.ARGUMENT(xmm_x, x)
MOVSS(xmm0, xmm_x)
RETURN()
code = function.format()
ref_code = """
float return_float_arg(float x)
LOAD.ARGUMENT xmm-vreg<1>, float x
MOVSS xmm0, xmm-vreg<1>
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
class ReturnDoubleArgument(unittest.TestCase):
def runTest(self):
x = Argument(double_)
with Function("return_float_arg", (x,), double_) as function:
xmm_x = XMMRegister()
LOAD.ARGUMENT(xmm_x, x)
MOVSD(xmm0, xmm_x)
RETURN()
code = function.format()
ref_code = """
double return_float_arg(double x)
LOAD.ARGUMENT xmm-vreg<1>, double x
MOVSD xmm0, xmm-vreg<1>
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
class ReturnM128Argument(unittest.TestCase):
def runTest(self):
x = Argument(m128)
with Function("return_m128_arg", (x,), m128) as function:
xmm_x = XMMRegister()
LOAD.ARGUMENT(xmm_x, x)
MOVAPS(xmm0, xmm_x)
RETURN()
code = function.format()
ref_code = """
__m128 return_m128_arg(__m128 x)
LOAD.ARGUMENT xmm-vreg<1>, __m128 x
MOVAPS xmm0, xmm-vreg<1>
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
class ComputeIntegerSum(unittest.TestCase):
def runTest(self):
x = Argument(uint32_t)
y = Argument(uint32_t)
with Function("integer_sum", (x, y), uint32_t) as function:
r_x = GeneralPurposeRegister32()
r_y = GeneralPurposeRegister32()
LOAD.ARGUMENT(r_x, x)
LOAD.ARGUMENT(r_y, y)
ADD(r_x, r_y)
MOV(eax, r_x)
RETURN()
code = function.format()
ref_code = """
uint32_t integer_sum(uint32_t x, uint32_t y)
LOAD.ARGUMENT gp32-vreg<1>, uint32_t x
LOAD.ARGUMENT gp32-vreg<2>, uint32_t y
ADD gp32-vreg<1>, gp32-vreg<2>
MOV eax, gp32-vreg<1>
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
class ComputeIntegerSumWithLocalVariable(unittest.TestCase):
def runTest(self):
x = Argument(uint32_t)
y = Argument(uint32_t)
with Function("integer_sum", (x, y), uint32_t) as function:
r_x = GeneralPurposeRegister32()
r_x_temp = GeneralPurposeRegister32()
r_y = GeneralPurposeRegister32()
buffer = LocalVariable(4)
LOAD.ARGUMENT(r_x, x)
LOAD.ARGUMENT(r_y, y)
MOV(buffer, r_x)
MOV(r_x_temp, buffer)
ADD(r_x_temp, r_y)
MOV(eax, r_x_temp)
RETURN()
code = function.format()
ref_code = """
uint32_t integer_sum(uint32_t x, uint32_t y)
LOAD.ARGUMENT gp32-vreg<1>, uint32_t x
LOAD.ARGUMENT gp32-vreg<3>, uint32_t y
MOV dword [rsp], gp32-vreg<1>
MOV gp32-vreg<2>, dword [rsp]
ADD gp32-vreg<2>, gp32-vreg<3>
MOV eax, gp32-vreg<2>
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
class SimpleLoop(unittest.TestCase):
def runTest(self):
x = Argument(ptr(const_float_))
y = Argument(ptr(float_))
length = Argument(size_t)
with Function("square", (x, y, length)) as function:
r_x = GeneralPurposeRegister64()
r_y = GeneralPurposeRegister64()
r_length = GeneralPurposeRegister64()
LOAD.ARGUMENT(r_x, x)
LOAD.ARGUMENT(r_y, y)
LOAD.ARGUMENT(r_length, length)
with Loop() as loop:
xmm_value = XMMRegister()
MOVSS(xmm_value, [r_x])
MULSS(xmm_value, xmm_value)
MOVSS([r_y], xmm_value)
SUB(r_length, 1)
JNZ(loop.begin)
RETURN()
code = function.format()
ref_code = """
void square(const float* x, float* y, size_t length)
LOAD.ARGUMENT gp64-vreg<1>, const float* x
LOAD.ARGUMENT gp64-vreg<2>, float* y
LOAD.ARGUMENT gp64-vreg<3>, size_t length
loop.begin:
MOVSS xmm-vreg<1>, [gp64-vreg<1>]
MULSS xmm-vreg<1>, xmm-vreg<1>
MOVSS [gp64-vreg<2>], xmm-vreg<1>
SUB gp64-vreg<3>, 1
JNZ loop.begin
RETURN
"""
assert equal_codes(code, ref_code), "Unexpected PeachPy code:\n" + code
# class SSEArgument(unittest.TestCase):
# def runTest(self):
#
# x_arg = Argument(m128d)
#
# # This optimized kernel will target Intel Nehalem processors. Any instructions which are not
# # supported on Intel Nehalem (e.g. AVX instructions) will generate an error. If you don't have
# # a particular target in mind, use "Unknown"
# with Function("_mm_sqr_pd", (x_arg,), abi=ABI.SystemV, report_generation=False) as add_function:
# x = SSERegister()
# LOAD.ARGUMENT(x, x_arg)
#
# MULPD(x, x)
# MOVAPD(xmm0, x)
#
# RETURN()
#
# print add_function.assembly
|
import unittest
from peachpy import *
from peachpy.x86_64 import *
class EndOfInstructionRelocation(unittest.TestCase):
def runTest(self):
constant = Constant.uint32(42)
constant.address = 0
instruction = ADD(ecx, constant)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 4
class EndOfREXInstructionRelocation(unittest.TestCase):
def runTest(self):
constant = Constant.uint64(42)
constant.address = 0
instruction = ADD(rcx, constant)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 4
class EndOfVEX2InstructionRelocation(unittest.TestCase):
def runTest(self):
constant = Constant.float32x4(1.0, 2.0, 3.0, 4.0)
constant.address = 0
instruction = VADDPS(xmm0, xmm1, constant)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 4
class EndOfVEX3InstructionRelocation(unittest.TestCase):
def runTest(self):
constant = Constant.uint32x4(1, 2, 3, 4)
constant.address = 0
instruction = VPADDD(xmm0, xmm1, constant)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 4
class EndOfXOPInstructionRelocation(unittest.TestCase):
def runTest(self):
constant = Constant.uint32x4(1, 2, 3, 4)
constant.address = 0
instruction = VPHADDDQ(xmm0, constant)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 4
@unittest.skip
class EndOfEVEXInstructionRelocation(unittest.TestCase):
def runTest(self):
constant = Constant.float32x4(1.0, 2.0, 3.0, 4.0)
constant.address = 0
instruction = VADDPS(xmm0(k1), xmm1, constant)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 4
class RelocationBeforeImm8(unittest.TestCase):
def runTest(self):
constant = Constant.uint32(42)
constant.address = 0
instruction = CMP(constant, 42)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 5
class RelocationBeforeREXImm8(unittest.TestCase):
def runTest(self):
constant = Constant.uint64(42)
constant.address = 0
instruction = CMP(constant, 42)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 5
class RelocationBeforeVEX2Imm8(unittest.TestCase):
def runTest(self):
constant = Constant.float32x4(1.0, 2.0, 3.0, 4.0)
constant.address = 0
instruction = VSHUFPS(xmm0, xmm1, constant, 0xAA)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 5
class RelocationBeforeVEX3Imm8(unittest.TestCase):
def runTest(self):
constant = Constant.uint32x4(1, 2, 3, 4)
constant.address = 0
instruction = VPALIGNR(xmm0, xmm1, constant, 6)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 5
class RelocationBeforeXOPImm8(unittest.TestCase):
def runTest(self):
constant = Constant.uint32x4(1, 2, 3, 4)
constant.address = 0
instruction = VPCOMUD(xmm0, xmm1, constant, 0)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 5
@unittest.skip
class RelocationBeforeEVEXImm8(unittest.TestCase):
def runTest(self):
constant = Constant.float32x8(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0)
constant.address = 0
instruction = VALIGND(ymm0, ymm1, constant, 2)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 5
class RelocationBeforeImm32(unittest.TestCase):
def runTest(self):
constant = Constant.uint32(42)
constant.address = 0
instruction = TEST(constant, 0x12345678)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 8
class RelocationBeforeREXImm32(unittest.TestCase):
def runTest(self):
constant = Constant.uint64(42)
constant.address = 0
instruction = TEST(constant, 0x12345678)
instruction.bytecode = instruction.encode()
relocation = instruction.relocation
assert relocation.offset == len(instruction.bytecode) - 8
|
import unittest
from test import equal_codes
from peachpy import *
from peachpy.x86_64 import *
class LoadAsm(unittest.TestCase):
def runTest(self):
x = Argument(int32_t)
y = Argument(float_)
with Function("Multiply", (x, y), double_) as asm_multiply:
reg_x = GeneralPurposeRegister32()
LOAD.ARGUMENT(reg_x, x)
xmm_y = XMMRegister()
LOAD.ARGUMENT(xmm_y, y)
xmm_x = XMMRegister()
CVTSI2SD(xmm_x, reg_x)
CVTSS2SD(xmm_y, xmm_y)
MULSD(xmm_x, xmm_y)
RETURN(xmm_x)
py_multiply = asm_multiply.finalize(abi.detect()).encode().load()
assert py_multiply(2, 2.0) == 4.0
assert py_multiply(2, 3.0) == 6.0
|
import unittest
from peachpy.x86_64 import *
class SALwithCL(unittest.TestCase):
def runTest(self):
with Function("test_sal_r32_cl", ()):
n = GeneralPurposeRegister32()
SAL(n, cl)
RETURN()
class SARwithCL(unittest.TestCase):
def runTest(self):
with Function("test_sar_r32_cl", ()):
n = GeneralPurposeRegister32()
SAR(n, cl)
RETURN()
class SHLwithCL(unittest.TestCase):
def runTest(self):
with Function("test_shl_r32_cl", ()):
n = GeneralPurposeRegister32()
SHL(n, cl)
RETURN()
class SHRwithCL(unittest.TestCase):
def runTest(self):
with Function("test_shr_r32_cl", ()):
n = GeneralPurposeRegister32()
SHR(n, cl)
RETURN()
class ROLwithCL(unittest.TestCase):
def runTest(self):
with Function("test_rol_r32_cl", ()):
n = GeneralPurposeRegister32()
ROL(n, cl)
RETURN()
class RORwithCL(unittest.TestCase):
def runTest(self):
with Function("test_ror_r32_cl", ()):
n = GeneralPurposeRegister32()
ROR(n, cl)
RETURN()
class RCLwithCL(unittest.TestCase):
def runTest(self):
with Function("test_rcl_r32_cl", ()):
n = GeneralPurposeRegister32()
RCL(n, cl)
RETURN()
class RCRwithCL(unittest.TestCase):
def runTest(self):
with Function("test_rcr_r32_cl", ()):
n = GeneralPurposeRegister32()
RCR(n, cl)
RETURN()
class SHLDwithCL(unittest.TestCase):
def runTest(self):
with Function("test_shld_r32_cl", ()):
lo = GeneralPurposeRegister32()
hi = GeneralPurposeRegister32()
SHLD(lo, hi, cl)
RETURN()
class SHRDwithCL(unittest.TestCase):
def runTest(self):
with Function("test_shrd_r32_cl", ()):
lo = GeneralPurposeRegister32()
hi = GeneralPurposeRegister32()
SHRD(lo, hi, cl)
RETURN()
class BLENDVPDwithXMM0(unittest.TestCase):
def runTest(self):
with Function("test_blendvpd_xmm_xmm_xmm0", (), target=uarch.default + isa.sse4_1):
x = XMMRegister()
y = XMMRegister()
BLENDVPD(x, y, xmm0)
RETURN()
class BLENDVPSwithXMM0(unittest.TestCase):
def runTest(self):
with Function("test_blendvps_xmm_xmm_xmm0", (), target=uarch.default + isa.sse4_1):
x = XMMRegister()
y = XMMRegister()
BLENDVPS(x, y, xmm0)
RETURN()
class PBLENDVBwithXMM0(unittest.TestCase):
def runTest(self):
with Function("test_pblendv_xmm_xmm_xmm0", (), target=uarch.default + isa.sse4_1):
x = XMMRegister()
y = XMMRegister()
PBLENDVB(x, y, xmm0)
RETURN()
class SHA256RNDS2withXMM0(unittest.TestCase):
def runTest(self):
with Function("test_sha256rnds2_xmm_xmm_xmm0", (), target=uarch.default + isa.sha):
x = XMMRegister()
y = XMMRegister()
SHA256RNDS2(x, y, xmm0)
RETURN()
|
# This file is auto-generated by /codegen/x86_64_test_encoding.py
# Reference opcodes are generated by:
# GNU assembler (GNU Binutils) 2.28.51.20170402
from peachpy.x86_64 import *
import unittest
class TestAESDEC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDE, 0xCE]), AESDEC(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDE, 0x4C, 0xC2, 0xB3]), AESDEC(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestAESDECLAST(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDF, 0xCE]), AESDECLAST(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDF, 0x4C, 0xC2, 0xB3]), AESDECLAST(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestAESENC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDC, 0xCE]), AESENC(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDC, 0x4C, 0xC2, 0xB3]), AESENC(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestAESENCLAST(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDD, 0xCE]), AESENCLAST(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDD, 0x4C, 0xC2, 0xB3]), AESENCLAST(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestAESIMC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDB, 0xCE]), AESIMC(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xDB, 0x4C, 0xC2, 0xB3]), AESIMC(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestAESKEYGENASSIST(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0xDF, 0xCE, 0x02]), AESKEYGENASSIST(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0xDF, 0x4C, 0xC2, 0xB3, 0x02]), AESKEYGENASSIST(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestVAESDEC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xDE, 0xCB]), VAESDEC(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xDE, 0x4C, 0xC2, 0xB3]), VAESDEC(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
class TestVAESDECLAST(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xDF, 0xCB]), VAESDECLAST(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xDF, 0x4C, 0xC2, 0xB3]), VAESDECLAST(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
class TestVAESENC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xDC, 0xCB]), VAESENC(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xDC, 0x4C, 0xC2, 0xB3]), VAESENC(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
class TestVAESENCLAST(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xDD, 0xCB]), VAESENCLAST(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xDD, 0x4C, 0xC2, 0xB3]), VAESENCLAST(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
class TestVAESIMC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0xDB, 0xCE]), VAESIMC(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0xDB, 0x4C, 0xC2, 0xB3]), VAESIMC(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVAESKEYGENASSIST(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0xDF, 0xCE, 0x02]), VAESKEYGENASSIST(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0xDF, 0x4C, 0xC2, 0xB3, 0x02]), VAESKEYGENASSIST(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestSHA1MSG1(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xC9, 0xCE]), SHA1MSG1(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xC9, 0x4C, 0xC2, 0xB3]), SHA1MSG1(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSHA1MSG2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xCA, 0xCE]), SHA1MSG2(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xCA, 0x4C, 0xC2, 0xB3]), SHA1MSG2(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSHA1NEXTE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xC8, 0xCE]), SHA1NEXTE(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xC8, 0x4C, 0xC2, 0xB3]), SHA1NEXTE(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSHA1RNDS4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x3A, 0xCC, 0xCE, 0x02]), SHA1RNDS4(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x3A, 0xCC, 0x4C, 0xC2, 0xB3, 0x02]), SHA1RNDS4(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestSHA256MSG1(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xCC, 0xCE]), SHA256MSG1(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xCC, 0x4C, 0xC2, 0xB3]), SHA256MSG1(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSHA256MSG2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xCD, 0xCE]), SHA256MSG2(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xCD, 0x4C, 0xC2, 0xB3]), SHA256MSG2(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSHA256RNDS2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xCB, 0xCE]), SHA256RNDS2(xmm1, xmm14, xmm0).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xCB, 0x4C, 0xC2, 0xB3]), SHA256RNDS2(xmm1, oword[r10 + rax*8 - 77], xmm0).encode())
class TestPCLMULQDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x44, 0xCE, 0x02]), PCLMULQDQ(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x44, 0x4C, 0xC2, 0xB3, 0x02]), PCLMULQDQ(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCLMULQDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x44, 0xCB, 0x02]), VPCLMULQDQ(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x44, 0x4C, 0xC2, 0xB3, 0x02]), VPCLMULQDQ(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestRDRAND(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x0F, 0xC7, 0xF6]), RDRAND(si).encode())
self.assertEqual(bytearray([0x0F, 0xC7, 0xF5]), RDRAND(ebp).encode())
self.assertEqual(bytearray([0x48, 0x0F, 0xC7, 0xF1]), RDRAND(rcx).encode())
class TestRDSEED(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x0F, 0xC7, 0xFE]), RDSEED(si).encode())
self.assertEqual(bytearray([0x0F, 0xC7, 0xFD]), RDSEED(ebp).encode())
self.assertEqual(bytearray([0x48, 0x0F, 0xC7, 0xF9]), RDSEED(rcx).encode())
|
# This file is auto-generated by /codegen/x86_64_test_encoding.py
# Reference opcodes are generated by:
# GNU assembler (GNU Binutils) 2.28.51.20170402
from peachpy.x86_64 import *
import unittest
class TestKADDB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD5, 0x4A, 0xED]), KADDB(k5, k5, k5).encode())
class TestKADDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD4, 0x4A, 0xED]), KADDW(k5, k5, k5).encode())
class TestKADDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD5, 0x4A, 0xED]), KADDD(k5, k5, k5).encode())
class TestKADDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD4, 0x4A, 0xED]), KADDQ(k5, k5, k5).encode())
class TestKANDB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD5, 0x41, 0xED]), KANDB(k5, k5, k5).encode())
class TestKANDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD4, 0x41, 0xED]), KANDW(k5, k5, k5).encode())
class TestKANDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD5, 0x41, 0xED]), KANDD(k5, k5, k5).encode())
class TestKANDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD4, 0x41, 0xED]), KANDQ(k5, k5, k5).encode())
class TestKANDNB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD5, 0x42, 0xED]), KANDNB(k5, k5, k5).encode())
class TestKANDNW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD4, 0x42, 0xED]), KANDNW(k5, k5, k5).encode())
class TestKANDND(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD5, 0x42, 0xED]), KANDND(k5, k5, k5).encode())
class TestKANDNQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD4, 0x42, 0xED]), KANDNQ(k5, k5, k5).encode())
class TestKORB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD5, 0x45, 0xED]), KORB(k5, k5, k5).encode())
class TestKORW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD4, 0x45, 0xED]), KORW(k5, k5, k5).encode())
class TestKORD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD5, 0x45, 0xED]), KORD(k5, k5, k5).encode())
class TestKORQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD4, 0x45, 0xED]), KORQ(k5, k5, k5).encode())
class TestKXNORB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD5, 0x46, 0xED]), KXNORB(k5, k5, k5).encode())
class TestKXNORW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD4, 0x46, 0xED]), KXNORW(k5, k5, k5).encode())
class TestKXNORD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD5, 0x46, 0xED]), KXNORD(k5, k5, k5).encode())
class TestKXNORQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD4, 0x46, 0xED]), KXNORQ(k5, k5, k5).encode())
class TestKXORB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD5, 0x47, 0xED]), KXORB(k5, k5, k5).encode())
class TestKXORW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD4, 0x47, 0xED]), KXORW(k5, k5, k5).encode())
class TestKXORD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD5, 0x47, 0xED]), KXORD(k5, k5, k5).encode())
class TestKXORQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD4, 0x47, 0xED]), KXORQ(k5, k5, k5).encode())
class TestKMOVB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xF9, 0x90, 0xED]), KMOVB(k5, k5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x92, 0xE8]), KMOVB(k5, r8d).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x90, 0x6E, 0x40]), KMOVB(k5, byte[r14 + 64]).encode())
self.assertEqual(bytearray([0xC5, 0xF9, 0x93, 0xED]), KMOVB(ebp, k5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x91, 0x6E, 0xC0]), KMOVB(byte[r14 - 64], k5).encode())
class TestKMOVW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xF8, 0x90, 0xED]), KMOVW(k5, k5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x92, 0xE8]), KMOVW(k5, r8d).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x90, 0x6D, 0x40]), KMOVW(k5, word[r13 + 64]).encode())
self.assertEqual(bytearray([0xC5, 0xF8, 0x93, 0xED]), KMOVW(ebp, k5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x91, 0x6D, 0xC0]), KMOVW(word[r13 - 64], k5).encode())
class TestKMOVD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xF9, 0x90, 0xED]), KMOVD(k5, k5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x92, 0xE8]), KMOVD(k5, r8d).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xF9, 0x90, 0x6C, 0x24, 0x40]), KMOVD(k5, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0xC5, 0xFB, 0x93, 0xED]), KMOVD(ebp, k5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xF9, 0x91, 0x6C, 0x24, 0xC0]), KMOVD(dword[r12 - 64], k5).encode())
class TestKMOVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xF8, 0x90, 0xED]), KMOVQ(k5, k5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFB, 0x92, 0xEF]), KMOVQ(k5, r15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xF8, 0x90, 0x6B, 0x40]), KMOVQ(k5, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xE1, 0xFB, 0x93, 0xCD]), KMOVQ(rcx, k5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xF8, 0x91, 0x6B, 0xC0]), KMOVQ(qword[r11 - 64], k5).encode())
class TestKNOTB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xF9, 0x44, 0xED]), KNOTB(k5, k5).encode())
class TestKNOTW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xF8, 0x44, 0xED]), KNOTW(k5, k5).encode())
class TestKNOTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xF9, 0x44, 0xED]), KNOTD(k5, k5).encode())
class TestKNOTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xF8, 0x44, 0xED]), KNOTQ(k5, k5).encode())
class TestKUNPCKBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD5, 0x4B, 0xED]), KUNPCKBW(k5, k5, k5).encode())
class TestKUNPCKWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xD4, 0x4B, 0xED]), KUNPCKWD(k5, k5, k5).encode())
class TestKUNPCKDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xD4, 0x4B, 0xED]), KUNPCKDQ(k5, k5, k5).encode())
class TestKTESTB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xF9, 0x99, 0xED]), KTESTB(k5, k5).encode())
class TestKTESTW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xF8, 0x99, 0xED]), KTESTW(k5, k5).encode())
class TestKTESTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xF9, 0x99, 0xED]), KTESTD(k5, k5).encode())
class TestKTESTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xF8, 0x99, 0xED]), KTESTQ(k5, k5).encode())
class TestKORTESTB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xF9, 0x98, 0xED]), KORTESTB(k5, k5).encode())
class TestKORTESTW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xF8, 0x98, 0xED]), KORTESTW(k5, k5).encode())
class TestKORTESTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xF9, 0x98, 0xED]), KORTESTD(k5, k5).encode())
class TestKORTESTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE1, 0xF8, 0x98, 0xED]), KORTESTQ(k5, k5).encode())
class TestKSHIFTLB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x79, 0x32, 0xED, 0x02]), KSHIFTLB(k5, k5, 2).encode())
class TestKSHIFTLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0xF9, 0x32, 0xED, 0x02]), KSHIFTLW(k5, k5, 2).encode())
class TestKSHIFTLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x79, 0x33, 0xED, 0x02]), KSHIFTLD(k5, k5, 2).encode())
class TestKSHIFTLQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0xF9, 0x33, 0xED, 0x02]), KSHIFTLQ(k5, k5, 2).encode())
class TestKSHIFTRB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x79, 0x30, 0xED, 0x02]), KSHIFTRB(k5, k5, 2).encode())
class TestKSHIFTRW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0xF9, 0x30, 0xED, 0x02]), KSHIFTRW(k5, k5, 2).encode())
class TestKSHIFTRD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x79, 0x31, 0xED, 0x02]), KSHIFTRD(k5, k5, 2).encode())
class TestKSHIFTRQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0xF9, 0x31, 0xED, 0x02]), KSHIFTRQ(k5, k5, 2).encode())
|
# This file is auto-generated by /codegen/x86_64_test_encoding.py
# Reference opcodes are generated by:
# GNU assembler (GNU Binutils) 2.28.51.20170402
from peachpy.x86_64 import *
import unittest
class TestVMOVSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x11, 0x64, 0x24, 0xC0]), VMOVSS(dword[r12 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7E, 0x8A, 0x10, 0x74, 0x24, 0x10]), VMOVSS(xmm30(k2.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x10, 0x4C, 0xCC, 0x9D]), VMOVSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7A, 0x11, 0x74, 0xCC, 0x9D]), VMOVSS(dword[r12 + rcx*8 - 99], xmm14).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5E, 0x8A, 0x10, 0xF3]), VMOVSS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0x10, 0xCB]), VMOVSS(xmm1, xmm14, xmm3).encode())
class TestVEXTRACTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x63, 0x79, 0x17, 0xF5, 0x02]), VEXTRACTPS(ebp, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x79, 0x17, 0xE5, 0x02]), VEXTRACTPS(ebp, xmm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0x43, 0x79, 0x17, 0x74, 0xCC, 0x9D, 0x02]), VEXTRACTPS(dword[r12 + rcx*8 - 99], xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x17, 0x64, 0x24, 0xC0, 0x02]), VEXTRACTPS(dword[r12 - 64], xmm4, 2).encode())
class TestVINSERTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x21, 0xCB, 0x02]), VINSERTPS(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0x5D, 0x08, 0x21, 0xC3, 0x02]), VINSERTPS(xmm16, xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x21, 0x4C, 0xCC, 0x9D, 0x02]), VINSERTPS(xmm1, xmm14, dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x5D, 0x08, 0x21, 0x44, 0x24, 0xE0, 0x02]), VINSERTPS(xmm16, xmm4, dword[r12 - 128], 2).encode())
class TestVADDSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5E, 0x8A, 0x58, 0x74, 0x24, 0xE0]), VADDSS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0x58, 0xCB]), VADDSS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x58, 0x4C, 0xCC, 0x9D]), VADDSS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5E, 0x9A, 0x58, 0xF3]), VADDSS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVSUBSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5E, 0x8A, 0x5C, 0x74, 0x24, 0xE0]), VSUBSS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0x5C, 0xCB]), VSUBSS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x5C, 0x4C, 0xCC, 0x9D]), VSUBSS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5E, 0x9A, 0x5C, 0xF3]), VSUBSS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVMULSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5E, 0x8A, 0x59, 0x74, 0x24, 0xE0]), VMULSS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0x59, 0xCB]), VMULSS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x59, 0x4C, 0xCC, 0x9D]), VMULSS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5E, 0x9A, 0x59, 0xF3]), VMULSS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVDIVSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5E, 0x8A, 0x5E, 0x74, 0x24, 0xE0]), VDIVSS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0x5E, 0xCB]), VDIVSS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x5E, 0x4C, 0xCC, 0x9D]), VDIVSS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5E, 0x9A, 0x5E, 0xF3]), VDIVSS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVSQRTSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5E, 0x8A, 0x51, 0x74, 0x24, 0xE0]), VSQRTSS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0x51, 0xCB]), VSQRTSS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x51, 0x4C, 0xCC, 0x9D]), VSQRTSS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5E, 0x9A, 0x51, 0xF3]), VSQRTSS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVROUNDSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x0A, 0xCB, 0x02]), VROUNDSS(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x0A, 0x4C, 0xCC, 0x9D, 0x02]), VROUNDSS(xmm1, xmm14, dword[r12 + rcx*8 - 99], 2).encode())
class TestVRNDSCALESS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x0A, 0x74, 0x24, 0xE0, 0x02]), VRNDSCALESS(xmm30(k2.z), xmm4, dword[r12 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x9A, 0x0A, 0xF3, 0x02]), VRNDSCALESS(xmm30(k2.z), xmm4, xmm19, {sae}, 2).encode())
class TestVRANGESS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x51, 0x74, 0x24, 0xE0, 0x02]), VRANGESS(xmm30(k2.z), xmm4, dword[r12 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x9A, 0x51, 0xF3, 0x02]), VRANGESS(xmm30(k2.z), xmm4, xmm19, {sae}, 2).encode())
class TestVMINSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5E, 0x8A, 0x5D, 0x74, 0x24, 0xE0]), VMINSS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0x5D, 0xCB]), VMINSS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x5D, 0x4C, 0xCC, 0x9D]), VMINSS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5E, 0x9A, 0x5D, 0xF3]), VMINSS(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVMAXSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5E, 0x8A, 0x5F, 0x74, 0x24, 0xE0]), VMAXSS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0x5F, 0xCB]), VMAXSS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x5F, 0x4C, 0xCC, 0x9D]), VMAXSS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5E, 0x9A, 0x5F, 0xF3]), VMAXSS(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVREDUCESS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x8A, 0x57, 0xF3, 0x02]), VREDUCESS(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x57, 0x74, 0x24, 0xE0, 0x02]), VREDUCESS(xmm30(k2.z), xmm4, dword[r12 - 128], 2).encode())
class TestVGETMANTSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x27, 0x74, 0x24, 0xE0, 0x02]), VGETMANTSS(xmm30(k2.z), xmm4, dword[r12 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x9A, 0x27, 0xF3, 0x02]), VGETMANTSS(xmm30(k2.z), xmm4, xmm19, {sae}, 2).encode())
class TestVGETEXPSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x43, 0x74, 0x24, 0xE0]), VGETEXPSS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0x43, 0xF3]), VGETEXPSS(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVSCALEFSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x2D, 0x74, 0x24, 0xE0]), VSCALEFSS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0x2D, 0xF3]), VSCALEFSS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFIXUPIMMSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x55, 0x74, 0x24, 0xE0, 0x02]), VFIXUPIMMSS(xmm30(k2.z), xmm4, dword[r12 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x9A, 0x55, 0xF3, 0x02]), VFIXUPIMMSS(xmm30(k2.z), xmm4, xmm19, {sae}, 2).encode())
class TestVFPCLASSSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF3, 0x7D, 0x0E, 0x67, 0xE4, 0x02]), VFPCLASSSS(k4(k6), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x7D, 0x0E, 0x67, 0x64, 0x24, 0x10, 0x02]), VFPCLASSSS(k4(k6), dword[r12 + 64], 2).encode())
class TestVRCPSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x8A, 0x53, 0xCB]), VRCPSS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x53, 0x4C, 0xCC, 0x9D]), VRCPSS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
class TestVRSQRTSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x8A, 0x52, 0xCB]), VRSQRTSS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x52, 0x4C, 0xCC, 0x9D]), VRSQRTSS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
class TestVRCP14SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x4D, 0xF3]), VRCP14SS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x4D, 0x74, 0x24, 0xE0]), VRCP14SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
class TestVRSQRT14SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x4F, 0xF3]), VRSQRT14SS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x4F, 0x74, 0x24, 0xE0]), VRSQRT14SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
class TestVRCP28SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xCB, 0x74, 0x24, 0xE0]), VRCP28SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xCB, 0xF3]), VRCP28SS(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVRSQRT28SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xCD, 0x74, 0x24, 0xE0]), VRSQRT28SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xCD, 0xF3]), VRSQRT28SS(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVCMPSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x5E, 0x0E, 0xC2, 0x64, 0x24, 0xE0, 0x02]), VCMPSS(k4(k6), xmm4, dword[r12 - 128], 2).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0xC2, 0xCB, 0x02]), VCMPSS(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0xC2, 0x4C, 0xCC, 0x9D, 0x02]), VCMPSS(xmm1, xmm14, dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x5E, 0x1E, 0xC2, 0xE3, 0x02]), VCMPSS(k4(k6), xmm4, xmm19, {sae}, 2).encode())
class TestVCOMISS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x2F, 0xCE]), VCOMISS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x2F, 0x4C, 0xCC, 0x9D]), VCOMISS(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7C, 0x08, 0x2F, 0x44, 0x24, 0x10]), VCOMISS(xmm16, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7C, 0x18, 0x2F, 0xC4]), VCOMISS(xmm16, xmm4, {sae}).encode())
class TestVUCOMISS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x2E, 0xCE]), VUCOMISS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x2E, 0x4C, 0xCC, 0x9D]), VUCOMISS(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7C, 0x08, 0x2E, 0x44, 0x24, 0x10]), VUCOMISS(xmm16, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7C, 0x18, 0x2E, 0xC4]), VUCOMISS(xmm16, xmm4, {sae}).encode())
class TestVMOVSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x11, 0x63, 0xC0]), VMOVSD(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFF, 0x8A, 0x10, 0x73, 0x08]), VMOVSD(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x10, 0x4C, 0xD3, 0xA8]), VMOVSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7B, 0x11, 0x74, 0xD3, 0xA8]), VMOVSD(qword[r11 + rdx*8 - 88], xmm14).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDF, 0x8A, 0x10, 0xF3]), VMOVSD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0x10, 0xCB]), VMOVSD(xmm1, xmm14, xmm3).encode())
class TestVADDSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDF, 0x8A, 0x58, 0x73, 0xF0]), VADDSD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0x58, 0xCB]), VADDSD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x58, 0x4C, 0xD3, 0xA8]), VADDSD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDF, 0x9A, 0x58, 0xF3]), VADDSD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVSUBSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDF, 0x8A, 0x5C, 0x73, 0xF0]), VSUBSD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0x5C, 0xCB]), VSUBSD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x5C, 0x4C, 0xD3, 0xA8]), VSUBSD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDF, 0x9A, 0x5C, 0xF3]), VSUBSD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVMULSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDF, 0x8A, 0x59, 0x73, 0xF0]), VMULSD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0x59, 0xCB]), VMULSD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x59, 0x4C, 0xD3, 0xA8]), VMULSD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDF, 0x9A, 0x59, 0xF3]), VMULSD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVDIVSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDF, 0x8A, 0x5E, 0x73, 0xF0]), VDIVSD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0x5E, 0xCB]), VDIVSD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x5E, 0x4C, 0xD3, 0xA8]), VDIVSD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDF, 0x9A, 0x5E, 0xF3]), VDIVSD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVSQRTSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDF, 0x8A, 0x51, 0x73, 0xF0]), VSQRTSD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0x51, 0xCB]), VSQRTSD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x51, 0x4C, 0xD3, 0xA8]), VSQRTSD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDF, 0x9A, 0x51, 0xF3]), VSQRTSD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVROUNDSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x0B, 0xCB, 0x02]), VROUNDSD(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x0B, 0x4C, 0xD3, 0xA8, 0x02]), VROUNDSD(xmm1, xmm14, qword[r11 + rdx*8 - 88], 2).encode())
class TestVRNDSCALESD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xDD, 0x8A, 0x0B, 0x73, 0xF0, 0x02]), VRNDSCALESD(xmm30(k2.z), xmm4, qword[r11 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0xDD, 0x9A, 0x0B, 0xF3, 0x02]), VRNDSCALESD(xmm30(k2.z), xmm4, xmm19, {sae}, 2).encode())
class TestVRANGESD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xDD, 0x8A, 0x51, 0x73, 0xF0, 0x02]), VRANGESD(xmm30(k2.z), xmm4, qword[r11 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0xDD, 0x9A, 0x51, 0xF3, 0x02]), VRANGESD(xmm30(k2.z), xmm4, xmm19, {sae}, 2).encode())
class TestVMINSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDF, 0x8A, 0x5D, 0x73, 0xF0]), VMINSD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0x5D, 0xCB]), VMINSD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x5D, 0x4C, 0xD3, 0xA8]), VMINSD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDF, 0x9A, 0x5D, 0xF3]), VMINSD(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVMAXSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDF, 0x8A, 0x5F, 0x73, 0xF0]), VMAXSD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0x5F, 0xCB]), VMAXSD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x5F, 0x4C, 0xD3, 0xA8]), VMAXSD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDF, 0x9A, 0x5F, 0xF3]), VMAXSD(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVREDUCESD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x23, 0xDD, 0x8A, 0x57, 0xF3, 0x02]), VREDUCESD(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0xDD, 0x8A, 0x57, 0x73, 0xF0, 0x02]), VREDUCESD(xmm30(k2.z), xmm4, qword[r11 - 128], 2).encode())
class TestVGETMANTSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xDD, 0x8A, 0x27, 0x73, 0xF0, 0x02]), VGETMANTSD(xmm30(k2.z), xmm4, qword[r11 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0xDD, 0x9A, 0x27, 0xF3, 0x02]), VGETMANTSD(xmm30(k2.z), xmm4, xmm19, {sae}, 2).encode())
class TestVGETEXPSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x43, 0x73, 0xF0]), VGETEXPSD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0x43, 0xF3]), VGETEXPSD(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVSCALEFSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x2D, 0x73, 0xF0]), VSCALEFSD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0x2D, 0xF3]), VSCALEFSD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFIXUPIMMSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xDD, 0x8A, 0x55, 0x73, 0xF0, 0x02]), VFIXUPIMMSD(xmm30(k2.z), xmm4, qword[r11 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0xDD, 0x9A, 0x55, 0xF3, 0x02]), VFIXUPIMMSD(xmm30(k2.z), xmm4, xmm19, {sae}, 2).encode())
class TestVFPCLASSSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF3, 0xFD, 0x0E, 0x67, 0xE4, 0x02]), VFPCLASSSD(k4(k6), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xFD, 0x0E, 0x67, 0x63, 0x08, 0x02]), VFPCLASSSD(k4(k6), qword[r11 + 64], 2).encode())
class TestVRCP14SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x4D, 0xF3]), VRCP14SD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x4D, 0x73, 0xF0]), VRCP14SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
class TestVRSQRT14SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x4F, 0xF3]), VRSQRT14SD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x4F, 0x73, 0xF0]), VRSQRT14SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
class TestVRCP28SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xCB, 0x73, 0xF0]), VRCP28SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xCB, 0xF3]), VRCP28SD(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVRSQRT28SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xCD, 0x73, 0xF0]), VRSQRT28SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xCD, 0xF3]), VRSQRT28SD(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVCMPSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0xDF, 0x0E, 0xC2, 0x63, 0xF0, 0x02]), VCMPSD(k4(k6), xmm4, qword[r11 - 128], 2).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0xC2, 0xCB, 0x02]), VCMPSD(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0xC2, 0x4C, 0xD3, 0xA8, 0x02]), VCMPSD(xmm1, xmm14, qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0xDF, 0x1E, 0xC2, 0xE3, 0x02]), VCMPSD(k4(k6), xmm4, xmm19, {sae}, 2).encode())
class TestVCOMISD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x2F, 0xCE]), VCOMISD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x2F, 0x4C, 0xD3, 0xA8]), VCOMISD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0x08, 0x2F, 0x43, 0x08]), VCOMISD(xmm16, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0x18, 0x2F, 0xC4]), VCOMISD(xmm16, xmm4, {sae}).encode())
class TestVUCOMISD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x2E, 0xCE]), VUCOMISD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x2E, 0x4C, 0xD3, 0xA8]), VUCOMISD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0x08, 0x2E, 0x43, 0x08]), VUCOMISD(xmm16, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0x18, 0x2E, 0xC4]), VUCOMISD(xmm16, xmm4, {sae}).encode())
class TestVMOVAPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x29, 0x62, 0xC0]), VMOVAPS(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7C, 0x8A, 0x28, 0xF4]), VMOVAPS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x29, 0x69, 0xC0]), VMOVAPS(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7C, 0xAD, 0x28, 0xDD]), VMOVAPS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x48, 0x29, 0x50, 0xFF]), VMOVAPS(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7C, 0xCE, 0x28, 0xCA]), VMOVAPS(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x8A, 0x28, 0x72, 0x04]), VMOVAPS(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7C, 0xAD, 0x28, 0x59, 0x02]), VMOVAPS(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7C, 0xCE, 0x28, 0x48, 0x01]), VMOVAPS(zmm9(k6.z), zword[r8 + 64]).encode())
self.assertEqual(bytearray([0xC5, 0x78, 0x29, 0xF1]), VMOVAPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x28, 0x4C, 0xC2, 0xB3]), VMOVAPS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x7C, 0x29, 0xFA]), VMOVAPS(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x28, 0x54, 0xD9, 0xBE]), VMOVAPS(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x78, 0x29, 0x74, 0xC2, 0xB3]), VMOVAPS(oword[r10 + rax*8 - 77], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7C, 0x29, 0x7C, 0xD9, 0xBE]), VMOVAPS(hword[r9 + rbx*8 - 66], ymm15).encode())
class TestVMOVUPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x11, 0x62, 0xC0]), VMOVUPS(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7C, 0x8A, 0x10, 0xF4]), VMOVUPS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x11, 0x69, 0xC0]), VMOVUPS(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7C, 0xAD, 0x10, 0xDD]), VMOVUPS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x48, 0x11, 0x50, 0xFF]), VMOVUPS(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7C, 0xCE, 0x10, 0xCA]), VMOVUPS(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x8A, 0x10, 0x72, 0x04]), VMOVUPS(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7C, 0xAD, 0x10, 0x59, 0x02]), VMOVUPS(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7C, 0xCE, 0x10, 0x48, 0x01]), VMOVUPS(zmm9(k6.z), zword[r8 + 64]).encode())
self.assertEqual(bytearray([0xC5, 0x78, 0x11, 0xF1]), VMOVUPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x10, 0x4C, 0xC2, 0xB3]), VMOVUPS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x7C, 0x11, 0xFA]), VMOVUPS(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x10, 0x54, 0xD9, 0xBE]), VMOVUPS(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x78, 0x11, 0x74, 0xC2, 0xB3]), VMOVUPS(oword[r10 + rax*8 - 77], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7C, 0x11, 0x7C, 0xD9, 0xBE]), VMOVUPS(hword[r9 + rbx*8 - 66], ymm15).encode())
class TestVMOVLPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x41, 0x78, 0x13, 0x74, 0xD3, 0xA8]), VMOVLPS(qword[r11 + rdx*8 - 88], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x13, 0x63, 0xC0]), VMOVLPS(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x12, 0x4C, 0xD3, 0xA8]), VMOVLPS(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x5C, 0x08, 0x12, 0x43, 0xF0]), VMOVLPS(xmm16, xmm4, qword[r11 - 128]).encode())
class TestVMOVHPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x41, 0x78, 0x17, 0x74, 0xD3, 0xA8]), VMOVHPS(qword[r11 + rdx*8 - 88], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x17, 0x63, 0xC0]), VMOVHPS(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x16, 0x4C, 0xD3, 0xA8]), VMOVHPS(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x5C, 0x08, 0x16, 0x43, 0xF0]), VMOVHPS(xmm16, xmm4, qword[r11 - 128]).encode())
class TestVMASKMOVPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x2C, 0x4C, 0xC2, 0xB3]), VMASKMOVPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x2C, 0x54, 0xD9, 0xBE]), VMASKMOVPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x2E, 0x5C, 0xC2, 0xB3]), VMASKMOVPS(oword[r10 + rax*8 - 77], xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x2E, 0x64, 0xD9, 0xBE]), VMASKMOVPS(hword[r9 + rbx*8 - 66], ymm15, ymm4).encode())
class TestVMOVMSKPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x50, 0xEE]), VMOVMSKPS(ebp, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x50, 0xEF]), VMOVMSKPS(ebp, ymm15).encode())
class TestVMOVNTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x41, 0x78, 0x2B, 0x74, 0xC2, 0xB3]), VMOVNTPS(oword[r10 + rax*8 - 77], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x2B, 0x62, 0xC0]), VMOVNTPS(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7C, 0x2B, 0x7C, 0xD9, 0xBE]), VMOVNTPS(hword[r9 + rbx*8 - 66], ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x2B, 0x69, 0xC0]), VMOVNTPS(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x48, 0x2B, 0x50, 0xFF]), VMOVNTPS(zword[r8 - 64], zmm26).encode())
class TestVBROADCASTSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x18, 0xDC]), VBROADCASTSS(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x18, 0xCC]), VBROADCASTSS(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x18, 0x5C, 0x24, 0x10]), VBROADCASTSS(ymm19(k5.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x18, 0x4C, 0x24, 0x10]), VBROADCASTSS(zmm9(k6.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x18, 0xCE]), VBROADCASTSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x18, 0x4C, 0xCC, 0x9D]), VBROADCASTSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x18, 0xD6]), VBROADCASTSS(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x18, 0x54, 0xCC, 0x9D]), VBROADCASTSS(ymm2, dword[r12 + rcx*8 - 99]).encode())
class TestVMOVSLDUP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x61, 0x7E, 0x8A, 0x12, 0xF4]), VMOVSLDUP(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7E, 0xAD, 0x12, 0xDD]), VMOVSLDUP(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7E, 0xCE, 0x12, 0xCA]), VMOVSLDUP(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7E, 0x8A, 0x12, 0x72, 0x04]), VMOVSLDUP(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7E, 0xAD, 0x12, 0x59, 0x02]), VMOVSLDUP(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7E, 0xCE, 0x12, 0x48, 0x01]), VMOVSLDUP(zmm9(k6.z), zword[r8 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x12, 0xCE]), VMOVSLDUP(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x12, 0x4C, 0xC2, 0xB3]), VMOVSLDUP(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0x12, 0xD7]), VMOVSLDUP(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0x12, 0x54, 0xD9, 0xBE]), VMOVSLDUP(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVMOVSHDUP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x61, 0x7E, 0x8A, 0x16, 0xF4]), VMOVSHDUP(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7E, 0xAD, 0x16, 0xDD]), VMOVSHDUP(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7E, 0xCE, 0x16, 0xCA]), VMOVSHDUP(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7E, 0x8A, 0x16, 0x72, 0x04]), VMOVSHDUP(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7E, 0xAD, 0x16, 0x59, 0x02]), VMOVSHDUP(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7E, 0xCE, 0x16, 0x48, 0x01]), VMOVSHDUP(zmm9(k6.z), zword[r8 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x16, 0xCE]), VMOVSHDUP(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x16, 0x4C, 0xC2, 0xB3]), VMOVSHDUP(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0x16, 0xD7]), VMOVSHDUP(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0x16, 0x54, 0xD9, 0xBE]), VMOVSHDUP(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVEXPANDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x88, 0xF4]), VEXPANDPS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x88, 0xDD]), VEXPANDPS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0x88, 0xCA]), VEXPANDPS(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x88, 0x72, 0x10]), VEXPANDPS(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x88, 0x59, 0x10]), VEXPANDPS(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x88, 0x48, 0x10]), VEXPANDPS(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVCOMPRESSPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7D, 0x8A, 0x8A, 0xE6]), VCOMPRESSPS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x08, 0x8A, 0x62, 0xF0]), VCOMPRESSPS(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0x7D, 0xAD, 0x8A, 0xEB]), VCOMPRESSPS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x28, 0x8A, 0x69, 0xF0]), VCOMPRESSPS(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0xCE, 0x8A, 0xD1]), VCOMPRESSPS(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x48, 0x8A, 0x50, 0xF0]), VCOMPRESSPS(zword[r8 - 64], zmm26).encode())
class TestVGATHERDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7D, 0x09, 0x92, 0x6C, 0x86, 0xE0]), VGATHERDPS(xmm5(k1), [rsi + xmm0 * 4 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7D, 0x2B, 0x92, 0x44, 0x83, 0x0C]), VGATHERDPS(ymm24(k3), [r11 + ymm8 * 4 + 48]).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x47, 0x92, 0x54, 0x9F, 0xFC]), VGATHERDPS(zmm26(k7), [r15 + zmm19 * 4 - 16]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x61, 0x92, 0x4C, 0x86, 0x80]), VGATHERDPS(xmm1, [rsi + xmm0 * 4 - 128], xmm3).encode())
self.assertEqual(bytearray([0xC4, 0x82, 0x5D, 0x92, 0x54, 0x83, 0x30]), VGATHERDPS(ymm2, [r11 + ymm8 * 4 + 48], ymm4).encode())
class TestVGATHERQPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7D, 0x09, 0x93, 0x6C, 0xCE, 0x0A]), VGATHERQPS(xmm5(k1), [rsi + xmm1 * 8 + 40]).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7D, 0x29, 0x93, 0x6C, 0xCB, 0xF2]), VGATHERQPS(xmm5(k1), [r11 + ymm9 * 8 - 56]).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x43, 0x93, 0x44, 0xE7, 0x12]), VGATHERQPS(ymm24(k3), [r15 + zmm20 * 8 + 72]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x61, 0x93, 0x4C, 0xCE, 0x28]), VGATHERQPS(xmm1, [rsi + xmm1 * 8 + 40], xmm3).encode())
self.assertEqual(bytearray([0xC4, 0x82, 0x65, 0x93, 0x4C, 0xCB, 0xC8]), VGATHERQPS(xmm1, [r11 + ymm9 * 8 - 56], xmm3).encode())
class TestVGATHERPF0DPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x43, 0xC6, 0x4C, 0x9F, 0xFC]), VGATHERPF0DPS([r15 + zmm19(k3) * 4 - 16]).encode())
class TestVGATHERPF0QPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x46, 0xC7, 0x4C, 0xE7, 0x12]), VGATHERPF0QPS([r15 + zmm20(k6) * 8 + 72]).encode())
class TestVGATHERPF1DPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x43, 0xC6, 0x54, 0x9F, 0xFC]), VGATHERPF1DPS([r15 + zmm19(k3) * 4 - 16]).encode())
class TestVGATHERPF1QPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x46, 0xC7, 0x54, 0xE7, 0x12]), VGATHERPF1QPS([r15 + zmm20(k6) * 8 + 72]).encode())
class TestVSCATTERDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7D, 0x09, 0xA2, 0x64, 0x86, 0xE0]), VSCATTERDPS([rsi + xmm0(k1) * 4 - 128], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7D, 0x2A, 0xA2, 0x6C, 0x83, 0x0C]), VSCATTERDPS([r11 + ymm8(k2) * 4 + 48], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x43, 0xA2, 0x54, 0x9F, 0xFC]), VSCATTERDPS([r15 + zmm19(k3) * 4 - 16], zmm26).encode())
class TestVSCATTERQPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7D, 0x0C, 0xA3, 0x64, 0xCE, 0x0A]), VSCATTERQPS([rsi + xmm1(k4) * 8 + 40], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7D, 0x2D, 0xA3, 0x64, 0xCB, 0xF2]), VSCATTERQPS([r11 + ymm9(k5) * 8 - 56], xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x46, 0xA3, 0x6C, 0xE7, 0x12]), VSCATTERQPS([r15 + zmm20(k6) * 8 + 72], ymm5).encode())
class TestVSCATTERPF0DPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x43, 0xC6, 0x6C, 0x9F, 0xFC]), VSCATTERPF0DPS([r15 + zmm19(k3) * 4 - 16]).encode())
class TestVSCATTERPF0QPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x46, 0xC7, 0x6C, 0xE7, 0x12]), VSCATTERPF0QPS([r15 + zmm20(k6) * 8 + 72]).encode())
class TestVSCATTERPF1DPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x43, 0xC6, 0x74, 0x9F, 0xFC]), VSCATTERPF1DPS([r15 + zmm19(k3) * 4 - 16]).encode())
class TestVSCATTERPF1QPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x46, 0xC7, 0x74, 0xE7, 0x12]), VSCATTERPF1QPS([r15 + zmm20(k6) * 8 + 72]).encode())
class TestVMOVAPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x29, 0x62, 0xC0]), VMOVAPD(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0x28, 0xF4]), VMOVAPD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x29, 0x69, 0xC0]), VMOVAPD(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0xAD, 0x28, 0xDD]), VMOVAPD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x48, 0x29, 0x50, 0xFF]), VMOVAPD(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFD, 0xCE, 0x28, 0xCA]), VMOVAPD(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0x28, 0x72, 0x04]), VMOVAPD(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xAD, 0x28, 0x59, 0x02]), VMOVAPD(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFD, 0xCE, 0x28, 0x48, 0x01]), VMOVAPD(zmm9(k6.z), zword[r8 + 64]).encode())
self.assertEqual(bytearray([0xC5, 0x79, 0x29, 0xF1]), VMOVAPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x28, 0x4C, 0xC2, 0xB3]), VMOVAPD(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x7D, 0x29, 0xFA]), VMOVAPD(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x28, 0x54, 0xD9, 0xBE]), VMOVAPD(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x79, 0x29, 0x74, 0xC2, 0xB3]), VMOVAPD(oword[r10 + rax*8 - 77], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7D, 0x29, 0x7C, 0xD9, 0xBE]), VMOVAPD(hword[r9 + rbx*8 - 66], ymm15).encode())
class TestVMOVUPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x11, 0x62, 0xC0]), VMOVUPD(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0x10, 0xF4]), VMOVUPD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x11, 0x69, 0xC0]), VMOVUPD(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0xAD, 0x10, 0xDD]), VMOVUPD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x48, 0x11, 0x50, 0xFF]), VMOVUPD(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFD, 0xCE, 0x10, 0xCA]), VMOVUPD(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0x10, 0x72, 0x04]), VMOVUPD(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xAD, 0x10, 0x59, 0x02]), VMOVUPD(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFD, 0xCE, 0x10, 0x48, 0x01]), VMOVUPD(zmm9(k6.z), zword[r8 + 64]).encode())
self.assertEqual(bytearray([0xC5, 0x79, 0x11, 0xF1]), VMOVUPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x10, 0x4C, 0xC2, 0xB3]), VMOVUPD(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x7D, 0x11, 0xFA]), VMOVUPD(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x10, 0x54, 0xD9, 0xBE]), VMOVUPD(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x79, 0x11, 0x74, 0xC2, 0xB3]), VMOVUPD(oword[r10 + rax*8 - 77], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7D, 0x11, 0x7C, 0xD9, 0xBE]), VMOVUPD(hword[r9 + rbx*8 - 66], ymm15).encode())
class TestVMOVLPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x41, 0x79, 0x13, 0x74, 0xD3, 0xA8]), VMOVLPD(qword[r11 + rdx*8 - 88], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x13, 0x63, 0xC0]), VMOVLPD(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x12, 0x4C, 0xD3, 0xA8]), VMOVLPD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xDD, 0x08, 0x12, 0x43, 0xF0]), VMOVLPD(xmm16, xmm4, qword[r11 - 128]).encode())
class TestVMOVHPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x41, 0x79, 0x17, 0x74, 0xD3, 0xA8]), VMOVHPD(qword[r11 + rdx*8 - 88], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x17, 0x63, 0xC0]), VMOVHPD(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x16, 0x4C, 0xD3, 0xA8]), VMOVHPD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xDD, 0x08, 0x16, 0x43, 0xF0]), VMOVHPD(xmm16, xmm4, qword[r11 - 128]).encode())
class TestVMASKMOVPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x2D, 0x4C, 0xC2, 0xB3]), VMASKMOVPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x2D, 0x54, 0xD9, 0xBE]), VMASKMOVPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x2F, 0x5C, 0xC2, 0xB3]), VMASKMOVPD(oword[r10 + rax*8 - 77], xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x2F, 0x64, 0xD9, 0xBE]), VMASKMOVPD(hword[r9 + rbx*8 - 66], ymm15, ymm4).encode())
class TestVMOVMSKPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x50, 0xEE]), VMOVMSKPD(ebp, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x50, 0xEF]), VMOVMSKPD(ebp, ymm15).encode())
class TestVMOVNTPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x41, 0x79, 0x2B, 0x74, 0xC2, 0xB3]), VMOVNTPD(oword[r10 + rax*8 - 77], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x2B, 0x62, 0xC0]), VMOVNTPD(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7D, 0x2B, 0x7C, 0xD9, 0xBE]), VMOVNTPD(hword[r9 + rbx*8 - 66], ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x2B, 0x69, 0xC0]), VMOVNTPD(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x48, 0x2B, 0x50, 0xFF]), VMOVNTPD(zword[r8 - 64], zmm26).encode())
class TestVBROADCASTSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0x19, 0xDC]), VBROADCASTSD(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0xFD, 0xCE, 0x19, 0xCC]), VBROADCASTSD(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x19, 0x5B, 0x08]), VBROADCASTSD(ymm19(k5.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x19, 0x4B, 0x08]), VBROADCASTSD(zmm9(k6.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x19, 0xD6]), VBROADCASTSD(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x19, 0x54, 0xD3, 0xA8]), VBROADCASTSD(ymm2, qword[r11 + rdx*8 - 88]).encode())
class TestVMOVDDUP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x61, 0xFF, 0x8A, 0x12, 0xF4]), VMOVDDUP(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFF, 0xAD, 0x12, 0xDD]), VMOVDDUP(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFF, 0xCE, 0x12, 0xCA]), VMOVDDUP(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFF, 0x8A, 0x12, 0x73, 0x08]), VMOVDDUP(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFF, 0xAD, 0x12, 0x59, 0x02]), VMOVDDUP(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFF, 0xCE, 0x12, 0x48, 0x01]), VMOVDDUP(zmm9(k6.z), zword[r8 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x12, 0xCE]), VMOVDDUP(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x12, 0x4C, 0xD3, 0xA8]), VMOVDDUP(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7F, 0x12, 0xD7]), VMOVDDUP(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7F, 0x12, 0x54, 0xD9, 0xBE]), VMOVDDUP(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVEXPANDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x8A, 0x88, 0xF4]), VEXPANDPD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0x88, 0xDD]), VEXPANDPD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0xCE, 0x88, 0xCA]), VEXPANDPD(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0x88, 0x72, 0x08]), VEXPANDPD(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x88, 0x59, 0x08]), VEXPANDPD(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x88, 0x48, 0x08]), VEXPANDPD(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVCOMPRESSPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0xFD, 0x8A, 0x8A, 0xE6]), VCOMPRESSPD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xFD, 0x08, 0x8A, 0x62, 0xF8]), VCOMPRESSPD(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xFD, 0xAD, 0x8A, 0xEB]), VCOMPRESSPD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xFD, 0x28, 0x8A, 0x69, 0xF8]), VCOMPRESSPD(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0xCE, 0x8A, 0xD1]), VCOMPRESSPD(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x48, 0x8A, 0x50, 0xF8]), VCOMPRESSPD(zword[r8 - 64], zmm26).encode())
class TestVGATHERDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x09, 0x92, 0x6C, 0x86, 0xF0]), VGATHERDPD(xmm5(k1), [rsi + xmm0 * 4 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x2B, 0x92, 0x44, 0x86, 0xF0]), VGATHERDPD(ymm24(k3), [rsi + xmm0 * 4 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x02, 0xFD, 0x4F, 0x92, 0x54, 0x83, 0x06]), VGATHERDPD(zmm26(k7), [r11 + ymm8 * 4 + 48]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0xE1, 0x92, 0x4C, 0x86, 0x80]), VGATHERDPD(xmm1, [rsi + xmm0 * 4 - 128], xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0xDD, 0x92, 0x54, 0x86, 0x80]), VGATHERDPD(ymm2, [rsi + xmm0 * 4 - 128], ymm4).encode())
class TestVGATHERQPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x09, 0x93, 0x6C, 0xCE, 0x05]), VGATHERQPD(xmm5(k1), [rsi + xmm1 * 8 + 40]).encode())
self.assertEqual(bytearray([0x62, 0x02, 0xFD, 0x2B, 0x93, 0x44, 0xCB, 0xF9]), VGATHERQPD(ymm24(k3), [r11 + ymm9 * 8 - 56]).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x47, 0x93, 0x54, 0xE7, 0x09]), VGATHERQPD(zmm26(k7), [r15 + zmm20 * 8 + 72]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0xE1, 0x93, 0x4C, 0xCE, 0x28]), VGATHERQPD(xmm1, [rsi + xmm1 * 8 + 40], xmm3).encode())
self.assertEqual(bytearray([0xC4, 0x82, 0xDD, 0x93, 0x54, 0xCB, 0xC8]), VGATHERQPD(ymm2, [r11 + ymm9 * 8 - 56], ymm4).encode())
class TestVGATHERPF0DPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0xFD, 0x4A, 0xC6, 0x4C, 0x83, 0x06]), VGATHERPF0DPD([r11 + ymm8(k2) * 4 + 48]).encode())
class TestVGATHERPF0QPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0xFD, 0x46, 0xC7, 0x4C, 0xE7, 0x09]), VGATHERPF0QPD([r15 + zmm20(k6) * 8 + 72]).encode())
class TestVGATHERPF1DPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0xFD, 0x4A, 0xC6, 0x54, 0x83, 0x06]), VGATHERPF1DPD([r11 + ymm8(k2) * 4 + 48]).encode())
class TestVGATHERPF1QPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0xFD, 0x46, 0xC7, 0x54, 0xE7, 0x09]), VGATHERPF1QPD([r15 + zmm20(k6) * 8 + 72]).encode())
class TestVSCATTERDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x09, 0xA2, 0x64, 0x86, 0xF0]), VSCATTERDPD([rsi + xmm0(k1) * 4 - 128], xmm4).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x29, 0xA2, 0x6C, 0x86, 0xF0]), VSCATTERDPD([rsi + xmm0(k1) * 4 - 128], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0xFD, 0x4A, 0xA2, 0x54, 0x83, 0x06]), VSCATTERDPD([r11 + ymm8(k2) * 4 + 48], zmm26).encode())
class TestVSCATTERQPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x0C, 0xA3, 0x64, 0xCE, 0x05]), VSCATTERQPD([rsi + xmm1(k4) * 8 + 40], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0xFD, 0x2D, 0xA3, 0x6C, 0xCB, 0xF9]), VSCATTERQPD([r11 + ymm9(k5) * 8 - 56], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x46, 0xA3, 0x54, 0xE7, 0x09]), VSCATTERQPD([r15 + zmm20(k6) * 8 + 72], zmm26).encode())
class TestVSCATTERPF0DPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0xFD, 0x4A, 0xC6, 0x6C, 0x83, 0x06]), VSCATTERPF0DPD([r11 + ymm8(k2) * 4 + 48]).encode())
class TestVSCATTERPF0QPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0xFD, 0x46, 0xC7, 0x6C, 0xE7, 0x09]), VSCATTERPF0QPD([r15 + zmm20(k6) * 8 + 72]).encode())
class TestVSCATTERPF1DPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0xFD, 0x4A, 0xC6, 0x74, 0x83, 0x06]), VSCATTERPF1DPD([r11 + ymm8(k2) * 4 + 48]).encode())
class TestVSCATTERPF1QPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0xFD, 0x46, 0xC7, 0x74, 0xE7, 0x09]), VSCATTERPF1QPD([r15 + zmm20(k6) * 8 + 72]).encode())
class TestVADDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x58, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VADDPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x58, 0xF3]), VADDPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x58, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VADDPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x58, 0xDC]), VADDPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x58, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VADDPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x58, 0xCB]), VADDPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x58, 0x4C, 0xC2, 0xB3]), VADDPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x58, 0xD4]), VADDPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x58, 0x54, 0xD9, 0xBE]), VADDPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0x96, 0x58, 0xC9]), VADDPS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVHADDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x8B, 0x7C, 0xCB]), VHADDPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x7C, 0x4C, 0xC2, 0xB3]), VHADDPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x87, 0x7C, 0xD4]), VHADDPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x07, 0x7C, 0x54, 0xD9, 0xBE]), VHADDPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVSUBPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x5C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VSUBPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x5C, 0xF3]), VSUBPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x5C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSUBPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x5C, 0xDC]), VSUBPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x5C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSUBPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x5C, 0xCB]), VSUBPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x5C, 0x4C, 0xC2, 0xB3]), VSUBPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x5C, 0xD4]), VSUBPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x5C, 0x54, 0xD9, 0xBE]), VSUBPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0x96, 0x5C, 0xC9]), VSUBPS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVHSUBPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x8B, 0x7D, 0xCB]), VHSUBPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x7D, 0x4C, 0xC2, 0xB3]), VHSUBPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x87, 0x7D, 0xD4]), VHSUBPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x07, 0x7D, 0x54, 0xD9, 0xBE]), VHSUBPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVADDSUBPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x8B, 0xD0, 0xCB]), VADDSUBPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0xD0, 0x4C, 0xC2, 0xB3]), VADDSUBPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x87, 0xD0, 0xD4]), VADDSUBPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x07, 0xD0, 0x54, 0xD9, 0xBE]), VADDSUBPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVMULPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x59, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VMULPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x59, 0xF3]), VMULPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x59, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMULPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x59, 0xDC]), VMULPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x59, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMULPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x59, 0xCB]), VMULPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x59, 0x4C, 0xC2, 0xB3]), VMULPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x59, 0xD4]), VMULPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x59, 0x54, 0xD9, 0xBE]), VMULPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0x96, 0x59, 0xC9]), VMULPS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVDIVPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x5E, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VDIVPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x5E, 0xF3]), VDIVPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x5E, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VDIVPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x5E, 0xDC]), VDIVPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x5E, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VDIVPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x5E, 0xCB]), VDIVPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x5E, 0x4C, 0xC2, 0xB3]), VDIVPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x5E, 0xD4]), VDIVPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x5E, 0x54, 0xD9, 0xBE]), VDIVPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0x96, 0x5E, 0xC9]), VDIVPS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVSQRTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x8A, 0x51, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VSQRTPS(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7C, 0xAD, 0x51, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSQRTPS(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7C, 0xCE, 0x51, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSQRTPS(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7C, 0x8A, 0x51, 0xF4]), VSQRTPS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7C, 0xAD, 0x51, 0xDD]), VSQRTPS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x51, 0xCE]), VSQRTPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x51, 0x4C, 0xC2, 0xB3]), VSQRTPS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x51, 0xD7]), VSQRTPS(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x51, 0x54, 0xD9, 0xBE]), VSQRTPS(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7C, 0x9E, 0x51, 0xCA]), VSQRTPS(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVADDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x58, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VADDPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x58, 0xF3]), VADDPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x58, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VADDPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x58, 0xDC]), VADDPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x58, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VADDPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x58, 0xCB]), VADDPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x58, 0x4C, 0xC2, 0xB3]), VADDPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x58, 0xD4]), VADDPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x58, 0x54, 0xD9, 0xBE]), VADDPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0x96, 0x58, 0xC9]), VADDPD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVHADDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x89, 0x7C, 0xCB]), VHADDPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x7C, 0x4C, 0xC2, 0xB3]), VHADDPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x7C, 0xD4]), VHADDPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x7C, 0x54, 0xD9, 0xBE]), VHADDPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVSUBPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x5C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VSUBPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x5C, 0xF3]), VSUBPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x5C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSUBPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x5C, 0xDC]), VSUBPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x5C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSUBPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x5C, 0xCB]), VSUBPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x5C, 0x4C, 0xC2, 0xB3]), VSUBPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x5C, 0xD4]), VSUBPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x5C, 0x54, 0xD9, 0xBE]), VSUBPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0x96, 0x5C, 0xC9]), VSUBPD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVHSUBPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x89, 0x7D, 0xCB]), VHSUBPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x7D, 0x4C, 0xC2, 0xB3]), VHSUBPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x7D, 0xD4]), VHSUBPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x7D, 0x54, 0xD9, 0xBE]), VHSUBPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVADDSUBPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x89, 0xD0, 0xCB]), VADDSUBPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xD0, 0x4C, 0xC2, 0xB3]), VADDSUBPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xD0, 0xD4]), VADDSUBPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xD0, 0x54, 0xD9, 0xBE]), VADDSUBPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVMULPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x59, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VMULPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x59, 0xF3]), VMULPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x59, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMULPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x59, 0xDC]), VMULPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x59, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMULPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x59, 0xCB]), VMULPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x59, 0x4C, 0xC2, 0xB3]), VMULPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x59, 0xD4]), VMULPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x59, 0x54, 0xD9, 0xBE]), VMULPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0x96, 0x59, 0xC9]), VMULPD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVDIVPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x5E, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VDIVPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x5E, 0xF3]), VDIVPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x5E, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VDIVPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x5E, 0xDC]), VDIVPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x5E, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VDIVPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x5E, 0xCB]), VDIVPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x5E, 0x4C, 0xC2, 0xB3]), VDIVPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x5E, 0xD4]), VDIVPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x5E, 0x54, 0xD9, 0xBE]), VDIVPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0x96, 0x5E, 0xC9]), VDIVPD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVSQRTPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0x51, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VSQRTPD(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xAD, 0x51, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSQRTPD(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFD, 0xCE, 0x51, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSQRTPD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0x51, 0xF4]), VSQRTPD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0xAD, 0x51, 0xDD]), VSQRTPD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x51, 0xCE]), VSQRTPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x51, 0x4C, 0xC2, 0xB3]), VSQRTPD(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x51, 0xD7]), VSQRTPD(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x51, 0x54, 0xD9, 0xBE]), VSQRTPD(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFD, 0x9E, 0x51, 0xCA]), VSQRTPD(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVROUNDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x08, 0xCE, 0x02]), VROUNDPS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x08, 0x4C, 0xC2, 0xB3, 0x02]), VROUNDPS(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7D, 0x08, 0xD7, 0x02]), VROUNDPS(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7D, 0x08, 0x54, 0xD9, 0xBE, 0x02]), VROUNDPS(ymm2, hword[r9 + rbx*8 - 66], 2).encode())
class TestVRNDSCALEPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x7D, 0x8A, 0x08, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VRNDSCALEPS(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x7D, 0xAD, 0x08, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VRNDSCALEPS(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x7D, 0xCE, 0x08, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VRNDSCALEPS(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x63, 0x7D, 0x8A, 0x08, 0xF4, 0x02]), VRNDSCALEPS(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0x7D, 0xAD, 0x08, 0xDD, 0x02]), VRNDSCALEPS(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x13, 0x7D, 0x9E, 0x08, 0xCA, 0x02]), VRNDSCALEPS(zmm9(k6.z), zmm26, {sae}, 2).encode())
class TestVRANGEPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x50, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VRANGEPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x8A, 0x50, 0xF3, 0x02]), VRANGEPS(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x50, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VRANGEPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x50, 0xDC, 0x02]), VRANGEPS(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x50, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VRANGEPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0x96, 0x50, 0xC9, 0x02]), VRANGEPS(zmm9(k6.z), zmm26, zmm9, {sae}, 2).encode())
class TestVMINPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x5D, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VMINPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x5D, 0xF3]), VMINPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x5D, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMINPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x5D, 0xDC]), VMINPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x5D, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMINPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x5D, 0xCB]), VMINPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x5D, 0x4C, 0xC2, 0xB3]), VMINPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x5D, 0xD4]), VMINPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x5D, 0x54, 0xD9, 0xBE]), VMINPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0x96, 0x5D, 0xC9]), VMINPS(zmm9(k6.z), zmm26, zmm9, {sae}).encode())
class TestVMAXPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x5F, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VMAXPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x5F, 0xF3]), VMAXPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x5F, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMAXPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x5F, 0xDC]), VMAXPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x5F, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMAXPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x5F, 0xCB]), VMAXPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x5F, 0x4C, 0xC2, 0xB3]), VMAXPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x5F, 0xD4]), VMAXPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x5F, 0x54, 0xD9, 0xBE]), VMAXPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0x96, 0x5F, 0xC9]), VMAXPS(zmm9(k6.z), zmm26, zmm9, {sae}).encode())
class TestVREDUCEPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x7D, 0x8A, 0x56, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VREDUCEPS(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x7D, 0xAD, 0x56, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VREDUCEPS(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x7D, 0xCE, 0x56, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VREDUCEPS(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x63, 0x7D, 0x8A, 0x56, 0xF4, 0x02]), VREDUCEPS(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0x7D, 0xAD, 0x56, 0xDD, 0x02]), VREDUCEPS(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x13, 0x7D, 0xCE, 0x56, 0xCA, 0x02]), VREDUCEPS(zmm9(k6.z), zmm26, 2).encode())
class TestVDPPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x40, 0xCB, 0x02]), VDPPS(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x40, 0x4C, 0xC2, 0xB3, 0x02]), VDPPS(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x40, 0xD4, 0x02]), VDPPS(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x40, 0x54, 0xD9, 0xBE, 0x02]), VDPPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVGETMANTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x7D, 0x8A, 0x26, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VGETMANTPS(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x7D, 0xAD, 0x26, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VGETMANTPS(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x7D, 0xCE, 0x26, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VGETMANTPS(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x63, 0x7D, 0x8A, 0x26, 0xF4, 0x02]), VGETMANTPS(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0x7D, 0xAD, 0x26, 0xDD, 0x02]), VGETMANTPS(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x13, 0x7D, 0x9E, 0x26, 0xCA, 0x02]), VGETMANTPS(zmm9(k6.z), zmm26, {sae}, 2).encode())
class TestVGETEXPPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x42, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VGETEXPPS(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x42, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VGETEXPPS(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x42, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VGETEXPPS(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x42, 0xF4]), VGETEXPPS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x42, 0xDD]), VGETEXPPS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0x9E, 0x42, 0xCA]), VGETEXPPS(zmm9(k6.z), zmm26, {sae}).encode())
class TestVSCALEFPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x2C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VSCALEFPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x2C, 0xF3]), VSCALEFPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x2C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSCALEFPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x2C, 0xDC]), VSCALEFPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x2C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSCALEFPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0x2C, 0xC9]), VSCALEFPS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFIXUPIMMPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x54, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VFIXUPIMMPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x8A, 0x54, 0xF3, 0x02]), VFIXUPIMMPS(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x54, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VFIXUPIMMPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x54, 0xDC, 0x02]), VFIXUPIMMPS(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x54, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VFIXUPIMMPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0x96, 0x54, 0xC9, 0x02]), VFIXUPIMMPS(zmm9(k6.z), zmm26, zmm9, {sae}, 2).encode())
class TestVFPCLASSPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD3, 0x7D, 0x0E, 0x66, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VFPCLASSPS(k4(k6), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x7D, 0x2E, 0x66, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VFPCLASSPS(k4(k6), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x7D, 0x4E, 0x66, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VFPCLASSPS(k4(k6), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF3, 0x7D, 0x0E, 0x66, 0xE4, 0x02]), VFPCLASSPS(k4(k6), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xF3, 0x7D, 0x2E, 0x66, 0xE5, 0x02]), VFPCLASSPS(k4(k6), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x93, 0x7D, 0x4E, 0x66, 0xE2, 0x02]), VFPCLASSPS(k4(k6), zmm26, 2).encode())
class TestVRCPPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x53, 0xCE]), VRCPPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x53, 0x4C, 0xC2, 0xB3]), VRCPPS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x53, 0xD7]), VRCPPS(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x53, 0x54, 0xD9, 0xBE]), VRCPPS(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVRSQRTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x52, 0xCE]), VRSQRTPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x52, 0x4C, 0xC2, 0xB3]), VRSQRTPS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x52, 0xD7]), VRSQRTPS(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x52, 0x54, 0xD9, 0xBE]), VRSQRTPS(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVRCP14PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x4C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VRCP14PS(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x4C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRCP14PS(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x4C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRCP14PS(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x4C, 0xF4]), VRCP14PS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x4C, 0xDD]), VRCP14PS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0x4C, 0xCA]), VRCP14PS(zmm9(k6.z), zmm26).encode())
class TestVRSQRT14PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x4E, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VRSQRT14PS(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x4E, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRSQRT14PS(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x4E, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRSQRT14PS(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x4E, 0xF4]), VRSQRT14PS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x4E, 0xDD]), VRSQRT14PS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0x4E, 0xCA]), VRSQRT14PS(zmm9(k6.z), zmm26).encode())
class TestVRCP28PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0xCA, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRCP28PS(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0x9E, 0xCA, 0xCA]), VRCP28PS(zmm9(k6.z), zmm26, {sae}).encode())
class TestVRSQRT28PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0xCC, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRSQRT28PS(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0x9E, 0xCC, 0xCA]), VRSQRT28PS(zmm9(k6.z), zmm26, {sae}).encode())
class TestVEXP2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0xC8, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VEXP2PS(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0x9E, 0xC8, 0xCA]), VEXP2PS(zmm9(k6.z), zmm26, {sae}).encode())
class TestVCMPPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x5C, 0x0E, 0xC2, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VCMPPS(k4(k6), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x5C, 0x0E, 0xC2, 0xE3, 0x02]), VCMPPS(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x54, 0x2E, 0xC2, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VCMPPS(k4(k6), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x54, 0x2E, 0xC2, 0xE4, 0x02]), VCMPPS(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2C, 0x46, 0xC2, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VCMPPS(k4(k6), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0xC2, 0xCB, 0x02]), VCMPPS(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0xC2, 0x4C, 0xC2, 0xB3, 0x02]), VCMPPS(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0xC2, 0xD4, 0x02]), VCMPPS(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0xC2, 0x54, 0xD9, 0xBE, 0x02]), VCMPPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2C, 0x16, 0xC2, 0xE1, 0x02]), VCMPPS(k4(k6), zmm26, zmm9, {sae}, 2).encode())
class TestVTESTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x0E, 0xCE]), VTESTPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x0E, 0x4C, 0xC2, 0xB3]), VTESTPS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x0E, 0xD7]), VTESTPS(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x0E, 0x54, 0xD9, 0xBE]), VTESTPS(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVROUNDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x09, 0xCE, 0x02]), VROUNDPD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x09, 0x4C, 0xC2, 0xB3, 0x02]), VROUNDPD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7D, 0x09, 0xD7, 0x02]), VROUNDPD(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7D, 0x09, 0x54, 0xD9, 0xBE, 0x02]), VROUNDPD(ymm2, hword[r9 + rbx*8 - 66], 2).encode())
class TestVRNDSCALEPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xFD, 0x8A, 0x09, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VRNDSCALEPD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xFD, 0xAD, 0x09, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VRNDSCALEPD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xFD, 0xCE, 0x09, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VRNDSCALEPD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x63, 0xFD, 0x8A, 0x09, 0xF4, 0x02]), VRNDSCALEPD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0xFD, 0xAD, 0x09, 0xDD, 0x02]), VRNDSCALEPD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x13, 0xFD, 0x9E, 0x09, 0xCA, 0x02]), VRNDSCALEPD(zmm9(k6.z), zmm26, {sae}, 2).encode())
class TestVRANGEPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xDD, 0x8A, 0x50, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VRANGEPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0xDD, 0x8A, 0x50, 0xF3, 0x02]), VRANGEPD(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xD5, 0xAD, 0x50, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VRANGEPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0xD5, 0xAD, 0x50, 0xDC, 0x02]), VRANGEPD(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x50, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VRANGEPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0x96, 0x50, 0xC9, 0x02]), VRANGEPD(zmm9(k6.z), zmm26, zmm9, {sae}, 2).encode())
class TestVMINPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x5D, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VMINPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x5D, 0xF3]), VMINPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x5D, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMINPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x5D, 0xDC]), VMINPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x5D, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMINPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x5D, 0xCB]), VMINPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x5D, 0x4C, 0xC2, 0xB3]), VMINPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x5D, 0xD4]), VMINPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x5D, 0x54, 0xD9, 0xBE]), VMINPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0x96, 0x5D, 0xC9]), VMINPD(zmm9(k6.z), zmm26, zmm9, {sae}).encode())
class TestVMAXPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x5F, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VMAXPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x5F, 0xF3]), VMAXPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x5F, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMAXPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x5F, 0xDC]), VMAXPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x5F, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VMAXPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x5F, 0xCB]), VMAXPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x5F, 0x4C, 0xC2, 0xB3]), VMAXPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x5F, 0xD4]), VMAXPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x5F, 0x54, 0xD9, 0xBE]), VMAXPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0x96, 0x5F, 0xC9]), VMAXPD(zmm9(k6.z), zmm26, zmm9, {sae}).encode())
class TestVREDUCEPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xFD, 0x8A, 0x56, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VREDUCEPD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xFD, 0xAD, 0x56, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VREDUCEPD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xFD, 0xCE, 0x56, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VREDUCEPD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x63, 0xFD, 0x8A, 0x56, 0xF4, 0x02]), VREDUCEPD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0xFD, 0xAD, 0x56, 0xDD, 0x02]), VREDUCEPD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x13, 0xFD, 0xCE, 0x56, 0xCA, 0x02]), VREDUCEPD(zmm9(k6.z), zmm26, 2).encode())
class TestVDPPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x41, 0xCB, 0x02]), VDPPD(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x41, 0x4C, 0xC2, 0xB3, 0x02]), VDPPD(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestVGETMANTPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xFD, 0x8A, 0x26, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VGETMANTPD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xFD, 0xAD, 0x26, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VGETMANTPD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xFD, 0xCE, 0x26, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VGETMANTPD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x63, 0xFD, 0x8A, 0x26, 0xF4, 0x02]), VGETMANTPD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0xFD, 0xAD, 0x26, 0xDD, 0x02]), VGETMANTPD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x13, 0xFD, 0x9E, 0x26, 0xCA, 0x02]), VGETMANTPD(zmm9(k6.z), zmm26, {sae}, 2).encode())
class TestVGETEXPPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0x42, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VGETEXPPD(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x42, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VGETEXPPD(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x42, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VGETEXPPD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x8A, 0x42, 0xF4]), VGETEXPPD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0x42, 0xDD]), VGETEXPPD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0x9E, 0x42, 0xCA]), VGETEXPPD(zmm9(k6.z), zmm26, {sae}).encode())
class TestVSCALEFPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x2C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VSCALEFPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x2C, 0xF3]), VSCALEFPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x2C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSCALEFPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x2C, 0xDC]), VSCALEFPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x2C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VSCALEFPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0x2C, 0xC9]), VSCALEFPD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFIXUPIMMPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xDD, 0x8A, 0x54, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VFIXUPIMMPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0xDD, 0x8A, 0x54, 0xF3, 0x02]), VFIXUPIMMPD(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xD5, 0xAD, 0x54, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VFIXUPIMMPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0xD5, 0xAD, 0x54, 0xDC, 0x02]), VFIXUPIMMPD(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x54, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VFIXUPIMMPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0x96, 0x54, 0xC9, 0x02]), VFIXUPIMMPD(zmm9(k6.z), zmm26, zmm9, {sae}, 2).encode())
class TestVFPCLASSPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD3, 0xFD, 0x0E, 0x66, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VFPCLASSPD(k4(k6), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xFD, 0x2E, 0x66, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VFPCLASSPD(k4(k6), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xFD, 0x4E, 0x66, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VFPCLASSPD(k4(k6), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF3, 0xFD, 0x0E, 0x66, 0xE4, 0x02]), VFPCLASSPD(k4(k6), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xF3, 0xFD, 0x2E, 0x66, 0xE5, 0x02]), VFPCLASSPD(k4(k6), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x93, 0xFD, 0x4E, 0x66, 0xE2, 0x02]), VFPCLASSPD(k4(k6), zmm26, 2).encode())
class TestVRCP14PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0x4C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VRCP14PD(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x4C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRCP14PD(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x4C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRCP14PD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x8A, 0x4C, 0xF4]), VRCP14PD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0x4C, 0xDD]), VRCP14PD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0xCE, 0x4C, 0xCA]), VRCP14PD(zmm9(k6.z), zmm26).encode())
class TestVRSQRT14PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0x4E, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VRSQRT14PD(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x4E, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRSQRT14PD(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x4E, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRSQRT14PD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x8A, 0x4E, 0xF4]), VRSQRT14PD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0x4E, 0xDD]), VRSQRT14PD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0xCE, 0x4E, 0xCA]), VRSQRT14PD(zmm9(k6.z), zmm26).encode())
class TestVRCP28PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0xCA, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRCP28PD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0x9E, 0xCA, 0xCA]), VRCP28PD(zmm9(k6.z), zmm26, {sae}).encode())
class TestVRSQRT28PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0xCC, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VRSQRT28PD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0x9E, 0xCC, 0xCA]), VRSQRT28PD(zmm9(k6.z), zmm26, {sae}).encode())
class TestVEXP2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0xC8, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VEXP2PD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0x9E, 0xC8, 0xCA]), VEXP2PD(zmm9(k6.z), zmm26, {sae}).encode())
class TestVCMPPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0xDD, 0x0E, 0xC2, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VCMPPD(k4(k6), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0xDD, 0x0E, 0xC2, 0xE3, 0x02]), VCMPPD(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xD5, 0x2E, 0xC2, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VCMPPD(k4(k6), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0xD5, 0x2E, 0xC2, 0xE4, 0x02]), VCMPPD(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xAD, 0x46, 0xC2, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VCMPPD(k4(k6), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xC2, 0xCB, 0x02]), VCMPPD(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xC2, 0x4C, 0xC2, 0xB3, 0x02]), VCMPPD(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xC2, 0xD4, 0x02]), VCMPPD(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xC2, 0x54, 0xD9, 0xBE, 0x02]), VCMPPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xAD, 0x16, 0xC2, 0xE1, 0x02]), VCMPPD(k4(k6), zmm26, zmm9, {sae}, 2).encode())
class TestVTESTPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x0F, 0xCE]), VTESTPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x0F, 0x4C, 0xC2, 0xB3]), VTESTPD(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x0F, 0xD7]), VTESTPD(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x0F, 0x54, 0xD9, 0xBE]), VTESTPD(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVANDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x54, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VANDPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x54, 0xF3]), VANDPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x54, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VANDPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x54, 0xDC]), VANDPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x54, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VANDPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x54, 0xC9]), VANDPS(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x54, 0xCB]), VANDPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x54, 0x4C, 0xC2, 0xB3]), VANDPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x54, 0xD4]), VANDPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x54, 0x54, 0xD9, 0xBE]), VANDPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVANDNPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x88, 0x55, 0xCB]), VANDNPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x55, 0x4C, 0xC2, 0xB3]), VANDNPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x55, 0xD4]), VANDNPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x55, 0x54, 0xD9, 0xBE]), VANDNPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVORPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x56, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VORPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x56, 0xF3]), VORPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x56, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VORPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x56, 0xDC]), VORPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x56, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VORPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x56, 0xC9]), VORPS(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x56, 0xCB]), VORPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x56, 0x4C, 0xC2, 0xB3]), VORPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x56, 0xD4]), VORPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x56, 0x54, 0xD9, 0xBE]), VORPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVXORPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x57, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VXORPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x57, 0xF3]), VXORPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x57, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VXORPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x57, 0xDC]), VXORPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x57, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VXORPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x57, 0xC9]), VXORPS(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x57, 0xCB]), VXORPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x57, 0x4C, 0xC2, 0xB3]), VXORPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x57, 0xD4]), VXORPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x57, 0x54, 0xD9, 0xBE]), VXORPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVBLENDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x0C, 0xCB, 0x02]), VBLENDPS(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x0C, 0x4C, 0xC2, 0xB3, 0x02]), VBLENDPS(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x0C, 0xD4, 0x02]), VBLENDPS(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x0C, 0x54, 0xD9, 0xBE, 0x02]), VBLENDPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVBLENDVPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x4A, 0xCB, 0x90]), VBLENDVPS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x4A, 0x4C, 0xC2, 0xB3, 0x90]), VBLENDVPS(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x4A, 0xD4, 0xA0]), VBLENDVPS(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x4A, 0x54, 0xD9, 0xBE, 0xA0]), VBLENDVPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVBLENDMPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x65, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VBLENDMPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x65, 0xF3]), VBLENDMPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x65, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VBLENDMPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x65, 0xDC]), VBLENDMPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x65, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VBLENDMPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x65, 0xC9]), VBLENDMPS(zmm9(k6.z), zmm26, zmm9).encode())
class TestVANDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x54, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VANDPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x54, 0xF3]), VANDPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x54, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VANDPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x54, 0xDC]), VANDPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x54, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VANDPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x54, 0xC9]), VANDPD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x54, 0xCB]), VANDPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x54, 0x4C, 0xC2, 0xB3]), VANDPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x54, 0xD4]), VANDPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x54, 0x54, 0xD9, 0xBE]), VANDPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVANDNPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x55, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VANDNPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x55, 0xF3]), VANDNPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x55, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VANDNPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x55, 0xDC]), VANDNPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x55, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VANDNPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x55, 0xC9]), VANDNPD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x55, 0xCB]), VANDNPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x55, 0x4C, 0xC2, 0xB3]), VANDNPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x55, 0xD4]), VANDNPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x55, 0x54, 0xD9, 0xBE]), VANDNPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVORPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x56, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VORPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x56, 0xF3]), VORPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x56, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VORPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x56, 0xDC]), VORPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x56, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VORPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x56, 0xC9]), VORPD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x56, 0xCB]), VORPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x56, 0x4C, 0xC2, 0xB3]), VORPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x56, 0xD4]), VORPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x56, 0x54, 0xD9, 0xBE]), VORPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVXORPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x57, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VXORPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x57, 0xF3]), VXORPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x57, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VXORPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x57, 0xDC]), VXORPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x57, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VXORPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x57, 0xC9]), VXORPD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x57, 0xCB]), VXORPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x57, 0x4C, 0xC2, 0xB3]), VXORPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x57, 0xD4]), VXORPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x57, 0x54, 0xD9, 0xBE]), VXORPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVBLENDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x0D, 0xCB, 0x02]), VBLENDPD(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x0D, 0x4C, 0xC2, 0xB3, 0x02]), VBLENDPD(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x0D, 0xD4, 0x02]), VBLENDPD(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x0D, 0x54, 0xD9, 0xBE, 0x02]), VBLENDPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVBLENDVPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x4B, 0xCB, 0x90]), VBLENDVPD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x4B, 0x4C, 0xC2, 0xB3, 0x90]), VBLENDVPD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x4B, 0xD4, 0xA0]), VBLENDVPD(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x4B, 0x54, 0xD9, 0xBE, 0xA0]), VBLENDVPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVBLENDMPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x65, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VBLENDMPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x65, 0xF3]), VBLENDMPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x65, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VBLENDMPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x65, 0xDC]), VBLENDMPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x65, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VBLENDMPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x65, 0xC9]), VBLENDMPD(zmm9(k6.z), zmm26, zmm9).encode())
class TestVUNPCKLPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x14, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VUNPCKLPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x14, 0xF3]), VUNPCKLPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x14, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VUNPCKLPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x14, 0xDC]), VUNPCKLPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x14, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VUNPCKLPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x14, 0xC9]), VUNPCKLPS(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x14, 0xCB]), VUNPCKLPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x14, 0x4C, 0xC2, 0xB3]), VUNPCKLPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x14, 0xD4]), VUNPCKLPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x14, 0x54, 0xD9, 0xBE]), VUNPCKLPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVUNPCKHPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0x15, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VUNPCKHPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0x15, 0xF3]), VUNPCKHPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0x15, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VUNPCKHPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0x15, 0xDC]), VUNPCKHPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x15, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VUNPCKHPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0x15, 0xC9]), VUNPCKHPS(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0x15, 0xCB]), VUNPCKHPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0x15, 0x4C, 0xC2, 0xB3]), VUNPCKHPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0x15, 0xD4]), VUNPCKHPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0x15, 0x54, 0xD9, 0xBE]), VUNPCKHPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVMOVLHPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x88, 0x16, 0xCB]), VMOVLHPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x5C, 0x08, 0x16, 0xC3]), VMOVLHPS(xmm16, xmm4, xmm19).encode())
class TestVMOVHLPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x88, 0x12, 0xCB]), VMOVHLPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x5C, 0x08, 0x12, 0xC3]), VMOVHLPS(xmm16, xmm4, xmm19).encode())
class TestVSHUFPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5C, 0x8A, 0xC6, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5C, 0x8A, 0xC6, 0xF3, 0x02]), VSHUFPS(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x54, 0xAD, 0xC6, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x54, 0xAD, 0xC6, 0xDC, 0x02]), VSHUFPS(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0xC6, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2C, 0xC6, 0xC6, 0xC9, 0x02]), VSHUFPS(zmm9(k6.z), zmm26, zmm9, 2).encode())
self.assertEqual(bytearray([0xC5, 0x88, 0xC6, 0xCB, 0x02]), VSHUFPS(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x08, 0xC6, 0x4C, 0xC2, 0xB3, 0x02]), VSHUFPS(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC5, 0x84, 0xC6, 0xD4, 0x02]), VSHUFPS(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x04, 0xC6, 0x54, 0xD9, 0xBE, 0x02]), VSHUFPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVUNPCKLPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x14, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VUNPCKLPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x14, 0xF3]), VUNPCKLPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x14, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VUNPCKLPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x14, 0xDC]), VUNPCKLPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x14, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VUNPCKLPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x14, 0xC9]), VUNPCKLPD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x14, 0xCB]), VUNPCKLPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x14, 0x4C, 0xC2, 0xB3]), VUNPCKLPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x14, 0xD4]), VUNPCKLPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x14, 0x54, 0xD9, 0xBE]), VUNPCKLPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVUNPCKHPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x15, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VUNPCKHPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x15, 0xF3]), VUNPCKHPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x15, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VUNPCKHPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x15, 0xDC]), VUNPCKHPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x15, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VUNPCKHPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x15, 0xC9]), VUNPCKHPD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x15, 0xCB]), VUNPCKHPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x15, 0x4C, 0xC2, 0xB3]), VUNPCKHPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x15, 0xD4]), VUNPCKHPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x15, 0x54, 0xD9, 0xBE]), VUNPCKHPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVSHUFPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xC6, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xC6, 0xF3, 0x02]), VSHUFPD(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xC6, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xC6, 0xDC, 0x02]), VSHUFPD(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xC6, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xC6, 0xC9, 0x02]), VSHUFPD(zmm9(k6.z), zmm26, zmm9, 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xC6, 0xCB, 0x02]), VSHUFPD(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xC6, 0x4C, 0xC2, 0xB3, 0x02]), VSHUFPD(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xC6, 0xD4, 0x02]), VSHUFPD(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xC6, 0x54, 0xD9, 0xBE, 0x02]), VSHUFPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPERMPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x16, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x16, 0xDC]), VPERMPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x16, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x16, 0xC9]), VPERMPS(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x16, 0xD4]), VPERMPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x16, 0x54, 0xD9, 0xBE]), VPERMPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPERMILPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x7D, 0x8A, 0x04, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPERMILPS(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x7D, 0xAD, 0x04, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPERMILPS(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x7D, 0xCE, 0x04, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPERMILPS(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x0C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMILPS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x63, 0x7D, 0x8A, 0x04, 0xF4, 0x02]), VPERMILPS(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x0C, 0xF3]), VPERMILPS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x0C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMILPS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0x7D, 0xAD, 0x04, 0xDD, 0x02]), VPERMILPS(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x0C, 0xDC]), VPERMILPS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x0C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMILPS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x13, 0x7D, 0xCE, 0x04, 0xCA, 0x02]), VPERMILPS(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x0C, 0xC9]), VPERMILPS(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x04, 0xCE, 0x02]), VPERMILPS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x0C, 0xCB]), VPERMILPS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x0C, 0x4C, 0xC2, 0xB3]), VPERMILPS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x04, 0x4C, 0xC2, 0xB3, 0x02]), VPERMILPS(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7D, 0x04, 0xD7, 0x02]), VPERMILPS(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x0C, 0xD4]), VPERMILPS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x0C, 0x54, 0xD9, 0xBE]), VPERMILPS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7D, 0x04, 0x54, 0xD9, 0xBE, 0x02]), VPERMILPS(ymm2, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPERMT2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x7F, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMT2PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x7F, 0xF3]), VPERMT2PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x7F, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMT2PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x7F, 0xDC]), VPERMT2PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x7F, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMT2PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x7F, 0xC9]), VPERMT2PS(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPERMI2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x77, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMI2PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x77, 0xF3]), VPERMI2PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x77, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMI2PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x77, 0xDC]), VPERMI2PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x77, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMI2PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x77, 0xC9]), VPERMI2PS(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPERMPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC3, 0xFD, 0xAD, 0x01, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPERMPD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xFD, 0xCE, 0x01, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPERMPD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x16, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0xFD, 0xAD, 0x01, 0xDD, 0x02]), VPERMPD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x16, 0xDC]), VPERMPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x16, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x13, 0xFD, 0xCE, 0x01, 0xCA, 0x02]), VPERMPD(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x16, 0xC9]), VPERMPD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0xFD, 0x01, 0xD7, 0x02]), VPERMPD(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0xFD, 0x01, 0x54, 0xD9, 0xBE, 0x02]), VPERMPD(ymm2, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPERMILPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xFD, 0x8A, 0x05, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPERMILPD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xFD, 0xAD, 0x05, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPERMILPD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xFD, 0xCE, 0x05, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPERMILPD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x0D, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMILPD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x63, 0xFD, 0x8A, 0x05, 0xF4, 0x02]), VPERMILPD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x0D, 0xF3]), VPERMILPD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x0D, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMILPD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0xFD, 0xAD, 0x05, 0xDD, 0x02]), VPERMILPD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x0D, 0xDC]), VPERMILPD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x0D, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMILPD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x13, 0xFD, 0xCE, 0x05, 0xCA, 0x02]), VPERMILPD(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x0D, 0xC9]), VPERMILPD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x05, 0xCE, 0x02]), VPERMILPD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x0D, 0xCB]), VPERMILPD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x0D, 0x4C, 0xC2, 0xB3]), VPERMILPD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x05, 0x4C, 0xC2, 0xB3, 0x02]), VPERMILPD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7D, 0x05, 0xD7, 0x02]), VPERMILPD(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x0D, 0xD4]), VPERMILPD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x0D, 0x54, 0xD9, 0xBE]), VPERMILPD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7D, 0x05, 0x54, 0xD9, 0xBE, 0x02]), VPERMILPD(ymm2, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPERMT2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x7F, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMT2PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x7F, 0xF3]), VPERMT2PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x7F, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMT2PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x7F, 0xDC]), VPERMT2PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x7F, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMT2PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x7F, 0xC9]), VPERMT2PD(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPERMI2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x77, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMI2PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x77, 0xF3]), VPERMI2PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x77, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMI2PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x77, 0xDC]), VPERMI2PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x77, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMI2PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x77, 0xC9]), VPERMI2PD(zmm9(k6.z), zmm26, zmm9).encode())
class TestVMOVD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x79, 0x7E, 0xF5]), VMOVD(ebp, xmm14).encode())
self.assertEqual(bytearray([0xC5, 0xF9, 0x7E, 0xE5]), VMOVD(ebp, xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x6E, 0xC8]), VMOVD(xmm1, r8d).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7D, 0x08, 0x6E, 0xC0]), VMOVD(xmm16, r8d).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x6E, 0x4C, 0xCC, 0x9D]), VMOVD(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7D, 0x08, 0x6E, 0x44, 0x24, 0x10]), VMOVD(xmm16, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x79, 0x7E, 0x74, 0xCC, 0x9D]), VMOVD(dword[r12 + rcx*8 - 99], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x7E, 0x64, 0x24, 0xC0]), VMOVD(dword[r12 - 64], xmm4).encode())
class TestVMOVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x61, 0xF9, 0x7E, 0xF1]), VMOVQ(rcx, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xE1, 0xF9, 0x7E, 0xE1]), VMOVQ(rcx, xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xF9, 0x6E, 0xCF]), VMOVQ(xmm1, r15).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0x08, 0x6E, 0xC7]), VMOVQ(xmm16, r15).encode())
self.assertEqual(bytearray([0xC5, 0x79, 0xD6, 0xF1]), VMOVQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFE, 0x08, 0x7E, 0xC4]), VMOVQ(xmm16, xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x7E, 0x4C, 0xD3, 0xA8]), VMOVQ(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0x08, 0x6E, 0x43, 0x08]), VMOVQ(xmm16, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x79, 0xD6, 0x74, 0xD3, 0xA8]), VMOVQ(qword[r11 + rdx*8 - 88], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0xD6, 0x63, 0xC0]), VMOVQ(qword[r11 - 64], xmm4).encode())
class TestVMOVDQA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x79, 0x7F, 0xF1]), VMOVDQA(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x6F, 0x4C, 0xC2, 0xB3]), VMOVDQA(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x7D, 0x7F, 0xFA]), VMOVDQA(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x6F, 0x54, 0xD9, 0xBE]), VMOVDQA(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x79, 0x7F, 0x74, 0xC2, 0xB3]), VMOVDQA(oword[r10 + rax*8 - 77], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7D, 0x7F, 0x7C, 0xD9, 0xBE]), VMOVDQA(hword[r9 + rbx*8 - 66], ymm15).encode())
class TestVMOVDQA32(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x7D, 0x08, 0x7F, 0x62, 0xFC]), VMOVDQA32(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7D, 0x8A, 0x6F, 0xF4]), VMOVDQA32(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x7D, 0x28, 0x7F, 0x69, 0xFE]), VMOVDQA32(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7D, 0xAD, 0x6F, 0xDD]), VMOVDQA32(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7D, 0x48, 0x7F, 0x50, 0xFF]), VMOVDQA32(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7D, 0xCE, 0x6F, 0xCA]), VMOVDQA32(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7D, 0x8A, 0x6F, 0x72, 0x04]), VMOVDQA32(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7D, 0xAD, 0x6F, 0x59, 0x02]), VMOVDQA32(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7D, 0xCE, 0x6F, 0x48, 0x01]), VMOVDQA32(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVMOVDQA64(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0xFD, 0x08, 0x7F, 0x62, 0xFC]), VMOVDQA64(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0x6F, 0xF4]), VMOVDQA64(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xFD, 0x28, 0x7F, 0x69, 0xFE]), VMOVDQA64(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0xAD, 0x6F, 0xDD]), VMOVDQA64(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x48, 0x7F, 0x50, 0xFF]), VMOVDQA64(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFD, 0xCE, 0x6F, 0xCA]), VMOVDQA64(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0x6F, 0x72, 0x04]), VMOVDQA64(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xAD, 0x6F, 0x59, 0x02]), VMOVDQA64(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFD, 0xCE, 0x6F, 0x48, 0x01]), VMOVDQA64(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVMOVDQU(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x7A, 0x7F, 0xF1]), VMOVDQU(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x6F, 0x4C, 0xC2, 0xB3]), VMOVDQU(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x7E, 0x7F, 0xFA]), VMOVDQU(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0x6F, 0x54, 0xD9, 0xBE]), VMOVDQU(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7A, 0x7F, 0x74, 0xC2, 0xB3]), VMOVDQU(oword[r10 + rax*8 - 77], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7E, 0x7F, 0x7C, 0xD9, 0xBE]), VMOVDQU(hword[r9 + rbx*8 - 66], ymm15).encode())
class TestVMOVDQU8(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x7F, 0x08, 0x7F, 0x62, 0xFC]), VMOVDQU8(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7F, 0x8A, 0x6F, 0xF4]), VMOVDQU8(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x7F, 0x28, 0x7F, 0x69, 0xFE]), VMOVDQU8(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7F, 0xAD, 0x6F, 0xDD]), VMOVDQU8(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7F, 0x48, 0x7F, 0x50, 0xFF]), VMOVDQU8(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7F, 0xCE, 0x6F, 0xCA]), VMOVDQU8(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7F, 0x8A, 0x6F, 0x72, 0x04]), VMOVDQU8(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7F, 0xAD, 0x6F, 0x59, 0x02]), VMOVDQU8(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7F, 0xCE, 0x6F, 0x48, 0x01]), VMOVDQU8(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVMOVDQU16(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0xFF, 0x08, 0x7F, 0x62, 0xFC]), VMOVDQU16(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFF, 0x8A, 0x6F, 0xF4]), VMOVDQU16(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xFF, 0x28, 0x7F, 0x69, 0xFE]), VMOVDQU16(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFF, 0xAD, 0x6F, 0xDD]), VMOVDQU16(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFF, 0x48, 0x7F, 0x50, 0xFF]), VMOVDQU16(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFF, 0xCE, 0x6F, 0xCA]), VMOVDQU16(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFF, 0x8A, 0x6F, 0x72, 0x04]), VMOVDQU16(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFF, 0xAD, 0x6F, 0x59, 0x02]), VMOVDQU16(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFF, 0xCE, 0x6F, 0x48, 0x01]), VMOVDQU16(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVMOVDQU32(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x7E, 0x08, 0x7F, 0x62, 0xFC]), VMOVDQU32(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7E, 0x8A, 0x6F, 0xF4]), VMOVDQU32(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x7E, 0x28, 0x7F, 0x69, 0xFE]), VMOVDQU32(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7E, 0xAD, 0x6F, 0xDD]), VMOVDQU32(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7E, 0x48, 0x7F, 0x50, 0xFF]), VMOVDQU32(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7E, 0xCE, 0x6F, 0xCA]), VMOVDQU32(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7E, 0x8A, 0x6F, 0x72, 0x04]), VMOVDQU32(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7E, 0xAD, 0x6F, 0x59, 0x02]), VMOVDQU32(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7E, 0xCE, 0x6F, 0x48, 0x01]), VMOVDQU32(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVMOVDQU64(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0xFE, 0x08, 0x7F, 0x62, 0xFC]), VMOVDQU64(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFE, 0x8A, 0x6F, 0xF4]), VMOVDQU64(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xFE, 0x28, 0x7F, 0x69, 0xFE]), VMOVDQU64(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFE, 0xAD, 0x6F, 0xDD]), VMOVDQU64(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFE, 0x48, 0x7F, 0x50, 0xFF]), VMOVDQU64(zword[r8 - 64], zmm26).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFE, 0xCE, 0x6F, 0xCA]), VMOVDQU64(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFE, 0x8A, 0x6F, 0x72, 0x04]), VMOVDQU64(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFE, 0xAD, 0x6F, 0x59, 0x02]), VMOVDQU64(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFE, 0xCE, 0x6F, 0x48, 0x01]), VMOVDQU64(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVLDDQU(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0xF0, 0x4C, 0xC2, 0xB3]), VLDDQU(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7F, 0xF0, 0x54, 0xD9, 0xBE]), VLDDQU(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVPBROADCASTB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x7A, 0xF0]), VPBROADCASTB(xmm30(k2.z), r8d).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x7A, 0xD8]), VPBROADCASTB(ymm19(k5.z), r8d).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x7A, 0xC8]), VPBROADCASTB(zmm9(k6.z), r8d).encode())
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x78, 0xF4]), VPBROADCASTB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x78, 0xDC]), VPBROADCASTB(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x78, 0xCC]), VPBROADCASTB(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x78, 0x76, 0x40]), VPBROADCASTB(xmm30(k2.z), byte[r14 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x78, 0x5E, 0x40]), VPBROADCASTB(ymm19(k5.z), byte[r14 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x78, 0x4E, 0x40]), VPBROADCASTB(zmm9(k6.z), byte[r14 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x78, 0xCE]), VPBROADCASTB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x78, 0x4C, 0xBE, 0x85]), VPBROADCASTB(xmm1, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x78, 0xD6]), VPBROADCASTB(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x78, 0x54, 0xBE, 0x85]), VPBROADCASTB(ymm2, byte[r14 + rdi*4 - 123]).encode())
class TestVPBROADCASTW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x7B, 0xF0]), VPBROADCASTW(xmm30(k2.z), r8d).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x7B, 0xD8]), VPBROADCASTW(ymm19(k5.z), r8d).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x7B, 0xC8]), VPBROADCASTW(zmm9(k6.z), r8d).encode())
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x79, 0xF4]), VPBROADCASTW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x79, 0xDC]), VPBROADCASTW(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x79, 0xCC]), VPBROADCASTW(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x79, 0x75, 0x20]), VPBROADCASTW(xmm30(k2.z), word[r13 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x79, 0x5D, 0x20]), VPBROADCASTW(ymm19(k5.z), word[r13 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x79, 0x4D, 0x20]), VPBROADCASTW(zmm9(k6.z), word[r13 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x79, 0xCE]), VPBROADCASTW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x79, 0x4C, 0xED, 0x95]), VPBROADCASTW(xmm1, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x79, 0xD6]), VPBROADCASTW(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x79, 0x54, 0xED, 0x95]), VPBROADCASTW(ymm2, word[r13 + rbp*8 - 107]).encode())
class TestVPBROADCASTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x7C, 0xF0]), VPBROADCASTD(xmm30(k2.z), r8d).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x7C, 0xD8]), VPBROADCASTD(ymm19(k5.z), r8d).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x7C, 0xC8]), VPBROADCASTD(zmm9(k6.z), r8d).encode())
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x58, 0xF4]), VPBROADCASTD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x58, 0xDC]), VPBROADCASTD(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x58, 0xCC]), VPBROADCASTD(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x58, 0x74, 0x24, 0x10]), VPBROADCASTD(xmm30(k2.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x58, 0x5C, 0x24, 0x10]), VPBROADCASTD(ymm19(k5.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x58, 0x4C, 0x24, 0x10]), VPBROADCASTD(zmm9(k6.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x58, 0xCE]), VPBROADCASTD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x58, 0x4C, 0xCC, 0x9D]), VPBROADCASTD(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x58, 0xD6]), VPBROADCASTD(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x58, 0x54, 0xCC, 0x9D]), VPBROADCASTD(ymm2, dword[r12 + rcx*8 - 99]).encode())
class TestVPBROADCASTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0x7C, 0xF7]), VPBROADCASTQ(xmm30(k2.z), r15).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x7C, 0xDF]), VPBROADCASTQ(ymm19(k5.z), r15).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x7C, 0xCF]), VPBROADCASTQ(zmm9(k6.z), r15).encode())
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x8A, 0x59, 0xF4]), VPBROADCASTQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0x59, 0xDC]), VPBROADCASTQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0xFD, 0xCE, 0x59, 0xCC]), VPBROADCASTQ(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0x59, 0x73, 0x08]), VPBROADCASTQ(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x59, 0x5B, 0x08]), VPBROADCASTQ(ymm19(k5.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x59, 0x4B, 0x08]), VPBROADCASTQ(zmm9(k6.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x59, 0xCE]), VPBROADCASTQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x59, 0x4C, 0xD3, 0xA8]), VPBROADCASTQ(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x59, 0xD6]), VPBROADCASTQ(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x59, 0x54, 0xD3, 0xA8]), VPBROADCASTQ(ymm2, qword[r11 + rdx*8 - 88]).encode())
class TestVPEXPANDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x89, 0xF4]), VPEXPANDD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x89, 0xDD]), VPEXPANDD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0x89, 0xCA]), VPEXPANDD(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x89, 0x72, 0x10]), VPEXPANDD(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x89, 0x59, 0x10]), VPEXPANDD(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x89, 0x48, 0x10]), VPEXPANDD(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVPEXPANDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x8A, 0x89, 0xF4]), VPEXPANDQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0x89, 0xDD]), VPEXPANDQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0xCE, 0x89, 0xCA]), VPEXPANDQ(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0x89, 0x72, 0x08]), VPEXPANDQ(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x89, 0x59, 0x08]), VPEXPANDQ(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x89, 0x48, 0x08]), VPEXPANDQ(zmm9(k6.z), zword[r8 + 64]).encode())
class TestVPCOMPRESSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7D, 0x8A, 0x8B, 0xE6]), VPCOMPRESSD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x08, 0x8B, 0x62, 0xF0]), VPCOMPRESSD(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0x7D, 0xAD, 0x8B, 0xEB]), VPCOMPRESSD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x28, 0x8B, 0x69, 0xF0]), VPCOMPRESSD(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0xCE, 0x8B, 0xD1]), VPCOMPRESSD(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x48, 0x8B, 0x50, 0xF0]), VPCOMPRESSD(zword[r8 - 64], zmm26).encode())
class TestVPCOMPRESSQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0xFD, 0x8A, 0x8B, 0xE6]), VPCOMPRESSQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xFD, 0x08, 0x8B, 0x62, 0xF8]), VPCOMPRESSQ(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xFD, 0xAD, 0x8B, 0xEB]), VPCOMPRESSQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xFD, 0x28, 0x8B, 0x69, 0xF8]), VPCOMPRESSQ(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0xCE, 0x8B, 0xD1]), VPCOMPRESSQ(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x48, 0x8B, 0x50, 0xF8]), VPCOMPRESSQ(zword[r8 - 64], zmm26).encode())
class TestVPMASKMOVD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x8C, 0x4C, 0xC2, 0xB3]), VPMASKMOVD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x8C, 0x54, 0xD9, 0xBE]), VPMASKMOVD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x8E, 0x5C, 0xC2, 0xB3]), VPMASKMOVD(oword[r10 + rax*8 - 77], xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x8E, 0x64, 0xD9, 0xBE]), VPMASKMOVD(hword[r9 + rbx*8 - 66], ymm15, ymm4).encode())
class TestVPMASKMOVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x8C, 0x4C, 0xC2, 0xB3]), VPMASKMOVQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x8C, 0x54, 0xD9, 0xBE]), VPMASKMOVQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x8E, 0x5C, 0xC2, 0xB3]), VPMASKMOVQ(oword[r10 + rax*8 - 77], xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x8E, 0x64, 0xD9, 0xBE]), VPMASKMOVQ(hword[r9 + rbx*8 - 66], ymm15, ymm4).encode())
class TestVMASKMOVDQU(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0xF7, 0xCE]), VMASKMOVDQU(xmm1, xmm14).encode())
class TestVMOVNTDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x41, 0x79, 0xE7, 0x74, 0xC2, 0xB3]), VMOVNTDQ(oword[r10 + rax*8 - 77], xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0xE7, 0x62, 0xC0]), VMOVNTDQ(oword[r10 - 64], xmm4).encode())
self.assertEqual(bytearray([0xC4, 0x41, 0x7D, 0xE7, 0x7C, 0xD9, 0xBE]), VMOVNTDQ(hword[r9 + rbx*8 - 66], ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0xE7, 0x69, 0xC0]), VMOVNTDQ(hword[r9 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7D, 0x48, 0xE7, 0x50, 0xFF]), VMOVNTDQ(zword[r8 - 64], zmm26).encode())
class TestVMOVNTDQA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x2A, 0x4C, 0xC2, 0xB3]), VMOVNTDQA(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0x08, 0x2A, 0x42, 0x04]), VMOVNTDQA(xmm16, oword[r10 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x2A, 0x54, 0xD9, 0xBE]), VMOVNTDQA(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0x28, 0x2A, 0x49, 0x02]), VMOVNTDQA(ymm17, hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x48, 0x2A, 0x58, 0x01]), VMOVNTDQA(zmm3, zword[r8 + 64]).encode())
class TestVPMOVSXBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x20, 0xF4]), VPMOVSXBW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x20, 0xDC]), VPMOVSXBW(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x20, 0xCD]), VPMOVSXBW(zmm9(k6.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x20, 0x73, 0x08]), VPMOVSXBW(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x20, 0x5A, 0x04]), VPMOVSXBW(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x20, 0x49, 0x02]), VPMOVSXBW(zmm9(k6.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x20, 0xCE]), VPMOVSXBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x20, 0x4C, 0xD3, 0xA8]), VPMOVSXBW(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x20, 0xD6]), VPMOVSXBW(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x20, 0x54, 0xC2, 0xB3]), VPMOVSXBW(ymm2, oword[r10 + rax*8 - 77]).encode())
class TestVPMOVSXBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x21, 0xF4]), VPMOVSXBD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x21, 0xDC]), VPMOVSXBD(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x21, 0xCC]), VPMOVSXBD(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x21, 0x74, 0x24, 0x10]), VPMOVSXBD(xmm30(k2.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x21, 0x5B, 0x08]), VPMOVSXBD(ymm19(k5.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x21, 0x4A, 0x04]), VPMOVSXBD(zmm9(k6.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x21, 0xCE]), VPMOVSXBD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x21, 0x4C, 0xCC, 0x9D]), VPMOVSXBD(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x21, 0xD6]), VPMOVSXBD(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x21, 0x54, 0xD3, 0xA8]), VPMOVSXBD(ymm2, qword[r11 + rdx*8 - 88]).encode())
class TestVPMOVSXBQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x22, 0xF4]), VPMOVSXBQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x22, 0xDC]), VPMOVSXBQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x22, 0xCC]), VPMOVSXBQ(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x22, 0x75, 0x20]), VPMOVSXBQ(xmm30(k2.z), word[r13 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x22, 0x5C, 0x24, 0x10]), VPMOVSXBQ(ymm19(k5.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x22, 0x4B, 0x08]), VPMOVSXBQ(zmm9(k6.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x22, 0xCE]), VPMOVSXBQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x22, 0x4C, 0xED, 0x95]), VPMOVSXBQ(xmm1, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x22, 0xD6]), VPMOVSXBQ(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x22, 0x54, 0xCC, 0x9D]), VPMOVSXBQ(ymm2, dword[r12 + rcx*8 - 99]).encode())
class TestVPMOVSXWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x23, 0xF4]), VPMOVSXWD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x23, 0xDC]), VPMOVSXWD(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x23, 0xCD]), VPMOVSXWD(zmm9(k6.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x23, 0x73, 0x08]), VPMOVSXWD(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x23, 0x5A, 0x04]), VPMOVSXWD(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x23, 0x49, 0x02]), VPMOVSXWD(zmm9(k6.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x23, 0xCE]), VPMOVSXWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x23, 0x4C, 0xD3, 0xA8]), VPMOVSXWD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x23, 0xD6]), VPMOVSXWD(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x23, 0x54, 0xC2, 0xB3]), VPMOVSXWD(ymm2, oword[r10 + rax*8 - 77]).encode())
class TestVPMOVSXWQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x24, 0xF4]), VPMOVSXWQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x24, 0xDC]), VPMOVSXWQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x24, 0xCC]), VPMOVSXWQ(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x24, 0x74, 0x24, 0x10]), VPMOVSXWQ(xmm30(k2.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x24, 0x5B, 0x08]), VPMOVSXWQ(ymm19(k5.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x24, 0x4A, 0x04]), VPMOVSXWQ(zmm9(k6.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x24, 0xCE]), VPMOVSXWQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x24, 0x4C, 0xCC, 0x9D]), VPMOVSXWQ(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x24, 0xD6]), VPMOVSXWQ(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x24, 0x54, 0xD3, 0xA8]), VPMOVSXWQ(ymm2, qword[r11 + rdx*8 - 88]).encode())
class TestVPMOVSXDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x25, 0xF4]), VPMOVSXDQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x25, 0xDC]), VPMOVSXDQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x25, 0xCD]), VPMOVSXDQ(zmm9(k6.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x25, 0x73, 0x08]), VPMOVSXDQ(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x25, 0x5A, 0x04]), VPMOVSXDQ(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x25, 0x49, 0x02]), VPMOVSXDQ(zmm9(k6.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x25, 0xCE]), VPMOVSXDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x25, 0x4C, 0xD3, 0xA8]), VPMOVSXDQ(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x25, 0xD6]), VPMOVSXDQ(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x25, 0x54, 0xC2, 0xB3]), VPMOVSXDQ(ymm2, oword[r10 + rax*8 - 77]).encode())
class TestVPMOVZXBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x30, 0xF4]), VPMOVZXBW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x30, 0xDC]), VPMOVZXBW(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x30, 0xCD]), VPMOVZXBW(zmm9(k6.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x30, 0x73, 0x08]), VPMOVZXBW(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x30, 0x5A, 0x04]), VPMOVZXBW(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x30, 0x49, 0x02]), VPMOVZXBW(zmm9(k6.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x30, 0xCE]), VPMOVZXBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x30, 0x4C, 0xD3, 0xA8]), VPMOVZXBW(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x30, 0xD6]), VPMOVZXBW(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x30, 0x54, 0xC2, 0xB3]), VPMOVZXBW(ymm2, oword[r10 + rax*8 - 77]).encode())
class TestVPMOVZXBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x31, 0xF4]), VPMOVZXBD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x31, 0xDC]), VPMOVZXBD(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x31, 0xCC]), VPMOVZXBD(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x31, 0x74, 0x24, 0x10]), VPMOVZXBD(xmm30(k2.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x31, 0x5B, 0x08]), VPMOVZXBD(ymm19(k5.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x31, 0x4A, 0x04]), VPMOVZXBD(zmm9(k6.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x31, 0xCE]), VPMOVZXBD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x31, 0x4C, 0xCC, 0x9D]), VPMOVZXBD(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x31, 0xD6]), VPMOVZXBD(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x31, 0x54, 0xD3, 0xA8]), VPMOVZXBD(ymm2, qword[r11 + rdx*8 - 88]).encode())
class TestVPMOVZXBQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x32, 0xF4]), VPMOVZXBQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x32, 0xDC]), VPMOVZXBQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x32, 0xCC]), VPMOVZXBQ(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x32, 0x75, 0x20]), VPMOVZXBQ(xmm30(k2.z), word[r13 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x32, 0x5C, 0x24, 0x10]), VPMOVZXBQ(ymm19(k5.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x32, 0x4B, 0x08]), VPMOVZXBQ(zmm9(k6.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x32, 0xCE]), VPMOVZXBQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x32, 0x4C, 0xED, 0x95]), VPMOVZXBQ(xmm1, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x32, 0xD6]), VPMOVZXBQ(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x32, 0x54, 0xCC, 0x9D]), VPMOVZXBQ(ymm2, dword[r12 + rcx*8 - 99]).encode())
class TestVPMOVZXWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x33, 0xF4]), VPMOVZXWD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x33, 0xDC]), VPMOVZXWD(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x33, 0xCD]), VPMOVZXWD(zmm9(k6.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x33, 0x73, 0x08]), VPMOVZXWD(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x33, 0x5A, 0x04]), VPMOVZXWD(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x33, 0x49, 0x02]), VPMOVZXWD(zmm9(k6.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x33, 0xCE]), VPMOVZXWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x33, 0x4C, 0xD3, 0xA8]), VPMOVZXWD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x33, 0xD6]), VPMOVZXWD(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x33, 0x54, 0xC2, 0xB3]), VPMOVZXWD(ymm2, oword[r10 + rax*8 - 77]).encode())
class TestVPMOVZXWQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x34, 0xF4]), VPMOVZXWQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x34, 0xDC]), VPMOVZXWQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x34, 0xCC]), VPMOVZXWQ(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x34, 0x74, 0x24, 0x10]), VPMOVZXWQ(xmm30(k2.z), dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x34, 0x5B, 0x08]), VPMOVZXWQ(ymm19(k5.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x34, 0x4A, 0x04]), VPMOVZXWQ(zmm9(k6.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x34, 0xCE]), VPMOVZXWQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x34, 0x4C, 0xCC, 0x9D]), VPMOVZXWQ(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x34, 0xD6]), VPMOVZXWQ(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x34, 0x54, 0xD3, 0xA8]), VPMOVZXWQ(ymm2, qword[r11 + rdx*8 - 88]).encode())
class TestVPMOVZXDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x35, 0xF4]), VPMOVZXDQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x35, 0xDC]), VPMOVZXDQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x35, 0xCD]), VPMOVZXDQ(zmm9(k6.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x35, 0x73, 0x08]), VPMOVZXDQ(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x35, 0x5A, 0x04]), VPMOVZXDQ(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x35, 0x49, 0x02]), VPMOVZXDQ(zmm9(k6.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x35, 0xCE]), VPMOVZXDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x35, 0x4C, 0xD3, 0xA8]), VPMOVZXDQ(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x35, 0xD6]), VPMOVZXDQ(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x35, 0x54, 0xC2, 0xB3]), VPMOVZXDQ(ymm2, oword[r10 + rax*8 - 77]).encode())
class TestVPMOVWB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x30, 0xE6]), VPMOVWB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x30, 0x63, 0xF8]), VPMOVWB(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x30, 0xEE]), VPMOVWB(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x30, 0x6A, 0xFC]), VPMOVWB(oword[r10 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x7E, 0xCD, 0x30, 0xD3]), VPMOVWB(ymm19(k5.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x30, 0x51, 0xFE]), VPMOVWB(hword[r9 - 64], zmm26).encode())
class TestVPMOVDB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x31, 0xE6]), VPMOVDB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x31, 0x64, 0x24, 0xF0]), VPMOVDB(dword[r12 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x31, 0xEE]), VPMOVDB(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x31, 0x6B, 0xF8]), VPMOVDB(qword[r11 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7E, 0xCA, 0x31, 0xD6]), VPMOVDB(xmm30(k2.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x31, 0x52, 0xFC]), VPMOVDB(oword[r10 - 64], zmm26).encode())
class TestVPMOVDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x33, 0xE6]), VPMOVDW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x33, 0x63, 0xF8]), VPMOVDW(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x33, 0xEE]), VPMOVDW(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x33, 0x6A, 0xFC]), VPMOVDW(oword[r10 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x7E, 0xCD, 0x33, 0xD3]), VPMOVDW(ymm19(k5.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x33, 0x51, 0xFE]), VPMOVDW(hword[r9 - 64], zmm26).encode())
class TestVPMOVQB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x32, 0xE6]), VPMOVQB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x32, 0x65, 0xE0]), VPMOVQB(word[r13 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x32, 0xEE]), VPMOVQB(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x32, 0x6C, 0x24, 0xF0]), VPMOVQB(dword[r12 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7E, 0xCA, 0x32, 0xD6]), VPMOVQB(xmm30(k2.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x32, 0x53, 0xF8]), VPMOVQB(qword[r11 - 64], zmm26).encode())
class TestVPMOVQW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x34, 0xE6]), VPMOVQW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x34, 0x64, 0x24, 0xF0]), VPMOVQW(dword[r12 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x34, 0xEE]), VPMOVQW(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x34, 0x6B, 0xF8]), VPMOVQW(qword[r11 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7E, 0xCA, 0x34, 0xD6]), VPMOVQW(xmm30(k2.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x34, 0x52, 0xFC]), VPMOVQW(oword[r10 - 64], zmm26).encode())
class TestVPMOVQD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x35, 0xE6]), VPMOVQD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x35, 0x63, 0xF8]), VPMOVQD(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x35, 0xEE]), VPMOVQD(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x35, 0x6A, 0xFC]), VPMOVQD(oword[r10 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x7E, 0xCD, 0x35, 0xD3]), VPMOVQD(ymm19(k5.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x35, 0x51, 0xFE]), VPMOVQD(hword[r9 - 64], zmm26).encode())
class TestVPMOVSWB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x20, 0xE6]), VPMOVSWB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x20, 0x63, 0xF8]), VPMOVSWB(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x20, 0xEE]), VPMOVSWB(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x20, 0x6A, 0xFC]), VPMOVSWB(oword[r10 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x7E, 0xCD, 0x20, 0xD3]), VPMOVSWB(ymm19(k5.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x20, 0x51, 0xFE]), VPMOVSWB(hword[r9 - 64], zmm26).encode())
class TestVPMOVSDB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x21, 0xE6]), VPMOVSDB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x21, 0x64, 0x24, 0xF0]), VPMOVSDB(dword[r12 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x21, 0xEE]), VPMOVSDB(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x21, 0x6B, 0xF8]), VPMOVSDB(qword[r11 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7E, 0xCA, 0x21, 0xD6]), VPMOVSDB(xmm30(k2.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x21, 0x52, 0xFC]), VPMOVSDB(oword[r10 - 64], zmm26).encode())
class TestVPMOVSDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x23, 0xE6]), VPMOVSDW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x23, 0x63, 0xF8]), VPMOVSDW(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x23, 0xEE]), VPMOVSDW(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x23, 0x6A, 0xFC]), VPMOVSDW(oword[r10 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x7E, 0xCD, 0x23, 0xD3]), VPMOVSDW(ymm19(k5.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x23, 0x51, 0xFE]), VPMOVSDW(hword[r9 - 64], zmm26).encode())
class TestVPMOVSQB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x22, 0xE6]), VPMOVSQB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x22, 0x65, 0xE0]), VPMOVSQB(word[r13 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x22, 0xEE]), VPMOVSQB(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x22, 0x6C, 0x24, 0xF0]), VPMOVSQB(dword[r12 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7E, 0xCA, 0x22, 0xD6]), VPMOVSQB(xmm30(k2.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x22, 0x53, 0xF8]), VPMOVSQB(qword[r11 - 64], zmm26).encode())
class TestVPMOVSQW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x24, 0xE6]), VPMOVSQW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x24, 0x64, 0x24, 0xF0]), VPMOVSQW(dword[r12 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x24, 0xEE]), VPMOVSQW(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x24, 0x6B, 0xF8]), VPMOVSQW(qword[r11 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7E, 0xCA, 0x24, 0xD6]), VPMOVSQW(xmm30(k2.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x24, 0x52, 0xFC]), VPMOVSQW(oword[r10 - 64], zmm26).encode())
class TestVPMOVSQD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x25, 0xE6]), VPMOVSQD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x25, 0x63, 0xF8]), VPMOVSQD(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x25, 0xEE]), VPMOVSQD(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x25, 0x6A, 0xFC]), VPMOVSQD(oword[r10 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x7E, 0xCD, 0x25, 0xD3]), VPMOVSQD(ymm19(k5.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x25, 0x51, 0xFE]), VPMOVSQD(hword[r9 - 64], zmm26).encode())
class TestVPMOVUSWB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x10, 0xE6]), VPMOVUSWB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x10, 0x63, 0xF8]), VPMOVUSWB(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x10, 0xEE]), VPMOVUSWB(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x10, 0x6A, 0xFC]), VPMOVUSWB(oword[r10 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x7E, 0xCD, 0x10, 0xD3]), VPMOVUSWB(ymm19(k5.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x10, 0x51, 0xFE]), VPMOVUSWB(hword[r9 - 64], zmm26).encode())
class TestVPMOVUSDB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x11, 0xE6]), VPMOVUSDB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x11, 0x64, 0x24, 0xF0]), VPMOVUSDB(dword[r12 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x11, 0xEE]), VPMOVUSDB(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x11, 0x6B, 0xF8]), VPMOVUSDB(qword[r11 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7E, 0xCA, 0x11, 0xD6]), VPMOVUSDB(xmm30(k2.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x11, 0x52, 0xFC]), VPMOVUSDB(oword[r10 - 64], zmm26).encode())
class TestVPMOVUSDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x13, 0xE6]), VPMOVUSDW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x13, 0x63, 0xF8]), VPMOVUSDW(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x13, 0xEE]), VPMOVUSDW(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x13, 0x6A, 0xFC]), VPMOVUSDW(oword[r10 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x7E, 0xCD, 0x13, 0xD3]), VPMOVUSDW(ymm19(k5.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x13, 0x51, 0xFE]), VPMOVUSDW(hword[r9 - 64], zmm26).encode())
class TestVPMOVUSQB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x12, 0xE6]), VPMOVUSQB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x12, 0x65, 0xE0]), VPMOVUSQB(word[r13 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x12, 0xEE]), VPMOVUSQB(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x12, 0x6C, 0x24, 0xF0]), VPMOVUSQB(dword[r12 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7E, 0xCA, 0x12, 0xD6]), VPMOVUSQB(xmm30(k2.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x12, 0x53, 0xF8]), VPMOVUSQB(qword[r11 - 64], zmm26).encode())
class TestVPMOVUSQW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x14, 0xE6]), VPMOVUSQW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x14, 0x64, 0x24, 0xF0]), VPMOVUSQW(dword[r12 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x14, 0xEE]), VPMOVUSQW(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x14, 0x6B, 0xF8]), VPMOVUSQW(qword[r11 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7E, 0xCA, 0x14, 0xD6]), VPMOVUSQW(xmm30(k2.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x14, 0x52, 0xFC]), VPMOVUSQW(oword[r10 - 64], zmm26).encode())
class TestVPMOVUSQD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x8A, 0x15, 0xE6]), VPMOVUSQD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x08, 0x15, 0x63, 0xF8]), VPMOVUSQD(qword[r11 - 64], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0xAA, 0x15, 0xEE]), VPMOVUSQD(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7E, 0x28, 0x15, 0x6A, 0xFC]), VPMOVUSQD(oword[r10 - 64], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x7E, 0xCD, 0x15, 0xD3]), VPMOVUSQD(ymm19(k5.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7E, 0x48, 0x15, 0x51, 0xFE]), VPMOVUSQD(hword[r9 - 64], zmm26).encode())
class TestVPEXTRB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x63, 0x79, 0x14, 0xF5, 0x02]), VPEXTRB(ebp, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x79, 0x14, 0xE5, 0x02]), VPEXTRB(ebp, xmm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0x43, 0x79, 0x14, 0x74, 0xBE, 0x85, 0x02]), VPEXTRB(byte[r14 + rdi*4 - 123], xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x14, 0x66, 0xC0, 0x02]), VPEXTRB(byte[r14 - 64], xmm4, 2).encode())
class TestVPEXTRW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0xC5, 0xEE, 0x02]), VPEXTRW(ebp, xmm14, 2).encode())
self.assertEqual(bytearray([0xC5, 0xF9, 0xC5, 0xEC, 0x02]), VPEXTRW(ebp, xmm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0x43, 0x79, 0x15, 0x74, 0xED, 0x95, 0x02]), VPEXTRW(word[r13 + rbp*8 - 107], xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x15, 0x65, 0xC0, 0x02]), VPEXTRW(word[r13 - 64], xmm4, 2).encode())
class TestVPEXTRD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x63, 0x79, 0x16, 0xF5, 0x02]), VPEXTRD(ebp, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x79, 0x16, 0xE5, 0x02]), VPEXTRD(ebp, xmm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0x43, 0x79, 0x16, 0x74, 0xCC, 0x9D, 0x02]), VPEXTRD(dword[r12 + rcx*8 - 99], xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x16, 0x64, 0x24, 0xC0, 0x02]), VPEXTRD(dword[r12 - 64], xmm4, 2).encode())
class TestVPEXTRQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x63, 0xF9, 0x16, 0xF1, 0x02]), VPEXTRQ(rcx, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0xF9, 0x16, 0xE1, 0x02]), VPEXTRQ(rcx, xmm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0x43, 0xF9, 0x16, 0x74, 0xD3, 0xA8, 0x02]), VPEXTRQ(qword[r11 + rdx*8 - 88], xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0xF9, 0x16, 0x63, 0xC0, 0x02]), VPEXTRQ(qword[r11 - 64], xmm4, 2).encode())
class TestVPINSRB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x20, 0xC8, 0x02]), VPINSRB(xmm1, xmm14, eax, 2).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0x5D, 0x08, 0x20, 0xC0, 0x02]), VPINSRB(xmm16, xmm4, eax, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x20, 0x4C, 0xBE, 0x85, 0x02]), VPINSRB(xmm1, xmm14, byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x5D, 0x08, 0x20, 0x46, 0x80, 0x02]), VPINSRB(xmm16, xmm4, byte[r14 - 128], 2).encode())
class TestVPINSRW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x89, 0xC4, 0xC8, 0x02]), VPINSRW(xmm1, xmm14, eax, 2).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x5D, 0x08, 0xC4, 0xC0, 0x02]), VPINSRW(xmm16, xmm4, eax, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xC4, 0x4C, 0xED, 0x95, 0x02]), VPINSRW(xmm1, xmm14, word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x5D, 0x08, 0xC4, 0x45, 0xC0, 0x02]), VPINSRW(xmm16, xmm4, word[r13 - 128], 2).encode())
class TestVPINSRD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x22, 0xC8, 0x02]), VPINSRD(xmm1, xmm14, eax, 2).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0x5D, 0x08, 0x22, 0xC0, 0x02]), VPINSRD(xmm16, xmm4, eax, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x22, 0x4C, 0xCC, 0x9D, 0x02]), VPINSRD(xmm1, xmm14, dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x5D, 0x08, 0x22, 0x44, 0x24, 0xE0, 0x02]), VPINSRD(xmm16, xmm4, dword[r12 - 128], 2).encode())
class TestVPINSRQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x89, 0x22, 0xC8, 0x02]), VPINSRQ(xmm1, xmm14, rax, 2).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0xDD, 0x08, 0x22, 0xC0, 0x02]), VPINSRQ(xmm16, xmm4, rax, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x22, 0x4C, 0xD3, 0xA8, 0x02]), VPINSRQ(xmm1, xmm14, qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xDD, 0x08, 0x22, 0x43, 0xF0, 0x02]), VPINSRQ(xmm16, xmm4, qword[r11 - 128], 2).encode())
class TestVPGATHERDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7D, 0x09, 0x90, 0x6C, 0x86, 0xE0]), VPGATHERDD(xmm5(k1), [rsi + xmm0 * 4 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x02, 0x7D, 0x2B, 0x90, 0x44, 0x83, 0x0C]), VPGATHERDD(ymm24(k3), [r11 + ymm8 * 4 + 48]).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x47, 0x90, 0x54, 0x9F, 0xFC]), VPGATHERDD(zmm26(k7), [r15 + zmm19 * 4 - 16]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x61, 0x90, 0x4C, 0x86, 0x80]), VPGATHERDD(xmm1, [rsi + xmm0 * 4 - 128], xmm3).encode())
self.assertEqual(bytearray([0xC4, 0x82, 0x5D, 0x90, 0x54, 0x83, 0x30]), VPGATHERDD(ymm2, [r11 + ymm8 * 4 + 48], ymm4).encode())
class TestVPGATHERDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x09, 0x90, 0x6C, 0x86, 0xF0]), VPGATHERDQ(xmm5(k1), [rsi + xmm0 * 4 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x2B, 0x90, 0x44, 0x86, 0xF0]), VPGATHERDQ(ymm24(k3), [rsi + xmm0 * 4 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x02, 0xFD, 0x4F, 0x90, 0x54, 0x83, 0x06]), VPGATHERDQ(zmm26(k7), [r11 + ymm8 * 4 + 48]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0xE1, 0x90, 0x4C, 0x86, 0x80]), VPGATHERDQ(xmm1, [rsi + xmm0 * 4 - 128], xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0xDD, 0x90, 0x54, 0x86, 0x80]), VPGATHERDQ(ymm2, [rsi + xmm0 * 4 - 128], ymm4).encode())
class TestVPGATHERQD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7D, 0x09, 0x91, 0x6C, 0xCE, 0x0A]), VPGATHERQD(xmm5(k1), [rsi + xmm1 * 8 + 40]).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7D, 0x29, 0x91, 0x6C, 0xCB, 0xF2]), VPGATHERQD(xmm5(k1), [r11 + ymm9 * 8 - 56]).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x43, 0x91, 0x44, 0xE7, 0x12]), VPGATHERQD(ymm24(k3), [r15 + zmm20 * 8 + 72]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x61, 0x91, 0x4C, 0xCE, 0x28]), VPGATHERQD(xmm1, [rsi + xmm1 * 8 + 40], xmm3).encode())
self.assertEqual(bytearray([0xC4, 0x82, 0x65, 0x91, 0x4C, 0xCB, 0xC8]), VPGATHERQD(xmm1, [r11 + ymm9 * 8 - 56], xmm3).encode())
class TestVPGATHERQQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x09, 0x91, 0x6C, 0xCE, 0x05]), VPGATHERQQ(xmm5(k1), [rsi + xmm1 * 8 + 40]).encode())
self.assertEqual(bytearray([0x62, 0x02, 0xFD, 0x2B, 0x91, 0x44, 0xCB, 0xF9]), VPGATHERQQ(ymm24(k3), [r11 + ymm9 * 8 - 56]).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x47, 0x91, 0x54, 0xE7, 0x09]), VPGATHERQQ(zmm26(k7), [r15 + zmm20 * 8 + 72]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0xE1, 0x91, 0x4C, 0xCE, 0x28]), VPGATHERQQ(xmm1, [rsi + xmm1 * 8 + 40], xmm3).encode())
self.assertEqual(bytearray([0xC4, 0x82, 0xDD, 0x91, 0x54, 0xCB, 0xC8]), VPGATHERQQ(ymm2, [r11 + ymm9 * 8 - 56], ymm4).encode())
class TestVPSCATTERDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7D, 0x09, 0xA0, 0x64, 0x86, 0xE0]), VPSCATTERDD([rsi + xmm0(k1) * 4 - 128], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7D, 0x2A, 0xA0, 0x6C, 0x83, 0x0C]), VPSCATTERDD([r11 + ymm8(k2) * 4 + 48], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x43, 0xA0, 0x54, 0x9F, 0xFC]), VPSCATTERDD([r15 + zmm19(k3) * 4 - 16], zmm26).encode())
class TestVPSCATTERDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x09, 0xA0, 0x64, 0x86, 0xF0]), VPSCATTERDQ([rsi + xmm0(k1) * 4 - 128], xmm4).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x29, 0xA0, 0x6C, 0x86, 0xF0]), VPSCATTERDQ([rsi + xmm0(k1) * 4 - 128], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x02, 0xFD, 0x4A, 0xA0, 0x54, 0x83, 0x06]), VPSCATTERDQ([r11 + ymm8(k2) * 4 + 48], zmm26).encode())
class TestVPSCATTERQD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7D, 0x0C, 0xA1, 0x64, 0xCE, 0x0A]), VPSCATTERQD([rsi + xmm1(k4) * 8 + 40], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7D, 0x2D, 0xA1, 0x64, 0xCB, 0xF2]), VPSCATTERQD([r11 + ymm9(k5) * 8 - 56], xmm4).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x7D, 0x46, 0xA1, 0x6C, 0xE7, 0x12]), VPSCATTERQD([r15 + zmm20(k6) * 8 + 72], ymm5).encode())
class TestVPSCATTERQQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFD, 0x0C, 0xA1, 0x64, 0xCE, 0x05]), VPSCATTERQQ([rsi + xmm1(k4) * 8 + 40], xmm4).encode())
self.assertEqual(bytearray([0x62, 0x92, 0xFD, 0x2D, 0xA1, 0x6C, 0xCB, 0xF9]), VPSCATTERQQ([r11 + ymm9(k5) * 8 - 56], ymm5).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x46, 0xA1, 0x54, 0xE7, 0x09]), VPSCATTERQQ([r15 + zmm20(k6) * 8 + 72], zmm26).encode())
class TestVPCONFLICTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0xC4, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPCONFLICTD(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0xC4, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCONFLICTD(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0xC4, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCONFLICTD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0xC4, 0xF4]), VPCONFLICTD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0xC4, 0xDD]), VPCONFLICTD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0xC4, 0xCA]), VPCONFLICTD(zmm9(k6.z), zmm26).encode())
class TestVPCONFLICTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0xC4, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPCONFLICTQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0xC4, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCONFLICTQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0xC4, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCONFLICTQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x8A, 0xC4, 0xF4]), VPCONFLICTQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0xC4, 0xDD]), VPCONFLICTQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0xCE, 0xC4, 0xCA]), VPCONFLICTQ(zmm9(k6.z), zmm26).encode())
class TestVPLZCNTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x44, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPLZCNTD(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x44, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPLZCNTD(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x44, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPLZCNTD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x44, 0xF4]), VPLZCNTD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x44, 0xDD]), VPLZCNTD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0x44, 0xCA]), VPLZCNTD(zmm9(k6.z), zmm26).encode())
class TestVPLZCNTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0x44, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPLZCNTQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x44, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPLZCNTQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x44, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPLZCNTQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x8A, 0x44, 0xF4]), VPLZCNTQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0x44, 0xDD]), VPLZCNTQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0xCE, 0x44, 0xCA]), VPLZCNTQ(zmm9(k6.z), zmm26).encode())
class TestVPTEST(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x17, 0xCE]), VPTEST(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x17, 0x4C, 0xC2, 0xB3]), VPTEST(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x17, 0xD7]), VPTEST(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x17, 0x54, 0xD9, 0xBE]), VPTEST(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVPMOVMSKB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0xD7, 0xEE]), VPMOVMSKB(ebp, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0xD7, 0xEF]), VPMOVMSKB(ebp, ymm15).encode())
class TestVPADDB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xFC, 0xF3]), VPADDB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xFC, 0x72, 0xF8]), VPADDB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xFC, 0xDC]), VPADDB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xFC, 0x59, 0xFC]), VPADDB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xFC, 0xC9]), VPADDB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xFC, 0x48, 0xFE]), VPADDB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xFC, 0xCB]), VPADDB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xFC, 0x4C, 0xC2, 0xB3]), VPADDB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xFC, 0xD4]), VPADDB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xFC, 0x54, 0xD9, 0xBE]), VPADDB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPADDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xFD, 0xF3]), VPADDW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xFD, 0x72, 0xF8]), VPADDW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xFD, 0xDC]), VPADDW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xFD, 0x59, 0xFC]), VPADDW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xFD, 0xC9]), VPADDW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xFD, 0x48, 0xFE]), VPADDW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xFD, 0xCB]), VPADDW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xFD, 0x4C, 0xC2, 0xB3]), VPADDW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xFD, 0xD4]), VPADDW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xFD, 0x54, 0xD9, 0xBE]), VPADDW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPADDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xFE, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPADDD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xFE, 0xF3]), VPADDD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xFE, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPADDD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xFE, 0xDC]), VPADDD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xFE, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPADDD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xFE, 0xC9]), VPADDD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xFE, 0xCB]), VPADDD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xFE, 0x4C, 0xC2, 0xB3]), VPADDD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xFE, 0xD4]), VPADDD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xFE, 0x54, 0xD9, 0xBE]), VPADDD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPADDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xD4, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPADDQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xD4, 0xF3]), VPADDQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xD4, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPADDQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xD4, 0xDC]), VPADDQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xD4, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPADDQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xD4, 0xC9]), VPADDQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xD4, 0xCB]), VPADDQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xD4, 0x4C, 0xC2, 0xB3]), VPADDQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xD4, 0xD4]), VPADDQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xD4, 0x54, 0xD9, 0xBE]), VPADDQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPADDSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xEC, 0xF3]), VPADDSB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xEC, 0x72, 0xF8]), VPADDSB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xEC, 0xDC]), VPADDSB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xEC, 0x59, 0xFC]), VPADDSB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEC, 0xC9]), VPADDSB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEC, 0x48, 0xFE]), VPADDSB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xEC, 0xCB]), VPADDSB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xEC, 0x4C, 0xC2, 0xB3]), VPADDSB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xEC, 0xD4]), VPADDSB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xEC, 0x54, 0xD9, 0xBE]), VPADDSB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPADDSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xED, 0xF3]), VPADDSW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xED, 0x72, 0xF8]), VPADDSW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xED, 0xDC]), VPADDSW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xED, 0x59, 0xFC]), VPADDSW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xED, 0xC9]), VPADDSW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xED, 0x48, 0xFE]), VPADDSW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xED, 0xCB]), VPADDSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xED, 0x4C, 0xC2, 0xB3]), VPADDSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xED, 0xD4]), VPADDSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xED, 0x54, 0xD9, 0xBE]), VPADDSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPADDUSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xDC, 0xF3]), VPADDUSB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xDC, 0x72, 0xF8]), VPADDUSB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xDC, 0xDC]), VPADDUSB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xDC, 0x59, 0xFC]), VPADDUSB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDC, 0xC9]), VPADDUSB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDC, 0x48, 0xFE]), VPADDUSB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xDC, 0xCB]), VPADDUSB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xDC, 0x4C, 0xC2, 0xB3]), VPADDUSB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xDC, 0xD4]), VPADDUSB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xDC, 0x54, 0xD9, 0xBE]), VPADDUSB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPADDUSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xDD, 0xF3]), VPADDUSW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xDD, 0x72, 0xF8]), VPADDUSW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xDD, 0xDC]), VPADDUSW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xDD, 0x59, 0xFC]), VPADDUSW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDD, 0xC9]), VPADDUSW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDD, 0x48, 0xFE]), VPADDUSW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xDD, 0xCB]), VPADDUSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xDD, 0x4C, 0xC2, 0xB3]), VPADDUSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xDD, 0xD4]), VPADDUSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xDD, 0x54, 0xD9, 0xBE]), VPADDUSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPHADDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x01, 0xCB]), VPHADDW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x01, 0x4C, 0xC2, 0xB3]), VPHADDW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x01, 0xD4]), VPHADDW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x01, 0x54, 0xD9, 0xBE]), VPHADDW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPHADDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x02, 0xCB]), VPHADDD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x02, 0x4C, 0xC2, 0xB3]), VPHADDD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x02, 0xD4]), VPHADDD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x02, 0x54, 0xD9, 0xBE]), VPHADDD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPHADDSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x03, 0xCB]), VPHADDSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x03, 0x4C, 0xC2, 0xB3]), VPHADDSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x03, 0xD4]), VPHADDSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x03, 0x54, 0xD9, 0xBE]), VPHADDSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSUBB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xF8, 0xF3]), VPSUBB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xF8, 0x72, 0xF8]), VPSUBB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xF8, 0xDC]), VPSUBB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xF8, 0x59, 0xFC]), VPSUBB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xF8, 0xC9]), VPSUBB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xF8, 0x48, 0xFE]), VPSUBB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xF8, 0xCB]), VPSUBB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xF8, 0x4C, 0xC2, 0xB3]), VPSUBB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xF8, 0xD4]), VPSUBB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xF8, 0x54, 0xD9, 0xBE]), VPSUBB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSUBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xF9, 0xF3]), VPSUBW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xF9, 0x72, 0xF8]), VPSUBW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xF9, 0xDC]), VPSUBW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xF9, 0x59, 0xFC]), VPSUBW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xF9, 0xC9]), VPSUBW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xF9, 0x48, 0xFE]), VPSUBW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xF9, 0xCB]), VPSUBW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xF9, 0x4C, 0xC2, 0xB3]), VPSUBW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xF9, 0xD4]), VPSUBW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xF9, 0x54, 0xD9, 0xBE]), VPSUBW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSUBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xFA, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPSUBD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xFA, 0xF3]), VPSUBD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xFA, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSUBD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xFA, 0xDC]), VPSUBD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xFA, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSUBD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xFA, 0xC9]), VPSUBD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xFA, 0xCB]), VPSUBD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xFA, 0x4C, 0xC2, 0xB3]), VPSUBD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xFA, 0xD4]), VPSUBD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xFA, 0x54, 0xD9, 0xBE]), VPSUBD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSUBQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xFB, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPSUBQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xFB, 0xF3]), VPSUBQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xFB, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSUBQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xFB, 0xDC]), VPSUBQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xFB, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSUBQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xFB, 0xC9]), VPSUBQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xFB, 0xCB]), VPSUBQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xFB, 0x4C, 0xC2, 0xB3]), VPSUBQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xFB, 0xD4]), VPSUBQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xFB, 0x54, 0xD9, 0xBE]), VPSUBQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSUBSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xE8, 0xF3]), VPSUBSB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xE8, 0x72, 0xF8]), VPSUBSB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xE8, 0xDC]), VPSUBSB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xE8, 0x59, 0xFC]), VPSUBSB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE8, 0xC9]), VPSUBSB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE8, 0x48, 0xFE]), VPSUBSB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xE8, 0xCB]), VPSUBSB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xE8, 0x4C, 0xC2, 0xB3]), VPSUBSB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xE8, 0xD4]), VPSUBSB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xE8, 0x54, 0xD9, 0xBE]), VPSUBSB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSUBSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xE9, 0xF3]), VPSUBSW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xE9, 0x72, 0xF8]), VPSUBSW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xE9, 0xDC]), VPSUBSW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xE9, 0x59, 0xFC]), VPSUBSW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE9, 0xC9]), VPSUBSW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE9, 0x48, 0xFE]), VPSUBSW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xE9, 0xCB]), VPSUBSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xE9, 0x4C, 0xC2, 0xB3]), VPSUBSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xE9, 0xD4]), VPSUBSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xE9, 0x54, 0xD9, 0xBE]), VPSUBSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSUBUSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xD8, 0xF3]), VPSUBUSB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xD8, 0x72, 0xF8]), VPSUBUSB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xD8, 0xDC]), VPSUBUSB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xD8, 0x59, 0xFC]), VPSUBUSB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xD8, 0xC9]), VPSUBUSB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xD8, 0x48, 0xFE]), VPSUBUSB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xD8, 0xCB]), VPSUBUSB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xD8, 0x4C, 0xC2, 0xB3]), VPSUBUSB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xD8, 0xD4]), VPSUBUSB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xD8, 0x54, 0xD9, 0xBE]), VPSUBUSB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSUBUSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xD9, 0xF3]), VPSUBUSW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xD9, 0x72, 0xF8]), VPSUBUSW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xD9, 0xDC]), VPSUBUSW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xD9, 0x59, 0xFC]), VPSUBUSW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xD9, 0xC9]), VPSUBUSW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xD9, 0x48, 0xFE]), VPSUBUSW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xD9, 0xCB]), VPSUBUSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xD9, 0x4C, 0xC2, 0xB3]), VPSUBUSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xD9, 0xD4]), VPSUBUSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xD9, 0x54, 0xD9, 0xBE]), VPSUBUSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPHSUBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x05, 0xCB]), VPHSUBW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x05, 0x4C, 0xC2, 0xB3]), VPHSUBW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x05, 0xD4]), VPHSUBW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x05, 0x54, 0xD9, 0xBE]), VPHSUBW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPHSUBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x06, 0xCB]), VPHSUBD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x06, 0x4C, 0xC2, 0xB3]), VPHSUBD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x06, 0xD4]), VPHSUBD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x06, 0x54, 0xD9, 0xBE]), VPHSUBD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPHSUBSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x07, 0xCB]), VPHSUBSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x07, 0x4C, 0xC2, 0xB3]), VPHSUBSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x07, 0xD4]), VPHSUBSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x07, 0x54, 0xD9, 0xBE]), VPHSUBSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMAXSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x3C, 0xF3]), VPMAXSB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x3C, 0x72, 0xF8]), VPMAXSB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x3C, 0xDC]), VPMAXSB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x3C, 0x59, 0xFC]), VPMAXSB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3C, 0xC9]), VPMAXSB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3C, 0x48, 0xFE]), VPMAXSB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x3C, 0xCB]), VPMAXSB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x3C, 0x4C, 0xC2, 0xB3]), VPMAXSB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x3C, 0xD4]), VPMAXSB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x3C, 0x54, 0xD9, 0xBE]), VPMAXSB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMAXSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xEE, 0xF3]), VPMAXSW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xEE, 0x72, 0xF8]), VPMAXSW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xEE, 0xDC]), VPMAXSW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xEE, 0x59, 0xFC]), VPMAXSW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEE, 0xC9]), VPMAXSW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEE, 0x48, 0xFE]), VPMAXSW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xEE, 0xCB]), VPMAXSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xEE, 0x4C, 0xC2, 0xB3]), VPMAXSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xEE, 0xD4]), VPMAXSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xEE, 0x54, 0xD9, 0xBE]), VPMAXSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMAXSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x3D, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMAXSD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x3D, 0xF3]), VPMAXSD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x3D, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMAXSD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x3D, 0xDC]), VPMAXSD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3D, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMAXSD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3D, 0xC9]), VPMAXSD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x3D, 0xCB]), VPMAXSD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x3D, 0x4C, 0xC2, 0xB3]), VPMAXSD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x3D, 0xD4]), VPMAXSD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x3D, 0x54, 0xD9, 0xBE]), VPMAXSD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMAXSQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x3D, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMAXSQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x3D, 0xF3]), VPMAXSQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x3D, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMAXSQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x3D, 0xDC]), VPMAXSQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x3D, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMAXSQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x3D, 0xC9]), VPMAXSQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPMAXUB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xDE, 0xF3]), VPMAXUB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xDE, 0x72, 0xF8]), VPMAXUB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xDE, 0xDC]), VPMAXUB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xDE, 0x59, 0xFC]), VPMAXUB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDE, 0xC9]), VPMAXUB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDE, 0x48, 0xFE]), VPMAXUB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xDE, 0xCB]), VPMAXUB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xDE, 0x4C, 0xC2, 0xB3]), VPMAXUB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xDE, 0xD4]), VPMAXUB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xDE, 0x54, 0xD9, 0xBE]), VPMAXUB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMAXUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x3E, 0xF3]), VPMAXUW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x3E, 0x72, 0xF8]), VPMAXUW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x3E, 0xDC]), VPMAXUW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x3E, 0x59, 0xFC]), VPMAXUW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3E, 0xC9]), VPMAXUW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3E, 0x48, 0xFE]), VPMAXUW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x3E, 0xCB]), VPMAXUW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x3E, 0x4C, 0xC2, 0xB3]), VPMAXUW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x3E, 0xD4]), VPMAXUW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x3E, 0x54, 0xD9, 0xBE]), VPMAXUW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMAXUD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x3F, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMAXUD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x3F, 0xF3]), VPMAXUD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x3F, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMAXUD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x3F, 0xDC]), VPMAXUD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3F, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMAXUD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3F, 0xC9]), VPMAXUD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x3F, 0xCB]), VPMAXUD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x3F, 0x4C, 0xC2, 0xB3]), VPMAXUD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x3F, 0xD4]), VPMAXUD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x3F, 0x54, 0xD9, 0xBE]), VPMAXUD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMAXUQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x3F, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMAXUQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x3F, 0xF3]), VPMAXUQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x3F, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMAXUQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x3F, 0xDC]), VPMAXUQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x3F, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMAXUQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x3F, 0xC9]), VPMAXUQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPMINSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x38, 0xF3]), VPMINSB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x38, 0x72, 0xF8]), VPMINSB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x38, 0xDC]), VPMINSB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x38, 0x59, 0xFC]), VPMINSB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x38, 0xC9]), VPMINSB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x38, 0x48, 0xFE]), VPMINSB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x38, 0xCB]), VPMINSB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x38, 0x4C, 0xC2, 0xB3]), VPMINSB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x38, 0xD4]), VPMINSB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x38, 0x54, 0xD9, 0xBE]), VPMINSB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMINSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xEA, 0xF3]), VPMINSW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xEA, 0x72, 0xF8]), VPMINSW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xEA, 0xDC]), VPMINSW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xEA, 0x59, 0xFC]), VPMINSW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEA, 0xC9]), VPMINSW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEA, 0x48, 0xFE]), VPMINSW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xEA, 0xCB]), VPMINSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xEA, 0x4C, 0xC2, 0xB3]), VPMINSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xEA, 0xD4]), VPMINSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xEA, 0x54, 0xD9, 0xBE]), VPMINSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMINSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x39, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMINSD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x39, 0xF3]), VPMINSD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x39, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMINSD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x39, 0xDC]), VPMINSD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x39, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMINSD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x39, 0xC9]), VPMINSD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x39, 0xCB]), VPMINSD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x39, 0x4C, 0xC2, 0xB3]), VPMINSD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x39, 0xD4]), VPMINSD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x39, 0x54, 0xD9, 0xBE]), VPMINSD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMINSQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x39, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMINSQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x39, 0xF3]), VPMINSQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x39, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMINSQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x39, 0xDC]), VPMINSQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x39, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMINSQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x39, 0xC9]), VPMINSQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPMINUB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xDA, 0xF3]), VPMINUB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xDA, 0x72, 0xF8]), VPMINUB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xDA, 0xDC]), VPMINUB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xDA, 0x59, 0xFC]), VPMINUB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDA, 0xC9]), VPMINUB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDA, 0x48, 0xFE]), VPMINUB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xDA, 0xCB]), VPMINUB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xDA, 0x4C, 0xC2, 0xB3]), VPMINUB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xDA, 0xD4]), VPMINUB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xDA, 0x54, 0xD9, 0xBE]), VPMINUB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMINUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x3A, 0xF3]), VPMINUW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x3A, 0x72, 0xF8]), VPMINUW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x3A, 0xDC]), VPMINUW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x3A, 0x59, 0xFC]), VPMINUW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3A, 0xC9]), VPMINUW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3A, 0x48, 0xFE]), VPMINUW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x3A, 0xCB]), VPMINUW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x3A, 0x4C, 0xC2, 0xB3]), VPMINUW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x3A, 0xD4]), VPMINUW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x3A, 0x54, 0xD9, 0xBE]), VPMINUW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMINUD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x3B, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMINUD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x3B, 0xF3]), VPMINUD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x3B, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMINUD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x3B, 0xDC]), VPMINUD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3B, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMINUD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x3B, 0xC9]), VPMINUD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x3B, 0xCB]), VPMINUD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x3B, 0x4C, 0xC2, 0xB3]), VPMINUD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x3B, 0xD4]), VPMINUD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x3B, 0x54, 0xD9, 0xBE]), VPMINUD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMINUQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x3B, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMINUQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x3B, 0xF3]), VPMINUQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x3B, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMINUQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x3B, 0xDC]), VPMINUQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x3B, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMINUQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x3B, 0xC9]), VPMINUQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPSLLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF1, 0x0D, 0x82, 0x71, 0xF4, 0x02]), VPSLLW(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xF1, 0xF3]), VPSLLW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xF1, 0x72, 0xF8]), VPSLLW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x65, 0xA5, 0x71, 0xF5, 0x02]), VPSLLW(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xF1, 0xDB]), VPSLLW(ymm19(k5.z), ymm5, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xF1, 0x5A, 0xF8]), VPSLLW(ymm19(k5.z), ymm5, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x35, 0xCE, 0x71, 0xF2, 0x02]), VPSLLW(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x31, 0x2D, 0xC6, 0xF1, 0xCB]), VPSLLW(zmm9(k6.z), zmm26, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xF1, 0x4A, 0xF8]), VPSLLW(zmm9(k6.z), zmm26, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x0D, 0x82, 0x71, 0x72, 0x04, 0x02]), VPSLLW(xmm30(k2.z), oword[r10 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0xA5, 0x71, 0x71, 0x02, 0x02]), VPSLLW(ymm19(k5.z), hword[r9 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x35, 0xCE, 0x71, 0x70, 0x01, 0x02]), VPSLLW(zmm9(k6.z), zword[r8 + 64], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x71, 0xF6, 0x02]), VPSLLW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xF1, 0xCB]), VPSLLW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xF1, 0x4C, 0xC2, 0xB3]), VPSLLW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x71, 0xF7, 0x02]), VPSLLW(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xF1, 0xD3]), VPSLLW(ymm2, ymm15, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xF1, 0x54, 0xC2, 0xB3]), VPSLLW(ymm2, ymm15, oword[r10 + rax*8 - 77]).encode())
class TestVPSLLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x0D, 0x82, 0x72, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPSLLD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0xA5, 0x72, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSLLD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x35, 0xCE, 0x72, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSLLD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x0D, 0x82, 0x72, 0xF4, 0x02]), VPSLLD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xF2, 0xF3]), VPSLLD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xF2, 0x72, 0xF8]), VPSLLD(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x65, 0xA5, 0x72, 0xF5, 0x02]), VPSLLD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xF2, 0xDB]), VPSLLD(ymm19(k5.z), ymm5, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xF2, 0x5A, 0xF8]), VPSLLD(ymm19(k5.z), ymm5, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x35, 0xCE, 0x72, 0xF2, 0x02]), VPSLLD(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x31, 0x2D, 0xC6, 0xF2, 0xCB]), VPSLLD(zmm9(k6.z), zmm26, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xF2, 0x4A, 0xF8]), VPSLLD(zmm9(k6.z), zmm26, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x72, 0xF6, 0x02]), VPSLLD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xF2, 0xCB]), VPSLLD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xF2, 0x4C, 0xC2, 0xB3]), VPSLLD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x72, 0xF7, 0x02]), VPSLLD(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xF2, 0xD3]), VPSLLD(ymm2, ymm15, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xF2, 0x54, 0xC2, 0xB3]), VPSLLD(ymm2, ymm15, oword[r10 + rax*8 - 77]).encode())
class TestVPSLLQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x8D, 0x82, 0x73, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPSLLQ(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xE5, 0xA5, 0x73, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSLLQ(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xB5, 0xCE, 0x73, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSLLQ(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x8D, 0x82, 0x73, 0xF4, 0x02]), VPSLLQ(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xF3, 0xF3]), VPSLLQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xF3, 0x72, 0xF8]), VPSLLQ(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xE5, 0xA5, 0x73, 0xF5, 0x02]), VPSLLQ(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xF3, 0xDB]), VPSLLQ(ymm19(k5.z), ymm5, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xF3, 0x5A, 0xF8]), VPSLLQ(ymm19(k5.z), ymm5, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x91, 0xB5, 0xCE, 0x73, 0xF2, 0x02]), VPSLLQ(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x31, 0xAD, 0xC6, 0xF3, 0xCB]), VPSLLQ(zmm9(k6.z), zmm26, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xF3, 0x4A, 0xF8]), VPSLLQ(zmm9(k6.z), zmm26, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x73, 0xF6, 0x02]), VPSLLQ(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xF3, 0xCB]), VPSLLQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xF3, 0x4C, 0xC2, 0xB3]), VPSLLQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x73, 0xF7, 0x02]), VPSLLQ(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xF3, 0xD3]), VPSLLQ(ymm2, ymm15, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xF3, 0x54, 0xC2, 0xB3]), VPSLLQ(ymm2, ymm15, oword[r10 + rax*8 - 77]).encode())
class TestVPSRLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF1, 0x0D, 0x82, 0x71, 0xD4, 0x02]), VPSRLW(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xD1, 0xF3]), VPSRLW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xD1, 0x72, 0xF8]), VPSRLW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x65, 0xA5, 0x71, 0xD5, 0x02]), VPSRLW(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xD1, 0xDB]), VPSRLW(ymm19(k5.z), ymm5, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xD1, 0x5A, 0xF8]), VPSRLW(ymm19(k5.z), ymm5, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x35, 0xCE, 0x71, 0xD2, 0x02]), VPSRLW(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x31, 0x2D, 0xC6, 0xD1, 0xCB]), VPSRLW(zmm9(k6.z), zmm26, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xD1, 0x4A, 0xF8]), VPSRLW(zmm9(k6.z), zmm26, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x0D, 0x82, 0x71, 0x52, 0x04, 0x02]), VPSRLW(xmm30(k2.z), oword[r10 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0xA5, 0x71, 0x51, 0x02, 0x02]), VPSRLW(ymm19(k5.z), hword[r9 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x35, 0xCE, 0x71, 0x50, 0x01, 0x02]), VPSRLW(zmm9(k6.z), zword[r8 + 64], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x71, 0xD6, 0x02]), VPSRLW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xD1, 0xCB]), VPSRLW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xD1, 0x4C, 0xC2, 0xB3]), VPSRLW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x71, 0xD7, 0x02]), VPSRLW(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xD1, 0xD3]), VPSRLW(ymm2, ymm15, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xD1, 0x54, 0xC2, 0xB3]), VPSRLW(ymm2, ymm15, oword[r10 + rax*8 - 77]).encode())
class TestVPSRLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x0D, 0x82, 0x72, 0x94, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPSRLD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0xA5, 0x72, 0x94, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSRLD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x35, 0xCE, 0x72, 0x94, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSRLD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x0D, 0x82, 0x72, 0xD4, 0x02]), VPSRLD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xD2, 0xF3]), VPSRLD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xD2, 0x72, 0xF8]), VPSRLD(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x65, 0xA5, 0x72, 0xD5, 0x02]), VPSRLD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xD2, 0xDB]), VPSRLD(ymm19(k5.z), ymm5, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xD2, 0x5A, 0xF8]), VPSRLD(ymm19(k5.z), ymm5, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x35, 0xCE, 0x72, 0xD2, 0x02]), VPSRLD(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x31, 0x2D, 0xC6, 0xD2, 0xCB]), VPSRLD(zmm9(k6.z), zmm26, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xD2, 0x4A, 0xF8]), VPSRLD(zmm9(k6.z), zmm26, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x72, 0xD6, 0x02]), VPSRLD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xD2, 0xCB]), VPSRLD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xD2, 0x4C, 0xC2, 0xB3]), VPSRLD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x72, 0xD7, 0x02]), VPSRLD(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xD2, 0xD3]), VPSRLD(ymm2, ymm15, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xD2, 0x54, 0xC2, 0xB3]), VPSRLD(ymm2, ymm15, oword[r10 + rax*8 - 77]).encode())
class TestVPSRLQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x8D, 0x82, 0x73, 0x94, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPSRLQ(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xE5, 0xA5, 0x73, 0x94, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSRLQ(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xB5, 0xCE, 0x73, 0x94, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSRLQ(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x8D, 0x82, 0x73, 0xD4, 0x02]), VPSRLQ(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xD3, 0xF3]), VPSRLQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xD3, 0x72, 0xF8]), VPSRLQ(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xE5, 0xA5, 0x73, 0xD5, 0x02]), VPSRLQ(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xD3, 0xDB]), VPSRLQ(ymm19(k5.z), ymm5, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xD3, 0x5A, 0xF8]), VPSRLQ(ymm19(k5.z), ymm5, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x91, 0xB5, 0xCE, 0x73, 0xD2, 0x02]), VPSRLQ(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x31, 0xAD, 0xC6, 0xD3, 0xCB]), VPSRLQ(zmm9(k6.z), zmm26, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xD3, 0x4A, 0xF8]), VPSRLQ(zmm9(k6.z), zmm26, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x73, 0xD6, 0x02]), VPSRLQ(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xD3, 0xCB]), VPSRLQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xD3, 0x4C, 0xC2, 0xB3]), VPSRLQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x73, 0xD7, 0x02]), VPSRLQ(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xD3, 0xD3]), VPSRLQ(ymm2, ymm15, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xD3, 0x54, 0xC2, 0xB3]), VPSRLQ(ymm2, ymm15, oword[r10 + rax*8 - 77]).encode())
class TestVPSRAW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF1, 0x0D, 0x82, 0x71, 0xE4, 0x02]), VPSRAW(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xE1, 0xF3]), VPSRAW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xE1, 0x72, 0xF8]), VPSRAW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x65, 0xA5, 0x71, 0xE5, 0x02]), VPSRAW(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xE1, 0xDB]), VPSRAW(ymm19(k5.z), ymm5, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xE1, 0x5A, 0xF8]), VPSRAW(ymm19(k5.z), ymm5, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x35, 0xCE, 0x71, 0xE2, 0x02]), VPSRAW(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x31, 0x2D, 0xC6, 0xE1, 0xCB]), VPSRAW(zmm9(k6.z), zmm26, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE1, 0x4A, 0xF8]), VPSRAW(zmm9(k6.z), zmm26, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x0D, 0x82, 0x71, 0x62, 0x04, 0x02]), VPSRAW(xmm30(k2.z), oword[r10 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0xA5, 0x71, 0x61, 0x02, 0x02]), VPSRAW(ymm19(k5.z), hword[r9 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x35, 0xCE, 0x71, 0x60, 0x01, 0x02]), VPSRAW(zmm9(k6.z), zword[r8 + 64], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x71, 0xE6, 0x02]), VPSRAW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xE1, 0xCB]), VPSRAW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xE1, 0x4C, 0xC2, 0xB3]), VPSRAW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x71, 0xE7, 0x02]), VPSRAW(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xE1, 0xD3]), VPSRAW(ymm2, ymm15, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xE1, 0x54, 0xC2, 0xB3]), VPSRAW(ymm2, ymm15, oword[r10 + rax*8 - 77]).encode())
class TestVPSRAD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x0D, 0x82, 0x72, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPSRAD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0xA5, 0x72, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSRAD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x35, 0xCE, 0x72, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSRAD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x0D, 0x82, 0x72, 0xE4, 0x02]), VPSRAD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xE2, 0xF3]), VPSRAD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xE2, 0x72, 0xF8]), VPSRAD(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x65, 0xA5, 0x72, 0xE5, 0x02]), VPSRAD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xE2, 0xDB]), VPSRAD(ymm19(k5.z), ymm5, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xE2, 0x5A, 0xF8]), VPSRAD(ymm19(k5.z), ymm5, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x35, 0xCE, 0x72, 0xE2, 0x02]), VPSRAD(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x31, 0x2D, 0xC6, 0xE2, 0xCB]), VPSRAD(zmm9(k6.z), zmm26, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE2, 0x4A, 0xF8]), VPSRAD(zmm9(k6.z), zmm26, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x72, 0xE6, 0x02]), VPSRAD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xE2, 0xCB]), VPSRAD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xE2, 0x4C, 0xC2, 0xB3]), VPSRAD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x72, 0xE7, 0x02]), VPSRAD(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xE2, 0xD3]), VPSRAD(ymm2, ymm15, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xE2, 0x54, 0xC2, 0xB3]), VPSRAD(ymm2, ymm15, oword[r10 + rax*8 - 77]).encode())
class TestVPSRAQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x8D, 0x82, 0x72, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPSRAQ(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xE5, 0xA5, 0x72, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSRAQ(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xB5, 0xCE, 0x72, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSRAQ(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x8D, 0x82, 0x72, 0xE4, 0x02]), VPSRAQ(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xE2, 0xF3]), VPSRAQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xE2, 0x72, 0xF8]), VPSRAQ(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xE5, 0xA5, 0x72, 0xE5, 0x02]), VPSRAQ(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xE2, 0xDB]), VPSRAQ(ymm19(k5.z), ymm5, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xE2, 0x5A, 0xF8]), VPSRAQ(ymm19(k5.z), ymm5, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x91, 0xB5, 0xCE, 0x72, 0xE2, 0x02]), VPSRAQ(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x31, 0xAD, 0xC6, 0xE2, 0xCB]), VPSRAQ(zmm9(k6.z), zmm26, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xE2, 0x4A, 0xF8]), VPSRAQ(zmm9(k6.z), zmm26, oword[r10 - 128]).encode())
class TestVPROLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x0D, 0x82, 0x72, 0x8C, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPROLD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0xA5, 0x72, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPROLD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x35, 0xCE, 0x72, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPROLD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x0D, 0x82, 0x72, 0xCC, 0x02]), VPROLD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x65, 0xA5, 0x72, 0xCD, 0x02]), VPROLD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x35, 0xCE, 0x72, 0xCA, 0x02]), VPROLD(zmm9(k6.z), zmm26, 2).encode())
class TestVPROLQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x8D, 0x82, 0x72, 0x8C, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPROLQ(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xE5, 0xA5, 0x72, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPROLQ(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xB5, 0xCE, 0x72, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPROLQ(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x8D, 0x82, 0x72, 0xCC, 0x02]), VPROLQ(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xE5, 0xA5, 0x72, 0xCD, 0x02]), VPROLQ(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x91, 0xB5, 0xCE, 0x72, 0xCA, 0x02]), VPROLQ(zmm9(k6.z), zmm26, 2).encode())
class TestVPRORD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x0D, 0x82, 0x72, 0x84, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPRORD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0xA5, 0x72, 0x84, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPRORD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x35, 0xCE, 0x72, 0x84, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPRORD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x0D, 0x82, 0x72, 0xC4, 0x02]), VPRORD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x65, 0xA5, 0x72, 0xC5, 0x02]), VPRORD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x35, 0xCE, 0x72, 0xC2, 0x02]), VPRORD(zmm9(k6.z), zmm26, 2).encode())
class TestVPRORQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x8D, 0x82, 0x72, 0x84, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPRORQ(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xE5, 0xA5, 0x72, 0x84, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPRORQ(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xB5, 0xCE, 0x72, 0x84, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPRORQ(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x8D, 0x82, 0x72, 0xC4, 0x02]), VPRORQ(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xE5, 0xA5, 0x72, 0xC5, 0x02]), VPRORQ(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x91, 0xB5, 0xCE, 0x72, 0xC2, 0x02]), VPRORQ(zmm9(k6.z), zmm26, 2).encode())
class TestVPSLLVW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x12, 0xF3]), VPSLLVW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x12, 0x72, 0xF8]), VPSLLVW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x12, 0xDC]), VPSLLVW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x12, 0x59, 0xFC]), VPSLLVW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x12, 0xC9]), VPSLLVW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x12, 0x48, 0xFE]), VPSLLVW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPSLLVD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x47, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPSLLVD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x47, 0xF3]), VPSLLVD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x47, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSLLVD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x47, 0xDC]), VPSLLVD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x47, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSLLVD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x47, 0xC9]), VPSLLVD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x47, 0xCB]), VPSLLVD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x47, 0x4C, 0xC2, 0xB3]), VPSLLVD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x47, 0xD4]), VPSLLVD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x47, 0x54, 0xD9, 0xBE]), VPSLLVD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSLLVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x47, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPSLLVQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x47, 0xF3]), VPSLLVQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x47, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSLLVQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x47, 0xDC]), VPSLLVQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x47, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSLLVQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x47, 0xC9]), VPSLLVQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x47, 0xCB]), VPSLLVQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x47, 0x4C, 0xC2, 0xB3]), VPSLLVQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0x47, 0xD4]), VPSLLVQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x47, 0x54, 0xD9, 0xBE]), VPSLLVQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSRLVW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x10, 0xF3]), VPSRLVW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x10, 0x72, 0xF8]), VPSRLVW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x10, 0xDC]), VPSRLVW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x10, 0x59, 0xFC]), VPSRLVW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x10, 0xC9]), VPSRLVW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x10, 0x48, 0xFE]), VPSRLVW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPSRLVD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x45, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPSRLVD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x45, 0xF3]), VPSRLVD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x45, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSRLVD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x45, 0xDC]), VPSRLVD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x45, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSRLVD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x45, 0xC9]), VPSRLVD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x45, 0xCB]), VPSRLVD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x45, 0x4C, 0xC2, 0xB3]), VPSRLVD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x45, 0xD4]), VPSRLVD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x45, 0x54, 0xD9, 0xBE]), VPSRLVD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSRLVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x45, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPSRLVQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x45, 0xF3]), VPSRLVQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x45, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSRLVQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x45, 0xDC]), VPSRLVQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x45, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSRLVQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x45, 0xC9]), VPSRLVQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x45, 0xCB]), VPSRLVQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x45, 0x4C, 0xC2, 0xB3]), VPSRLVQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0x45, 0xD4]), VPSRLVQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x45, 0x54, 0xD9, 0xBE]), VPSRLVQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSRAVW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x11, 0xF3]), VPSRAVW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x11, 0x72, 0xF8]), VPSRAVW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x11, 0xDC]), VPSRAVW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x11, 0x59, 0xFC]), VPSRAVW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x11, 0xC9]), VPSRAVW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x11, 0x48, 0xFE]), VPSRAVW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPSRAVD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x46, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPSRAVD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x46, 0xF3]), VPSRAVD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x46, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSRAVD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x46, 0xDC]), VPSRAVD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x46, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSRAVD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x46, 0xC9]), VPSRAVD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x46, 0xCB]), VPSRAVD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x46, 0x4C, 0xC2, 0xB3]), VPSRAVD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x46, 0xD4]), VPSRAVD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x46, 0x54, 0xD9, 0xBE]), VPSRAVD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSRAVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x46, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPSRAVQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x46, 0xF3]), VPSRAVQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x46, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSRAVQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x46, 0xDC]), VPSRAVQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x46, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPSRAVQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x46, 0xC9]), VPSRAVQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPROLVD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x15, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPROLVD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x15, 0xF3]), VPROLVD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x15, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPROLVD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x15, 0xDC]), VPROLVD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x15, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPROLVD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x15, 0xC9]), VPROLVD(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPROLVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x15, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPROLVQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x15, 0xF3]), VPROLVQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x15, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPROLVQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x15, 0xDC]), VPROLVQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x15, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPROLVQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x15, 0xC9]), VPROLVQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPRORVD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x14, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPRORVD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x14, 0xF3]), VPRORVD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x14, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPRORVD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x14, 0xDC]), VPRORVD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x14, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPRORVD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x14, 0xC9]), VPRORVD(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPRORVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x14, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPRORVQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x14, 0xF3]), VPRORVQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x14, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPRORVQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x14, 0xDC]), VPRORVQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x14, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPRORVQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x14, 0xC9]), VPRORVQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPMULLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xD5, 0xF3]), VPMULLW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xD5, 0x72, 0xF8]), VPMULLW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xD5, 0xDC]), VPMULLW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xD5, 0x59, 0xFC]), VPMULLW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xD5, 0xC9]), VPMULLW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xD5, 0x48, 0xFE]), VPMULLW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xD5, 0xCB]), VPMULLW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xD5, 0x4C, 0xC2, 0xB3]), VPMULLW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xD5, 0xD4]), VPMULLW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xD5, 0x54, 0xD9, 0xBE]), VPMULLW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMULHW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xE5, 0xF3]), VPMULHW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xE5, 0x72, 0xF8]), VPMULHW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xE5, 0xDC]), VPMULHW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xE5, 0x59, 0xFC]), VPMULHW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE5, 0xC9]), VPMULHW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE5, 0x48, 0xFE]), VPMULHW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xE5, 0xCB]), VPMULHW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xE5, 0x4C, 0xC2, 0xB3]), VPMULHW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xE5, 0xD4]), VPMULHW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xE5, 0x54, 0xD9, 0xBE]), VPMULHW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMULHUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xE4, 0xF3]), VPMULHUW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xE4, 0x72, 0xF8]), VPMULHUW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xE4, 0xDC]), VPMULHUW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xE4, 0x59, 0xFC]), VPMULHUW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE4, 0xC9]), VPMULHUW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE4, 0x48, 0xFE]), VPMULHUW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xE4, 0xCB]), VPMULHUW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xE4, 0x4C, 0xC2, 0xB3]), VPMULHUW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xE4, 0xD4]), VPMULHUW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xE4, 0x54, 0xD9, 0xBE]), VPMULHUW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMULLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x40, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMULLD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x40, 0xF3]), VPMULLD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x40, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULLD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x40, 0xDC]), VPMULLD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x40, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULLD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x40, 0xC9]), VPMULLD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x40, 0xCB]), VPMULLD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x40, 0x4C, 0xC2, 0xB3]), VPMULLD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x40, 0xD4]), VPMULLD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x40, 0x54, 0xD9, 0xBE]), VPMULLD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMULLQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x40, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMULLQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x40, 0xF3]), VPMULLQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x40, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULLQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x40, 0xDC]), VPMULLQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x40, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULLQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x40, 0xC9]), VPMULLQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPMULDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x28, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMULDQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x28, 0xF3]), VPMULDQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x28, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULDQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x28, 0xDC]), VPMULDQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x28, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULDQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x28, 0xC9]), VPMULDQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x28, 0xCB]), VPMULDQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x28, 0x4C, 0xC2, 0xB3]), VPMULDQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x28, 0xD4]), VPMULDQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x28, 0x54, 0xD9, 0xBE]), VPMULDQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMULUDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xF4, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMULUDQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xF4, 0xF3]), VPMULUDQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xF4, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULUDQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xF4, 0xDC]), VPMULUDQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xF4, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULUDQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xF4, 0xC9]), VPMULUDQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xF4, 0xCB]), VPMULUDQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xF4, 0x4C, 0xC2, 0xB3]), VPMULUDQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xF4, 0xD4]), VPMULUDQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xF4, 0x54, 0xD9, 0xBE]), VPMULUDQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMULHRSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x0B, 0xF3]), VPMULHRSW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x0B, 0x72, 0xF8]), VPMULHRSW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x0B, 0xDC]), VPMULHRSW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x0B, 0x59, 0xFC]), VPMULHRSW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x0B, 0xC9]), VPMULHRSW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x0B, 0x48, 0xFE]), VPMULHRSW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x0B, 0xCB]), VPMULHRSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x0B, 0x4C, 0xC2, 0xB3]), VPMULHRSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x0B, 0xD4]), VPMULHRSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x0B, 0x54, 0xD9, 0xBE]), VPMULHRSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMADDWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xF5, 0xF3]), VPMADDWD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xF5, 0x72, 0xF8]), VPMADDWD(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xF5, 0xDC]), VPMADDWD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xF5, 0x59, 0xFC]), VPMADDWD(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xF5, 0xC9]), VPMADDWD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xF5, 0x48, 0xFE]), VPMADDWD(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xF5, 0xCB]), VPMADDWD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xF5, 0x4C, 0xC2, 0xB3]), VPMADDWD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xF5, 0xD4]), VPMADDWD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xF5, 0x54, 0xD9, 0xBE]), VPMADDWD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMADDUBSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x04, 0xF3]), VPMADDUBSW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x04, 0x72, 0xF8]), VPMADDUBSW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x04, 0xDC]), VPMADDUBSW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x04, 0x59, 0xFC]), VPMADDUBSW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x04, 0xC9]), VPMADDUBSW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x04, 0x48, 0xFE]), VPMADDUBSW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x04, 0xCB]), VPMADDUBSW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x04, 0x4C, 0xC2, 0xB3]), VPMADDUBSW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x04, 0xD4]), VPMADDUBSW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x04, 0x54, 0xD9, 0xBE]), VPMADDUBSW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPMADD52LUQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xB4, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMADD52LUQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xB4, 0xF3]), VPMADD52LUQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xB4, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMADD52LUQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xB4, 0xDC]), VPMADD52LUQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xB4, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMADD52LUQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xB4, 0xC9]), VPMADD52LUQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPMADD52HUQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xB5, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMADD52HUQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xB5, 0xF3]), VPMADD52HUQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xB5, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMADD52HUQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xB5, 0xDC]), VPMADD52HUQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xB5, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMADD52HUQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xB5, 0xC9]), VPMADD52HUQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPAVGB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xE0, 0xF3]), VPAVGB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xE0, 0x72, 0xF8]), VPAVGB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xE0, 0xDC]), VPAVGB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xE0, 0x59, 0xFC]), VPAVGB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE0, 0xC9]), VPAVGB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE0, 0x48, 0xFE]), VPAVGB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xE0, 0xCB]), VPAVGB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xE0, 0x4C, 0xC2, 0xB3]), VPAVGB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xE0, 0xD4]), VPAVGB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xE0, 0x54, 0xD9, 0xBE]), VPAVGB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPAVGW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xE3, 0xF3]), VPAVGW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xE3, 0x72, 0xF8]), VPAVGW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xE3, 0xDC]), VPAVGW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xE3, 0x59, 0xFC]), VPAVGW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE3, 0xC9]), VPAVGW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xE3, 0x48, 0xFE]), VPAVGW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0xE3, 0xCB]), VPAVGW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xE3, 0x4C, 0xC2, 0xB3]), VPAVGW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xE3, 0xD4]), VPAVGW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xE3, 0x54, 0xD9, 0xBE]), VPAVGW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSADBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x89, 0xF6, 0xCB]), VPSADBW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x5D, 0x08, 0xF6, 0xC3]), VPSADBW(xmm16, xmm4, xmm19).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xF6, 0x4C, 0xC2, 0xB3]), VPSADBW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x5D, 0x08, 0xF6, 0x42, 0xF8]), VPSADBW(xmm16, xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xF6, 0xD4]), VPSADBW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0x28, 0xF6, 0xCC]), VPSADBW(ymm17, ymm5, ymm20).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xF6, 0x54, 0xD9, 0xBE]), VPSADBW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0x28, 0xF6, 0x49, 0xFC]), VPSADBW(ymm17, ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x40, 0xF6, 0xD9]), VPSADBW(zmm3, zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x40, 0xF6, 0x58, 0xFE]), VPSADBW(zmm3, zmm26, zword[r8 - 128]).encode())
class TestVMPSADBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x42, 0xCB, 0x02]), VMPSADBW(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x42, 0x4C, 0xC2, 0xB3, 0x02]), VMPSADBW(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x42, 0xD4, 0x02]), VMPSADBW(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x42, 0x54, 0xD9, 0xBE, 0x02]), VMPSADBW(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVDBPSADBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x8A, 0x42, 0xF3, 0x02]), VDBPSADBW(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x42, 0x72, 0xF8, 0x02]), VDBPSADBW(xmm30(k2.z), xmm4, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x42, 0xDC, 0x02]), VDBPSADBW(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x42, 0x59, 0xFC, 0x02]), VDBPSADBW(ymm19(k5.z), ymm5, hword[r9 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x42, 0xC9, 0x02]), VDBPSADBW(zmm9(k6.z), zmm26, zmm9, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x42, 0x48, 0xFE, 0x02]), VDBPSADBW(zmm9(k6.z), zmm26, zword[r8 - 128], 2).encode())
class TestVPHMINPOSUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x41, 0xCE]), VPHMINPOSUW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x41, 0x4C, 0xC2, 0xB3]), VPHMINPOSUW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPCMPEQB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB1, 0x5D, 0x0E, 0x74, 0xE3]), VPCMPEQB(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x5D, 0x0E, 0x74, 0x62, 0xF8]), VPCMPEQB(k4(k6), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x55, 0x2E, 0x74, 0xE4]), VPCMPEQB(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x55, 0x2E, 0x74, 0x61, 0xFC]), VPCMPEQB(k4(k6), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x74, 0xE1]), VPCMPEQB(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x74, 0x60, 0xFE]), VPCMPEQB(k4(k6), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x74, 0xCB]), VPCMPEQB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x74, 0x4C, 0xC2, 0xB3]), VPCMPEQB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x74, 0xD4]), VPCMPEQB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x74, 0x54, 0xD9, 0xBE]), VPCMPEQB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPCMPEQW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB1, 0x5D, 0x0E, 0x75, 0xE3]), VPCMPEQW(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x5D, 0x0E, 0x75, 0x62, 0xF8]), VPCMPEQW(k4(k6), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x55, 0x2E, 0x75, 0xE4]), VPCMPEQW(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x55, 0x2E, 0x75, 0x61, 0xFC]), VPCMPEQW(k4(k6), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x75, 0xE1]), VPCMPEQW(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x75, 0x60, 0xFE]), VPCMPEQW(k4(k6), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x75, 0xCB]), VPCMPEQW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x75, 0x4C, 0xC2, 0xB3]), VPCMPEQW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x75, 0xD4]), VPCMPEQW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x75, 0x54, 0xD9, 0xBE]), VPCMPEQW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPCMPEQD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x5D, 0x0E, 0x76, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPCMPEQD(k4(k6), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x5D, 0x0E, 0x76, 0xE3]), VPCMPEQD(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x55, 0x2E, 0x76, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCMPEQD(k4(k6), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x55, 0x2E, 0x76, 0xE4]), VPCMPEQD(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x76, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCMPEQD(k4(k6), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x76, 0xE1]), VPCMPEQD(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x76, 0xCB]), VPCMPEQD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x76, 0x4C, 0xC2, 0xB3]), VPCMPEQD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x76, 0xD4]), VPCMPEQD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x76, 0x54, 0xD9, 0xBE]), VPCMPEQD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPCMPEQQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0xDD, 0x0E, 0x29, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPCMPEQQ(k4(k6), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xDD, 0x0E, 0x29, 0xE3]), VPCMPEQQ(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xD5, 0x2E, 0x29, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCMPEQQ(k4(k6), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xD5, 0x2E, 0x29, 0xE4]), VPCMPEQQ(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAD, 0x46, 0x29, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCMPEQQ(k4(k6), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAD, 0x46, 0x29, 0xE1]), VPCMPEQQ(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x29, 0xCB]), VPCMPEQQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x29, 0x4C, 0xC2, 0xB3]), VPCMPEQQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x29, 0xD4]), VPCMPEQQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x29, 0x54, 0xD9, 0xBE]), VPCMPEQQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPCMPGTB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB1, 0x5D, 0x0E, 0x64, 0xE3]), VPCMPGTB(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x5D, 0x0E, 0x64, 0x62, 0xF8]), VPCMPGTB(k4(k6), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x55, 0x2E, 0x64, 0xE4]), VPCMPGTB(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x55, 0x2E, 0x64, 0x61, 0xFC]), VPCMPGTB(k4(k6), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x64, 0xE1]), VPCMPGTB(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x64, 0x60, 0xFE]), VPCMPGTB(k4(k6), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x64, 0xCB]), VPCMPGTB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x64, 0x4C, 0xC2, 0xB3]), VPCMPGTB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x64, 0xD4]), VPCMPGTB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x64, 0x54, 0xD9, 0xBE]), VPCMPGTB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPCMPGTW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB1, 0x5D, 0x0E, 0x65, 0xE3]), VPCMPGTW(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x5D, 0x0E, 0x65, 0x62, 0xF8]), VPCMPGTW(k4(k6), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x55, 0x2E, 0x65, 0xE4]), VPCMPGTW(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x55, 0x2E, 0x65, 0x61, 0xFC]), VPCMPGTW(k4(k6), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x65, 0xE1]), VPCMPGTW(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x65, 0x60, 0xFE]), VPCMPGTW(k4(k6), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x65, 0xCB]), VPCMPGTW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x65, 0x4C, 0xC2, 0xB3]), VPCMPGTW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x65, 0xD4]), VPCMPGTW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x65, 0x54, 0xD9, 0xBE]), VPCMPGTW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPCMPGTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x5D, 0x0E, 0x66, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPCMPGTD(k4(k6), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x5D, 0x0E, 0x66, 0xE3]), VPCMPGTD(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x55, 0x2E, 0x66, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCMPGTD(k4(k6), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xB1, 0x55, 0x2E, 0x66, 0xE4]), VPCMPGTD(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x66, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCMPGTD(k4(k6), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x2D, 0x46, 0x66, 0xE1]), VPCMPGTD(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x66, 0xCB]), VPCMPGTD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x66, 0x4C, 0xC2, 0xB3]), VPCMPGTD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x66, 0xD4]), VPCMPGTD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x66, 0x54, 0xD9, 0xBE]), VPCMPGTD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPCMPGTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0xDD, 0x0E, 0x37, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPCMPGTQ(k4(k6), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xDD, 0x0E, 0x37, 0xE3]), VPCMPGTQ(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xD5, 0x2E, 0x37, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCMPGTQ(k4(k6), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xD5, 0x2E, 0x37, 0xE4]), VPCMPGTQ(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAD, 0x46, 0x37, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPCMPGTQ(k4(k6), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAD, 0x46, 0x37, 0xE1]), VPCMPGTQ(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x37, 0xCB]), VPCMPGTQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x37, 0x4C, 0xC2, 0xB3]), VPCMPGTQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x37, 0xD4]), VPCMPGTQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x37, 0x54, 0xD9, 0xBE]), VPCMPGTQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPCMPB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB3, 0x5D, 0x0E, 0x3F, 0xE3, 0x02]), VPCMPB(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x5D, 0x0E, 0x3F, 0x62, 0xF8, 0x02]), VPCMPB(k4(k6), xmm4, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0x55, 0x2E, 0x3F, 0xE4, 0x02]), VPCMPB(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x55, 0x2E, 0x3F, 0x61, 0xFC, 0x02]), VPCMPB(k4(k6), ymm5, hword[r9 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x2D, 0x46, 0x3F, 0xE1, 0x02]), VPCMPB(k4(k6), zmm26, zmm9, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x2D, 0x46, 0x3F, 0x60, 0xFE, 0x02]), VPCMPB(k4(k6), zmm26, zword[r8 - 128], 2).encode())
class TestVPCMPW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB3, 0xDD, 0x0E, 0x3F, 0xE3, 0x02]), VPCMPW(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xDD, 0x0E, 0x3F, 0x62, 0xF8, 0x02]), VPCMPW(k4(k6), xmm4, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0xD5, 0x2E, 0x3F, 0xE4, 0x02]), VPCMPW(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xD5, 0x2E, 0x3F, 0x61, 0xFC, 0x02]), VPCMPW(k4(k6), ymm5, hword[r9 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xAD, 0x46, 0x3F, 0xE1, 0x02]), VPCMPW(k4(k6), zmm26, zmm9, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xAD, 0x46, 0x3F, 0x60, 0xFE, 0x02]), VPCMPW(k4(k6), zmm26, zword[r8 - 128], 2).encode())
class TestVPCMPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD3, 0x5D, 0x0E, 0x1F, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPD(k4(k6), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0x5D, 0x0E, 0x1F, 0xE3, 0x02]), VPCMPD(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x55, 0x2E, 0x1F, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPD(k4(k6), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0x55, 0x2E, 0x1F, 0xE4, 0x02]), VPCMPD(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x2D, 0x46, 0x1F, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPD(k4(k6), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x2D, 0x46, 0x1F, 0xE1, 0x02]), VPCMPD(k4(k6), zmm26, zmm9, 2).encode())
class TestVPCMPQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD3, 0xDD, 0x0E, 0x1F, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPQ(k4(k6), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0xDD, 0x0E, 0x1F, 0xE3, 0x02]), VPCMPQ(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xD5, 0x2E, 0x1F, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPQ(k4(k6), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0xD5, 0x2E, 0x1F, 0xE4, 0x02]), VPCMPQ(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xAD, 0x46, 0x1F, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPQ(k4(k6), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xAD, 0x46, 0x1F, 0xE1, 0x02]), VPCMPQ(k4(k6), zmm26, zmm9, 2).encode())
class TestVPCMPUB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB3, 0x5D, 0x0E, 0x3E, 0xE3, 0x02]), VPCMPUB(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x5D, 0x0E, 0x3E, 0x62, 0xF8, 0x02]), VPCMPUB(k4(k6), xmm4, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0x55, 0x2E, 0x3E, 0xE4, 0x02]), VPCMPUB(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x55, 0x2E, 0x3E, 0x61, 0xFC, 0x02]), VPCMPUB(k4(k6), ymm5, hword[r9 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x2D, 0x46, 0x3E, 0xE1, 0x02]), VPCMPUB(k4(k6), zmm26, zmm9, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x2D, 0x46, 0x3E, 0x60, 0xFE, 0x02]), VPCMPUB(k4(k6), zmm26, zword[r8 - 128], 2).encode())
class TestVPCMPUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB3, 0xDD, 0x0E, 0x3E, 0xE3, 0x02]), VPCMPUW(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xDD, 0x0E, 0x3E, 0x62, 0xF8, 0x02]), VPCMPUW(k4(k6), xmm4, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0xD5, 0x2E, 0x3E, 0xE4, 0x02]), VPCMPUW(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xD5, 0x2E, 0x3E, 0x61, 0xFC, 0x02]), VPCMPUW(k4(k6), ymm5, hword[r9 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xAD, 0x46, 0x3E, 0xE1, 0x02]), VPCMPUW(k4(k6), zmm26, zmm9, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xAD, 0x46, 0x3E, 0x60, 0xFE, 0x02]), VPCMPUW(k4(k6), zmm26, zword[r8 - 128], 2).encode())
class TestVPCMPUD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD3, 0x5D, 0x0E, 0x1E, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPUD(k4(k6), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0x5D, 0x0E, 0x1E, 0xE3, 0x02]), VPCMPUD(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x55, 0x2E, 0x1E, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPUD(k4(k6), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0x55, 0x2E, 0x1E, 0xE4, 0x02]), VPCMPUD(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x2D, 0x46, 0x1E, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPUD(k4(k6), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x2D, 0x46, 0x1E, 0xE1, 0x02]), VPCMPUD(k4(k6), zmm26, zmm9, 2).encode())
class TestVPCMPUQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD3, 0xDD, 0x0E, 0x1E, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPUQ(k4(k6), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0xDD, 0x0E, 0x1E, 0xE3, 0x02]), VPCMPUQ(k4(k6), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xD5, 0x2E, 0x1E, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPUQ(k4(k6), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xB3, 0xD5, 0x2E, 0x1E, 0xE4, 0x02]), VPCMPUQ(k4(k6), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xAD, 0x46, 0x1E, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPCMPUQ(k4(k6), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xAD, 0x46, 0x1E, 0xE1, 0x02]), VPCMPUQ(k4(k6), zmm26, zmm9, 2).encode())
class TestVPABSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x1C, 0xF4]), VPABSB(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x1C, 0xDD]), VPABSB(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0x1C, 0xCA]), VPABSB(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x1C, 0x72, 0x04]), VPABSB(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x1C, 0x59, 0x02]), VPABSB(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x1C, 0x48, 0x01]), VPABSB(zmm9(k6.z), zword[r8 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x1C, 0xCE]), VPABSB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x1C, 0x4C, 0xC2, 0xB3]), VPABSB(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x1C, 0xD7]), VPABSB(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x1C, 0x54, 0xD9, 0xBE]), VPABSB(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVPABSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x1D, 0xF4]), VPABSW(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x1D, 0xDD]), VPABSW(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0x1D, 0xCA]), VPABSW(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x1D, 0x72, 0x04]), VPABSW(xmm30(k2.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x1D, 0x59, 0x02]), VPABSW(ymm19(k5.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x1D, 0x48, 0x01]), VPABSW(zmm9(k6.z), zword[r8 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x1D, 0xCE]), VPABSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x1D, 0x4C, 0xC2, 0xB3]), VPABSW(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x1D, 0xD7]), VPABSW(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x1D, 0x54, 0xD9, 0xBE]), VPABSW(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVPABSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x1E, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPABSD(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x1E, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPABSD(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x1E, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPABSD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x1E, 0xF4]), VPABSD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x1E, 0xDD]), VPABSD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0x1E, 0xCA]), VPABSD(zmm9(k6.z), zmm26).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x1E, 0xCE]), VPABSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x1E, 0x4C, 0xC2, 0xB3]), VPABSD(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x1E, 0xD7]), VPABSD(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x1E, 0x54, 0xD9, 0xBE]), VPABSD(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVPABSQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xFD, 0x8A, 0x1F, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPABSQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x1F, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPABSQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x1F, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPABSQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x62, 0xFD, 0x8A, 0x1F, 0xF4]), VPABSQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFD, 0xAD, 0x1F, 0xDD]), VPABSQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0xCE, 0x1F, 0xCA]), VPABSQ(zmm9(k6.z), zmm26).encode())
class TestVPSIGNB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x08, 0xCB]), VPSIGNB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x08, 0x4C, 0xC2, 0xB3]), VPSIGNB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x08, 0xD4]), VPSIGNB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x08, 0x54, 0xD9, 0xBE]), VPSIGNB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSIGNW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x09, 0xCB]), VPSIGNW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x09, 0x4C, 0xC2, 0xB3]), VPSIGNW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x09, 0xD4]), VPSIGNW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x09, 0x54, 0xD9, 0xBE]), VPSIGNW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSIGND(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x0A, 0xCB]), VPSIGND(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x0A, 0x4C, 0xC2, 0xB3]), VPSIGND(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x0A, 0xD4]), VPSIGND(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x0A, 0x54, 0xD9, 0xBE]), VPSIGND(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPAND(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x89, 0xDB, 0xCB]), VPAND(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xDB, 0x4C, 0xC2, 0xB3]), VPAND(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xDB, 0xD4]), VPAND(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xDB, 0x54, 0xD9, 0xBE]), VPAND(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPANDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xDB, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPANDD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xDB, 0xF3]), VPANDD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xDB, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPANDD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xDB, 0xDC]), VPANDD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDB, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPANDD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDB, 0xC9]), VPANDD(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPANDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xDB, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPANDQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xDB, 0xF3]), VPANDQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xDB, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPANDQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xDB, 0xDC]), VPANDQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xDB, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPANDQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xDB, 0xC9]), VPANDQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPANDN(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x89, 0xDF, 0xCB]), VPANDN(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xDF, 0x4C, 0xC2, 0xB3]), VPANDN(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xDF, 0xD4]), VPANDN(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xDF, 0x54, 0xD9, 0xBE]), VPANDN(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPANDND(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xDF, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPANDND(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xDF, 0xF3]), VPANDND(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xDF, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPANDND(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xDF, 0xDC]), VPANDND(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDF, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPANDND(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xDF, 0xC9]), VPANDND(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPANDNQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xDF, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPANDNQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xDF, 0xF3]), VPANDNQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xDF, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPANDNQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xDF, 0xDC]), VPANDNQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xDF, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPANDNQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xDF, 0xC9]), VPANDNQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPOR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x89, 0xEB, 0xCB]), VPOR(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xEB, 0x4C, 0xC2, 0xB3]), VPOR(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xEB, 0xD4]), VPOR(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xEB, 0x54, 0xD9, 0xBE]), VPOR(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPORD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xEB, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPORD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xEB, 0xF3]), VPORD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xEB, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPORD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xEB, 0xDC]), VPORD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEB, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPORD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEB, 0xC9]), VPORD(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPORQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xEB, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPORQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xEB, 0xF3]), VPORQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xEB, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPORQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xEB, 0xDC]), VPORQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xEB, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPORQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xEB, 0xC9]), VPORQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPXOR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x89, 0xEF, 0xCB]), VPXOR(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0xEF, 0x4C, 0xC2, 0xB3]), VPXOR(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0xEF, 0xD4]), VPXOR(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0xEF, 0x54, 0xD9, 0xBE]), VPXOR(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPXORD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0xEF, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPXORD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0xEF, 0xF3]), VPXORD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0xEF, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPXORD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0xEF, 0xDC]), VPXORD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEF, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPXORD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0xEF, 0xC9]), VPXORD(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPXORQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0xEF, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPXORQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0xEF, 0xF3]), VPXORQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0xEF, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPXORQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0xEF, 0xDC]), VPXORQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xEF, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPXORQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0xEF, 0xC9]), VPXORQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPTERNLOGD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x25, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPTERNLOGD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x8A, 0x25, 0xF3, 0x02]), VPTERNLOGD(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x25, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPTERNLOGD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x25, 0xDC, 0x02]), VPTERNLOGD(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x25, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPTERNLOGD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x25, 0xC9, 0x02]), VPTERNLOGD(zmm9(k6.z), zmm26, zmm9, 2).encode())
class TestVPTERNLOGQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xDD, 0x8A, 0x25, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPTERNLOGQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0xDD, 0x8A, 0x25, 0xF3, 0x02]), VPTERNLOGQ(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xD5, 0xAD, 0x25, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPTERNLOGQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0xD5, 0xAD, 0x25, 0xDC, 0x02]), VPTERNLOGQ(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x25, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPTERNLOGQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x25, 0xC9, 0x02]), VPTERNLOGQ(zmm9(k6.z), zmm26, zmm9, 2).encode())
class TestVPBLENDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x0E, 0xCB, 0x02]), VPBLENDW(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x0E, 0x4C, 0xC2, 0xB3, 0x02]), VPBLENDW(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x0E, 0xD4, 0x02]), VPBLENDW(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x0E, 0x54, 0xD9, 0xBE, 0x02]), VPBLENDW(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPBLENDVB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x4C, 0xCB, 0x90]), VPBLENDVB(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x4C, 0x4C, 0xC2, 0xB3, 0x90]), VPBLENDVB(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x4C, 0xD4, 0xA0]), VPBLENDVB(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x4C, 0x54, 0xD9, 0xBE, 0xA0]), VPBLENDVB(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVPBLENDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x02, 0xCB, 0x02]), VPBLENDD(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x02, 0x4C, 0xC2, 0xB3, 0x02]), VPBLENDD(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x02, 0xD4, 0x02]), VPBLENDD(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x02, 0x54, 0xD9, 0xBE, 0x02]), VPBLENDD(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPBLENDMB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x66, 0xF3]), VPBLENDMB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x66, 0x72, 0xF8]), VPBLENDMB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x66, 0xDC]), VPBLENDMB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x66, 0x59, 0xFC]), VPBLENDMB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x66, 0xC9]), VPBLENDMB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x66, 0x48, 0xFE]), VPBLENDMB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPBLENDMW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x66, 0xF3]), VPBLENDMW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x66, 0x72, 0xF8]), VPBLENDMW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x66, 0xDC]), VPBLENDMW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x66, 0x59, 0xFC]), VPBLENDMW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x66, 0xC9]), VPBLENDMW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x66, 0x48, 0xFE]), VPBLENDMW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPBLENDMD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x64, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPBLENDMD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x64, 0xF3]), VPBLENDMD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x64, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPBLENDMD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x64, 0xDC]), VPBLENDMD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x64, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPBLENDMD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x64, 0xC9]), VPBLENDMD(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPBLENDMQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x64, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPBLENDMQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x64, 0xF3]), VPBLENDMQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x64, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPBLENDMQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x64, 0xDC]), VPBLENDMQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x64, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPBLENDMQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x64, 0xC9]), VPBLENDMQ(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPUNPCKLBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0x60, 0xF3]), VPUNPCKLBW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0x60, 0x72, 0xF8]), VPUNPCKLBW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0x60, 0xDC]), VPUNPCKLBW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0x60, 0x59, 0xFC]), VPUNPCKLBW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x60, 0xC9]), VPUNPCKLBW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x60, 0x48, 0xFE]), VPUNPCKLBW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x60, 0xCB]), VPUNPCKLBW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x60, 0x4C, 0xC2, 0xB3]), VPUNPCKLBW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x60, 0xD4]), VPUNPCKLBW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x60, 0x54, 0xD9, 0xBE]), VPUNPCKLBW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPUNPCKLWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0x61, 0xF3]), VPUNPCKLWD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0x61, 0x72, 0xF8]), VPUNPCKLWD(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0x61, 0xDC]), VPUNPCKLWD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0x61, 0x59, 0xFC]), VPUNPCKLWD(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x61, 0xC9]), VPUNPCKLWD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x61, 0x48, 0xFE]), VPUNPCKLWD(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x61, 0xCB]), VPUNPCKLWD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x61, 0x4C, 0xC2, 0xB3]), VPUNPCKLWD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x61, 0xD4]), VPUNPCKLWD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x61, 0x54, 0xD9, 0xBE]), VPUNPCKLWD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPUNPCKLDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0x62, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPUNPCKLDQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0x62, 0xF3]), VPUNPCKLDQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0x62, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPUNPCKLDQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0x62, 0xDC]), VPUNPCKLDQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x62, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPUNPCKLDQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x62, 0xC9]), VPUNPCKLDQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x62, 0xCB]), VPUNPCKLDQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x62, 0x4C, 0xC2, 0xB3]), VPUNPCKLDQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x62, 0xD4]), VPUNPCKLDQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x62, 0x54, 0xD9, 0xBE]), VPUNPCKLDQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPUNPCKLQDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x6C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPUNPCKLQDQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x6C, 0xF3]), VPUNPCKLQDQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x6C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPUNPCKLQDQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x6C, 0xDC]), VPUNPCKLQDQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x6C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPUNPCKLQDQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x6C, 0xC9]), VPUNPCKLQDQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x6C, 0xCB]), VPUNPCKLQDQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x6C, 0x4C, 0xC2, 0xB3]), VPUNPCKLQDQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x6C, 0xD4]), VPUNPCKLQDQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x6C, 0x54, 0xD9, 0xBE]), VPUNPCKLQDQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPUNPCKHBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0x68, 0xF3]), VPUNPCKHBW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0x68, 0x72, 0xF8]), VPUNPCKHBW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0x68, 0xDC]), VPUNPCKHBW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0x68, 0x59, 0xFC]), VPUNPCKHBW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x68, 0xC9]), VPUNPCKHBW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x68, 0x48, 0xFE]), VPUNPCKHBW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x68, 0xCB]), VPUNPCKHBW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x68, 0x4C, 0xC2, 0xB3]), VPUNPCKHBW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x68, 0xD4]), VPUNPCKHBW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x68, 0x54, 0xD9, 0xBE]), VPUNPCKHBW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPUNPCKHWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0x69, 0xF3]), VPUNPCKHWD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0x69, 0x72, 0xF8]), VPUNPCKHWD(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0x69, 0xDC]), VPUNPCKHWD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0x69, 0x59, 0xFC]), VPUNPCKHWD(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x69, 0xC9]), VPUNPCKHWD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x69, 0x48, 0xFE]), VPUNPCKHWD(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x69, 0xCB]), VPUNPCKHWD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x69, 0x4C, 0xC2, 0xB3]), VPUNPCKHWD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x69, 0xD4]), VPUNPCKHWD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x69, 0x54, 0xD9, 0xBE]), VPUNPCKHWD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPUNPCKHDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0x6A, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPUNPCKHDQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0x6A, 0xF3]), VPUNPCKHDQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0x6A, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPUNPCKHDQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0x6A, 0xDC]), VPUNPCKHDQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x6A, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPUNPCKHDQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x6A, 0xC9]), VPUNPCKHDQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x6A, 0xCB]), VPUNPCKHDQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x6A, 0x4C, 0xC2, 0xB3]), VPUNPCKHDQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x6A, 0xD4]), VPUNPCKHDQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x6A, 0x54, 0xD9, 0xBE]), VPUNPCKHDQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPUNPCKHQDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDD, 0x8A, 0x6D, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPUNPCKHQDQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDD, 0x8A, 0x6D, 0xF3]), VPUNPCKHQDQ(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xD5, 0xAD, 0x6D, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPUNPCKHQDQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0xD5, 0xAD, 0x6D, 0xDC]), VPUNPCKHQDQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x6D, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPUNPCKHQDQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xAD, 0xC6, 0x6D, 0xC9]), VPUNPCKHQDQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x6D, 0xCB]), VPUNPCKHQDQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x6D, 0x4C, 0xC2, 0xB3]), VPUNPCKHQDQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x6D, 0xD4]), VPUNPCKHQDQ(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x6D, 0x54, 0xD9, 0xBE]), VPUNPCKHQDQ(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPACKSSWB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0x63, 0xF3]), VPACKSSWB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0x63, 0x72, 0xF8]), VPACKSSWB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0x63, 0xDC]), VPACKSSWB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0x63, 0x59, 0xFC]), VPACKSSWB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x63, 0xC9]), VPACKSSWB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x63, 0x48, 0xFE]), VPACKSSWB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x63, 0xCB]), VPACKSSWB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x63, 0x4C, 0xC2, 0xB3]), VPACKSSWB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x63, 0xD4]), VPACKSSWB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x63, 0x54, 0xD9, 0xBE]), VPACKSSWB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPACKSSDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0x6B, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPACKSSDW(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0x6B, 0xF3]), VPACKSSDW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0x6B, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPACKSSDW(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0x6B, 0xDC]), VPACKSSDW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x6B, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPACKSSDW(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x6B, 0xC9]), VPACKSSDW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x6B, 0xCB]), VPACKSSDW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x6B, 0x4C, 0xC2, 0xB3]), VPACKSSDW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x6B, 0xD4]), VPACKSSDW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x6B, 0x54, 0xD9, 0xBE]), VPACKSSDW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPACKUSWB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x21, 0x5D, 0x8A, 0x67, 0xF3]), VPACKUSWB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x5D, 0x8A, 0x67, 0x72, 0xF8]), VPACKUSWB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA1, 0x55, 0xAD, 0x67, 0xDC]), VPACKUSWB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x55, 0xAD, 0x67, 0x59, 0xFC]), VPACKUSWB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x67, 0xC9]), VPACKUSWB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x2D, 0xC6, 0x67, 0x48, 0xFE]), VPACKUSWB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x89, 0x67, 0xCB]), VPACKUSWB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x09, 0x67, 0x4C, 0xC2, 0xB3]), VPACKUSWB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC5, 0x85, 0x67, 0xD4]), VPACKUSWB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x05, 0x67, 0x54, 0xD9, 0xBE]), VPACKUSWB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPACKUSDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x2B, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPACKUSDW(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x2B, 0xF3]), VPACKUSDW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x2B, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPACKUSDW(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x2B, 0xDC]), VPACKUSDW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x2B, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPACKUSDW(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x2B, 0xC9]), VPACKUSDW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x2B, 0xCB]), VPACKUSDW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x2B, 0x4C, 0xC2, 0xB3]), VPACKUSDW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x2B, 0xD4]), VPACKUSDW(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x2B, 0x54, 0xD9, 0xBE]), VPACKUSDW(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSHUFB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x00, 0xF3]), VPSHUFB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x00, 0x72, 0xF8]), VPSHUFB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x00, 0xDC]), VPSHUFB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x00, 0x59, 0xFC]), VPSHUFB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x00, 0xC9]), VPSHUFB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x00, 0x48, 0xFE]), VPSHUFB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x00, 0xCB]), VPSHUFB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x00, 0x4C, 0xC2, 0xB3]), VPSHUFB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x00, 0xD4]), VPSHUFB(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x00, 0x54, 0xD9, 0xBE]), VPSHUFB(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPSHUFLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x61, 0x7F, 0x8A, 0x70, 0xF4, 0x02]), VPSHUFLW(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7F, 0xAD, 0x70, 0xDD, 0x02]), VPSHUFLW(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7F, 0xCE, 0x70, 0xCA, 0x02]), VPSHUFLW(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7F, 0x8A, 0x70, 0x72, 0x04, 0x02]), VPSHUFLW(xmm30(k2.z), oword[r10 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7F, 0xAD, 0x70, 0x59, 0x02, 0x02]), VPSHUFLW(ymm19(k5.z), hword[r9 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7F, 0xCE, 0x70, 0x48, 0x01, 0x02]), VPSHUFLW(zmm9(k6.z), zword[r8 + 64], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x70, 0xCE, 0x02]), VPSHUFLW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x70, 0x4C, 0xC2, 0xB3, 0x02]), VPSHUFLW(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7F, 0x70, 0xD7, 0x02]), VPSHUFLW(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7F, 0x70, 0x54, 0xD9, 0xBE, 0x02]), VPSHUFLW(ymm2, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPSHUFHW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x61, 0x7E, 0x8A, 0x70, 0xF4, 0x02]), VPSHUFHW(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7E, 0xAD, 0x70, 0xDD, 0x02]), VPSHUFHW(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7E, 0xCE, 0x70, 0xCA, 0x02]), VPSHUFHW(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x41, 0x7E, 0x8A, 0x70, 0x72, 0x04, 0x02]), VPSHUFHW(xmm30(k2.z), oword[r10 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7E, 0xAD, 0x70, 0x59, 0x02, 0x02]), VPSHUFHW(ymm19(k5.z), hword[r9 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7E, 0xCE, 0x70, 0x48, 0x01, 0x02]), VPSHUFHW(zmm9(k6.z), zword[r8 + 64], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x70, 0xCE, 0x02]), VPSHUFHW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x70, 0x4C, 0xC2, 0xB3, 0x02]), VPSHUFHW(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0x70, 0xD7, 0x02]), VPSHUFHW(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0x70, 0x54, 0xD9, 0xBE, 0x02]), VPSHUFHW(ymm2, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPSHUFD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7D, 0x8A, 0x70, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VPSHUFD(xmm30(k2.z), oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7D, 0xAD, 0x70, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSHUFD(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7D, 0xCE, 0x70, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPSHUFD(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7D, 0x8A, 0x70, 0xF4, 0x02]), VPSHUFD(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7D, 0xAD, 0x70, 0xDD, 0x02]), VPSHUFD(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7D, 0xCE, 0x70, 0xCA, 0x02]), VPSHUFD(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x70, 0xCE, 0x02]), VPSHUFD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x70, 0x4C, 0xC2, 0xB3, 0x02]), VPSHUFD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x70, 0xD7, 0x02]), VPSHUFD(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x70, 0x54, 0xD9, 0xBE, 0x02]), VPSHUFD(ymm2, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPERMB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x8D, 0xF3]), VPERMB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x8D, 0x72, 0xF8]), VPERMB(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x8D, 0xDC]), VPERMB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x8D, 0x59, 0xFC]), VPERMB(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x8D, 0xC9]), VPERMB(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x8D, 0x48, 0xFE]), VPERMB(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPERMW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x8D, 0xF3]), VPERMW(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x8D, 0x72, 0xF8]), VPERMW(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x8D, 0xDC]), VPERMW(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x8D, 0x59, 0xFC]), VPERMW(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x8D, 0xC9]), VPERMW(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x8D, 0x48, 0xFE]), VPERMW(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPERMD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x36, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x36, 0xDC]), VPERMD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x36, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x36, 0xC9]), VPERMD(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x36, 0xD4]), VPERMD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x36, 0x54, 0xD9, 0xBE]), VPERMD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
class TestVPERMQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC3, 0xFD, 0xAD, 0x00, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPERMQ(ymm19(k5.z), hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xFD, 0xCE, 0x00, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VPERMQ(zmm9(k6.z), zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x36, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xE3, 0xFD, 0xAD, 0x00, 0xDD, 0x02]), VPERMQ(ymm19(k5.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x36, 0xDC]), VPERMQ(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x36, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x13, 0xFD, 0xCE, 0x00, 0xCA, 0x02]), VPERMQ(zmm9(k6.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x36, 0xC9]), VPERMQ(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0xFD, 0x00, 0xD7, 0x02]), VPERMQ(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0xFD, 0x00, 0x54, 0xD9, 0xBE, 0x02]), VPERMQ(ymm2, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPERMT2B(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x7D, 0xF3]), VPERMT2B(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x7D, 0x72, 0xF8]), VPERMT2B(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x7D, 0xDC]), VPERMT2B(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x7D, 0x59, 0xFC]), VPERMT2B(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x7D, 0xC9]), VPERMT2B(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x7D, 0x48, 0xFE]), VPERMT2B(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPERMT2W(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x7D, 0xF3]), VPERMT2W(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x7D, 0x72, 0xF8]), VPERMT2W(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x7D, 0xDC]), VPERMT2W(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x7D, 0x59, 0xFC]), VPERMT2W(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x7D, 0xC9]), VPERMT2W(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x7D, 0x48, 0xFE]), VPERMT2W(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPERMT2D(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x7E, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMT2D(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x7E, 0xF3]), VPERMT2D(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x7E, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMT2D(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x7E, 0xDC]), VPERMT2D(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x7E, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMT2D(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x7E, 0xC9]), VPERMT2D(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPERMT2Q(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x7E, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMT2Q(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x7E, 0xF3]), VPERMT2Q(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x7E, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMT2Q(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x7E, 0xDC]), VPERMT2Q(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x7E, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMT2Q(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x7E, 0xC9]), VPERMT2Q(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPERMI2B(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x75, 0xF3]), VPERMI2B(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x75, 0x72, 0xF8]), VPERMI2B(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x75, 0xDC]), VPERMI2B(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x75, 0x59, 0xFC]), VPERMI2B(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x75, 0xC9]), VPERMI2B(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x75, 0x48, 0xFE]), VPERMI2B(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPERMI2W(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x75, 0xF3]), VPERMI2W(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x75, 0x72, 0xF8]), VPERMI2W(xmm30(k2.z), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x75, 0xDC]), VPERMI2W(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x75, 0x59, 0xFC]), VPERMI2W(ymm19(k5.z), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x75, 0xC9]), VPERMI2W(zmm9(k6.z), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x75, 0x48, 0xFE]), VPERMI2W(zmm9(k6.z), zmm26, zword[r8 - 128]).encode())
class TestVPERMI2D(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x76, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMI2D(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x76, 0xF3]), VPERMI2D(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x76, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMI2D(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x76, 0xDC]), VPERMI2D(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x76, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMI2D(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x76, 0xC9]), VPERMI2D(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPERMI2Q(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x76, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPERMI2Q(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x76, 0xF3]), VPERMI2Q(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x76, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMI2Q(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x76, 0xDC]), VPERMI2Q(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x76, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPERMI2Q(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x76, 0xC9]), VPERMI2Q(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPSLLDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x73, 0xFE, 0x02]), VPSLLDQ(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7D, 0x00, 0x73, 0xFC, 0x02]), VPSLLDQ(xmm16, xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x7D, 0x00, 0x73, 0x7A, 0x04, 0x02]), VPSLLDQ(xmm16, oword[r10 + 64], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x73, 0xFF, 0x02]), VPSLLDQ(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x75, 0x20, 0x73, 0xFD, 0x02]), VPSLLDQ(ymm17, ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x75, 0x20, 0x73, 0x79, 0x02, 0x02]), VPSLLDQ(ymm17, hword[r9 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x65, 0x48, 0x73, 0xFA, 0x02]), VPSLLDQ(zmm3, zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0x48, 0x73, 0x78, 0x01, 0x02]), VPSLLDQ(zmm3, zword[r8 + 64], 2).encode())
class TestVPSRLDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x71, 0x73, 0xDE, 0x02]), VPSRLDQ(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7D, 0x00, 0x73, 0xDC, 0x02]), VPSRLDQ(xmm16, xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x7D, 0x00, 0x73, 0x5A, 0x04, 0x02]), VPSRLDQ(xmm16, oword[r10 + 64], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x6D, 0x73, 0xDF, 0x02]), VPSRLDQ(ymm2, ymm15, 2).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x75, 0x20, 0x73, 0xDD, 0x02]), VPSRLDQ(ymm17, ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x75, 0x20, 0x73, 0x59, 0x02, 0x02]), VPSRLDQ(ymm17, hword[r9 + 64], 2).encode())
self.assertEqual(bytearray([0x62, 0x91, 0x65, 0x48, 0x73, 0xDA, 0x02]), VPSRLDQ(zmm3, zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0x65, 0x48, 0x73, 0x58, 0x01, 0x02]), VPSRLDQ(zmm3, zword[r8 + 64], 2).encode())
class TestVPALIGNR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x8A, 0x0F, 0xF3, 0x02]), VPALIGNR(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x0F, 0x72, 0xF8, 0x02]), VPALIGNR(xmm30(k2.z), xmm4, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x0F, 0xDC, 0x02]), VPALIGNR(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x0F, 0x59, 0xFC, 0x02]), VPALIGNR(ymm19(k5.z), ymm5, hword[r9 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x0F, 0xC9, 0x02]), VPALIGNR(zmm9(k6.z), zmm26, zmm9, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x0F, 0x48, 0xFE, 0x02]), VPALIGNR(zmm9(k6.z), zmm26, zword[r8 - 128], 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x0F, 0xCB, 0x02]), VPALIGNR(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x0F, 0x4C, 0xC2, 0xB3, 0x02]), VPALIGNR(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x0F, 0xD4, 0x02]), VPALIGNR(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x0F, 0x54, 0xD9, 0xBE, 0x02]), VPALIGNR(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVALIGND(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0x5D, 0x8A, 0x03, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VALIGND(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0x5D, 0x8A, 0x03, 0xF3, 0x02]), VALIGND(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x03, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VALIGND(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x03, 0xDC, 0x02]), VALIGND(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x03, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VALIGND(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x03, 0xC9, 0x02]), VALIGND(zmm9(k6.z), zmm26, zmm9, 2).encode())
class TestVALIGNQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x43, 0xDD, 0x8A, 0x03, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF, 0x02]), VALIGNQ(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0xDD, 0x8A, 0x03, 0xF3, 0x02]), VALIGNQ(xmm30(k2.z), xmm4, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xD5, 0xAD, 0x03, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VALIGNQ(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0xD5, 0xAD, 0x03, 0xDC, 0x02]), VALIGNQ(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x03, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VALIGNQ(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x03, 0xC9, 0x02]), VALIGNQ(zmm9(k6.z), zmm26, zmm9, 2).encode())
class TestVPMULTISHIFTQB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x83, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPMULTISHIFTQB(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x83, 0xF3]), VPMULTISHIFTQB(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x83, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULTISHIFTQB(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x83, 0xDC]), VPMULTISHIFTQB(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x83, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPMULTISHIFTQB(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x83, 0xC9]), VPMULTISHIFTQB(zmm9(k6.z), zmm26, zmm9).encode())
class TestVPOPCNTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x55, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPOPCNTD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x12, 0x7D, 0xCE, 0x55, 0xCA]), VPOPCNTD(zmm9(k6.z), zmm26).encode())
class TestVPOPCNTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x55, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPOPCNTQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x12, 0xFD, 0xCE, 0x55, 0xCA]), VPOPCNTQ(zmm9(k6.z), zmm26).encode())
class TestVPCMPESTRI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x61, 0xCE, 0x02]), VPCMPESTRI(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x61, 0x4C, 0xC2, 0xB3, 0x02]), VPCMPESTRI(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCMPESTRM(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x60, 0xCE, 0x02]), VPCMPESTRM(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x60, 0x4C, 0xC2, 0xB3, 0x02]), VPCMPESTRM(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCMPISTRI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x63, 0xCE, 0x02]), VPCMPISTRI(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x63, 0x4C, 0xC2, 0xB3, 0x02]), VPCMPISTRI(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCMPISTRM(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x62, 0xCE, 0x02]), VPCMPISTRM(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x62, 0x4C, 0xC2, 0xB3, 0x02]), VPCMPISTRM(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestVCVTSS2SI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x2D, 0xEE]), VCVTSS2SI(ebp, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x2D, 0x6C, 0xCC, 0x9D]), VCVTSS2SI(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x2D, 0x6C, 0x24, 0x40]), VCVTSS2SI(ebp, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFA, 0x2D, 0xCE]), VCVTSS2SI(rcx, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFA, 0x2D, 0x4C, 0xCC, 0x9D]), VCVTSS2SI(rcx, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFA, 0x2D, 0x4C, 0x24, 0x40]), VCVTSS2SI(rcx, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7E, 0x18, 0x2D, 0xEC]), VCVTSS2SI(ebp, xmm4, {rn_sae}).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xFE, 0x18, 0x2D, 0xCC]), VCVTSS2SI(rcx, xmm4, {rn_sae}).encode())
class TestVCVTSS2USI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x7E, 0x08, 0x79, 0x6C, 0x24, 0x10]), VCVTSS2USI(ebp, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xFE, 0x08, 0x79, 0x4C, 0x24, 0x10]), VCVTSS2USI(rcx, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7E, 0x18, 0x79, 0xEC]), VCVTSS2USI(ebp, xmm4, {rn_sae}).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xFE, 0x18, 0x79, 0xCC]), VCVTSS2USI(rcx, xmm4, {rn_sae}).encode())
class TestVCVTTSS2SI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x2C, 0xEE]), VCVTTSS2SI(ebp, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x2C, 0x6C, 0xCC, 0x9D]), VCVTTSS2SI(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x2C, 0x6C, 0x24, 0x40]), VCVTTSS2SI(ebp, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFA, 0x2C, 0xCE]), VCVTTSS2SI(rcx, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFA, 0x2C, 0x4C, 0xCC, 0x9D]), VCVTTSS2SI(rcx, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFA, 0x2C, 0x4C, 0x24, 0x40]), VCVTTSS2SI(rcx, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7E, 0x18, 0x2C, 0xEC]), VCVTTSS2SI(ebp, xmm4, {sae}).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xFE, 0x18, 0x2C, 0xCC]), VCVTTSS2SI(rcx, xmm4, {sae}).encode())
class TestVCVTTSS2USI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x7E, 0x08, 0x78, 0x6C, 0x24, 0x10]), VCVTTSS2USI(ebp, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xFE, 0x08, 0x78, 0x4C, 0x24, 0x10]), VCVTTSS2USI(rcx, dword[r12 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7E, 0x18, 0x78, 0xEC]), VCVTTSS2USI(ebp, xmm4, {sae}).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xFE, 0x18, 0x78, 0xCC]), VCVTTSS2USI(rcx, xmm4, {sae}).encode())
class TestVCVTSI2SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x8A, 0x2A, 0xC8]), VCVTSI2SS(xmm1, xmm14, eax).encode())
self.assertEqual(bytearray([0xC4, 0xE1, 0x8A, 0x2A, 0xC8]), VCVTSI2SS(xmm1, xmm14, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x2A, 0x4C, 0xCC, 0x9D]), VCVTSI2SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x5E, 0x08, 0x2A, 0x44, 0x24, 0xE0]), VCVTSI2SS(xmm16, xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x8A, 0x2A, 0x4C, 0xD3, 0xA8]), VCVTSI2SS(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xDE, 0x08, 0x2A, 0x43, 0xF0]), VCVTSI2SS(xmm16, xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x5E, 0x18, 0x2A, 0xC0]), VCVTSI2SS(xmm16, xmm4, eax, {rn_sae}).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xDE, 0x18, 0x2A, 0xC0]), VCVTSI2SS(xmm16, xmm4, rax, {rn_sae}).encode())
class TestVCVTUSI2SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC1, 0x5E, 0x08, 0x7B, 0x44, 0x24, 0xE0]), VCVTUSI2SS(xmm16, xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xDE, 0x08, 0x7B, 0x43, 0xF0]), VCVTUSI2SS(xmm16, xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x5E, 0x18, 0x7B, 0xC0]), VCVTUSI2SS(xmm16, xmm4, eax, {rn_sae}).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xDE, 0x18, 0x7B, 0xC0]), VCVTUSI2SS(xmm16, xmm4, rax, {rn_sae}).encode())
class TestVCVTSD2SI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x2D, 0xEE]), VCVTSD2SI(ebp, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x2D, 0x6C, 0xD3, 0xA8]), VCVTSD2SI(ebp, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x2D, 0x6B, 0x40]), VCVTSD2SI(ebp, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFB, 0x2D, 0xCE]), VCVTSD2SI(rcx, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFB, 0x2D, 0x4C, 0xD3, 0xA8]), VCVTSD2SI(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFB, 0x2D, 0x4B, 0x40]), VCVTSD2SI(rcx, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7F, 0x18, 0x2D, 0xEC]), VCVTSD2SI(ebp, xmm4, {rn_sae}).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xFF, 0x18, 0x2D, 0xCC]), VCVTSD2SI(rcx, xmm4, {rn_sae}).encode())
class TestVCVTSD2USI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x7F, 0x08, 0x79, 0x6B, 0x08]), VCVTSD2USI(ebp, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xFF, 0x08, 0x79, 0x4B, 0x08]), VCVTSD2USI(rcx, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7F, 0x18, 0x79, 0xEC]), VCVTSD2USI(ebp, xmm4, {rn_sae}).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xFF, 0x18, 0x79, 0xCC]), VCVTSD2USI(rcx, xmm4, {rn_sae}).encode())
class TestVCVTTSD2SI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x2C, 0xEE]), VCVTTSD2SI(ebp, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x2C, 0x6C, 0xD3, 0xA8]), VCVTTSD2SI(ebp, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0x2C, 0x6B, 0x40]), VCVTTSD2SI(ebp, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFB, 0x2C, 0xCE]), VCVTTSD2SI(rcx, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFB, 0x2C, 0x4C, 0xD3, 0xA8]), VCVTTSD2SI(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0xFB, 0x2C, 0x4B, 0x40]), VCVTTSD2SI(rcx, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7F, 0x18, 0x2C, 0xEC]), VCVTTSD2SI(ebp, xmm4, {sae}).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xFF, 0x18, 0x2C, 0xCC]), VCVTTSD2SI(rcx, xmm4, {sae}).encode())
class TestVCVTTSD2USI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD1, 0x7F, 0x08, 0x78, 0x6B, 0x08]), VCVTTSD2USI(ebp, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xD1, 0xFF, 0x08, 0x78, 0x4B, 0x08]), VCVTTSD2USI(rcx, qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0x7F, 0x18, 0x78, 0xEC]), VCVTTSD2USI(ebp, xmm4, {sae}).encode())
self.assertEqual(bytearray([0x62, 0xF1, 0xFF, 0x18, 0x78, 0xCC]), VCVTTSD2USI(rcx, xmm4, {sae}).encode())
class TestVCVTSI2SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0x8B, 0x2A, 0xC8]), VCVTSI2SD(xmm1, xmm14, eax).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x5F, 0x08, 0x2A, 0xC0]), VCVTSI2SD(xmm16, xmm4, eax).encode())
self.assertEqual(bytearray([0xC4, 0xE1, 0x8B, 0x2A, 0xC8]), VCVTSI2SD(xmm1, xmm14, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x2A, 0x4C, 0xCC, 0x9D]), VCVTSI2SD(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x5F, 0x08, 0x2A, 0x44, 0x24, 0xE0]), VCVTSI2SD(xmm16, xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x8B, 0x2A, 0x4C, 0xD3, 0xA8]), VCVTSI2SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xDF, 0x08, 0x2A, 0x43, 0xF0]), VCVTSI2SD(xmm16, xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xDF, 0x18, 0x2A, 0xC0]), VCVTSI2SD(xmm16, xmm4, rax, {rn_sae}).encode())
class TestVCVTUSI2SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE1, 0x5F, 0x08, 0x7B, 0xC0]), VCVTUSI2SD(xmm16, xmm4, eax).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x5F, 0x08, 0x7B, 0x44, 0x24, 0xE0]), VCVTUSI2SD(xmm16, xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xDF, 0x08, 0x7B, 0x43, 0xF0]), VCVTUSI2SD(xmm16, xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xDF, 0x18, 0x7B, 0xC0]), VCVTUSI2SD(xmm16, xmm4, rax, {rn_sae}).encode())
class TestVCVTPS2DQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7D, 0x8A, 0x5B, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPS2DQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7D, 0xAD, 0x5B, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPS2DQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7D, 0xCE, 0x5B, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPS2DQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7D, 0x8A, 0x5B, 0xF4]), VCVTPS2DQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7D, 0xAD, 0x5B, 0xDD]), VCVTPS2DQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x5B, 0xCE]), VCVTPS2DQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x5B, 0x4C, 0xC2, 0xB3]), VCVTPS2DQ(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x5B, 0xD7]), VCVTPS2DQ(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x5B, 0x54, 0xD9, 0xBE]), VCVTPS2DQ(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7D, 0x9E, 0x5B, 0xCA]), VCVTPS2DQ(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVCVTPS2UDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x8A, 0x79, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPS2UDQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7C, 0xAD, 0x79, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPS2UDQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7C, 0xCE, 0x79, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPS2UDQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7C, 0x8A, 0x79, 0xF4]), VCVTPS2UDQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7C, 0xAD, 0x79, 0xDD]), VCVTPS2UDQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7C, 0x9E, 0x79, 0xCA]), VCVTPS2UDQ(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVCVTTPS2DQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7E, 0x8A, 0x5B, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTTPS2DQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7E, 0xAD, 0x5B, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPS2DQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7E, 0xCE, 0x5B, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPS2DQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7E, 0x8A, 0x5B, 0xF4]), VCVTTPS2DQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7E, 0xAD, 0x5B, 0xDD]), VCVTTPS2DQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x5B, 0xCE]), VCVTTPS2DQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0x5B, 0x4C, 0xC2, 0xB3]), VCVTTPS2DQ(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0x5B, 0xD7]), VCVTTPS2DQ(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0x5B, 0x54, 0xD9, 0xBE]), VCVTTPS2DQ(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7E, 0x9E, 0x5B, 0xCA]), VCVTTPS2DQ(zmm9(k6.z), zmm26, {sae}).encode())
class TestVCVTTPS2UDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x8A, 0x78, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTTPS2UDQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7C, 0xAD, 0x78, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPS2UDQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7C, 0xCE, 0x78, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPS2UDQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7C, 0x8A, 0x78, 0xF4]), VCVTTPS2UDQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7C, 0xAD, 0x78, 0xDD]), VCVTTPS2UDQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7C, 0x9E, 0x78, 0xCA]), VCVTTPS2UDQ(zmm9(k6.z), zmm26, {sae}).encode())
class TestVCVTDQ2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x8A, 0x5B, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTDQ2PS(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7C, 0xAD, 0x5B, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTDQ2PS(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7C, 0xCE, 0x5B, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTDQ2PS(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7C, 0x8A, 0x5B, 0xF4]), VCVTDQ2PS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7C, 0xAD, 0x5B, 0xDD]), VCVTDQ2PS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x5B, 0xCE]), VCVTDQ2PS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x5B, 0x4C, 0xC2, 0xB3]), VCVTDQ2PS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x5B, 0xD7]), VCVTDQ2PS(ymm2, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x5B, 0x54, 0xD9, 0xBE]), VCVTDQ2PS(ymm2, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7C, 0x9E, 0x5B, 0xCA]), VCVTDQ2PS(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVCVTUDQ2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7F, 0x8A, 0x7A, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTUDQ2PS(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7F, 0xAD, 0x7A, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTUDQ2PS(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7F, 0xCE, 0x7A, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTUDQ2PS(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7F, 0x8A, 0x7A, 0xF4]), VCVTUDQ2PS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7F, 0xAD, 0x7A, 0xDD]), VCVTUDQ2PS(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0x7F, 0x9E, 0x7A, 0xCA]), VCVTUDQ2PS(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVCVTPS2QQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7D, 0x8A, 0x7B, 0x74, 0xD3, 0xF5]), VCVTPS2QQ(xmm30(k2.z), qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7D, 0xAD, 0x7B, 0x9C, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPS2QQ(ymm19(k5.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7D, 0xCE, 0x7B, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPS2QQ(zmm9(k6.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7D, 0x8A, 0x7B, 0xF4]), VCVTPS2QQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7D, 0xAD, 0x7B, 0xDC]), VCVTPS2QQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x71, 0x7D, 0x9E, 0x7B, 0xCD]), VCVTPS2QQ(zmm9(k6.z), ymm5, {rn_sae}).encode())
class TestVCVTPS2UQQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7D, 0x8A, 0x79, 0x74, 0xD3, 0xF5]), VCVTPS2UQQ(xmm30(k2.z), qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7D, 0xAD, 0x79, 0x9C, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPS2UQQ(ymm19(k5.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7D, 0xCE, 0x79, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPS2UQQ(zmm9(k6.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7D, 0x8A, 0x79, 0xF4]), VCVTPS2UQQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7D, 0xAD, 0x79, 0xDC]), VCVTPS2UQQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x71, 0x7D, 0x9E, 0x79, 0xCD]), VCVTPS2UQQ(zmm9(k6.z), ymm5, {rn_sae}).encode())
class TestVCVTTPS2QQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7D, 0x8A, 0x7A, 0x74, 0xD3, 0xF5]), VCVTTPS2QQ(xmm30(k2.z), qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7D, 0xAD, 0x7A, 0x9C, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTTPS2QQ(ymm19(k5.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7D, 0xCE, 0x7A, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPS2QQ(zmm9(k6.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7D, 0x8A, 0x7A, 0xF4]), VCVTTPS2QQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7D, 0xAD, 0x7A, 0xDC]), VCVTTPS2QQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x71, 0x7D, 0x9E, 0x7A, 0xCD]), VCVTTPS2QQ(zmm9(k6.z), ymm5, {sae}).encode())
class TestVCVTTPS2UQQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7D, 0x8A, 0x78, 0x74, 0xD3, 0xF5]), VCVTTPS2UQQ(xmm30(k2.z), qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7D, 0xAD, 0x78, 0x9C, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTTPS2UQQ(ymm19(k5.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7D, 0xCE, 0x78, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPS2UQQ(zmm9(k6.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7D, 0x8A, 0x78, 0xF4]), VCVTTPS2UQQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7D, 0xAD, 0x78, 0xDC]), VCVTTPS2UQQ(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x71, 0x7D, 0x9E, 0x78, 0xCD]), VCVTTPS2UQQ(zmm9(k6.z), ymm5, {sae}).encode())
class TestVCVTQQ2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFC, 0x8A, 0x5B, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTQQ2PS(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFC, 0xAA, 0x5B, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTQQ2PS(xmm30(k2.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFC, 0xCD, 0x5B, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTQQ2PS(ymm19(k5.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFC, 0x8A, 0x5B, 0xF4]), VCVTQQ2PS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFC, 0xAA, 0x5B, 0xF5]), VCVTQQ2PS(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x81, 0xFC, 0x9D, 0x5B, 0xDA]), VCVTQQ2PS(ymm19(k5.z), zmm26, {rn_sae}).encode())
class TestVCVTUQQ2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFF, 0x8A, 0x7A, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTUQQ2PS(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFF, 0xAA, 0x7A, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTUQQ2PS(xmm30(k2.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFF, 0xCD, 0x7A, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTUQQ2PS(ymm19(k5.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFF, 0x8A, 0x7A, 0xF4]), VCVTUQQ2PS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFF, 0xAA, 0x7A, 0xF5]), VCVTUQQ2PS(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x81, 0xFF, 0x9D, 0x7A, 0xDA]), VCVTUQQ2PS(ymm19(k5.z), zmm26, {rn_sae}).encode())
class TestVCVTPD2DQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFF, 0x8A, 0xE6, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPD2DQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFF, 0xAA, 0xE6, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2DQ(xmm30(k2.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFF, 0xCD, 0xE6, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2DQ(ymm19(k5.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFF, 0x8A, 0xE6, 0xF4]), VCVTPD2DQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFF, 0xAA, 0xE6, 0xF5]), VCVTPD2DQ(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0xE6, 0xCE]), VCVTPD2DQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7F, 0xE6, 0xCF]), VCVTPD2DQ(xmm1, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7B, 0xE6, 0x4C, 0xC2, 0xB3]), VCVTPD2DQ(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7F, 0xE6, 0x4C, 0xD9, 0xBE]), VCVTPD2DQ(xmm1, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x81, 0xFF, 0x9D, 0xE6, 0xDA]), VCVTPD2DQ(ymm19(k5.z), zmm26, {rn_sae}).encode())
class TestVCVTPD2UDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFC, 0x8A, 0x79, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPD2UDQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFC, 0xAA, 0x79, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2UDQ(xmm30(k2.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFC, 0xCD, 0x79, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2UDQ(ymm19(k5.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFC, 0x8A, 0x79, 0xF4]), VCVTPD2UDQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFC, 0xAA, 0x79, 0xF5]), VCVTPD2UDQ(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x81, 0xFC, 0x9D, 0x79, 0xDA]), VCVTPD2UDQ(ymm19(k5.z), zmm26, {rn_sae}).encode())
class TestVCVTTPD2DQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0xE6, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTTPD2DQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0xAA, 0xE6, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPD2DQ(xmm30(k2.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xCD, 0xE6, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPD2DQ(ymm19(k5.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0xE6, 0xF4]), VCVTTPD2DQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0xAA, 0xE6, 0xF5]), VCVTTPD2DQ(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0xE6, 0xCE]), VCVTTPD2DQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0xE6, 0xCF]), VCVTTPD2DQ(xmm1, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0xE6, 0x4C, 0xC2, 0xB3]), VCVTTPD2DQ(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0xE6, 0x4C, 0xD9, 0xBE]), VCVTTPD2DQ(xmm1, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x81, 0xFD, 0x9D, 0xE6, 0xDA]), VCVTTPD2DQ(ymm19(k5.z), zmm26, {sae}).encode())
class TestVCVTTPD2UDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFC, 0x8A, 0x78, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTTPD2UDQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFC, 0xAA, 0x78, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPD2UDQ(xmm30(k2.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFC, 0xCD, 0x78, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPD2UDQ(ymm19(k5.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFC, 0x8A, 0x78, 0xF4]), VCVTTPD2UDQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFC, 0xAA, 0x78, 0xF5]), VCVTTPD2UDQ(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x81, 0xFC, 0x9D, 0x78, 0xDA]), VCVTTPD2UDQ(ymm19(k5.z), zmm26, {sae}).encode())
class TestVCVTDQ2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7E, 0x8A, 0xE6, 0x74, 0xD3, 0xF5]), VCVTDQ2PD(xmm30(k2.z), qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7E, 0xAD, 0xE6, 0x9C, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTDQ2PD(ymm19(k5.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7E, 0xCE, 0xE6, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTDQ2PD(zmm9(k6.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7E, 0x8A, 0xE6, 0xF4]), VCVTDQ2PD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7E, 0xAD, 0xE6, 0xDC]), VCVTDQ2PD(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x71, 0x7E, 0xCE, 0xE6, 0xCD]), VCVTDQ2PD(zmm9(k6.z), ymm5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0xE6, 0xCE]), VCVTDQ2PD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7A, 0xE6, 0x4C, 0xD3, 0xA8]), VCVTDQ2PD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0xE6, 0xD6]), VCVTDQ2PD(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7E, 0xE6, 0x54, 0xC2, 0xB3]), VCVTDQ2PD(ymm2, oword[r10 + rax*8 - 77]).encode())
class TestVCVTUDQ2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7E, 0x8A, 0x7A, 0x74, 0xD3, 0xF5]), VCVTUDQ2PD(xmm30(k2.z), qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7E, 0xAD, 0x7A, 0x9C, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTUDQ2PD(ymm19(k5.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7E, 0xCE, 0x7A, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTUDQ2PD(zmm9(k6.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7E, 0x8A, 0x7A, 0xF4]), VCVTUDQ2PD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7E, 0xAD, 0x7A, 0xDC]), VCVTUDQ2PD(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x71, 0x7E, 0xCE, 0x7A, 0xCD]), VCVTUDQ2PD(zmm9(k6.z), ymm5).encode())
class TestVCVTPD2QQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0x7B, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPD2QQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xAD, 0x7B, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2QQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFD, 0xCE, 0x7B, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2QQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0x7B, 0xF4]), VCVTPD2QQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0xAD, 0x7B, 0xDD]), VCVTPD2QQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFD, 0x9E, 0x7B, 0xCA]), VCVTPD2QQ(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVCVTPD2UQQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0x79, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPD2UQQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xAD, 0x79, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2UQQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFD, 0xCE, 0x79, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2UQQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0x79, 0xF4]), VCVTPD2UQQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0xAD, 0x79, 0xDD]), VCVTPD2UQQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFD, 0x9E, 0x79, 0xCA]), VCVTPD2UQQ(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVCVTTPD2QQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0x7A, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTTPD2QQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xAD, 0x7A, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPD2QQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFD, 0xCE, 0x7A, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPD2QQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0x7A, 0xF4]), VCVTTPD2QQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0xAD, 0x7A, 0xDD]), VCVTTPD2QQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFD, 0x9E, 0x7A, 0xCA]), VCVTTPD2QQ(zmm9(k6.z), zmm26, {sae}).encode())
class TestVCVTTPD2UQQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0x78, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTTPD2UQQ(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xAD, 0x78, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPD2UQQ(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFD, 0xCE, 0x78, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTTPD2UQQ(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0x78, 0xF4]), VCVTTPD2UQQ(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFD, 0xAD, 0x78, 0xDD]), VCVTTPD2UQQ(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFD, 0x9E, 0x78, 0xCA]), VCVTTPD2UQQ(zmm9(k6.z), zmm26, {sae}).encode())
class TestVCVTQQ2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFE, 0x8A, 0xE6, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTQQ2PD(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFE, 0xAD, 0xE6, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTQQ2PD(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFE, 0xCE, 0xE6, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTQQ2PD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFE, 0x8A, 0xE6, 0xF4]), VCVTQQ2PD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFE, 0xAD, 0xE6, 0xDD]), VCVTQQ2PD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFE, 0x9E, 0xE6, 0xCA]), VCVTQQ2PD(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVCVTUQQ2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFE, 0x8A, 0x7A, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTUQQ2PD(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFE, 0xAD, 0x7A, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTUQQ2PD(ymm19(k5.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0xFE, 0xCE, 0x7A, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTUQQ2PD(zmm9(k6.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFE, 0x8A, 0x7A, 0xF4]), VCVTUQQ2PD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0xFE, 0xAD, 0x7A, 0xDD]), VCVTUQQ2PD(ymm19(k5.z), ymm5).encode())
self.assertEqual(bytearray([0x62, 0x11, 0xFE, 0x9E, 0x7A, 0xCA]), VCVTUQQ2PD(zmm9(k6.z), zmm26, {rn_sae}).encode())
class TestVCVTSD2SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xDF, 0x8A, 0x5A, 0x73, 0xF0]), VCVTSD2SS(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8B, 0x5A, 0xCB]), VCVTSD2SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0B, 0x5A, 0x4C, 0xD3, 0xA8]), VCVTSD2SS(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0xDF, 0x9A, 0x5A, 0xF3]), VCVTSD2SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVCVTSS2SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x5E, 0x8A, 0x5A, 0x74, 0x24, 0xE0]), VCVTSS2SD(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC5, 0x8A, 0x5A, 0xCB]), VCVTSS2SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x0A, 0x5A, 0x4C, 0xCC, 0x9D]), VCVTSS2SD(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x21, 0x5E, 0x9A, 0x5A, 0xF3]), VCVTSS2SD(xmm30(k2.z), xmm4, xmm19, {sae}).encode())
class TestVCVTPD2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0x8A, 0x5A, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPD2PS(xmm30(k2.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x41, 0xFD, 0xAA, 0x5A, 0xB4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2PS(xmm30(k2.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0xFD, 0xCD, 0x5A, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPD2PS(ymm19(k5.z), zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0x8A, 0x5A, 0xF4]), VCVTPD2PS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x61, 0xFD, 0xAA, 0x5A, 0xF5]), VCVTPD2PS(xmm30(k2.z), ymm5).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x5A, 0xCE]), VCVTPD2PS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x5A, 0xCF]), VCVTPD2PS(xmm1, ymm15).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x79, 0x5A, 0x4C, 0xC2, 0xB3]), VCVTPD2PS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7D, 0x5A, 0x4C, 0xD9, 0xBE]), VCVTPD2PS(xmm1, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x81, 0xFD, 0x9D, 0x5A, 0xDA]), VCVTPD2PS(ymm19(k5.z), zmm26, {rn_sae}).encode())
class TestVCVTPS2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x41, 0x7C, 0x8A, 0x5A, 0x74, 0xD3, 0xF5]), VCVTPS2PD(xmm30(k2.z), qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0xC1, 0x7C, 0xAD, 0x5A, 0x9C, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VCVTPS2PD(ymm19(k5.z), oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x51, 0x7C, 0xCE, 0x5A, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VCVTPS2PD(zmm9(k6.z), hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x61, 0x7C, 0x8A, 0x5A, 0xF4]), VCVTPS2PD(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE1, 0x7C, 0xAD, 0x5A, 0xDC]), VCVTPS2PD(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x5A, 0xCE]), VCVTPS2PD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0x5A, 0x4C, 0xD3, 0xA8]), VCVTPS2PD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x5A, 0xD6]), VCVTPS2PD(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC1, 0x7C, 0x5A, 0x54, 0xC2, 0xB3]), VCVTPS2PD(ymm2, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x71, 0x7C, 0x9E, 0x5A, 0xCD]), VCVTPS2PD(zmm9(k6.z), ymm5, {sae}).encode())
class TestVCVTPS2PH(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x93, 0x7D, 0x8A, 0x1D, 0xE6, 0x02]), VCVTPS2PH(xmm30(k2.z), xmm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x79, 0x1D, 0x63, 0xC0, 0x02]), VCVTPS2PH(qword[r11 - 64], xmm4, 2).encode())
self.assertEqual(bytearray([0x62, 0x93, 0x7D, 0xAA, 0x1D, 0xEE, 0x02]), VCVTPS2PH(xmm30(k2.z), ymm5, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7D, 0x1D, 0x6A, 0xC0, 0x02]), VCVTPS2PH(oword[r10 - 64], ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0x7D, 0x48, 0x1D, 0x51, 0xFE, 0x02]), VCVTPS2PH(hword[r9 - 64], zmm26, 2).encode())
self.assertEqual(bytearray([0xC4, 0x63, 0x79, 0x1D, 0xF1, 0x02]), VCVTPS2PH(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0x63, 0x7D, 0x1D, 0xF9, 0x02]), VCVTPS2PH(xmm1, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0x43, 0x79, 0x1D, 0x74, 0xD3, 0xA8, 0x02]), VCVTPS2PH(qword[r11 + rdx*8 - 88], xmm14, 2).encode())
self.assertEqual(bytearray([0xC4, 0x43, 0x7D, 0x1D, 0x7C, 0xC2, 0xB3, 0x02]), VCVTPS2PH(oword[r10 + rax*8 - 77], ymm15, 2).encode())
self.assertEqual(bytearray([0x62, 0x23, 0x7D, 0x9D, 0x1D, 0xD3, 0x02]), VCVTPS2PH(ymm19(k5.z), zmm26, {sae}, 2).encode())
class TestVCVTPH2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x13, 0xF4]), VCVTPH2PS(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x13, 0xDC]), VCVTPH2PS(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x13, 0x73, 0x08]), VCVTPH2PS(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x13, 0x5A, 0x04]), VCVTPH2PS(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x13, 0x49, 0x02]), VCVTPH2PS(zmm9(k6.z), hword[r9 + 64]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x13, 0xCE]), VCVTPH2PS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0x13, 0x4C, 0xD3, 0xA8]), VCVTPH2PS(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x13, 0xD6]), VCVTPH2PS(ymm2, xmm14).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x13, 0x54, 0xC2, 0xB3]), VCVTPH2PS(ymm2, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0x9E, 0x13, 0xCD]), VCVTPH2PS(zmm9(k6.z), ymm5, {sae}).encode())
class TestVBROADCASTF128(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x1A, 0x54, 0xC2, 0xB3]), VBROADCASTF128(ymm2, oword[r10 + rax*8 - 77]).encode())
class TestVBROADCASTI128(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x7D, 0x5A, 0x54, 0xC2, 0xB3]), VBROADCASTI128(ymm2, oword[r10 + rax*8 - 77]).encode())
class TestVBROADCASTF32X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x19, 0xDC]), VBROADCASTF32X2(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x19, 0xCC]), VBROADCASTF32X2(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x19, 0x5B, 0x08]), VBROADCASTF32X2(ymm19(k5.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x19, 0x4B, 0x08]), VBROADCASTF32X2(zmm9(k6.z), qword[r11 + 64]).encode())
class TestVBROADCASTI32X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x62, 0x7D, 0x8A, 0x59, 0xF4]), VBROADCASTI32X2(xmm30(k2.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7D, 0xAD, 0x59, 0xDC]), VBROADCASTI32X2(ymm19(k5.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x72, 0x7D, 0xCE, 0x59, 0xCC]), VBROADCASTI32X2(zmm9(k6.z), xmm4).encode())
self.assertEqual(bytearray([0x62, 0x42, 0x7D, 0x8A, 0x59, 0x73, 0x08]), VBROADCASTI32X2(xmm30(k2.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x59, 0x5B, 0x08]), VBROADCASTI32X2(ymm19(k5.z), qword[r11 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x59, 0x4B, 0x08]), VBROADCASTI32X2(zmm9(k6.z), qword[r11 + 64]).encode())
class TestVBROADCASTF32X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x1A, 0x5A, 0x04]), VBROADCASTF32X4(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x1A, 0x4A, 0x04]), VBROADCASTF32X4(zmm9(k6.z), oword[r10 + 64]).encode())
class TestVBROADCASTI32X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC2, 0x7D, 0xAD, 0x5A, 0x5A, 0x04]), VBROADCASTI32X4(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x5A, 0x4A, 0x04]), VBROADCASTI32X4(zmm9(k6.z), oword[r10 + 64]).encode())
class TestVBROADCASTF32X8(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x1B, 0x49, 0x02]), VBROADCASTF32X8(zmm9(k6.z), hword[r9 + 64]).encode())
class TestVBROADCASTI32X8(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0x7D, 0xCE, 0x5B, 0x49, 0x02]), VBROADCASTI32X8(zmm9(k6.z), hword[r9 + 64]).encode())
class TestVBROADCASTF64X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x1A, 0x5A, 0x04]), VBROADCASTF64X2(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x1A, 0x4A, 0x04]), VBROADCASTF64X2(zmm9(k6.z), oword[r10 + 64]).encode())
class TestVBROADCASTI64X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC2, 0xFD, 0xAD, 0x5A, 0x5A, 0x04]), VBROADCASTI64X2(ymm19(k5.z), oword[r10 + 64]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x5A, 0x4A, 0x04]), VBROADCASTI64X2(zmm9(k6.z), oword[r10 + 64]).encode())
class TestVBROADCASTF64X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x1B, 0x49, 0x02]), VBROADCASTF64X4(zmm9(k6.z), hword[r9 + 64]).encode())
class TestVBROADCASTI64X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x52, 0xFD, 0xCE, 0x5B, 0x49, 0x02]), VBROADCASTI64X4(zmm9(k6.z), hword[r9 + 64]).encode())
class TestVEXTRACTF128(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x63, 0x7D, 0x19, 0xF9, 0x02]), VEXTRACTF128(xmm1, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0x43, 0x7D, 0x19, 0x7C, 0xC2, 0xB3, 0x02]), VEXTRACTF128(oword[r10 + rax*8 - 77], ymm15, 2).encode())
class TestVEXTRACTI128(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0x63, 0x7D, 0x39, 0xF9, 0x02]), VEXTRACTI128(xmm1, ymm15, 2).encode())
self.assertEqual(bytearray([0xC4, 0x43, 0x7D, 0x39, 0x7C, 0xC2, 0xB3, 0x02]), VEXTRACTI128(oword[r10 + rax*8 - 77], ymm15, 2).encode())
class TestVEXTRACTF32X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x93, 0x7D, 0xAA, 0x19, 0xEE, 0x02]), VEXTRACTF32X4(xmm30(k2.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x7D, 0x28, 0x19, 0x6A, 0xFC, 0x02]), VEXTRACTF32X4(oword[r10 - 64], ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x03, 0x7D, 0xCA, 0x19, 0xD6, 0x02]), VEXTRACTF32X4(xmm30(k2.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0x7D, 0x48, 0x19, 0x52, 0xFC, 0x02]), VEXTRACTF32X4(oword[r10 - 64], zmm26, 2).encode())
class TestVEXTRACTI32X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x93, 0x7D, 0xAA, 0x39, 0xEE, 0x02]), VEXTRACTI32X4(xmm30(k2.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0x7D, 0x28, 0x39, 0x6A, 0xFC, 0x02]), VEXTRACTI32X4(oword[r10 - 64], ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x03, 0x7D, 0xCA, 0x39, 0xD6, 0x02]), VEXTRACTI32X4(xmm30(k2.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0x7D, 0x48, 0x39, 0x52, 0xFC, 0x02]), VEXTRACTI32X4(oword[r10 - 64], zmm26, 2).encode())
class TestVEXTRACTF32X8(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x23, 0x7D, 0xCD, 0x1B, 0xD3, 0x02]), VEXTRACTF32X8(ymm19(k5.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0x7D, 0x48, 0x1B, 0x51, 0xFE, 0x02]), VEXTRACTF32X8(hword[r9 - 64], zmm26, 2).encode())
class TestVEXTRACTI32X8(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x23, 0x7D, 0xCD, 0x3B, 0xD3, 0x02]), VEXTRACTI32X8(ymm19(k5.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0x7D, 0x48, 0x3B, 0x51, 0xFE, 0x02]), VEXTRACTI32X8(hword[r9 - 64], zmm26, 2).encode())
class TestVEXTRACTF64X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x93, 0xFD, 0xAA, 0x19, 0xEE, 0x02]), VEXTRACTF64X2(xmm30(k2.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xFD, 0x28, 0x19, 0x6A, 0xFC, 0x02]), VEXTRACTF64X2(oword[r10 - 64], ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x03, 0xFD, 0xCA, 0x19, 0xD6, 0x02]), VEXTRACTF64X2(xmm30(k2.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0xFD, 0x48, 0x19, 0x52, 0xFC, 0x02]), VEXTRACTF64X2(oword[r10 - 64], zmm26, 2).encode())
class TestVEXTRACTI64X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x93, 0xFD, 0xAA, 0x39, 0xEE, 0x02]), VEXTRACTI64X2(xmm30(k2.z), ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0xD3, 0xFD, 0x28, 0x39, 0x6A, 0xFC, 0x02]), VEXTRACTI64X2(oword[r10 - 64], ymm5, 2).encode())
self.assertEqual(bytearray([0x62, 0x03, 0xFD, 0xCA, 0x39, 0xD6, 0x02]), VEXTRACTI64X2(xmm30(k2.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0xFD, 0x48, 0x39, 0x52, 0xFC, 0x02]), VEXTRACTI64X2(oword[r10 - 64], zmm26, 2).encode())
class TestVEXTRACTF64X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x23, 0xFD, 0xCD, 0x1B, 0xD3, 0x02]), VEXTRACTF64X4(ymm19(k5.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0xFD, 0x48, 0x1B, 0x51, 0xFE, 0x02]), VEXTRACTF64X4(hword[r9 - 64], zmm26, 2).encode())
class TestVEXTRACTI64X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x23, 0xFD, 0xCD, 0x3B, 0xD3, 0x02]), VEXTRACTI64X4(ymm19(k5.z), zmm26, 2).encode())
self.assertEqual(bytearray([0x62, 0x43, 0xFD, 0x48, 0x3B, 0x51, 0xFE, 0x02]), VEXTRACTI64X4(hword[r9 - 64], zmm26, 2).encode())
class TestVINSERTF128(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x18, 0xD3, 0x02]), VINSERTF128(ymm2, ymm15, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x18, 0x54, 0xC2, 0xB3, 0x02]), VINSERTF128(ymm2, ymm15, oword[r10 + rax*8 - 77], 2).encode())
class TestVINSERTI128(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x38, 0xD3, 0x02]), VINSERTI128(ymm2, ymm15, xmm3, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x38, 0x54, 0xC2, 0xB3, 0x02]), VINSERTI128(ymm2, ymm15, oword[r10 + rax*8 - 77], 2).encode())
class TestVINSERTF32X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x18, 0xDB, 0x02]), VINSERTF32X4(ymm19(k5.z), ymm5, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x18, 0x5A, 0xF8, 0x02]), VINSERTF32X4(ymm19(k5.z), ymm5, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x33, 0x2D, 0xC6, 0x18, 0xCB, 0x02]), VINSERTF32X4(zmm9(k6.z), zmm26, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x18, 0x4A, 0xF8, 0x02]), VINSERTF32X4(zmm9(k6.z), zmm26, oword[r10 - 128], 2).encode())
class TestVINSERTI32X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x38, 0xDB, 0x02]), VINSERTI32X4(ymm19(k5.z), ymm5, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x38, 0x5A, 0xF8, 0x02]), VINSERTI32X4(ymm19(k5.z), ymm5, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x33, 0x2D, 0xC6, 0x38, 0xCB, 0x02]), VINSERTI32X4(zmm9(k6.z), zmm26, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x38, 0x4A, 0xF8, 0x02]), VINSERTI32X4(zmm9(k6.z), zmm26, oword[r10 - 128], 2).encode())
class TestVINSERTF32X8(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x33, 0x2D, 0xC6, 0x1A, 0xCC, 0x02]), VINSERTF32X8(zmm9(k6.z), zmm26, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x1A, 0x49, 0xFC, 0x02]), VINSERTF32X8(zmm9(k6.z), zmm26, hword[r9 - 128], 2).encode())
class TestVINSERTI32X8(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x33, 0x2D, 0xC6, 0x3A, 0xCC, 0x02]), VINSERTI32X8(zmm9(k6.z), zmm26, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x3A, 0x49, 0xFC, 0x02]), VINSERTI32X8(zmm9(k6.z), zmm26, hword[r9 - 128], 2).encode())
class TestVINSERTF64X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xA3, 0xD5, 0xAD, 0x18, 0xDB, 0x02]), VINSERTF64X2(ymm19(k5.z), ymm5, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xD5, 0xAD, 0x18, 0x5A, 0xF8, 0x02]), VINSERTF64X2(ymm19(k5.z), ymm5, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x33, 0xAD, 0xC6, 0x18, 0xCB, 0x02]), VINSERTF64X2(zmm9(k6.z), zmm26, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x18, 0x4A, 0xF8, 0x02]), VINSERTF64X2(zmm9(k6.z), zmm26, oword[r10 - 128], 2).encode())
class TestVINSERTI64X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xA3, 0xD5, 0xAD, 0x38, 0xDB, 0x02]), VINSERTI64X2(ymm19(k5.z), ymm5, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0xC3, 0xD5, 0xAD, 0x38, 0x5A, 0xF8, 0x02]), VINSERTI64X2(ymm19(k5.z), ymm5, oword[r10 - 128], 2).encode())
self.assertEqual(bytearray([0x62, 0x33, 0xAD, 0xC6, 0x38, 0xCB, 0x02]), VINSERTI64X2(zmm9(k6.z), zmm26, xmm19, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x38, 0x4A, 0xF8, 0x02]), VINSERTI64X2(zmm9(k6.z), zmm26, oword[r10 - 128], 2).encode())
class TestVINSERTF64X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x33, 0xAD, 0xC6, 0x1A, 0xCC, 0x02]), VINSERTF64X4(zmm9(k6.z), zmm26, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x1A, 0x49, 0xFC, 0x02]), VINSERTF64X4(zmm9(k6.z), zmm26, hword[r9 - 128], 2).encode())
class TestVINSERTI64X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x33, 0xAD, 0xC6, 0x3A, 0xCC, 0x02]), VINSERTI64X4(zmm9(k6.z), zmm26, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x3A, 0x49, 0xFC, 0x02]), VINSERTI64X4(zmm9(k6.z), zmm26, hword[r9 - 128], 2).encode())
class TestVPERM2F128(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x06, 0xD4, 0x02]), VPERM2F128(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x06, 0x54, 0xD9, 0xBE, 0x02]), VPERM2F128(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVPERM2I128(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x46, 0xD4, 0x02]), VPERM2I128(ymm2, ymm15, ymm4, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x46, 0x54, 0xD9, 0xBE, 0x02]), VPERM2I128(ymm2, ymm15, hword[r9 + rbx*8 - 66], 2).encode())
class TestVSHUFF32X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x23, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFF32X4(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x23, 0xDC, 0x02]), VSHUFF32X4(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x23, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFF32X4(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x23, 0xC9, 0x02]), VSHUFF32X4(zmm9(k6.z), zmm26, zmm9, 2).encode())
class TestVSHUFI32X4(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC3, 0x55, 0xAD, 0x43, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFI32X4(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0x55, 0xAD, 0x43, 0xDC, 0x02]), VSHUFI32X4(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x43, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFI32X4(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0x2D, 0xC6, 0x43, 0xC9, 0x02]), VSHUFI32X4(zmm9(k6.z), zmm26, zmm9, 2).encode())
class TestVSHUFF64X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC3, 0xD5, 0xAD, 0x23, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFF64X2(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0xD5, 0xAD, 0x23, 0xDC, 0x02]), VSHUFF64X2(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x23, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFF64X2(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x23, 0xC9, 0x02]), VSHUFF64X2(zmm9(k6.z), zmm26, zmm9, 2).encode())
class TestVSHUFI64X2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xC3, 0xD5, 0xAD, 0x43, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFI64X2(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0xA3, 0xD5, 0xAD, 0x43, 0xDC, 0x02]), VSHUFI64X2(ymm19(k5.z), ymm5, ymm20, 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x43, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF, 0x02]), VSHUFI64X2(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66], 2).encode())
self.assertEqual(bytearray([0x62, 0x53, 0xAD, 0xC6, 0x43, 0xC9, 0x02]), VSHUFI64X2(zmm9(k6.z), zmm26, zmm9, 2).encode())
class TestVPMOVB2M(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7E, 0x08, 0x29, 0xEC]), VPMOVB2M(k5, xmm4).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0x7E, 0x28, 0x29, 0xED]), VPMOVB2M(k5, ymm5).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x48, 0x29, 0xEA]), VPMOVB2M(k5, zmm26).encode())
class TestVPMOVW2M(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFE, 0x08, 0x29, 0xEC]), VPMOVW2M(k5, xmm4).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0xFE, 0x28, 0x29, 0xED]), VPMOVW2M(k5, ymm5).encode())
self.assertEqual(bytearray([0x62, 0x92, 0xFE, 0x48, 0x29, 0xEA]), VPMOVW2M(k5, zmm26).encode())
class TestVPMOVD2M(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0x7E, 0x08, 0x39, 0xEC]), VPMOVD2M(k5, xmm4).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0x7E, 0x28, 0x39, 0xED]), VPMOVD2M(k5, ymm5).encode())
self.assertEqual(bytearray([0x62, 0x92, 0x7E, 0x48, 0x39, 0xEA]), VPMOVD2M(k5, zmm26).encode())
class TestVPMOVQ2M(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xF2, 0xFE, 0x08, 0x39, 0xEC]), VPMOVQ2M(k5, xmm4).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0xFE, 0x28, 0x39, 0xED]), VPMOVQ2M(k5, ymm5).encode())
self.assertEqual(bytearray([0x62, 0x92, 0xFE, 0x48, 0x39, 0xEA]), VPMOVQ2M(k5, zmm26).encode())
class TestVPMOVM2B(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE2, 0x7E, 0x08, 0x28, 0xC5]), VPMOVM2B(xmm16, k5).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7E, 0x28, 0x28, 0xCD]), VPMOVM2B(ymm17, k5).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0x7E, 0x48, 0x28, 0xDD]), VPMOVM2B(zmm3, k5).encode())
class TestVPMOVM2W(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE2, 0xFE, 0x08, 0x28, 0xC5]), VPMOVM2W(xmm16, k5).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFE, 0x28, 0x28, 0xCD]), VPMOVM2W(ymm17, k5).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0xFE, 0x48, 0x28, 0xDD]), VPMOVM2W(zmm3, k5).encode())
class TestVPMOVM2D(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE2, 0x7E, 0x08, 0x38, 0xC5]), VPMOVM2D(xmm16, k5).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7E, 0x28, 0x38, 0xCD]), VPMOVM2D(ymm17, k5).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0x7E, 0x48, 0x38, 0xDD]), VPMOVM2D(zmm3, k5).encode())
class TestVPMOVM2Q(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE2, 0xFE, 0x08, 0x38, 0xC5]), VPMOVM2Q(xmm16, k5).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFE, 0x28, 0x38, 0xCD]), VPMOVM2Q(ymm17, k5).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0xFE, 0x48, 0x38, 0xDD]), VPMOVM2Q(zmm3, k5).encode())
class TestVPBROADCASTMB2Q(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE2, 0xFE, 0x08, 0x2A, 0xC5]), VPBROADCASTMB2Q(xmm16, k5).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0xFE, 0x28, 0x2A, 0xCD]), VPBROADCASTMB2Q(ymm17, k5).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0xFE, 0x48, 0x2A, 0xDD]), VPBROADCASTMB2Q(zmm3, k5).encode())
class TestVPBROADCASTMW2D(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xE2, 0x7E, 0x08, 0x3A, 0xC5]), VPBROADCASTMW2D(xmm16, k5).encode())
self.assertEqual(bytearray([0x62, 0xE2, 0x7E, 0x28, 0x3A, 0xCD]), VPBROADCASTMW2D(ymm17, k5).encode())
self.assertEqual(bytearray([0x62, 0xF2, 0x7E, 0x48, 0x3A, 0xDD]), VPBROADCASTMW2D(zmm3, k5).encode())
class TestVPTESTMB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB2, 0x5D, 0x0E, 0x26, 0xE3]), VPTESTMB(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x5D, 0x0E, 0x26, 0x62, 0xF8]), VPTESTMB(k4(k6), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0x55, 0x2E, 0x26, 0xE4]), VPTESTMB(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x55, 0x2E, 0x26, 0x61, 0xFC]), VPTESTMB(k4(k6), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x2D, 0x46, 0x26, 0xE1]), VPTESTMB(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x2D, 0x46, 0x26, 0x60, 0xFE]), VPTESTMB(k4(k6), zmm26, zword[r8 - 128]).encode())
class TestVPTESTMW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB2, 0xDD, 0x0E, 0x26, 0xE3]), VPTESTMW(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xDD, 0x0E, 0x26, 0x62, 0xF8]), VPTESTMW(k4(k6), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xD5, 0x2E, 0x26, 0xE4]), VPTESTMW(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xD5, 0x2E, 0x26, 0x61, 0xFC]), VPTESTMW(k4(k6), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAD, 0x46, 0x26, 0xE1]), VPTESTMW(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAD, 0x46, 0x26, 0x60, 0xFE]), VPTESTMW(k4(k6), zmm26, zword[r8 - 128]).encode())
class TestVPTESTMD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x5D, 0x0E, 0x27, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPTESTMD(k4(k6), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0x5D, 0x0E, 0x27, 0xE3]), VPTESTMD(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x55, 0x2E, 0x27, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPTESTMD(k4(k6), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0x55, 0x2E, 0x27, 0xE4]), VPTESTMD(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x2D, 0x46, 0x27, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPTESTMD(k4(k6), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x2D, 0x46, 0x27, 0xE1]), VPTESTMD(k4(k6), zmm26, zmm9).encode())
class TestVPTESTMQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0xDD, 0x0E, 0x27, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPTESTMQ(k4(k6), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xDD, 0x0E, 0x27, 0xE3]), VPTESTMQ(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xD5, 0x2E, 0x27, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPTESTMQ(k4(k6), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xD5, 0x2E, 0x27, 0xE4]), VPTESTMQ(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAD, 0x46, 0x27, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPTESTMQ(k4(k6), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAD, 0x46, 0x27, 0xE1]), VPTESTMQ(k4(k6), zmm26, zmm9).encode())
class TestVPTESTNMB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB2, 0x5E, 0x0E, 0x26, 0xE3]), VPTESTNMB(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x5E, 0x0E, 0x26, 0x62, 0xF8]), VPTESTNMB(k4(k6), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0x56, 0x2E, 0x26, 0xE4]), VPTESTNMB(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x56, 0x2E, 0x26, 0x61, 0xFC]), VPTESTNMB(k4(k6), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x2E, 0x46, 0x26, 0xE1]), VPTESTNMB(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x2E, 0x46, 0x26, 0x60, 0xFE]), VPTESTNMB(k4(k6), zmm26, zword[r8 - 128]).encode())
class TestVPTESTNMW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xB2, 0xDE, 0x0E, 0x26, 0xE3]), VPTESTNMW(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xDE, 0x0E, 0x26, 0x62, 0xF8]), VPTESTNMW(k4(k6), xmm4, oword[r10 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xD6, 0x2E, 0x26, 0xE4]), VPTESTNMW(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xD6, 0x2E, 0x26, 0x61, 0xFC]), VPTESTNMW(k4(k6), ymm5, hword[r9 - 128]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAE, 0x46, 0x26, 0xE1]), VPTESTNMW(k4(k6), zmm26, zmm9).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAE, 0x46, 0x26, 0x60, 0xFE]), VPTESTNMW(k4(k6), zmm26, zword[r8 - 128]).encode())
class TestVPTESTNMD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0x5E, 0x0E, 0x27, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPTESTNMD(k4(k6), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0x5E, 0x0E, 0x27, 0xE3]), VPTESTNMD(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x56, 0x2E, 0x27, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPTESTNMD(k4(k6), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0x56, 0x2E, 0x27, 0xE4]), VPTESTNMD(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x2E, 0x46, 0x27, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPTESTNMD(k4(k6), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0x2E, 0x46, 0x27, 0xE1]), VPTESTNMD(k4(k6), zmm26, zmm9).encode())
class TestVPTESTNMQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0xD2, 0xDE, 0x0E, 0x27, 0xA4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VPTESTNMQ(k4(k6), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xDE, 0x0E, 0x27, 0xE3]), VPTESTNMQ(k4(k6), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xD6, 0x2E, 0x27, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPTESTNMQ(k4(k6), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xB2, 0xD6, 0x2E, 0x27, 0xE4]), VPTESTNMQ(k4(k6), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAE, 0x46, 0x27, 0xA4, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VPTESTNMQ(k4(k6), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xD2, 0xAE, 0x46, 0x27, 0xE1]), VPTESTNMQ(k4(k6), zmm26, zmm9).encode())
class TestVLDMXCSR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0xAE, 0x54, 0xCC, 0x9D]), VLDMXCSR(dword[r12 + rcx*8 - 99]).encode())
class TestVSTMXCSR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC1, 0x78, 0xAE, 0x5C, 0xCC, 0x9D]), VSTMXCSR(dword[r12 + rcx*8 - 99]).encode())
class TestVZEROUPPER(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xF8, 0x77]), VZEROUPPER().encode())
class TestVZEROALL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC5, 0xFC, 0x77]), VZEROALL().encode())
|
# This file is auto-generated by /codegen/x86_64_test_encoding.py
# Reference opcodes are generated by:
# GNU assembler (GNU Binutils) 2.28.51.20170402
from peachpy.x86_64 import *
import unittest
class TestADD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x04, 0x02]), ADD(al, 2).encode())
self.assertEqual(bytearray([0x80, 0xC3, 0x02]), ADD(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x00, 0xCB]), ADD(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x02, 0x5C, 0xBE, 0x85]), ADD(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x05, 0x00, 0x7D]), ADD(ax, 32000).encode())
self.assertEqual(bytearray([0x66, 0x83, 0xC6, 0x02]), ADD(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x81, 0xC6, 0x00, 0x7D]), ADD(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x01, 0xE6]), ADD(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x03, 0x74, 0xED, 0x95]), ADD(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x05, 0x00, 0x00, 0x00, 0x10]), ADD(eax, 0x10000000).encode())
self.assertEqual(bytearray([0x83, 0xC5, 0x02]), ADD(ebp, 2).encode())
self.assertEqual(bytearray([0x81, 0xC5, 0x00, 0x00, 0x00, 0x10]), ADD(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x01, 0xC5]), ADD(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x03, 0x6C, 0xCC, 0x9D]), ADD(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x48, 0x05, 0x00, 0x00, 0x00, 0x10]), ADD(rax, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xC1, 0x02]), ADD(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0x81, 0xC1, 0x00, 0x00, 0x00, 0x10]), ADD(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x4C, 0x01, 0xF9]), ADD(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x03, 0x4C, 0xD3, 0xA8]), ADD(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0x80, 0x44, 0xBE, 0x85, 0x02]), ADD(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x00, 0x4C, 0xBE, 0x85]), ADD(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x83, 0x44, 0xED, 0x95, 0x02]), ADD(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x81, 0x44, 0xED, 0x95, 0x00, 0x7D]), ADD(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x01, 0x64, 0xED, 0x95]), ADD(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x83, 0x44, 0xCC, 0x9D, 0x02]), ADD(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0x81, 0x44, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), ADD(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x01, 0x44, 0xCC, 0x9D]), ADD(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x83, 0x44, 0xD3, 0xA8, 0x02]), ADD(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0x81, 0x44, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), ADD(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x01, 0x7C, 0xD3, 0xA8]), ADD(qword[r11 + rdx*8 - 88], r15).encode())
class TestSUB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x2C, 0x02]), SUB(al, 2).encode())
self.assertEqual(bytearray([0x80, 0xEB, 0x02]), SUB(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x28, 0xCB]), SUB(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x2A, 0x5C, 0xBE, 0x85]), SUB(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x2D, 0x00, 0x7D]), SUB(ax, 32000).encode())
self.assertEqual(bytearray([0x66, 0x83, 0xEE, 0x02]), SUB(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x81, 0xEE, 0x00, 0x7D]), SUB(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x29, 0xE6]), SUB(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x2B, 0x74, 0xED, 0x95]), SUB(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x2D, 0x00, 0x00, 0x00, 0x10]), SUB(eax, 0x10000000).encode())
self.assertEqual(bytearray([0x83, 0xED, 0x02]), SUB(ebp, 2).encode())
self.assertEqual(bytearray([0x81, 0xED, 0x00, 0x00, 0x00, 0x10]), SUB(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x29, 0xC5]), SUB(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x2B, 0x6C, 0xCC, 0x9D]), SUB(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x48, 0x2D, 0x00, 0x00, 0x00, 0x10]), SUB(rax, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xE9, 0x02]), SUB(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0x81, 0xE9, 0x00, 0x00, 0x00, 0x10]), SUB(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x4C, 0x29, 0xF9]), SUB(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x2B, 0x4C, 0xD3, 0xA8]), SUB(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0x80, 0x6C, 0xBE, 0x85, 0x02]), SUB(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x28, 0x4C, 0xBE, 0x85]), SUB(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x83, 0x6C, 0xED, 0x95, 0x02]), SUB(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x81, 0x6C, 0xED, 0x95, 0x00, 0x7D]), SUB(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x29, 0x64, 0xED, 0x95]), SUB(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x83, 0x6C, 0xCC, 0x9D, 0x02]), SUB(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0x81, 0x6C, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), SUB(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x29, 0x44, 0xCC, 0x9D]), SUB(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x83, 0x6C, 0xD3, 0xA8, 0x02]), SUB(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0x81, 0x6C, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), SUB(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x29, 0x7C, 0xD3, 0xA8]), SUB(qword[r11 + rdx*8 - 88], r15).encode())
class TestADC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x14, 0x02]), ADC(al, 2).encode())
self.assertEqual(bytearray([0x80, 0xD3, 0x02]), ADC(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x10, 0xCB]), ADC(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x12, 0x5C, 0xBE, 0x85]), ADC(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x15, 0x00, 0x7D]), ADC(ax, 32000).encode())
self.assertEqual(bytearray([0x66, 0x83, 0xD6, 0x02]), ADC(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x81, 0xD6, 0x00, 0x7D]), ADC(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x11, 0xE6]), ADC(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x13, 0x74, 0xED, 0x95]), ADC(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x15, 0x00, 0x00, 0x00, 0x10]), ADC(eax, 0x10000000).encode())
self.assertEqual(bytearray([0x83, 0xD5, 0x02]), ADC(ebp, 2).encode())
self.assertEqual(bytearray([0x81, 0xD5, 0x00, 0x00, 0x00, 0x10]), ADC(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x11, 0xC5]), ADC(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x13, 0x6C, 0xCC, 0x9D]), ADC(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x48, 0x15, 0x00, 0x00, 0x00, 0x10]), ADC(rax, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xD1, 0x02]), ADC(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0x81, 0xD1, 0x00, 0x00, 0x00, 0x10]), ADC(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x4C, 0x11, 0xF9]), ADC(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x13, 0x4C, 0xD3, 0xA8]), ADC(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0x80, 0x54, 0xBE, 0x85, 0x02]), ADC(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x10, 0x4C, 0xBE, 0x85]), ADC(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x83, 0x54, 0xED, 0x95, 0x02]), ADC(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x81, 0x54, 0xED, 0x95, 0x00, 0x7D]), ADC(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x11, 0x64, 0xED, 0x95]), ADC(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x83, 0x54, 0xCC, 0x9D, 0x02]), ADC(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0x81, 0x54, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), ADC(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x11, 0x44, 0xCC, 0x9D]), ADC(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x83, 0x54, 0xD3, 0xA8, 0x02]), ADC(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0x81, 0x54, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), ADC(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x11, 0x7C, 0xD3, 0xA8]), ADC(qword[r11 + rdx*8 - 88], r15).encode())
class TestSBB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x1C, 0x02]), SBB(al, 2).encode())
self.assertEqual(bytearray([0x80, 0xDB, 0x02]), SBB(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x18, 0xCB]), SBB(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x1A, 0x5C, 0xBE, 0x85]), SBB(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x1D, 0x00, 0x7D]), SBB(ax, 32000).encode())
self.assertEqual(bytearray([0x66, 0x83, 0xDE, 0x02]), SBB(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x81, 0xDE, 0x00, 0x7D]), SBB(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x19, 0xE6]), SBB(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x1B, 0x74, 0xED, 0x95]), SBB(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x1D, 0x00, 0x00, 0x00, 0x10]), SBB(eax, 0x10000000).encode())
self.assertEqual(bytearray([0x83, 0xDD, 0x02]), SBB(ebp, 2).encode())
self.assertEqual(bytearray([0x81, 0xDD, 0x00, 0x00, 0x00, 0x10]), SBB(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x19, 0xC5]), SBB(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x1B, 0x6C, 0xCC, 0x9D]), SBB(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x48, 0x1D, 0x00, 0x00, 0x00, 0x10]), SBB(rax, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xD9, 0x02]), SBB(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0x81, 0xD9, 0x00, 0x00, 0x00, 0x10]), SBB(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x4C, 0x19, 0xF9]), SBB(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x1B, 0x4C, 0xD3, 0xA8]), SBB(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0x80, 0x5C, 0xBE, 0x85, 0x02]), SBB(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x18, 0x4C, 0xBE, 0x85]), SBB(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x83, 0x5C, 0xED, 0x95, 0x02]), SBB(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x81, 0x5C, 0xED, 0x95, 0x00, 0x7D]), SBB(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x19, 0x64, 0xED, 0x95]), SBB(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x83, 0x5C, 0xCC, 0x9D, 0x02]), SBB(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0x81, 0x5C, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), SBB(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x19, 0x44, 0xCC, 0x9D]), SBB(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x83, 0x5C, 0xD3, 0xA8, 0x02]), SBB(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0x81, 0x5C, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), SBB(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x19, 0x7C, 0xD3, 0xA8]), SBB(qword[r11 + rdx*8 - 88], r15).encode())
class TestADCX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xF6, 0xE8]), ADCX(ebp, r8d).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xF6, 0x6C, 0xCC, 0x9D]), ADCX(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x66, 0x49, 0x0F, 0x38, 0xF6, 0xCF]), ADCX(rcx, r15).encode())
self.assertEqual(bytearray([0x66, 0x49, 0x0F, 0x38, 0xF6, 0x4C, 0xD3, 0xA8]), ADCX(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestADOX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x38, 0xF6, 0xE8]), ADOX(ebp, r8d).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x38, 0xF6, 0x6C, 0xCC, 0x9D]), ADOX(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0x38, 0xF6, 0xCF]), ADOX(rcx, r15).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0x38, 0xF6, 0x4C, 0xD3, 0xA8]), ADOX(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestAND(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x24, 0x02]), AND(al, 2).encode())
self.assertEqual(bytearray([0x80, 0xE3, 0x02]), AND(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x20, 0xCB]), AND(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x22, 0x5C, 0xBE, 0x85]), AND(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x25, 0x00, 0x7D]), AND(ax, 32000).encode())
self.assertEqual(bytearray([0x66, 0x83, 0xE6, 0x02]), AND(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x81, 0xE6, 0x00, 0x7D]), AND(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x21, 0xE6]), AND(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x23, 0x74, 0xED, 0x95]), AND(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x25, 0x00, 0x00, 0x00, 0x10]), AND(eax, 0x10000000).encode())
self.assertEqual(bytearray([0x83, 0xE5, 0x02]), AND(ebp, 2).encode())
self.assertEqual(bytearray([0x81, 0xE5, 0x00, 0x00, 0x00, 0x10]), AND(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x21, 0xC5]), AND(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x23, 0x6C, 0xCC, 0x9D]), AND(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x48, 0x25, 0x00, 0x00, 0x00, 0x10]), AND(rax, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xE1, 0x02]), AND(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0x81, 0xE1, 0x00, 0x00, 0x00, 0x10]), AND(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x4C, 0x21, 0xF9]), AND(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x23, 0x4C, 0xD3, 0xA8]), AND(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0x80, 0x64, 0xBE, 0x85, 0x02]), AND(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x20, 0x4C, 0xBE, 0x85]), AND(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x83, 0x64, 0xED, 0x95, 0x02]), AND(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x81, 0x64, 0xED, 0x95, 0x00, 0x7D]), AND(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x21, 0x64, 0xED, 0x95]), AND(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x83, 0x64, 0xCC, 0x9D, 0x02]), AND(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0x81, 0x64, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), AND(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x21, 0x44, 0xCC, 0x9D]), AND(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x83, 0x64, 0xD3, 0xA8, 0x02]), AND(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0x81, 0x64, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), AND(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x21, 0x7C, 0xD3, 0xA8]), AND(qword[r11 + rdx*8 - 88], r15).encode())
class TestOR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0C, 0x02]), OR(al, 2).encode())
self.assertEqual(bytearray([0x80, 0xCB, 0x02]), OR(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x08, 0xCB]), OR(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x0A, 0x5C, 0xBE, 0x85]), OR(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x0D, 0x00, 0x7D]), OR(ax, 32000).encode())
self.assertEqual(bytearray([0x66, 0x83, 0xCE, 0x02]), OR(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x81, 0xCE, 0x00, 0x7D]), OR(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x09, 0xE6]), OR(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0B, 0x74, 0xED, 0x95]), OR(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x0D, 0x00, 0x00, 0x00, 0x10]), OR(eax, 0x10000000).encode())
self.assertEqual(bytearray([0x83, 0xCD, 0x02]), OR(ebp, 2).encode())
self.assertEqual(bytearray([0x81, 0xCD, 0x00, 0x00, 0x00, 0x10]), OR(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x09, 0xC5]), OR(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0B, 0x6C, 0xCC, 0x9D]), OR(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x48, 0x0D, 0x00, 0x00, 0x00, 0x10]), OR(rax, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xC9, 0x02]), OR(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0x81, 0xC9, 0x00, 0x00, 0x00, 0x10]), OR(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x4C, 0x09, 0xF9]), OR(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0B, 0x4C, 0xD3, 0xA8]), OR(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0x80, 0x4C, 0xBE, 0x85, 0x02]), OR(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x08, 0x4C, 0xBE, 0x85]), OR(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x83, 0x4C, 0xED, 0x95, 0x02]), OR(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x81, 0x4C, 0xED, 0x95, 0x00, 0x7D]), OR(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x09, 0x64, 0xED, 0x95]), OR(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x83, 0x4C, 0xCC, 0x9D, 0x02]), OR(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0x81, 0x4C, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), OR(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x09, 0x44, 0xCC, 0x9D]), OR(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x83, 0x4C, 0xD3, 0xA8, 0x02]), OR(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0x81, 0x4C, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), OR(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x09, 0x7C, 0xD3, 0xA8]), OR(qword[r11 + rdx*8 - 88], r15).encode())
class TestXOR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x34, 0x02]), XOR(al, 2).encode())
self.assertEqual(bytearray([0x80, 0xF3, 0x02]), XOR(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x30, 0xCB]), XOR(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x32, 0x5C, 0xBE, 0x85]), XOR(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x35, 0x00, 0x7D]), XOR(ax, 32000).encode())
self.assertEqual(bytearray([0x66, 0x83, 0xF6, 0x02]), XOR(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x81, 0xF6, 0x00, 0x7D]), XOR(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x31, 0xE6]), XOR(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x33, 0x74, 0xED, 0x95]), XOR(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x35, 0x00, 0x00, 0x00, 0x10]), XOR(eax, 0x10000000).encode())
self.assertEqual(bytearray([0x83, 0xF5, 0x02]), XOR(ebp, 2).encode())
self.assertEqual(bytearray([0x81, 0xF5, 0x00, 0x00, 0x00, 0x10]), XOR(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x31, 0xC5]), XOR(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x33, 0x6C, 0xCC, 0x9D]), XOR(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x48, 0x35, 0x00, 0x00, 0x00, 0x10]), XOR(rax, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xF1, 0x02]), XOR(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0x81, 0xF1, 0x00, 0x00, 0x00, 0x10]), XOR(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x4C, 0x31, 0xF9]), XOR(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x33, 0x4C, 0xD3, 0xA8]), XOR(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0x80, 0x74, 0xBE, 0x85, 0x02]), XOR(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x30, 0x4C, 0xBE, 0x85]), XOR(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x83, 0x74, 0xED, 0x95, 0x02]), XOR(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x81, 0x74, 0xED, 0x95, 0x00, 0x7D]), XOR(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x31, 0x64, 0xED, 0x95]), XOR(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x83, 0x74, 0xCC, 0x9D, 0x02]), XOR(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0x81, 0x74, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), XOR(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x31, 0x44, 0xCC, 0x9D]), XOR(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x83, 0x74, 0xD3, 0xA8, 0x02]), XOR(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0x81, 0x74, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), XOR(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x31, 0x7C, 0xD3, 0xA8]), XOR(qword[r11 + rdx*8 - 88], r15).encode())
class TestANDN(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x38, 0xF2, 0xE8]), ANDN(ebp, r8d, eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x38, 0xF2, 0x6C, 0xCC, 0x9D]), ANDN(ebp, r8d, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x80, 0xF2, 0xC8]), ANDN(rcx, r15, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x80, 0xF2, 0x4C, 0xD3, 0xA8]), ANDN(rcx, r15, qword[r11 + rdx*8 - 88]).encode())
class TestNOT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF6, 0xD3]), NOT(bl).encode())
self.assertEqual(bytearray([0x66, 0xF7, 0xD6]), NOT(si).encode())
self.assertEqual(bytearray([0xF7, 0xD5]), NOT(ebp).encode())
self.assertEqual(bytearray([0x48, 0xF7, 0xD1]), NOT(rcx).encode())
self.assertEqual(bytearray([0x41, 0xF6, 0x54, 0xBE, 0x85]), NOT(byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xF7, 0x54, 0xED, 0x95]), NOT(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0xF7, 0x54, 0xCC, 0x9D]), NOT(dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0xF7, 0x54, 0xD3, 0xA8]), NOT(qword[r11 + rdx*8 - 88]).encode())
class TestNEG(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF6, 0xDB]), NEG(bl).encode())
self.assertEqual(bytearray([0x66, 0xF7, 0xDE]), NEG(si).encode())
self.assertEqual(bytearray([0xF7, 0xDD]), NEG(ebp).encode())
self.assertEqual(bytearray([0x48, 0xF7, 0xD9]), NEG(rcx).encode())
self.assertEqual(bytearray([0x41, 0xF6, 0x5C, 0xBE, 0x85]), NEG(byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xF7, 0x5C, 0xED, 0x95]), NEG(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0xF7, 0x5C, 0xCC, 0x9D]), NEG(dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0xF7, 0x5C, 0xD3, 0xA8]), NEG(qword[r11 + rdx*8 - 88]).encode())
class TestINC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xFE, 0xC3]), INC(bl).encode())
self.assertEqual(bytearray([0x66, 0xFF, 0xC6]), INC(si).encode())
self.assertEqual(bytearray([0xFF, 0xC5]), INC(ebp).encode())
self.assertEqual(bytearray([0x48, 0xFF, 0xC1]), INC(rcx).encode())
self.assertEqual(bytearray([0x41, 0xFE, 0x44, 0xBE, 0x85]), INC(byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xFF, 0x44, 0xED, 0x95]), INC(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0xFF, 0x44, 0xCC, 0x9D]), INC(dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0xFF, 0x44, 0xD3, 0xA8]), INC(qword[r11 + rdx*8 - 88]).encode())
class TestDEC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xFE, 0xCB]), DEC(bl).encode())
self.assertEqual(bytearray([0x66, 0xFF, 0xCE]), DEC(si).encode())
self.assertEqual(bytearray([0xFF, 0xCD]), DEC(ebp).encode())
self.assertEqual(bytearray([0x48, 0xFF, 0xC9]), DEC(rcx).encode())
self.assertEqual(bytearray([0x41, 0xFE, 0x4C, 0xBE, 0x85]), DEC(byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xFF, 0x4C, 0xED, 0x95]), DEC(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0xFF, 0x4C, 0xCC, 0x9D]), DEC(dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0xFF, 0x4C, 0xD3, 0xA8]), DEC(qword[r11 + rdx*8 - 88]).encode())
class TestTEST(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xA8, 0x02]), TEST(al, 2).encode())
self.assertEqual(bytearray([0xF6, 0xC3, 0x02]), TEST(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x84, 0xCB]), TEST(bl, r9b).encode())
self.assertEqual(bytearray([0x66, 0xA9, 0x00, 0x7D]), TEST(ax, 32000).encode())
self.assertEqual(bytearray([0x66, 0xF7, 0xC6, 0x00, 0x7D]), TEST(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x85, 0xE6]), TEST(si, r12w).encode())
self.assertEqual(bytearray([0xA9, 0x00, 0x00, 0x00, 0x10]), TEST(eax, 0x10000000).encode())
self.assertEqual(bytearray([0xF7, 0xC5, 0x00, 0x00, 0x00, 0x10]), TEST(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x85, 0xC5]), TEST(ebp, r8d).encode())
self.assertEqual(bytearray([0x48, 0xA9, 0x00, 0x00, 0x00, 0x10]), TEST(rax, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0xF7, 0xC1, 0x00, 0x00, 0x00, 0x10]), TEST(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x4C, 0x85, 0xF9]), TEST(rcx, r15).encode())
self.assertEqual(bytearray([0x41, 0xF6, 0x44, 0xBE, 0x85, 0x02]), TEST(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x84, 0x4C, 0xBE, 0x85]), TEST(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xF7, 0x44, 0xED, 0x95, 0x00, 0x7D]), TEST(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x85, 0x64, 0xED, 0x95]), TEST(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0xF7, 0x44, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), TEST(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x85, 0x44, 0xCC, 0x9D]), TEST(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0xF7, 0x44, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), TEST(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x85, 0x7C, 0xD3, 0xA8]), TEST(qword[r11 + rdx*8 - 88], r15).encode())
class TestCMP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x3C, 0x02]), CMP(al, 2).encode())
self.assertEqual(bytearray([0x80, 0xFB, 0x02]), CMP(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x38, 0xCB]), CMP(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x3A, 0x5C, 0xBE, 0x85]), CMP(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x3D, 0x00, 0x7D]), CMP(ax, 32000).encode())
self.assertEqual(bytearray([0x66, 0x83, 0xFE, 0x02]), CMP(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x81, 0xFE, 0x00, 0x7D]), CMP(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x39, 0xE6]), CMP(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x3B, 0x74, 0xED, 0x95]), CMP(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x3D, 0x00, 0x00, 0x00, 0x10]), CMP(eax, 0x10000000).encode())
self.assertEqual(bytearray([0x83, 0xFD, 0x02]), CMP(ebp, 2).encode())
self.assertEqual(bytearray([0x81, 0xFD, 0x00, 0x00, 0x00, 0x10]), CMP(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x39, 0xC5]), CMP(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x3B, 0x6C, 0xCC, 0x9D]), CMP(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x48, 0x3D, 0x00, 0x00, 0x00, 0x10]), CMP(rax, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xF9, 0x02]), CMP(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0x81, 0xF9, 0x00, 0x00, 0x00, 0x10]), CMP(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x4C, 0x39, 0xF9]), CMP(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x3B, 0x4C, 0xD3, 0xA8]), CMP(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0x80, 0x7C, 0xBE, 0x85, 0x02]), CMP(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x38, 0x4C, 0xBE, 0x85]), CMP(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x83, 0x7C, 0xED, 0x95, 0x02]), CMP(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x81, 0x7C, 0xED, 0x95, 0x00, 0x7D]), CMP(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x39, 0x64, 0xED, 0x95]), CMP(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x83, 0x7C, 0xCC, 0x9D, 0x02]), CMP(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0x81, 0x7C, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), CMP(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x39, 0x44, 0xCC, 0x9D]), CMP(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x83, 0x7C, 0xD3, 0xA8, 0x02]), CMP(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0x81, 0x7C, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), CMP(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x39, 0x7C, 0xD3, 0xA8]), CMP(qword[r11 + rdx*8 - 88], r15).encode())
class TestMOV(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xB3, 0x02]), MOV(bl, 2).encode())
self.assertEqual(bytearray([0x44, 0x88, 0xCB]), MOV(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x8A, 0x5C, 0xBE, 0x85]), MOV(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0xBE, 0x00, 0x7D]), MOV(si, 32000).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x89, 0xE6]), MOV(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x8B, 0x74, 0xED, 0x95]), MOV(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xBD, 0x00, 0x00, 0x00, 0x10]), MOV(ebp, 0x10000000).encode())
self.assertEqual(bytearray([0x44, 0x89, 0xC5]), MOV(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x8B, 0x6C, 0xCC, 0x9D]), MOV(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x48, 0xC7, 0xC1, 0x00, 0x00, 0x00, 0x10]), MOV(rcx, 0x10000000).encode())
self.assertEqual(bytearray([0x48, 0xB9, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00]), MOV(rcx, 0x100000000).encode())
self.assertEqual(bytearray([0x4C, 0x89, 0xF9]), MOV(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x8B, 0x4C, 0xD3, 0xA8]), MOV(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0xC6, 0x44, 0xBE, 0x85, 0x02]), MOV(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x45, 0x88, 0x4C, 0xBE, 0x85]), MOV(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xC7, 0x44, 0xED, 0x95, 0x00, 0x7D]), MOV(word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x89, 0x64, 0xED, 0x95]), MOV(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0xC7, 0x44, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), MOV(dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x45, 0x89, 0x44, 0xCC, 0x9D]), MOV(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0xC7, 0x44, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), MOV(qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0x4D, 0x89, 0x7C, 0xD3, 0xA8]), MOV(qword[r11 + rdx*8 - 88], r15).encode())
class TestMOVZX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xB6, 0xF1]), MOVZX(si, r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xB6, 0x74, 0xBE, 0x85]), MOVZX(si, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xB6, 0xE9]), MOVZX(ebp, r9b).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xB7, 0xEC]), MOVZX(ebp, r12w).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xB6, 0x6C, 0xBE, 0x85]), MOVZX(ebp, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xB7, 0x6C, 0xED, 0x95]), MOVZX(ebp, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xB6, 0xC9]), MOVZX(rcx, r9b).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xB7, 0xCC]), MOVZX(rcx, r12w).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xB6, 0x4C, 0xBE, 0x85]), MOVZX(rcx, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xB7, 0x4C, 0xED, 0x95]), MOVZX(rcx, word[r13 + rbp*8 - 107]).encode())
class TestMOVSX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBE, 0xF1]), MOVSX(si, r9b).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBE, 0x74, 0xBE, 0x85]), MOVSX(si, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBE, 0xE9]), MOVSX(ebp, r9b).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBF, 0xEC]), MOVSX(ebp, r12w).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBE, 0x6C, 0xBE, 0x85]), MOVSX(ebp, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBF, 0x6C, 0xED, 0x95]), MOVSX(ebp, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBE, 0xC9]), MOVSX(rcx, r9b).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBF, 0xCC]), MOVSX(rcx, r12w).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBE, 0x4C, 0xBE, 0x85]), MOVSX(rcx, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBF, 0x4C, 0xED, 0x95]), MOVSX(rcx, word[r13 + rbp*8 - 107]).encode())
class TestMOVSXD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x49, 0x63, 0xC8]), MOVSXD(rcx, r8d).encode())
self.assertEqual(bytearray([0x49, 0x63, 0x4C, 0xCC, 0x9D]), MOVSXD(rcx, dword[r12 + rcx*8 - 99]).encode())
class TestMOVBE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0xF0, 0x74, 0xED, 0x95]), MOVBE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0xF0, 0x6C, 0xCC, 0x9D]), MOVBE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x38, 0xF0, 0x4C, 0xD3, 0xA8]), MOVBE(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x38, 0xF1, 0x64, 0xED, 0x95]), MOVBE(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0x38, 0xF1, 0x44, 0xCC, 0x9D]), MOVBE(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0x38, 0xF1, 0x7C, 0xD3, 0xA8]), MOVBE(qword[r11 + rdx*8 - 88], r15).encode())
class TestMOVNTI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x45, 0x0F, 0xC3, 0x44, 0xCC, 0x9D]), MOVNTI(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xC3, 0x7C, 0xD3, 0xA8]), MOVNTI(qword[r11 + rdx*8 - 88], r15).encode())
class TestBT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x0F, 0xBA, 0xE6, 0x02]), BT(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xA3, 0xE6]), BT(si, r12w).encode())
self.assertEqual(bytearray([0x0F, 0xBA, 0xE5, 0x02]), BT(ebp, 2).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xA3, 0xC5]), BT(ebp, r8d).encode())
self.assertEqual(bytearray([0x48, 0x0F, 0xBA, 0xE1, 0x02]), BT(rcx, 2).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xA3, 0xF9]), BT(rcx, r15).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBA, 0x64, 0xED, 0x95, 0x02]), BT(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xA3, 0x64, 0xED, 0x95]), BT(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBA, 0x64, 0xCC, 0x9D, 0x02]), BT(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xA3, 0x44, 0xCC, 0x9D]), BT(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBA, 0x64, 0xD3, 0xA8, 0x02]), BT(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xA3, 0x7C, 0xD3, 0xA8]), BT(qword[r11 + rdx*8 - 88], r15).encode())
class TestBTS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x0F, 0xBA, 0xEE, 0x02]), BTS(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xAB, 0xE6]), BTS(si, r12w).encode())
self.assertEqual(bytearray([0x0F, 0xBA, 0xED, 0x02]), BTS(ebp, 2).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xAB, 0xC5]), BTS(ebp, r8d).encode())
self.assertEqual(bytearray([0x48, 0x0F, 0xBA, 0xE9, 0x02]), BTS(rcx, 2).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xAB, 0xF9]), BTS(rcx, r15).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBA, 0x6C, 0xED, 0x95, 0x02]), BTS(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xAB, 0x64, 0xED, 0x95]), BTS(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBA, 0x6C, 0xCC, 0x9D, 0x02]), BTS(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xAB, 0x44, 0xCC, 0x9D]), BTS(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBA, 0x6C, 0xD3, 0xA8, 0x02]), BTS(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xAB, 0x7C, 0xD3, 0xA8]), BTS(qword[r11 + rdx*8 - 88], r15).encode())
class TestBTR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x0F, 0xBA, 0xF6, 0x02]), BTR(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xB3, 0xE6]), BTR(si, r12w).encode())
self.assertEqual(bytearray([0x0F, 0xBA, 0xF5, 0x02]), BTR(ebp, 2).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xB3, 0xC5]), BTR(ebp, r8d).encode())
self.assertEqual(bytearray([0x48, 0x0F, 0xBA, 0xF1, 0x02]), BTR(rcx, 2).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xB3, 0xF9]), BTR(rcx, r15).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBA, 0x74, 0xED, 0x95, 0x02]), BTR(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xB3, 0x64, 0xED, 0x95]), BTR(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBA, 0x74, 0xCC, 0x9D, 0x02]), BTR(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xB3, 0x44, 0xCC, 0x9D]), BTR(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBA, 0x74, 0xD3, 0xA8, 0x02]), BTR(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xB3, 0x7C, 0xD3, 0xA8]), BTR(qword[r11 + rdx*8 - 88], r15).encode())
class TestBTC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x0F, 0xBA, 0xFE, 0x02]), BTC(si, 2).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xBB, 0xE6]), BTC(si, r12w).encode())
self.assertEqual(bytearray([0x0F, 0xBA, 0xFD, 0x02]), BTC(ebp, 2).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xBB, 0xC5]), BTC(ebp, r8d).encode())
self.assertEqual(bytearray([0x48, 0x0F, 0xBA, 0xF9, 0x02]), BTC(rcx, 2).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xBB, 0xF9]), BTC(rcx, r15).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBA, 0x7C, 0xED, 0x95, 0x02]), BTC(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xBB, 0x64, 0xED, 0x95]), BTC(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBA, 0x7C, 0xCC, 0x9D, 0x02]), BTC(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xBB, 0x44, 0xCC, 0x9D]), BTC(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBA, 0x7C, 0xD3, 0xA8, 0x02]), BTC(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xBB, 0x7C, 0xD3, 0xA8]), BTC(qword[r11 + rdx*8 - 88], r15).encode())
class TestPOPCNT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xB8, 0xF4]), POPCNT(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xB8, 0x74, 0xED, 0x95]), POPCNT(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xB8, 0xE8]), POPCNT(ebp, r8d).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xB8, 0x6C, 0xCC, 0x9D]), POPCNT(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xB8, 0xCF]), POPCNT(rcx, r15).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xB8, 0x4C, 0xD3, 0xA8]), POPCNT(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBSWAP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xCD]), BSWAP(ebp).encode())
self.assertEqual(bytearray([0x48, 0x0F, 0xC9]), BSWAP(rcx).encode())
class TestBSF(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBC, 0xF4]), BSF(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBC, 0x74, 0xED, 0x95]), BSF(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBC, 0xE8]), BSF(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBC, 0x6C, 0xCC, 0x9D]), BSF(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBC, 0xCF]), BSF(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBC, 0x4C, 0xD3, 0xA8]), BSF(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBSR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBD, 0xF4]), BSR(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xBD, 0x74, 0xED, 0x95]), BSR(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBD, 0xE8]), BSR(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xBD, 0x6C, 0xCC, 0x9D]), BSR(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBD, 0xCF]), BSR(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xBD, 0x4C, 0xD3, 0xA8]), BSR(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestLZCNT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xBD, 0xF4]), LZCNT(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xBD, 0x74, 0xED, 0x95]), LZCNT(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xBD, 0xE8]), LZCNT(ebp, r8d).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xBD, 0x6C, 0xCC, 0x9D]), LZCNT(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xBD, 0xCF]), LZCNT(rcx, r15).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xBD, 0x4C, 0xD3, 0xA8]), LZCNT(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestTZCNT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xBC, 0xF4]), TZCNT(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xBC, 0x74, 0xED, 0x95]), TZCNT(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xBC, 0xE8]), TZCNT(ebp, r8d).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xBC, 0x6C, 0xCC, 0x9D]), TZCNT(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xBC, 0xCF]), TZCNT(rcx, r15).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xBC, 0x4C, 0xD3, 0xA8]), TZCNT(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestSHR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xD0, 0xEB]), SHR(bl, 1).encode())
self.assertEqual(bytearray([0xC0, 0xEB, 0x02]), SHR(bl, 2).encode())
self.assertEqual(bytearray([0xD2, 0xEB]), SHR(bl, cl).encode())
self.assertEqual(bytearray([0x66, 0xD1, 0xEE]), SHR(si, 1).encode())
self.assertEqual(bytearray([0x66, 0xC1, 0xEE, 0x02]), SHR(si, 2).encode())
self.assertEqual(bytearray([0x66, 0xD3, 0xEE]), SHR(si, cl).encode())
self.assertEqual(bytearray([0xD1, 0xED]), SHR(ebp, 1).encode())
self.assertEqual(bytearray([0xC1, 0xED, 0x02]), SHR(ebp, 2).encode())
self.assertEqual(bytearray([0xD3, 0xED]), SHR(ebp, cl).encode())
self.assertEqual(bytearray([0x48, 0xD1, 0xE9]), SHR(rcx, 1).encode())
self.assertEqual(bytearray([0x48, 0xC1, 0xE9, 0x02]), SHR(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0xD3, 0xE9]), SHR(rcx, cl).encode())
self.assertEqual(bytearray([0x41, 0xD0, 0x6C, 0xBE, 0x85]), SHR(byte[r14 + rdi*4 - 123], 1).encode())
self.assertEqual(bytearray([0x41, 0xC0, 0x6C, 0xBE, 0x85, 0x02]), SHR(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x41, 0xD2, 0x6C, 0xBE, 0x85]), SHR(byte[r14 + rdi*4 - 123], cl).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD1, 0x6C, 0xED, 0x95]), SHR(word[r13 + rbp*8 - 107], 1).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xC1, 0x6C, 0xED, 0x95, 0x02]), SHR(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD3, 0x6C, 0xED, 0x95]), SHR(word[r13 + rbp*8 - 107], cl).encode())
self.assertEqual(bytearray([0x41, 0xD1, 0x6C, 0xCC, 0x9D]), SHR(dword[r12 + rcx*8 - 99], 1).encode())
self.assertEqual(bytearray([0x41, 0xC1, 0x6C, 0xCC, 0x9D, 0x02]), SHR(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0xD3, 0x6C, 0xCC, 0x9D]), SHR(dword[r12 + rcx*8 - 99], cl).encode())
self.assertEqual(bytearray([0x49, 0xD1, 0x6C, 0xD3, 0xA8]), SHR(qword[r11 + rdx*8 - 88], 1).encode())
self.assertEqual(bytearray([0x49, 0xC1, 0x6C, 0xD3, 0xA8, 0x02]), SHR(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0xD3, 0x6C, 0xD3, 0xA8]), SHR(qword[r11 + rdx*8 - 88], cl).encode())
class TestSAR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xD0, 0xFB]), SAR(bl, 1).encode())
self.assertEqual(bytearray([0xC0, 0xFB, 0x02]), SAR(bl, 2).encode())
self.assertEqual(bytearray([0xD2, 0xFB]), SAR(bl, cl).encode())
self.assertEqual(bytearray([0x66, 0xD1, 0xFE]), SAR(si, 1).encode())
self.assertEqual(bytearray([0x66, 0xC1, 0xFE, 0x02]), SAR(si, 2).encode())
self.assertEqual(bytearray([0x66, 0xD3, 0xFE]), SAR(si, cl).encode())
self.assertEqual(bytearray([0xD1, 0xFD]), SAR(ebp, 1).encode())
self.assertEqual(bytearray([0xC1, 0xFD, 0x02]), SAR(ebp, 2).encode())
self.assertEqual(bytearray([0xD3, 0xFD]), SAR(ebp, cl).encode())
self.assertEqual(bytearray([0x48, 0xD1, 0xF9]), SAR(rcx, 1).encode())
self.assertEqual(bytearray([0x48, 0xC1, 0xF9, 0x02]), SAR(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0xD3, 0xF9]), SAR(rcx, cl).encode())
self.assertEqual(bytearray([0x41, 0xD0, 0x7C, 0xBE, 0x85]), SAR(byte[r14 + rdi*4 - 123], 1).encode())
self.assertEqual(bytearray([0x41, 0xC0, 0x7C, 0xBE, 0x85, 0x02]), SAR(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x41, 0xD2, 0x7C, 0xBE, 0x85]), SAR(byte[r14 + rdi*4 - 123], cl).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD1, 0x7C, 0xED, 0x95]), SAR(word[r13 + rbp*8 - 107], 1).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xC1, 0x7C, 0xED, 0x95, 0x02]), SAR(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD3, 0x7C, 0xED, 0x95]), SAR(word[r13 + rbp*8 - 107], cl).encode())
self.assertEqual(bytearray([0x41, 0xD1, 0x7C, 0xCC, 0x9D]), SAR(dword[r12 + rcx*8 - 99], 1).encode())
self.assertEqual(bytearray([0x41, 0xC1, 0x7C, 0xCC, 0x9D, 0x02]), SAR(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0xD3, 0x7C, 0xCC, 0x9D]), SAR(dword[r12 + rcx*8 - 99], cl).encode())
self.assertEqual(bytearray([0x49, 0xD1, 0x7C, 0xD3, 0xA8]), SAR(qword[r11 + rdx*8 - 88], 1).encode())
self.assertEqual(bytearray([0x49, 0xC1, 0x7C, 0xD3, 0xA8, 0x02]), SAR(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0xD3, 0x7C, 0xD3, 0xA8]), SAR(qword[r11 + rdx*8 - 88], cl).encode())
class TestSHL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xD0, 0xE3]), SHL(bl, 1).encode())
self.assertEqual(bytearray([0xC0, 0xE3, 0x02]), SHL(bl, 2).encode())
self.assertEqual(bytearray([0xD2, 0xE3]), SHL(bl, cl).encode())
self.assertEqual(bytearray([0x66, 0xD1, 0xE6]), SHL(si, 1).encode())
self.assertEqual(bytearray([0x66, 0xC1, 0xE6, 0x02]), SHL(si, 2).encode())
self.assertEqual(bytearray([0x66, 0xD3, 0xE6]), SHL(si, cl).encode())
self.assertEqual(bytearray([0xD1, 0xE5]), SHL(ebp, 1).encode())
self.assertEqual(bytearray([0xC1, 0xE5, 0x02]), SHL(ebp, 2).encode())
self.assertEqual(bytearray([0xD3, 0xE5]), SHL(ebp, cl).encode())
self.assertEqual(bytearray([0x48, 0xD1, 0xE1]), SHL(rcx, 1).encode())
self.assertEqual(bytearray([0x48, 0xC1, 0xE1, 0x02]), SHL(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0xD3, 0xE1]), SHL(rcx, cl).encode())
self.assertEqual(bytearray([0x41, 0xD0, 0x64, 0xBE, 0x85]), SHL(byte[r14 + rdi*4 - 123], 1).encode())
self.assertEqual(bytearray([0x41, 0xC0, 0x64, 0xBE, 0x85, 0x02]), SHL(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x41, 0xD2, 0x64, 0xBE, 0x85]), SHL(byte[r14 + rdi*4 - 123], cl).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD1, 0x64, 0xED, 0x95]), SHL(word[r13 + rbp*8 - 107], 1).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xC1, 0x64, 0xED, 0x95, 0x02]), SHL(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD3, 0x64, 0xED, 0x95]), SHL(word[r13 + rbp*8 - 107], cl).encode())
self.assertEqual(bytearray([0x41, 0xD1, 0x64, 0xCC, 0x9D]), SHL(dword[r12 + rcx*8 - 99], 1).encode())
self.assertEqual(bytearray([0x41, 0xC1, 0x64, 0xCC, 0x9D, 0x02]), SHL(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0xD3, 0x64, 0xCC, 0x9D]), SHL(dword[r12 + rcx*8 - 99], cl).encode())
self.assertEqual(bytearray([0x49, 0xD1, 0x64, 0xD3, 0xA8]), SHL(qword[r11 + rdx*8 - 88], 1).encode())
self.assertEqual(bytearray([0x49, 0xC1, 0x64, 0xD3, 0xA8, 0x02]), SHL(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0xD3, 0x64, 0xD3, 0xA8]), SHL(qword[r11 + rdx*8 - 88], cl).encode())
class TestSAL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xD0, 0xE3]), SAL(bl, 1).encode())
self.assertEqual(bytearray([0xC0, 0xE3, 0x02]), SAL(bl, 2).encode())
self.assertEqual(bytearray([0xD2, 0xE3]), SAL(bl, cl).encode())
self.assertEqual(bytearray([0x66, 0xD1, 0xE6]), SAL(si, 1).encode())
self.assertEqual(bytearray([0x66, 0xC1, 0xE6, 0x02]), SAL(si, 2).encode())
self.assertEqual(bytearray([0x66, 0xD3, 0xE6]), SAL(si, cl).encode())
self.assertEqual(bytearray([0xD1, 0xE5]), SAL(ebp, 1).encode())
self.assertEqual(bytearray([0xC1, 0xE5, 0x02]), SAL(ebp, 2).encode())
self.assertEqual(bytearray([0xD3, 0xE5]), SAL(ebp, cl).encode())
self.assertEqual(bytearray([0x48, 0xD1, 0xE1]), SAL(rcx, 1).encode())
self.assertEqual(bytearray([0x48, 0xC1, 0xE1, 0x02]), SAL(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0xD3, 0xE1]), SAL(rcx, cl).encode())
self.assertEqual(bytearray([0x41, 0xD0, 0x64, 0xBE, 0x85]), SAL(byte[r14 + rdi*4 - 123], 1).encode())
self.assertEqual(bytearray([0x41, 0xC0, 0x64, 0xBE, 0x85, 0x02]), SAL(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x41, 0xD2, 0x64, 0xBE, 0x85]), SAL(byte[r14 + rdi*4 - 123], cl).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD1, 0x64, 0xED, 0x95]), SAL(word[r13 + rbp*8 - 107], 1).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xC1, 0x64, 0xED, 0x95, 0x02]), SAL(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD3, 0x64, 0xED, 0x95]), SAL(word[r13 + rbp*8 - 107], cl).encode())
self.assertEqual(bytearray([0x41, 0xD1, 0x64, 0xCC, 0x9D]), SAL(dword[r12 + rcx*8 - 99], 1).encode())
self.assertEqual(bytearray([0x41, 0xC1, 0x64, 0xCC, 0x9D, 0x02]), SAL(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0xD3, 0x64, 0xCC, 0x9D]), SAL(dword[r12 + rcx*8 - 99], cl).encode())
self.assertEqual(bytearray([0x49, 0xD1, 0x64, 0xD3, 0xA8]), SAL(qword[r11 + rdx*8 - 88], 1).encode())
self.assertEqual(bytearray([0x49, 0xC1, 0x64, 0xD3, 0xA8, 0x02]), SAL(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0xD3, 0x64, 0xD3, 0xA8]), SAL(qword[r11 + rdx*8 - 88], cl).encode())
class TestSHRX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x7B, 0xF7, 0xE8]), SHRX(ebp, r8d, eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7B, 0xF7, 0x6C, 0xCC, 0x9D]), SHRX(ebp, dword[r12 + rcx*8 - 99], eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xFB, 0xF7, 0xCF]), SHRX(rcx, r15, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xFB, 0xF7, 0x4C, 0xD3, 0xA8]), SHRX(rcx, qword[r11 + rdx*8 - 88], rax).encode())
class TestSARX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x7A, 0xF7, 0xE8]), SARX(ebp, r8d, eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x7A, 0xF7, 0x6C, 0xCC, 0x9D]), SARX(ebp, dword[r12 + rcx*8 - 99], eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xFA, 0xF7, 0xCF]), SARX(rcx, r15, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xFA, 0xF7, 0x4C, 0xD3, 0xA8]), SARX(rcx, qword[r11 + rdx*8 - 88], rax).encode())
class TestSHLX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0xF7, 0xE8]), SHLX(ebp, r8d, eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x79, 0xF7, 0x6C, 0xCC, 0x9D]), SHLX(ebp, dword[r12 + rcx*8 - 99], eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF9, 0xF7, 0xCF]), SHLX(rcx, r15, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF9, 0xF7, 0x4C, 0xD3, 0xA8]), SHLX(rcx, qword[r11 + rdx*8 - 88], rax).encode())
class TestSHRD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xAC, 0xE6, 0x02]), SHRD(si, r12w, 2).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xAD, 0xE6]), SHRD(si, r12w, cl).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xAC, 0xC5, 0x02]), SHRD(ebp, r8d, 2).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xAD, 0xC5]), SHRD(ebp, r8d, cl).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xAC, 0xF9, 0x02]), SHRD(rcx, r15, 2).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xAD, 0xF9]), SHRD(rcx, r15, cl).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xAC, 0x64, 0xED, 0x95, 0x02]), SHRD(word[r13 + rbp*8 - 107], r12w, 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xAD, 0x64, 0xED, 0x95]), SHRD(word[r13 + rbp*8 - 107], r12w, cl).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xAC, 0x44, 0xCC, 0x9D, 0x02]), SHRD(dword[r12 + rcx*8 - 99], r8d, 2).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xAD, 0x44, 0xCC, 0x9D]), SHRD(dword[r12 + rcx*8 - 99], r8d, cl).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xAC, 0x7C, 0xD3, 0xA8, 0x02]), SHRD(qword[r11 + rdx*8 - 88], r15, 2).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xAD, 0x7C, 0xD3, 0xA8]), SHRD(qword[r11 + rdx*8 - 88], r15, cl).encode())
class TestSHLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xA4, 0xE6, 0x02]), SHLD(si, r12w, 2).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xA5, 0xE6]), SHLD(si, r12w, cl).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xA4, 0xC5, 0x02]), SHLD(ebp, r8d, 2).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xA5, 0xC5]), SHLD(ebp, r8d, cl).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xA4, 0xF9, 0x02]), SHLD(rcx, r15, 2).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xA5, 0xF9]), SHLD(rcx, r15, cl).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xA4, 0x64, 0xED, 0x95, 0x02]), SHLD(word[r13 + rbp*8 - 107], r12w, 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xA5, 0x64, 0xED, 0x95]), SHLD(word[r13 + rbp*8 - 107], r12w, cl).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xA4, 0x44, 0xCC, 0x9D, 0x02]), SHLD(dword[r12 + rcx*8 - 99], r8d, 2).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xA5, 0x44, 0xCC, 0x9D]), SHLD(dword[r12 + rcx*8 - 99], r8d, cl).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xA4, 0x7C, 0xD3, 0xA8, 0x02]), SHLD(qword[r11 + rdx*8 - 88], r15, 2).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xA5, 0x7C, 0xD3, 0xA8]), SHLD(qword[r11 + rdx*8 - 88], r15, cl).encode())
class TestROR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xD0, 0xCB]), ROR(bl, 1).encode())
self.assertEqual(bytearray([0xC0, 0xCB, 0x02]), ROR(bl, 2).encode())
self.assertEqual(bytearray([0xD2, 0xCB]), ROR(bl, cl).encode())
self.assertEqual(bytearray([0x66, 0xD1, 0xCE]), ROR(si, 1).encode())
self.assertEqual(bytearray([0x66, 0xC1, 0xCE, 0x02]), ROR(si, 2).encode())
self.assertEqual(bytearray([0x66, 0xD3, 0xCE]), ROR(si, cl).encode())
self.assertEqual(bytearray([0xD1, 0xCD]), ROR(ebp, 1).encode())
self.assertEqual(bytearray([0xC1, 0xCD, 0x02]), ROR(ebp, 2).encode())
self.assertEqual(bytearray([0xD3, 0xCD]), ROR(ebp, cl).encode())
self.assertEqual(bytearray([0x48, 0xD1, 0xC9]), ROR(rcx, 1).encode())
self.assertEqual(bytearray([0x48, 0xC1, 0xC9, 0x02]), ROR(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0xD3, 0xC9]), ROR(rcx, cl).encode())
self.assertEqual(bytearray([0x41, 0xD0, 0x4C, 0xBE, 0x85]), ROR(byte[r14 + rdi*4 - 123], 1).encode())
self.assertEqual(bytearray([0x41, 0xC0, 0x4C, 0xBE, 0x85, 0x02]), ROR(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x41, 0xD2, 0x4C, 0xBE, 0x85]), ROR(byte[r14 + rdi*4 - 123], cl).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD1, 0x4C, 0xED, 0x95]), ROR(word[r13 + rbp*8 - 107], 1).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xC1, 0x4C, 0xED, 0x95, 0x02]), ROR(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD3, 0x4C, 0xED, 0x95]), ROR(word[r13 + rbp*8 - 107], cl).encode())
self.assertEqual(bytearray([0x41, 0xD1, 0x4C, 0xCC, 0x9D]), ROR(dword[r12 + rcx*8 - 99], 1).encode())
self.assertEqual(bytearray([0x41, 0xC1, 0x4C, 0xCC, 0x9D, 0x02]), ROR(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0xD3, 0x4C, 0xCC, 0x9D]), ROR(dword[r12 + rcx*8 - 99], cl).encode())
self.assertEqual(bytearray([0x49, 0xD1, 0x4C, 0xD3, 0xA8]), ROR(qword[r11 + rdx*8 - 88], 1).encode())
self.assertEqual(bytearray([0x49, 0xC1, 0x4C, 0xD3, 0xA8, 0x02]), ROR(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0xD3, 0x4C, 0xD3, 0xA8]), ROR(qword[r11 + rdx*8 - 88], cl).encode())
class TestROL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xD0, 0xC3]), ROL(bl, 1).encode())
self.assertEqual(bytearray([0xC0, 0xC3, 0x02]), ROL(bl, 2).encode())
self.assertEqual(bytearray([0xD2, 0xC3]), ROL(bl, cl).encode())
self.assertEqual(bytearray([0x66, 0xD1, 0xC6]), ROL(si, 1).encode())
self.assertEqual(bytearray([0x66, 0xC1, 0xC6, 0x02]), ROL(si, 2).encode())
self.assertEqual(bytearray([0x66, 0xD3, 0xC6]), ROL(si, cl).encode())
self.assertEqual(bytearray([0xD1, 0xC5]), ROL(ebp, 1).encode())
self.assertEqual(bytearray([0xC1, 0xC5, 0x02]), ROL(ebp, 2).encode())
self.assertEqual(bytearray([0xD3, 0xC5]), ROL(ebp, cl).encode())
self.assertEqual(bytearray([0x48, 0xD1, 0xC1]), ROL(rcx, 1).encode())
self.assertEqual(bytearray([0x48, 0xC1, 0xC1, 0x02]), ROL(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0xD3, 0xC1]), ROL(rcx, cl).encode())
self.assertEqual(bytearray([0x41, 0xD0, 0x44, 0xBE, 0x85]), ROL(byte[r14 + rdi*4 - 123], 1).encode())
self.assertEqual(bytearray([0x41, 0xC0, 0x44, 0xBE, 0x85, 0x02]), ROL(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x41, 0xD2, 0x44, 0xBE, 0x85]), ROL(byte[r14 + rdi*4 - 123], cl).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD1, 0x44, 0xED, 0x95]), ROL(word[r13 + rbp*8 - 107], 1).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xC1, 0x44, 0xED, 0x95, 0x02]), ROL(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD3, 0x44, 0xED, 0x95]), ROL(word[r13 + rbp*8 - 107], cl).encode())
self.assertEqual(bytearray([0x41, 0xD1, 0x44, 0xCC, 0x9D]), ROL(dword[r12 + rcx*8 - 99], 1).encode())
self.assertEqual(bytearray([0x41, 0xC1, 0x44, 0xCC, 0x9D, 0x02]), ROL(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0xD3, 0x44, 0xCC, 0x9D]), ROL(dword[r12 + rcx*8 - 99], cl).encode())
self.assertEqual(bytearray([0x49, 0xD1, 0x44, 0xD3, 0xA8]), ROL(qword[r11 + rdx*8 - 88], 1).encode())
self.assertEqual(bytearray([0x49, 0xC1, 0x44, 0xD3, 0xA8, 0x02]), ROL(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0xD3, 0x44, 0xD3, 0xA8]), ROL(qword[r11 + rdx*8 - 88], cl).encode())
class TestRORX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x7B, 0xF0, 0xE8, 0x02]), RORX(ebp, r8d, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x7B, 0xF0, 0x6C, 0xCC, 0x9D, 0x02]), RORX(ebp, dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0xFB, 0xF0, 0xCF, 0x02]), RORX(rcx, r15, 2).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0xFB, 0xF0, 0x4C, 0xD3, 0xA8, 0x02]), RORX(rcx, qword[r11 + rdx*8 - 88], 2).encode())
class TestRCR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xD0, 0xDB]), RCR(bl, 1).encode())
self.assertEqual(bytearray([0xC0, 0xDB, 0x02]), RCR(bl, 2).encode())
self.assertEqual(bytearray([0xD2, 0xDB]), RCR(bl, cl).encode())
self.assertEqual(bytearray([0x66, 0xD1, 0xDE]), RCR(si, 1).encode())
self.assertEqual(bytearray([0x66, 0xC1, 0xDE, 0x02]), RCR(si, 2).encode())
self.assertEqual(bytearray([0x66, 0xD3, 0xDE]), RCR(si, cl).encode())
self.assertEqual(bytearray([0xD1, 0xDD]), RCR(ebp, 1).encode())
self.assertEqual(bytearray([0xC1, 0xDD, 0x02]), RCR(ebp, 2).encode())
self.assertEqual(bytearray([0xD3, 0xDD]), RCR(ebp, cl).encode())
self.assertEqual(bytearray([0x48, 0xD1, 0xD9]), RCR(rcx, 1).encode())
self.assertEqual(bytearray([0x48, 0xC1, 0xD9, 0x02]), RCR(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0xD3, 0xD9]), RCR(rcx, cl).encode())
self.assertEqual(bytearray([0x41, 0xD0, 0x5C, 0xBE, 0x85]), RCR(byte[r14 + rdi*4 - 123], 1).encode())
self.assertEqual(bytearray([0x41, 0xC0, 0x5C, 0xBE, 0x85, 0x02]), RCR(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x41, 0xD2, 0x5C, 0xBE, 0x85]), RCR(byte[r14 + rdi*4 - 123], cl).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD1, 0x5C, 0xED, 0x95]), RCR(word[r13 + rbp*8 - 107], 1).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xC1, 0x5C, 0xED, 0x95, 0x02]), RCR(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD3, 0x5C, 0xED, 0x95]), RCR(word[r13 + rbp*8 - 107], cl).encode())
self.assertEqual(bytearray([0x41, 0xD1, 0x5C, 0xCC, 0x9D]), RCR(dword[r12 + rcx*8 - 99], 1).encode())
self.assertEqual(bytearray([0x41, 0xC1, 0x5C, 0xCC, 0x9D, 0x02]), RCR(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0xD3, 0x5C, 0xCC, 0x9D]), RCR(dword[r12 + rcx*8 - 99], cl).encode())
self.assertEqual(bytearray([0x49, 0xD1, 0x5C, 0xD3, 0xA8]), RCR(qword[r11 + rdx*8 - 88], 1).encode())
self.assertEqual(bytearray([0x49, 0xC1, 0x5C, 0xD3, 0xA8, 0x02]), RCR(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0xD3, 0x5C, 0xD3, 0xA8]), RCR(qword[r11 + rdx*8 - 88], cl).encode())
class TestRCL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xD0, 0xD3]), RCL(bl, 1).encode())
self.assertEqual(bytearray([0xC0, 0xD3, 0x02]), RCL(bl, 2).encode())
self.assertEqual(bytearray([0xD2, 0xD3]), RCL(bl, cl).encode())
self.assertEqual(bytearray([0x66, 0xD1, 0xD6]), RCL(si, 1).encode())
self.assertEqual(bytearray([0x66, 0xC1, 0xD6, 0x02]), RCL(si, 2).encode())
self.assertEqual(bytearray([0x66, 0xD3, 0xD6]), RCL(si, cl).encode())
self.assertEqual(bytearray([0xD1, 0xD5]), RCL(ebp, 1).encode())
self.assertEqual(bytearray([0xC1, 0xD5, 0x02]), RCL(ebp, 2).encode())
self.assertEqual(bytearray([0xD3, 0xD5]), RCL(ebp, cl).encode())
self.assertEqual(bytearray([0x48, 0xD1, 0xD1]), RCL(rcx, 1).encode())
self.assertEqual(bytearray([0x48, 0xC1, 0xD1, 0x02]), RCL(rcx, 2).encode())
self.assertEqual(bytearray([0x48, 0xD3, 0xD1]), RCL(rcx, cl).encode())
self.assertEqual(bytearray([0x41, 0xD0, 0x54, 0xBE, 0x85]), RCL(byte[r14 + rdi*4 - 123], 1).encode())
self.assertEqual(bytearray([0x41, 0xC0, 0x54, 0xBE, 0x85, 0x02]), RCL(byte[r14 + rdi*4 - 123], 2).encode())
self.assertEqual(bytearray([0x41, 0xD2, 0x54, 0xBE, 0x85]), RCL(byte[r14 + rdi*4 - 123], cl).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD1, 0x54, 0xED, 0x95]), RCL(word[r13 + rbp*8 - 107], 1).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xC1, 0x54, 0xED, 0x95, 0x02]), RCL(word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xD3, 0x54, 0xED, 0x95]), RCL(word[r13 + rbp*8 - 107], cl).encode())
self.assertEqual(bytearray([0x41, 0xD1, 0x54, 0xCC, 0x9D]), RCL(dword[r12 + rcx*8 - 99], 1).encode())
self.assertEqual(bytearray([0x41, 0xC1, 0x54, 0xCC, 0x9D, 0x02]), RCL(dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0xD3, 0x54, 0xCC, 0x9D]), RCL(dword[r12 + rcx*8 - 99], cl).encode())
self.assertEqual(bytearray([0x49, 0xD1, 0x54, 0xD3, 0xA8]), RCL(qword[r11 + rdx*8 - 88], 1).encode())
self.assertEqual(bytearray([0x49, 0xC1, 0x54, 0xD3, 0xA8, 0x02]), RCL(qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0xD3, 0x54, 0xD3, 0xA8]), RCL(qword[r11 + rdx*8 - 88], cl).encode())
class TestIMUL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF6, 0xEB]), IMUL(bl).encode())
self.assertEqual(bytearray([0x66, 0xF7, 0xEE]), IMUL(si).encode())
self.assertEqual(bytearray([0xF7, 0xED]), IMUL(ebp).encode())
self.assertEqual(bytearray([0x48, 0xF7, 0xE9]), IMUL(rcx).encode())
self.assertEqual(bytearray([0x41, 0xF6, 0x6C, 0xBE, 0x85]), IMUL(byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xF7, 0x6C, 0xED, 0x95]), IMUL(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0xF7, 0x6C, 0xCC, 0x9D]), IMUL(dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0xF7, 0x6C, 0xD3, 0xA8]), IMUL(qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xAF, 0xF4]), IMUL(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xAF, 0x74, 0xED, 0x95]), IMUL(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xAF, 0xE8]), IMUL(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xAF, 0x6C, 0xCC, 0x9D]), IMUL(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xAF, 0xCF]), IMUL(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0xAF, 0x4C, 0xD3, 0xA8]), IMUL(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x6B, 0xF4, 0x02]), IMUL(si, r12w, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x69, 0xF4, 0x00, 0x7D]), IMUL(si, r12w, 32000).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x6B, 0x74, 0xED, 0x95, 0x02]), IMUL(si, word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x69, 0x74, 0xED, 0x95, 0x00, 0x7D]), IMUL(si, word[r13 + rbp*8 - 107], 32000).encode())
self.assertEqual(bytearray([0x41, 0x6B, 0xE8, 0x02]), IMUL(ebp, r8d, 2).encode())
self.assertEqual(bytearray([0x41, 0x69, 0xE8, 0x00, 0x00, 0x00, 0x10]), IMUL(ebp, r8d, 0x10000000).encode())
self.assertEqual(bytearray([0x41, 0x6B, 0x6C, 0xCC, 0x9D, 0x02]), IMUL(ebp, dword[r12 + rcx*8 - 99], 2).encode())
self.assertEqual(bytearray([0x41, 0x69, 0x6C, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), IMUL(ebp, dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0x49, 0x6B, 0xCF, 0x02]), IMUL(rcx, r15, 2).encode())
self.assertEqual(bytearray([0x49, 0x69, 0xCF, 0x00, 0x00, 0x00, 0x10]), IMUL(rcx, r15, 0x10000000).encode())
self.assertEqual(bytearray([0x49, 0x6B, 0x4C, 0xD3, 0xA8, 0x02]), IMUL(rcx, qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x49, 0x69, 0x4C, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), IMUL(rcx, qword[r11 + rdx*8 - 88], 0x10000000).encode())
class TestMUL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF6, 0xE3]), MUL(bl).encode())
self.assertEqual(bytearray([0x66, 0xF7, 0xE6]), MUL(si).encode())
self.assertEqual(bytearray([0xF7, 0xE5]), MUL(ebp).encode())
self.assertEqual(bytearray([0x48, 0xF7, 0xE1]), MUL(rcx).encode())
self.assertEqual(bytearray([0x41, 0xF6, 0x64, 0xBE, 0x85]), MUL(byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xF7, 0x64, 0xED, 0x95]), MUL(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0xF7, 0x64, 0xCC, 0x9D]), MUL(dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0xF7, 0x64, 0xD3, 0xA8]), MUL(qword[r11 + rdx*8 - 88]).encode())
class TestMULX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x3B, 0xF6, 0xE8]), MULX(ebp, r8d, eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x3B, 0xF6, 0x6C, 0xCC, 0x9D]), MULX(ebp, r8d, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x83, 0xF6, 0xC8]), MULX(rcx, r15, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x83, 0xF6, 0x4C, 0xD3, 0xA8]), MULX(rcx, r15, qword[r11 + rdx*8 - 88]).encode())
class TestIDIV(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF6, 0xFB]), IDIV(bl).encode())
self.assertEqual(bytearray([0x66, 0xF7, 0xFE]), IDIV(si).encode())
self.assertEqual(bytearray([0xF7, 0xFD]), IDIV(ebp).encode())
self.assertEqual(bytearray([0x48, 0xF7, 0xF9]), IDIV(rcx).encode())
self.assertEqual(bytearray([0x41, 0xF6, 0x7C, 0xBE, 0x85]), IDIV(byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xF7, 0x7C, 0xED, 0x95]), IDIV(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0xF7, 0x7C, 0xCC, 0x9D]), IDIV(dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0xF7, 0x7C, 0xD3, 0xA8]), IDIV(qword[r11 + rdx*8 - 88]).encode())
class TestDIV(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF6, 0xF3]), DIV(bl).encode())
self.assertEqual(bytearray([0x66, 0xF7, 0xF6]), DIV(si).encode())
self.assertEqual(bytearray([0xF7, 0xF5]), DIV(ebp).encode())
self.assertEqual(bytearray([0x48, 0xF7, 0xF1]), DIV(rcx).encode())
self.assertEqual(bytearray([0x41, 0xF6, 0x74, 0xBE, 0x85]), DIV(byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xF7, 0x74, 0xED, 0x95]), DIV(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0xF7, 0x74, 0xCC, 0x9D]), DIV(dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0xF7, 0x74, 0xD3, 0xA8]), DIV(qword[r11 + rdx*8 - 88]).encode())
class TestLEA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x8D, 0x74, 0xF7, 0x80]), LEA(si, [r15 + rsi*8 - 128]).encode())
self.assertEqual(bytearray([0x41, 0x8D, 0x6C, 0xF7, 0x80]), LEA(ebp, [r15 + rsi*8 - 128]).encode())
self.assertEqual(bytearray([0x49, 0x8D, 0x4C, 0xF7, 0x80]), LEA(rcx, [r15 + rsi*8 - 128]).encode())
class TestPUSH(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x6A, 0x02]), PUSH(2).encode())
self.assertEqual(bytearray([0x68, 0x00, 0x00, 0x00, 0x10]), PUSH(0x10000000).encode())
self.assertEqual(bytearray([0x66, 0x56]), PUSH(si).encode())
self.assertEqual(bytearray([0x51]), PUSH(rcx).encode())
self.assertEqual(bytearray([0x66, 0x41, 0xFF, 0x74, 0xED, 0x95]), PUSH(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0xFF, 0x74, 0xD3, 0xA8]), PUSH(qword[r11 + rdx*8 - 88]).encode())
class TestPOP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x5E]), POP(si).encode())
self.assertEqual(bytearray([0x59]), POP(rcx).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x8F, 0x44, 0xED, 0x95]), POP(word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x8F, 0x44, 0xD3, 0xA8]), POP(qword[r11 + rdx*8 - 88]).encode())
class TestPOPCNT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xB8, 0xF4]), POPCNT(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xB8, 0x74, 0xED, 0x95]), POPCNT(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xB8, 0xE8]), POPCNT(ebp, r8d).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xB8, 0x6C, 0xCC, 0x9D]), POPCNT(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xB8, 0xCF]), POPCNT(rcx, r15).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xB8, 0x4C, 0xD3, 0xA8]), POPCNT(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestLZCNT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xBD, 0xF4]), LZCNT(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xBD, 0x74, 0xED, 0x95]), LZCNT(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xBD, 0xE8]), LZCNT(ebp, r8d).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xBD, 0x6C, 0xCC, 0x9D]), LZCNT(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xBD, 0xCF]), LZCNT(rcx, r15).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xBD, 0x4C, 0xD3, 0xA8]), LZCNT(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestTZCNT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xBC, 0xF4]), TZCNT(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0xF3, 0x41, 0x0F, 0xBC, 0x74, 0xED, 0x95]), TZCNT(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xBC, 0xE8]), TZCNT(ebp, r8d).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xBC, 0x6C, 0xCC, 0x9D]), TZCNT(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xBC, 0xCF]), TZCNT(rcx, r15).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0xBC, 0x4C, 0xD3, 0xA8]), TZCNT(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBEXTR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xCA, 0x78, 0x10, 0xE8, 0x00, 0x00, 0x00, 0x10]), BEXTR(ebp, r8d, 0x10000000).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x78, 0xF7, 0xE8]), BEXTR(ebp, r8d, eax).encode())
self.assertEqual(bytearray([0x8F, 0xCA, 0x78, 0x10, 0x6C, 0xCC, 0x9D, 0x00, 0x00, 0x00, 0x10]), BEXTR(ebp, dword[r12 + rcx*8 - 99], 0x10000000).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x78, 0xF7, 0x6C, 0xCC, 0x9D]), BEXTR(ebp, dword[r12 + rcx*8 - 99], eax).encode())
self.assertEqual(bytearray([0x8F, 0xCA, 0xF8, 0x10, 0xCF, 0x00, 0x00, 0x00, 0x10]), BEXTR(rcx, r15, 0x10000000).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF8, 0xF7, 0xCF]), BEXTR(rcx, r15, rax).encode())
self.assertEqual(bytearray([0x8F, 0xCA, 0xF8, 0x10, 0x4C, 0xD3, 0xA8, 0x00, 0x00, 0x00, 0x10]), BEXTR(rcx, qword[r11 + rdx*8 - 88], 0x10000000).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF8, 0xF7, 0x4C, 0xD3, 0xA8]), BEXTR(rcx, qword[r11 + rdx*8 - 88], rax).encode())
class TestPDEP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x3B, 0xF5, 0xE8]), PDEP(ebp, r8d, eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x3B, 0xF5, 0x6C, 0xCC, 0x9D]), PDEP(ebp, r8d, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x83, 0xF5, 0xC8]), PDEP(rcx, r15, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x83, 0xF5, 0x4C, 0xD3, 0xA8]), PDEP(rcx, r15, qword[r11 + rdx*8 - 88]).encode())
class TestPEXT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE2, 0x3A, 0xF5, 0xE8]), PEXT(ebp, r8d, eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x3A, 0xF5, 0x6C, 0xCC, 0x9D]), PEXT(ebp, r8d, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x82, 0xF5, 0xC8]), PEXT(rcx, r15, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x82, 0xF5, 0x4C, 0xD3, 0xA8]), PEXT(rcx, r15, qword[r11 + rdx*8 - 88]).encode())
class TestBZHI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x78, 0xF5, 0xE8]), BZHI(ebp, r8d, eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x78, 0xF5, 0x6C, 0xCC, 0x9D]), BZHI(ebp, dword[r12 + rcx*8 - 99], eax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF8, 0xF5, 0xCF]), BZHI(rcx, r15, rax).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF8, 0xF5, 0x4C, 0xD3, 0xA8]), BZHI(rcx, qword[r11 + rdx*8 - 88], rax).encode())
class TestBLCFILL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0xC8]), BLCFILL(ebp, r8d).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0x4C, 0xCC, 0x9D]), BLCFILL(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0xCF]), BLCFILL(rcx, r15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0x4C, 0xD3, 0xA8]), BLCFILL(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBLCI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x02, 0xF0]), BLCI(ebp, r8d).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x02, 0x74, 0xCC, 0x9D]), BLCI(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x02, 0xF7]), BLCI(rcx, r15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x02, 0x74, 0xD3, 0xA8]), BLCI(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBLCIC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0xE8]), BLCIC(ebp, r8d).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0x6C, 0xCC, 0x9D]), BLCIC(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0xEF]), BLCIC(rcx, r15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0x6C, 0xD3, 0xA8]), BLCIC(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBLCMSK(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x02, 0xC8]), BLCMSK(ebp, r8d).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x02, 0x4C, 0xCC, 0x9D]), BLCMSK(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x02, 0xCF]), BLCMSK(rcx, r15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x02, 0x4C, 0xD3, 0xA8]), BLCMSK(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBLCS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0xD8]), BLCS(ebp, r8d).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0x5C, 0xCC, 0x9D]), BLCS(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0xDF]), BLCS(rcx, r15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0x5C, 0xD3, 0xA8]), BLCS(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBLSFILL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0xD0]), BLSFILL(ebp, r8d).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0x54, 0xCC, 0x9D]), BLSFILL(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0xD7]), BLSFILL(rcx, r15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0x54, 0xD3, 0xA8]), BLSFILL(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBLSI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x50, 0xF3, 0xD8]), BLSI(ebp, r8d).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x50, 0xF3, 0x5C, 0xCC, 0x9D]), BLSI(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF0, 0xF3, 0xDF]), BLSI(rcx, r15).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF0, 0xF3, 0x5C, 0xD3, 0xA8]), BLSI(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBLSIC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0xF0]), BLSIC(ebp, r8d).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0x74, 0xCC, 0x9D]), BLSIC(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0xF7]), BLSIC(rcx, r15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0x74, 0xD3, 0xA8]), BLSIC(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBLSMSK(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x50, 0xF3, 0xD0]), BLSMSK(ebp, r8d).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x50, 0xF3, 0x54, 0xCC, 0x9D]), BLSMSK(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF0, 0xF3, 0xD7]), BLSMSK(rcx, r15).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF0, 0xF3, 0x54, 0xD3, 0xA8]), BLSMSK(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestBLSR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC2, 0x50, 0xF3, 0xC8]), BLSR(ebp, r8d).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x50, 0xF3, 0x4C, 0xCC, 0x9D]), BLSR(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF0, 0xF3, 0xCF]), BLSR(rcx, r15).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0xF0, 0xF3, 0x4C, 0xD3, 0xA8]), BLSR(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestT1MSKC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0xF8]), T1MSKC(ebp, r8d).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0x7C, 0xCC, 0x9D]), T1MSKC(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0xFF]), T1MSKC(rcx, r15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0x7C, 0xD3, 0xA8]), T1MSKC(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestTZMSK(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0xE0]), TZMSK(ebp, r8d).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x50, 0x01, 0x64, 0xCC, 0x9D]), TZMSK(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0xE7]), TZMSK(rcx, r15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0xF0, 0x01, 0x64, 0xD3, 0xA8]), TZMSK(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCRC32(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x38, 0xF0, 0xE9]), CRC32(ebp, r9b).encode())
self.assertEqual(bytearray([0x66, 0xF2, 0x41, 0x0F, 0x38, 0xF1, 0xEC]), CRC32(ebp, r12w).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x38, 0xF1, 0xE8]), CRC32(ebp, r8d).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x38, 0xF0, 0x6C, 0xBE, 0x85]), CRC32(ebp, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0xF2, 0x41, 0x0F, 0x38, 0xF1, 0x6C, 0xED, 0x95]), CRC32(ebp, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x38, 0xF1, 0x6C, 0xCC, 0x9D]), CRC32(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x38, 0xF0, 0xC9]), CRC32(rcx, r9b).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x38, 0xF1, 0xCF]), CRC32(rcx, r15).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x38, 0xF0, 0x4C, 0xBE, 0x85]), CRC32(rcx, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x38, 0xF1, 0x4C, 0xD3, 0xA8]), CRC32(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x98]), CBW().encode())
class TestCDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x99]), CDQ().encode())
class TestCQO(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x48, 0x99]), CQO().encode())
class TestCWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x99]), CWD().encode())
class TestCWDE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x98]), CWDE().encode())
class TestCDQE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x48, 0x98]), CDQE().encode())
class TestCMOVA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x47, 0xF4]), CMOVA(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x47, 0x74, 0xED, 0x95]), CMOVA(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x47, 0xE8]), CMOVA(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x47, 0x6C, 0xCC, 0x9D]), CMOVA(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x47, 0xCF]), CMOVA(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x47, 0x4C, 0xD3, 0xA8]), CMOVA(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x46, 0xF4]), CMOVNA(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x46, 0x74, 0xED, 0x95]), CMOVNA(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x46, 0xE8]), CMOVNA(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x46, 0x6C, 0xCC, 0x9D]), CMOVNA(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x46, 0xCF]), CMOVNA(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x46, 0x4C, 0xD3, 0xA8]), CMOVNA(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVAE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x43, 0xF4]), CMOVAE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x43, 0x74, 0xED, 0x95]), CMOVAE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x43, 0xE8]), CMOVAE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x43, 0x6C, 0xCC, 0x9D]), CMOVAE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x43, 0xCF]), CMOVAE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x43, 0x4C, 0xD3, 0xA8]), CMOVAE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNAE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x42, 0xF4]), CMOVNAE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x42, 0x74, 0xED, 0x95]), CMOVNAE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x42, 0xE8]), CMOVNAE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x42, 0x6C, 0xCC, 0x9D]), CMOVNAE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x42, 0xCF]), CMOVNAE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x42, 0x4C, 0xD3, 0xA8]), CMOVNAE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x42, 0xF4]), CMOVB(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x42, 0x74, 0xED, 0x95]), CMOVB(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x42, 0xE8]), CMOVB(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x42, 0x6C, 0xCC, 0x9D]), CMOVB(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x42, 0xCF]), CMOVB(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x42, 0x4C, 0xD3, 0xA8]), CMOVB(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x43, 0xF4]), CMOVNB(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x43, 0x74, 0xED, 0x95]), CMOVNB(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x43, 0xE8]), CMOVNB(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x43, 0x6C, 0xCC, 0x9D]), CMOVNB(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x43, 0xCF]), CMOVNB(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x43, 0x4C, 0xD3, 0xA8]), CMOVNB(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVBE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x46, 0xF4]), CMOVBE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x46, 0x74, 0xED, 0x95]), CMOVBE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x46, 0xE8]), CMOVBE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x46, 0x6C, 0xCC, 0x9D]), CMOVBE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x46, 0xCF]), CMOVBE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x46, 0x4C, 0xD3, 0xA8]), CMOVBE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNBE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x47, 0xF4]), CMOVNBE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x47, 0x74, 0xED, 0x95]), CMOVNBE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x47, 0xE8]), CMOVNBE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x47, 0x6C, 0xCC, 0x9D]), CMOVNBE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x47, 0xCF]), CMOVNBE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x47, 0x4C, 0xD3, 0xA8]), CMOVNBE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x42, 0xF4]), CMOVC(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x42, 0x74, 0xED, 0x95]), CMOVC(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x42, 0xE8]), CMOVC(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x42, 0x6C, 0xCC, 0x9D]), CMOVC(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x42, 0xCF]), CMOVC(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x42, 0x4C, 0xD3, 0xA8]), CMOVC(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x43, 0xF4]), CMOVNC(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x43, 0x74, 0xED, 0x95]), CMOVNC(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x43, 0xE8]), CMOVNC(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x43, 0x6C, 0xCC, 0x9D]), CMOVNC(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x43, 0xCF]), CMOVNC(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x43, 0x4C, 0xD3, 0xA8]), CMOVNC(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x44, 0xF4]), CMOVE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x44, 0x74, 0xED, 0x95]), CMOVE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x44, 0xE8]), CMOVE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x44, 0x6C, 0xCC, 0x9D]), CMOVE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x44, 0xCF]), CMOVE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x44, 0x4C, 0xD3, 0xA8]), CMOVE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x45, 0xF4]), CMOVNE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x45, 0x74, 0xED, 0x95]), CMOVNE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x45, 0xE8]), CMOVNE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x45, 0x6C, 0xCC, 0x9D]), CMOVNE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x45, 0xCF]), CMOVNE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x45, 0x4C, 0xD3, 0xA8]), CMOVNE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVG(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4F, 0xF4]), CMOVG(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4F, 0x74, 0xED, 0x95]), CMOVG(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4F, 0xE8]), CMOVG(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4F, 0x6C, 0xCC, 0x9D]), CMOVG(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4F, 0xCF]), CMOVG(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4F, 0x4C, 0xD3, 0xA8]), CMOVG(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNG(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4E, 0xF4]), CMOVNG(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4E, 0x74, 0xED, 0x95]), CMOVNG(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4E, 0xE8]), CMOVNG(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4E, 0x6C, 0xCC, 0x9D]), CMOVNG(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4E, 0xCF]), CMOVNG(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4E, 0x4C, 0xD3, 0xA8]), CMOVNG(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVGE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4D, 0xF4]), CMOVGE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4D, 0x74, 0xED, 0x95]), CMOVGE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4D, 0xE8]), CMOVGE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4D, 0x6C, 0xCC, 0x9D]), CMOVGE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4D, 0xCF]), CMOVGE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4D, 0x4C, 0xD3, 0xA8]), CMOVGE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNGE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4C, 0xF4]), CMOVNGE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4C, 0x74, 0xED, 0x95]), CMOVNGE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4C, 0xE8]), CMOVNGE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4C, 0x6C, 0xCC, 0x9D]), CMOVNGE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4C, 0xCF]), CMOVNGE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4C, 0x4C, 0xD3, 0xA8]), CMOVNGE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4C, 0xF4]), CMOVL(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4C, 0x74, 0xED, 0x95]), CMOVL(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4C, 0xE8]), CMOVL(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4C, 0x6C, 0xCC, 0x9D]), CMOVL(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4C, 0xCF]), CMOVL(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4C, 0x4C, 0xD3, 0xA8]), CMOVL(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4D, 0xF4]), CMOVNL(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4D, 0x74, 0xED, 0x95]), CMOVNL(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4D, 0xE8]), CMOVNL(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4D, 0x6C, 0xCC, 0x9D]), CMOVNL(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4D, 0xCF]), CMOVNL(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4D, 0x4C, 0xD3, 0xA8]), CMOVNL(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVLE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4E, 0xF4]), CMOVLE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4E, 0x74, 0xED, 0x95]), CMOVLE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4E, 0xE8]), CMOVLE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4E, 0x6C, 0xCC, 0x9D]), CMOVLE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4E, 0xCF]), CMOVLE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4E, 0x4C, 0xD3, 0xA8]), CMOVLE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNLE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4F, 0xF4]), CMOVNLE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4F, 0x74, 0xED, 0x95]), CMOVNLE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4F, 0xE8]), CMOVNLE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4F, 0x6C, 0xCC, 0x9D]), CMOVNLE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4F, 0xCF]), CMOVNLE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4F, 0x4C, 0xD3, 0xA8]), CMOVNLE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVO(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x40, 0xF4]), CMOVO(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x40, 0x74, 0xED, 0x95]), CMOVO(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x40, 0xE8]), CMOVO(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x40, 0x6C, 0xCC, 0x9D]), CMOVO(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x40, 0xCF]), CMOVO(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x40, 0x4C, 0xD3, 0xA8]), CMOVO(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNO(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x41, 0xF4]), CMOVNO(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x41, 0x74, 0xED, 0x95]), CMOVNO(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x41, 0xE8]), CMOVNO(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x41, 0x6C, 0xCC, 0x9D]), CMOVNO(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x41, 0xCF]), CMOVNO(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x41, 0x4C, 0xD3, 0xA8]), CMOVNO(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4A, 0xF4]), CMOVP(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4A, 0x74, 0xED, 0x95]), CMOVP(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4A, 0xE8]), CMOVP(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4A, 0x6C, 0xCC, 0x9D]), CMOVP(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4A, 0xCF]), CMOVP(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4A, 0x4C, 0xD3, 0xA8]), CMOVP(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4B, 0xF4]), CMOVNP(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4B, 0x74, 0xED, 0x95]), CMOVNP(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4B, 0xE8]), CMOVNP(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4B, 0x6C, 0xCC, 0x9D]), CMOVNP(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4B, 0xCF]), CMOVNP(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4B, 0x4C, 0xD3, 0xA8]), CMOVNP(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x48, 0xF4]), CMOVS(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x48, 0x74, 0xED, 0x95]), CMOVS(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x48, 0xE8]), CMOVS(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x48, 0x6C, 0xCC, 0x9D]), CMOVS(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x48, 0xCF]), CMOVS(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x48, 0x4C, 0xD3, 0xA8]), CMOVS(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x49, 0xF4]), CMOVNS(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x49, 0x74, 0xED, 0x95]), CMOVNS(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x49, 0xE8]), CMOVNS(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x49, 0x6C, 0xCC, 0x9D]), CMOVNS(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x49, 0xCF]), CMOVNS(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x49, 0x4C, 0xD3, 0xA8]), CMOVNS(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVZ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x44, 0xF4]), CMOVZ(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x44, 0x74, 0xED, 0x95]), CMOVZ(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x44, 0xE8]), CMOVZ(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x44, 0x6C, 0xCC, 0x9D]), CMOVZ(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x44, 0xCF]), CMOVZ(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x44, 0x4C, 0xD3, 0xA8]), CMOVZ(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVNZ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x45, 0xF4]), CMOVNZ(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x45, 0x74, 0xED, 0x95]), CMOVNZ(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x45, 0xE8]), CMOVNZ(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x45, 0x6C, 0xCC, 0x9D]), CMOVNZ(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x45, 0xCF]), CMOVNZ(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x45, 0x4C, 0xD3, 0xA8]), CMOVNZ(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVPE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4A, 0xF4]), CMOVPE(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4A, 0x74, 0xED, 0x95]), CMOVPE(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4A, 0xE8]), CMOVPE(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4A, 0x6C, 0xCC, 0x9D]), CMOVPE(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4A, 0xCF]), CMOVPE(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4A, 0x4C, 0xD3, 0xA8]), CMOVPE(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCMOVPO(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4B, 0xF4]), CMOVPO(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x4B, 0x74, 0xED, 0x95]), CMOVPO(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4B, 0xE8]), CMOVPO(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x4B, 0x6C, 0xCC, 0x9D]), CMOVPO(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4B, 0xCF]), CMOVPO(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x4B, 0x4C, 0xD3, 0xA8]), CMOVPO(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestSETA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x97, 0xC3]), SETA(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x97, 0x44, 0xBE, 0x85]), SETA(byte[r14 + rdi*4 - 123]).encode())
class TestSETNA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x96, 0xC3]), SETNA(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x96, 0x44, 0xBE, 0x85]), SETNA(byte[r14 + rdi*4 - 123]).encode())
class TestSETAE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x93, 0xC3]), SETAE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x93, 0x44, 0xBE, 0x85]), SETAE(byte[r14 + rdi*4 - 123]).encode())
class TestSETNAE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x92, 0xC3]), SETNAE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x92, 0x44, 0xBE, 0x85]), SETNAE(byte[r14 + rdi*4 - 123]).encode())
class TestSETB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x92, 0xC3]), SETB(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x92, 0x44, 0xBE, 0x85]), SETB(byte[r14 + rdi*4 - 123]).encode())
class TestSETNB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x93, 0xC3]), SETNB(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x93, 0x44, 0xBE, 0x85]), SETNB(byte[r14 + rdi*4 - 123]).encode())
class TestSETBE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x96, 0xC3]), SETBE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x96, 0x44, 0xBE, 0x85]), SETBE(byte[r14 + rdi*4 - 123]).encode())
class TestSETNBE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x97, 0xC3]), SETNBE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x97, 0x44, 0xBE, 0x85]), SETNBE(byte[r14 + rdi*4 - 123]).encode())
class TestSETC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x92, 0xC3]), SETC(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x92, 0x44, 0xBE, 0x85]), SETC(byte[r14 + rdi*4 - 123]).encode())
class TestSETNC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x93, 0xC3]), SETNC(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x93, 0x44, 0xBE, 0x85]), SETNC(byte[r14 + rdi*4 - 123]).encode())
class TestSETE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x94, 0xC3]), SETE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x94, 0x44, 0xBE, 0x85]), SETE(byte[r14 + rdi*4 - 123]).encode())
class TestSETNE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x95, 0xC3]), SETNE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x95, 0x44, 0xBE, 0x85]), SETNE(byte[r14 + rdi*4 - 123]).encode())
class TestSETG(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9F, 0xC3]), SETG(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9F, 0x44, 0xBE, 0x85]), SETG(byte[r14 + rdi*4 - 123]).encode())
class TestSETNG(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9E, 0xC3]), SETNG(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9E, 0x44, 0xBE, 0x85]), SETNG(byte[r14 + rdi*4 - 123]).encode())
class TestSETGE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9D, 0xC3]), SETGE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9D, 0x44, 0xBE, 0x85]), SETGE(byte[r14 + rdi*4 - 123]).encode())
class TestSETNGE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9C, 0xC3]), SETNGE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9C, 0x44, 0xBE, 0x85]), SETNGE(byte[r14 + rdi*4 - 123]).encode())
class TestSETL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9C, 0xC3]), SETL(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9C, 0x44, 0xBE, 0x85]), SETL(byte[r14 + rdi*4 - 123]).encode())
class TestSETNL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9D, 0xC3]), SETNL(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9D, 0x44, 0xBE, 0x85]), SETNL(byte[r14 + rdi*4 - 123]).encode())
class TestSETLE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9E, 0xC3]), SETLE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9E, 0x44, 0xBE, 0x85]), SETLE(byte[r14 + rdi*4 - 123]).encode())
class TestSETNLE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9F, 0xC3]), SETNLE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9F, 0x44, 0xBE, 0x85]), SETNLE(byte[r14 + rdi*4 - 123]).encode())
class TestSETO(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x90, 0xC3]), SETO(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x90, 0x44, 0xBE, 0x85]), SETO(byte[r14 + rdi*4 - 123]).encode())
class TestSETNO(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x91, 0xC3]), SETNO(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x91, 0x44, 0xBE, 0x85]), SETNO(byte[r14 + rdi*4 - 123]).encode())
class TestSETP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9A, 0xC3]), SETP(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9A, 0x44, 0xBE, 0x85]), SETP(byte[r14 + rdi*4 - 123]).encode())
class TestSETNP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9B, 0xC3]), SETNP(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9B, 0x44, 0xBE, 0x85]), SETNP(byte[r14 + rdi*4 - 123]).encode())
class TestSETS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x98, 0xC3]), SETS(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x98, 0x44, 0xBE, 0x85]), SETS(byte[r14 + rdi*4 - 123]).encode())
class TestSETNS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x99, 0xC3]), SETNS(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x99, 0x44, 0xBE, 0x85]), SETNS(byte[r14 + rdi*4 - 123]).encode())
class TestSETZ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x94, 0xC3]), SETZ(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x94, 0x44, 0xBE, 0x85]), SETZ(byte[r14 + rdi*4 - 123]).encode())
class TestSETNZ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x95, 0xC3]), SETNZ(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x95, 0x44, 0xBE, 0x85]), SETNZ(byte[r14 + rdi*4 - 123]).encode())
class TestSETPE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9A, 0xC3]), SETPE(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9A, 0x44, 0xBE, 0x85]), SETPE(byte[r14 + rdi*4 - 123]).encode())
class TestSETPO(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x9B, 0xC3]), SETPO(bl).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x9B, 0x44, 0xBE, 0x85]), SETPO(byte[r14 + rdi*4 - 123]).encode())
class TestJA(unittest.TestCase):
def runTest(self):
pass
class TestJNA(unittest.TestCase):
def runTest(self):
pass
class TestJAE(unittest.TestCase):
def runTest(self):
pass
class TestJNAE(unittest.TestCase):
def runTest(self):
pass
class TestJB(unittest.TestCase):
def runTest(self):
pass
class TestJNB(unittest.TestCase):
def runTest(self):
pass
class TestJBE(unittest.TestCase):
def runTest(self):
pass
class TestJNBE(unittest.TestCase):
def runTest(self):
pass
class TestJC(unittest.TestCase):
def runTest(self):
pass
class TestJNC(unittest.TestCase):
def runTest(self):
pass
class TestJE(unittest.TestCase):
def runTest(self):
pass
class TestJNE(unittest.TestCase):
def runTest(self):
pass
class TestJG(unittest.TestCase):
def runTest(self):
pass
class TestJNG(unittest.TestCase):
def runTest(self):
pass
class TestJGE(unittest.TestCase):
def runTest(self):
pass
class TestJNGE(unittest.TestCase):
def runTest(self):
pass
class TestJL(unittest.TestCase):
def runTest(self):
pass
class TestJNL(unittest.TestCase):
def runTest(self):
pass
class TestJLE(unittest.TestCase):
def runTest(self):
pass
class TestJNLE(unittest.TestCase):
def runTest(self):
pass
class TestJO(unittest.TestCase):
def runTest(self):
pass
class TestJNO(unittest.TestCase):
def runTest(self):
pass
class TestJP(unittest.TestCase):
def runTest(self):
pass
class TestJNP(unittest.TestCase):
def runTest(self):
pass
class TestJS(unittest.TestCase):
def runTest(self):
pass
class TestJNS(unittest.TestCase):
def runTest(self):
pass
class TestJZ(unittest.TestCase):
def runTest(self):
pass
class TestJNZ(unittest.TestCase):
def runTest(self):
pass
class TestJPE(unittest.TestCase):
def runTest(self):
pass
class TestJPO(unittest.TestCase):
def runTest(self):
pass
class TestJMP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xFF, 0xE1]), JMP(rcx).encode())
self.assertEqual(bytearray([0x41, 0xFF, 0x64, 0xD3, 0xA8]), JMP(qword[r11 + rdx*8 - 88]).encode())
class TestJRCXZ(unittest.TestCase):
def runTest(self):
pass
class TestJECXZ(unittest.TestCase):
def runTest(self):
pass
class TestRET(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC3]), RET().encode())
self.assertEqual(bytearray([0xC2, 0x00, 0x7D]), RET(32000).encode())
class TestCALL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xFF, 0xD1]), CALL(rcx).encode())
self.assertEqual(bytearray([0x41, 0xFF, 0x54, 0xD3, 0xA8]), CALL(qword[r11 + rdx*8 - 88]).encode())
class TestPAUSE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x90]), PAUSE().encode())
class TestNOP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x90]), NOP().encode())
class TestINT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xCC]), INT(3).encode())
self.assertEqual(bytearray([0xCD, 0x02]), INT(2).encode())
class TestUD2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0B]), UD2().encode())
class TestCPUID(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xA2]), CPUID().encode())
class TestRDTSC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x31]), RDTSC().encode())
class TestRDTSCP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x01, 0xF9]), RDTSCP().encode())
class TestXGETBV(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x01, 0xD0]), XGETBV().encode())
class TestSYSCALL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x05]), SYSCALL().encode())
class TestSTC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF9]), STC().encode())
class TestCLC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF8]), CLC().encode())
class TestCMC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF5]), CMC().encode())
class TestSTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xFD]), STD().encode())
class TestCLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xFC]), CLD().encode())
class TestXADD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x44, 0x0F, 0xC0, 0xCB]), XADD(bl, r9b).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xC1, 0xE6]), XADD(si, r12w).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xC1, 0xC5]), XADD(ebp, r8d).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xC1, 0xF9]), XADD(rcx, r15).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xC0, 0x4C, 0xBE, 0x85]), XADD(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xC1, 0x64, 0xED, 0x95]), XADD(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xC1, 0x44, 0xCC, 0x9D]), XADD(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xC1, 0x7C, 0xD3, 0xA8]), XADD(qword[r11 + rdx*8 - 88], r15).encode())
class TestXCHG(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x44, 0x86, 0xCB]), XCHG(bl, r9b).encode())
self.assertEqual(bytearray([0x41, 0x86, 0x5C, 0xBE, 0x85]), XCHG(bl, byte[r14 + rdi*4 - 123]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x94]), XCHG(ax, r12w).encode())
self.assertEqual(bytearray([0x66, 0x96]), XCHG(si, ax).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x87, 0xE6]), XCHG(si, r12w).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x87, 0x74, 0xED, 0x95]), XCHG(si, word[r13 + rbp*8 - 107]).encode())
self.assertEqual(bytearray([0x41, 0x90]), XCHG(eax, r8d).encode())
self.assertEqual(bytearray([0x95]), XCHG(ebp, eax).encode())
self.assertEqual(bytearray([0x44, 0x87, 0xC5]), XCHG(ebp, r8d).encode())
self.assertEqual(bytearray([0x41, 0x87, 0x6C, 0xCC, 0x9D]), XCHG(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x49, 0x97]), XCHG(rax, r15).encode())
self.assertEqual(bytearray([0x48, 0x91]), XCHG(rcx, rax).encode())
self.assertEqual(bytearray([0x4C, 0x87, 0xF9]), XCHG(rcx, r15).encode())
self.assertEqual(bytearray([0x49, 0x87, 0x4C, 0xD3, 0xA8]), XCHG(rcx, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x45, 0x86, 0x4C, 0xBE, 0x85]), XCHG(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x87, 0x64, 0xED, 0x95]), XCHG(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x45, 0x87, 0x44, 0xCC, 0x9D]), XCHG(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x4D, 0x87, 0x7C, 0xD3, 0xA8]), XCHG(qword[r11 + rdx*8 - 88], r15).encode())
class TestCMPXCHG(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x44, 0x0F, 0xB0, 0xCB]), CMPXCHG(bl, r9b).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0xB1, 0xE6]), CMPXCHG(si, r12w).encode())
self.assertEqual(bytearray([0x44, 0x0F, 0xB1, 0xC5]), CMPXCHG(ebp, r8d).encode())
self.assertEqual(bytearray([0x4C, 0x0F, 0xB1, 0xF9]), CMPXCHG(rcx, r15).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xB0, 0x4C, 0xBE, 0x85]), CMPXCHG(byte[r14 + rdi*4 - 123], r9b).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xB1, 0x64, 0xED, 0x95]), CMPXCHG(word[r13 + rbp*8 - 107], r12w).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0xB1, 0x44, 0xCC, 0x9D]), CMPXCHG(dword[r12 + rcx*8 - 99], r8d).encode())
self.assertEqual(bytearray([0x4D, 0x0F, 0xB1, 0x7C, 0xD3, 0xA8]), CMPXCHG(qword[r11 + rdx*8 - 88], r15).encode())
class TestCMPXCHG8B(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0xC7, 0x4C, 0xD3, 0xA8]), CMPXCHG8B(qword[r11 + rdx*8 - 88]).encode())
class TestCMPXCHG16B(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x49, 0x0F, 0xC7, 0x4C, 0xC2, 0xB3]), CMPXCHG16B(oword[r10 + rax*8 - 77]).encode())
class TestSFENCE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xAE, 0xF8]), SFENCE().encode())
class TestMFENCE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xAE, 0xF0]), MFENCE().encode())
class TestLFENCE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xAE, 0xE8]), LFENCE().encode())
class TestPREFETCHNTA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x18, 0x44, 0xBE, 0x85]), PREFETCHNTA(byte[r14 + rdi*4 - 123]).encode())
class TestPREFETCHT0(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x18, 0x4C, 0xBE, 0x85]), PREFETCHT0(byte[r14 + rdi*4 - 123]).encode())
class TestPREFETCHT1(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x18, 0x54, 0xBE, 0x85]), PREFETCHT1(byte[r14 + rdi*4 - 123]).encode())
class TestPREFETCHT2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x18, 0x5C, 0xBE, 0x85]), PREFETCHT2(byte[r14 + rdi*4 - 123]).encode())
class TestPREFETCH(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x0D, 0x44, 0xBE, 0x85]), PREFETCH(byte[r14 + rdi*4 - 123]).encode())
class TestPREFETCHW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x0D, 0x4C, 0xBE, 0x85]), PREFETCHW(byte[r14 + rdi*4 - 123]).encode())
class TestPREFETCHWT1(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x0D, 0x54, 0xBE, 0x85]), PREFETCHWT1(byte[r14 + rdi*4 - 123]).encode())
class TestCLFLUSH(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0xAE, 0x7C, 0xBE, 0x85]), CLFLUSH(byte[r14 + rdi*4 - 123]).encode())
class TestCLFLUSHOPT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xAE, 0x7C, 0xBE, 0x85]), CLFLUSHOPT(byte[r14 + rdi*4 - 123]).encode())
class TestCLWB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xAE, 0x74, 0xBE, 0x85]), CLWB(byte[r14 + rdi*4 - 123]).encode())
class TestCLZERO(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x01, 0xFC]), CLZERO().encode())
|
# This file is auto-generated by /codegen/x86_64_test_encoding.py
# Reference opcodes are generated by:
# GNU assembler (GNU Binutils) 2.25
from peachpy.x86_64 import *
import unittest
class TestImm8(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x49, 0x83, 0xF8, 0x00]), CMP(r8, 0).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xC1, 0x7F]), ADD(rcx, 127).encode())
self.assertEqual(bytearray([0x41, 0x83, 0xEE, 0x80]), SUB(r14d, -128).encode())
self.assertEqual(bytearray([0x48, 0x83, 0xCE, 0x80]), OR(rsi, 0xFFFFFFFFFFFFFF80).encode())
class TestImm32(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x48, 0x81, 0xC1, 0x80, 0x00, 0x00, 0x00]), ADD(rcx, 128).encode())
self.assertEqual(bytearray([0x41, 0x81, 0xEE, 0x7F, 0xFF, 0xFF, 0xFF]), SUB(r14d, -129).encode())
self.assertEqual(bytearray([0x48, 0x81, 0xCE, 0x7F, 0xFF, 0xFF, 0xFF]), OR(rsi, 0xFFFFFFFFFFFFFF7F).encode())
|
# This file is auto-generated by /codegen/x86_64_test_encoding.py
# Reference opcodes are generated by:
# GNU assembler (GNU Binutils) 2.28.51.20170402
from peachpy.x86_64 import *
import unittest
class TestMOVSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x10, 0xCE]), MOVSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x10, 0x4C, 0xCC, 0x9D]), MOVSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x45, 0x0F, 0x11, 0x74, 0xCC, 0x9D]), MOVSS(dword[r12 + rcx*8 - 99], xmm14).encode())
class TestEXTRACTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0x3A, 0x17, 0xF5, 0x02]), EXTRACTPS(ebp, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x3A, 0x17, 0x74, 0xCC, 0x9D, 0x02]), EXTRACTPS(dword[r12 + rcx*8 - 99], xmm14, 2).encode())
class TestINSERTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x21, 0xCE, 0x02]), INSERTPS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x21, 0x4C, 0xCC, 0x9D, 0x02]), INSERTPS(xmm1, dword[r12 + rcx*8 - 99], 2).encode())
class TestADDSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x58, 0xCE]), ADDSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x58, 0x4C, 0xCC, 0x9D]), ADDSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestSUBSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5C, 0xCE]), SUBSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5C, 0x4C, 0xCC, 0x9D]), SUBSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestMULSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x59, 0xCE]), MULSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x59, 0x4C, 0xCC, 0x9D]), MULSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestDIVSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5E, 0xCE]), DIVSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5E, 0x4C, 0xCC, 0x9D]), DIVSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestSQRTSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x51, 0xCE]), SQRTSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x51, 0x4C, 0xCC, 0x9D]), SQRTSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestROUNDSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0A, 0xCE, 0x02]), ROUNDSS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0A, 0x4C, 0xCC, 0x9D, 0x02]), ROUNDSS(xmm1, dword[r12 + rcx*8 - 99], 2).encode())
class TestMINSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5D, 0xCE]), MINSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5D, 0x4C, 0xCC, 0x9D]), MINSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestMAXSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5F, 0xCE]), MAXSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5F, 0x4C, 0xCC, 0x9D]), MAXSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestRCPSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x53, 0xCE]), RCPSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x53, 0x4C, 0xCC, 0x9D]), RCPSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestRSQRTSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x52, 0xCE]), RSQRTSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x52, 0x4C, 0xCC, 0x9D]), RSQRTSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestCMPSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xC2, 0xCE, 0x02]), CMPSS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xC2, 0x4C, 0xCC, 0x9D, 0x02]), CMPSS(xmm1, dword[r12 + rcx*8 - 99], 2).encode())
class TestCOMISS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x2F, 0xCE]), COMISS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x2F, 0x4C, 0xCC, 0x9D]), COMISS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestUCOMISS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x2E, 0xCE]), UCOMISS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x2E, 0x4C, 0xCC, 0x9D]), UCOMISS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestMOVSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x10, 0xCE]), MOVSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x10, 0x4C, 0xD3, 0xA8]), MOVSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xF2, 0x45, 0x0F, 0x11, 0x74, 0xD3, 0xA8]), MOVSD(qword[r11 + rdx*8 - 88], xmm14).encode())
class TestADDSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x58, 0xCE]), ADDSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x58, 0x4C, 0xD3, 0xA8]), ADDSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestSUBSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5C, 0xCE]), SUBSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5C, 0x4C, 0xD3, 0xA8]), SUBSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestMULSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x59, 0xCE]), MULSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x59, 0x4C, 0xD3, 0xA8]), MULSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestDIVSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5E, 0xCE]), DIVSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5E, 0x4C, 0xD3, 0xA8]), DIVSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestSQRTSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x51, 0xCE]), SQRTSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x51, 0x4C, 0xD3, 0xA8]), SQRTSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestROUNDSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0B, 0xCE, 0x02]), ROUNDSD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0B, 0x4C, 0xD3, 0xA8, 0x02]), ROUNDSD(xmm1, qword[r11 + rdx*8 - 88], 2).encode())
class TestMINSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5D, 0xCE]), MINSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5D, 0x4C, 0xD3, 0xA8]), MINSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestMAXSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5F, 0xCE]), MAXSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5F, 0x4C, 0xD3, 0xA8]), MAXSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestCMPSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0xC2, 0xCE, 0x02]), CMPSD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0xC2, 0x4C, 0xD3, 0xA8, 0x02]), CMPSD(xmm1, qword[r11 + rdx*8 - 88], 2).encode())
class TestCOMISD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x2F, 0xCE]), COMISD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x2F, 0x4C, 0xD3, 0xA8]), COMISD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestUCOMISD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x2E, 0xCE]), UCOMISD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x2E, 0x4C, 0xD3, 0xA8]), UCOMISD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestMOVAPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x28, 0xCE]), MOVAPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x28, 0x4C, 0xC2, 0xB3]), MOVAPS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0x29, 0x74, 0xC2, 0xB3]), MOVAPS(oword[r10 + rax*8 - 77], xmm14).encode())
class TestMOVUPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x10, 0xCE]), MOVUPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x10, 0x4C, 0xC2, 0xB3]), MOVUPS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0x11, 0x74, 0xC2, 0xB3]), MOVUPS(oword[r10 + rax*8 - 77], xmm14).encode())
class TestMOVLPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x12, 0x4C, 0xD3, 0xA8]), MOVLPS(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0x13, 0x74, 0xD3, 0xA8]), MOVLPS(qword[r11 + rdx*8 - 88], xmm14).encode())
class TestMOVNTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x45, 0x0F, 0x2B, 0x74, 0xC2, 0xB3]), MOVNTPS(oword[r10 + rax*8 - 77], xmm14).encode())
class TestMOVHPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x16, 0x4C, 0xD3, 0xA8]), MOVHPS(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x45, 0x0F, 0x17, 0x74, 0xD3, 0xA8]), MOVHPS(qword[r11 + rdx*8 - 88], xmm14).encode())
class TestMOVSLDUP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x12, 0xCE]), MOVSLDUP(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x12, 0x4C, 0xC2, 0xB3]), MOVSLDUP(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestMOVSHDUP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x16, 0xCE]), MOVSHDUP(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x16, 0x4C, 0xC2, 0xB3]), MOVSHDUP(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestMOVAPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x28, 0xCE]), MOVAPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x28, 0x4C, 0xC2, 0xB3]), MOVAPD(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x29, 0x74, 0xC2, 0xB3]), MOVAPD(oword[r10 + rax*8 - 77], xmm14).encode())
class TestMOVUPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x10, 0xCE]), MOVUPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x10, 0x4C, 0xC2, 0xB3]), MOVUPD(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x11, 0x74, 0xC2, 0xB3]), MOVUPD(oword[r10 + rax*8 - 77], xmm14).encode())
class TestMOVLPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x12, 0x4C, 0xD3, 0xA8]), MOVLPD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x13, 0x74, 0xD3, 0xA8]), MOVLPD(qword[r11 + rdx*8 - 88], xmm14).encode())
class TestMOVNTPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x2B, 0x74, 0xC2, 0xB3]), MOVNTPD(oword[r10 + rax*8 - 77], xmm14).encode())
class TestMOVHPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x16, 0x4C, 0xD3, 0xA8]), MOVHPD(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x17, 0x74, 0xD3, 0xA8]), MOVHPD(qword[r11 + rdx*8 - 88], xmm14).encode())
class TestMOVDDUP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x12, 0xCE]), MOVDDUP(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x12, 0x4C, 0xD3, 0xA8]), MOVDDUP(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestADDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x58, 0xCE]), ADDPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x58, 0x4C, 0xC2, 0xB3]), ADDPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestHADDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x7C, 0xCE]), HADDPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x7C, 0x4C, 0xC2, 0xB3]), HADDPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSUBPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x5C, 0xCE]), SUBPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x5C, 0x4C, 0xC2, 0xB3]), SUBPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestHSUBPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x7D, 0xCE]), HSUBPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x7D, 0x4C, 0xC2, 0xB3]), HSUBPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestADDSUBPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0xD0, 0xCE]), ADDSUBPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0xD0, 0x4C, 0xC2, 0xB3]), ADDSUBPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestMULPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x59, 0xCE]), MULPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x59, 0x4C, 0xC2, 0xB3]), MULPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestDIVPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x5E, 0xCE]), DIVPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x5E, 0x4C, 0xC2, 0xB3]), DIVPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSQRTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x51, 0xCE]), SQRTPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x51, 0x4C, 0xC2, 0xB3]), SQRTPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestADDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x58, 0xCE]), ADDPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x58, 0x4C, 0xC2, 0xB3]), ADDPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestHADDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x7C, 0xCE]), HADDPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x7C, 0x4C, 0xC2, 0xB3]), HADDPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSUBPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5C, 0xCE]), SUBPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5C, 0x4C, 0xC2, 0xB3]), SUBPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestHSUBPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x7D, 0xCE]), HSUBPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x7D, 0x4C, 0xC2, 0xB3]), HSUBPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestADDSUBPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD0, 0xCE]), ADDSUBPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD0, 0x4C, 0xC2, 0xB3]), ADDSUBPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestMULPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x59, 0xCE]), MULPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x59, 0x4C, 0xC2, 0xB3]), MULPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestDIVPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5E, 0xCE]), DIVPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5E, 0x4C, 0xC2, 0xB3]), DIVPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSQRTPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x51, 0xCE]), SQRTPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x51, 0x4C, 0xC2, 0xB3]), SQRTPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestROUNDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x08, 0xCE, 0x02]), ROUNDPS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x08, 0x4C, 0xC2, 0xB3, 0x02]), ROUNDPS(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestMINPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x5D, 0xCE]), MINPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x5D, 0x4C, 0xC2, 0xB3]), MINPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestMAXPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x5F, 0xCE]), MAXPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x5F, 0x4C, 0xC2, 0xB3]), MAXPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestRCPPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x53, 0xCE]), RCPPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x53, 0x4C, 0xC2, 0xB3]), RCPPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestRSQRTPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x52, 0xCE]), RSQRTPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x52, 0x4C, 0xC2, 0xB3]), RSQRTPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestDPPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x40, 0xCE, 0x02]), DPPS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x40, 0x4C, 0xC2, 0xB3, 0x02]), DPPS(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestCMPPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0xC2, 0xCE, 0x02]), CMPPS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xC2, 0x4C, 0xC2, 0xB3, 0x02]), CMPPS(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestMOVMSKPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x50, 0xEE]), MOVMSKPS(ebp, xmm14).encode())
class TestROUNDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x09, 0xCE, 0x02]), ROUNDPD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x09, 0x4C, 0xC2, 0xB3, 0x02]), ROUNDPD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestMINPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5D, 0xCE]), MINPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5D, 0x4C, 0xC2, 0xB3]), MINPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestMAXPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5F, 0xCE]), MAXPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5F, 0x4C, 0xC2, 0xB3]), MAXPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestDPPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x41, 0xCE, 0x02]), DPPD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x41, 0x4C, 0xC2, 0xB3, 0x02]), DPPD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestCMPPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xC2, 0xCE, 0x02]), CMPPD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xC2, 0x4C, 0xC2, 0xB3, 0x02]), CMPPD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestMOVMSKPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x50, 0xEE]), MOVMSKPD(ebp, xmm14).encode())
class TestANDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x54, 0xCE]), ANDPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x54, 0x4C, 0xC2, 0xB3]), ANDPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestANDNPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x55, 0xCE]), ANDNPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x55, 0x4C, 0xC2, 0xB3]), ANDNPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestORPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x56, 0xCE]), ORPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x56, 0x4C, 0xC2, 0xB3]), ORPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestXORPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x57, 0xCE]), XORPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x57, 0x4C, 0xC2, 0xB3]), XORPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestBLENDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0C, 0xCE, 0x02]), BLENDPS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0C, 0x4C, 0xC2, 0xB3, 0x02]), BLENDPS(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestBLENDVPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x14, 0xCE]), BLENDVPS(xmm1, xmm14, xmm0).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x14, 0x4C, 0xC2, 0xB3]), BLENDVPS(xmm1, oword[r10 + rax*8 - 77], xmm0).encode())
class TestANDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x54, 0xCE]), ANDPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x54, 0x4C, 0xC2, 0xB3]), ANDPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestANDNPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x55, 0xCE]), ANDNPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x55, 0x4C, 0xC2, 0xB3]), ANDNPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestORPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x56, 0xCE]), ORPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x56, 0x4C, 0xC2, 0xB3]), ORPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestXORPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x57, 0xCE]), XORPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x57, 0x4C, 0xC2, 0xB3]), XORPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestBLENDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0D, 0xCE, 0x02]), BLENDPD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0D, 0x4C, 0xC2, 0xB3, 0x02]), BLENDPD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestBLENDVPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x15, 0xCE]), BLENDVPD(xmm1, xmm14, xmm0).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x15, 0x4C, 0xC2, 0xB3]), BLENDVPD(xmm1, oword[r10 + rax*8 - 77], xmm0).encode())
class TestUNPCKLPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x14, 0xCE]), UNPCKLPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x14, 0x4C, 0xC2, 0xB3]), UNPCKLPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestUNPCKHPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x15, 0xCE]), UNPCKHPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x15, 0x4C, 0xC2, 0xB3]), UNPCKHPS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestMOVLHPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x16, 0xCE]), MOVLHPS(xmm1, xmm14).encode())
class TestMOVHLPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x12, 0xCE]), MOVHLPS(xmm1, xmm14).encode())
class TestSHUFPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0xC6, 0xCE, 0x02]), SHUFPS(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xC6, 0x4C, 0xC2, 0xB3, 0x02]), SHUFPS(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestUNPCKLPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x14, 0xCE]), UNPCKLPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x14, 0x4C, 0xC2, 0xB3]), UNPCKLPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestUNPCKHPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x15, 0xCE]), UNPCKHPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x15, 0x4C, 0xC2, 0xB3]), UNPCKHPD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestSHUFPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xC6, 0xCE, 0x02]), SHUFPD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xC6, 0x4C, 0xC2, 0xB3, 0x02]), SHUFPD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestMOVD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x7E, 0xED]), MOVD(ebp, mm5).encode())
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0x7E, 0xF5]), MOVD(ebp, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x6E, 0xD8]), MOVD(mm3, r8d).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x6E, 0x5C, 0xCC, 0x9D]), MOVD(mm3, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6E, 0xC8]), MOVD(xmm1, r8d).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6E, 0x4C, 0xCC, 0x9D]), MOVD(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x7E, 0x6C, 0xCC, 0x9D]), MOVD(dword[r12 + rcx*8 - 99], mm5).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x7E, 0x74, 0xCC, 0x9D]), MOVD(dword[r12 + rcx*8 - 99], xmm14).encode())
class TestMOVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x48, 0x0F, 0x7E, 0xE9]), MOVQ(rcx, mm5).encode())
self.assertEqual(bytearray([0x66, 0x4C, 0x0F, 0x7E, 0xF1]), MOVQ(rcx, xmm14).encode())
self.assertEqual(bytearray([0x49, 0x0F, 0x6E, 0xDF]), MOVQ(mm3, r15).encode())
self.assertEqual(bytearray([0x0F, 0x6F, 0xDD]), MOVQ(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x6F, 0x5C, 0xD3, 0xA8]), MOVQ(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x49, 0x0F, 0x6E, 0xCF]), MOVQ(xmm1, r15).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x7E, 0xCE]), MOVQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x7E, 0x4C, 0xD3, 0xA8]), MOVQ(xmm1, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x7F, 0x6C, 0xD3, 0xA8]), MOVQ(qword[r11 + rdx*8 - 88], mm5).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xD6, 0x74, 0xD3, 0xA8]), MOVQ(qword[r11 + rdx*8 - 88], xmm14).encode())
class TestMOVDQ2Q(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0xD6, 0xDE]), MOVDQ2Q(mm3, xmm14).encode())
class TestMOVQ2DQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x0F, 0xD6, 0xCD]), MOVQ2DQ(xmm1, mm5).encode())
class TestMOVDQA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6F, 0xCE]), MOVDQA(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6F, 0x4C, 0xC2, 0xB3]), MOVDQA(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x7F, 0x74, 0xC2, 0xB3]), MOVDQA(oword[r10 + rax*8 - 77], xmm14).encode())
class TestMOVDQU(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x6F, 0xCE]), MOVDQU(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x6F, 0x4C, 0xC2, 0xB3]), MOVDQU(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xF3, 0x45, 0x0F, 0x7F, 0x74, 0xC2, 0xB3]), MOVDQU(oword[r10 + rax*8 - 77], xmm14).encode())
class TestLDDQU(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0xF0, 0x4C, 0xC2, 0xB3]), LDDQU(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestMASKMOVQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xF7, 0xDD]), MASKMOVQ(mm3, mm5).encode())
class TestMASKMOVDQU(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF7, 0xCE]), MASKMOVDQU(xmm1, xmm14).encode())
class TestMOVNTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0xE7, 0x6C, 0xD3, 0xA8]), MOVNTQ(qword[r11 + rdx*8 - 88], mm5).encode())
class TestMOVNTDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0xE7, 0x74, 0xC2, 0xB3]), MOVNTDQ(oword[r10 + rax*8 - 77], xmm14).encode())
class TestMOVNTDQA(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x2A, 0x4C, 0xC2, 0xB3]), MOVNTDQA(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMOVSXBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x20, 0xCE]), PMOVSXBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x20, 0x4C, 0xD3, 0xA8]), PMOVSXBW(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestPMOVSXBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x21, 0xCE]), PMOVSXBD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x21, 0x4C, 0xCC, 0x9D]), PMOVSXBD(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestPMOVSXBQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x22, 0xCE]), PMOVSXBQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x22, 0x4C, 0xED, 0x95]), PMOVSXBQ(xmm1, word[r13 + rbp*8 - 107]).encode())
class TestPMOVSXWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x23, 0xCE]), PMOVSXWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x23, 0x4C, 0xD3, 0xA8]), PMOVSXWD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestPMOVSXWQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x24, 0xCE]), PMOVSXWQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x24, 0x4C, 0xCC, 0x9D]), PMOVSXWQ(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestPMOVSXDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x25, 0xCE]), PMOVSXDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x25, 0x4C, 0xD3, 0xA8]), PMOVSXDQ(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestPMOVZXBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x30, 0xCE]), PMOVZXBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x30, 0x4C, 0xD3, 0xA8]), PMOVZXBW(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestPMOVZXBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x31, 0xCE]), PMOVZXBD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x31, 0x4C, 0xCC, 0x9D]), PMOVZXBD(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestPMOVZXBQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x32, 0xCE]), PMOVZXBQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x32, 0x4C, 0xED, 0x95]), PMOVZXBQ(xmm1, word[r13 + rbp*8 - 107]).encode())
class TestPMOVZXWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x33, 0xCE]), PMOVZXWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x33, 0x4C, 0xD3, 0xA8]), PMOVZXWD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestPMOVZXWQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x34, 0xCE]), PMOVZXWQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x34, 0x4C, 0xCC, 0x9D]), PMOVZXWQ(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestPMOVZXDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x35, 0xCE]), PMOVZXDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x35, 0x4C, 0xD3, 0xA8]), PMOVZXDQ(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestPEXTRB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0x3A, 0x14, 0xF5, 0x02]), PEXTRB(ebp, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x3A, 0x14, 0x74, 0xBE, 0x85, 0x02]), PEXTRB(byte[r14 + rdi*4 - 123], xmm14, 2).encode())
class TestPEXTRW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xC5, 0xED, 0x02]), PEXTRW(ebp, mm5, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xC5, 0xEE, 0x02]), PEXTRW(ebp, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x3A, 0x15, 0x74, 0xED, 0x95, 0x02]), PEXTRW(word[r13 + rbp*8 - 107], xmm14, 2).encode())
class TestPEXTRD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x44, 0x0F, 0x3A, 0x16, 0xF5, 0x02]), PEXTRD(ebp, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x45, 0x0F, 0x3A, 0x16, 0x74, 0xCC, 0x9D, 0x02]), PEXTRD(dword[r12 + rcx*8 - 99], xmm14, 2).encode())
class TestPEXTRQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x4C, 0x0F, 0x3A, 0x16, 0xF1, 0x02]), PEXTRQ(rcx, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x4D, 0x0F, 0x3A, 0x16, 0x74, 0xD3, 0xA8, 0x02]), PEXTRQ(qword[r11 + rdx*8 - 88], xmm14, 2).encode())
class TestPINSRB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x20, 0xC8, 0x02]), PINSRB(xmm1, r8d, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x20, 0x4C, 0xBE, 0x85, 0x02]), PINSRB(xmm1, byte[r14 + rdi*4 - 123], 2).encode())
class TestPINSRW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0xC4, 0xD8, 0x02]), PINSRW(mm3, r8d, 2).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xC4, 0x5C, 0xED, 0x95, 0x02]), PINSRW(mm3, word[r13 + rbp*8 - 107], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xC4, 0xC8, 0x02]), PINSRW(xmm1, r8d, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xC4, 0x4C, 0xED, 0x95, 0x02]), PINSRW(xmm1, word[r13 + rbp*8 - 107], 2).encode())
class TestPINSRD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x22, 0xC8, 0x02]), PINSRD(xmm1, r8d, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x22, 0x4C, 0xCC, 0x9D, 0x02]), PINSRD(xmm1, dword[r12 + rcx*8 - 99], 2).encode())
class TestPINSRQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x49, 0x0F, 0x3A, 0x22, 0xCF, 0x02]), PINSRQ(xmm1, r15, 2).encode())
self.assertEqual(bytearray([0x66, 0x49, 0x0F, 0x3A, 0x22, 0x4C, 0xD3, 0xA8, 0x02]), PINSRQ(xmm1, qword[r11 + rdx*8 - 88], 2).encode())
class TestPMOVMSKB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xD7, 0xED]), PMOVMSKB(ebp, mm5).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD7, 0xEE]), PMOVMSKB(ebp, xmm14).encode())
class TestPTEST(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x17, 0xCE]), PTEST(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x17, 0x4C, 0xC2, 0xB3]), PTEST(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPADDB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xFC, 0xDD]), PADDB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xFC, 0x5C, 0xD3, 0xA8]), PADDB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFC, 0xCE]), PADDB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFC, 0x4C, 0xC2, 0xB3]), PADDB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPADDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xFD, 0xDD]), PADDW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xFD, 0x5C, 0xD3, 0xA8]), PADDW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFD, 0xCE]), PADDW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFD, 0x4C, 0xC2, 0xB3]), PADDW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPADDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xFE, 0xDD]), PADDD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xFE, 0x5C, 0xD3, 0xA8]), PADDD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFE, 0xCE]), PADDD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFE, 0x4C, 0xC2, 0xB3]), PADDD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPADDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xD4, 0xDD]), PADDQ(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xD4, 0x5C, 0xD3, 0xA8]), PADDQ(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD4, 0xCE]), PADDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD4, 0x4C, 0xC2, 0xB3]), PADDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPADDSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xEC, 0xDD]), PADDSB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xEC, 0x5C, 0xD3, 0xA8]), PADDSB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEC, 0xCE]), PADDSB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEC, 0x4C, 0xC2, 0xB3]), PADDSB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPADDSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xED, 0xDD]), PADDSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xED, 0x5C, 0xD3, 0xA8]), PADDSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xED, 0xCE]), PADDSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xED, 0x4C, 0xC2, 0xB3]), PADDSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPADDUSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xDC, 0xDD]), PADDUSB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xDC, 0x5C, 0xD3, 0xA8]), PADDUSB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDC, 0xCE]), PADDUSB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDC, 0x4C, 0xC2, 0xB3]), PADDUSB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPADDUSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xDD, 0xDD]), PADDUSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xDD, 0x5C, 0xD3, 0xA8]), PADDUSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDD, 0xCE]), PADDUSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDD, 0x4C, 0xC2, 0xB3]), PADDUSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPHADDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x01, 0xDD]), PHADDW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x01, 0x5C, 0xD3, 0xA8]), PHADDW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x01, 0xCE]), PHADDW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x01, 0x4C, 0xC2, 0xB3]), PHADDW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPHADDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x02, 0xDD]), PHADDD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x02, 0x5C, 0xD3, 0xA8]), PHADDD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x02, 0xCE]), PHADDD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x02, 0x4C, 0xC2, 0xB3]), PHADDD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPHADDSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x03, 0xDD]), PHADDSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x03, 0x5C, 0xD3, 0xA8]), PHADDSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x03, 0xCE]), PHADDSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x03, 0x4C, 0xC2, 0xB3]), PHADDSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSUBB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xF8, 0xDD]), PSUBB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xF8, 0x5C, 0xD3, 0xA8]), PSUBB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF8, 0xCE]), PSUBB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF8, 0x4C, 0xC2, 0xB3]), PSUBB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSUBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xF9, 0xDD]), PSUBW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xF9, 0x5C, 0xD3, 0xA8]), PSUBW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF9, 0xCE]), PSUBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF9, 0x4C, 0xC2, 0xB3]), PSUBW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSUBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xFA, 0xDD]), PSUBD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xFA, 0x5C, 0xD3, 0xA8]), PSUBD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFA, 0xCE]), PSUBD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFA, 0x4C, 0xC2, 0xB3]), PSUBD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSUBQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xFB, 0xDD]), PSUBQ(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xFB, 0x5C, 0xD3, 0xA8]), PSUBQ(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFB, 0xCE]), PSUBQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xFB, 0x4C, 0xC2, 0xB3]), PSUBQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSUBSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xE8, 0xDD]), PSUBSB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xE8, 0x5C, 0xD3, 0xA8]), PSUBSB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE8, 0xCE]), PSUBSB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE8, 0x4C, 0xC2, 0xB3]), PSUBSB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSUBSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xE9, 0xDD]), PSUBSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xE9, 0x5C, 0xD3, 0xA8]), PSUBSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE9, 0xCE]), PSUBSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE9, 0x4C, 0xC2, 0xB3]), PSUBSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSUBUSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xD8, 0xDD]), PSUBUSB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xD8, 0x5C, 0xD3, 0xA8]), PSUBUSB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD8, 0xCE]), PSUBUSB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD8, 0x4C, 0xC2, 0xB3]), PSUBUSB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSUBUSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xD9, 0xDD]), PSUBUSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xD9, 0x5C, 0xD3, 0xA8]), PSUBUSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD9, 0xCE]), PSUBUSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD9, 0x4C, 0xC2, 0xB3]), PSUBUSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPHSUBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x05, 0xDD]), PHSUBW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x05, 0x5C, 0xD3, 0xA8]), PHSUBW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x05, 0xCE]), PHSUBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x05, 0x4C, 0xC2, 0xB3]), PHSUBW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPHSUBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x06, 0xDD]), PHSUBD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x06, 0x5C, 0xD3, 0xA8]), PHSUBD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x06, 0xCE]), PHSUBD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x06, 0x4C, 0xC2, 0xB3]), PHSUBD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPHSUBSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x07, 0xDD]), PHSUBSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x07, 0x5C, 0xD3, 0xA8]), PHSUBSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x07, 0xCE]), PHSUBSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x07, 0x4C, 0xC2, 0xB3]), PHSUBSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMAXSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3C, 0xCE]), PMAXSB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3C, 0x4C, 0xC2, 0xB3]), PMAXSB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMAXSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xEE, 0xDD]), PMAXSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xEE, 0x5C, 0xD3, 0xA8]), PMAXSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEE, 0xCE]), PMAXSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEE, 0x4C, 0xC2, 0xB3]), PMAXSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMAXSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3D, 0xCE]), PMAXSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3D, 0x4C, 0xC2, 0xB3]), PMAXSD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMAXUB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xDE, 0xDD]), PMAXUB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xDE, 0x5C, 0xD3, 0xA8]), PMAXUB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDE, 0xCE]), PMAXUB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDE, 0x4C, 0xC2, 0xB3]), PMAXUB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMAXUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3E, 0xCE]), PMAXUW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3E, 0x4C, 0xC2, 0xB3]), PMAXUW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMAXUD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3F, 0xCE]), PMAXUD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3F, 0x4C, 0xC2, 0xB3]), PMAXUD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMINSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x38, 0xCE]), PMINSB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x38, 0x4C, 0xC2, 0xB3]), PMINSB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMINSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xEA, 0xDD]), PMINSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xEA, 0x5C, 0xD3, 0xA8]), PMINSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEA, 0xCE]), PMINSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEA, 0x4C, 0xC2, 0xB3]), PMINSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMINSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x39, 0xCE]), PMINSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x39, 0x4C, 0xC2, 0xB3]), PMINSD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMINUB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xDA, 0xDD]), PMINUB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xDA, 0x5C, 0xD3, 0xA8]), PMINUB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDA, 0xCE]), PMINUB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDA, 0x4C, 0xC2, 0xB3]), PMINUB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMINUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3A, 0xCE]), PMINUW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3A, 0x4C, 0xC2, 0xB3]), PMINUW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMINUD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3B, 0xCE]), PMINUD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x3B, 0x4C, 0xC2, 0xB3]), PMINUD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSLLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x71, 0xF3, 0x02]), PSLLW(mm3, 2).encode())
self.assertEqual(bytearray([0x0F, 0xF1, 0xDD]), PSLLW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xF1, 0x5C, 0xD3, 0xA8]), PSLLW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x0F, 0x71, 0xF1, 0x02]), PSLLW(xmm1, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF1, 0xCE]), PSLLW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF1, 0x4C, 0xC2, 0xB3]), PSLLW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSLLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x72, 0xF3, 0x02]), PSLLD(mm3, 2).encode())
self.assertEqual(bytearray([0x0F, 0xF2, 0xDD]), PSLLD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xF2, 0x5C, 0xD3, 0xA8]), PSLLD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x0F, 0x72, 0xF1, 0x02]), PSLLD(xmm1, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF2, 0xCE]), PSLLD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF2, 0x4C, 0xC2, 0xB3]), PSLLD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSLLQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x73, 0xF3, 0x02]), PSLLQ(mm3, 2).encode())
self.assertEqual(bytearray([0x0F, 0xF3, 0xDD]), PSLLQ(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xF3, 0x5C, 0xD3, 0xA8]), PSLLQ(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x0F, 0x73, 0xF1, 0x02]), PSLLQ(xmm1, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF3, 0xCE]), PSLLQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF3, 0x4C, 0xC2, 0xB3]), PSLLQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSRLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x71, 0xD3, 0x02]), PSRLW(mm3, 2).encode())
self.assertEqual(bytearray([0x0F, 0xD1, 0xDD]), PSRLW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xD1, 0x5C, 0xD3, 0xA8]), PSRLW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x0F, 0x71, 0xD1, 0x02]), PSRLW(xmm1, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD1, 0xCE]), PSRLW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD1, 0x4C, 0xC2, 0xB3]), PSRLW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSRLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x72, 0xD3, 0x02]), PSRLD(mm3, 2).encode())
self.assertEqual(bytearray([0x0F, 0xD2, 0xDD]), PSRLD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xD2, 0x5C, 0xD3, 0xA8]), PSRLD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x0F, 0x72, 0xD1, 0x02]), PSRLD(xmm1, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD2, 0xCE]), PSRLD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD2, 0x4C, 0xC2, 0xB3]), PSRLD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSRLQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x73, 0xD3, 0x02]), PSRLQ(mm3, 2).encode())
self.assertEqual(bytearray([0x0F, 0xD3, 0xDD]), PSRLQ(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xD3, 0x5C, 0xD3, 0xA8]), PSRLQ(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x0F, 0x73, 0xD1, 0x02]), PSRLQ(xmm1, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD3, 0xCE]), PSRLQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD3, 0x4C, 0xC2, 0xB3]), PSRLQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSRAW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x71, 0xE3, 0x02]), PSRAW(mm3, 2).encode())
self.assertEqual(bytearray([0x0F, 0xE1, 0xDD]), PSRAW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xE1, 0x5C, 0xD3, 0xA8]), PSRAW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x0F, 0x71, 0xE1, 0x02]), PSRAW(xmm1, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE1, 0xCE]), PSRAW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE1, 0x4C, 0xC2, 0xB3]), PSRAW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSRAD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x72, 0xE3, 0x02]), PSRAD(mm3, 2).encode())
self.assertEqual(bytearray([0x0F, 0xE2, 0xDD]), PSRAD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xE2, 0x5C, 0xD3, 0xA8]), PSRAD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x0F, 0x72, 0xE1, 0x02]), PSRAD(xmm1, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE2, 0xCE]), PSRAD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE2, 0x4C, 0xC2, 0xB3]), PSRAD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMULLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xD5, 0xDD]), PMULLW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xD5, 0x5C, 0xD3, 0xA8]), PMULLW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD5, 0xCE]), PMULLW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xD5, 0x4C, 0xC2, 0xB3]), PMULLW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMULHW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xE5, 0xDD]), PMULHW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xE5, 0x5C, 0xD3, 0xA8]), PMULHW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE5, 0xCE]), PMULHW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE5, 0x4C, 0xC2, 0xB3]), PMULHW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMULHUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xE4, 0xDD]), PMULHUW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xE4, 0x5C, 0xD3, 0xA8]), PMULHUW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE4, 0xCE]), PMULHUW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE4, 0x4C, 0xC2, 0xB3]), PMULHUW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMULLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x40, 0xCE]), PMULLD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x40, 0x4C, 0xC2, 0xB3]), PMULLD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMULDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x28, 0xCE]), PMULDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x28, 0x4C, 0xC2, 0xB3]), PMULDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMULUDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xF4, 0xDD]), PMULUDQ(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xF4, 0x5C, 0xD3, 0xA8]), PMULUDQ(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF4, 0xCE]), PMULUDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF4, 0x4C, 0xC2, 0xB3]), PMULUDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMULHRSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x0B, 0xDD]), PMULHRSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x0B, 0x5C, 0xD3, 0xA8]), PMULHRSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x0B, 0xCE]), PMULHRSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x0B, 0x4C, 0xC2, 0xB3]), PMULHRSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMADDWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xF5, 0xDD]), PMADDWD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xF5, 0x5C, 0xD3, 0xA8]), PMADDWD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF5, 0xCE]), PMADDWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF5, 0x4C, 0xC2, 0xB3]), PMADDWD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPMADDUBSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x04, 0xDD]), PMADDUBSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x04, 0x5C, 0xD3, 0xA8]), PMADDUBSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x04, 0xCE]), PMADDUBSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x04, 0x4C, 0xC2, 0xB3]), PMADDUBSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPAVGB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xE0, 0xDD]), PAVGB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xE0, 0x5C, 0xD3, 0xA8]), PAVGB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE0, 0xCE]), PAVGB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE0, 0x4C, 0xC2, 0xB3]), PAVGB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPAVGW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xE3, 0xDD]), PAVGW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xE3, 0x5C, 0xD3, 0xA8]), PAVGW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE3, 0xCE]), PAVGW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE3, 0x4C, 0xC2, 0xB3]), PAVGW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSADBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xF6, 0xDD]), PSADBW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xF6, 0x5C, 0xD3, 0xA8]), PSADBW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF6, 0xCE]), PSADBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xF6, 0x4C, 0xC2, 0xB3]), PSADBW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestMPSADBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x42, 0xCE, 0x02]), MPSADBW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x42, 0x4C, 0xC2, 0xB3, 0x02]), MPSADBW(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestPHMINPOSUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x41, 0xCE]), PHMINPOSUW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x41, 0x4C, 0xC2, 0xB3]), PHMINPOSUW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPCMPEQB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x74, 0xDD]), PCMPEQB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x74, 0x5C, 0xD3, 0xA8]), PCMPEQB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x74, 0xCE]), PCMPEQB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x74, 0x4C, 0xC2, 0xB3]), PCMPEQB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPCMPEQW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x75, 0xDD]), PCMPEQW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x75, 0x5C, 0xD3, 0xA8]), PCMPEQW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x75, 0xCE]), PCMPEQW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x75, 0x4C, 0xC2, 0xB3]), PCMPEQW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPCMPEQD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x76, 0xDD]), PCMPEQD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x76, 0x5C, 0xD3, 0xA8]), PCMPEQD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x76, 0xCE]), PCMPEQD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x76, 0x4C, 0xC2, 0xB3]), PCMPEQD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPCMPEQQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x29, 0xCE]), PCMPEQQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x29, 0x4C, 0xC2, 0xB3]), PCMPEQQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPCMPGTB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x64, 0xDD]), PCMPGTB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x64, 0x5C, 0xD3, 0xA8]), PCMPGTB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x64, 0xCE]), PCMPGTB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x64, 0x4C, 0xC2, 0xB3]), PCMPGTB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPCMPGTW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x65, 0xDD]), PCMPGTW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x65, 0x5C, 0xD3, 0xA8]), PCMPGTW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x65, 0xCE]), PCMPGTW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x65, 0x4C, 0xC2, 0xB3]), PCMPGTW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPCMPGTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x66, 0xDD]), PCMPGTD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x66, 0x5C, 0xD3, 0xA8]), PCMPGTD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x66, 0xCE]), PCMPGTD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x66, 0x4C, 0xC2, 0xB3]), PCMPGTD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPCMPGTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x37, 0xCE]), PCMPGTQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x37, 0x4C, 0xC2, 0xB3]), PCMPGTQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPABSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x1C, 0xDD]), PABSB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x1C, 0x5C, 0xD3, 0xA8]), PABSB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x1C, 0xCE]), PABSB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x1C, 0x4C, 0xC2, 0xB3]), PABSB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPABSW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x1D, 0xDD]), PABSW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x1D, 0x5C, 0xD3, 0xA8]), PABSW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x1D, 0xCE]), PABSW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x1D, 0x4C, 0xC2, 0xB3]), PABSW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPABSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x1E, 0xDD]), PABSD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x1E, 0x5C, 0xD3, 0xA8]), PABSD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x1E, 0xCE]), PABSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x1E, 0x4C, 0xC2, 0xB3]), PABSD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSIGNB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x08, 0xDD]), PSIGNB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x08, 0x5C, 0xD3, 0xA8]), PSIGNB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x08, 0xCE]), PSIGNB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x08, 0x4C, 0xC2, 0xB3]), PSIGNB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSIGNW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x09, 0xDD]), PSIGNW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x09, 0x5C, 0xD3, 0xA8]), PSIGNW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x09, 0xCE]), PSIGNW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x09, 0x4C, 0xC2, 0xB3]), PSIGNW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSIGND(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x0A, 0xDD]), PSIGND(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x0A, 0x5C, 0xD3, 0xA8]), PSIGND(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x0A, 0xCE]), PSIGND(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x0A, 0x4C, 0xC2, 0xB3]), PSIGND(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPAND(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xDB, 0xDD]), PAND(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xDB, 0x5C, 0xD3, 0xA8]), PAND(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDB, 0xCE]), PAND(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDB, 0x4C, 0xC2, 0xB3]), PAND(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPANDN(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xDF, 0xDD]), PANDN(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xDF, 0x5C, 0xD3, 0xA8]), PANDN(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDF, 0xCE]), PANDN(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xDF, 0x4C, 0xC2, 0xB3]), PANDN(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPOR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xEB, 0xDD]), POR(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xEB, 0x5C, 0xD3, 0xA8]), POR(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEB, 0xCE]), POR(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEB, 0x4C, 0xC2, 0xB3]), POR(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPXOR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0xEF, 0xDD]), PXOR(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0xEF, 0x5C, 0xD3, 0xA8]), PXOR(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEF, 0xCE]), PXOR(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xEF, 0x4C, 0xC2, 0xB3]), PXOR(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPBLENDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0E, 0xCE, 0x02]), PBLENDW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0E, 0x4C, 0xC2, 0xB3, 0x02]), PBLENDW(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestPBLENDVB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x10, 0xCE]), PBLENDVB(xmm1, xmm14, xmm0).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x10, 0x4C, 0xC2, 0xB3]), PBLENDVB(xmm1, oword[r10 + rax*8 - 77], xmm0).encode())
class TestPUNPCKLBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x60, 0xDD]), PUNPCKLBW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x60, 0x5C, 0xCC, 0x9D]), PUNPCKLBW(mm3, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x60, 0xCE]), PUNPCKLBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x60, 0x4C, 0xC2, 0xB3]), PUNPCKLBW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPUNPCKLWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x61, 0xDD]), PUNPCKLWD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x61, 0x5C, 0xCC, 0x9D]), PUNPCKLWD(mm3, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x61, 0xCE]), PUNPCKLWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x61, 0x4C, 0xC2, 0xB3]), PUNPCKLWD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPUNPCKLDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x62, 0xDD]), PUNPCKLDQ(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x62, 0x5C, 0xCC, 0x9D]), PUNPCKLDQ(mm3, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x62, 0xCE]), PUNPCKLDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x62, 0x4C, 0xC2, 0xB3]), PUNPCKLDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPUNPCKLQDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6C, 0xCE]), PUNPCKLQDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6C, 0x4C, 0xC2, 0xB3]), PUNPCKLQDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPUNPCKHBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x68, 0xDD]), PUNPCKHBW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x68, 0x5C, 0xD3, 0xA8]), PUNPCKHBW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x68, 0xCE]), PUNPCKHBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x68, 0x4C, 0xC2, 0xB3]), PUNPCKHBW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPUNPCKHWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x69, 0xDD]), PUNPCKHWD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x69, 0x5C, 0xD3, 0xA8]), PUNPCKHWD(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x69, 0xCE]), PUNPCKHWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x69, 0x4C, 0xC2, 0xB3]), PUNPCKHWD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPUNPCKHDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x6A, 0xDD]), PUNPCKHDQ(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x6A, 0x5C, 0xD3, 0xA8]), PUNPCKHDQ(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6A, 0xCE]), PUNPCKHDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6A, 0x4C, 0xC2, 0xB3]), PUNPCKHDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPUNPCKHQDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6D, 0xCE]), PUNPCKHQDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6D, 0x4C, 0xC2, 0xB3]), PUNPCKHQDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPACKSSWB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x63, 0xDD]), PACKSSWB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x63, 0x5C, 0xD3, 0xA8]), PACKSSWB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x63, 0xCE]), PACKSSWB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x63, 0x4C, 0xC2, 0xB3]), PACKSSWB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPACKSSDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x6B, 0xDD]), PACKSSDW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x6B, 0x5C, 0xD3, 0xA8]), PACKSSDW(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6B, 0xCE]), PACKSSDW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x6B, 0x4C, 0xC2, 0xB3]), PACKSSDW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPACKUSWB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x67, 0xDD]), PACKUSWB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x67, 0x5C, 0xD3, 0xA8]), PACKUSWB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x67, 0xCE]), PACKUSWB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x67, 0x4C, 0xC2, 0xB3]), PACKUSWB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPACKUSDW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x2B, 0xCE]), PACKUSDW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x2B, 0x4C, 0xC2, 0xB3]), PACKUSDW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSHUFB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x38, 0x00, 0xDD]), PSHUFB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x38, 0x00, 0x5C, 0xD3, 0xA8]), PSHUFB(mm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x00, 0xCE]), PSHUFB(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x38, 0x00, 0x4C, 0xC2, 0xB3]), PSHUFB(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestPSHUFW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x70, 0xDD, 0x02]), PSHUFW(mm3, mm5, 2).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x70, 0x5C, 0xD3, 0xA8, 0x02]), PSHUFW(mm3, qword[r11 + rdx*8 - 88], 2).encode())
class TestPSHUFLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x70, 0xCE, 0x02]), PSHUFLW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x70, 0x4C, 0xC2, 0xB3, 0x02]), PSHUFLW(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestPSHUFHW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x70, 0xCE, 0x02]), PSHUFHW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x70, 0x4C, 0xC2, 0xB3, 0x02]), PSHUFHW(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestPSHUFD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x70, 0xCE, 0x02]), PSHUFD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x70, 0x4C, 0xC2, 0xB3, 0x02]), PSHUFD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestPSLLDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x0F, 0x73, 0xF9, 0x02]), PSLLDQ(xmm1, 2).encode())
class TestPSRLDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x0F, 0x73, 0xD9, 0x02]), PSRLDQ(xmm1, 2).encode())
class TestPALIGNR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x3A, 0x0F, 0xDD, 0x02]), PALIGNR(mm3, mm5, 2).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x3A, 0x0F, 0x5C, 0xD3, 0xA8, 0x02]), PALIGNR(mm3, qword[r11 + rdx*8 - 88], 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0F, 0xCE, 0x02]), PALIGNR(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x0F, 0x4C, 0xC2, 0xB3, 0x02]), PALIGNR(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestPCMPESTRI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x61, 0xCE, 0x02]), PCMPESTRI(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x61, 0x4C, 0xC2, 0xB3, 0x02]), PCMPESTRI(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestPCMPESTRM(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x60, 0xCE, 0x02]), PCMPESTRM(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x60, 0x4C, 0xC2, 0xB3, 0x02]), PCMPESTRM(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestPCMPISTRI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x63, 0xCE, 0x02]), PCMPISTRI(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x63, 0x4C, 0xC2, 0xB3, 0x02]), PCMPISTRI(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestPCMPISTRM(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x62, 0xCE, 0x02]), PCMPISTRM(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x3A, 0x62, 0x4C, 0xC2, 0xB3, 0x02]), PCMPISTRM(xmm1, oword[r10 + rax*8 - 77], 2).encode())
class TestCVTSS2SI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x2D, 0xEE]), CVTSS2SI(ebp, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x2D, 0x6C, 0xCC, 0x9D]), CVTSS2SI(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0x2D, 0xCE]), CVTSS2SI(rcx, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0x2D, 0x4C, 0xCC, 0x9D]), CVTSS2SI(rcx, dword[r12 + rcx*8 - 99]).encode())
class TestCVTTSS2SI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x2C, 0xEE]), CVTTSS2SI(ebp, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x2C, 0x6C, 0xCC, 0x9D]), CVTTSS2SI(ebp, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0x2C, 0xCE]), CVTTSS2SI(rcx, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0x2C, 0x4C, 0xCC, 0x9D]), CVTTSS2SI(rcx, dword[r12 + rcx*8 - 99]).encode())
class TestCVTSI2SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x2A, 0xC8]), CVTSI2SS(xmm1, r8d).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0x2A, 0xCF]), CVTSI2SS(xmm1, r15).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x2A, 0x4C, 0xCC, 0x9D]), CVTSI2SS(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF3, 0x49, 0x0F, 0x2A, 0x4C, 0xD3, 0xA8]), CVTSI2SS(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestCVTSD2SI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x2D, 0xEE]), CVTSD2SI(ebp, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x2D, 0x6C, 0xD3, 0xA8]), CVTSD2SI(ebp, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x2D, 0xCE]), CVTSD2SI(rcx, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x2D, 0x4C, 0xD3, 0xA8]), CVTSD2SI(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCVTTSD2SI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x2C, 0xEE]), CVTTSD2SI(ebp, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x2C, 0x6C, 0xD3, 0xA8]), CVTTSD2SI(ebp, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x2C, 0xCE]), CVTTSD2SI(rcx, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x2C, 0x4C, 0xD3, 0xA8]), CVTTSD2SI(rcx, qword[r11 + rdx*8 - 88]).encode())
class TestCVTSI2SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x2A, 0xC8]), CVTSI2SD(xmm1, r8d).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x2A, 0xCF]), CVTSI2SD(xmm1, r15).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x2A, 0x4C, 0xCC, 0x9D]), CVTSI2SD(xmm1, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xF2, 0x49, 0x0F, 0x2A, 0x4C, 0xD3, 0xA8]), CVTSI2SD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestCVTPS2DQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5B, 0xCE]), CVTPS2DQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5B, 0x4C, 0xC2, 0xB3]), CVTPS2DQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestCVTTPS2DQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5B, 0xCE]), CVTTPS2DQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5B, 0x4C, 0xC2, 0xB3]), CVTTPS2DQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestCVTDQ2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x5B, 0xCE]), CVTDQ2PS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x5B, 0x4C, 0xC2, 0xB3]), CVTDQ2PS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestCVTPD2DQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0xE6, 0xCE]), CVTPD2DQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0xE6, 0x4C, 0xC2, 0xB3]), CVTPD2DQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestCVTTPD2DQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE6, 0xCE]), CVTTPD2DQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0xE6, 0x4C, 0xC2, 0xB3]), CVTTPD2DQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestCVTDQ2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xE6, 0xCE]), CVTDQ2PD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0xE6, 0x4C, 0xD3, 0xA8]), CVTDQ2PD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestCVTPS2PI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x2D, 0xDE]), CVTPS2PI(mm3, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x2D, 0x5C, 0xD3, 0xA8]), CVTPS2PI(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestCVTTPS2PI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x2C, 0xDE]), CVTTPS2PI(mm3, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x2C, 0x5C, 0xD3, 0xA8]), CVTTPS2PI(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestCVTPI2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x2A, 0xCD]), CVTPI2PS(xmm1, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x2A, 0x4C, 0xD3, 0xA8]), CVTPI2PS(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestCVTPD2PI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x2D, 0xDE]), CVTPD2PI(mm3, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x2D, 0x5C, 0xC2, 0xB3]), CVTPD2PI(mm3, oword[r10 + rax*8 - 77]).encode())
class TestCVTTPD2PI(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x2C, 0xDE]), CVTTPD2PI(mm3, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x2C, 0x5C, 0xC2, 0xB3]), CVTTPD2PI(mm3, oword[r10 + rax*8 - 77]).encode())
class TestCVTPI2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x0F, 0x2A, 0xCD]), CVTPI2PD(xmm1, mm5).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x2A, 0x4C, 0xD3, 0xA8]), CVTPI2PD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestCVTSD2SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5A, 0xCE]), CVTSD2SS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x5A, 0x4C, 0xD3, 0xA8]), CVTSD2SS(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestCVTSS2SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5A, 0xCE]), CVTSS2SD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF3, 0x41, 0x0F, 0x5A, 0x4C, 0xCC, 0x9D]), CVTSS2SD(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestCVTPD2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5A, 0xCE]), CVTPD2PS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x5A, 0x4C, 0xC2, 0xB3]), CVTPD2PS(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestCVTPS2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0x5A, 0xCE]), CVTPS2PD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x5A, 0x4C, 0xD3, 0xA8]), CVTPS2PD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestLDMXCSR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0xAE, 0x54, 0xCC, 0x9D]), LDMXCSR(dword[r12 + rcx*8 - 99]).encode())
class TestSTMXCSR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x41, 0x0F, 0xAE, 0x5C, 0xCC, 0x9D]), STMXCSR(dword[r12 + rcx*8 - 99]).encode())
class TestEMMS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x77]), EMMS().encode())
|
# This file is auto-generated by /codegen/x86_64_test_encoding.py
# Reference opcodes are generated by:
# GNU assembler (GNU Binutils) 2.28.51.20170402
from peachpy.x86_64 import *
import unittest
class TestPAVGUSB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xBF]), PAVGUSB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xBF]), PAVGUSB(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPMULHRW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xB7]), PMULHRW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xB7]), PMULHRW(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPF2ID(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x1D]), PF2ID(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x1D]), PF2ID(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPF2IW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x1C]), PF2IW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x1C]), PF2IW(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPI2FW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x0C]), PI2FW(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x0C]), PI2FW(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPI2FD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x0D]), PI2FD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x0D]), PI2FD(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFADD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x9E]), PFADD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x9E]), PFADD(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFSUB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x9A]), PFSUB(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x9A]), PFSUB(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFSUBR(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xAA]), PFSUBR(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xAA]), PFSUBR(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFMUL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xB4]), PFMUL(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xB4]), PFMUL(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFMAX(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xA4]), PFMAX(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xA4]), PFMAX(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFMIN(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x94]), PFMIN(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x94]), PFMIN(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFACC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xAE]), PFACC(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xAE]), PFACC(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFNACC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x8A]), PFNACC(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x8A]), PFNACC(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFPNACC(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x8E]), PFPNACC(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x8E]), PFPNACC(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPSWAPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xBB]), PSWAPD(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xBB]), PSWAPD(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFCMPEQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xB0]), PFCMPEQ(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xB0]), PFCMPEQ(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFCMPGT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xA0]), PFCMPGT(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xA0]), PFCMPGT(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFCMPGE(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x90]), PFCMPGE(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x90]), PFCMPGE(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFRCP(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x96]), PFRCP(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x96]), PFRCP(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFRCPIT1(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xA6]), PFRCPIT1(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xA6]), PFRCPIT1(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFRCPIT2(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xB6]), PFRCPIT2(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xB6]), PFRCPIT2(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFRSQRT(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0x97]), PFRSQRT(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0x97]), PFRSQRT(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestPFRSQIT1(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0F, 0xDD, 0xA7]), PFRSQIT1(mm3, mm5).encode())
self.assertEqual(bytearray([0x41, 0x0F, 0x0F, 0x5C, 0xD3, 0xA8, 0xA7]), PFRSQIT1(mm3, qword[r11 + rdx*8 - 88]).encode())
class TestFEMMS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x0F, 0x0E]), FEMMS().encode())
class TestMOVNTSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF3, 0x45, 0x0F, 0x2B, 0x74, 0xCC, 0x9D]), MOVNTSS(dword[r12 + rcx*8 - 99], xmm14).encode())
class TestMOVNTSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x45, 0x0F, 0x2B, 0x74, 0xD3, 0xA8]), MOVNTSD(qword[r11 + rdx*8 - 88], xmm14).encode())
class TestINSERTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x79, 0xCE]), INSERTQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0xF2, 0x41, 0x0F, 0x78, 0xCE, 0x02, 0x02]), INSERTQ(xmm1, xmm14, 2, 2).encode())
class TestEXTRQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x66, 0x41, 0x0F, 0x79, 0xCE]), EXTRQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x66, 0x0F, 0x78, 0xC1, 0x02, 0x02]), EXTRQ(xmm1, 2, 2).encode())
class TestVPPERM(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xA3, 0xCB, 0x90]), VPPERM(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x88, 0xA3, 0x4C, 0xC2, 0xB3, 0x30]), VPPERM(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xA3, 0x4C, 0xC2, 0xB3, 0x90]), VPPERM(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPCMOV(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xA2, 0xCB, 0x90]), VPCMOV(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x88, 0xA2, 0x4C, 0xC2, 0xB3, 0x30]), VPCMOV(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xA2, 0x4C, 0xC2, 0xB3, 0x90]), VPCMOV(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xE8, 0x04, 0xA2, 0xD4, 0xA0]), VPCMOV(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x84, 0xA2, 0x54, 0xD9, 0xBE, 0x40]), VPCMOV(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x04, 0xA2, 0x54, 0xD9, 0xBE, 0xA0]), VPCMOV(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVPROTB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC8, 0x78, 0xC0, 0xCE, 0x02]), VPROTB(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x90, 0xCE]), VPROTB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x90, 0x4C, 0xC2, 0xB3]), VPROTB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x78, 0xC0, 0x4C, 0xC2, 0xB3, 0x02]), VPROTB(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x90, 0x4C, 0xC2, 0xB3]), VPROTB(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPROTW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC8, 0x78, 0xC1, 0xCE, 0x02]), VPROTW(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x91, 0xCE]), VPROTW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x91, 0x4C, 0xC2, 0xB3]), VPROTW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x78, 0xC1, 0x4C, 0xC2, 0xB3, 0x02]), VPROTW(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x91, 0x4C, 0xC2, 0xB3]), VPROTW(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPROTD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC8, 0x78, 0xC2, 0xCE, 0x02]), VPROTD(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x92, 0xCE]), VPROTD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x92, 0x4C, 0xC2, 0xB3]), VPROTD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x78, 0xC2, 0x4C, 0xC2, 0xB3, 0x02]), VPROTD(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x92, 0x4C, 0xC2, 0xB3]), VPROTD(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPROTQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC8, 0x78, 0xC3, 0xCE, 0x02]), VPROTQ(xmm1, xmm14, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x93, 0xCE]), VPROTQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x93, 0x4C, 0xC2, 0xB3]), VPROTQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x78, 0xC3, 0x4C, 0xC2, 0xB3, 0x02]), VPROTQ(xmm1, oword[r10 + rax*8 - 77], 2).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x93, 0x4C, 0xC2, 0xB3]), VPROTQ(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPSHAB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x98, 0xCE]), VPSHAB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x98, 0x4C, 0xC2, 0xB3]), VPSHAB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x98, 0x4C, 0xC2, 0xB3]), VPSHAB(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPSHAW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x99, 0xCE]), VPSHAW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x99, 0x4C, 0xC2, 0xB3]), VPSHAW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x99, 0x4C, 0xC2, 0xB3]), VPSHAW(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPSHAD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x9A, 0xCE]), VPSHAD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x9A, 0x4C, 0xC2, 0xB3]), VPSHAD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x9A, 0x4C, 0xC2, 0xB3]), VPSHAD(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPSHAQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x9B, 0xCE]), VPSHAQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x9B, 0x4C, 0xC2, 0xB3]), VPSHAQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x9B, 0x4C, 0xC2, 0xB3]), VPSHAQ(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPSHLB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x94, 0xCE]), VPSHLB(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x94, 0x4C, 0xC2, 0xB3]), VPSHLB(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x94, 0x4C, 0xC2, 0xB3]), VPSHLB(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPSHLW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x95, 0xCE]), VPSHLW(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x95, 0x4C, 0xC2, 0xB3]), VPSHLW(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x95, 0x4C, 0xC2, 0xB3]), VPSHLW(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPSHLD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x96, 0xCE]), VPSHLD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x96, 0x4C, 0xC2, 0xB3]), VPSHLD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x96, 0x4C, 0xC2, 0xB3]), VPSHLD(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPSHLQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x97, 0xCE]), VPSHLQ(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x88, 0x97, 0x4C, 0xC2, 0xB3]), VPSHLQ(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x60, 0x97, 0x4C, 0xC2, 0xB3]), VPSHLQ(xmm1, oword[r10 + rax*8 - 77], xmm3).encode())
class TestVPCOMB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xCC, 0xCB, 0x02]), VPCOMB(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xCC, 0x4C, 0xC2, 0xB3, 0x02]), VPCOMB(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCOMW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xCD, 0xCB, 0x02]), VPCOMW(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xCD, 0x4C, 0xC2, 0xB3, 0x02]), VPCOMW(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCOMD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xCE, 0xCB, 0x02]), VPCOMD(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xCE, 0x4C, 0xC2, 0xB3, 0x02]), VPCOMD(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCOMQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xCF, 0xCB, 0x02]), VPCOMQ(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xCF, 0x4C, 0xC2, 0xB3, 0x02]), VPCOMQ(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCOMUB(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xEC, 0xCB, 0x02]), VPCOMUB(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xEC, 0x4C, 0xC2, 0xB3, 0x02]), VPCOMUB(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCOMUW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xED, 0xCB, 0x02]), VPCOMUW(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xED, 0x4C, 0xC2, 0xB3, 0x02]), VPCOMUW(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCOMUD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xEE, 0xCB, 0x02]), VPCOMUD(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xEE, 0x4C, 0xC2, 0xB3, 0x02]), VPCOMUD(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestVPCOMUQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xEF, 0xCB, 0x02]), VPCOMUQ(xmm1, xmm14, xmm3, 2).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xEF, 0x4C, 0xC2, 0xB3, 0x02]), VPCOMUQ(xmm1, xmm14, oword[r10 + rax*8 - 77], 2).encode())
class TestVPHADDBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC1, 0xCE]), VPHADDBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC1, 0x4C, 0xC2, 0xB3]), VPHADDBW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC2, 0xCE]), VPHADDBD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC2, 0x4C, 0xC2, 0xB3]), VPHADDBD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDBQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC3, 0xCE]), VPHADDBQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC3, 0x4C, 0xC2, 0xB3]), VPHADDBQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC6, 0xCE]), VPHADDWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC6, 0x4C, 0xC2, 0xB3]), VPHADDWD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDWQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC7, 0xCE]), VPHADDWQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xC7, 0x4C, 0xC2, 0xB3]), VPHADDWQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xCB, 0xCE]), VPHADDDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xCB, 0x4C, 0xC2, 0xB3]), VPHADDDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDUBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD1, 0xCE]), VPHADDUBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD1, 0x4C, 0xC2, 0xB3]), VPHADDUBW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDUBD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD2, 0xCE]), VPHADDUBD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD2, 0x4C, 0xC2, 0xB3]), VPHADDUBD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDUBQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD3, 0xCE]), VPHADDUBQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD3, 0x4C, 0xC2, 0xB3]), VPHADDUBQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDUWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD6, 0xCE]), VPHADDUWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD6, 0x4C, 0xC2, 0xB3]), VPHADDUWD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDUWQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD7, 0xCE]), VPHADDUWQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xD7, 0x4C, 0xC2, 0xB3]), VPHADDUWQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHADDUDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xDB, 0xCE]), VPHADDUDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xDB, 0x4C, 0xC2, 0xB3]), VPHADDUDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHSUBBW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xE1, 0xCE]), VPHSUBBW(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xE1, 0x4C, 0xC2, 0xB3]), VPHSUBBW(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHSUBWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xE2, 0xCE]), VPHSUBWD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xE2, 0x4C, 0xC2, 0xB3]), VPHSUBWD(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPHSUBDQ(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xE3, 0xCE]), VPHSUBDQ(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0xE3, 0x4C, 0xC2, 0xB3]), VPHSUBDQ(xmm1, oword[r10 + rax*8 - 77]).encode())
class TestVPMACSDQH(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x9F, 0xCB, 0x90]), VPMACSDQH(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x9F, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSDQH(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMACSDQL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x97, 0xCB, 0x90]), VPMACSDQL(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x97, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSDQL(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMACSDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x9E, 0xCB, 0x90]), VPMACSDD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x9E, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSDD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMACSWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x96, 0xCB, 0x90]), VPMACSWD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x96, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSWD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMACSWW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x95, 0xCB, 0x90]), VPMACSWW(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x95, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSWW(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMADCSWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xB6, 0xCB, 0x90]), VPMADCSWD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xB6, 0x4C, 0xC2, 0xB3, 0x90]), VPMADCSWD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMACSSDD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x8E, 0xCB, 0x90]), VPMACSSDD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x8E, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSSDD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMACSSDQH(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x8F, 0xCB, 0x90]), VPMACSSDQH(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x8F, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSSDQH(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMACSSDQL(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x87, 0xCB, 0x90]), VPMACSSDQL(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x87, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSSDQL(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMACSSWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x86, 0xCB, 0x90]), VPMACSSWD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x86, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSSWD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMACSSWW(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0x85, 0xCB, 0x90]), VPMACSSWW(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0x85, 0x4C, 0xC2, 0xB3, 0x90]), VPMACSSWW(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVPMADCSSWD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xE8, 0x08, 0xA6, 0xCB, 0x90]), VPMADCSSWD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0x8F, 0xC8, 0x08, 0xA6, 0x4C, 0xC2, 0xB3, 0x90]), VPMADCSSWD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
class TestVFRCZSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0x82, 0xCE]), VFRCZSS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0x82, 0x4C, 0xCC, 0x9D]), VFRCZSS(xmm1, dword[r12 + rcx*8 - 99]).encode())
class TestVFRCZSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0x83, 0xCE]), VFRCZSD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0x83, 0x4C, 0xD3, 0xA8]), VFRCZSD(xmm1, qword[r11 + rdx*8 - 88]).encode())
class TestVFRCZPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0x80, 0xCE]), VFRCZPS(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0x80, 0x4C, 0xC2, 0xB3]), VFRCZPS(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x7C, 0x80, 0xD7]), VFRCZPS(ymm2, ymm15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x7C, 0x80, 0x54, 0xD9, 0xBE]), VFRCZPS(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVFRCZPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0x81, 0xCE]), VFRCZPD(xmm1, xmm14).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x78, 0x81, 0x4C, 0xC2, 0xB3]), VFRCZPD(xmm1, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x7C, 0x81, 0xD7]), VFRCZPD(ymm2, ymm15).encode())
self.assertEqual(bytearray([0x8F, 0xC9, 0x7C, 0x81, 0x54, 0xD9, 0xBE]), VFRCZPD(ymm2, hword[r9 + rbx*8 - 66]).encode())
class TestVPERMIL2PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x49, 0xCB, 0x93]), VPERMIL2PD(xmm1, xmm14, xmm3, xmm9, 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x49, 0x4C, 0xC2, 0xB3, 0x33]), VPERMIL2PD(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77], 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x49, 0x4C, 0xC2, 0xB3, 0x93]), VPERMIL2PD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9, 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x49, 0xD4, 0xA3]), VPERMIL2PD(ymm2, ymm15, ymm4, ymm10, 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x49, 0x54, 0xD9, 0xBE, 0x43]), VPERMIL2PD(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66], 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x49, 0x54, 0xD9, 0xBE, 0xA3]), VPERMIL2PD(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10, 0b11).encode())
class TestVPERMIL2PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xE3, 0x09, 0x48, 0xCB, 0x93]), VPERMIL2PS(xmm1, xmm14, xmm3, xmm9, 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x48, 0x4C, 0xC2, 0xB3, 0x33]), VPERMIL2PS(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77], 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x48, 0x4C, 0xC2, 0xB3, 0x93]), VPERMIL2PS(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9, 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xE3, 0x05, 0x48, 0xD4, 0xA3]), VPERMIL2PS(ymm2, ymm15, ymm4, ymm10, 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x48, 0x54, 0xD9, 0xBE, 0x43]), VPERMIL2PS(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66], 0b11).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x48, 0x54, 0xD9, 0xBE, 0xA3]), VPERMIL2PS(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10, 0b11).encode())
|
# This file is auto-generated by /codegen/x86_64_test_encoding.py
# Reference opcodes are generated by:
# GNU assembler (GNU Binutils) 2.28.51.20170402
from peachpy.x86_64 import *
import unittest
class TestVFMADD132SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x99, 0x74, 0x24, 0xE0]), VFMADD132SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x99, 0xCB]), VFMADD132SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x99, 0x4C, 0xCC, 0x9D]), VFMADD132SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0x99, 0xF3]), VFMADD132SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMADD213SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xA9, 0x74, 0x24, 0xE0]), VFMADD213SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xA9, 0xCB]), VFMADD213SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xA9, 0x4C, 0xCC, 0x9D]), VFMADD213SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xA9, 0xF3]), VFMADD213SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMADD231SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xB9, 0x74, 0x24, 0xE0]), VFMADD231SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xB9, 0xCB]), VFMADD231SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xB9, 0x4C, 0xCC, 0x9D]), VFMADD231SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xB9, 0xF3]), VFMADD231SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMADDSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6A, 0xC9, 0x30]), VFMADDSS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6A, 0x4C, 0xCC, 0x9D, 0x30]), VFMADDSS(xmm1, xmm14, xmm3, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x6A, 0x4C, 0xCC, 0x9D, 0x90]), VFMADDSS(xmm1, xmm14, dword[r12 + rcx*8 - 99], xmm9).encode())
class TestVFMSUB132SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x9B, 0x74, 0x24, 0xE0]), VFMSUB132SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x9B, 0xCB]), VFMSUB132SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x9B, 0x4C, 0xCC, 0x9D]), VFMSUB132SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0x9B, 0xF3]), VFMSUB132SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMSUB213SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xAB, 0x74, 0x24, 0xE0]), VFMSUB213SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xAB, 0xCB]), VFMSUB213SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xAB, 0x4C, 0xCC, 0x9D]), VFMSUB213SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xAB, 0xF3]), VFMSUB213SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMSUB231SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xBB, 0x74, 0x24, 0xE0]), VFMSUB231SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xBB, 0xCB]), VFMSUB231SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xBB, 0x4C, 0xCC, 0x9D]), VFMSUB231SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xBB, 0xF3]), VFMSUB231SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMSUBSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6E, 0xC9, 0x30]), VFMSUBSS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6E, 0x4C, 0xCC, 0x9D, 0x30]), VFMSUBSS(xmm1, xmm14, xmm3, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x6E, 0x4C, 0xCC, 0x9D, 0x90]), VFMSUBSS(xmm1, xmm14, dword[r12 + rcx*8 - 99], xmm9).encode())
class TestVFNMADD132SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x9D, 0x74, 0x24, 0xE0]), VFNMADD132SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x9D, 0xCB]), VFNMADD132SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x9D, 0x4C, 0xCC, 0x9D]), VFNMADD132SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0x9D, 0xF3]), VFNMADD132SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMADD213SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xAD, 0x74, 0x24, 0xE0]), VFNMADD213SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xAD, 0xCB]), VFNMADD213SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xAD, 0x4C, 0xCC, 0x9D]), VFNMADD213SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xAD, 0xF3]), VFNMADD213SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMADD231SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xBD, 0x74, 0x24, 0xE0]), VFNMADD231SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xBD, 0xCB]), VFNMADD231SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xBD, 0x4C, 0xCC, 0x9D]), VFNMADD231SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xBD, 0xF3]), VFNMADD231SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMADDSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7A, 0xC9, 0x30]), VFNMADDSS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7A, 0x4C, 0xCC, 0x9D, 0x30]), VFNMADDSS(xmm1, xmm14, xmm3, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x7A, 0x4C, 0xCC, 0x9D, 0x90]), VFNMADDSS(xmm1, xmm14, dword[r12 + rcx*8 - 99], xmm9).encode())
class TestVFNMSUB132SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x9F, 0x74, 0x24, 0xE0]), VFNMSUB132SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x9F, 0xCB]), VFNMSUB132SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x9F, 0x4C, 0xCC, 0x9D]), VFNMSUB132SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0x9F, 0xF3]), VFNMSUB132SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMSUB213SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xAF, 0x74, 0x24, 0xE0]), VFNMSUB213SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xAF, 0xCB]), VFNMSUB213SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xAF, 0x4C, 0xCC, 0x9D]), VFNMSUB213SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xAF, 0xF3]), VFNMSUB213SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMSUB231SS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xBF, 0x74, 0x24, 0xE0]), VFNMSUB231SS(xmm30(k2.z), xmm4, dword[r12 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xBF, 0xCB]), VFNMSUB231SS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xBF, 0x4C, 0xCC, 0x9D]), VFNMSUB231SS(xmm1, xmm14, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x9A, 0xBF, 0xF3]), VFNMSUB231SS(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMSUBSS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7E, 0xC9, 0x30]), VFNMSUBSS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7E, 0x4C, 0xCC, 0x9D, 0x30]), VFNMSUBSS(xmm1, xmm14, xmm3, dword[r12 + rcx*8 - 99]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x7E, 0x4C, 0xCC, 0x9D, 0x90]), VFNMSUBSS(xmm1, xmm14, dword[r12 + rcx*8 - 99], xmm9).encode())
class TestVFMADD132SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x99, 0x73, 0xF0]), VFMADD132SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x99, 0xCB]), VFMADD132SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x99, 0x4C, 0xD3, 0xA8]), VFMADD132SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0x99, 0xF3]), VFMADD132SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMADD213SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xA9, 0x73, 0xF0]), VFMADD213SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xA9, 0xCB]), VFMADD213SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xA9, 0x4C, 0xD3, 0xA8]), VFMADD213SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xA9, 0xF3]), VFMADD213SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMADD231SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xB9, 0x73, 0xF0]), VFMADD231SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xB9, 0xCB]), VFMADD231SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xB9, 0x4C, 0xD3, 0xA8]), VFMADD231SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xB9, 0xF3]), VFMADD231SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMADDSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6B, 0xC9, 0x30]), VFMADDSD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6B, 0x4C, 0xD3, 0xA8, 0x30]), VFMADDSD(xmm1, xmm14, xmm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x6B, 0x4C, 0xD3, 0xA8, 0x90]), VFMADDSD(xmm1, xmm14, qword[r11 + rdx*8 - 88], xmm9).encode())
class TestVFMSUB132SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x9B, 0x73, 0xF0]), VFMSUB132SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x9B, 0xCB]), VFMSUB132SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x9B, 0x4C, 0xD3, 0xA8]), VFMSUB132SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0x9B, 0xF3]), VFMSUB132SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMSUB213SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xAB, 0x73, 0xF0]), VFMSUB213SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xAB, 0xCB]), VFMSUB213SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xAB, 0x4C, 0xD3, 0xA8]), VFMSUB213SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xAB, 0xF3]), VFMSUB213SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMSUB231SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xBB, 0x73, 0xF0]), VFMSUB231SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xBB, 0xCB]), VFMSUB231SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xBB, 0x4C, 0xD3, 0xA8]), VFMSUB231SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xBB, 0xF3]), VFMSUB231SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFMSUBSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6F, 0xC9, 0x30]), VFMSUBSD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6F, 0x4C, 0xD3, 0xA8, 0x30]), VFMSUBSD(xmm1, xmm14, xmm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x6F, 0x4C, 0xD3, 0xA8, 0x90]), VFMSUBSD(xmm1, xmm14, qword[r11 + rdx*8 - 88], xmm9).encode())
class TestVFNMADD132SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x9D, 0x73, 0xF0]), VFNMADD132SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x9D, 0xCB]), VFNMADD132SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x9D, 0x4C, 0xD3, 0xA8]), VFNMADD132SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0x9D, 0xF3]), VFNMADD132SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMADD213SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xAD, 0x73, 0xF0]), VFNMADD213SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xAD, 0xCB]), VFNMADD213SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xAD, 0x4C, 0xD3, 0xA8]), VFNMADD213SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xAD, 0xF3]), VFNMADD213SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMADD231SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xBD, 0x73, 0xF0]), VFNMADD231SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xBD, 0xCB]), VFNMADD231SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xBD, 0x4C, 0xD3, 0xA8]), VFNMADD231SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xBD, 0xF3]), VFNMADD231SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMADDSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7B, 0xC9, 0x30]), VFNMADDSD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7B, 0x4C, 0xD3, 0xA8, 0x30]), VFNMADDSD(xmm1, xmm14, xmm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x7B, 0x4C, 0xD3, 0xA8, 0x90]), VFNMADDSD(xmm1, xmm14, qword[r11 + rdx*8 - 88], xmm9).encode())
class TestVFNMSUB132SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x9F, 0x73, 0xF0]), VFNMSUB132SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x9F, 0xCB]), VFNMSUB132SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x9F, 0x4C, 0xD3, 0xA8]), VFNMSUB132SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0x9F, 0xF3]), VFNMSUB132SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMSUB213SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xAF, 0x73, 0xF0]), VFNMSUB213SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xAF, 0xCB]), VFNMSUB213SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xAF, 0x4C, 0xD3, 0xA8]), VFNMSUB213SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xAF, 0xF3]), VFNMSUB213SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMSUB231SD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xBF, 0x73, 0xF0]), VFNMSUB231SD(xmm30(k2.z), xmm4, qword[r11 - 128]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xBF, 0xCB]), VFNMSUB231SD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xBF, 0x4C, 0xD3, 0xA8]), VFNMSUB231SD(xmm1, xmm14, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x9A, 0xBF, 0xF3]), VFNMSUB231SD(xmm30(k2.z), xmm4, xmm19, {rn_sae}).encode())
class TestVFNMSUBSD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7F, 0xC9, 0x30]), VFNMSUBSD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7F, 0x4C, 0xD3, 0xA8, 0x30]), VFNMSUBSD(xmm1, xmm14, xmm3, qword[r11 + rdx*8 - 88]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x7F, 0x4C, 0xD3, 0xA8, 0x90]), VFNMSUBSD(xmm1, xmm14, qword[r11 + rdx*8 - 88], xmm9).encode())
class TestVFMADD132PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x98, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADD132PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x98, 0xF3]), VFMADD132PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x98, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD132PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x98, 0xDC]), VFMADD132PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x98, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD132PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x98, 0xCB]), VFMADD132PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x98, 0x4C, 0xC2, 0xB3]), VFMADD132PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x98, 0xD4]), VFMADD132PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x98, 0x54, 0xD9, 0xBE]), VFMADD132PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0x98, 0xC9]), VFMADD132PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADD213PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xA8, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADD213PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xA8, 0xF3]), VFMADD213PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xA8, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD213PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xA8, 0xDC]), VFMADD213PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xA8, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD213PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xA8, 0xCB]), VFMADD213PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xA8, 0x4C, 0xC2, 0xB3]), VFMADD213PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xA8, 0xD4]), VFMADD213PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xA8, 0x54, 0xD9, 0xBE]), VFMADD213PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xA8, 0xC9]), VFMADD213PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADD231PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xB8, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADD231PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xB8, 0xF3]), VFMADD231PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xB8, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD231PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xB8, 0xDC]), VFMADD231PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xB8, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD231PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xB8, 0xCB]), VFMADD231PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xB8, 0x4C, 0xC2, 0xB3]), VFMADD231PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xB8, 0xD4]), VFMADD231PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xB8, 0x54, 0xD9, 0xBE]), VFMADD231PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xB8, 0xC9]), VFMADD231PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x68, 0xC9, 0x30]), VFMADDPS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x68, 0x4C, 0xC2, 0xB3, 0x30]), VFMADDPS(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x68, 0x4C, 0xC2, 0xB3, 0x90]), VFMADDPS(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x68, 0xD2, 0x40]), VFMADDPS(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x68, 0x54, 0xD9, 0xBE, 0x40]), VFMADDPS(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x68, 0x54, 0xD9, 0xBE, 0xA0]), VFMADDPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFMSUB132PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x9A, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUB132PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x9A, 0xF3]), VFMSUB132PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x9A, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB132PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x9A, 0xDC]), VFMSUB132PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x9A, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB132PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x9A, 0xCB]), VFMSUB132PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x9A, 0x4C, 0xC2, 0xB3]), VFMSUB132PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x9A, 0xD4]), VFMSUB132PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x9A, 0x54, 0xD9, 0xBE]), VFMSUB132PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0x9A, 0xC9]), VFMSUB132PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUB213PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xAA, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUB213PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xAA, 0xF3]), VFMSUB213PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xAA, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB213PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xAA, 0xDC]), VFMSUB213PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xAA, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB213PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xAA, 0xCB]), VFMSUB213PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xAA, 0x4C, 0xC2, 0xB3]), VFMSUB213PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xAA, 0xD4]), VFMSUB213PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xAA, 0x54, 0xD9, 0xBE]), VFMSUB213PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xAA, 0xC9]), VFMSUB213PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUB231PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xBA, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUB231PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xBA, 0xF3]), VFMSUB231PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xBA, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB231PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xBA, 0xDC]), VFMSUB231PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xBA, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB231PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xBA, 0xCB]), VFMSUB231PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xBA, 0x4C, 0xC2, 0xB3]), VFMSUB231PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xBA, 0xD4]), VFMSUB231PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xBA, 0x54, 0xD9, 0xBE]), VFMSUB231PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xBA, 0xC9]), VFMSUB231PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUBPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6C, 0xC9, 0x30]), VFMSUBPS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6C, 0x4C, 0xC2, 0xB3, 0x30]), VFMSUBPS(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x6C, 0x4C, 0xC2, 0xB3, 0x90]), VFMSUBPS(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x6C, 0xD2, 0x40]), VFMSUBPS(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x6C, 0x54, 0xD9, 0xBE, 0x40]), VFMSUBPS(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x6C, 0x54, 0xD9, 0xBE, 0xA0]), VFMSUBPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFNMADD132PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x9C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMADD132PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x9C, 0xF3]), VFNMADD132PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x9C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD132PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x9C, 0xDC]), VFNMADD132PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x9C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD132PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x9C, 0xCB]), VFNMADD132PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x9C, 0x4C, 0xC2, 0xB3]), VFNMADD132PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x9C, 0xD4]), VFNMADD132PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x9C, 0x54, 0xD9, 0xBE]), VFNMADD132PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0x9C, 0xC9]), VFNMADD132PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMADD213PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xAC, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMADD213PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xAC, 0xF3]), VFNMADD213PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xAC, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD213PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xAC, 0xDC]), VFNMADD213PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xAC, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD213PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xAC, 0xCB]), VFNMADD213PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xAC, 0x4C, 0xC2, 0xB3]), VFNMADD213PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xAC, 0xD4]), VFNMADD213PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xAC, 0x54, 0xD9, 0xBE]), VFNMADD213PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xAC, 0xC9]), VFNMADD213PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMADD231PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xBC, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMADD231PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xBC, 0xF3]), VFNMADD231PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xBC, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD231PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xBC, 0xDC]), VFNMADD231PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xBC, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD231PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xBC, 0xCB]), VFNMADD231PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xBC, 0x4C, 0xC2, 0xB3]), VFNMADD231PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xBC, 0xD4]), VFNMADD231PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xBC, 0x54, 0xD9, 0xBE]), VFNMADD231PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xBC, 0xC9]), VFNMADD231PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMADDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x78, 0xC9, 0x30]), VFNMADDPS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x78, 0x4C, 0xC2, 0xB3, 0x30]), VFNMADDPS(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x78, 0x4C, 0xC2, 0xB3, 0x90]), VFNMADDPS(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x78, 0xD2, 0x40]), VFNMADDPS(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x78, 0x54, 0xD9, 0xBE, 0x40]), VFNMADDPS(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x78, 0x54, 0xD9, 0xBE, 0xA0]), VFNMADDPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFNMSUB132PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x9E, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMSUB132PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x9E, 0xF3]), VFNMSUB132PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x9E, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB132PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x9E, 0xDC]), VFNMSUB132PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x9E, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB132PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x9E, 0xCB]), VFNMSUB132PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x9E, 0x4C, 0xC2, 0xB3]), VFNMSUB132PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x9E, 0xD4]), VFNMSUB132PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x9E, 0x54, 0xD9, 0xBE]), VFNMSUB132PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0x9E, 0xC9]), VFNMSUB132PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMSUB213PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xAE, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMSUB213PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xAE, 0xF3]), VFNMSUB213PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xAE, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB213PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xAE, 0xDC]), VFNMSUB213PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xAE, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB213PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xAE, 0xCB]), VFNMSUB213PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xAE, 0x4C, 0xC2, 0xB3]), VFNMSUB213PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xAE, 0xD4]), VFNMSUB213PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xAE, 0x54, 0xD9, 0xBE]), VFNMSUB213PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xAE, 0xC9]), VFNMSUB213PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMSUB231PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xBE, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMSUB231PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xBE, 0xF3]), VFNMSUB231PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xBE, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB231PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xBE, 0xDC]), VFNMSUB231PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xBE, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB231PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xBE, 0xCB]), VFNMSUB231PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xBE, 0x4C, 0xC2, 0xB3]), VFNMSUB231PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xBE, 0xD4]), VFNMSUB231PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xBE, 0x54, 0xD9, 0xBE]), VFNMSUB231PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xBE, 0xC9]), VFNMSUB231PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMSUBPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7C, 0xC9, 0x30]), VFNMSUBPS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7C, 0x4C, 0xC2, 0xB3, 0x30]), VFNMSUBPS(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x7C, 0x4C, 0xC2, 0xB3, 0x90]), VFNMSUBPS(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x7C, 0xD2, 0x40]), VFNMSUBPS(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x7C, 0x54, 0xD9, 0xBE, 0x40]), VFNMSUBPS(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x7C, 0x54, 0xD9, 0xBE, 0xA0]), VFNMSUBPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFMADD132PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x98, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADD132PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x98, 0xF3]), VFMADD132PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x98, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD132PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x98, 0xDC]), VFMADD132PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x98, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD132PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x98, 0xCB]), VFMADD132PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x98, 0x4C, 0xC2, 0xB3]), VFMADD132PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0x98, 0xD4]), VFMADD132PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x98, 0x54, 0xD9, 0xBE]), VFMADD132PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0x98, 0xC9]), VFMADD132PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADD213PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xA8, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADD213PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xA8, 0xF3]), VFMADD213PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xA8, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD213PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xA8, 0xDC]), VFMADD213PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xA8, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD213PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xA8, 0xCB]), VFMADD213PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xA8, 0x4C, 0xC2, 0xB3]), VFMADD213PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xA8, 0xD4]), VFMADD213PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xA8, 0x54, 0xD9, 0xBE]), VFMADD213PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xA8, 0xC9]), VFMADD213PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADD231PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xB8, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADD231PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xB8, 0xF3]), VFMADD231PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xB8, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD231PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xB8, 0xDC]), VFMADD231PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xB8, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADD231PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xB8, 0xCB]), VFMADD231PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xB8, 0x4C, 0xC2, 0xB3]), VFMADD231PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xB8, 0xD4]), VFMADD231PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xB8, 0x54, 0xD9, 0xBE]), VFMADD231PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xB8, 0xC9]), VFMADD231PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x69, 0xC9, 0x30]), VFMADDPD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x69, 0x4C, 0xC2, 0xB3, 0x30]), VFMADDPD(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x69, 0x4C, 0xC2, 0xB3, 0x90]), VFMADDPD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x69, 0xD2, 0x40]), VFMADDPD(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x69, 0x54, 0xD9, 0xBE, 0x40]), VFMADDPD(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x69, 0x54, 0xD9, 0xBE, 0xA0]), VFMADDPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFMSUB132PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x9A, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUB132PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x9A, 0xF3]), VFMSUB132PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x9A, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB132PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x9A, 0xDC]), VFMSUB132PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x9A, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB132PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x9A, 0xCB]), VFMSUB132PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x9A, 0x4C, 0xC2, 0xB3]), VFMSUB132PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0x9A, 0xD4]), VFMSUB132PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x9A, 0x54, 0xD9, 0xBE]), VFMSUB132PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0x9A, 0xC9]), VFMSUB132PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUB213PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xAA, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUB213PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xAA, 0xF3]), VFMSUB213PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xAA, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB213PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xAA, 0xDC]), VFMSUB213PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xAA, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB213PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xAA, 0xCB]), VFMSUB213PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xAA, 0x4C, 0xC2, 0xB3]), VFMSUB213PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xAA, 0xD4]), VFMSUB213PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xAA, 0x54, 0xD9, 0xBE]), VFMSUB213PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xAA, 0xC9]), VFMSUB213PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUB231PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xBA, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUB231PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xBA, 0xF3]), VFMSUB231PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xBA, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB231PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xBA, 0xDC]), VFMSUB231PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xBA, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUB231PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xBA, 0xCB]), VFMSUB231PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xBA, 0x4C, 0xC2, 0xB3]), VFMSUB231PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xBA, 0xD4]), VFMSUB231PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xBA, 0x54, 0xD9, 0xBE]), VFMSUB231PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xBA, 0xC9]), VFMSUB231PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUBPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6D, 0xC9, 0x30]), VFMSUBPD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x6D, 0x4C, 0xC2, 0xB3, 0x30]), VFMSUBPD(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x6D, 0x4C, 0xC2, 0xB3, 0x90]), VFMSUBPD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x6D, 0xD2, 0x40]), VFMSUBPD(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x6D, 0x54, 0xD9, 0xBE, 0x40]), VFMSUBPD(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x6D, 0x54, 0xD9, 0xBE, 0xA0]), VFMSUBPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFNMADD132PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x9C, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMADD132PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x9C, 0xF3]), VFNMADD132PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x9C, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD132PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x9C, 0xDC]), VFNMADD132PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x9C, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD132PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x9C, 0xCB]), VFNMADD132PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x9C, 0x4C, 0xC2, 0xB3]), VFNMADD132PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0x9C, 0xD4]), VFNMADD132PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x9C, 0x54, 0xD9, 0xBE]), VFNMADD132PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0x9C, 0xC9]), VFNMADD132PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMADD213PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xAC, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMADD213PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xAC, 0xF3]), VFNMADD213PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xAC, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD213PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xAC, 0xDC]), VFNMADD213PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xAC, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD213PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xAC, 0xCB]), VFNMADD213PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xAC, 0x4C, 0xC2, 0xB3]), VFNMADD213PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xAC, 0xD4]), VFNMADD213PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xAC, 0x54, 0xD9, 0xBE]), VFNMADD213PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xAC, 0xC9]), VFNMADD213PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMADD231PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xBC, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMADD231PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xBC, 0xF3]), VFNMADD231PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xBC, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD231PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xBC, 0xDC]), VFNMADD231PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xBC, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMADD231PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xBC, 0xCB]), VFNMADD231PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xBC, 0x4C, 0xC2, 0xB3]), VFNMADD231PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xBC, 0xD4]), VFNMADD231PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xBC, 0x54, 0xD9, 0xBE]), VFNMADD231PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xBC, 0xC9]), VFNMADD231PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMADDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x79, 0xC9, 0x30]), VFNMADDPD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x79, 0x4C, 0xC2, 0xB3, 0x30]), VFNMADDPD(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x79, 0x4C, 0xC2, 0xB3, 0x90]), VFNMADDPD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x79, 0xD2, 0x40]), VFNMADDPD(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x79, 0x54, 0xD9, 0xBE, 0x40]), VFNMADDPD(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x79, 0x54, 0xD9, 0xBE, 0xA0]), VFNMADDPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFNMSUB132PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x9E, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMSUB132PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x9E, 0xF3]), VFNMSUB132PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x9E, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB132PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x9E, 0xDC]), VFNMSUB132PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x9E, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB132PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x9E, 0xCB]), VFNMSUB132PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x9E, 0x4C, 0xC2, 0xB3]), VFNMSUB132PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0x9E, 0xD4]), VFNMSUB132PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x9E, 0x54, 0xD9, 0xBE]), VFNMSUB132PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0x9E, 0xC9]), VFNMSUB132PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMSUB213PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xAE, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMSUB213PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xAE, 0xF3]), VFNMSUB213PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xAE, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB213PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xAE, 0xDC]), VFNMSUB213PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xAE, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB213PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xAE, 0xCB]), VFNMSUB213PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xAE, 0x4C, 0xC2, 0xB3]), VFNMSUB213PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xAE, 0xD4]), VFNMSUB213PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xAE, 0x54, 0xD9, 0xBE]), VFNMSUB213PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xAE, 0xC9]), VFNMSUB213PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMSUB231PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xBE, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFNMSUB231PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xBE, 0xF3]), VFNMSUB231PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xBE, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB231PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xBE, 0xDC]), VFNMSUB231PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xBE, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFNMSUB231PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xBE, 0xCB]), VFNMSUB231PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xBE, 0x4C, 0xC2, 0xB3]), VFNMSUB231PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xBE, 0xD4]), VFNMSUB231PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xBE, 0x54, 0xD9, 0xBE]), VFNMSUB231PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xBE, 0xC9]), VFNMSUB231PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFNMSUBPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7D, 0xC9, 0x30]), VFNMSUBPD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x7D, 0x4C, 0xC2, 0xB3, 0x30]), VFNMSUBPD(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x7D, 0x4C, 0xC2, 0xB3, 0x90]), VFNMSUBPD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x7D, 0xD2, 0x40]), VFNMSUBPD(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x7D, 0x54, 0xD9, 0xBE, 0x40]), VFNMSUBPD(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x7D, 0x54, 0xD9, 0xBE, 0xA0]), VFNMSUBPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFMADDSUB132PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x96, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADDSUB132PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x96, 0xF3]), VFMADDSUB132PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x96, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB132PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x96, 0xDC]), VFMADDSUB132PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x96, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB132PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x96, 0xCB]), VFMADDSUB132PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x96, 0x4C, 0xC2, 0xB3]), VFMADDSUB132PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x96, 0xD4]), VFMADDSUB132PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x96, 0x54, 0xD9, 0xBE]), VFMADDSUB132PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0x96, 0xC9]), VFMADDSUB132PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADDSUB213PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xA6, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADDSUB213PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xA6, 0xF3]), VFMADDSUB213PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xA6, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB213PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xA6, 0xDC]), VFMADDSUB213PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xA6, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB213PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xA6, 0xCB]), VFMADDSUB213PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xA6, 0x4C, 0xC2, 0xB3]), VFMADDSUB213PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xA6, 0xD4]), VFMADDSUB213PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xA6, 0x54, 0xD9, 0xBE]), VFMADDSUB213PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xA6, 0xC9]), VFMADDSUB213PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADDSUB231PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xB6, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADDSUB231PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xB6, 0xF3]), VFMADDSUB231PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xB6, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB231PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xB6, 0xDC]), VFMADDSUB231PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xB6, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB231PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xB6, 0xCB]), VFMADDSUB231PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xB6, 0x4C, 0xC2, 0xB3]), VFMADDSUB231PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xB6, 0xD4]), VFMADDSUB231PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xB6, 0x54, 0xD9, 0xBE]), VFMADDSUB231PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xB6, 0xC9]), VFMADDSUB231PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADDSUBPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x5C, 0xC9, 0x30]), VFMADDSUBPS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x5C, 0x4C, 0xC2, 0xB3, 0x30]), VFMADDSUBPS(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x5C, 0x4C, 0xC2, 0xB3, 0x90]), VFMADDSUBPS(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x5C, 0xD2, 0x40]), VFMADDSUBPS(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x5C, 0x54, 0xD9, 0xBE, 0x40]), VFMADDSUBPS(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x5C, 0x54, 0xD9, 0xBE, 0xA0]), VFMADDSUBPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFMSUBADD132PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0x97, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUBADD132PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0x97, 0xF3]), VFMSUBADD132PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0x97, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD132PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0x97, 0xDC]), VFMSUBADD132PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0x97, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD132PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0x97, 0xCB]), VFMSUBADD132PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0x97, 0x4C, 0xC2, 0xB3]), VFMSUBADD132PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0x97, 0xD4]), VFMSUBADD132PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0x97, 0x54, 0xD9, 0xBE]), VFMSUBADD132PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0x97, 0xC9]), VFMSUBADD132PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUBADD213PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xA7, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUBADD213PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xA7, 0xF3]), VFMSUBADD213PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xA7, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD213PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xA7, 0xDC]), VFMSUBADD213PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xA7, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD213PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xA7, 0xCB]), VFMSUBADD213PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xA7, 0x4C, 0xC2, 0xB3]), VFMSUBADD213PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xA7, 0xD4]), VFMSUBADD213PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xA7, 0x54, 0xD9, 0xBE]), VFMSUBADD213PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xA7, 0xC9]), VFMSUBADD213PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUBADD231PS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0x5D, 0x8A, 0xB7, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUBADD231PS(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0x5D, 0x8A, 0xB7, 0xF3]), VFMSUBADD231PS(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0x55, 0xAD, 0xB7, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD231PS(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0x55, 0xAD, 0xB7, 0xDC]), VFMSUBADD231PS(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0xC6, 0xB7, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD231PS(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x09, 0xB7, 0xCB]), VFMSUBADD231PS(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x09, 0xB7, 0x4C, 0xC2, 0xB3]), VFMSUBADD231PS(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x05, 0xB7, 0xD4]), VFMSUBADD231PS(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x05, 0xB7, 0x54, 0xD9, 0xBE]), VFMSUBADD231PS(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0x2D, 0x96, 0xB7, 0xC9]), VFMSUBADD231PS(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUBADDPS(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x5E, 0xC9, 0x30]), VFMSUBADDPS(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x5E, 0x4C, 0xC2, 0xB3, 0x30]), VFMSUBADDPS(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x5E, 0x4C, 0xC2, 0xB3, 0x90]), VFMSUBADDPS(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x5E, 0xD2, 0x40]), VFMSUBADDPS(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x5E, 0x54, 0xD9, 0xBE, 0x40]), VFMSUBADDPS(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x5E, 0x54, 0xD9, 0xBE, 0xA0]), VFMSUBADDPS(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFMADDSUB132PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x96, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADDSUB132PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x96, 0xF3]), VFMADDSUB132PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x96, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB132PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x96, 0xDC]), VFMADDSUB132PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x96, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB132PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x96, 0xCB]), VFMADDSUB132PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x96, 0x4C, 0xC2, 0xB3]), VFMADDSUB132PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0x96, 0xD4]), VFMADDSUB132PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x96, 0x54, 0xD9, 0xBE]), VFMADDSUB132PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0x96, 0xC9]), VFMADDSUB132PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADDSUB213PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xA6, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADDSUB213PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xA6, 0xF3]), VFMADDSUB213PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xA6, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB213PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xA6, 0xDC]), VFMADDSUB213PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xA6, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB213PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xA6, 0xCB]), VFMADDSUB213PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xA6, 0x4C, 0xC2, 0xB3]), VFMADDSUB213PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xA6, 0xD4]), VFMADDSUB213PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xA6, 0x54, 0xD9, 0xBE]), VFMADDSUB213PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xA6, 0xC9]), VFMADDSUB213PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADDSUB231PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xB6, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMADDSUB231PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xB6, 0xF3]), VFMADDSUB231PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xB6, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB231PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xB6, 0xDC]), VFMADDSUB231PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xB6, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMADDSUB231PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xB6, 0xCB]), VFMADDSUB231PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xB6, 0x4C, 0xC2, 0xB3]), VFMADDSUB231PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xB6, 0xD4]), VFMADDSUB231PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xB6, 0x54, 0xD9, 0xBE]), VFMADDSUB231PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xB6, 0xC9]), VFMADDSUB231PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMADDSUBPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x5D, 0xC9, 0x30]), VFMADDSUBPD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x5D, 0x4C, 0xC2, 0xB3, 0x30]), VFMADDSUBPD(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x5D, 0x4C, 0xC2, 0xB3, 0x90]), VFMADDSUBPD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x5D, 0xD2, 0x40]), VFMADDSUBPD(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x5D, 0x54, 0xD9, 0xBE, 0x40]), VFMADDSUBPD(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x5D, 0x54, 0xD9, 0xBE, 0xA0]), VFMADDSUBPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
class TestVFMSUBADD132PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0x97, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUBADD132PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0x97, 0xF3]), VFMSUBADD132PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0x97, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD132PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0x97, 0xDC]), VFMSUBADD132PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0x97, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD132PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0x97, 0xCB]), VFMSUBADD132PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0x97, 0x4C, 0xC2, 0xB3]), VFMSUBADD132PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0x97, 0xD4]), VFMSUBADD132PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0x97, 0x54, 0xD9, 0xBE]), VFMSUBADD132PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0x97, 0xC9]), VFMSUBADD132PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUBADD213PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xA7, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUBADD213PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xA7, 0xF3]), VFMSUBADD213PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xA7, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD213PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xA7, 0xDC]), VFMSUBADD213PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xA7, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD213PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xA7, 0xCB]), VFMSUBADD213PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xA7, 0x4C, 0xC2, 0xB3]), VFMSUBADD213PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xA7, 0xD4]), VFMSUBADD213PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xA7, 0x54, 0xD9, 0xBE]), VFMSUBADD213PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xA7, 0xC9]), VFMSUBADD213PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUBADD231PD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0x62, 0x42, 0xDD, 0x8A, 0xB7, 0xB4, 0xC2, 0xB3, 0xFF, 0xFF, 0xFF]), VFMSUBADD231PD(xmm30(k2.z), xmm4, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0x62, 0x22, 0xDD, 0x8A, 0xB7, 0xF3]), VFMSUBADD231PD(xmm30(k2.z), xmm4, xmm19).encode())
self.assertEqual(bytearray([0x62, 0xC2, 0xD5, 0xAD, 0xB7, 0x9C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD231PD(ymm19(k5.z), ymm5, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0xA2, 0xD5, 0xAD, 0xB7, 0xDC]), VFMSUBADD231PD(ymm19(k5.z), ymm5, ymm20).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0xC6, 0xB7, 0x8C, 0xD9, 0xBE, 0xFF, 0xFF, 0xFF]), VFMSUBADD231PD(zmm9(k6.z), zmm26, zword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x89, 0xB7, 0xCB]), VFMSUBADD231PD(xmm1, xmm14, xmm3).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x89, 0xB7, 0x4C, 0xC2, 0xB3]), VFMSUBADD231PD(xmm1, xmm14, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xE2, 0x85, 0xB7, 0xD4]), VFMSUBADD231PD(ymm2, ymm15, ymm4).encode())
self.assertEqual(bytearray([0xC4, 0xC2, 0x85, 0xB7, 0x54, 0xD9, 0xBE]), VFMSUBADD231PD(ymm2, ymm15, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0x62, 0x52, 0xAD, 0x96, 0xB7, 0xC9]), VFMSUBADD231PD(zmm9(k6.z), zmm26, zmm9, {rn_sae}).encode())
class TestVFMSUBADDPD(unittest.TestCase):
def runTest(self):
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x5F, 0xC9, 0x30]), VFMSUBADDPD(xmm1, xmm14, xmm3, xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x89, 0x5F, 0x4C, 0xC2, 0xB3, 0x30]), VFMSUBADDPD(xmm1, xmm14, xmm3, oword[r10 + rax*8 - 77]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x09, 0x5F, 0x4C, 0xC2, 0xB3, 0x90]), VFMSUBADDPD(xmm1, xmm14, oword[r10 + rax*8 - 77], xmm9).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x5F, 0xD2, 0x40]), VFMSUBADDPD(ymm2, ymm15, ymm4, ymm10).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x85, 0x5F, 0x54, 0xD9, 0xBE, 0x40]), VFMSUBADDPD(ymm2, ymm15, ymm4, hword[r9 + rbx*8 - 66]).encode())
self.assertEqual(bytearray([0xC4, 0xC3, 0x05, 0x5F, 0x54, 0xD9, 0xBE, 0xA0]), VFMSUBADDPD(ymm2, ymm15, hword[r9 + rbx*8 - 66], ymm10).encode())
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# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from __future__ import print_function
import opcodes
import copy
import six
from opcodes.x86_64 import *
from codegen.code import CodeWriter, CodeBlock
import operator
import json
import os
instruction_set = read_instruction_set()
for instruction in instruction_set:
extra_instruction_forms = []
for instruction_form in instruction.forms:
if any(operand.type in ["{sae}", "{er}"] for operand in instruction_form.operands):
new_instruction_form = copy.deepcopy(instruction_form)
new_instruction_form.operands = \
[operand for operand in new_instruction_form.operands if operand.type not in ["{sae}", "{er}"]]
new_evex = next(component for component in new_instruction_form.encodings[0].components
if isinstance(component, EVEX))
new_evex.LL = 0b10
new_evex.b = 0
extra_instruction_forms.append(new_instruction_form)
old_evex = next(component for component in instruction_form.encodings[0].components
if isinstance(component, EVEX))
if not isinstance(old_evex.LL, Operand):
# EVEX.LL didn't encode rounding control.
# Set LL to 0.
# This is contrary to Intel spec (319433-023), but this is what binutils does. See discussion at
# https://software.intel.com/en-us/forums/intel-isa-extensions/topic/562664
old_evex.LL = 0
old_evex.b = 1
instruction.forms.extend(extra_instruction_forms)
instruction_groups = json.load(open(os.path.join(os.path.dirname(os.path.abspath(__file__)), "x86_64.json")))
def filter_instruction_forms(instruction_forms):
"""Removes the instruction forms that are currently not supported"""
new_instruction_forms = list()
for instruction_form in instruction_forms:
if all([operand.type not in {"r8l", "r16l", "r32l", "moffs32", "moffs64"} for operand in instruction_form.operands]):
new_instruction_forms.append(instruction_form)
return new_instruction_forms
def is_avx512_instruction_form(instruction_form):
"""Indicates whether the instruction form belongs to AVX512 extensions"""
return instruction_form.isa_extensions and instruction_form.isa_extensions[0].name.startswith("AVX512")
def aggregate_instruction_forms(instruction_forms):
"""Hierarhically chains instruction forms
Combines operand types that differ only by a single operand together
"""
nested_operand_types = {
("1", "imm8"),
("3", "imm8"),
("rel8", "rel32"),
("imm8", "imm16"),
("imm8", "imm32"),
("imm16", "imm32"),
("imm32", "imm64"),
("al", "r8"),
("ax", "r16"),
("eax", "r32"),
("rax", "r64")
}
def find_single_operand_difference(form, other_form):
"""Checks if two forms differ only by a single operand type and returns the operand number"""
if form == other_form:
return None
if len(form.operands) != len(other_form.operands):
return None
different_operand_numbers = \
list(filter(lambda n: form.operands[n].type != other_form.operands[n].type,
range(len(form.operands))))
if len(different_operand_numbers) == 1:
return different_operand_numbers[0]
else:
return None
from collections import OrderedDict
new_instruction_forms = OrderedDict()
for form in instruction_forms:
for other_form in instruction_forms:
n = find_single_operand_difference(form, other_form)
if n is not None and (form.operands[n].type, other_form.operands[n].type) in nested_operand_types:
break
else:
new_instruction_forms[form] = []
for form in instruction_forms:
for other_form in instruction_forms:
n = find_single_operand_difference(form, other_form)
if n is not None and (form.operands[n].type, other_form.operands[n].type) in nested_operand_types:
assert other_form.isa_extensions == form.isa_extensions
assert other_form.mmx_mode == form.mmx_mode
assert other_form.xmm_mode == form.xmm_mode
if other_form in new_instruction_forms:
new_instruction_forms[other_form].insert(0, (n, form))
break
return new_instruction_forms
def generate_operand_check(operand_index, operand,
ignore_imm_size=True, ext_imm_size=None, lambda_form=False, evex_form=False):
check_map = {
"r8": "is_r8(%s)",
"r16": "is_r16(%s)",
"r32": "is_r32(%s)",
"r64": "is_r64(%s)",
"mm": "is_mm(%s)",
"xmm": "is_xmm(%s)",
"xmm{k}": "is_xmmk(%s)",
"xmm{k}{z}": "is_xmmkz(%s)",
"ymm": "is_ymm(%s)",
"ymm{k}": "is_ymmk(%s)",
"ymm{k}{z}": "is_ymmkz(%s)",
"zmm": "is_zmm(%s)",
"zmm{k}": "is_zmmk(%s)",
"zmm{k}{z}": "is_zmmkz(%s)",
"k": "is_k(%s)",
"k{k}": "is_kk(%s)",
"m": "is_m(%s)",
"m8": "is_m8(%s)",
"m16": "is_m16(%s)",
"m16{k}{z}": "is_m16kz(%s)",
"m32": "is_m32(%s)",
"m32{k}": "is_m32k(%s)",
"m32{k}{z}": "is_m32kz(%s)",
"m64": "is_m64(%s)",
"m64{k}": "is_m64k(%s)",
"m64{k}{z}": "is_m64kz(%s)",
"m128": "is_m128(%s)",
"m128{k}{z}": "is_m128kz(%s)",
"m256": "is_m256(%s)",
"m256{k}{z}": "is_m256kz(%s)",
"m512": "is_m512(%s)",
"m512{k}{z}": "is_m512kz(%s)",
"m64/m32bcst": "is_m64_m32bcst(%s)",
"m128/m32bcst": "is_m128_m32bcst(%s)",
"m256/m32bcst": "is_m256_m32bcst(%s)",
"m512/m32bcst": "is_m512_m32bcst(%s)",
"m128/m64bcst": "is_m128_m64bcst(%s)",
"m256/m64bcst": "is_m256_m64bcst(%s)",
"m512/m64bcst": "is_m512_m64bcst(%s)",
"vm32x": "is_vmx(%s)",
"vm64x": "is_vmx(%s)",
"vm32x{k}": "is_vmxk(%s)",
"vm64x{k}": "is_vmxk(%s)",
"vm32y": "is_vmy(%s)",
"vm64y": "is_vmy(%s)",
"vm32y{k}": "is_vmyk(%s)",
"vm64y{k}": "is_vmyk(%s)",
"vm32z": "is_vmz(%s)",
"vm64z": "is_vmz(%s)",
"vm32z{k}": "is_vmzk(%s)",
"vm64z{k}": "is_vmzk(%s)",
"imm": "is_imm(%s)",
"imm4": "is_imm4(%s)",
"imm8": "is_imm8(%s)",
"imm16": "is_imm16(%s)",
"imm32": "is_imm32(%s)",
"imm64": "is_imm64(%s)",
"rel32": "is_rel32(%s)",
"rel8": "is_rel8(%s)",
"al": "is_al(%s)",
"cl": "is_cl(%s)",
"ax": "is_ax(%s)",
"eax": "is_eax(%s)",
"rax": "is_rax(%s)",
"xmm0": "is_xmm0(%s)",
"1": "%s == 1",
"3": "%s == 3",
"{er}": "is_er(%s)",
"{sae}": "is_sae(%s)"
}
evex_check_map = {
"xmm": "is_evex_xmm(%s)",
"ymm": "is_evex_ymm(%s)",
"vm32x": "is_evex_vmx(%s)",
"vm64x": "is_evex_vmx(%s)",
"vm32y": "is_evex_vmy(%s)",
"vm64y": "is_evex_vmy(%s)",
}
imm_check_map = {
"imm4": "is_imm4(%s, ext_size=%d)",
"imm8": "is_imm8(%s, ext_size=%d)",
"imm16": "is_imm16(%s, ext_size=%d)",
"imm32": "is_imm32(%s, ext_size=%d)",
}
imm_map = {
"imm4": "imm",
"imm8": "imm",
"imm16": "imm",
"imm32": "imm",
"imm64": "imm"
}
optype = operand.type
assert optype in check_map, "Unknown operand type: " + optype
operands = "op" if lambda_form else "self.operands"
if ignore_imm_size:
optype = imm_map.get(optype, optype)
if ext_imm_size is not None and optype in imm_check_map:
return imm_check_map[optype] % (operands + "[" + str(operand_index) + "]", ext_imm_size)
elif evex_form and optype in evex_check_map:
return evex_check_map[optype] % (operands + "[" + str(operand_index) + "]")
else:
return check_map[optype] % (operands + "[" + str(operand_index) + "]")
def generate_isa_extensions(extensions):
assert len(extensions) == 1
extension_map = {
"MMX+": "MMXPlus"
}
extension = extensions[0]
return "Extension.%s" % extension_map.get(extension, extension)
class Flags:
AccumulatorOp0 = 0x01
AccumulatorOp1 = 0x02
Rel8Label = 0x04
Rel32Label = 0x08
ModRMSIBDisp = 0x10
OptionalREX = 0x20
VEX2 = 0x40
EVEX = 0x80
def generate_encoding_lambda(encoding, operands, use_off_argument=False):
byte_sequence = []
parts = []
flags = 0
disp8xN = None
def generate_bytes(byte_sequence):
if byte_sequence:
parts.append("bytearray([%s])" % ", ".join(byte_sequence))
return []
for component in encoding.components:
if isinstance(component, Prefix):
prefix = "0x%02X" % component.byte
byte_sequence.append(prefix)
elif isinstance(component, REX):
component.set_ignored()
if component.is_mandatory:
if isinstance(component.X, Operand):
assert component.X == component.B and component.X.is_memory, \
"REX.X must refers to the same memory operand as REX.B. " \
"Register operands must have constant REX.X"
byte_sequence = generate_bytes(byte_sequence)
rex_args = [str(component.W)]
if isinstance(component.R, Operand):
rex_args.append("op[%d].hcode" % operands.index(component.R))
else:
rex_args.append(str(component.R))
rex_args.append("op[%d].address" % operands.index(component.X))
rex = "rex(%s)" % ", ".join(rex_args)
parts.append(rex)
else:
assert not isinstance(component.B, Operand) or component.B.is_register, \
"Memory operands must have non-constant REX.B"
assert component.X in {0, 1}
rex_byte = 0x40 | (component.W << 3)
rex_parts = []
if isinstance(component.R, Operand):
rex_parts.append("op[%d].hcode << 2" % operands.index(component.R))
else:
rex_byte |= component.R << 2
if isinstance(component.B, Operand):
rex_parts.append("op[%d].hcode" % operands.index(component.B))
else:
rex_byte |= component.B
rex_byte |= component.X << 1
rex = " | ".join(["0x%02X" % rex_byte] + rex_parts)
byte_sequence.append(rex)
else:
assert component.W == 0, "Instructions with REX.W == 1 must mandate REX prefix"
byte_sequence = generate_bytes(byte_sequence)
rex_args = []
if isinstance(component.R, Operand):
rex_args.append("op[%d].hcode" % operands.index(component.R))
else:
rex_args.append(str(component.R))
if isinstance(component.X, Operand):
assert component.X == component.B and component.X.is_memory, \
"REX.X must refers to the same memory operand as REX.B. " \
"Register operands must have constant REX.X"
rex_args.append("op[%d].address" % operands.index(component.X))
else:
assert not isinstance(component.B, Operand) or component.B.is_register, \
"Memory operands must have non-constant REX.B"
rex_args.append("op[%d]" % operands.index(component.B))
r8_operands = [i for (i, op) in enumerate(operands) if op.type == "r8"]
force_rex_conditions = ["rex"]
for r8_operand in r8_operands:
force_rex_conditions.append("is_r8rex(op[%d])" % r8_operand)
rex_args.append(" or ".join(force_rex_conditions))
rex = "optional_rex(%s)" % ", ".join(rex_args)
flags |= Flags.OptionalREX
parts.append(rex)
elif isinstance(component, VEX):
component.set_ignored()
if component.type == "VEX" and component.mmmmm == 0b00001 and component.W == 0:
if component.R == 1 and component.X == 1 and component.B == 1:
# VZEROUPPER and VZEROALL instructions are VEX-encoded and have no arguments
byte_sequence.append("0xC5")
byte_sequence.append("0x%02X" % (0xF8 | component.L << 2 | component.pp))
else:
byte_sequence = generate_bytes(byte_sequence)
vex_args = [str(component.L << 2 | component.pp)]
if isinstance(component.R, Operand):
vex_args.append("op[%d].hcode" % operands.index(component.R))
else:
assert component.R == 0
vex_args.append("0")
if isinstance(component.X, Operand):
assert component.X == component.B and component.X.is_memory, \
"VEX.X must refers to the same memory operand as VEX.B. " \
"Register operands must have constant VEX.X"
vex_args.append("op[%d].address" % operands.index(component.X))
else:
assert not isinstance(component.B, Operand) or component.B.is_register, \
"Memory operands must have non-constant VEX.B"
if isinstance(component.B, Operand):
vex_args.append("op[%d]" % operands.index(component.B))
else:
assert component.B == 0
vex_args.append("None")
if isinstance(component.vvvv, Operand):
vex_args.append("op[%d].hlcode" % operands.index(component.vvvv))
else:
assert component.vvvv == 0b0000
vex_args.append("0")
vex_args.append("vex3")
vex = "vex2(%s)" % ", ".join(vex_args)
flags |= Flags.VEX2
parts.append(vex)
else:
if isinstance(component.X, Operand):
assert component.X == component.B and component.X.is_memory, \
"VEX.X must refers to the same memory operand as VEX.B. " \
"Register operands must have constant VEX.X"
byte_sequence = generate_bytes(byte_sequence)
vex_args = [{"VEX": "0xC4", "XOP": "0x8F"}[component.type],
bin(component.mmmmm),
"0x%02X" % (component.W << 7 | component.L << 2 | component.pp)]
if isinstance(component.R, Operand):
vex_args.append("op[%d].hcode" % operands.index(component.R))
else:
assert component.R == 0
vex_args.append("0")
vex_args.append("op[%d].address" % operands.index(component.X))
if isinstance(component.vvvv, Operand):
vex_args.append("op[%d].hlcode" % operands.index(component.vvvv))
else:
assert component.vvvv == 0b0000
vex = "vex3(%s)" % ", ".join(vex_args)
parts.append(vex)
else:
assert isinstance(component.B, Operand) and component.B.is_register or component.B == 0, \
"Memory operands must have non-constant VEX.B"
byte_sequence.append({"VEX": "0xC4", "XOP": "0x8F"}[component.type])
vex_byte1 = "0x%02X" % (0xE0 | component.mmmmm)
if isinstance(component.R, Operand):
vex_byte1 += " ^ (op[%d].hcode << 7)" % operands.index(component.R)
else:
assert component.R == 0
if isinstance(component.B, Operand):
vex_byte1 += " ^ (op[%d].hcode << 5)" % operands.index(component.B)
else:
assert component.B == 0
byte_sequence.append(vex_byte1)
if isinstance(component.vvvv, Operand):
byte_sequence.append("0x%02X ^ (op[%d].hlcode << 3)" %
(0x78 | (component.W << 7) | (component.L << 2) | component.pp,
operands.index(component.vvvv)))
else:
assert component.vvvv == 0b0000
byte_sequence.append("0x%02X" % (0x78 | (component.W << 7) | (component.L << 2) | component.pp))
elif isinstance(component, EVEX):
disp8xN = component.disp8xN
component.set_ignored()
if component.X.is_memory:
assert component.X is component.B
evex_args = ["0b" + format(component.mm, "02b"), "0x%02X" % (component.W << 7 | component.pp | 0b100)]
if isinstance(component.LL, Operand):
evex_args.append("op[%d].code" % operands.index(component.LL))
else:
evex_args.append("0b" + format(component.LL, "02b"))
if isinstance(component.RR, Operand):
evex_args.append("op[%d].ehcode" % operands.index(component.RR))
else:
evex_args.append(str(component.RR))
evex_args.append("op[%d].address" % operands.index(component.X))
if component.vvvv != 0:
assert component.vvvv is component.V
# Component.V | Compnent.vvvv encode the operand
evex_args.append("op[%d].code" % operands.index(component.vvvv))
else:
assert component.V == 0 or isinstance(component.V, Operand) and component.V.is_memory
if component.aaa != 0:
evex_args.append("aaa=op[%d].kcode" % operands.index(component.aaa))
if component.z != 0:
evex_args.append("z=op[%d].zcode" % operands.index(component.z))
if isinstance(component.b, Operand):
evex_args.append("b=op[%d].bcode" % operands.index(component.b))
elif component.b != 0:
evex_args.append("b=" + str(component.b))
evex = "evex(%s)" % ", ".join(evex_args)
flags |= Flags.EVEX
parts.append(evex)
else:
byte_sequence.append("0x62")
if isinstance(component.RR, Operand):
byte_sequence.append("((op[%d].hcode << 7) | (op[%d].ehcode << 5) | (op[%d].ecode << 4)) ^ %d" %
(operands.index(component.RR), operands.index(component.B),
operands.index(component.RR), 0xF0 | component.mm))
else:
r = component.RR & 1
r_ = (component.RR >> 1) & 1
byte = (component.mm | (r << 7) | (r_ << 4)) ^ 0xF0
if byte == 0:
byte_sequence.append("op[%d].ehcode << 5" % operands.index(component.B))
else:
byte_sequence.append("(op[%d].ehcode << 5) ^ 0x%02X" % (operands.index(component.B), byte))
if isinstance(component.vvvv, Operand):
byte_sequence.append("0x%02X ^ (op[%d].hlcode << 3)" %
(component.W << 7 | component.pp | 0b01111100, operands.index(component.vvvv)))
else:
assert component.vvvv == 0
byte_sequence.append("0x%02X" % (component.W << 7 | component.pp | 0b01111100))
byte = component.b << 4
byte_parts = []
if isinstance(component.z, Operand):
byte_parts.append("(op[%d].zcode << 7)" % operands.index(component.z))
else:
byte |= component.z << 7
if isinstance(component.LL, Operand):
byte_parts.append("(op[%d].code << 5)" % operands.index(component.LL))
else:
byte |= component.LL << 5
if isinstance(component.V, Operand):
byte_parts.append("(op[%d].ecode << 3 ^ 0x8)" % operands.index(component.V))
else:
byte |= (component.V ^ 1) << 3
if isinstance(component.aaa, Operand):
byte_parts.append("op[%d].kcode" % operands.index(component.aaa))
else:
assert component.aaa == 0
byte_parts.append("0x%02X" % byte)
byte_sequence.append(" | ".join(byte_parts))
elif isinstance(component, Opcode):
opcode = "0x%02X" % component.byte
if component.addend:
opcode += " | op[%d].lcode" % operands.index(component.addend)
byte_sequence.append(opcode)
elif isinstance(component, ModRM):
if isinstance(component.mode, Operand):
assert component.mode == component.rm and component.rm.is_memory, \
"Mod R/M:mode must refer to the same memory operand as Mod R/M:rm. " \
"Register operands must have Mod R/M:mode == 0b11"
byte_sequence = generate_bytes(byte_sequence)
if isinstance(component.reg, Operand):
modrm_reg = "op[%d].lcode" % operands.index(component.reg)
else:
modrm_reg = str(component.reg)
modrm_rm = "op[%d].address" % operands.index(component.rm)
if disp8xN is None:
modrm = "modrm_sib_disp(%s, %s, sib, min_disp)" % (modrm_reg, modrm_rm)
else:
modrm = "modrm_sib_disp(%s, %s, sib, min_disp, disp8xN=%d)" % (modrm_reg, modrm_rm, disp8xN)
flags |= Flags.ModRMSIBDisp
parts.append(modrm)
else:
assert component.mode == 0b11 and component.rm.is_register, \
"Register operands must have Mod R/M:mode == 0b11. " \
"For memory operands Mod R/M:mode must refer to an operand object"
modrm_byte = component.mode << 6
modrm_parts = []
if isinstance(component.reg, Operand):
modrm_parts.append("op[%d].lcode << 3" % operands.index(component.reg))
elif component.reg:
modrm_byte |= component.reg << 3
modrm_parts.append("op[%d].lcode" % operands.index(component.rm))
modrm = " | ".join(["0x%02X" % modrm_byte] + modrm_parts)
byte_sequence.append(modrm)
elif isinstance(component, Immediate):
assert component.size in {1, 2, 4, 8}
if component.size == 1:
if isinstance(component.value, Operand):
ib = "op[%d] & 0xFF" % operands.index(component.value)
else:
ib = "0x%02X" % component.value
byte_sequence.append(ib)
elif component.size == 2:
assert isinstance(component.value, Operand)
iw = ["op[%d] & 0xFF" % operands.index(component.value),
"(op[%d] >> 8) & 0xFF" % operands.index(component.value)]
byte_sequence.extend(iw)
elif component.size == 4:
assert isinstance(component.value, Operand)
id = ["op[%d] & 0xFF" % operands.index(component.value),
"(op[%d] >> 8) & 0xFF" % operands.index(component.value),
"(op[%d] >> 16) & 0xFF" % operands.index(component.value),
"(op[%d] >> 24) & 0xFF" % operands.index(component.value)]
byte_sequence.extend(id)
elif component.size == 8:
assert isinstance(component.value, Operand)
iq = ["op[%d] & 0xFF" % operands.index(component.value),
"(op[%d] >> 8) & 0xFF" % operands.index(component.value),
"(op[%d] >> 16) & 0xFF" % operands.index(component.value),
"(op[%d] >> 24) & 0xFF" % operands.index(component.value),
"(op[%d] >> 32) & 0xFF" % operands.index(component.value),
"(op[%d] >> 40) & 0xFF" % operands.index(component.value),
"(op[%d] >> 48) & 0xFF" % operands.index(component.value),
"(op[%d] >> 56) & 0xFF" % operands.index(component.value)]
byte_sequence.extend(iq)
elif isinstance(component, RegisterByte):
ibr = "op[%d].hlcode << 4" % operands.index(component.register)
if component.payload is not None:
assert isinstance(component.payload, Operand)
ibr += " | op[%d] & 0xF" % operands.index(component.payload)
byte_sequence.append(ibr)
elif isinstance(component, CodeOffset):
assert component.size in {1, 4}
if component.size == 1:
if use_off_argument:
byte_sequence.append("off & 0xFF")
else:
byte_sequence.append("op[%d].offset & 0xFF" % operands.index(component.value))
elif component.size == 4:
if use_off_argument:
byte_sequence.extend([
"off & 0xFF", "(off >> 8) & 0xFF", "(off >> 16) & 0xFF", "(off >> 24) & 0xFF"
])
else:
byte_sequence.extend([
"op[%d].offset & 0xFF" % operands.index(component.value),
"(op[%d].offset >> 8) & 0xFF" % operands.index(component.value),
"(op[%d].offset >> 16) & 0xFF" % operands.index(component.value),
"(op[%d].offset >> 24) & 0xFF" % operands.index(component.value)
])
else:
print("UNKNOWN: " + component.__class__.__name__)
return ""
generate_bytes(byte_sequence)
if use_off_argument:
return flags, "lambda off: " + " + ".join(parts)
else:
lambda_args = ["op"]
if flags & Flags.OptionalREX:
lambda_args.append("rex=False")
if flags & Flags.VEX2:
lambda_args.append("vex3=False")
if flags & Flags.ModRMSIBDisp:
lambda_args.append("sib=False")
lambda_args.append("min_disp=0")
return flags, "lambda %s: %s" % (", ".join(lambda_args), " + ".join(parts))
def get_in_regs(instruction_form):
"""Returns a list indicating which operands might contain input registers for this instruction form"""
return tuple([bool(o.is_input and o.is_variable or o.is_output and o.is_memory) for o in instruction_form.operands])
def get_out_regs(instruction_form):
"""Returns a list indicating which operands might contain output registers for this instruction form"""
return tuple([bool(o.is_output and o.is_register) for o in instruction_form.operands])
def get_out_operands(instruction_form):
"""Returns a list indicating which operands are written by this instruction form"""
return tuple(map(operator.attrgetter("is_output"), instruction_form.operands))
def get_isa_extensions(instruction_form):
"""Returns a hashable immutable set with names of ISA extensions required for this instructions form"""
return frozenset(map(operator.attrgetter("name"), instruction_form.isa_extensions))
def go_name_init(code, instruction_form):
"""Generates initialization code for go_name property"""
if instruction_form.go_name:
code.line("self.go_name = \"%s\"" % instruction_form.go_name)
def gas_name_init(code, instruction_form):
"""Generates initialization code for gas_name property"""
if instruction_form.gas_name != instruction_form.name.lower():
code.line("self._gas_name = \"%s\"" % instruction_form.gas_name)
def implicit_regs_init(code, instruction_form):
"""Generates initialization code for _implicit_in_regs and _implicit_out_regs properties"""
name_reg_map = {
"al": (0, 0x1),
"ax": (0, 0x3),
"eax": (0, 0x7),
"rax": (0, 0xF),
"cl": (1, 0x1),
"ecx": (1, 0x7),
"rcx": (1, 0xF),
"dx": (2, 0x3),
"edx": (2, 0x7),
"rdx": (2, 0xF),
"ebx": (3, 0x7),
"rbx": (3, 0xF),
"rsi": (6, 0xF),
"rdi": (7, 0xF),
"r11": (11, 0xF),
"xmm0": (0, 0x100)}
implicit_in_regs = dict()
for in_reg_name in instruction_form.implicit_inputs:
(in_reg_id, in_reg_mask) = name_reg_map[in_reg_name]
implicit_in_regs[in_reg_id] = \
implicit_in_regs.get(in_reg_id, 0) | in_reg_mask
implicit_out_regs = dict()
for out_reg_name in instruction_form.implicit_outputs:
(out_reg_id, out_reg_mask) = name_reg_map[out_reg_name]
implicit_out_regs[out_reg_id] = \
implicit_out_regs.get(out_reg_id, 0) | out_reg_mask
if implicit_in_regs:
code.line("self._implicit_in_regs = " + str(dict(sorted(implicit_in_regs.items()))))
if implicit_out_regs:
code.line("self._implicit_out_regs = " + str(dict(sorted(implicit_out_regs.items()))))
def in_regs_init(code, instruction_form):
"""Generates initialization code for in_regs tuple"""
# Record which operands may contain input registers
if instruction_form.operands:
in_regs = get_in_regs(instruction_form)
code.line("self.in_regs = " + str(in_regs))
def out_regs_init(code, instruction_form):
"""Generates initialization code for out_regs tuple"""
# Record which operands may contain output registers
if instruction_form.operands:
out_regs = get_out_regs(instruction_form)
code.line("self.out_regs = " + str(out_regs))
def out_operands_init(code, instruction_form):
"""Generates initialization code for out_operands tuple"""
if instruction_form.operands:
out_operands = get_out_operands(instruction_form)
code.line("self.out_operands = " + str(out_operands))
def mmx_mode_init(code, instruction_form):
"""Generates initialization code for mmx_mode attribute"""
if instruction_form.mmx_mode:
mmx_mode_map = {"MMX": True, "FPU": False}
code.line("self.mmx_mode = " + str(mmx_mode_map[instruction_form.mmx_mode]))
def xmm_mode_init(code, instruction_form):
"""Generates initialization code for avx_mode attribute"""
if instruction_form.xmm_mode:
avx_mode_map = {"SSE": False, "AVX": True}
code.line("self.avx_mode = " + str(avx_mode_map[instruction_form.xmm_mode]))
def isa_extensions_init(code, instruction_form):
"""Generates initialization code for isa_extensions attribute"""
if instruction_form.isa_extensions:
isa_extensions_map = {
"MMX+": "mmx_plus",
"3dnow!": "three_d_now",
"3dnow!+": "three_d_now_plus",
"3dnow! Prefetch": "three_d_now_prefetch",
"SSE4.1": "sse4_1",
"SSE4.2": "sse4_2"
}
isa_extensions = ["peachpy.x86_64.isa." + isa_extensions_map.get(extension.name, extension.name.lower())
for extension in instruction_form.isa_extensions]
code.line("self.isa_extensions = frozenset([%s])" %
", ".join(isa_extensions))
def instruction_branch_label_form_init(code, instruction_form, instruction_subforms,
write_gas_name=True, write_in_regs=True):
"""Generates initialization code for a label operand form of a branch instruction"""
if write_gas_name:
gas_name_init(code, instruction_form)
for form in ([instruction_form] + list(map(operator.itemgetter(1), instruction_subforms))):
encoding_lambdas = list(map(lambda e: generate_encoding_lambda(e, form.operands, use_off_argument=True),
form.encodings))
assert len(encoding_lambdas) == 1, \
"Branch label instructions are expected to have only one encoding for each operand type"
flags, encoding_lambda = encoding_lambdas[0]
assert form.operands[0].type in {"rel8", "rel32"}, \
"Branch label operand type expected to be rel8 or rel32"
flags |= {"rel8": Flags.Rel8Label, "rel32": Flags.Rel32Label}[form.operands[0].type]
code.line("self.encodings.append((0x%02X, %s))" % (flags, encoding_lambda))
implicit_regs_init(code, instruction_form)
if write_in_regs:
in_regs_init(code, instruction_form)
def instruction_form_init(code, instruction_form, instruction_subforms,
write_go_name=True, write_gas_name=True,
write_in_regs=True, write_out_regs=True, write_out_operands=True,
write_mmx_mode=True, write_xmm_mode=True,
write_isa_extensions=True):
"""Generates initialization code for a particular instruction form"""
immediate_operands = [(i, op) for (i, op) in enumerate(instruction_form.operands) if op.is_immediate]
for (i, operand) in immediate_operands:
code.line("if not %s:" % generate_operand_check(i, operand,
ignore_imm_size=False, ext_imm_size=operand.extended_size))
code.indent_line("raise ValueError(\"Argument #%d can not be encoded as %s\")" % (i, operand.type))
if write_go_name:
go_name_init(code, instruction_form)
if write_gas_name:
gas_name_init(code, instruction_form)
for (operand_number, instruction_subform) in instruction_subforms:
operand_check = generate_operand_check(operand_number, instruction_subform.operands[operand_number],
ignore_imm_size=False,
ext_imm_size=instruction_subform.operands[operand_number].extended_size)
code.line("if %s:" % operand_check)
with CodeBlock():
# Record lambda functions that encode the instruction subform
encoding_lambdas = map(lambda e: generate_encoding_lambda(e, instruction_subform.operands),
instruction_subform.encodings)
flags = 0
if instruction_subform.operands[operand_number].is_variable:
assert instruction_subform.operands[operand_number].type in {"al", "ax", "eax", "rax"}, \
"Expect a special accumulator form, got: " + str(instruction_subform.operands[operand_number])
assert operand_number in {0, 1}, \
"Expect that the accumulator is either the first or the second operand"
flags |= {0: Flags.AccumulatorOp0, 1: Flags.AccumulatorOp1}[operand_number]
for encoding_flags, encoding_lambda in encoding_lambdas:
code.line("self.encodings.append((0x%02X, %s))" % (flags | encoding_flags, encoding_lambda))
# Record lambda functions that encode the most generic instruction form
encodings = map(lambda e: generate_encoding_lambda(e, instruction_form.operands), instruction_form.encodings)
for (flags, encoding_lambda) in encodings:
code.line("self.encodings.append((0x%02X, %s))" % (flags, encoding_lambda))
implicit_regs_init(code, instruction_form)
if write_in_regs:
in_regs_init(code, instruction_form)
if write_out_regs:
out_regs_init(code, instruction_form)
if write_out_operands:
out_operands_init(code, instruction_form)
if write_mmx_mode:
mmx_mode_init(code, instruction_form)
if write_xmm_mode:
xmm_mode_init(code, instruction_form)
if write_isa_extensions:
isa_extensions_init(code, instruction_form)
if instruction_form.cancelling_inputs:
code.line("self._cancelling_inputs = " + str(instruction_form.cancelling_inputs))
def reduce_operand_types(operand_types_list):
"""Combines operand types that differ only by a single operand together"""
nested_operand_types = {
("1", "imm8"),
("3", "imm8"),
("imm8", "imm16"),
("imm8", "imm32"),
("imm16", "imm32"),
("imm32", "imm64"),
("al", "r8"),
("ax", "r16"),
("eax", "r32"),
("rax", "r64")
}
# Remove operands combination which differ only by one operand and there
# is a more general instruction form for this operand, e.g.
# ADD eax, imm32 + ADD r32, imm32 -> ADD r32, imm32
new_operand_types_list = []
for (i, operand_types) in enumerate(operand_types_list):
for (j, other_operand_types) in enumerate(operand_types_list):
if j == i:
continue
if len(operand_types) != len(other_operand_types):
continue
different_operand_numbers = \
list(filter(lambda n: operand_types[n] != other_operand_types[n],
range(len(operand_types))))
if len(different_operand_numbers) == 1:
operand_number = different_operand_numbers[0]
if (operand_types[operand_number], other_operand_types[operand_number]) in nested_operand_types:
break
else:
new_operand_types_list.append(operand_types)
operand_types_list = new_operand_types_list
mergeble_operand_types = {
("r8", "m8"),
("r16", "m16"),
("r32", "m32"),
("r64", "m64"),
("mm", "m32"),
("mm", "m64"),
("xmm", "m8"),
("xmm", "m16"),
("xmm", "m32"),
("xmm", "m64"),
("xmm", "m128"),
("ymm", "m8"),
("ymm", "m16"),
("ymm", "m32"),
("ymm", "m64"),
("ymm", "m128"),
("ymm", "m256"),
("zmm", "m512")
}
# Indicator of whether this argument list was merged into another argument list
is_merged = [False] * len(operand_types_list)
new_operand_types_list = []
for (i, operand_types) in enumerate(operand_types_list):
for (j, other_operand_types) in enumerate(operand_types_list):
if j == i:
continue
if len(operand_types) != len(other_operand_types):
continue
different_operand_numbers = \
list(filter(lambda n: operand_types[n] != other_operand_types[n],
range(len(operand_types))))
if len(different_operand_numbers) == 1:
operand_number = different_operand_numbers[0]
if (other_operand_types[operand_number], operand_types[operand_number]) in mergeble_operand_types:
is_merged[j] = True
new_operand_types = list(operand_types)
new_operand_types[operand_number] = \
other_operand_types[operand_number] + "/" + operand_types[operand_number]
new_operand_types_list.append(tuple(new_operand_types))
break
else:
new_operand_types_list.append(operand_types)
return [operand_types for (operand_types, remove) in zip(new_operand_types_list, is_merged) if not remove]
def score_isa_extensions(isa_extensions):
if isa_extensions:
return max(map(operator.attrgetter("score"), isa_extensions))
return 0
def supported_forms_comment(code, instruction_forms):
"""Generates document comment that describes supported instruction forms"""
code.line()
def format_form_descriptions(name, operand_types_list):
form_descriptions = []
for operand_types in operand_types_list:
if operand_types:
form_descriptions.append(name + "(" + ", ".join(operand_types) + ")")
else:
form_descriptions.append(name + "()")
return form_descriptions
def get_operand_types_list(instruction_forms):
operand_types_list = [list(map(operator.attrgetter("type"), instruction_form.operands))
for instruction_form in instruction_forms]
return reduce_operand_types(operand_types_list)
def get_isa_extensions(instruction_forms):
isa_extensions = map(operator.attrgetter("isa_extensions"), instruction_forms)
isa_extensions = map(lambda ext: sorted(ext, key=operator.attrgetter("score")), isa_extensions)
return isa_extensions
form_descriptions = format_form_descriptions(instruction_forms[0].name, get_operand_types_list(instruction_forms))
padding_length = max(map(len, form_descriptions))
form_isa_extensions_options = sorted(set(map(tuple, get_isa_extensions(instruction_forms))),
key=lambda isa_tuple: score_isa_extensions(isa_tuple))
lines = []
for isa_extensions_option in form_isa_extensions_options:
isa_description = ""
if isa_extensions_option:
isa_description = "[" + " and ".join(map(str, isa_extensions_option)) + "]"
isa_forms = list(filter(lambda form: tuple(sorted(form.isa_extensions, key=operator.attrgetter("score"))) == isa_extensions_option, instruction_forms))
for form_description in format_form_descriptions(instruction_forms[0].name, get_operand_types_list(isa_forms)):
if isa_description:
padding = " " * (4 + padding_length - len(form_description))
lines.append("* " + form_description + padding + isa_description)
else:
lines.append("* " + form_description)
for x in sorted(lines):
code.line(x)
def is_label_branch(instruction_form):
return len(instruction_form.operands) == 1 and instruction_form.operands[0].type in {"rel8", "rel32"}
def main(package_root="."):
for group, instruction_names in six.iteritems(instruction_groups):
with open(os.path.join(package_root, "peachpy", "x86_64", group + ".py"), "w") as out:
with CodeWriter() as code:
code.line("# This file is auto-generated by /codegen/x86_64.py")
code.line("# Instruction data is based on package opcodes %s" % opcodes.__version__)
code.line()
code.line("import inspect")
code.line()
code.line("import peachpy.stream")
code.line("import peachpy.x86_64.options")
code.line("import peachpy.x86_64.isa")
code.line("from peachpy.util import is_sint8, is_sint32")
code.line("from peachpy.x86_64.encoding import rex, optional_rex, vex2, vex3, evex, modrm_sib_disp")
code.line("from peachpy.x86_64.instructions import Instruction, BranchInstruction")
code.line("from peachpy.x86_64.operand import is_al, is_ax, is_eax, is_rax, is_cl, is_xmm0, is_r8, is_r8rex, is_r16, is_r32, is_r64, \\")
code.indent_line("is_mm, is_xmm, is_ymm, is_m, is_m8, is_m16, is_m32, is_m64, is_m80, is_m128, is_m256, is_m512, \\")
code.indent_line("is_evex_xmm, is_xmmk, is_xmmkz, is_evex_ymm, is_ymmk, is_ymmkz, is_zmm, is_zmmk, is_zmmkz, is_k, is_kk, \\")
code.indent_line("is_m32k, is_m64k, is_m16kz, is_m32kz, is_m64kz, is_m128kz, is_m256kz, is_m512kz, \\")
code.indent_line("is_m64_m32bcst, is_m128_m32bcst, is_m256_m32bcst, is_m512_m32bcst, \\")
code.indent_line("is_m128_m64bcst, is_m256_m64bcst, is_m512_m64bcst, \\")
code.indent_line("is_vmx, is_vmy, is_evex_vmx, is_evex_vmy, is_vmz, is_vmxk, is_vmyk, is_vmzk, \\")
code.indent_line("is_imm, is_imm4, is_imm8, is_imm16, is_imm32, is_imm64, \\")
code.indent_line("is_rel8, is_rel32, is_label, is_er, is_sae, check_operand, format_operand_type")
code.line()
code.line()
for name in instruction_names:
# Instructions with `name` name
name_instructions = list(filter(lambda i: i.name == name, instruction_set))
if not name_instructions:
print("No forms for instruction: " + name)
continue
assert len(name_instructions) == 1
name_instruction = name_instructions[0]
instruction_forms = filter_instruction_forms(name_instruction.forms)
if not instruction_forms:
print("No forms for instruction: " + name)
continue
instruction_forms = aggregate_instruction_forms(instruction_forms)
base_class = "Instruction"
if name in {
"JA", "JNA",
"JAE", "JNAE",
"JB", "JNB",
"JBE", "JNBE",
"JC", "JNC",
"JE", "JNE",
"JG", "JNG",
"JGE", "JNGE",
"JL", "JNL",
"JLE", "JNLE",
"JO", "JNO",
"JP", "JNP",
"JS", "JNS",
"JZ", "JNZ",
"JPE", "JPO",
"JECXZ", "JRCXZ",
"JMP"
}:
base_class = "BranchInstruction"
code.line("class %s(%s):" % (name, base_class))
# Class scope
with CodeBlock():
# Generate documentation comment for the class
code.line("\"\"\"%s\"\"\"" % name_instruction.summary)
code.line()
# Generate constructor
code.line("def __init__(self, *args, **kwargs):")
with CodeBlock():
code.line("\"\"\"Supported forms:")
with CodeBlock():
supported_forms_comment(code, list(six.iterkeys(instruction_forms)))
code.line("\"\"\"")
code.line()
code.line("origin = kwargs.get(\"origin\")")
code.line("prototype = kwargs.get(\"prototype\")")
code.line("if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:")
code.indent_line("origin = inspect.stack()")
code.line("super(%s, self).__init__(\"%s\", origin=origin, prototype=prototype)" % (name, name))
code.line("self.operands = tuple(map(check_operand, args))")
operand_count_options = sorted(set([len(instruction_form.operands)
for instruction_form in six.iterkeys(instruction_forms)]))
if len(operand_count_options) == 1:
code.line("if len(self.operands) != %d:" % operand_count_options[0])
code.indent_line("raise SyntaxError(\"Instruction \\\"%s\\\" requires %d operands\")" % (name, operand_count_options[0]))
consider_operand_count = len(operand_count_options) > 1
for index, count in enumerate(operand_count_options):
if consider_operand_count:
code.line("%s len(self.operands) == %d:" % ("if" if index == 0 else "elif", count))
with CodeBlock(consider_operand_count):
# Consider only instruction forms that have exactly `count` operands
count_operand_form_trees = list(filter(lambda form_subforms:
len(form_subforms[0].operands) == count,
six.iteritems(instruction_forms)))
# Make sure operand forms with simpler ISA are checked first.
# This is needed because AVX instructions can be encoded as AVX-512 instructions.
# Thus, we should first check if operands match AVX specification, and only if that
# fails try to match AVX-512 specification
count_operand_form_trees = sorted(count_operand_form_trees,
key=lambda form_subforms: score_isa_extensions(form_subforms[0].isa_extensions))
# The most generic instruction forms
count_operand_forms = list(map(operator.itemgetter(0), count_operand_form_trees))
combine_attrs = len(count_operand_forms) > 1 or is_label_branch(count_operand_forms[0])
# Check how many in_regs combinations exist
in_regs_options = set(map(get_in_regs, count_operand_forms))
common_in_regs = combine_attrs and len(in_regs_options) == 1
# Check how many out_regs combinations exist
out_regs_options = set(map(get_out_regs, count_operand_forms))
common_out_regs = combine_attrs and len(out_regs_options) == 1
# Check how many out_operands combinations exist
out_operands_options = set(map(get_out_operands, count_operand_forms))
common_out_operands = combine_attrs and len(out_operands_options) == 1
# Check how many gas names exist
gas_names = set(map(lambda form: form.gas_name, count_operand_forms))
common_gas_name = combine_attrs and len(gas_names) == 1
# Check how many go names exist
go_names = set(map(lambda form: str(form.go_name), count_operand_forms))
common_go_name = combine_attrs and len(go_names) == 1
# Check how many mmx modes exist
mmx_modes = set(map(operator.attrgetter("mmx_mode"), count_operand_forms))
common_mmx_mode = combine_attrs and len(mmx_modes) == 1
# Check how many xmm modes exist
xmm_modes = set(map(operator.attrgetter("xmm_mode"), count_operand_forms))
common_xmm_mode = combine_attrs and len(xmm_modes) == 1
# Check how many ISA extension options exist
isa_extensions_options = set(map(get_isa_extensions, count_operand_forms))
common_isa_extensions = combine_attrs and len(isa_extensions_options) == 1
if common_go_name:
# Initialize go_name only once for all forms with `count` operands
go_name_init(code, count_operand_forms[0])
if common_gas_name:
# Initialize gas_name only once for all forms with `count` operands
gas_name_init(code, count_operand_forms[0])
if common_in_regs:
# Initialize in_regs only once for all registers with count operands
in_regs_init(code, count_operand_forms[0])
if common_out_regs:
# Initialize out_regs only once for all registers with count operands
out_regs_init(code, count_operand_forms[0])
if common_out_operands:
# Initialize out_operands only once for all registers with count operands
out_operands_init(code, count_operand_forms[0])
if common_mmx_mode:
# Initialize mmx_mode only once for all registers with count operands
mmx_mode_init(code, count_operand_forms[0])
if common_xmm_mode:
# Initialize avx_mode only once for all registers with count operands
xmm_mode_init(code, count_operand_forms[0])
if common_isa_extensions:
# Initialize isa_extensions only once for all forms with `count` operands
isa_extensions_init(code, count_operand_forms[0])
if count > 0:
# Instruction form with one or more operands
for (form_index, (instruction_form, instruction_subforms)) \
in enumerate(count_operand_form_trees):
is_avx512 = is_avx512_instruction_form(instruction_form)
operand_checks = map(
lambda o: generate_operand_check(o[0], o[1], evex_form=is_avx512),
enumerate(instruction_form.operands))
code.line("%s %s:" % ("if" if form_index == 0 else "elif", " and ".join(operand_checks)))
with CodeBlock():
instruction_form_init(code, instruction_form, instruction_subforms,
not common_go_name, not common_gas_name,
not common_in_regs, not common_out_regs,
not common_out_operands,
not common_mmx_mode, not common_xmm_mode,
not common_isa_extensions)
# For branch instructions with rel32 operand additionally generate label form
if is_label_branch(instruction_form):
code.line("elif is_label(self.operands[0]):")
with CodeBlock():
instruction_branch_label_form_init(code,
instruction_form, instruction_subforms,
not common_gas_name, not common_in_regs)
code.line("else:")
with CodeBlock():
code.line("raise SyntaxError(\"Invalid operand types: " + name + " \" + \", \".join(map(format_operand_type, self.operands)))")
else:
# Instruction form with no operands
instruction_form_init(code, count_operand_forms[0], count_operand_form_trees[0][1],
not common_go_name, not common_gas_name,
not common_in_regs, not common_out_regs,
not common_out_operands,
not common_mmx_mode, not common_xmm_mode,
not common_isa_extensions)
if consider_operand_count:
code.line("else:")
code.indent_line("raise SyntaxError(\"Invalid number of operands for instruction \\\"" + name + "\\\"\")")
code.line("if peachpy.stream.active_stream is not None:")
code.line("peachpy.stream.active_stream.add_instruction(self)", indent=1)
code.line()
code.line()
print(str(code), file=out)
if __name__ == "__main__":
main()
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
active_writer = None
class CodeWriter:
def __init__(self):
self.lines = list()
self.indent = 0
self.previous_writer = None
def __enter__(self):
global active_writer
self.previous_writer = active_writer
active_writer = self
return self
def __exit__(self, exc_type, exc_value, traceback):
global active_writer
active_writer = self.previous_writer
self.previous_writer = None
def line(self, line="", indent=0):
if line != "":
self.lines.append(" "*(self.indent+int(indent)) + str(line))
else:
self.lines.append(line)
def indent_line(self, line=""):
self.line(line, indent=1)
def __str__(self):
return "\n".join(self.lines)
class CodeBlock:
def __init__(self, indent=True):
self.indent = bool(indent)
def __enter__(self):
global active_writer
active_writer.indent += int(self.indent)
return self
def __exit__(self, exc_type, exc_value, traceback):
global active_writer
active_writer.indent -= int(self.indent)
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from __future__ import print_function
from opcodes.x86_64 import *
from codegen.code import CodeWriter, CodeBlock
import operator
import json
instruction_set = read_instruction_set()
active_code_writer = None
instruction_groups = json.load(open(os.path.join(os.path.dirname(__file__), "x86_64.json")))
def filter_instruction_forms(instruction_forms):
"""Removes the instruction forms that are currently not supported"""
new_instruction_forms = list()
for instruction_form in instruction_forms:
if all([operand.type not in {"r8l", "r16l", "r32l", "moffs32", "moffs64"} for operand in instruction_form.operands]):
new_instruction_forms.append(instruction_form)
return new_instruction_forms
def generate_operand(operand):
value_map = {
"r8": "dl",
"r16": "cx",
"r32": "ebx",
"r64": "rdi",
"mm": "mm4",
"xmm": "xmm7",
"ymm": "ymm3",
"m": "[r15+rsi*1-128]",
"m8": "byte[r15+rsi*1+8]",
"m16": "word[r15+rsi*1+16]",
"m32": "dword[r15+rsi*1+32]",
"m64": "qword[r15+rsi*1+64]",
"m128": "oword[r15+rsi*1+128]",
"m256": "hword[r15+rsi*1+256]",
"imm4": "0b11",
"imm8": "2",
"imm16": "32000",
"imm32": "0x10000000",
"imm64": "0x100000000",
"rel32": "rip+0",
"rel8": "rip+0",
"al": "al",
"cl": "cl",
"ax": "ax",
"eax": "eax",
"rax": "rax",
"xmm0": "xmm0",
"1": "1",
"3": "3"
}
optype = operand.type
return value_map.get(optype)
tab = " " * 4
with open("codegen/x86_64_nacl.py", "w") as out:
print("from __future__ import print_function\n\
from peachpy.x86_64 import *\n\
\n\
instruction_list = []\n\
", file=out)
for group, instruction_names in instruction_groups.iteritems():
with CodeWriter() as code:
code.line("# " + group)
for name in instruction_names:
# Instructions with `name` name
name_instructions = filter(lambda i: i.name == name, instruction_set)
if not name_instructions:
print("No forms for instruction: " + name)
continue
assert len(name_instructions) == 1
name_instruction = name_instructions[0]
code.line()
for instruction_form in filter_instruction_forms(name_instruction.forms):
operands = map(generate_operand, instruction_form.operands)
if not any(map(lambda op: op is None, operands)):
instruction_text = "%s(%s)" % (instruction_form.name, ", ".join(operands))
if any(map(operator.attrgetter("is_memory"), instruction_form.operands)):
code.line("instruction_list.append((\"%s\", (MOV(esi, esi), %s)))" % (str(instruction_form), instruction_text))
else:
code.line("instruction_list.append((\"%s\", (%s,)))" % (str(instruction_form), instruction_text))
print(str(code), file=out)
print("\n\
import operator\n\
\n\
bundles = open(\"codegen/x86_64_bundles.h\", \"w\")\n\
names = open(\"codegen/x86_64_names.h\", \"w\")\n\
\n\
print(\"static const uint8_t bundles[][32] = {\", file=bundles)\n\
print(\"static const char* names[] = {\", file=names)\n\
\n\
for (text, instructions) in instruction_list:\n\
bundle = bytearray([0xF4] * 32)\n\
encoding = sum(map(operator.methodcaller(\"encode\"), instructions), bytearray())\n\
bundle[0:len(encoding)] = encoding\n\
print(\"\\t{\" + \", \".join(map(lambda b: \"0x%02X\" % b, bundle)) + \"},\", file=bundles)\n\
print(\"\\t\\\"%s\\\",\" % text, file=names)\n\
\n\
print(\"};\\n\", file=names)\n\
print(\"};\\n\", file=bundles)", file=out) |
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from __future__ import print_function
from opcodes.x86_64 import *
from codegen.code import CodeWriter, CodeBlock
import os
import json
import subprocess
import tempfile
instruction_set = read_instruction_set()
instruction_groups = json.load(open(os.path.join(os.path.dirname(__file__), "x86_64.json")))
def filter_instruction_forms(instruction_forms):
"""Removes the instruction forms that are currently not supported"""
new_instruction_forms = list()
for instruction_form in instruction_forms:
if all([operand.type not in {"r8l", "r16l", "r32l", "moffs32", "moffs64"} for operand in instruction_form.operands]):
new_instruction_forms.append(instruction_form)
return new_instruction_forms
def is_avx512_instruction_form(instruction_form):
return instruction_form.isa_extensions and instruction_form.isa_extensions[0].name.startswith("AVX512")
def objcopy(*args):
objdump_path = os.environ.get("OBJCOPY_FOR_X86", os.environ.get("OBJCOPY"))
assert objdump_path, "objcopy not found, please set the environment variable OBJCOPY_FOR_X86"
objdump_process = subprocess.Popen([objdump_path] + list(args),
shell=False,
stdin=subprocess.PIPE, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
(stdoutdata, stderrdata) = objdump_process.communicate()
if objdump_process.returncode != 0:
print(stdoutdata)
print(stderrdata)
def gas(*args):
gas_path = os.environ.get("AS_FOR_X86", os.environ.get("GAS"))
assert gas_path, "GNU assembler not found, please set the environment variable AS_FOR_X86"
gas_process = subprocess.Popen([gas_path] + list(args),
shell=False,
stdin=subprocess.PIPE, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
(stdoutdata, stderrdata) = gas_process.communicate()
if gas_process.returncode != 0:
print(stdoutdata)
print(stderrdata)
return stdoutdata.decode ('ascii', errors='replace')
def binutils_encode(assembly):
with tempfile.NamedTemporaryFile(mode='w+', delete=False) as asm_file:
print(".text", file=asm_file)
print(".intel_syntax noprefix", file=asm_file)
print(assembly, file=asm_file)
obj_file = tempfile.NamedTemporaryFile(delete=False)
obj_file.close()
bin_file = tempfile.NamedTemporaryFile(delete=False)
bin_file.close()
try:
gas("-o", obj_file.name, asm_file.name)
os.remove(asm_file.name)
objcopy("-O", "binary", "-j", ".text", obj_file.name, bin_file.name)
os.remove(obj_file.name)
except OSError:
print(assembly)
raise
bytecode = bytearray(open(bin_file.name, "rb").read())
os.remove(bin_file.name)
return "bytearray([%s])" % ", ".join(["0x%02X" % b for b in bytecode])
def generate_operand(operand, operand_number, peachpy=True, evex=False):
value_map = {
"r8": ["bl", "r9b", "dl", "r11b"],
"r16": ["si", "r12w", "di", "r14w"],
"r32": ["ebp", "r8d", "eax", "r10d"],
"r64": ["rcx", "r15", "rax", "r13"],
"mm": ["mm3", "mm5"],
"xmm": ["xmm1", "xmm14", "xmm3", "xmm9"],
"xmm{k}": "xmm5{k1}",
"xmm{k}{z}": "xmm30{k2}{z}",
"ymm": ["ymm2", "ymm15", "ymm4", "ymm10"],
"ymm{k}": "ymm24{k3}",
"ymm{k}{z}": "ymm19{k5}{z}",
"zmm": ["zmm3", "zmm26", "zmm9", "zmm17"],
"zmm{k}": "zmm26{k7}",
"zmm{k}{z}": "zmm9{k6}{z}",
"k": "k5",
"k{k}": "k4{k6}",
"m": "[r15 + rsi*8 - 128]",
"m8": "byte[r14 + rdi*4 - 123]",
"m16": "word[r13 + rbp*8 - 107]",
"m32": "dword[r12 + rcx*8 - 99]",
"m64": "qword[r11 + rdx*8 - 88]",
"m64/m32bcst": "qword[r11 + rdx*8 - 88]",
"m128": "oword[r10 + rax*8 - 77]",
"m128/m32bcst": "oword[r10 + rax*8 - 77]",
"m128/m64bcst": "oword[r10 + rax*8 - 77]",
"m256": "hword[r9 + rbx*8 - 66]",
"m256/m32bcst": "hword[r9 + rbx*8 - 66]",
"m256/m64bcst": "hword[r9 + rbx*8 - 66]",
"m512": "zword[r9 + rbx*8 - 66]",
"m512/m32bcst": "zword[r9 + rbx*8 - 66]",
"m512/m64bcst": "zword[r9 + rbx*8 - 66]",
"m8{k}{z}": ["byte[r14 - 64]", "byte[r14 + 64]", "byte[r14 - 128]{k1}{z}"],
"m16{k}{z}": ["word[r13 - 64]", "word[r13 + 64]", "word[r13 - 128]{k2}{z}"],
"m32{k}{z}": ["dword[r12 - 64]", "dword[r12 + 64]", "dword[r12 - 128]{k3}{z}"],
"m64{k}{z}": ["qword[r11 - 64]", "qword[r11 + 64]", "qword[r11 - 128]{k4}{z}"],
"m128{k}{z}": ["oword[r10 - 64]", "oword[r10 + 64]", "oword[r10 - 128]{k5}{z}"],
"m256{k}{z}": ["hword[r9 - 64]", "hword[r9 + 64]", "hword[r9 - 128]{k6}{z}"],
"m512{k}{z}": ["zword[r8 - 64]", "zword[r8 + 64]", "zword[r8 - 128]{k7}{z}"],
"m32{k}": ["dword[r12 - 64]", "dword[r12 + 64]", "dword[r12 - 128]{k5}"],
"m64{k}": ["qword[r11 - 64]", "qword[r11 + 64]", "qword[r11 - 128]{k6}"],
"vm32x": "[rsi + xmm0 * 4 - 128]",
"vm32y": "[r11 + ymm8 * 4 + 48]",
"vm32z": "[r15 + zmm19 * 4 - 16]",
"vm64x": "[rsi + xmm1 * 8 + 40]",
"vm64y": "[r11 + ymm9 * 8 - 56]",
"vm64z": "[r15 + zmm20 * 8 + 72]",
"vm32x{k}": "[rsi + xmm0 * 4 - 128]{k1}",
"vm32y{k}": "[r11 + ymm8 * 4 + 48]{k2}",
"vm32z{k}": "[r15 + zmm19 * 4 - 16]{k3}",
"vm64x{k}": "[rsi + xmm1 * 8 + 40]{k4}",
"vm64y{k}": "[r11 + ymm9 * 8 - 56]{k5}",
"vm64z{k}": "[r15 + zmm20 * 8 + 72]{k6}",
"imm4": "0b11",
"imm8": "2",
"imm16": "32000",
"imm32": "0x10000000",
"imm64": "0x100000000",
# "rel32": "rip+0x11223344",
# "rel8": "rip-100",
"al": "al",
"cl": "cl",
"ax": "ax",
"eax": "eax",
"rax": "rax",
"xmm0": "xmm0",
"1": "1",
"3": "3",
"{sae}": "{sae}",
"{er}": "{rn-sae}",
}
evex_value_map = {
"xmm": ["xmm16", "xmm4", "xmm19", "xmm31"],
"ymm": ["ymm17", "ymm5", "ymm20", "ymm30"],
"m8": ["byte[r14 - 64]", "byte[r14 + 64]", "byte[r14 - 128]"],
"m16": ["word[r13 - 64]", "word[r13 + 64]", "word[r13 - 128]"],
"m32": ["dword[r12 - 64]", "dword[r12 + 64]", "dword[r12 - 128]"],
"m64": ["qword[r11 - 64]", "qword[r11 + 64]", "qword[r11 - 128]"],
"m128": ["oword[r10 - 64]", "oword[r10 + 64]", "oword[r10 - 128]"],
"m256": ["hword[r9 - 64]", "hword[r9 + 64]", "hword[r9 - 128]"],
"m512": ["zword[r8 - 64]", "zword[r8 + 64]", "zword[r8 - 128]"],
}
peachpy_value_map = {
"vm32x{k}": "[rsi + xmm0(k1) * 4 - 128]",
"vm32y{k}": "[r11 + ymm8(k2) * 4 + 48]",
"vm32z{k}": "[r15 + zmm19(k3) * 4 - 16]",
"vm64x{k}": "[rsi + xmm1(k4) * 8 + 40]",
"vm64y{k}": "[r11 + ymm9(k5) * 8 - 56]",
"vm64z{k}": "[r15 + zmm20(k6) * 8 + 72]",
}
optype = operand.type
operand = value_map.get(optype)
if evex:
operand = evex_value_map.get(optype, operand)
if peachpy:
operand = peachpy_value_map.get(optype, operand)
if isinstance(operand, list):
operand = operand[operand_number]
if operand is not None and not peachpy:
operand = operand.\
replace("byte", "BYTE PTR ").\
replace("dword", "DWORD PTR").\
replace("qword", "QWORD PTR").\
replace("oword", "XMMWORD PTR").\
replace("hword", "YMMWORD PTR").\
replace("zword", "ZMMWORD PTR").\
replace("word", "WORD PTR").\
replace("rip", "$+2")
if operand is not None and peachpy:
for kn in range(1, 8):
kreg = "k" + str(kn)
operand = operand.replace("{" + kreg + "}", "(" + kreg + ")")
operand = operand.replace("){z}", ".z)")
operand = operand.replace("{rn-sae}", "{rn_sae}")
operand = operand.replace("{rz-sae}", "{rz_sae}")
operand = operand.replace("{ru-sae}", "{ru_sae}")
operand = operand.replace("{rd-sae}", "{rd_sae}")
return operand
tab = " " * 4
def main(package_root="."):
for group, instruction_names in instruction_groups.items():
with open(os.path.join (package_root, "test", "x86_64", "encoding", "test_%s.py" % group), "w") as out:
with CodeWriter() as code:
code.line("# This file is auto-generated by /codegen/x86_64_test_encoding.py")
code.line("# Reference opcodes are generated by:")
code.line("# " + gas("--version").splitlines()[0])
code.line()
code.line("from peachpy.x86_64 import *")
code.line("import unittest")
code.line()
code.line()
for name in instruction_names:
code.line("class Test%s(unittest.TestCase):" % name)
with CodeBlock():
code.line("def runTest(self):")
with CodeBlock():
# Instructions with `name` name
name_instructions = list(filter(lambda i: i.name == name, instruction_set))
if not name_instructions:
print("No forms for instruction: " + name)
continue
assert len(name_instructions) == 1
name_instruction = name_instructions[0]
has_assertions = False
for instruction_form in filter_instruction_forms(name_instruction.forms):
is_avx512 = is_avx512_instruction_form(instruction_form)
peachpy_operands = [generate_operand(o, i, peachpy=True, evex=is_avx512) for (i, o)
in enumerate(instruction_form.operands)]
gas_operands = [generate_operand(o, i, peachpy=False, evex=is_avx512) for (i, o)
in enumerate(instruction_form.operands)]
if not any(map(lambda op: op is None, gas_operands)):
gas_assembly = "%s %s" % (instruction_form.name, ", ".join(gas_operands))
peachpy_assembly = "%s(%s)" % (instruction_form.name, ", ".join(peachpy_operands))
reference_bytecode = binutils_encode(gas_assembly)
code.line("self.assertEqual(%s, %s.encode())" %
(reference_bytecode, peachpy_assembly))
has_assertions = True
if not has_assertions:
code.line("pass")
code.line()
code.line()
print(str(code), file=out)
if __name__ == '__main__':
main()
|
import sphinx_bootstrap_theme
from peachpy import __version__
extensions = [
'sphinx.ext.autodoc'
]
source_suffix = '.rst'
master_doc = 'index'
autoclass_content = "both"
project = u'PeachPy'
copyright = u'2013-2015, Georgia Institute of Technology'
version = __version__
release = __version__
pygments_style = 'sphinx'
html_theme = 'bootstrap'
html_theme_path = sphinx_bootstrap_theme.get_html_theme_path()
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy.x86_64 import *
from peachpy import *
a = Argument(ptr(const_float_))
b = Argument(ptr(const_float_))
c = Argument(ptr(float_))
with Function("matmul", (a, b, c)) as function:
reg_a = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_a, a)
reg_b = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_b, b)
reg_c = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_c, c)
xmm_Brow0 = XMMRegister()
MOVUPS(xmm_Brow0, [reg_b + 0])
xmm_Brow1 = XMMRegister()
MOVUPS(xmm_Brow1, [reg_b + 16])
xmm_Brow2 = XMMRegister()
MOVUPS(xmm_Brow2, [reg_b + 32])
xmm_Brow3 = XMMRegister()
MOVUPS(xmm_Brow3, [reg_b + 48])
for k in range(4):
xmm_Ak0 = XMMRegister()
MOVSS(xmm_Ak0, [reg_a + k * 16])
SHUFPS(xmm_Ak0, xmm_Ak0, 0x00)
MULPS(xmm_Ak0, xmm_Brow0)
xmm_Ak1 = XMMRegister()
MOVSS(xmm_Ak1, [reg_a + k * 16 + 4])
SHUFPS(xmm_Ak1, xmm_Ak1, 0x00)
MULPS(xmm_Ak1, xmm_Brow1)
ADDPS(xmm_Ak0, xmm_Ak1)
xmm_Ak2 = XMMRegister()
MOVSS(xmm_Ak2, [reg_a + k * 16 + 8])
SHUFPS(xmm_Ak2, xmm_Ak2, 0x00)
MULPS(xmm_Ak2, xmm_Brow2)
xmm_Ak3 = XMMRegister()
MOVSS(xmm_Ak3, [reg_a + k * 16 + 12])
SHUFPS(xmm_Ak3, xmm_Ak3, 0x00)
MULPS(xmm_Ak3, xmm_Brow3)
ADDPS(xmm_Ak2, xmm_Ak3)
ADDPS(xmm_Ak0, xmm_Ak2)
MOVUPS([reg_c + k * 16], xmm_Ak0)
RETURN()
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy.x86_64 import *
from peachpy import *
matrix = Argument(ptr(float_))
with Function("transpose4x4_opt", (matrix,)):
reg_matrix = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_matrix, matrix)
xmm_rows = [XMMRegister() for _ in range(4)]
for i, xmm_row in enumerate(xmm_rows):
MOVUPS(xmm_row, [reg_matrix + i * XMMRegister.size])
xmm_temps = [XMMRegister() for _ in range(2)]
# xmm_temps[0] = ( m00, m01, m02, m03 )
MOVAPS(xmm_temps[0], xmm_rows[0])
# xmm_temps[1] = ( m20, m21, m22, m23 )
MOVAPS(xmm_temps[1], xmm_rows[2])
# xmm_rows[0] = ( m00, m10, m01, m11 )
UNPCKLPS(xmm_rows[0], xmm_rows[1])
# xmm_rows[2] = ( m20, m30, m21, m31 )
UNPCKLPS(xmm_rows[2], xmm_rows[3])
# xmm_rows[1] = ( m02, m12, m03, m13 )
UNPCKHPS(xmm_temps[0], xmm_rows[1])
xmm_rows[1] = xmm_temps[0]
# xmm_rows[3] = ( m22, m32, m23, m33 )
UNPCKHPS(xmm_temps[1], xmm_rows[3])
xmm_rows[3] = xmm_temps[1]
xmm_temps = [XMMRegister() for _ in range(2)]
# xmm_temps[0] = ( m00, m10, m01, m11 )
MOVAPS(xmm_temps[0], xmm_rows[0])
# xmm_temps[1] = ( m02, m12, m03, m13 )
MOVAPS(xmm_temps[1], xmm_rows[1])
# xmm_rows[0] = ( m00, m10, m20, m30 )
MOVLHPS(xmm_rows[0], xmm_rows[2])
MOVUPS([reg_matrix], xmm_rows[0])
# xmm_rows[2] = ( m01, m11, m21, m31 )
MOVHLPS(xmm_rows[2], xmm_temps[0])
MOVUPS([reg_matrix + 16], xmm_rows[2])
# xmm_rows[1] = ( m02, m12, m22, m32 )
MOVLHPS(xmm_rows[1], xmm_rows[3])
MOVUPS([reg_matrix + 32], xmm_rows[1])
# xmm_rows[3] = ( m03, m13, m23, m33 )
MOVHLPS(xmm_rows[3], xmm_temps[1])
MOVUPS([reg_matrix + 48], xmm_rows[3])
RETURN()
|
# This file is part of PeachPy package and is licensed under the Simplified BSD license.
# See license.rst for the full text of the license.
from peachpy import *
from peachpy.x86_64 import *
x = Argument(ptr(const_float_))
y = Argument(ptr(const_float_))
length = Argument(size_t)
with Function("DotProduct", (x, y, length), float_, target=uarch.default + isa.fma3) as function:
reg_x = GeneralPurposeRegister64()
reg_y = GeneralPurposeRegister64()
reg_length = GeneralPurposeRegister64()
LOAD.ARGUMENT(reg_x, x)
LOAD.ARGUMENT(reg_y, y)
LOAD.ARGUMENT(reg_length, length)
vector_loop = Loop()
scalar_loop = Loop()
unroll_factor = 6
ymm_accs = [YMMRegister() for _ in range(unroll_factor)]
for ymm_acc in ymm_accs:
xmm_acc = ymm_acc.as_xmm
VXORPS(xmm_acc, xmm_acc, xmm_acc)
SUB(reg_length, 8*unroll_factor)
JB(vector_loop.end)
with vector_loop:
ymm_xs = [YMMRegister() for _ in range(unroll_factor)]
for (i, ymm_x) in enumerate(ymm_xs):
VMOVUPS(ymm_x, [reg_x + 32*i])
for (i, (ymm_acc, ymm_x)) in enumerate(zip(ymm_accs, ymm_xs)):
VFMADD132PS(ymm_acc, ymm_x, [reg_y + 32*i])
ADD(reg_x, 32*unroll_factor)
ADD(reg_y, 32*unroll_factor)
SUB(reg_length, 8*unroll_factor)
JAE(vector_loop.begin)
# Reduction of multiple YMM registers into into YMM register
VADDPS(ymm_accs[0], ymm_accs[0], ymm_accs[1])
VADDPS(ymm_accs[2], ymm_accs[2], ymm_accs[3])
VADDPS(ymm_accs[4], ymm_accs[4], ymm_accs[5])
VADDPS(ymm_accs[0], ymm_accs[0], ymm_accs[2])
VADDPS(ymm_accs[0], ymm_accs[0], ymm_accs[4])
ymm_acc = ymm_accs[0]
xmm_acc = ymm_acc.as_xmm
xmm_scalar_acc = XMMRegister()
VXORPS(xmm_scalar_acc, xmm_scalar_acc, xmm_scalar_acc)
ADD(reg_length, 8*unroll_factor)
JZ(scalar_loop.end)
with scalar_loop:
xmm_scalar_x = XMMRegister()
VMOVSS(xmm_scalar_x, [reg_x])
VFMADD132SS(xmm_scalar_acc, xmm_scalar_x, [reg_y])
ADD(reg_x, 4)
ADD(reg_y, 4)
SUB(reg_length, 1)
JNZ(scalar_loop.begin)
# Add remainder
VADDPS(ymm_acc, ymm_acc, xmm_scalar_acc.as_ymm)
xmm_temp = XMMRegister()
VEXTRACTF128(xmm_temp, ymm_acc, 1)
VADDPS(xmm_acc, xmm_acc, xmm_temp)
VHADDPS(xmm_acc, xmm_acc, xmm_acc)
VHADDPS(xmm_acc, xmm_acc, xmm_acc)
RETURN(xmm_acc)
|
"""GitHub Label Utilities."""
import json
from functools import lru_cache
from typing import Any, List, Tuple, TYPE_CHECKING, Union
from urllib.request import Request, urlopen
from github_utils import gh_fetch_url, GitHubComment
# TODO: this is a temp workaround to avoid circular dependencies,
# and should be removed once GitHubPR is refactored out of trymerge script.
if TYPE_CHECKING:
from trymerge import GitHubPR
BOT_AUTHORS = ["github-actions", "pytorchmergebot", "pytorch-bot"]
LABEL_ERR_MSG_TITLE = "This PR needs a label"
LABEL_ERR_MSG = f"""# {LABEL_ERR_MSG_TITLE}
If your changes are user facing and intended to be a part of release notes, please use a label starting with `release notes:`.
If not, please add the `topic: not user facing` label.
To add a label, you can comment to pytorchbot, for example
`@pytorchbot label "topic: not user facing"`
For more information, see
https://github.com/pytorch/pytorch/wiki/PyTorch-AutoLabel-Bot#why-categorize-for-release-notes-and-how-does-it-work.
"""
# Modified from https://github.com/pytorch/pytorch/blob/b00206d4737d1f1e7a442c9f8a1cadccd272a386/torch/hub.py#L129
def _read_url(url: Request) -> Tuple[Any, Any]:
with urlopen(url) as r:
return r.headers, r.read().decode(r.headers.get_content_charset("utf-8"))
def request_for_labels(url: str) -> Tuple[Any, Any]:
headers = {"Accept": "application/vnd.github.v3+json"}
return _read_url(Request(url, headers=headers))
def update_labels(labels: List[str], info: str) -> None:
labels_json = json.loads(info)
labels.extend([x["name"] for x in labels_json])
def get_last_page_num_from_header(header: Any) -> int:
# Link info looks like: <https://api.github.com/repositories/65600975/labels?per_page=100&page=2>;
# rel="next", <https://api.github.com/repositories/65600975/labels?per_page=100&page=3>; rel="last"
link_info = header["link"]
prefix = "&page="
suffix = ">;"
return int(
link_info[link_info.rindex(prefix) + len(prefix) : link_info.rindex(suffix)]
)
@lru_cache()
def gh_get_labels(org: str, repo: str) -> List[str]:
prefix = f"https://api.github.com/repos/{org}/{repo}/labels?per_page=100"
header, info = request_for_labels(prefix + "&page=1")
labels: List[str] = []
update_labels(labels, info)
last_page = get_last_page_num_from_header(header)
assert (
last_page > 0
), "Error reading header info to determine total number of pages of labels"
for page_number in range(2, last_page + 1): # skip page 1
_, info = request_for_labels(prefix + f"&page={page_number}")
update_labels(labels, info)
return labels
def gh_add_labels(
org: str, repo: str, pr_num: int, labels: Union[str, List[str]]
) -> None:
gh_fetch_url(
url=f"https://api.github.com/repos/{org}/{repo}/issues/{pr_num}/labels",
data={"labels": labels},
)
def gh_remove_label(org: str, repo: str, pr_num: int, label: str) -> None:
gh_fetch_url(
url=f"https://api.github.com/repos/{org}/{repo}/issues/{pr_num}/labels/{label}",
method="DELETE",
)
def get_release_notes_labels(org: str, repo: str) -> List[str]:
return [
label
for label in gh_get_labels(org, repo)
if label.lstrip().startswith("release notes:")
]
def has_required_labels(pr: "GitHubPR") -> bool:
pr_labels = pr.get_labels()
# Check if PR is not user facing
is_not_user_facing_pr = any(
label.strip() == "topic: not user facing" for label in pr_labels
)
return is_not_user_facing_pr or any(
label.strip() in get_release_notes_labels(pr.org, pr.project)
for label in pr_labels
)
def is_label_err_comment(comment: GitHubComment) -> bool:
return (
comment.body_text.lstrip(" #").startswith(LABEL_ERR_MSG_TITLE)
and comment.author_login in BOT_AUTHORS
)
|
#!/usr/bin/env python3
import base64
import json
import os
import re
import time
import urllib.parse
from dataclasses import dataclass
from datetime import datetime
from functools import lru_cache
import yaml
from typing import (
Any,
Callable,
Dict,
Iterable,
List,
Optional,
Pattern,
Tuple,
Union,
cast,
NamedTuple
)
from urllib.error import HTTPError
from urllib.request import Request, urlopen
from warnings import warn
from gitutils import (
GitRepo,
get_git_remote_name,
get_git_repo_dir,
patterns_to_regex,
)
from trymerge_explainer import (
TryMergeExplainer,
get_land_check_troubleshooting_message,
get_revert_message,
)
class WorkflowCheckState(NamedTuple):
status: Optional[str]
url: str
name: str
GH_PR_REVIEWS_FRAGMENT = """
fragment PRReviews on PullRequestReviewConnection {
nodes {
author {
login
}
state
}
pageInfo {
startCursor
hasPreviousPage
}
}
"""
GH_CHECKSUITES_FRAGMENT = """
fragment PRCheckSuites on CheckSuiteConnection {
edges {
node {
app {
name
databaseId
}
workflowRun {
workflow {
name
}
}
checkRuns(first: 50) {
nodes {
name
conclusion
detailsUrl
}
pageInfo {
endCursor
hasNextPage
}
}
conclusion
url
}
cursor
}
pageInfo {
hasNextPage
}
}
"""
GH_COMMIT_AUTHORS_FRAGMENT = """
fragment CommitAuthors on PullRequestCommitConnection {
nodes {
commit {
author {
user {
login
}
email
name
}
oid
}
}
pageInfo {
endCursor
hasNextPage
}
}
"""
GH_GET_PR_INFO_QUERY = GH_PR_REVIEWS_FRAGMENT + GH_CHECKSUITES_FRAGMENT + GH_COMMIT_AUTHORS_FRAGMENT + """
query ($owner: String!, $name: String!, $number: Int!) {
repository(owner: $owner, name: $name) {
pullRequest(number: $number) {
closed
isCrossRepository
author {
login
}
title
body
headRefName
headRepository {
nameWithOwner
}
baseRefName
baseRepository {
nameWithOwner
isPrivate
defaultBranchRef {
name
}
}
mergeCommit {
oid
}
commits_with_authors: commits(first: 100) {
...CommitAuthors
totalCount
}
commits(last: 1) {
nodes {
commit {
checkSuites(first: 10) {
...PRCheckSuites
}
pushedDate
oid
}
}
}
changedFiles
files(first: 100) {
nodes {
path
}
pageInfo {
endCursor
hasNextPage
}
}
reviews(last: 100) {
...PRReviews
}
comments(last: 5) {
nodes {
bodyText
author {
login
}
authorAssociation
editor {
login
}
databaseId
}
pageInfo {
startCursor
hasPreviousPage
}
}
labels(first: 100) {
edges {
node {
name
}
}
}
}
}
}
"""
GH_GET_PR_NEXT_FILES_QUERY = """
query ($owner: String!, $name: String!, $number: Int!, $cursor: String!) {
repository(name: $name, owner: $owner) {
pullRequest(number: $number) {
files(first: 100, after: $cursor) {
nodes {
path
}
pageInfo {
endCursor
hasNextPage
}
}
}
}
}
"""
GH_GET_PR_NEXT_CHECKSUITES = GH_CHECKSUITES_FRAGMENT + """
query ($owner: String!, $name: String!, $number: Int!, $cursor: String!) {
repository(name: $name, owner: $owner) {
pullRequest(number: $number) {
commits(last: 1) {
nodes {
commit {
oid
checkSuites(first: 10, after: $cursor) {
...PRCheckSuites
}
}
}
}
}
}
}
"""
GH_GET_COMMIT_CHECKSUITES = GH_CHECKSUITES_FRAGMENT + """
query ($owner: String!, $name: String!, $commit: String) {
repository(name: $name, owner: $owner) {
object(expression: $commit) {
... on Commit {
checkSuites {
...PRCheckSuites
}
}
}
}
}
"""
GH_GET_COMMIT_NEXT_CHECKSUITES = GH_CHECKSUITES_FRAGMENT + """
query ($owner: String!, $name: String!, $commit: String, $cursor: String!) {
repository(name: $name, owner: $owner) {
object(expression: $commit) {
... on Commit {
oid
checkSuites(first: 10, after: $cursor) {
...PRCheckSuites
}
}
}
}
}
"""
GH_GET_COMMIT_NEXT_CHECK_RUNS = """
query ($owner: String!, $name: String!, $cs_cursor: String, $cr_cursor: String!, $commit: String) {
repository(name: $name, owner: $owner) {
object(expression: $commit) {
... on Commit {
oid
checkSuites(first: 1, after: $cs_cursor) {
nodes {
checkRuns(first: 100, after: $cr_cursor) {
nodes {
name
conclusion
detailsUrl
}
pageInfo {
endCursor
hasNextPage
}
}
}
}
}
}
}
}
"""
GH_GET_PR_NEXT_CHECK_RUNS = """
query ($owner: String!, $name: String!, $number: Int!, $cs_cursor: String, $cr_cursor: String!) {
repository(name: $name, owner: $owner) {
pullRequest(number: $number) {
commits(last: 1) {
nodes {
commit {
oid
checkSuites(first: 1, after: $cs_cursor) {
nodes {
checkRuns(first: 100, after: $cr_cursor) {
nodes {
name
conclusion
detailsUrl
}
pageInfo {
endCursor
hasNextPage
}
}
}
}
}
}
}
}
}
}
"""
GH_GET_PR_PREV_COMMENTS = """
query ($owner: String!, $name: String!, $number: Int!, $cursor: String!) {
repository(name: $name, owner: $owner) {
pullRequest(number: $number) {
comments(last: 100, before: $cursor) {
nodes {
bodyText
author {
login
}
authorAssociation
editor {
login
}
databaseId
}
pageInfo {
startCursor
hasPreviousPage
}
}
}
}
}
"""
# This query needs read-org permission
GH_GET_TEAM_MEMBERS_QUERY = """
query($org: String!, $name: String!, $cursor: String) {
organization(login: $org) {
team(slug: $name) {
members(first: 100, after: $cursor) {
nodes {
login
}
pageInfo {
hasNextPage
endCursor
}
}
}
}
}
"""
GH_GET_PR_NEXT_AUTHORS_QUERY = GH_COMMIT_AUTHORS_FRAGMENT + """
query ($owner: String!, $name: String!, $number: Int!, $cursor: String) {
repository(name: $name, owner: $owner) {
pullRequest(number: $number) {
commits_with_authors: commits(first: 100, after: $cursor) {
...CommitAuthors
}
}
}
}
"""
GH_GET_PR_PREV_REVIEWS_QUERY = GH_PR_REVIEWS_FRAGMENT + """
query ($owner: String!, $name: String!, $number: Int!, $cursor: String!) {
repository(name: $name, owner: $owner) {
pullRequest(number: $number) {
reviews(last: 100, before: $cursor) {
...PRReviews
}
}
}
}
"""
RE_GHSTACK_HEAD_REF = re.compile(r"^(gh/[^/]+/[0-9]+/)head$")
RE_GHSTACK_DESC = re.compile(r'Stack.*:\r?\n(\* [^\r\n]+\r?\n)+', re.MULTILINE)
RE_PULL_REQUEST_RESOLVED = re.compile(
r'Pull Request resolved: '
r'https://github.com/(?P<owner>[^/]+)/(?P<repo>[^/]+)/pull/(?P<number>[0-9]+)',
re.MULTILINE
)
RE_DIFF_REV = re.compile(r'^Differential Revision:.+?(D[0-9]+)', re.MULTILINE)
CIFLOW_LABEL = re.compile(r"^ciflow/.+")
CIFLOW_TRUNK_LABEL = re.compile(r"^ciflow/trunk")
def _fetch_url(url: str, *,
headers: Optional[Dict[str, str]] = None,
data: Optional[Dict[str, Any]] = None,
method: Optional[str] = None,
reader: Callable[[Any], Any] = lambda x: x.read()) -> Any:
if headers is None:
headers = {}
token = os.environ.get("GITHUB_TOKEN")
if token is not None and url.startswith('https://api.github.com/'):
headers['Authorization'] = f'token {token}'
data_ = json.dumps(data).encode() if data is not None else None
try:
with urlopen(Request(url, headers=headers, data=data_, method=method)) as conn:
return reader(conn)
except HTTPError as err:
if err.code == 403 and all(key in err.headers for key in ['X-RateLimit-Limit', 'X-RateLimit-Used']):
print(f"Rate limit exceeded: {err.headers['X-RateLimit-Used']}/{err.headers['X-RateLimit-Limit']}")
raise
def fetch_json(url: str,
params: Optional[Dict[str, Any]] = None,
data: Optional[Dict[str, Any]] = None) -> List[Dict[str, Any]]:
headers = {'Accept': 'application/vnd.github.v3+json'}
if params is not None and len(params) > 0:
url += '?' + '&'.join(f"{name}={urllib.parse.quote(str(val))}" for name, val in params.items())
return cast(List[Dict[str, Any]], _fetch_url(url, headers=headers, data=data, reader=json.load))
def fetch_json_dict(url: str,
params: Optional[Dict[str, Any]] = None,
data: Optional[Dict[str, Any]] = None) -> Dict[str, Any] :
headers = {'Accept': 'application/vnd.github.v3+json'}
if params is not None and len(params) > 0:
url += '?' + '&'.join(f"{name}={urllib.parse.quote(str(val))}" for name, val in params.items())
return cast(Dict[str, Any], _fetch_url(url, headers=headers, data=data, reader=json.load))
def _gh_post_comment(url: str, comment: str, dry_run: bool = False) -> List[Dict[str, Any]]:
if dry_run:
print(comment)
return []
return fetch_json(url, data={"body": comment})
def gh_post_pr_comment(org: str, project: str, pr_num: int, comment: str, dry_run: bool = False) -> List[Dict[str, Any]]:
return _gh_post_comment(f'https://api.github.com/repos/{org}/{project}/issues/{pr_num}/comments', comment, dry_run)
def gh_post_commit_comment(org: str, project: str, sha: str, comment: str, dry_run: bool = False) -> List[Dict[str, Any]]:
return _gh_post_comment(f'https://api.github.com/repos/{org}/{project}/commits/{sha}/comments', comment, dry_run)
def gh_add_labels(org: str, project: str, pr_num: int, labels: Union[str, List[str]]) -> None:
fetch_json(f'https://api.github.com/repos/{org}/{project}/issues/{pr_num}/labels',
data={"labels": labels})
def gh_graphql(query: str, **kwargs: Any) -> Dict[str, Any]:
rc = _fetch_url("https://api.github.com/graphql", data={"query": query, "variables": kwargs}, reader=json.load)
if "errors" in rc:
raise RuntimeError(f"GraphQL query {query}, args {kwargs} failed: {rc['errors']}")
return cast(Dict[str, Any], rc)
def gh_get_pr_info(org: str, proj: str, pr_no: int) -> Any:
rc = gh_graphql(GH_GET_PR_INFO_QUERY, name=proj, owner=org, number=pr_no)
return rc["data"]["repository"]["pullRequest"]
def gh_get_land_check_info(org: str, proj: str, commit: str) -> Any:
rc = gh_graphql(GH_GET_COMMIT_CHECKSUITES, name=proj, owner=org, commit=commit)
return rc["data"]["repository"]["object"]
@lru_cache(maxsize=None)
def gh_get_team_members(org: str, name: str) -> List[str]:
rc: List[str] = []
team_members: Dict[str, Any] = {"pageInfo": {"hasNextPage": "true", "endCursor": None}}
while bool(team_members["pageInfo"]["hasNextPage"]):
query = gh_graphql(GH_GET_TEAM_MEMBERS_QUERY, org=org, name=name, cursor=team_members["pageInfo"]["endCursor"])
team = query["data"]["organization"]["team"]
if team is None:
warn(f"Requested non-existing team {org}/{name}")
return []
team_members = team["members"]
rc += [member["login"] for member in team_members["nodes"]]
return rc
def get_check_run_name_prefix(workflow_run: Any) -> str:
if workflow_run is None:
return ""
else:
return f'{workflow_run["workflow"]["name"]} / '
def add_workflow_conclusions(
checksuites: Any,
get_next_checkruns_page: Callable[[List[Dict[str, Dict[str, Any]]], int, Any], Any],
get_next_checksuites: Callable[[Any], Any]
) -> Dict[str, WorkflowCheckState]:
conclusions = {}
def add_conclusions(edges: Any) -> None:
for edge_idx, edge in enumerate(edges):
node = edge["node"]
workflow_run = node["workflowRun"]
checkruns = node["checkRuns"]
if workflow_run is not None:
workflow_name = workflow_run["workflow"]["name"]
workflow_conclusion = node["conclusion"]
# Do not override existing status with cancelled
if workflow_conclusion == "CANCELLED" and workflow_name in conclusions:
continue
conclusions[workflow_name] = WorkflowCheckState(
name=workflow_name,
status=workflow_conclusion,
url=node["url"])
has_failing_check = False
while checkruns is not None:
for checkrun_node in checkruns["nodes"]:
if not isinstance(checkrun_node, dict):
warn(f"Expected dictionary, but got {type(checkrun_node)}")
continue
if checkrun_node["conclusion"] == 'FAILURE':
has_failing_check = True
checkrun_name = f'{get_check_run_name_prefix(workflow_run)}{checkrun_node["name"]}'
conclusions[checkrun_name] = WorkflowCheckState(
name=checkrun_name,
status=checkrun_node["conclusion"],
url=checkrun_node["detailsUrl"]
)
if bool(checkruns["pageInfo"]["hasNextPage"]):
checkruns = get_next_checkruns_page(edges, edge_idx, checkruns)
else:
checkruns = None
# Github doesn't set conclusion to failure if a job is still pending
if workflow_run is not None and has_failing_check:
workflow_name = workflow_run["workflow"]["name"]
conclusions[workflow_name] = WorkflowCheckState(
name=workflow_name,
status="FAILURE",
url=node["url"])
add_conclusions(checksuites["edges"])
while bool(checksuites["pageInfo"]["hasNextPage"]):
checksuites = get_next_checksuites(checksuites)
add_conclusions(checksuites["edges"])
return conclusions
def parse_args() -> Any:
from argparse import ArgumentParser
parser = ArgumentParser("Merge PR into default branch")
parser.add_argument("--dry-run", action="store_true")
parser.add_argument("--on-green", action="store_true")
parser.add_argument("--on-mandatory", action="store_true")
parser.add_argument("--land-checks", action="store_true")
parser.add_argument("--revert", action="store_true")
parser.add_argument("--force", action="store_true")
parser.add_argument("--comment-id", type=int)
parser.add_argument("--reason", type=str)
parser.add_argument("pr_num", type=int)
return parser.parse_args()
def can_skip_internal_checks(pr: "GitHubPR", comment_id: Optional[int] = None) -> bool:
if comment_id is None:
return False
comment = pr.get_comment_by_id(comment_id)
if comment.editor_login is not None:
return False
return comment.author_login == "facebook-github-bot"
@dataclass
class GitHubComment:
body_text: str
author_login: str
author_association: str
editor_login: Optional[str]
database_id: int
class GitHubPR:
def __init__(self, org: str, project: str, pr_num: int) -> None:
assert isinstance(pr_num, int)
self.org = org
self.project = project
self.pr_num = pr_num
self.info = gh_get_pr_info(org, project, pr_num)
self.changed_files: Optional[List[str]] = None
self.labels: Optional[List[str]] = None
self.conclusions: Optional[Dict[str, WorkflowCheckState]] = None
self.comments: Optional[List[GitHubComment]] = None
self._authors: Optional[List[Tuple[str, str]]] = None
self._reviews: Optional[List[Tuple[str, str]]] = None
def is_closed(self) -> bool:
return bool(self.info["closed"])
def is_cross_repo(self) -> bool:
return bool(self.info["isCrossRepository"])
def base_ref(self) -> str:
return cast(str, self.info["baseRefName"])
def default_branch(self) -> str:
return cast(str, self.info["baseRepository"]["defaultBranchRef"]["name"])
def head_ref(self) -> str:
return cast(str, self.info["headRefName"])
def is_ghstack_pr(self) -> bool:
return RE_GHSTACK_HEAD_REF.match(self.head_ref()) is not None
def is_base_repo_private(self) -> bool:
return bool(self.info["baseRepository"]["isPrivate"])
def get_changed_files_count(self) -> int:
return int(self.info["changedFiles"])
def last_pushed_at(self) -> datetime:
return datetime.fromisoformat(self.last_commit()['pushedDate'][:-1])
def last_commit(self) -> Any:
return self.info["commits"]["nodes"][-1]["commit"]
def get_changed_files(self) -> List[str]:
if self.changed_files is None:
info = self.info
self.changed_files = []
# Do not try to fetch more than 10K files
for _ in range(100):
self.changed_files += [x["path"] for x in info["files"]["nodes"]]
if not info["files"]["pageInfo"]["hasNextPage"]:
break
rc = gh_graphql(GH_GET_PR_NEXT_FILES_QUERY,
name=self.project,
owner=self.org,
number=self.pr_num,
cursor=info["files"]["pageInfo"]["endCursor"])
info = rc["data"]["repository"]["pullRequest"]
if len(self.changed_files) != self.get_changed_files_count():
raise RuntimeError("Changed file count mismatch")
return self.changed_files
def _get_reviews(self) -> List[Tuple[str, str]]:
if self._reviews is None:
self._reviews = []
info = self.info
for _ in range(100):
nodes = info["reviews"]["nodes"]
self._reviews = [(node["author"]["login"], node["state"]) for node in nodes] + self._reviews
if not info["reviews"]["pageInfo"]["hasPreviousPage"]:
break
rc = gh_graphql(GH_GET_PR_PREV_REVIEWS_QUERY,
name=self.project,
owner=self.org,
number=self.pr_num,
cursor=info["reviews"]["pageInfo"]["startCursor"])
info = rc["data"]["repository"]["pullRequest"]
reviews = {}
for (author, state) in self._reviews:
if state != "COMMENTED":
reviews[author] = state
return list(reviews.items())
def get_approved_by(self) -> List[str]:
return [login for (login, state) in self._get_reviews() if state == "APPROVED"]
def get_commit_count(self) -> int:
return int(self.info["commits_with_authors"]["totalCount"])
def get_pr_creator_login(self) -> str:
return cast(str, self.info["author"]["login"])
def _fetch_authors(self) -> List[Tuple[str, str]]:
if self._authors is not None:
return self._authors
authors: List[Tuple[str, str]] = []
def add_authors(info: Dict[str, Any]) -> None:
for node in info["commits_with_authors"]["nodes"]:
author_node = node["commit"]["author"]
user_node = author_node["user"]
author = f"{author_node['name']} <{author_node['email']}>"
if user_node is None:
# If author is not github user, user node will be null
authors.append(("", author))
else:
authors.append((cast(str, user_node["login"]), author))
info = self.info
for _ in range(100):
add_authors(info)
if not info["commits_with_authors"]["pageInfo"]["hasNextPage"]:
break
rc = gh_graphql(GH_GET_PR_NEXT_AUTHORS_QUERY,
name=self.project,
owner=self.org,
number=self.pr_num,
cursor=info["commits_with_authors"]["pageInfo"]["endCursor"])
info = rc["data"]["repository"]["pullRequest"]
self._authors = authors
return authors
def get_committer_login(self, num: int = 0) -> str:
return self._fetch_authors()[num][0]
def get_committer_author(self, num: int = 0) -> str:
return self._fetch_authors()[num][1]
def get_labels(self) -> List[str]:
if self.labels is not None:
return self.labels
labels = [node['node']['name'] for node in self.info["labels"]["edges"]] if "labels" in self.info else []
self.labels = labels
return self.labels
def get_checkrun_conclusions(self) -> Dict[str, WorkflowCheckState]:
""" Returns dict of checkrun -> [conclusion, url] """
if self.conclusions is not None:
return self.conclusions
orig_last_commit = self.info["commits"]["nodes"][-1]["commit"]
def get_pr_next_check_runs(edges: List[Dict[str, Dict[str, Any]]], edge_idx: int, checkruns: Any) -> Any:
rc = gh_graphql(GH_GET_PR_NEXT_CHECK_RUNS,
name=self.project,
owner=self.org,
number=self.pr_num,
cs_cursor=edges[edge_idx - 1]["cursor"] if edge_idx > 0 else None,
cr_cursor=checkruns["pageInfo"]["endCursor"])
last_commit = rc["data"]["repository"]["pullRequest"]["commits"]["nodes"][-1]["commit"]
checkruns = last_commit["checkSuites"]["nodes"][-1]["checkRuns"]
return checkruns
def get_pr_next_checksuites(checksuites: Any) -> Any:
rc = gh_graphql(GH_GET_PR_NEXT_CHECKSUITES,
name=self.project,
owner=self.org,
number=self.pr_num,
cursor=checksuites["edges"][-1]["cursor"])
info = rc["data"]["repository"]["pullRequest"]
last_commit = info["commits"]["nodes"][-1]["commit"]
if last_commit["oid"] != orig_last_commit["oid"]:
raise RuntimeError("Last commit changed on PR")
return last_commit["checkSuites"]
checksuites = orig_last_commit["checkSuites"]
self.conclusions = add_workflow_conclusions(checksuites, get_pr_next_check_runs, get_pr_next_checksuites)
return self.conclusions
def get_authors(self) -> Dict[str, str]:
rc = {}
# TODO: replace with `self.get_commit_count()` when GraphQL pagination can be used
# to fetch all commits, see https://gist.github.com/malfet/4f35321b0c9315bcd7116c7b54d83372
# and https://support.github.com/ticket/enterprise/1642/1659119
if self.get_commit_count() <= 250:
assert len(self._fetch_authors()) == self.get_commit_count()
for idx in range(len(self._fetch_authors())):
rc[self.get_committer_login(idx)] = self.get_committer_author(idx)
return rc
def get_author(self) -> str:
authors = self.get_authors()
if len(authors) == 1:
return next(iter(authors.values()))
creator = self.get_pr_creator_login()
# If PR creator is not among authors
# Assume it was authored by first commit author
if creator not in authors:
return self.get_committer_author(0)
return authors[creator]
def get_title(self) -> str:
return cast(str, self.info["title"])
def get_body(self) -> str:
return cast(str, self.info["body"])
def get_merge_commit(self) -> Optional[str]:
mc = self.info["mergeCommit"]
return mc["oid"] if mc is not None else None
def get_pr_url(self) -> str:
return f"https://github.com/{self.org}/{self.project}/pull/{self.pr_num}"
@staticmethod
def _comment_from_node(node: Any) -> GitHubComment:
editor = node["editor"]
return GitHubComment(body_text=node["bodyText"],
author_login=node["author"]["login"],
author_association=node["authorAssociation"],
editor_login=editor["login"] if editor else None,
database_id=node["databaseId"]
)
def get_comments(self) -> List[GitHubComment]:
if self.comments is not None:
return self.comments
self.comments = []
info = self.info["comments"]
# Do not try to fetch more than 10K comments
for _ in range(100):
self.comments = [self._comment_from_node(node) for node in info["nodes"]] + self.comments
if not info["pageInfo"]["hasPreviousPage"]:
break
rc = gh_graphql(GH_GET_PR_PREV_COMMENTS,
name=self.project,
owner=self.org,
number=self.pr_num,
cursor=info["pageInfo"]["startCursor"])
info = rc["data"]["repository"]["pullRequest"]["comments"]
return self.comments
def get_last_comment(self) -> GitHubComment:
return self._comment_from_node(self.info["comments"]["nodes"][-1])
def get_comment_by_id(self, database_id: int) -> GitHubComment:
if self.comments is None:
# Fastpath - try searching in partial prefetched comments
for node in self.info["comments"]["nodes"]:
comment = self._comment_from_node(node)
if comment.database_id == database_id:
return comment
for comment in self.get_comments():
if comment.database_id == database_id:
return comment
raise RuntimeError(f"Comment with id {database_id} not found")
def get_diff_revision(self) -> Optional[str]:
rc = RE_DIFF_REV.search(self.get_body())
return rc.group(1) if rc is not None else None
def has_internal_changes(self) -> bool:
checkrun_name = "Meta Internal-Only Changes Check"
if self.get_diff_revision() is None:
return False
checks = self.get_checkrun_conclusions()
if checks is None or checkrun_name not in checks:
return False
return checks[checkrun_name].status != "SUCCESS"
def merge_ghstack_into(
self,
repo: GitRepo,
force: bool,
comment_id: Optional[int] = None,
land_check_commit: Optional[str] = None
) -> None:
assert self.is_ghstack_pr()
# For ghstack, cherry-pick commits based from origin
orig_ref = f"{repo.remote}/{re.sub(r'/head$', '/orig', self.head_ref())}"
rev_list = repo.revlist(f"{self.default_branch()}..{orig_ref}")
for idx, rev in enumerate(reversed(rev_list)):
msg = repo.commit_message(rev)
m = RE_PULL_REQUEST_RESOLVED.search(msg)
if m is None:
raise RuntimeError(f"Could not find PR-resolved string in {msg} of ghstacked PR {self.pr_num}")
if self.org != m.group('owner') or self.project != m.group('repo'):
raise RuntimeError(f"PR {m.group('number')} resolved to wrong owner/repo pair")
pr_num = int(m.group('number'))
commit_msg = self.gen_commit_message(filter_ghstack=True)
if pr_num != self.pr_num:
pr = GitHubPR(self.org, self.project, pr_num)
if pr.is_closed():
print(f"Skipping {idx+1} of {len(rev_list)} PR (#{pr_num}) as its already been merged")
continue
commit_msg = pr.gen_commit_message(filter_ghstack=True)
# Raises exception if matching rule is not found
find_matching_merge_rule(
pr,
repo,
force=force,
skip_internal_checks=can_skip_internal_checks(self, comment_id),
land_check_commit=land_check_commit)
repo.cherry_pick(rev)
repo.amend_commit_message(commit_msg)
def gen_commit_message(self, filter_ghstack: bool = False) -> str:
""" Fetches title and body from PR description
adds reviewed by, pull request resolved and optionally
filters out ghstack info """
# Adding the url here makes it clickable within the Github UI
approved_by_urls = ', '.join(prefix_with_github_url(login) for login in self.get_approved_by())
msg = self.get_title() + f" (#{self.pr_num})\n\n"
msg += self.get_body() if not filter_ghstack else re.sub(RE_GHSTACK_DESC, "", self.get_body())
msg += f"\nPull Request resolved: {self.get_pr_url()}\n"
msg += f"Approved by: {approved_by_urls}\n"
return msg
def add_numbered_label(self, label_base: str) -> None:
labels = self.get_labels()
label = label_base
for i in range(len(labels) if labels is not None else 0):
if label in labels:
label = f"{label_base}X{i+2}"
gh_add_labels(self.org, self.project, self.pr_num, [label])
def merge_into(self, repo: GitRepo, *,
force: bool = False,
dry_run: bool = False,
comment_id: Optional[int] = None,
land_check_commit: Optional[str] = None) -> None:
# Raises exception if matching rule is not found
find_matching_merge_rule(
self,
repo,
force=force,
skip_internal_checks=can_skip_internal_checks(self, comment_id),
land_check_commit=land_check_commit)
self.merge_changes(repo, force, comment_id, land_check_commit=land_check_commit)
repo.push(self.default_branch(), dry_run)
if not dry_run:
self.add_numbered_label("merged")
def merge_changes(self,
repo: GitRepo,
force: bool = False,
comment_id: Optional[int] = None,
land_check_commit: Optional[str] = None,
branch: Optional[str] = None) -> None:
branch_to_merge_into = self.default_branch() if branch is None else branch
if repo.current_branch() != branch_to_merge_into:
repo.checkout(branch_to_merge_into)
if not self.is_ghstack_pr():
msg = self.gen_commit_message()
pr_branch_name = f"__pull-request-{self.pr_num}__init__"
repo.fetch(f"pull/{self.pr_num}/head", pr_branch_name)
repo._run_git("merge", "--squash", pr_branch_name)
repo._run_git("commit", f"--author=\"{self.get_author()}\"", "-m", msg)
else:
self.merge_ghstack_into(repo, force, comment_id=comment_id, land_check_commit=land_check_commit)
def create_land_time_check_branch(self,
repo: GitRepo,
branch: str,
force: bool = False,
comment_id: Optional[int] = None,) -> str:
self.merge_changes(repo, branch=branch, force=force, comment_id=comment_id)
land_check_branch = f'landchecks/{self.pr_num}'
try:
repo._run_git('branch', "-D", land_check_branch)
except Exception:
pass
repo._run_git('checkout', "-b", land_check_branch)
repo._run_git('push', '-u', 'origin', land_check_branch, '--force')
commit = repo.get_commit('HEAD').commit_hash
return commit
class MandatoryChecksMissingError(Exception):
pass
class PostCommentError(Exception):
pass
@dataclass
class MergeRule:
name: str
patterns: List[str]
approved_by: List[str]
mandatory_checks_name: Optional[List[str]]
def read_merge_rules(repo: Optional[GitRepo], org: str, project: str) -> List[MergeRule]:
from pathlib import Path
repo_relative_rules_path = Path(".github") / "merge_rules.yaml"
if repo is None:
json_data = _fetch_url(
f"https://api.github.com/repos/{org}/{project}/contents/{repo_relative_rules_path}",
headers={'Accept': 'application/vnd.github.v3+json'},
reader=json.load,
)
content = base64.b64decode(json_data["content"])
return [MergeRule(**x) for x in yaml.safe_load(content)]
else:
rules_path = Path(repo.repo_dir) / repo_relative_rules_path
if not rules_path.exists():
print(f"{rules_path} does not exist, returning empty rules")
return []
with open(rules_path) as fp:
rc = yaml.safe_load(fp)
return [MergeRule(**x) for x in rc]
def find_matching_merge_rule(pr: GitHubPR,
repo: Optional[GitRepo] = None,
force: bool = False,
skip_internal_checks: bool = False,
land_check_commit: Optional[str] = None,
) -> MergeRule:
"""Returns merge rule matching to this pr or raises an exception"""
changed_files = pr.get_changed_files()
approved_by = set(pr.get_approved_by())
rules = read_merge_rules(repo, pr.org, pr.project)
reject_reason = f"PR {pr.pr_num} does not match merge rules"
# Used to determine best rejection reason
# Score 0 to 10K - how many files rule matched
# Score 10K - matched all files, but no overlapping approvers
# Score 20K - matched all files and approvers, but mandatory checks are pending
# Score 30k - Matched all files and approvers, but mandatory checks failed
reject_reason_score = 0
for rule in rules:
rule_name = rule.name
patterns_re = patterns_to_regex(rule.patterns)
non_matching_files = []
for fname in changed_files:
if not patterns_re.match(fname):
non_matching_files.append(fname)
if len(non_matching_files) > 0:
num_matching_files = len(changed_files) - len(non_matching_files)
if num_matching_files > reject_reason_score:
reject_reason_score = num_matching_files
reject_reason = (f"{num_matching_files} files matched rule {rule_name}, but there are still non-matching files: " +
f"{','.join(non_matching_files[:5])}{', ...' if len(non_matching_files) > 5 else ''}")
continue
# If rule needs approvers but PR has not been reviewed, skip it
if len(rule.approved_by) > 0 and len(approved_by) == 0:
if reject_reason_score < 10000:
reject_reason_score = 10000
reject_reason = f"Matched rule {rule_name}, but PR #{pr.pr_num} has not been reviewed yet"
continue
rule_approvers_set = set()
for approver in rule.approved_by:
if "/" in approver:
org, name = approver.split("/")
rule_approvers_set.update(gh_get_team_members(org, name))
else:
rule_approvers_set.add(approver)
approvers_intersection = approved_by.intersection(rule_approvers_set)
# If rule requires approvers but they aren't the ones that reviewed PR
if len(approvers_intersection) == 0 and len(rule_approvers_set) > 0:
if reject_reason_score < 10000:
reject_reason_score = 10000
reject_reason = (f"Matched rule {rule_name}, but PR #{pr.pr_num} was not reviewed yet by any of: " +
f"{', '.join(list(rule_approvers_set)[:5])}{', ...' if len(rule_approvers_set) > 5 else ''}")
continue
mandatory_checks = rule.mandatory_checks_name if rule.mandatory_checks_name is not None else []
checks = get_combined_checks_from_pr_and_land_validation(pr, land_check_commit)
required_checks = filter(lambda x: force is False or "CLA Check" in x, mandatory_checks)
[pending_checks, failed_checks] = categorize_checks(checks, required_checks)
if len(failed_checks) > 0:
if reject_reason_score < 30000:
reject_reason_score = 30000
reject_reason = (
f"[View failures on hud](https://hud.pytorch.org/{pr.org}/{pr.project}/commit/{pr.last_commit()['oid']}). "
+ f"Refusing to merge as mandatory check(s) {checks_to_str(failed_checks)} failed for "
+ f"rule {rule_name}."
)
continue
elif len(pending_checks) > 0:
if reject_reason_score < 20000:
reject_reason_score = 20000
reject_reason = (
f"[View pending jobs on hud](https://hud.pytorch.org/{pr.org}/{pr.project}/commit/{pr.last_commit()['oid']}). "
+ f"Refusing to merge as mandatory check(s) {checks_to_str(pending_checks)} are pending/not yet run for "
+ f"rule {rule_name}."
)
continue
if not skip_internal_checks and pr.has_internal_changes():
raise RuntimeError("This PR has internal changes and must be landed via Phabricator")
return rule
if reject_reason_score == 20000:
raise MandatoryChecksMissingError(reject_reason)
raise RuntimeError(reject_reason)
def get_land_checkrun_conclusions(org: str, project: str, commit: str) -> Dict[str, WorkflowCheckState]:
def get_commit_next_check_runs(edges: List[Dict[str, Dict[str, Any]]], edge_idx: int, checkruns: Any) -> Any:
rc = gh_graphql(GH_GET_COMMIT_NEXT_CHECK_RUNS,
name=project,
owner=org,
cs_cursor=edges[edge_idx - 1]["cursor"] if edge_idx > 0 else None,
cr_cursor=checkruns["pageInfo"]["endCursor"],
commit=commit)
return rc["data"]["repository"]["object"]["checkSuites"]["nodes"][-1]["checkRuns"]
def get_commit_next_checksuites(checksuites: Any) -> Any:
rc = gh_graphql(GH_GET_COMMIT_NEXT_CHECKSUITES,
name=project,
owner=org,
commit=commit,
cursor=checksuites["edges"][-1]["cursor"])
info = rc["data"]["repository"]["object"]
return info["checkSuites"]
land_check_info = gh_get_land_check_info(org, project, commit)
checksuites = land_check_info["checkSuites"]
return add_workflow_conclusions(checksuites, get_commit_next_check_runs, get_commit_next_checksuites)
def checks_to_str(checks: List[Tuple[str, Optional[str]]]) -> str:
return ", ".join(f"[{c[0]}]({c[1]})" if c[1] is not None else c[0] for c in checks)
def get_combined_checks_from_pr_and_land_validation(
pr: GitHubPR,
land_check_commit: Optional[str]
) -> Dict[str, WorkflowCheckState]:
"""
Combines checks from both the PR and land validation to get a holistic view
of all checks.
This helps us cover the corner case where certain workflows may have been
requested on the PR but are not part of land validation (e.g. nightly
builds) or are implicitly run on PRs but not on land validation branches
(like CLA Checks).
At the same time, we prioritize the signal workflows which do run on land
validation.
E.g. if a workflow fails on the PR but passes on land validation then we'd
use the successful result from the land validation.
"""
pr_checks = pr.get_checkrun_conclusions()
land_validation_checks = get_land_checkrun_conclusions(pr.org, pr.project, land_check_commit) if land_check_commit else {}
# Merge the two checks together. Land validation check results (if any) overwrite pr check results
merged_checks = {**pr_checks, **land_validation_checks} # explanation: https://stackoverflow.com/a/26853961/21539
return merged_checks
def filter_checks_with_lambda(
checks: Dict[str, WorkflowCheckState],
status_filter: Callable[[Optional[str]], bool]
) -> List[WorkflowCheckState]:
return [check for check in checks.values() if status_filter(check.status)]
def filter_pending_checks(checks: Dict[str, WorkflowCheckState]) -> List[WorkflowCheckState]:
return filter_checks_with_lambda(checks, lambda x: x is None)
def filter_failed_checks(checks: Dict[str, WorkflowCheckState]) -> List[WorkflowCheckState]:
return filter_checks_with_lambda(checks, lambda x: x in ["FAILURE", "STARTUP_FAILURE"])
def validate_revert(repo: GitRepo, pr: GitHubPR, *,
comment_id: Optional[int] = None) -> Tuple[str, str]:
comment = pr.get_last_comment() if comment_id is None else pr.get_comment_by_id(comment_id)
if comment.editor_login is not None:
raise PostCommentError("Don't want to revert based on edited command")
author_association = comment.author_association
author_login = comment.author_login
allowed_reverters = ["COLLABORATOR", "MEMBER", "OWNER"]
# For some reason, one can not be a member of private repo, only CONTRIBUTOR
if pr.is_base_repo_private():
allowed_reverters.append("CONTRIBUTOR")
if author_association not in allowed_reverters:
raise PostCommentError((
f"Will not revert as @{author_login} is not one of "
f"[{', '.join(allowed_reverters)}], but instead is {author_association}."
))
skip_internal_checks = can_skip_internal_checks(pr, comment_id)
# Raises exception if matching rule is not found, but ignores all status checks
find_matching_merge_rule(pr, repo, force=True, skip_internal_checks=skip_internal_checks)
commit_sha = pr.get_merge_commit()
if commit_sha is None:
commits = repo.commits_resolving_gh_pr(pr.pr_num)
if len(commits) == 0:
raise PostCommentError("Can't find any commits resolving PR")
commit_sha = commits[0]
msg = repo.commit_message(commit_sha)
rc = RE_DIFF_REV.search(msg)
if rc is not None and not can_skip_internal_checks:
raise PostCommentError(f"Can't revert PR that was landed via phabricator as {rc.group(1)}")
return (author_login, commit_sha)
def try_revert(repo: GitRepo, pr: GitHubPR, *,
dry_run: bool = False,
comment_id: Optional[int] = None,
reason: Optional[str] = None) -> None:
def post_comment(msg: str) -> None:
gh_post_pr_comment(pr.org, pr.project, pr.pr_num, msg, dry_run=dry_run)
try:
author_login, commit_sha = validate_revert(repo, pr, comment_id=comment_id)
except PostCommentError as e:
return post_comment(str(e))
revert_msg = f"\nReverted {pr.get_pr_url()} on behalf of {prefix_with_github_url(author_login)}"
revert_msg += f" due to {reason}\n" if reason is not None else "\n"
repo.checkout(pr.default_branch())
repo.revert(commit_sha)
msg = repo.commit_message("HEAD")
msg = re.sub(RE_PULL_REQUEST_RESOLVED, "", msg)
msg += revert_msg
repo.amend_commit_message(msg)
repo.push(pr.default_branch(), dry_run)
post_comment(f"@{pr.get_pr_creator_login()} your PR has been successfully reverted.")
if not dry_run:
pr.add_numbered_label("reverted")
gh_post_commit_comment(pr.org, pr.project, commit_sha, revert_msg)
def prefix_with_github_url(suffix_str: str) -> str:
return f"https://github.com/{suffix_str}"
def check_for_sev(org: str, project: str, force: bool) -> None:
if force:
return
response = cast(
Dict[str, Any],
fetch_json(
"https://api.github.com/search/issues",
params={"q": f'repo:{org}/{project} is:open is:issue label:"ci: sev"'},
),
)
if response["total_count"] != 0:
for item in response["items"]:
if "merge blocking" in item["body"].lower():
raise RuntimeError(
"Not merging any PRs at the moment because there is a "
+ "merge blocking https://github.com/pytorch/pytorch/labels/ci:%20sev issue open at: \n"
+ f"{item['html_url']}"
)
return
def validate_land_time_checks(org: str, project: str, commit: str) -> None:
checks = get_land_checkrun_conclusions(org, project, commit)
if len(checks) == 0:
raise MandatoryChecksMissingError("Refusing to merge as land check(s) are not yet run")
[pending_checks, failed_checks] = categorize_checks(checks, checks)
if len(failed_checks) > 0:
raise RuntimeError(f"Failed to merge; some land checks failed: {checks_to_str(failed_checks)}")
if len(pending_checks) > 0:
raise MandatoryChecksMissingError(f"Refusing to merge as land check(s) {checks_to_str(pending_checks)} are not yet run")
def has_label(labels: List[str], pattern: Pattern[str] = CIFLOW_LABEL) -> bool:
return len(list(filter(pattern.match, labels))) > 0
def categorize_checks(check_runs: Dict[str, WorkflowCheckState],
required_checks: Iterable[str]) -> Tuple[List[Tuple[str, Optional[str]]], List[Tuple[str, Optional[str]]]]:
pending_checks: List[Tuple[str, Optional[str]]] = []
failed_checks: List[Tuple[str, Optional[str]]] = []
for checkname in required_checks:
if checkname not in check_runs:
pending_checks.append((checkname, None))
elif check_runs[checkname].status is None:
pending_checks.append((checkname, check_runs[checkname].url))
elif (str(check_runs[checkname].status).upper() not in ['SUCCESS', 'SKIPPED', 'NEUTRAL']):
failed_checks.append((checkname, check_runs[checkname].url))
return (pending_checks, failed_checks)
def merge(pr_num: int, repo: GitRepo,
dry_run: bool = False,
force: bool = False,
comment_id: Optional[int] = None,
mandatory_only: bool = False,
on_green: bool = False,
land_checks: bool = False,
timeout_minutes: int = 400,
stale_pr_days: int = 3) -> None:
repo = GitRepo(get_git_repo_dir(), get_git_remote_name())
org, project = repo.gh_owner_and_name()
pr = GitHubPR(org, project, pr_num)
initial_commit_sha = pr.last_commit()['oid']
explainer = TryMergeExplainer(force, on_green, land_checks, pr.get_labels(), pr.pr_num, org, project)
on_green, land_checks = explainer.get_flags()
land_check_commit = None
check_for_sev(org, project, force)
if force or can_skip_internal_checks(pr, comment_id):
# do not wait for any pending signals if PR is closed as part of co-development process
gh_post_pr_comment(org, project, pr.pr_num, explainer.get_merge_message())
return pr.merge_into(repo, dry_run=dry_run, force=force, comment_id=comment_id)
if land_checks:
land_check_commit = pr.create_land_time_check_branch(repo, 'viable/strict', force=force, comment_id=comment_id)
gh_post_pr_comment(org, project, pr.pr_num, explainer.get_merge_message(land_check_commit))
if (datetime.utcnow() - pr.last_pushed_at()).days > stale_pr_days:
raise RuntimeError("This PR is too stale; the last push date was more than 3 days ago. Please rebase and try again.")
start_time = time.time()
last_exception = ''
elapsed_time = 0.0
while elapsed_time < timeout_minutes * 60:
check_for_sev(org, project, force)
current_time = time.time()
elapsed_time = current_time - start_time
print(f"Attempting merge of https://github.com/{org}/{project}/pull/{pr_num} ({elapsed_time / 60} minutes elapsed)")
pr = GitHubPR(org, project, pr_num)
if initial_commit_sha != pr.last_commit()['oid']:
raise RuntimeError("New commits were pushed while merging. Please rerun the merge command.")
try:
find_matching_merge_rule(pr, repo)
checks = get_combined_checks_from_pr_and_land_validation(pr, land_check_commit)
pending = filter_pending_checks(checks)
failing = filter_failed_checks(checks)
# HACK until GitHub will be better about surfacing those
startup_failures = filter_checks_with_lambda(checks, lambda status: status == "STARTUP_FAILURE")
if len(startup_failures) > 0:
raise RuntimeError(f"{len(failing)} STARTUP failures reported, please check workflows syntax! " +
' ,'.join(f"[{x.name}]({x.url})" for x in startup_failures[:5]))
# END of HACK
if (not mandatory_only and on_green) and len(failing) > 0:
raise RuntimeError(f"{len(failing)} additional jobs have failed, first few of them are: " +
' ,'.join(f"[{x.name}]({x.url})" for x in failing[:5]))
if (not mandatory_only and on_green) and len(pending) > 0:
raise MandatoryChecksMissingError(f"Still waiting for {len(pending)} additional jobs to finish, " +
f"first few of them are: {' ,'.join(x.name for x in pending[:5])}")
if land_checks and land_check_commit is not None:
validate_land_time_checks(org, project, land_check_commit)
return pr.merge_into(repo, dry_run=dry_run, force=force, comment_id=comment_id, land_check_commit=land_check_commit)
except MandatoryChecksMissingError as ex:
last_exception = str(ex)
print(f"Merge of https://github.com/{org}/{project}/pull/{pr_num} failed due to: {ex}. Retrying in 5 min")
time.sleep(5 * 60)
# Finally report timeout back
msg = f"Merged timed out after {timeout_minutes} minutes. Please contact the pytorch_dev_infra team."
msg += f"The last exception was: {last_exception}"
if not dry_run:
gh_add_labels(org, project, pr_num, ["land-failed"])
raise RuntimeError(msg)
def main() -> None:
args = parse_args()
repo = GitRepo(get_git_repo_dir(), get_git_remote_name())
org, project = repo.gh_owner_and_name()
pr = GitHubPR(org, project, args.pr_num)
def handle_exception(e: Exception, msg: str = "Merge failed") -> None:
msg += f"\nReason: {e}"
run_url = os.getenv("GH_RUN_URL")
if run_url is not None:
msg += f"\nRaised by [workflow job]({run_url})"
if args.land_checks:
msg += get_land_check_troubleshooting_message()
gh_post_pr_comment(org, project, args.pr_num, msg, dry_run=args.dry_run)
import traceback
traceback.print_exc()
if args.revert:
try:
gh_post_pr_comment(org, project, args.pr_num, get_revert_message(org, project, pr.pr_num), args.dry_run)
try_revert(repo, pr, dry_run=args.dry_run, comment_id=args.comment_id, reason=args.reason)
except Exception as e:
handle_exception(e, f"Reverting PR {args.pr_num} failed")
return
if pr.is_closed():
gh_post_pr_comment(org, project, args.pr_num, f"Can't merge closed PR #{args.pr_num}", dry_run=args.dry_run)
return
if pr.is_cross_repo() and pr.is_ghstack_pr():
gh_post_pr_comment(org, project, args.pr_num, "Cross-repo ghstack merges are not supported", dry_run=args.dry_run)
return
try:
merge(args.pr_num, repo,
dry_run=args.dry_run,
force=args.force,
comment_id=args.comment_id,
on_green=args.on_green,
mandatory_only=args.on_mandatory,
land_checks=args.land_checks)
except Exception as e:
handle_exception(e)
if __name__ == "__main__":
main()
|
import os
import re
from typing import List, Pattern, Tuple, Optional
BOT_COMMANDS_WIKI = "https://github.com/pytorch/pytorch/wiki/Bot-commands"
CIFLOW_LABEL = re.compile(r"^ciflow/.+")
CIFLOW_TRUNK_LABEL = re.compile(r"^ciflow/trunk")
OFFICE_HOURS_LINK = "https://github.com/pytorch/pytorch/wiki/Dev-Infra-Office-Hours"
CONTACT_US = f"Please reach out to the [PyTorch DevX Team]({OFFICE_HOURS_LINK}) with feedback or questions!"
ALTERNATIVES = (
"If this is not the intended behavior, feel free to use some "
+ f"of the other merge options in the [wiki]({BOT_COMMANDS_WIKI})."
)
LAND_CHECK_ROLLOUT = "https://github.com/pytorch/test-infra/blob/main/torchci/lib/bot/rolloutUtils.ts#L1-L34"
def has_label(labels: List[str], pattern: Pattern[str] = CIFLOW_LABEL) -> bool:
return len(list(filter(pattern.match, labels))) > 0
class TryMergeExplainer(object):
force: bool
on_green: bool
land_checks: bool
labels: List[str]
pr_num: int
org: str
project: str
has_trunk_label: bool
has_ciflow_label: bool
def __init__(
self,
force: bool,
on_green: bool,
land_checks: bool,
labels: List[str],
pr_num: int,
org: str,
project: str,
):
self.force = force
self.on_green = on_green
self.land_checks = land_checks
self.labels = labels
self.pr_num = pr_num
self.org = org
self.project = project
self.get_flags()
def get_flags(self) -> Tuple[bool, bool]:
self.has_trunk_label = has_label(self.labels, CIFLOW_TRUNK_LABEL)
self.has_ciflow_label = has_label(self.labels, CIFLOW_LABEL)
should_check_land_branch = self.land_checks and not self.has_trunk_label
should_check_green = self.on_green or self.has_ciflow_label
return (should_check_green, should_check_land_branch)
def _get_flag_msg(self) -> str:
if self.force:
return " the force (-f) flag."
elif self.on_green:
return " the green (-g) flag."
elif self.land_checks:
return (
" the land checks (-l) flag."
+ " If you did not specify this flag yourself, "
+ f" you are likely enrolled in the [land checks rollout]({LAND_CHECK_ROLLOUT})."
)
else:
return "out a flag."
def _get_land_check_progress(self, commit: Optional[str]) -> str:
if commit is not None:
return (
" and land check "
+ f"progress [here](https://hud.pytorch.org/{self.org}/{self.project}/commit/{commit})"
)
else:
return ""
def _get_flag_explanation_message(self) -> str:
if self.force:
return "This means your change will be merged **immediately**, bypassing any CI checks (ETA: 1-5 minutes)."
elif self.on_green:
return "This means that your change will be merged once all checks on your PR have passed (ETA: 0-4 Hours)."
elif self.land_checks:
if self.has_trunk_label:
land_check_msg_suffix = "have passed since you have added the `ciflow/trunk` label to your PR (ETA 0-4 Hours)."
else:
land_check_msg_suffix = (
"and the land checks have passed (**ETA 4 Hours**). "
)
land_check_msg_suffix += "If you need to coordinate lands between different changes and cannot risk a land race, "
land_check_msg_suffix += "please add the `ciflow/trunk` label to your PR and wait for signal to complete, "
land_check_msg_suffix += "and then land your changes in proper order."
land_check_msg_suffix += (
" Having `trunk`, `pull`, and `Lint` pre-run on a "
)
land_check_msg_suffix += (
"PR will bypass land checks and the ETA should be immediate."
)
return (
"This means that your change will be merged once all checks on your PR "
+ land_check_msg_suffix
)
else:
return "This means that your change will be merged once all checks on your PR have passed (ETA: 0-4 Hours)."
def get_merge_message(self, commit: Optional[str] = None) -> str:
message_prefix = "@pytorchbot successfully started a merge job."
progress_links = f"Check the current status [here]({os.getenv('GH_RUN_URL')}){self._get_land_check_progress(commit)}."
flag_message = f"The merge job was triggered with{self._get_flag_msg()}"
explanation_message = self._get_flag_explanation_message()
msg = message_prefix + " "
msg += progress_links + "\n"
msg += flag_message + " "
msg += explanation_message + " "
msg += ALTERNATIVES + "\n"
msg += CONTACT_US
return msg
def get_revert_message(org: str, project: str, pr_num: int) -> str:
msg = (
"@pytorchbot successfully started a revert job."
+ f" Check the current status [here]({os.getenv('GH_RUN_URL')}).\n"
)
msg += CONTACT_US
return msg
def get_land_check_troubleshooting_message() -> str:
return (
" If you believe this is an error, you can use the old behavior with `@pytorchbot merge -g`"
+ " (optionally with the `ciflow/trunk` to get land checks)"
+ ' or use `@pytorchbot merge -f "some reason here"`.'
+ f" For more information, see the [bot wiki]({BOT_COMMANDS_WIKI}). \n"
+ CONTACT_US
)
|
"""GitHub Utilities"""
import json
import os
from dataclasses import dataclass
from typing import Any, Callable, cast, Dict, List, Optional
from urllib.error import HTTPError
from urllib.parse import quote
from urllib.request import Request, urlopen
@dataclass
class GitHubComment:
body_text: str
created_at: str
author_login: str
author_association: str
editor_login: Optional[str]
database_id: int
url: str
def gh_fetch_url(
url: str,
*,
headers: Optional[Dict[str, str]] = None,
data: Optional[Dict[str, Any]] = None,
method: Optional[str] = None,
reader: Callable[[Any], Any] = lambda x: x.read(),
) -> Any:
if headers is None:
headers = {}
token = os.environ.get("GITHUB_TOKEN")
if token is not None and url.startswith("https://api.github.com/"):
headers["Authorization"] = f"token {token}"
data_ = json.dumps(data).encode() if data is not None else None
try:
with urlopen(Request(url, headers=headers, data=data_, method=method)) as conn:
return reader(conn)
except HTTPError as err:
if err.code == 403 and all(
key in err.headers for key in ["X-RateLimit-Limit", "X-RateLimit-Used"]
):
print(
f"""Rate limit exceeded:
Used: {err.headers['X-RateLimit-Used']}
Limit: {err.headers['X-RateLimit-Limit']}
Remaining: {err.headers['X-RateLimit-Remaining']}
Resets at: {err.headers['x-RateLimit-Reset']}"""
)
raise
def gh_fetch_json(
url: str,
params: Optional[Dict[str, Any]] = None,
data: Optional[Dict[str, Any]] = None,
method: Optional[str] = None,
) -> List[Dict[str, Any]]:
headers = {"Accept": "application/vnd.github.v3+json"}
if params is not None and len(params) > 0:
url += "?" + "&".join(
f"{name}={quote(str(val))}" for name, val in params.items()
)
return cast(
List[Dict[str, Any]],
gh_fetch_url(url, headers=headers, data=data, reader=json.load, method=method),
)
def _gh_fetch_json_any(
url: str,
params: Optional[Dict[str, Any]] = None,
data: Optional[Dict[str, Any]] = None,
) -> Any:
headers = {"Accept": "application/vnd.github.v3+json"}
if params is not None and len(params) > 0:
url += "?" + "&".join(
f"{name}={quote(str(val))}" for name, val in params.items()
)
return gh_fetch_url(url, headers=headers, data=data, reader=json.load)
def gh_fetch_json_list(
url: str,
params: Optional[Dict[str, Any]] = None,
data: Optional[Dict[str, Any]] = None,
) -> List[Dict[str, Any]]:
return cast(List[Dict[str, Any]], _gh_fetch_json_any(url, params, data))
def gh_fetch_json_dict(
url: str,
params: Optional[Dict[str, Any]] = None,
data: Optional[Dict[str, Any]] = None,
) -> Dict[str, Any]:
return cast(Dict[str, Any], _gh_fetch_json_any(url, params, data))
def _gh_post_comment(
url: str, comment: str, dry_run: bool = False
) -> List[Dict[str, Any]]:
if dry_run:
print(comment)
return []
return gh_fetch_json_list(url, data={"body": comment})
def gh_post_pr_comment(
org: str, repo: str, pr_num: int, comment: str, dry_run: bool = False
) -> List[Dict[str, Any]]:
return _gh_post_comment(
f"https://api.github.com/repos/{org}/{repo}/issues/{pr_num}/comments",
comment,
dry_run,
)
def gh_post_commit_comment(
org: str, repo: str, sha: str, comment: str, dry_run: bool = False
) -> List[Dict[str, Any]]:
return _gh_post_comment(
f"https://api.github.com/repos/{org}/{repo}/commits/{sha}/comments",
comment,
dry_run,
)
def gh_delete_comment(org: str, repo: str, comment_id: int) -> None:
url = f"https://api.github.com/repos/{org}/{repo}/issues/comments/{comment_id}"
gh_fetch_url(url, method="DELETE")
|
#!/usr/bin/env python3
"""Check whether a PR has required labels."""
from typing import Any
from github_utils import gh_delete_comment, gh_post_pr_comment
from gitutils import get_git_remote_name, get_git_repo_dir, GitRepo
from label_utils import has_required_labels, is_label_err_comment, LABEL_ERR_MSG
from trymerge import GitHubPR
def delete_all_label_err_comments(pr: "GitHubPR") -> None:
for comment in pr.get_comments():
if is_label_err_comment(comment):
gh_delete_comment(pr.org, pr.project, comment.database_id)
def add_label_err_comment(pr: "GitHubPR") -> None:
# Only make a comment if one doesn't exist already
if not any(is_label_err_comment(comment) for comment in pr.get_comments()):
gh_post_pr_comment(pr.org, pr.project, pr.pr_num, LABEL_ERR_MSG)
def parse_args() -> Any:
from argparse import ArgumentParser
parser = ArgumentParser("Check PR labels")
parser.add_argument("pr_num", type=int)
return parser.parse_args()
def main() -> None:
args = parse_args()
repo = GitRepo(get_git_repo_dir(), get_git_remote_name())
org, project = repo.gh_owner_and_name()
pr = GitHubPR(org, project, args.pr_num)
try:
if not has_required_labels(pr):
print(LABEL_ERR_MSG)
add_label_err_comment(pr)
else:
delete_all_label_err_comments(pr)
except Exception as e:
pass
exit(0)
if __name__ == "__main__":
main()
|
#!/usr/bin/env python3
import os
import re
import tempfile
from collections import defaultdict
from datetime import datetime
from typing import cast, Any, Dict, Iterator, List, Optional, Tuple, Union
RE_GITHUB_URL_MATCH = re.compile("^https://.*@?github.com/(.+)/(.+)$")
def get_git_remote_name() -> str:
return os.getenv("GIT_REMOTE_NAME", "origin")
def get_git_repo_dir() -> str:
from pathlib import Path
return os.getenv("GIT_REPO_DIR", str(Path(__file__).resolve().parent.parent.parent))
def fuzzy_list_to_dict(items: List[Tuple[str, str]]) -> Dict[str, List[str]]:
"""
Converts list to dict preserving elements with duplicate keys
"""
rc: Dict[str, List[str]] = defaultdict(lambda: [])
for (key, val) in items:
rc[key].append(val)
return dict(rc)
def _check_output(items: List[str], encoding: str = "utf-8") -> str:
from subprocess import check_output, CalledProcessError, STDOUT
try:
return check_output(items, stderr=STDOUT).decode(encoding)
except CalledProcessError as e:
msg = f"Command `{' '.join(e.cmd)}` returned non-zero exit code {e.returncode}"
stdout = e.stdout.decode(encoding) if e.stdout is not None else ""
stderr = e.stderr.decode(encoding) if e.stderr is not None else ""
if len(stderr) == 0:
msg += f"\n```\n{stdout}```"
else:
msg += f"\nstdout:\n```\n{stdout}```\nstderr:\n```\n{stderr}```"
raise RuntimeError(msg) from e
class GitCommit:
commit_hash: str
title: str
body: str
author: str
author_date: datetime
commit_date: Optional[datetime]
def __init__(self,
commit_hash: str,
author: str,
author_date: datetime,
title: str,
body: str,
commit_date: Optional[datetime] = None) -> None:
self.commit_hash = commit_hash
self.author = author
self.author_date = author_date
self.commit_date = commit_date
self.title = title
self.body = body
def __repr__(self) -> str:
return f"{self.title} ({self.commit_hash})"
def __contains__(self, item: Any) -> bool:
return item in self.body or item in self.title
def parse_fuller_format(lines: Union[str, List[str]]) -> GitCommit:
"""
Expect commit message generated using `--format=fuller --date=unix` format, i.e.:
commit <sha1>
Author: <author>
AuthorDate: <author date>
Commit: <committer>
CommitDate: <committer date>
<title line>
<full commit message>
"""
if isinstance(lines, str):
lines = lines.split("\n")
# TODO: Handle merge commits correctly
if len(lines) > 1 and lines[1].startswith("Merge:"):
del lines[1]
assert len(lines) > 7
assert lines[0].startswith("commit")
assert lines[1].startswith("Author: ")
assert lines[2].startswith("AuthorDate: ")
assert lines[3].startswith("Commit: ")
assert lines[4].startswith("CommitDate: ")
assert len(lines[5]) == 0
return GitCommit(commit_hash=lines[0].split()[1].strip(),
author=lines[1].split(":", 1)[1].strip(),
author_date=datetime.fromtimestamp(int(lines[2].split(":", 1)[1].strip())),
commit_date=datetime.fromtimestamp(int(lines[4].split(":", 1)[1].strip())),
title=lines[6].strip(),
body="\n".join(lines[7:]),
)
class GitRepo:
def __init__(self, path: str, remote: str = "origin", debug: bool = False) -> None:
self.repo_dir = path
self.remote = remote
self.debug = debug
def _run_git(self, *args: Any) -> str:
if self.debug:
print(f"+ git -C {self.repo_dir} {' '.join(args)}")
return _check_output(["git", "-C", self.repo_dir] + list(args))
def revlist(self, revision_range: str) -> List[str]:
rc = self._run_git("rev-list", revision_range, "--", ".").strip()
return rc.split("\n") if len(rc) > 0 else []
def current_branch(self) -> str:
return self._run_git("symbolic-ref", "--short", "HEAD").strip()
def checkout(self, branch: str) -> None:
self._run_git("checkout", branch)
def fetch(self, ref: Optional[str] = None, branch: Optional[str] = None) -> None:
if branch is None and ref is None:
self._run_git("fetch", self.remote)
elif branch is None:
self._run_git("fetch", self.remote, ref)
else:
self._run_git("fetch", self.remote, f"{ref}:{branch}")
def show_ref(self, name: str) -> str:
refs = self._run_git('show-ref', '-s', name).strip().split('\n')
if not all(refs[i] == refs[0] for i in range(1, len(refs))):
raise RuntimeError(f"referce {name} is ambigous")
return refs[0]
def rev_parse(self, name: str) -> str:
return self._run_git('rev-parse', '--verify', name).strip()
def get_merge_base(self, from_ref: str, to_ref: str) -> str:
return self._run_git('merge-base', from_ref, to_ref).strip()
def patch_id(self, ref: Union[str, List[str]]) -> List[Tuple[str, str]]:
is_list = isinstance(ref, list)
if is_list:
if len(ref) == 0:
return []
ref = " ".join(ref)
rc = _check_output(['sh', '-c', f'git -C {self.repo_dir} show {ref}|git patch-id --stable']).strip()
return [cast(Tuple[str, str], x.split(" ", 1)) for x in rc.split("\n")]
def commits_resolving_gh_pr(self, pr_num: int) -> List[str]:
owner, name = self.gh_owner_and_name()
msg = f"Pull Request resolved: https://github.com/{owner}/{name}/pull/{pr_num}"
rc = self._run_git('log', '--format=%H', '--grep', msg).strip()
return rc.split("\n") if len(rc) > 0 else []
def get_commit(self, ref: str) -> GitCommit:
return parse_fuller_format(self._run_git('show', '--format=fuller', '--date=unix', '--shortstat', ref))
def cherry_pick(self, ref: str) -> None:
self._run_git('cherry-pick', '-x', ref)
def revert(self, ref: str) -> None:
self._run_git("revert", "--no-edit", ref)
def compute_branch_diffs(self, from_branch: str, to_branch: str) -> Tuple[List[str], List[str]]:
"""
Returns list of commmits that are missing in each other branch since their merge base
Might be slow if merge base is between two branches is pretty far off
"""
from_ref = self.rev_parse(from_branch)
to_ref = self.rev_parse(to_branch)
merge_base = self.get_merge_base(from_ref, to_ref)
from_commits = self.revlist(f'{merge_base}..{from_ref}')
to_commits = self.revlist(f'{merge_base}..{to_ref}')
from_ids = fuzzy_list_to_dict(self.patch_id(from_commits))
to_ids = fuzzy_list_to_dict(self.patch_id(to_commits))
for patch_id in set(from_ids).intersection(set(to_ids)):
from_values = from_ids[patch_id]
to_values = to_ids[patch_id]
if len(from_values) != len(to_values):
# Eliminate duplicate commits+reverts from the list
while len(from_values) > 0 and len(to_values) > 0:
frc = self.get_commit(from_values.pop())
toc = self.get_commit(to_values.pop())
# FRC branch might have PR number added to the title
if frc.title != toc.title or frc.author_date != toc.author_date:
# HACK: Same commit were merged, reverted and landed again
# which creates a tracking problem
if (
"pytorch/pytorch" not in self.remote_url() or
frc.commit_hash not in {"0a6a1b27a464ba5be5f587cce2ee12ab8c504dbf",
"6d0f4a1d545a8f161df459e8d4ccafd4b9017dbe",
"edf909e58f06150f7be41da2f98a3b9de3167bca",
"a58c6aea5a0c9f8759a4154e46f544c8b03b8db1",
"7106d216c29ca16a3504aa2bedad948ebcf4abc2"}
):
raise RuntimeError(f"Unexpected differences between {frc} and {toc}")
from_commits.remove(frc.commit_hash)
to_commits.remove(toc.commit_hash)
continue
for commit in from_values:
from_commits.remove(commit)
for commit in to_values:
to_commits.remove(commit)
# Another HACK: Patch-id is not stable for commits with binary files or for big changes across commits
# I.e. cherry-picking those from one branch into another will change patchid
if "pytorch/pytorch" in self.remote_url():
for excluded_commit in {"8e09e20c1dafcdbdb45c2d1574da68a32e54a3a5",
"5f37e5c2a39c3acb776756a17730b865f0953432",
"b5222584e6d6990c6585981a936defd1af14c0ba",
"84d9a2e42d5ed30ec3b8b4140c38dd83abbce88d",
"f211ec90a6cdc8a2a5795478b5b5c8d7d7896f7e"}:
if excluded_commit in from_commits:
from_commits.remove(excluded_commit)
return (from_commits, to_commits)
def cherry_pick_commits(self, from_branch: str, to_branch: str) -> None:
orig_branch = self.current_branch()
self.checkout(to_branch)
from_commits, to_commits = self.compute_branch_diffs(from_branch, to_branch)
if len(from_commits) == 0:
print("Nothing to do")
self.checkout(orig_branch)
return
for commit in reversed(from_commits):
print(f"Cherry picking commit {commit}")
self.cherry_pick(commit)
self.checkout(orig_branch)
def push(self, branch: str, dry_run: bool, retry: int = 3) -> None:
for cnt in range(retry):
try:
if dry_run:
self._run_git("push", "--dry-run", self.remote, branch)
else:
self._run_git("push", self.remote, branch)
except RuntimeError as e:
print(f"{cnt} push attempt failed with {e}")
self.fetch()
self._run_git("rebase", f"{self.remote}/{branch}")
def head_hash(self) -> str:
return self._run_git("show-ref", "--hash", "HEAD").strip()
def remote_url(self) -> str:
return self._run_git("remote", "get-url", self.remote)
def gh_owner_and_name(self) -> Tuple[str, str]:
url = os.getenv("GIT_REMOTE_URL", None)
if url is None:
url = self.remote_url()
rc = RE_GITHUB_URL_MATCH.match(url)
if rc is None:
raise RuntimeError(f"Unexpected url format {url}")
return cast(Tuple[str, str], rc.groups())
def commit_message(self, ref: str) -> str:
return self._run_git("log", "-1", "--format=%B", ref)
def amend_commit_message(self, msg: str) -> None:
self._run_git("commit", "--amend", "-m", msg)
def clone_repo(username: str, password: str, org: str, project: str) -> GitRepo:
path = tempfile.mkdtemp()
_check_output(['git', 'clone', f'https://{username}:{password}@github.com/{org}/{project}', path]).strip()
return GitRepo(path=path)
class PeekableIterator(Iterator[str]):
def __init__(self, val: str) -> None:
self._val = val
self._idx = -1
def peek(self) -> Optional[str]:
if self._idx + 1 >= len(self._val):
return None
return self._val[self._idx + 1]
def __iter__(self) -> "PeekableIterator":
return self
def __next__(self) -> str:
rc = self.peek()
if rc is None:
raise StopIteration
self._idx += 1
return rc
def patterns_to_regex(allowed_patterns: List[str]) -> Any:
"""
pattern is glob-like, i.e. the only special sequences it has are:
- ? - matches single character
- * - matches any non-folder separator characters
- ** - matches any characters
Assuming that patterns are free of braces and backslashes
the only character that needs to be escaped are dot and plus
"""
rc = "("
for idx, pattern in enumerate(allowed_patterns):
if idx > 0:
rc += "|"
pattern_ = PeekableIterator(pattern)
assert not any(c in pattern for c in "{}()[]\\")
for c in pattern_:
if c == ".":
rc += "\\."
elif c == "+":
rc += "\\+"
elif c == "*":
if pattern_.peek() == "*":
next(pattern_)
rc += ".+"
else:
rc += "[^/]+"
else:
rc += c
rc += ")"
return re.compile(rc)
|
#!/usr/bin/env python3
from gitutils import get_git_repo_dir, GitRepo
from typing import Any
def parse_args() -> Any:
from argparse import ArgumentParser
parser = ArgumentParser("Merge PR/branch into default branch")
parser.add_argument("--sync-branch", default="sync")
parser.add_argument("--default-branch", type=str, default="main")
parser.add_argument("--dry-run", action="store_true")
parser.add_argument("--debug", action="store_true")
return parser.parse_args()
def main() -> None:
args = parse_args()
repo = GitRepo(get_git_repo_dir(), debug=args.debug)
repo.cherry_pick_commits(args.sync_branch, args.default_branch)
repo.push(args.default_branch, args.dry_run)
if __name__ == '__main__':
main()
|
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