ID
int64 1
1.96k
| Split
stringclasses 1
value | Domain
stringclasses 4
values | SubDomain
stringclasses 24
values | Format
stringclasses 1
value | Tag
stringclasses 2
values | Language
stringclasses 1
value | Question
stringlengths 15
717
| A
stringlengths 1
292
| B
stringlengths 1
232
| C
stringlengths 1
217
| D
stringlengths 1
192
| Answer
stringclasses 4
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stringlengths 21
1.43k
⌀ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
657
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
The refresh of DRAM is done in units of ( ).
|
storage unit
|
row
|
column
|
Storage Word
|
B
| null |
658
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
Which of the following refresh methods for dynamic RAM does not involve dead time ( )?
|
Focused Refresh
|
Distributed Refresh
|
Asynchronous Refresh
|
None of them are correct.
|
B
| null |
659
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
A DRAM chip that employs address multiplexing technology has a capacity of 1024x8 bits. Excluding the power and ground pins, the minimum number of pins required for this chip is (with two control lines for read/write)().
|
16
|
17
|
19
|
21
|
B
| null |
660
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
Among the following types of memory, ( ) is volatile memory.
|
Cache
|
EPROM
|
Flash memory
|
CD-ROM
|
A
| null |
661
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
The word length of a certain computer is 16 bits, with a memory capacity of 256KB, and the CPU addresses by word. Its addressing range is ( ).
|
0 to 2^19-1
|
0 to (2^20 - 1)
|
0 to 2^18-1
|
0 to 2^17-1
|
D
| null |
662
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
16 pieces of 2Kx4 bit memory can be designed as a ( ) storage capacity of 16-bit memory.
|
16K
|
32K
|
8K
|
2K
|
C
| null |
663
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
If the memory address range is 4000H~43FFH, and each storage unit can store a 16-bit binary number, this memory area is composed of 4 memory chips, the capacity of the memory chips used to construct this memory is ( ).
|
512x16bit
|
256x8bit
|
256x16bit
|
1024x8bit
|
C
| null |
664
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
When accessing the Cache system fails, it is common that not only does the main memory transfer information to the CPU, but it also needs to write the information into the Cache. During this process, the data width for transferring and writing information is each ( ).
|
block, page
|
character, character
|
character, block
|
block, block
|
C
| null |
665
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
The foundation of the virtual storage management system is the principle of locality of program access, the basic meaning of which is()
|
During the execution of a program, the program's access to the main memory is uneven.
|
Spatial locality
|
Temporal locality
|
Sequential execution of code
|
A
| null |
666
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
The common management methods for virtual memory include segmentation, paging, and segmented paging. The correct description regarding the units they use when exchanging information with the main memory is:()
|
Segmentation uses "pages".
|
Paging uses "blocks".
|
Segmentation and paging use "segments" and "pages".
|
Both paging and segmented paging only use "pages".
|
D
| null |
667
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Knowledge
|
English
|
Among the following statements about virtual memory, the correct one is ( ).
|
Transparent to application programmers, opaque to system programmers.
|
Opaque to application programmers, transparent to system programmers.
|
Opaque to both application programmers and system programmers
|
Transparent to both application programmers and system programmers.
|
A
| null |
668
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
Assuming a machine word length of 32 bits and a memory capacity of 16MB, the CPU addresses by half-word, the number of addressable units is ( ).
|
2^24
|
2^23
|
2^22
|
2^21
|
B
|
16MB = 2^24B, and since the word length is 32 bits, the number of addressable units when addressing by half-word (2B) is 2^24B/2B = 2^23.
|
669
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
If a memory has a storage cycle of 250ns and reads out 16 bits each time, the data transfer rate of the memory is ( ).
|
4x10^6 B/s
|
4MB/s
|
8x10^6 B/s
|
8x2^20 B/s
|
C
|
The data transfer rate is 2B / (250 x 10^{-9}s), which is 8x10^6B/s.
|
670
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
In a multi-level storage hierarchy, the role of the "Cache-Main Memory" structure is to address the problem of ( ).
|
Insufficient main memory capacity
|
The speed mismatch between main memory and auxiliary memory.
|
Mismatch between auxiliary storage and CPU speed
|
Mismatch between main memory and CPU speed
|
D
|
The contents in the Cache are merely partial replicas of the main memory, thus the "Cache-Main Memory" structure does not increase the capacity of the main memory. The purpose is to address the mismatch in speed between the main memory and the CPU.
|
671
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
In a two-level storage hierarchy consisting of Cache and main memory, where Cache and main memory are accessed simultaneously, the access time for Cache is 100ns, and the access time for main memory is 1000ns. Assuming simultaneous access to Cache and main memory, if the desired effective (average) access time is not to exceed 115% of the Cache access time, then the minimum hit rate for the Cache should be ( ).
|
0.9
|
0.98
|
0.95
|
0.99
|
D
|
The hit rate is at least 99%.
|
672
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
The following are descriptions of DRAM and SRAM memory chips: I. DRAM chips have higher integration than SRAM chips II. DRAM chips are more expensive than SRAM chips III. DRAM chips are faster than SRAM chips IV. DRAM chips require refreshing during operation, while SRAM chips do not require refreshing. Usually, the incorrect statement is ( ).
|
Type I and Type II
|
II and III
|
III and IV
|
I and IV
|
B
|
DRAM has a higher integration level than SRAM, and SRAM is faster than DRAM; therefore, statements II and III are incorrect.
|
673
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
Given that the storage cycle of a single memory module is 110ns and the bus transfer cycle is 10ns, when using a multi-module memory with low-order interleaved addressing, the number of memory modules should be ( ).
|
Less than 11
|
equals 11
|
Greater than 11
|
greater than or equal to 11
|
D
|
To ensure that the last access operation has been completed when a certain storage element is started for the second time, the number of storage elements should be greater than or equal to 11 (110ns/10ns = 11).
|
674
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
Among the following statements, the correct ones are (I. High-order interleaved memory can well satisfy the principle of locality of programs II. High-order four-way interleaved memory may access 4 modules consecutively within one memory cycle III. Dual-port memory can access the same area and the same cell simultaneously IV. In dual-port memory, when the address codes of the two ports are the same, a conflict will inevitably occur.
|
I, III
|
II, III
|
II, III, and IV
|
III, IV
|
B
|
High-order interleaved memory stores words consecutively within a single memory, which does not adhere to the principle of locality of reference; whereas low-order interleaved memory stores words in an interleaved manner, which well satisfies the principle of locality of reference, I is incorrect. Although high-order four-way interleaved memory cannot satisfy the need for consecutive reading of programs, it is still possible to read out four words at once whose addresses differ by the capacity of one memory bank, but the probability of such reading is lower, II is correct. Dual-port memory has two sets of independent read/write interfaces, each with its own address register and decoding circuitry, allowing simultaneous access to the same range and the same cell, III is correct. When both ports read from the same cell at the same time, there will be no conflict, IV is incorrect.
|
675
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
To construct a 64Kx8 bit memory using memory chips with a storage capacity of 16Kx1 bit, the expansion in the word direction and bit direction is respectively ( ) times.
|
4,2
|
8,4
|
2,4
|
4,8
|
D
|
The word direction has been expanded by a factor of 4, and the bit direction has been expanded by a factor of 8.
|
676
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
When the chip select address is 111, selecting a 32Kx16 bit memory chip to work, the starting and ending addresses of this chip in the memory are respectively ( ).
|
00000H, 01000H
|
38000H, 3FFFFH
|
3800H, 3FFFH
|
0000H, 0100H
|
B
|
A 32Kx16-bit memory chip has 15 address lines (internal address) and a 3-bit chip select address, making a total of 18 address bits. Given the chip select address 111, the starting address is 111000000000000000=38000H, and the ending address is 111111111111111111=3FFFFH.
|
677
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
The rotational speed of a disk is 7200 RPM, with 160 sectors per track, and each sector contains 512 bytes. Therefore, under ideal conditions, its data transfer rate is ( ).
|
7200x160KB/s
|
7200KB/s
|
9600KB/s
|
19200KB/s
|
C
|
The rotational speed of the disk is 7200 RPM (revolutions per minute) = 120 RPM (revolutions per second), passing through 160 sectors per revolution, with each sector being 512B. Therefore, the data transfer rate is 120 x 160 x 512 / 1024 = 9600KB/s.
|
678
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
Among the following statements about disks, the incorrect one is ( ).
|
Essentially, a USB flash drive (flash memory) is a type of read-only memory.
|
RAID technology can increase the magnetic recording density and disk utilization of hard drives.
|
The unformatted capacity of a hard drive is greater than the actual capacity after formatting.
|
When calculating the access time of a disk, the "seek time" and "rotational latency" are often taken as their average values.
|
B
|
Flash memory evolved from programmable read-only memory (PROM), and is essentially read-only memory. RAID combines multiple physical disks to appear as a single logical disk, which does not affect magnetic recording density, nor can it increase disk utilization.
|
679
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
A virtual memory system adopts a paging memory management and uses the LRU page replacement algorithm. Consider the following page access address stream (each access is completed within one time unit): 18178272183821317137. Assuming the memory capacity is 4 pages and initially empty, the page fault rate is ( ).
|
0.3
|
0.05
|
0.015
|
0.15
|
A
|
Page fault rate = 6/20 = 30%
|
680
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
The capacity of the Cache in a 32-bit computer is 16KB, and the size of a Cache line is 16B. If the main memory and Cache address mapping use direct mapping, then the address in the Cache where the cell with the main memory address 0x1234E8F8 is loaded is ( ).
|
00010001001101
|
01000100011010
|
10100011111000
|
11010011101000
|
C
|
The direct-mapped method uses the lower 14 bits as the Cache address.
|
681
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
In Cache, commonly used replacement strategies include Random (RAND), First In First Out (FIFO), and Least Recently Used (LRU). Among these, the one related to the principle of locality is ( ).
|
Random Method (RAND)
|
First-In, First-Out method (FIFO)
|
Least Recently Used (LRU)
|
None of them
|
C
|
The LRU algorithm selects the least recently used memory block based on the principle of locality of reference.
|
682
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
Assuming the main memory address is 32 bits, byte-addressable, and the mapping between main memory and Cache is fully associative, with a main memory block size of one word, each word being 32 bits, using write-back policy and random replacement strategy, then a Cache that can store 32K words of data should have a total capacity of at least ( ) bits.
|
1536K
|
1568K
|
2016K
|
2048K
|
D
|
The total capacity calculated based on various parameters is 2048K bit.
|
683
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
Assuming the main memory is byte-addressable, the Cache has a total of 64 lines, uses a 4-way set associative mapping scheme, and the main memory block size is 32 bytes, with all numbering starting from 0. The Cache set number for the main memory block containing storage cell number 2593 is ( ).
|
1
|
17
|
34
|
81
|
A
|
The cache set number for the main memory block where storage cell number 2593 is located is 1.
|
684
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
Assuming the process for the CPU to read data through the memory bus is: sending the address and read command requires 1 clock cycle, the memory preparing one piece of data requires 8 clock cycles, and each data transfer on the bus requires 1 clock cycle. If the block size exchanged between main memory and Cache is 64B, and both the access width and bus width are 8B, then the minimum cache miss penalty is () clock cycles.
|
64
|
72
|
80
|
160
|
C
|
A single cache miss requires fetching a cache block from the main memory, taking a total of 80 clock cycles.
|
685
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
Assuming a multi-module interleaved memory organization is used, with memory chips and buses supporting burst transfer, the process of the CPU reading data through the memory bus is as follows: sending the initial address and read command requires 1 clock cycle, the memory takes 8 clock cycles to prepare the first piece of data, and subsequently, 1 piece of data is transferred on the bus per clock cycle, with a continuous transfer of 8 pieces of data (i.e., burst length is 8). If the size of the main memory block exchanged between the main memory and Cache is 64B, and both the access width and bus width are 8B, then the minimum cache miss penalty is ( ) clock cycles.
|
17
|
20
|
33
|
80
|
A
|
A single cache miss requires reading a cache block (64B) from the main memory. Each burst transfer bus transaction can read 64B, so only one burst transfer bus transaction is needed, taking a total of 17 clock cycles.
|
686
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
In virtual memory, address mapping is performed by ( ).
|
Programmer
|
Compiler
|
Loader
|
Operating System
|
D
|
In virtual memory, address mapping is performed by the operating system.
|
687
|
Test
|
Computer Organization
|
Storage System
|
Multiple-choice
|
Reasoning
|
English
|
The page table in virtual memory is divided into a fast table and a slow table, and the correct statement about the page table is ( ).
|
The TLB (Translation Lookaside Buffer) and the page table are both stored in main memory, but the TLB has a smaller capacity than the page table.
|
The TLB (Translation Lookaside Buffer) employs an optimized search algorithm, thus enabling fast lookup speeds.
|
The hit rate of the fast table is higher than that of the slow table, therefore the fast table can obtain more search results.
|
The TLB (Translation Lookaside Buffer) is composed of associative memory devices and is accessed based on the content being looked up, therefore it has a faster lookup speed than a page table.
|
D
|
The TLB (Translation Lookaside Buffer) is composed of associative memory devices and is accessed based on the content being looked up, therefore it has a faster search speed compared to a slower table.
|
688
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What are the characteristics of a zero-address instruction?()
|
Requires two operands
|
No operand required
|
Only one operand is needed.
|
The number of operands is variable.
|
B
| null |
689
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What usually happens during the operation of a one-address instruction?()
|
The result is stored in the source address.
|
The operand is retrieved from the ACC.
|
The result is stored in the destination address.
|
The operand comes from the instruction itself.
|
A
| null |
690
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What are the advantages of immediate addressing?()
|
Expand the addressing range
|
Support Vector/Matrix Operations
|
No need to access main memory.
|
Simplified Instruction Format
|
C
| null |
691
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What are the main advantages of indirect addressing?()
|
Fast execution speed
|
Shorten the instruction word length
|
Expandable addressing range
|
Operands do not access main memory.
|
C
| null |
692
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the main advantage of register indirect addressing compared to general indirect addressing?()
|
Faster execution speed
|
Can expand the addressing range
|
The instruction word length is shorter.
|
No need to access main memory.
|
A
| null |
693
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
In base addressing, how is the effective address calculated?()
|
EA = (PC) + A
|
EA = (BR) + A
|
EA = (IX) + A
|
EA = (Ri)
|
B
| null |
694
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the primary use of indexed addressing?()
|
Simplified Programming
|
Handling array issues
|
Optimize code execution
|
Reduce Addressing Time
|
B
| null |
695
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is a major difference between CISC and RISC architectures?()
|
CISC has more general-purpose registers.
|
RISC instruction word length is not fixed.
|
CISC typically has more than 200 instructions.
|
RISC uses microprogram control.
|
C
| null |
696
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the frequency of use for various instructions in the RISC architecture?()
|
Vastly different
|
are all commonly used
|
Limited to basic operations
|
Primarily focused on specific types of instructions
|
B
| null |
697
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
How difficult is it to generate target code for CISC architecture?()
|
Easily generates efficient target code programs.
|
Manual optimization is usually required.
|
Difficult to generate efficient target code programs with optimization compilation.
|
Dependent on advanced programming skills
|
C
| null |
698
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the implementation of the instruction pipeline in RISC architecture?()
|
It can be realized in certain ways.
|
Must be implemented
|
Typically not implemented
|
Implemented only in high-performance systems
|
B
| null |
699
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What are the main advantages of relative addressing?()
|
The address of the operand changes with the variation of the PC.
|
Operands do not need to access main memory.
|
Can expand the addressing range
|
The operand address is fixed.
|
A
| null |
700
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the purpose of the destination operand address in a two-address instruction?()
|
For data reading only
|
Used to store calculation results
|
Used for storing instruction addresses
|
For data storage only
|
B
| null |
701
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
In four-address instructions, what is the usual role of the fourth address?()
|
Store the calculation result
|
The address pointing to the next instruction to be executed.
|
Indicate the source of data
|
Store temporary variables
|
B
| null |
702
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
In sequential addressing mode, what is the function of the Program Counter (PC)?()
|
Address of the current instruction
|
Calculate and save the address of the next instruction.
|
Store the calculation result
|
Indicate the order of program execution
|
B
| null |
703
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What are the main advantages of the implied addressing mode?()
|
Accelerate execution speed
|
Shorten the instruction word length
|
Increased hardware for storing operands
|
Expand the addressing range
|
B
| null |
704
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the main disadvantage of register addressing mode?()
|
The number of registers is limited.
|
Slow execution speed
|
Increase in instruction word length
|
Requires multiple accesses to the main memory.
|
A
| null |
705
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
In relative addressing mode, the calculation of the effective address depends on the contents of which register?()
|
Accumulator (ACC)
|
Base Register (BR)
|
Index Register (IX)
|
Program Counter (PC)
|
D
| null |
706
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What computing scenario is the indexed addressing mode primarily used for?()
|
Simple arithmetic operations
|
Logical operations
|
Array processing
|
String manipulation
|
C
| null |
707
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What are the characteristics of the instruction word length in RISC architecture?()
|
Variable length
|
Fixed
|
Extremely short
|
Extremely long
|
B
| null |
708
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What are the characteristics of instruction execution time in CISC architecture?()
|
All completed within one cycle.
|
significantly different
|
They are all very fast.
|
They are all very slow.
|
B
| null |
709
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
In RISC architecture, how does the number of general-purpose registers compare to that in CISC?()
|
Less
|
identical
|
More
|
No general-purpose registers
|
C
| null |
710
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the primary instruction control method in RISC architecture?()
|
Microprogram Control
|
Combinational Logic Control
|
Hardware Control
|
Software Control
|
B
| null |
711
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
In stack addressing mode, how is the address of the operand determined?()
|
Through the Program Counter (PC)
|
Through the accumulator (ACC)
|
Using the stack pointer
|
Using the Base Register (BR)
|
C
| null |
712
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the primary function of zero-address instructions in a stack machine?()
|
Perform complex arithmetic operations
|
Directly manipulate the elements at the top of the stack.
|
Management of Program Flow
|
Storing large amounts of data
|
B
| null |
713
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the memory accessibility of instructions in CISC architecture?()
|
Strictly limit
|
Unrestricted
|
Only Load/Store instructions
|
Limited to specific instructions
|
B
| null |
714
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What determines the necessity of the instruction pipeline in RISC architecture?()
|
The complexity of instructions
|
The number of instructions
|
The execution time of an instruction
|
Processor's Design
|
D
| null |
715
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What types of memory access instructions are there in the RISC architecture?()
|
All types
|
Arithmetic instructions only
|
Only Load/Store instructions
|
Control Commands Only
|
C
| null |
716
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the main advantage of register indirect addressing compared to direct addressing?()
|
Wider addressing range
|
Faster execution speed
|
The instruction word length is shorter.
|
Requires fewer registers
|
A
| null |
717
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
In base addressing, how is the Effective Address (EA) calculated?()
|
EA = (PC) + A
|
EA = (BR) + A
|
EA = A
|
EA = (IX) + A
|
B
| null |
718
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
How is the effective address calculated in indexed addressing mode?()
|
EA = A
|
EA = (BR) + A
|
EA = (IX) + A
|
EA = (PC) + A
|
C
| null |
719
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the main disadvantage of relative addressing mode?()
|
The instruction execution speed is slow.
|
Limited Addressing Range
|
The address of the operand is fixed.
|
Requires multiple accesses to the main memory.
|
B
| null |
720
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the usual control method of RISC architecture?()
|
Microprogram Control
|
Hardware Control
|
Software Control
|
Combinational Logic Control
|
D
| null |
721
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
What is the characteristic of the number of instructions in RISC architecture?()
|
fewer
|
Same as CISC
|
a large number of
|
Variable
|
A
| null |
722
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
The function of program control instructions is ( )
|
Perform arithmetic and logical operations
|
Data transfer between main memory and CPU
|
Perform data transfer between CPU and IO devices.
|
Change the order of program execution
|
D
| null |
723
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
The instruction that should not be used in the following ARM application is ( ).
|
Loop instruction
|
Conversion instruction
|
privileged instruction
|
Conditional branch instruction
|
C
| null |
724
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
The purpose of adopting different addressing modes in the instruction system is()
|
Provide the possibility of extended operation codes and reduce the difficulty of instruction decoding.
|
Shorten instruction word length, expand addressing space, and enhance programming flexibility.
|
Implement program control
|
All three are correct.
|
B
| null |
725
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
The function of an unconditional jump instruction with direct addressing is to load the address code from the instruction into()
|
Program Counter (PC)
|
Accumulator (ACC)
|
Instruction Register (IR)
|
Memory Address Register (MAR)
|
A
| null |
726
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
The basic method to simplify the address structure is to adopt as much as possible.()
|
Register Addressing
|
Anonymized Address
|
Direct Addressing
|
Indirect Addressing
|
B
| null |
727
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Knowledge
|
English
|
For machines that use byte addressing, the number of bits in the program counter and the instruction register each depends on ( ).
|
Machine word length, number of words in memory
|
The number of words in memory, instruction word length
|
Instruction word length, machine word length
|
Address bus width, number of words in memory
|
B
| null |
728
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
The difference between the addressing of operational instructions and the addressing of transfer instructions lies in ( ).
|
The former fetches the operand, while the latter determines the program transfer address.
|
The latter fetches the operand, while the former determines the program transfer address.
|
The former is a short instruction, while the latter is a long instruction.
|
The former is a long instruction, while the latter is a short instruction.
|
A
|
Arithmetic instructions address operands, while branch instructions address the address of the next instruction to be executed.
|
729
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
Among the following instructions, the one that does not belong to program control instructions is ( )
|
Unconditional transfer instruction
|
Conditional branch instruction
|
Interrupt Implicit Instruction
|
Loop instruction
|
C
|
Interrupt implicit instructions are implemented by hardware and are not part of the instruction set, nor can they be classified as program control instructions.
|
730
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
In stack computers, some zero-address stack operation instructions do not specify operand addresses in the instruction format; the two participating operands come from ( ).
|
Accumulator and Register
|
Accumulator and Temporary Register
|
Top of the stack and the second-to-top element of the stack
|
Top of stack unit and temporary register
|
C
|
Zero-address instructions, also known as stack operation instructions, involve two operands from the top and the second-to-top cells of the stack.
|
731
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
The following statement is incorrect ( )
|
To facilitate instruction fetching, the length of an instruction is usually an integer multiple of the storage word length.
|
Single-address instructions are of fixed length.
|
Fixed word length instructions can speed up instruction fetch.
|
Single-address instructions may have one operand or two operands.
|
B
|
The number of addresses in an instruction does not necessarily correlate with the fixed length of the instruction; even single-address instructions may vary in length due to different addressing modes for the single address.
|
732
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
Among the various addressing modes for instructions, the fastest way to obtain an operand is
|
Direct Addressing
|
Immediate Addressing
|
Register Addressing
|
Indirect Addressing
|
B
|
Immediate addressing is the fastest, as the operand is directly provided by the instruction. Register addressing comes next, requiring only one access to the register. Direct addressing is slower, involving one memory access. Indirect addressing is the slowest, requiring two or more memory accesses. Note: The speed of fetching operands with register indirect addressing is close to that of direct addressing.
|
733
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
In relative addressing mode, the relative address provided by the instruction is essentially a()
|
immediate value
|
memory address
|
Offset based on the starting address of this instruction in memory
|
The following instructions have an offset from the base address in memory.
|
D
|
In relative addressing, the effective address EA = (PC) + A (where A is the displacement address). When this instruction is executed, the PC has already completed the increment operation, and the PC contains the address of the next instruction. Therefore, the displacement is based on the address of the following instruction.
|
734
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
In multiprogramming, the most important addressing mode is ( ).
|
Relative addressing
|
Indirect Addressing
|
Immediate Addressing
|
Content Addressable
|
A
|
In multiprogramming, different program segments may need to float in memory, and relative addressing is particularly advantageous for program floating, therefore option A is chosen.
|
735
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
The word length of a certain machine instruction is 16 bits, and the main memory is byte-addressable. When fetching instructions, the PC (Program Counter) automatically increments by 1 for each byte fetched. If the address of the previous instruction is 2000H and the current instruction is an unconditional jump instruction with relative addressing, with the operand being 40H, then the content of the PC after fetching the instruction and after the execution of the instruction is ().
|
2000H, 2042H
|
2002H, 2040H
|
2002H, 2042H
|
2000H, 2040H
|
C
|
The instruction word length is 16 bits, 2 bytes, so after fetching the instruction, the content of PC is (PC) + 2 = 2002H; the unconditional jump instruction sends the address of the next instruction to PC, with the effective address being 40H, and after the instruction is executed, PC = 2002H + 0040H = 2042H.
|
736
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
Assuming the value in register R is 200, and the contents of the main memory cells at addresses 200 and 300 are 300 and 400 respectively, the operand accessed in the () mode is 200.
|
Direct addressing 200
|
Register indirect addressing (R)
|
Memory indirect addressing (200)
|
Register Addressing R
|
D
|
Register addressing R means the content of register R is the operand, only D is correct.
|
737
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
Assuming the first operand of an instruction uses register indirect addressing, and the register number given in the instruction is 8, the content of register 8 is 1200H, the content of the cell at address 1200H is 12FCH, the content of the cell at address 12FCH is 38D8H, and the content of the cell at address 38D8H is 88F9H, then the effective address of the operand is ( ).
|
1200H
|
12FCH
|
38D8H
|
88F9H
|
A
|
In register indirect addressing, the effective address (EA) of the operand is EA = (R). Since the content of register 8 is 1200H, therefore EA = 1200H.
|
738
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
Assuming R[ax] = FFE8H, R[bx] = 7FE6H, after executing the instruction "addw %bx,%ax", the content of the register and the changes in the flags are ().
|
R[ax] = 7FCEH, OF = 1, SF = 0, CF = 0, ZF = 0
|
R[bx] = 7FCEH, OF = 1, SF = 0, CF = 0, ZF = 0
|
R[ax] = 7FCEH, OF = 0, SF = 0, CF = 1, ZF = 0
|
R[bx] = 7FCEH, OF = 0, SF = 0, CF = 1, ZF = 0
|
C
|
The instruction format indicates that the instruction is in AT&T syntax, with the destination register for the add instruction being ax. The two's complement addition process for the add instruction is 1111 1111 1110 1000 + 111 1111 1110 0110 = (1) 0111 1111 1100 1110 (7FCEH). Since the two numbers involved in the addition have different signs, overflow is impossible, OF = 0. The sign bit of the result is 0, SF = 0, there is a carry out CF = 1, and since the result is not zero, ZF = 0.
|
739
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
The correct statement among the following is ( ).
|
RISC machines definitely employ pipelining technology.
|
Machines that employ pipeline technology are necessarily RISC machines.
|
RISC machines have better compatibility than CISC machines.
|
The CPU is equipped with very few general-purpose registers.
|
A
|
RISC inherently adopts pipeline technology, which is determined by the characteristics of its instructions. CISC, on the other hand, does not have this mandatory requirement, but in order to increase the speed of instruction execution, CISC often also employs pipeline technology. Therefore, pipeline technology is not exclusive to RISC.
|
740
|
Test
|
Computer Organization
|
Instruction System
|
Multiple-choice
|
Reasoning
|
English
|
Among the following descriptions, the one that does not conform to the characteristics of RISC (Reduced Instruction Set Computer) systems is ( ).
|
The instruction length is fixed, and there are few types of instructions.
|
Minimize the number of addressing modes, and maximize the functionality of instructions.
|
Increase the number of registers to minimize the frequency of memory access.
|
Select some simple instructions that are used most frequently, as well as useful but uncomplicated instructions.
|
B
|
Options A, C, and D are characteristics of RISC. Option B is correct in that the number of addressing modes is minimized, but RISC aims to simplify the function of each individual instruction, with complex instruction functionalities being achieved through the combination of simple instructions, whereas enhancing the functionality of instructions is a characteristic of CISC.
|
741
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
Which of the following is not a basic function of the CPU?()
|
Instruction Control
|
Data Processing
|
Graphic rendering
|
Time Control
|
C
| null |
742
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
Which of the following is not a component of the CPU's arithmetic logic unit (ALU)?()
|
Arithmetic Logic Unit (ALU)
|
Memory Address Register (MAR)
|
Program Status Word Register
|
General-purpose register set
|
B
| null |
743
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
Which phases are typically included in the instruction cycle?()
|
Fetch, Indirect Addressing, Execute, Interrupt
|
Compilation, interpretation, execution, feedback
|
Input, Processing, Output, Storage
|
Start, Execute, Pause, Terminate
|
A
| null |
744
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
How is the length of the instruction cycle determined in a single instruction cycle execution scheme?()
|
The execution time of the instruction with the shortest execution time
|
The execution time of the longest-running instruction
|
Average execution time of all instructions
|
The execution time of the first instruction
|
B
| null |
745
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What is the main disadvantage of the single-bus structure inside a CPU?()
|
Structurally complex
|
There are many conflict phenomena in data transmission.
|
Large volume of hardware
|
Poor scalability
|
B
| null |
746
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What is the working principle of a microprogrammed control unit?()
|
Execute the instruction upon reading.
|
Generated instantaneously by combinational logic circuits
|
According to the operation code of the instruction.
|
Works by directly connecting to the CPU.
|
A
| null |
747
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What does the speedup ratio of a pipeline refer to?()
|
The speed ratio of completing the same task
|
Efficiency ratio of different task executions
|
Pipeline throughput to single-core processor ratio
|
The ratio of pipeline efficiency to non-pipeline efficiency
|
A
| null |
748
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What are the characteristics of superscalar pipeline technology?()
|
Multiple independent instructions can be executed concurrently in each clock cycle.
|
Execute a single instruction in segments within one clock cycle.
|
Pipeline for executing a single function
|
Pipeline for executing linear tasks
|
A
| null |
749
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What operations are primarily completed by the CPU during the instruction fetch stage of instruction execution?()
|
Write the instruction result back to the register.
|
Fetch the instruction code from the main memory and place it into the Instruction Register (IR).
|
Decode the instruction
|
Perform arithmetic or logical operations
|
B
| null |
750
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What is the main function of the Program Status Word (PSW) register in the structure of a CPU?()
|
Store the state information of the currently running program.
|
The address indicating the next instruction to be executed.
|
Store the currently executing instruction.
|
The value of a variable in a stored program
|
A
| null |
751
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What does "structural hazard" refer to in pipeline technology?()
|
Conflicts arising from data dependencies among multiple instructions.
|
The delay caused by control signal conflicts between instructions.
|
Contention caused by multiple instructions competing for the same resource at the same moment.
|
Logical errors during the instruction execution process
|
C
| null |
752
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What is the primary function of the accumulator register in a CPU?()
|
Address of the storage instruction
|
Intermediate results during the execution of a store instruction
|
Storing the state information of a program
|
Directly involved in logical operations
|
B
| null |
753
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
Which of the following is not a category of pipeline in processor-level pipelining?()
|
Single-function pipeline
|
Multi-functional assembly line
|
Dynamic Pipeline
|
Nonlinear Pipeline
|
D
| null |
754
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What is the primary function of the "shifter" in CPU architecture?()
|
Perform logical shift operation
|
Store instructions or data
|
Control data transmission
|
Generate time series signal
|
A
| null |
755
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What are the main characteristics of "inter-field indirect encoding" in microinstructions?()
|
One bit in the microinstruction word corresponds to one control signal.
|
The micro-operation code field specifies the function of the microinstruction.
|
The micro-operation field is divided into several subfields to improve encoding efficiency.
|
Use implicit encoding to reduce the length of microinstructions.
|
D
| null |
756
|
Test
|
Computer Organization
|
Central Processing Unit
|
Multiple-choice
|
Knowledge
|
English
|
What is the main function of the general-purpose register set inside the CPU?()
|
Instructions for storing the operating system
|
The source code of the stored program
|
Store the state information of the currently running program.
|
Used for temporary storage of data and calculation results
|
D
| null |
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