lmms-lab/CSBench_MCQ · Datasets at Hugging Face

ID int64 1 1.96k	Split stringclasses 1 value	Domain stringclasses 4 values	SubDomain stringclasses 24 values	Format stringclasses 1 value	Tag stringclasses 2 values	Language stringclasses 1 value	Question stringlengths 15 717	A stringlengths 1 292	B stringlengths 1 232	C stringlengths 1 217	D stringlengths 1 192	Answer stringclasses 4 values	Explanation stringlengths 21 1.43k ⌀
757	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	What are micro-operations in a microprogrammed controller?()	The combination of control signals	Microinstruction address	Data in the main memory	Operating System Instructions	A	null
758	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	In the structure of a CPU, which component is used to store the currently executing instruction?()	General-purpose register set	Instruction Register (IR)	Program Status Word Register (PSW)	Arithmetic unit component	B	null
759	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	What is the main function of the data path in a CPU?()	Address of the storage instruction	Execution process of control instructions	Implement data exchange between the arithmetic unit and registers.	Handling of Interrupt Request Control	C	null
760	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	What is the main task of the controller in the structure of a CPU?()	Storing Data	Execution flow of control instructions	Perform arithmetic operations	Manage Main Memory	B	null
761	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	Which type of pipeline does not belong to the common classifications in processor-level pipelining?()	Single-function pipeline	Multi-functional assembly line	Dynamic Pipeline	Static Pipeline	D	null
762	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	What are the typical cycles included in the instruction cycle of a CPU?()	Fetch, Indirect Addressing, Execute, and Interrupt	Storage, Execution, Interruption, and Instruction Fetch	Fetch, Decode, Execute, and Control	Storage, Indirect Addressing, Execution, and Interrupt	A	null
763	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The following component is not part of the controller ( ).	Instruction Register	Program Counter	Program Status Word Register	Sequential circuit	C	null
764	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	General-purpose registers are ().	Instruction Register	A register that can store the program status word (PSW)	A register that inherently possesses counting logic and shifting logic.	Programmable register with multiple specified functions	D	null
765	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The register in the CPU that holds the currently executing instruction is ( ).	Instruction Register	Instruction Decoder	Data Register	Address Register	A	null
766	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	In the so-called n-bit CPU, n refers to ().	Number of address bus lines	Number of data bus lines	Number of control bus lines	Number of I/O lines	B	null
767	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The ( ) in the CPU's registers are transparent to the user.	Program Counter	Status Register	Instruction Register	General-purpose register	C	null
768	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	During the instruction cycle of an unconditional jump instruction, the value of PC is modified ( ) times.	1	2	3	Unable to determine	B	null
769	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The status register is used to store ( ).	Arithmetic operation result	Logical operation result	Operation type	Arithmetic, logical operations, and test instruction result states	D	null
770	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	Direct decoding refers to the decoding of ( ).	The entire instruction	The operation code field of an instruction	The address code field of the instruction	Instruction address	B	null
771	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The CPU does not include ( ).	Memory Address Register (MAR)	Instruction Register	Address Decoder	Program Counter	C	null
772	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The current period refers to ( ).	The time it takes for the CPU to fetch an instruction from the main memory.	The time it takes for a CPU to execute an instruction	The time it takes for the CPU to fetch an instruction from the main memory plus the time to execute this instruction.	Clock cycle time	C	null
773	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The instruction ( ) is read out from the main memory.	Always based on the program counter	Sometimes based on the program counter, sometimes based on the jump instruction.	According to the address register	Sometimes based on the program counter, sometimes based on the address register.	A	null
774	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	After the fetch operation, the program counter contains ( ).	The address of the current instruction	The number of instructions in the program	Number of executed instructions	The address of the next instruction	D	null
775	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The following statement is incorrect ( ).	The first operation of the instruction cycle is fetching the instruction.	To perform the fetch operation, the controller needs to obtain the corresponding instruction.	The fetch operation is automatically performed by the controller.	Some operations are identical or similar during the execution of instructions.	B	null
776	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	Among the following statements, the reasonable one is ( ).	The number of machine cycles required to execute each instruction is the same, and the length of each machine cycle is uniform.	The number of machine cycles required to execute each instruction is the same, but the length of each machine cycle can vary.	The number of machine cycles required to execute each instruction can vary, but the length of each machine cycle is uniform.	The number of machine cycles required to execute each instruction can vary, and the length of each machine cycle can also vary.	D	null
777	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The time it takes for the CPU to respond to an interrupt is ( ).	The instruction execution is complete.	I/O devices issue an interrupt.	Instruction fetch cycle complete	Instruction cycle complete	A	null
778	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	Which of the following does not belong to the CPU data path structure? ( )	Single Bus Structure	Multi-bus architecture	Internal bus structure of the component	Dedicated Data Path Architecture	C	null
779	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	In a single-bus CPU, ( ).	The two input ports and the output port of the ALU can all be connected to the bus.	The two input ports of the ALU can be connected to the bus, but the output port must be connected to the bus through a register.	One input of the ALU can be connected to the bus, and its output can also be connected to the bus.	The ALU can only have one input connected to the bus, while the other input must be connected to the bus through a temporary register.	D	null
780	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	Which of the following is not an objective pursued in micro-instruction structure design ( ).	Increase the execution speed of microprograms	Provide the flexibility of microprogram design.	Shorten the length of microinstructions.	Increase the capacity of the control memory	D	null
781	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The correct statement among the following is ( )	Using a microprogrammed controller is to increase speed.	The control memory is composed of high-speed RAM circuits.	The microinstruction counter determines the order of instruction execution.	A microinstruction is stored in a control memory unit of the controller.	B	null
782	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	Compared to horizontal microinstructions, vertical microinstructions ( )	The former can only complete one basic operation at a time.	The latter can only complete one basic operation at a time.	Both can only complete one basic operation at a time.	Both can complete multiple basic operations at once.	B	null
783	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	Compatibility micro-operations refer to several micro-operations ( ).	The following can occur simultaneously:	can appear in succession	Interchangeable	Tolerant of coexistence	A	null
784	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The following components are control units ( ). Ⅰ. Instruction Register Ⅱ. Operation Controller Ⅲ. Program Counter Ⅳ. Status Condition Register	Ⅰ、Ⅲ、Ⅳ	Ⅰ、Ⅱ、Ⅲ	Ⅰ、Ⅱ、Ⅳ	Ⅰ、Ⅱ、Ⅲ、Ⅳ	B	null
785	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The following components are considered as execution units ( ). Ⅰ. Controller Ⅱ. Memory Ⅲ. Arithmetic unit Ⅳ. Peripheral devices	Ⅰ、Ⅲ、Ⅳ	Ⅱ、Ⅲ、Ⅳ	Ⅱ、Ⅳ	Ⅰ、Ⅱ、Ⅲ、Ⅳ	B	null
786	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The interrupt caused by an abnormal result of instruction execution is ( ).	I/O Interrupt	Machine Check Exception	Procedural Interrupt	External Interrupt	C	null
787	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The interrupt caused by main memory failure is ( ).	Fault Anomaly	Procedural Interrupt	Hardware Interrupt	External Interrupt	C	null
788	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	The common feature of dual-core CPUs and hyper-threading CPUs is ().	Both have two cores.	Can perform two operations simultaneously	Both contain two CPUs.	There will be no competition for resources.	B	null
789	Test	Computer Organization	Central Processing Unit	Multiple-choice	Knowledge	English	Among the following statements about dual-core technology, the correct one is ( ).	Dual-core refers to a motherboard with two CPUs.	Dual-core is achieved through the use of Hyper-Threading technology.	Dual-core refers to the integration of two processing cores on a CPU.	Dual-core CPU is a form of parallel computing based on time parallelism.	C	null
790	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Among the following statements about the Program Counter (PC), the incorrect one is ( ).	The PC always holds the instruction address.	The value of the PC is modified by the CPU during the execution of instructions.	During a jump instruction, the value of the PC is always changed to the target address of the jump instruction.	The bit size of a PC generally matches the number of bits in the Memory Address Register (MAR).	C	The PC holds the address of the next instruction to be executed, so option A is correct. The value of the PC is modified during the execution of instructions by the CPU (specifically at the end of the fetch cycle), either by incrementing or by jumping to a certain part of the program, so option B is correct. When a jump instruction is executed, it is necessary to determine whether the jump is successful; if it is, the PC is changed to the target address of the jump instruction, otherwise, the address of the next instruction remains the address after the PC is incremented, so option C is incorrect. The PC has the same number of bits as the MAR, so option D is correct.
791	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Among the following concepts about computer systems, the correct one(s) is (are) ( ). I. The CPU does not include an address decoder II. The program counter in the CPU stores the operand address III. The component in the CPU that determines the order of instruction execution is the program counter IV. The status register of the CPU is completely transparent to the user.	I, III	III, IV	II, III, IV	I, III, IV	A	The address decoder is a component of memory storage such as main memory, not a part of the CPU, I is correct. The program counter in the CPU holds the address of the next instruction, not the address of the operand, II is incorrect. The program counter determines the execution order of the program, III is correct. The status register is opaque to the user, IV is correct.
792	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	The following statement about the machine cycle is incorrect ( ).	A machine cycle is typically defined as the time taken to access the main memory or I/O once through a single bus transaction.	An instruction cycle typically consists of multiple machine cycles.	The number of machine cycles contained in different instruction cycles may vary.	Each instruction cycle includes an interrupt response machine cycle.	D	After the execution cycle of an instruction is completed, the processor will determine whether an interrupt request has occurred, and it will only enter the interrupt cycle if an interrupt request is present.
793	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	The correct description of the indirect addressing cycle is ( ).	The indirect addressing operations for all instructions are identical.	For instructions that use indirect addressing through memory, their operations are all the same.	For memory indirect addressing and register indirect addressing, their operations are different.	None of them are correct.	C	Indirect addressing is divided into single-level indirect addressing, two-level indirect addressing, and multi-level indirect addressing, hence their operations are different; therefore, A and B are incorrect. Memory indirect addressing accesses memory through a formal address, while register indirect addressing accesses memory through the contents of a register; C is correct.
794	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Among the following statements, the correct one is ( ) I. Assuming the instruction length is equal to the machine word length, the instruction fetch cycle is equal to the machine cycle II. Assuming the instruction word length is equal to the storage word length, the instruction fetch cycle is equal to the machine cycle III. The length of the instruction word length has no relation to the machine word length IV. For the convenience of hardware design, the instruction word length is always the same as the storage word length.	II, III	II, III, IV	I, III, IV	I, IV	A	The instruction word length is generally an integer multiple of the storage word length. If the instruction word length is twice the storage word length, it requires two memory accesses, and the instruction fetch cycle is twice the machine cycle. If the instruction word length is equal to the storage word length, then the instruction fetch cycle is equal to the machine cycle; this statement is incorrect. According to the analysis of statement I, it is known that statement II is correct. The instruction word length depends on the length of the opcode, the length of the operand address, and the number of operand addresses, and is not necessarily related to the machine word length. However, for the convenience of hardware design, the instruction word length is generally taken as a byte or an integer multiple of the storage word length, so statement I is correct. According to the analysis of statement I, the instruction word length is generally a byte or an integer multiple of the storage word length, and is not necessarily the same size as the storage word length, therefore statement IV is incorrect. In summary, statements II and III are correct.
795	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	In a combinational logic controller, the formation of micro-operation control signals is mainly related to the ( ) signal.	Instruction opcode and address code	Decode the signal and clock today.	Opcode and Condition Code	State information and conditions	B	The input signals of the CUP originate from the following sources: instruction information generated by the instruction decoder, machine cycle signals and beat signals produced by the timing system, and feedback information from the execution unit, namely flags. The first two are the primary factors.
796	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	In a microprogrammed control unit, the entity that forms the microprogram entry address is ( ).	The address field of a machine instruction	Microinstruction's microaddress code field	operation code field of a machine instruction	Microinstruction's micro-operation code field	C	The common fetch microprogram retrieves machine instructions from the main memory, and the operation code field of the machine instruction indicates the entry addresses (initial microaddresses) of each microprogram.
797	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	The speed of a microprogrammed control unit is slower than that of a hardwired control unit, mainly because ( )	Increased the time to read microinstructions from disk storage.	Increased the time to read microinstructions from main memory.	Increased the time to read micro-instructions from the instruction register.	Increased the time to read microinstructions from the control memory.	D	In microprogram control, microinstructions are stored in the control memory, and the corresponding microinstructions need to be read out during execution, which increases the time consumption.
798	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Compared to a microprogrammed controller, a hardwired controller ( )	The timing system of a hard-wired controller is relatively simple.	The timing system of the microprogrammed controller is relatively simple.	The temporal system complexity of both is the same.	It could be that the timing system of the hardwired controller is simpler, or it could be that the timing system of the microprogrammed controller is simpler.	B	The hardwired controller requires a comprehensive analysis that combines the timing arrangement of each micro-operation to write logical expressions and then design them into logic circuits, making the timing system more complex. In contrast, microprogramming simply executes microinstructions in sequence according to the timing arrangement, making it relatively simpler.
799	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	In a microprogrammed control unit, the relationship between machine instructions and microinstructions is ( ).	Each machine instruction is executed by a microinstruction.	Each machine instruction is now interpreted and executed by a microprogram composed of several microinstructions.	A program composed of several machine instructions can be executed by a microprogram.	Each machine instruction is now executed by a series of microprograms.	B	In a CPU cycle, a combination of micro-operations that implement a certain function constitutes a microinstruction, and an ordered sequence of microinstructions forms a microprogram. The purpose of the microprogram is to implement a corresponding machine instruction.
800	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	In the microprogram control method, the correct statements are ( )I. A processor that uses a microprogram controller is called a microprocessor II. Each machine instruction is interpreted and executed by a microprogram III. In the encoding of microinstructions, the least efficient is the direct encoding method IV. Horizontal microinstructions can fully utilize the parallel structure of the data path.	I, II	II, IV	I, III	III, IV	B	A microprocessor is relative to some larger processors and is not necessarily associated with a microprogrammed controller. Whether a microprogrammed controller or a hardwired controller is used, the CPU of a microcomputer is still a microprocessor, which is incorrect. The design idea of microprogramming is to write each machine instruction as a microprogram, which contains several microinstructions, each corresponding to one or several micro-operations, which is correct. In the direct encoding method, each bit represents a micro-operation and does not require decoding, thus the execution efficiency is the highest, but this method significantly increases the number of bits in the microinstruction, which is incorrect. A horizontal microinstruction can define and execute several parallel basic operations, thus making fuller use of the parallel structure of the data path, which is correct.
801	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Among the following statements, the correct one(s) is (are) ( )I. Compared to hardwired control, microprogrammed control can make the execution of instructions faster.II. If microprogrammed control is used, uPC can replace PC.III. Control memory can be implemented using ROM.IV. Instruction cycle is also known as CPU cycle	I, III	II, III	Only III	I, II, III, IV	C	Microprogram control uses a programming approach to execute instructions, while hardwired control uses a hardware approach, hence the latter is faster, I incorrect. HPC cannot replace PC, as it is merely a register that points to the address of the next microinstruction in a microprogram. Therefore, it cannot possibly know what the next instruction will be after the completion of this microprogram, II incorrect. Since the control signals emitted during the execution of each microinstruction are pre-designed and do not need to be changed, the memory that stores all control signals should be ROM, III correct. Instruction cycle refers to the interval from the start of one instruction to the start of the next, while CPU cycle is the machine cycle, which refers to the time required for each step of instruction execution, IV incorrect.
802	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	The following statement about the "Trap" exception is incorrect ( ).	"Self-trapping" is a specific processing event that is pre-set artificially.	The execution can be entered by either a trap gate or a task gate.	There must be some abnormal situation for "self-trapping" to occur.	"After a trap occurs, the CPU will enter and execute the operating system kernel program."	C	Trap is a special interrupt mechanism set by humans, not generated by certain exceptional conditions. Therefore, option C is incorrect.
803	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	The following statement about exception and interrupt handling is incorrect ( )	Anomaly event detection is conducted by the CPU during the execution of each instruction.	Interrupt request detection is performed by the CPU after the execution of each instruction and before fetching the next instruction.	The processing performed by the CPU after detecting an exception is exactly the same as the processing performed after detecting an interrupt request.	Upon interrupt response, the CPU will disable interrupts, save the breakpoint and program state, and then switch to the corresponding interrupt service routine.	C	The processing performed by the CPU after detecting an exception and after detecting an interrupt request is essentially the same, but there may be some differences. For example, for fault-type exceptions, since the breakpoint is the instruction address where the fault occurred, it is necessary to recalculate the PC value. However, the breakpoint for an interrupt is the address of the next instruction (i.e., the PC value), so there is no need to recalculate the PC value.
804	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Among the following events, the one that does not require an exception handler is ().	Page Fault	Cache miss	Address out of bounds	Division by zero	B	Page faults, address out-of-bounds, and division by zero are all faults that occur during the execution of an instruction, requiring the invocation of the corresponding exception handling routines in the operating system kernel to address them, whereas Cache misses are handled by the CPU hardware and do not require the invocation of an exception handler.
805	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Among the following descriptions of superscalar pipelines, the incorrect one is ( ).	Within a single clock cycle, a pipeline can execute more than one instruction.	An instruction is divided into multiple stages, each executed by different circuit units.	Superscalar architecture achieves simultaneous execution of multiple instructions by incorporating multiple pipelines, essentially trading space for time.	Superscalar pipeline refers to parallel execution of operations.	D	A superscalar pipeline refers to a pipeline that can execute more than one instruction per clock cycle, thus A is correct. An instruction is divided into multiple stages, completed by different circuit units, so B is correct. Superscalar achieves simultaneous execution of multiple processors by incorporating multiple pipelines, essentially trading space for time, hence C is correct. Superscalar pipelines typically include the characteristic of parallel arithmetic operations, therefore D is incorrect.
806	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Among the following descriptions of dynamic pipelines, the correct one is ( ).	A dynamic pipeline refers to a situation where, at the same time, some segments are performing one type of operation while other segments are conducting another type of operation. This is beneficial for improving the efficiency of the pipeline, but it can make pipeline control quite complex.	Dynamic pipeline refers to parallel computational operations.	Dynamic pipeline refers to the parallelism of steps.	Dynamic pipelining refers to the parallel execution of program steps.	A	Dynamic pipeline is in contrast to static pipeline. The connection method between the upper and lower sections of a static pipeline is fixed, whereas the connection method of a dynamic pipeline is variable. Therefore, A is correct.
807	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	A pipelined CPU consists of a series of processing circuits called "stages." The throughput of an m-stage pipeline when stable, compared to the throughput of a CPU with m parallel components, is ( ).	With equivalent throughput capacity	Does not possess equivalent throughput capacity.	Throughput greater than that of the former.	Throughput capacity is less than that of the former.	A	An m-stage pipeline can complete one instruction after one clock cycle, and with each subsequent clock cycle, it can complete another instruction. Meanwhile, m parallel components can complete all m instructions after m clock cycles, which is equivalent to completing one instruction per clock cycle on average. Therefore, the throughput of both is equal, so statement A is correct.
808	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Data hazards in the instruction pipeline can cause pipeline stalls, and ( ) can resolve data dependency issues.	Increase hardware resources	Adopting bypass technology	Employ branch prediction technology.	All of the above are acceptable.	B	There are two methods to deal with data-related issues: one is to suspend the execution of the relevant instructions, that is, to stall the pipeline until the register operands can be correctly read; the other is to use a dedicated data path to directly feed the result into the input of the ALU, which is known as bypassing technique, therefore B is correct.
809	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Which of the following statements about pipeline technology is incorrect ( )?	Superscalar technology requires the configuration of multiple functional units and instruction decoding circuits, etc.	Compared to superscalar and superpipelining technologies, Very Long Instruction Word (VLIW) technology places higher demands on optimizing compilers, without additional hardware requirements.	When the pipeline flows in sequence, only RAW hazards can occur among RAW, WAR, and WAW hazards.	Super-pipelining technology is equivalent to further segmenting the pipeline, thereby increasing the usage frequency of functional units within each cycle.	B	Very Long Instruction Word (VLIW) technology imposes higher requirements on the compiler, but it is hardware-independent, hence A is correct. When the pipeline flows in order, only Read After Write (RAW) hazards can occur, so C is correct. Super-pipelining is the technique of further segmenting the pipeline to increase the utilization of functional units, thus D is correct. Superscalar technology requires the configuration of multiple functional units and instruction decoding circuits, therefore A is correct.
810	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	The following description of Hyper-Threading (HT) technology is correct ( ).	Hyper-threading technology can turn a quad-core Intel Core i7 processor into eight cores.	Hyper-threading is a hardware technology that can significantly enhance system performance, independent of the operating system and application software.	A CPU with hyper-threading technology requires chipset support to leverage its technical advantages.	Each CPU core simulated by hyper-threading has independent resources and operates without interfering with each other.	C	Hyper-threading technology requires the support of the chipset, operating system, and application software to fully realize its advantages, C is correct.
811	Test	Computer Organization	Central Processing Unit	Multiple-choice	Reasoning	English	Among the following descriptions of multi-core CPUs and single-core CPUs, the incorrect one is ( ).	The frequency of the dual-core is 2.4GHz, which means the frequency of each core is also 2.4GHz.	Using a dual-core CPU can reduce the power consumption and size of a computer system.	Multi-core CPUs share a set of memory, allowing for data sharing.	All programs run faster on multi-core CPUs.	D	The statement that all programs run faster on multi-core CPUs is inaccurate, as program performance is influenced by a variety of factors, and not all programs can achieve speed improvements on multi-core CPUs, D is incorrect.
812	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	In the classification of system buses, which type of bus is used for transmitting data information between various functional components, supports bidirectional transmission, and its width is related to the machine word length and storage word length?()	Data Bus	Address Bus	Control Bus	Communication Bus	A	null
813	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	In the four stages of bus operation, which stage involves the master module that needs to use the bus making a request, and the bus arbitration mechanism decides to grant the bus usage rights for the next transmission cycle to one of the applicants?()	Addressing stage	Transmission Stage	End Phase	Application for Allocation Phase	D	null
814	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which bus standard is the latest bus and interface standard that will completely replace the current PCI and AGP, ultimately achieving the unification of bus standards?()	VESA bus	PCI bus	USB bus	PCI-Express (PCI-E)	D	null
815	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which bus standard is used as the standard interface between Data Terminal Equipment (DTE) and Data Communication Equipment (DCE) for serial binary data interchange?()	USB bus	PCMCIA	SCSI	RS-232C bus	D	null
816	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	In the performance metrics of a bus, what is the transmission cycle also known as?()	Bus cycle	Bus bandwidth	Clock frequency	Bus width	A	null
817	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	In the four stages of bus operation, during which stage do the master module and the slave module exchange data, allowing for unidirectional or bidirectional data transfer?()	Addressing stage	Transmission stage	End Phase	Application for Allocation Phase	B	null
818	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which bus standard is used as an independent processor standard between computers and smart devices, suitable for system-level interfaces?()	SATA	IDE bus	RS-232C bus	SCSI	D	null
819	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which bus standard is designed as an interconnect mechanism specifically for highly integrated peripherals, expansion cards, and processor/memory systems, and is considered a local bus?()	PCI-Express (PCI-E)	PCMCIA	ISA bus	EISA bus	A	null
820	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which bus standard is a 32-bit standard for a local computer bus that is used for high-speed transmission of large amounts of active image data?()	SCSI	VESA bus	USB bus	AGP	B	null
821	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which indicator among the bus performance metrics represents the bus data transfer rate, that is, the number of bits of data that can be transferred on the bus per unit of time?()	Bus bandwidth	Bus width	Bus Cycle	Clock frequency	A	null
822	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	In the four stages of bus operation, which stage involves the master module obtaining bus control and issuing a request to use the bus?()	Addressing stage	Transmission stage	End Phase	Application for Allocation Phase	D	null
823	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which bus arbitration method uses an independent request approach, has a fast response time, and offers considerable flexibility in controlling priority order?()	Counter-timed polling method	Distributed Arbitration Method	Independent Request Method	Chained query method	C	null
824	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which bus standard is a common connection line that connects between internal registers of a computer, and between a register and the ALU?()	Data Bus	Address Bus	Control Bus	Communication Bus	A	null
825	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which bus standard is an interface standard used for transmitting audio and sound data, connecting audio devices to computer systems?()	USB bus	PCI bus	IDE bus	AC'97 bus	D	null
826	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Which bus arbitration method centralizes all bus requests and uses a specific arbitration algorithm to make decisions, where components closer to the bus controller have higher priority?()	Counter Timing Query Method	Distributed Arbitration Method	Independent Request Method	Chained query method	D	null
827	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Multiple components connected to the bus ( )	Data can only be sent to the bus in a time-division manner, and can only be received from the bus in a time-division manner.	Data can only be sent to the bus in a time-division manner, but it can be received from the bus simultaneously.	Data can be sent to the bus,but it can be received from the bus simultaneously.	Data can be sent to the bus and can only be received from the bus in a time-division manner.	B	null
828	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	On the bus, at the same moment ( ).	Only one master device can control the bus transfer operation.	There can only be one transfer operation from the device control bus.	There can only be one master device and one slave device controlling the bus transmission operation.	Multiple master devices can control bus transmission operations.	A	null
829	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	In computer systems, the public pathway for information transmission between multiple system components is called a bus. With respect to the nature of the information transmitted, the following ( ) is not information transmitted on the public pathway.	Data Information	Address Information	System Information	Control Information	C	null
830	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	The system bus is used to connect ().	Register and Arithmetic Unit Components	Arithmetic Logic Unit (ALU) and Control Unit (CU) components	CPU, main memory, and peripheral components	Interfaces and external devices	C	null
831	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Computers use a bus structure to facilitate the addition and removal of peripherals, while ( )	Reduce the amount of information transmission	Increase the transmission speed of information	Reduce the number of information transmission lines	Enhance the parallelism of information transmission	C	null
832	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Indirect addressing involves the first memory access information being transmitted to the CPU via the ().	Data Bus	Address Bus	Control Bus	Bus Controller	A	null
833	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	In a single-machine system, the bus system composition of a computer with a triple bus structure is ( ).	On-chip bus, system bus, and communication bus.	Data bus, address bus, and control bus	DMA bus, main memory bus, and I/O bus	ISA bus, VESA bus, and PCI bus.	C	null
834	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	The main memory identifies whether the information is an address or data through ().	Types of Buses	Memory Data Register (MDR)	Memory Address Register (MAR)	Control Unit (CU)	A	null
835	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	The following bus standard that belongs to serial bus is ( ).	PCI	USB	EISA	ISA	B	null
836	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	In modern microcomputer motherboards, the function of adopting local bus technology is ( ).	Conserve the system's total bandwidth	Enhance Anti-Interference Capability	Suppress bus terminal reflection	Form a tightly coupled system	A	null
837	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Transferring data between devices with different speeds, ( )	Synchronous control mode must be adopted.	Asynchronous control methods must be adopted.	You can choose synchronous control mode, or asynchronous control mode.	The response mode must be adopted.	C	null
838	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	The synchronous control mode is ().	Applicable only to CPU-controlled methods	Applicable only to external device control methods	Controlled by a unified timing signal	A method where all instruction execution times are identical.	C	null
839	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	In an asynchronous bus, the transfer operation ( ).	Controlled by the device controller	Controlled by the CPU	Controlled by a unified timing signal	Allocate time on demand	D	null
840	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	The asynchronous communication mode of the bus is ( ).	Neither using a clock signal nor employing a "handshake" signal.	Only clock signals are used, without employing "handshake" signals.	Asynchronous communication, utilizing only "handshake" signals without a clock signal.	Uses both clock signals and "handshake" signals.	C	null
841	Test	Computer Organization	Bus	Multiple-choice	Knowledge	English	Among various asynchronous communication methods, () has the fastest speed.	Interlocking	Semi-interlocking	Non-interlocking	All velocities are equal.	C	null
842	Test	Computer Organization	Bus	Multiple-choice	Reasoning	English	To transmit an uncompressed photo with a resolution of 640x480 pixels and a color depth of 65536, given a data transfer rate of 56kb/s, the approximate time required is ( ).	34.82s	43.86s	85.71s	87.77s	D	The total number of pixels is 307,200 pixels, and each pixel has 65,536 colors (i.e., 16-bit color), so each pixel occupies 2 bytes. Therefore, the total data volume is: 307,200 * 2 = 614,400 bytes = 4,915,200 bits. Thus, the transmission time is: 4,915,200 / 56,000 = 87.77s.
843	Test	Computer Organization	Bus	Multiple-choice	Reasoning	English	A bus has 104 signal lines, of which 32 are data lines (DB). If the bus operates at a frequency of 33MHz, then its theoretical maximum transfer rate is ( ).	33MB/s	64MB/s	132MB/s	164MB/s	C	The calculated theoretical maximum transfer rate is 132MB/s.
844	Test	Computer Organization	Bus	Multiple-choice	Reasoning	English	The I/O device of a certain machine adopts asynchronous serial transmission to transfer character information, with a character information format of 1 start bit, 7 data bits, 1 parity bit, and 1 stop bit. If it is required to transmit 480 characters per second, then the data transfer rate of the device is ( ).	380 b/s	4800 B/s	480 B/s	4800 b/s	D	First, calculate the total number of bits per character: 1 start bit + 7 data bits + 1 parity bit + 1 stop bit = 10 bits. Transmitting 480 characters per second, calculate the total number of bits to be transmitted per second: 480 characters/second × 10 bits/character = 4800 bits/second.
845	Test	Computer Organization	Bus	Multiple-choice	Reasoning	English	During the surgical procedure, the doctor extends their hand, waiting for the nurse to pass the scalpel. Once the doctor has a firm grip, the nurse lets go. If we consider the doctor and nurse as two communication modules, the aforementioned action is equivalent to ( ).	Synchronous Communication	Asynchronous communication with full interlocking.	Semi-interlocking mode of asynchronous communication	Non-interlocked Asynchronous Communication	B	The actions of doctors and nurses conform to the full interlocking mode of asynchronous communication.
846	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	What are the three components that make up the average access time of a disk?()	Seek time, rotational latency, data transmission time	Transmission time, read time, write time	Rotational latency, seek time, data caching time	Transmission time, rotational latency, DMA time	A	null
847	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	In the basic structure of the I/O interface, the internal interface is connected to the system bus. What is the data transfer method?()	Parallel transmission	Serial transmission	DMA transfer	Channel Transmission	A	null
848	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	Which addressing mode for I/O ports treats I/O ports as memory unit locations for address allocation, eliminating the need for specialized I/O instructions?()	Unified Addressing Method	Independent Addressing Mode	Unified read-write method	Memory Mapping Method	A	null
849	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	In interrupt programming, what is a non-maskable interrupt (NMI)?()	Interrupts caused by components other than the processor and memory	Interrupts generated within the processor and memory	A software interrupt	an inside interrupt	A	null
850	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	One of the main differences between DMA mode and interrupt mode is what?()	DMA mode requires program switching, while interrupt mode does not.	DMA mode only occupies a small portion of CPU time, while interrupt mode occupies CPU resources throughout the entire process.	DMA mode responds slower.	DMA mode is only suitable for high-speed peripherals.	B	null
851	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	Which type of I/O interface connects to peripherals via an interface cable, and may use serial transmission for data transfer?()	I/O port	Internal Interface	External Interface	Data Interface	C	null
852	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	What does the interrupt vector address refer to?()	Interrupt Service Routine entry address	Priority of Interrupt Requests	The address of the interrupt source	Interrupt Controller Address	A	null
853	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	What type of error-correcting code is used in the RAID 2 scheme of RAID to enhance data fault tolerance?()	Hamming code	Parity Check Code	List code	Mirror code	A	null
854	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	Which function of the I/O interface is used to implement address decoding and device selection?()	Perform data buffering	Implement communication and control between the host and peripherals.	Transmit control commands and status information.	Perform address decoding and device selection.	D	null
855	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	In computers, what is an I/O port?()	Register for storing data from I/O devices	Direct data path between CPU and I/O devices	Registers that can be directly accessed by the CPU, used for reading and writing data.	Cable that controls data transfer between the CPU and I/O devices	C	null
856	Test	Computer Organization	Input/Output System	Multiple-choice	Knowledge	English	What does seek time refer to in the average access time of a hard drive?()	Time spent on data transmission	The time it takes for the read/write head to move to the target track	Time for disk to position to the relevant sector	The time it takes for a hard disk to make one rotation.	B	null

757

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

What are micro-operations in a microprogrammed controller?()

The combination of control signals

Microinstruction address

Data in the main memory

Operating System Instructions

A

null

758

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

In the structure of a CPU, which component is used to store the currently executing instruction?()

General-purpose register set

Instruction Register (IR)

Program Status Word Register (PSW)

Arithmetic unit component

B

null

759

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

What is the main function of the data path in a CPU?()

Address of the storage instruction

Execution process of control instructions

Implement data exchange between the arithmetic unit and registers.

Handling of Interrupt Request Control

C

null

760

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

What is the main task of the controller in the structure of a CPU?()

Storing Data

Execution flow of control instructions

Perform arithmetic operations

Manage Main Memory

B

null

761

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

Which type of pipeline does not belong to the common classifications in processor-level pipelining?()

Single-function pipeline

Multi-functional assembly line

Dynamic Pipeline

Static Pipeline

D

null

762

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

What are the typical cycles included in the instruction cycle of a CPU?()

Fetch, Indirect Addressing, Execute, and Interrupt

Storage, Execution, Interruption, and Instruction Fetch

Fetch, Decode, Execute, and Control

Storage, Indirect Addressing, Execution, and Interrupt

A

null

763

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The following component is not part of the controller ( ).

Instruction Register

Program Counter

Program Status Word Register

Sequential circuit

C

null

764

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

General-purpose registers are ().

Instruction Register

A register that can store the program status word (PSW)

A register that inherently possesses counting logic and shifting logic.

Programmable register with multiple specified functions

D

null

765

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The register in the CPU that holds the currently executing instruction is ( ).

Instruction Register

Instruction Decoder

Data Register

Address Register

A

null

766

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

In the so-called n-bit CPU, n refers to ().

Number of address bus lines

Number of data bus lines

Number of control bus lines

Number of I/O lines

B

null

767

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The ( ) in the CPU's registers are transparent to the user.

Program Counter

Status Register

Instruction Register

General-purpose register

C

null

768

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

During the instruction cycle of an unconditional jump instruction, the value of PC is modified ( ) times.

1

2

3

Unable to determine

B

null

769

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The status register is used to store ( ).

Arithmetic operation result

Logical operation result

Operation type

Arithmetic, logical operations, and test instruction result states

D

null

770

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

Direct decoding refers to the decoding of ( ).

The entire instruction

The operation code field of an instruction

The address code field of the instruction

Instruction address

B

null

771

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The CPU does not include ( ).

Memory Address Register (MAR)

Instruction Register

Address Decoder

Program Counter

C

null

772

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The current period refers to ( ).

The time it takes for the CPU to fetch an instruction from the main memory.

The time it takes for a CPU to execute an instruction

The time it takes for the CPU to fetch an instruction from the main memory plus the time to execute this instruction.

Clock cycle time

C

null

773

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The instruction ( ) is read out from the main memory.

Always based on the program counter

Sometimes based on the program counter, sometimes based on the jump instruction.

According to the address register

Sometimes based on the program counter, sometimes based on the address register.

A

null

774

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

After the fetch operation, the program counter contains ( ).

The address of the current instruction

The number of instructions in the program

Number of executed instructions

The address of the next instruction

D

null

775

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The following statement is incorrect ( ).

The first operation of the instruction cycle is fetching the instruction.

To perform the fetch operation, the controller needs to obtain the corresponding instruction.

The fetch operation is automatically performed by the controller.

Some operations are identical or similar during the execution of instructions.

B

null

776

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

Among the following statements, the reasonable one is ( ).

The number of machine cycles required to execute each instruction is the same, and the length of each machine cycle is uniform.

The number of machine cycles required to execute each instruction is the same, but the length of each machine cycle can vary.

The number of machine cycles required to execute each instruction can vary, but the length of each machine cycle is uniform.

The number of machine cycles required to execute each instruction can vary, and the length of each machine cycle can also vary.

D

null

777

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The time it takes for the CPU to respond to an interrupt is ( ).

The instruction execution is complete.

I/O devices issue an interrupt.

Instruction fetch cycle complete

Instruction cycle complete

A

null

778

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

Which of the following does not belong to the CPU data path structure? ( )

Single Bus Structure

Multi-bus architecture

Internal bus structure of the component

Dedicated Data Path Architecture

C

null

779

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

In a single-bus CPU, ( ).

The two input ports and the output port of the ALU can all be connected to the bus.

The two input ports of the ALU can be connected to the bus, but the output port must be connected to the bus through a register.

One input of the ALU can be connected to the bus, and its output can also be connected to the bus.

The ALU can only have one input connected to the bus, while the other input must be connected to the bus through a temporary register.

D

null

780

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

Which of the following is not an objective pursued in micro-instruction structure design ( ).

Increase the execution speed of microprograms

Provide the flexibility of microprogram design.

Shorten the length of microinstructions.

Increase the capacity of the control memory

D

null

781

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The correct statement among the following is ( )

Using a microprogrammed controller is to increase speed.

The control memory is composed of high-speed RAM circuits.

The microinstruction counter determines the order of instruction execution.

A microinstruction is stored in a control memory unit of the controller.

B

null

782

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

Compared to horizontal microinstructions, vertical microinstructions ( )

The former can only complete one basic operation at a time.

The latter can only complete one basic operation at a time.

Both can only complete one basic operation at a time.

Both can complete multiple basic operations at once.

B

null

783

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

Compatibility micro-operations refer to several micro-operations ( ).

The following can occur simultaneously:

can appear in succession

Interchangeable

Tolerant of coexistence

A

null

784

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The following components are control units ( ). Ⅰ. Instruction Register Ⅱ. Operation Controller Ⅲ. Program Counter Ⅳ. Status Condition Register

Ⅰ、Ⅲ、Ⅳ

Ⅰ、Ⅱ、Ⅲ

Ⅰ、Ⅱ、Ⅳ

Ⅰ、Ⅱ、Ⅲ、Ⅳ

B

null

785

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The following components are considered as execution units ( ). Ⅰ. Controller Ⅱ. Memory Ⅲ. Arithmetic unit Ⅳ. Peripheral devices

Ⅰ、Ⅲ、Ⅳ

Ⅱ、Ⅲ、Ⅳ

Ⅱ、Ⅳ

Ⅰ、Ⅱ、Ⅲ、Ⅳ

B

null

786

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The interrupt caused by an abnormal result of instruction execution is ( ).

I/O Interrupt

Machine Check Exception

Procedural Interrupt

External Interrupt

C

null

787

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The interrupt caused by main memory failure is ( ).

Fault Anomaly

Procedural Interrupt

Hardware Interrupt

External Interrupt

C

null

788

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

The common feature of dual-core CPUs and hyper-threading CPUs is ().

Both have two cores.

Can perform two operations simultaneously

Both contain two CPUs.

There will be no competition for resources.

B

null

789

Test

Computer Organization

Central Processing Unit

Multiple-choice

Knowledge

English

Among the following statements about dual-core technology, the correct one is ( ).

Dual-core refers to a motherboard with two CPUs.

Dual-core is achieved through the use of Hyper-Threading technology.

Dual-core refers to the integration of two processing cores on a CPU.

Dual-core CPU is a form of parallel computing based on time parallelism.

C

null

790

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Among the following statements about the Program Counter (PC), the incorrect one is ( ).

The PC always holds the instruction address.

The value of the PC is modified by the CPU during the execution of instructions.

During a jump instruction, the value of the PC is always changed to the target address of the jump instruction.

The bit size of a PC generally matches the number of bits in the Memory Address Register (MAR).

C

The PC holds the address of the next instruction to be executed, so option A is correct. The value of the PC is modified during the execution of instructions by the CPU (specifically at the end of the fetch cycle), either by incrementing or by jumping to a certain part of the program, so option B is correct. When a jump instruction is executed, it is necessary to determine whether the jump is successful; if it is, the PC is changed to the target address of the jump instruction, otherwise, the address of the next instruction remains the address after the PC is incremented, so option C is incorrect. The PC has the same number of bits as the MAR, so option D is correct.

791

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Among the following concepts about computer systems, the correct one(s) is (are) ( ). I. The CPU does not include an address decoder II. The program counter in the CPU stores the operand address III. The component in the CPU that determines the order of instruction execution is the program counter IV. The status register of the CPU is completely transparent to the user.

I, III

III, IV

II, III, IV

I, III, IV

A

The address decoder is a component of memory storage such as main memory, not a part of the CPU, I is correct. The program counter in the CPU holds the address of the next instruction, not the address of the operand, II is incorrect. The program counter determines the execution order of the program, III is correct. The status register is opaque to the user, IV is correct.

792

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

The following statement about the machine cycle is incorrect ( ).

A machine cycle is typically defined as the time taken to access the main memory or I/O once through a single bus transaction.

An instruction cycle typically consists of multiple machine cycles.

The number of machine cycles contained in different instruction cycles may vary.

Each instruction cycle includes an interrupt response machine cycle.

D

After the execution cycle of an instruction is completed, the processor will determine whether an interrupt request has occurred, and it will only enter the interrupt cycle if an interrupt request is present.

793

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

The correct description of the indirect addressing cycle is ( ).

The indirect addressing operations for all instructions are identical.

For instructions that use indirect addressing through memory, their operations are all the same.

For memory indirect addressing and register indirect addressing, their operations are different.

None of them are correct.

C

Indirect addressing is divided into single-level indirect addressing, two-level indirect addressing, and multi-level indirect addressing, hence their operations are different; therefore, A and B are incorrect. Memory indirect addressing accesses memory through a formal address, while register indirect addressing accesses memory through the contents of a register; C is correct.

794

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Among the following statements, the correct one is ( ) I. Assuming the instruction length is equal to the machine word length, the instruction fetch cycle is equal to the machine cycle II. Assuming the instruction word length is equal to the storage word length, the instruction fetch cycle is equal to the machine cycle III. The length of the instruction word length has no relation to the machine word length IV. For the convenience of hardware design, the instruction word length is always the same as the storage word length.

II, III

II, III, IV

I, III, IV

I, IV

A

The instruction word length is generally an integer multiple of the storage word length. If the instruction word length is twice the storage word length, it requires two memory accesses, and the instruction fetch cycle is twice the machine cycle. If the instruction word length is equal to the storage word length, then the instruction fetch cycle is equal to the machine cycle; this statement is incorrect. According to the analysis of statement I, it is known that statement II is correct. The instruction word length depends on the length of the opcode, the length of the operand address, and the number of operand addresses, and is not necessarily related to the machine word length. However, for the convenience of hardware design, the instruction word length is generally taken as a byte or an integer multiple of the storage word length, so statement I is correct. According to the analysis of statement I, the instruction word length is generally a byte or an integer multiple of the storage word length, and is not necessarily the same size as the storage word length, therefore statement IV is incorrect. In summary, statements II and III are correct.

795

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

In a combinational logic controller, the formation of micro-operation control signals is mainly related to the ( ) signal.

Instruction opcode and address code

Decode the signal and clock today.

Opcode and Condition Code

State information and conditions

B

The input signals of the CUP originate from the following sources: instruction information generated by the instruction decoder, machine cycle signals and beat signals produced by the timing system, and feedback information from the execution unit, namely flags. The first two are the primary factors.

796

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

In a microprogrammed control unit, the entity that forms the microprogram entry address is ( ).

The address field of a machine instruction

Microinstruction's microaddress code field

operation code field of a machine instruction

Microinstruction's micro-operation code field

C

The common fetch microprogram retrieves machine instructions from the main memory, and the operation code field of the machine instruction indicates the entry addresses (initial microaddresses) of each microprogram.

797

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

The speed of a microprogrammed control unit is slower than that of a hardwired control unit, mainly because ( )

Increased the time to read microinstructions from disk storage.

Increased the time to read microinstructions from main memory.

Increased the time to read micro-instructions from the instruction register.

Increased the time to read microinstructions from the control memory.

D

In microprogram control, microinstructions are stored in the control memory, and the corresponding microinstructions need to be read out during execution, which increases the time consumption.

798

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Compared to a microprogrammed controller, a hardwired controller ( )

The timing system of a hard-wired controller is relatively simple.

The timing system of the microprogrammed controller is relatively simple.

The temporal system complexity of both is the same.

It could be that the timing system of the hardwired controller is simpler, or it could be that the timing system of the microprogrammed controller is simpler.

B

The hardwired controller requires a comprehensive analysis that combines the timing arrangement of each micro-operation to write logical expressions and then design them into logic circuits, making the timing system more complex. In contrast, microprogramming simply executes microinstructions in sequence according to the timing arrangement, making it relatively simpler.

799

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

In a microprogrammed control unit, the relationship between machine instructions and microinstructions is ( ).

Each machine instruction is executed by a microinstruction.

Each machine instruction is now interpreted and executed by a microprogram composed of several microinstructions.

A program composed of several machine instructions can be executed by a microprogram.

Each machine instruction is now executed by a series of microprograms.

B

In a CPU cycle, a combination of micro-operations that implement a certain function constitutes a microinstruction, and an ordered sequence of microinstructions forms a microprogram. The purpose of the microprogram is to implement a corresponding machine instruction.

800

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

In the microprogram control method, the correct statements are ( )I. A processor that uses a microprogram controller is called a microprocessor II. Each machine instruction is interpreted and executed by a microprogram III. In the encoding of microinstructions, the least efficient is the direct encoding method IV. Horizontal microinstructions can fully utilize the parallel structure of the data path.

I, II

II, IV

I, III

III, IV

B

A microprocessor is relative to some larger processors and is not necessarily associated with a microprogrammed controller. Whether a microprogrammed controller or a hardwired controller is used, the CPU of a microcomputer is still a microprocessor, which is incorrect. The design idea of microprogramming is to write each machine instruction as a microprogram, which contains several microinstructions, each corresponding to one or several micro-operations, which is correct. In the direct encoding method, each bit represents a micro-operation and does not require decoding, thus the execution efficiency is the highest, but this method significantly increases the number of bits in the microinstruction, which is incorrect. A horizontal microinstruction can define and execute several parallel basic operations, thus making fuller use of the parallel structure of the data path, which is correct.

801

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Among the following statements, the correct one(s) is (are) ( )I. Compared to hardwired control, microprogrammed control can make the execution of instructions faster.II. If microprogrammed control is used, uPC can replace PC.III. Control memory can be implemented using ROM.IV. Instruction cycle is also known as CPU cycle

I, III

II, III

Only III

I, II, III, IV

C

Microprogram control uses a programming approach to execute instructions, while hardwired control uses a hardware approach, hence the latter is faster, I incorrect. HPC cannot replace PC, as it is merely a register that points to the address of the next microinstruction in a microprogram. Therefore, it cannot possibly know what the next instruction will be after the completion of this microprogram, II incorrect. Since the control signals emitted during the execution of each microinstruction are pre-designed and do not need to be changed, the memory that stores all control signals should be ROM, III correct. Instruction cycle refers to the interval from the start of one instruction to the start of the next, while CPU cycle is the machine cycle, which refers to the time required for each step of instruction execution, IV incorrect.

802

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

The following statement about the "Trap" exception is incorrect ( ).

"Self-trapping" is a specific processing event that is pre-set artificially.

The execution can be entered by either a trap gate or a task gate.

There must be some abnormal situation for "self-trapping" to occur.

"After a trap occurs, the CPU will enter and execute the operating system kernel program."

C

Trap is a special interrupt mechanism set by humans, not generated by certain exceptional conditions. Therefore, option C is incorrect.

803

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

The following statement about exception and interrupt handling is incorrect ( )

Anomaly event detection is conducted by the CPU during the execution of each instruction.

Interrupt request detection is performed by the CPU after the execution of each instruction and before fetching the next instruction.

The processing performed by the CPU after detecting an exception is exactly the same as the processing performed after detecting an interrupt request.

Upon interrupt response, the CPU will disable interrupts, save the breakpoint and program state, and then switch to the corresponding interrupt service routine.

C

The processing performed by the CPU after detecting an exception and after detecting an interrupt request is essentially the same, but there may be some differences. For example, for fault-type exceptions, since the breakpoint is the instruction address where the fault occurred, it is necessary to recalculate the PC value. However, the breakpoint for an interrupt is the address of the next instruction (i.e., the PC value), so there is no need to recalculate the PC value.

804

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Among the following events, the one that does not require an exception handler is ().

Page Fault

Cache miss

Address out of bounds

Division by zero

B

Page faults, address out-of-bounds, and division by zero are all faults that occur during the execution of an instruction, requiring the invocation of the corresponding exception handling routines in the operating system kernel to address them, whereas Cache misses are handled by the CPU hardware and do not require the invocation of an exception handler.

805

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Among the following descriptions of superscalar pipelines, the incorrect one is ( ).

Within a single clock cycle, a pipeline can execute more than one instruction.

An instruction is divided into multiple stages, each executed by different circuit units.

Superscalar architecture achieves simultaneous execution of multiple instructions by incorporating multiple pipelines, essentially trading space for time.

Superscalar pipeline refers to parallel execution of operations.

D

A superscalar pipeline refers to a pipeline that can execute more than one instruction per clock cycle, thus A is correct. An instruction is divided into multiple stages, completed by different circuit units, so B is correct. Superscalar achieves simultaneous execution of multiple processors by incorporating multiple pipelines, essentially trading space for time, hence C is correct. Superscalar pipelines typically include the characteristic of parallel arithmetic operations, therefore D is incorrect.

806

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Among the following descriptions of dynamic pipelines, the correct one is ( ).

A dynamic pipeline refers to a situation where, at the same time, some segments are performing one type of operation while other segments are conducting another type of operation. This is beneficial for improving the efficiency of the pipeline, but it can make pipeline control quite complex.

Dynamic pipeline refers to parallel computational operations.

Dynamic pipeline refers to the parallelism of steps.

Dynamic pipelining refers to the parallel execution of program steps.

A

Dynamic pipeline is in contrast to static pipeline. The connection method between the upper and lower sections of a static pipeline is fixed, whereas the connection method of a dynamic pipeline is variable. Therefore, A is correct.

807

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

A pipelined CPU consists of a series of processing circuits called "stages." The throughput of an m-stage pipeline when stable, compared to the throughput of a CPU with m parallel components, is ( ).

With equivalent throughput capacity

Does not possess equivalent throughput capacity.

Throughput greater than that of the former.

Throughput capacity is less than that of the former.

A

An m-stage pipeline can complete one instruction after one clock cycle, and with each subsequent clock cycle, it can complete another instruction. Meanwhile, m parallel components can complete all m instructions after m clock cycles, which is equivalent to completing one instruction per clock cycle on average. Therefore, the throughput of both is equal, so statement A is correct.

808

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Data hazards in the instruction pipeline can cause pipeline stalls, and ( ) can resolve data dependency issues.

Increase hardware resources

Adopting bypass technology

Employ branch prediction technology.

All of the above are acceptable.

B

There are two methods to deal with data-related issues: one is to suspend the execution of the relevant instructions, that is, to stall the pipeline until the register operands can be correctly read; the other is to use a dedicated data path to directly feed the result into the input of the ALU, which is known as bypassing technique, therefore B is correct.

809

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Which of the following statements about pipeline technology is incorrect ( )?

Superscalar technology requires the configuration of multiple functional units and instruction decoding circuits, etc.

Compared to superscalar and superpipelining technologies, Very Long Instruction Word (VLIW) technology places higher demands on optimizing compilers, without additional hardware requirements.

When the pipeline flows in sequence, only RAW hazards can occur among RAW, WAR, and WAW hazards.

Super-pipelining technology is equivalent to further segmenting the pipeline, thereby increasing the usage frequency of functional units within each cycle.

B

Very Long Instruction Word (VLIW) technology imposes higher requirements on the compiler, but it is hardware-independent, hence A is correct. When the pipeline flows in order, only Read After Write (RAW) hazards can occur, so C is correct. Super-pipelining is the technique of further segmenting the pipeline to increase the utilization of functional units, thus D is correct. Superscalar technology requires the configuration of multiple functional units and instruction decoding circuits, therefore A is correct.

810

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

The following description of Hyper-Threading (HT) technology is correct ( ).

Hyper-threading technology can turn a quad-core Intel Core i7 processor into eight cores.

Hyper-threading is a hardware technology that can significantly enhance system performance, independent of the operating system and application software.

A CPU with hyper-threading technology requires chipset support to leverage its technical advantages.

Each CPU core simulated by hyper-threading has independent resources and operates without interfering with each other.

C

Hyper-threading technology requires the support of the chipset, operating system, and application software to fully realize its advantages, C is correct.

811

Test

Computer Organization

Central Processing Unit

Multiple-choice

Reasoning

English

Among the following descriptions of multi-core CPUs and single-core CPUs, the incorrect one is ( ).

The frequency of the dual-core is 2.4GHz, which means the frequency of each core is also 2.4GHz.

Using a dual-core CPU can reduce the power consumption and size of a computer system.

Multi-core CPUs share a set of memory, allowing for data sharing.

All programs run faster on multi-core CPUs.

D

The statement that all programs run faster on multi-core CPUs is inaccurate, as program performance is influenced by a variety of factors, and not all programs can achieve speed improvements on multi-core CPUs, D is incorrect.

812

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

In the classification of system buses, which type of bus is used for transmitting data information between various functional components, supports bidirectional transmission, and its width is related to the machine word length and storage word length?()

Data Bus

Address Bus

Control Bus

Communication Bus

A

null

813

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

In the four stages of bus operation, which stage involves the master module that needs to use the bus making a request, and the bus arbitration mechanism decides to grant the bus usage rights for the next transmission cycle to one of the applicants?()

Addressing stage

Transmission Stage

End Phase

Application for Allocation Phase

D

null

814

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which bus standard is the latest bus and interface standard that will completely replace the current PCI and AGP, ultimately achieving the unification of bus standards?()

VESA bus

PCI bus

USB bus

PCI-Express (PCI-E)

D

null

815

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which bus standard is used as the standard interface between Data Terminal Equipment (DTE) and Data Communication Equipment (DCE) for serial binary data interchange?()

USB bus

PCMCIA

SCSI

RS-232C bus

D

null

816

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

In the performance metrics of a bus, what is the transmission cycle also known as?()

Bus cycle

Bus bandwidth

Clock frequency

Bus width

A

null

817

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

In the four stages of bus operation, during which stage do the master module and the slave module exchange data, allowing for unidirectional or bidirectional data transfer?()

Addressing stage

Transmission stage

End Phase

Application for Allocation Phase

B

null

818

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which bus standard is used as an independent processor standard between computers and smart devices, suitable for system-level interfaces?()

SATA

IDE bus

RS-232C bus

SCSI

D

null

819

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which bus standard is designed as an interconnect mechanism specifically for highly integrated peripherals, expansion cards, and processor/memory systems, and is considered a local bus?()

PCI-Express (PCI-E)

PCMCIA

ISA bus

EISA bus

A

null

820

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which bus standard is a 32-bit standard for a local computer bus that is used for high-speed transmission of large amounts of active image data?()

SCSI

VESA bus

USB bus

AGP

B

null

821

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which indicator among the bus performance metrics represents the bus data transfer rate, that is, the number of bits of data that can be transferred on the bus per unit of time?()

Bus bandwidth

Bus width

Bus Cycle

Clock frequency

A

null

822

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

In the four stages of bus operation, which stage involves the master module obtaining bus control and issuing a request to use the bus?()

Addressing stage

Transmission stage

End Phase

Application for Allocation Phase

D

null

823

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which bus arbitration method uses an independent request approach, has a fast response time, and offers considerable flexibility in controlling priority order?()

Counter-timed polling method

Distributed Arbitration Method

Independent Request Method

Chained query method

C

null

824

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which bus standard is a common connection line that connects between internal registers of a computer, and between a register and the ALU?()

Data Bus

Address Bus

Control Bus

Communication Bus

A

null

825

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which bus standard is an interface standard used for transmitting audio and sound data, connecting audio devices to computer systems?()

USB bus

PCI bus

IDE bus

AC'97 bus

D

null

826

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Which bus arbitration method centralizes all bus requests and uses a specific arbitration algorithm to make decisions, where components closer to the bus controller have higher priority?()

Counter Timing Query Method

Distributed Arbitration Method

Independent Request Method

Chained query method

D

null

827

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Multiple components connected to the bus ( )

Data can only be sent to the bus in a time-division manner, and can only be received from the bus in a time-division manner.

Data can only be sent to the bus in a time-division manner, but it can be received from the bus simultaneously.

Data can be sent to the bus,but it can be received from the bus simultaneously.

Data can be sent to the bus and can only be received from the bus in a time-division manner.

B

null

828

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

On the bus, at the same moment ( ).

Only one master device can control the bus transfer operation.

There can only be one transfer operation from the device control bus.

There can only be one master device and one slave device controlling the bus transmission operation.

Multiple master devices can control bus transmission operations.

A

null

829

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

In computer systems, the public pathway for information transmission between multiple system components is called a bus. With respect to the nature of the information transmitted, the following ( ) is not information transmitted on the public pathway.

Data Information

Address Information

System Information

Control Information

C

null

830

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

The system bus is used to connect ().

Register and Arithmetic Unit Components

Arithmetic Logic Unit (ALU) and Control Unit (CU) components

CPU, main memory, and peripheral components

Interfaces and external devices

C

null

831

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Computers use a bus structure to facilitate the addition and removal of peripherals, while ( )

Reduce the amount of information transmission

Increase the transmission speed of information

Reduce the number of information transmission lines

Enhance the parallelism of information transmission

C

null

832

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Indirect addressing involves the first memory access information being transmitted to the CPU via the ().

Data Bus

Address Bus

Control Bus

Bus Controller

A

null

833

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

In a single-machine system, the bus system composition of a computer with a triple bus structure is ( ).

On-chip bus, system bus, and communication bus.

Data bus, address bus, and control bus

DMA bus, main memory bus, and I/O bus

ISA bus, VESA bus, and PCI bus.

C

null

834

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

The main memory identifies whether the information is an address or data through ().

Types of Buses

Memory Data Register (MDR)

Memory Address Register (MAR)

Control Unit (CU)

A

null

835

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

The following bus standard that belongs to serial bus is ( ).

PCI

USB

EISA

ISA

B

null

836

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

In modern microcomputer motherboards, the function of adopting local bus technology is ( ).

Conserve the system's total bandwidth

Enhance Anti-Interference Capability

Suppress bus terminal reflection

Form a tightly coupled system

A

null

837

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Transferring data between devices with different speeds, ( )

Synchronous control mode must be adopted.

Asynchronous control methods must be adopted.

You can choose synchronous control mode, or asynchronous control mode.

The response mode must be adopted.

C

null

838

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

The synchronous control mode is ().

Applicable only to CPU-controlled methods

Applicable only to external device control methods

Controlled by a unified timing signal

A method where all instruction execution times are identical.

C

null

839

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

In an asynchronous bus, the transfer operation ( ).

Controlled by the device controller

Controlled by the CPU

Controlled by a unified timing signal

Allocate time on demand

D

null

840

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

The asynchronous communication mode of the bus is ( ).

Neither using a clock signal nor employing a "handshake" signal.

Only clock signals are used, without employing "handshake" signals.

Asynchronous communication, utilizing only "handshake" signals without a clock signal.

Uses both clock signals and "handshake" signals.

C

null

841

Test

Computer Organization

Bus

Multiple-choice

Knowledge

English

Among various asynchronous communication methods, () has the fastest speed.

Interlocking

Semi-interlocking

Non-interlocking

All velocities are equal.

C

null

842

Test

Computer Organization

Bus

Multiple-choice

Reasoning

English

To transmit an uncompressed photo with a resolution of 640x480 pixels and a color depth of 65536, given a data transfer rate of 56kb/s, the approximate time required is ( ).

34.82s

43.86s

85.71s

87.77s

D

The total number of pixels is 307,200 pixels, and each pixel has 65,536 colors (i.e., 16-bit color), so each pixel occupies 2 bytes. Therefore, the total data volume is: 307,200 * 2 = 614,400 bytes = 4,915,200 bits. Thus, the transmission time is: 4,915,200 / 56,000 = 87.77s.

843

Test

Computer Organization

Bus

Multiple-choice

Reasoning

English

A bus has 104 signal lines, of which 32 are data lines (DB). If the bus operates at a frequency of 33MHz, then its theoretical maximum transfer rate is ( ).

33MB/s

64MB/s

132MB/s

164MB/s

C

The calculated theoretical maximum transfer rate is 132MB/s.

844

Test

Computer Organization

Bus

Multiple-choice

Reasoning

English

The I/O device of a certain machine adopts asynchronous serial transmission to transfer character information, with a character information format of 1 start bit, 7 data bits, 1 parity bit, and 1 stop bit. If it is required to transmit 480 characters per second, then the data transfer rate of the device is ( ).

380 b/s

4800 B/s

480 B/s

4800 b/s

D

First, calculate the total number of bits per character: 1 start bit + 7 data bits + 1 parity bit + 1 stop bit = 10 bits. Transmitting 480 characters per second, calculate the total number of bits to be transmitted per second: 480 characters/second × 10 bits/character = 4800 bits/second.

845

Test

Computer Organization

Bus

Multiple-choice

Reasoning

English

During the surgical procedure, the doctor extends their hand, waiting for the nurse to pass the scalpel. Once the doctor has a firm grip, the nurse lets go. If we consider the doctor and nurse as two communication modules, the aforementioned action is equivalent to ( ).

Synchronous Communication

Asynchronous communication with full interlocking.

Semi-interlocking mode of asynchronous communication

Non-interlocked Asynchronous Communication

B

The actions of doctors and nurses conform to the full interlocking mode of asynchronous communication.

846

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

What are the three components that make up the average access time of a disk?()

Seek time, rotational latency, data transmission time

Transmission time, read time, write time

Rotational latency, seek time, data caching time

Transmission time, rotational latency, DMA time

A

null

847

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

In the basic structure of the I/O interface, the internal interface is connected to the system bus. What is the data transfer method?()

Parallel transmission

Serial transmission

DMA transfer

Channel Transmission

A

null

848

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

Which addressing mode for I/O ports treats I/O ports as memory unit locations for address allocation, eliminating the need for specialized I/O instructions?()

Unified Addressing Method

Independent Addressing Mode

Unified read-write method

Memory Mapping Method

A

null

849

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

In interrupt programming, what is a non-maskable interrupt (NMI)?()

Interrupts caused by components other than the processor and memory

Interrupts generated within the processor and memory

A software interrupt

an inside interrupt

A

null

850

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

One of the main differences between DMA mode and interrupt mode is what?()

DMA mode requires program switching, while interrupt mode does not.

DMA mode only occupies a small portion of CPU time, while interrupt mode occupies CPU resources throughout the entire process.

DMA mode responds slower.

DMA mode is only suitable for high-speed peripherals.

B

null

851

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

Which type of I/O interface connects to peripherals via an interface cable, and may use serial transmission for data transfer?()

I/O port

Internal Interface

External Interface

Data Interface

C

null

852

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

What does the interrupt vector address refer to?()

Interrupt Service Routine entry address

Priority of Interrupt Requests

The address of the interrupt source

Interrupt Controller Address

A

null

853

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

What type of error-correcting code is used in the RAID 2 scheme of RAID to enhance data fault tolerance?()

Hamming code

Parity Check Code

List code

Mirror code

A

null

854

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

Which function of the I/O interface is used to implement address decoding and device selection?()

Perform data buffering

Implement communication and control between the host and peripherals.

Transmit control commands and status information.

Perform address decoding and device selection.

D

null

855

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

In computers, what is an I/O port?()

Register for storing data from I/O devices

Direct data path between CPU and I/O devices

Registers that can be directly accessed by the CPU, used for reading and writing data.

Cable that controls data transfer between the CPU and I/O devices

C

null

856

Test

Computer Organization

Input/Output System

Multiple-choice

Knowledge

English

What does seek time refer to in the average access time of a hard drive?()

Time spent on data transmission

The time it takes for the read/write head to move to the target track

Time for disk to position to the relevant sector

The time it takes for a hard disk to make one rotation.

B

null