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jotego/jt12 | hdl/jt03_acc.v | 2,033 | module MODULE1
(
input rst,
input clk,
input VAR7 ,
input signed [13:0] VAR4,
input VAR15,
input VAR3,
input VAR9,
input VAR6,
input VAR16,
input [2:0] VAR14,
output signed [15:0] VAR12
);
reg VAR5;
always @(*) begin
case ( VAR14 )
default: VAR5 = VAR6;
3'd4: VAR5 = VAR3 | VAR6;
3'd5,3'd6: VAR5 = ~VAR15;
3'd7: VAR5 = 1'b1;
endcase
end
localparam VAR13=18;
wire [VAR13-1:0] VAR2;
assign VAR12 = VAR2[VAR13-1:VAR13-16];
VAR10 #(.VAR8(14),.VAR1(VAR13)) VAR11(
.clk ( clk ),
.VAR7 ( VAR7 ),
.VAR4 ( VAR4 ),
.VAR5 ( VAR5 ),
.VAR16 ( VAR16 ),
.VAR12 ( VAR2 )
);
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkTimeClient.v | 4,245 | module MODULE1(VAR32,
VAR37,
VAR15,
VAR29,
VAR21,
VAR11,
VAR16,
VAR8,
VAR33,
VAR6,
VAR30,
VAR9);
input VAR32;
input VAR37;
input VAR15;
input VAR29;
input VAR21;
input VAR11;
input [63 : 0] VAR16;
input VAR8;
output VAR33;
output [66 : 0] VAR6;
input VAR30;
input VAR9;
wire [66 : 0] VAR6;
wire VAR33;
wire VAR31,
VAR17,
VAR28;
reg [66 : 0] VAR39;
wire [66 : 0] VAR13;
wire VAR27;
reg VAR36;
wire VAR23, VAR19;
reg VAR10;
wire VAR34, VAR12;
wire [63 : 0] VAR35, VAR18;
wire VAR41, VAR22;
assign VAR33 = VAR22 ;
assign VAR6 = VAR10 ? 67'h0AAAAAAAAAAAAAAAA : VAR39 ;
VAR25 #(.VAR40(32'd64), .VAR2(64'd0)) VAR5(.VAR20(VAR32),
.VAR26(VAR15),
.VAR7(VAR37),
.VAR38(VAR18),
.VAR14(VAR41),
.VAR24(VAR35),
.VAR1(VAR22));
assign VAR31 = 1'd1 ;
assign VAR17 = VAR9 ;
assign VAR28 = VAR30 ;
assign VAR13 = { 3'd1, VAR35 } ;
assign VAR27 = 1'd1 ;
assign VAR23 = VAR9 ;
assign VAR19 = 1'd1 ;
assign VAR34 = VAR30 ;
assign VAR12 = 1'd1 ;
assign VAR18 = VAR16 ;
assign VAR41 = VAR8 ;
always@(posedge VAR15)
begin
if (VAR29 == VAR4)
begin
VAR39 <= VAR3 67'd0;
VAR36 <= VAR3 1'd0;
VAR10 <= VAR3 1'd1;
end
else
begin
if (VAR27)
VAR39 <= VAR3 VAR13;
if (VAR19)
VAR36 <= VAR3 VAR23;
if (VAR12)
VAR10 <= VAR3 VAR34;
end
end
begin
VAR39 = 67'h2AAAAAAAAAAAAAAAA;
VAR36 = 1'h0;
VAR10 = 1'h0;
end | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtp/sky130_fd_sc_ls__dfrtp.behavioral.pp.v | 2,243 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR18 ,
VAR1,
VAR15 ,
VAR9 ,
VAR20 ,
VAR6
);
output VAR8 ;
input VAR2 ;
input VAR18 ;
input VAR1;
input VAR15 ;
input VAR9 ;
input VAR20 ;
input VAR6 ;
wire VAR5 ;
wire VAR12 ;
reg VAR13 ;
wire VAR14 ;
wire VAR3;
wire VAR11 ;
wire VAR7 ;
wire VAR16 ;
wire VAR21 ;
not VAR4 (VAR12 , VAR3 );
VAR17 VAR19 (VAR5 , VAR14, VAR11, VAR12, VAR13, VAR15, VAR9);
assign VAR7 = ( VAR15 === 1'b1 );
assign VAR16 = ( VAR7 && ( VAR3 === 1'b1 ) );
assign VAR21 = ( VAR7 && ( VAR1 === 1'b1 ) );
buf VAR10 (VAR8 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.symbol.v | 1,438 | module MODULE1 (
input VAR3 ,
output VAR1 ,
input VAR5 ,
input VAR2,
input VAR4 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi_4.v | 2,450 | module MODULE2 (
VAR9 ,
VAR7 ,
VAR10 ,
VAR1 ,
VAR12 ,
VAR3 ,
VAR6,
VAR4,
VAR5 ,
VAR2
);
output VAR9 ;
input VAR7 ;
input VAR10 ;
input VAR1 ;
input VAR12 ;
input VAR3 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR2 ;
VAR11 VAR8 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR9 ,
VAR7,
VAR10,
VAR1,
VAR12,
VAR3
);
output VAR9 ;
input VAR7;
input VAR10;
input VAR1;
input VAR12;
input VAR3;
supply1 VAR6;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR2 ;
VAR11 VAR8 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4b/sky130_fd_sc_ms__nor4b.pp.blackbox.v | 1,341 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR9 ,
VAR4 ,
VAR2 ,
VAR8,
VAR5,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR2 ;
input VAR8;
input VAR5;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
rhalstea/cidr_15_fpga_join | probe_engine/verilog/engine.v | 4,976 | module MODULE1 (
input clk,
input rst,
output VAR46,
input [63:0] VAR19,
input [63:0] VAR49,
input [63:0] VAR35,
input [63:0] VAR4, input [63:0] VAR45,
input VAR42,
output VAR53,
output [47:0] VAR5,
output VAR31,
input VAR1,
input [63:0] VAR47,
input VAR58,
output VAR21,
output [47:0] VAR52,
output VAR41,
input VAR27,
input [63:0] VAR56,
input VAR48,
output VAR24,
output [47:0] VAR36,
output VAR30,
input VAR37,
input [63:0] VAR55,
input VAR57,
output VAR34,
output [47:0] VAR25,
output VAR11,
input VAR2,
input [63:0] VAR13,
output VAR38,
input VAR51,
output [63:0] VAR6,
output [63:0] VAR39
);
wire VAR43;
wire VAR9;
wire VAR8;
wire [63:0] VAR7;
wire [63:0] VAR54;
wire [47:0] VAR16;
wire VAR28;
wire VAR23;
wire [47:0] VAR12;
wire [47:0] VAR32;
wire VAR33;
wire VAR15;
wire [63:0] VAR22;
wire [63:0] VAR26;
VAR17 VAR20 (
.clk (clk),
.rst (rst),
.VAR46 (VAR43),
.VAR19 (VAR19),
.VAR49 (VAR49),
.VAR35 (VAR35),
.VAR4 (VAR4),
.VAR45 (VAR45),
.VAR38 (VAR9),
.VAR51 (VAR8),
.VAR50 (VAR7),
.VAR18 (VAR54),
.VAR42 (VAR42),
.VAR53 (VAR53),
.VAR5 (VAR5),
.VAR31 (VAR31),
.VAR1 (VAR1),
.VAR47 (VAR47)
);
assign VAR8 = !VAR9 && !VAR23;
VAR44 VAR29 (
.clk (clk),
.rst (rst),
.VAR46 (VAR28),
.VAR40 (VAR23),
.VAR3 (VAR8),
.VAR14 (VAR7),
.VAR10 (VAR54),
.VAR58 (VAR58),
.VAR21 (VAR21),
.VAR52 (VAR52),
.VAR41 (VAR41),
.VAR27 (VAR27),
.VAR56 (VAR56),
.VAR48 (VAR48),
.VAR24 (VAR24),
.VAR36 (VAR36),
.VAR30 (VAR30),
.VAR37 (VAR37),
.VAR55 (VAR55),
.VAR57 (VAR57),
.VAR34 (VAR34),
.VAR25 (VAR25),
.VAR11 (VAR11),
.VAR2 (VAR2),
.VAR13 (VAR13),
.VAR38 (VAR38),
.VAR51 (VAR51),
.VAR6 (VAR6),
.VAR39 (VAR39)
);
assign VAR46 = VAR43 && VAR28;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai.pp.symbol.v | 1,319 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR3 ,
output VAR1 ,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
rhalstea/cidr_15_fpga_join | probe_engine/verilog/probe_phase.v | 5,150 | module MODULE1 (
input clk,
input rst,
output VAR42,
output VAR59,
input VAR20,
input [63:0] VAR51,
input [63:0] VAR16,
input VAR55,
output VAR40,
output [47:0] VAR43,
output VAR52,
input VAR15,
input [63:0] VAR31,
input VAR6,
output VAR25,
output [47:0] VAR44,
output VAR57,
input VAR29,
input [63:0] VAR37,
input VAR35,
output VAR5,
output [47:0] VAR2,
output VAR19,
input VAR39,
input [63:0] VAR17,
output VAR12,
input VAR24,
output [63:0] VAR21,
output [63:0] VAR56
);
wire [1:0] VAR1;
wire VAR30;
wire VAR47;
wire [63:0] VAR27;
wire [63:0] VAR60;
wire [1:0] VAR18;
wire VAR32;
wire [63:0] VAR3;
wire [63:0] VAR58;
wire VAR36;
wire VAR8;
VAR11 VAR45 (
.clk (clk),
.rst (rst),
.VAR53 (VAR1),
.VAR54 ({VAR20, VAR20}),
.VAR48 (VAR51),
.VAR13 (VAR16),
.VAR4 (VAR30),
.VAR14 (VAR47),
.VAR50 (VAR27),
.VAR9 (VAR60)
);
assign VAR59 = (VAR1 != 2'd0);
assign VAR47 = !VAR30 && !VAR55 && !VAR18[1];
assign VAR40 = VAR47;
assign VAR43 = VAR60[47:0];
VAR11 VAR41 (
.clk (clk),
.rst (rst),
.VAR53 (VAR18),
.VAR54 ({VAR47, VAR15}),
.VAR48 (VAR27),
.VAR13 (VAR31),
.VAR4 (VAR32),
.VAR14 (VAR36),
.VAR50 (VAR3),
.VAR9 (VAR58)
);
assign VAR52 = VAR18[0];
wire VAR49;
VAR34 VAR23 (
.clk (clk),
.rst (rst),
.VAR42 (VAR49),
.VAR7 (VAR47),
.VAR26 (VAR15)
);
VAR22 VAR46 (
.clk (clk),
.rst (rst),
.VAR42 (VAR8),
.VAR33 (VAR32),
.VAR28 (VAR36),
.VAR38 (VAR3),
.VAR10 (VAR58),
.VAR6 (VAR6),
.VAR25 (VAR25),
.VAR44 (VAR44),
.VAR57 (VAR57),
.VAR29 (VAR29),
.VAR37 (VAR37),
.VAR35 (VAR35),
.VAR5 (VAR5),
.VAR2 (VAR2),
.VAR19 (VAR19),
.VAR39 (VAR39),
.VAR17 (VAR17),
.VAR12 (VAR12),
.VAR24 (VAR24),
.VAR21 (VAR21),
.VAR56 (VAR56)
);
assign VAR42 = VAR30 && VAR32 && VAR49 && VAR8;
endmodule | bsd-3-clause |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/tx_engine_ultrascale.v | 12,315 | module MODULE1
parameter VAR84 = 1,
parameter VAR82 = 0,
parameter VAR50 = 64)
( input VAR7,
input VAR42, input VAR33, output VAR1,
output VAR73,
input [VAR65-1:0] VAR64,
input VAR83,
output VAR61,
output VAR67,
output [VAR34-1:0] VAR28,
output [(VAR34/32)-1:0] VAR24,
output [VAR66-1:0] VAR35,
input VAR41,
input [VAR34-1:0] VAR20,
input VAR43,
input [VAR58(VAR34/32)-1:0] VAR13,
input VAR22,
input [VAR58(VAR34/32)-1:0] VAR49,
output VAR69,
input VAR40,
input [VAR74-1:0] VAR75,
input [VAR19-1:0] VAR30,
input [VAR45-1:0] VAR47,
input [VAR26-1:0] VAR32,
input [VAR44-1:0] VAR63,
input [VAR15-1:0] VAR9,
input [VAR16-1:0] VAR12,
input [VAR56-1:0] VAR76,
input [VAR80-1:0] VAR70,
input [VAR10-1:0] VAR52,
input VAR11,
output VAR17,
output VAR48,
input VAR39,
output VAR77,
output VAR6,
output [VAR34-1:0] VAR55,
output [(VAR34/32)-1:0] VAR8,
output [VAR72-1:0] VAR51,
input VAR2,
input [VAR34-1:0] VAR62,
input VAR60,
input [VAR58(VAR34/32)-1:0] VAR29,
input VAR18,
input [VAR58(VAR34/32)-1:0] VAR27,
output VAR38,
input VAR23,
input [VAR74-1:0] VAR5,
input [VAR19-1:0] VAR46,
input [VAR54-1:0] VAR21,
input [VAR44-1:0] VAR36,
input [VAR16-1:0] VAR59,
input [VAR80-1:0] VAR79,
input [VAR10-1:0] VAR31,
input [VAR26-1:0] VAR25,
input VAR81,
output VAR3,
output VAR37
);
localparam VAR57 = 10;
reg VAR78;
reg VAR71;
assign VAR48 = VAR78;
assign VAR37 = VAR71;
always @(posedge VAR7) begin
VAR78 <= VAR67 & VAR61 & VAR83;
VAR71 <= VAR6 & VAR77 & VAR39;
end
VAR14
.VAR34 (VAR34),
.VAR84 (VAR84),
.VAR82 (VAR82),
.VAR57 (VAR57),
.VAR50 (VAR50))
VAR4
(
.VAR73 (VAR73),
.VAR77 (VAR77),
.VAR6 (VAR6),
.VAR55 (VAR55[VAR34-1:0]),
.VAR8 (VAR8[(VAR34/32)-1:0]),
.VAR51 (VAR51[VAR72-1:0]),
.VAR38 (VAR38),
.VAR3 (VAR3),
.VAR7 (VAR7),
.VAR42 (VAR42),
.VAR33 (VAR33),
.VAR64 (VAR64[VAR65-1:0]),
.VAR39 (VAR39),
.VAR2 (VAR2),
.VAR62 (VAR62[VAR34-1:0]),
.VAR60 (VAR60),
.VAR29 (VAR29[VAR58(VAR34/32)-1:0]),
.VAR18 (VAR18),
.VAR27 (VAR27[VAR58(VAR34/32)-1:0]),
.VAR23 (VAR23),
.VAR5 (VAR5[VAR74-1:0]),
.VAR46 (VAR46[VAR19-1:0]),
.VAR21 (VAR21[VAR54-1:0]),
.VAR36 (VAR36[VAR44-1:0]),
.VAR59 (VAR59[VAR16-1:0]),
.VAR79 (VAR79[VAR80-1:0]),
.VAR31 (VAR31[VAR10-1:0]),
.VAR25 (VAR25[VAR26-1:0]),
.VAR81 (VAR81));
VAR53
.VAR34 (VAR34),
.VAR84 (VAR84),
.VAR82 (VAR82),
.VAR57 (VAR57),
.VAR50 (VAR50))
VAR68
(
.VAR1 (VAR1),
.VAR61 (VAR61),
.VAR67 (VAR67),
.VAR28 (VAR28[VAR34-1:0]),
.VAR24 (VAR24[(VAR34/32)-1:0]),
.VAR35 (VAR35[VAR66-1:0]),
.VAR69 (VAR69),
.VAR17 (VAR17),
.VAR7 (VAR7),
.VAR42 (VAR42),
.VAR33 (VAR33),
.VAR64 (VAR64[VAR65-1:0]),
.VAR83 (VAR83),
.VAR41 (VAR41),
.VAR20 (VAR20[VAR34-1:0]),
.VAR43 (VAR43),
.VAR13 (VAR13[VAR58(VAR34/32)-1:0]),
.VAR22 (VAR22),
.VAR49 (VAR49[VAR58(VAR34/32)-1:0]),
.VAR40 (VAR40),
.VAR75 (VAR75[VAR74-1:0]),
.VAR30 (VAR30[VAR19-1:0]),
.VAR47 (VAR47[VAR45-1:0]),
.VAR32 (VAR32[VAR26-1:0]),
.VAR63 (VAR63[VAR44-1:0]),
.VAR9 (VAR9[VAR15-1:0]),
.VAR12 (VAR12[VAR16-1:0]),
.VAR76 (VAR76[VAR56-1:0]),
.VAR70 (VAR70[VAR80-1:0]),
.VAR52 (VAR52[VAR10-1:0]),
.VAR11 (VAR11));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2/sky130_fd_sc_hd__mux2.symbol.v | 1,322 | module MODULE1 (
input VAR8,
input VAR6,
output VAR2 ,
input VAR7
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3.blackbox.v | 1,288 | module MODULE1 (
VAR8,
VAR6,
VAR1,
VAR2
);
output VAR8;
input VAR6;
input VAR1;
input VAR2;
supply1 VAR5;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_srams.v | 3,948 | module MODULE1(
input VAR1,
input VAR21,
input VAR16,
input VAR18,
input [VAR5-1:0] VAR11,
input [VAR38-1:0] VAR3,
input [VAR6-1:0] VAR14,
output [VAR6-1:0] VAR19,
input VAR17,
input VAR37,
input VAR13,
input VAR42,
input VAR23,
input VAR12,
input [VAR30-1:0] VAR31,
input [VAR25-1:0] VAR34,
input [VAR33-1:0] VAR10,
output [VAR33-1:0] VAR24,
input VAR29,
input VAR8,
input VAR4
);
VAR41 VAR36 (
.VAR40 (VAR28),
.VAR27 (VAR1),
.VAR20 (VAR21),
.VAR32 (VAR16 ),
.VAR2 (VAR18 ),
.addr (VAR11 ),
.VAR26 (VAR3 ),
.din (VAR14 ),
.dout (VAR7 ),
.VAR35(VAR37 ),
.clk (VAR17 )
);
assign VAR19 = VAR7;
VAR39 VAR9 (
.VAR40 (VAR22),
.VAR27 (VAR13),
.VAR20 (VAR42),
.VAR32 (VAR23 ),
.VAR2 (VAR12 ),
.addr (VAR31 ),
.VAR26 (VAR34 ),
.din (VAR10 ),
.dout (VAR15 ),
.VAR35(VAR8 ),
.clk (VAR29 )
);
assign VAR24 = VAR15;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi.pp.blackbox.v | 1,391 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR8 ,
VAR9 ,
VAR7 ,
VAR1,
VAR4,
VAR3 ,
VAR5
);
output VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/cdp/rule_32_30_bb.v | 5,571 | module MODULE1 (
VAR3,
VAR5,
VAR6,
VAR4,
VAR1,
VAR7,
VAR2);
input VAR3;
input VAR5;
input [29:0] VAR6;
input VAR4;
input VAR1;
output [29:0] VAR7;
output [4:0] VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22o/sky130_fd_sc_ms__a22o_2.v | 2,339 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR2 ,
VAR4 ,
VAR9 ,
VAR7,
VAR6,
VAR8 ,
VAR1
);
output VAR3 ;
input VAR11 ;
input VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR7;
input VAR6;
input VAR8 ;
input VAR1 ;
VAR10 VAR5 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3 ,
VAR11,
VAR2,
VAR4,
VAR9
);
output VAR3 ;
input VAR11;
input VAR2;
input VAR4;
input VAR9;
supply1 VAR7;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR1 ;
VAR10 VAR5 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule | apache-2.0 |
ak-fau/fpga-cyclone_iv | bemicro/sys_pll_bb.v | 11,209 | module MODULE1 (
VAR3,
VAR2,
VAR1,
VAR4);
input VAR3;
input VAR2;
output VAR1;
output VAR4;
tri0 VAR3;
endmodule | bsd-2-clause |
glennchid/font5-firmware | src/verilog/synthesis/Combiner.v | 2,379 | module MODULE1(
input clk,
input signed [15:0] din,
input VAR5,
input VAR12,
output signed [15:0] dout
);
parameter real VAR6 = 357e6; parameter real VAR2 = 280e-9;
localparam integer VAR11 = VAR3(VAR6 * VAR2);
localparam [VAR11-1:0] VAR10 = (VAR6 * VAR2);
reg signed [17:0] VAR9 [0:VAR10-1];
integer VAR1, VAR8;
VAR7 for (VAR1=0; VAR1 < VAR10; VAR1=VAR1+1) VAR9[VAR1] = 18'h00000;
wire signed [17:0] VAR4 = (VAR12) ? {din, 2'b00} : {{2{din[15]}}, din} + VAR9[VAR10-1];
always @(posedge clk) begin
VAR9[0] <= (VAR5) ? VAR4 : 18'h00000; for (VAR8=VAR10-1; VAR8 > 0; VAR8=VAR8-1) VAR9[VAR8] <= VAR9[VAR8-1]; end
assign dout = VAR9[1][17:2];
endmodule | gpl-3.0 |
titorgalaxy/Titor | rtl/verilog/util/StripedDualMemory.v | 7,484 | module MODULE1(
VAR16,
VAR10,
VAR28,
VAR23,
VAR49,
VAR41,
VAR43,
VAR21,
VAR12,
VAR36,
VAR46,
VAR25,
clk,
reset
);
parameter VAR1 = VAR15;
output reg [VAR33-1:0] VAR16;
input [VAR33-1:0] VAR10;
input [VAR33-1:0] VAR28;
input [VAR27-1:0] VAR23; input VAR49;
input VAR41;
output reg [VAR33-1:0] VAR43;
input [VAR33-1:0] VAR21;
input [VAR33-1:0] VAR12;
input [VAR27-1:0] VAR36; input VAR46;
input VAR25;
input clk;
input reset;
wire [VAR33-1:0] VAR26 [VAR20-1:0];
reg [VAR33-1:0] VAR8 [VAR20-1:0];
reg [VAR33-1:0] VAR48 [VAR20-1:0];
reg [VAR27-1:0] VAR29 [VAR20-1:0];
reg VAR39 [VAR20-1:0];
reg VAR2 [VAR20-1:0];
wire [VAR33-1:0] VAR45 [VAR20-1:0];
reg [VAR33-1:0] VAR11 [VAR20-1:0];
reg [VAR33-1:0] VAR5 [VAR20-1:0];
reg [VAR27-1:0] VAR19 [VAR20-1:0];
reg VAR24 [VAR20-1:0];
reg VAR6 [VAR20-1:0];
reg [VAR27-1:0] VAR35;
reg [VAR27-1:0] VAR30;
reg [VAR27-1:0] VAR44 [VAR20-1:0];
reg [VAR33-1:0] VAR38 [VAR20-1:0];
reg [VAR27-1:0] VAR13 [VAR20-1:0];
reg [VAR27-1:0] VAR34 [VAR20-1:0];
reg [VAR18-1:0] VAR7 [VAR20-1:0];
reg [VAR27-1:0] VAR40;
reg [VAR27-1:0] VAR14 [VAR20-1:0];
reg [VAR27-1:0] VAR4;
reg [VAR27-1:0] VAR42;
reg [VAR27-1:0] VAR37 [VAR20-1:0];
reg [VAR33-1:0] VAR22 [VAR20-1:0];
reg [VAR27-1:0] VAR31 [VAR20-1:0];
reg [VAR27-1:0] VAR32 [VAR20-1:0];
reg [VAR18-1:0] VAR17 [VAR20-1:0];
reg [VAR27-1:0] VAR47;
reg [VAR27-1:0] VAR9 [VAR20-1:0];
always @(posedge clk) begin
if(reset) begin VAR40 <= 0; end
else begin VAR40 <= VAR23; end
if(reset) begin VAR47 <= 0; end
else begin VAR47 <= VAR36; end
end
always @ begin
VAR48[VAR3] <= VAR38[VAR3];
VAR39[VAR3] <= VAR49;
VAR2[VAR3] <= VAR41 && (
(VAR35 <= VAR30) ?
((VAR35<=VAR3) && (VAR3<=VAR30)) :
((VAR35<=VAR3) || (VAR3<=VAR30))
);
VAR29[VAR3] <= 0;
VAR44[VAR3] <= VAR35 <= VAR3 ? VAR3-VAR35 : (VAR20-VAR35)+VAR3;
VAR38[VAR3] <= (VAR28+VAR44[VAR3]) / VAR20;
VAR8[VAR3] <= VAR7[VAR13[VAR3]];
VAR13[VAR3] <= (VAR3 + VAR20 - VAR35) % VAR20;
VAR34[VAR3] <= (VAR3 + VAR20 + VAR35) % VAR20;
VAR7[VAR3] <= VAR10[ (VAR18*(VAR3+1))-1 : (VAR18*(VAR3+0)) ];
VAR16[ (VAR18*(VAR3+1))-1 : (VAR18*(VAR3+0))-0 ] <= (VAR3<=VAR40) ? VAR26[VAR14[VAR3]] : 0;
VAR5[VAR3] <= VAR22[VAR3];
VAR24[VAR3] <= VAR46;
VAR6[VAR3] <= VAR25 && (
(VAR4 <= VAR42) ?
((VAR4<=VAR3) && (VAR3<=VAR42)) :
((VAR4<=VAR3) || (VAR3<=VAR42))
);
VAR19[VAR3] <= 0;
VAR37[VAR3] <= VAR4 <= VAR3 ? VAR3-VAR4 : (VAR20-VAR4)+VAR3;
VAR22[VAR3] <= (VAR12+VAR37[VAR3]) / VAR20;
VAR11[VAR3] <= VAR17[VAR31[VAR3]];
VAR31[VAR3] <= (VAR3 + VAR20 - VAR4) % VAR20;
VAR32[VAR3] <= (VAR3 + VAR20 + VAR4) % VAR20;
VAR17[VAR3] <= VAR21[ (VAR18*(VAR3+1))-1 : (VAR18*(VAR3+0)) ];
VAR43[ (VAR18*(VAR3+1))-1 : (VAR18*(VAR3+0))-0 ] <= (VAR3<=VAR47) ? VAR45[VAR9[VAR3]] : 0;
end
always @(posedge clk) begin
if(reset) begin VAR14[VAR3] <= 0; end
else begin VAR14[VAR3] <= VAR34[VAR3]; end
if(reset) begin VAR9[VAR3] <= 0; end
else begin VAR9[VAR3] <= VAR32[VAR3]; end
end
end
endgenerate
endmodule | gpl-3.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_SW.v | 1,861 | module MODULE1 (
address,
clk,
VAR3,
VAR2,
VAR5
)
;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input clk;
input [ 3: 0] VAR3;
input VAR2;
wire VAR4;
wire [ 3: 0] VAR6;
wire [ 3: 0] VAR1;
reg [ 31: 0] VAR5;
assign VAR4 = 1;
assign VAR1 = {4 {(address == 0)}} & VAR6;
always @(posedge clk or negedge VAR2)
begin
if (VAR2 == 0)
VAR5 <= 0;
end
else if (VAR4)
VAR5 <= {32'b0 | VAR1};
end
assign VAR6 = VAR3;
endmodule | mit |
zhangly/azpr_cpu | rtl/cpu/rtl/if_stage.v | 4,119 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR1] VAR8, output wire [VAR32] VAR24, output wire VAR15, output wire VAR17, output wire [VAR1] VAR28,
input wire [VAR1] VAR21, input wire VAR4, input wire VAR5, output wire VAR13, output wire [VAR32] VAR31, output wire VAR33, output wire VAR14, output wire [VAR1] VAR9,
input wire VAR6, input wire VAR7, input wire [VAR32] VAR30, input wire VAR34, input wire [VAR32] VAR19, output wire VAR20,
output wire [VAR32] VAR25, output wire [VAR1] VAR2, output wire VAR23 );
wire [VAR1] VAR26;
VAR18 VAR18 (
.clk (clk), .reset (reset),
.VAR6 (VAR6), .VAR7 (VAR7), .VAR20 (VAR20),
.addr (VAR25), .VAR27 (VAR3), .VAR22 (VAR11), .VAR10 (VAR29'h0), .VAR12 (VAR26),
.VAR8 (VAR8), .VAR24 (VAR24), .VAR15 (VAR15), .VAR17 (VAR17), .VAR28 (VAR28),
.VAR21 (VAR21), .VAR4 (VAR4), .VAR5 (VAR5), .VAR13 (VAR13), .VAR31 (VAR31), .VAR33 (VAR33), .VAR14 (VAR14), .VAR9 (VAR9) );
VAR16 VAR16 (
.clk (clk), .reset (reset),
.VAR26 (VAR26),
.VAR6 (VAR6), .VAR7 (VAR7), .VAR30 (VAR30), .VAR34 (VAR34), .VAR19 (VAR19),
.VAR25 (VAR25), .VAR2 (VAR2), .VAR23 (VAR23) );
endmodule | mit |
osecpu/fpga | alu.v | 1,647 | module MODULE2(VAR1, VAR4, dout, VAR5, VAR3);
input signed [31:0] VAR1, VAR4;
output signed [31:0] dout;
input[3:0] VAR5;
input VAR3;
assign dout = VAR2(VAR5, VAR1, VAR4);
function signed [31:0] VAR2(input [3:0] VAR5, input signed [31:0] VAR1, input signed [31:0] VAR4);
if(VAR3 == 0) begin
case (VAR5)
default: VAR2 = 0;
endcase
end
else begin
case (VAR5)
default: VAR2 = 0;
endcase
end
endfunction
endmodule
module MODULE1();
reg signed [31:0] VAR1, VAR4;
reg signed [3:0] VAR5;
wire signed [31:0] dout;
MODULE2 MODULE1(VAR1, VAR4, dout, VAR5); | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4.functional.v | 1,337 | module MODULE1 (
VAR4,
VAR1,
VAR5,
VAR3,
VAR8
);
output VAR4;
input VAR1;
input VAR5;
input VAR3;
input VAR8;
wire VAR6;
nor VAR2 (VAR6, VAR1, VAR5, VAR3, VAR8 );
buf VAR7 (VAR4 , VAR6 );
endmodule | apache-2.0 |
olofk/wb_intercon | rtl/verilog/wb_mux.v | 4,682 | module MODULE1
parameter [VAR22*VAR37-1:0] VAR30 = 0)
(input VAR40,
input VAR8,
input [VAR37-1:0] VAR28,
input [VAR18-1:0] VAR4,
input [3:0] VAR38,
input VAR5,
input VAR6,
input VAR27,
input [2:0] VAR13,
input [1:0] VAR21,
output [VAR18-1:0] VAR14,
output VAR23,
output VAR11,
output VAR35,
output [VAR22*VAR37-1:0] VAR16,
output [VAR22*VAR18-1:0] VAR17,
output [VAR22*4-1:0] VAR29,
output [VAR22-1:0] VAR7,
output [VAR22-1:0] VAR31,
output [VAR22-1:0] VAR33,
output [VAR22*3-1:0] VAR34,
output [VAR22*2-1:0] VAR19,
input [VAR22*VAR18-1:0] VAR20,
input [VAR22-1:0] VAR3,
input [VAR22-1:0] VAR15,
input [VAR22-1:0] VAR1);
parameter VAR32 = VAR22 > 1 ? VAR12(VAR22) : 1;
reg VAR39;
wire [VAR32-1:0] VAR26;
wire [VAR22-1:0] VAR10;
genvar VAR9;
generate
for(VAR9=0; VAR9<VAR22 ; VAR9=VAR9+1) begin : VAR24
assign VAR10[VAR9] = (VAR28 & VAR30[VAR9*VAR37+:VAR37]) == VAR25[VAR9*VAR37+:VAR37];
end
endgenerate
function [VAR32-1:0] VAR2;
input [VAR22-1:0] in;
integer VAR36;
begin
VAR2 = 0;
for (VAR36 = VAR22-1; VAR36 >= 0; VAR36=VAR36-1) begin
if (in[VAR36])
VAR2 = VAR36;
end
end
endfunction
assign VAR26 = VAR2(VAR10);
always @(posedge VAR40)
VAR39 <= VAR6 & !(|VAR10);
assign VAR16 = {VAR22{VAR28}};
assign VAR17 = {VAR22{VAR4}};
assign VAR29 = {VAR22{VAR38}};
assign VAR7 = {VAR22{VAR5}};
assign VAR31 = VAR10 & (VAR6 << VAR26);
assign VAR33 = {VAR22{VAR27}};
assign VAR34 = {VAR22{VAR13}};
assign VAR19 = {VAR22{VAR21}};
assign VAR14 = VAR20[VAR26*VAR18+:VAR18];
assign VAR23 = VAR3[VAR26];
assign VAR11 = VAR15[VAR26] | VAR39;
assign VAR35 = VAR1[VAR26];
endmodule | lgpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fpu/bsg_fpu_f2i.v | 3,248 | module MODULE1
, parameter VAR2(VAR24)
, localparam VAR36=(VAR30+VAR24+1)
, localparam VAR31={1'b0, {(VAR30-1){1'b1}}}
)
(
input [VAR36-1:0] VAR8 , input VAR10
, output logic [VAR36-1:0] VAR6 , output logic VAR22
);
logic VAR28;
logic [VAR30-1:0] VAR27;
logic [VAR24-1:0] VAR26;
logic VAR18;
logic VAR19;
logic VAR3;
VAR12 #(
.VAR30(VAR30)
,.VAR24(VAR24)
) VAR23 (
.VAR8(VAR8)
,.VAR5(VAR18)
,.VAR14(VAR19)
,.VAR16()
,.VAR1(VAR3)
,.VAR9()
,.VAR33()
,.VAR7()
,.VAR17(VAR28)
,.VAR34(VAR27)
,.VAR25(VAR26)
);
logic VAR21;
logic VAR32;
assign VAR21 = VAR10
? (VAR27 > (VAR31+VAR36-2))
: (VAR27 > (VAR31+VAR36-1));
assign VAR32 = VAR27 < VAR31;
logic [VAR36-1:0] VAR15;
logic [VAR30-1:0] VAR35;
logic [VAR36-1:0] VAR4;
assign VAR15 = VAR10
? {1'b0, 1'b1, VAR26, {(VAR36-2-VAR24){1'b0}}}
: {1'b1, VAR26, {(VAR36-1-VAR24){1'b0}}};
assign VAR35 = VAR10
? (VAR30)'((VAR31+VAR36-2) - VAR27)
: (VAR30)'((VAR31+VAR36-1) - VAR27);
assign VAR4 = VAR15 >> VAR35[VAR13(VAR36):0];
logic [VAR36-1:0] VAR20;
logic [VAR36-1:0] VAR11;
assign VAR20 = {VAR36{VAR10 & VAR28}} ^ {VAR4};
assign VAR11 = VAR20 + (VAR28);
VAR29 begin
if (VAR19) begin
VAR6 = VAR10
? {1'b0, {(VAR36-1){1'b1}}}
: {(VAR36){1'b1}};
VAR22 = 1'b1;
end
else if (VAR3) begin
VAR6 = VAR28
? {VAR10, {(VAR36-1){1'b0}}}
: {~VAR10, {(VAR36-1){1'b1}}};
VAR22 = 1'b1;
end
else if (~VAR10 & VAR28) begin
VAR6 = '0;
VAR22 = 1'b1;
end
else if (VAR18) begin
VAR6 = '0;
VAR22 = 1'b0;
end
else if (VAR21) begin
VAR6 = VAR28
? {1'b1, {(VAR36-1){1'b0}}}
: {1'b0, {(VAR36-1){1'b1}}};
VAR22 = 1'b1;
end
else if (VAR32) begin
VAR6 = '0;
VAR22 = 1'b0;
end
else begin
VAR6 = VAR11;
VAR22 = 1'b0;
end
end
endmodule | bsd-3-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9680/axi_ad9680_channel.v | 5,893 | module MODULE1 (
VAR37,
VAR61,
VAR12,
VAR20,
VAR4,
VAR67,
VAR19,
VAR26,
VAR9,
VAR34,
VAR21,
VAR2,
VAR7,
VAR16,
VAR66,
VAR27,
VAR44,
VAR60,
VAR58);
parameter VAR48 = 0;
parameter VAR38 = 0;
input VAR37;
input VAR61;
input [55:0] VAR12;
input VAR20;
output [63:0] VAR4;
output VAR67;
output VAR19;
output VAR26;
output VAR9;
input VAR34;
input VAR21;
input VAR2;
input [13:0] VAR7;
input [31:0] VAR16;
output VAR66;
input VAR27;
input [13:0] VAR44;
output [31:0] VAR60;
output VAR58;
wire VAR24;
wire VAR10;
wire VAR28;
wire VAR8;
wire VAR35;
wire [ 3:0] VAR17;
VAR18 VAR15 (
.VAR37 (VAR37),
.VAR12 (VAR12),
.VAR52 (VAR24),
.VAR3 (VAR10),
.VAR31 (VAR17));
genvar VAR53;
generate
for (VAR53 = 0; VAR53 < 4; VAR53 = VAR53 + 1) begin: VAR40
VAR62 #(.VAR13(14)) VAR36 (
.clk (VAR37),
.valid (1'b1),
.VAR57 (VAR12[VAR53*14+13:VAR53*14]),
.VAR25 (),
.VAR41 (VAR4[VAR53*16+15:VAR53*16]),
.VAR39 (VAR28),
.VAR46 (VAR8),
.VAR22 (VAR35));
end
endgenerate
VAR14 #(.VAR42(VAR38)) VAR59 (
.VAR37 (VAR37),
.VAR61 (VAR61),
.VAR67 (VAR67),
.VAR11 (),
.VAR54 (),
.VAR23 (VAR35),
.VAR64 (VAR8),
.VAR30 (VAR28),
.VAR69 (),
.VAR65 (),
.VAR32 (),
.VAR33 (),
.VAR31 (VAR17),
.VAR29 (),
.VAR3 (VAR10),
.VAR52 (VAR24),
.VAR20 (VAR20),
.VAR19 (VAR19),
.VAR26 (VAR26),
.VAR9 (VAR9),
.VAR56 (),
.VAR49 (),
.VAR47 (),
.VAR51 (),
.VAR50 (),
.VAR6 (),
.VAR43 (),
.VAR1 (1'b0),
.VAR5 (1'b1),
.VAR45 (8'd0),
.VAR55 (8'd16),
.VAR63 (8'd16),
.VAR70 (16'd1),
.VAR68 (16'd1),
.VAR34 (VAR34),
.VAR21 (VAR21),
.VAR2 (VAR2),
.VAR7 (VAR7),
.VAR16 (VAR16),
.VAR66 (VAR66),
.VAR27 (VAR27),
.VAR44 (VAR44),
.VAR60 (VAR60),
.VAR58 (VAR58));
endmodule | gpl-3.0 |
dvanmali/Superscalar_Pipeline_Processor | branchhistorytable.v | 2,338 | module MODULE1(clk,VAR8,VAR4,VAR3,VAR7,VAR6,VAR5);
input clk;
input [1:0] VAR8;
input [31:0] VAR7, VAR3, VAR4;
output reg [31:0] VAR6;
output reg VAR5;
reg [65:0] VAR1[127:0];
reg [31:0] VAR10;
integer VAR2;
reg VAR9; | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufbuf/sky130_fd_sc_hdll__bufbuf.behavioral.pp.v | 1,786 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR1,
VAR3,
VAR5 ,
VAR2
);
output VAR9 ;
input VAR4 ;
input VAR1;
input VAR3;
input VAR5 ;
input VAR2 ;
wire VAR11 ;
wire VAR7;
buf VAR12 (VAR11 , VAR4 );
VAR6 VAR10 (VAR7, VAR11, VAR1, VAR3);
buf VAR8 (VAR9 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.behavioral.v | 1,440 | module MODULE1 (
VAR9,
VAR2
);
output VAR9;
input VAR2;
supply1 VAR3;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR8 ;
wire VAR7;
not VAR1 (VAR7, VAR2 );
buf VAR5 (VAR9 , VAR7 );
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build4/regfileww.v | 4,749 | module MODULE1(VAR1,VAR15,VAR10,VAR2,VAR6,VAR7,
VAR11,VAR8,VAR16,VAR5,clk);
output [127:0] VAR1,VAR15;
input [0:127] VAR10;
input clk;
input VAR16;
input VAR11, VAR8;
input [4:0] VAR7, VAR2, VAR6;
input [15:0] VAR5;
reg [127:0] VAR1,VAR15;
reg [127:0] VAR9 [31:0];
reg [127:0] VAR3; reg [127:0] VAR12; reg [7:0] VAR4;
always @(posedge clk)
begin
VAR3=128'd0;
VAR3=VAR3-1'd1;
if(VAR16)
begin
if(VAR5==16'h1)
begin
VAR4=VAR10[0:7];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h3)
begin
VAR4=VAR10[8:15];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h7)
begin
VAR4=VAR10[16:23];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'hf)
begin
VAR4=VAR10[24:31];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h1f)
begin
VAR4=VAR10[32:39];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h3f)
begin
VAR4=VAR10[40:47];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h7f)
begin
VAR4=VAR10[48:55];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'hff)
begin
VAR4=VAR10[56:63];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h1ff)
begin
VAR4=VAR10[64:71];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h3ff)
begin
VAR4=VAR10[72:79];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h7ff)
begin
VAR4=VAR10[80:87];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'hfff)
begin
VAR4=VAR10[88:95];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h1fff)
begin
VAR4=VAR10[96:103];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h3fff)
begin
VAR4=VAR10[104:111];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'h7fff)
begin
VAR4=VAR10[112:119];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
else if(VAR5==16'hffff)
begin
VAR4=VAR10[120:127];
VAR12 = VAR3 & VAR4;
VAR9[VAR7] <= VAR12;
end
end
if(VAR11 && (VAR2!==5'VAR13) && (VAR2!==5'VAR14))
begin
VAR1<=VAR9[VAR2];
end
else
begin
VAR1=128'VAR14;
end
if(VAR8 && (VAR6!==5'VAR13) && (VAR6!==5'VAR14))
begin
VAR15<=VAR9[VAR6];
end
else
begin
VAR15=128'VAR14;
end
end
endmodule | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/dma_engine_rr_arb.v | 5,446 | module MODULE1 (
input [3:0] VAR3,
input [15:0] VAR17, input VAR13,
output reg [3:0] VAR5,
output [15:0] VAR6,
output reg VAR12,
input VAR4,
input VAR16,
input VAR15,
input VAR19,
input reset,
input clk
);
reg [3:0] VAR20;
reg [3:0] VAR14;
wire [15:0] VAR9;
always @(posedge clk)
begin
if (reset || VAR19)
VAR20 <= 4'h0;
end
else if (VAR4 && VAR15)
VAR20 <= VAR20 + 'h1;
else if (VAR13)
VAR20 <= VAR5;
end
always @(posedge clk)
begin
if (reset || VAR19) begin
VAR5 <= 4'hf;
VAR14 <= 4'hf;
VAR12 <= 1'b0;
end
else if (VAR13 && VAR15) begin
VAR12 <= 1'b0;
end
else if (VAR4 && VAR15) begin
VAR5 <= VAR20;
VAR14 <= VAR20;
VAR12 <= 1'b0;
end
else begin
if (VAR5 != VAR20) begin
if (VAR14 == VAR20)
VAR14 <= VAR5;
end
else
VAR14 <= VAR14 - 'h1;
if (VAR9 & VAR17) begin
VAR5 <= VAR14;
VAR12 <= 1'b1;
end
end
end
end
assign VAR6 = {VAR3 == 4'VAR1 VAR18,
VAR3 == 4'VAR1 VAR2,
VAR3 == 4'VAR1 VAR7,
VAR3 == 4'VAR1 VAR10,
VAR3 == 4'VAR1 VAR8,
VAR3 == 4'VAR1 VAR11,
VAR3 == 4'VAR1 9,
VAR3 == 4'VAR1 8,
VAR3 == 4'VAR1 7,
VAR3 == 4'VAR1 6,
VAR3 == 4'VAR1 5,
VAR3 == 4'VAR1 4,
VAR3 == 4'VAR1 3,
VAR3 == 4'VAR1 2,
VAR3 == 4'VAR1 1,
VAR3 == 4'VAR1 0};
assign VAR9 = {VAR14 == 4'VAR1 VAR18,
VAR14 == 4'VAR1 VAR2,
VAR14 == 4'VAR1 VAR7,
VAR14 == 4'VAR1 VAR10,
VAR14 == 4'VAR1 VAR8,
VAR14 == 4'VAR1 VAR11,
VAR14 == 4'VAR1 9,
VAR14 == 4'VAR1 8,
VAR14 == 4'VAR1 7,
VAR14 == 4'VAR1 6,
VAR14 == 4'VAR1 5,
VAR14 == 4'VAR1 4,
VAR14 == 4'VAR1 3,
VAR14 == 4'VAR1 2,
VAR14 == 4'VAR1 1,
VAR14 == 4'VAR1 0};
endmodule | mit |
SergKolo/msudenver_eet_4020_verilog | proj2_elevator/elevator.v | 7,375 | module MODULE1(VAR19,VAR17,VAR1,VAR9);
input [9:0] VAR1;
output reg [9:0] VAR17;
wire [9:0] VAR6;
wire [9:0] VAR22;
input VAR9;
output wire [4:0] VAR19;
reg [4:0] VAR18;
reg VAR5;
MODULE2 MODULE1(VAR22,VAR19,VAR5,VAR18,VAR9);
VAR7 VAR16(VAR6[0],
VAR22[0],VAR1[0],VAR9);
VAR7 VAR2(VAR6[1],
VAR22[1],VAR1[1],VAR9);
VAR7 VAR10(VAR6[2],
VAR22[2],VAR1[2],VAR9);
VAR7 VAR3(VAR6[3],
VAR22[3],VAR1[3],VAR9);
VAR7 VAR21(VAR6[4],
VAR22[4],VAR1[4],VAR9);
VAR7 VAR11(VAR6[5],
VAR22[5],VAR1[5],VAR9);
VAR7 VAR12(VAR6[6],
VAR22[6],VAR1[6],VAR9);
VAR7 VAR14(VAR6[7],
VAR22[7],VAR1[7],VAR9);
VAR7 VAR20(VAR6[8],
VAR22[8],VAR1[8],VAR9);
VAR7 VAR23(VAR6[9],
VAR22[9],VAR1[9],VAR9);
always @(posedge VAR9) begin
if (|VAR6) begin
if (VAR6[0]) begin
VAR17[0] <= 1;
VAR18 <= 0;
if (VAR19 > 0)
VAR5 <= 0;
end
else
VAR17[0] <= 0;
if (VAR6[1]) begin
VAR17[1] <= 1;
VAR18 <= 1;
if ( VAR19 > 1)
VAR5 <= 0;
end
else
VAR5 <= 1;
end
else
VAR17[1] <= 0;
if (VAR6[2]) begin
VAR17[2] <= 1;
VAR18 <= 2;
if ( VAR19 > 2)
VAR5 <= 0;
end
else
VAR5 <= 1;
end
else
VAR17[2] <= 0;
end
else
if ( VAR19 < 5 ) begin
VAR18 <= 0;
VAR5 <= 0;
end
else begin
VAR18 <= 9;
VAR5 <= 1;
end
end
endmodule
module MODULE2(VAR8,VAR19,VAR15,VAR4,VAR9);
output reg [4:0] VAR19; output reg [9:0] VAR8;
input VAR15; input [4:0] VAR4;
input VAR9;
reg [4:0] counter; | mit |
pwwu/FPGA | VGAbased/final/lcd_write_number.v | 2,689 | module MODULE1
(
input VAR33,
output VAR2,
output VAR7,
output VAR28,
output [3:0] VAR16,
input [31:0] VAR34,
input VAR13,
output VAR23
);
reg [7:0] VAR6;
reg VAR8;
reg [31:0] VAR15;
reg VAR20;
wire VAR26;
reg VAR30;
reg [7:0] VAR4;
reg [1:0] state;
reg [31:0] VAR21;
reg VAR11;
reg VAR3;
reg [4:0] VAR5;
reg VAR27;
assign VAR23 = VAR27;
VAR24 VAR22
(.clk(VAR33),
.rst(1'b0),
.VAR18(VAR2),
.VAR1(VAR28),
.VAR32(VAR7),
.VAR17(VAR16),
.VAR34(VAR6),
.VAR12(VAR8),
.VAR25(VAR15),
.VAR13(VAR20),
.VAR23(VAR26),
.VAR10(VAR30)
);
parameter VAR29 = 8'd12;
parameter VAR9 = 2'b00,
VAR31 = 2'b01,
VAR19 = 2'b10,
VAR14 = 2'b11;
begin
begin
begin
begin
begin
begin
begin | mit |
siamumar/TinyGarbled | circuit_synthesis/mips/Data_Mem.v | 3,910 | module MODULE1
(
parameter VAR8 = 32,
parameter VAR9 = 6
)
(
clk,
rst,
VAR5,
VAR3,
VAR7,
addr,
VAR13,
VAR4
);
localparam VAR1 = 2**VAR9;
input clk;
input rst;
input [VAR8*VAR1-1:0] VAR5;
output [VAR8*VAR1-1:0] VAR3;
input [3:0] VAR7;
input [31:0] addr;
input [VAR8-1:0] VAR13;
output [VAR8-1:0] VAR4;
reg [VAR8-1:0] VAR4;
reg [VAR8-1:0] memory [0:VAR1-1];
genvar VAR15;
wire [VAR8-1:0] VAR6 [0:VAR1-1];
generate
for (VAR15 = 0; VAR15 < VAR1; VAR15 = VAR15 + 1)
begin:VAR11
assign VAR6[VAR15] = VAR5[(VAR15+1)*VAR8-1:VAR15*VAR8];
end
endgenerate
generate
for (VAR15 = 0; VAR15 < VAR1; VAR15 = VAR15 + 1)
begin:VAR10
assign VAR3[(VAR15+1)*VAR8-1:VAR15*VAR8] = memory[VAR15];
end
endgenerate
integer VAR14;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
for(VAR14=0;VAR14<VAR1;VAR14=VAR14+1)
begin
memory[VAR14] <= VAR6[VAR14];
end
end
else if (VAR7 == VAR2)
begin
memory[addr[VAR9+1:2]] <= VAR13;
end
else if (VAR7 == VAR16)
begin
if(addr[1]==1'b0)
memory[addr[VAR9+1:2]][15:0] <= VAR13[15:0];
end
else if (addr[1]==1'b1)
memory[addr[VAR9+1:2]][31:16] <= VAR13[15:0];
end
else if (VAR7 == VAR12)
begin
if(addr[1:0]==2'b00)
memory[addr[VAR9+1:2]][7:0] <= VAR13[7:0];
end
else if(addr[1:0]==2'b01)
memory[addr[VAR9+1:2]][15:8] <= VAR13[7:0];
else if(addr[1:0]==2'b10)
memory[addr[VAR9+1:2]][23:16] <= VAR13[7:0];
else if(addr[1:0]==2'b11)
memory[addr[VAR9+1:2]][31:24] <= VAR13[7:0];
end
end
always@(*)
begin
VAR4 <= 32'b0;
case(VAR7)
begin
VAR4 <= memory[addr[VAR9+1:2]];
end
begin
if(addr[1]==1'b0)
VAR4 <= {16'b0, memory[addr[VAR9+1:2]][15:0]};
end
else if (addr[1]==1'b1)
VAR4 <= {16'b0, memory[addr[VAR9+1:2]][31:16]};
end
begin
if(addr[1]==1'b0)
VAR4 <= {{16{memory[addr[VAR9+1:2]][15]}}, memory[addr[VAR9+1:2]][15:0]};
end
else if (addr[1]==1'b1)
VAR4 <= {{16{memory[addr[VAR9+1:2]][16]}}, memory[addr[VAR9+1:2]][31:16]};
end
begin
if(addr[1:0]==2'b00)
VAR4 <= {24'b0, memory[addr[VAR9+1:2]][7:0]};
end
else if(addr[1:0]==2'b01)
VAR4 <= {24'b0, memory[addr[VAR9+1:2]][15:8]};
else if(addr[1:0]==2'b10)
VAR4 <= {24'b0, memory[addr[VAR9+1:2]][23:16]};
else if(addr[1:0]==2'b11)
VAR4 <= {24'b0, memory[addr[VAR9+1:2]][31:24]};
end
begin
if(addr[1:0]==2'b00)
VAR4 <= {{24{memory[addr[VAR9+1:2]][7]}}, memory[addr[VAR9+1:2]][7:0]};
end
else if(addr[1:0]==2'b01)
VAR4 <= {{24{memory[addr[VAR9+1:2]][7]}}, memory[addr[VAR9+1:2]][15:8]};
else if(addr[1:0]==2'b10)
VAR4 <= {{24{memory[addr[VAR9+1:2]][7]}}, memory[addr[VAR9+1:2]][23:16]};
else if(addr[1:0]==2'b11)
VAR4 <= {{24{memory[addr[VAR9+1:2]][7]}}, memory[addr[VAR9+1:2]][31:24]};
end
default:
VAR4 <= 32'b0;
endcase
end
endmodule | gpl-3.0 |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/d74462b9dbd19694/mult_17x16_stub.v | 1,315 | module MODULE1(VAR2, VAR4, VAR1, VAR3)
;
input VAR2;
input [16:0]VAR4;
input [15:0]VAR1;
output [24:0]VAR3;
endmodule | bsd-3-clause |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/SyncHandshake.v | 4,082 | module MODULE1(
VAR3,
VAR5,
VAR7,
VAR9,
VAR11,
VAR15
);
parameter VAR4 = 1'b0;
parameter VAR13 = 1'b0;
input VAR3 ;
input VAR5 ;
input VAR9 ;
output VAR11 ;
input VAR7 ;
output VAR15 ;
reg VAR12, VAR18 ;
reg VAR1 ;
reg VAR10 ;
reg VAR19, VAR2 ;
assign VAR15 = VAR18 != VAR1 ;
assign VAR11 = VAR2 == VAR10;
wire VAR6 = VAR13 ? VAR1 : VAR18 ;
always @(posedge VAR3 or VAR8 VAR5)
begin
if (VAR5 == VAR16)
begin
VAR19 <= VAR14 ! VAR4 ; VAR2 <= VAR14 ! VAR4 ;
VAR10 <= VAR14 VAR4 ;
end
else
begin
VAR19 <= VAR14 VAR6 ; VAR2 <= VAR14 VAR19 ;
if ( VAR9 )
begin
VAR10 <= VAR14 ! VAR10 ;
end
end
end
always @(posedge VAR7 or VAR8 VAR5)
begin
if (VAR5 == VAR16)
begin
VAR12 <= VAR14 VAR4;
VAR18 <= VAR14 VAR4;
VAR1 <= VAR14 VAR4 ;
end
else
begin
VAR12 <= VAR14 VAR10 ; VAR18 <= VAR14 VAR12 ;
VAR1 <= VAR14 VAR18 ;
end
end
begin
VAR12 = VAR4 ;
VAR18 = VAR4 ;
VAR1 = VAR4 ;
VAR10 = VAR4 ;
VAR19 = ! VAR4 ;
VAR2 = ! VAR4 ;
end VAR17
endmodule | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_axi_basic_rx_null_gen.v | 15,544 | module MODULE1 # (
parameter VAR27 = 128, parameter VAR19 = 1,
parameter VAR30 = VAR27 / 8 ) (
input [VAR27-1:0] VAR12, input VAR23, input VAR18, input VAR15, input [21:0] VAR25,
output VAR21, output VAR5, output [VAR30-1:0] VAR26, output VAR28, output reg [4:0] VAR36,
input VAR11, input VAR8 );
localparam VAR1 = (VAR27 == 128) ? 11'd4 :
(VAR27 == 64) ? 11'd2 : 11'd1;
localparam VAR3 = 0;
localparam VAR9 = 1;
reg VAR17;
reg VAR16;
reg [11:0] VAR35;
reg [11:0] VAR7;
wire [11:0] VAR24;
wire VAR37;
wire [11:0] VAR2;
wire [9:0] VAR38;
wire [1:0] VAR22;
wire VAR33;
reg [3:0] VAR13;
wire [VAR30-1:0] VAR6;
wire VAR4;
wire VAR34;
assign VAR34 = VAR25[21];
generate
if(VAR27 == 128) begin : VAR29
assign VAR4 = (VAR25[14:13] == 2'b11);
end
else begin : VAR10
assign VAR4 = 1'b0;
end
endgenerate
generate
if(VAR27 == 128) begin : VAR31
assign VAR22 = VAR4 ?
VAR12[94:93] : VAR12[30:29];
assign VAR33 = VAR4 ?
VAR12[79] : VAR12[15];
assign VAR38 = VAR22[1] ?
(VAR4 ? VAR12[73:64] : VAR12[9:0]) : 10'h0;
always @ begin
case({VAR22[0], VAR33})
2'b00: VAR13 = 4'd3 + 4'd0 - 4'd2;
2'b01: VAR13 = 4'd3 + 4'd1 - 4'd2;
2'b10: VAR13 = 4'd4 + 4'd0 - 4'd2;
2'b11: VAR13 = 4'd4 + 4'd1 - 4'd2;
endcase
end
end
else begin : VAR14
assign VAR22 = VAR12[30:29];
assign VAR33 = VAR12[15];
assign VAR38 = VAR22[1] ? VAR12[9:0] : 10'h0;
always @ begin
case (VAR17)
VAR3: begin
if(VAR23 && VAR18 && !VAR34) begin
VAR16 = VAR9;
end
else begin
VAR16 = VAR3;
end
VAR7 = VAR2;
end
VAR9: begin
if((VAR27 == 128) && VAR4 && VAR23) begin
VAR7 = VAR2;
VAR16 = VAR9;
end
else if(VAR18 && VAR37)
begin
VAR7 = VAR2;
VAR16 = VAR3;
end
else begin
if(VAR18) begin
VAR7 = VAR24;
end
else begin
VAR7 = VAR35;
end
VAR16 = VAR9;
end
end
default: begin
VAR7 = VAR35;
VAR16 = VAR3;
end
endcase
end
always @(posedge VAR11) begin
if(VAR8) begin
end
else begin
end
end
generate
if(VAR27 == 128) begin : VAR32
always @ begin
case(VAR7)
10'd1: VAR36 = 5'b10011;
10'd2: VAR36 = 5'b10111;
default: VAR36 = 5'b00011;
endcase
end
assign VAR6 = { ((VAR7 == 12'd2) ? 4'hF:4'h0), 4'hF };
end
else begin : VAR20
always @(*) begin
if(VAR7 == 12'd1) begin
VAR36 = 5'b10011;
end
else begin
VAR36 = 5'b00011;
end
end
assign VAR6 = 4'hF;
end
endgenerate
assign VAR21 = 1'b1;
assign VAR5 = (VAR7 <= VAR1);
assign VAR26 = VAR5 ? VAR6 : {VAR30{1'b1}};
assign VAR28 = VAR5;
endmodule | mit |
kyzhai/NUNY | src/hardware/bg.v | 6,302 | module MODULE1 (
address,
VAR50,
VAR8);
input [9:0] address;
input VAR50;
output [23:0] VAR8;
tri1 VAR50;
wire [23:0] VAR19;
wire [23:0] VAR8 = VAR19[23:0];
VAR13 VAR21 (
.VAR37 (address),
.VAR22 (VAR50),
.VAR33 (VAR19),
.VAR20 (1'b0),
.VAR38 (1'b0),
.VAR4 (1'b1),
.VAR36 (1'b0),
.VAR16 (1'b0),
.VAR17 (1'b1),
.VAR30 (1'b1),
.VAR6 (1'b1),
.VAR11 (1'b1),
.VAR39 (1'b1),
.VAR49 (1'b1),
.VAR24 (1'b1),
.VAR12 ({24{1'b1}}),
.VAR28 (1'b1),
.VAR32 (),
.VAR10 (),
.VAR46 (1'b1),
.VAR35 (1'b1),
.VAR43 (1'b0),
.VAR27 (1'b0));
VAR21.VAR34 = "VAR48",
VAR21.VAR47 = "VAR14",
VAR21.VAR51 = "VAR14",
VAR21.VAR15 = "VAR25/MODULE1.VAR18",
VAR21.VAR41 = "VAR42 VAR2",
VAR21.VAR29 = "VAR45=VAR52",
VAR21.VAR44 = "VAR13",
VAR21.VAR31 = 1024,
VAR21.VAR7 = "VAR3",
VAR21.VAR26 = "VAR48",
VAR21.VAR9 = "VAR5",
VAR21.VAR40 = 10,
VAR21.VAR23 = 24,
VAR21.VAR1 = 1;
endmodule | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms1/vc707/system_top.v | 10,548 | module MODULE1 (
VAR12,
VAR103,
VAR81,
VAR66,
VAR67,
VAR5,
VAR130,
VAR43,
VAR39,
VAR131,
VAR99,
VAR79,
VAR86,
VAR100,
VAR107,
VAR101,
VAR113,
VAR122,
VAR84,
VAR61,
VAR42,
VAR77,
VAR133,
VAR114,
VAR115,
VAR75,
VAR65,
VAR78,
VAR27,
VAR87,
VAR69,
VAR59,
VAR9,
VAR118,
VAR45,
VAR136,
VAR102,
VAR104,
VAR44,
VAR28,
VAR38,
VAR89,
VAR82,
VAR117,
VAR51,
VAR37,
VAR21,
VAR124,
VAR11,
VAR3,
VAR126,
VAR62,
VAR137,
VAR127,
VAR30,
VAR128,
VAR92 );
input VAR12;
input VAR103;
input VAR81;
input VAR66;
output VAR67;
output [13:0] VAR5;
output [ 2:0] VAR130;
output VAR43;
output [ 0:0] VAR39;
output [ 0:0] VAR131;
output [ 0:0] VAR99;
output [ 0:0] VAR79;
output [ 7:0] VAR86;
inout [63:0] VAR100;
inout [ 7:0] VAR107;
inout [ 7:0] VAR101;
output [ 0:0] VAR113;
output VAR122;
output VAR84;
output VAR61;
input VAR42;
input VAR77;
output VAR133;
output VAR114;
output VAR115;
input VAR75;
input VAR65;
output VAR78;
inout VAR27;
output VAR87;
output [26:1] VAR69;
output VAR59;
output VAR9;
output VAR118;
output VAR45;
inout [15:0] VAR136;
inout [ 6:0] VAR102;
inout [20:0] VAR104;
output VAR44;
inout VAR28;
inout VAR38;
input VAR89;
input VAR82;
output VAR117;
output VAR51;
output VAR37;
output VAR21;
output [15:0] VAR124;
output [15:0] VAR11;
input VAR3;
input VAR126;
input VAR62;
input VAR137;
input [13:0] VAR127;
input [13:0] VAR30;
output VAR128;
output VAR92;
reg [63:0] VAR119 = 'd0;
reg [63:0] VAR16 = 'd0;
reg VAR33 = 'd0;
reg VAR46 = 'd0;
reg VAR105 = 'd0;
reg [31:0] VAR109 = 'd0;
wire [63:0] VAR52;
wire [63:0] VAR85;
wire [63:0] VAR138;
wire [ 7:0] VAR29;
wire VAR55;
wire VAR13;
wire VAR116;
wire VAR83;
wire VAR93;
wire VAR108;
wire VAR71;
wire VAR31;
wire [63:0] VAR20;
wire VAR57;
wire VAR68;
wire VAR70;
wire [15:0] VAR40;
wire VAR17;
wire VAR34;
wire [15:0] VAR23;
wire VAR6;
wire VAR135;
assign VAR87 = 1'b1;
assign VAR44 = 1'b1;
VAR129 #(
.VAR15 ("VAR41"),
.VAR112 (1'b0),
.VAR7 ("VAR73"))
VAR123 (
.VAR22 (1'b0),
.VAR24 (1'b1),
.VAR90 (1'b0),
.VAR91 (VAR6),
.VAR19 (1'b1),
.VAR1 (1'b0),
.VAR98 (VAR135));
VAR25 VAR74 (
.VAR110 (VAR135),
.VAR14 (VAR128),
.VAR35 (VAR92));
always @(posedge VAR83) begin
VAR33 <= VAR93 & VAR108;
VAR16[63:48] <= VAR20[63:48];
VAR16[47:32] <= VAR20[63:48];
VAR16[31:16] <= VAR20[31:16];
VAR16[15: 0] <= VAR20[31:16];
VAR119[63:48] <= VAR20[47:32];
VAR119[47:32] <= VAR20[47:32];
VAR119[31:16] <= VAR20[15: 0];
VAR119[15: 0] <= VAR20[15: 0];
end
always @(posedge VAR57) begin
VAR46 <= ~VAR46;
case ({VAR34, VAR70})
2'b10: begin
VAR105 <= VAR46;
VAR109 <= {VAR23, VAR109[31:16]};
end
2'b01: begin
VAR105 <= VAR46;
VAR109 <= {VAR40, VAR109[31:16]};
end
default: begin
VAR105 <= 1'b1;
VAR109 <= {VAR23, VAR40};
end
endcase
end
VAR72 #(.VAR26(21)) VAR36 (
.VAR49 (VAR138[20:0]),
.VAR134 (VAR85[20:0]),
.VAR58 (VAR52[20:0]),
.VAR121 (VAR104));
VAR95 VAR10 (
.VAR5 (VAR5),
.VAR130 (VAR130),
.VAR43 (VAR43),
.VAR39 (VAR39),
.VAR131 (VAR131),
.VAR99 (VAR99),
.VAR79 (VAR79),
.VAR86 (VAR86),
.VAR100 (VAR100),
.VAR107 (VAR107),
.VAR101 (VAR101),
.VAR113 (VAR113),
.VAR122 (VAR122),
.VAR84 (VAR84),
.VAR61 (VAR61),
.VAR48 (VAR28),
.VAR53 (VAR38),
.VAR69 (VAR69),
.VAR59 (VAR59),
.VAR9 (VAR9),
.VAR118 (VAR118),
.VAR45 (VAR45),
.VAR136(VAR136),
.VAR60 (VAR52[31:0]),
.VAR76 (VAR85[31:0]),
.VAR120 (VAR138[31:0]),
.VAR125 (VAR52[63:32]),
.VAR111 (VAR85[63:32]),
.VAR47 (VAR138[63:32]),
.VAR88 (VAR102),
.VAR57 (VAR57),
.VAR126 (VAR126),
.VAR3 (VAR3),
.VAR40 (VAR40),
.VAR23 (VAR23),
.VAR30 (VAR30),
.VAR127 (VAR127),
.VAR109 (VAR109),
.VAR105 (VAR105),
.VAR70 (VAR70),
.VAR34 (VAR34),
.VAR137 (VAR137),
.VAR62 (VAR62),
.VAR68 (VAR68),
.VAR17 (VAR17),
.VAR83 (VAR83),
.VAR82 (VAR82),
.VAR89 (VAR89),
.VAR51 (VAR51),
.VAR117 (VAR117),
.VAR11 (VAR11),
.VAR124 (VAR124),
.VAR119 (VAR119),
.VAR16 (VAR16),
.VAR33 (VAR33),
.VAR20 (VAR20),
.VAR108 (VAR108),
.VAR31 (VAR31),
.VAR21 (VAR21),
.VAR37 (VAR37),
.VAR93 (VAR93),
.VAR71 (VAR71),
.VAR6 (VAR6),
.VAR50 (1'b0),
.VAR63 (1'b0),
.VAR94 (1'b0),
.VAR4 (1'b0),
.VAR106 (1'b0),
.VAR78 (VAR78),
.VAR80 (VAR27),
.VAR132 (VAR65),
.VAR97 (VAR75),
.VAR115 (VAR115),
.VAR18 (1'b1),
.VAR77 (VAR77),
.VAR42 (VAR42),
.VAR114 (VAR114),
.VAR133 (VAR133),
.VAR64 (1'b0),
.VAR2 (VAR55),
.VAR96 (8'hff),
.VAR54 (VAR29),
.VAR32 (VAR116),
.VAR8 (1'b0),
.VAR56 (VAR13),
.VAR81 (VAR81),
.VAR103 (VAR103),
.VAR12 (VAR12),
.VAR66 (VAR66),
.VAR67 (VAR67));
endmodule | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/db_ram_1p.v | 3,203 | module MODULE1 (
clk ,
VAR2 ,
VAR6 ,
VAR4 ,
VAR10 ,
VAR5 ,
VAR11
);
parameter VAR12 = 128;
parameter VAR7 = 8 ;
input clk ; input VAR2; input VAR6; input VAR4; input [VAR7-1:0] VAR10; input [VAR12-1:0] VAR5; output [VAR12-1:0] VAR11;
reg [VAR12-1:0] VAR8[(1<<VAR7)-1:0];
reg [VAR12-1:0] VAR9;
always @(posedge clk) begin
if(!VAR2 && !VAR4)
VAR8[VAR10] <= VAR5;
end
always @(posedge clk) begin
if (!VAR2 && VAR4)
VAR9 <= VAR8[VAR10];
end
else
VAR9 <= 'VAR1;
end
assign VAR11 = VAR6 ? 'VAR3 : VAR9;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22a/sky130_fd_sc_hs__o22a.pp.symbol.v | 1,335 | module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR6 ,
input VAR5 ,
output VAR2 ,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
CospanDesign/nysa-sata | rtl/phy/sata_phy_layer.v | 5,123 | module MODULE1 (
input rst, input clk,
input VAR4, output VAR13,
output VAR14,
output [31:0] VAR3,
output VAR7,
output VAR1,
output VAR24,
output VAR16,
input VAR9,
input [31:0] VAR28,
input [3:0] VAR30,
input VAR6,
input VAR17,
input VAR12,
input VAR25,
output VAR18,
input VAR2,
output [3:0] VAR10
);
parameter VAR32 = 4'h0;
parameter VAR34 = 4'h1;
parameter VAR22 = 4'h2;
parameter VAR31 = 4'h3;
reg [3:0] state;
reg [7:0] VAR21;
wire [31:0] VAR33;
wire VAR26;
wire [31:0] VAR15;
wire VAR19;
wire VAR8;
reg VAR11;
VAR29 VAR27 (
.rst (rst ),
.clk (clk ),
.VAR2 (VAR2 ),
.VAR4 (VAR4 ),
.VAR13 (VAR8 ),
.VAR14 (VAR14 ),
.VAR3 (VAR33 ),
.VAR7 (VAR26 ),
.VAR1 (VAR1 ),
.VAR24 (VAR24 ),
.VAR20 (VAR16 ),
.VAR9 (VAR9 ),
.VAR28 (VAR28 ),
.VAR30 (VAR30 ),
.VAR12 (VAR12 ),
.VAR25 (VAR25 ),
.VAR23 (VAR6 ),
.VAR17 (VAR17 ),
.VAR10 (VAR10 )
);
assign VAR3 = !VAR14 ? VAR33 : VAR15;
assign VAR7 = !VAR14 ? VAR26 : VAR19;
assign VAR15 = VAR5;
assign VAR19 = 1;
assign VAR18 = (state == VAR31);
assign VAR13 = VAR8 || VAR11;
always @ (posedge clk) begin
if (rst) begin
state <= VAR32;
VAR21 <= 0;
VAR11<= 0;
end
else begin
if (state == VAR31) begin
VAR21 <= VAR21 + 8'h01;
end
case (state)
VAR32: begin
VAR21 <= 0;
VAR11 <= 0;
if (VAR14) begin
state <= VAR34;
end
end
VAR34: begin
state <= VAR22;
end
VAR22: begin
state <= VAR31;
end
VAR31: begin
if (VAR21 == 255) begin
state <= VAR34;
end
if (VAR2) begin
VAR11 <= 1;
end
end
default: begin
end
endcase
end
end
endmodule | mit |
fabianmcg/usbc_tcpc | src/debug_module.v | 1,195 | module MODULE1(output reg [31:0] VAR1, input wire VAR3,input wire VAR2);
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/rtr_flow_ctrl_input.v | 5,024 | module MODULE1
(clk, reset, VAR4, VAR14, VAR8,
VAR23);
parameter VAR22 = 4;
parameter VAR15 = VAR13;
parameter VAR9 = VAR3;
localparam VAR19 = VAR7(VAR22);
localparam VAR21
= (VAR15 == VAR13) ? (1 + VAR19) :
-1;
input clk;
input reset;
input VAR4;
input [0:VAR21-1] VAR14;
output VAR8;
wire VAR8;
output [0:VAR22-1] VAR23;
wire [0:VAR22-1] VAR23;
generate
case(VAR15)
begin
wire VAR20;
wire VAR24;
assign VAR24 = VAR4 | VAR20;
wire VAR12;
assign VAR12 = VAR14[0];
VAR18
.VAR9(VAR9))
VAR20
(.clk(clk),
.reset(reset),
.VAR4(VAR24),
.VAR10(VAR12),
.VAR5(VAR20));
assign VAR8 = VAR20;
if(VAR22 > 1)
begin
wire [0:VAR19-1] VAR6, VAR2;
assign VAR6 = VAR14[1:VAR19];
VAR18
.VAR9(VAR9))
VAR2
(.clk(clk),
.reset(1'b0),
.VAR4(VAR4),
.VAR10(VAR6),
.VAR5(VAR2));
VAR16
VAR1
(.VAR11(VAR2),
.VAR17(VAR23));
end
else
assign VAR23 = 1'b1;
end
endcase
endgenerate
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ai/sky130_fd_sc_ms__o21ai.symbol.v | 1,349 | module MODULE1 (
input VAR6,
input VAR7,
input VAR3,
output VAR4
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/edc/edc_module.v | 7,983 | module MODULE1 (
input VAR22,
input VAR2,
input [31:0] VAR40,
input [15:0] VAR47,
input VAR8,
output [127:0] VAR39, input [127:0] VAR3, input VAR53,
input VAR19,
output VAR30,
output VAR33
);
parameter VAR18 = 26;
wire VAR11; wire VAR6;
reg [31:0] VAR1[0:3]; wire [3:0]VAR31;
VAR42 #(
.VAR27 ( 128 ),
.VAR25 ( 16 )
)
VAR14 (
.VAR51 ( VAR22 ),
.VAR52 ( VAR2 ),
.VAR24 ( VAR40 ),
.VAR34 ( VAR47 ),
.VAR20 ( VAR8 ),
.VAR15 ( ), .VAR10 ( VAR3 ), .VAR32 ( VAR53 ),
.VAR35 ( VAR19 ),
.VAR13 ( ), .VAR4 ( ) );
VAR44 #(
.VAR37 ( 32 ),
.VAR38 ( VAR18-2 ), .VAR7 ( 0 ) )
VAR48
(
.VAR51 ( VAR22 ),
.VAR41 ( VAR8 ),
.VAR49 ( VAR40[27:4] ),
.VAR12 ( ), .VAR55 ( ) );
genvar VAR16;
generate
localparam VAR54 = 8;
localparam VAR36 = 32;
for(VAR16=0; VAR16<4; VAR16=VAR16+1) begin
VAR29 VAR17 (
.VAR45 ( VAR1[VAR16] ), .VAR46 ( VAR48.VAR12[VAR54*VAR16+:VAR54] ), .VAR5 ( VAR8 ), .VAR21 ( VAR48.VAR55[VAR54*VAR16+:VAR54] ) );
VAR43 VAR28 (
.VAR45 ( VAR14.VAR15[VAR36*VAR16+:VAR36] ), .VAR23 ( VAR17.VAR21 ), .VAR9 ( VAR39[VAR36*VAR16+:VAR36] ), .VAR50 ( ), .VAR26 ( VAR31[VAR16] ) );
end
endgenerate
always@(VAR8 or VAR3 or VAR14.VAR15)
begin
case(VAR8)
'b1: begin VAR1[0] = VAR3[31:0];
VAR1[1] = VAR3[63:32];
VAR1[2] = VAR3[95:64];
VAR1[3] = VAR3[127:96];
end
default: begin VAR1[0] = VAR14.VAR15[31:0];
VAR1[1] = VAR14.VAR15[63:32];
VAR1[2] = VAR14.VAR15[95:64];
VAR1[3] = VAR14.VAR15[127:96];
end
endcase
end
assign VAR30 = VAR14.VAR13;
assign VAR33 = VAR30 & ( VAR14.VAR4 | ( ~VAR8 & (| VAR31)));
endmodule | lgpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/z80/tv80_alu.v | 11,495 | module MODULE1 (
VAR27, VAR29,
VAR18, VAR9, VAR14, VAR19, VAR31, VAR33, VAR20, VAR10
);
parameter VAR24 = 0;
parameter VAR26 = 0;
parameter VAR30 = 1;
parameter VAR16 = 2;
parameter VAR1 = 3;
parameter VAR5 = 4;
parameter VAR34 = 5;
parameter VAR15 = 6;
parameter VAR17 = 7;
input VAR18;
input VAR9;
input [3:0] VAR14 ;
input [5:0] VAR19;
input [1:0] VAR31;
input [7:0] VAR33;
input [7:0] VAR20;
input [7:0] VAR10;
output [7:0] VAR27;
output [7:0] VAR29;
reg [7:0] VAR27;
reg [7:0] VAR29;
function [4:0] VAR3;
input [3:0] VAR35;
input [3:0] VAR21;
input VAR23;
input VAR11;
begin
VAR3 = { 1'b0, VAR35 } + { 1'b0, (VAR23)?~VAR21:VAR21 } + {4'h0,VAR11};
end
endfunction
function [3:0] VAR28;
input [2:0] VAR35;
input [2:0] VAR21;
input VAR23;
input VAR11;
begin
VAR28 = { 1'b0, VAR35 } + { 1'b0, (VAR23)?~VAR21:VAR21 } + {3'h0,VAR11};
end
endfunction
function [1:0] VAR7;
input VAR35;
input VAR21;
input VAR23;
input VAR11;
begin
VAR7 = { 1'b0, VAR35 } + { 1'b0, (VAR23)?~VAR21:VAR21 } + {1'h0,VAR11};
end
endfunction
reg VAR4;
reg VAR6;
reg VAR2;
reg VAR13;
reg VAR22;
reg [7:0] VAR8;
reg [7:0] VAR32;
always @(VAR14 or VAR33 or VAR20 or VAR10 or VAR19)
begin
case (VAR19[5:3])
3'b000 : VAR32 = 8'b00000001;
3'b001 : VAR32 = 8'b00000010;
3'b010 : VAR32 = 8'b00000100;
3'b011 : VAR32 = 8'b00001000;
3'b100 : VAR32 = 8'b00010000;
3'b101 : VAR32 = 8'b00100000;
3'b110 : VAR32 = 8'b01000000;
default: VAR32 = 8'b10000000;
endcase
VAR4 = ~ VAR14[2] && VAR14[0];
{ VAR13, VAR8[3:0] } = VAR3(VAR33[3:0], VAR20[3:0], VAR14[1], VAR14[1] ^ (VAR4 && VAR10[VAR26]) );
{ VAR6, VAR8[6:4] } = VAR28(VAR33[6:4], VAR20[6:4], VAR14[1], VAR13);
{ VAR22, VAR8[7] } = VAR7(VAR33[7], VAR20[7], VAR14[1], VAR6);
VAR2 = VAR22 ^ VAR6;
end
reg [7:0] VAR12;
reg [8:0] VAR36;
always @ (VAR14 or VAR18 or VAR32 or VAR33 or VAR20
or VAR22 or VAR10 or VAR13 or VAR19 or VAR31
or VAR2 or VAR8 or VAR9)
begin
VAR12 = 8'VAR37;
VAR36 = {9{1'VAR25}};
VAR29 = VAR10;
case (VAR14)
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
begin
VAR29[VAR30] = 1'b0;
VAR29[VAR26] = 1'b0;
case (VAR14[2:0])
3'b000, 3'b001 : begin
VAR12 = VAR8;
VAR29[VAR26] = VAR22;
VAR29[VAR5] = VAR13;
VAR29[VAR16] = VAR2;
end
3'b010, 3'b011, 3'b111 : begin
VAR12 = VAR8;
VAR29[VAR30] = 1'b1;
VAR29[VAR26] = ~ VAR22;
VAR29[VAR5] = ~ VAR13;
VAR29[VAR16] = VAR2;
end
3'b100 : begin
VAR12[7:0] = VAR33 & VAR20;
VAR29[VAR5] = 1'b1;
end
3'b101 : begin
VAR12[7:0] = VAR33 ^ VAR20;
VAR29[VAR5] = 1'b0;
end
default : begin
VAR12[7:0] = VAR33 | VAR20;
VAR29[VAR5] = 1'b0;
end
endcase
if (VAR14[2:0] == 3'b111 )
begin VAR29[VAR1] = VAR20[3];
VAR29[VAR34] = VAR20[5];
end
else
begin
VAR29[VAR1] = VAR12[3];
VAR29[VAR34] = VAR12[5];
end
if (VAR12[7:0] == 8'b00000000 )
begin
VAR29[VAR15] = 1'b1;
if (VAR9 == 1'b1 )
begin
VAR29[VAR15] = VAR10[VAR15]; end
end
else
begin
VAR29[VAR15] = 1'b0;
end
VAR29[VAR17] = VAR12[7];
case (VAR14[2:0])
3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : ;
default :
VAR29[VAR16] = ~(^VAR12);
endcase
if (VAR18 == 1'b1 )
begin
VAR29[VAR17] = VAR10[VAR17];
VAR29[VAR15] = VAR10[VAR15];
VAR29[VAR16] = VAR10[VAR16];
end
end
4'b1100 :
begin
VAR29[VAR5] = VAR10[VAR5];
VAR29[VAR26] = VAR10[VAR26];
VAR36[7:0] = VAR33;
VAR36[8] = 1'b0;
if (VAR10[VAR30] == 1'b0 )
begin
if (VAR36[3:0] > 9 || VAR10[VAR5] == 1'b1 )
begin
if ((VAR36[3:0] > 9) )
begin
VAR29[VAR5] = 1'b1;
end
else
begin
VAR29[VAR5] = 1'b0;
end
VAR36 = VAR36 + 6;
end
if (VAR36[8:4] > 9 || VAR10[VAR26] == 1'b1 )
begin
VAR36 = VAR36 + 96; end
end
else
begin
if (VAR36[3:0] > 9 || VAR10[VAR5] == 1'b1 )
begin
if (VAR36[3:0] > 5 )
begin
VAR29[VAR5] = 1'b0;
end
VAR36[7:0] = VAR36[7:0] - 6;
end
if (VAR33 > 153 || VAR10[VAR26] == 1'b1 )
begin
VAR36 = VAR36 - 352; end
end
VAR29[VAR1] = VAR36[3];
VAR29[VAR34] = VAR36[5];
VAR29[VAR26] = VAR10[VAR26] || VAR36[8];
VAR12 = VAR36[7:0];
if (VAR36[7:0] == 8'b00000000 )
begin
VAR29[VAR15] = 1'b1;
end
else
begin
VAR29[VAR15] = 1'b0;
end
VAR29[VAR17] = VAR36[7];
VAR29[VAR16] = ~ (^VAR36);
end
4'b1101, 4'b1110 :
begin
VAR12[7:4] = VAR33[7:4];
if (VAR14[0] == 1'b1 )
begin
VAR12[3:0] = VAR20[7:4];
end
else
begin
VAR12[3:0] = VAR20[3:0];
end
VAR29[VAR5] = 1'b0;
VAR29[VAR30] = 1'b0;
VAR29[VAR1] = VAR12[3];
VAR29[VAR34] = VAR12[5];
if (VAR12[7:0] == 8'b00000000 )
begin
VAR29[VAR15] = 1'b1;
end
else
begin
VAR29[VAR15] = 1'b0;
end
VAR29[VAR17] = VAR12[7];
VAR29[VAR16] = ~(^VAR12);
end
4'b1001 :
begin
VAR12[7:0] = VAR20 & VAR32;
VAR29[VAR17] = VAR12[7];
if (VAR12[7:0] == 8'b00000000 )
begin
VAR29[VAR15] = 1'b1;
VAR29[VAR16] = 1'b1;
end
else
begin
VAR29[VAR15] = 1'b0;
VAR29[VAR16] = 1'b0;
end
VAR29[VAR5] = 1'b1;
VAR29[VAR30] = 1'b0;
VAR29[VAR1] = 1'b0;
VAR29[VAR34] = 1'b0;
if (VAR19[2:0] != 3'b110 )
begin
VAR29[VAR1] = VAR20[3];
VAR29[VAR34] = VAR20[5];
end
end
4'b1010 :
VAR12[7:0] = VAR20 | VAR32;
4'b1011 :
VAR12[7:0] = VAR20 & ~ VAR32;
4'b1000 :
begin
case (VAR19[5:3])
3'b000 : begin
VAR12[7:1] = VAR33[6:0];
VAR12[0] = VAR33[7];
VAR29[VAR26] = VAR33[7];
end
3'b010 : begin
VAR12[7:1] = VAR33[6:0];
VAR12[0] = VAR10[VAR26];
VAR29[VAR26] = VAR33[7];
end
3'b001 : begin
VAR12[6:0] = VAR33[7:1];
VAR12[7] = VAR33[0];
VAR29[VAR26] = VAR33[0];
end
3'b011 : begin
VAR12[6:0] = VAR33[7:1];
VAR12[7] = VAR10[VAR26];
VAR29[VAR26] = VAR33[0];
end
3'b100 : begin
VAR12[7:1] = VAR33[6:0];
VAR12[0] = 1'b0;
VAR29[VAR26] = VAR33[7];
end
3'b110 : begin
if (VAR24 == 3 )
begin
VAR12[7:4] = VAR33[3:0];
VAR12[3:0] = VAR33[7:4];
VAR29[VAR26] = 1'b0;
end
else
begin
VAR12[7:1] = VAR33[6:0];
VAR12[0] = 1'b1;
VAR29[VAR26] = VAR33[7];
end end
3'b101 : begin
VAR12[6:0] = VAR33[7:1];
VAR12[7] = VAR33[7];
VAR29[VAR26] = VAR33[0];
end
default : begin
VAR12[6:0] = VAR33[7:1];
VAR12[7] = 1'b0;
VAR29[VAR26] = VAR33[0];
end
endcase
VAR29[VAR5] = 1'b0;
VAR29[VAR30] = 1'b0;
VAR29[VAR1] = VAR12[3];
VAR29[VAR34] = VAR12[5];
VAR29[VAR17] = VAR12[7];
if (VAR12[7:0] == 8'b00000000 )
begin
VAR29[VAR15] = 1'b1;
end
else
begin
VAR29[VAR15] = 1'b0;
end
VAR29[VAR16] = ~(^VAR12);
if (VAR31 == 2'b00 )
begin
VAR29[VAR16] = VAR10[VAR16];
VAR29[VAR17] = VAR10[VAR17];
VAR29[VAR15] = VAR10[VAR15];
end
end
default :
;
endcase
VAR27 = VAR12;
end
endmodule | gpl-3.0 |
SymbiFlow/nextpnr | ice40/benchmark/picorv32.v | 92,423 | module MODULE1 #(
parameter [ 0:0] VAR1 = 1,
parameter [ 0:0] VAR69 = 1,
parameter [ 0:0] VAR16 = 1,
parameter [ 0:0] VAR74 = 1,
parameter [ 0:0] VAR20 = 0,
parameter [ 0:0] VAR90 = 1,
parameter [ 0:0] VAR38 = 0,
parameter [ 0:0] VAR60 = 0,
parameter [ 0:0] VAR18 = 0,
parameter [ 0:0] VAR79 = 0,
parameter [ 0:0] VAR57 = 1,
parameter [ 0:0] VAR83 = 1,
parameter [ 0:0] VAR8 = 0,
parameter [ 0:0] VAR2 = 0,
parameter [ 0:0] VAR92 = 0,
parameter [ 0:0] VAR96 = 0,
parameter [ 0:0] VAR97 = 0,
parameter [ 0:0] VAR82 = 1,
parameter [ 0:0] VAR76 = 1,
parameter [ 0:0] VAR105 = 0,
parameter [ 0:0] VAR40 = 0,
parameter [31:0] VAR58 = 32'VAR30 00000000,
parameter [31:0] VAR100 = 32'VAR30 VAR67,
parameter [31:0] VAR88 = 32'VAR30 00000000,
parameter [31:0] VAR36 = 32'VAR30 00000010,
parameter [31:0] VAR56 = 32'VAR30 VAR67
) (
input clk, VAR89,
output reg VAR32,
output reg VAR98,
output reg VAR42,
input VAR7,
output reg [31:0] VAR104,
output reg [31:0] VAR101,
output reg [ 3:0] VAR23,
input [31:0] VAR77,
output VAR81,
output VAR15,
output [31:0] VAR21,
output reg [31:0] VAR13,
output reg [ 3:0] VAR41,
output reg VAR54,
output reg [31:0] VAR5,
output [31:0] VAR70,
output [31:0] VAR27,
input VAR63,
input [31:0] VAR43,
input VAR26,
input VAR14,
input [31:0] irq,
output reg [31:0] VAR52,
output reg VAR10,
output reg [63:0] VAR91,
output reg [31:0] VAR86,
output reg VAR34,
output reg VAR3,
output reg VAR46,
output reg [ 4:0] VAR62,
output reg [ 4:0] VAR95,
output reg [31:0] VAR25,
output reg [31:0] VAR65,
output reg [ 4:0] VAR39,
output reg [31:0] VAR87,
output reg [31:0] VAR61,
output reg [31:0] VAR59,
output reg [31:0] VAR11,
output reg [ 3:0] VAR45,
output reg [ 3:0] VAR102,
output reg [31:0] VAR55,
output reg [31:0] VAR9,
output reg VAR29,
output reg [35:0] VAR80
);
localparam integer VAR75 = 0;
localparam integer VAR99 = 1;
localparam integer VAR4 = 2;
localparam integer VAR31 = VAR16 ? 32 : 16;
localparam integer VAR85 = (VAR16 ? 32 : 16) + 4*VAR97*VAR82;
localparam integer VAR103 = (VAR16 ? 5 : 4) + VAR97*VAR82;
localparam VAR64 = VAR8 || VAR2 || VAR92 || VAR96;
localparam [35:0] VAR6 = {4'VAR33 0001, 32'VAR33 0};
localparam [35:0] VAR71 = {4'VAR33 0010, 32'VAR33 0};
localparam [35:0] VAR49 = {4'VAR33 1000, 32'VAR33 0};
reg [63:0] VAR94, VAR107;
reg [31:0] VAR19, VAR17, VAR66, VAR22, VAR78;
reg [4:0] VAR68;
reg [31:0] VAR24;
reg [31:0] VAR37;
reg [31:0] VAR93;
wire VAR50 = VAR98;
wire VAR109 = VAR42;
wire VAR44 = VAR7;
wire [31:0] VAR73 = VAR104;
wire [31:0] VAR108 = VAR101;
wire [ 3:0] VAR28 = VAR23;
wire [31:0] VAR12 = VAR77;
assign VAR70 = VAR66;
assign VAR27 = VAR22;
wire [31:0] VAR47;
reg VAR53;
reg VAR72;
reg [31:0] VAR35;
reg [31:0] VAR106;
reg [31:0] VAR48;
reg [31:0] VAR51 [0:VAR85-1];
integer VAR84; | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai_2.v | 2,261 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR8 ,
VAR3 ,
VAR5,
VAR4,
VAR7 ,
VAR6
);
output VAR1 ;
input VAR9 ;
input VAR8 ;
input VAR3 ;
input VAR5;
input VAR4;
input VAR7 ;
input VAR6 ;
VAR2 VAR10 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR1 ,
VAR9,
VAR8,
VAR3
);
output VAR1 ;
input VAR9;
input VAR8;
input VAR3;
supply1 VAR5;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR6 ;
VAR2 VAR10 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_pll.v | 11,149 | module MODULE1
(
VAR8,
VAR2,
VAR3,
VAR1) ;
input VAR8;
input VAR2;
input [0:0] VAR3;
output [0:0] VAR1;
tri0 VAR8;
tri1 VAR2;
reg [0:0] VAR7;
reg [0:0] VAR4;
reg [0:0] VAR10;
wire VAR5;
wire VAR6;
wire VAR9; | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/intra/intra_ctrl.v | 25,832 | module MODULE1(
clk ,
VAR6 ,
VAR39 ,
VAR32 ,
VAR31 ,
VAR21 ,
VAR17 ,
VAR43 ,
VAR5 ,
VAR7 ,
VAR8 ,
VAR15 ,
VAR13 ,
VAR35 ,
VAR42 ,
VAR22 ,
VAR25 ,
VAR24 ,
VAR29 ,
VAR30 ,
VAR2 ,
VAR4
);
localparam VAR9 = 'd00 ,
VAR33 = 'd01 ,
VAR10 = 'd02 ,
VAR41 = 'd03 ,
VAR34 = 'd04 ,
VAR16 = 'd05 ,
VAR26 = 'd06 ,
VAR28 = 'd07 ,
VAR23 = 'd08 ,
VAR44 = 'd09 ,
VAR36 = 'd10 ;
input clk ;
input VAR6 ;
input VAR39 ;
output reg VAR32 ;
input VAR31 ;
input [20 : 0] VAR21 ;
output reg VAR17 ;
output reg [9 : 0] VAR43 ;
input [5 : 0] VAR5 ;
output reg VAR7 ;
input VAR8 ;
input VAR15 ;
output reg [1 : 0] VAR13 ;
output reg [5 : 0] VAR35 ;
output reg [1 : 0] VAR42 ;
output reg [7 : 0] VAR22 ;
output reg VAR25 ;
output [5 : 0] VAR24 ;
output [1 : 0] VAR29 ;
output [1 : 0] VAR30 ;
output reg [3 : 0] VAR2 ;
output reg [3 : 0] VAR4 ;
reg [5 : 0] VAR19 ;
reg VAR1 ;
reg [3 : 0] state ;
reg [3 : 0] VAR20 ;
wire [7 : 0] VAR14 ;
reg [1 : 0] VAR11 ;
wire VAR40 ;
wire [3 : 0] VAR27 ;
wire [15 : 0] VAR3 ;
wire VAR18 ;
wire VAR37 ;
reg [7 : 0] VAR38 ;
always @(posedge clk or negedge VAR6) begin
if(!VAR6)
state <= VAR9;
end
else begin
state <= VAR20 ;
end
end
always @ begin
if( VAR42==2'b00 )
VAR38 = 'd0 ;
end
else begin
case( VAR13 )
2'b00 : VAR38 = VAR22 + 'd04 ;
2'b01 : VAR38 = VAR22 + 'd16 ;
2'b10 : VAR38 = VAR22 + 'd64 ;
default : VAR38 = 'VAR12 ;
endcase
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 )
VAR32 <= 'd0 ;
end
else if( VAR32 )
VAR32 <= 'd0 ;
else if( (VAR8) && ( ((state==VAR26)&&(VAR22[7:0]==8'b11111100)) ||
((state==VAR23)&&(VAR22[7:0]==8'b11110000)) ||
((state==VAR36)&&(VAR22[7:0]==8'b11000000)) ||
((state==VAR34 )&&(VAR22[7:0]==8'b11000000))&&(VAR11==2'b00)
)
) begin
VAR32 <= 'd1 ;
end
end
always @(posedge clk or negedge VAR6) begin
if(!VAR6)
VAR17 <= 'd0;
end
else begin
if( VAR17 ) begin
VAR17 <= 'd0;
end
else begin
if( state==VAR9 ) begin
if( VAR39 ) begin
VAR17 <= 'd1;
end
end
else begin
if( VAR8 ) begin
case( state )
VAR16 ,
VAR28 ,
VAR44 : VAR17 <= 'd0 ;
default : VAR17 <= 'd1 ;
endcase
end
end
end
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 )
VAR43 <= 'd0;
end
else begin
if( state==VAR9 ) begin
if( VAR39 ) begin
VAR43 <= 'd0;
end
end
else begin
if( VAR8 ) begin
if( (VAR42!=2'b00) || ((state==VAR34)&&(VAR22[7:0]==8'b11000000)) )
if( VAR31==1'b0 )
case( VAR11 )
2'b01 : VAR43 <= VAR38[7:6] + VAR38[7:4] + VAR38[7:2]*5 + 4 ;
2'b10 : VAR43 <= VAR38[7:6] + VAR38[7:4]*21 + 20;
2'b11 : VAR43 <= VAR38[7:6]*85 + 84 ;
endcase
end
else begin
case( VAR11 )
2'b01 : VAR43 <= VAR38[7:6] + VAR38[7:4] + VAR38[7:2] ;
2'b10 : VAR43 <= VAR38[7:6] + VAR38[7:4]*5 + 4 ;
2'b11 : VAR43 <= VAR38[7:6]*21 + 20;
endcase
end
else begin
VAR43 <= VAR43 + 'd1 ;
end
end
end
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 ) begin
VAR7 <= 'd0 ;
end
else begin
if( VAR7 ) begin
VAR7 <= 'd0 ;
end
else begin
if( state==VAR9 ) begin
if( VAR39 ) begin
VAR7 <= 'd1 ;
end
end
else begin
if( VAR8 && ( ! ((state==VAR26)&&(VAR22[7:0]==8'b11111100)) )
&& ( ! ((state==VAR23)&&(VAR22[7:0]==8'b11110000)) )
&& ( ! ((state==VAR36)&&(VAR22[7:0]==8'b11000000)) )
&& ( ! ((state==VAR34 )&&(VAR22[7:0]==8'b11000000)&&(VAR11==2'b00)) )
) begin
VAR7 <= 'd1 ;
end
end
end
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 ) begin
VAR13 <= 2'b00 ;
end
else begin
case( VAR20 )
VAR33 ,VAR16 ,VAR26 : VAR13 <= 2'b00 ;
VAR10 ,VAR28 ,VAR23 : VAR13 <= 2'b01 ;
VAR41 ,VAR44 ,VAR36 : VAR13 <= 2'b10 ;
VAR34 : VAR13 <= 2'b11 ;
endcase
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 )
VAR1 <= 'd0 ;
end
else begin
VAR1 <= VAR17 ;
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 )
VAR35 <= 'd0 ;
end
else begin
if( VAR1 ) begin
VAR35 <= VAR5 ;
end
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 )
VAR42 <= 'd0 ;
end
else begin
case( VAR20 )
VAR33 ,VAR10 ,VAR41 ,VAR34 : VAR42 <= 2'b00 ;
VAR16,VAR28,VAR44 : VAR42 <= 2'b10 ;
VAR26,VAR23,VAR36 : VAR42 <= 2'b11 ;
default : VAR42 <= 2'b00 ;
endcase
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 )
VAR22 <= 'd0 ;
end
else begin
if( VAR42==2'b00 ) begin
case( state )
VAR9 : begin if( VAR39 ) VAR22 <= 'd0 ;
end
VAR33 : begin if( VAR8 ) begin
if( VAR22[1:0]==2'b11 ) VAR22 <= VAR22 - 'd03 ;
end
else VAR22 <= VAR22 + 'd01 ;
end
end
VAR10 : begin if( VAR8 ) begin
if( VAR22[3:0]==4'b1100 ) VAR22 <= VAR22 - 'd12 ;
end
else VAR22 <= VAR22 + 'd04 ;
end
end
VAR41 : begin if( VAR8 ) begin
if( VAR22[5:0]==6'b110000 ) VAR22 <= VAR22 - 'd48 ;
end
else VAR22 <= VAR22 + 'd16 ;
end
end
VAR34 : begin if( VAR8 ) begin
if( VAR22[7:0]==8'b11000000 ) VAR22 <= 'd0 ;
end
else VAR22 <= VAR22 + 'd64 ;
end
end
endcase
end
else begin
if( VAR8 ) begin
case( state )
end
VAR26: begin if( VAR22[7:0]==8'b11111100 ) VAR22 <= 'd0 ; else VAR22 <= VAR22 + 'd04 ;
end
VAR23: begin if( VAR22[7:0]==8'b11110000 ) VAR22 <= 'd0 ; else VAR22 <= VAR22 + 'd16 ;
end
VAR36: begin if( VAR22[7:0]==8'b11000000 ) VAR22 <= 'd0 ; else VAR22 <= VAR22 + 'd64 ;
end
endcase
end
end
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 ) begin
VAR19 <= 'd0 ;
end
else begin
if( VAR15 ) begin
VAR19 <= 'd0 ;
end
else begin
if( VAR25 )
VAR19 <= VAR19+1 ;
end
end
end
always @(posedge clk or negedge VAR6) begin
if( !VAR6 ) begin
VAR25 <= 'd0 ;
end
else begin
if( VAR15 ) begin
VAR25 <= 'd1 ;
end
else begin
case( state )
VAR33 ,VAR16 ,VAR26: begin if( VAR25 ) VAR25 <= 'd0;
end
VAR10 ,VAR28 ,VAR23: begin if( VAR19=='d3 ) VAR25 <= 'd0;
end
VAR41 ,VAR44 ,VAR36: begin if( VAR19=='d15 ) VAR25 <= 'd0;
end
VAR34: begin if( VAR19=='d63 ) VAR25 <= 'd0;
end
endcase
end
end
end
assign VAR24 = VAR35 ;
assign VAR29 = VAR42 ;
assign VAR30 = VAR13 ;
assign VAR14 = (VAR42==2'b00) ? VAR22 : (VAR22>>2) ;
always @(posedge clk or negedge VAR6) begin
if(!VAR6) begin
VAR4 <= 'd0;
VAR2 <= 'd0;
end
else begin
if(VAR15) begin
VAR4 <= {VAR14[7], VAR14[5], VAR14[3], VAR14[1]};
VAR2 <= {VAR14[6], VAR14[4], VAR14[2], VAR14[0]};
end
else begin
if(VAR25) begin
case(VAR30)
2'b01: begin if(!VAR2[0]) VAR2 <= VAR2+1;
end
else begin VAR2 <= {VAR14[6], VAR14[4], VAR14[2], VAR14[0]};
VAR4 <= VAR4+1;
end
end
2'b10: begin if(VAR2[1:0]!=2'b11) VAR2 <= VAR2+1;
end
else begin VAR2 <= {VAR14[6], VAR14[4], VAR14[2], VAR14[0]};
VAR4 <= VAR4+1;
end
end
2'b11: begin if(VAR2[2:0]!=3'b111) VAR2 <= VAR2+1;
end
else begin VAR2 <= {VAR14[6], VAR14[4], VAR14[2], VAR14[0]};
VAR4 <= VAR4+1;
end
end
endcase
end
end
end
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111a/sky130_fd_sc_ls__o2111a.behavioral.pp.v | 2,074 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR16 ,
VAR18 ,
VAR10 ,
VAR14 ,
VAR17,
VAR2,
VAR12 ,
VAR9
);
output VAR3 ;
input VAR11 ;
input VAR16 ;
input VAR18 ;
input VAR10 ;
input VAR14 ;
input VAR17;
input VAR2;
input VAR12 ;
input VAR9 ;
wire VAR5 ;
wire VAR1 ;
wire VAR8;
or VAR7 (VAR5 , VAR16, VAR11 );
and VAR15 (VAR1 , VAR18, VAR10, VAR5, VAR14 );
VAR4 VAR6 (VAR8, VAR1, VAR17, VAR2);
buf VAR13 (VAR3 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4bb/sky130_fd_sc_hd__nor4bb_4.v | 2,325 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR8,
VAR11,
VAR2 ,
VAR10
);
output VAR4 ;
input VAR9 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR8;
input VAR11;
input VAR2 ;
input VAR10 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR10(VAR10)
);
endmodule
module MODULE1 (
VAR4 ,
VAR9 ,
VAR7 ,
VAR1,
VAR3
);
output VAR4 ;
input VAR9 ;
input VAR7 ;
input VAR1;
input VAR3;
supply1 VAR8;
supply0 VAR11;
supply1 VAR2 ;
supply0 VAR10 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b_2.v | 2,245 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR9,
VAR2,
VAR3 ,
VAR8
);
output VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR9;
input VAR2;
input VAR3 ;
input VAR8 ;
VAR5 VAR10 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR4 ,
VAR6,
VAR7 ,
VAR1
);
output VAR4 ;
input VAR6;
input VAR7 ;
input VAR1 ;
supply1 VAR9;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR8 ;
VAR5 VAR10 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi.behavioral.v | 1,552 | module MODULE1 (
VAR14 ,
VAR6,
VAR1,
VAR4,
VAR5
);
output VAR14 ;
input VAR6;
input VAR1;
input VAR4;
input VAR5;
supply1 VAR2;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR8 ;
wire VAR13 ;
wire VAR9;
and VAR12 (VAR13 , VAR4, VAR6, VAR1 );
nor VAR10 (VAR9, VAR5, VAR13 );
buf VAR11 (VAR14 , VAR9 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9434_v1_00_a/hdl/verilog/axi_ad9434_pnmon.v | 10,294 | module MODULE1 (
VAR10,
VAR14,
VAR15,
VAR6,
VAR7);
input VAR10;
input [47:0] VAR14;
output VAR15;
output VAR6;
input VAR7;
reg [47:0] VAR4 = 'd0;
reg [ 6:0] VAR5 = 'd0;
reg VAR15 = 'd0;
reg VAR6 = 'd0;
wire [47:0] VAR9;
wire VAR13;
wire VAR8;
wire VAR12;
wire [47:0] VAR3;
wire VAR2;
wire VAR16;
function [47:0] VAR11;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[22] ^ din[17];
dout[46] = din[21] ^ din[16];
dout[45] = din[20] ^ din[15];
dout[44] = din[19] ^ din[14];
dout[43] = din[18] ^ din[13];
dout[42] = din[17] ^ din[12];
dout[41] = din[16] ^ din[11];
dout[40] = din[15] ^ din[10];
dout[39] = din[14] ^ din[ 9];
dout[38] = din[13] ^ din[ 8];
dout[37] = din[12] ^ din[ 7];
dout[36] = din[11] ^ din[ 6];
dout[35] = din[10] ^ din[ 5];
dout[34] = din[ 9] ^ din[ 4];
dout[33] = din[ 8] ^ din[ 3];
dout[32] = din[ 7] ^ din[ 2];
dout[31] = din[ 6] ^ din[ 1];
dout[30] = din[ 5] ^ din[ 0];
dout[29] = din[ 4] ^ din[22] ^ din[17];
dout[28] = din[ 3] ^ din[21] ^ din[16];
dout[27] = din[ 2] ^ din[20] ^ din[15];
dout[26] = din[ 1] ^ din[19] ^ din[14];
dout[25] = din[ 0] ^ din[18] ^ din[13];
dout[24] = din[22] ^ din[12];
dout[23] = din[21] ^ din[11];
dout[22] = din[20] ^ din[10];
dout[21] = din[19] ^ din[ 9];
dout[20] = din[18] ^ din[ 8];
dout[19] = din[17] ^ din[ 7];
dout[18] = din[16] ^ din[ 6];
dout[17] = din[15] ^ din[ 5];
dout[16] = din[14] ^ din[ 4];
dout[15] = din[13] ^ din[ 3];
dout[14] = din[12] ^ din[ 2];
dout[13] = din[11] ^ din[ 1];
dout[12] = din[10] ^ din[ 0];
dout[11] = din[ 9] ^ din[22] ^ din[17];
dout[10] = din[ 8] ^ din[21] ^ din[16];
dout[ 9] = din[ 7] ^ din[20] ^ din[15];
dout[ 8] = din[ 6] ^ din[19] ^ din[14];
dout[ 7] = din[ 5] ^ din[18] ^ din[13];
dout[ 6] = din[ 4] ^ din[17] ^ din[12];
dout[ 5] = din[ 3] ^ din[16] ^ din[11];
dout[ 4] = din[ 2] ^ din[15] ^ din[10];
dout[ 3] = din[ 1] ^ din[14] ^ din[ 9];
dout[ 2] = din[ 0] ^ din[13] ^ din[ 8];
dout[ 1] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[ 0] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
VAR11 = dout;
end
endfunction
function [47:0] VAR1;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[ 8] ^ din[ 4];
dout[46] = din[ 7] ^ din[ 3];
dout[45] = din[ 6] ^ din[ 2];
dout[44] = din[ 5] ^ din[ 1];
dout[43] = din[ 4] ^ din[ 0];
dout[42] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[41] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[40] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[39] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[38] = din[ 8] ^ din[ 0];
dout[37] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[36] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[35] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[34] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[33] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[32] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[31] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[30] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[29] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[28] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[27] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[26] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[25] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[24] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[23] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[22] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[21] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[20] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[19] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[18] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[17] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[16] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[15] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[14] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[13] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[11] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[10] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[ 9] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 8] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8];
dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7];
dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6];
dout[ 4] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5];
dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1];
dout[ 2] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0];
dout[ 1] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3];
VAR1 = dout;
end
endfunction
assign VAR9 = {VAR14[11:0], VAR14[23:12], VAR14[35:24], VAR14[47:36]};
assign VAR13 = (VAR9 == VAR4) ? 1'b1 : 1'b0;
assign VAR8 = (VAR9 == 48'd0) ? 1'b0 : 1'b1;
assign VAR12 = VAR13 & VAR8;
assign VAR3 = (VAR15 == 1'b1) ? VAR9 : VAR4;
assign VAR2 = ~(VAR15 ^ VAR12);
assign VAR16 = ~(VAR15 | VAR12);
always @(posedge VAR10) begin
if (VAR7 == 1'b0) begin
VAR4 <= VAR1(VAR3);
end else begin
VAR4 <= VAR11(VAR3);
end
end
always @(posedge VAR10) begin
if (VAR2 == 1'b1) begin
if (VAR5 >= 16) begin
VAR5 <= 'd0;
VAR15 <= ~VAR15;
end else begin
VAR5 <= VAR5 + 1'b1;
VAR15 <= VAR15;
end
end else begin
VAR5 <= 'd0;
VAR15 <= VAR15;
end
VAR6 <= VAR16;
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba.blackbox.v | 1,345 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR5 ,
VAR1
);
output VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR1;
supply1 VAR3;
supply0 VAR4;
endmodule | apache-2.0 |
eleqian/WiDSO | CPLD/DSO_LA/src/reg_rw.v | 2,584 | module MODULE1(en, din, dout);
input en;
input [2:0] din;
output reg [7:0] dout;
always @ begin
case (addr)
3'h0: dout <= VAR4;
3'h1: dout <= VAR3;
3'h2: dout <= VAR2;
3'h3: dout <= VAR1;
3'h4: dout <= VAR6;
3'h5: dout <= VAR8;
3'h6: dout <= VAR5;
3'h7: dout <= VAR7;
default: dout <= 8'b0;
endcase
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2.symbol.v | 1,301 | module MODULE1 (
input VAR3,
input VAR6,
output VAR7
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp.behavioral.v | 2,202 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR10 ,
VAR17
);
output VAR4 ;
input VAR8 ;
input VAR10 ;
input VAR17;
supply1 VAR6;
supply0 VAR12;
supply1 VAR14 ;
supply0 VAR9 ;
wire VAR5 ;
wire VAR18 ;
reg VAR11 ;
wire VAR21 ;
wire VAR15;
wire VAR20 ;
wire VAR13 ;
wire VAR16 ;
wire VAR1 ;
not VAR3 (VAR18 , VAR15 );
VAR2 VAR7 (VAR5 , VAR21, VAR20, VAR18, VAR11, VAR6, VAR12);
assign VAR13 = ( VAR6 === 1'b1 );
assign VAR16 = ( VAR13 && ( VAR15 === 1'b1 ) );
assign VAR1 = ( VAR13 && ( VAR17 === 1'b1 ) );
buf VAR19 (VAR4 , VAR5 );
endmodule | apache-2.0 |
mballance/oc_wb_ip | rtl/wb_uart/uart_wb.v | 11,880 | module MODULE1 #(
parameter reg VAR3=1,
parameter reg VAR26=0,
parameter reg VAR6=1) (
clk, VAR23, VAR24, VAR7, VAR19, VAR4, VAR21,
VAR29, VAR22, VAR27, VAR1, VAR5, VAR10, VAR12,
VAR25, VAR17 );
parameter int VAR13 = (VAR26==1)?8:32;
input clk;
input VAR23;
input VAR24;
input VAR7;
input VAR19;
input [3:0] VAR12;
input [VAR28-1:0] VAR21;
input [VAR13-1:0] VAR22; output [VAR13-1:0] VAR27;
reg [VAR13-1:0] VAR27;
wire [VAR13-1:0] VAR22;
reg [VAR13-1:0] VAR14;
output [VAR28-1:0] VAR29; input [7:0] VAR5; output [7:0] VAR1;
input [31:0] VAR10; output VAR4;
output VAR25;
output VAR17;
wire VAR25;
reg VAR4;
reg [7:0] VAR1;
wire [7:0] VAR5;
wire [VAR28-1:0] VAR29; reg [VAR28-1:0] VAR15;
reg VAR8;
reg VAR16;
reg VAR11;
reg [3:0] VAR18;
wire [3:0] VAR12;
reg VAR20 ;
reg [1:0] VAR9;
always @(posedge clk or posedge VAR23)
if (VAR23) begin
VAR4 <= 1'b0;
VAR9 <= 0;
VAR20 <= 1'b1;
end else
case (VAR9)
0: begin
if (VAR11 & VAR16) begin
VAR20 <= 0;
VAR9 <= 1;
VAR4 <= 1;
end else begin
VAR20 <= 1;
VAR4 <= 0;
end
end
1: begin
VAR4 <= 0;
VAR9 <= 2;
VAR20 <= 0;
end
2,3: begin
VAR4 <= 0;
VAR9 <= 0;
VAR20 <= 0;
end
endcase
assign VAR25 = VAR8 & VAR11 & VAR16 & VAR20 ; assign VAR17 = ~VAR8 & VAR11 & VAR16 & VAR20 ;
always @(posedge clk or posedge VAR23)
if (VAR23) begin
VAR15 <= 0;
VAR8 <= 0;
VAR16 <= 0;
VAR11 <= 0;
VAR14 <= 0;
VAR18 <= 0;
end else begin
VAR15 <= VAR21;
VAR8 <= VAR24;
VAR16 <= VAR19;
VAR11 <= VAR7;
VAR14 <= VAR22;
VAR18 <= VAR12;
end
generate
if (VAR26 == 1) begin
always @(posedge clk or posedge VAR23)
if (VAR23)
VAR27 <= 0;
end
else
VAR27 <= VAR5;
always @(VAR14)
VAR1 = VAR14;
assign VAR29 = VAR15;
end else begin if (VAR6 == 1) begin
always @(posedge clk or posedge VAR23) begin
if (VAR23) begin
VAR27 <= 0;
end else if (VAR17) begin
VAR27 <= {VAR5, VAR5, VAR5, VAR5};
end
end
always @(VAR18 or VAR14) begin
VAR1 = VAR14[7:0];
end
assign VAR29 = {2'b0, VAR15[VAR28-1:2]};
end else begin always @(posedge clk or posedge VAR23)
if (VAR23)
VAR27 <= 0;
end
else if (VAR17)
case (VAR18)
4'b0001: VAR27 <= {24'b0, VAR5};
4'b0010: VAR27 <= {16'b0, VAR5, 8'b0};
4'b0100: VAR27 <= {8'b0, VAR5, 16'b0};
4'b1000: VAR27 <= {VAR5, 24'b0};
4'b1111: VAR27 <= VAR10; default: VAR27 <= 0;
endcase
reg [1:0] VAR2;
always @(VAR18 or VAR14)
begin
case (VAR18)
4'b0001 : VAR1 = VAR14[7:0];
4'b0010 : VAR1 = VAR14[15:8];
4'b0100 : VAR1 = VAR14[23:16];
4'b1000 : VAR1 = VAR14[31:24];
default : VAR1 = VAR14[7:0];
endcase
if (VAR3 == 1) begin
case (VAR18)
4'b0001 : VAR2 = 2'h0;
4'b0010 : VAR2 = 2'h1;
4'b0100 : VAR2 = 2'h2;
4'b1000 : VAR2 = 2'h3;
default : VAR2 = 2'h0;
endcase end else begin case (VAR18)
4'b0001 : VAR2 = 2'h3;
4'b0010 : VAR2 = 2'h2;
4'b0100 : VAR2 = 2'h1;
4'b1000 : VAR2 = 2'h0;
default : VAR2 = 2'h0;
endcase end
end
assign VAR29 = {VAR15[VAR28-1:2], VAR2};
end
end
endgenerate
endmodule | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/CPU/controlunit6.v | 7,280 | module MODULE1 (output reg VAR10, VAR16, VAR6, VAR14, VAR8, VAR21, VAR2, VAR5,VAR20,VAR1,VAR9,VAR15,VAR22,output reg[4:0] VAR19, output reg[3:0] VAR11, input VAR7, VAR13,VAR18, input [31:0] VAR3,input [3:0] VAR17);
reg [4:0] VAR4, VAR12;
always @ (negedge VAR18, posedge VAR13)
if (VAR13) begin
VAR4 <= 5'b00001;VAR21 = 0 ; VAR10= 0 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ;VAR11=0; VAR19=5'b10010;end
else
VAR4 <= VAR12;
always @ (VAR4, VAR7)
case (VAR4)
5'b00000 : VAR12 = 5'b00000;
5'b00001 : if(VAR7) VAR12 = 5'b10001 ; else VAR12 = 5'b00010; 5'b00010 : VAR12 = 5'b00011;
5'b00011 : if(VAR7)VAR12 = 5'b00100; else VAR12 = 5'b00011;
5'b00100 : VAR12 = 5'b00101;
5'b00101 : case(VAR3[31:28]) 4'b0000: if(VAR17[2]==1) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b0001: if(VAR17[2]==0) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b0010: if(VAR17[1]==1) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b0011: if(VAR17[1]==0) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b0100: if(VAR17[3]==1) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b0101: if(VAR17[3]==0) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b0110: if(VAR17[0]==1) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b0111: if(VAR17[0]==0) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b1000: if(VAR17[1]==1&VAR17[2]==0) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b1001: if(VAR17[1]==0|VAR17[2]==1) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b1010: if(VAR17[3]==VAR17[0]) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b1011: if(VAR17[3]!=VAR17[0]) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b1100: if(VAR17[2]==0&VAR17[3]==VAR17[0]) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b1101: if(VAR17[2]==1|VAR17[3]!=VAR17[0]) VAR12 = 5'b00110; else VAR12 = 5'b00001;
4'b1110: VAR12 = 5'b00110;
endcase
5'b00110 : case(VAR3[27:25])
3'b000,3'b001:VAR12 = 5'b00111;
3'b010,3'b011:VAR12 = 5'b01000; 3'b101:VAR12 = 5'b01110; default:VAR12 = 5'b0001;
endcase
5'b00111 : VAR12 = 5'b00001; 5'b01000 : if(VAR3[24] == 0 & VAR3[0] ==0 ) VAR12 = 5'b01001; else if(VAR3[20]) VAR12 = 5'b01010;else VAR12 = 5'b01011; 5'b01001 : if(VAR3[20]) VAR12 = 5'b01010;else VAR12 = 5'b01011; 5'b01010 : if(VAR7) VAR12 = 5'b01100; else VAR12 = 5'b01010; 5'b01011 : VAR12 = 5'b01101; 5'b01100 : VAR12 = 5'b00001; 5'b01101 : if(VAR7) VAR12 = 5'b00001 ; else VAR12 = 5'b01101; 5'b01110 : VAR12 = 5'b00001; 5'b01111 : VAR12 = 5'b10000; 5'b10000 : VAR12 = 5'b00001; 5'b10001 : if(VAR7) VAR12 = 5'b10001 ; else VAR12 = 5'b00010; endcase
always @ (VAR4, VAR7)
case (VAR4)
5'b00000 : begin end
5'b00001 : begin VAR21 = 1 ;VAR10= 0 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 1 ; VAR11=4'hf;VAR19=5'b10010;end 5'b00010 : begin VAR21 = 1 ;VAR10= 0 ; VAR16= 0 ; VAR6= 1 ; VAR14= 0 ; VAR8= 0 ; VAR2= 1 ; VAR5= 1 ;VAR20= 1 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ; VAR11=4'hf;VAR19=5'b10001;end 5'b00011 : begin VAR21 = 0 ;VAR10= 0 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 1 ; VAR5= 1 ;VAR20= 1 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ; VAR11=4'hf;VAR19=5'b10010;end 5'b00100 : begin VAR21 = 0 ;VAR10= 0 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 1 ;VAR9= 0 ;VAR15= 1 ;VAR22 = 0 ; VAR11=4'hf;VAR19=5'b10010;end 5'b00101 : begin VAR21 = 1 ;VAR10=1 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ; VAR11=4'h0;end 5'b00110 : begin VAR21 = 0 ;VAR10= 1 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ;end 5'b00111 : begin VAR21 = 1 ;VAR10= 1 ; VAR16= 1 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ;VAR19 = {1'b0,VAR3[24:21]};end 5'b01000 : begin VAR21 = 1 ;VAR10= 1 ; VAR16= VAR3[21]==1&VAR3[24]==1 ? 1 : 0; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 1 ;VAR19 = VAR3[24] == 0 & VAR3[0] ==0 ? 5'b10010 : VAR3[23] ? 5'b00100:5'b00010 ; end 5'b01001 : begin VAR21 = 1 ;VAR10= 1 ; VAR16=1; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ;VAR19 = VAR3[23] ? 5'b00100:5'b00010 ; end 5'b01010 : begin VAR21 = 0 ;VAR10= 0 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 1 ; VAR5= 1 ;VAR20= 1 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ;end 5'b01011 : begin VAR21 = 1 ;VAR10= 1 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 1 ;VAR15= 0 ;VAR22 = 0 ; VAR19=5'b10010; end 5'b01100 : begin VAR21 = 0 ;VAR10= 1 ; VAR16= 1 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 1 ;VAR22 = 0 ;end 5'b01101 : begin VAR21 = 0 ;VAR10= 0 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 1 ; VAR5= 1 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ;end 5'b01110 : begin VAR21 = 1 ;VAR10= 0 ; VAR16= 0 ; VAR6= 1 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ; VAR11=4'hf;VAR19=5'b00100;end 5'b01111 : begin end
5'b10000 : begin end
5'b10001 : begin VAR21 = 0 ;VAR10= 0 ; VAR16= 0 ; VAR6= 0 ; VAR14= 0 ; VAR8= 0 ; VAR2= 0 ; VAR5= 0 ;VAR20= 0 ;VAR1= 0 ;VAR9= 0 ;VAR15= 0 ;VAR22 = 0 ; VAR11=4'hf;VAR19=5'b10001;end
default : begin end
endcase
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/start_for_Loop_lojbC.v | 3,003 | module MODULE2 (
clk,
VAR2,
VAR19,
VAR22,
VAR4);
parameter VAR13 = 32'd1;
parameter VAR18 = 32'd2;
parameter VAR7 = 32'd3;
input clk;
input [VAR13-1:0] VAR2;
input VAR19;
input [VAR18-1:0] VAR22;
output [VAR13-1:0] VAR4;
reg[VAR13-1:0] VAR10 [0:VAR7-1];
integer VAR14;
always @ (posedge clk)
begin
if (VAR19)
begin
for (VAR14=0;VAR14<VAR7-1;VAR14=VAR14+1)
VAR10[VAR14+1] <= VAR10[VAR14];
VAR10[0] <= VAR2;
end
end
assign VAR4 = VAR10[VAR22];
endmodule
module MODULE1 (
clk,
reset,
VAR17,
VAR11,
VAR16,
VAR25,
VAR27,
VAR15,
VAR6,
VAR9);
parameter VAR23 = "VAR12";
parameter VAR13 = 32'd1;
parameter VAR18 = 32'd2;
parameter VAR7 = 32'd3;
input clk;
input reset;
output VAR17;
input VAR11;
input VAR16;
output[VAR13 - 1:0] VAR25;
output VAR27;
input VAR15;
input VAR6;
input[VAR13 - 1:0] VAR9;
wire[VAR18 - 1:0] VAR24 ;
wire[VAR13 - 1:0] VAR21, VAR5;
wire VAR26;
reg[VAR18:0] VAR1 = {(VAR18+1){1'b1}};
reg VAR3 = 0, VAR8 = 1;
assign VAR17 = VAR3;
assign VAR27 = VAR8;
assign VAR21 = VAR9;
assign VAR25 = VAR5;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR1 <= ~{VAR18+1{1'b0}};
VAR3 <= 1'b0;
VAR8 <= 1'b1;
end
else begin
if (((VAR16 & VAR11) == 1 & VAR3 == 1) &&
((VAR6 & VAR15) == 0 | VAR8 == 0))
begin
VAR1 <= VAR1 - 1;
if (VAR1 == 0)
VAR3 <= 1'b0;
VAR8 <= 1'b1;
end
else if (((VAR16 & VAR11) == 0 | VAR3 == 0) &&
((VAR6 & VAR15) == 1 & VAR8 == 1))
begin
VAR1 <= VAR1 + 1;
VAR3 <= 1'b1;
if (VAR1 == VAR7 - 2)
VAR8 <= 1'b0;
end
end
end
assign VAR24 = VAR1[VAR18] == 1'b0 ? VAR1[VAR18-1:0]:{VAR18{1'b0}};
assign VAR26 = (VAR6 & VAR15) & VAR8;
MODULE2
.VAR13(VAR13),
.VAR18(VAR18),
.VAR7(VAR7))
VAR20 (
.clk(clk),
.VAR2(VAR21),
.VAR19(VAR26),
.VAR22(VAR24),
.VAR4(VAR5));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp.behavioral.pp.v | 1,788 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR4 ,
VAR5,
VAR6,
VAR12 ,
VAR2
);
output VAR1 ;
input VAR11 ;
input VAR4 ;
input VAR5;
input VAR6;
input VAR12 ;
input VAR2 ;
wire VAR8 ;
reg VAR3 ;
wire VAR7 ;
wire VAR14;
wire VAR13 ;
VAR9 VAR10 (VAR8 , VAR7, VAR14, VAR3, VAR5, VAR6);
assign VAR13 = ( VAR5 === 1'b1 );
buf VAR15 (VAR1 , VAR8 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/traffic_gen/mcb_flow_control.v | 17,386 | module MODULE1 #
(
parameter VAR22 = 100,
parameter VAR21 = "VAR54"
)
(
input VAR37,
input [9:0] VAR52,
output reg VAR59,
input VAR62,
input [2:0] VAR31,
input [31:0] VAR33,
input [5:0] VAR39,
input VAR34,
output reg [2:0] VAR29,
output reg [31:0] VAR10,
output reg [5:0] VAR56,
output VAR15, input VAR9,
input VAR63,
output VAR45,
output VAR42,
output VAR26,
output [31:0] VAR43,
output [5:0] VAR55,
input VAR20,
input VAR30,
output VAR12,
output [31:0] VAR53,
output [5:0] VAR5
);
localparam VAR32 = 5'b00001,
VAR6 = 5'b00010,
VAR49 = 5'b00100,
VAR57 = 5'b01000,
VAR3 = 5'b10000;
localparam VAR58 = 3'b001;
localparam VAR36 = 3'b011;
localparam VAR11 = 3'b000;
localparam VAR48 = 3'b010;
localparam VAR16 = 3'b100;
localparam VAR19 = 3'b101;
reg VAR64;
wire VAR35;
wire VAR60; wire VAR18;
reg VAR41;
reg VAR51;
reg VAR2 ;
reg VAR47;
reg VAR38;
reg [2:0] VAR23;
reg [31:0] VAR44;
reg [5:0] VAR7;
reg VAR13;
reg VAR17,VAR14,VAR24;
reg [4:0] VAR61;
reg [4:0] VAR46;
reg [3:0] VAR28;
reg VAR4;
reg VAR50;
reg VAR27 ;
reg VAR40;
reg VAR1;
assign VAR15 = VAR27;
always @ (posedge VAR37) begin
end
always @ (posedge VAR37)
begin
if (VAR52[8])
end
else if ( VAR51)
else if (!VAR34)
end
always @ (posedge VAR37)
begin
if (VAR52[9])
end
else if (VAR51)
else if (!VAR34)
end
always @ (posedge VAR37)
begin
if (VAR52[9]) begin
end
else if (VAR51 ) begin
if (VAR21 == "VAR54")
end
else
end
end
assign VAR43 = VAR33;
assign VAR53 = VAR33;
assign VAR5 = VAR39 ;
assign VAR55 = VAR39 ;
assign VAR45 = VAR17;
assign VAR42 = VAR14;
assign VAR26 = VAR24;
assign VAR12 = VAR13;
always @ (posedge VAR37)
begin
if (VAR52[8])
end
else if (VAR4)
else if (VAR59 && VAR62 && VAR21 == "VAR54")
end
always @ (posedge VAR37)
begin
end
always @ (posedge VAR37)
if (VAR41)
begin
end
assign VAR60 = ((VAR31 == VAR11 | VAR31 == VAR48) & VAR62 ) ? 1'b1 : 1'b0;
assign VAR35 = ((VAR31 == VAR58 | VAR31 == VAR36) & VAR62) ? 1'b1 : 1'b0;
assign VAR18 = ((VAR31[2] == 1'b1)& VAR62 && (VAR21 == "VAR54")) ? 1'b1 : 1'b0;
reg VAR8;
reg VAR25;
always @ (posedge VAR37)
begin
if (VAR52[0])
end
else if ( VAR9 )
end
always @ (posedge VAR37)
begin
if (VAR35 & VAR41)
end
else if (VAR51)
end
always @ (posedge VAR37)
begin
if (VAR52[0])
end
else if (VAR9)
else if (VAR61 == VAR49)
end
always @ (posedge VAR37)
begin
if (VAR52[0])
end
else
end
always @ (*)
begin
VAR41 = 1'b0;
VAR51 = 1'b0;
VAR17 = 1'b0;
VAR14 = 1'b0;
VAR24 = 1'b0;
VAR13 = 1'b0;
VAR38 = 1'b0;
VAR46 = VAR61;
case(VAR61)
VAR32:
begin
if(VAR30 & VAR35 & VAR64)
begin
VAR46 = VAR6;
VAR41 = 1'b1;
VAR51 = 1'b0;
VAR13 = 1'b1;
end
else if (VAR63 & VAR60 & VAR64)
begin
VAR46 = VAR49;
VAR41 = 1'b1;
VAR17 = 1'b1;
VAR14 = 1'b1;
VAR24 = 1'b1;
end
else if ( VAR18 & VAR64)
begin
VAR46 = VAR3;
VAR41 = 1'b1;
VAR51 = 1'b0;
end
else
begin
VAR46 = VAR32;
VAR41 = 1'b0;
end
if (VAR64)
VAR38 = 1'b1;
end
else
VAR38 = 1'b0;
end
VAR3 : begin
if (VAR30 && VAR35 && VAR64 )
begin
VAR46 = VAR6;
VAR41 = 1'b1;
VAR13 = 1'b1;
VAR17 = 1'b0;
VAR51 = 1'b1;
end
else if (VAR64 && VAR60 && VAR63 )
begin
VAR46 = VAR49;
VAR41 = 1'b1;
VAR51 = 1'b1;
VAR17 = 1'b1;
VAR14 = 1'b1;
VAR24 = 1'b1;
end
else if (VAR64 && VAR18)
begin
VAR41 = 1'b1;
VAR51 = 1'b1;
end
else if (!VAR64)
begin
VAR46 = VAR57;
VAR28 = 4'b1001;
end
else
VAR46 = VAR6;
if (VAR64 && ((VAR30 && VAR35) || (VAR63 && VAR60) || (VAR18)))
VAR38 = 1'b1;
end
else
VAR38 = 1'b0;
end
VAR6: begin
if (VAR30 && VAR35 && VAR64 )
begin
VAR46 = VAR6;
VAR41 = 1'b1;
VAR13 = 1'b1;
VAR17 = 1'b0;
VAR51 = 1'b1;
VAR28 = 4'b0101;
end
else if (VAR64 && VAR60 && VAR63 )
begin
VAR46 = VAR49;
VAR41 = 1'b1;
VAR51 = 1'b1;
VAR17 = 1'b1;
VAR14 = 1'b1;
VAR24 = 1'b1;
VAR28 = 4'b0110;
end
else if (!VAR30 )
begin
VAR46 = VAR6;
VAR41 = 1'b0;
VAR51 = 1'b0;
VAR28 = 4'b0111;
VAR17 = 1'b0;
VAR14 = 1'b0;
VAR24 = 1'b0;
VAR13 = 1'b0;
end
else if (VAR20 && VAR18 && VAR64 )
begin
VAR46 = VAR3;
VAR41 = 1'b1;
VAR51 = 1'b1;
VAR17 = 1'b0;
VAR14 = 1'b0;
VAR24 = 1'b0;
VAR13 = 1'b0;
VAR28 = 4'b1000;
end
else if (!VAR64 || !VAR63)
begin
VAR46 = VAR57;
VAR28 = 4'b1001;
end
else
VAR46 = VAR6;
if ((VAR30 && VAR35 || VAR60 && VAR63 || VAR18) && VAR64)
end
VAR38 = VAR50; else
VAR38 = 1'b0;
end
VAR49: begin if (VAR64 && VAR35 && VAR30 && VAR9)
begin
VAR46 = VAR6;
VAR41 = 1'b1;
VAR51 = 1'b1;
VAR13 = 1'b1;
VAR28 = 4'b0000;
end
else if (!VAR63 || (VAR63 && VAR60 && VAR64 && VAR9) )
begin
VAR46 = VAR49;
VAR28 = 4'b0001;
if (VAR60 && VAR9) begin
VAR17 = 1'b1;
VAR14 = 1'b1;
VAR24 = 1'b1;
end
else begin
VAR17 = 1'b0;
VAR14 = 1'b0;
VAR24 = 1'b0;
end
if (VAR9 ) begin
VAR41 = 1'b1;
VAR51 = 1'b1;
end
else begin
VAR41 = 1'b0;
VAR51 = 1'b0;
end
end
else if (VAR9 && VAR18 && VAR64)
begin
VAR46 = VAR3;
VAR41 = 1'b1;
VAR51 = 1'b1;
VAR28 = 4'b0010;
VAR17 = 1'b0;
VAR14 = 1'b0;
VAR24 = 1'b0;
VAR13 = 1'b0;
end
else if (!VAR64 && VAR9 || !VAR30 || (!VAR62 && VAR50) )
begin
VAR46 = VAR57;
VAR41 = 1'b0;
VAR51 = 1'b0;
VAR28 = 4'b0011;
end
else begin
VAR46 = VAR49;
VAR28 = 4'b0100;
end
if (VAR9 && (VAR18 || VAR30 && VAR35 || VAR60 && VAR63) && VAR64)
end
VAR38 = VAR50; else
VAR38 = 1'b0;
end
VAR57: if (!VAR64 || VAR40)
begin
VAR46 = VAR57;
VAR38 = 1'b0;
VAR28 = 4'b1010;
end
else if (VAR64 && VAR30 && VAR35)
begin
VAR46 = VAR6;
VAR41 = 1'b1;
VAR51 = 1'b1;
VAR38 = 1'b1;
VAR13 = 1'b1;
VAR28 = 4'b1011;
end
else if (VAR64 && VAR60 && (VAR50 || VAR8))
begin
VAR46 = VAR49;
VAR41 = 1'b1;
VAR51 = 1'b1;
VAR17 = 1'b1;
VAR14 = 1'b1;
VAR24 = 1'b1;
VAR38 = 1'b1;
VAR28 = 4'b1100;
end
else if (VAR64 && VAR18)
begin
VAR46 = VAR3;
VAR41 = 1'b1; VAR51 = 1'b1;
VAR28 = 4'b1101;
VAR38 = 1'b1;
end
else
begin
VAR46 = VAR57;
VAR28 = 4'b1110;
if ((VAR63 && VAR30))
VAR38 = 1'b1;
end
else
VAR38 = 1'b0;
end
default:
begin
VAR41 = 1'b0;
VAR51 = 1'b0;
VAR17 = 1'b0;
VAR14 = 1'b0;
VAR24 = 1'b0;
VAR46 = VAR32;
end
endcase
end
endmodule | lgpl-3.0 |
Elphel/x393_sata | x393/util_modules/resync_data.v | 4,081 | module MODULE1
parameter integer VAR4=16,
parameter integer VAR9=4, parameter VAR8 = 0
) (
input VAR5, input VAR13, input VAR1, input VAR10, input VAR11, input VAR6, input [VAR4-1:0] VAR14, output reg [VAR4-1:0] VAR12, output reg valid );
localparam integer VAR7=(1<<VAR9)-1;
reg [VAR4-1:0] VAR3 [0:VAR7];
reg [VAR9-1:0] VAR15;
reg [VAR9-1:0] VAR2;
reg [1:0] VAR16 = 3;
always @ (posedge VAR10 or posedge VAR5) begin
if (VAR5) valid <= 0;
end
else if (VAR13) valid <= 0;
else if (&VAR2[VAR9-2:0] && VAR11) valid <= 1; end
always @ (posedge VAR1 or posedge VAR5) begin
if (VAR5) VAR2 <= 0;
end
else if (VAR13) VAR2 <= 0;
else if (VAR11) VAR2 <= VAR2 + 1;
end
always @ (posedge VAR10 or posedge VAR5) begin
if (VAR5) VAR16 <= 3;
end
else if (VAR13) VAR16 <= 3; else VAR16 <= VAR16 << 1;
if (VAR5) VAR15 <= 0;
else if (VAR16[0]) VAR15 <= 0;
else if (VAR6 || VAR16[1]) VAR15 <= VAR15 + 1;
if (VAR5) VAR12 <= VAR8;
else if (VAR16[0]) VAR12 <= VAR8;
else if (VAR6 || VAR16[1]) VAR12 <= VAR3[VAR15];
end
always @ (posedge VAR1) begin
if (VAR11) VAR3[VAR2] <= VAR14;
end
endmodule | gpl-3.0 |
efabless/openlane | designs/sha3/src/sha3.v | 25,477 | module MODULE2(
input wire clk,
input wire VAR51,
input wire VAR32,
input wire VAR33,
input wire [7 : 0] address,
input wire [31 : 0] VAR7,
output wire [31 : 0] VAR13
);
localparam VAR113 = 8'h00;
localparam VAR26 = 8'h01;
localparam VAR14 = 8'h02;
localparam VAR22 = 8'h08;
localparam VAR124 = 0;
localparam VAR62 = 1;
localparam VAR114 = 8'h09;
localparam VAR66 = 0;
localparam VAR28 = 1;
localparam VAR48 = 2;
localparam VAR146 = 8'h10;
localparam VAR96 = 8'h2f;
localparam VAR50 = 8'h40;
localparam VAR57 = 8'h4f;
localparam VAR122 = 32'h7368612d; localparam VAR67 = 32'h33202020; localparam VAR56 = 32'h302e3130;
localparam VAR79 = 2'h0;
localparam VAR142 = 2'h1;
localparam VAR64 = 2'h2;
localparam VAR16 = 2'h3;
reg VAR71;
reg VAR60;
reg VAR75;
reg VAR49;
reg [1 : 0] VAR8;
reg [1 : 0] VAR12;
reg VAR104;
reg VAR131;
reg [31 : 0] VAR83 [0 : 31];
reg [4 : 0] VAR24;
reg VAR73;
reg [511 : 0] VAR36;
reg [7 : 0] VAR133;
reg VAR53;
wire VAR108;
wire VAR21;
wire [1 : 0] VAR140;
wire VAR42;
wire [31 : 0] VAR29;
wire VAR15;
wire [1023 : 0] VAR105;
wire [511 : 0] VAR9;
wire VAR40;
reg [31 : 0] VAR41;
assign VAR108 = VAR71;
assign VAR21 = VAR75;
assign VAR140 = VAR8;
assign VAR105 = {VAR83[00], VAR83[01], VAR83[02], VAR83[03],
VAR83[04], VAR83[04], VAR83[05], VAR83[07],
VAR83[08], VAR83[09], VAR83[10], VAR83[11],
VAR83[12], VAR83[13], VAR83[14], VAR83[15],
VAR83[16], VAR83[17], VAR83[18], VAR83[19],
VAR83[20], VAR83[21], VAR83[22], VAR83[23],
VAR83[24], VAR83[24], VAR83[25], VAR83[27],
VAR83[28], VAR83[29], VAR83[30], VAR83[31]};
assign VAR13 = VAR41;
MODULE1 MODULE1(
.clk(clk),
.VAR51(VAR51),
.VAR136(VAR108),
.VAR132(VAR21),
.VAR88(VAR140),
.VAR112(VAR105),
.ready(VAR15),
.VAR52(VAR9),
.VAR77(VAR40)
);
always @ (posedge clk)
begin : VAR27
integer VAR135;
if (!VAR51)
begin
VAR71 <= 0;
VAR75 <= 0;
VAR8 <= VAR142;
VAR131 <= 0;
VAR36 <= 512'h0;
VAR53 <= 0;
for (VAR135 = 0 ; VAR135 < 32 ; VAR135 = VAR135 + 1)
VAR83[VAR135] = 32'h0;
end
else
begin
VAR131 <= VAR15;
VAR53 <= VAR40;
VAR71 <= VAR60;
VAR75 <= VAR49;
if (VAR104)
VAR8 <= VAR7[3 : 2];
if (VAR40)
VAR36 <= VAR9;
if (VAR73)
VAR83[VAR24] <= VAR7;
end
end
always @*
begin : VAR87
VAR60 = 0;
VAR49 = 0;
VAR104 = 0;
VAR73 = 0;
VAR41 = 32'h0;
VAR24 = address - VAR146;
VAR133 = 8'h10 - (address - VAR50);
if (VAR32)
begin
if (VAR33)
begin
if ((address >= VAR146) && (address <= VAR96))
VAR73 = 1;
case (address)
VAR22:
begin
VAR60 = VAR7[VAR124];
VAR49 = VAR7[VAR62];
VAR104 = 1;
end
default:
begin
end
endcase end
else
begin
if ((address >= VAR146) && (address <= VAR96))
VAR41 = VAR83[VAR24];
if ((address >= VAR50) && (address <= VAR57))
VAR41 = VAR36[32 * VAR133 -: 32];
case (address)
VAR113:
VAR41 = VAR122;
VAR26:
VAR41 = VAR67;
VAR14:
VAR41 = VAR56;
VAR22:
VAR41 = {28'h0, VAR8, VAR75, VAR71};
VAR114:
VAR41 = {30'h0, VAR53, VAR131};
default:
begin
end
endcase end
end
end endmodule
module MODULE1(
input wire clk,
input wire VAR51,
input wire VAR136,
input wire VAR132,
input wire [1 : 0] VAR88,
input wire VAR18,
input wire [31 : 0] VAR10,
input wire [1023 : 0] VAR112,
output wire ready,
output wire [511 : 0] VAR52,
output wire VAR77
);
parameter VAR43 = 79;
parameter VAR17 = 0;
parameter VAR118 = 1;
parameter VAR102 = 2;
reg [63 : 0] VAR107;
reg [63 : 0] VAR38;
reg [63 : 0] VAR61;
reg [63 : 0] VAR76;
reg [63 : 0] VAR101;
reg [63 : 0] VAR99;
reg [63 : 0] VAR147;
reg [63 : 0] VAR25;
reg [63 : 0] VAR89;
reg [63 : 0] VAR106;
reg [63 : 0] VAR126;
reg [63 : 0] VAR129;
reg [63 : 0] VAR145;
reg [63 : 0] VAR58;
reg [63 : 0] VAR55;
reg [63 : 0] VAR70;
reg VAR46;
reg [63 : 0] VAR95;
reg [63 : 0] VAR138;
reg [63 : 0] VAR78;
reg [63 : 0] VAR11;
reg [63 : 0] VAR35;
reg [63 : 0] VAR100;
reg [63 : 0] VAR1;
reg [63 : 0] VAR63;
reg [63 : 0] VAR54;
reg [63 : 0] VAR45;
reg [63 : 0] VAR111;
reg [63 : 0] VAR5;
reg [63 : 0] VAR72;
reg [63 : 0] VAR94;
reg [63 : 0] VAR20;
reg [63 : 0] VAR144;
reg VAR59;
reg [6 : 0] VAR97;
reg [6 : 0] VAR134;
reg VAR2;
reg VAR139;
reg VAR109;
reg [31 : 0] VAR141;
reg [31 : 0] VAR116;
reg VAR92;
reg VAR91;
reg VAR130;
reg VAR115;
reg VAR53;
reg VAR110;
reg VAR19;
reg [1 : 0] VAR3;
reg [1 : 0] VAR98;
reg VAR85;
reg VAR39;
reg VAR93;
reg VAR68;
reg VAR103;
reg VAR143;
reg VAR84;
reg [63 : 0] VAR119;
reg [63 : 0] VAR82;
wire [63 : 0] VAR6;
reg VAR69;
reg VAR74;
wire [63 : 0] VAR44;
wire [63 : 0] VAR65;
wire [63 : 0] VAR23;
wire [63 : 0] VAR120;
wire [63 : 0] VAR4;
wire [63 : 0] VAR81;
wire [63 : 0] VAR31;
wire [63 : 0] VAR127;
wire [63 : 0] VAR117;
assign ready = VAR84;
assign VAR52 = {VAR95, VAR78, VAR35, VAR1,
VAR54, VAR111, VAR72, VAR20};
assign VAR77 = VAR53;
always @ (posedge clk or negedge VAR51)
begin : VAR27
if (!VAR51)
begin
VAR107 <= 64'h0000000000000000;
VAR61 <= 64'h0000000000000000;
VAR101 <= 64'h0000000000000000;
VAR147 <= 64'h0000000000000000;
VAR89 <= 64'h0000000000000000;
VAR126 <= 64'h0000000000000000;
VAR145 <= 64'h0000000000000000;
VAR55 <= 64'h0000000000000000;
VAR95 <= 64'h0000000000000000;
VAR78 <= 64'h0000000000000000;
VAR35 <= 64'h0000000000000000;
VAR1 <= 64'h0000000000000000;
VAR54 <= 64'h0000000000000000;
VAR111 <= 64'h0000000000000000;
VAR72 <= 64'h0000000000000000;
VAR20 <= 64'h0000000000000000;
VAR141 <= 32'h00000000;
VAR53 <= 0;
VAR97 <= 7'h00;
VAR3 <= VAR17;
end
else
begin
if (VAR46)
begin
VAR107 <= VAR38;
VAR61 <= VAR76;
VAR101 <= VAR99;
VAR147 <= VAR25;
VAR89 <= VAR106;
VAR126 <= VAR129;
VAR145 <= VAR58;
VAR55 <= VAR70;
end
if (VAR59)
begin
VAR95 <= VAR138;
VAR78 <= VAR11;
VAR35 <= VAR100;
VAR1 <= VAR63;
VAR54 <= VAR45;
VAR111 <= VAR5;
VAR72 <= VAR94;
VAR20 <= VAR144;
end
if (VAR2)
begin
VAR97 <= VAR134;
end
if (VAR115)
begin
VAR141 <= VAR116;
end
if (VAR19)
begin
VAR53 <= VAR110;
end
if (VAR85)
begin
VAR3 <= VAR98;
end
end
end
always @*
begin : VAR47
VAR138 = 64'h00000000;
VAR11 = 64'h00000000;
VAR100 = 64'h00000000;
VAR63 = 64'h00000000;
VAR45 = 64'h00000000;
VAR5 = 64'h00000000;
VAR94 = 64'h00000000;
VAR144 = 64'h00000000;
VAR59 = 0;
if (VAR39)
begin
VAR138 = VAR65;
VAR11 = VAR23;
VAR100 = VAR120;
VAR63 = VAR4;
VAR45 = VAR81;
VAR5 = VAR31;
VAR94 = VAR127;
VAR144 = VAR117;
VAR59 = 1;
end
if (VAR93)
begin
VAR138 = VAR95 + VAR107;
VAR11 = VAR78 + VAR61;
VAR100 = VAR35 + VAR101;
VAR63 = VAR1 + VAR147;
VAR45 = VAR54 + VAR89;
VAR5 = VAR111 + VAR126;
VAR94 = VAR72 + VAR145;
VAR144 = VAR20 + VAR55;
VAR59 = 1;
end
end
always @*
begin : VAR123
reg [63 : 0] VAR125;
reg [63 : 0] VAR37;
VAR125 = {VAR89[13 : 0], VAR89[63 : 14]} ^
{VAR89[17 : 0], VAR89[63 : 18]} ^
{VAR89[40 : 0], VAR89[63 : 41]};
VAR37 = (VAR89 & VAR126) ^ ((~VAR89) & VAR145);
VAR119 = VAR55 + VAR125 + VAR37 + VAR6 + VAR44;
end
always @*
begin : VAR90
reg [63 : 0] VAR86;
reg [63 : 0] VAR121;
VAR86 = {VAR107[27 : 0], VAR107[63 : 28]} ^
{VAR107[33 : 0], VAR107[63 : 34]} ^
{VAR107[38 : 0], VAR107[63 : 39]};
VAR121 = (VAR107 & VAR61) ^ (VAR107 & VAR101) ^ (VAR61 & VAR101);
VAR82 = VAR86 + VAR121;
end
always @*
begin : VAR80
VAR38 = 64'h00000000;
VAR76 = 64'h00000000;
VAR99 = 64'h00000000;
VAR25 = 64'h00000000;
VAR106 = 64'h00000000;
VAR129 = 64'h00000000;
VAR58 = 64'h00000000;
VAR70 = 64'h00000000;
VAR46 = 0;
if (VAR68)
begin
if (VAR143)
begin
VAR38 = VAR65;
VAR76 = VAR23;
VAR99 = VAR120;
VAR25 = VAR4;
VAR106 = VAR81;
VAR129 = VAR31;
VAR58 = VAR127;
VAR70 = VAR117;
VAR46 = 1;
end
else
begin
VAR38 = VAR95;
VAR76 = VAR78;
VAR99 = VAR35;
VAR25 = VAR1;
VAR106 = VAR54;
VAR129 = VAR111;
VAR58 = VAR72;
VAR70 = VAR20;
VAR46 = 1;
end
end
if (VAR103)
begin
VAR38 = VAR119 + VAR82;
VAR76 = VAR107;
VAR99 = VAR61;
VAR25 = VAR101;
VAR106 = VAR147 + VAR119;
VAR129 = VAR89;
VAR58 = VAR126;
VAR70 = VAR145;
VAR46 = 1;
end
end
always @*
begin : VAR128
VAR134 = 7'h00;
VAR2 = 0;
if (VAR109)
begin
VAR134 = 7'h00;
VAR2 = 1;
end
if (VAR139)
begin
VAR134 = VAR97 + 1'b1;
VAR2 = 1;
end
end
always @*
begin : VAR30
VAR116 = 32'h00000000;
VAR115 = 0;
VAR130 = 0;
if (VAR141 == VAR10)
begin
VAR130 = 1;
end
if (VAR92)
begin
VAR116 = 32'h00000000;
VAR115 = 1;
end
if (VAR91)
begin
VAR116 = VAR141 + 1'b1;
VAR115 = 1;
end
end
always @*
begin : VAR137
VAR39 = 0;
VAR93 = 0;
VAR68 = 0;
VAR103 = 0;
VAR143 = 0;
VAR84 = 0;
VAR69 = 0;
VAR74 = 0;
VAR139 = 0;
VAR109 = 0;
VAR110 = 0;
VAR19 = 0;
VAR92 = 0;
VAR91 = 0;
VAR98 = VAR17;
VAR85 = 0;
case (VAR3)
VAR17:
begin
VAR84 = 1;
if (VAR136)
begin
VAR92 = 1;
VAR39 = 1;
VAR69 = 1;
VAR68 = 1;
VAR143 = 1;
VAR109 = 1;
VAR110 = 0;
VAR19 = 1;
VAR98 = VAR118;
VAR85 = 1;
end
if (VAR132)
begin
VAR92 = 1;
VAR69 = 1;
VAR68 = 1;
VAR109 = 1;
VAR110 = 0;
VAR19 = 1;
VAR98 = VAR118;
VAR85 = 1;
end
end
VAR118:
begin
VAR74 = 1;
VAR103 = 1;
VAR139 = 1;
if (VAR97 == VAR43)
begin
VAR91 = 1;
VAR98 = VAR102;
VAR85 = 1;
end
end
VAR102:
begin
if (VAR18)
begin
if (!VAR130)
begin
VAR69 = 1;
VAR68 = 1;
VAR109 = 1;
VAR98 = VAR118;
VAR85 = 1;
end
else
begin
VAR93 = 1;
VAR110 = 1;
VAR19 = 1;
VAR98 = VAR17;
VAR85 = 1;
end
end
else
begin
VAR93 = 1;
VAR110 = 1;
VAR19 = 1;
VAR98 = VAR17;
VAR85 = 1;
end
end
endcase end
endmodule | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/fp_sub.v | 132,950 | module MODULE1
(
VAR5,
VAR10,
VAR8,
VAR9,
VAR2,
VAR1) ;
input VAR5;
input VAR10;
input VAR8;
input [54:0] VAR9;
input [5:0] VAR2;
output [54:0] VAR1;
reg [54:0] VAR7;
wire VAR4;
wire [31:0] VAR6;
wire [384:0] VAR3;
wire [5:0] VAR11; | apache-2.0 |
hpcn-uam/hardware_packet_train | NetFPGA10G/Verilog/tx_queue.v | 6,981 | module MODULE1
parameter VAR4 = 64 )
(
input [VAR4-1:0] VAR46,
input [VAR4/8-1:0] VAR13,
input VAR70,
input VAR77,
output VAR33,
input clk,
input reset,
output [63:0] VAR72,
output reg [ 7:0] VAR9,
output reg VAR58,
input VAR26,
input VAR54,
input [63:0] VAR47
);
localparam VAR59 = 0;
localparam VAR79 = 1;
localparam VAR53 = 2;
localparam VAR60 = 3;
wire [3:0] VAR37;
reg [7:0] VAR31;
reg [3:0] VAR28;
wire VAR61;
wire VAR67;
wire VAR2;
wire VAR56, VAR85;
reg VAR5, VAR12;
reg VAR84;
reg [2:0] state, VAR8;
reg VAR62, VAR25;
reg [4:0] word;
reg [VAR4-1:0] VAR65;
reg [VAR4/8-1:0] VAR55;
reg VAR23;
reg VAR41;
reg [63:0] VAR34;
assign VAR33 = ~VAR2;
assign VAR61 = VAR41;
VAR39 #(
.VAR15("VAR19"),
.VAR1(9'hA),
.VAR11(9'hA),
.VAR74(1),
.VAR32("VAR64"),
.VAR68("VAR64"),
.VAR50("VAR64"),
.VAR35("VAR73")
) VAR57 (
.VAR22(),
.VAR14(VAR2),
.VAR29(),
.VAR63(VAR72),
.VAR27({VAR67, VAR37}),
.VAR36(),
.VAR40(VAR56),
.VAR81(),
.VAR49(),
.VAR80(),
.VAR30(),
.VAR38(),
.VAR42(),
.VAR24(VAR65),
.VAR51({VAR61 , VAR28}),
.VAR7(VAR54),
.VAR10(VAR5),
.VAR18(reset),
.VAR3(clk),
.VAR78(VAR23 & VAR33)
);
VAR75
.VAR82 (1),
.VAR20 (9),
.VAR17(500)
) VAR76
(
.VAR43(1'b0),
.VAR83(VAR84), .VAR48(clk),
.VAR45(),
.VAR71(VAR12),
.VAR66(VAR54),
.VAR52(VAR85),
.VAR69(),
.VAR44(),
.VAR21(),
.VAR6(~reset),
.VAR16(~reset)
);
always @(posedge clk) begin
if (VAR70==1'b1) begin
if (word==5 && VAR46[63:16]==48'hFFFFFFFFFFFF) begin
VAR65[63:56]<=VAR34[23:16]; VAR65[55:48]<=VAR34[31:24]; VAR65[47:40]<=VAR34[39:32]; VAR65[39:32]<=VAR34[47:40]; VAR65[31:24]<=VAR34[55:48]; VAR65[23:16]<=VAR34[63:53];
VAR65[15:0] <= VAR46[15:0];
end
else if (word==6 && VAR46[15:0]==16'hFFFF) begin
VAR65[63:16] <= VAR46[63:16];
VAR65[15:8]<=VAR34[7:0]; VAR65[7:0]<=VAR34[15:8];
end
else begin
VAR65 <= VAR46;
end
word = word + 1;
end
if (VAR13 !=8'hFF) begin
word = 0;
VAR34 <=VAR47;
end
VAR55 <= VAR13;
VAR23 <=VAR70;
VAR41 <=VAR77;
end
always @* begin
case (VAR37)
4'h0: VAR31 = 8'h1;
4'h1: VAR31 = 8'h3;
4'h2: VAR31 = 8'h7;
4'h3: VAR31 = 8'hF;
4'h4: VAR31 = 8'h1F;
4'h5: VAR31 = 8'h3F;
4'h6: VAR31 = 8'h7F;
4'h7: VAR31 = 8'hFF;
default: VAR31 = 8'h0;
endcase
case (VAR55)
8'h1: VAR28 = 4'h0;
8'h3: VAR28 = 4'h1;
8'h7: VAR28 = 4'h2;
8'hF: VAR28 = 4'h3;
8'h1F: VAR28 = 4'h4;
8'h3F: VAR28 = 4'h5;
8'h7F: VAR28 = 4'h6;
8'hFF: VAR28 = 4'h7;
default: VAR28 = 4'h8;
endcase
end
always @* begin
VAR8 = state;
VAR5 = 1'b0;
VAR12 = 1'b0;
VAR58 = 1'b0;
VAR9 = VAR31;
case(state)
VAR59: begin
VAR9 = 8'b0;
if(~VAR85) begin
VAR12 = 1'b1;
VAR58 = 1'b1;
VAR8 = VAR79;
end
end
VAR79: begin
if(VAR26) begin
VAR5 = 1'b1;
VAR8 = VAR53;
end
end
VAR53: begin
VAR5 = 1'b1;
if(VAR67) begin
VAR8 = VAR59;
end
end
VAR60: begin
VAR8 = VAR59;
VAR9 = 8'b0;
end
endcase
end
always @(posedge VAR54) begin
if(reset) begin
state <= VAR59;
end
else begin
state <= VAR8;
end
end
always @(posedge clk) begin
VAR84 <= VAR41 & VAR23 & VAR33;
end
endmodule | gpl-2.0 |
iExalt/HelloWorld | helloworld/helloworld.v | 1,679 | module MODULE1 (clk, VAR5, VAR1, VAR2, VAR3);
input clk;
input VAR2;
input VAR3;
input [3:0] VAR1;
output reg [7:0] VAR5;
reg [31:0] counter = 0;
integer VAR4 = 0;
reg [3:0] VAR6 = 0;
always @ (posedge clk)
begin
if (counter <= 25000000)
begin
counter <= counter + 1;
end
else
begin
counter <= 0;
if (~VAR2)
begin
VAR5[VAR4] = 0;
if (VAR1[0] == 1)
begin
VAR6 = VAR6 + 1'b1;
end
if (VAR1[1] == 1)
begin
VAR6 = VAR6 + 1'b1;
end
if (VAR1[2] == 1)
begin
VAR6 = VAR6 + 1'b1;
end
if (VAR1[3] == 1)
begin
VAR6 = VAR6 + 1'b1;
end
VAR4 = VAR4 + VAR6;
if (VAR4 > 7)
begin
VAR4 = VAR4 - 8;
end
VAR5[VAR4] = 1;
end
else if (~VAR3)
begin
VAR5[VAR4] = 0;
if (VAR1[0] == 1)
begin
VAR6 = VAR6 + 1'b1;
end
if (VAR1[1] == 1)
begin
VAR6 = VAR6 + 1'b1;
end
if (VAR1[2] == 1)
begin
VAR6 = VAR6 + 1'b1;
end
if (VAR1[3] == 1)
begin
VAR6 = VAR6 + 1'b1;
end
VAR4 = VAR4 - VAR6;
if (VAR4 < 0)
begin
VAR4 = VAR4 + 8;
end
VAR5[VAR4] = 1;
end
else
begin
end
VAR5[VAR4] = ~VAR5[VAR4];
VAR6 = 0;
end
end
endmodule | gpl-3.0 |
cpulabs/mist1032isa | src/core/l1_instruction/l1_inst_cache_hit_counter.v | 3,280 | module MODULE1(
input wire VAR7,
input wire VAR5,
input wire VAR4,
input wire VAR8,
output wire [6:0] VAR9
);
reg [99:0] VAR3;
always@(posedge VAR7 or negedge VAR5)begin
if(!VAR5)begin
VAR3 <= 100'h0;
end
else begin
if(VAR4)begin
VAR3 <= {VAR3[98:0], VAR8};
end
end
end
reg [3:0] VAR6[0:9]; reg [5:0] VAR1[0:1]; reg [6:0] VAR2; always@(posedge VAR7 or negedge VAR5)begin
if(!VAR5)begin
VAR6[0] <= 4'h0;
VAR6[1] <= 4'h0;
VAR6[2] <= 4'h0;
VAR6[3] <= 4'h0;
VAR6[4] <= 4'h0;
VAR6[5] <= 4'h0;
VAR6[6] <= 4'h0;
VAR6[7] <= 4'h0;
VAR6[8] <= 4'h0;
VAR6[9] <= 4'h0;
VAR1[0] <= 6'h0;
VAR1[1] <= 6'h1;
VAR2 <= 7'h0;
end
else begin
VAR6[0] <= 4'h0
+ VAR3[0] + VAR3[1] + VAR3[2] + VAR3[3] + VAR3[4]
+ VAR3[5] + VAR3[6] + VAR3[7] + VAR3[8] + VAR3[9];
VAR6[1] <= 4'h0
+ VAR3[10] + VAR3[11] + VAR3[12] + VAR3[13] + VAR3[14]
+ VAR3[15] + VAR3[16] + VAR3[17] + VAR3[18] + VAR3[19];
VAR6[2] <= 4'h0
+ VAR3[20] + VAR3[21] + VAR3[22] + VAR3[23] + VAR3[24]
+ VAR3[25] + VAR3[26] + VAR3[27] + VAR3[28] + VAR3[29];
VAR6[3] <= 4'h0
+ VAR3[30] + VAR3[31] + VAR3[32] + VAR3[33] + VAR3[34]
+ VAR3[35] + VAR3[36] + VAR3[37] + VAR3[38] + VAR3[39];
VAR6[4] <= 4'h0
+ VAR3[40] + VAR3[41] + VAR3[42] + VAR3[43] + VAR3[44]
+ VAR3[45] + VAR3[46] + VAR3[47] + VAR3[48] + VAR3[49];
VAR6[5] <= 4'h0
+ VAR3[50] + VAR3[51] + VAR3[52] + VAR3[53] + VAR3[54]
+ VAR3[55] + VAR3[56] + VAR3[57] + VAR3[58] + VAR3[59];
VAR6[6] <= 4'h0
+ VAR3[60] + VAR3[61] + VAR3[62] + VAR3[63] + VAR3[64]
+ VAR3[65] + VAR3[66] + VAR3[67] + VAR3[68] + VAR3[69];
VAR6[7] <= 4'h0
+ VAR3[70] + VAR3[71] + VAR3[72] + VAR3[73] + VAR3[74]
+ VAR3[75] + VAR3[76] + VAR3[77] + VAR3[78] + VAR3[79];
VAR6[8] <= 4'h0
+ VAR3[80] + VAR3[81] + VAR3[82] + VAR3[83] + VAR3[84]
+ VAR3[85] + VAR3[86] + VAR3[87] + VAR3[88] + VAR3[89];
VAR6[9] <= 4'h0
+ VAR3[90] + VAR3[91] + VAR3[92] + VAR3[93] + VAR3[94]
+ VAR3[95] + VAR3[96] + VAR3[97] + VAR3[98] + VAR3[99];
VAR1[0] <= 6'h0 + VAR6[0] + VAR6[1] + VAR6[2] + VAR6[3] + VAR6[4];
VAR1[1] <= 6'h0 + VAR6[5] + VAR6[6] + VAR6[7] + VAR6[8] + VAR6[9];
VAR2 <= VAR1[0] + VAR1[1];
end
end
assign VAR9 = VAR2;
endmodule | bsd-2-clause |
dingzh/piplined-MIPS-CPU | src/LAB6/dataMemory.v | 1,963 | module MODULE1(
input VAR2,
input [31:0] address,
input [31:0] VAR1,
output wire [31:0] VAR7,
input VAR3,
input VAR5
);
wire [6:0] VAR6;
reg [31:0] VAR4 [127:0];
begin | gpl-3.0 |
merckhung/zet | cores/zet/rtl/zet_mux8_16.v | 1,281 | module MODULE1(sel, VAR5, VAR3, VAR4, VAR7, VAR1, VAR6, VAR8, VAR2, out);
input [2:0] sel;
input [15:0] VAR5, VAR3, VAR4, VAR7, VAR1, VAR6, VAR8, VAR2;
output [15:0] out;
reg [15:0] out;
always @(sel or VAR5 or VAR3 or VAR4 or VAR7 or VAR1 or VAR6 or VAR8 or VAR2)
case(sel)
3'd0: out = VAR5;
3'd1: out = VAR3;
3'd2: out = VAR4;
3'd3: out = VAR7;
3'd4: out = VAR1;
3'd5: out = VAR6;
3'd6: out = VAR8;
3'd7: out = VAR2;
endcase
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_ecc_decoder.v | 13,339 | module MODULE1 #
( parameter
VAR43 = 40,
VAR10 = 8,
VAR32 = 1,
VAR46 = 0,
VAR6 = 7,
VAR2 = 7,
VAR37 = 1
)
(
VAR3,
VAR7,
VAR4,
VAR38,
VAR13,
VAR40,
VAR21,
VAR17,
VAR36,
VAR8,
VAR41,
VAR24,
VAR5
);
localparam VAR33 = (VAR43 > 8) ? (VAR43 - VAR10) : (VAR43);
input VAR3;
input VAR7;
input [VAR6 - 1 : 0] VAR4;
input [VAR2 - 1 : 0] VAR38;
input [VAR37 - 1 : 0] VAR13;
input [VAR43 - 1 : 0] VAR40;
input VAR21;
output [VAR43 - 1 : 0] VAR17;
output VAR36;
output [VAR10 - 1 : 0] VAR8;
output VAR41;
output VAR24;
output VAR5;
reg [VAR43 - 1 : 0] VAR47;
reg [VAR43 - 1 : 0] VAR31;
reg [VAR43 - 1 : 0] VAR44;
reg [VAR43 - 1 : 0] VAR12;
reg [VAR43 - 1 : 0] VAR17;
reg VAR36;
reg [VAR10 - 1 : 0] VAR8;
reg VAR41;
reg VAR24;
reg VAR5;
wire VAR19;
wire VAR9;
wire VAR30;
reg [VAR10 - 1 : 0] VAR1;
wire [VAR43 - 1 : 0] VAR18;
wire [VAR33 - 1 : 0] VAR34;
reg VAR26;
reg [VAR33 - 1 : 0] VAR27;
reg VAR42;
reg VAR22;
reg VAR45;
reg VAR20;
reg [VAR10 - 1 : 0] VAR11;
wire VAR28 = 1'b0;
generate
genvar VAR23;
for (VAR23 = 0;VAR23 < VAR43;VAR23 = VAR23 + 1)
begin : VAR15
always @
begin
VAR47 = VAR31;
end
always @
begin
VAR1 = {VAR10{VAR28}};
end
end
else
begin
always @
begin
if (VAR13)
begin
VAR17 = {{VAR10{1'b0}}, VAR27}; VAR36 = VAR42;
VAR41 = VAR22;
VAR24 = VAR45;
VAR5 = VAR20;
VAR8 = VAR11;
end
else
begin
VAR17 = VAR40;
VAR36 = VAR21;
VAR41 = 1'b0;
VAR24 = 1'b0;
VAR5 = 1'b0;
VAR8 = VAR1;
end
end
end
else
begin
always @ (*)
begin
if (VAR13)
begin
VAR17 = {{VAR10{1'b0}}, VAR34}; VAR36 = VAR26;
VAR41 = VAR19;
VAR24 = VAR9;
VAR5 = VAR30;
VAR8 = VAR1;
end
else
begin
VAR17 = VAR40;
VAR36 = VAR21;
VAR41 = 1'b0;
VAR24 = 1'b0;
VAR5 = 1'b0;
VAR8 = VAR1;
end
end
end
end
endgenerate
generate
begin
if (VAR33 == 8 && VAR43 > 8) begin
wire [39 : 0] VAR47;
wire [32 : 0] VAR16;
assign VAR47 = {VAR18 [VAR43 - 1 : VAR33], 24'd0, VAR18 [VAR33 - 1 : 0]};
assign VAR34 = VAR16 [VAR33 - 1 : 0];
VAR35 VAR39
(
.VAR14 (VAR47 [38 : 0]),
.VAR41 (VAR19 ),
.VAR24 (VAR9 ),
.VAR5 (VAR30 ),
.VAR29 (VAR16 )
);
end
else if (VAR33 == 16)
begin
wire [39 : 0] VAR47;
wire [32 : 0] VAR16;
assign VAR47 = {VAR18 [VAR43 - 1 : VAR33], 16'd0, VAR18 [VAR33 - 1 : 0]};
assign VAR34 = VAR16 [VAR33 - 1 : 0];
VAR35 VAR39
(
.VAR14 (VAR47 [38 : 0]),
.VAR41 (VAR19 ),
.VAR24 (VAR9 ),
.VAR5 (VAR30 ),
.VAR29 (VAR16 )
);
end
else if (VAR33 == 32)
begin
VAR35 VAR39
(
.VAR14 (VAR18 [38 : 0]),
.VAR41 (VAR19 ),
.VAR24 (VAR9 ),
.VAR5 (VAR30 ),
.VAR29 (VAR34 )
);
end
else if (VAR33 == 64)
begin
VAR25 VAR39
(
.VAR14 (VAR18 ),
.VAR41 (VAR19),
.VAR24 (VAR9 ),
.VAR5 (VAR30 ),
.VAR29 (VAR34 )
);
end
end
endgenerate
endmodule | lgpl-3.0 |
CospanDesign/sdio-device | rtl/generic/crc16_2bit.v | 2,805 | module MODULE1 #(
parameter VAR6 = 16'h1021,
parameter VAR2 = 16'h0000
)(
input clk,
input rst,
input en,
input VAR1,
input VAR7,
output reg [15:0] VAR4
);
wire VAR5;
wire VAR3;
assign VAR3 = VAR7 ^ VAR4[15];
assign VAR5 = (VAR1 ^ VAR4[14]);
always @ (posedge clk) begin
if (rst) begin
VAR4 <= 0;
end
else begin
if (en) begin
VAR4[15] <= VAR4[13];
VAR4[14] <= VAR4[12];
VAR4[13] <= VAR4[11] ^ VAR3;
VAR4[12] <= VAR4[10] ^ VAR5;
VAR4[11] <= VAR4[9];
VAR4[10] <= VAR4[8];
VAR4[9] <= VAR4[7];
VAR4[8] <= VAR4[6];
VAR4[7] <= VAR4[5];
VAR4[6] <= VAR4[4] ^ VAR3;
VAR4[5] <= VAR4[3] ^ VAR5;
VAR4[4] <= VAR4[2];
VAR4[3] <= VAR4[1];
VAR4[2] <= VAR4[0];
VAR4[1] <= VAR3;
VAR4[0] <= VAR5;
end
end
end
endmodule | mit |
wyvernSemi/lm32fpga | HDL/rtl/Sdram_Controller/command.v | 18,178 | module MODULE1(
VAR6,
VAR10,
VAR7,
VAR5,
VAR4,
VAR55,
VAR37,
VAR49,
VAR16,
VAR24,
VAR8,
VAR3,
VAR29,
VAR39,
VAR46,
VAR48,
VAR28,
VAR27,
VAR11,
VAR13,
VAR19,
VAR54,
VAR60
);
input VAR6; input VAR10; input [VAR59-1:0] VAR7; input VAR5; input VAR4; input VAR55; input VAR37; input VAR49; input VAR16; input VAR24; input VAR8; input VAR3; input VAR29; output VAR39; output VAR46; output VAR48; output [11:0] VAR28; output [1:0] VAR27; output [1:0] VAR11; output VAR13; output VAR19; output VAR54; output VAR60;
reg VAR46;
reg VAR39;
reg VAR48;
reg [11:0] VAR28;
reg [1:0] VAR27;
reg [1:0] VAR11;
reg VAR13;
reg VAR19;
reg VAR54;
reg VAR60;
reg VAR18;
reg VAR41;
reg VAR56;
reg VAR40;
reg VAR53;
reg VAR14;
reg VAR2;
reg [7:0] VAR33;
reg [1:0] VAR9;
reg VAR47;
reg VAR51;
reg VAR38;
reg [6:0] VAR12;
reg VAR36;
reg VAR17;
reg VAR45;
reg VAR20;
reg [3:0] VAR25;
reg VAR52;
reg VAR50;
reg VAR30;
wire [VAR57 - 1:0] VAR44;
wire [VAR31 - 1:0] VAR1;
wire [VAR32 - 1:0] VAR58;
assign VAR44 = VAR7[VAR21 + VAR57 - 1: VAR21]; assign VAR1 = VAR7[VAR15 + VAR31 - 1:VAR15]; assign VAR58 = VAR7[VAR35 + VAR32 - 1:VAR35];
always @(posedge VAR6 or negedge VAR10)
begin
if (VAR10 == 0)
begin
VAR18 <= 0;
VAR41 <= 0;
VAR56 <= 0;
VAR40 <= 0;
VAR53 <= 0;
VAR14 <= 0;
VAR2 <= 0;
VAR33 <= 0;
VAR51 <= 0;
VAR25 <= 0;
VAR52 <= 0;
VAR50 <= 0;
VAR30 <= 0;
end
else
begin
if( VAR8 == 1 )
begin
VAR18 <= 0;
VAR41 <= 0;
VAR56 <= 0;
VAR40 <= 0;
VAR53 <= 0;
VAR14 <= 1;
VAR2 <= 0;
VAR33 <= 0;
VAR51 <= 0;
VAR25 <= 0;
VAR52 <= 0;
VAR50 <= 0;
VAR30 <= 0;
end
else
begin
VAR14 <= 0;
if ((VAR24 == 1 | VAR37 == 1) & VAR2 == 0 & VAR56 == 0 & VAR52 == 0 & VAR18 == 0 & VAR41 == 0)
VAR56 <= 1;
end
else
VAR56 <= 0;
if ((VAR4 == 1) & (VAR2 == 0) & (VAR18 == 0) & (VAR52 == 0) & (VAR24 == 0)) begin
VAR18 <= 1;
VAR50 <= 1;
end
else
VAR18 <= 0;
if ((VAR55 == 1) & (VAR2 == 0) & (VAR41 == 0) & (VAR52 == 0) & (VAR24 == 0)) begin
VAR41 <= 1;
VAR30 <= 1;
end
else
VAR41 <= 0;
if ((VAR49 == 1) & (VAR2 == 0) & (VAR40 == 0)) VAR40 <= 1;
end
else
VAR40 <= 0;
if ((VAR16 == 1) & (VAR2 == 0) & (VAR53 == 0)) VAR53 <= 1;
end
else
VAR53 <= 0;
if ((VAR56 == 1) | (VAR18 == 1) | (VAR41 == 1) | (VAR40 == 1)
| (VAR53 == 1))
begin
VAR33 <= 8'b11111111;
VAR2 <= 1;
VAR51 <= VAR18;
end
else
begin
VAR2 <= VAR33[0]; VAR33 <= (VAR33>>1);
end
if (VAR33[0] == 0 & VAR2 == 1)
begin
VAR25 <= 4'b1111;
VAR52 <= 1;
end
else
begin
if(VAR34 == 0)
begin
VAR25 <= (VAR25>>1);
VAR52 <= VAR25[0];
end
else
begin
if( (VAR50 == 0) && (VAR30 == 0) )
begin
VAR25 <= (VAR25>>1);
VAR52 <= VAR25[0];
end
else
begin
if( VAR3==1 )
begin
VAR25 <= (VAR25>>1);
VAR52 <= VAR25[0];
VAR50 <= 1'b0;
VAR30 <= 1'b0;
end
end
end
end
end
end
end
always @(posedge VAR6 or negedge VAR10)
begin
if (VAR10 == 0)
begin
VAR12 <= 0;
VAR36 <= 0;
VAR17 <= 0;
VAR48 <= 0;
end
else
begin
if (VAR34 == 0)
begin
if (VAR41 == 1)
begin
end
if (VAR43 == 1) VAR12 <= 0; else if (VAR43 == 2)
VAR12 <= 1;
end
else if (VAR43 == 4)
VAR12 <= 7;
end
else if (VAR43 == 8)
VAR12 <= 127;
VAR36 <= 1;
end
else
begin
VAR12 <= (VAR12>>1);
VAR36 <= VAR12[0];
VAR17 <= VAR36;
VAR45 <= VAR17;
VAR20 <= VAR45;
if (VAR26 == 2)
VAR48 <= VAR45;
end
else
VAR48 <= VAR20;
end
end
else
begin
if (VAR41 == 1) VAR20 <= 1;
end
else if (VAR40 == 1 | VAR18 == 1 | VAR56==1 | VAR14 == 1 | VAR3==1 )
VAR20 <= 0;
VAR48 <= VAR20;
end
end
end
always @(posedge VAR6 or negedge VAR10)
begin
if (VAR10 == 0)
begin
VAR9 <= 0;
VAR38 <= 0;
end
else
begin
if ((VAR18 == 1) | (VAR41 == 1))
begin
if (VAR26 == 1) VAR38 <= 1;
end
else if (VAR26 == 2)
VAR9 <= 1;
end
else if (VAR26 == 3)
VAR9 <= 2;
end
else
begin
VAR9 <= (VAR9>>1);
VAR38 <= VAR9[0];
end
end
end
always @(posedge VAR6 or negedge VAR10)
begin
if (VAR10 == 0)
begin
VAR46 <= 0;
VAR39 <= 0;
end
else
begin
if (VAR56 == 1 & VAR24 == 1) VAR39 <= 1;
end
else if ((VAR56 == 1) | (VAR18 == 1) | (VAR41 == 1) | (VAR40 == 1) | (VAR53))
VAR46 <= 1;
end
else
begin
VAR39 <= 0;
VAR46 <= 0;
end
end
end
always @(posedge VAR6 ) begin
if (VAR10==0) begin
VAR28 <= 0;
VAR27 <= 0;
VAR11 <= 1;
VAR19 <= 1;
VAR54 <= 1;
VAR60 <= 1;
VAR13 <= 0;
end
else begin
VAR13 <= 1;
if (VAR41 == 1 | VAR18 == 1) VAR28 <= VAR44;
end
else
VAR28 <= VAR1; if ((VAR38==1) | (VAR40))
VAR28[10] <= !VAR34; if (VAR40==1 | VAR53==1)
end
VAR27 <= 0; else
VAR27 <= VAR58[1:0];
if (VAR56==1 | VAR40==1 | VAR53==1 | VAR14==1)
VAR11 <= 0; else begin
VAR11[0] <= VAR7[VAR59-1]; VAR11[1] <= ~VAR7[VAR59-1]; end
if(VAR53==1)
VAR28 <= {2'b00,VAR23,VAR22,VAR42};
if ( VAR56==1 ) begin VAR19 <= 0;
VAR54 <= 0;
VAR60 <= 1;
end
else if ((VAR40==1) & ((VAR20 == 1) | (VAR51 == 1))) begin VAR19 <= 1;
VAR54 <= 1;
VAR60 <= 0;
end
else if (VAR40==1) begin VAR19 <= 0;
VAR54 <= 1;
VAR60 <= 0;
end
else if (VAR53==1) begin VAR19 <= 0;
VAR54 <= 0;
VAR60 <= 0;
end
else if (VAR18 == 1 | VAR41 == 1) begin VAR19 <= 0;
VAR54 <= 1;
VAR60 <= 1;
end
else if (VAR38 == 1) begin VAR19 <= 1;
VAR54 <= 0;
VAR60 <= VAR51;
end
else if (VAR14 ==1) begin
VAR19 <= 1;
VAR54 <= 1;
VAR60 <= 1;
end
else begin VAR19 <= 1;
VAR54 <= 1;
VAR60 <= 1;
end
end
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3b/sky130_fd_sc_ms__and3b.behavioral.pp.v | 1,961 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR10 ,
VAR6 ,
VAR14,
VAR11,
VAR15 ,
VAR1
);
output VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR6 ;
input VAR14;
input VAR11;
input VAR15 ;
input VAR1 ;
wire VAR8 ;
wire VAR16 ;
wire VAR2;
not VAR4 (VAR8 , VAR9 );
and VAR7 (VAR16 , VAR6, VAR8, VAR10 );
VAR12 VAR3 (VAR2, VAR16, VAR14, VAR11);
buf VAR13 (VAR5 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai_4.v | 2,297 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR6 ,
VAR7 ,
VAR3 ,
VAR9 ,
VAR1,
VAR10
);
output VAR4 ;
input VAR5 ;
input VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR9 ;
input VAR1;
input VAR10;
VAR8 VAR2 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR4 ,
VAR5,
VAR6,
VAR7,
VAR3,
VAR9
);
output VAR4 ;
input VAR5;
input VAR6;
input VAR7;
input VAR3;
input VAR9;
supply1 VAR1;
supply0 VAR10;
VAR8 VAR2 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule | apache-2.0 |
cpulabs/hdl_square_root | src/square_root32.v | 8,214 | module MODULE1(
input wire VAR36,
input wire VAR15,
input wire VAR64,
output wire VAR29,
input wire [31:0] VAR45,
output wire VAR54,
input wire VAR10,
output wire [15:0] VAR3
);
localparam VAR18 = 0;
localparam VAR34 = 1;
localparam VAR41 = 0;
localparam VAR52 = 1;
localparam VAR40 = 0;
localparam VAR6 = 1;
localparam VAR51 = 0;
localparam VAR4 = 1;
localparam VAR20 = 0;
localparam VAR11 = 1;
localparam VAR59 = 0;
localparam VAR14 = 1;
localparam VAR61 = 0;
localparam VAR38 = 1;
localparam VAR27 = 0;
localparam VAR13 = 1;
wire [15:0] VAR24;
wire [15:0] VAR46;
wire [0:0] VAR7;
wire [1:0] VAR44;
wire [2:0] VAR26;
wire [3:0] VAR49;
wire [4:0] VAR21;
wire [5:0] VAR31;
wire [6:0] VAR42;
wire [7:0] VAR1;
wire [8:0] VAR16;
wire [9:0] VAR28;
wire [10:0] VAR50;
wire [11:0] VAR56;
wire [12:0] VAR63;
wire [13:0] VAR39;
wire [14:0] VAR62;
wire [15:0] VAR57;
wire [31:0] VAR23[0:15];
VAR17 #(2, VAR18) VAR30(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR64),
.VAR29(VAR29),
.VAR22(1'b1),
.VAR47(VAR45),
.VAR54(VAR24[0]),
.VAR10(VAR46[0]),
.VAR9(VAR7),
.VAR5(VAR23[0])
);
VAR17 #(4, VAR34) VAR12(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[0]),
.VAR29(VAR46[0]),
.VAR22({VAR7, 1'b1}),
.VAR47(VAR23[0]),
.VAR54(VAR24[1]),
.VAR10(VAR46[1]),
.VAR9(VAR44),
.VAR5(VAR23[1])
);
VAR17 #(6, VAR41) VAR55(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[1]),
.VAR29(VAR46[1]),
.VAR22({VAR44, 1'b1}),
.VAR47(VAR23[1]),
.VAR54(VAR24[2]),
.VAR10(VAR46[2]),
.VAR9(VAR26),
.VAR5(VAR23[2])
);
VAR17 #(8, VAR52) VAR58(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[2]),
.VAR29(VAR46[2]),
.VAR22({VAR26, 1'b1}),
.VAR47(VAR23[2]),
.VAR54(VAR24[3]),
.VAR10(VAR46[3]),
.VAR9(VAR49),
.VAR5(VAR23[3])
);
VAR17 #(10, VAR40) VAR43(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[3]),
.VAR29(VAR46[3]),
.VAR22({VAR49, 1'b1}),
.VAR47(VAR23[3]),
.VAR54(VAR24[4]),
.VAR10(VAR46[4]),
.VAR9(VAR21),
.VAR5(VAR23[4])
);
VAR17 #(12, VAR6) VAR60(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[4]),
.VAR29(VAR46[4]),
.VAR22({VAR21, 1'b1}),
.VAR47(VAR23[4]),
.VAR54(VAR24[5]),
.VAR10(VAR46[5]),
.VAR9(VAR31),
.VAR5(VAR23[5])
);
VAR17 #(14, VAR51) VAR8(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[5]),
.VAR29(VAR46[5]),
.VAR22({VAR31, 1'b1}),
.VAR47(VAR23[5]),
.VAR54(VAR24[6]),
.VAR10(VAR46[6]),
.VAR9(VAR42),
.VAR5(VAR23[6])
);
VAR17 #(16, VAR4) VAR32(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[6]),
.VAR29(VAR46[6]),
.VAR22({VAR42, 1'b1}),
.VAR47(VAR23[6]),
.VAR54(VAR24[7]),
.VAR10(VAR46[7]),
.VAR9(VAR1),
.VAR5(VAR23[7])
);
VAR17 #(18, VAR20) VAR53(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[7]),
.VAR29(VAR46[7]),
.VAR22({VAR1, 1'b1}),
.VAR47(VAR23[7]),
.VAR54(VAR24[8]),
.VAR10(VAR46[8]),
.VAR9(VAR16),
.VAR5(VAR23[8])
);
VAR17 #(20, VAR11) VAR2(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[8]),
.VAR29(VAR46[8]),
.VAR22({VAR16, 1'b1}),
.VAR47(VAR23[8]),
.VAR54(VAR24[9]),
.VAR10(VAR46[9]),
.VAR9(VAR28),
.VAR5(VAR23[9])
);
VAR17 #(22, VAR59) VAR35(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[9]),
.VAR29(VAR46[9]),
.VAR22({VAR28, 1'b1}),
.VAR47(VAR23[9]),
.VAR54(VAR24[10]),
.VAR10(VAR46[10]),
.VAR9(VAR50),
.VAR5(VAR23[10])
);
VAR17 #(24, VAR14) VAR25(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[10]),
.VAR29(VAR46[10]),
.VAR22({VAR50, 1'b1}),
.VAR47(VAR23[10]),
.VAR54(VAR24[11]),
.VAR10(VAR46[11]),
.VAR9(VAR56),
.VAR5(VAR23[11])
);
VAR17 #(26, VAR61) VAR33(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[11]),
.VAR29(VAR46[11]),
.VAR22({VAR56, 1'b1}),
.VAR47(VAR23[11]),
.VAR54(VAR24[12]),
.VAR10(VAR46[12]),
.VAR9(VAR63),
.VAR5(VAR23[12])
);
VAR17 #(28, VAR38) VAR37(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[12]),
.VAR29(VAR46[12]),
.VAR22({VAR63, 1'b1}),
.VAR47(VAR23[12]),
.VAR54(VAR24[13]),
.VAR10(VAR46[13]),
.VAR9(VAR39),
.VAR5(VAR23[13])
);
VAR17 #(30, VAR27) VAR48(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[13]),
.VAR29(VAR46[13]),
.VAR22({VAR39, 1'b1}),
.VAR47(VAR23[13]),
.VAR54(VAR24[14]),
.VAR10(VAR46[14]),
.VAR9(VAR62),
.VAR5(VAR23[14])
);
VAR17 #(32, VAR13) VAR19(
.VAR36(VAR36),
.VAR15(VAR15),
.VAR64(VAR24[14]),
.VAR29(VAR46[14]),
.VAR22({VAR62, 1'b1}),
.VAR47(VAR23[14]),
.VAR54(VAR24[15]),
.VAR10(VAR46[15]),
.VAR9(VAR57),
.VAR5(VAR23[15])
);
assign VAR54 = VAR24[15];
assign VAR46[15] = VAR10;
assign VAR3 = VAR57;
endmodule | gpl-3.0 |
takeshineshiro/fpga_linear_128 | LOG_Table_bb.v | 5,110 | module MODULE1 (
address,
VAR2,
VAR1);
input [12:0] address;
input VAR2;
output [7:0] VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai.behavioral.pp.v | 2,174 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR1 ,
VAR16,
VAR8,
VAR5,
VAR11 ,
VAR9
);
output VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR16;
input VAR8;
input VAR5;
input VAR11 ;
input VAR9 ;
wire VAR4 ;
wire VAR17 ;
wire VAR15 ;
wire VAR2;
not VAR3 (VAR4 , VAR16 );
or VAR6 (VAR17 , VAR1, VAR7 );
nand VAR18 (VAR15 , VAR4, VAR17 );
VAR12 VAR13 (VAR2, VAR15, VAR8, VAR5);
buf VAR14 (VAR10 , VAR2 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.behavioral.v | 1,116 | module MODULE1( VAR4, VAR3 );
input VAR4;
output VAR3;
VAR5 VAR1(.VAR4(VAR4),.VAR3(VAR3));
VAR5 VAR2(.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
esonghori/TinyGarbled | circuit_synthesis/knns_td/first_nns_comb_td.v | 1,960 | module MODULE1
(
parameter VAR21 = 15,
parameter VAR31 = 32
)
(
VAR13,
VAR25,
VAR10
);
function integer VAR16;
input [31:0] VAR8;
reg [31:0] VAR24;
begin
VAR24 = VAR8;
for (VAR16=0; VAR24>0; VAR16=VAR16+1)
VAR24 = VAR24>>1;
end
endfunction
localparam VAR15 = VAR16(VAR21);
input [2*VAR21-1:0] VAR13;
input [2*VAR21*VAR31-1:0] VAR25;
output [2*VAR21-1:0] VAR10;
wire [VAR21-1:0] VAR28[VAR31-1:0];
wire [VAR21-1:0] VAR20[VAR31-1:0];
wire [VAR21-1:0] VAR18, VAR32;
wire [2*VAR21-1:0] VAR22;
assign VAR18 = VAR13[2*VAR21-1:VAR21];
assign VAR32 = VAR13[VAR21-1:0];
assign VAR22 = VAR10;
wire [VAR21+1:0] dist[VAR31-1:0];
wire [VAR21-1:0] VAR4[VAR31-1:0];
wire [VAR21-1:0] VAR11[VAR31-1:0];
wire [VAR21+1:0] VAR19[VAR31-1:0];
wire VAR27[VAR31-1:1];
genvar VAR26;
generate
for (VAR26=0;VAR26<VAR31;VAR26=VAR26+1)
begin:VAR7
assign VAR28[VAR26] = VAR25[2*VAR21*(VAR26+1)-1:2*VAR21*(VAR26+1)-VAR21];
assign VAR20[VAR26] = VAR25[2*VAR21*(VAR26+1)-VAR21-1:2*VAR21*VAR26];
end
endgenerate
generate
for (VAR26=0;VAR26<VAR31;VAR26=VAR26+1)
begin:VAR30
VAR14
.VAR31(VAR21)
)
VAR14
(
.VAR28(VAR28[VAR26]), .VAR20(VAR20[VAR26]), .VAR18(VAR18), .VAR32(VAR32),
.dist(dist[VAR26])
);
end
endgenerate
assign VAR4[0] = VAR28[0];
assign VAR11[0] = VAR20[0];
assign VAR19[0] = dist[0];
generate
for (VAR26=1;VAR26<VAR31;VAR26=VAR26+1)
begin:VAR3
VAR5
.VAR31(VAR21+2)
)
VAR5
(
.VAR23(VAR19[VAR26-1]),
.VAR9(dist[VAR26]),
.VAR17(VAR27[VAR26])
);
end
endgenerate
generate
for (VAR26=1;VAR26<VAR31;VAR26=VAR26+1)
begin:VAR29
VAR2
.VAR31(2*VAR21)
)
VAR12
(
.VAR23({VAR28[VAR26], VAR20[VAR26]}),
.VAR9({VAR4[VAR26-1], VAR11[VAR26-1]}),
.VAR6(VAR27[VAR26]),
.VAR17({VAR4[VAR26], VAR11[VAR26]})
);
VAR2
.VAR31(VAR21+2)
)
VAR1
(
.VAR23(dist[VAR26]),
.VAR9(VAR19[VAR26-1]),
.VAR6(VAR27[VAR26]),
.VAR17(VAR19[VAR26])
);
end
endgenerate
assign VAR10 = {VAR4[VAR31-1], VAR11[VAR31-1]};
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap.behavioral.pp.v | 1,121 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
MForever78/CPUFly | ipcore_dir/Instruction_Memory ([email protected] 2015-09-19-15-43-09).v | 3,976 | module MODULE1(
VAR28,
VAR21
);
input [13 : 0] VAR28;
output [31 : 0] VAR21;
VAR22 #(
.VAR13(14),
.VAR23("0"),
.VAR45(16384),
.VAR29("VAR19"),
.VAR26(0),
.VAR33(0),
.VAR54(0),
.VAR42(0),
.VAR25(0),
.VAR12(0),
.VAR3(0),
.VAR20(0),
.VAR27(0),
.VAR47(0),
.VAR7(0),
.VAR15(0),
.VAR32(0),
.VAR35(0),
.VAR34(1),
.VAR37(0),
.VAR1(0),
.VAR49("MODULE1.VAR10"),
.VAR41(0),
.VAR53(1),
.VAR51(0),
.VAR56(0),
.VAR2(0),
.VAR50(1),
.VAR18(0),
.VAR16(0),
.VAR4(1),
.VAR55(32)
)
VAR46 (
.VAR14(VAR28),
.VAR36(VAR21),
.VAR11(),
.VAR5(),
.VAR43(),
.VAR17(),
.VAR52(),
.VAR31(),
.VAR40(),
.VAR44(),
.VAR30(),
.VAR9(),
.VAR38(),
.VAR8(),
.VAR48(),
.VAR39(),
.VAR6(),
.VAR24()
);
endmodule | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_2pi_Once.v | 2,419 | module MODULE1
(
VAR8,
VAR6
);
input signed [31:0] VAR8; output signed [31:0] VAR6;
wire signed [31:0] VAR4; wire VAR2;
wire signed [31:0] VAR3; wire VAR14;
wire signed [31:0] VAR5; wire signed [31:0] VAR13; wire signed [31:0] VAR12; wire signed [31:0] VAR1; wire signed [31:0] VAR9; wire signed [31:0] VAR11;
assign VAR4 = 32'VAR7;
assign VAR2 = (VAR8 >= VAR4 ? 1'b1 :
1'b0);
assign VAR3 = 32'VAR10;
assign VAR14 = (VAR8 < VAR3 ? 1'b1 :
1'b0);
assign VAR5 = 32'VAR7;
assign VAR13 = VAR8 + VAR5;
assign VAR12 = (VAR14 == 1'b0 ? VAR8 :
VAR13);
assign VAR1 = 32'VAR7;
assign VAR9 = VAR8 - VAR1;
assign VAR11 = (VAR2 == 1'b0 ? VAR12 :
VAR9);
assign VAR6 = VAR11;
endmodule | gpl-3.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/cal_ctl.v | 17,932 | module MODULE1(VAR5,clk,reset,VAR2);
input clk;
input reset;
input [31:0] VAR5;
output [4:0] VAR2;
reg [5:0] VAR10;
reg [5:0] VAR8;
reg VAR13;
reg VAR9;
reg [4:0] VAR12;
reg [4:0] VAR2;
reg [31:0] VAR7;
reg VAR4;
always @(posedge clk)
begin
if(reset)
VAR4 <= 1'b0;
end
else if(VAR12 >= 5'd3)
VAR4 <= 1'b1;
else
VAR4 <= 1'b0;
end
always @(posedge clk)
begin
if(reset)
VAR7 <= 32'd0;
end
else if(VAR10[5] == 1'b1)
VAR7 <= VAR5;
else
VAR7 <= VAR7;
end
always @(posedge clk)
begin
if(reset || (VAR10[5] == 1'b1))
VAR10[5:0] <= 6'b0;
end
else
VAR10[5:0] <= VAR10[5:0] + 1'b1;
end
always @(posedge clk)
begin
if(reset || (VAR8[5] == 1'b1))
VAR8[5:0] <= 6'b0;
end
else
VAR8[5:0] <= VAR8[5:0] + 1'b1;
end
always @(posedge clk)
begin
if(reset || (VAR10[5] == 1'b1))
begin
VAR12 <= 5'd0;
end
else if (VAR13 & (~VAR9))
VAR12 <= VAR12 + 1;
end
else
VAR12 <= VAR12;
end
always @(posedge clk)
begin
if(reset)
begin
VAR13 <= 1'b0;
VAR9 <= 1'b0;
end
else if(VAR10[5] == 1'b1) begin
VAR13 <= 1'b0;
VAR9 <= 1'b0;
end
else if (VAR10[4:0] == 5'd0)
begin
if ((VAR7[0] ~^ VAR7[1]))
begin
VAR13 <= 1'b1;
VAR9 <= 1'b0;
end
end
else if ((VAR10[4:0] == 5'd1) & (VAR9 == 1'b0))
begin
if (VAR7[1] ~^ VAR7[2])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd2) & (VAR9 == 1'b0) )
begin
if (VAR7[2] ~^ VAR7[3])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd3) & (VAR9 == 1'b0))
begin
if (VAR7[3] ~^ VAR7[4])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd4) & (VAR9 == 1'b0))
begin
if (VAR7[4] ~^ VAR7[5])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd5) & (VAR9 == 1'b0))
begin
if (VAR7[5] ~^ VAR7[6])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd6) & (VAR9 == 1'b0))
begin
if (VAR7[6] ~^ VAR7[7])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd7) & (VAR9 == 1'b0))
begin
if (VAR7[7] ~^ VAR7[8])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd8) & (VAR9 == 1'b0))
begin
if (VAR7[8] ~^ VAR7[9])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd9) & (VAR9 == 1'b0))
begin
if (VAR7[9] ~^ VAR7[10])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd10) & (VAR9 == 1'b0))
begin
if (VAR7[10] ~^ VAR7[11])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd11) & (VAR9 == 1'b0))
begin
if (VAR7[11] ~^ VAR7[12])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd12) & (VAR9 == 1'b0))
begin
if (VAR7[12] ~^ VAR7[13])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR10[4:0] == 5'd13) & (VAR9 == 1'b0))
begin
if (VAR7[13] ~^ VAR7[14])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd14) & (VAR9 == 1'b0))
begin
if (VAR7[14] ~^ VAR7[15])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd15) & (VAR9 == 1'b0))
begin
if (VAR7[15] ~^ VAR7[16])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd16) & (VAR9 == 1'b0))
begin
if (VAR7[16] ~^ VAR7[17])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd17) & (VAR9 == 1'b0))
begin
if (VAR7[17] ~^ VAR7[18])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd18) & (VAR9 == 1'b0))
begin
if (VAR7[18] ~^ VAR7[19])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd19) & (VAR9 == 1'b0))
begin
if (VAR7[19] ~^ VAR7[20])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd20) & (VAR9 == 1'b0))
begin
if (VAR7[20] ~^ VAR7[21])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd21) & (VAR9 == 1'b0))
begin
if (VAR7[21] ~^ VAR7[22])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd22) & (VAR9 == 1'b0))
begin
if (VAR7[22] ~^ VAR7[23])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd23) & (VAR9 == 1'b0))
begin
if (VAR7[23] ~^ VAR7[24])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd24) & (VAR9 == 1'b0))
begin
if (VAR7[24] ~^ VAR7[25])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd25) & (VAR9 == 1'b0))
begin
if (VAR7[25] ~^ VAR7[26])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd26) & (VAR9 == 1'b0))
begin
if (VAR7[26] ~^ VAR7[27])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd27) & (VAR9 == 1'b0))
begin
if (VAR7[27] ~^ VAR7[28])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd28) & (VAR9 == 1'b0))
begin
if (VAR7[28] ~^ VAR7[29])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd29) & (VAR9 == 1'b0))
begin
if (VAR7[29] ~^ VAR7[30])
begin
if((VAR13 == 1'b1) && (VAR4) )
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else if ((VAR8[4:0] == 5'd30) & (VAR9 == 1'b0))
begin
if (VAR7[30] ~^ VAR7[31])
begin
if((VAR13 == 1'b1) && (VAR4))
begin
VAR9 <= 1'b1;
end
else
begin
VAR13 <= 1'b1;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
else
begin
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
always @(posedge clk)
begin
if(reset)
VAR2 <= VAR6;
end
else if(VAR8[4] && VAR8[3] && VAR8[2] && VAR8[1] && VAR8[0])
begin
if((VAR13 == 1'b0) || (VAR9 == 1'b0) || (VAR12 > 5'b01011))
VAR2 <= VAR11;
end
else if((VAR12 < 5'b01000))
VAR2 <= VAR3;
else if((VAR12 < 5'b01010))
VAR2 <= VAR1;
else
VAR2 <= VAR1;
end
else
VAR2 <= VAR2;
end
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp.pp.symbol.v | 1,358 | module MODULE1 (
input VAR8 ,
output VAR6 ,
output VAR1 ,
input VAR3,
input VAR4 ,
input VAR7,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/system1_nios2_gen2_0_cpu_debug_slave_tck.v | 8,473 | module MODULE1 (
VAR5,
VAR21,
VAR15,
VAR10,
VAR31,
VAR28,
VAR1,
VAR26,
VAR9,
VAR38,
VAR23,
VAR32,
VAR27,
VAR11,
VAR35,
VAR22,
VAR33,
VAR24,
VAR17,
VAR20,
VAR34,
VAR25,
VAR13,
VAR3,
VAR7,
VAR40,
VAR14,
VAR29,
VAR36,
VAR37,
VAR30
)
;
output [ 1: 0] VAR14;
output VAR29;
output [ 37: 0] VAR36;
output VAR37;
output VAR30;
input [ 31: 0] VAR5;
input [ 31: 0] VAR21;
input VAR15;
input VAR10;
input VAR31;
input VAR28;
input VAR1;
input [ 1: 0] VAR26;
input VAR9;
input VAR38;
input VAR23;
input VAR32;
input VAR27;
input VAR11;
input VAR35;
input VAR22;
input [ 35: 0] VAR33;
input VAR24;
input [ 6: 0] VAR17;
input VAR20;
input VAR34;
input VAR25;
input VAR13;
input VAR3;
input VAR7;
input VAR40;
reg [ 2: 0] VAR39 ;
wire VAR19;
reg [ 1: 0] VAR14;
wire VAR29;
wire VAR4;
reg [ 37: 0] VAR36 ;
wire VAR37;
wire VAR30;
wire VAR18;
wire VAR2;
always @(posedge VAR11)
begin
if (VAR3)
case (VAR26)
2'b00: begin
VAR36[35] <= VAR19;
VAR36[34] <= VAR38;
VAR36[33] <= VAR27;
VAR36[32 : 1] <= VAR5;
VAR36[0] <= VAR4;
end
2'b01: begin
VAR36[35 : 0] <= VAR33;
VAR36[37] <= VAR24;
VAR36[36] <= VAR22;
end
2'b10: begin
VAR36[37] <= VAR13;
VAR36[36] <= VAR28;
VAR36[35] <= VAR31;
VAR36[34] <= VAR10;
VAR36[33] <= VAR15;
VAR36[32 : 1] <= VAR21;
VAR36[0] <= VAR25;
end
2'b11: begin
VAR36[15 : 2] <= VAR17;
VAR36[1] <= VAR34;
VAR36[0] <= VAR20;
end
endcase if (VAR7)
case (VAR39)
3'b000: begin
VAR36 <= {VAR35, VAR36[37 : 2], VAR35};
end
3'b001: begin
VAR36 <= {VAR35, VAR36[37 : 9], VAR35, VAR36[7 : 1]};
end
3'b010: begin
VAR36 <= {VAR35, VAR36[37 : 17], VAR35, VAR36[15 : 1]};
end
3'b011: begin
VAR36 <= {VAR35, VAR36[37 : 33], VAR35, VAR36[31 : 1]};
end
3'b100: begin
VAR36 <= {VAR35, VAR36[37], VAR35, VAR36[35 : 1]};
end
3'b101: begin
VAR36 <= {VAR35, VAR36[37 : 1]};
end
default: begin
VAR36 <= {VAR35, VAR36[37 : 2], VAR35};
end
endcase if (VAR40)
case (VAR26)
2'b00: begin
VAR39 <= 3'b100;
end
2'b01: begin
VAR39 <= 3'b101;
end
2'b10: begin
VAR39 <= 3'b101;
end
2'b11: begin
VAR39 <= 3'b010;
end
endcase end
assign VAR30 = VAR36[0];
assign VAR37 = VAR9;
assign VAR18 = VAR29;
VAR8 VAR6
(
.clk (VAR11),
.din (VAR1),
.dout (VAR19),
.VAR32 (VAR18)
);
assign VAR2 = VAR29;
VAR8 VAR16
(
.clk (VAR11),
.din (VAR23),
.dout (VAR4),
.VAR32 (VAR2)
);
always @(posedge VAR11 or negedge VAR29)
begin
if (VAR29 == 0)
VAR14 <= 2'b0;
end
else
VAR14 <= {VAR19, VAR4};
end
assign VAR29 = VAR32;
endmodule | mit |
chriz2600/DreamcastHDMI | Core/source/pll_hdmi/pll_hdmi_reconfig.v | 1,561 | module MODULE1 (
input VAR13,
input [7:0] address,
input VAR5,
input [7:0] VAR2,
input VAR12,
output VAR7,
output VAR4,
output reg VAR10
);
reg VAR5 = 0;
reg VAR6;
reg VAR11;
reg VAR9;
reg VAR3;
reg VAR8;
reg [7:0] VAR1 = 0;
assign VAR7 = VAR11;
assign VAR4 = VAR8;
always @(posedge VAR13) begin
VAR5 <= VAR5;
if (VAR5 && ~VAR5) begin
VAR9 <= 1;
end else begin
VAR9 <= 0;
end
if (~VAR12 && VAR1 != VAR2) begin
VAR1 <= VAR2;
VAR10 <= 1'b1;
end else begin
VAR10 <= 1'b0;
end
case (VAR1[6:0])
endcase
VAR11 <= VAR6;
VAR3 <= VAR9;
VAR8 <= VAR3;
end
endmodule | mit |
ultraembedded/riscv | top_cache_axi/src_v/icache.v | 17,087 | module MODULE1
parameter VAR95 = 0
)
(
input VAR7
,input VAR45
,input VAR31
,input VAR57
,input VAR92
,input [ 31:0] VAR75
,input VAR27
,input VAR61
,input VAR60
,input [ 1:0] VAR5
,input [ 3:0] VAR13
,input VAR29
,input VAR2
,input [ 31:0] VAR71
,input [ 1:0] VAR3
,input [ 3:0] VAR17
,input VAR98
,output VAR103
,output VAR21
,output VAR62
,output [ 31:0] VAR91
,output VAR89
,output [ 31:0] VAR59
,output [ 3:0] VAR49
,output [ 7:0] VAR33
,output [ 1:0] VAR24
,output VAR36
,output [ 31:0] VAR8
,output [ 3:0] VAR55
,output VAR102
,output VAR104
,output VAR35
,output [ 31:0] VAR48
,output [ 3:0] VAR69
,output [ 7:0] VAR97
,output [ 1:0] VAR11
,output VAR76
);
localparam VAR65 = 2;
localparam VAR80 = 256;
localparam VAR19 = 8;
localparam VAR100 = 5;
localparam VAR50 = 32;
localparam VAR73 = 8;
localparam VAR39 = 5; localparam VAR81 = 12; localparam VAR70 = 8; VAR10 VAR18 VAR81:VAR39
localparam VAR47 = 19;
localparam VAR87 = VAR47;
localparam VAR96 = VAR87 + 1;
localparam VAR37 = VAR81 + 1;
localparam VAR56 = 32-1;
localparam VAR52 = VAR56 - VAR37 + 1;
wire [VAR70-1:0] VAR4 = VAR75[VAR18];
localparam VAR6 = VAR19+VAR100-2;
wire [VAR6-1:0] VAR66 = VAR75[VAR6+2-1:2];
localparam VAR105 = 2;
localparam VAR22 = 2'd0;
localparam VAR1 = 2'd1;
localparam VAR30 = 2'd2;
localparam VAR53 = 2'd3;
reg [VAR105-1:0] VAR14;
reg [VAR105-1:0] VAR83;
reg VAR40;
reg [0:0] VAR28;
reg VAR74;
always @ (posedge VAR7 or posedge VAR45)
if (VAR45)
VAR74 <= 1'b0;
else if (VAR31 && VAR103)
VAR74 <= 1'b1;
else if (VAR21)
VAR74 <= 1'b0;
reg [31:0] VAR99;
always @ (posedge VAR7 or posedge VAR45)
if (VAR45)
VAR99 <= 32'b0;
else if (VAR31 && VAR103)
VAR99 <= VAR75;
wire [VAR52-1:0] VAR25 = VAR99[VAR72];
reg [VAR70-1:0] VAR58;
always @ *
begin
VAR58 = VAR16;
if (VAR83 == VAR22)
VAR58 = VAR16;
end
else if (VAR83 == VAR30 || VAR83 == VAR53)
VAR58 = VAR99[VAR18];
else
VAR58 = VAR4;
end
reg [VAR96-1:0] VAR67;
always @ *
begin
VAR67 = {(VAR96){1'b0}};
if (VAR83 == VAR22)
VAR67 = {(VAR96){1'b0}};
end
else if (VAR83 == VAR30)
begin
VAR67[VAR87] = 1'b1;
VAR67[VAR15] = VAR99[VAR72];
end
end
reg VAR78;
always @ *
begin
VAR78 = 1'b0;
if (VAR83 == VAR22)
VAR78 = 1'b1;
end
else if (VAR83 == VAR30)
VAR78 = VAR2 && VAR98 && (VAR28 == 0);
end
wire [VAR96-1:0] VAR9;
VAR34
VAR93
(
.VAR7(VAR7),
.VAR45(VAR45),
.VAR41(VAR58),
.VAR51(VAR67),
.VAR84(VAR78),
.VAR101(VAR9)
);
wire VAR32 = VAR9[VAR87];
wire [VAR47-1:0] VAR88 = VAR9[VAR15];
wire VAR54 = VAR32 ? (VAR88 == VAR25) : 1'b0;
reg VAR26;
always @ *
begin
VAR26 = 1'b0;
if (VAR83 == VAR22)
VAR26 = 1'b1;
end
else if (VAR83 == VAR30)
VAR26 = VAR2 && VAR98 && (VAR28 == 1);
end
wire [VAR96-1:0] VAR79;
VAR34
VAR63
(
.VAR7(VAR7),
.VAR45(VAR45),
.VAR41(VAR58),
.VAR51(VAR67),
.VAR84(VAR26),
.VAR101(VAR79)
);
wire VAR86 = VAR79[VAR87];
wire [VAR47-1:0] VAR77 = VAR79[VAR15];
wire VAR46 = VAR86 ? (VAR77 == VAR25) : 1'b0;
wire VAR44 = 1'b0
| VAR54
| VAR46
;
reg [VAR6-1:0] VAR82;
reg [VAR6-1:0] VAR43;
always @ (posedge VAR7 or posedge VAR45)
if (VAR45)
VAR43 <= {(VAR6){1'b0}};
else if (VAR83 == VAR1 && VAR14 == VAR30)
VAR43 <= VAR48[VAR6+2-1:2];
else if (VAR83 == VAR30 && VAR2)
VAR43 <= VAR43 + 1;
always @ *
begin
VAR82 = VAR66;
if (VAR83 == VAR30)
VAR82 = VAR43;
end
else if (VAR83 == VAR53)
VAR82 = VAR99[VAR6+2-1:2];
else
VAR82 = VAR66;
end
reg VAR38;
always @ *
begin
VAR38 = VAR2 && VAR28 == 0;
end
wire [31:0] VAR94;
VAR23
VAR85
(
.VAR7(VAR7),
.VAR45(VAR45),
.VAR41(VAR82),
.VAR51(VAR71),
.VAR84(VAR38),
.VAR101(VAR94)
);
reg VAR68;
always @ *
begin
VAR68 = VAR2 && VAR28 == 1;
end
wire [31:0] VAR64;
VAR23
VAR90
(
.VAR7(VAR7),
.VAR45(VAR45),
.VAR41(VAR82),
.VAR51(VAR71),
.VAR84(VAR68),
.VAR101(VAR64)
);
reg [VAR70-1:0] VAR16;
always @ (posedge VAR7 or posedge VAR45)
if (VAR45)
VAR16 <= {(VAR70){1'b0}};
else if (VAR83 == VAR22)
VAR16 <= VAR16 + 1;
else if (VAR92 && VAR103)
VAR16 <= VAR4;
else
VAR16 <= {(VAR70){1'b0}};
always @ (posedge VAR7 or posedge VAR45)
if (VAR45)
VAR28 <= 0;
else if (VAR2 && VAR98)
VAR28 <= VAR28 + 1;
assign VAR21 = VAR74 && ((VAR83 == VAR1) ? VAR44 : 1'b0);
reg [31:0] VAR20;
always @ *
begin
VAR20 = VAR94;
case (1'b1)
VAR54: VAR20 = VAR94;
VAR46: VAR20 = VAR64;
endcase
end
assign VAR91 = VAR20;
always @ *
begin
VAR14 = VAR83;
case (VAR83)
VAR22 :
begin
if (VAR40)
VAR14 = VAR1;
end
else if (VAR16 == {(VAR70){1'b1}})
VAR14 = VAR1;
end
VAR1 :
begin
if (VAR74 && !VAR44)
VAR14 = VAR30;
end
else if (VAR92 || VAR57)
VAR14 = VAR22;
end
VAR30 :
begin
if (VAR2 && VAR98)
VAR14 = VAR53;
end
VAR53 :
begin
VAR14 = VAR1;
end
default:
;
endcase
end
always @ (posedge VAR7 or posedge VAR45)
if (VAR45)
VAR83 <= VAR22;
else
VAR83 <= VAR14;
assign VAR103 = (VAR83 == VAR1 && VAR14 != VAR30);
always @ (posedge VAR7 or posedge VAR45)
if (VAR45)
VAR40 <= 1'b0;
else if (VAR92 && VAR103)
VAR40 <= 1'b1;
else
VAR40 <= 1'b0;
reg VAR12;
always @ (posedge VAR7 or posedge VAR45)
if (VAR45)
VAR12 <= 1'b0;
else if (VAR35 && !VAR29)
VAR12 <= 1'b1;
else
VAR12 <= 1'b0;
reg VAR42;
always @ (posedge VAR7 or posedge VAR45)
if (VAR45)
VAR42 <= 1'b0;
else if (VAR2 && VAR76 && VAR3 != 2'b0)
VAR42 <= 1'b1;
else if (VAR21)
VAR42 <= 1'b0;
assign VAR62 = VAR42;
assign VAR89 = 1'b0;
assign VAR59 = 32'b0;
assign VAR49 = 4'b0;
assign VAR33 = 8'b0;
assign VAR24 = 2'b0;
assign VAR36 = 1'b0;
assign VAR8 = 32'b0;
assign VAR55 = 4'b0;
assign VAR102 = 1'b0;
assign VAR104 = 1'b0;
assign VAR35 = (VAR83 == VAR1 && VAR14 == VAR30) || VAR12;
assign VAR48 = {VAR99[31:VAR100], {(VAR100){1'b0}}};
assign VAR11 = 2'd1; assign VAR69 = VAR95;
assign VAR97 = 8'd7;
assign VAR76 = 1'b1;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor3/sky130_fd_sc_hdll__xnor3_2.v | 2,200 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR1 ,
VAR2 ,
VAR6,
VAR9,
VAR7 ,
VAR5
);
output VAR10 ;
input VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR6;
input VAR9;
input VAR7 ;
input VAR5 ;
VAR3 VAR8 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR10,
VAR4,
VAR1,
VAR2
);
output VAR10;
input VAR4;
input VAR1;
input VAR2;
supply1 VAR6;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR5 ;
VAR3 VAR8 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.behavioral.v | 1,802 | module MODULE1( VAR1, VAR3, VAR5, VAR2, VAR7 );
input VAR5, VAR1, VAR2, VAR7;
output VAR3;
VAR6 VAR8(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7));
VAR6 VAR4(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/video_sys_Onchip_Memory.v | 3,923 | module MODULE1 (
address,
VAR3,
VAR18,
clk,
VAR30,
reset,
write,
VAR27,
VAR6
)
;
parameter VAR19 = "../MODULE1.VAR8";
output [ 31: 0] VAR6;
input [ 11: 0] address;
input [ 3: 0] VAR3;
input VAR18;
input clk;
input VAR30;
input reset;
input write;
input [ 31: 0] VAR27;
wire [ 31: 0] VAR6;
wire VAR22;
assign VAR22 = VAR18 & write;
VAR29 VAR11
(
.VAR23 (address),
.VAR2 (VAR3),
.VAR5 (clk),
.VAR12 (VAR30),
.VAR32 (VAR27),
.VAR24 (VAR6),
.VAR9 (VAR22)
);
VAR11.VAR7 = VAR19,
VAR11.VAR25 = "VAR29",
VAR11.VAR13 = 4096,
VAR11.VAR14 = 4096,
VAR11.VAR31 = "VAR21",
VAR11.VAR28 = "VAR15",
VAR11.VAR26 = "VAR10",
VAR11.VAR33 = "VAR20",
VAR11.VAR17 = 32,
VAR11.VAR4 = 4,
VAR11.VAR16 = 12;
endmodule | gpl-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/MAC_REG_ACC.v | 1,792 | module MODULE1(
input clk,
input reset,
input VAR2,
input [31:0] VAR7,
output reg [7:0] address,
output reg write,
output reg read,
output reg [31:0] VAR9);
reg [2:0] VAR1;
reg [3:0] VAR3;
reg [1:0] VAR8;
parameter VAR4 = 2'b00,
VAR5 = 2'b01,
VAR6 = 2'b10,
VAR10 = 2'b11;
always@(posedge clk or negedge reset)
if(!reset) begin
address <= 8'b0;
write <= 1'b0;
read <= 1'b0;
VAR9 <= 32'b0;
VAR1 <= 3'b0;
VAR3 <= 4'b0;
VAR8 <= VAR5;
end
else begin
case(VAR8)
VAR5:begin
VAR1 <= 3'b0;
VAR3 <=VAR3 +1'b1;
if(VAR3[3] == 1'b1)
VAR8 <= VAR4;
end
else
VAR8 <= VAR5;
end
VAR4: begin
address <= 8'b0;
write <= 1'b0;
read <= 1'b0;
VAR9 <= 32'b0;
VAR3 <= 4'b0;
if(VAR1 < 3'd4)begin
VAR1 <= VAR1 + 3'b1;
VAR8 <= VAR6;
end
else begin
VAR8 <= VAR4;
end
end
VAR6: begin
VAR8 <= VAR10;
case(VAR1)
3'd1: begin
address <= 8'h2;
write <= 1'b1;
VAR9 <= 32'h1000093;
end
3'd2: begin
address <= 8'he;
write <= 1'b1;
VAR9 <= 32'h4;
end
3'd3: begin
address <= 8'h94;
write <= 1'b1;
VAR9 <= 32'h7;
end
default: begin
address <= 8'h2;
VAR9 <= 32'h1000093;
end
endcase
end
VAR10: begin
write <= 1'b1;
if(VAR2 == 1'b0)begin
VAR8 <= VAR4;
write <= 1'b1;
end
else begin
VAR8 <= VAR10;
end
end
endcase
end
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_pipe_drp.v | 22,851 | module MODULE1 #
(
parameter VAR117 = "1.1", parameter VAR57 = "VAR90", parameter VAR87 = "VAR66", parameter VAR46 = "VAR115", parameter VAR28 = 0, parameter VAR78 = 0, parameter VAR59 = 4'd11
)
(
input VAR68,
input VAR12,
input VAR26,
input [ 1:0] VAR70,
input VAR71,
input [15:0] VAR109,
input VAR10,
output [ 8:0] VAR20,
output VAR103,
output [15:0] VAR18,
output VAR3,
output VAR96,
output [ 6:0] VAR41
);
reg VAR88;
reg [ 1:0] VAR24;
reg VAR73;
reg [15:0] VAR9;
reg VAR47;
reg VAR80;
reg [ 1:0] VAR113;
reg VAR65;
reg [15:0] VAR102;
reg VAR35;
reg [ 3:0] VAR33 = 4'd0;
reg VAR4 = 1'd0;
reg [ 8:0] VAR56 = 9'd0;
reg [15:0] VAR58 = 16'd0;
reg VAR98 = 1'd0;
reg [ 6:0] fsm = 7'd1;
localparam VAR120 = 9'h06F;
localparam VAR67 = 9'h088;
localparam VAR43 = 9'h088;
localparam VAR95 = 9'h06B;
localparam VAR34 = 9'h06B;
localparam VAR86 = 9'h011;
localparam VAR119 = 9'h011;
localparam VAR38 = 9'h01C;
localparam VAR37 = 9'h09D;
localparam VAR93 = 9'h059;
localparam VAR51 = 9'h059;
localparam VAR27 = 9'h044;
localparam VAR52 = 9'h019;
localparam VAR106 = 9'h0A7;
localparam VAR83 = 16'b1111111111111001; localparam VAR11 = 16'b1111111110001111; localparam VAR19 = 16'b1111111111111000; localparam VAR25 = 16'b1111111111111000; localparam VAR29 = 16'b1111111111101111; localparam VAR85 = 16'b1100011111111111; localparam VAR13 = 16'b1011111111111111; localparam VAR7 = 16'b1011111111111111; localparam VAR76 = 16'b1111111111111101; localparam VAR101 = 16'b1111111101111111; localparam VAR110 = 16'b1111111110111111; localparam VAR5 = 16'b1011111111111111; localparam VAR89 = 16'b1111111111100000; localparam VAR62 = 16'b1100011111111111;
localparam VAR72 = (VAR57 == "VAR107") ? 16'b0000000000100000 : 16'b0000000000010000; localparam VAR108 = (VAR57 == "VAR107") ? 16'b0000000000000010 : 16'b0000000000000001; localparam VAR30 = 16'b0000000000000011; localparam VAR77 = 16'b0000000000000000; localparam VAR50 = 16'b0001100000000000; localparam VAR100 = 16'b0000000000000000; localparam VAR17 = 16'b0100000000000000; localparam VAR82 = 16'b0000000000000010; localparam VAR44 = 16'b0000000000000000; localparam VAR14 = 16'b0000000000000000; localparam VAR32 = 16'b0100000000000000; localparam VAR94 = 16'b0000000000000001; localparam VAR40 = 16'b0011000000000000;
localparam VAR118 = 16'b0000000000000000; localparam VAR105 = 16'b0000000000000000; localparam VAR81 = 16'b0000000000000100; localparam VAR112 = 16'b0000000000010000; localparam VAR55 = 16'b0010000000000000; localparam VAR116 = 16'b0100000000000000; localparam VAR1 = 16'b0000000000000000; localparam VAR111 = 16'b0000000000000000; localparam VAR31 = 16'b0000000010000000; localparam VAR49 = 16'b0000000001000000; localparam VAR75 = 16'b0000000000000000; localparam VAR2 = 16'b0000000000000010; localparam VAR60 = 16'b0000100000000000;
localparam VAR99 = 16'b0000000000000000; localparam VAR53 = 16'b0000000000000010; localparam VAR22 = 16'b0000000000000100;
wire [15:0] VAR104;
wire [15:0] VAR63;
wire [15:0] VAR23;
wire [15:0] VAR74;
wire [15:0] VAR21;
wire [15:0] VAR42;
wire [15:0] VAR114;
wire [15:0] VAR64;
wire [15:0] VAR84;
wire [15:0] VAR45;
wire [15:0] VAR16;
wire [15:0] VAR39;
wire [15:0] VAR54;
wire [15:0] VAR15;
wire [15:0] VAR36;
wire [15:0] VAR61;
wire [15:0] VAR92;
localparam VAR6 = 7'b0000001;
localparam VAR79 = 7'b0000010;
localparam VAR8 = 7'b0000100;
localparam VAR97 = 7'b0001000;
localparam VAR48 = 7'b0010000;
localparam VAR69 = 7'b0100000;
localparam VAR91 = 7'b1000000;
always @ (posedge VAR68)
begin
if (!VAR12)
begin
VAR88 <= 1'd0;
VAR24 <= 2'd0;
VAR9 <= 16'd0;
VAR47 <= 1'd0;
VAR73 <= 1'd0;
VAR80 <= 1'd0;
VAR113 <= 2'd0;
VAR102 <= 16'd0;
VAR35 <= 1'd0;
VAR65 <= 1'd0;
end
else
begin
VAR88 <= VAR26;
VAR24 <= VAR70;
VAR9 <= VAR109;
VAR47 <= VAR10;
VAR73 <= VAR71;
VAR80 <= VAR88;
VAR113 <= VAR24;
VAR102 <= VAR9;
VAR35 <= VAR47;
VAR65 <= VAR73;
end
end
assign VAR104 = (VAR113 == 2'd2) ? VAR118 : VAR72;
assign VAR63 = (VAR113 == 2'd2) ? VAR105 : VAR108;
assign VAR23 = (VAR113 == 2'd2) ? VAR81 : VAR30;
assign VAR74 = (VAR113 == 2'd2) ? VAR112 : VAR77;
assign VAR21 = (VAR113 == 2'd2) ? VAR55 : VAR50;
assign VAR42 = (VAR113 == 2'd2) ? VAR116 : VAR100;
assign VAR114 = ((VAR113 == 2'd2) || (VAR87 == "VAR66")) ? VAR1 : VAR17;
assign VAR64 = ((VAR113 == 2'd2) && (VAR46 == "VAR66")) ? VAR111 : VAR82;
assign VAR84 = ((VAR113 == 2'd2) || (VAR87 == "VAR66")) ? VAR31 : VAR44;
assign VAR45 = ((VAR113 == 2'd2) && (VAR46 == "VAR66")) ? VAR49 : VAR14;
assign VAR16 = (VAR113 == 2'd2) ? VAR75 : VAR32;
assign VAR39 = (VAR113 == 2'd2) ? VAR2 : VAR94;
assign VAR54 = (VAR113 == 2'd2) ? VAR60 : VAR40;
assign VAR15 = VAR99;
assign VAR36 = VAR28 ? VAR99 : VAR53;
assign VAR61 = VAR78 ? VAR99 : VAR22;
assign VAR92 = VAR36 | VAR61;
always @ (posedge VAR68)
begin
if (!VAR12)
begin
VAR56 <= 9'd0;
VAR58 <= 16'd0;
end
else
begin
case (VAR33)
4'd0:
begin
VAR56 <= VAR4 ? VAR120 : VAR67;
VAR58 <= VAR4 ? ((VAR102 & VAR83) | VAR15)
: ((VAR102 & VAR11) | VAR104);
end
4'd1:
begin
VAR56 <= VAR4 ? VAR120 : VAR43;
VAR58 <= VAR4 ? ((VAR102 & VAR83) | VAR92)
: ((VAR102 & VAR19) | VAR63);
end
4'd2 :
begin
VAR56 <= VAR95;
VAR58 <= (VAR102 & VAR25) | VAR23;
end
4'd3 :
begin
VAR56 <= VAR34;
VAR58 <= (VAR102 & VAR29) | VAR74;
end
4'd4 :
begin
VAR56 <= VAR86;
VAR58 <= (VAR102 & VAR85) | VAR21;
end
4'd5 :
begin
VAR56 <= VAR119;
VAR58 <= (VAR102 & VAR13) | VAR42;
end
4'd6 :
begin
VAR56 <= VAR38;
VAR58 <= (VAR102 & VAR7) | VAR114;
end
4'd7 :
begin
VAR56 <= VAR37;
VAR58 <= (VAR102 & VAR76) | VAR64;
end
4'd8 :
begin
VAR56 <= VAR93;
VAR58 <= (VAR102 & VAR101) | VAR84;
end
4'd9 :
begin
VAR56 <= VAR51;
VAR58 <= (VAR102 & VAR110) | VAR45;
end
4'd10 :
begin
VAR56 <= VAR27;
VAR58 <= (VAR102 & VAR5) | VAR16;
end
4'd11 :
begin
VAR56 <= VAR52;
VAR58 <= (VAR102 & VAR89) | VAR39;
end
4'd12 :
begin
VAR56 <= VAR106;
VAR58 <= (VAR102 & VAR62) | VAR54;
end
default :
begin
VAR56 <= 9'd0;
VAR58 <= 16'd0;
end
endcase
end
end
always @ (posedge VAR68)
begin
if (!VAR12)
begin
fsm <= VAR6;
VAR33 <= 4'd0;
VAR4 <= 1'd0;
VAR98 <= 1'd0;
end
else
begin
case (fsm)
VAR6 :
begin
if (VAR65)
begin
fsm <= VAR79;
VAR33 <= 4'd0;
VAR4 <= 1'd0;
VAR98 <= 1'd0;
end
else if ((VAR80 && !VAR88) && ((VAR28 == 0) || (VAR78 == 0)) && (VAR117 == "1.0"))
begin
fsm <= VAR79;
VAR33 <= 4'd0;
VAR4 <= 1'd1;
VAR98 <= 1'd0;
end
else
begin
fsm <= VAR6;
VAR33 <= 4'd0;
VAR4 <= 1'd0;
VAR98 <= 1'd1;
end
end
VAR79 :
begin
fsm <= VAR8;
VAR33 <= VAR33;
VAR4 <= VAR4;
VAR98 <= 1'd0;
end
VAR8 :
begin
fsm <= VAR97;
VAR33 <= VAR33;
VAR4 <= VAR4;
VAR98 <= 1'd0;
end
VAR97 :
begin
fsm <= VAR35 ? VAR48 : VAR97;
VAR33 <= VAR33;
VAR4 <= VAR4;
VAR98 <= 1'd0;
end
VAR48 :
begin
fsm <= VAR69;
VAR33 <= VAR33;
VAR4 <= VAR4;
VAR98 <= 1'd0;
end
VAR69 :
begin
fsm <= VAR35 ? VAR91 : VAR69;
VAR33 <= VAR33;
VAR4 <= VAR4;
VAR98 <= 1'd0;
end
VAR91 :
begin
if ((VAR33 == VAR59) || (VAR4 && (VAR33 == 4'd1)))
begin
fsm <= VAR6;
VAR33 <= 4'd0;
VAR4 <= 1'd0;
VAR98 <= 1'd0;
end
else
begin
fsm <= VAR79;
VAR33 <= VAR33 + 4'd1;
VAR4 <= VAR4;
VAR98 <= 1'd0;
end
end
default :
begin
fsm <= VAR6;
VAR33 <= 4'd0;
VAR4 <= 1'd0;
VAR98 <= 1'd0;
end
endcase
end
end
assign VAR20 = VAR56;
assign VAR103 = (fsm == VAR8) || (fsm == VAR48);
assign VAR18 = VAR58;
assign VAR3 = (fsm == VAR48) || (fsm == VAR69);
assign VAR96 = VAR98;
assign VAR41 = fsm;
endmodule | lgpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_csr.v | 51,663 | module MODULE1 #
( parameter
VAR186 = 2,
VAR62 = 1,
VAR61 = 1,
VAR104 = 0,
VAR33 = 0,
VAR137 = 8,
VAR75 = 32,
VAR47 = 1,
VAR51 = 72,
VAR5 = 1, VAR108 = 13, VAR85 = 10, VAR57 = 3,
VAR23 = 1,
VAR133 = 1,
VAR118 = 0,
VAR126 = 4, VAR159 = 3, VAR2 = 4, VAR120 = 5, VAR64 = 4, VAR24 = 6, VAR174 = 8, VAR125 = 13, VAR3 = 4, VAR123 = 4, VAR119 = 4, VAR103 = 4, VAR69 = 4, VAR176 = 5, VAR21 = 6, VAR115 = 16, VAR164 = 8,
VAR54 = 0, VAR157 = 0, VAR29 = 0, VAR37 = 0, VAR70 = 0, VAR149 = 0, VAR100 = 0, VAR25 = 0, VAR132 = 0, VAR184 = 0, VAR146 = 0, VAR169 = 0, VAR194 = 0, VAR44 = 0, VAR87 = 0, VAR58 = 0,
VAR142 = 1, VAR131 = 0,
VAR8 = 0,
VAR46 = 5,
VAR163 = 5,
VAR193 = 3,
VAR177 = 3
)
(
VAR50,
VAR68,
VAR7,
VAR79,
VAR145,
VAR81,
VAR11,
VAR52,
VAR144,
VAR180,
VAR15,
VAR152,
VAR122,
VAR63,
VAR136,
VAR83,
VAR67,
VAR130,
VAR92,
VAR45,
VAR66,
VAR128,
VAR1,
VAR84,
VAR65,
VAR148,
VAR99,
VAR117,
VAR189,
VAR94,
VAR19,
VAR111,
VAR165,
VAR170,
VAR35,
VAR22,
VAR38,
VAR59,
VAR158,
VAR141,
VAR171,
VAR155,
VAR156,
VAR78,
VAR30,
VAR77,
VAR74,
VAR191,
VAR86,
VAR13,
VAR17,
VAR124,
VAR73,
VAR88,
VAR26,
VAR72,
VAR150,
VAR112
);
localparam integer VAR43 = (2**VAR5);
input VAR50;
input VAR68;
input VAR145;
input VAR11;
input [VAR137 - 1 : 0] VAR7;
input [VAR75 - 1 : 0] VAR81;
input [(VAR75 / 8) - 1 : 0] VAR79;
output VAR180;
output VAR144;
output [VAR75 - 1 : 0] VAR52;
input VAR15;
input VAR152;
input VAR122;
input VAR63;
input VAR136;
input VAR83;
input VAR67;
input [7 : 0] VAR130;
input [7 : 0] VAR92;
input [7 : 0] VAR45;
input [31 : 0] VAR66;
input [31 : 0] VAR128;
output VAR1;
output [VAR47 - 1 : 0] VAR84;
output [VAR51 * VAR43 - 1 : 0] VAR65;
output [VAR126 - 1 : 0] VAR148;
output [VAR159 - 1 : 0] VAR99;
output [VAR2 - 1 : 0] VAR117;
output [VAR120 - 1 : 0] VAR189;
output [VAR64 - 1 : 0] VAR94;
output [VAR24 - 1 : 0] VAR19;
output [VAR174 - 1 : 0] VAR111;
output [VAR125 - 1 : 0] VAR165;
output [VAR3 - 1 : 0] VAR170;
output [VAR123 - 1 : 0] VAR35;
output [VAR119 - 1 : 0] VAR22;
output [VAR103 - 1 : 0] VAR38;
output [VAR69 - 1 : 0] VAR59;
output [VAR176 - 1 : 0] VAR158;
output [VAR21 - 1 : 0] VAR141;
output [VAR115 - 1 : 0] VAR171;
output [1 : 0] VAR155;
output VAR150;
output [VAR164-1: 0] VAR112;
output [VAR46 - 1 : 0] VAR156;
output [VAR163 - 1 : 0] VAR78;
output [VAR193 - 1 : 0] VAR30;
output [VAR177 - 1 : 0] VAR77;
output VAR74;
output VAR191;
output VAR86;
output VAR13;
output VAR17;
output VAR124;
output VAR73;
output VAR88;
output VAR26;
output VAR72;
wire VAR180;
wire VAR144;
wire [VAR75 - 1 : 0] VAR52;
reg VAR56;
reg VAR36;
reg VAR185;
reg [8 - 1 : 0] VAR91; reg [VAR75 - 1 : 0] VAR109;
reg [VAR75 - 1 : 0] VAR161;
reg [(VAR75 / 8) - 1 : 0] VAR102;
reg VAR162;
reg VAR42;
reg VAR76;
reg VAR188;
wire VAR1;
wire [VAR47 - 1 : 0] VAR84;
wire [VAR51 * VAR43 - 1 : 0] VAR65;
wire [VAR126 - 1 : 0] VAR148;
wire [VAR159 - 1 : 0] VAR99;
wire [VAR2 - 1 : 0] VAR117;
wire [VAR120 - 1 : 0] VAR189;
wire [VAR64 - 1 : 0] VAR94;
wire [VAR24 - 1 : 0] VAR19;
wire [VAR174 - 1 : 0] VAR111;
wire [VAR125 - 1 : 0] VAR165;
wire [VAR3 - 1 : 0] VAR170;
wire [VAR123 - 1 : 0] VAR35;
wire [VAR119 - 1 : 0] VAR22;
wire [VAR103 - 1 : 0] VAR38;
wire [VAR69 - 1 : 0] VAR59;
wire [VAR176 - 1 : 0] VAR158;
wire [VAR21 - 1 : 0] VAR141;
wire [VAR115 - 1 : 0] VAR171;
wire [1 : 0] VAR155;
wire VAR150;
wire [VAR164-1: 0] VAR112;
wire [VAR46 - 1 : 0] VAR156;
wire [VAR163 - 1 : 0] VAR78;
wire [VAR193 - 1 : 0] VAR30;
wire [VAR177 - 1 : 0] VAR77;
wire VAR74;
wire VAR191;
wire VAR86;
wire VAR13;
wire VAR17;
wire VAR124;
wire VAR73;
wire VAR88;
wire VAR26;
wire VAR72;
reg [VAR75 - 1 : 0] VAR97;
reg [VAR75 - 1 : 0] VAR138;
reg [VAR75 - 1 : 0] VAR192;
reg [VAR75 - 1 : 0] VAR48;
reg [VAR75 - 1 : 0] VAR40;
reg [VAR75 - 1 : 0] VAR129;
reg [VAR75 - 1 : 0] VAR90;
reg [VAR75 - 1 : 0] VAR18;
reg [VAR75 - 1 : 0] VAR71;
reg [VAR75 - 1 : 0] VAR173;
reg [VAR75 - 1 : 0] VAR151;
reg [VAR75 - 1 : 0] VAR107;
reg [VAR75 - 1 : 0] VAR113;
reg [VAR75 - 1 : 0] VAR105;
assign VAR180 = 1'b0;
generate
if (!VAR62 && !VAR61)
begin
assign VAR52 = 0;
assign VAR144 = 0;
end
else
begin
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR56 <= 0;
VAR36 <= 0;
VAR91 <= 0;
VAR109 <= 0;
VAR102 <= 0;
end
else
begin
VAR91 <= VAR7 [7 : 0]; VAR109 <= VAR81;
VAR102 <= VAR79;
if (VAR145)
VAR56 <= 1'b1;
end
else
VAR56 <= 1'b0;
if (VAR11)
VAR36 <= 1'b1;
end
else
VAR36 <= 1'b0;
end
end
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR162 <= 1'b0;
VAR42 <= 1'b0;
VAR76 <= 1'b0;
VAR188 <= 1'b0;
end
else
begin
if (VAR104)
begin
VAR162 <= 1'b1;
VAR42 <= 1'b0;
end
else
begin
VAR162 <= 1'b0;
VAR42 <= 1'b0;
end
if (VAR33)
begin
VAR76 <= 1'b1;
VAR188 <= 1'b0;
end
else
begin
VAR76 <= 1'b0;
VAR188 <= 1'b0;
end
end
end
assign VAR52 = VAR161;
assign VAR144 = VAR185;
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR161 <= 0;
VAR185 <= 0;
end
else
begin
if (VAR36)
begin
if (VAR91 == 8'h00)
VAR161 <= VAR97;
end
else if (VAR91 == 8'h10)
VAR161 <= VAR138;
end
else if (VAR91 == 8'h20)
VAR161 <= VAR192;
end
else if (VAR91 == 8'h21)
VAR161 <= VAR48;
else if (VAR91 == 8'h22)
VAR161 <= VAR40;
else if (VAR91 == 8'h23)
VAR161 <= VAR129;
else if (VAR91 == 8'h24)
VAR161 <= VAR90;
else if (VAR91 == 8'h25)
VAR161 <= VAR18;
else if (VAR91 == 8'h26)
VAR161 <= VAR71;
else if (VAR91 == 8'h30)
VAR161 <= VAR173;
else if (VAR91 == 8'h31)
VAR161 <= VAR151;
else if (VAR91 == 8'h32)
VAR161 <= VAR107;
else if (VAR91 == 8'h33)
VAR161 <= VAR113;
else if (VAR91 == 8'h34)
VAR161 <= VAR105;
end
if (VAR36)
VAR185 <= 1'b1;
else
VAR185 <= 1'b0;
end
end
end
endgenerate
generate
genvar VAR98;
if (!VAR62) begin
assign VAR148 = VAR54;
assign VAR99 = VAR157;
assign VAR117 = VAR29;
assign VAR189 = VAR37;
assign VAR94 = VAR70;
assign VAR19 = VAR149;
assign VAR111 = VAR100;
assign VAR165 = VAR25;
assign VAR170 = VAR132;
assign VAR35 = VAR184;
assign VAR22 = VAR146;
assign VAR38 = VAR169;
assign VAR59 = VAR194;
assign VAR158 = VAR44;
assign VAR141 = VAR87;
assign VAR171 = VAR58;
assign VAR155 = VAR142;
assign VAR150 = VAR131;
assign VAR112 = VAR8;
assign VAR77 = VAR43 > 1 ? VAR5 : 0;
assign VAR30 = VAR57;
assign VAR78 = VAR108;
assign VAR156 = VAR85;
assign VAR1 = 0;
assign VAR84 = 0;
assign VAR65 = 0;
assign VAR72 = 1'b1; end
else
begin
reg VAR172;
reg VAR135;
reg VAR49;
reg [5 : 0] VAR34;
assign VAR1 = VAR49;
assign VAR84 = VAR34 [VAR47 - 1 : 0];
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR49 <= 0;
VAR34 <= 0;
end
else
begin
if (VAR56 && VAR91 == 8'h00)
begin
if (VAR102 [0])
begin
VAR49 <= VAR109 [2] ;
end
if (VAR102 [1])
begin
VAR34 <= VAR109 [13 : 8];
end
end
end
end
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR172 <= 0;
VAR135 <= 0;
end
else
begin
VAR172 <= VAR15;
VAR135 <= VAR152;
end
end
always @
begin
VAR138 = 0;
VAR138 [15 : 0 ] = VAR181;
VAR138 [16] = VAR9;
VAR138 [17] = VAR89;
VAR138 [18] = VAR28;
VAR138 [19] = VAR101;
VAR138 [21 : 20] = VAR190;
VAR138 [22] = VAR187;
VAR138 [24 : 23] = VAR167;
end
reg [7 : 0] VAR31;
reg [7 : 0] VAR27;
reg [3 : 0] VAR39;
reg [3 : 0] VAR183;
assign VAR77 = VAR183 [VAR177 - 1 : 0];
assign VAR30 = VAR39 [VAR193 - 1 : 0];
assign VAR78 = VAR27 [VAR163 - 1 : 0];
assign VAR156 = VAR31 [VAR46 - 1 : 0];
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR31 <= VAR85; VAR27 <= VAR108; VAR39 <= VAR57; VAR183 <= VAR43 > 1 ? VAR5 : 0; end
else
begin
if (!VAR162 && VAR56 && VAR91 == 8'h20)
begin
if (VAR102 [0])
begin
if (VAR109 [7 : 0] <= VAR85)
begin
VAR31 <= VAR109 [7 : 0 ];
end
end
if (VAR102 [1])
begin
if (VAR109 [15 : 8] <= VAR108)
begin
VAR27 <= VAR109 [15 : 8 ];
end
end
if (VAR102 [2])
begin
if (VAR109 [19 : 16] <= VAR57)
begin
VAR39 <= VAR109 [19 : 16];
end
if (VAR109 [23 : 20] <= (VAR43 > 1 ? VAR5 : 0))
begin
VAR183 <= VAR109 [23 : 20];
end
end
end
end
end
always @
begin
VAR48 = 0;
VAR48 [31 : 0 ] = VAR6;
end
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR53 <= {VAR43{1'b1}};
end
else
begin
if (!VAR162 && VAR56 && VAR91 == 8'h22)
begin
if (VAR102 [0])
begin
VAR53 [ 7 : 0] <= VAR109 [7 : 0 ];
end
end
end
end
always @
begin
VAR129 = 0;
VAR129 [3 : 0 ] = VAR134;
VAR129 [7 : 4 ] = VAR55;
VAR129 [11 : 8 ] = VAR166;
VAR129 [15 : 12] = VAR147;
VAR129 [23 : 16] = VAR10;
VAR129 [31 : 24] = VAR80;
end
reg [3 : 0] VAR20;
reg [3 : 0] VAR140;
reg [5 : 0] VAR16;
assign VAR38 = VAR20 [VAR103 - 1 : 0];
assign VAR59 = VAR140 [VAR69 - 1 : 0];
assign VAR19 = VAR16 [VAR24 - 1 : 0];
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR20 <= VAR169;
VAR140 <= VAR194;
VAR16 <= VAR149;
end
else
begin
if (!VAR162 && VAR56 && VAR91 == 8'h24)
begin
if (VAR102 [0])
begin
VAR20 <= VAR109 [3 : 0 ];
VAR140 <= VAR109 [7 : 4 ];
end
if (VAR102 [1])
begin
VAR16 <= VAR109 [13 : 8 ];
end
end
end
end
always @
begin
VAR18 = 0;
VAR18 [15 : 0 ] = VAR154;
VAR18 [23 : 16] = VAR41;
end
reg [3 : 0] VAR110;
reg [3 : 0] VAR160;
reg [3 : 0] VAR32;
reg [3 : 0] VAR139;
reg [7 : 0] VAR179;
assign VAR117 = VAR110 [VAR2 - 1 : 0];
assign VAR99 = VAR160 [VAR159 - 1 : 0];
assign VAR148 = VAR32 [VAR126 - 1 : 0];
assign VAR22 = VAR139 [VAR119 - 1 : 0];
assign VAR189 = VAR179 [VAR120 - 1 : 0];
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR110 <= VAR29;
VAR160 <= VAR157;
VAR32 <= VAR54;
VAR139 <= VAR146;
VAR179 <= VAR37;
end
else
begin
if (!VAR162 && VAR56 && VAR91 == 8'h26)
begin
if (VAR102 [0])
begin
VAR110 <= VAR109 [3 : 0 ];
VAR160 <= VAR109 [7 : 4 ];
end
if (VAR102 [1])
begin
VAR32 <= VAR109 [11 : 8 ];
VAR139 <= VAR109 [15 : 12];
end
if (VAR102 [2])
begin
VAR179 <= VAR109 [23 : 16];
end
end
end
end
always @
begin
VAR173 = 0;
VAR173 [0] = VAR106;
VAR173 [1] = VAR4;
VAR173 [2] = VAR93;
VAR173 [3] = VAR175;
VAR173 [4] = VAR12;
VAR173 [5] = VAR121;
VAR173 [6] = VAR60;
VAR173 [7] = VAR95;
VAR173 [8] = VAR182;
end
reg VAR82;
reg VAR127;
reg VAR153;
reg [7 : 0] VAR178;
reg [7 : 0] VAR114;
reg [7 : 0] VAR116;
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR82 <= 0;
VAR127 <= 0;
VAR178 <= 0;
VAR114 <= 0;
VAR153 <= 0;
VAR116 <= 0;
end
else
begin
if (VAR95)
begin
VAR82 <= 0;
VAR127 <= 0;
VAR178 <= 0;
VAR114 <= 0;
VAR153 <= 0;
VAR116 <= 0;
end
else
begin
VAR82 <= VAR136;
VAR127 <= VAR83;
VAR178 <= VAR130;
VAR114 <= VAR92;
VAR153 <= VAR67;
VAR116 <= VAR45;
end
end
end
always @
begin
VAR107 = VAR14;
end
reg [31 : 0] VAR96;
always @ (posedge VAR50 or negedge VAR68)
begin
if (!VAR68)
begin
VAR96 <= 0;
end
else
begin
if (VAR95)
VAR96 <= 0;
end
else
VAR96 <= VAR128;
end
end
always @
begin
VAR105 = 0;
VAR105 [ 0 ] = VAR143;
VAR105 [ 23 : 16 ] = VAR168;
end
end
endgenerate
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai.pp.symbol.v | 1,409 | module MODULE1 (
input VAR10 ,
input VAR3 ,
input VAR5 ,
input VAR9 ,
input VAR8 ,
output VAR6 ,
input VAR1 ,
input VAR2,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/spu/rtl/spu_mared.v | 21,068 | module MODULE1 (
VAR71,
VAR20,
VAR98,
VAR160,
VAR155,
VAR99,
VAR90,
VAR159,
VAR125,
VAR76,
VAR113,
VAR31,
VAR123,
VAR23,
VAR119,
VAR18,
VAR116,
VAR118,
VAR57,
VAR86,
VAR122,
VAR22,
VAR78,
VAR30,
VAR79,
VAR17,
VAR15,
VAR96,
VAR121,
VAR134,
VAR1,
VAR26,
VAR3,
VAR148,
VAR27,
VAR132,
VAR29,
VAR37,
VAR133,
VAR106,
VAR128,
reset,
VAR111);
input reset;
input VAR111;
input VAR128;
input VAR15;
input VAR96;
input VAR121;
input VAR134;
input VAR1;
input VAR26;
input VAR3;
input VAR148;
input VAR27;
input VAR132;
input VAR29;
input VAR37;
input VAR133;
input VAR106;
output [3:0] VAR71;
output VAR20;
output VAR98;
output VAR160;
output VAR155;
output VAR99;
output VAR90;
output VAR159;
output VAR125;
output VAR76;
output VAR113;
output VAR31;
output VAR123;
output VAR23;
output VAR119;
output VAR18;
output VAR116;
output VAR118;
output VAR57;
output VAR86;
output VAR122;
output VAR22;
output VAR78;
output VAR30;
output VAR79;
output VAR17;
wire VAR48;
wire VAR78;
wire VAR120,VAR47,VAR2;
wire VAR69;
wire VAR157,VAR11,VAR158;
wire VAR52,VAR102,VAR145,
VAR154,VAR74;
wire VAR25;
wire VAR49;
wire VAR84;
wire VAR146 = reset | VAR78 | VAR133 |
VAR49;
wire VAR80 = (VAR78 | VAR133 | VAR49) &
(VAR1 | VAR26);
wire VAR110 = reset | VAR148;
VAR70 #(1) VAR60 (
.din(1'b1) ,
.VAR34(VAR86),
.en(VAR80),
.rst(VAR110), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR8 #(1) VAR131 (
.din(VAR53) ,
.VAR34(VAR152),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR35 #(1) VAR97 (
.din(VAR83) ,
.VAR34(VAR84),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR49 = VAR84 & VAR106;
VAR35 #(1) VAR66 (
.din(VAR88) ,
.VAR34(VAR151),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR35 #(1) VAR85 (
.din(VAR45) ,
.VAR34(VAR9),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR35 #(1) VAR38 (
.din(VAR140) ,
.VAR34(VAR56),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR35 #(1) VAR55 (
.din(VAR21) ,
.VAR34(VAR43),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR35 #(1) VAR105 (
.din(VAR107) ,
.VAR34(VAR112),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR35 #(1) VAR68 (
.din(VAR6) ,
.VAR34(VAR130),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR35 #(1) VAR149 (
.din(VAR75) ,
.VAR34(VAR72),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR35 #(1) VAR10 (
.din(VAR94) ,
.VAR34(VAR141),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
wire VAR32,VAR92;
wire VAR7 = VAR96 & ~(VAR92 | VAR32);
wire VAR91 = ~(VAR96 | VAR32) & VAR121;
wire VAR24 = VAR146;
wire VAR62 = VAR3 & ~VAR133;
wire VAR16 = (VAR1 | VAR134) & VAR62;
wire VAR54 = VAR16;
VAR70 #(1) VAR108 (
.din(1'b1) ,
.VAR34(VAR40),
.en(VAR16),
.rst(VAR24), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR48 = VAR146;
assign VAR120 = ((VAR1 | VAR134) & VAR15 & VAR62) |
(VAR72 & ~VAR92);
VAR70 #(1) VAR89 (
.din(1'b1) ,
.VAR34(VAR32),
.en(VAR120),
.rst(VAR48), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR47 = VAR146;
assign VAR2 = VAR56 & VAR91;
VAR70 #(1) VAR63 (
.din(1'b1) ,
.VAR34(VAR92),
.en(VAR2),
.rst(VAR47), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
wire VAR153;
VAR8 #(1) VAR138 (
.din(VAR54) ,
.VAR34(VAR153),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
wire VAR44 = VAR26 & VAR148;
wire VAR143,VAR95;
VAR8 #(2) VAR51 (
.din({VAR44,VAR143}) ,
.VAR34({VAR143,VAR95}),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR122 = VAR143 | VAR25 | VAR62;
assign VAR22 = VAR143 | VAR25 | VAR3;
assign VAR69 = VAR153 | VAR95;
assign VAR157 = VAR43 & VAR27;
assign VAR11 = VAR112 & VAR27;
assign VAR158 = VAR130 & VAR132;
wire VAR136 = VAR157 | VAR11 |
VAR158;
VAR35 #(2) VAR36 (
.din({VAR136,VAR59}) ,
.VAR34({VAR59,VAR64}),
.rst(VAR146), .clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR78 = VAR64 | VAR49;
assign VAR17 = ~VAR152;
assign VAR53 = (
VAR146 | VAR78 |
(VAR152 & ~VAR69));
wire VAR126;
assign VAR52 = VAR43 & ~VAR27;
assign VAR102 = VAR126 & ~VAR152;
assign VAR154 = VAR130 & ~VAR132;
assign VAR74 = VAR112 & VAR92 & ~VAR27;
assign VAR83 = (
VAR74 |
VAR52 | VAR102 |
VAR154 |
(VAR152 & VAR69 & ~(VAR92|VAR32)));
assign VAR119 = VAR84;
assign VAR88 = (
(VAR84 & VAR92) );
assign VAR45 = (
(VAR84 & ~VAR92));
assign VAR23 = VAR9 | VAR29;
assign VAR140 = (
(VAR9 & ~(VAR92 | VAR32)));
assign VAR21 = (
(VAR56 & VAR7));
assign VAR107 = (
(VAR151) );
assign VAR6 = (
(VAR141));
assign VAR75 = (
(VAR152 & VAR69 & VAR32) |
(VAR56 & ~VAR7));
VAR35 #(1) VAR46 (
.din(VAR72) ,
.VAR34(VAR145),
.clk (VAR111),
.rst(VAR146), .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR123 = VAR72 & ~VAR92;
assign VAR31 = VAR145 & ~VAR92;
assign VAR25 = VAR72 & VAR92;
VAR35 #(1) VAR5 (
.din(VAR145) ,
.VAR34(VAR126),
.clk (VAR111),
.rst(VAR146), .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR94 = (
(VAR9 & VAR32));
assign VAR113 = VAR52 | VAR74 |
VAR154;
assign VAR18 = (VAR83 | VAR45) & ~VAR106;
assign VAR79 = VAR21 | VAR107 |
VAR6;
VAR8 #(3) VAR19(
.din({VAR21,VAR50,VAR147}) ,
.VAR34({VAR50,VAR147,VAR117}),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR8 #(3) VAR73(
.din({VAR6,VAR150,VAR124}) ,
.VAR34({VAR150,VAR124,VAR77}),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR8 #(2) VAR81(
.din({VAR107,VAR39}) ,
.VAR34({VAR39,VAR58}),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR116 = VAR117 | VAR58 |
VAR77;
VAR8 #(2) VAR144(
.din({VAR122,VAR13}) ,
.VAR34({VAR13,VAR135}),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR8 #(2) VAR101(
.din({VAR31,VAR137}) ,
.VAR34({VAR137,VAR61}),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
VAR8 #(1) VAR42 (
.din(VAR116) ,
.VAR34(VAR100),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR30 = VAR61 | VAR135 |
VAR100;
assign VAR160 = VAR83 & VAR1;
assign VAR98 = VAR45 & (VAR1 | VAR134);
assign VAR99 = VAR116 & VAR1;
assign VAR155 = VAR83 & VAR134;
assign VAR90 = VAR116 & VAR134;
assign VAR125 = VAR83 & VAR26;
assign VAR159 = VAR45 & VAR26;
assign VAR76 = VAR116 & VAR26;
assign VAR20 = VAR18 ;
wire [3:0] VAR142;
assign VAR142[0] = ~(VAR40 | VAR26);
assign VAR142[1] = (VAR40 | VAR26) & ~VAR92 & ~VAR32;
assign VAR142[2] = (VAR40 | VAR26) & VAR92 & ~VAR32;
assign VAR142[3] = (VAR40 | VAR26) & VAR32;
assign VAR71[3:0] = ~VAR142[3:0];
assign VAR118 = VAR142[2] | VAR142[1];
wire VAR87 = (~VAR27 & VAR32) & ~VAR69;
wire VAR41;
VAR67 #(1) VAR65 (
.VAR109 (1'b0),
.VAR115 (1'b1),
.VAR114 (VAR37),
.VAR129 (1'b0),
.VAR12 (~VAR87),
.VAR14 (VAR87),
.dout (VAR41)
);
wire VAR104;
wire VAR93 = VAR69 | VAR104;
wire VAR33;
VAR70 #(1) VAR139 (
.din(VAR41) ,
.VAR34(VAR33),
.en(VAR93),
.rst(reset),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
wire VAR28 = VAR134 | VAR1 | VAR26;
wire VAR4;
VAR8 #(1) VAR156 (
.din(VAR28) ,
.VAR34(VAR4),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
assign VAR57 = VAR33 & VAR4;
VAR8 #(1) VAR82 (
.din(VAR130) ,
.VAR34(VAR104),
.clk (VAR111)
, .VAR128(VAR128), .VAR103(), .VAR127());
endmodule | gpl-2.0 |
shahid313/MSCourseWork | Adv ASIC Design and FPGA/Assign4/qstn1_SequenceDetection/sqncdetct.v | 1,271 | module MODULE1(input in, clk,rst,output VAR5
);
localparam VAR1=5'b00001,
VAR8=5'b00010,
VAR4=5'b00100, VAR2=5'b01000,
VAR3=5'b10000;
reg [4:0] VAR7,VAR6;
always @(posedge clk,posedge rst)
if(rst)
VAR7<=VAR1;
else
VAR7<=VAR6;
always@(*)
case(VAR7)
VAR1: if(in) VAR6=VAR8;
else VAR6=VAR1;
VAR8: if(in) VAR6=VAR8;
else VAR6=VAR4;
VAR4: if(in) VAR6=VAR2;
else VAR6=VAR8;
VAR2: if(in) VAR6=VAR3;
else VAR6=VAR1;
VAR3: if(in) VAR6=VAR8;
else VAR6=VAR1;
default: VAR6=VAR1;
endcase
assign VAR5= in?(VAR7==VAR3):1'b0;
endmodule | gpl-2.0 |
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