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google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3/sky130_fd_sc_ms__nand3_4.v | 2,175 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR7 ,
VAR2 ,
VAR6,
VAR9,
VAR10 ,
VAR1
);
output VAR5 ;
input VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR6;
input VAR9;
input VAR10 ;
input VAR1 ;
VAR4 VAR3 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5,
VAR8,
VAR7,
VAR2
);
output VAR5;
input VAR8;
input VAR7;
input VAR2;
supply1 VAR6;
supply0 VAR9;
supply1 VAR10 ;
supply0 VAR1 ;
VAR4 VAR3 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b.pp.blackbox.v | 1,349 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR7 ,
VAR2 ,
VAR5 ,
VAR3,
VAR9,
VAR1 ,
VAR6
);
output VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR3;
input VAR9;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_jtag_dc_streaming/altera_jtag_streaming.v | 23,657 | module MODULE1 (
output VAR41,
input VAR88,
output [7:0] VAR75,
output VAR82,
input [7:0] VAR50,
input VAR14,
output VAR115,
input VAR6,
input VAR37,
output reg VAR61 = 1'b0
);
function integer VAR71;
input [31:0] VAR5;
integer VAR43;
begin
VAR43 = VAR5;
if ( VAR43 <= 0 ) VAR71 = 0;
end
else begin
for(VAR71 = -1; VAR43 > 0; VAR71 = VAR71 + 1)
VAR43 = VAR43 >> 1;
end
end
endfunction
parameter VAR107 = 0;
parameter VAR76 = 0;
parameter VAR34 = 0;
localparam VAR60 = VAR71(VAR76);
localparam VAR9 = VAR71(VAR34);
parameter VAR42 = 8;
parameter VAR40 = 3;
localparam VAR46 = 0;
localparam VAR51 = 1;
localparam VAR17 = 2;
localparam VAR90 = 3;
localparam VAR11 = 4;
localparam VAR48 = 3;
wire [VAR48 - 1 : 0] VAR31;
wire [VAR48 - 1 : 0] VAR98;
reg VAR105 = 0;
wire VAR91;
wire VAR27;
wire VAR113;
wire VAR66;
localparam VAR59 = 'h0;
localparam VAR56 = 'h1;
localparam VAR69 = 'h2;
localparam VAR16 = 'h3;
localparam VAR102 = 'h0;
localparam VAR111 = 'h1;
localparam VAR62 = 'h2;
reg [1:0] VAR26 = VAR59;
reg [1:0] VAR28 = VAR102;
reg [ 7:0] VAR63 = 'b0;
reg [ 7:0] VAR39 = 'b0;
reg VAR114 = 'b0;
reg [ 2:0] VAR93 = 'b0;
reg [10:0] VAR64 = 'b0;
reg [ 8:0] VAR7 = 'b0;
reg [ 8:0] VAR35 = 'b0;
reg [ 7:0] VAR77 = 'b0;
reg [ 2:0] VAR70 = 'b0;
reg [ 2:0] VAR8 = 'b0;
reg [ 3:0] VAR72 = 'b0;
reg [ 3:0] VAR12 = 'b0;
reg [18:0] VAR103 = 'b0;
reg [18:0] VAR67 = 'b0;
reg VAR68 = 'b0;
reg VAR49 = 'b0;
reg VAR95 = 'b0;
reg VAR83 = 'b0;
reg VAR96 = 'b0;
wire VAR4;
wire VAR45;
wire VAR85;
wire VAR55;
assign VAR4 = (VAR70 == 1);
assign VAR45 = (VAR8 == 1);
assign VAR85 = (VAR35[2:0] == 'b0);
assign VAR55 = (VAR103 == 'b0);
reg [ 7:0] VAR13 = 'b0;
reg [15:0] VAR80 = 'b0;
reg [9:0] VAR74 = 'b0;
reg [2:0] VAR79 = 'b0;
reg [2:0] VAR47 = 'b0;
wire [7:0] VAR21;
wire VAR58;
wire VAR108;
wire [7:0] VAR99;
reg VAR73 = 'b0;
reg [7:0] VAR30 = 'b0;
reg VAR101 = 'b0;
wire [7:0] VAR92;
wire VAR110;
assign VAR75 = VAR92;
assign VAR82 = VAR110;
assign VAR115 = VAR108;
assign VAR21 = VAR50;
assign VAR58 = VAR14;
reg VAR112 = 'b0;
reg VAR44 = 'b0;
reg VAR116 = 'b1;
wire VAR100;
assign VAR100 = VAR14;
wire [18:0] VAR86;
wire [18:0] VAR53;
wire [18:0] VAR87;
assign VAR86 = { VAR74, {8{1'b1}} };
assign VAR53 = (VAR47 == 0) ? 19'h0 : (19'h00080 << VAR47);
assign VAR87 = (VAR79 == 0) ? 19'h0 : (19'h00080 << VAR79);
wire VAR78;
wire VAR57;
wire VAR22;
wire VAR23;
VAR2 #(.VAR36(VAR40)) VAR3 (
.clk(VAR41),
.VAR88(1'b1),
.din(VAR112),
.dout(VAR78));
VAR2 #(.VAR36(VAR40)) VAR97 (
.clk(VAR41),
.VAR88(1'b1),
.din(VAR37),
.dout(VAR57));
VAR2 #(.VAR36(VAR40)) VAR19 (
.clk(VAR41),
.VAR88(1'b1),
.din(VAR44),
.dout(VAR22));
VAR2 #(.VAR36(VAR42)) VAR32 (
.clk(VAR6),
.VAR88(VAR116),
.din(1'b1),
.dout(VAR23));
always @ (posedge VAR6 or negedge VAR23) begin
if (~VAR23) begin
VAR112 <= 1'b0;
end else begin
VAR112 <= 1'b1;
end
end
always @ (posedge VAR6) begin
VAR44 <= ~VAR44;
end
always @ (posedge VAR41) begin
VAR101 <= 1'b0;
VAR73 <= 1'b0;
if (VAR98 == VAR46) begin
if (VAR113) begin
if (VAR13 == 'b0) begin
VAR26 <= VAR56;
end else begin
VAR26 <= VAR59;
end
VAR77 <= VAR13;
VAR72 <= 15;
VAR70 <= 0;
VAR83 <= 1'b0;
VAR96 <= 1'b0;
VAR95 <= 1'b0;
VAR67 <= 0;
end
if (VAR27) begin
case (VAR26)
VAR59: begin
VAR77 <= VAR77 - 1'b1;
if (VAR77 == 1) begin
VAR26 <= VAR56;
end
end
VAR56: begin
VAR80 <= {VAR91, VAR80[15:1]};
VAR72 <= VAR72 - 1'b1;
if (VAR72 == 3) begin
VAR79 <= {VAR91, VAR80[15:14]};
VAR74 <= VAR80[13:4];
VAR26 <= VAR69;
VAR83 <= 1'b1;
end
end
VAR69: begin
VAR80 <= {VAR91, VAR80[15:1]};
VAR72 <= VAR72 - 1'b1;
if (VAR83) begin
VAR83 <= 1'b0;
if (VAR79 == 3'b111) begin
VAR95 <= 1'b1;
end
VAR103 <= VAR86;
end
if (VAR72 == 0) begin
VAR47 <= {VAR91, VAR80[15:14]};
VAR26 <= VAR16;
VAR96 <= 1'b1;
end
end
VAR16: begin
VAR63 <= {VAR91, VAR63[7:1]};
if (VAR96) begin
VAR96 <= 1'b0;
case (VAR47)
3'b111: VAR67 <= VAR86 + 1'b1;
3'b000: VAR67 <= 'b0;
default: VAR67 <= VAR53;
endcase
end
VAR70 <= VAR70 - 1'b1;
VAR68 <= (VAR67 != 0);
if (VAR4 && VAR68) begin
VAR67 <= VAR67 - 1'b1;
VAR101 <= 1'b1;
VAR30 <= {VAR91, VAR63[7:1]};
end
end
endcase
end
end
if (VAR98 == VAR46) begin
if (VAR113) begin
VAR28 <= VAR102;
if (|VAR13[2:0]) begin
VAR35[8:3] <= VAR13[7:3] + 1'b1;
VAR35[2:0] <= 3'b0;
end else begin
VAR35 <= {1'b0, VAR13};
end
VAR12 <= 0;
VAR8 <= 0;
VAR39 <= {{7{1'b0}}, VAR100};
VAR49 <= 0;
end
if (VAR27) begin
VAR39 <= {1'b0, VAR39[7:1]};
case (VAR28)
VAR102: begin
VAR12 <= VAR12 - 1'b1;
if (VAR12 == 2) begin
if (VAR35 == 0) begin
VAR73 <= VAR95;
end
end
if (VAR12 == 1) begin
if (VAR35 == 0) begin
VAR28 <= VAR62;
VAR49 <= VAR95 || (VAR103<=VAR87+1);
VAR39 <= VAR95 ? VAR99 : 8'h4a;
end else begin
VAR28 <= VAR111;
VAR35 <= VAR35 - 1'b1;
VAR73 <= 1'b0;
VAR39 <= 8'h4a;
end
end
end
VAR111: begin
VAR35 <= VAR35 - 1'b1;
if (VAR85) begin
VAR39 <= 8'h4a;
end
if (VAR35 == 1) begin
VAR73 <= VAR95;
end
if (VAR35 == 0) begin VAR28 <= VAR62;
VAR49 <= VAR95 || (VAR103<=VAR87+1);
VAR39 <= VAR95 ? VAR99 : 8'h4a;
end
end
VAR62: begin
VAR8 <= VAR8 - 1'b1;
if (VAR8 == 2) begin
VAR73 <= VAR55 ? 1'b0 : VAR49;
end
if (VAR45) begin
if (~VAR55) begin
VAR103 <= VAR103 - 1'b1;
end
VAR49 <= VAR95 || (VAR103<=VAR87+1);
VAR39 <= (VAR49 & ~VAR55) ? VAR99 : 8'h4a;
end
end
endcase
end
end
if (VAR98 == VAR51) begin
if (VAR113) begin
VAR114 <= 1'b0; end
if (VAR27) begin
VAR114 <= VAR91;
end
end
if (VAR98 == VAR17) begin
if (VAR113) begin
VAR93 <= {VAR78, VAR22, VAR57};
end
if (VAR27) begin
VAR93 <= {1'b0, VAR93[2:1]}; end
if (VAR66) begin
VAR116 <= 1'b0;
end else begin
VAR116 <= 1'b1;
end
end
if (VAR98 == VAR90) begin
if (VAR113) begin
VAR64 <= {VAR107[2:0], VAR60[3:0], VAR9[3:0]};
end
if (VAR27) begin
VAR64 <= {1'b0, VAR64[10:1]}; end
end
if (VAR98 == VAR11) begin
if (VAR113) begin
VAR7 <= 'b0; end
if (VAR27) begin
VAR7 <= {VAR91, VAR7[8:1]};
end
if (VAR66) begin
{VAR61, VAR13} <= VAR7;
end
end
end
always @ * begin
if (VAR27) begin
case (VAR98)
VAR46: VAR105 <= VAR39[0];
VAR51: VAR105 <= VAR114;
VAR17: VAR105 <= VAR93[0];
VAR90: VAR105 <= VAR64[0];
VAR11: VAR105 <= VAR7[0];
default: VAR105 <= 1'b0;
endcase
end else begin
VAR105 <= 1'b0;
end
end
VAR104 VAR25 (
.VAR31 (VAR31),
.VAR105 (VAR105),
.VAR98 (VAR98),
.VAR41 (VAR41),
.VAR91 (VAR91),
.VAR52 (VAR113),
.VAR38 (),
.VAR84 (),
.VAR10 (),
.VAR18 (),
.VAR54 (VAR27),
.VAR20 (VAR66),
.VAR65 ()
);
VAR1 VAR81 (
.clk (VAR41),
.VAR88 (VAR88),
.VAR109 (), .VAR89 (VAR101),
.VAR24 (VAR30),
.VAR94 (1'b1), .VAR15 (VAR110),
.VAR33 (VAR92)
);
VAR29 VAR106 (
.clk (VAR41),
.VAR88 (VAR88),
.VAR109 (VAR108),
.VAR89 (VAR58),
.VAR24 (VAR21),
.VAR94 (VAR73),
.VAR15 (),
.VAR33 (VAR99)
);
endmodule | mit |
pwwu/FPGA | VGAbased/vga_game_graph.v | 13,405 | module MODULE1
(
input wire clk, reset,
input wire VAR37,
input wire [1:0] VAR65,
input wire [1:0] VAR11,
input wire VAR29,
input wire [9:0] VAR23, VAR52,
output reg VAR49, VAR26, VAR7,
output wire VAR10,
output reg [2:0] VAR51
);
localparam VAR44 = 640;
localparam VAR67 = 480;
wire VAR34;
localparam VAR6 = 20;
localparam VAR46 = 25;
localparam VAR8 = 50;
localparam VAR63 = 53;
wire [9:0] VAR12;
wire [9:0] VAR32;
reg [9:0] VAR35;
reg [9:0] VAR59;
localparam VAR9 = 2;
localparam VAR21 = 62;
localparam VAR22 = 9;
localparam VAR30 = 5;
wire [9:0] VAR70, VAR31;
wire [9:0] VAR62, VAR72;
reg [9:0] VAR58;
reg [9:0] VAR28;
reg [9:0] VAR33;
reg [9:0] VAR53;
localparam VAR55 = 600;
localparam VAR39 = 603;
wire [9:0] VAR61, VAR5;
localparam VAR1 = 72;
reg [9:0] VAR38, VAR69;
localparam VAR27 = 4;
localparam VAR25 = 8;
wire [9:0] VAR43, VAR24;
wire [9:0] VAR47, VAR71;
reg [9:0] VAR68, VAR17;
wire [9:0] VAR40, VAR54;
reg [9:0] VAR41, VAR19;
reg [9:0] VAR15, VAR13;
localparam VAR16 = 2;
localparam VAR18 = -2;
wire [2:0] VAR42, VAR66;
reg [7:0] VAR20;
wire VAR57;
wire VAR2, VAR64, VAR56, VAR60, VAR4, VAR50;
wire [2:0] VAR48, VAR3, VAR36, VAR14, VAR45;
always @*
case (VAR42)
3'h0: VAR20 = 8'b00111100; 3'h1: VAR20 = 8'b01111110; 3'h2: VAR20 = 8'b11111111; 3'h3: VAR20 = 8'b11111111; 3'h4: VAR20 = 8'b11111111; 3'h5: VAR20 = 8'b11111111; 3'h6: VAR20 = 8'b01111110; 3'h7: VAR20 = 8'b00111100; endcase
always @(posedge clk, posedge reset)
if (reset)
begin
VAR38 <= 0;
VAR35 <= 0;
VAR68 <= 0;
VAR17 <= 0;
VAR58 <= VAR63;
VAR28 <= 0+VAR21/2;
VAR41 <= 10'h004;
VAR15 <= 10'h004;
end
else
begin
VAR38 <= VAR69;
VAR35 <= VAR59;
VAR68 <= VAR40;
VAR17 <= VAR54;
VAR41 <= VAR19;
VAR15 <= VAR13;
VAR58 <= VAR33; VAR28 <= VAR53;
end
assign VAR34 = (VAR52==481) && (VAR23==0);
assign VAR2 = (VAR6<=VAR23) && (VAR23<=VAR46);
assign VAR48 = 3'b001; assign VAR61 = VAR38;
assign VAR5 = VAR61 + VAR1 - 1;
assign VAR64 = (VAR55<=VAR23) && (VAR23<=VAR39) &&
(VAR61<=VAR52) && (VAR52<=VAR5);
assign VAR14 = 3'b010; always @*
begin
VAR69 = VAR38; if(VAR29)
VAR69 = (VAR67-VAR1)/2;
end
else if (VAR34)
if (VAR65[1] & (VAR5 < (VAR67-1-VAR27)))
VAR69 = VAR38 + VAR27; else if (VAR65[0] & (VAR61 > VAR27))
VAR69 = VAR38 - VAR27; end
assign VAR12 = VAR35;
assign VAR32 = VAR12 + VAR21 -1;
assign VAR56 = (VAR8<=VAR23) && (VAR23<=VAR63) && (VAR12<=VAR52) && (VAR52<=VAR32);
assign VAR3 = 3'b000;
always @*
begin
VAR59 = VAR35;
if(VAR29)
VAR59 = (VAR67-VAR21)/2;
end
else if (VAR34)
if (VAR11[0] & (VAR32 < (VAR67-1-VAR9)))
VAR59 = VAR35 + VAR9; else if ( (~VAR11[0]) & (VAR12 > VAR9) )
VAR59 = VAR35 - VAR9; end
assign VAR70 = VAR58;
assign VAR31 = VAR70 + VAR22 -1;
assign VAR62 = VAR28;
assign VAR72 = VAR62 + VAR22 -1;
assign VAR60 =
(VAR70<=VAR23) && (VAR23<=VAR31) &&
(VAR62<=VAR52) && (VAR52<=VAR72);
assign VAR36 = 3'b000; always @*
begin
VAR7 = 1'b0;
VAR33 = VAR58;
VAR53 = VAR28;
if(VAR29)
begin
VAR33 = VAR63;
VAR53 = (VAR67-VAR21)/2 + VAR21/2;
end
else if (VAR34)
if ((VAR55<=VAR31) && (VAR31<=VAR39) &&
(VAR61<=VAR72) && (VAR62<=VAR5))
begin
VAR33 = VAR63;
VAR53 = VAR35+VAR21/2;
VAR7 = 1'b1;
end
else if ( VAR11[1] || (VAR70 >= VAR63+5) )
VAR33 = VAR58 + VAR30;
end
else if ( (VAR58<=(VAR8-1)) || (VAR58>=(VAR44-VAR22-1)) )
begin
VAR33 = VAR63;
VAR53 = VAR35+VAR21/2;
end
else
begin
VAR33 = VAR63;
VAR53 = VAR35+VAR21/2;
end
end
assign VAR43 = VAR68;
assign VAR47 = VAR17;
assign VAR24 = VAR43 + VAR25 - 1;
assign VAR71 = VAR47 + VAR25 - 1;
assign VAR4 =
(VAR43<=VAR23) && (VAR23<=VAR24) &&
(VAR47<=VAR52) && (VAR52<=VAR71);
assign VAR42 = VAR52[2:0] - VAR47[2:0];
assign VAR66 = VAR23[2:0] - VAR43[2:0];
assign VAR57 = VAR20[VAR66];
assign VAR50 = VAR4 & VAR57;
assign VAR45 = 3'b100; assign VAR40 = (VAR29) ? VAR44/2 :
(VAR34) ? VAR68+VAR41 :
VAR68 ;
assign VAR54 = (VAR29) ? VAR67/2 :
(VAR34) ? VAR17+VAR15 :
VAR17 ;
always @*
begin
VAR49 = 1'b0;
VAR26 = 1'b0;
VAR19 = VAR41;
VAR13 = VAR15;
if (VAR29) begin
VAR19 = VAR18;
VAR13 = VAR16;
end
else if (VAR47 < 1) VAR13 = VAR16;
end
else if (VAR71 > (VAR67-1)) VAR13 = VAR18;
else if (VAR43 <= VAR46) VAR19 = VAR16; else if ((VAR55<=VAR24) && (VAR24<=VAR39) &&
(VAR61<=VAR71) && (VAR47<=VAR5))
begin
VAR19 = VAR18;
VAR49 = 1'b1;
end
else if (VAR24>VAR44) VAR26 = 1'b1; end
always @*
if (~VAR37)
VAR51 = 3'b000; else
if (VAR2)
VAR51 = VAR48;
else if (VAR60)
VAR51 = VAR36;
else if (VAR64)
VAR51 = VAR14;
else if (VAR56)
VAR51 = VAR3;
else if (VAR50)
VAR51 = VAR45;
else
VAR51 = 3'b110;
assign VAR10 = VAR2 | VAR64 | VAR50 | VAR60 | VAR56;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi.pp.blackbox.v | 1,482 | module MODULE1 (
VAR5 ,
VAR2,
VAR6,
VAR4 ,
VAR8 ,
VAR1,
VAR7,
VAR3 ,
VAR9
);
output VAR5 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR8 ;
input VAR1;
input VAR7;
input VAR3 ;
input VAR9 ;
endmodule | apache-2.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/bee3Top/src/c3dClkGen2.v | 5,924 | module MODULE1 (
input VAR2,
output VAR10,
output VAR53,
output VAR59,
output VAR27,
output VAR52
);
VAR61 #(.VAR32("VAR18"), .VAR46(2), .VAR19(0.0), .VAR55(3.2),
.VAR47(4), .VAR50(0.5), .VAR60(0.0),
.VAR5(2), .VAR13(0.5), .VAR63(0.0),
.VAR12(16), .VAR62(0.375), .VAR21(0.0),
.VAR11(4), .VAR8(0.5), .VAR33(180.0),
.VAR15(8), .VAR66(0.5), .VAR41(0.0),
.VAR7(4), .VAR3(0.5), .VAR51(180.0),
.VAR49("VAR34"), .VAR44(1), .VAR48(0.100))
VAR24 (.VAR31(VAR67 ), .VAR39 (VAR23 ), .VAR4 (VAR40 ), .VAR68 ( ), .VAR14 (VAR27 ), .VAR43 ( ), .VAR45 ( ), .VAR9 (VAR52 ), .VAR16 (VAR67 ), .VAR2 (VAR2 ), .VAR1 (1'b0 )
);
VAR25 VAR30 (.VAR69(VAR23), .VAR54(VAR10));
VAR25 VAR64 (.VAR69(VAR40), .VAR54(VAR53));
assign VAR59 = VAR23;
VAR61 #(.VAR32("VAR18"), .VAR46(20), .VAR19(0.0), .VAR55(10.0),
.VAR47(4), .VAR50(0.5), .VAR60(0.0),
.VAR5(4), .VAR13(0.5), .VAR63(90.0),
.VAR12(16), .VAR62(0.375), .VAR21(0.0),
.VAR11(4), .VAR8(0.5), .VAR33(180.0),
.VAR15(8), .VAR66(0.5), .VAR41(0.0),
.VAR7(4), .VAR3(0.5), .VAR51(180.0),
.VAR49("VAR34"), .VAR44(2), .VAR48(0.100))
VAR6 (.VAR31(VAR22 ), .VAR39 (VAR36 ), .VAR4 (VAR37 ), .VAR68 (VAR56 ), .VAR14 (VAR57 ),
.VAR43 (VAR42 ), .VAR45 ( ),
.VAR9 (VAR35), .VAR16 (VAR22 ), .VAR2 (VAR2 ), .VAR1 (1'b0 )
);
VAR25 VAR26 (.VAR69(VAR36), .VAR54(VAR65)); VAR25 VAR20 (.VAR69(VAR37), .VAR54(VAR28)); VAR25 VAR17 (.VAR69(VAR56), .VAR54(VAR38)); VAR25 VAR58 (.VAR69(VAR42), .VAR54(VAR29));
endmodule | gpl-3.0 |
ychaim/FPGA-Litecoin-Miner | source/altera_ram.v | 7,266 | module MODULE1 # ( parameter VAR42=10 ) (
address,
VAR4,
VAR38,
VAR11,
VAR53);
input [VAR42-1:0] address;
input VAR4;
input [255:0] VAR38;
input VAR11;
output [255:0] VAR53;
tri1 VAR4;
wire [255:0] VAR45;
wire [255:0] VAR53 = VAR45[255:0];
VAR15 VAR20 (
.VAR28 (address),
.VAR26 (VAR4),
.VAR7 (VAR38),
.VAR10 (VAR11),
.VAR6 (VAR45),
.VAR2 (1'b0),
.VAR14 (1'b0),
.VAR35 (1'b1),
.VAR47 (1'b0),
.VAR29 (1'b0),
.VAR30 (1'b1),
.VAR34 (1'b1),
.VAR24 (1'b1),
.VAR36 (1'b1),
.VAR43 (1'b1),
.VAR8 (1'b1),
.VAR17 (1'b1),
.VAR50 (1'b1),
.VAR16 (),
.VAR55 (),
.VAR9 (1'b1),
.VAR19 (1'b1),
.VAR21 (1'b0));
VAR20.VAR41 = "VAR39",
VAR20.VAR56 = "VAR39",
VAR20.VAR1 = "VAR32 VAR40 VAR37",
VAR20.VAR52 = "VAR44=VAR48",
VAR20.VAR54 = "VAR15",
VAR20.VAR49 = 2 << (VAR42-1),
VAR20.VAR13 = "VAR12",
VAR20.VAR18 = "VAR5",
VAR20.VAR31 = "VAR33",
VAR20.VAR46 = "VAR23",
VAR20.VAR3 = "VAR22",
VAR20.VAR25 = VAR42,
VAR20.VAR27 = 256,
VAR20.VAR51 = 1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2.pp.blackbox.v | 1,301 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR1 ,
VAR6,
VAR4,
VAR5 ,
VAR3
);
output VAR2 ;
input VAR7 ;
input VAR1 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2b/sky130_fd_sc_hd__nor2b.symbol.v | 1,326 | module MODULE1 (
input VAR2 ,
input VAR1,
output VAR3
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_of_pre_fifo.v | 8,024 | module MODULE1 #
(
parameter VAR20 = 100, parameter VAR12 = 4, parameter VAR16 = 32 )
(
input clk, input rst, input VAR18, input VAR8, input [VAR16-1:0] din, output VAR22, output [VAR16-1:0] dout, output VAR6 );
localparam VAR15
= (VAR12 == 2) ? 1 :
((VAR12 == 3) || (VAR12 == 4)) ? 2 :
(((VAR12 == 5) || (VAR12 == 6) ||
(VAR12 == 7) || (VAR12 == 8)) ? 3 :
VAR12 == 9 ? 4 : 'VAR3);
localparam VAR7 = VAR12 - 5;
integer VAR17;
reg [VAR16-1:0] VAR1[0:VAR12-1] ;
reg [8:0] VAR13 ;
reg [5:0] VAR9 ;
reg [VAR15-1:0] VAR21 ;
reg [VAR15-1:0] VAR23 ;
reg [VAR15-1:0] VAR11 ;
reg [VAR15-1:0] VAR14 ;
reg [VAR15:0] VAR4;
wire [VAR15-1:0] VAR19;
wire [VAR15-1:0] VAR10;
wire [VAR16-1:0] VAR5;
wire VAR2;
assign dout = VAR13[0] ? din : VAR5;
assign VAR22 = !VAR18 && (!VAR13[1] || VAR8);
assign VAR2 = VAR8 & ((!VAR13[3] & !VAR18)|(!VAR9[2] & VAR18));
always @ (posedge clk)
if (VAR2)
assign VAR5 = VAR1[VAR21];
assign VAR19 = (VAR21 + 1'b1)%VAR12;
always @ (posedge clk)
begin
if (rst) begin
VAR21 <= 'b0;
VAR11 <= 'b0;
end
else if ((!VAR13[4]) & (!VAR18)) begin
VAR21 <= VAR19;
VAR11 <= VAR19;
end
end
always @ (posedge clk)
begin
if (rst)
VAR13 <= 9'h1ff;
end
else begin
if (VAR13[2] & !VAR9[3] & VAR18 & VAR8)
VAR13[3:0] <= 4'b0000;
end
else if (!VAR13[2] & !VAR9[3] & !VAR18 & !VAR8) begin
VAR13[0] <= (VAR19 == VAR14);
VAR13[1] <= (VAR19 == VAR14);
VAR13[2] <= (VAR19 == VAR14);
VAR13[3] <= (VAR19 == VAR14);
end
if (VAR13[8] & !VAR9[5] & VAR18 & VAR8)
VAR13[8:4] <= 5'b00000;
else if (!VAR13[8] & !VAR9[5] & !VAR18 & !VAR8) begin
VAR13[4] <= (VAR19 == VAR14);
VAR13[5] <= (VAR19 == VAR14);
VAR13[6] <= (VAR19 == VAR14);
VAR13[7] <= (VAR19 == VAR14);
VAR13[8] <= (VAR19 == VAR14);
end
end
end
assign VAR10 = (VAR23 + 1'b1)%VAR12;
always @ (posedge clk)
begin
if (rst) begin
VAR23 <= 'b0;
VAR14 <= 'b0;
end
else if ((VAR8) & ((!VAR13[5] & !VAR18) | (!VAR9[1] & VAR18))) begin
VAR23 <= VAR10;
VAR14 <= VAR10;
end
end
always @ (posedge clk)
begin
if (rst)
VAR9 <= 6'b000000;
end
else if (!VAR13[6] & VAR9[0] & !VAR18 & !VAR8)
VAR9 <= 6'b000000;
else if (!VAR13[6] & !VAR9[0] & VAR18 & VAR8) begin
VAR9[0] <= (VAR10 == VAR11);
VAR9[1] <= (VAR10 == VAR11);
VAR9[2] <= (VAR10 == VAR11);
VAR9[3] <= (VAR10 == VAR11);
VAR9[4] <= (VAR10 == VAR11);
VAR9[5] <= (VAR10 == VAR11);
end
end
always @ (posedge clk)
begin
if (rst)
VAR4 <= 'b0;
end
else if (VAR8 & VAR18 & !VAR9[4])
VAR4 <= VAR4 + 1'b1;
else if (!VAR8 & !VAR18 & !VAR13[7])
VAR4 <= VAR4 - 1'b1;
end
assign VAR6 = (VAR4 >= VAR7);
endmodule | bsd-2-clause |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/verilog/convolve_kernel.v | 67,957 | module MODULE1 (
VAR241,
VAR143,
VAR442,
VAR207,
VAR189,
VAR175,
VAR88,
VAR36,
VAR384,
VAR490,
VAR254,
VAR136,
VAR351,
VAR42,
VAR115,
VAR89,
VAR79,
VAR157,
VAR74,
VAR406,
VAR299,
VAR165,
VAR96,
VAR285,
VAR83,
VAR271,
VAR473
);
parameter VAR318 = 137'd1;
parameter VAR201 = 137'd2;
parameter VAR482 = 137'd4;
parameter VAR319 = 137'd8;
parameter VAR121 = 137'd16;
parameter VAR416 = 137'd32;
parameter VAR462 = 137'd64;
parameter VAR251 = 137'd128;
parameter VAR397 = 137'd256;
parameter VAR261 = 137'd512;
parameter VAR331 = 137'd1024;
parameter VAR350 = 137'd2048;
parameter VAR303 = 137'd4096;
parameter VAR477 = 137'd8192;
parameter VAR362 = 137'd16384;
parameter VAR265 = 137'd32768;
parameter VAR193 = 137'd65536;
parameter VAR148 = 137'd131072;
parameter VAR22 = 137'd262144;
parameter VAR452 = 137'd524288;
parameter VAR374 = 137'd1048576;
parameter VAR131 = 137'd2097152;
parameter VAR376 = 137'd4194304;
parameter VAR149 = 137'd8388608;
parameter VAR8 = 137'd16777216;
parameter VAR56 = 137'd33554432;
parameter VAR379 = 137'd67108864;
parameter VAR267 = 137'd134217728;
parameter VAR39 = 137'd268435456;
parameter VAR230 = 137'd536870912;
parameter VAR177 = 137'd1073741824;
parameter VAR474 = 137'd2147483648;
parameter VAR345 = 137'd4294967296;
parameter VAR393 = 137'd8589934592;
parameter VAR232 = 137'd17179869184;
parameter VAR161 = 137'd34359738368;
parameter VAR53 = 137'd68719476736;
parameter VAR426 = 137'd137438953472;
parameter VAR295 = 137'd274877906944;
parameter VAR436 = 137'd549755813888;
parameter VAR220 = 137'd1099511627776;
parameter VAR140 = 137'd2199023255552;
parameter VAR28 = 137'd4398046511104;
parameter VAR480 = 137'd8796093022208;
parameter VAR23 = 137'd17592186044416;
parameter VAR113 = 137'd35184372088832;
parameter VAR280 = 137'd70368744177664;
parameter VAR269 = 137'd140737488355328;
parameter VAR304 = 137'd281474976710656;
parameter VAR17 = 137'd562949953421312;
parameter VAR472 = 137'd1125899906842624;
parameter VAR13 = 137'd2251799813685248;
parameter VAR402 = 137'd4503599627370496;
parameter VAR205 = 137'd9007199254740992;
parameter VAR215 = 137'd18014398509481984;
parameter VAR156 = 137'd36028797018963968;
parameter VAR420 = 137'd72057594037927936;
parameter VAR146 = 137'd144115188075855872;
parameter VAR63 = 137'd288230376151711744;
parameter VAR40 = 137'd576460752303423488;
parameter VAR238 = 137'd1152921504606846976;
parameter VAR81 = 137'd2305843009213693952;
parameter VAR195 = 137'd4611686018427387904;
parameter VAR308 = 137'd9223372036854775808;
parameter VAR203 = 137'd18446744073709551616;
parameter VAR388 = 137'd36893488147419103232;
parameter VAR323 = 137'd73786976294838206464;
parameter VAR59 = 137'd147573952589676412928;
parameter VAR479 = 137'd295147905179352825856;
parameter VAR434 = 137'd590295810358705651712;
parameter VAR68 = 137'd1180591620717411303424;
parameter VAR268 = 137'd2361183241434822606848;
parameter VAR404 = 137'd4722366482869645213696;
parameter VAR114 = 137'd9444732965739290427392;
parameter VAR221 = 137'd18889465931478580854784;
parameter VAR325 = 137'd37778931862957161709568;
parameter VAR347 = 137'd75557863725914323419136;
parameter VAR425 = 137'd151115727451828646838272;
parameter VAR292 = 137'd302231454903657293676544;
parameter VAR90 = 137'd604462909807314587353088;
parameter VAR223 = 137'd1208925819614629174706176;
parameter VAR339 = 137'd2417851639229258349412352;
parameter VAR386 = 137'd4835703278458516698824704;
parameter VAR357 = 137'd9671406556917033397649408;
parameter VAR127 = 137'd19342813113834066795298816;
parameter VAR179 = 137'd38685626227668133590597632;
parameter VAR62 = 137'd77371252455336267181195264;
parameter VAR395 = 137'd154742504910672534362390528;
parameter VAR47 = 137'd309485009821345068724781056;
parameter VAR284 = 137'd618970019642690137449562112;
parameter VAR190 = 137'd1237940039285380274899124224;
parameter VAR170 = 137'd2475880078570760549798248448;
parameter VAR320 = 137'd4951760157141521099596496896;
parameter VAR341 = 137'd9903520314283042199192993792;
parameter VAR102 = 137'd19807040628566084398385987584;
parameter VAR92 = 137'd39614081257132168796771975168;
parameter VAR412 = 137'd79228162514264337593543950336;
parameter VAR198 = 137'd158456325028528675187087900672;
parameter VAR300 = 137'd316912650057057350374175801344;
parameter VAR132 = 137'd633825300114114700748351602688;
parameter VAR485 = 137'd1267650600228229401496703205376;
parameter VAR159 = 137'd2535301200456458802993406410752;
parameter VAR76 = 137'd5070602400912917605986812821504;
parameter VAR219 = 137'd10141204801825835211973625643008;
parameter VAR70 = 137'd20282409603651670423947251286016;
parameter VAR471 = 137'd40564819207303340847894502572032;
parameter VAR44 = 137'd81129638414606681695789005144064;
parameter VAR213 = 137'd162259276829213363391578010288128;
parameter VAR317 = 137'd324518553658426726783156020576256;
parameter VAR449 = 137'd649037107316853453566312041152512;
parameter VAR138 = 137'd1298074214633706907132624082305024;
parameter VAR433 = 137'd2596148429267413814265248164610048;
parameter VAR33 = 137'd5192296858534827628530496329220096;
parameter VAR217 = 137'd10384593717069655257060992658440192;
parameter VAR27 = 137'd20769187434139310514121985316880384;
parameter VAR277 = 137'd41538374868278621028243970633760768;
parameter VAR358 = 137'd83076749736557242056487941267521536;
parameter VAR246 = 137'd166153499473114484112975882535043072;
parameter VAR450 = 137'd332306998946228968225951765070086144;
parameter VAR171 = 137'd664613997892457936451903530140172288;
parameter VAR31 = 137'd1329227995784915872903807060280344576;
parameter VAR85 = 137'd2658455991569831745807614120560689152;
parameter VAR134 = 137'd5316911983139663491615228241121378304;
parameter VAR250 = 137'd10633823966279326983230456482242756608;
parameter VAR488 = 137'd21267647932558653966460912964485513216;
parameter VAR71 = 137'd42535295865117307932921825928971026432;
parameter VAR196 = 137'd85070591730234615865843651857942052864;
parameter VAR435 = 137'd170141183460469231731687303715884105728;
parameter VAR105 = 137'd340282366920938463463374607431768211456;
parameter VAR99 = 137'd680564733841876926926749214863536422912;
parameter VAR328 = 137'd1361129467683753853853498429727072845824;
parameter VAR235 = 137'd2722258935367507707706996859454145691648;
parameter VAR446 = 137'd5444517870735015415413993718908291383296;
parameter VAR229 = 137'd10889035741470030830827987437816582766592;
parameter VAR45 = 137'd21778071482940061661655974875633165533184;
parameter VAR120 = 137'd43556142965880123323311949751266331066368;
parameter VAR158 = 137'd87112285931760246646623899502532662132736;
input VAR241;
input VAR143;
input VAR442;
output VAR207;
output VAR189;
output VAR175;
output [31:0] VAR88;
output VAR36;
output [3:0] VAR384;
output [31:0] VAR490;
input [31:0] VAR254;
output VAR136;
output VAR351;
output [31:0] VAR42;
output VAR115;
output [3:0] VAR89;
output [31:0] VAR79;
input [31:0] VAR157;
output VAR74;
output VAR406;
output [31:0] VAR299;
output VAR165;
output [3:0] VAR96;
output [31:0] VAR285;
input [31:0] VAR83;
output VAR271;
output VAR473;
reg VAR207;
reg VAR189;
reg VAR175;
reg VAR36;
reg VAR115;
reg VAR165;
reg[3:0] VAR96;
reg [136:0] VAR214;
wire VAR340;
reg [31:0] VAR106;
wire VAR248;
wire VAR129;
wire VAR38;
wire VAR32;
wire VAR97;
wire VAR37;
wire VAR476;
wire VAR371;
wire VAR344;
wire VAR154;
wire VAR290;
wire VAR366;
wire VAR460;
wire VAR188;
wire VAR470;
wire VAR18;
wire VAR231;
wire VAR151;
wire VAR41;
wire VAR296;
wire VAR456;
wire VAR29;
wire VAR398;
wire VAR60;
wire VAR192;
reg [31:0] VAR51;
wire [31:0] VAR26;
reg [31:0] VAR110;
wire VAR162;
wire VAR403;
wire VAR130;
wire VAR211;
wire VAR332;
wire VAR365;
wire VAR310;
wire VAR7;
wire VAR439;
wire VAR336;
wire VAR107;
wire VAR244;
wire VAR354;
wire VAR342;
wire VAR123;
wire VAR243;
wire VAR91;
wire VAR204;
wire VAR112;
wire VAR57;
wire VAR135;
wire VAR184;
wire VAR180;
wire VAR178;
wire VAR427;
wire [31:0] VAR117;
reg [31:0] VAR125;
wire VAR109;
wire signed [5:0] VAR330;
reg signed [5:0] VAR237;
wire VAR210;
wire [1:0] VAR133;
reg [1:0] VAR466;
wire signed [8:0] VAR2;
reg signed [8:0] VAR52;
wire VAR408;
wire [5:0] VAR390;
reg [5:0] VAR410;
wire [0:0] VAR298;
reg [0:0] VAR313;
wire [1:0] VAR126;
reg [1:0] VAR11;
reg [7:0] VAR326;
wire VAR343;
reg [7:0] VAR467;
reg [7:0] VAR377;
reg [7:0] VAR5;
reg [7:0] VAR359;
reg [7:0] VAR383;
reg [7:0] VAR441;
reg [7:0] VAR463;
reg [7:0] VAR368;
reg [7:0] VAR361;
reg [7:0] VAR278;
reg [7:0] VAR381;
reg [7:0] VAR458;
reg [7:0] VAR256;
reg [7:0] VAR209;
reg [7:0] VAR43;
reg [7:0] VAR160;
reg [7:0] VAR183;
reg [7:0] VAR279;
reg [7:0] VAR385;
reg [7:0] VAR468;
reg [7:0] VAR309;
reg [7:0] VAR20;
reg [7:0] VAR216;
reg [7:0] VAR150;
wire signed [6:0] VAR69;
reg signed [6:0] VAR212;
wire [8:0] VAR311;
reg [8:0] VAR329;
wire VAR373;
wire [5:0] VAR226;
reg [5:0] VAR375;
wire [1:0] VAR275;
reg [1:0] VAR176;
wire [8:0] VAR356;
reg [8:0] VAR312;
wire [0:0] VAR197;
wire [8:0] VAR249;
reg [8:0] VAR164;
wire [8:0] VAR281;
reg [8:0] VAR75;
wire [8:0] VAR86;
reg [8:0] VAR260;
wire VAR428;
reg [7:0] VAR263;
reg [7:0] VAR240;
reg [7:0] VAR324;
reg [7:0] VAR6;
reg [4:0] VAR104;
wire [2:0] VAR66;
reg [2:0] VAR58;
wire [1:0] VAR46;
reg [1:0] VAR289;
reg [31:0] VAR409;
wire [8:0] VAR461;
reg [8:0] VAR273;
wire [8:0] VAR108;
reg [8:0] VAR242;
wire [8:0] VAR486;
reg [8:0] VAR264;
wire [8:0] VAR94;
reg [8:0] VAR233;
wire [8:0] VAR432;
reg [8:0] VAR360;
wire [8:0] VAR316;
reg [8:0] VAR291;
wire [8:0] VAR447;
reg [8:0] VAR286;
wire [8:0] VAR54;
reg [8:0] VAR489;
wire [8:0] VAR475;
reg [8:0] VAR124;
reg [1:0] VAR101;
reg [1:0] VAR24;
wire [0:0] VAR50;
reg [1:0] VAR122;
wire [0:0] VAR380;
reg [1:0] VAR144;
wire VAR457;
wire signed [63:0] VAR153;
wire signed [63:0] VAR98;
wire signed [63:0] VAR77;
wire signed [63:0] VAR224;
wire signed [63:0] VAR333;
wire signed [63:0] VAR141;
wire signed [63:0] VAR166;
wire signed [63:0] VAR431;
wire signed [63:0] VAR338;
wire signed [63:0] VAR444;
wire signed [63:0] VAR93;
wire signed [63:0] VAR315;
wire signed [63:0] VAR335;
wire signed [63:0] VAR440;
wire signed [63:0] VAR1;
wire signed [63:0] VAR372;
wire signed [63:0] VAR287;
wire signed [63:0] VAR48;
wire signed [63:0] VAR469;
wire signed [63:0] VAR181;
wire signed [63:0] VAR145;
wire signed [63:0] VAR14;
wire signed [63:0] VAR422;
wire signed [63:0] VAR78;
wire signed [63:0] VAR394;
wire [63:0] VAR247;
wire [63:0] VAR61;
wire [63:0] VAR382;
wire [63:0] VAR392;
wire [63:0] VAR451;
wire [63:0] VAR257;
wire [63:0] VAR152;
wire [63:0] VAR454;
wire [63:0] VAR194;
wire [63:0] VAR182;
wire [63:0] VAR10;
wire [63:0] VAR155;
wire [63:0] VAR272;
wire [63:0] VAR142;
wire [63:0] VAR334;
wire [63:0] VAR185;
wire [63:0] VAR327;
wire [63:0] VAR191;
wire [63:0] VAR12;
wire [63:0] VAR84;
wire [63:0] VAR465;
wire [63:0] VAR387;
wire [63:0] VAR283;
wire [63:0] VAR199;
wire [63:0] VAR174;
wire [63:0] VAR15;
reg [31:0] VAR348;
reg [31:0] VAR443;
wire VAR168;
wire [31:0] VAR4;
reg [31:0] VAR391;
wire VAR321;
wire VAR346;
wire VAR418;
wire VAR484;
wire VAR424;
wire VAR103;
wire VAR274;
wire VAR301;
wire VAR483;
wire VAR370;
wire VAR430;
wire VAR49;
wire VAR3;
wire VAR297;
wire VAR167;
wire VAR288;
wire VAR413;
wire VAR307;
wire VAR34;
wire VAR55;
wire VAR389;
wire VAR294;
wire VAR270;
wire VAR399;
wire VAR415;
wire VAR100;
wire [3:0] VAR137;
wire [4:0] VAR364;
wire [4:0] VAR222;
wire [4:0] VAR448;
wire [4:0] VAR21;
wire [5:0] VAR276;
wire [5:0] VAR259;
wire [8:0] VAR355;
wire [8:0] VAR35;
wire [8:0] VAR187;
wire [8:0] VAR25;
wire [8:0] VAR305;
wire [8:0] VAR453;
wire [8:0] VAR352;
wire [8:0] VAR405;
wire [8:0] VAR455;
wire [8:0] VAR236;
wire [8:0] VAR227;
wire [8:0] VAR253;
wire [8:0] VAR245;
wire [8:0] VAR87;
wire [8:0] VAR252;
wire [8:0] VAR464;
wire [8:0] VAR95;
wire [8:0] VAR67;
wire [8:0] VAR172;
wire [8:0] VAR118;
wire [8:0] VAR411;
wire [8:0] VAR349;
wire [8:0] VAR421;
wire [8:0] VAR72;
wire [6:0] VAR396;
wire [6:0] VAR293;
wire [5:0] VAR111;
wire [8:0] VAR337;
wire signed [8:0] VAR139;
wire [5:0] VAR169;
wire [5:0] VAR445;
wire [5:0] VAR239;
wire [6:0] VAR369;
wire [6:0] VAR478;
wire [5:0] VAR218;
wire [8:0] VAR414;
wire signed [8:0] VAR73;
wire [2:0] VAR401;
wire [2:0] VAR116;
wire [6:0] VAR314;
wire [6:0] VAR363;
wire [5:0] VAR119;
wire [8:0] VAR208;
wire signed [8:0] VAR186;
wire [2:0] VAR9;
wire [5:0] VAR206;
wire [5:0] VAR228;
wire [8:0] VAR128;
wire [8:0] VAR423;
wire [2:0] VAR419;
wire [6:0] VAR82;
wire [6:0] VAR459;
wire [5:0] VAR163;
wire [8:0] VAR481;
wire signed [8:0] VAR438;
wire [8:0] VAR255;
wire [8:0] VAR64;
wire [8:0] VAR322;
wire [8:0] VAR282;
wire [8:0] VAR400;
wire [8:0] VAR302;
wire [5:0] VAR417;
wire [5:0] VAR353;
wire [8:0] VAR487;
wire [2:0] VAR437;
wire [8:0] VAR65;
wire [2:0] VAR367;
wire [8:0] VAR407;
wire [2:0] VAR266;
wire [8:0] VAR234;
wire [8:0] VAR378;
wire [8:0] VAR173;
wire [8:0] VAR491;
wire [8:0] VAR429;
wire [8:0] VAR80;
wire [8:0] VAR262;
wire [8:0] VAR200;
wire [8:0] VAR306;
wire [8:0] VAR147;
wire [8:0] VAR16;
wire [8:0] VAR258;
wire signed [4:0] VAR202;
wire [1:0] VAR19;
wire [5:0] VAR225;
reg [136:0] VAR30; | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_047.v | 1,538 | module MODULE2 (
VAR6,
VAR7
);
input [31:0] VAR6;
output [31:0]
VAR7;
wire [31:0]
VAR4,
VAR3,
VAR14,
VAR11,
VAR13,
VAR9,
VAR12,
VAR1,
VAR8;
assign VAR4 = VAR6;
assign VAR3 = VAR4 << 7;
assign VAR14 = VAR4 + VAR3;
assign VAR11 = VAR4 << 14;
assign VAR13 = VAR14 + VAR11;
assign VAR12 = VAR13 + VAR9;
assign VAR8 = VAR12 + VAR1;
assign VAR9 = VAR14 << 4;
assign VAR1 = VAR14 << 2;
assign VAR7 = VAR8;
endmodule
module MODULE1(
VAR6,
VAR7,
clk
);
input [31:0] VAR6;
output [31:0] VAR7;
reg [31:0] VAR7;
input clk;
reg [31:0] VAR2;
wire [30:0] VAR5;
always @(posedge clk) begin
VAR2 <= VAR6;
VAR7 <= VAR5;
end
MODULE2 MODULE1(
.VAR6(VAR2),
.VAR7(VAR5)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn.blackbox.v | 1,451 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR7 ,
VAR10 ,
VAR9 ,
VAR2
);
output VAR8 ;
output VAR3 ;
input VAR7 ;
input VAR10 ;
input VAR9 ;
input VAR2;
supply1 VAR1;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0p/sky130_fd_sc_lp__iso0p.behavioral.v | 1,360 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR7
);
output VAR1 ;
input VAR9 ;
input VAR7;
supply1 VAR3;
supply0 VAR4 ;
supply1 VAR6 ;
supply0 VAR5 ;
wire VAR8;
not VAR2 (VAR8, VAR7 );
and VAR10 (VAR1 , VAR9, VAR8 );
endmodule | apache-2.0 |
CospanDesign/sdio-device | rtl/sdio_device_stack.v | 25,637 | module MODULE1 (
input VAR147,
input VAR28,
input rst,
output VAR45,
output [7:0] VAR195, input [7:0] VAR227, output [2:0] VAR268,
input [7:0] VAR200,
input [7:0] VAR95,
output VAR89,
output [3:0] VAR275,
output [15:0] VAR153,
output VAR246,
output [3:0] VAR126,
output [15:0] VAR60,
output VAR107,
output [3:0] VAR291,
output [15:0] VAR8,
output VAR198,
output [3:0] VAR180,
output [15:0] VAR21,
output VAR66,
output [3:0] VAR163,
output [15:0] VAR15,
output VAR136,
output [3:0] VAR218,
output [15:0] VAR190,
output VAR156,
output [3:0] VAR14,
output [15:0] VAR165,
output VAR159,
output [7:0] VAR191,
input VAR46,
input [7:0] VAR219,
output VAR12,
input VAR96,
output VAR155,
output VAR5,
output [7:0] VAR6,
input VAR117,
input [7:0] VAR211,
output VAR235,
input VAR32,
output VAR39,
output VAR186,
output [7:0] VAR204,
input VAR179,
input [7:0] VAR171,
output VAR279,
input VAR217,
output VAR143,
output VAR225,
output [7:0] VAR59,
input VAR31,
input [7:0] VAR287,
output VAR113,
input VAR38,
output VAR141,
output VAR109,
output [7:0] VAR83,
input VAR207,
input [7:0] VAR269,
output VAR213,
input VAR119,
output VAR220,
output VAR271,
output [7:0] VAR297,
input VAR289,
input [7:0] VAR35,
output VAR68,
input VAR288,
output VAR82,
output VAR253,
output [7:0] VAR216,
input VAR263,
input [7:0] VAR48,
output VAR110,
input VAR266,
output VAR248,
output VAR121,
output [7:0] VAR10,
input VAR97,
input [7:0] VAR77,
output VAR65,
input VAR283,
output VAR81,
output VAR188,
output VAR120,
output [3:0] VAR49,
output VAR194,
output VAR261,
output [17:0] VAR259,
output [12:0] VAR80,
input [7:0] VAR300,
input VAR56,
output VAR4,
input VAR226,
output VAR201,
output VAR244,
output [7:0] VAR212,
input [7:0] VAR203
);
wire [3:0] VAR277;
wire VAR13;
wire VAR234;
wire VAR299;
wire [3:0] VAR169;
wire [3:0] VAR281;
wire VAR22;
wire VAR57;
wire VAR152;
wire VAR224;
wire VAR182;
wire VAR75;
wire VAR223;
wire [5:0] VAR257;
wire [31:0] VAR262;
wire [17:0] VAR24;
wire [12:0] VAR99;
wire [39:0] VAR239;
wire [7:0] VAR245;
wire VAR238;
wire VAR215;
wire interrupt;
wire VAR112;
wire VAR85;
wire VAR243;
wire VAR17;
wire VAR183;
wire VAR145;
wire VAR50;
wire [15:0] VAR72;
wire VAR29;
wire VAR142;
wire VAR148;
wire VAR100;
wire VAR106;
wire VAR301;
wire VAR233;
wire VAR104;
wire VAR115;
wire VAR87;
wire VAR151;
wire VAR135;
wire VAR252;
wire [7:0] VAR227;
wire [7:0] VAR69;
wire [7:0] VAR37;
wire VAR247;
wire VAR67;
wire [7:0] VAR278;
wire [7:0] VAR170;
wire VAR108;
wire VAR16;
wire [17:0] VAR192;
wire VAR230;
wire VAR177;
wire VAR125;
wire VAR134;
wire VAR168;
wire [7:0] VAR70;
wire VAR286;
wire [7:0] VAR2;
wire VAR174;
wire VAR88;
wire VAR129;
wire [7:0] VAR76;
wire VAR158;
wire [7:0] VAR101;
wire VAR92;
wire VAR209;
wire VAR181;
wire VAR86;
VAR127 VAR20 (
.VAR147 (VAR147 ),
.rst (rst ),
.VAR187 (VAR187 ),
.VAR3 (VAR300 ),
.VAR265 (VAR69 ),
.VAR254 (interrupt ),
.VAR45 (VAR45 ),
.VAR49 (VAR49 ),
.VAR261 (VAR261 ),
.VAR120 (VAR120 ),
.VAR188 (VAR188 ),
.VAR194 (VAR194 ),
.VAR259 (VAR24 ),
.VAR80 (VAR99 ),
.VAR160 (VAR85 ),
.VAR25 (VAR230 ),
.VAR175 (VAR177 ),
.VAR157 (VAR278 ),
.VAR274 (VAR170 ),
.VAR167 (VAR243 ),
.VAR43 (VAR182 ),
.VAR154 (VAR75 ),
.VAR293 (VAR260 ),
.VAR62 (VAR257 ),
.VAR42 (VAR262 ),
.VAR189 (VAR112 ),
.VAR208 (VAR239 ),
.VAR290 (VAR245 ),
.VAR267 (VAR9 ),
.VAR164 (VAR238 ),
.VAR73 (VAR215 )
);
VAR26 VAR18(
.clk (VAR147 ),
.rst (rst ),
.VAR222 (VAR247 ),
.VAR140 (VAR67 ),
.VAR302 (VAR188 ),
.VAR264 (VAR120 ),
.VAR52 (VAR99 ),
.VAR124 (VAR80 ),
.VAR131 (VAR261 ),
.VAR184 (VAR24 ),
.VAR93 (VAR259 ),
.VAR53 (VAR230 ),
.VAR284 (VAR177 ),
.VAR11 (VAR85 ),
.VAR150 (VAR45 ),
.VAR229 (VAR49 ),
.VAR298 (VAR278 ),
.VAR36 (VAR170 ),
.VAR44 (VAR168 ),
.VAR139 (VAR70 ),
.VAR282 (VAR286 ),
.VAR138 (VAR2 ),
.VAR242 (VAR174 ),
.VAR258 (VAR88 ),
.VAR41 (VAR125 ),
.VAR98 (VAR134 ),
.VAR256 (VAR129 ),
.VAR172 (VAR76 ),
.VAR241 (VAR158 ),
.VAR276 (VAR101 ),
.VAR205 (VAR92 ),
.VAR272 (VAR209 ),
.VAR178 (VAR181 ),
.VAR196 (VAR72 ),
.VAR159 (VAR159 ),
.VAR191 (VAR191 ),
.VAR46 (VAR46 ),
.VAR219 (VAR219 ),
.VAR12 (VAR12 ),
.VAR96 (VAR96 ),
.VAR155 (VAR155 ),
.VAR133 (VAR153 ),
.VAR5 (VAR5 ),
.VAR6 (VAR6 ),
.VAR117 (VAR117 ),
.VAR211 (VAR211 ),
.VAR235 (VAR235 ),
.VAR32 (VAR32 ),
.VAR39 (VAR39 ),
.VAR273 (VAR60 ),
.VAR186 (VAR186 ),
.VAR204 (VAR204 ),
.VAR179 (VAR179 ),
.VAR171 (VAR171 ),
.VAR279 (VAR279 ),
.VAR217 (VAR217 ),
.VAR143 (VAR143 ),
.VAR237 (VAR8 ),
.VAR225 (VAR225 ),
.VAR59 (VAR59 ),
.VAR31 (VAR31 ),
.VAR287 (VAR287 ),
.VAR113 (VAR113 ),
.VAR38 (VAR38 ),
.VAR141 (VAR141 ),
.VAR240 (VAR21 ),
.VAR109 (VAR109 ),
.VAR83 (VAR83 ),
.VAR207 (VAR207 ),
.VAR269 (VAR269 ),
.VAR213 (VAR213 ),
.VAR119 (VAR119 ),
.VAR220 (VAR220 ),
.VAR292 (VAR15 ),
.VAR271 (VAR271 ),
.VAR297 (VAR297 ),
.VAR289 (VAR289 ),
.VAR35 (VAR35 ),
.VAR68 (VAR68 ),
.VAR288 (VAR288 ),
.VAR82 (VAR82 ),
.VAR118 (VAR190 ),
.VAR253 (VAR253 ),
.VAR216 (VAR216 ),
.VAR263 (VAR263 ),
.VAR48 (VAR48 ),
.VAR110 (VAR110 ),
.VAR266 (VAR266 ),
.VAR248 (VAR248 ),
.VAR51 (VAR165 ),
.VAR121 (VAR121 ),
.VAR10 (VAR10 ),
.VAR97 (VAR97 ),
.VAR77 (VAR77 ),
.VAR65 (VAR65 ),
.VAR283 (VAR283 ),
.VAR81 (VAR81 ),
.VAR294 (16'h0000 )
);
VAR7 VAR255 (
.clk (VAR147 ),
.rst (rst ),
.VAR137 (VAR188 ),
.VAR236 (VAR259 ),
.VAR58 (VAR261 ),
.VAR231 (VAR80 ),
.VAR53 (VAR181 ),
.VAR284 (VAR86 ),
.VAR102 (VAR92 ),
.VAR33 (VAR129 ),
.VAR30 (VAR76 ),
.VAR1 (VAR209 ),
.VAR221 (VAR101 ),
.VAR162 (VAR158 ),
.VAR89 (VAR89 ),
.VAR275 (VAR275 ),
.VAR153 (VAR153 ),
.VAR246 (VAR246 ),
.VAR126 (VAR126 ),
.VAR60 (VAR60 ),
.VAR107 (VAR107 ),
.VAR291 (VAR291 ),
.VAR8 (VAR8 ),
.VAR198 (VAR198 ),
.VAR180 (VAR180 ),
.VAR21 (VAR21 ),
.VAR66 (VAR66 ),
.VAR163 (VAR163 ),
.VAR15 (VAR15 ),
.VAR136 (VAR136 ),
.VAR218 (VAR218 ),
.VAR190 (VAR190 ),
.VAR156 (VAR156 ),
.VAR14 (VAR14 ),
.VAR165 (VAR165 ),
.VAR195 (VAR195 ),
.VAR227 (VAR227 ),
.VAR146 (VAR69 ),
.VAR166 (VAR37 ),
.VAR95 (VAR95 ),
.VAR268 (VAR268 ),
.VAR200 (VAR200 ),
.VAR199 (VAR247 ),
.VAR132 (VAR183 ),
.VAR197 (VAR145 ),
.VAR63 (VAR50 ),
.VAR23 (VAR17 ),
.VAR270 (VAR67 ),
.VAR105 (VAR72 ),
.VAR128 (VAR29 ),
.VAR111 (VAR142 ),
.VAR130 (VAR148 ),
.VAR250 (VAR100 ),
.VAR90 (VAR106 ),
.VAR78 (VAR301 ),
.VAR116 (VAR233 ),
.VAR173 (VAR104 ),
.VAR285 (VAR115 ),
.VAR149 (VAR87 ),
.VAR202 (VAR151 ),
.VAR103 (VAR135 ),
.VAR91 (VAR252 )
);
VAR161 VAR71(
.rst (rst ),
.VAR79 (VAR56 ),
.VAR54 (VAR57 ),
.VAR228 (VAR152 ),
.VAR64 (VAR224 ),
.VAR296 (VAR182 ),
.VAR251 (VAR75 ),
.VAR94 (VAR260 ),
.VAR122 (VAR257 ),
.VAR206 (VAR262 ),
.VAR55 (VAR9 ),
.VAR84 (VAR239 ),
.VAR144 (VAR245 ),
.VAR27 (VAR238 ),
.VAR19 (VAR215 ),
.VAR300 (interrupt ),
.VAR231 (VAR80 ),
.VAR185 (VAR125 ),
.VAR123 (VAR134 ),
.VAR137 (VAR188 ),
.VAR280 (VAR168 ),
.VAR210 (VAR70 ),
.VAR34 (VAR286 ),
.VAR47 (VAR2 ),
.VAR114 (VAR174 ),
.VAR295 (VAR88 ),
.VAR249 (VAR147 ),
.VAR214 (VAR28 ),
.VAR74 (VAR4 ),
.VAR40 (VAR226 ),
.VAR61 (VAR201 ),
.VAR232 (VAR244 ),
.VAR176 (VAR203 ),
.VAR193 (VAR212 )
);
assign VAR37 = VAR300;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.behavioral.v | 1,135 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Obijuan/FPGA-peripherals | servos/osc/genrom.v | 1,538 | module MODULE1 #( parameter VAR4 = 6, parameter VAR8 = 8)
( input clk, input wire [VAR4-1: 0] addr, output reg [VAR8-1: 0] VAR3);
parameter VAR6 = "VAR1.VAR5";
localparam VAR2 = 2 ** VAR4;
reg [VAR8-1: 0] VAR7 [0: VAR2-1];
always @(posedge clk) begin
VAR3 <= VAR7[addr];
end | gpl-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_phy_wrcal.v | 54,326 | module MODULE1 #
(
parameter VAR210 = 100, parameter VAR189 = 2, parameter VAR156 = 2500,
parameter VAR13 = 64, parameter VAR158 = 3, parameter VAR58 = 8, parameter VAR9 = 8, parameter VAR130 = "VAR214", parameter VAR115 = "VAR192" )
(
input clk,
input rst,
input VAR237,
input VAR40,
input VAR60,
input VAR193,
input VAR225,
output VAR174,
output VAR183,
output reg VAR86,
output reg VAR44,
output reg VAR59,
output reg VAR63,
output reg VAR10,
output reg VAR168,
input VAR37,
input [2*VAR189*VAR13-1:0] VAR75,
input [3*VAR58-1:0] VAR71,
input [6*VAR58-1:0] VAR204,
input VAR206,
output reg VAR107,
output reg VAR87,
output reg VAR211,
output reg VAR95,
output reg VAR134, output reg [VAR158:0] VAR157,
output VAR221,
output [6*VAR58-1:0] VAR179,
output [3*VAR58-1:0] VAR216,
output [99:0] VAR65
);
localparam VAR93 = 1;
localparam VAR201 = 2;
localparam VAR25 = 12;
localparam VAR17 = (VAR156/VAR189 <= 2500) ? 3 : 6;
localparam VAR108 = (VAR156/VAR189 <= 2500) ? 22 : 44;
localparam VAR119 = 4'h0;
localparam VAR96 = 4'h1;
localparam VAR127 = 4'h2;
localparam VAR152 = 4'h3;
localparam VAR89 = 4'h4;
localparam VAR167 = 4'h5;
localparam VAR105 = 4'h6;
localparam VAR171 = 4'h7;
localparam VAR41 = 4'h8;
integer VAR23,VAR188,VAR110,VAR184,VAR143,VAR68,VAR30,VAR203;
reg [2:0] VAR161 [0:VAR58-1];
reg [3*VAR58-1:0] VAR103;
reg [5:0] VAR84 [0:VAR58-1];
reg [6*VAR58-1:0] VAR208;
reg [VAR158:0] VAR70;
reg [4:0] VAR113;
reg [3:0] VAR118;
reg VAR73;
reg VAR35;
reg VAR212;
reg [3:0] VAR34;
reg [3:0] VAR194;
reg [2:0] VAR19 [0:VAR58-1];
reg [5:0] VAR4 [0:VAR58-1];
reg VAR54;
reg VAR99;
reg VAR43;
reg VAR50;
reg VAR230;
reg [VAR9-1:0] VAR151;
reg [VAR9-1:0] VAR101;
reg [VAR9-1:0] VAR85;
reg [VAR9-1:0] VAR205;
reg [VAR9-1:0] VAR98;
reg [VAR9-1:0] VAR135;
reg [VAR9-1:0] VAR64;
reg [VAR9-1:0] VAR233;
reg VAR16;
reg VAR131;
reg VAR133;
reg VAR91;
reg VAR218;
wire [VAR93-1:0] VAR128 [3:0];
wire [VAR93-1:0] VAR21 [3:0];
wire [VAR93-1:0] VAR111 [3:0];
wire [VAR93-1:0] VAR164 [3:0];
wire [VAR93-1:0] VAR24 [3:0];
wire [VAR93-1:0] VAR136 [3:0];
wire [VAR93-1:0] VAR148 [3:0];
wire [VAR93-1:0] VAR223 [3:0];
wire [VAR93-1:0] VAR144 [3:0];
wire [VAR93-1:0] VAR220 [3:0];
wire [VAR93-1:0] VAR12 [3:0];
wire [VAR93-1:0] VAR20 [3:0];
wire [VAR93-1:0] VAR90 [3:0];
wire [VAR93-1:0] VAR147 [3:0];
wire [VAR93-1:0] VAR173 [3:0];
wire [VAR93-1:0] VAR198 [3:0];
reg [VAR9-1:0] VAR76;
reg VAR182;
reg [VAR9-1:0] VAR232;
reg VAR114;
reg [VAR9-1:0] VAR94;
reg VAR185;
reg [VAR9-1:0] VAR29;
reg VAR106;
reg [VAR9-1:0] VAR137;
reg VAR3;
reg [VAR9-1:0] VAR213;
reg VAR231;
reg [VAR9-1:0] VAR55;
reg VAR42;
reg [VAR9-1:0] VAR165;
reg VAR57;
reg [VAR9-1:0] VAR222;
reg [VAR9-1:0] VAR52;
reg [VAR9-1:0] VAR82;
reg [VAR9-1:0] VAR141;
reg [VAR9-1:0] VAR18;
reg [VAR9-1:0] VAR176;
reg [VAR9-1:0] VAR178;
reg [VAR9-1:0] VAR56;
reg VAR123;
reg VAR170;
reg VAR160;
reg VAR177;
reg VAR129;
reg VAR69;
reg VAR180;
reg VAR219;
reg VAR139;
reg VAR92;
reg [VAR9-1:0] VAR228;
reg VAR33;
reg [VAR9-1:0] VAR196;
reg VAR163;
reg [VAR9-1:0] VAR104;
reg VAR238;
reg [VAR9-1:0] VAR227;
reg VAR66;
reg [VAR9-1:0] VAR145;
reg VAR200;
reg [VAR9-1:0] VAR120;
reg VAR81;
reg [VAR9-1:0] VAR74;
reg VAR175;
reg [VAR9-1:0] VAR22;
reg VAR109;
reg VAR122;
reg [VAR9-1:0] VAR207;
reg VAR155;
reg [VAR9-1:0] VAR191;
reg VAR154;
reg [VAR9-1:0] VAR6;
reg VAR88;
reg [VAR9-1:0] VAR138;
reg VAR102;
reg [VAR9-1:0] VAR100;
reg VAR140;
reg [VAR9-1:0] VAR146;
reg VAR125;
reg [VAR9-1:0] VAR112;
reg VAR79;
reg [VAR9-1:0] VAR186;
reg VAR28;
wire [VAR93-1:0] VAR116 [3:0];
wire [VAR93-1:0] VAR36 [3:0];
wire [VAR93-1:0] VAR11 [3:0];
wire [VAR93-1:0] VAR39 [3:0];
wire [VAR93-1:0] VAR51 [3:0];
wire [VAR93-1:0] VAR217 [3:0];
wire [VAR93-1:0] VAR190 [3:0];
wire [VAR93-1:0] VAR197 [3:0];
wire [VAR93-1:0] VAR32 [3:0];
wire [VAR93-1:0] VAR172 [3:0];
wire [VAR93-1:0] VAR236 [3:0];
wire [VAR93-1:0] VAR187 [3:0];
wire [VAR93-1:0] VAR226 [3:0];
wire [VAR93-1:0] VAR97 [3:0];
wire [VAR93-1:0] VAR132 [3:0];
wire [VAR93-1:0] VAR169 [3:0];
wire [VAR13-1:0] VAR121;
wire [VAR13-1:0] VAR142;
wire [VAR13-1:0] VAR126;
wire [VAR13-1:0] VAR45;
wire [VAR13-1:0] VAR72;
wire [VAR13-1:0] VAR8;
wire [VAR13-1:0] VAR235;
wire [VAR13-1:0] VAR153;
reg [VAR158:0] VAR2;
reg VAR27;
reg VAR48;
reg VAR150;
reg VAR159;
reg VAR5;
reg VAR199;
reg VAR14;
reg [VAR93-1:0] VAR15 [VAR9-1:0];
reg [VAR93-1:0] VAR83 [VAR9-1:0];
reg [VAR93-1:0] VAR67 [VAR9-1:0];
reg [VAR93-1:0] VAR162 [VAR9-1:0];
reg [VAR93-1:0] VAR7 [VAR9-1:0];
reg [VAR93-1:0] VAR47 [VAR9-1:0];
reg [VAR93-1:0] VAR224 [VAR9-1:0];
reg [VAR93-1:0] VAR166 [VAR9-1:0];
reg VAR46;
reg VAR234;
reg VAR195;
reg VAR31;
reg VAR202;
reg VAR209;
always @ begin
for (VAR143 = 0; VAR143 < VAR58; VAR143 = VAR143 + 1) begin
VAR19[VAR143] = VAR71[3*VAR143+:3];
VAR4[VAR143] = VAR204[6*VAR143+:6];
end
end
always @(posedge clk) begin
if (rst) begin
for (VAR68 = 0; VAR68 < VAR58; VAR68 = VAR68 + 1) begin
end
end else if (VAR73 && ~VAR35) begin
for (VAR30 = 0; VAR30 < VAR58; VAR30 = VAR30 + 1) begin
end
end
end
always @(posedge clk) begin
end
generate
genvar VAR124;
if (VAR189 == 4) begin: VAR62
for (VAR124 = 0; VAR124 < VAR9; VAR124 = VAR124 + 1) begin: VAR49
always @(posedge clk) begin
end
end
end else if (VAR189 == 2) begin: VAR80
for (VAR124 = 0; VAR124 < VAR9; VAR124 = VAR124 + 1) begin: VAR49
always @(posedge clk) begin
end
end
end
endgenerate
always @(posedge clk)
if (rst)
end
else
generate
genvar VAR215;
if (VAR189 == 4) begin: VAR53
for (VAR215 = 0; VAR215 < VAR9; VAR215 = VAR215 + 1) begin: VAR149
always @(posedge clk) begin
end
end
end else if (VAR189 == 2) begin: VAR77
for (VAR215 = 0; VAR215 < VAR9; VAR215 = VAR215 + 1) begin: VAR149
always @(posedge clk) begin
end
end
end
endgenerate
always @(posedge clk) begin
end
generate
if (VAR189 == 4) begin: VAR117
assign VAR116[3] = 1'b1;
assign VAR128[3] = 1'b0;
assign VAR36[3] = 1'b1;
assign VAR21[3] = 1'b0;
assign VAR11[3] = 1'b0;
assign VAR111[3] = 1'b1;
assign VAR39[3] = 1'b1;
assign VAR164[3] = 1'b0;
assign VAR116[2] = 1'b1;
assign VAR128[2] = 1'b0;
assign VAR36[2] = 1'b0;
assign VAR21[2] = 1'b1;
assign VAR11[2] = 1'b1;
assign VAR111[2] = 1'b0;
assign VAR39[2] = 1'b0;
assign VAR164[2] = 1'b1;
assign VAR116[1] = 1'b1;
assign VAR128[1] = 1'b0;
assign VAR36[1] = 1'b1;
assign VAR21[1] = 1'b0;
assign VAR11[1] = 1'b0;
assign VAR111[1] = 1'b1;
assign VAR39[1] = 1'b0;
assign VAR164[1] = 1'b1;
assign VAR116[0] = 1'b1;
assign VAR128[0] = 1'b0;
assign VAR36[0] = 1'b0;
assign VAR21[0] = 1'b1;
assign VAR11[0] = 1'b1;
assign VAR111[0] = 1'b0;
assign VAR39[0] = 1'b1;
assign VAR164[0] = 1'b0;
assign VAR32[3] = 1'b1;
assign VAR144[3] = 1'b0;
assign VAR172[3] = 1'b1;
assign VAR220[3] = 1'b0;
assign VAR236[3] = 1'b0;
assign VAR12[3] = 1'b1;
assign VAR187[3] = 1'b1;
assign VAR20[3] = 1'b1;
assign VAR32[2] = 1'b0;
assign VAR144[2] = 1'b0;
assign VAR172[2] = 1'b1;
assign VAR220[2] = 1'b1;
assign VAR236[2] = 1'b1;
assign VAR12[2] = 1'b1;
assign VAR187[2] = 1'b1;
assign VAR20[2] = 1'b0;
assign VAR32[1] = 1'b1;
assign VAR144[1] = 1'b0;
assign VAR172[1] = 1'b1;
assign VAR220[1] = 1'b0;
assign VAR236[1] = 1'b0;
assign VAR12[1] = 1'b1;
assign VAR187[1] = 1'b0;
assign VAR20[1] = 1'b0;
assign VAR32[0] = 1'b1;
assign VAR144[0] = 1'b1;
assign VAR172[0] = 1'b0;
assign VAR220[0] = 1'b0;
assign VAR236[0] = 1'b0;
assign VAR12[0] = 1'b0;
assign VAR187[0] = 1'b1;
assign VAR20[0] = 1'b0;
end else if (VAR189 == 2) begin: VAR38
assign VAR51[3] = 1'b1;
assign VAR24[3] = 1'b0;
assign VAR217[3] = 1'b1;
assign VAR136[3] = 1'b0;
assign VAR51[2] = 1'b1;
assign VAR24[2] = 1'b0;
assign VAR217[2] = 1'b0;
assign VAR136[2] = 1'b1;
assign VAR51[1] = 1'b1;
assign VAR24[1] = 1'b0;
assign VAR217[1] = 1'b1;
assign VAR136[1] = 1'b0;
assign VAR51[0] = 1'b1;
assign VAR24[0] = 1'b0;
assign VAR217[0] = 1'b0;
assign VAR136[0] = 1'b1;
assign VAR190[3] = 1'b0;
assign VAR148[3] = 1'b1;
assign VAR197[3] = 1'b1;
assign VAR223[3] = 1'b0;
assign VAR190[2] = 1'b1;
assign VAR148[2] = 1'b0;
assign VAR197[2] = 1'b0;
assign VAR223[2] = 1'b1;
assign VAR190[1] = 1'b0;
assign VAR148[1] = 1'b1;
assign VAR197[1] = 1'b0;
assign VAR223[1] = 1'b1;
assign VAR190[0] = 1'b1;
assign VAR148[0] = 1'b0;
assign VAR197[0] = 1'b1;
assign VAR223[0] = 1'b0;
assign VAR226[3] = 2'b1;
assign VAR90[3] = 2'b0;
assign VAR97[3] = 2'b0;
assign VAR147[3] = 2'b1;
assign VAR226[2] = 2'b0;
assign VAR90[2] = 2'b1;
assign VAR97[2] = 2'b1;
assign VAR147[2] = 2'b0;
assign VAR226[1] = 2'b1;
assign VAR90[1] = 2'b0;
assign VAR97[1] = 2'b0;
assign VAR147[1] = 2'b1;
assign VAR226[0] = 2'b0;
assign VAR90[0] = 2'b1;
assign VAR97[0] = 2'b1;
assign VAR147[0] = 2'b0;
assign VAR132[3] = 2'b1;
assign VAR173[3] = 2'b0;
assign VAR169[3] = 2'b1;
assign VAR198[3] = 2'b0;
assign VAR132[2] = 2'b0;
assign VAR173[2] = 2'b1;
assign VAR169[2] = 2'b0;
assign VAR198[2] = 2'b0;
assign VAR132[1] = 2'b0;
assign VAR173[1] = 2'b1;
assign VAR169[1] = 2'b1;
assign VAR198[1] = 2'b0;
assign VAR132[0] = 2'b1;
assign VAR173[0] = 2'b0;
assign VAR169[0] = 2'b1;
assign VAR198[0] = 2'b1;
end
endgenerate
generate
genvar VAR78;
if (VAR189 == 4) begin: VAR26
for (VAR78 = 0; VAR78 < VAR9; VAR78 = VAR78 + 1) begin: VAR61
always @(posedge clk) begin
if (VAR67[VAR78] == VAR116[VAR78%4])
end
else
if (VAR15[VAR78] == VAR128[VAR78%4])
end
else
if (VAR162[VAR78] == VAR36[VAR78%4])
end
else
if (VAR83[VAR78] == VAR21[VAR78%4])
end
else
if (VAR224[VAR78] == VAR11[VAR78%4])
end
else
if (VAR7[VAR78] == VAR111[VAR78%4])
end
else
if (VAR166[VAR78] == VAR39[VAR78%4])
else
if (VAR47[VAR78] == VAR164[VAR78%4])
else
end
always @(posedge clk) begin
if (VAR67[VAR78] == VAR36[VAR78%4])
end
else
if (VAR15[VAR78] == VAR21[VAR78%4])
else
if (VAR162[VAR78] == VAR11[VAR78%4])
else
if (VAR83[VAR78] == VAR111[VAR78%4])
else
if (VAR224[VAR78] == VAR39[VAR78%4])
else
if (VAR7[VAR78] == VAR164[VAR78%4])
else
if (VAR166[VAR78] == VAR32[VAR78%4])
else
if (VAR47[VAR78] == VAR144[VAR78%4])
else
end
always @(posedge clk) begin
if (VAR67[VAR78] == VAR11[VAR78%4])
end
else
if (VAR15[VAR78] == VAR111[VAR78%4])
else
if (VAR162[VAR78] == VAR39[VAR78%4])
else
if (VAR83[VAR78] == VAR164[VAR78%4])
else
if (VAR224[VAR78] == VAR32[VAR78%4])
else
if (VAR7[VAR78] == VAR144[VAR78%4])
else
if (VAR166[VAR78] == VAR172[VAR78%4])
else
if (VAR47[VAR78] == VAR220[VAR78%4])
else
end
end
always @(posedge clk) begin
VAR182 &&
VAR231 &&
VAR114 &&
VAR42 &&
VAR185 &&
VAR57 &&
VAR106);
end
always @(posedge clk) begin
VAR33 &&
VAR81 &&
VAR163 &&
VAR175 &&
VAR238 &&
VAR109 &&
VAR66);
end
always @(posedge clk) begin
VAR155 &&
VAR125 &&
VAR154 &&
VAR79 &&
VAR88 &&
VAR28 &&
VAR102);
end
end else if (VAR189 == 2) begin: VAR229
for (VAR78 = 0; VAR78 < VAR9; VAR78 = VAR78 + 1) begin: VAR61
always @(posedge clk) begin
if (VAR67[VAR78] == VAR51[VAR78%4])
end
else
if (VAR15[VAR78] == VAR24[VAR78%4])
end
else
if (VAR162[VAR78] == VAR217[VAR78%4])
end
else
if (VAR83[VAR78] == VAR136[VAR78%4])
else
end
always @(posedge clk) begin
if (VAR67[VAR78] == VAR190[VAR78%4])
end
else
if (VAR15[VAR78] == VAR148[VAR78%4])
else
if (VAR162[VAR78] == VAR197[VAR78%4])
else
if (VAR83[VAR78] == VAR223[VAR78%4])
else
end
always @(posedge clk) begin
if (VAR67[VAR78] == VAR226[VAR78%4])
end
else
if (VAR15[VAR78] == VAR90[VAR78%4])
else
if (VAR162[VAR78] == VAR97[VAR78%4])
else
if (VAR83[VAR78] == VAR147[VAR78%4])
else
end
always @(posedge clk) begin
if (VAR67[VAR78] == VAR132[VAR78%4])
end
else
if (VAR15[VAR78] == VAR173[VAR78%4])
else
if (VAR162[VAR78] == VAR169[VAR78%4])
else
if (VAR83[VAR78] == VAR198[VAR78%4])
else
end
end
always @(posedge clk) begin
VAR160 &&
VAR170 &&
VAR177);
VAR180 &&
VAR69 &&
VAR219);
end
always @(posedge clk) begin
VAR33 &&
VAR81 &&
VAR163);
VAR155 &&
VAR125 &&
VAR154);
end
end
endgenerate
always @(posedge clk) begin
end
always @(posedge clk) begin
if (rst)
end
else if ((VAR34 == VAR167) ||
(VAR34 == VAR89) ||
(VAR34 == VAR171))
else
end
always @(posedge clk) begin
if (rst)
end
else if ((VAR34 == VAR96) && VAR40)
else
end
always @(posedge clk)
always @(posedge clk) begin
if (rst) begin
end else begin
case (VAR34)
VAR119: begin
if (VAR237) begin
if (VAR115 == "VAR181")
end
else
end
end
VAR96: begin
if (VAR218 && (VAR189 == 4)) begin
if (VAR16)
end
else begin
if (VAR202)
end
else if (VAR139) begin
end else if (VAR122) begin
end else if (~VAR234) begin
end else
end
end else if (VAR218 && (VAR189 == 2)) begin
if ((VAR133 && VAR91) ||
(VAR195 && VAR91))
end
else if (VAR133 && ~VAR91) begin
end else begin
if (VAR202)
end
else if ((VAR92 && VAR122) ||
(VAR31 && VAR122)) begin
end else if (VAR92 && ~VAR122) begin
end else if (~VAR234) begin
end else
end
end else if (VAR113 == 'd31)
end
VAR152: begin
if (VAR206 && ~VAR46)
if (VAR206) begin
if (VAR150 && ~VAR48) begin
end
end
end
VAR167: begin
if (VAR118 == 'd4) begin
end
end
VAR89: begin
if (VAR118 == 'd15) begin
if (VAR202)
end
else if (VAR234) begin
end else
end
end
VAR127: begin
if (VAR202 && (VAR70 != VAR58-1)) begin
end else
if (VAR37)
if (((VAR58 == 1) || (VAR115 == "VAR1")) ||
(VAR70 == VAR58-1)) begin
if (VAR202) begin
end else
end else begin
end
end
VAR171: begin
if (VAR118 == 'd15) begin
end
end
VAR105: begin
if (VAR60 && ~VAR202) begin
end else
if (VAR202)
end
VAR41: begin
if (VAR202)
end
else
end
endcase
end
end
always @(posedge clk)
if (rst)
end
else
always @(posedge clk)
if (rst || (VAR60 && ~VAR202))
end
else if (VAR73)
endmodule | bsd-2-clause |
fallen/milkymist-mmu | cores/fmlarb/rtl/fmlarb.v | 5,824 | module MODULE1 #(
parameter VAR62 = 26
) (
input VAR56,
input VAR68,
input [VAR62-1:0] VAR41,
input VAR29,
input VAR34,
output VAR42,
input [7:0] VAR6,
input [63:0] VAR49,
output [63:0] VAR38,
input [VAR62-1:0] VAR27,
input VAR20,
input VAR43,
output VAR3,
input [7:0] VAR65,
input [63:0] VAR33,
output [63:0] VAR37,
input [VAR62-1:0] VAR1,
input VAR66,
input VAR51,
output VAR64,
input [7:0] VAR54,
input [63:0] VAR63,
output [63:0] VAR11,
input [VAR62-1:0] VAR40,
input VAR44,
input VAR53,
output VAR61,
input [7:0] VAR58,
input [63:0] VAR14,
output [63:0] VAR50,
input [VAR62-1:0] VAR5,
input VAR25,
input VAR32,
output VAR26,
input [7:0] VAR4,
input [63:0] VAR28,
output [63:0] VAR67,
input [VAR62-1:0] VAR59,
input VAR55,
input VAR31,
output VAR17,
input [7:0] VAR22,
input [63:0] VAR35,
output [63:0] VAR10,
output reg [VAR62-1:0] VAR71,
output reg VAR16,
output reg VAR69,
input VAR24,
output reg [7:0] VAR18,
input [63:0] VAR2,
output reg [63:0] VAR23
);
assign VAR38 = VAR2;
assign VAR37 = VAR2;
assign VAR11 = VAR2;
assign VAR50 = VAR2;
assign VAR67 = VAR2;
assign VAR10 = VAR2;
wire VAR52;
wire VAR70;
wire VAR36;
wire VAR60;
wire VAR9;
wire VAR72;
reg [2:0] VAR8;
reg [2:0] VAR7;
always @(posedge VAR56) begin
if(VAR68)
VAR8 <= 3'd0;
end
else
VAR8 <= VAR7;
end
always @ begin
case(VAR8)
3'd0: begin
VAR71 = VAR41;
VAR16 = VAR52;
VAR69 = VAR34;
end
3'd1: begin
VAR71 = VAR27;
VAR16 = VAR70;
VAR69 = VAR43;
end
3'd2: begin
VAR71 = VAR1;
VAR16 = VAR36;
VAR69 = VAR51;
end
3'd3: begin
VAR71 = VAR40;
VAR16 = VAR60;
VAR69 = VAR53;
end
3'd4: begin
VAR71 = VAR5;
VAR16 = VAR9;
VAR69 = VAR32;
end
default: begin VAR71 = VAR59;
VAR16 = VAR72;
VAR69 = VAR31;
end
endcase
end
VAR13 VAR21(.VAR56(VAR56), .VAR68(VAR68),
.VAR48(VAR29), .VAR47((VAR8 == 3'd0) & VAR24), .VAR30(VAR34),
.VAR15(VAR52), .ack(VAR42));
VAR13 VAR57(.VAR56(VAR56), .VAR68(VAR68),
.VAR48(VAR20), .VAR47((VAR8 == 3'd1) & VAR24), .VAR30(VAR43),
.VAR15(VAR70), .ack(VAR3));
VAR13 VAR46(.VAR56(VAR56), .VAR68(VAR68),
.VAR48(VAR66), .VAR47((VAR8 == 3'd2) & VAR24), .VAR30(VAR51),
.VAR15(VAR36), .ack(VAR64));
VAR13 VAR45(.VAR56(VAR56), .VAR68(VAR68),
.VAR48(VAR44), .VAR47((VAR8 == 3'd3) & VAR24), .VAR30(VAR53),
.VAR15(VAR60), .ack(VAR61));
VAR13 VAR19(.VAR56(VAR56), .VAR68(VAR68),
.VAR48(VAR25), .VAR47((VAR8 == 3'd4) & VAR24), .VAR30(VAR32),
.VAR15(VAR9), .ack(VAR26));
VAR13 VAR12(.VAR56(VAR56), .VAR68(VAR68),
.VAR48(VAR55), .VAR47((VAR8 == 3'd5) & VAR24), .VAR30(VAR31),
.VAR15(VAR72), .ack(VAR17));
reg [2:0] VAR39;
always @(posedge VAR56) begin
if(VAR68)
VAR39 <= 3'd0;
end
else if(VAR69 & VAR24)
VAR39 <= VAR8;
end
always @(*) begin
case(VAR39)
3'd0: begin
VAR23 = VAR49;
VAR18 = VAR6;
end
3'd1: begin
VAR23 = VAR33;
VAR18 = VAR65;
end
3'd2: begin
VAR23 = VAR63;
VAR18 = VAR54;
end
3'd3: begin
VAR23 = VAR14;
VAR18 = VAR58;
end
3'd4: begin
VAR23 = VAR28;
VAR18 = VAR4;
end
default: begin VAR23 = VAR35;
VAR18 = VAR22;
end
endcase
end
endmodule | lgpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v | 12,727 | module MODULE1(
VAR66, VAR73, VAR43,
clk, rst, VAR49, VAR72, VAR20, addr, VAR17, VAR8
);
input VAR66;
input [VAR29 - 1:0] VAR43; output VAR73;
input clk; input rst; input VAR49; input [3:0] VAR72; input VAR20; input [9:0] addr; input [31:0] VAR17; output [31:0] VAR8;
assign VAR73 = VAR66;
VAR13 VAR30(
VAR42 VAR30(
VAR13 VAR30(
.VAR66(VAR66),
.VAR73(VAR73),
.VAR43(VAR43),
.VAR70(clk),
.VAR24(~VAR49),
.VAR35(~VAR72),
.VAR48(addr),
.VAR44(VAR17),
.VAR39(~VAR20),
.VAR75(VAR8)
);
VAR68 VAR68(
.VAR56(~VAR72),
.VAR53(),
.VAR64(~VAR20),
.VAR2(),
.VAR58(),
.VAR16(addr),
.VAR28(addr),
.VAR17(VAR17),
.VAR8(VAR8)
);
VAR74 VAR74(
.clk(clk),
.VAR3(addr),
.VAR45(VAR17),
.VAR72(VAR72),
.VAR20(VAR20),
.VAR6(VAR49),
.VAR60(VAR8)
);
wire VAR23;
wire VAR61;
wire VAR59;
wire VAR15;
wire VAR77;
wire VAR5;
wire VAR25;
wire VAR18;
assign VAR23 = VAR66;
assign VAR61 = VAR77;
assign VAR59 = VAR5;
assign VAR15 = VAR25;
assign VAR73 = VAR18;
VAR38 VAR11(
VAR21 VAR11(
VAR38 VAR11(
.VAR66(VAR23),
.VAR73(VAR77),
.VAR43(VAR43),
.VAR52(clk),
.VAR34(addr),
.VAR10(VAR17[7:0]),
.VAR35(~VAR72[0]),
.VAR24(~VAR49),
.VAR39(~VAR20),
.VAR7(VAR8[7:0])
);
VAR38 VAR41(
VAR21 VAR41(
VAR38 VAR41(
.VAR66(VAR61),
.VAR73(VAR5),
.VAR43(VAR43),
.VAR52(clk),
.VAR34(addr),
.VAR10(VAR17[15:8]),
.VAR35(~VAR72[1]),
.VAR24(~VAR49),
.VAR39(~VAR20),
.VAR7(VAR8[15:8])
);
VAR38 VAR31(
VAR21 VAR31(
VAR38 VAR31(
.VAR66(VAR59),
.VAR73(VAR25),
.VAR43(VAR43),
.VAR52(clk),
.VAR34(addr),
.VAR10(VAR17[23:16]),
.VAR35(~VAR72[2]),
.VAR24(~VAR49),
.VAR39(~VAR20),
.VAR7(VAR8[23:16])
);
VAR38 VAR37(
VAR21 VAR37(
VAR38 VAR37(
.VAR66(VAR15),
.VAR73(VAR18),
.VAR43(VAR43),
.VAR52(clk),
.VAR34(addr),
.VAR10(VAR17[31:24]),
.VAR35(~VAR72[3]),
.VAR24(~VAR49),
.VAR39(~VAR20),
.VAR7(VAR8[31:24])
);
VAR55 VAR47(
.VAR70(clk),
.VAR4(rst),
.VAR27(addr),
.VAR10(VAR17[3:0]),
.VAR46(VAR49),
.VAR62(VAR72[0]),
.VAR57(VAR8[3:0])
);
VAR55 VAR22(
.VAR70(clk),
.VAR4(rst),
.VAR27(addr),
.VAR10(VAR17[7:4]),
.VAR46(VAR49),
.VAR62(VAR72[0]),
.VAR57(VAR8[7:4])
);
VAR55 VAR12(
.VAR70(clk),
.VAR4(rst),
.VAR27(addr),
.VAR10(VAR17[11:8]),
.VAR46(VAR49),
.VAR62(VAR72[1]),
.VAR57(VAR8[11:8])
);
VAR55 VAR14(
.VAR70(clk),
.VAR4(rst),
.VAR27(addr),
.VAR10(VAR17[15:12]),
.VAR46(VAR49),
.VAR62(VAR72[1]),
.VAR57(VAR8[15:12])
);
VAR55 VAR67(
.VAR70(clk),
.VAR4(rst),
.VAR27(addr),
.VAR10(VAR17[19:16]),
.VAR46(VAR49),
.VAR62(VAR72[2]),
.VAR57(VAR8[19:16])
);
VAR55 VAR50(
.VAR70(clk),
.VAR4(rst),
.VAR27(addr),
.VAR10(VAR17[23:20]),
.VAR46(VAR49),
.VAR62(VAR72[2]),
.VAR57(VAR8[23:20])
);
VAR55 VAR40(
.VAR70(clk),
.VAR4(rst),
.VAR27(addr),
.VAR10(VAR17[27:24]),
.VAR46(VAR49),
.VAR62(VAR72[3]),
.VAR57(VAR8[27:24])
);
VAR55 VAR65(
.VAR70(clk),
.VAR4(rst),
.VAR27(addr),
.VAR10(VAR17[31:28]),
.VAR46(VAR49),
.VAR62(VAR72[3]),
.VAR57(VAR8[31:28])
);
VAR33 VAR32(
.VAR70(clk),
.VAR51(rst),
.VAR27({1'b0,addr}),
.VAR10(VAR17[7:0]),
.VAR36(1'b0),
.VAR46(VAR49),
.VAR62(VAR72[0]),
.VAR57(VAR8[7:0]),
.VAR63()
);
VAR33 VAR69(
.VAR70(clk),
.VAR51(rst),
.VAR27({1'b0,addr}),
.VAR10(VAR17[15:8]),
.VAR36(1'b0),
.VAR46(VAR49),
.VAR62(VAR72[1]),
.VAR57(VAR8[15:8]),
.VAR63()
);
VAR33 VAR19(
.VAR70(clk),
.VAR51(rst),
.VAR27({1'b0,addr}),
.VAR10(VAR17[23:16]),
.VAR36(1'b0),
.VAR46(VAR49),
.VAR62(VAR72[2]),
.VAR57(VAR8[23:16]),
.VAR63()
);
VAR33 VAR26(
.VAR70(clk),
.VAR51(rst),
.VAR27({1'b0,addr}),
.VAR10(VAR17[31:24]),
.VAR36(1'b0),
.VAR46(VAR49),
.VAR62(VAR72[3]),
.VAR57(VAR8[31:24]),
.VAR63()
);
reg [7:0] VAR76 [1023:0]; reg [7:0] VAR9 [1023:0]; reg [7:0] VAR54 [1023:0]; reg [7:0] VAR71 [1023:0]; reg [9:0] VAR1;
assign VAR8 = (VAR20) ? {VAR71[VAR1], VAR54[VAR1], VAR9[VAR1], VAR76[VAR1]} : {32{1'b0}};
always @(posedge clk or posedge rst)
if (rst)
VAR1 <= 10'h000;
else if (VAR49)
VAR1 <= addr;
always @(posedge clk)
if (VAR49 && VAR72[0])
VAR76[addr] <= VAR17[7:0];
always @(posedge clk)
if (VAR49 && VAR72[1])
VAR9[addr] <= VAR17[15:8];
always @(posedge clk)
if (VAR49 && VAR72[2])
VAR54[addr] <= VAR17[23:16];
always @(posedge clk)
if (VAR49 && VAR72[3])
VAR71[addr] <= VAR17[31:24];
endmodule | gpl-2.0 |
Kipsora/MIPS-CPU | source/machine/memory/ram.v | 1,900 | module MODULE1(
input wire VAR9,
input wire VAR15,
input wire VAR7,
input wire[VAR11] addr,
input wire[VAR20] VAR6,
input wire[VAR8] VAR13,
output reg[VAR8] VAR3
);
reg[VAR17] VAR18[0 : VAR4 - 1];
reg[VAR17] VAR5[0 : VAR4 - 1];
reg[VAR17] VAR19[0 : VAR4 - 1];
reg[VAR17] VAR14[0 : VAR4 - 1];
always @ (posedge VAR9) begin
if (VAR15 == VAR1 && VAR7 == VAR12) begin
if (VAR6[3]) begin
VAR14[addr[VAR16 + 1 : 2]] <= VAR13[31 : 24];
end
if (VAR6[2]) begin
VAR19[addr[VAR16 + 1 : 2]] <= VAR13[23 : 16];
end
if (VAR6[1]) begin
VAR5[addr[VAR16 + 1 : 2]] <= VAR13[15 : 8];
end
if (VAR6[0]) begin
VAR18[addr[VAR16 + 1 : 2]] <= VAR13[7 : 0];
end
end
end
always @ (*) begin
if (VAR15 == VAR2) begin
VAR3 <= 0; end else if (VAR7 == VAR10) begin
VAR3 = {
VAR14[addr[VAR16 + 1 : 2]],
VAR19[addr[VAR16 + 1 : 2]],
VAR5[addr[VAR16 + 1 : 2]],
VAR18[addr[VAR16 + 1 : 2]]
};
end else begin
VAR3 <= 0; end
end
endmodule MODULE1 | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/gpio/gpio.v | 5,576 | module MODULE1 (
input wire clk,
input wire reset,
input wire VAR23,
input wire VAR12,
input wire VAR21,
input wire [VAR29] addr,
input wire [VAR2] VAR3,
output reg [VAR2] VAR27,
output reg VAR26
, input wire [VAR8-1:0] VAR20
, output reg [VAR22-1:0] VAR28
, inout wire [VAR11-1:0] VAR4
);
wire [VAR11-1:0] VAR1;
reg [VAR11-1:0] VAR15;
reg [VAR11-1:0] VAR30;
reg [VAR11-1:0] VAR5;
integer VAR17;
assign VAR1 = VAR4;
assign VAR4 = VAR5;
always @(*) begin
for (VAR17 = 0; VAR17 < VAR11; VAR17 = VAR17 + 1) begin : VAR7
VAR5[VAR17] = (VAR30[VAR17] == VAR24) ? 1'VAR10 : VAR15[VAR17];
end
end
always @(posedge clk or VAR19 reset) begin
if (reset == VAR9) begin
VAR27 <= VAR14'h0;
VAR26 <= VAR13;
VAR28 <= {VAR22{VAR16}};
VAR15 <= {VAR11{VAR16}};
VAR30 <= {VAR11{VAR24}};
end else begin
if ((VAR23 == VAR18) && (VAR12 == VAR18)) begin
VAR26 <= VAR18;
end else begin
VAR26 <= VAR13;
end
if ((VAR23 == VAR18) && (VAR12 == VAR18) && (VAR21 == VAR25)) begin
case (addr)
VAR27 <= {{VAR14-VAR8{1'b0}},
VAR20};
end
VAR27 <= {{VAR14-VAR22{1'b0}},
VAR28};
end
VAR27 <= {{VAR14-VAR11{1'b0}},
VAR1};
end
VAR27 <= {{VAR14-VAR11{1'b0}},
VAR30};
end
endcase
end else begin
VAR27 <= VAR14'h0;
end
if ((VAR23 == VAR18) && (VAR12 == VAR18) && (VAR21 == VAR6)) begin
case (addr)
VAR28 <= VAR3[VAR22-1:0];
end
VAR15 <= VAR3[VAR11-1:0];
end
VAR30 <= VAR3[VAR11-1:0];
end
endcase
end
end
end
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/rd_bitslip.v | 5,424 | module MODULE1 #
(
parameter VAR2 = 100
)
(
input clk,
input [1:0] VAR8,
input [1:0] VAR9,
input [5:0] din,
output reg [3:0] VAR3
);
reg VAR6;
reg [3:0] VAR1;
reg [3:0] VAR7;
reg [3:0] VAR5;
reg [3:0] VAR4;
always @(posedge clk)
always @(VAR8 or din or VAR6)
case (VAR8)
2'b00: VAR1 = {din[3], din[2], din[1], din[0]};
2'b01: VAR1 = {din[4], din[3], din[2], din[1]};
2'b10: VAR1 = {din[5], din[4], din[3], din[2]};
2'b11: VAR1 = {VAR6, din[5], din[4], din[3]};
endcase
always @(posedge clk) begin
end
always @(posedge clk)
case (VAR9)
endcase
endmodule | mit |
CospanDesign/sdio-device | rtl/phy/sdio_data_phy.v | 13,960 | module MODULE1 (
input clk,
input rst,
input VAR19,
input VAR8,
input VAR20,
input VAR35,
input VAR6,
input VAR51,
input VAR57,
output reg VAR56,
input VAR18,
input [12:0] VAR53,
output reg VAR41,
output [7:0] VAR25,
input VAR58,
input [7:0] VAR59,
output reg VAR22, input VAR2,
output reg VAR36,
output reg VAR50,
input [7:0] VAR13,
output reg [7:0] VAR9
);
localparam VAR47 = 4'h0;
localparam VAR12 = 4'h1;
localparam VAR24 = 4'h2;
localparam VAR65 = 4'h3;
localparam VAR23 = 4'h4;
localparam VAR11 = 4'h5;
localparam VAR49 = 4'h6;
localparam VAR7 = 4'h1;
reg [3:0] state;
reg [3:0] VAR21;
reg [12:0] VAR32;
wire VAR54;
reg [3:0] VAR16;
wire [15:0] VAR3 [0:3];
reg VAR46;
wire VAR26;
wire VAR15;
reg [15:0] VAR61 [0:3];
wire [15:0] VAR31;
wire [15:0] VAR55;
wire [15:0] VAR10;
wire [15:0] VAR30;
wire [15:0] VAR4;
wire [15:0] VAR48;
wire [15:0] VAR27;
wire [15:0] VAR38;
reg [7:0] VAR63;
reg [7:0] VAR43;
wire VAR5;
wire VAR60;
wire VAR17;
reg VAR34;
reg VAR44;
reg VAR64;
wire VAR28;
reg VAR37;
reg [7:0] VAR52;
integer VAR39;
genvar VAR42;
generate
for (VAR42 = 0; VAR42 < 4; VAR42 = VAR42 + 1) begin : VAR1
VAR14 VAR40(
.clk (clk ),
.rst (VAR26 ),
.en (VAR15 ),
.VAR62 (VAR43[VAR42] ),
.VAR33 (VAR43[VAR42 + 4] ),
.VAR40 (VAR3[VAR42] )
);
end
endgenerate
assign VAR26 = VAR58 ? 1'b0 : VAR46;
assign VAR15 = VAR58 ? 1'b1 : VAR44;
assign VAR4 = VAR3[0];
assign VAR48 = VAR3[1];
assign VAR27 = VAR3[2];
assign VAR38 = VAR3[3];
assign VAR31 = VAR61[0];
assign VAR55 = VAR61[1];
assign VAR10 = VAR61[2];
assign VAR30 = VAR61[3];
assign VAR25= VAR50 ? 8'h00 : VAR13;
assign VAR54 = ( (VAR61[0] == VAR3[0]) &&
(VAR61[1] == VAR3[1]) &&
(VAR61[2] == VAR3[2]) &&
(VAR61[3] == VAR3[3]));
reg VAR45;
always @ (posedge clk) begin
if (rst) begin
VAR46 <= 1;
VAR21 <= VAR47;
VAR44 <= 0;
VAR43 <= 0;
VAR45 <= 0;
end
else begin
case (VAR21)
VAR47: begin
VAR46 <= 1;
VAR43 <= 0;
if (VAR34) begin
VAR45 <= 1;
VAR46 <= 0;
VAR21 <= VAR7;
VAR44 <= 1;
end
end
VAR7: begin
if (VAR18) begin
VAR43[0] <= VAR13[4'h3];
VAR43[1] <= VAR13[4'h2];
VAR43[2] <= VAR13[4'h1];
VAR43[3] <= VAR13[4'h0];
VAR43[4] <= VAR13[4'h7];
VAR43[5] <= VAR13[4'h6];
VAR43[6] <= VAR13[4'h5];
VAR43[7] <= VAR13[4'h4];
end
else begin
VAR43[0] <= VAR59[4'h3];
VAR43[1] <= VAR59[4'h3];
VAR43[2] <= VAR59[4'h1];
VAR43[3] <= VAR59[4'h0];
VAR43[4] <= VAR59[4'h7];
VAR43[5] <= VAR59[4'h6];
VAR43[6] <= VAR59[4'h5];
VAR43[7] <= VAR59[4'h4];
end
if (!VAR34) begin
VAR21 <= VAR49;
VAR44 <= 0;
end
end
VAR49: begin
if (state == VAR47) begin
VAR21 <= VAR47;
end
end
endcase
VAR45 <= ~VAR45;
end
end
always @ (posedge clk)begin
if (rst) begin
VAR37 <= 1'b0;
VAR52 <= 8'h00;
end
else begin
VAR37 <= VAR58;
VAR52 <= VAR59;
end
end
always @ (posedge clk) begin
if (rst) begin
VAR9 <= 8'hFF;
end
else begin
VAR9 <= VAR63;
end
end
always @ (posedge clk) begin
VAR41 <= 0;
if (rst) begin
VAR36 <= 0;
state <= VAR47;
VAR22 <= 0;
VAR32 <= 0;
VAR50 <= 0;
VAR34 <= 0;
VAR63 <= 0;
VAR56 <= 0;
for (VAR39 = 0; VAR39 < 4; VAR39 = VAR39 + 1) begin
VAR61[VAR39] <= 0;
end
end
else begin
VAR63 <= VAR59;
case (state)
VAR47: begin
VAR56 <= 0;
VAR32 <= 0;
if (VAR8) begin
VAR50 <= 1;
VAR63 <= 8'hFD;
end
else begin
VAR50 <= 0;
VAR63 <= 8'hFF;
end
VAR22 <= 0;
if (VAR57) begin
VAR50 <= 0;
VAR36 <= 0;
for (VAR39 = 0; VAR39 < 4; VAR39 = VAR39 + 1) begin
VAR61[VAR39] <= 0;
end
state <= VAR12;
end
end
VAR12: begin
VAR63 <= 8'hFF;
if (VAR18) begin
VAR22 <= 1;
if (VAR13[0] == 0) begin
VAR34 <= 1;
state <= VAR24;
end
else begin
end
end
else begin
if (VAR13[2]) begin
VAR22 <= 1;
if (VAR2) begin
VAR50 <= 1;
state <= VAR65;
end
end
end
if (!VAR57) begin
state <= VAR47;
end
end
VAR24: begin
VAR41 <= 1;
if (VAR32 == VAR53 - 1) begin
end
if (VAR32 < VAR53) begin
VAR32 <= VAR32 + 1;
end
else begin
VAR41 <= 0;
VAR34 <= 0;
state <= VAR23;
VAR32 <= 0;
VAR61[0] <= {VAR61[0][13:0], VAR13[7], VAR13[3]};
VAR61[1] <= {VAR61[1][13:0], VAR13[6], VAR13[2]};
VAR61[2] <= {VAR61[2][13:0], VAR13[5], VAR13[1]};
VAR61[3] <= {VAR61[3][13:0], VAR13[4], VAR13[0]};
end
if (!VAR57) begin
state <= VAR47;
end
end
VAR65: begin
if (VAR58) begin
VAR61[0] <= VAR3[0];
VAR61[1] <= VAR3[1];
VAR61[2] <= VAR3[2];
VAR61[3] <= VAR3[3];
end
if (!VAR57) begin
state <= VAR47;
end
if (VAR32 < VAR53) begin
if (!VAR37) begin
VAR63 <= 8'hFF;
end
if (VAR58 && !VAR37) begin
VAR63 <= 8'h00;
end
if (VAR37) begin
VAR63 <= VAR52;
VAR32 <= VAR32 + 1;
end
end
if (VAR32 >= VAR53) begin
VAR34 <= 0;
state <= VAR11;
VAR32 <= 0;
VAR63 <= {VAR31[15], VAR55[15], VAR10[15], VAR30[15],
VAR31[14], VAR55[14], VAR10[14], VAR30[14]};
VAR61[0] <= {VAR61[0][13:0], 2'b00};
VAR61[1] <= {VAR61[1][13:0], 2'b00};
VAR61[2] <= {VAR61[2][13:0], 2'b00};
VAR61[3] <= {VAR61[3][13:0], 2'b00};
end
end
VAR23: begin
if (VAR32 < (VAR29 - 1)) begin
VAR32 <= VAR32 + 1;
VAR61[0] <= {VAR61[0][13:0], VAR13[7], VAR13[3]};
VAR61[1] <= {VAR61[1][13:0], VAR13[6], VAR13[2]};
VAR61[2] <= {VAR61[2][13:0], VAR13[5], VAR13[1]};
VAR61[3] <= {VAR61[3][13:0], VAR13[4], VAR13[0]};
end
else begin
state <= VAR49;
end
end
VAR11: begin
if (VAR32 < VAR29) begin
VAR32 <= VAR32 + 1;
VAR63 <= {VAR61[0][15], VAR61[1][15], VAR61[2][15], VAR61[3][15],
VAR61[0][14], VAR61[1][14], VAR61[2][14], VAR61[3][14]};
VAR61[0] <= {VAR61[0][13:0], 2'b00};
VAR61[1] <= {VAR61[1][13:0], 2'b00};
VAR61[2] <= {VAR61[2][13:0], 2'b00};
VAR61[3] <= {VAR61[3][13:0], 2'b00};
end
else begin
VAR63 <= 8'hFF;
state <= VAR49;
end
end
VAR49: begin
VAR56 <= 1;
VAR22 <= 0;
VAR63 <= 8'hFF;
VAR50 <= 0;
VAR36 <= VAR54;
if (!VAR57) begin
state <= VAR47;
end
end
default: begin
if (!VAR57) begin
state <= VAR47;
end
end
endcase
end
end
endmodule | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_gcd_0_1/gcd_block_design_gcd_0_1_stub.v | 2,706 | module MODULE1(VAR12,
VAR6, VAR10, VAR19, VAR9,
VAR13, VAR3, VAR1, VAR5,
VAR17, VAR8, VAR18,
VAR15, VAR16, VAR11, VAR4,
VAR2, VAR7, VAR14, interrupt)
;
input [5:0]VAR12;
input VAR6;
output VAR10;
input [31:0]VAR19;
input [3:0]VAR9;
input VAR13;
output VAR3;
output [1:0]VAR1;
output VAR5;
input VAR17;
input [5:0]VAR8;
input VAR18;
output VAR15;
output [31:0]VAR16;
output [1:0]VAR11;
output VAR4;
input VAR2;
input VAR7;
input VAR14;
output interrupt;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2.functional.v | 1,177 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
olgirard/opengfx430 | core/bench/verilog/ram.v | 3,097 | module MODULE1 (
VAR10,
VAR6, VAR5, VAR3, VAR9, VAR4 );
parameter VAR8 = 6; parameter VAR1 = 256;
output [15:0] VAR10;
input [VAR8:0] VAR6; input VAR5; input VAR3; input [15:0] VAR9; input [1:0] VAR4;
reg [15:0] VAR7 [0:(VAR1/2)-1];
reg [VAR8:0] VAR11;
wire [15:0] VAR2 = VAR7[VAR6];
always @(posedge VAR3)
if (~VAR5 & VAR6<(VAR1/2))
begin
if (VAR4==2'b00) VAR7[VAR6] <= VAR9;
end
else if (VAR4==2'b01) VAR7[VAR6] <= {VAR9[15:8], VAR2[7:0]};
else if (VAR4==2'b10) VAR7[VAR6] <= {VAR2[15:8], VAR9[7:0]};
VAR11 <= VAR6;
end
assign VAR10 = VAR7[VAR11];
endmodule | bsd-3-clause |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/ModulosBasicos/PruebasFPGA/contadorprueba/conmutacion.v | 1,097 | module MODULE1 (
input [3:0] VAR1,
input [3:0] VAR7,
input [3:0] VAR3,
input VAR9,
input VAR11,
input VAR10,
input VAR5,
output reg [1:0] VAR6,
output reg [3:0] VAR2
);
reg VAR4;
reg [1:0] VAR8;
begin
begin
begin
end
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
begin | gpl-3.0 |
jmahler/mips-cpu | regm.v | 2,004 | module MODULE1(
input wire clk,
input wire [4:0] VAR4, VAR5,
output wire [31:0] VAR3, VAR1,
input wire VAR7,
input wire [4:0] VAR8,
input wire [31:0] VAR6);
reg [31:0] VAR2 [0:31];
reg [31:0] VAR3, VAR1; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai.behavioral.pp.v | 2,191 | module MODULE1 (
VAR15 ,
VAR2 ,
VAR8 ,
VAR11 ,
VAR19 ,
VAR16 ,
VAR6,
VAR13,
VAR5 ,
VAR14
);
output VAR15 ;
input VAR2 ;
input VAR8 ;
input VAR11 ;
input VAR19 ;
input VAR16 ;
input VAR6;
input VAR13;
input VAR5 ;
input VAR14 ;
wire VAR12 ;
wire VAR4 ;
wire VAR1 ;
wire VAR20;
nor VAR10 (VAR12 , VAR11, VAR2, VAR8 );
nor VAR9 (VAR4 , VAR19, VAR16 );
or VAR7 (VAR1 , VAR4, VAR12 );
VAR18 VAR3 (VAR20, VAR1, VAR6, VAR13);
buf VAR17 (VAR15 , VAR20 );
endmodule | apache-2.0 |
Kumikomi/openreroc_posturesensor | hardware/src/MPU_gyro_controller.v | 12,842 | module MODULE1(
input clk,
input reset,
output reg [15:0] VAR29, output reg [15:0] VAR35, output reg [15:0] VAR27, output VAR20, output VAR23, output VAR34, input VAR7, output reg VAR42
);
parameter VAR16 = 18,
VAR36 = 19,
VAR30 = 20,
VAR21 = 21,
VAR41 = 22,
VAR3 = 23,
VAR14 = 24,
VAR46 = 25,
VAR49 = 26,
VAR9 = 27,
VAR31 = 28,
VAR5 = 29,
VAR40 = 30,
VAR50 = 31,
VAR18 = 32,
VAR39 = 33,
VAR25 = 34,
VAR47 = 35;
wire VAR1; wire [7:0] VAR44;
reg [31:0] VAR33 = 0; parameter VAR48 = 32'd10;
reg [4:0] state;
reg [5:0] VAR32;
reg [6:0] VAR6; reg [7:0] VAR45; reg VAR28; reg VAR17 = 0; reg [7:0] VAR11; reg [7:0] VAR43; reg [7:0] VAR52;
reg [7:0] VAR24;
VAR8 VAR8(
.clk(clk),
.rst(reset),
.VAR22(VAR6),
.VAR2(VAR45),
.VAR38(VAR44), .VAR26(VAR28),
.VAR15(VAR17),
.VAR13(VAR1),
.VAR20(VAR20), .VAR23(VAR23), .VAR34(VAR34), .VAR7(VAR7) );
always@ (posedge clk)
begin
if(reset)
state <= 0;
end
else
begin
case(state)
0:if(VAR1 == 0) state <= 1; 1: state <= 2; 2:if(VAR1 == 0) state <= 16; 16:state <= 17; 17:if(VAR1 == 0) state <= 18; 18:state <= 19;
19:state <= 20; 20:if(VAR1 == 0) state <= 3;
3:if(VAR1 == 0)state <= 7;
7:if(VAR32 == 24 && VAR1 == 0) state <= 8; 8:if(VAR32 == 30 && VAR1 == 0) state <= 9; 9:if(VAR32 == 36 && VAR1 == 0) state <= 10; 10:if(VAR33 == VAR48) state <= 3;
default state <= 0;
endcase
end
end
always@ (posedge clk)
begin
if(reset)
begin
VAR29 <= 0;
VAR35 <= 0;
VAR27 <= 0;
VAR6 <= 0;
VAR45 <= 0;
VAR28 <= 1; VAR17 <= 0;
VAR32 <= 0;
VAR42 <= 0;
end
else
begin
case (state)
0:begin VAR29 <= 0;
VAR35 <= 0;
VAR27 <= 0;
VAR11 <= 0;
VAR43 <= 0;
VAR52 <= 0;
VAR6 <= 0;
VAR45 <= 0;
VAR17 <= 0;
VAR32 <= 0;
VAR33 <= 0;
VAR42 <= 0;
end
1:begin VAR17 <= 1;
VAR28 <= 0; VAR6 <= 8'h6B;
VAR45 <= 8'h00;
end
2:begin VAR17 <= 0;
end
16:begin VAR17 <= 1;
VAR28 <= 1; VAR6 <= 8'h75; end
17:begin VAR17 <= 0;
end
18:begin VAR24 <= VAR44;
end
19:begin VAR17 <= 1;
VAR28 <= 0; VAR6 <= 8'h37; VAR45 <= 8'h02;
end
20:begin VAR17 <= 0;
end
3:begin VAR42 <= 0;
VAR11 <= 0;
VAR43 <= 0;
VAR52 <= 0;
VAR32 <= 18;
VAR33 <= 0;
end
7:begin case(VAR32)
VAR16:begin
if(VAR1 == 0) begin
VAR17 <= 1;
VAR28 <= 1;
VAR6 <= VAR10; VAR32 <= VAR32 + 1;
end
end
VAR36:begin
VAR17 <= 0;
if(VAR1 == 0) VAR32 <= VAR32 + 1;
end
VAR30:begin
VAR11 <= VAR44;
VAR32 <= VAR32 + 1;
end
VAR21:begin
if(VAR1 == 0) begin
VAR17 <= 1;
VAR28 <= 1;
VAR6 <= VAR12; VAR32 <= VAR32 + 1;
end
end
VAR41:begin
VAR17 <= 0;
if(VAR1 == 0) VAR32 <= VAR32 + 1;
end
VAR3:begin
VAR29 <= { VAR44,VAR11};
VAR32 <= VAR32 + 1;
end
endcase
end
8:begin case(VAR32)
VAR14:begin
if(VAR1 == 0) begin
VAR17 <= 1;
VAR28 <= 1;
VAR6 <= VAR4; VAR32 <= VAR32 + 1;
end
end
VAR46:begin
VAR17 <= 0;
if(VAR1 == 0) VAR32 <= VAR32 + 1;
end
VAR49:begin
VAR43 <= VAR44;
VAR32 <= VAR32 + 1;
end
VAR9:begin
if(VAR1 == 0) begin
VAR17 <= 1;
VAR28 <= 1;
VAR6 <= VAR51; VAR32 <= VAR32 + 1;
end
end
VAR31:begin
VAR17 <= 0;
if(VAR1 == 0) VAR32 <= VAR32 + 1;
end
VAR5:begin
VAR35 <= {VAR44,VAR43};
VAR32 <= VAR32 + 1;
end
endcase
end
9:begin case(VAR32)
VAR40:begin
if(VAR1 == 0) begin
VAR17 <= 1;
VAR28 <= 1;
VAR6 <= VAR37; VAR32 <= VAR32 + 1;
end
end
VAR50:begin
VAR17 <= 0;
if(VAR1 == 0) VAR32 <= VAR32 + 1;
end
VAR18:begin
VAR52 <= VAR44;
VAR32 <= VAR32 + 1;
end
VAR39:begin
if(VAR1 == 0) begin
VAR17 <= 1;
VAR28 <= 1;
VAR6 <= VAR19; VAR32 <= VAR32 + 1;
end
end
VAR25:begin
VAR17 <= 0;
if(VAR1 == 0) VAR32 <= VAR32 + 1;
end
VAR47:begin
VAR27 <= {VAR44,VAR52};
VAR32 <= VAR32 + 1;
end
endcase
end
10:begin if(VAR33 == (VAR48 - 5)) begin
VAR42 <= 1;
VAR33 <= VAR33 + 1;
end
else begin
VAR33 <= VAR33 + 1;
end
end
endcase
end
end
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22o/sky130_fd_sc_ls__a22o.behavioral.pp.v | 2,151 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR12 ,
VAR14 ,
VAR16 ,
VAR7,
VAR4,
VAR2 ,
VAR5
);
output VAR6 ;
input VAR9 ;
input VAR12 ;
input VAR14 ;
input VAR16 ;
input VAR7;
input VAR4;
input VAR2 ;
input VAR5 ;
wire VAR8 ;
wire VAR19 ;
wire VAR13 ;
wire VAR18;
and VAR11 (VAR8 , VAR14, VAR16 );
and VAR1 (VAR19 , VAR9, VAR12 );
or VAR3 (VAR13 , VAR19, VAR8 );
VAR17 VAR15 (VAR18, VAR13, VAR7, VAR4);
buf VAR10 (VAR6 , VAR18 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3.behavioral.v | 1,440 | module MODULE1 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR7;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR4 ;
wire VAR8;
not VAR3 (VAR8, VAR1 );
buf VAR5 (VAR6 , VAR8 );
endmodule | apache-2.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CoreAPB3/4.0.100/rtl/vlog/amba_bfm/bfm_ahbtoapb.v | 3,820 | module
MODULE1
(
VAR21
,
VAR1
,
VAR31
,
VAR6
,
VAR18
,
VAR11
,
VAR19
,
VAR37
,
VAR28
,
VAR7
,
VAR23
,
VAR12
,
VAR34
,
VAR40
,
VAR33
,
VAR29
,
VAR4
,
VAR20
,
VAR30
,
VAR2
,
VAR25
,
VAR16
,
VAR3
)
;
parameter
VAR13
=
1
;
input
VAR21
;
input
VAR1
;
input
VAR31
;
input
VAR6
;
input
[
31
:
0
]
VAR18
;
input
[
31
:
0
]
VAR11
;
output
[
31
:
0
]
VAR19
;
wire
[
31
:
0
]
VAR19
;
input
VAR37
;
output
VAR28
;
wire
VAR28
;
input
[
1
:
0
]
VAR7
;
input
[
2
:
0
]
VAR23
;
input
[
2
:
0
]
VAR12
;
input
VAR34
;
input
[
3
:
0
]
VAR40
;
output
VAR33
;
wire
VAR33
;
output
[
15
:
0
]
VAR29
;
wire
[
15
:
0
]
VAR29
;
output
[
31
:
0
]
VAR4
;
wire
[
31
:
0
]
VAR4
;
output
VAR20
;
wire
VAR20
;
output
VAR30
;
wire
VAR30
;
output
[
31
:
0
]
VAR2
;
wire
[
31
:
0
]
VAR2
;
input
[
31
:
0
]
VAR25
;
input
VAR16
;
input
VAR3
;
parameter
[
1
:
0
]
VAR32
=
0
;
parameter
[
1
:
0
]
VAR8
=
1
;
parameter
[
1
:
0
]
VAR38
=
2
;
parameter
[
1
:
0
]
VAR26
=
3
;
reg
[
1
:
0
]
VAR10
;
reg
VAR22
;
reg
VAR42
;
reg
[
15
:
0
]
VAR17
;
reg
[
31
:
0
]
VAR39
;
reg
VAR24
;
reg
VAR14
;
reg
[
31
:
0
]
VAR36
;
wire
[
31
:
0
]
VAR41
;
reg
VAR35
;
reg
VAR15
;
always
@
(
posedge
VAR21
or
negedge
VAR1
)
begin
if
(
VAR1
==
1
'VAR9
0
)
begin
VAR10
<=
VAR32
;
VAR22
<=
1
'VAR9
1
;
VAR39
<=
{
32
{
1
'VAR9
0
}
}
;
VAR36
<=
{
32
{
1
'VAR9
0
}
}
;
VAR24
<=
1
'VAR9
0
;
VAR14
<=
1
'VAR9
0
;
VAR42
<=
1
'VAR9
0
;
VAR35
<=
1
'VAR9
0
;
VAR15
<=
1
'VAR9
0
;
end
else
begin
VAR42
<=
1
'VAR9
0
;
VAR22
<=
1
'VAR9
0
;
VAR35
<=
1
'VAR9
0
;
case
(
VAR10
)
VAR32
:
begin
if
(
VAR31
==
1
'VAR9
1
&
VAR37
==
1
'VAR9
1
&
(
VAR7
[
1
]
)
==
1
'VAR9
1
)
begin
VAR10
<=
VAR8
;
VAR39
<=
VAR18
;
VAR24
<=
VAR6
;
VAR36
<=
VAR11
;
VAR14
<=
1
'VAR9
0
;
VAR35
<=
VAR6
;
VAR15
<=
1
'VAR9
1
;
end
else
begin
VAR22
<=
1
'VAR9
1
;
end
end
VAR8
:
begin
VAR14
<=
1
'VAR9
1
;
VAR10
<=
VAR38
;
end
VAR38
:
begin
if
(
VAR16
==
1
'VAR9
1
)
begin
VAR14
<=
1
'VAR9
0
;
VAR15
<=
1
'VAR9
0
;
if
(
VAR3
==
1
'VAR9
0
)
begin
VAR10
<=
VAR32
;
if
(
VAR31
==
1
'VAR9
1
&
VAR37
==
1
'VAR9
1
&
(
VAR7
[
1
]
)
==
1
'VAR9
1
)
begin
VAR10
<=
VAR8
;
VAR39
<=
VAR18
;
VAR24
<=
VAR6
;
VAR35
<=
VAR6
;
VAR15
<=
1
'VAR9
1
;
end
end
else
begin
VAR42
<=
1
'VAR9
1
;
VAR10
<=
VAR26
;
end
end
end
VAR26
:
begin
VAR42
<=
1
'VAR9
1
;
VAR22
<=
1
'VAR9
1
;
VAR10
<=
VAR32
;
end
endcase
if
(
VAR35
==
1
'VAR9
1
)
begin
VAR36
<=
VAR11
;
end
end
end
always
@
(
VAR39
or
VAR15
)
begin
VAR17
<=
{
16
{
1
'VAR9
0
}
}
;
if
(
VAR15
==
1
'VAR9
1
)
begin
begin
:
VAR27
integer
VAR5
;
for
(
VAR5
=
0
;
VAR5
<=
15
;
VAR5
=
VAR5
+
1
)
begin
VAR17
[
VAR5
]
<=
(
VAR39
[
27
:
24
]
==
VAR5
)
;
end
end
end
end
assign
VAR41
=
(
VAR35
==
1
'VAR9
1
)
?
VAR11
:
VAR36
;
assign
VAR13
VAR19
=
VAR25
;
assign
VAR13
VAR28
=
VAR22
|
(
VAR16
&
VAR15
&
VAR14
&
~
VAR3
)
;
assign
VAR13
VAR33
=
VAR42
;
assign
VAR13
VAR29
=
VAR17
;
assign
VAR13
VAR4
=
VAR39
;
assign
VAR13
VAR20
=
VAR24
;
assign
VAR13
VAR30
=
VAR14
;
assign
VAR13
VAR2
=
VAR41
;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf_6.v | 2,050 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR3,
VAR7,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR6 ;
input VAR3;
input VAR7;
input VAR2 ;
input VAR1 ;
VAR8 VAR5 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR3;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR1 ;
VAR8 VAR5 (
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fa/sky130_fd_sc_ms__fa_1.v | 2,278 | module MODULE1 (
VAR9,
VAR10 ,
VAR4 ,
VAR11 ,
VAR8 ,
VAR2,
VAR6,
VAR5 ,
VAR3
);
output VAR9;
output VAR10 ;
input VAR4 ;
input VAR11 ;
input VAR8 ;
input VAR2;
input VAR6;
input VAR5 ;
input VAR3 ;
VAR7 VAR1 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR9,
VAR10 ,
VAR4 ,
VAR11 ,
VAR8
);
output VAR9;
output VAR10 ;
input VAR4 ;
input VAR11 ;
input VAR8 ;
supply1 VAR2;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
VAR7 VAR1 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR8(VAR8)
);
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_gmultp2_32x32.v | 5,153 | module MODULE1 ( VAR3, VAR7, VAR4, VAR8, VAR6 );
input [VAR11-1:0] VAR3;
input [VAR11-1:0] VAR7;
input VAR4;
input VAR8;
output [VAR9-1:0] VAR6;
reg [VAR9-1:0] VAR2;
reg [VAR9-1:0] VAR1;
integer VAR5;
integer VAR10;
always @(VAR3)
VAR5 <= VAR3;
always @(VAR7)
VAR10 <= VAR7;
always @(posedge VAR4 or posedge VAR8)
if (VAR8)
VAR2 <= VAR9'b0;
else
VAR2 <= VAR5 * VAR10;
always @(posedge VAR4 or posedge VAR8)
if (VAR8)
VAR1 <= VAR9'b0;
else
VAR1 <= VAR2;
assign VAR6 = VAR1;
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/sine_cosine_CORDIC/CORDIC_FSM_v2.v | 8,519 | module MODULE1
(
input wire clk, input wire reset, input wire VAR3, input wire VAR26, input wire VAR24, input wire VAR9,
input wire [1:0] VAR8, input wire [1:0] VAR31, input wire VAR40, input wire VAR20, VAR32, input wire VAR33, VAR47,
output reg VAR37,
output reg VAR38, output reg VAR29, output reg VAR35, output reg VAR39, VAR6, output reg [1:0] VAR30, output reg VAR2, VAR10, output reg VAR1, VAR43, output reg VAR23, VAR27, output reg VAR14, VAR44, VAR11, output reg VAR15,VAR42, output reg VAR49,
output reg VAR41,VAR4,VAR25
);
localparam [3:0] VAR19 = 4'b0000,
VAR34 = 4'b0001,
VAR12 = 4'b0010,
VAR28 = 4'b0011,
VAR48 = 4'b0100,
VAR13 = 4'b0101,
VAR5 = 4'b0110,
VAR45 = 4'b0111,
VAR17 = 4'b1000,
VAR21 = 4'b1001,
VAR36 = 4'b1010,
VAR22 = 4'b1011,
VAR7 = 4'b1100,
VAR46 = 4'b1101;
reg [3:0] VAR16, VAR18;
always @( posedge clk, posedge reset)
begin
if(reset) VAR16 <= VAR19;
end
else VAR16 <= VAR18;
end
always @*
begin
VAR18 = VAR16;
VAR38 = 1'b0;
VAR29 = 1'b0;
VAR35 = 1'b0;
VAR39 = 1'b0;
VAR30 = 2'b00;
VAR6 = 1'b0;
VAR2 = 1'b0;
VAR10 = 1'b0;
VAR1 = 1'b0;
VAR43 = 1'b0;
VAR23 = 1'b0;
VAR27 = 1'b0;
VAR49 = 1'b0;
VAR14 = 1'b0;
VAR44 = 1'b0;
VAR11 = 1'b0;
VAR15 = 1'b0;
VAR37 = 1'b0;
VAR42 = 1'b0;
VAR41 = 1'b0;
VAR4 = 1'b0;
VAR25 = 1'b0;
case(VAR16)
VAR19:
begin
VAR37 = 1'b1;
VAR41 = 1'b1;
VAR4 = 1'b1;
VAR25 = 1'b1;
VAR18 = VAR34;
end
VAR34:
begin
if(VAR3)
begin
VAR18 = VAR12;
end
else
VAR18 = VAR34;
end
VAR12:
begin
VAR23 = 1'b1;
VAR2 = 1'b1;
VAR10 = 1'b1;
VAR18 = VAR28;
end
VAR28:
begin
if(VAR32)
VAR39 = 1'b0;
end
else
VAR39 = 1'b1;
VAR41 = 1'b1;
VAR18 = VAR48;
end
VAR48:
begin
if(VAR9)
VAR18 = VAR19;
end
else
VAR18 = VAR13;
VAR27 = 1'b1;
end
VAR13:
begin
VAR49 = 1'b1;
VAR1 = 1'b1;
VAR43 = 1'b1;
VAR18 = VAR5;
end
VAR5:
begin
if(VAR20)
begin
if(VAR24 == 1'b0)
begin
if(VAR8 == 2'b00)
VAR30 = 2'b00;
end
else if(VAR8 == 2'b01)
VAR30 = 2'b01;
end
else if(VAR8 == 2'b10)
VAR30 = 2'b01;
end
else
VAR30 = 2'b00;
VAR4 = 1'b1;
end
else
begin
if(VAR8 == 2'b00)
VAR30 = 2'b01;
end
else if(VAR8 == 2'b01)
VAR30 = 2'b00;
else if(VAR8 == 2'b10)
VAR30 = 2'b00;
else
VAR30 = 2'b01;
VAR4 = 1'b1;
end
end
else
VAR30 = VAR31;
VAR4 = 1'b1;
VAR18 = VAR45;
end
VAR45:
begin
VAR29 = 1'b1;
VAR18 = VAR17;
end
VAR17:
begin
if(VAR40)
begin
if(VAR20)
begin
if(VAR24 == 1'b0)
begin
if(VAR8 == 2'b00)
VAR14 = 1'b1;
end
else if(VAR8 == 2'b01)
VAR44 = 1'b1;
end
else if(VAR8 == 2'b10)
VAR44 = 1'b1;
end
else
VAR14 = 1'b1;
end
else
begin
if(VAR8 == 2'b00)
VAR44 = 1'b1;
end
else if(VAR8 == 2'b01)
VAR14 = 1'b1;
else if(VAR8 == 2'b10)
VAR14 = 1'b1;
else
VAR44 = 1'b1;
end
end
else
begin
if(VAR47)
VAR14 = 1'b1;
end
else if(VAR33)
VAR11 = 1'b1;
else
VAR44 = 1'b1;
end
VAR18 = VAR21;
end
else
VAR18 = VAR17;
end
VAR21:
begin
VAR35 = 1'b1;
if(VAR20)
begin
VAR18 = VAR36;
end
else
begin
if(VAR33)
begin
VAR2 = 1'b1;
VAR18 = VAR28;
end
else
begin
VAR1 = 1'b1;
VAR18 = VAR5;
end
end
end
VAR36:
begin
if(VAR24 == 1'b0)
begin
if(VAR8 == 2'b00)
VAR6 = 1'b0;
end
else if(VAR8 == 2'b01)
VAR6 = 1'b1;
end
else if(VAR8 == 2'b10)
VAR6 = 1'b1;
else
VAR6 = 1'b0;
VAR25 = 1'b1;
end
else
begin
if(VAR8 == 2'b00)
VAR6 = 1'b1;
end
else if(VAR8 == 2'b01)
VAR6 = 1'b0;
else if(VAR8 == 2'b10)
VAR6 = 1'b0;
else
VAR6 = 1'b1;
VAR25 = 1'b1;
end
VAR25 = 1'b1;
VAR18 = VAR22;
end
VAR22:
begin
VAR42 = 1'b1;
VAR18 = VAR7;
end
VAR7:
begin
VAR15 = 1'b1;
VAR18 = VAR46;
end
VAR46:
begin
VAR38 = 1'b1;
if(VAR26)
VAR18 = VAR19;
end
else
VAR18 = VAR46;
end
default : VAR18 = VAR19;
endcase
end
endmodule | gpl-3.0 |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/micron/ddr/ddr2.v | 130,488 | module MODULE1 (
VAR73,
VAR164,
VAR116,
VAR142,
VAR7,
VAR107,
VAR137,
VAR40,
VAR125,
addr,
VAR130,
VAR132,
VAR55,
VAR34,
VAR99
);
parameter VAR71 = 2500; parameter VAR14 = 100; parameter VAR44 = 100; parameter VAR42 = 200; parameter VAR151 = 150; parameter VAR97 = 175; parameter VAR59 = 200; parameter VAR52 = 200; parameter VAR160 = 300; parameter VAR53 = 450; parameter VAR92 = 300; parameter VAR41 = 400; parameter VAR101 = 50; parameter VAR126 = 125; parameter VAR170 = 350; parameter VAR150 = 200; parameter VAR74 = 0.35; parameter VAR60 = 200; parameter VAR47 = 275; parameter VAR46 = 55000; parameter VAR155 = 12000; parameter VAR103 = 7500; parameter VAR146 = 12500; parameter VAR95 = 8; parameter VAR140 = 12500; else VAR163 VAR80
parameter VAR71 = 2500; parameter VAR14 = 100; parameter VAR44 = 100; parameter VAR42 = 200; parameter VAR151 = 150; parameter VAR97 = 175; parameter VAR59 = 200; parameter VAR52 = 200; parameter VAR160 = 300; parameter VAR53 = 450; parameter VAR92 = 300; parameter VAR41 = 400; parameter VAR101 = 50; parameter VAR126 = 125; parameter VAR170 = 350; parameter VAR150 = 200; parameter VAR74 = 0.35; parameter VAR60 = 200; parameter VAR47 = 275; parameter VAR46 = 55000; parameter VAR155 = 15000; parameter VAR103 = 10000; parameter VAR146 = 15000; parameter VAR95 = 8; parameter VAR140 = 15000; else VAR163 VAR84
parameter VAR71 = 3000; parameter VAR14 = 125; parameter VAR44 = 125; parameter VAR42 = 250; parameter VAR151 = 175; parameter VAR97 = 225; parameter VAR59 = 250; parameter VAR52 = 250; parameter VAR160 = 350; parameter VAR53 = 450; parameter VAR92 = 340; parameter VAR41 = 450; parameter VAR101 = 100; parameter VAR126 = 175; parameter VAR170 = 400; parameter VAR150 = 240; parameter VAR74 = 0.35; parameter VAR60 = 200; parameter VAR47 = 275; parameter VAR46 = 54000; parameter VAR155 = 12000; parameter VAR103 = 7500; parameter VAR146 = 12000; parameter VAR95 = 7; parameter VAR140 = 12000; else VAR163 VAR6
parameter VAR71 = 3000; parameter VAR14 = 125; parameter VAR44 = 125; parameter VAR42 = 250; parameter VAR151 = 175; parameter VAR97 = 225; parameter VAR59 = 250; parameter VAR52 = 250; parameter VAR160 = 350; parameter VAR53 = 450; parameter VAR92 = 340; parameter VAR41 = 450; parameter VAR101 = 100; parameter VAR126 = 175; parameter VAR170 = 400; parameter VAR150 = 240; parameter VAR74 = 0.35; parameter VAR60 = 200; parameter VAR47 = 275; parameter VAR46 = 55000; parameter VAR155 = 15000; parameter VAR103 = 7500; parameter VAR146 = 15000; parameter VAR95 = 7; parameter VAR140 = 15000; else VAR163 VAR13
parameter VAR71 = 3750; parameter VAR14 = 125; parameter VAR44 = 125; parameter VAR42 = 250; parameter VAR151 = 175; parameter VAR97 = 225; parameter VAR59 = 250; parameter VAR52 = 250; parameter VAR160 = 350; parameter VAR53 = 450; parameter VAR92 = 400; parameter VAR41 = 500; parameter VAR101 = 100; parameter VAR126 = 225; parameter VAR170 = 450; parameter VAR150 = 300; parameter VAR74 = 0.25; parameter VAR60 = 250; parameter VAR47 = 375; parameter VAR46 = 55000; parameter VAR155 = 15000; parameter VAR103 = 7500; parameter VAR146 = 15000; parameter VAR95 = 6; parameter VAR140 = 15000; else VAR111 VAR19
parameter VAR71 = 5000; parameter VAR14 = 125; parameter VAR44 = 150; parameter VAR42 = 250; parameter VAR151 = 175; parameter VAR97 = 225; parameter VAR59 = 250; parameter VAR52 = 250; parameter VAR160 = 350; parameter VAR53 = 450; parameter VAR92 = 450; parameter VAR41 = 600; parameter VAR101 = 150; parameter VAR126 = 275; parameter VAR170 = 500; parameter VAR150 = 350; parameter VAR74 = 0.25; parameter VAR60 = 350; parameter VAR47 = 475; parameter VAR46 = 55000; parameter VAR155 = 15000; parameter VAR103 = 10000; parameter VAR146 = 15000; parameter VAR95 = 6; parameter VAR140 = 15000; VAR110 VAR110 VAR110 VAR110 VAR110
parameter VAR27 = 0; parameter VAR169 = 5; parameter VAR134 = 3; parameter VAR56 = 6; parameter VAR79 = 2; parameter VAR82 = 6; parameter VAR128 = 4; parameter VAR149 = 8; parameter VAR66 = 8000; parameter VAR114 = 0.48; parameter VAR45 = 0.52; parameter VAR24 = 0.48; parameter VAR117 = 0.52; parameter VAR158 = VAR41; parameter VAR121 = VAR41; parameter VAR54 = 0.35; parameter VAR65 = 0.35; parameter VAR26 = 0.35; parameter VAR136 = 0.20; parameter VAR38 = 0.20; parameter VAR15 = 0.40; parameter VAR50 = 0.25; parameter VAR104 = 0.6; parameter VAR109 = 2; parameter VAR102 = 40000; parameter VAR138 =70000000; parameter VAR36 = 7500; parameter VAR28 = 15000; parameter VAR16 = 2; parameter VAR159 = 200; parameter VAR120 = 75000; parameter VAR87 =70000000; parameter VAR21 = VAR120 + 10000; parameter VAR113 = 200; parameter VAR91 = VAR60; parameter VAR148 = 2; parameter VAR143 = 2.5; parameter VAR119 = 2000; parameter VAR2 = 2000; parameter VAR145 = 3; parameter VAR133 = 8; parameter VAR123 = 12000; parameter VAR122 = 2; parameter VAR115 = 2; parameter VAR96 = 3;
parameter VAR93 = 1; parameter VAR11 = 13; parameter VAR67 = 13; parameter VAR77 = 11; parameter VAR94 = 4; parameter VAR61 = 1; parameter VAR139 = 7500; parameter VAR72 = 37500; else VAR163 VAR153
parameter VAR93 = 1; parameter VAR11 = 13; parameter VAR67 = 13; parameter VAR77 = 10; parameter VAR94 = 8; parameter VAR61 = 1; parameter VAR139 = 7500; parameter VAR72 = 37500; else VAR111 VAR83
parameter VAR93 = 2; parameter VAR11 = 13; parameter VAR67 = 13; parameter VAR77 = 9; parameter VAR94 = 16; parameter VAR61 = 2; parameter VAR139 = 10000; parameter VAR72 = 50000; VAR110 VAR110
parameter VAR112 = 2; parameter VAR68 = 10; parameter VAR85 = 10; parameter VAR17 = 3; parameter VAR105 = 2;
parameter VAR165 = 1; parameter VAR4 = 0; parameter VAR23 = 0; parameter VAR154 = 0; parameter VAR144 = 711689044;
parameter VAR33 = 2; parameter VAR22 = 1; parameter VAR88 = 2; parameter VAR156 = 1; parameter VAR31 = 0; parameter VAR25 = 0; parameter VAR81 = 1; parameter VAR32 = 1; VAR111 VAR162 VAR94/VAR61
input VAR73;
input VAR164;
input VAR116;
input VAR142;
input VAR7;
input VAR107;
input VAR137;
inout [VAR93-1:0] VAR40;
input [VAR112-1:0] VAR125;
input [VAR11-1:0] addr;
inout [VAR94-1:0] VAR130;
inout [VAR61-1:0] VAR132;
inout [VAR61-1:0] VAR55;
output [VAR61-1:0] VAR34;
input VAR99;
real VAR12;
VAR157 VAR98 [VAR159-1:0];
VAR157 VAR129 [VAR159-1:0];
VAR157 VAR5 [VAR159-1:0];
VAR157 VAR147;
VAR157 VAR86;
VAR157 VAR76;
real VAR29;
real VAR78;
VAR157 VAR30;
VAR157 VAR51;
real VAR3;
integer VAR70;
real VAR10;
real VAR69;
integer VAR100 [VAR61-1:0];
integer VAR48;
integer VAR58;
integer VAR166;
integer VAR64;
integer VAR135;
reg VAR167;
reg [VAR17:0] VAR152;
integer VAR20;
integer VAR124;
reg VAR62;
reg VAR161;
reg VAR57;
integer VAR127;
reg VAR131;
reg [1:0] VAR37;
reg VAR35;
reg [2:0] VAR75;
reg VAR63;
reg VAR118;
reg VAR43;
integer VAR141;
integer VAR90;
parameter
VAR89 = 4'b0000,
VAR9 = 4'b0001,
VAR108 = 4'b0010,
VAR8 = 4'b0011,
VAR49 = 4'b0100,
VAR168 = 4'b0101,
VAR39 = 4'b0111,
VAR18 = 4'b1000,
VAR1 = 4'b1001
;
reg [8*9-1:0] VAR106 [9:0];
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | mit |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/tc_router_wrap.v | 16,029 | module MODULE1
(clk, reset, VAR42, VAR99, VAR90, VAR23, VAR72,
VAR93, VAR84, VAR61);
localparam VAR144 = VAR122 * VAR76;
localparam VAR97 = VAR144 * VAR69;
localparam VAR57 = VAR110(VAR97);
localparam VAR41
= (VAR100 + VAR27 - 1) / VAR27;
localparam VAR68 = VAR50(VAR41, VAR35);
localparam VAR107 = VAR110(VAR68);
localparam VAR127 = VAR35 * VAR107;
localparam VAR22 = VAR110(VAR27);
localparam VAR121 = VAR127 + VAR22;
localparam VAR65
= (VAR58 == VAR140) ?
(VAR58 == VAR87) ?
(VAR58 == VAR19) ?
-1;
localparam VAR34
= ((VAR65 == VAR103) ||
(VAR65 == VAR142)) ?
2 :
(VAR65 == VAR89) ?
(VAR68 - 1) :
-1;
localparam VAR104
= VAR35 * VAR34 + VAR27;
localparam VAR43
= (VAR7 == VAR115) ?
(1 + VAR57 + 1 + 1) :
(VAR7 == VAR53) ?
(1 + VAR57 + 1) :
-1;
localparam VAR123 = 1 + VAR57;
parameter VAR109 = 0;
parameter VAR49 = 10;
parameter VAR108 = 6;
localparam VAR48 = VAR49 + VAR108;
parameter VAR120 = 32;
localparam VAR21 = VAR49;
localparam VAR26 = VAR108;
localparam VAR4 = VAR21 + VAR26;
localparam VAR78 = VAR120;
parameter VAR1 = 16;
parameter VAR125 = 16;
parameter VAR95 = 4;
parameter VAR86 = 4;
parameter VAR128 = 4;
parameter VAR16 = 2;
parameter VAR64 = 8;
parameter VAR45 = 6;
localparam VAR12 = 2 + 2;
localparam VAR6 = 1 + VAR104;
parameter VAR46 = 1;
input clk;
input reset;
input [0:VAR21-1] VAR42;
input VAR99;
input VAR90;
input [0:VAR4-1] VAR23;
input [0:VAR78-1] VAR72;
output [0:VAR78-1] VAR93;
wire [0:VAR78-1] VAR93;
output VAR84;
wire VAR84;
output VAR61;
wire VAR61;
wire [0:VAR127-1] VAR11;
genvar VAR116;
generate
for(VAR116 = 0; VAR116 < VAR35; VAR116 = VAR116 + 1)
begin:VAR94
assign VAR11[VAR116*VAR107:(VAR116+1)*VAR107-1]
= VAR68 / 2;
end
endgenerate
wire [0:VAR49-1] VAR145;
assign VAR145 = VAR42;
wire VAR146;
wire VAR37;
wire [0:VAR48-1] VAR8;
wire [0:VAR120-1] VAR66;
wire [0:VAR120-1] VAR148;
wire VAR56;
wire [0:VAR12-1] VAR117;
wire [0:VAR6-1] VAR54;
VAR15
.VAR108(VAR108),
.VAR133(1),
.VAR120(VAR120),
.VAR45(VAR45),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR55(VAR55))
VAR73
(.clk(clk),
.reset(reset),
.VAR99(VAR99),
.VAR90(VAR90),
.VAR23(VAR23),
.VAR72(VAR72),
.VAR93(VAR93),
.VAR84(VAR84),
.VAR10(VAR145),
.VAR146(VAR146),
.VAR37(VAR37),
.VAR8(VAR8),
.VAR66(VAR66),
.VAR148(VAR148),
.VAR56(VAR56),
.VAR117(VAR117),
.VAR54(VAR54));
wire VAR101;
assign VAR101 = VAR117[0];
wire VAR113;
assign VAR113 = reset | ~VAR101;
wire VAR85;
assign VAR85 = VAR117[1];
wire VAR98;
assign VAR98 = clk & VAR85;
wire VAR38;
assign VAR38 = VAR117[2];
wire VAR141;
assign VAR141 = reset | ~VAR38;
wire VAR80;
assign VAR80 = VAR117[3];
wire VAR3;
assign VAR3 = clk & VAR80;
wire [0:VAR104*VAR43-1] VAR91;
wire [0:VAR104*VAR36-1] VAR88;
wire [0:VAR104*VAR123-1] VAR13;
wire [0:VAR104*VAR43-1] VAR79;
wire [0:VAR104*VAR36-1] VAR39;
wire [0:VAR104*VAR123-1] VAR135;
wire [0:VAR104*VAR120-1] VAR81;
wire [0:VAR104-1] VAR60;
wire [0:VAR104-1] VAR67;
genvar VAR30;
generate
for(VAR30 = 0; VAR30 < VAR104; VAR30 = VAR30 + 1)
begin:VAR51
wire [0:VAR43-1] VAR132;
assign VAR132
= VAR79[VAR30*VAR43:
(VAR30+1)*VAR43-1];
wire [0:VAR36-1] VAR71;
assign VAR71
= VAR39[VAR30*VAR36:
(VAR30+1)*VAR36-1];
wire [0:VAR123-1] VAR137;
assign VAR137
= VAR135[VAR30*VAR123:
(VAR30+1)*VAR123-1];
wire [0:2*VAR49-1] VAR143;
assign VAR143[0:VAR49-1]
= VAR42 + VAR30 + 1;
assign VAR143[VAR49:
2*VAR49-1]
= VAR42 + VAR104 + 1;
wire [0:VAR43-1] VAR118;
wire [0:VAR36-1] VAR75;
wire [0:VAR123-1] VAR124;
wire [0:VAR120-1] VAR148;
wire VAR56;
wire VAR149;
if(VAR30 >= (VAR104 - VAR27))
begin
wire [0:VAR121-1] address;
assign address[0:VAR127-1] = VAR11;
if(VAR27 > 1)
assign address[VAR127:VAR121-1]
= (VAR30 - (VAR104 - VAR27));
VAR47
.VAR2(VAR2),
.VAR122(VAR122),
.VAR76(VAR76),
.VAR69(VAR69),
.VAR68(VAR68),
.VAR35(VAR35),
.VAR27(VAR27),
.VAR65(VAR65),
.VAR7(VAR7),
.VAR52(VAR52),
.VAR40(VAR40),
.VAR36(VAR36),
.VAR74(VAR74),
.VAR63(VAR63),
.VAR9(VAR9),
.VAR109( VAR109 ),
.VAR49(VAR49),
.VAR108(VAR108),
.VAR133(2),
.VAR120(VAR120),
.VAR1(VAR1),
.VAR125(VAR125),
.VAR95(VAR95),
.VAR86(VAR86),
.VAR128(VAR128),
.VAR16(VAR16),
.VAR64(VAR64),
.VAR55(VAR55))
VAR106
(.clk(VAR98),
.reset(VAR113),
.address(address),
.VAR118(VAR118),
.VAR75(VAR75),
.VAR137(VAR137),
.VAR132(VAR132),
.VAR71(VAR71),
.VAR124(VAR124),
.VAR10(VAR143),
.VAR146(VAR146),
.VAR37(VAR37),
.VAR8(VAR8),
.VAR66(VAR66),
.VAR148(VAR148),
.VAR56(VAR56),
.VAR61(VAR149));
end
else
begin
assign VAR118 = {VAR43{1'b0}};
assign VAR75 = {VAR36{1'b0}};
wire [0:VAR43-1] VAR77;
VAR24
.VAR92(VAR46),
.VAR55(VAR55))
VAR5
(.clk(clk),
.reset(reset),
.enable(1'b1),
.VAR139(VAR132),
.VAR32(VAR77));
assign VAR124 = VAR77[0:VAR123-1];
assign VAR148 = {VAR120{1'b0}};
assign VAR56 = 1'b0;
assign VAR149 = 1'b0;
end
assign VAR91[VAR30*VAR43:
(VAR30+1)*VAR43-1]
= VAR118;
assign VAR88[VAR30*VAR36:
(VAR30+1)*VAR36-1]
= VAR75;
assign VAR13[VAR30*VAR123:
(VAR30+1)*VAR123-1]
= VAR124;
assign VAR81[VAR30*VAR120:(VAR30+1)*VAR120-1]
= VAR148;
assign VAR60[VAR30] = VAR56;
assign VAR67[VAR30] = VAR149;
end
endgenerate
wire VAR31;
VAR126
.VAR59(VAR59),
.VAR2(VAR2),
.VAR122(VAR122),
.VAR76(VAR76),
.VAR69(VAR69),
.VAR100(VAR100),
.VAR35(VAR35),
.VAR27(VAR27),
.VAR7(VAR7),
.VAR52(VAR52),
.VAR40(VAR40),
.VAR29(VAR29),
.VAR25(VAR25),
.VAR74(VAR74),
.VAR70(VAR70),
.VAR114(VAR114),
.VAR36(VAR36),
.VAR9(VAR9),
.VAR129(VAR129),
.VAR17(VAR17),
.VAR130(VAR130),
.VAR147(VAR147),
.VAR102(VAR102),
.VAR136(VAR136),
.VAR138(VAR138),
.VAR14(VAR14),
.VAR44(VAR44),
.VAR62(VAR62),
.VAR55(VAR55))
VAR33
(.clk(VAR3),
.reset(VAR141),
.VAR11(VAR11),
.VAR18(VAR91),
.VAR83(VAR88),
.VAR119(VAR135),
.VAR111(VAR79),
.VAR131(VAR39),
.VAR105(VAR13),
.VAR61(VAR31));
VAR96
.VAR20(VAR120))
VAR134
(.select(VAR60),
.VAR139(VAR81),
.VAR32(VAR148));
VAR112
.VAR20(1))
VAR82
(.VAR139(VAR60),
.VAR32(VAR56));
wire [0:VAR104] VAR28;
assign VAR28 = {VAR31, VAR67};
assign VAR61 = |VAR28;
assign VAR54 = VAR28;
endmodule | mit |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/IDEX_Stage.v | 9,120 | module MODULE1(
input VAR39,
input reset,
input VAR96,
input VAR72,
input VAR1,
input VAR45,
input VAR59,
input VAR76,
input [4:0] VAR100,
input VAR77,
input VAR9,
input VAR18,
input VAR95,
input VAR40,
input VAR35,
input VAR10,
input VAR32,
input VAR73,
input VAR29,
input VAR11,
input VAR46,
input VAR63,
input [4:0] VAR31,
input [4:0] VAR87,
input VAR75,
input VAR8,
input VAR67,
input VAR94,
input VAR3,
input [31:0] VAR106,
input VAR28,
input VAR62,
input VAR83,
input VAR102,
input VAR12,
input [31:0] VAR88,
input [31:0] VAR34,
input [16:0] VAR41, output [4:0] VAR42,
output [4:0] VAR71,
output [1:0] VAR2,
output [31:0] VAR86,
input [16:0] VAR80,
input VAR74,
input VAR65,
input VAR53,
input [4:0] VAR55,
input VAR103,
input VAR44,
input VAR69,
input VAR82,
input VAR20,
input VAR25,
input VAR61,
input VAR22,
input VAR23,
input VAR66,
input VAR68,
input VAR6,
input VAR60,
input [4:0] VAR21,
input [4:0] VAR92,
input VAR38,
input VAR97,
input VAR64,
input VAR99,
input VAR93,
input [31:0] VAR14,
input VAR85,
input VAR98,
input VAR81,
input VAR78,
input VAR101,
input [31:0] VAR26,
input [31:0] VAR52,
output reg [16:0] VAR58,
output reg VAR15,
output reg VAR49,
output reg VAR104,
output reg [4:0] VAR70,
output reg VAR19,
output reg VAR50,
output reg VAR107,
output reg VAR91,
output reg VAR51,
output reg VAR84,
output reg VAR79,
output reg VAR30,
output reg VAR5,
output reg VAR47,
output reg VAR17,
output reg VAR16,
output reg VAR89,
output reg [4:0] VAR36,
output reg [4:0] VAR13,
output reg VAR37,
output reg VAR57,
output reg VAR33,
output reg VAR7,
output reg VAR24,
output reg [31:0] VAR54,
output reg VAR48,
output reg VAR4,
output reg VAR27,
output reg VAR43,
output reg VAR90,
output reg [31:0] VAR105,
output reg [31:0] VAR56
);
assign VAR2 = (VAR65) ? 2'b10 : ((VAR74) ? 2'b01 : 2'b00);
assign VAR42 = VAR86[15:11];
assign VAR71 = VAR86[10:6];
assign VAR86 = (VAR80[16]) ? {15'h7fff, VAR80[16:0]} : {15'h0000, VAR80[16:0]};
always @(posedge VAR39) begin
VAR49 <= (reset) ? 1'b0 : ((VAR1) ? VAR65 : VAR45);
VAR15 <= (reset) ? 1'b0 : ((VAR1) ? VAR74 : VAR59);
VAR104 <= (reset) ? 1'b0 : ((VAR1) ? VAR53 : VAR76);
VAR70 <= (reset) ? 5'b0 : ((VAR1) ? VAR55 : ((VAR72 | VAR96) ? 5'b0 : VAR100));
VAR19 <= (reset) ? 1'b0 : ((VAR1) ? VAR103 : VAR77);
VAR50 <= (reset) ? 1'b0 : ((VAR1) ? VAR44 : VAR9);
VAR107 <= (reset) ? 1'b0 : ((VAR1) ? VAR69 : VAR18);
VAR91 <= (reset) ? 1'b0 : ((VAR1) ? VAR82 : ((VAR72 | VAR96) ? 1'b0 : VAR95));
VAR51 <= (reset) ? 1'b0 : ((VAR1) ? VAR20 : ((VAR72 | VAR96) ? 1'b0 : VAR40));
VAR84 <= (reset) ? 1'b0 : ((VAR1) ? VAR25 : VAR35);
VAR79 <= (reset) ? 1'b0 : ((VAR1) ? VAR61 : VAR10);
VAR30 <= (reset) ? 1'b0 : ((VAR1) ? VAR22 : VAR32);
VAR5 <= (reset) ? 1'b0 : ((VAR1) ? VAR23 : VAR73);
VAR47 <= (reset) ? 1'b0 : ((VAR1) ? VAR66 : VAR29);
VAR17 <= (reset) ? 1'b0 : ((VAR1) ? VAR68 : ((VAR72 | VAR96) ? 1'b0 : VAR11));
VAR16 <= (reset) ? 1'b0 : ((VAR1) ? VAR6 : VAR46);
VAR89 <= (reset) ? 1'b0 : ((VAR1) ? VAR60 : VAR63);
VAR54 <= (reset) ? 32'b0 : ((VAR1) ? VAR14 : VAR106);
VAR48 <= (reset) ? 1'b0 : ((VAR1) ? VAR85 : VAR28);
VAR4 <= (reset) ? 1'b0 : ((VAR1) ? VAR98 : ((VAR72 | VAR96) ? 1'b0 : VAR62));
VAR27 <= (reset) ? 1'b0 : ((VAR1) ? VAR81 : VAR83);
VAR43 <= (reset) ? 1'b0 : ((VAR1) ? VAR78 : ((VAR72 | VAR96) ? 1'b0 : VAR102));
VAR90 <= (reset) ? 1'b0 : ((VAR1) ? VAR101 : ((VAR72 | VAR96) ? 1'b0 : VAR12));
VAR105 <= (reset) ? 32'b0 : ((VAR1) ? VAR26 : VAR88);
VAR56 <= (reset) ? 32'b0 : ((VAR1) ? VAR52 : VAR34);
VAR58 <= (reset) ? 17'b0 : ((VAR1) ? VAR80 : VAR41);
VAR36 <= (reset) ? 5'b0 : ((VAR1) ? VAR21 : VAR31);
VAR13 <= (reset) ? 5'b0 : ((VAR1) ? VAR92 : VAR87);
VAR37 <= (reset) ? 1'b0 : ((VAR1) ? VAR38 : ((VAR72 | VAR96) ? 1'b0 : VAR75));
VAR57 <= (reset) ? 1'b0 : ((VAR1) ? VAR97 : ((VAR72 | VAR96) ? 1'b0 : VAR8));
VAR33 <= (reset) ? 1'b0 : ((VAR1) ? VAR64 : ((VAR72 | VAR96) ? 1'b0 : VAR67));
VAR7 <= (reset) ? 1'b0 : ((VAR1) ? VAR99 : ((VAR72 | VAR96) ? 1'b0 : VAR94));
VAR24 <= (reset) ? 1'b0 : ((VAR1) ? VAR93 : VAR3);
end
endmodule | lgpl-3.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter_001.v | 6,161 | module MODULE1 #(
parameter VAR5 = 34,
parameter VAR22 = 0,
parameter VAR14 = 34,
parameter VAR16 = 0,
parameter VAR25 = 0,
parameter VAR20 = 0,
parameter VAR13 = 1,
parameter VAR3 = 1,
parameter VAR21 = 0,
parameter VAR23 = 34,
parameter VAR10 = 0,
parameter VAR1 = 1,
parameter VAR9 = 0,
parameter VAR2 = 1,
parameter VAR6 = 1,
parameter VAR11 = 0
) (
input wire VAR18, input wire VAR7, input wire [33:0] VAR24, input wire VAR17, output wire VAR4, output wire [33:0] VAR15, output wire VAR12, input wire VAR8, output wire [0:0] VAR19 );
generate
if (VAR5 != 34)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/xess_top.v | 10,094 | module MODULE1 (
);
VAR46 VAR30();
VAR10 VAR10();
VAR60 VAR60();
reg VAR20;
reg VAR33;
wire VAR38;
wire clk;
wire [31:0] VAR31;
wire [31:0] VAR27;
wire VAR76;
wire VAR59;
wire VAR52;
wire VAR45;
wire VAR1;
wire VAR5;
wire [7:0] VAR73;
wire [20:0] VAR56;
wire [31:0] VAR68; wire [31:0] VAR36; wire [1:0] VAR40; wire VAR77;
wire VAR79;
wire VAR9;
wire VAR63;
wire [18:0] VAR41;
wire [15:0] VAR54;
wire VAR50;
wire VAR65;
wire VAR23;
wire VAR78;
wire [18:0] VAR13;
wire [15:0] VAR24;
wire VAR57;
wire VAR8;
wire VAR75;
wire VAR25;
wire VAR43;
wire VAR29;
wire VAR47;
wire [1:0] VAR2;
wire [1:0] VAR61;
wire [1:0] VAR21;
wire VAR22;
wire VAR18;
wire VAR55;
wire [4:0] VAR39;
wire VAR12;
wire VAR3;
wire VAR81;
wire [4:0] VAR49;
wire VAR28;
wire VAR17;
wire VAR67;
wire VAR35;
wire VAR74;
wire VAR58;
wire [2:1] VAR42;
wire VAR4;
wire VAR15;
wire VAR48;
wire VAR26;
wire VAR62;
wire VAR14;
wire VAR19;
wire [6:3] VAR6;
VAR44 VAR11(
.clk( clk ),
.VAR38( VAR38 ),
.VAR31( VAR31 ),
.VAR27( VAR27 ),
.VAR76( VAR76 ),
.VAR59( VAR59 ),
.VAR45( VAR45 ),
.VAR52( VAR52 ),
.VAR1( VAR1 ),
.VAR5( VAR5 ),
.VAR73( VAR73 ),
.VAR56( VAR56 ),
.VAR77( VAR77 ),
.VAR63( VAR63 ),
.VAR79( VAR79 ),
.VAR9( VAR9 ),
.VAR54( VAR54 ),
.VAR41( VAR41 ),
.VAR50( VAR50 ),
.VAR78( VAR78 ),
.VAR65( VAR65 ),
.VAR23( VAR23 ),
.VAR24( VAR24 ),
.VAR13( VAR13 ),
.VAR51( VAR42 ),
.VAR69(1'b0),
.VAR53(1'b0),
.VAR70()
);
VAR71 VAR71(
VAR64 VAR71(
.VAR66(VAR48),
.VAR37(VAR26),
.VAR80(VAR62),
.VAR72(VAR14),
.VAR34(VAR19)
);
assign VAR48 = 1'b0;
assign VAR26 = 1'b0;
assign VAR62 = VAR38;
assign VAR14 = 1'b0;
assign VAR18 = 1'b0;
assign VAR12 = 1'b0;
assign VAR3 = 1'b0;
assign VAR81 = 1'b0;
assign VAR49 = 5'b0;
assign VAR28= 1'b0;
assign VAR17 = 1'b0;
assign VAR35 = 1'b0;
assign VAR74 = 1'VAR32;
assign VAR42 = 2'b0;
assign VAR7 = 1'b0;
assign VAR16 = 1'b0;
begin
begin | gpl-3.0 |
samyk/proxmark3 | fpga/fpga_lf.v | 8,629 | module MODULE1(
input VAR17, output VAR62, input VAR56, input VAR64,
input VAR93, input VAR91, input VAR74,
output VAR90, output VAR89,
output VAR28, output VAR26, output VAR23, output VAR61,
input [7:0] VAR1, output VAR40, output VAR55,
output VAR45, output VAR20, input VAR78, output VAR63,
input VAR32, input VAR92,
output VAR41
);
reg [15:0] VAR27;
reg [7:0] VAR50;
reg [7:0] VAR54;
reg [11:0] VAR75;
wire [2:0] VAR73 = VAR75[8:6];
wire VAR48 = VAR75[0];
wire VAR82 = VAR75[1];
always @(posedge VAR64)
begin
case (VAR27[15:12])
begin
VAR75 <= VAR27[11:0];
if (VAR27[8:6] == VAR37)
begin
VAR54 <= 127; end
end
VAR50 <= VAR27[7:0];
VAR54 <= VAR27[7:0]; endcase
end
always @(posedge VAR17)
begin
if (~VAR64)
begin
VAR27[15:1] <= VAR27[14:0];
VAR27[0] <= VAR56;
end
end
wire [7:0] VAR13;
wire VAR76;
VAR69 VAR31(VAR93, VAR50, VAR13, VAR76);
VAR68 VAR36(
VAR93, VAR13, VAR76,
VAR67, VAR12, VAR9, VAR51, VAR18, VAR47,
VAR1, VAR29,
VAR86, VAR35, VAR42,
VAR84, VAR48
);
VAR65 VAR2(
VAR76,
VAR87, VAR66, VAR10, VAR25, VAR53, VAR8,
VAR33,
VAR43, VAR78,
VAR92,
VAR72
);
VAR5 VAR88(
VAR93, VAR76,
VAR34, VAR52, VAR57, VAR58, VAR38, VAR19,
VAR1, VAR21,
VAR70, VAR78, VAR11,
VAR92,
VAR7,
VAR48,
VAR82, VAR54
);
VAR77 VAR94(
VAR93,
VAR46, VAR79, VAR15, VAR81, VAR83, VAR71,
VAR1, VAR3,
VAR96, VAR85, VAR78, VAR49,
VAR30, VAR50,
VAR48
);
VAR14 VAR24 (VAR73, VAR63, VAR42, VAR11, 1'b0, VAR49, 1'b0, 1'b0, 1'b0, 1'b0);
VAR14 VAR4 (VAR73, VAR20, VAR35, 1'b0, VAR43, VAR85, 1'b0, 1'b0, 1'b0, 1'b0);
VAR14 VAR59 (VAR73, VAR45, VAR86, VAR70, 1'b0, VAR96, 1'b0, 1'b0, 1'b0, 1'b0);
VAR14 VAR95 (VAR73, VAR28, VAR9, VAR57, VAR10, VAR15, 1'b0, 1'b0, 1'b0, 1'b0);
VAR14 VAR44 (VAR73, VAR26, VAR51, VAR58, VAR25, VAR81, 1'b0, 1'b0, 1'b0, 1'b0);
VAR14 VAR22 (VAR73, VAR23, VAR18, VAR38, VAR53, VAR83, 1'b0, 1'b0, 1'b0, 1'b0);
VAR14 VAR39 (VAR73, VAR61, VAR47, VAR19, VAR8, VAR71, 1'b0, 1'b0, 1'b0, 1'b0);
VAR14 VAR16 (VAR73, VAR90, VAR67, VAR34, VAR87, VAR46, 1'b0, 1'b0, 1'b1, 1'b0);
VAR14 VAR80 (VAR73, VAR89, VAR12, VAR52, VAR66, VAR79, 1'b0, 1'b0, 1'b0, 1'b0);
VAR14 VAR60 (VAR73, VAR40, VAR29, VAR21, VAR33, VAR3, 1'b0, 1'b0, 1'b0, 1'b0);
VAR14 VAR6 (VAR73, VAR41, VAR84, VAR7, VAR72, VAR30, 1'b0, 1'b0, 1'b0, 1'b0);
assign VAR55 = 1'b0;
endmodule | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_gmii_to_rgmii/mdc_mdio.v | 4,037 | module MODULE1 (
VAR10,
VAR7,
VAR5,
VAR8,
VAR13);
parameter VAR11 = 5'b10000;
input VAR10;
input VAR7;
input VAR5;
output [ 1:0] VAR8;
output VAR13;
localparam VAR12 = 2'b01;
localparam VAR6 = 2'b10;
wire VAR3;
reg [ 1:0] VAR4 = VAR12;
reg [ 1:0] VAR14 = VAR12;
reg [31:0] VAR1 = 32'h0;
reg [31:0] VAR9 = 32'h0;
reg [ 5:0] VAR2 = 6'h0;
reg [ 1:0] VAR8 = 2'h0;
reg VAR13 = 1'h0;
assign VAR3 = &VAR1;
always @(posedge VAR10) begin
VAR4 <= VAR14;
VAR1 <= {VAR1[30:0], VAR7};
if (VAR4 == VAR6) begin
VAR2 <= VAR2 + 1;
end else begin
VAR2 <= 0;
end
if (VAR2 == 6'h1f) begin
if (VAR1[31] == 1'b0 && VAR1[29:28]==2'b10 && VAR1[27:23] == VAR11 && VAR1[22:18] == 5'h11) begin
VAR8 <= VAR9[16:15] ;
VAR13 <= VAR9[14];
end
end
end
always @(negedge VAR10) begin
VAR9 <= {VAR9[30:0], VAR5};
end
always @(*) begin
case (VAR4)
VAR12: begin
if (VAR3 == 1 && VAR7 == 0) begin
VAR14 <= VAR6;
end else begin
VAR14 <= VAR12;
end
end
VAR6: begin
if (VAR2 == 6'h1f) begin
VAR14 <= VAR12;
end else begin
VAR14 <= VAR6;
end
end
default: begin
VAR14 <= VAR12;
end
endcase
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn.pp.symbol.v | 1,428 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR2,
input VAR4 ,
input VAR8 ,
input VAR5 ,
input VAR1 ,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp.behavioral.pp.v | 2,235 | module MODULE1 (
VAR14 ,
VAR7 ,
VAR13 ,
VAR5,
VAR8 ,
VAR19
);
input VAR14 ;
input VAR7 ;
output VAR13 ;
input VAR5;
input VAR8 ;
input VAR19 ;
wire VAR16 ;
reg VAR15 ;
wire VAR18 ;
wire VAR4 ;
wire VAR3 ;
wire VAR6;
wire VAR1 ;
wire VAR12 ;
wire VAR11 ;
wire VAR9 ;
not VAR17 (VAR16 , VAR6 );
VAR2 VAR10 (VAR1 , VAR18, VAR4, VAR16, VAR15, VAR14, VAR7);
assign VAR12 = ( VAR14 === 1'b1 );
assign VAR11 = ( VAR12 && ( VAR6 === 1'b1 ) );
assign VAR9 = ( VAR12 && ( VAR5 === 1'b1 ) );
buf VAR20 (VAR13 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/diode/sky130_fd_sc_hs__diode.behavioral.v | 1,177 | module MODULE1 (
VAR5
);
input VAR5;
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
tanelikaivola/blinkenlichten | fpga/sr_timer.v | 1,412 | module MODULE1 #(VAR1 = 8)
(
input VAR2,
input VAR8,
input VAR7,
output reg VAR6 = 0
);
reg [VAR3(VAR1)-1:0] VAR5 = 0;
reg VAR9 = 0;
always @(posedge VAR7) begin
if(VAR8) begin
VAR6 <= 0;
VAR5 <= 0;
VAR9 <= 0;
end else if(VAR2 & !VAR9) begin
VAR6 <= 1;
VAR9 <= 1;
end else if(VAR9) begin
VAR5 <= VAR5 + 1;
if(VAR5+1 == VAR1) begin
VAR9 <= 0;
VAR6 <= 0;
VAR5 <= 0;
end
end
end
endmodule
module MODULE2 #(VAR4 = 8)
(
input VAR2,
input VAR8,
input VAR7,
input [VAR4-1:0] VAR1,
output reg VAR6 = 0
);
reg [VAR4-1:0] VAR5 = 0;
reg VAR9 = 0;
always @(posedge VAR7) begin
if(VAR8) begin
VAR6 <= 0;
VAR5 <= 0;
VAR9 <= 0;
end else if(VAR2 & !VAR9) begin
VAR6 <= 1;
VAR9 <= 1;
end else if(VAR9) begin
VAR5 <= VAR5 + 1;
if(VAR5+1 == VAR1) begin
VAR9 <= 0;
VAR6 <= 0;
VAR5 <= 0;
end
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai.pp.blackbox.v | 1,433 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR4 ,
VAR8 ,
VAR9 ,
VAR10 ,
VAR6,
VAR1,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR10 ;
input VAR6;
input VAR1;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s.functional.v | 1,342 | module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
wire VAR2;
buf VAR4 (VAR2, VAR1 );
buf VAR5 (VAR3 , VAR2 );
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_41.v | 27,415 | module MODULE1 (
clk,
reset,
VAR87,
VAR154,
VAR215,
VAR104,
VAR3
);
parameter VAR74 = 18;
parameter VAR22 = 41;
parameter VAR28 = 21;
localparam VAR174 = 42;
input clk;
input reset;
input VAR87;
input VAR154;
input [VAR74-1:0] VAR215; output VAR104;
output [VAR74-1:0] VAR3;
localparam VAR138 = 18; localparam VAR110 = 36; localparam VAR116 = 17;
localparam VAR241 = 41;
reg [VAR74-1:0] VAR117;
reg [VAR74-1:0] VAR218;
reg [VAR74-1:0] VAR181;
reg [VAR74-1:0] VAR119;
reg [VAR74-1:0] VAR213;
reg [VAR74-1:0] VAR23;
reg [VAR74-1:0] VAR113;
reg [VAR74-1:0] VAR158;
reg [VAR74-1:0] VAR246;
reg [VAR74-1:0] VAR209;
reg [VAR74-1:0] VAR122;
reg [VAR74-1:0] VAR231;
reg [VAR74-1:0] VAR83;
reg [VAR74-1:0] VAR125;
reg [VAR74-1:0] VAR179;
reg [VAR74-1:0] VAR224;
reg [VAR74-1:0] VAR153;
reg [VAR74-1:0] VAR249;
reg [VAR74-1:0] VAR96;
reg [VAR74-1:0] VAR105;
reg [VAR74-1:0] VAR235;
always@(posedge clk) begin
VAR117 <= 18'd88;
VAR218 <= 18'd0;
VAR181 <= -18'd97;
VAR119 <= -18'd197;
VAR213 <= -18'd294;
VAR23 <= -18'd380;
VAR113 <= -18'd447;
VAR158 <= -18'd490;
VAR246 <= -18'd504;
VAR209 <= -18'd481;
VAR122 <= -18'd420;
VAR231 <= -18'd319;
VAR83 <= -18'd178;
VAR125 <= 18'd0;
VAR179 <= 18'd212;
VAR224 <= 18'd451;
VAR153 <= 18'd710;
VAR249 <= 18'd980;
VAR96 <= 18'd1252;
VAR105 <= 18'd1514;
VAR235 <= 18'd1756;
end
reg [VAR174-1:0] VAR167;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR167 <= 0;
end else begin
if(VAR87) begin
VAR167 <= {VAR167[VAR174-2:0], VAR154};
end else begin
VAR167 <= VAR167;
end
end
end
wire [VAR74-1:0] VAR58;
wire [VAR74-1:0] VAR54;
wire [VAR74-1:0] VAR35;
wire [VAR74-1:0] VAR148;
wire [VAR74-1:0] VAR196;
wire [VAR74-1:0] VAR216;
wire [VAR74-1:0] VAR46;
wire [VAR74-1:0] VAR43;
wire [VAR74-1:0] VAR127;
wire [VAR74-1:0] VAR248;
wire [VAR74-1:0] VAR165;
wire [VAR74-1:0] VAR61;
wire [VAR74-1:0] VAR106;
wire [VAR74-1:0] VAR2;
wire [VAR74-1:0] VAR193;
wire [VAR74-1:0] VAR131;
wire [VAR74-1:0] VAR79;
wire [VAR74-1:0] VAR144;
wire [VAR74-1:0] VAR183;
wire [VAR74-1:0] VAR98;
wire [VAR74-1:0] VAR52;
wire [VAR74-1:0] VAR115;
wire [VAR74-1:0] VAR20;
wire [VAR74-1:0] VAR67;
wire [VAR74-1:0] VAR208;
wire [VAR74-1:0] VAR51;
wire [VAR74-1:0] VAR238;
wire [VAR74-1:0] VAR12;
wire [VAR74-1:0] VAR166;
wire [VAR74-1:0] VAR99;
wire [VAR74-1:0] VAR130;
wire [VAR74-1:0] VAR16;
wire [VAR74-1:0] VAR71;
wire [VAR74-1:0] VAR232;
wire [VAR74-1:0] VAR120;
wire [VAR74-1:0] VAR156;
wire [VAR74-1:0] VAR34;
wire [VAR74-1:0] VAR86;
wire [VAR74-1:0] VAR233;
wire [VAR74-1:0] VAR73;
wire [VAR74-1:0] VAR194;
MODULE3 MODULE11(
.clk(clk), .VAR87(VAR87),
.VAR32(VAR215),
.VAR225(VAR58),
.VAR178(VAR54),
.VAR24(VAR35),
.VAR171(VAR148),
.VAR77(VAR196),
.VAR207(VAR216),
.VAR33(VAR46),
.VAR226(VAR43),
.VAR93(VAR127),
.VAR49(VAR248),
.VAR169(VAR165),
.VAR126(VAR61),
.VAR155(VAR106),
.VAR100(VAR2),
.VAR29(VAR193),
.VAR26(VAR131),
.VAR19(VAR79),
.VAR161(VAR144),
.VAR45(VAR183),
.VAR250(VAR98),
.VAR236(VAR52),
.VAR242(VAR115),
.VAR1(VAR20),
.VAR159(VAR67),
.VAR70(VAR208),
.VAR223(VAR51),
.VAR188(VAR238),
.VAR222(VAR12),
.VAR109(VAR166),
.VAR145(VAR99),
.VAR173(VAR130),
.VAR5(VAR16),
.VAR150(VAR71),
.VAR101(VAR232),
.VAR57(VAR120),
.VAR78(VAR156),
.VAR91(VAR34),
.VAR88(VAR86),
.VAR175(VAR233),
.VAR230(VAR73),
.VAR141(VAR194),
.reset(reset) );
wire [VAR74-1:0] VAR123;
wire [VAR74-1:0] VAR191;
wire [VAR74-1:0] VAR239;
wire [VAR74-1:0] VAR252;
wire [VAR74-1:0] VAR82;
wire [VAR74-1:0] VAR114;
wire [VAR74-1:0] VAR152;
wire [VAR74-1:0] VAR240;
wire [VAR74-1:0] VAR132;
wire [VAR74-1:0] VAR84;
wire [VAR74-1:0] VAR214;
wire [VAR74-1:0] VAR53;
wire [VAR74-1:0] VAR146;
wire [VAR74-1:0] VAR112;
wire [VAR74-1:0] VAR128;
wire [VAR74-1:0] VAR103;
wire [VAR74-1:0] VAR111;
wire [VAR74-1:0] VAR237;
wire [VAR74-1:0] VAR162;
wire [VAR74-1:0] VAR203;
wire [VAR74-1:0] VAR197;
MODULE2 VAR147(
.VAR94 (VAR58),
.VAR182 (VAR194),
.VAR62(VAR123)
);
MODULE2 VAR39(
.VAR94 (VAR54),
.VAR182 (VAR73),
.VAR62(VAR191)
);
MODULE2 VAR251(
.VAR94 (VAR35),
.VAR182 (VAR233),
.VAR62(VAR239)
);
MODULE2 VAR139(
.VAR94 (VAR148),
.VAR182 (VAR86),
.VAR62(VAR252)
);
MODULE2 VAR190(
.VAR94 (VAR196),
.VAR182 (VAR34),
.VAR62(VAR82)
);
MODULE2 VAR221(
.VAR94 (VAR216),
.VAR182 (VAR156),
.VAR62(VAR114)
);
MODULE2 VAR212(
.VAR94 (VAR46),
.VAR182 (VAR120),
.VAR62(VAR152)
);
MODULE2 VAR184(
.VAR94 (VAR43),
.VAR182 (VAR232),
.VAR62(VAR240)
);
MODULE2 VAR140(
.VAR94 (VAR127),
.VAR182 (VAR71),
.VAR62(VAR132)
);
MODULE2 VAR219(
.VAR94 (VAR248),
.VAR182 (VAR16),
.VAR62(VAR84)
);
MODULE2 VAR137(
.VAR94 (VAR165),
.VAR182 (VAR130),
.VAR62(VAR214)
);
MODULE2 VAR37(
.VAR94 (VAR61),
.VAR182 (VAR99),
.VAR62(VAR53)
);
MODULE2 VAR72(
.VAR94 (VAR106),
.VAR182 (VAR166),
.VAR62(VAR146)
);
MODULE2 VAR202(
.VAR94 (VAR2),
.VAR182 (VAR12),
.VAR62(VAR112)
);
MODULE2 VAR180(
.VAR94 (VAR193),
.VAR182 (VAR238),
.VAR62(VAR128)
);
MODULE2 VAR11(
.VAR94 (VAR131),
.VAR182 (VAR51),
.VAR62(VAR103)
);
MODULE2 VAR6(
.VAR94 (VAR79),
.VAR182 (VAR208),
.VAR62(VAR111)
);
MODULE2 VAR27(
.VAR94 (VAR144),
.VAR182 (VAR67),
.VAR62(VAR237)
);
MODULE2 VAR95(
.VAR94 (VAR183),
.VAR182 (VAR20),
.VAR62(VAR162)
);
MODULE2 VAR189(
.VAR94 (VAR98),
.VAR182 (VAR115),
.VAR62(VAR203)
);
MODULE5 VAR108(
.VAR94 (VAR52),
.VAR62(VAR197)
);
wire [VAR74-1:0] VAR160;
wire [VAR74-1:0] VAR210;
wire [VAR74-1:0] VAR199;
wire [VAR74-1:0] VAR253;
wire [VAR74-1:0] VAR177;
wire [VAR74-1:0] VAR25;
wire [VAR74-1:0] VAR38;
wire [VAR74-1:0] VAR80;
wire [VAR74-1:0] VAR42;
wire [VAR74-1:0] VAR170;
wire [VAR74-1:0] VAR200;
wire [VAR74-1:0] VAR30;
wire [VAR74-1:0] VAR4;
wire [VAR74-1:0] VAR198;
wire [VAR74-1:0] VAR47;
wire [VAR74-1:0] VAR195;
wire [VAR74-1:0] VAR163;
wire [VAR74-1:0] VAR227;
wire [VAR74-1:0] VAR14;
wire [VAR74-1:0] VAR90;
wire [VAR74-1:0] VAR136;
MODULE4 VAR247(
.VAR94 (VAR123),
.VAR182 (VAR117),
.VAR62(VAR160)
);
MODULE4 VAR59(
.VAR94 (VAR191),
.VAR182 (VAR218),
.VAR62(VAR210)
);
MODULE4 VAR205(
.VAR94 (VAR239),
.VAR182 (VAR181),
.VAR62(VAR199)
);
MODULE4 VAR8(
.VAR94 (VAR252),
.VAR182 (VAR119),
.VAR62(VAR253)
);
MODULE4 VAR44(
.VAR94 (VAR82),
.VAR182 (VAR213),
.VAR62(VAR177)
);
MODULE4 VAR135(
.VAR94 (VAR114),
.VAR182 (VAR23),
.VAR62(VAR25)
);
MODULE4 VAR143(
.VAR94 (VAR152),
.VAR182 (VAR113),
.VAR62(VAR38)
);
MODULE4 VAR217(
.VAR94 (VAR240),
.VAR182 (VAR158),
.VAR62(VAR80)
);
MODULE4 VAR85(
.VAR94 (VAR132),
.VAR182 (VAR246),
.VAR62(VAR42)
);
MODULE4 VAR10(
.VAR94 (VAR84),
.VAR182 (VAR209),
.VAR62(VAR170)
);
MODULE4 VAR68(
.VAR94 (VAR214),
.VAR182 (VAR122),
.VAR62(VAR200)
);
MODULE4 VAR55(
.VAR94 (VAR53),
.VAR182 (VAR231),
.VAR62(VAR30)
);
MODULE4 VAR118(
.VAR94 (VAR146),
.VAR182 (VAR83),
.VAR62(VAR4)
);
MODULE4 VAR187(
.VAR94 (VAR112),
.VAR182 (VAR125),
.VAR62(VAR198)
);
MODULE4 VAR50(
.VAR94 (VAR128),
.VAR182 (VAR179),
.VAR62(VAR47)
);
MODULE4 VAR81(
.VAR94 (VAR103),
.VAR182 (VAR224),
.VAR62(VAR195)
);
MODULE4 VAR129(
.VAR94 (VAR111),
.VAR182 (VAR153),
.VAR62(VAR163)
);
MODULE4 VAR89(
.VAR94 (VAR237),
.VAR182 (VAR249),
.VAR62(VAR227)
);
MODULE4 VAR60(
.VAR94 (VAR162),
.VAR182 (VAR96),
.VAR62(VAR14)
);
MODULE4 VAR229(
.VAR94 (VAR203),
.VAR182 (VAR105),
.VAR62(VAR90)
);
MODULE4 VAR185(
.VAR94 (VAR197),
.VAR182 (VAR235),
.VAR62(VAR136)
);
wire [VAR74-1:0] VAR66;
wire [VAR74-1:0] VAR151;
wire [VAR74-1:0] VAR220;
wire [VAR74-1:0] VAR97;
wire [VAR74-1:0] VAR172;
wire [VAR74-1:0] VAR133;
wire [VAR74-1:0] VAR41;
wire [VAR74-1:0] VAR7;
wire [VAR74-1:0] VAR17;
wire [VAR74-1:0] VAR228;
wire [VAR74-1:0] VAR176;
MODULE2 VAR40(
.VAR94 (VAR160),
.VAR182 (VAR210),
.VAR62(VAR66)
);
MODULE2 VAR206(
.VAR94 (VAR199),
.VAR182 (VAR253),
.VAR62(VAR151)
);
MODULE2 VAR36(
.VAR94 (VAR177),
.VAR182 (VAR25),
.VAR62(VAR220)
);
MODULE2 VAR243(
.VAR94 (VAR38),
.VAR182 (VAR80),
.VAR62(VAR97)
);
MODULE2 VAR124(
.VAR94 (VAR42),
.VAR182 (VAR170),
.VAR62(VAR172)
);
MODULE2 VAR186(
.VAR94 (VAR200),
.VAR182 (VAR30),
.VAR62(VAR133)
);
MODULE2 VAR102(
.VAR94 (VAR4),
.VAR182 (VAR198),
.VAR62(VAR41)
);
MODULE2 VAR63(
.VAR94 (VAR47),
.VAR182 (VAR195),
.VAR62(VAR7)
);
MODULE2 VAR15(
.VAR94 (VAR163),
.VAR182 (VAR227),
.VAR62(VAR17)
);
MODULE2 VAR48(
.VAR94 (VAR14),
.VAR182 (VAR90),
.VAR62(VAR228)
);
MODULE5 VAR92(
.VAR94 (VAR136),
.VAR62(VAR176)
);
wire [VAR74-1:0] VAR75;
wire [VAR74-1:0] VAR142;
wire [VAR74-1:0] VAR192;
wire [VAR74-1:0] VAR64;
wire [VAR74-1:0] VAR234;
wire [VAR74-1:0] VAR56;
MODULE2 VAR164(
.VAR94 (VAR66),
.VAR182 (VAR151),
.VAR62(VAR75)
);
MODULE2 VAR149(
.VAR94 (VAR220),
.VAR182 (VAR97),
.VAR62(VAR142)
);
MODULE2 VAR107(
.VAR94 (VAR172),
.VAR182 (VAR133),
.VAR62(VAR192)
);
MODULE2 VAR65(
.VAR94 (VAR41),
.VAR182 (VAR7),
.VAR62(VAR64)
);
MODULE2 VAR69(
.VAR94 (VAR17),
.VAR182 (VAR228),
.VAR62(VAR234)
);
MODULE5 VAR168(
.VAR94 (VAR176),
.VAR62(VAR56)
);
wire [VAR74-1:0] VAR9;
wire [VAR74-1:0] VAR21;
wire [VAR74-1:0] VAR121;
MODULE2 VAR245(
.VAR94 (VAR75),
.VAR182 (VAR142),
.VAR62(VAR9)
);
MODULE2 VAR76(
.VAR94 (VAR192),
.VAR182 (VAR64),
.VAR62(VAR21)
);
MODULE2 VAR18(
.VAR94 (VAR234),
.VAR182 (VAR56),
.VAR62(VAR121)
);
wire [VAR74-1:0] VAR134;
wire [VAR74-1:0] VAR31;
MODULE2 VAR201(
.VAR94 (VAR9),
.VAR182 (VAR21),
.VAR62(VAR134)
);
MODULE5 VAR211(
.VAR94 (VAR121),
.VAR62(VAR31)
);
wire [VAR74-1:0] VAR157;
MODULE2 VAR13(
.VAR94 (VAR134),
.VAR182 (VAR31),
.VAR62(VAR157)
);
reg [17:0] VAR3;
always @(posedge clk) begin
if(VAR87) begin
VAR3 <= VAR157;
end
end
assign VAR104 = VAR167[VAR174-1];
endmodule
module MODULE3 (
clk,
VAR87,
VAR32,
VAR225,
VAR178,
VAR24,
VAR171,
VAR77,
VAR207,
VAR33,
VAR226,
VAR93,
VAR49,
VAR169,
VAR126,
VAR155,
VAR100,
VAR29,
VAR26,
VAR19,
VAR161,
VAR45,
VAR250,
VAR236,
VAR242,
VAR1,
VAR159,
VAR70,
VAR223,
VAR188,
VAR222,
VAR109,
VAR145,
VAR173,
VAR5,
VAR150,
VAR101,
VAR57,
VAR78,
VAR91,
VAR88,
VAR175,
VAR230,
VAR141,
reset);
parameter VAR244 = 1;
input clk;
input VAR87;
input [VAR244-1:0] VAR32;
output [VAR244-1:0] VAR225;
output [VAR244-1:0] VAR178;
output [VAR244-1:0] VAR24;
output [VAR244-1:0] VAR171;
output [VAR244-1:0] VAR77;
output [VAR244-1:0] VAR207;
output [VAR244-1:0] VAR33;
output [VAR244-1:0] VAR226;
output [VAR244-1:0] VAR93;
output [VAR244-1:0] VAR49;
output [VAR244-1:0] VAR169;
output [VAR244-1:0] VAR126;
output [VAR244-1:0] VAR155;
output [VAR244-1:0] VAR100;
output [VAR244-1:0] VAR29;
output [VAR244-1:0] VAR26;
output [VAR244-1:0] VAR19;
output [VAR244-1:0] VAR161;
output [VAR244-1:0] VAR45;
output [VAR244-1:0] VAR250;
output [VAR244-1:0] VAR236;
output [VAR244-1:0] VAR242;
output [VAR244-1:0] VAR1;
output [VAR244-1:0] VAR159;
output [VAR244-1:0] VAR70;
output [VAR244-1:0] VAR223;
output [VAR244-1:0] VAR188;
output [VAR244-1:0] VAR222;
output [VAR244-1:0] VAR109;
output [VAR244-1:0] VAR145;
output [VAR244-1:0] VAR173;
output [VAR244-1:0] VAR5;
output [VAR244-1:0] VAR150;
output [VAR244-1:0] VAR101;
output [VAR244-1:0] VAR57;
output [VAR244-1:0] VAR78;
output [VAR244-1:0] VAR91;
output [VAR244-1:0] VAR88;
output [VAR244-1:0] VAR175;
output [VAR244-1:0] VAR230;
output [VAR244-1:0] VAR141;
reg [VAR244-1:0] VAR225;
reg [VAR244-1:0] VAR178;
reg [VAR244-1:0] VAR24;
reg [VAR244-1:0] VAR171;
reg [VAR244-1:0] VAR77;
reg [VAR244-1:0] VAR207;
reg [VAR244-1:0] VAR33;
reg [VAR244-1:0] VAR226;
reg [VAR244-1:0] VAR93;
reg [VAR244-1:0] VAR49;
reg [VAR244-1:0] VAR169;
reg [VAR244-1:0] VAR126;
reg [VAR244-1:0] VAR155;
reg [VAR244-1:0] VAR100;
reg [VAR244-1:0] VAR29;
reg [VAR244-1:0] VAR26;
reg [VAR244-1:0] VAR19;
reg [VAR244-1:0] VAR161;
reg [VAR244-1:0] VAR45;
reg [VAR244-1:0] VAR250;
reg [VAR244-1:0] VAR236;
reg [VAR244-1:0] VAR242;
reg [VAR244-1:0] VAR1;
reg [VAR244-1:0] VAR159;
reg [VAR244-1:0] VAR70;
reg [VAR244-1:0] VAR223;
reg [VAR244-1:0] VAR188;
reg [VAR244-1:0] VAR222;
reg [VAR244-1:0] VAR109;
reg [VAR244-1:0] VAR145;
reg [VAR244-1:0] VAR173;
reg [VAR244-1:0] VAR5;
reg [VAR244-1:0] VAR150;
reg [VAR244-1:0] VAR101;
reg [VAR244-1:0] VAR57;
reg [VAR244-1:0] VAR78;
reg [VAR244-1:0] VAR91;
reg [VAR244-1:0] VAR88;
reg [VAR244-1:0] VAR175;
reg [VAR244-1:0] VAR230;
reg [VAR244-1:0] VAR141;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR225 <= 0;
VAR178 <= 0;
VAR24 <= 0;
VAR171 <= 0;
VAR77 <= 0;
VAR207 <= 0;
VAR33 <= 0;
VAR226 <= 0;
VAR93 <= 0;
VAR49 <= 0;
VAR169 <= 0;
VAR126 <= 0;
VAR155 <= 0;
VAR100 <= 0;
VAR29 <= 0;
VAR26 <= 0;
VAR19 <= 0;
VAR161 <= 0;
VAR45 <= 0;
VAR250 <= 0;
VAR236 <= 0;
VAR242 <= 0;
VAR1 <= 0;
VAR159 <= 0;
VAR70 <= 0;
VAR223 <= 0;
VAR188 <= 0;
VAR222 <= 0;
VAR109 <= 0;
VAR145 <= 0;
VAR173 <= 0;
VAR5 <= 0;
VAR150 <= 0;
VAR101 <= 0;
VAR57 <= 0;
VAR78 <= 0;
VAR91 <= 0;
VAR88 <= 0;
VAR175 <= 0;
VAR230 <= 0;
VAR141 <= 0;
end else begin
if(VAR87) begin
VAR225 <= VAR32;
VAR178 <= VAR225;
VAR24 <= VAR178;
VAR171 <= VAR24;
VAR77 <= VAR171;
VAR207 <= VAR77;
VAR33 <= VAR207;
VAR226 <= VAR33;
VAR93 <= VAR226;
VAR49 <= VAR93;
VAR169 <= VAR49;
VAR126 <= VAR169;
VAR155 <= VAR126;
VAR100 <= VAR155;
VAR29 <= VAR100;
VAR26 <= VAR29;
VAR19 <= VAR26;
VAR161 <= VAR19;
VAR45 <= VAR161;
VAR250 <= VAR45;
VAR236 <= VAR250;
VAR242 <= VAR236;
VAR1 <= VAR242;
VAR159 <= VAR1;
VAR70 <= VAR159;
VAR223 <= VAR70;
VAR188 <= VAR223;
VAR222 <= VAR188;
VAR109 <= VAR222;
VAR145 <= VAR109;
VAR173 <= VAR145;
VAR5 <= VAR173;
VAR150 <= VAR5;
VAR101 <= VAR150;
VAR57 <= VAR101;
VAR78 <= VAR57;
VAR91 <= VAR78;
VAR88 <= VAR91;
VAR175 <= VAR88;
VAR230 <= VAR175;
VAR141 <= VAR230;
end end
end
endmodule
module MODULE2 (
VAR94,
VAR182,
VAR62);
input clk;
input VAR87;
input [17:0] VAR94;
input [17:0] VAR182;
output [17:0] VAR62;
assign VAR62 = VAR94 + VAR182;
endmodule
module MODULE4 (
VAR94,
VAR182,
VAR62);
input clk;
input VAR87;
input [17:0] VAR94;
input [17:0] VAR182;
output [17:0] VAR62;
assign VAR62 = VAR94 * VAR182;
endmodule
module MODULE5 (
VAR94,
VAR62);
input clk;
input VAR87;
input [17:0] VAR94;
output [17:0] VAR62;
assign VAR62 = VAR94;
endmodule | mit |
ultraembedded/altor32 | rtl/cpu/altor32_lfu.v | 4,597 | module MODULE1
(
input [7:0] VAR1 ,
input [31:0] VAR5 ,
input [1:0] VAR4 ,
output reg [31:0] VAR2 ,
output reg VAR3
);
always @ *
begin
VAR2 = 32'h00000000;
VAR3 = 1'b0;
case (VAR1)
case (VAR4)
2'b00 : VAR2[7:0] = VAR5[31:24];
2'b01 : VAR2[7:0] = VAR5[23:16];
2'b10 : VAR2[7:0] = VAR5[15:8];
2'b11 : VAR2[7:0] = VAR5[7:0];
default : ;
endcase
if (VAR2[7] == 1'b1)
VAR2[31:8] = 24'hFFFFFF;
VAR3 = 1'b1;
end
case (VAR4)
2'b00 : VAR2[7:0] = VAR5[31:24];
2'b01 : VAR2[7:0] = VAR5[23:16];
2'b10 : VAR2[7:0] = VAR5[15:8];
2'b11 : VAR2[7:0] = VAR5[7:0];
default : ;
endcase
VAR3 = 1'b1;
end
case (VAR4)
2'b00 : VAR2[15:0] = VAR5[31:16];
2'b10 : VAR2[15:0] = VAR5[15:0];
default : ;
endcase
if (VAR2[15] == 1'b1)
VAR2[31:16] = 16'hFFFF;
VAR3 = 1'b1;
end
case (VAR4)
2'b00 : VAR2[15:0] = VAR5[31:16];
2'b10 : VAR2[15:0] = VAR5[15:0];
default : ;
endcase
VAR3 = 1'b1;
end
VAR2 = VAR5;
VAR3 = 1'b1;
end
default :
;
endcase
end
endmodule | lgpl-3.0 |
trun/fpgaboy | src/io/debug/cls_spi.v | 9,247 | module MODULE1(
input wire VAR16,
input wire reset,
input wire [15:0] VAR32,
input wire [7:0] VAR51,
input wire [7:0] VAR2,
input wire [15:0] VAR48,
input wire [15:0] VAR20,
input wire [15:0] VAR57,
input wire [15:0] VAR33,
input wire [15:0] VAR21,
input wire [15:0] VAR46,
input wire [15:0] VAR35,
input wire [1:0] VAR52,
output wire VAR5,
output reg VAR15,
input wire VAR55,
output wire VAR12
);
parameter VAR8 = 1;
parameter VAR39 = 2;
parameter VAR31 = 3;
parameter VAR37 = 4;
parameter VAR7 = 5;
parameter VAR38 = 6;
parameter VAR28 = 7;
parameter VAR36 = 8;
parameter VAR23 = 10;
parameter VAR22 = 11;
parameter VAR56 = 12;
parameter VAR18 = 13;
parameter VAR49 = 20;
parameter VAR3 = 21;
parameter VAR4 = 22;
parameter VAR40 = 23;
parameter VAR17 = 24;
parameter VAR47 = 25;
parameter VAR54 = 26;
parameter VAR29 = 27;
parameter VAR34 = 28;
parameter VAR43 = 29;
parameter VAR58 = 30;
parameter VAR27 = 31;
parameter VAR24 = 32;
reg [63:0] VAR14; reg [2:0] VAR42; reg [2:0] VAR10; reg [2:0] VAR26;
reg [31:0] VAR19; reg [31:0] VAR44;
reg [2:0] VAR13; reg [3:0] VAR6; reg [1:0] VAR50;
reg [7:0] state;
reg [7:0] VAR9;
reg [7:0] VAR30;
reg [7:0] VAR45;
reg VAR25;
reg VAR11;
reg [7:0] VAR1 [15:0];
reg [31:0] VAR41;
reg [1:0] VAR53; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor3/sky130_fd_sc_ms__xor3_1.v | 2,199 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR2 ,
VAR6 ,
VAR7,
VAR8,
VAR10 ,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR7;
input VAR8;
input VAR10 ;
input VAR1 ;
VAR5 VAR9 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR3,
VAR4,
VAR2,
VAR6
);
output VAR3;
input VAR4;
input VAR2;
input VAR6;
supply1 VAR7;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR1 ;
VAR5 VAR9 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v | 1,158 | module MODULE1
VAR4 = 32,
VAR3 = 32,
VAR2 = 32,
VAR5 = 16, VAR7 = 32,
VAR9 = 8,
VAR10 = 1,
VAR8 = 8,
VAR1 = 1,
VAR6 = 1
) (
);
endmodule | gpl-3.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_fp_convert_to_internal.v | 3,383 | module MODULE1(VAR15, VAR1, VAR19, VAR21, VAR20, VAR22, VAR14, VAR13, VAR17, VAR18, enable);
parameter VAR4 = 1;
parameter VAR10 = 1;
parameter VAR16 = 0;
parameter VAR6 = 1;
input VAR15, VAR1;
input [31:0] VAR19;
output [26:0] VAR21;
output [8:0] VAR20;
output VAR22;
input enable, VAR14, VAR17;
output VAR13, VAR18;
reg VAR3;
wire VAR9;
wire VAR12;
assign VAR9 = (VAR4 ? (~VAR12 | ~VAR3) : enable);
assign VAR18 = VAR12 & VAR3;
reg [26:0] VAR8;
reg [8:0] VAR2;
reg VAR11;
generate
if (VAR10 == 1)
begin
always @(posedge VAR15 or negedge VAR1)
begin
if (~VAR1)
begin
VAR8 <= 27'VAR5;
VAR2 <= 9'VAR5;
VAR11 <= 1'VAR7;
VAR3 <= 1'b0;
end
else if (VAR9)
begin
VAR3 <= VAR14;
if ((VAR16) && (VAR19[30:23] == 8'd0))
VAR8 <= 27'd0;
end
else
VAR8 <= {|VAR19[30:23],VAR19[22:0],3'd0};
if (VAR6 == 0)
VAR2 <= {&VAR19[30:23], VAR19[30:23]};
end
else
VAR2 <= {1'b0, VAR19[30:23]};
VAR11 <= VAR19[31];
end
end
end
else
begin
always @(*)
begin
VAR3 <= VAR14;
if ((VAR16) && (VAR19[30:23] == 8'd0))
VAR8 <= 27'd0;
end
else
VAR8 <= {|VAR19[30:23],VAR19[22:0],3'd0};
if (VAR6 == 0)
VAR2 <= {&VAR19[30:23], VAR19[30:23]};
end
else
VAR2 <= {1'b0, VAR19[30:23]};
VAR11 <= VAR19[31];
end
end
endgenerate
assign VAR12 = VAR17;
assign VAR13 = VAR3;
assign VAR21 = VAR8;
assign VAR20 = VAR2;
assign VAR22 = VAR11;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai.behavioral.v | 1,674 | module MODULE1 (
VAR3 ,
VAR12,
VAR10,
VAR11 ,
VAR8
);
output VAR3 ;
input VAR12;
input VAR10;
input VAR11 ;
input VAR8 ;
supply1 VAR6;
supply0 VAR15;
supply1 VAR2 ;
supply0 VAR5 ;
wire VAR9 ;
wire VAR16 ;
wire VAR7;
nand VAR1 (VAR9 , VAR10, VAR12 );
or VAR14 (VAR16 , VAR8, VAR11 );
nand VAR4 (VAR7, VAR9, VAR16);
buf VAR13 (VAR3 , VAR7 );
endmodule | apache-2.0 |
prernaa/CPUVerilog | id_ex.v | 4,056 | module MODULE1(
clk, VAR12, VAR53, VAR7,
VAR62, VAR47, VAR64,
VAR51, VAR4, VAR14, VAR26, VAR43, VAR1,
VAR38, VAR11, VAR55, VAR24,VAR18, VAR5, VAR22, VAR16,
VAR52, VAR23, VAR40, VAR41, VAR8,
VAR48, VAR20, VAR21, VAR6,
VAR65, VAR54 , VAR17, VAR59, VAR31,
VAR3, VAR67,
VAR56, VAR39,
VAR29,VAR37,
VAR34, VAR19,
VAR32, VAR46,
VAR35
);
input clk;
input [15:0] VAR12;
input [3:0] VAR53;
input VAR62;
input VAR47;
input [2:0] VAR64;
input VAR51;
input VAR4;
input VAR14;
input VAR26;
input [15:0] VAR7;
input [15:0] VAR43;
input [15:0] VAR1;
input [15:0] VAR38;
input [7:0] VAR11;
input VAR55;
input VAR24;
input VAR18;
input VAR3;
input [15:0] VAR56;
input VAR29;
input VAR34;
input VAR32;
input VAR35;
output VAR22; reg VAR2;
output VAR16; reg VAR57;
output [2:0] VAR52; reg [2:0] VAR10;
output VAR23; reg VAR63;
output VAR40; reg VAR13;
output VAR41; reg VAR50;
output VAR8; reg VAR9;
output [15:0] VAR5;
output [15:0] VAR48;
output [15:0] VAR20;
output [15:0] VAR21;
output [7:0] VAR6;
output [15:0] VAR59; reg [15:0] VAR30;
output [3:0] VAR31; reg [3:0] VAR33;
output VAR65; reg VAR45;
output VAR54; reg VAR28;
output VAR17; reg VAR42;
output VAR67;
output [15:0] VAR39;
output VAR37;
output VAR19;
output VAR46;
reg [15:0] VAR44;
reg [7:0] VAR25;
reg [15:0] VAR66;
reg [15:0] VAR36;
reg [15:0] VAR27;
reg VAR60;
reg VAR61;
reg [15:0] VAR58;
reg VAR49;
reg VAR15;
always @ (posedge clk)
begin
if(VAR35!==1'b1) begin
VAR2 <= VAR62;
VAR57 <= VAR47;
VAR10 <= VAR64;
VAR63 <= VAR51;
VAR13 <= VAR4;
VAR50 <= VAR14;
VAR9 <= VAR26;
VAR36 <= VAR43;
VAR27 <= VAR1;
VAR44 <= VAR38;
VAR25 <= VAR11;
VAR30 <= VAR12;
VAR33 <= VAR53;
VAR45 <= VAR55;
VAR28 <= VAR24;
VAR42 <= VAR18;
VAR60 <= VAR3;
VAR61 <= VAR29;
VAR66 <= VAR7;
VAR58 <= VAR56;
VAR49 <= VAR34;
VAR15 <= VAR32;
end
end
assign VAR22 = VAR2;
assign VAR16 = VAR57;
assign VAR52 = VAR10;
assign VAR23 = VAR63;
assign VAR40 = VAR13;
assign VAR41 = VAR50;
assign VAR8 = VAR9;
assign VAR48 = VAR36;
assign VAR20 = VAR27;
assign VAR21 = VAR44;
assign VAR6 = VAR25;
assign VAR65 = VAR45;
assign VAR54 = VAR28;
assign VAR17 = VAR42;
assign VAR5 = VAR66;
assign VAR59 = VAR30;
assign VAR31 = VAR33;
assign VAR67 = VAR60;
assign VAR37 = VAR61;
assign VAR39 = VAR58;
assign VAR19 = VAR49;
assign VAR46 = VAR15;
endmodule | mit |
alexforencich/verilog-axis | rtl/axis_cobs_decode.v | 11,865 | module MODULE1
(
input wire clk,
input wire rst,
input wire [7:0] VAR6,
input wire VAR34,
output wire VAR7,
input wire VAR17,
input wire VAR33,
output wire [7:0] VAR27,
output wire VAR39,
input wire VAR16,
output wire VAR20,
output wire VAR13
);
localparam [1:0]
VAR14 = 2'd0,
VAR2 = 2'd1,
VAR35 = 2'd2;
reg [1:0] VAR31 = VAR14, VAR3;
reg [7:0] VAR19 = 8'd0, VAR21;
reg VAR40 = 1'b0, VAR30;
reg [7:0] VAR32 = 8'd0, VAR4;
reg VAR43 = 1'b0, VAR25;
reg [7:0] VAR24;
reg VAR1;
reg VAR29 = 1'b0;
reg VAR22;
reg VAR38;
wire VAR9;
reg VAR15 = 1'b0, VAR11;
assign VAR7 = VAR15;
always @* begin
VAR3 = VAR14;
VAR21 = VAR19;
VAR30 = VAR40;
VAR4 = VAR32;
VAR25 = VAR43;
VAR24 = 8'd0;
VAR1 = 1'b0;
VAR22 = 1'b0;
VAR38 = 1'b0;
VAR11 = 1'b0;
case (VAR31)
VAR14: begin
VAR11 = VAR9 || !VAR43;
VAR24 = VAR32;
VAR1 = VAR43;
VAR22 = VAR43;
VAR25 = VAR43 && !VAR29;
if (VAR7 && VAR34) begin
if (VAR6 != 8'd0) begin
VAR21 = VAR6-1;
VAR30 = (VAR6 == 8'd255);
VAR11 = VAR9;
if (VAR6 == 8'd1) begin
VAR3 = VAR35;
end else begin
VAR3 = VAR2;
end
end else begin
VAR3 = VAR14;
end
end else begin
VAR3 = VAR14;
end
end
VAR2: begin
VAR11 = VAR9;
if (VAR7 && VAR34) begin
VAR4 = VAR6;
VAR25 = 1'b1;
VAR24 = VAR32;
VAR1 = VAR43;
VAR21 = VAR19 - 1;
if (VAR6 == 8'd0) begin
VAR25 = 1'b0;
VAR1 = 1'b1;
VAR38 = 1'b1;
VAR22 = 1'b1;
VAR11 = 1'b1;
VAR3 = VAR14;
end else if (VAR17) begin
if (VAR19 == 8'd1 && !VAR33) begin
VAR3 = VAR14;
end else begin
VAR25 = 1'b0;
VAR1 = 1'b1;
VAR38 = 1'b1;
VAR22 = 1'b1;
VAR11 = 1'b1;
VAR3 = VAR14;
end
end else if (VAR19 == 8'd1) begin
VAR3 = VAR35;
end else begin
VAR3 = VAR2;
end
end else begin
VAR3 = VAR2;
end
end
VAR35: begin
VAR11 = VAR9;
if (VAR7 && VAR34) begin
VAR4 = 8'd0;
VAR25 = !VAR40;
VAR24 = VAR32;
VAR1 = VAR43;
if (VAR6 == 8'd0) begin
VAR25 = 1'b0;
VAR38 = VAR33;
VAR22 = 1'b1;
VAR11 = 1'b1;
VAR3 = VAR14;
end else if (VAR17) begin
if (VAR6 == 8'd1 && !VAR33) begin
VAR3 = VAR14;
end else begin
VAR25 = 1'b0;
VAR1 = 1'b1;
VAR38 = 1'b1;
VAR22 = 1'b1;
VAR11 = 1'b1;
VAR3 = VAR14;
end
end else begin
VAR21 = VAR6-1;
VAR30 = (VAR6 == 8'd255);
VAR11 = VAR9;
if (VAR6 == 8'd1) begin
VAR3 = VAR35;
end else begin
VAR3 = VAR2;
end
end
end else begin
VAR3 = VAR35;
end
end
endcase
end
always @(posedge clk) begin
VAR31 <= VAR3;
VAR19 <= VAR21;
VAR40 <= VAR30;
VAR32 <= VAR4;
VAR43 <= VAR25;
VAR15 <= VAR11;
if (rst) begin
VAR31 <= VAR14;
VAR43 <= 1'b0;
VAR15 <= 1'b0;
end
end
reg [7:0] VAR26 = 8'd0;
reg VAR5 = 1'b0, VAR44;
reg VAR42 = 1'b0;
reg VAR37 = 1'b0;
reg [7:0] VAR23 = 8'd0;
reg VAR12 = 1'b0, VAR41;
reg VAR36 = 1'b0;
reg VAR18 = 1'b0;
reg VAR10;
reg VAR8;
reg VAR28;
assign VAR27 = VAR26;
assign VAR39 = VAR5;
assign VAR20 = VAR42;
assign VAR13 = VAR37;
assign VAR9 = VAR16 || (!VAR12 && (!VAR5 || !VAR1));
always @* begin
VAR44 = VAR5;
VAR41 = VAR12;
VAR10 = 1'b0;
VAR8 = 1'b0;
VAR28 = 1'b0;
if (VAR29) begin
if (VAR16 || !VAR5) begin
VAR44 = VAR1;
VAR10 = 1'b1;
end else begin
VAR41 = VAR1;
VAR8 = 1'b1;
end
end else if (VAR16) begin
VAR44 = VAR12;
VAR41 = 1'b0;
VAR28 = 1'b1;
end
end
always @(posedge clk) begin
VAR5 <= VAR44;
VAR29 <= VAR9;
VAR12 <= VAR41;
if (VAR10) begin
VAR26 <= VAR24;
VAR42 <= VAR22;
VAR37 <= VAR38;
end else if (VAR28) begin
VAR26 <= VAR23;
VAR42 <= VAR36;
VAR37 <= VAR18;
end
if (VAR8) begin
VAR23 <= VAR24;
VAR36 <= VAR22;
VAR18 <= VAR38;
end
if (rst) begin
VAR5 <= 1'b0;
VAR29 <= 1'b0;
VAR12 <= 1'b0;
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n.behavioral.pp.v | 1,803 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR1,
VAR4 ,
VAR9 ,
VAR11 ,
VAR3
);
output VAR2 ;
input VAR8 ;
input VAR1;
input VAR4 ;
input VAR9 ;
input VAR11 ;
input VAR3 ;
wire VAR7;
and VAR10 (VAR7, VAR8, VAR1 );
VAR5 VAR6 (VAR2 , VAR7, VAR4, VAR9);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.behavioral.pp.v | 18,950 | module MODULE1( VAR241, VAR282, VAR301, VAR212, VAR220, VAR142, VAR57, VAR108 );
input VAR212, VAR301, VAR241, VAR220, VAR282;
inout VAR57, VAR108;
output VAR142;
reg VAR166;
VAR112 VAR73(.VAR241(VAR241),.VAR282(VAR282),.VAR301(VAR301),.VAR212(VAR212),.VAR220(VAR220),.VAR142(VAR142),.VAR57(VAR57),.VAR108(VAR108),.VAR166(VAR166));
VAR112 VAR140(.VAR241(VAR241),.VAR282(VAR282),.VAR301(VAR301),.VAR212(VAR212),.VAR220(VAR220),.VAR142(VAR142),.VAR57(VAR57),.VAR108(VAR108),.VAR166(VAR166));
not VAR75(VAR83,VAR301);
not VAR174(VAR185,VAR241);
and VAR198(VAR54,VAR185,VAR83);
and VAR162(VAR19,VAR220,VAR54);
not VAR188(VAR186,VAR282);
and VAR102(VAR230,VAR186,VAR19);
not VAR305(VAR91,VAR301);
not VAR127(VAR81,VAR241);
and VAR67(VAR234,VAR81,VAR91);
and VAR32(VAR134,VAR220,VAR234);
and VAR237(VAR243,VAR282,VAR134);
not VAR255(VAR93,VAR301);
and VAR232(VAR278,VAR241,VAR93);
and VAR191(VAR169,VAR220,VAR278);
not VAR126(VAR36,VAR282);
and VAR246(VAR118,VAR36,VAR169);
not VAR37(VAR23,VAR301);
and VAR48(VAR114,VAR241,VAR23);
and VAR148(VAR51,VAR220,VAR114);
and VAR179(VAR211,VAR282,VAR51);
not VAR167(VAR94,VAR241);
and VAR181(VAR152,VAR94,VAR301);
and VAR33(VAR180,VAR220,VAR152);
not VAR272(VAR286,VAR282);
and VAR39(VAR219,VAR286,VAR180);
not VAR269(VAR247,VAR241);
and VAR227(VAR123,VAR247,VAR301);
and VAR97(VAR204,VAR220,VAR123);
and VAR132(VAR56,VAR282,VAR204);
and VAR155(VAR300,VAR241,VAR301);
and VAR290(VAR119,VAR220,VAR300);
not VAR209(VAR70,VAR282);
and VAR213(VAR14,VAR70,VAR119);
and VAR215(VAR236,VAR241,VAR301);
and VAR235(VAR46,VAR220,VAR236);
and VAR113(VAR13,VAR282,VAR46);
not VAR288(VAR254,VAR241);
and VAR136(VAR143,VAR220,VAR254);
not VAR218(VAR72,VAR282);
and VAR287(VAR291,VAR72,VAR143);
not VAR256(VAR176,VAR241);
and VAR7(VAR78,VAR220,VAR176);
and VAR104(VAR192,VAR282,VAR78);
not VAR60(VAR172,VAR301);
and VAR11(VAR177,VAR220,VAR172);
and VAR34(VAR82,VAR282,VAR177);
and VAR30(VAR20,VAR220,VAR301);
not VAR59(VAR10,VAR282);
and VAR79(VAR5,VAR10,VAR20);
not VAR238(VAR116,VAR301);
not VAR294(VAR64,VAR241);
and VAR248(VAR62,VAR64,VAR116);
not VAR52(VAR170,VAR282);
and VAR262(VAR250,VAR170,VAR62);
not VAR298(VAR226,VAR301);
not VAR147(VAR175,VAR241);
and VAR65(VAR263,VAR175,VAR226);
and VAR280(VAR223,VAR282,VAR263);
not VAR41(VAR257,VAR301);
and VAR58(VAR50,VAR241,VAR257);
not VAR200(VAR3,VAR282);
and VAR163(VAR289,VAR3,VAR50);
and VAR121(VAR80,VAR241,VAR301);
not VAR264(VAR35,VAR282);
and VAR117(VAR306,VAR35,VAR80);
not VAR103(VAR216,VAR212);
not VAR92(VAR98,VAR301);
and VAR150(VAR183,VAR98,VAR216);
not VAR275(VAR206,VAR241);
and VAR42(VAR260,VAR206,VAR183);
not VAR26(VAR261,VAR282);
and VAR61(VAR68,VAR261,VAR260);
not VAR197(VAR221,VAR212);
not VAR292(VAR239,VAR301);
and VAR184(VAR101,VAR239,VAR221);
not VAR71(VAR222,VAR241);
and VAR90(VAR55,VAR222,VAR101);
and VAR178(VAR125,VAR282,VAR55);
not VAR244(VAR110,VAR212);
not VAR25(VAR144,VAR301);
and VAR96(VAR115,VAR144,VAR110);
and VAR135(VAR274,VAR241,VAR115);
not VAR74(VAR45,VAR282);
and VAR252(VAR296,VAR45,VAR274);
not VAR86(VAR268,VAR212);
not VAR124(VAR12,VAR301);
and VAR187(VAR44,VAR12,VAR268);
and VAR165(VAR109,VAR241,VAR44);
and VAR281(VAR31,VAR282,VAR109);
not VAR21(VAR277,VAR212);
and VAR141(VAR210,VAR301,VAR277);
not VAR266(VAR228,VAR241);
and VAR173(VAR276,VAR228,VAR210);
not VAR310(VAR259,VAR282);
and VAR233(VAR171,VAR259,VAR276);
not VAR131(VAR49,VAR212);
and VAR249(VAR6,VAR301,VAR49);
not VAR297(VAR17,VAR241);
and VAR95(VAR43,VAR17,VAR6);
and VAR245(VAR265,VAR282,VAR43);
not VAR283(VAR161,VAR212);
and VAR189(VAR111,VAR301,VAR161);
and VAR18(VAR302,VAR241,VAR111);
not VAR88(VAR270,VAR282);
and VAR137(VAR168,VAR270,VAR302);
not VAR149(VAR130,VAR212);
and VAR271(VAR63,VAR301,VAR130);
and VAR156(VAR312,VAR241,VAR63);
and VAR128(VAR53,VAR282,VAR312);
not VAR84(VAR229,VAR301);
and VAR105(VAR225,VAR229,VAR212);
not VAR120(VAR273,VAR241);
and VAR151(VAR164,VAR273,VAR225);
not VAR196(VAR16,VAR282);
and VAR133(VAR311,VAR16,VAR164);
not VAR258(VAR40,VAR301);
and VAR27(VAR38,VAR40,VAR212);
not VAR202(VAR22,VAR241);
and VAR251(VAR158,VAR22,VAR38);
and VAR76(VAR304,VAR282,VAR158);
not VAR214(VAR159,VAR301);
and VAR99(VAR160,VAR159,VAR212);
and VAR240(VAR2,VAR241,VAR160);
not VAR106(VAR139,VAR282);
and VAR89(VAR1,VAR139,VAR2);
not VAR153(VAR205,VAR301);
and VAR87(VAR279,VAR205,VAR212);
and VAR299(VAR157,VAR241,VAR279);
and VAR253(VAR24,VAR282,VAR157);
and VAR284(VAR146,VAR301,VAR212);
not VAR28(VAR231,VAR241);
and VAR138(VAR307,VAR231,VAR146);
not VAR224(VAR190,VAR282);
and VAR285(VAR85,VAR190,VAR307);
and VAR267(VAR29,VAR301,VAR212);
not VAR107(VAR217,VAR241);
and VAR293(VAR122,VAR217,VAR29);
and VAR199(VAR15,VAR282,VAR122);
and VAR100(VAR295,VAR301,VAR212);
and VAR47(VAR242,VAR241,VAR295);
not VAR154(VAR8,VAR282);
and VAR208(VAR182,VAR8,VAR242);
and VAR145(VAR309,VAR301,VAR212);
and VAR9(VAR193,VAR241,VAR309);
and VAR69(VAR129,VAR282,VAR193);
not VAR66(VAR195,VAR301);
and VAR4(VAR194,VAR241,VAR195);
and VAR201(VAR203,VAR220,VAR194);
and VAR303(VAR308,VAR241,VAR301);
and VAR207(VAR77,VAR220,VAR308); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.functional.v | 2,127 | module MODULE1 (
VAR13,
VAR1,
VAR19 ,
VAR12 ,
VAR8 ,
VAR7
);
input VAR13;
input VAR1;
output VAR19 ;
input VAR12 ;
input VAR8 ;
input VAR7 ;
wire VAR16, VAR9 ;
wire VAR16, VAR18 ;
wire VAR6 ;
wire VAR15 ;
wire VAR14;
or VAR10 (VAR6 , VAR8, VAR12 );
and VAR4 (VAR9 , VAR6, VAR7 );
and VAR11 (VAR18 , VAR12, VAR8 );
or VAR5 (VAR15 , VAR18, VAR9 );
VAR17 VAR3 (VAR14, VAR15, VAR13, VAR1);
buf VAR2 (VAR19 , VAR14 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1n/sky130_fd_sc_hd__lpflow_inputiso1n_1.v | 2,378 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR2,
VAR7 ,
VAR1 ,
VAR3 ,
VAR9
);
output VAR5 ;
input VAR4 ;
input VAR2;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
VAR6 VAR8 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR5 ,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR4 ;
input VAR2;
supply1 VAR7;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR9 ;
VAR6 VAR8 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp.functional.pp.v | 1,822 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR2 ,
VAR5,
VAR13,
VAR8,
VAR11 ,
VAR1
);
output VAR9 ;
output VAR6 ;
input VAR2 ;
input VAR5;
input VAR13;
input VAR8;
input VAR11 ;
input VAR1 ;
wire VAR10;
VAR4 VAR3 VAR7 (VAR10 , VAR2, VAR5, , VAR13, VAR8);
buf VAR12 (VAR9 , VAR10 );
not VAR14 (VAR6 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbn/sky130_fd_sc_ls__dlxbn.pp.blackbox.v | 1,362 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR8 ,
VAR7,
VAR2 ,
VAR3 ,
VAR6 ,
VAR4
);
output VAR5 ;
output VAR1 ;
input VAR8 ;
input VAR7;
input VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
kielfriedt/ece472 | lab5/reg_file.v | 1,716 | module MODULE1(clk, VAR6, VAR4, VAR8, VAR7, VAR1, VAR3, VAR5);
input clk;
input VAR6;
input [4:0] VAR4, VAR8, VAR7;
input [31:0] VAR5;
output [31:0] VAR1, VAR3;
reg [31:0] VAR1, VAR3;
reg [31:0] VAR2 [31:1];
always @(VAR4 or VAR2[VAR4])
begin
if (VAR4 == 0) VAR1 = 32'd0;
end
else VAR1 = VAR2[VAR4];
", VAR4, VAR1);
end
always @(VAR8 or VAR2[VAR8])
begin
if (VAR8 == 0) VAR3 = 32'd0;
end
else VAR3 = VAR2[VAR8];
", VAR8, VAR3);
end
always @(posedge clk)
if (VAR6 && (VAR7 != 0))
begin
VAR2[VAR7] <= VAR5;
", VAR7, VAR5);
end
endmodule | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_mask_rows_V.v | 2,983 | module MODULE2 (
clk,
VAR7,
VAR11,
VAR23,
VAR1);
parameter VAR22 = 32'd12;
parameter VAR18 = 32'd2;
parameter VAR2 = 32'd3;
input clk;
input [VAR22-1:0] VAR7;
input VAR11;
input [VAR18-1:0] VAR23;
output [VAR22-1:0] VAR1;
reg[VAR22-1:0] VAR27 [0:VAR2-1];
integer VAR13;
always @ (posedge clk)
begin
if (VAR11)
begin
for (VAR13=0;VAR13<VAR2-1;VAR13=VAR13+1)
VAR27[VAR13+1] <= VAR27[VAR13];
VAR27[0] <= VAR7;
end
end
assign VAR1 = VAR27[VAR23];
endmodule
module MODULE1 (
clk,
reset,
VAR12,
VAR17,
VAR8,
VAR25,
VAR4,
VAR6,
VAR15,
VAR24);
parameter VAR9 = "VAR21";
parameter VAR22 = 32'd12;
parameter VAR18 = 32'd2;
parameter VAR2 = 32'd3;
input clk;
input reset;
output VAR12;
input VAR17;
input VAR8;
output[VAR22 - 1:0] VAR25;
output VAR4;
input VAR6;
input VAR15;
input[VAR22 - 1:0] VAR24;
wire[VAR18 - 1:0] VAR16 ;
wire[VAR22 - 1:0] VAR26, VAR20;
reg[VAR18:0] VAR19 = {(VAR18+1){1'b1}};
reg VAR3 = 0, VAR14 = 1;
assign VAR12 = VAR3;
assign VAR4 = VAR14;
assign VAR26 = VAR24;
assign VAR25 = VAR20;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR19 <= ~{VAR18+1{1'b0}};
VAR3 <= 1'b0;
VAR14 <= 1'b1;
end
else begin
if (((VAR8 & VAR17) == 1 & VAR3 == 1) &&
((VAR15 & VAR6) == 0 | VAR14 == 0))
begin
VAR19 <= VAR19 -1;
if (VAR19 == 0)
VAR3 <= 1'b0;
VAR14 <= 1'b1;
end
else if (((VAR8 & VAR17) == 0 | VAR3 == 0) &&
((VAR15 & VAR6) == 1 & VAR14 == 1))
begin
VAR19 <= VAR19 +1;
VAR3 <= 1'b1;
if (VAR19 == VAR2-2)
VAR14 <= 1'b0;
end
end
end
assign VAR16 = VAR19[VAR18] == 1'b0 ? VAR19[VAR18-1:0]:{VAR18{1'b0}};
assign VAR10 = (VAR15 & VAR6) & VAR14;
MODULE2
.VAR22(VAR22),
.VAR18(VAR18),
.VAR2(VAR2))
VAR5 (
.clk(clk),
.VAR7(VAR26),
.VAR11(VAR10),
.VAR23(VAR16),
.VAR1(VAR20));
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.behavioral.pp.v | 1,923 | module MODULE1 (
VAR2 ,
VAR14 ,
VAR1 ,
VAR11 ,
VAR9,
VAR7,
VAR3 ,
VAR13
);
output VAR2 ;
output VAR14 ;
input VAR1 ;
input VAR11 ;
input VAR9;
input VAR7;
input VAR3 ;
input VAR13 ;
wire VAR8 ;
reg VAR4 ;
wire VAR15 ;
wire VAR5;
wire VAR10 ;
VAR6 VAR16 (VAR8 , VAR15, VAR5, VAR4, VAR9, VAR7);
assign VAR10 = ( VAR9 === 1'b1 );
buf VAR12 (VAR2 , VAR8 );
not VAR17 (VAR14 , VAR8 );
endmodule | apache-2.0 |
chriz2600/DreamcastHDMI | Core/source/preproc/gamma.v | 1,469 | module MODULE1(
input VAR2,
input [4:0] VAR1,
input [7:0] in,
output reg [7:0] out
);
always @(posedge VAR2) begin
case (VAR1)
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
default: out <= in;
endcase
end
endmodule | mit |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/verilog/axi_vdma_v6_2_axis_dwidth_converter_v1_0_axisc_downsizer.v | 14,214 | module MODULE1 #
(
parameter VAR75 = "VAR37",
parameter integer VAR21 = 96,
parameter integer VAR74 = 32,
parameter integer VAR25 = 1,
parameter integer VAR19 = 1,
parameter integer VAR11 = 3,
parameter integer VAR49 = 1,
parameter [31:0] VAR12 = 32'hFF ,
parameter integer VAR13 = 3 )
(
input wire VAR47,
input wire VAR8,
input wire VAR39,
input wire VAR48,
output wire VAR73,
input wire [VAR21-1:0] VAR69,
input wire [VAR21/8-1:0] VAR34,
input wire [VAR21/8-1:0] VAR6,
input wire VAR54,
input wire [VAR25-1:0] VAR2,
input wire [VAR19-1:0] VAR20,
input wire [VAR11-1:0] VAR64,
output wire VAR29,
input wire VAR71,
output wire [VAR74-1:0] VAR28,
output wire [VAR74/8-1:0] VAR23,
output wire [VAR74/8-1:0] VAR26,
output wire VAR9,
output wire [VAR25-1:0] VAR36,
output wire [VAR19-1:0] VAR38,
output wire [VAR49-1:0] VAR42
);
localparam VAR41 = VAR21/8;
localparam VAR44 = VAR74/8;
localparam VAR56 = VAR51(VAR13);
localparam VAR40 = 3'b000;
localparam VAR62 = 3'b001;
localparam VAR27 = 3'b010;
localparam VAR31 = 3'b011;
localparam VAR18 = 3'b110;
reg [2:0] state;
wire [VAR13-1:0] VAR58;
wire [VAR13-1:0] VAR3;
wire [VAR74-1:0] VAR14;
wire [VAR44-1:0] VAR30;
wire [VAR44-1:0] VAR17;
wire VAR72;
wire [VAR25-1:0] VAR15;
wire [VAR19-1:0] VAR22;
wire [VAR49-1:0] VAR33;
reg [VAR21-1:0] VAR76;
reg [VAR41-1:0] VAR70;
reg [VAR41-1:0] VAR16;
reg VAR24;
reg [VAR25-1:0] VAR35;
reg [VAR19-1:0] VAR7;
reg [VAR11-1:0] VAR78;
reg [VAR13-1:0] VAR77;
wire VAR10;
reg [VAR74-1:0] VAR1;
reg [VAR44-1:0] VAR4;
reg [VAR44-1:0] VAR53;
reg VAR5;
reg [VAR25-1:0] VAR46;
reg [VAR19-1:0] VAR43;
reg [VAR49-1:0] VAR66;
wire VAR52;
reg [VAR56-1:0] VAR50;
wire [VAR56-1:0] VAR32;
wire VAR68;
reg [VAR56-1:0] VAR63;
wire [VAR56-1:0] VAR45;
reg VAR55;
reg VAR61;
assign VAR73 = state[0];
assign VAR29 = state[1];
always @(posedge VAR47) begin
if (VAR8) begin
state <= VAR40;
end else if (VAR39) begin
case (state)
VAR40: begin
state <= VAR62;
end
VAR62: begin
if (VAR48) begin
state <= VAR27;
end
else begin
state <= VAR62;
end
end
VAR27: begin
if (VAR71 & VAR3[0]) begin
state <= VAR62;
end
else if (VAR71 & VAR61) begin
state <= VAR31;
end
else begin
state <= VAR27;
end
end
VAR31: begin
if (VAR71 & VAR48) begin
state <= VAR27;
end
else if (VAR71 & ~VAR48) begin
state <= VAR62;
end
else if (~VAR71 & VAR48) begin
state <= VAR18;
end
else begin
state <= VAR31;
end
end
VAR18: begin
if (VAR71) begin
state <= VAR27;
end
else begin
state <= VAR18;
end
end
default: begin
state <= VAR62;
end
endcase end
end
genvar VAR57;
generate
if (VAR12[VAR67]) begin : VAR59
for (VAR57 = 0; VAR57 < VAR13-1; VAR57 = VAR57 + 1) begin : VAR65
assign VAR58[VAR57] = ~(|VAR6[VAR57*VAR44 +: VAR44]);
assign VAR3[VAR57] = (&VAR77[VAR13-1:VAR57+1]);
end
assign VAR58[VAR13-1] = ~(|VAR6[(VAR13-1)*VAR44 +: VAR44]);
assign VAR3[VAR13-1] = 1'b1;
end
else begin : VAR60
assign VAR58 = {VAR13{1'b0}};
assign VAR3 = {1'b1, {VAR13-1{1'b0}}};
end
endgenerate
assign VAR28 = VAR14[0+:VAR74];
assign VAR23 = VAR30[0+:VAR44];
assign VAR26 = VAR17[0+:VAR44];
assign VAR9 = VAR72;
assign VAR36 = VAR15[0+:VAR25];
assign VAR38 = VAR22[0+:VAR19];
assign VAR42 = VAR33[0+:VAR49];
assign VAR14 = {VAR1, VAR76[0+:VAR74*(VAR13-1)]} >> (VAR74*VAR50);
assign VAR30 = {VAR4, VAR70[0+:VAR44*(VAR13-1)]} >> (VAR44*VAR50);
assign VAR17 = {VAR53, VAR16[0+:VAR44*(VAR13-1)]} >> (VAR44*VAR50);
assign VAR72 = (state == VAR31 || state == VAR18) ? VAR5 : VAR24 & VAR3[0];
assign VAR15 = (state == VAR31 || state == VAR18) ? VAR46 : VAR35;
assign VAR22 = (state == VAR31 || state == VAR18) ? VAR43 : VAR7;
assign VAR33 = {VAR66, VAR78[0+:VAR49*(VAR13-1)]} >> (VAR49*VAR50);
always @(posedge VAR47) begin
if (VAR39) begin
VAR76 <= VAR10 ? VAR69 : VAR76;
VAR70 <= VAR10 ? VAR34 : VAR70;
VAR16 <= VAR10 ? VAR6 : VAR16;
VAR24 <= VAR10 ? VAR54 : VAR24;
VAR35 <= VAR10 ? VAR2 : VAR35 ;
VAR7 <= VAR10 ? VAR20 : VAR7;
VAR78 <= VAR10 ? VAR64 : VAR78;
end
end
always @(posedge VAR47) begin
if (VAR8) begin
VAR77 <= {VAR13{1'b0}};
end
else if (VAR39) begin
VAR77 <= VAR10 & VAR48 ? VAR58 : VAR77;
end
end
assign VAR10 = (state == VAR62) || (state == VAR31);
always @(posedge VAR47) begin
if (VAR39) begin
VAR1 <= VAR52 ? VAR76 >> (VAR74*VAR63) : VAR1;
VAR4 <= VAR52 ? VAR70 >> (VAR44*VAR63) : VAR4;
VAR53 <= VAR52 ? VAR16 >> (VAR44*VAR63) : VAR53;
VAR5 <= VAR52 ? VAR24 : VAR5;
VAR46 <= VAR52 ? VAR35 : VAR46 ;
VAR43 <= VAR52 ? VAR7 : VAR43;
VAR66 <= VAR52 ? VAR78 >> (VAR49*VAR63) : VAR66;
end
end
assign VAR52 = (state == VAR27);
always @(posedge VAR47) begin
if (VAR8) begin
VAR50 <= {VAR56{1'b0}};
end else if (VAR39) begin
VAR50 <= VAR32;
end
end
assign VAR32 = (VAR55 & VAR68) || (state == VAR62) ? {VAR56{1'b0}}
: VAR61 & VAR68 ? VAR13[VAR56-1:0]-1'b1
: VAR68 ? VAR63 : VAR50;
assign VAR68 = VAR71;
always @(posedge VAR47) begin
if (VAR8) begin
VAR63 <= {VAR56{1'b0}} + 1'b1;
end else if (VAR39) begin
VAR63 <= VAR45;
end
end
assign VAR45 = (VAR55 & VAR68) || (state == VAR62) ? {VAR56{1'b0}} + 1'b1
: ~VAR61 & VAR68 ? VAR63 + 1'b1
: VAR63;
always @ begin
VAR61 = VAR3[VAR63];
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1.behavioral.v | 1,405 | module MODULE1 (
VAR8,
VAR2
);
output VAR8;
input VAR2;
supply1 VAR7;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR3 ;
wire VAR9;
buf VAR1 (VAR9, VAR2 );
buf VAR5 (VAR8 , VAR9 );
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cart/cart.v | 4,454 | module MODULE1 (
input VAR28,
input [39:0] VAR12, input VAR27,
input VAR13, input [14:0] VAR26, input VAR17, input [ 7:0] VAR24, output [ 7:0] VAR25,
input [13:0] VAR18, input VAR4, input [ 7:0] VAR5, output [ 7:0] VAR20, output VAR8, output VAR11 );
wire VAR16;
wire [14:0] VAR7;
wire [7:0] VAR14;
VAR23 #(
.VAR21 (15 ),
.VAR10 (8 ))
VAR3 (
.clk (VAR28 ),
.VAR6 (VAR16 ),
.VAR2 (VAR7 ),
.VAR22 (VAR24 ),
.VAR19 (VAR14 )
);
assign VAR16 = (~VAR13) ? ~VAR17 : 1'b0;
assign VAR25 = (~VAR13) ? VAR14 : 8'h00;
assign VAR7 = (VAR12[33]) ? VAR26[14:0] : { 1'b0, VAR26[13:0] };
wire VAR15;
wire [7:0] VAR1;
VAR23 #(
.VAR21 (13 ),
.VAR10 (8 ))
VAR9 (
.clk (VAR28 ),
.VAR6 (VAR15 ),
.VAR2 (VAR18[12:0] ),
.VAR22 (VAR5 ),
.VAR19 (VAR1 )
);
assign VAR8 = ~VAR18[13];
assign VAR11 = (VAR12[16]) ? VAR18[10] : VAR18[11];
assign VAR15 = (VAR8) ? ~VAR4 : 1'b0;
assign VAR20 = (VAR8) ? VAR1 : 8'h00;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp.blackbox.v | 1,319 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR6 ,
VAR3
);
output VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR3;
supply1 VAR4;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.behavioral.pp.v | 1,089 | module MODULE1( VAR1, VAR5 );
inout VAR1, VAR5;
VAR3 VAR2(.VAR1(VAR1),.VAR5(VAR5));
VAR3 VAR4(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1p/sky130_fd_sc_lp__iso1p.functional.pp.v | 1,872 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR8,
VAR1,
VAR2 ,
VAR9 ,
VAR10
);
output VAR11 ;
input VAR7 ;
input VAR8;
input VAR1;
input VAR2 ;
input VAR9 ;
input VAR10 ;
wire VAR6 ;
wire VAR4;
VAR3 VAR12 (VAR6 , VAR7, VAR1, VAR2 );
VAR3 VAR13 (VAR4, VAR8, VAR1, VAR2 );
or VAR5 (VAR11 , VAR6, VAR4);
endmodule | apache-2.0 |
oblivioncth/DE0-Verilog-Processor | src/ID_01_Handler.v | 2,436 | module MODULE1 (VAR2, VAR1, VAR3);
input [13:0] VAR2;
output reg [15:0] VAR3;
output reg [18:0] VAR1;
always @(VAR2) begin
case (VAR2[13:9])
5'b10000: begin VAR1 = {6'b100001,VAR2[8:6],VAR2[5:3],7'b0000100}; VAR3 = 16'b1111111111111111; end
5'b10100: begin VAR1 = {6'b101001,VAR2[8:6],VAR2[5:3],VAR2[2:0],4'b1100}; VAR3 = 16'b1111111111111111; end
5'b10110: begin VAR1 = {6'b101101,VAR2[8:6],VAR2[5:3],VAR2[2:0],4'b1100}; VAR3 = 16'b1111111111111111; end
5'b10010: begin VAR1 = {6'b100101,VAR2[8:6],VAR2[5:3],7'b0000100}; VAR3 = 16'b1111111111111111; end
5'b10001: begin VAR1 = {6'b100011,VAR2[8:6],VAR2[5:3],7'b0000100}; VAR3 = 16'b1111111111111111; end
5'b01100: begin VAR1 = {6'b011001,VAR2[8:6],VAR2[5:3],7'b0000100}; VAR3 = 16'b1111111111111111; end
5'b01010: begin VAR1 = {6'b010101,VAR2[8:6],3'b000,VAR2[2:0],4'b1100}; VAR3 = 16'b1111111111111111; end
5'b11001: begin VAR1 = {6'b110011,VAR2[8:6],VAR2[5:3],7'b0000100}; VAR3 = 16'b1111111111111111; end
5'b11000: begin VAR1 = {6'b110001,VAR2[8:6],VAR2[5:3],7'b0000100}; VAR3 = 16'b1111111111111111; end
5'b00000: begin VAR1 = {6'b000001,VAR2[8:6],VAR2[8:6],VAR2[8:6],4'b0100}; VAR3 = 16'b1111111111111111; end
5'b01111: begin VAR1 = {6'b011111,VAR2[8:6],VAR2[8:6],VAR2[8:6],4'b0100}; VAR3 = 16'b1111111111111111; end
5'b00011: begin VAR1 = {6'b000111,VAR2[8:6],VAR2[5:3],7'b0000100}; VAR3 = 16'b1111111111111111; end
5'b01000: begin VAR1 = {6'b010001,VAR2[8:6],VAR2[5:3],VAR2[2:0],4'b1100}; VAR3 = 16'b1111111111111111; end
5'b01110: begin VAR1 = {6'b011101,VAR2[8:6],VAR2[5:3],VAR2[2:0],4'b1100}; VAR3 = 16'b1111111111111111; end
5'b00110: begin VAR1 = {6'b001101,VAR2[8:6],VAR2[5:3],VAR2[2:0],4'b1100}; VAR3 = 16'b1111111111111111; end
5'b10111: begin VAR1 = {6'b110101,VAR2[8:6],VAR2[5:3],VAR2[2:0],4'b1100}; VAR3 = 16'b1111111111111111; end
5'b10101: begin VAR1 = {6'b110111,VAR2[8:6],VAR2[5:3],VAR2[2:0],4'b1100}; VAR3 = 16'b1111111111111111; end
5'b11011: begin VAR1 = {6'b111001,VAR2[8:6],VAR2[5:3],7'b0000100}; VAR3 = 16'b1111111111111111; end
endcase
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv.functional.pp.v | 1,748 | module MODULE1 (
VAR2 ,
VAR12 ,
VAR7,
VAR11,
VAR1 ,
VAR5
);
output VAR2 ;
input VAR12 ;
input VAR7;
input VAR11;
input VAR1 ;
input VAR5 ;
wire VAR6 ;
wire VAR8;
not VAR3 (VAR6 , VAR12 );
VAR9 VAR10 (VAR8, VAR6, VAR7, VAR11);
buf VAR4 (VAR2 , VAR8 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/dest_fifo_inf.v | 4,564 | module MODULE1 (
input clk,
input VAR11,
input enable,
output VAR35,
input VAR38,
output VAR42,
input [VAR37-1:0] VAR6,
output [VAR37-1:0] VAR12,
output [VAR37-1:0] VAR21,
input VAR9,
input VAR23,
input en,
output [VAR25-1:0] dout,
output valid,
output VAR14,
output VAR24,
output VAR39,
input VAR2,
input [VAR25-1:0] VAR3,
input VAR44,
output VAR30,
input [VAR15-1:0] VAR33,
output VAR5,
input VAR34,
output VAR22,
output [1:0] VAR20
);
parameter VAR37 = 3;
parameter VAR25 = 64;
parameter VAR15 = 4;
assign VAR42 = VAR38;
wire VAR19;
wire VAR39;
assign VAR39 = VAR39 | ~VAR35;
reg VAR27;
wire VAR13;
wire VAR26;
always @(posedge clk)
begin
if (VAR11 == 1'b0) begin
VAR27 <= 1'b0;
end else begin
VAR27 <= en;
end
end
assign VAR14 = VAR27 & (~VAR26 | ~enable);
assign VAR13 = VAR27 & (VAR26 | ~enable);
assign valid = VAR27 & VAR26 & enable;
VAR16 # (
.VAR37(VAR37),
.VAR25(VAR25),
.VAR15(VAR15),
.VAR28(0)
) VAR36 (
.clk(clk),
.VAR11(VAR11),
.enable(enable),
.VAR35(VAR19),
.VAR38(VAR38),
.VAR24(VAR24),
.VAR6(VAR6),
.VAR12(VAR21),
.VAR7(VAR9),
.VAR44(VAR44),
.VAR30(VAR30),
.VAR33(VAR33),
.VAR41(VAR39),
.VAR29(VAR2),
.VAR8(VAR3),
.VAR43(VAR13),
.VAR45(VAR26),
.VAR31(dout),
.VAR4()
);
VAR1 # (
.VAR37(VAR37)
) VAR40 (
.clk(clk),
.VAR11(VAR11),
.enable(VAR19),
.VAR35(VAR35),
.VAR38(VAR38),
.VAR6(VAR21),
.VAR12(VAR12),
.VAR7(VAR23),
.VAR32(VAR5),
.VAR10(VAR34),
.VAR17(VAR22),
.VAR18(VAR20)
);
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.behavioral.v | 1,802 | module MODULE1( VAR4, VAR2, VAR7, VAR1, VAR8 );
input VAR7, VAR2, VAR1, VAR8;
output VAR4;
VAR6 VAR3(.VAR4(VAR4),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8));
VAR6 VAR5(.VAR4(VAR4),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8)); | apache-2.0 |
orbancedric/DeepGate | other/convPrototype/convLayerControl.v | 3,541 | module MODULE1 #(
parameter VAR18 = 16'd125, parameter VAR13 = 16'd100, parameter VAR1 = 16'd10, parameter VAR11 = 16'd10, parameter VAR14 = 16'd10,
parameter VAR4 = 16'd10,
parameter VAR3 = 16'd1
)(
input clk,
input VAR9,
input VAR12,
input VAR10,
output reg enable = 0,
output reg VAR16 = 0,
output reg VAR7 = 0,
output reg VAR19 = 0,
output reg VAR17 = 0,
output reg [15:0] VAR21 = 0
);
localparam VAR2 = 4'b0001,
VAR5 = 4'b0010,
VAR20 = 4'b0100,
VAR15 = 4'b1000;
reg [3:0] VAR23 = VAR2;
reg VAR8 = 0;
reg [VAR6(VAR13):0] VAR22 = 0;
always@(posedge clk) begin
if(VAR9) begin
enable <= 0;
VAR16 <= 0;
VAR21 <= 0;
VAR22 <= 0;
VAR7 <= 0;
VAR8 <= 0;
VAR19 <= 1;
VAR23 <= VAR2;
end
else begin
VAR19 <= 0;
case(VAR23)
VAR2: begin
VAR7 <= 1;
if(VAR12) begin
VAR7 <= 0;
VAR17 <= 1;
VAR23 <= VAR5;
end
end
VAR5: begin
VAR21 <= VAR21 + 1'd1;
if(VAR21 == VAR1*VAR11 - 1)
VAR17 <= 0;
if(VAR21 < VAR1*VAR11)
enable <= 1;
end
else begin
enable <= 0;
VAR21 <= 0;
VAR22 <= VAR22 + 1'b1;
VAR16 <= 1;
VAR23 <= VAR20;
end
end
VAR20: begin
VAR21 <= VAR21 + 1'b1;
if(VAR21 == VAR18 - 1'b1) begin
VAR21 <= 0;
VAR16 <= 0;
VAR19 <= 1;
if(VAR22 < VAR13) begin
VAR17 <= 1;
VAR23 <= VAR5;
end
else begin
VAR23 <= VAR15;
VAR22 <= 0;
end
end
end
VAR15: begin
VAR8 <= 1;
if(!VAR10 && VAR8) begin
VAR8 <= 0;
VAR7 <= 1;
VAR23 <= VAR2;
end
end
endcase
end
end
endmodule | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | Registro_universal.v | 1,206 | module MODULE1
input wire VAR7,
input wire [VAR3-1:0]VAR1,
input wire [VAR3-1:0]VAR8,
input wire clk, input wire reset, input wire VAR4, output wire [VAR3-1:0]VAR5
);
reg [VAR3-1:0]VAR6;
reg [VAR3-1:0]VAR2;
always@(negedge clk, posedge reset)
begin
if(reset) VAR6 <= 0;
end
else VAR6 <= VAR2;
end
always@*
begin
if (~VAR7) begin
case(VAR4)
1'b0: VAR2 = VAR1;
1'b1: VAR2 = VAR8;
endcase
end
else VAR2 = VAR6;
end
assign VAR5 = VAR6;
endmodule | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_onchip_sram.v | 2,946 | module MODULE1 (
address,
VAR17,
VAR21,
clk,
VAR32,
reset,
VAR10,
write,
VAR31,
VAR13
)
;
parameter VAR20 = "MODULE1.VAR26";
output [ 31: 0] VAR13;
input [ 16: 0] address;
input [ 3: 0] VAR17;
input VAR21;
input clk;
input VAR32;
input reset;
input VAR10;
input write;
input [ 31: 0] VAR31;
wire VAR6;
wire [ 31: 0] VAR13;
wire VAR23;
assign VAR23 = VAR21 & write;
assign VAR6 = VAR32 & ~VAR10;
VAR5 VAR7
(
.VAR1 (address),
.VAR33 (VAR17),
.VAR18 (clk),
.VAR6 (VAR6),
.VAR3 (VAR31),
.VAR16 (VAR13),
.VAR12 (VAR23)
);
VAR7.VAR4 = VAR20,
VAR7.VAR9 = "VAR5",
VAR7.VAR15 = 90112,
VAR7.VAR25 = 90112,
VAR7.VAR29 = "VAR22",
VAR7.VAR27 = "VAR19",
VAR7.VAR14 = "VAR28",
VAR7.VAR11 = "VAR8",
VAR7.VAR30 = 32,
VAR7.VAR2 = 4,
VAR7.VAR34 = 17;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi.pp.symbol.v | 1,394 | module MODULE1 (
input VAR1 ,
input VAR6 ,
input VAR8,
output VAR4 ,
input VAR3 ,
input VAR5,
input VAR2,
input VAR7
);
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_fifo_index.v | 1,887 | module MODULE1 (VAR16, reset, enable, VAR17, VAR25, VAR20);
parameter VAR12 = VAR1;
parameter VAR6 = 1;
parameter VAR2 = 1;
parameter VAR13 = 1;
parameter VAR7 = 1; parameter VAR22 = VAR14;
parameter VAR3 = VAR4;
parameter VAR24 = VAR5;
parameter VAR15 = VAR8;
parameter VAR9 = VAR18;
parameter VAR19 = VAR10;
input VAR16, reset, enable;
input [VAR2-1:0] VAR17;
input [VAR13-1:0] VAR25;
output [VAR21-1:0] VAR20;
parameter VAR23 = "VAR11"; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp.functional.pp.v | 1,928 | module MODULE1 (
VAR4 ,
VAR12,
VAR1 ,
VAR9 ,
VAR3 ,
VAR7 ,
VAR15 ,
VAR13
);
output VAR4 ;
input VAR12;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR7 ;
input VAR15 ;
input VAR13 ;
wire VAR5;
wire VAR6;
not VAR2 (VAR5 , VAR12 );
VAR8 VAR10 VAR14 (VAR6 , VAR1, VAR9, VAR5, , VAR3, VAR7);
buf VAR11 (VAR4 , VAR6 );
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fanout_merger.v | 2,548 | module MODULE1(VAR5, VAR17,
VAR14, VAR1, VAR3,
VAR12, VAR16, VAR13,
VAR4, VAR10);
parameter VAR6 = 32;
parameter VAR2 = 4;
parameter VAR8 = 3;
parameter VAR9 = 0;
input VAR5, VAR17;
input [VAR2*VAR6-1:0] VAR14;
input [VAR2-1:0] VAR1;
output [VAR2-1:0] VAR3;
output [VAR6-1:0] VAR12;
input VAR16;
output VAR13;
input [VAR8-1:0] VAR4;
input VAR10;
reg [VAR6-1:0] VAR15;
generate
if ( VAR9 == 1) begin
always @(*)
begin
integer VAR7,VAR11;
for (VAR7=0; VAR7 < VAR6; VAR7 =VAR7+1)
begin
VAR15[VAR7] = 1'b0;
for (VAR11=0; VAR11 < VAR2; VAR11 = VAR11+1)
begin
VAR15[VAR7] = VAR15[VAR7] | VAR14[VAR11*VAR6+VAR7];
end
end
end
assign VAR12 = VAR15;
assign VAR13 = |VAR1;
assign VAR3 = {VAR2{VAR16}};
end
else
begin
assign VAR12 = VAR14[VAR6*VAR4[VAR8-1:1] +: VAR6];
assign VAR13 = !(VAR4[0] & VAR10) ? 1'b0 : VAR1[VAR4[VAR8-1:1]];
assign VAR3 = !(VAR4[0] & VAR10) ? {VAR2{1'b0}} : {{VAR2{1'b0}}, VAR16} << VAR4[VAR8-1:1];
end
endgenerate
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41a/sky130_fd_sc_hd__o41a_1.v | 2,411 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR4 ,
VAR10 ,
VAR2 ,
VAR12 ,
VAR3,
VAR8,
VAR5 ,
VAR6
);
output VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR12 ;
input VAR3;
input VAR8;
input VAR5 ;
input VAR6 ;
VAR11 VAR1 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7 ,
VAR9,
VAR4,
VAR10,
VAR2,
VAR12
);
output VAR7 ;
input VAR9;
input VAR4;
input VAR10;
input VAR2;
input VAR12;
supply1 VAR3;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR6 ;
VAR11 VAR1 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR12(VAR12)
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | scripts/auguste/bram/mkDelay.v | 3,597 | module MODULE1(VAR25,
VAR14,
VAR20,
VAR8,
VAR11,
VAR17,
read,
VAR22);
input VAR25;
input VAR14;
input [31 : 0] VAR20;
input VAR8;
output VAR11;
input VAR17;
output [31 : 0] read;
output VAR22;
reg [31 : 0] read;
wire VAR22, VAR11;
reg [3 : 0] VAR2;
wire [3 : 0] VAR6;
wire VAR10;
reg [31 : 0] VAR24;
wire [31 : 0] VAR23;
wire VAR13;
reg [31 : 0] VAR19;
wire [31 : 0] VAR12;
wire VAR1;
reg [31 : 0] VAR5;
wire [31 : 0] VAR26;
wire VAR4;
reg [31 : 0] VAR7;
wire [31 : 0] VAR15;
wire VAR18;
reg [3 : 0] VAR3;
wire [3 : 0] VAR9;
wire VAR21;
assign VAR11 = 1'd1 ;
always@(VAR2 or VAR7 or VAR24 or VAR19 or VAR5)
begin
case (VAR2)
4'd0: read = VAR24;
4'd1: read = VAR19;
4'd2: read = VAR5;
default: read = VAR7;
endcase
end
assign VAR22 = 1'd1 ;
assign VAR6 = VAR2 + 4'd1 ;
assign VAR10 = VAR17 ;
assign VAR23 = VAR20 ;
assign VAR13 = VAR8 && VAR3 == 4'd0 ;
assign VAR12 = VAR20 ;
assign VAR1 = VAR8 && VAR3 == 4'd1 ;
assign VAR26 = VAR20 ;
assign VAR4 = VAR8 && VAR3 == 4'd2 ;
assign VAR15 = VAR20 ;
assign VAR18 = VAR8 && VAR3 == 4'd3 ;
assign VAR9 = VAR3 ;
assign VAR21 = VAR8 ;
always@(posedge VAR25)
begin
if (!VAR14)
begin
VAR2 <= VAR16 4'd0;
VAR3 <= VAR16 4'd0;
end
else
begin
if (VAR10) VAR2 <= VAR16 VAR6;
if (VAR21) VAR3 <= VAR16 VAR9;
end
if (VAR13) VAR24 <= VAR16 VAR23;
if (VAR1) VAR19 <= VAR16 VAR12;
if (VAR4) VAR5 <= VAR16 VAR26;
if (VAR18) VAR7 <= VAR16 VAR15;
end
begin
VAR2 = 4'hA;
VAR24 = 32'hAAAAAAAA;
VAR19 = 32'hAAAAAAAA;
VAR5 = 32'hAAAAAAAA;
VAR7 = 32'hAAAAAAAA;
VAR3 = 4'hA;
end | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.behavioral.pp.v | 1,388 | module MODULE1( VAR4, VAR3, VAR5, VAR2, VAR10, VAR8, VAR1 );
input VAR4, VAR3, VAR5, VAR2;
inout VAR8, VAR1;
output VAR10;
VAR9 VAR7(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2),.VAR10(VAR10),.VAR8(VAR8),.VAR1(VAR1));
VAR9 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2),.VAR10(VAR10),.VAR8(VAR8),.VAR1(VAR1)); | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_source_sync_upstream_sync.v | 6,345 | module MODULE1
,parameter VAR9 = 3
,parameter VAR1 = 0
,parameter VAR41 = 0
)
( input VAR33
,input VAR49
,input VAR27
,input VAR17
,input [VAR21-1:0] VAR14
,output VAR5
,output VAR43
,output [VAR21-1:0] VAR38
,input VAR3
);
logic VAR11, VAR12;
logic [VAR21-1:0] VAR18;
if (VAR41 == 0)
begin: VAR31
VAR24
) VAR48
(.VAR46 (VAR33)
,.VAR32(VAR49)
,.VAR51(VAR5)
,.VAR23 (VAR14)
,.VAR54 (VAR17)
,.VAR7 (VAR11)
,.VAR50 (VAR18)
,.VAR10 (VAR11 & VAR12)
);
end
else
begin: VAR57
assign VAR11 = VAR17;
assign VAR18 = VAR14;
assign VAR5 = (VAR49)? 1'b1 : VAR12;
end
logic VAR52;
assign VAR43 = (VAR49)? '0 : VAR52;
assign VAR38 = (VAR49 | ~VAR52)? '0 : VAR18;
logic [VAR1+1-1:0] VAR28;
VAR44
,.VAR39(0) ,.VAR42(1) )
VAR8
(.VAR46 (VAR33)
,.VAR32(VAR49)
,.VAR26(1'b0)
,.VAR6 (VAR52)
,.VAR45(VAR28)
);
wire VAR37 = VAR28[VAR1];
logic VAR55, VAR30;
wire VAR29 = VAR37
? VAR55
: VAR30;
assign VAR52 = VAR29 & VAR11;
assign VAR12 = (VAR49)? 1'b1 : VAR29;
wire VAR19 = VAR52 & VAR37;
wire VAR56 = VAR52 & ~VAR37;
VAR58
,.VAR1(VAR1)
,.VAR53(1'b0)
,.VAR13(0)
,.VAR25(1)
,.VAR4(1'b1)
) VAR20
(
.VAR40 (VAR3)
,.VAR22(1'b1)
,.VAR34(VAR27)
,.VAR36 (VAR33 )
,.VAR15 (VAR49 )
,.VAR2 (VAR56)
,.VAR35(1'b0 )
,.VAR16 (VAR30)
);
VAR58
,.VAR1(VAR1)
,.VAR53(1'b1)
,.VAR13(0)
,.VAR25(1)
,.VAR4(1'b1)
) VAR47
(
.VAR40 (VAR3)
,.VAR22(1'b1)
,.VAR34(VAR27)
,.VAR36 (VAR33 )
,.VAR15 (VAR49 )
,.VAR2 (VAR19)
,.VAR35(1'b0 )
,.VAR16 (VAR55)
);
endmodule | bsd-3-clause |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_fp_custom_mul_dbl_pumped.v | 3,497 | module MODULE1
(
input VAR2,
input VAR9,
input enable,
input VAR13,
input [VAR4-1:0] VAR7,
input [VAR4-1:0] b1,
input [VAR4-1:0] VAR16,
input [VAR4-1:0] VAR17,
output reg [VAR4-1:0] VAR5,
output reg [VAR4-1:0] VAR12
);
reg [VAR4-1:0] VAR8;
reg [VAR4-1:0] VAR14;
reg [VAR4-1:0] VAR11;
reg [VAR4-1:0] VAR10;
reg VAR15 ;
wire [VAR4-1:0] VAR6;
wire [VAR4-1:0] VAR3;
wire [VAR4-1:0] VAR1;
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
end
begin | mit |
azonenberg/yosys | techlibs/intel/cyclone10/cells_arith.v | 2,584 | module MODULE1(
module 80alteraa10gxalu (VAR18, VAR17, VAR35, VAR9, VAR27, VAR20, VAR24);
parameter VAR3 = 0;
parameter VAR31 = 0;
parameter VAR11 = 1;
parameter VAR29 = 1;
parameter VAR22 = 1;
input [VAR11-1:0] VAR18;
input [VAR29-1:0] VAR17;
output [VAR22-1:0] VAR27, VAR20;
input VAR35, VAR9;
output VAR24;
wire VAR28 = VAR22 <= 4;
wire [VAR22-1:0] VAR34, VAR30;
\pos #(.VAR3(VAR3), .VAR11(VAR11), .VAR22(VAR22)) VAR16 (.VAR18(VAR18), .VAR20(VAR34));
\pos #(.VAR3(VAR31), .VAR11(VAR29), .VAR22(VAR22)) VAR26 (.VAR18(VAR17), .VAR20(VAR30));
wire [VAR22-1:0] VAR21 = VAR34;
wire [VAR22-1:0] VAR14 = VAR9 ? ~VAR30 : VAR30;
wire [VAR22+1:0] VAR32;
wire [VAR22+1:0] VAR12 = {VAR32, VAR35};
VAR33 #(.VAR19(16'b0000000010101010), .VAR10("VAR2")) VAR36 (.VAR7(VAR32[0]), .VAR8(VAR12[0]), .VAR4(1'b1), .VAR13(1'b1), .VAR23(1'b1));
genvar VAR5;
generate for (VAR5 = 0; VAR5 < VAR22; VAR5 = VAR5 + 1) begin: VAR1
if(VAR5==VAR22-1) begin
VAR33 #(.VAR19(16'b1111000011100000), .VAR10("VAR2")) VAR15 (.VAR6(VAR32[VAR22]), .VAR8(1'b1), .VAR4(1'b1), .VAR13(1'b1), .VAR23(1'b1), .VAR2(VAR12[VAR22]));
assign VAR24 = VAR32[VAR22];
end
else
VAR33 #(.VAR19(16'b1001011011101000), .VAR10("VAR2")) VAR25 (.VAR6(VAR20[VAR5]), .VAR7(VAR32[VAR5+1]), .VAR8(VAR21[VAR5]), .VAR4(VAR14[VAR5]), .VAR13(1'b1), .VAR23(1'b1), .VAR2(VAR12[VAR5+1]));
end: VAR1
endgenerate
assign VAR27 = VAR21 ^ VAR14;
endmodule | isc |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/cluster_header_sync.v | 2,362 | module MODULE1 (
VAR10, VAR2, VAR14,
VAR7, VAR4,
VAR9, VAR16, VAR17,
VAR18, VAR1, VAR11, VAR12, VAR13
);
output VAR10;
output VAR2;
output VAR14;
output VAR7;
output VAR4;
input VAR9;
input VAR16;
input VAR17;
input VAR18;
input VAR1;
input VAR11;
input VAR12;
input VAR13;
wire VAR8;
wire VAR15;
wire VAR3;
VAR6 VAR5 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR14(VAR14),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR16(VAR16),
.VAR17(VAR17),
.VAR18(VAR18),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR13(VAR13)
);
endmodule | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_dac_common.v | 19,450 | module MODULE1 (
VAR92,
VAR70,
VAR24,
VAR115,
VAR37,
VAR58,
VAR42,
VAR32,
VAR73,
VAR76,
VAR90,
VAR120,
VAR15,
VAR20,
VAR36,
VAR114,
VAR88,
VAR41,
VAR75,
VAR71,
VAR85,
VAR61,
VAR14,
VAR118,
VAR2,
VAR99,
VAR77,
VAR69,
VAR7,
VAR23,
VAR48,
VAR98,
VAR106,
VAR111,
VAR43,
VAR25);
parameter VAR30 = 32'h00040062;
parameter VAR91 = 0;
output VAR92;
input VAR70;
output VAR24;
output VAR115;
output VAR37;
output VAR58;
output VAR42;
output VAR32;
output VAR73;
output [ 3:0] VAR76;
output [ 7:0] VAR90;
input VAR120;
input [31:0] VAR15;
input VAR20;
output VAR36;
output VAR114;
output VAR88;
output [11:0] VAR41;
output [15:0] VAR75;
input [15:0] VAR71;
input VAR85;
input VAR61;
output VAR14;
output [31:0] VAR118;
input VAR2;
input VAR99;
output [ 7:0] VAR77;
input [ 7:0] VAR69;
input VAR7;
input VAR23;
input VAR48;
input VAR98;
input [13:0] VAR106;
input [31:0] VAR111;
output [31:0] VAR43;
output VAR25;
reg [31:0] VAR11 = 'd0;
reg VAR113 = 'd0;
reg VAR93 = 'd0;
reg VAR35 = 'd0;
reg VAR45 = 'd0;
reg VAR59 = 'd0;
reg VAR124 = 'd0;
reg VAR17 = 'd0;
reg [ 3:0] VAR51 = 'd0;
reg [ 7:0] VAR53 = 'd0;
reg VAR74 = 'd0;
reg VAR64 = 'd0;
reg VAR67 = 'd0;
reg [11:0] VAR81 = 'd0;
reg [15:0] VAR126 = 'd0;
reg [31:0] VAR10 = 'd0;
reg [ 7:0] VAR77 = 'd0;
reg VAR25 = 'd0;
reg [31:0] VAR43 = 'd0;
reg VAR125 = 'd0;
reg VAR109 = 'd0;
reg VAR6 = 'd0;
reg VAR103 = 'd0;
reg VAR49 = 'd0;
reg VAR121 = 'd0;
reg VAR12 = 'd0;
reg VAR78 = 'd0;
reg VAR29 = 'd0;
reg VAR3 = 'd0;
reg VAR115 = 'd0;
reg VAR37 = 'd0;
reg VAR58 = 'd0;
reg VAR42 = 'd0;
reg VAR32 = 'd0;
reg VAR73 = 'd0;
reg [ 3:0] VAR76 = 'd0;
reg [ 7:0] VAR90 = 'd0;
reg VAR84 = 'd0;
reg VAR46 = 'd0;
reg VAR63 = 'd0;
reg VAR68 = 'd0;
reg VAR52 = 'd0;
reg VAR100 = 'd0;
reg [15:0] VAR31 = 'd0;
reg [31:0] VAR102 = 'd0;
reg VAR122 = 'd0;
reg VAR33 = 'd0;
reg VAR55 = 'd0;
reg VAR117 = 'd0;
reg [31:0] VAR13 = 'd0;
reg [32:0] VAR89 = 'd0;
reg VAR39 = 'd0;
reg VAR97 = 'd0;
reg VAR60 = 'd0;
reg VAR114 = 'd0;
reg VAR88 = 'd0;
reg [11:0] VAR41 = 'd0;
reg [15:0] VAR75 = 'd0;
reg VAR8 = 'd0;
reg VAR18 = 'd0;
reg VAR65 = 'd0;
reg VAR86 = 'd0;
reg VAR79 = 'd0;
reg [15:0] VAR38 = 'd0;
reg VAR47 = 'd0;
reg VAR83 = 'd0;
reg VAR57 = 'd0;
reg [31:0] VAR118 = 'd0;
reg [ 5:0] VAR62 = 'd0;
reg VAR56 = 'd0;
reg VAR4 = 'd0;
reg VAR5 = 'd0;
reg VAR28 = 'd0;
reg VAR105 = 'd0;
reg VAR50 = 'd0;
reg VAR95 = 'd0;
reg VAR66 = 'd0;
reg VAR34 = 'd0;
reg VAR104 = 'd0;
reg VAR19 = 'd0;
reg VAR110 = 'd0;
wire VAR87;
wire VAR1;
wire VAR72;
wire VAR82;
wire VAR26;
wire VAR27;
wire VAR112;
wire VAR116;
wire VAR21;
wire VAR108;
wire VAR44;
wire VAR94;
assign VAR87 = (VAR106[13:8] == 6'h10) ? VAR48 : 1'b0;
assign VAR1 = VAR87 & VAR98;
assign VAR72 = ~VAR93;
assign VAR82 = ~VAR113;
always @(negedge VAR7 or posedge VAR23) begin
if (VAR7 == 0) begin
VAR11 <= 'd0;
VAR113 <= 'd0;
VAR93 <= 'd0;
VAR35 <= 'd0;
VAR45 <= 'd0;
VAR59 <= 'd0;
VAR124 <= 'd0;
VAR17 <= 'd0;
VAR51 <= 'd0;
VAR53 <= 'd0;
VAR74 <= 'd0;
VAR64 <= 'd0;
VAR67 <= 'd0;
VAR81 <= 'd0;
VAR126 <= 'd0;
VAR10 <= 'd0;
VAR77 <= 'd0;
end else begin
if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h02)) begin
VAR11 <= VAR111;
end
if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h10)) begin
VAR113 <= VAR111[1];
VAR93 <= VAR111[0];
end
if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h11)) begin
VAR35 <= VAR111[0];
end
if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h12)) begin
VAR45 <= VAR111[7];
VAR59 <= VAR111[6];
VAR124 <= VAR111[5];
VAR17 <= VAR111[4];
VAR51 <= VAR111[3:0];
end
if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h13)) begin
VAR53 <= VAR111[7:0];
end
if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h14)) begin
VAR74 <= VAR111[0];
end
if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h1c)) begin
VAR64 <= ~VAR64;
VAR67 <= VAR111[28];
VAR81 <= VAR111[27:16];
VAR126 <= VAR111[15:0];
end
if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h21)) begin
VAR10 <= VAR111;
end
if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h28)) begin
VAR77 <= VAR111[7:0];
end
end
end
always @(negedge VAR7 or posedge VAR23) begin
if (VAR7 == 0) begin
VAR25 <= 'd0;
VAR43 <= 'd0;
end else begin
VAR25 <= VAR87;
if (VAR87 == 1'b1) begin
case (VAR106[7:0])
8'h00: VAR43 <= VAR30;
8'h01: VAR43 <= VAR91;
8'h02: VAR43 <= VAR11;
8'h10: VAR43 <= {30'd0, VAR113, VAR93};
8'h11: VAR43 <= {31'd0, VAR35};
8'h12: VAR43 <= {24'd0, VAR45, VAR59, VAR124,
VAR17, VAR51};
8'h13: VAR43 <= {24'd0, VAR53};
8'h14: VAR43 <= {31'd0, VAR74};
8'h15: VAR43 <= VAR102;
8'h16: VAR43 <= VAR15;
8'h17: VAR43 <= {31'd0, VAR46};
8'h1c: VAR43 <= {3'd0, VAR67, VAR81, VAR126};
8'h1d: VAR43 <= {15'd0, VAR79, VAR38};
8'h21: VAR43 <= VAR10;
8'h22: VAR43 <= {30'd0, VAR19, VAR110};
8'h28: VAR43 <= {24'd0, VAR69};
default: VAR43 <= 0;
endcase
end else begin
VAR43 <= 32'd0;
end
end
end
always @(negedge VAR7 or posedge VAR23) begin
if (VAR7 == 0) begin
VAR125 <= 'd0;
end else begin
if (VAR1 == 1'b1) begin
VAR125 <= ~VAR125;
end
end
end
VAR16 #(.VAR123(1'b1)) VAR40 (
.VAR107 (1'b1),
.VAR80 (1'b0),
.VAR22 (VAR82),
.VAR96 (VAR20),
.VAR9 (VAR92));
VAR16 #(.VAR123(1'b1)) VAR119 (
.VAR107 (1'b1),
.VAR80 (1'b0),
.VAR22 (VAR72),
.VAR96 (VAR70),
.VAR9 (VAR24));
assign VAR27 = VAR103 ^ VAR6;
always @(posedge VAR70) begin
if (VAR24 == 1'b1) begin
VAR109 <= 'd0;
VAR6 <= 'd0;
VAR103 <= 'd0;
VAR49 <= 'd0;
VAR121 <= 'd0;
VAR12 <= 'd0;
VAR78 <= 'd0;
VAR29 <= 'd0;
VAR3 <= 'd0;
end else begin
VAR109 <= VAR125;
VAR6 <= VAR109;
VAR103 <= VAR6;
VAR49 <= VAR35;
VAR121 <= VAR49;
VAR12 <= VAR121;
VAR78 <= VAR74;
VAR29 <= VAR78;
VAR3 <= VAR29;
end
VAR115 <= VAR12;
VAR37 <= VAR29 & ~VAR3;
if (VAR27 == 1'b1) begin
VAR58 <= VAR45;
VAR42 <= VAR59;
VAR32 <= VAR124;
VAR73 <= VAR17;
VAR76 <= VAR51;
VAR90 <= VAR53;
end
end
always @(negedge VAR7 or posedge VAR23) begin
if (VAR7 == 0) begin
VAR84 <= 'd0;
VAR46 <= 'd0;
end else begin
VAR84 <= VAR120;
VAR46 <= VAR84;
end
end
assign VAR26 = VAR52 ^ VAR68;
always @(negedge VAR7 or posedge VAR23) begin
if (VAR7 == 0) begin
VAR63 <= 'd0;
VAR68 <= 'd0;
VAR52 <= 'd0;
VAR100 <= 'd0;
VAR31 <= 'd0;
VAR102 <= 'd0;
end else begin
VAR63 <= VAR117;
VAR68 <= VAR63;
VAR52 <= VAR68;
if (VAR31 == 16'd0) begin
VAR100 <= ~VAR100;
end
VAR31 <= VAR31 + 1'b1;
if (VAR26 == 1'b1) begin
VAR102 <= VAR13;
end
end
end
assign VAR112 = VAR55 ^ VAR33;
always @(posedge VAR70) begin
if (VAR24 == 1'b1) begin
VAR122 <= 'd0;
VAR33 <= 'd0;
VAR55 <= 'd0;
end else begin
VAR122 <= VAR100;
VAR33 <= VAR122;
VAR55 <= VAR33;
end
if (VAR112 == 1'b1) begin
VAR117 <= ~VAR117;
VAR13 <= VAR89[31:0];
end
if (VAR112 == 1'b1) begin
VAR89 <= 33'd1;
end else if (VAR89[32] == 1'b0) begin
VAR89 <= VAR89 + 1'b1;
end else begin
VAR89 <= {33{1'b1}};
end
end
VAR16 #(.VAR123(1'b1)) VAR101 (
.VAR107 (1'b1),
.VAR80 (1'b0),
.VAR22 (VAR72),
.VAR96 (VAR20),
.VAR9 (VAR36));
assign VAR116 = VAR97 ^ VAR60;
always @(posedge VAR20) begin
if (VAR36 == 1'b1) begin
VAR39 <= 'd0;
VAR97 <= 'd0;
VAR60 <= 'd0;
end else begin
VAR39 <= VAR64;
VAR97 <= VAR39;
VAR60 <= VAR97;
end
if (VAR116 == 1'b1) begin
VAR114 <= 1'b1;
VAR88 <= ~VAR67;
VAR41 <= VAR81;
VAR75 <= VAR126;
end else begin
VAR114 <= 1'b0;
VAR88 <= 1'b0;
VAR41 <= 12'd0;
VAR75 <= 16'd0;
end
end
assign VAR21 = VAR65 ^ VAR18;
assign VAR108 = VAR64 ^ VAR86;
always @(negedge VAR7 or posedge VAR23) begin
if (VAR7 == 0) begin
VAR8 <= 'd0;
VAR18 <= 'd0;
VAR65 <= 'd0;
VAR86 <= 'd0;
VAR79 <= 'd0;
VAR38 <= 'd0;
end else begin
VAR8 <= VAR85;
VAR18 <= VAR8;
VAR65 <= VAR18;
VAR86 <= VAR64;
if (VAR21 == 1'b1) begin
VAR79 <= 1'b0;
end else if (VAR108 == 1'b1) begin
VAR79 <= 1'b1;
end
if (VAR21 == 1'b1) begin
VAR38 <= VAR71;
end
end
end
VAR16 #(.VAR123(1'b1)) VAR54 (
.VAR107 (1'b1),
.VAR80 (1'b0),
.VAR22 (VAR72),
.VAR96 (VAR61),
.VAR9 (VAR14));
assign VAR44 = VAR57 ^ VAR83;
always @(posedge VAR61) begin
if (VAR14 == 1'b1) begin
VAR47 <= 'd0;
VAR83 <= 'd0;
VAR57 <= 'd0;
end else begin
VAR47 <= VAR125;
VAR83 <= VAR47;
VAR57 <= VAR83;
end
if (VAR44 == 1'b1) begin
VAR118 <= VAR10;
end
end
always @(posedge VAR61) begin
VAR62 <= VAR62 + 1'b1;
if (VAR62 == 6'd0) begin
VAR56 <= ~VAR56;
VAR4 <= VAR28;
VAR5 <= VAR105;
end
if (VAR62 == 6'd0) begin
VAR28 <= VAR2;
VAR105 <= VAR99;
end else begin
VAR28 <= VAR28 | VAR2;
VAR105 <= VAR105 | VAR99;
end
end
assign VAR94 = VAR95 ^ VAR66;
always @(negedge VAR7 or posedge VAR23) begin
if (VAR7 == 0) begin
VAR50 <= 'd0;
VAR95 <= 'd0;
VAR66 <= 'd0;
VAR34 <= 'd0;
VAR104 <= 'd0;
VAR19 <= 'd0;
VAR110 <= 'd0;
end else begin
VAR50 <= VAR56;
VAR95 <= VAR50;
VAR66 <= VAR95;
if (VAR94 == 1'b1) begin
VAR34 <= VAR4;
VAR104 <= VAR5;
end
if (VAR34 == 1'b1) begin
VAR19 <= 1'b1;
end else if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h22)) begin
VAR19 <= VAR19 & ~VAR111[1];
end
if (VAR104 == 1'b1) begin
VAR110 <= 1'b1;
end else if ((VAR1 == 1'b1) && (VAR106[7:0] == 8'h22)) begin
VAR110 <= VAR110 & ~VAR111[0];
end
end
end
endmodule | mit |
dcsun88/ntpserver-fpga | cpu/ip/cpu_processing_system7_0_0/hdl/processing_system7_bfm_v2_0_axi_master.v | 20,925 | module MODULE1 (
VAR6,
VAR40,
VAR5,
VAR22,
VAR43,
VAR31,
VAR57,
VAR23,
VAR21,
VAR49,
VAR18,
VAR42,
VAR16,
VAR50,
VAR46,
VAR61,
VAR17,
VAR14,
VAR12,
VAR38,
VAR30,
VAR33,
VAR47,
VAR19,
VAR56,
VAR1, VAR58, VAR25,
VAR59,
VAR10,
VAR9,
VAR15,
VAR52,
VAR4,
VAR24,
VAR28,
VAR34,
VAR44,
VAR3,
VAR27
);
parameter VAR41 = 0;
parameter VAR62 = "VAR2";
parameter VAR51 = 32;
parameter VAR7 = 32;
parameter VAR39 = 6;
parameter VAR48 = 8;
parameter VAR60 = 0;
parameter VAR37 = 12'hC00;
input VAR6;
output VAR40;
output VAR5;
output VAR22;
output VAR43;
output VAR31;
output VAR57;
output [VAR39-1:0] VAR23;
output [VAR39-1:0] VAR21;
output [VAR39-1:0] VAR49;
output [VAR8-1:0] VAR18;
output [VAR45-1:0] VAR42;
output [VAR53-1:0] VAR16;
output [VAR8-1:0] VAR50;
output [VAR45-1:0] VAR46;
output [VAR53-1:0] VAR61;
output [VAR36-1:0] VAR17;
output [VAR36-1:0] VAR14;
output [VAR7-1:0] VAR12;
output [VAR7-1:0] VAR38;
output [VAR51-1:0] VAR30;
output [VAR32-1:0] VAR33;
output [VAR54-1:0] VAR47;
output [VAR35-1:0] VAR1; output [VAR32-1:0] VAR19;
output [VAR54-1:0] VAR56;
output [VAR35-1:0] VAR58; output [(VAR51/8)-1:0] VAR25;
input VAR59;
input VAR10;
input VAR9;
input VAR15;
input VAR52;
input VAR4;
input VAR24;
input [VAR39-1:0] VAR28;
input [VAR39-1:0] VAR34;
input [VAR55-1:0] VAR44;
input [VAR55-1:0] VAR3;
input [VAR51-1:0] VAR27;
wire VAR20;
wire VAR11;
wire VAR63;
reg VAR29 = 1'b1;
reg VAR13 = 1'b1;
integer VAR26 = 0;
assign VAR1 = 'b0;
assign VAR58 = 'b0;
assign VAR20 = VAR6; assign VAR11 = VAR41 ? VAR4 : 1'b0;
assign VAR63 = VAR41 ? VAR15 : 1'b0;
begin
end
begin
end
begin
end
begin
end
begin
end
begin
begin
begin
end | gpl-3.0 |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | Verilog_AES/AES/ClockGenerator.v | 1,391 | module MODULE1(
output reg VAR1,
output reg reset
);
always begin
VAR1 = ~VAR1;
end
begin | lgpl-2.1 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/example_design/PIO_TX_ENGINE.v | 14,012 | module MODULE1 #(
parameter VAR29 = 64,
parameter VAR5 = 1,
parameter VAR43 = VAR29 / 8
)(
input clk,
input VAR17,
input VAR3,
output reg [VAR29-1:0] VAR6,
output reg [VAR43-1:0] VAR52,
output reg VAR40,
output reg VAR18,
output VAR48,
input VAR8,
input VAR24,
output reg VAR12,
input [2:0] VAR51,
input VAR22,
input VAR41,
input [1:0] VAR2,
input [9:0] VAR15,
input [15:0] VAR28,
input [7:0] VAR47,
input [7:0] VAR1,
input [12:0] VAR42,
output [10:0] VAR7,
output [3:0] VAR14,
input [31:0] VAR39,
input [15:0] VAR45
);
localparam VAR44 = 7'b1001010;
localparam VAR30 = 7'b0001010;
localparam VAR34 = 1'b0;
localparam VAR9 = 1'b1;
reg [11:0] VAR35;
reg [6:0] VAR50;
reg VAR31;
reg VAR49;
reg VAR36;
reg VAR38;
wire VAR46;
assign VAR48 = 1'b0;
assign VAR7 = VAR42[12:2];
assign VAR14 = VAR1[3:0];
always @ (VAR14) begin
casex (VAR14[3:0])
4'VAR21 : VAR35 = 12'h004;
4'VAR37 : VAR35 = 12'h003;
4'VAR26 : VAR35 = 12'h003;
4'b0011 : VAR35 = 12'h002;
4'b0110 : VAR35 = 12'h002;
4'b1100 : VAR35 = 12'h002;
4'b0001 : VAR35 = 12'h001;
4'b0010 : VAR35 = 12'h001;
4'b0100 : VAR35 = 12'h001;
4'b1000 : VAR35 = 12'h001;
4'b0000 : VAR35 = 12'h001;
endcase
end
always @ ( posedge clk ) begin
if (!VAR17 )
begin
end else
begin
end end
generate
if (VAR29 == 128) begin : VAR32
always @ ( posedge clk ) begin
if (!VAR17 )
begin
end else
begin
end end
end
endgenerate
generate
if (VAR29 == 64) begin : VAR19
assign VAR46 = VAR49;
end
else if (VAR29 == 128) begin : VAR25
assign VAR46 = VAR38;
end
endgenerate
always @ (VAR14 or VAR42 or VAR46) begin
casex ({VAR46, VAR14[3:0]})
5'VAR13 : VAR50 = 8'h0;
5'VAR20 : VAR50 = {VAR42[6:2], 2'b00};
5'VAR23 : VAR50 = {VAR42[6:2], 2'b00};
5'VAR16 : VAR50 = {VAR42[6:2], 2'b01};
5'VAR10 : VAR50 = {VAR42[6:2], 2'b10};
5'VAR27 : VAR50 = {VAR42[6:2], 2'b11};
endcase end
generate
if (VAR29 == 64) begin : VAR11
reg state;
always @ ( posedge clk ) begin
if (!VAR17 )
begin
end else
begin
case ( state )
VAR34 : begin
if (VAR31)
begin
VAR44 :
VAR30), {1'b0}, VAR51, {4'b0}, VAR22, VAR41, VAR2, {2'b0}, VAR15 };
if (VAR3)
end
else
end else
begin
end
end
VAR9 : begin
if (VAR3)
begin
if (VAR49)
end
else
end else
end
default : begin
end
endcase
end end
end
else if (VAR29 == 128) begin : VAR33
reg VAR4;
always @ ( posedge clk ) begin
if (!VAR17 )
begin
end else
begin
if (VAR36 | VAR4)
begin
if (VAR3)
begin
VAR44 :
VAR30), {1'b0}, VAR51, {4'b0}, VAR22, VAR41, VAR2, {2'b0}, VAR15 };
if (VAR38)
end
else
end else
end else
begin
end end end
end
endgenerate
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b.behavioral.pp.v | 1,998 | module MODULE1 (
VAR3 ,
VAR16 ,
VAR12 ,
VAR2 ,
VAR10 ,
VAR7,
VAR6,
VAR5 ,
VAR9
);
output VAR3 ;
input VAR16 ;
input VAR12 ;
input VAR2 ;
input VAR10 ;
input VAR7;
input VAR6;
input VAR5 ;
input VAR9 ;
wire VAR8 ;
wire VAR13 ;
wire VAR11;
not VAR15 (VAR8 , VAR16 );
nand VAR14 (VAR13 , VAR10, VAR2, VAR12, VAR8 );
VAR1 VAR4 (VAR11, VAR13, VAR7, VAR6);
buf VAR17 (VAR3 , VAR11 );
endmodule | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/02CAD-JOYSTICK/Version_02/02 verilog/adc/fifo.v | 2,232 | module MODULE1
parameter VAR10 = 10,
parameter VAR7 = 8
)
(
input VAR5, reset,
input wr,rd,
input [VAR7-1:0] VAR8,
output [VAR7-1:0] VAR14,
output VAR15,
output VAR16
);
parameter VAR6 = (1 << VAR10);
reg [VAR7-1:0] VAR11 [VAR6-1:0];
reg [VAR10-1:0] VAR17, VAR4;
reg [VAR10-1:0] VAR1, VAR12;
reg VAR9, VAR18, VAR13, VAR2;
wire VAR3;
assign VAR14 = VAR11[VAR1];
assign VAR3 = wr & ~VAR9;
assign VAR16 = VAR9;
assign VAR15 = VAR18;
always @(posedge VAR5) begin
if (VAR3)
VAR11[VAR17] <= VAR8;
end
always @(posedge VAR5, posedge reset) begin
if (reset)
begin
VAR17 <= 0;
VAR1 <= 0;
VAR9 <= 1'b0;
VAR18 <= 1'b1;
end
else
begin
VAR17 <= VAR4;
VAR1 <= VAR12;
VAR9 <= VAR13;
VAR18 <= VAR2;
end
end
always @(*)
begin
if (reset) begin
VAR4 = 0;
VAR12 = 0;
end else begin
VAR13 = VAR9;
VAR2 = VAR18;
case ({wr, rd})
2'b01: if (~VAR18) begin
VAR12 = VAR1 + 1;
VAR13 = 1'b0;
if (VAR12==VAR17)
VAR2 = 1'b1;
end
2'b10: if (~VAR9) begin
VAR4 = VAR17 + 1;
VAR2 = 1'b0;
if (VAR4==VAR1)
VAR13 = 1'b1;
end
2'b11: begin
VAR4 = VAR17 + 1;
VAR12 = VAR1 + 1;
end
endcase
end
end
endmodule | gpl-3.0 |
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