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Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_nios2_qsys_0_jtag_debug_module_tck.v | 8,596 | module MODULE1 (
VAR38,
VAR9,
VAR22,
VAR19,
VAR7,
VAR37,
VAR31,
VAR3,
VAR12,
VAR2,
VAR36,
VAR32,
VAR33,
VAR10,
VAR14,
VAR13,
VAR29,
VAR28,
VAR1,
VAR25,
VAR5,
VAR23,
VAR4,
VAR11,
VAR15,
VAR34,
VAR6,
VAR21,
VAR8,
VAR30,
VAR27
)
;
output [ 1: 0] VAR6;
output VAR21;
output [ 37: 0] VAR8;
output VAR30;
output VAR27;
input [ 31: 0] VAR38;
input [ 31: 0] VAR9;
input VAR22;
input VAR19;
input VAR7;
input VAR37;
input VAR31;
input [ 1: 0] VAR3;
input VAR12;
input VAR2;
input VAR36;
input VAR32;
input VAR33;
input VAR10;
input VAR14;
input VAR13;
input [ 35: 0] VAR29;
input VAR28;
input [ 6: 0] VAR1;
input VAR25;
input VAR5;
input VAR23;
input VAR4;
input VAR11;
input VAR15;
input VAR34;
reg [ 2: 0] VAR16 ;
wire VAR24;
reg [ 1: 0] VAR6;
wire VAR21;
wire VAR20;
reg [ 37: 0] VAR8 ;
wire VAR30;
wire VAR27;
wire VAR26;
wire VAR17;
always @(posedge VAR10)
begin
if (VAR11)
case (VAR3)
2'b00: begin
VAR8[35] <= VAR24;
VAR8[34] <= VAR2;
VAR8[33] <= VAR33;
VAR8[32 : 1] <= VAR38;
VAR8[0] <= VAR20;
end
2'b01: begin
VAR8[35 : 0] <= VAR29;
VAR8[37] <= VAR28;
VAR8[36] <= VAR13;
end
2'b10: begin
VAR8[37] <= VAR4;
VAR8[36] <= VAR37;
VAR8[35] <= VAR7;
VAR8[34] <= VAR19;
VAR8[33] <= VAR22;
VAR8[32 : 1] <= VAR9;
VAR8[0] <= VAR23;
end
2'b11: begin
VAR8[15 : 2] <= VAR1;
VAR8[1] <= VAR5;
VAR8[0] <= VAR25;
end
endcase if (VAR15)
case (VAR16)
3'b000: begin
VAR8 <= {VAR14, VAR8[37 : 2], VAR14};
end
3'b001: begin
VAR8 <= {VAR14, VAR8[37 : 9], VAR14, VAR8[7 : 1]};
end
3'b010: begin
VAR8 <= {VAR14, VAR8[37 : 17], VAR14, VAR8[15 : 1]};
end
3'b011: begin
VAR8 <= {VAR14, VAR8[37 : 33], VAR14, VAR8[31 : 1]};
end
3'b100: begin
VAR8 <= {VAR14, VAR8[37], VAR14, VAR8[35 : 1]};
end
3'b101: begin
VAR8 <= {VAR14, VAR8[37 : 1]};
end
default: begin
VAR8 <= {VAR14, VAR8[37 : 2], VAR14};
end
endcase if (VAR34)
case (VAR3)
2'b00: begin
VAR16 <= 3'b100;
end
2'b01: begin
VAR16 <= 3'b101;
end
2'b10: begin
VAR16 <= 3'b101;
end
2'b11: begin
VAR16 <= 3'b010;
end
endcase end
assign VAR27 = VAR8[0];
assign VAR30 = VAR12;
assign VAR26 = VAR21;
VAR35 VAR18
(
.clk (VAR10),
.din (VAR31),
.dout (VAR24),
.VAR32 (VAR26)
);
assign VAR17 = VAR21;
VAR35 VAR40
(
.clk (VAR10),
.din (VAR36),
.dout (VAR20),
.VAR32 (VAR17)
);
always @(posedge VAR10 or negedge VAR21)
begin
if (VAR21 == 0)
VAR6 <= 2'b0;
end
else
VAR6 <= {VAR24, VAR20};
end
assign VAR21 = VAR32;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/26bit/BinaryKOA/ks26.v | 2,789 | module MODULE1(VAR4, VAR12, VAR13);
input wire [25:0] VAR4;
input wire [25:0] VAR12;
output wire [50:0] VAR13;
wire [18:0] VAR5;
wire [30:0] VAR7;
wire [30:0] VAR1;
wire [15:0] VAR9;
wire [15:0] VAR3;
VAR2 VAR11(VAR4[15:0], VAR12[15:0], VAR7);
VAR6 VAR10(VAR4[25:16], VAR12[25:16], VAR5);
assign VAR9[9:0] = VAR4[25:16] ^ VAR4[9:0];
assign VAR9[15:10] = VAR4[15:10];
assign VAR3[9:0] = VAR12[25:16] ^ VAR12[9:0];
assign VAR3[15:10] = VAR12[15:10];
VAR2 VAR8(VAR9, VAR3, VAR1);
assign VAR13[00] = VAR7[00];
assign VAR13[01] = VAR7[01];
assign VAR13[02] = VAR7[02];
assign VAR13[03] = VAR7[03];
assign VAR13[04] = VAR7[04];
assign VAR13[05] = VAR7[05];
assign VAR13[06] = VAR7[06];
assign VAR13[07] = VAR7[07];
assign VAR13[08] = VAR7[08];
assign VAR13[09] = VAR7[09];
assign VAR13[10] = VAR7[10];
assign VAR13[11] = VAR7[11];
assign VAR13[12] = VAR7[12];
assign VAR13[13] = VAR7[13];
assign VAR13[14] = VAR7[14];
assign VAR13[15] = VAR7[15];
assign VAR13[16] = VAR7[16] ^ VAR5[00] ^ VAR7[00] ^ VAR1[00];
assign VAR13[17] = VAR7[17] ^ VAR5[01] ^ VAR7[01] ^ VAR1[01];
assign VAR13[18] = VAR7[18] ^ VAR5[02] ^ VAR7[02] ^ VAR1[02];
assign VAR13[19] = VAR7[19] ^ VAR5[03] ^ VAR7[03] ^ VAR1[03];
assign VAR13[20] = VAR7[20] ^ VAR5[04] ^ VAR7[04] ^ VAR1[04];
assign VAR13[21] = VAR7[21] ^ VAR5[05] ^ VAR7[05] ^ VAR1[05];
assign VAR13[22] = VAR7[22] ^ VAR5[06] ^ VAR7[06] ^ VAR1[06];
assign VAR13[23] = VAR7[23] ^ VAR5[07] ^ VAR7[07] ^ VAR1[07];
assign VAR13[24] = VAR7[24] ^ VAR5[08] ^ VAR7[08] ^ VAR1[08];
assign VAR13[25] = VAR7[25] ^ VAR5[09] ^ VAR7[09] ^ VAR1[09];
assign VAR13[26] = VAR7[26] ^ VAR5[10] ^ VAR7[10] ^ VAR1[10];
assign VAR13[27] = VAR7[27] ^ VAR5[11] ^ VAR7[11] ^ VAR1[11];
assign VAR13[28] = VAR7[28] ^ VAR5[12] ^ VAR7[12] ^ VAR1[12];
assign VAR13[29] = VAR7[29] ^ VAR5[13] ^ VAR7[13] ^ VAR1[13];
assign VAR13[30] = VAR7[30] ^ VAR5[14] ^ VAR7[14] ^ VAR1[14];
assign VAR13[31] = VAR5[15] ^ VAR7[15] ^ VAR1[15];
assign VAR13[32] = VAR5[16] ^ VAR7[16] ^ VAR1[16] ^ VAR5[00];
assign VAR13[33] = VAR5[17] ^ VAR7[17] ^ VAR1[17] ^ VAR5[01];
assign VAR13[34] = VAR5[18] ^ VAR7[18] ^ VAR1[18] ^ VAR5[02];
assign VAR13[35] = VAR7[19] ^ VAR1[19] ^ VAR5[03];
assign VAR13[36] = VAR7[20] ^ VAR1[20] ^ VAR5[04];
assign VAR13[37] = VAR7[21] ^ VAR1[21] ^ VAR5[05];
assign VAR13[38] = VAR7[22] ^ VAR1[22] ^ VAR5[06];
assign VAR13[39] = VAR7[23] ^ VAR1[23] ^ VAR5[07];
assign VAR13[40] = VAR7[24] ^ VAR1[24] ^ VAR5[08];
assign VAR13[41] = VAR7[25] ^ VAR1[25] ^ VAR5[09];
assign VAR13[42] = VAR7[26] ^ VAR1[26] ^ VAR5[10];
assign VAR13[43] = VAR7[27] ^ VAR1[27] ^ VAR5[11];
assign VAR13[44] = VAR7[28] ^ VAR1[28] ^ VAR5[12];
assign VAR13[45] = VAR7[29] ^ VAR1[29] ^ VAR5[13];
assign VAR13[46] = VAR7[30] ^ VAR1[30] ^ VAR5[14];
assign VAR13[47] = VAR5[15];
assign VAR13[48] = VAR5[16];
assign VAR13[49] = VAR5[17];
assign VAR13[50] = VAR5[18];
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.functional.pp.v | 1,681 | module MODULE1 (
VAR6,
VAR1,
VAR7 ,
VAR5 ,
VAR8
);
input VAR6;
input VAR1;
output VAR7 ;
input VAR5 ;
input VAR8 ;
wire VAR10 ;
wire VAR11;
nor VAR4 (VAR10 , VAR5, VAR8 );
VAR9 VAR3 (VAR11, VAR10, VAR6, VAR1);
buf VAR2 (VAR7 , VAR11 );
endmodule | apache-2.0 |
olajep/oh | src/common/hdl/oh_clockmux.v | 1,186 | module MODULE1 #(parameter VAR6 = 1) (
input [VAR6-1:0] en, input [VAR6-1:0] VAR1, output VAR10
);
localparam VAR3 = VAR9;
generate
if(VAR3& (VAR6==2))
begin : VAR4
VAR8 VAR7 (.VAR1(VAR1[VAR6-1:0]),
.en(en[VAR6-1:0]),
.VAR10(VAR10));
end
else if(VAR3 & (VAR6==4))
begin : VAR4
VAR2 VAR7 (.VAR1(VAR1[VAR6-1:0]),
.en(en[VAR6-1:0]),
.VAR10(VAR10));
end
else
begin : VAR5
assign VAR10 = |(VAR1[VAR6-1:0] & en[VAR6-1:0]);
end
endgenerate
endmodule | mit |
olajep/oh | src/common/hdl/oh_ser2par.v | 1,168 | module MODULE1 #(parameter VAR6 = 64, parameter VAR5 = 1, parameter VAR1 = VAR8(VAR6/VAR5) )
(
input clk, input [VAR5-1:0] din, output reg [VAR6-1:0] dout, input VAR3, input VAR4 );
reg [VAR1-1:0] VAR2;
wire [VAR6-1:0] VAR7;
always @ (posedge clk)
if(VAR4 & VAR3)
dout[VAR6-1:0] <= {din[VAR5-1:0],dout[VAR6-1:VAR5]};
else if(VAR4)
dout[VAR6-1:0] <= {dout[VAR6-VAR5-1:0],din[VAR5-1:0]};
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.blackbox.v | 1,324 | module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
supply1 VAR5;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
hanw/sonic-lite | hw/verilog/enc_dec/decoder.v | 37,401 | module MODULE1 (clk, VAR50, VAR67, VAR38, VAR15, VAR64, VAR51, VAR45);
input clk;
input[65:0] VAR50;
output[63:0] VAR67;
wire[63:0] VAR67;
output[7:0] VAR38;
wire[7:0] VAR38;
output [2:0] VAR15;
wire [2:0] VAR15;
input VAR64;
input VAR51;
output[7:0] VAR45;
wire[7:0] VAR45;
reg[7:0] VAR6;
reg[7:0] VAR23;
reg[7:0] VAR3;
reg[7:0] VAR36;
reg[7:0] VAR40;
reg[7:0] VAR44;
reg[7:0] VAR4;
reg[7:0] VAR37;
reg VAR14;
reg VAR58;
reg VAR7;
reg VAR62;
reg VAR28;
reg VAR57;
reg VAR48;
reg VAR43;
wire[1:0] VAR9;
wire[7:0] VAR22;
wire[65:0] VAR18;
wire VAR61;
wire VAR34;
wire VAR31;
wire VAR24;
wire VAR8;
wire VAR20;
wire VAR21;
wire VAR39;
wire VAR49;
wire VAR26;
wire VAR69;
wire VAR54;
wire VAR29;
wire VAR53;
wire VAR42;
wire VAR27;
wire VAR30;
reg[14:0] VAR52;
wire[65:0] VAR1;
reg[65:0] VAR59;
reg[7:0] VAR47;
reg[7:0] VAR25;
reg[7:0] VAR5;
reg[7:0] VAR63;
reg[7:0] VAR2;
reg[7:0] VAR68;
reg[7:0] VAR16;
reg[7:0] VAR32;
reg VAR19;
reg VAR11;
reg VAR17;
reg VAR66;
wire VAR46;
reg [2:0] VAR65;
wire[2:0] VAR41;
wire[2:0] VAR55;
wire VAR12;
wire VAR70;
parameter VAR35 = 1;
parameter [2:0] VAR13 = 3'b000;
parameter [2:0] VAR10 = 3'b001;
parameter [2:0] VAR60 = 3'b010;
parameter [2:0] VAR56 = 3'b011;
parameter [2:0] VAR33 = 3'b100;
assign VAR12 = 1'b0 ;
assign VAR1 = VAR50 ;
assign VAR46 = VAR51 | ~(VAR64) ;
assign VAR9 = VAR1[1:0] ;
assign VAR22 = VAR1[9:2] ;
assign VAR18 = VAR1 ;
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR59 <= #VAR35 {66{1'b0}} ;
end
else
begin
VAR59 <= #VAR35 VAR18 ;
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR47 <= #VAR35 {8{1'b0}} ;
end
else
begin
if (VAR18[16:10] == 7'b0000000)
begin
VAR47 <= #VAR35 8'b00000111 ; end
else if (VAR18[16:10] == 7'b0101101)
begin
VAR47 <= #VAR35 8'b00011100 ; end
else if (VAR18[16:10] == 7'b0110011)
begin
VAR47 <= #VAR35 8'b00111100 ; end
else if (VAR18[16:10] == 7'b1001011)
begin
VAR47 <= #VAR35 8'b01111100 ; end
else if (VAR18[16:10] == 7'b1010101)
begin
VAR47 <= #VAR35 8'b10111100 ; end
else if (VAR18[16:10] == 7'b1100110)
begin
VAR47 <= #VAR35 8'b11011100 ; end
else if (VAR18[16:10] == 7'b1111000)
begin
VAR47 <= #VAR35 8'b11110111 ; end
else
begin
VAR47 <= #VAR35 8'b11111110 ; end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR19 <= #VAR35 1'b0 ;
VAR11 <= #VAR35 1'b0 ;
end
else
begin
VAR19 <= #VAR35 (VAR9[0] & ~(VAR9[1])) & ((VAR20 | VAR21 | VAR49) & ~(VAR18[35]) & ~(VAR18[34]) & ~(VAR18[33]) & ~(VAR18[32])) ;
VAR11 <= #VAR35 (VAR9[0] & ~(VAR9[1])) & ((VAR20 | VAR21 | VAR49) & VAR18[35] & VAR18[34] & VAR18[33] & VAR18[32]) ;
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR25 <= #VAR35 {8{1'b0}} ;
end
else
begin
if (VAR18[23:17] == 7'b0000000)
begin
VAR25 <= #VAR35 8'b00000111 ; end
else if (VAR18[23:17] == 7'b0101101)
begin
VAR25 <= #VAR35 8'b00011100 ; end
else if (VAR18[23:17] == 7'b0110011)
begin
VAR25 <= #VAR35 8'b00111100 ; end
else if (VAR18[23:17] == 7'b1001011)
begin
VAR25 <= #VAR35 8'b01111100 ; end
else if (VAR18[23:17] == 7'b1010101)
begin
VAR25 <= #VAR35 8'b10111100 ; end
else if (VAR18[23:17] == 7'b1100110)
begin
VAR25 <= #VAR35 8'b11011100 ; end
else if (VAR18[23:17] == 7'b1111000)
begin
VAR25 <= #VAR35 8'b11110111 ; end
else
begin
VAR25 <= #VAR35 8'b11111110 ; end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR5 <= #VAR35 {8{1'b0}} ;
end
else
begin
if (VAR18[30:24] == 7'b0000000)
begin
VAR5 <= #VAR35 8'b00000111 ; end
else if (VAR18[30:24] == 7'b0101101)
begin
VAR5 <= #VAR35 8'b00011100 ; end
else if (VAR18[30:24] == 7'b0110011)
begin
VAR5 <= #VAR35 8'b00111100 ; end
else if (VAR18[30:24] == 7'b1001011)
begin
VAR5 <= #VAR35 8'b01111100 ; end
else if (VAR18[30:24] == 7'b1010101)
begin
VAR5 <= #VAR35 8'b10111100 ; end
else if (VAR18[30:24] == 7'b1100110)
begin
VAR5 <= #VAR35 8'b11011100 ; end
else if (VAR18[30:24] == 7'b1111000)
begin
VAR5 <= #VAR35 8'b11110111 ; end
else
begin
VAR5 <= #VAR35 8'b11111110 ; end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR63 <= #VAR35 {8{1'b0}} ;
end
else
begin
if (VAR18[37:31] == 7'b0000000)
begin
VAR63 <= #VAR35 8'b00000111 ; end
else if (VAR18[37:31] == 7'b0101101)
begin
VAR63 <= #VAR35 8'b00011100 ; end
else if (VAR18[37:31] == 7'b0110011)
begin
VAR63 <= #VAR35 8'b00111100 ; end
else if (VAR18[37:31] == 7'b1001011)
begin
VAR63 <= #VAR35 8'b01111100 ; end
else if (VAR18[37:31] == 7'b1010101)
begin
VAR63 <= #VAR35 8'b10111100 ; end
else if (VAR18[37:31] == 7'b1100110)
begin
VAR63 <= #VAR35 8'b11011100 ; end
else if (VAR18[37:31] == 7'b1111000)
begin
VAR63 <= #VAR35 8'b11110111 ; end
else
begin
VAR63 <= #VAR35 8'b11111110 ; end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR2 <= #VAR35 {8{1'b0}} ;
end
else
begin
if (VAR18[44:38] == 7'b0000000)
begin
VAR2 <= #VAR35 8'b00000111 ; end
else if (VAR18[44:38] == 7'b0101101)
begin
VAR2 <= #VAR35 8'b00011100 ; end
else if (VAR18[44:38] == 7'b0110011)
begin
VAR2 <= #VAR35 8'b00111100 ; end
else if (VAR18[44:38] == 7'b1001011)
begin
VAR2 <= #VAR35 8'b01111100 ; end
else if (VAR18[44:38] == 7'b1010101)
begin
VAR2 <= #VAR35 8'b10111100 ; end
else if (VAR18[44:38] == 7'b1100110)
begin
VAR2 <= #VAR35 8'b11011100 ; end
else if (VAR18[44:38] == 7'b1111000)
begin
VAR2 <= #VAR35 8'b11110111 ; end
else
begin
VAR2 <= #VAR35 8'b11111110 ; end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR17 <= #VAR35 1'b0 ;
VAR66 <= #VAR35 1'b0 ;
end
else
begin
VAR17 <= #VAR35 (VAR9[0] & ~(VAR9[1])) & ((VAR24 | VAR21) & ~(VAR18[39]) & ~(VAR18[38]) & ~(VAR18[37]) & ~(VAR18[36])) ;
VAR66 <= #VAR35 (VAR9[0] & ~(VAR9[1])) & ((VAR24 | VAR21) & VAR18[39] & VAR18[38] & VAR18[37] & VAR18[36]) ;
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR68 <= #VAR35 {8{1'b0}} ;
end
else
begin
if (VAR18[51:45] == 7'b0000000)
begin
VAR68 <= #VAR35 8'b00000111 ; end
else if (VAR18[51:45] == 7'b0101101)
begin
VAR68 <= #VAR35 8'b00011100 ; end
else if (VAR18[51:45] == 7'b0110011)
begin
VAR68 <= #VAR35 8'b00111100 ; end
else if (VAR18[51:45] == 7'b1001011)
begin
VAR68 <= #VAR35 8'b01111100 ; end
else if (VAR18[51:45] == 7'b1010101)
begin
VAR68 <= #VAR35 8'b10111100 ; end
else if (VAR18[51:45] == 7'b1100110)
begin
VAR68 <= #VAR35 8'b11011100 ; end
else if (VAR18[51:45] == 7'b1111000)
begin
VAR68 <= #VAR35 8'b11110111 ; end
else
begin
VAR68 <= #VAR35 8'b11111110 ; end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR16 <= #VAR35 {8{1'b0}} ;
end
else
begin
if (VAR18[58:52] == 7'b0000000)
begin
VAR16 <= #VAR35 8'b00000111 ; end
else if (VAR18[58:52] == 7'b0101101)
begin
VAR16 <= #VAR35 8'b00011100 ; end
else if (VAR18[58:52] == 7'b0110011)
begin
VAR16 <= #VAR35 8'b00111100 ; end
else if (VAR18[58:52] == 7'b1001011)
begin
VAR16 <= #VAR35 8'b01111100 ; end
else if (VAR18[58:52] == 7'b1010101)
begin
VAR16 <= #VAR35 8'b10111100 ; end
else if (VAR18[58:52] == 7'b1100110)
begin
VAR16 <= #VAR35 8'b11011100 ; end
else if (VAR18[58:52] == 7'b1111000)
begin
VAR16 <= #VAR35 8'b11110111 ; end
else
begin
VAR16 <= #VAR35 8'b11111110 ; end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR32 <= #VAR35 {8{1'b0}} ;
end
else
begin
if (VAR18[65:59] == 7'b0000000)
begin
VAR32 <= #VAR35 8'b00000111 ; end
else if (VAR18[65:59] == 7'b0101101)
begin
VAR32 <= #VAR35 8'b00011100 ; end
else if (VAR18[65:59] == 7'b0110011)
begin
VAR32 <= #VAR35 8'b00111100 ; end
else if (VAR18[65:59] == 7'b1001011)
begin
VAR32 <= #VAR35 8'b01111100 ; end
else if (VAR18[65:59] == 7'b1010101)
begin
VAR32 <= #VAR35 8'b10111100 ; end
else if (VAR18[65:59] == 7'b1100110)
begin
VAR32 <= #VAR35 8'b11011100 ; end
else if (VAR18[65:59] == 7'b1111000)
begin
VAR32 <= #VAR35 8'b11110111 ; end
else
begin
VAR32 <= #VAR35 8'b11111110 ; end
end
end
assign VAR61 = ~(VAR9[0]) & VAR9[1] ;
assign VAR34 = VAR9[0] & ~(VAR9[1]) ;
assign VAR31 = ~(VAR22[7]) & ~(VAR22[6]) & ~(VAR22[5]) & VAR22[4] & VAR22[3] & VAR22[2] & VAR22[1] & ~(VAR22[0]) ;
assign VAR24 = ~(VAR22[7]) & ~(VAR22[6]) & VAR22[5] & ~(VAR22[4]) & VAR22[3] & VAR22[2] & ~(VAR22[1]) & VAR22[0] ;
assign VAR8 = ~(VAR22[7]) & ~(VAR22[6]) & VAR22[5] & VAR22[4] & ~(VAR22[3]) & ~(VAR22[2]) & VAR22[1] & VAR22[0] ;
assign VAR20 = ~(VAR22[7]) & VAR22[6] & VAR22[5] & ~(VAR22[4]) & ~(VAR22[3]) & VAR22[2] & VAR22[1] & ~(VAR22[0]) ;
assign VAR21 = ~(VAR22[7]) & VAR22[6] & ~(VAR22[5]) & VAR22[4] & ~(VAR22[3]) & VAR22[2] & ~(VAR22[1]) & VAR22[0] ;
assign VAR39 = ~(VAR22[7]) & VAR22[6] & VAR22[5] & VAR22[4] & VAR22[3] & ~(VAR22[2]) & ~(VAR22[1]) & ~(VAR22[0]) ;
assign VAR49 = ~(VAR22[7]) & VAR22[6] & ~(VAR22[5]) & ~(VAR22[4]) & VAR22[3] & ~(VAR22[2]) & VAR22[1] & VAR22[0] ;
assign VAR26 = VAR22[7] & ~(VAR22[6]) & ~(VAR22[5]) & ~(VAR22[4]) & ~(VAR22[3]) & VAR22[2] & VAR22[1] & VAR22[0] ;
assign VAR69 = VAR22[7] & ~(VAR22[6]) & ~(VAR22[5]) & VAR22[4] & VAR22[3] & ~(VAR22[2]) & ~(VAR22[1]) & VAR22[0] ;
assign VAR54 = VAR22[7] & ~(VAR22[6]) & VAR22[5] & ~(VAR22[4]) & VAR22[3] & ~(VAR22[2]) & VAR22[1] & ~(VAR22[0]) ;
assign VAR29 = VAR22[7] & ~(VAR22[6]) & VAR22[5] & VAR22[4] & ~(VAR22[3]) & VAR22[2] & ~(VAR22[1]) & ~(VAR22[0]) ;
assign VAR53 = VAR22[7] & VAR22[6] & ~(VAR22[5]) & ~(VAR22[4]) & VAR22[3] & VAR22[2] & ~(VAR22[1]) & ~(VAR22[0]) ;
assign VAR42 = VAR22[7] & VAR22[6] & ~(VAR22[5]) & VAR22[4] & ~(VAR22[3]) & ~(VAR22[2]) & VAR22[1] & ~(VAR22[0]) ;
assign VAR27 = VAR22[7] & VAR22[6] & VAR22[5] & ~(VAR22[4]) & ~(VAR22[3]) & ~(VAR22[2]) & ~(VAR22[1]) & VAR22[0] ;
assign VAR30 = VAR22[7] & VAR22[6] & VAR22[5] & VAR22[4] & VAR22[3] & VAR22[2] & VAR22[1] & VAR22[0] ;
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR52 <= #VAR35 {15{1'b0}} ;
end
else
begin
VAR52 <= #VAR35 ({(VAR34 & VAR30), (VAR34 & VAR27), (VAR34 & VAR42), (VAR34 & VAR53), (VAR34 & VAR29), (VAR34 & VAR54), (VAR34 & VAR69), (VAR34 & VAR26), (VAR34 & VAR49), (VAR34 & VAR39), (VAR34 & VAR21), (VAR34 & VAR20), (VAR34 & VAR8), (VAR34 & VAR24), (VAR34 & VAR31)}) ;
end
end
always @(posedge VAR51 or posedge clk)
begin if (VAR51 == 1'b1)
begin
VAR65 <= #VAR35 VAR13 ;
end
else
begin
if (VAR34 == 1'b1 & (VAR30 == 1'b1 | VAR27 == 1'b1 | VAR42 == 1'b1 | VAR53 == 1'b1 | VAR29 == 1'b1 | VAR54 == 1'b1 | VAR69 == 1'b1 | VAR26 == 1'b1))
begin
VAR65 <= #VAR35 VAR56 ;
end
else if (VAR34 == 1'b1 & (VAR31 == 1'b1 | VAR24 == 1'b1 | VAR21 == 1'b1 | VAR49 == 1'b1))
begin
VAR65 <= #VAR35 VAR13 ;
end
else if (VAR34 == 1'b1 & (VAR8 == 1'b1 | VAR20 == 1'b1 | VAR39 == 1'b1))
begin
VAR65 <= #VAR35 VAR10 ;
end
else if (VAR34 == 1'b0)
begin
VAR65 <= #VAR35 VAR60 ;
end
else
begin
VAR65 <= #VAR35 VAR33 ;
end
end
end
assign VAR15 = VAR65 ;
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR6 <= #VAR35 {8{1'b0}} ;
VAR14 <= #VAR35 1'b0 ;
end
else
begin
if (VAR52[2:0] != 3'b000)
begin
VAR6 <= #VAR35 VAR47 ; VAR14 <= #VAR35 1'b1 ;
end
else if ((VAR52[3]) == 1'b1 & VAR19 == 1'b1)
begin
VAR6 <= #VAR35 8'b10011100 ; VAR14 <= #VAR35 1'b1 ;
end
else if ((VAR52[3]) == 1'b1 & VAR11 == 1'b1)
begin
VAR6 <= #VAR35 8'b01011100 ; VAR14 <= #VAR35 1'b1 ;
end
else if ((VAR52[4]) == 1'b1 & VAR19 == 1'b1)
begin
VAR6 <= #VAR35 8'b10011100 ; VAR14 <= #VAR35 1'b1 ;
end
else if ((VAR52[4]) == 1'b1 & VAR11 == 1'b1)
begin
VAR6 <= #VAR35 8'b01011100 ; VAR14 <= #VAR35 1'b1 ;
end
else if ((VAR52[5]) == 1'b1)
begin
VAR6 <= #VAR35 8'b11111011 ; VAR14 <= #VAR35 1'b1 ;
end
else if ((VAR52[6]) == 1'b1 & VAR19 == 1'b1)
begin
VAR6 <= #VAR35 8'b10011100 ; VAR14 <= #VAR35 1'b1 ;
end
else if ((VAR52[6]) == 1'b1 & VAR11 == 1'b1)
begin
VAR6 <= #VAR35 8'b01011100 ; VAR14 <= #VAR35 1'b1 ;
end
else if ((VAR52[7]) == 1'b1)
begin
VAR6 <= #VAR35 8'b11111101 ; VAR14 <= #VAR35 1'b1 ;
end
else if (VAR52[14:8] != 7'b0000000)
begin
VAR6 <= #VAR35 VAR59[17:10] ; VAR14 <= #VAR35 1'b0 ;
end
else
begin
VAR6 <= #VAR35 VAR59[9:2] ;
VAR14 <= #VAR35 1'b0 ;
end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR23 <= #VAR35 {8{1'b0}} ;
VAR58 <= #VAR35 1'b0 ;
end
else
begin
if (VAR52[2:0] != 3'b000)
begin
VAR23 <= #VAR35 VAR25 ; VAR58 <= #VAR35 1'b1 ;
end
else if (VAR52[6:3] != 3'b000)
begin
VAR23 <= #VAR35 VAR59[17:10] ; VAR58 <= #VAR35 1'b0 ;
end
else if ((VAR52[7]) == 1'b1)
begin
VAR23 <= #VAR35 VAR25 ; VAR58 <= #VAR35 1'b1 ;
end
else if ((VAR52[8]) == 1'b1)
begin
VAR23 <= #VAR35 8'b11111101 ; VAR58 <= #VAR35 1'b1 ;
end
else if (VAR52[14:9] != 6'b000000)
begin
VAR23 <= #VAR35 VAR59[25:18] ; VAR58 <= #VAR35 1'b0 ;
end
else
begin
VAR23 <= #VAR35 VAR59[17:10] ;
VAR58 <= #VAR35 1'b0 ;
end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR3 <= #VAR35 {8{1'b0}} ;
VAR7 <= #VAR35 1'b0 ;
end
else
begin
if (VAR52[2:0] != 3'b000 | VAR52[8:7] != 2'b00)
begin
VAR3 <= #VAR35 VAR5 ; VAR7 <= #VAR35 1'b1 ;
end
else if (VAR52[6:3] != 3'b000)
begin
VAR3 <= #VAR35 VAR59[25:18] ; VAR7 <= #VAR35 1'b0 ;
end
else if ((VAR52[9]) == 1'b1)
begin
VAR3 <= #VAR35 8'b11111101 ; VAR7 <= #VAR35 1'b1 ;
end
else if (VAR52[14:10] != 5'b00000)
begin
VAR3 <= #VAR35 VAR59[33:26] ; VAR7 <= #VAR35 1'b0 ;
end
else
begin
VAR3 <= #VAR35 VAR59[25:18] ;
VAR7 <= #VAR35 1'b0 ;
end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR36 <= #VAR35 {8{1'b0}} ;
VAR62 <= #VAR35 1'b0 ;
end
else
begin
if (VAR52[2:0] != 3'b000 | VAR52[9:7] != 3'b000)
begin
VAR36 <= #VAR35 VAR63 ; VAR62 <= #VAR35 1'b1 ;
end
else if (VAR52[6:3] != 3'b000)
begin
VAR36 <= #VAR35 VAR59[33:26] ; VAR62 <= #VAR35 1'b0 ;
end
else if ((VAR52[10]) == 1'b1)
begin
VAR36 <= #VAR35 8'b11111101 ; VAR62 <= #VAR35 1'b1 ;
end
else if (VAR52[14:11] != 4'b0000)
begin
VAR36 <= #VAR35 VAR59[41:34] ; VAR62 <= #VAR35 1'b0 ;
end
else
begin
VAR36 <= #VAR35 VAR59[33:26] ;
VAR62 <= #VAR35 1'b0 ;
end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR40 <= #VAR35 {8{1'b0}} ;
VAR28 <= #VAR35 1'b0 ;
end
else
begin
if ((VAR52[0]) == 1'b1 | VAR52[10:6] != 5'b00000)
begin
VAR40 <= #VAR35 VAR2 ; VAR28 <= #VAR35 1'b1 ;
end
else if ((VAR52[1]) == 1'b1 & VAR17 == 1'b1)
begin
VAR40 <= #VAR35 8'b10011100 ; VAR28 <= #VAR35 1'b1 ;
end
else if ((VAR52[1]) == 1'b1 & VAR66 == 1'b1)
begin
VAR40 <= #VAR35 8'b01011100 ; VAR28 <= #VAR35 1'b1 ;
end
else if ((VAR52[2]) == 1'b1)
begin
VAR40 <= #VAR35 8'b11111011 ; VAR28 <= #VAR35 1'b1 ;
end
else if ((VAR52[3]) == 1'b1)
begin
VAR40 <= #VAR35 8'b11111011 ; VAR28 <= #VAR35 1'b1 ;
end
else if ((VAR52[4]) == 1'b1 & VAR17 == 1'b1)
begin
VAR40 <= #VAR35 8'b10011100 ; VAR28 <= #VAR35 1'b1 ;
end
else if ((VAR52[4]) == 1'b1 & VAR66 == 1'b1)
begin
VAR40 <= #VAR35 8'b01011100 ; VAR28 <= #VAR35 1'b1 ;
end
else if ((VAR52[5]) == 1'b1)
begin
VAR40 <= #VAR35 VAR59[41:34] ; VAR28 <= #VAR35 1'b0 ;
end
else if ((VAR52[11]) == 1'b1)
begin
VAR40 <= #VAR35 8'b11111101 ; VAR28 <= #VAR35 1'b1 ;
end
else if (VAR52[14:12] != 3'b000)
begin
VAR40 <= #VAR35 VAR59[49:42] ; VAR28 <= #VAR35 1'b0 ;
end
else
begin
VAR40 <= #VAR35 VAR59[41:34] ;
VAR28 <= #VAR35 1'b0 ;
end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR44 <= #VAR35 {8{1'b0}} ;
VAR57 <= #VAR35 1'b0 ;
end
else
begin
if ((VAR52[0]) == 1'b1 | VAR52[11:6] != 6'b000000)
begin
VAR44 <= #VAR35 VAR68 ; VAR57 <= #VAR35 1'b1 ;
end
else if (VAR52[5:1] != 5'b00000)
begin
VAR44 <= #VAR35 VAR59[49:42] ; VAR57 <= #VAR35 1'b0 ;
end
else if ((VAR52[12]) == 1'b1)
begin
VAR44 <= #VAR35 8'b11111101 ; VAR57 <= #VAR35 1'b1 ;
end
else if (VAR52[14:13] != 2'b00)
begin
VAR44 <= #VAR35 VAR59[57:50] ; VAR57 <= #VAR35 1'b0 ;
end
else
begin
VAR44 <= #VAR35 VAR59[49:42] ;
VAR57 <= #VAR35 1'b0 ;
end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR4 <= #VAR35 {8{1'b0}} ;
VAR48 <= #VAR35 1'b0 ;
end
else
begin
if ((VAR52[0]) == 1'b1 | VAR52[12:6] != 7'b0000000)
begin
VAR4 <= #VAR35 VAR16 ; VAR48 <= #VAR35 1'b1 ;
end
else if (VAR52[5:1] != 5'b00000)
begin
VAR4 <= #VAR35 VAR59[57:50] ; VAR48 <= #VAR35 1'b0 ;
end
else if ((VAR52[13]) == 1'b1)
begin
VAR4 <= #VAR35 8'b11111101 ; VAR48 <= #VAR35 1'b1 ;
end
else if ((VAR52[14]) == 1'b1)
begin
VAR4 <= #VAR35 VAR59[65:58] ; VAR48 <= #VAR35 1'b0 ;
end
else
begin
VAR4 <= #VAR35 VAR59[57:50] ;
VAR48 <= #VAR35 1'b0 ;
end
end
end
always @(posedge VAR46 or posedge clk)
begin if (VAR46 == 1'b1)
begin
VAR37 <= #VAR35 {8{1'b0}} ;
VAR43 <= #VAR35 1'b0 ;
end
else
begin
if ((VAR52[0]) == 1'b1 | VAR52[13:6] != 8'b00000000)
begin
VAR37 <= #VAR35 VAR32 ; VAR43 <= #VAR35 1'b1 ;
end
else if (VAR52[5:1] != 5'b00000)
begin
VAR37 <= #VAR35 VAR59[65:58] ; VAR43 <= #VAR35 1'b0 ;
end
else if ((VAR52[14]) == 1'b1)
begin
VAR37 <= #VAR35 8'b11111101 ; VAR43 <= #VAR35 1'b1 ;
end
else
begin
VAR37 <= #VAR35 VAR59[65:58] ;
VAR43 <= #VAR35 1'b0 ;
end
end
end
assign VAR67 = {VAR37, VAR4, VAR44, VAR40, VAR36, VAR3, VAR23, VAR6} ;
assign VAR38 = {VAR43, VAR48, VAR57, VAR28, VAR62, VAR7, VAR58, VAR14} ;
endmodule | mit |
jbelloncastro/amber_arm | hw/vlog/amber23/a23_fetch.v | 8,195 | module MODULE1
(
input VAR25,
input [31:0] VAR30,
input VAR17,
input [31:0] VAR4, input [31:0] VAR29,
input VAR22,
output [31:0] VAR13,
input VAR16,
input VAR23, input [3:0] VAR19,
input VAR2, input VAR11, input VAR44, input [31:0] VAR1, input VAR9,
output VAR18,
output [31:0] VAR12,
output [3:0] VAR36,
output VAR7,
input [31:0] VAR35,
output [31:0] VAR15,
output VAR27,
output VAR45,
input VAR24,
input VAR28
);
wire VAR20;
wire VAR38;
wire [31:0] VAR34;
wire VAR40;
wire VAR33;
wire VAR3;
wire VAR8;
assign VAR8 = VAR14( VAR30 ) && VAR1[VAR30[25:21]];
assign VAR40 = VAR8 && VAR17 && VAR11 && !VAR23;
assign VAR33 = !VAR40 && VAR17 && !(VAR20);
assign VAR13 = VAR40 ? VAR34 :
VAR33 ? VAR35 :
32'hffeeddcc ;
assign VAR18 = !VAR9 || VAR38 || VAR20;
VAR31 VAR32 (
.VAR25 ( VAR25 ),
.VAR37 ( VAR40 ),
.VAR23 ( VAR23 ),
.VAR29 ( VAR29 ),
.VAR22 ( VAR22 ),
.VAR30 ( VAR30 ),
.VAR4 ( VAR4 ),
.VAR19 ( VAR19 ),
.VAR11 ( VAR11 ),
.VAR44 ( VAR44 ),
.VAR13 ( VAR34 ),
.VAR10 ( VAR20 ),
.VAR42 ( VAR18 ),
.VAR21 ( VAR3 ),
.VAR6 ( VAR12 ),
.VAR26 ( VAR35 ),
.VAR41 ( VAR45 & ~VAR24 )
);
VAR5 VAR43 (
.VAR25 ( VAR25 ),
.VAR37 ( VAR33 ),
.VAR29 ( VAR29 ),
.VAR22 ( VAR22 ),
.VAR19 ( VAR19 ),
.VAR2 ( VAR2 ),
.VAR23 ( VAR23 ),
.VAR30 ( VAR30 ),
.VAR10 ( VAR38 ),
.VAR39 ( VAR3 ),
.VAR12 ( VAR12 ),
.VAR36 ( VAR36 ),
.VAR7 ( VAR7 ),
.VAR35 ( VAR35 ),
.VAR15 ( VAR15 ),
.VAR27 ( VAR27 ),
.VAR45 ( VAR45 ),
.VAR24 ( VAR24 ),
.VAR28 ( VAR28 )
);
endmodule | lgpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/rx_queue.v | 18,554 | module MODULE1
parameter VAR120 = VAR113/8,
parameter VAR98 = 0,
parameter VAR131 = 'hff,
parameter VAR64 = 0
)
(output reg [VAR113-1:0] VAR42,
output reg [VAR120-1:0] VAR38,
output reg VAR121,
input VAR44,
input [7:0] VAR58,
input VAR89,
input VAR61,
input VAR25,
output VAR77,
output VAR23,
output VAR7,
output reg [11:0] VAR47,
output reg [9:0] VAR12,
output reg VAR96,
input VAR52,
input reset,
input clk,
input VAR41
);
function integer VAR67;
input integer VAR8;
begin
VAR67=0;
while(2**VAR67<VAR8) begin
VAR67=VAR67+1;
end
end
endfunction
parameter VAR48 = 0;
parameter VAR97 = 1;
parameter VAR85 = 2;
parameter VAR29 = 1;
parameter VAR128 = 2;
parameter VAR21 = 4;
parameter VAR115= 8;
parameter VAR127 = 16;
parameter VAR73 = 32;
localparam VAR4 = 2048;
localparam VAR51 = VAR67(VAR120);
localparam VAR81 = VAR67(VAR4)+1;
localparam VAR94 = VAR81 - VAR51;
wire [VAR120+VAR113-1:0]VAR119;
reg VAR11;
reg VAR118;
reg VAR130;
wire VAR45;
wire VAR105;
wire VAR10;
reg VAR88;
wire VAR84;
wire VAR59;
reg [1:0] VAR14;
reg [1:0] VAR102;
reg [7:0] VAR39;
reg VAR46;
reg [5:0] VAR125;
reg [5:0] VAR93;
reg VAR117;
reg VAR36;
reg VAR2;
reg VAR37;
reg [VAR81-1:0] VAR123;
wire [VAR81-1:0] VAR110;
wire [VAR94-1:0] VAR34;
reg VAR79;
wire [VAR113-1:0] VAR91;
wire [VAR120-1:0] VAR95;
reg VAR17;
reg VAR19;
wire [VAR28 - VAR62-1:0] VAR31 = VAR64;
wire [12:0] VAR80;
reg VAR35;
generate
if(VAR113==32) begin: VAR124
VAR63 VAR129
(
.VAR6 ( reset ),
.VAR103 ( {VAR11,VAR39} ),
.VAR74 ( clk ),
.VAR20 ( VAR130 ),
.VAR40 ( VAR41 ),
.VAR56 ( VAR118 ),
.VAR109 ( VAR119 ),
.VAR114 ( VAR45 ),
.VAR65 ( VAR105 ),
.VAR80 ( VAR80 ) );
end
else if(VAR113==64) begin: VAR18
VAR9 VAR129
(
.VAR6 ( reset ),
.VAR103 ( {VAR11,VAR39} ),
.VAR74 ( clk ),
.VAR20 ( VAR130 ),
.VAR40 ( VAR41 ),
.VAR56 ( VAR118 ),
.VAR109 ( VAR119 ),
.VAR114 ( VAR45 ),
.VAR65 ( VAR105 ),
.VAR80 ( VAR80 )
);
end
endgenerate
generate
if (VAR98) begin
VAR55 VAR100
(
.VAR6 ( reset ),
.VAR103 ( {VAR36, VAR123} ),
.VAR74 ( clk ),
.VAR20 ( VAR88 ),
.VAR40 ( VAR41 ),
.VAR56 ( VAR117 | VAR36 ),
.VAR109 ( {VAR84, VAR110} ),
.VAR114 ( VAR59 ),
.VAR65 ( )
);
end
else begin
VAR27
.VAR26(7))
VAR100
( .din (VAR77),
.VAR116 (VAR23 | VAR77),
.VAR33 (VAR88),
.dout (VAR84),
.VAR60 (),
.VAR53 (),
.VAR111 (),
.VAR132 (VAR59),
.reset (reset),
.clk (clk)
);
end endgenerate
VAR78 VAR112
(.VAR87 (VAR117),
.VAR126 (VAR41),
.VAR69(VAR23),
.VAR75 (clk),
.VAR70 (VAR37),
.VAR90 (reset));
VAR78 VAR92
(.VAR87 (VAR36),
.VAR126 (VAR41),
.VAR69(VAR77),
.VAR75 (clk),
.VAR70 (VAR37),
.VAR90 (reset));
VAR78 VAR22
(.VAR87 (VAR2),
.VAR126 (VAR41),
.VAR69(VAR7),
.VAR75 (clk),
.VAR70 (VAR37),
.VAR90 (reset));
reg VAR106;
always @(posedge clk) begin
if (reset) VAR106 <= 1;
end
else if (VAR37) VAR106 <= 0;
end
always @(posedge VAR41) VAR37 <= VAR106;
generate
genvar VAR50;
if (VAR98) begin
wire [VAR113-1:0] VAR5;
wire [VAR120-1:0] VAR30;
for (VAR50=0; VAR50<VAR120; VAR50=VAR50+1) begin: VAR72
assign VAR5[(VAR120-1-VAR50)*8+7:(VAR120-1-VAR50)*8] =
VAR119[VAR50*9+7:VAR50*9];
assign VAR30[VAR50] = VAR119[VAR50*9+8];
end
assign VAR34 = VAR110[VAR51-1:0] == 0 ?
VAR110[VAR81-1:VAR51] :
VAR110[VAR81-1:VAR51] + 1;
assign VAR91 = VAR79 ?
{VAR34,
VAR31,
{(VAR62 - VAR81){1'b0}}, VAR110} : VAR5;
assign VAR95 = VAR79 ? VAR131 : VAR30;
end
else begin
for (VAR50=0; VAR50<VAR120; VAR50=VAR50+1) begin: VAR72
assign VAR91[(VAR120-1-VAR50)*8+7:(VAR120-1-VAR50)*8] =
VAR119[VAR50*9+7:VAR50*9];
assign VAR95[VAR50] = VAR119[VAR50*9+8];
end end endgenerate
always @ begin
VAR93 = VAR125;
VAR118 = 0;
VAR11 = 0;
VAR117 = 0;
VAR36 = 0;
VAR2 = 0;
case(VAR125)
VAR29: begin
if(VAR46 & !VAR10 & VAR52) begin
VAR118 = 1;
VAR93 = VAR128;
end
else if(VAR46) begin
VAR104("%VAR76 %VAR101 VAR54: MODULE1 MODULE1 VAR43 VAR57 VAR108 VAR43 VAR32 VAR60 or VAR82",
);
VAR93 = VAR73;
VAR2 = 1;
end
end
VAR128: begin
if(VAR105) begin
VAR104("%VAR76 %VAR101 VAR1: MODULE1 VAR32 VAR107 VAR24! VAR66 VAR122 VAR99 VAR71 VAR86 VAR83 VAR16",
);
end
VAR118 = 1;
if(!VAR89) begin
VAR11 = 1;
VAR93 = VAR115;
end
else if (VAR123 >= VAR4-2) begin
VAR11 = 1;
VAR93 = VAR127;
VAR117 = 1;
end end
VAR115: begin
if(VAR61) begin
VAR36 = 1;
VAR93 = VAR127;
end
else if(VAR25) begin
VAR117 = 1;
VAR93 = VAR127;
VAR104("%VAR76 %VAR101 VAR49: VAR66 with VAR68 VAR15 VAR13.",
);
end
end
VAR127: begin
if(VAR123[VAR51-1:0] == 0) begin
VAR93 = VAR29;
end
else begin
VAR118 = 1;
end
end
VAR73: begin
if(!VAR46) begin
VAR93 = VAR29;
end
end
default: begin end
endcase end
always @(posedge VAR41) begin
if(VAR37) begin
VAR125 <= VAR29;
VAR39 <= 0;
VAR46 <= 0;
VAR123 <= 0;
end
else begin
VAR125 <= VAR93;
VAR39 <= VAR58;
VAR46 <= VAR89;
if (VAR118)
VAR123 <= VAR123 + 'b1;
end
else if(VAR125 == VAR29)
VAR123 <= 0;
end
end
always @(posedge clk) begin
if(VAR7) begin
end
end
always @(posedge VAR41) begin
if ( VAR80 > 13'd6100) begin
VAR35 = 1'b1;
end
else
VAR35 = 1'b0;
end
assign VAR10 = VAR35;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | mult8x8_bb.v | 3,861 | module MODULE1 (
VAR3,
VAR1,
VAR2);
input [7:0] VAR3;
input [7:0] VAR1;
output [15:0] VAR2;
endmodule | mit |
hoangt/multiported-ram | lvt_1ht.v | 9,400 | module MODULE1
localparam VAR43 = VAR7(VAR22); localparam VAR16 = VAR9 - 1;
reg [VAR43*VAR9-1:0] VAR3; reg [ VAR9-1:0] VAR39 ; always @(posedge clk) begin
VAR3 <= VAR41;
VAR39 <= VAR4 ;
end
reg [VAR43 -1:0] VAR31 [VAR9-1:0] ; reg [VAR43 -1:0] VAR14 [VAR9-1:0] ; wire [VAR16 *VAR40-1:0] VAR30 [VAR9-1:0] ; reg [VAR16 -1:0] VAR12 [VAR9-1:0][VAR40-1:0]; reg [VAR43*VAR16 -1:0] VAR21 [VAR9-1:0] ; reg [VAR43 -1:0] VAR27 [VAR9-1:0][VAR16 -1:0]; wire [VAR16 *VAR16 -1:0] VAR34 [VAR9-1:0] ; reg [VAR16 -1:0] VAR37 [VAR9-1:0][VAR16 -1:0]; reg [VAR16 -1:0] VAR32 [VAR9-1:0] ; reg [VAR16 -1:0] VAR11 [VAR9-1:0] ; reg [VAR9 -1:0] VAR18 [VAR40-1:0] ; VAR15;
always @* begin
end
genvar VAR19;
generate
for (VAR19=0 ; VAR19<VAR9 ; VAR19=VAR19+1) begin: VAR25
VAR33 #( .VAR22 (VAR22 ), .VAR36 (VAR16 ), .VAR40(VAR9-1 ), .VAR29 (VAR28||VAR10||VAR24 ), .VAR38 (VAR38 ), .VAR1 (VAR1 )) VAR8 ( .clk (clk ), .VAR4 (VAR39[VAR19] ), .VAR41 (VAR14[VAR19] ), .VAR17 (VAR32[VAR19] ), .VAR26 (VAR21[VAR19] ), .VAR2 (VAR34[VAR19] )); VAR33 #( .VAR22 (VAR22 ), .VAR36 (VAR16 ), .VAR40(VAR40 ), .VAR29 (VAR10 ? 2 : VAR24 ), .VAR38 (VAR38 ), .VAR1 (VAR1 )) VAR42 ( .clk (clk ), .VAR4 (VAR39[VAR19] ), .VAR41 (VAR14[VAR19] ), .VAR17 (VAR32[VAR19] ), .VAR26 (VAR26 ), .VAR2 (VAR30[VAR19]));
end
endgenerate
integer VAR23; integer VAR5; integer VAR13; integer VAR6; integer VAR35; integer VAR20; always @* begin
for(VAR23=0;VAR23<VAR9;VAR23=VAR23+1) VAR11[VAR23] = (1<<VAR23)-1; for(VAR6=0;VAR6<VAR40;VAR6=VAR6+1)
for(VAR23=0;VAR23<VAR9;VAR23=VAR23+1)
VAR18[VAR6][VAR23] = 1;
for(VAR23=0;VAR23<VAR9;VAR23=VAR23+1) begin
VAR5 = 0;
for(VAR35=0;VAR35<VAR16;VAR35=VAR35+1) begin
VAR5=VAR5+(VAR35==VAR23);
VAR13=VAR23-(VAR5<VAR23);
VAR20=VAR23-(VAR11[VAR23][VAR35]);
VAR27[VAR23][VAR35] = VAR31[VAR5];
VAR32[VAR23][VAR35] = VAR37[VAR5][VAR13][VAR20] ^ VAR11[VAR23][VAR35];
for(VAR6=0;VAR6<VAR40;VAR6=VAR6+1) VAR18[VAR6][VAR23] = VAR18[VAR6][VAR23] && (( VAR12[VAR5][VAR6][VAR20] ^ VAR11[VAR23][VAR35]) == VAR12[VAR23][VAR6][VAR35]);
VAR5=VAR5+1;
end
end
end
endmodule | bsd-3-clause |
dcsun88/ntpserver-fpga | cpu/ip/cpu_auto_pc_0/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v | 10,416 | module MODULE1 #
(
parameter VAR33 = "none",
parameter integer VAR39 = 1,
parameter integer VAR6 = 32,
parameter integer VAR31 = 32,
parameter integer VAR21 = 0,
parameter integer VAR43 = 1,
parameter integer VAR32 = 1,
parameter integer VAR34 = 1
)
(
input wire VAR25,
input wire VAR4,
input wire VAR9,
input wire [VAR39-1:0] VAR22,
input wire [4-1:0] VAR1,
output wire VAR10,
input wire [VAR31-1:0] VAR37,
input wire [VAR31/8-1:0] VAR35,
input wire VAR36,
input wire [VAR43-1:0] VAR27,
input wire VAR8,
output wire VAR44,
output wire [VAR39-1:0] VAR41,
output wire [VAR31-1:0] VAR2,
output wire [VAR31/8-1:0] VAR15,
output wire VAR5,
output wire [VAR43-1:0] VAR29,
output wire VAR11,
input wire VAR40
);
reg VAR42;
reg [8-1:0] VAR23;
reg [8-1:0] VAR30;
wire [8-1:0] VAR13;
wire VAR7;
wire VAR3;
wire VAR20;
wire VAR12;
wire VAR24;
wire VAR16;
wire [VAR39-1:0] VAR14;
wire [VAR31-1:0] VAR19;
wire [VAR31/8-1:0] VAR28;
wire VAR17;
wire [VAR43-1:0] VAR38;
wire VAR26;
wire VAR18;
assign VAR16 = VAR8 & VAR9 & ~VAR24;
assign VAR44 = VAR16;
assign VAR26 = VAR8 & VAR9;
assign VAR12 = VAR26 & VAR18;
assign VAR20 = VAR9 & VAR12 & VAR3;
assign VAR10 = VAR20;
assign VAR24 = VAR26 & ~VAR18;
always @ *
begin
if ( VAR42 )
VAR30 = VAR1;
end
else
VAR30 = VAR23;
end
assign VAR13 = VAR30 - 1'b1;
always @ (posedge VAR25) begin
if (VAR4) begin
VAR42 <= 1'b1;
VAR23 <= 4'b0;
end else begin
if ( VAR12 ) begin
if ( VAR17 ) begin
VAR42 <= 1'b1;
end else begin
VAR42 <= 1'b0;
end
VAR23 <= VAR13;
end
end
end
assign VAR7 = ( VAR30 == 4'b0 );
assign VAR3 = ( VAR7 ) |
( VAR34 == 0 );
assign VAR38 = ( VAR21 ) ? VAR27 : {VAR43{1'b0}};
assign VAR19 = VAR37;
assign VAR28 = VAR35;
assign VAR14 = VAR22;
assign VAR17 = VAR3;
assign VAR41 = VAR14;
assign VAR2 = VAR19;
assign VAR15 = VAR28;
assign VAR5 = VAR17;
assign VAR29 = VAR38;
assign VAR11 = VAR26;
assign VAR18 = VAR40;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai.symbol.v | 1,358 | module MODULE1 (
input VAR6,
input VAR1,
input VAR2 ,
input VAR7 ,
output VAR3
);
supply1 VAR4;
supply0 VAR5;
endmodule | apache-2.0 |
eleqian/WiDSO | CPLD/DSO_LA/src/dso_trig.v | 1,333 | module MODULE1(VAR9, clk, VAR8, VAR7, VAR10, VAR1, VAR3,
VAR2, VAR5, VAR6);
input VAR9;
input clk;
input VAR8;
input VAR7;
input VAR10;
input VAR1;
input VAR3;
input VAR2;
output VAR5;
output VAR6;
reg VAR5;
reg VAR4;
wire VAR11;
assign VAR11 = (VAR8 | VAR7) & (VAR1 | VAR3) & VAR10;
assign VAR6 = VAR5 & ~VAR4;
always @(posedge clk or negedge VAR9) begin
if (~VAR9) begin
VAR5 <= 1'b0;
end else if (VAR2) begin
VAR5 <= 1'b0;
end else if (VAR11) begin
VAR5 <= 1'b1;
end
end
always @(posedge clk or negedge VAR9) begin
if (~VAR9) begin
VAR4 <= 1'b0;
end else begin
VAR4 <= VAR5;
end
end
endmodule | mit |
Jafet95/proy_3_grupo_2_sem_1_2016 | clock_screen_top_v2.v | 9,038 | module MODULE1
(
input wire VAR18, reset,
input wire [7:0] VAR63, VAR14,
input wire VAR29, VAR4,
output wire [7:0]VAR41,VAR66,VAR68,
output wire [7:0]VAR90,VAR6,VAR113,
output wire [7:0]VAR98,VAR5,VAR80,
output reg VAR52,output wire VAR64, VAR109,
output wire [7:0] VAR12
);
wire [9:0] VAR81,VAR37;
wire VAR87;
wire VAR102;
reg [7:0] VAR50, VAR89;
wire VAR49, VAR13, VAR48;
wire [7:0] VAR97, VAR108, VAR95;
wire VAR117;
wire VAR33, VAR110;
wire VAR86;
wire VAR19;
wire VAR91;
wire VAR31;
wire VAR58;
wire VAR82;
wire VAR92;
wire VAR107;
wire VAR9;
wire VAR43;
wire VAR23;
wire VAR27;
wire VAR73;
wire VAR11;
wire VAR24;
wire VAR15;
wire VAR42;
wire VAR40;
wire VAR21;
wire [7:0]VAR60;
wire [7:0]VAR83;
wire [7:0]VAR1;
wire [7:0]VAR46;
wire [7:0]VAR38;
wire [7:0]VAR61;
wire [7:0]VAR99;
wire [7:0]VAR106;
wire [7:0]VAR67;
wire [1:0]VAR16;
wire [1:0] VAR34, VAR96;
wire VAR32;
localparam VAR7 =24;
reg [VAR7-1:0] VAR93;
reg VAR36;
localparam VAR105 = 25;
reg [VAR105-1:0] VAR71;
reg VAR55;
VAR116 VAR3
(
.clk(VAR18),
.reset(reset),
.VAR64(VAR64),
.VAR109(VAR109),
.VAR87(VAR87),
.VAR17(VAR102),
.VAR81(VAR81),
.VAR37(VAR37)
);
VAR26 VAR10
(
.VAR87(VAR87),.VAR81(VAR81),
.VAR37(VAR37),.VAR13(VAR13),
.VAR97(VAR97) );
VAR28 VAR115
(
.clk(VAR18),
.VAR118(VAR68[3:0]), .VAR51(VAR68[7:4]), .VAR59(VAR66[3:0]), .VAR2(VAR66[7:4]), .VAR65(VAR41[3:0]), .VAR8(VAR41[7:4]),.VAR35(VAR90[3:0]), .VAR100(VAR90[7:4]), .VAR114(VAR6[3:0]), .VAR39(VAR6[7:4]), .VAR56(VAR113[3:0]), .VAR75(VAR113[7:4]),.VAR57(VAR80[3:0]), .VAR74(VAR80[7:4]), .VAR72(VAR5[3:0]), .VAR77(VAR5[7:4]), .VAR112(VAR98[3:0]), .VAR54(VAR98[7:4]),.VAR32(VAR32),.VAR34(VAR34),
.VAR96(VAR96),.VAR81(VAR81), .VAR37(VAR37),
.VAR104(VAR55),
.VAR49(VAR49),
.VAR110(VAR110), .VAR108(VAR108) );
VAR69 VAR70
(
.VAR87(VAR87),.VAR81(VAR81),
.VAR37(VAR37),
.VAR117(VAR117),
.VAR33(VAR33),
.VAR48(VAR48),
.VAR95(VAR95)
);
VAR103 VAR84
(
.clk(VAR18),
.reset(reset),
.VAR79(VAR16[1]),
.VAR86(VAR86),
.VAR19(VAR19),
.VAR91(VAR91),
.VAR31(VAR31),
.VAR58(VAR58),
.VAR82(VAR82),
.VAR92(VAR92),
.VAR107(VAR107),
.VAR9(VAR9),
.VAR43(VAR43),
.VAR23(VAR23),
.VAR27(VAR27),
.VAR73(VAR73),
.VAR11(VAR11),
.VAR24(VAR24),
.VAR15(VAR15),
.VAR42(VAR42),
.VAR40(VAR40),
.VAR21(VAR21),
.VAR85(VAR63),
.VAR60(VAR60),
.VAR83(VAR83),
.VAR1(VAR1),
.VAR46(VAR46),
.VAR38(VAR38),
.VAR61(VAR61),
.VAR99(VAR99),
.VAR106(VAR106),
.VAR67(VAR67),
.VAR41(VAR41),
.VAR66(VAR66),
.VAR68(VAR68),
.VAR90(VAR90),
.VAR6(VAR6),
.VAR113(VAR113),
.VAR98(VAR98),
.VAR5(VAR5),
.VAR80(VAR80),
.VAR16(VAR16),
.VAR32(VAR32)
);
VAR30 VAR25 (
.clk(VAR18),
.reset(reset),
.VAR63(VAR63),
.VAR14(VAR14),
.VAR29(VAR29),
.VAR4(VAR4),
.VAR101(VAR60),
.VAR53(VAR83),
.VAR94(VAR1),
.VAR76(VAR61),
.VAR44(VAR38),
.VAR62(VAR46),
.VAR119(VAR99),
.VAR45(VAR106),
.VAR47(VAR67),
.VAR96(VAR96),
.VAR34(VAR34)
);
VAR22 VAR78 (
.VAR29(VAR29),
.VAR14(VAR14),
.VAR34(VAR34),
.VAR43(VAR43),
.VAR23(VAR23),
.VAR27(VAR27),
.VAR73(VAR73),
.VAR11(VAR11),
.VAR24(VAR24),
.VAR15(VAR15),
.VAR42(VAR42),
.VAR40(VAR40),
.VAR21(VAR21)
);
VAR88 VAR20 (
.VAR111(VAR34),
.VAR86(VAR86),
.VAR19(VAR19),
.VAR91(VAR91),
.VAR31(VAR31),
.VAR58(VAR58),
.VAR82(VAR82),
.VAR92(VAR92),
.VAR107(VAR107),
.VAR9(VAR9)
);
always @(posedge VAR18, posedge reset)
begin
if (reset)begin VAR93 <= 0; VAR36 <= 0; end
else
begin
if (VAR93 == 24'd16666666)
begin
VAR93 <= 0;
VAR36 <= ~VAR36;
end
else
VAR93 <= VAR93 + 1'b1;
end
end
always@*
begin
if (VAR16[0] && VAR36) VAR52 = 1'b1;
end
else VAR52 = 1'b0;
end
always @(posedge VAR18, posedge reset)
begin
if (reset)begin VAR71 <= 0; VAR55 <= 0; end
else
begin
if (VAR71 == 25'd24999999)
begin
VAR71 <= 0;
VAR55 <= ~VAR55;
end
else
VAR71 <= VAR71 + 1'b1;
end
end
always@*
begin
if(~VAR87)
VAR89 = "0";
end
else
if(VAR49) VAR89 = VAR108;
else if (VAR110 && VAR16[1]) VAR89 = VAR108;
else if (VAR13) VAR89 = VAR97;
else if (VAR48) VAR89 = VAR95;
else if (VAR33 && VAR16[0] && VAR36) VAR89 = VAR95;
else if (VAR117 && VAR16[0] && VAR36) VAR89 = VAR95;
else VAR89 = 8'h00;end
always @(posedge VAR18)
if (VAR102) VAR50 <= VAR89;
assign VAR12 = VAR50;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.behavioral.pp.v | 2,949 | module MODULE1 (
VAR5 ,
VAR19 ,
VAR25 ,
VAR26 ,
VAR17 ,
VAR16 ,
VAR20,
VAR29 ,
VAR23 ,
VAR28 ,
VAR7
);
output VAR5 ;
output VAR19 ;
input VAR25 ;
input VAR26 ;
input VAR17 ;
input VAR16 ;
input VAR20;
input VAR29 ;
input VAR23 ;
input VAR28 ;
input VAR7 ;
wire VAR18 ;
wire VAR32 ;
wire VAR1 ;
reg VAR30 ;
wire VAR3 ;
wire VAR27 ;
wire VAR21 ;
wire VAR12;
wire VAR9 ;
wire VAR4 ;
wire VAR15 ;
wire VAR24 ;
wire VAR31 ;
wire VAR10 ;
wire VAR2 ;
not VAR14 (VAR32 , VAR12 );
VAR22 VAR13 (VAR1, VAR3, VAR27, VAR21 );
VAR33 VAR11 (VAR18 , VAR1, VAR9, VAR32, VAR30, VAR29, VAR23);
assign VAR4 = ( VAR29 === 1'b1 );
assign VAR15 = ( ( VAR12 === 1'b1 ) && VAR4 );
assign VAR24 = ( ( VAR21 === 1'b0 ) && VAR15 );
assign VAR31 = ( ( VAR21 === 1'b1 ) && VAR15 );
assign VAR10 = ( ( VAR3 !== VAR27 ) && VAR15 );
assign VAR2 = ( ( VAR20 === 1'b1 ) && VAR4 );
buf VAR8 (VAR5 , VAR18 );
not VAR6 (VAR19 , VAR18 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4bb/sky130_fd_sc_hs__and4bb.behavioral.pp.v | 1,895 | module MODULE1 (
VAR3,
VAR13,
VAR9 ,
VAR4 ,
VAR2 ,
VAR14 ,
VAR1
);
input VAR3;
input VAR13;
output VAR9 ;
input VAR4 ;
input VAR2 ;
input VAR14 ;
input VAR1 ;
wire VAR1 VAR12 ;
wire VAR11 ;
wire VAR10;
nor VAR8 (VAR12 , VAR4, VAR2 );
and VAR6 (VAR11 , VAR12, VAR14, VAR1 );
VAR15 VAR7 (VAR10, VAR11, VAR3, VAR13);
buf VAR5 (VAR9 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2.pp.blackbox.v | 1,260 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR7 ,
VAR2,
VAR1,
VAR6 ,
VAR4
);
output VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR2;
input VAR1;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a.functional.v | 1,420 | module MODULE1 (
VAR5 ,
VAR1,
VAR7,
VAR6
);
output VAR5 ;
input VAR1;
input VAR7;
input VAR6;
wire VAR2 ;
wire VAR4;
or VAR9 (VAR2 , VAR7, VAR1 );
and VAR3 (VAR4, VAR2, VAR6 );
buf VAR8 (VAR5 , VAR4 );
endmodule | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/async_ram_1port.v | 4,447 | module MODULE1
( input [VAR6(VAR7)-1:0] VAR9
,input VAR5
,input [VAR8-1:0] VAR10
,output reg [VAR8-1:0] VAR1
);
reg [VAR8-1:0] VAR4 [VAR7-1:0]; reg [VAR8-1:0] VAR3;
VAR2 begin
if (VAR5) begin
VAR3 = 'b0;
end else begin
VAR3 = VAR4[VAR9];
end
end
always @(VAR9 or VAR10 or VAR5) begin
if (VAR5) begin
VAR4[VAR9] = VAR10;
end
end
VAR2 begin
VAR1 = VAR3;
end
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_get_0_val_r_0/synth/zc702_get_0_val_r_0.v | 3,255 | module MODULE1 (
VAR4,
VAR8,
VAR7,
clk,
VAR3,
VAR6
);
input wire [31 : 0] VAR4;
input wire VAR8;
input wire VAR7;
input wire clk;
output wire [31 : 0] VAR3;
output wire VAR6;
VAR2 #(
.VAR5(32)
) VAR1 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.clk(clk),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_jp_bs_baseblk.v | 1,951 | module MODULE1(VAR20 ,VAR22 ,VAR23 ,VAR13 ,VAR26
,VAR2 ,in );
output VAR20 ;
output VAR2 ;
input VAR22 ;
input VAR23 ;
input VAR13 ;
input VAR26 ;
input in ;
supply1 VAR28 ;
wire VAR3 ;
wire VAR7 ;
wire VAR12 ;
wire VAR24 ;
VAR11 VAR25 (
.VAR9 (VAR7 ),
.VAR8 (VAR3 ),
.VAR19 (VAR13 ),
.VAR5 (in ),
.VAR6 (VAR26 ),
.VAR17 (VAR22 ) );
VAR27 VAR10 (
.VAR14 (VAR12 ),
.VAR18 (VAR23 ) );
VAR16 VAR1 (
.VAR14 (VAR2 ),
.VAR18 (VAR24 ) );
VAR27 VAR4 (
.VAR14 (VAR24 ),
.VAR18 (VAR7 ) );
VAR15 VAR21 (
.VAR8 (VAR20 ),
.VAR17 (VAR7 ),
.VAR19 (VAR12 ),
.VAR6 (VAR28 ) );
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi.symbol.v | 1,397 | module MODULE1 (
input VAR4 ,
input VAR3 ,
input VAR8,
output VAR7
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaPhaseGen.v | 1,433 | module MODULE1 ( VAR3, reset, VAR8, enable, VAR2, VAR5, VAR11, VAR9);
parameter VAR4 = 0;
parameter VAR7 = 32;
input VAR3, reset, VAR8, enable, VAR2;
input wire [11:0] VAR11; inout wire [7:0] VAR9; output reg [VAR7-1:0] VAR5;
wire [VAR7-1:0] VAR10;
VAR6 #(VAR4) VAR1(.reset(reset), .out( VAR10), .VAR11(VAR11), .VAR9(VAR9) );
always @(posedge VAR3)
begin
if(reset | VAR8)
VAR5 <= 32'b0;
end
else if(enable & VAR2)
VAR5 <= VAR5 + VAR10;
end
endmodule VAR12 | gpl-2.0 |
secworks/sha512 | src/rtl/sha512_h_constants.v | 5,100 | module MODULE1(
input wire [1 : 0] VAR17,
output wire [63 : 0] VAR13,
output wire [63 : 0] VAR8,
output wire [63 : 0] VAR5,
output wire [63 : 0] VAR11,
output wire [63 : 0] VAR4,
output wire [63 : 0] VAR18,
output wire [63 : 0] VAR2,
output wire [63 : 0] VAR1
);
reg [63 : 0] VAR7;
reg [63 : 0] VAR3;
reg [63 : 0] VAR14;
reg [63 : 0] VAR15;
reg [63 : 0] VAR9;
reg [63 : 0] VAR10;
reg [63 : 0] VAR6;
reg [63 : 0] VAR16;
assign VAR13 = VAR7;
assign VAR8 = VAR3;
assign VAR5 = VAR14;
assign VAR11 = VAR15;
assign VAR4 = VAR9;
assign VAR18 = VAR10;
assign VAR2 = VAR6;
assign VAR1 = VAR16;
always @*
begin : VAR12
case(VAR17)
0:
begin
VAR7 = 64'h8c3d37c819544da2;
VAR3 = 64'h73e1996689dcd4d6;
VAR14 = 64'h1dfab7ae32ff9c82;
VAR15 = 64'h679dd514582f9fcf;
VAR9 = 64'h0f6d2b697bd44da8;
VAR10 = 64'h77e36f7304c48942;
VAR6 = 64'h3f9d85a86a1d36c8;
VAR16 = 64'h1112e6ad91d692a1;
end
1:
begin
VAR7 = 64'h22312194fc2bf72c;
VAR3 = 64'h9f555fa3c84c64c2;
VAR14 = 64'h2393b86b6f53b151;
VAR15 = 64'h963877195940eabd;
VAR9 = 64'h96283ee2a88effe3;
VAR10 = 64'hbe5e1e2553863992;
VAR6 = 64'h2b0199fc2c85b8aa;
VAR16 = 64'h0eb72ddc81c52ca2;
end
2:
begin
VAR7 = 64'hcbbb9d5dc1059ed8;
VAR3 = 64'h629a292a367cd507;
VAR14 = 64'h9159015a3070dd17;
VAR15 = 64'h152fecd8f70e5939;
VAR9 = 64'h67332667ffc00b31;
VAR10 = 64'h8eb44a8768581511;
VAR6 = 64'hdb0c2e0d64f98fa7;
VAR16 = 64'h47b5481dbefa4fa4;
end
3:
begin
VAR7 = 64'h6a09e667f3bcc908;
VAR3 = 64'hbb67ae8584caa73b;
VAR14 = 64'h3c6ef372fe94f82b;
VAR15 = 64'ha54ff53a5f1d36f1;
VAR9 = 64'h510e527fade682d1;
VAR10 = 64'h9b05688c2b3e6c1f;
VAR6 = 64'h1f83d9abfb41bd6b;
VAR16 = 64'h5be0cd19137e2179;
end
endcase end endmodule | bsd-2-clause |
wgml/sysrek | arithm/ipcore_dir/EpF.v | 28,086 | module MODULE2 (
clk, VAR226, VAR156, VAR239, VAR237
);
input clk;
input VAR226;
output [19 : 0] VAR156;
input [18 : 0] VAR239;
input [18 : 0] VAR237;
wire \VAR270/VAR140 ;
wire \VAR270/VAR154 ;
wire \VAR270/VAR187 ;
wire \VAR270/VAR7 ;
wire \VAR270/VAR90 ;
wire \VAR270/VAR284 ;
wire \VAR270/VAR258 ;
wire \VAR270/VAR152 ;
wire \VAR270/VAR155 ;
wire \VAR270/VAR51 ;
wire \VAR270/VAR128 ;
wire \VAR270/VAR121 ;
wire \VAR270/VAR4 ;
wire \VAR270/VAR175 ;
wire \VAR270/VAR216 ;
wire \VAR270/VAR282 ;
wire \VAR270/VAR281 ;
wire \VAR270/VAR289 ;
wire \VAR270/VAR9 ;
wire \VAR270/VAR291 ;
wire \VAR270/VAR235 ;
wire \VAR270/VAR294 ;
wire \VAR270/VAR210 ;
wire \VAR270/VAR60 ;
wire \VAR270/VAR2 ;
wire \VAR270/VAR112 ;
wire \VAR270/VAR100 ;
wire \VAR270/VAR255 ;
wire \VAR270/VAR31 ;
wire \VAR270/VAR89 ;
wire \VAR270/VAR190 ;
wire \VAR270/VAR217 ;
wire \VAR270/VAR57 ;
wire \VAR270/VAR80 ;
wire \VAR270/VAR63 ;
wire \VAR270/VAR75 ;
wire \VAR270/VAR17 ;
wire \VAR270/VAR218 ;
wire \VAR270/VAR138 ;
wire \VAR270/VAR36 ;
wire \VAR270/VAR67 ;
wire \VAR270/VAR45 ;
wire \VAR270/VAR298 ;
wire \VAR270/VAR162 ;
wire \VAR270/VAR287 ;
wire \VAR270/VAR276 ;
wire \VAR270/VAR202 ;
wire \VAR270/VAR64 ;
wire \VAR270/VAR192 ;
wire \VAR270/VAR129 ;
wire \VAR270/VAR256 ;
wire \VAR270/VAR262 ;
wire \VAR270/VAR286 ;
wire \VAR270/VAR180 ;
wire \VAR270/VAR61 ;
wire \VAR270/VAR305 ;
wire \VAR270/VAR143 ;
wire \VAR270/VAR35 ;
wire \VAR270/VAR241 ;
wire \VAR270/VAR91 ;
wire \VAR270/VAR199 ;
wire \VAR270/VAR72 ;
wire \VAR270/VAR103 ;
wire \VAR270/VAR110 ;
wire \VAR270/VAR153 ;
wire \VAR270/VAR254 ;
wire \VAR270/VAR160 ;
wire \VAR270/VAR197 ;
wire \VAR270/VAR81 ;
wire \VAR270/VAR87 ;
wire \VAR270/VAR203 ;
wire \VAR270/VAR238 ;
wire \VAR270/VAR223 ;
wire \VAR270/VAR171 ;
wire \VAR270/VAR277 ;
wire \VAR270/VAR74 ;
wire \VAR270/VAR234 ;
wire \VAR270/VAR178 ;
wire \VAR270/VAR24 ;
wire \VAR270/VAR53 ;
wire \VAR270/VAR233 ;
wire \VAR270/VAR46 ;
wire \VAR270/VAR242 ;
wire \VAR270/VAR133 ;
wire \VAR270/VAR40 ;
wire \VAR270/VAR297 ;
wire \VAR270/VAR161 ;
wire \VAR270/VAR167 ;
wire \VAR270/VAR56 ;
wire \VAR270/VAR240 ;
wire \VAR270/VAR126 ;
wire \VAR270/VAR131 ;
wire \VAR270/VAR22 ;
wire \VAR270/VAR65 ;
wire \VAR270/VAR301 ;
wire \VAR270/VAR124 ;
wire \VAR270/VAR111 ;
wire \VAR270/VAR117 ;
wire \VAR270/VAR145 ;
wire \VAR270/VAR300 ;
wire \VAR270/VAR283 ;
wire \VAR270/VAR101 ;
wire \VAR270/VAR32 ;
wire \VAR270/VAR200 ;
wire \VAR270/VAR15 ;
wire \VAR270/VAR172 ;
wire \VAR270/VAR208 ;
wire \VAR270/VAR168 ;
wire \VAR270/VAR79 ;
wire \VAR270/VAR220 ;
wire \VAR186/VAR55 ;
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR54 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR138 ),
.VAR249(VAR156[0])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR8 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR167 ),
.VAR249(\VAR270/VAR138 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR263 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR17 ),
.VAR249(VAR156[1])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR280 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR161 ),
.VAR249(\VAR270/VAR17 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR209 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR63 ),
.VAR249(VAR156[3])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR193 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR40 ),
.VAR249(\VAR270/VAR63 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR5 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR80 ),
.VAR249(VAR156[4])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR105 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR133 ),
.VAR249(\VAR270/VAR80 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR76 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR75 ),
.VAR249(VAR156[2])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR179 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR297 ),
.VAR249(\VAR270/VAR75 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR201 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR57 ),
.VAR249(VAR156[5])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR29 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR242 ),
.VAR249(\VAR270/VAR57 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR185 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR217 ),
.VAR249(VAR156[6])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR279 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR46 ),
.VAR249(\VAR270/VAR217 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR97 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR89 ),
.VAR249(VAR156[8])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR247 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR53 ),
.VAR249(\VAR270/VAR89 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR148 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR218 ),
.VAR249(VAR156[9])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR37 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR24 ),
.VAR249(\VAR270/VAR218 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR164 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR190 ),
.VAR249(VAR156[7])
);
VAR23 #(
.VAR166 ( 16'h0000 ))
\VAR270/VAR28 (
.VAR246(\VAR270/VAR220 ),
.VAR127(\VAR270/VAR220 ),
.VAR173(\VAR270/VAR220 ),
.VAR26(\VAR270/VAR220 ),
.VAR299(VAR226),
.VAR170(clk),
.VAR232(\VAR270/VAR233 ),
.VAR249(\VAR270/VAR190 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR183 (
.VAR259(\VAR270/VAR241 ),
.VAR228(\VAR270/VAR128 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR11 (
.VAR259(\VAR270/VAR35 ),
.VAR228(\VAR270/VAR121 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR250 (
.VAR259(\VAR270/VAR143 ),
.VAR228(\VAR270/VAR291 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR85 (
.VAR259(\VAR270/VAR305 ),
.VAR228(\VAR270/VAR9 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR13 (
.VAR259(\VAR270/VAR61 ),
.VAR228(\VAR270/VAR289 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR191 (
.VAR259(\VAR270/VAR180 ),
.VAR228(\VAR270/VAR281 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR215 (
.VAR259(\VAR270/VAR286 ),
.VAR228(\VAR270/VAR282 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR182 (
.VAR259(\VAR270/VAR262 ),
.VAR228(\VAR270/VAR216 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR98 (
.VAR259(\VAR270/VAR256 ),
.VAR228(\VAR270/VAR175 )
);
VAR243 #(
.VAR166 ( 2'h2 ))
\VAR270/VAR261 (
.VAR259(\VAR270/VAR129 ),
.VAR228(\VAR270/VAR4 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR206 (
.VAR259(VAR237[0]),
.VAR260(VAR239[0]),
.VAR228(\VAR270/VAR145 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR116 (
.VAR259(VAR237[10]),
.VAR260(VAR239[10]),
.VAR228(\VAR270/VAR81 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR120 (
.VAR259(VAR237[1]),
.VAR260(VAR239[1]),
.VAR228(\VAR270/VAR117 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR211 (
.VAR259(VAR237[11]),
.VAR260(VAR239[11]),
.VAR228(\VAR270/VAR197 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR42 (
.VAR259(VAR237[2]),
.VAR260(VAR239[2]),
.VAR228(\VAR270/VAR111 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR41 (
.VAR259(VAR237[12]),
.VAR260(VAR239[12]),
.VAR228(\VAR270/VAR160 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR39 (
.VAR259(VAR237[3]),
.VAR260(VAR239[3]),
.VAR228(\VAR270/VAR124 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR144 (
.VAR259(VAR237[13]),
.VAR260(VAR239[13]),
.VAR228(\VAR270/VAR254 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR181 (
.VAR259(VAR237[4]),
.VAR260(VAR239[4]),
.VAR228(\VAR270/VAR301 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR34 (
.VAR259(VAR237[14]),
.VAR260(VAR239[14]),
.VAR228(\VAR270/VAR153 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR229 (
.VAR259(VAR237[5]),
.VAR260(VAR239[5]),
.VAR228(\VAR270/VAR65 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR274 (
.VAR259(VAR237[15]),
.VAR260(VAR239[15]),
.VAR228(\VAR270/VAR110 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR94 (
.VAR259(VAR237[6]),
.VAR260(VAR239[6]),
.VAR228(\VAR270/VAR22 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR134 (
.VAR259(VAR237[16]),
.VAR260(VAR239[16]),
.VAR228(\VAR270/VAR103 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR214 (
.VAR259(VAR237[7]),
.VAR260(VAR239[7]),
.VAR228(\VAR270/VAR131 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR150 (
.VAR259(VAR237[17]),
.VAR260(VAR239[17]),
.VAR228(\VAR270/VAR72 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR10 (
.VAR259(VAR237[8]),
.VAR260(VAR239[8]),
.VAR228(\VAR270/VAR126 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR107 (
.VAR259(VAR237[18]),
.VAR260(VAR239[18]),
.VAR228(\VAR270/VAR199 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR86 (
.VAR259(VAR237[9]),
.VAR260(VAR239[9]),
.VAR228(\VAR270/VAR240 )
);
VAR293 #(
.VAR166 ( 4'h6 ))
\VAR270/VAR207 (
.VAR259(VAR237[18]),
.VAR260(VAR239[18]),
.VAR228(\VAR270/VAR91 )
);
VAR122 \VAR270/VAR204 (
.VAR95(\VAR270/VAR220 ),
.VAR135(VAR239[0]),
.VAR18(\VAR270/VAR145 ),
.VAR228(\VAR270/VAR79 )
);
VAR83 \VAR270/VAR158 (
.VAR95(\VAR270/VAR220 ),
.VAR267(\VAR270/VAR145 ),
.VAR228(\VAR270/VAR167 )
);
VAR83 \VAR270/VAR70 (
.VAR95(\VAR270/VAR283 ),
.VAR267(\VAR270/VAR240 ),
.VAR228(\VAR270/VAR24 )
);
VAR122 \VAR270/VAR253 (
.VAR95(\VAR270/VAR283 ),
.VAR135(VAR239[9]),
.VAR18(\VAR270/VAR240 ),
.VAR228(\VAR270/VAR300 )
);
VAR122 \VAR270/VAR109 (
.VAR95(\VAR270/VAR79 ),
.VAR135(VAR239[1]),
.VAR18(\VAR270/VAR117 ),
.VAR228(\VAR270/VAR168 )
);
VAR83 \VAR270/VAR25 (
.VAR95(\VAR270/VAR79 ),
.VAR267(\VAR270/VAR117 ),
.VAR228(\VAR270/VAR161 )
);
VAR122 \VAR270/VAR252 (
.VAR95(\VAR270/VAR168 ),
.VAR135(VAR239[2]),
.VAR18(\VAR270/VAR111 ),
.VAR228(\VAR270/VAR208 )
);
VAR83 \VAR270/VAR251 (
.VAR95(\VAR270/VAR168 ),
.VAR267(\VAR270/VAR111 ),
.VAR228(\VAR270/VAR297 )
);
VAR122 \VAR270/VAR71 (
.VAR95(\VAR270/VAR208 ),
.VAR135(VAR239[3]),
.VAR18(\VAR270/VAR124 ),
.VAR228(\VAR270/VAR172 )
);
VAR83 \VAR270/VAR130 (
.VAR95(\VAR270/VAR208 ),
.VAR267(\VAR270/VAR124 ),
.VAR228(\VAR270/VAR40 )
);
VAR122 \VAR270/VAR27 (
.VAR95(\VAR270/VAR172 ),
.VAR135(VAR239[4]),
.VAR18(\VAR270/VAR301 ),
.VAR228(\VAR270/VAR15 )
);
VAR83 \VAR270/VAR177 (
.VAR95(\VAR270/VAR172 ),
.VAR267(\VAR270/VAR301 ),
.VAR228(\VAR270/VAR133 )
);
VAR122 \VAR270/VAR88 (
.VAR95(\VAR270/VAR15 ),
.VAR135(VAR239[5]),
.VAR18(\VAR270/VAR65 ),
.VAR228(\VAR270/VAR200 )
);
VAR83 \VAR270/VAR176 (
.VAR95(\VAR270/VAR15 ),
.VAR267(\VAR270/VAR65 ),
.VAR228(\VAR270/VAR242 )
);
VAR122 \VAR270/VAR205 (
.VAR95(\VAR270/VAR200 ),
.VAR135(VAR239[6]),
.VAR18(\VAR270/VAR22 ),
.VAR228(\VAR270/VAR32 )
);
VAR83 \VAR270/VAR269 (
.VAR95(\VAR270/VAR200 ),
.VAR267(\VAR270/VAR22 ),
.VAR228(\VAR270/VAR46 )
);
VAR122 \VAR270/VAR266 (
.VAR95(\VAR270/VAR32 ),
.VAR135(VAR239[7]),
.VAR18(\VAR270/VAR131 ),
.VAR228(\VAR270/VAR101 )
);
VAR83 \VAR270/VAR264 (
.VAR95(\VAR270/VAR32 ),
.VAR267(\VAR270/VAR131 ),
.VAR228(\VAR270/VAR233 )
);
VAR122 \VAR270/VAR66 (
.VAR95(\VAR270/VAR101 ),
.VAR135(VAR239[8]),
.VAR18(\VAR270/VAR126 ),
.VAR228(\VAR270/VAR283 )
);
VAR83 \VAR270/VAR104 (
.VAR95(\VAR270/VAR101 ),
.VAR267(\VAR270/VAR126 ),
.VAR228(\VAR270/VAR53 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR115 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR300 ),
.VAR249(\VAR270/VAR56 )
);
VAR122 \VAR270/VAR139 (
.VAR95(\VAR270/VAR220 ),
.VAR135(VAR239[10]),
.VAR18(\VAR270/VAR81 ),
.VAR228(\VAR270/VAR178 )
);
VAR83 \VAR270/VAR106 (
.VAR95(\VAR270/VAR220 ),
.VAR267(\VAR270/VAR81 ),
.VAR228(\VAR270/VAR192 )
);
VAR83 \VAR270/VAR188 (
.VAR95(\VAR270/VAR87 ),
.VAR267(\VAR270/VAR91 ),
.VAR228(\VAR270/VAR36 )
);
VAR122 \VAR270/VAR141 (
.VAR95(\VAR270/VAR178 ),
.VAR135(VAR239[11]),
.VAR18(\VAR270/VAR197 ),
.VAR228(\VAR270/VAR234 )
);
VAR83 \VAR270/VAR194 (
.VAR95(\VAR270/VAR178 ),
.VAR267(\VAR270/VAR197 ),
.VAR228(\VAR270/VAR64 )
);
VAR122 \VAR270/VAR48 (
.VAR95(\VAR270/VAR234 ),
.VAR135(VAR239[12]),
.VAR18(\VAR270/VAR160 ),
.VAR228(\VAR270/VAR74 )
);
VAR83 \VAR270/VAR163 (
.VAR95(\VAR270/VAR234 ),
.VAR267(\VAR270/VAR160 ),
.VAR228(\VAR270/VAR202 )
);
VAR122 \VAR270/VAR302 (
.VAR95(\VAR270/VAR74 ),
.VAR135(VAR239[13]),
.VAR18(\VAR270/VAR254 ),
.VAR228(\VAR270/VAR277 )
);
VAR83 \VAR270/VAR303 (
.VAR95(\VAR270/VAR74 ),
.VAR267(\VAR270/VAR254 ),
.VAR228(\VAR270/VAR276 )
);
VAR122 \VAR270/VAR102 (
.VAR95(\VAR270/VAR277 ),
.VAR135(VAR239[14]),
.VAR18(\VAR270/VAR153 ),
.VAR228(\VAR270/VAR171 )
);
VAR83 \VAR270/VAR3 (
.VAR95(\VAR270/VAR277 ),
.VAR267(\VAR270/VAR153 ),
.VAR228(\VAR270/VAR287 )
);
VAR122 \VAR270/VAR114 (
.VAR95(\VAR270/VAR171 ),
.VAR135(VAR239[15]),
.VAR18(\VAR270/VAR110 ),
.VAR228(\VAR270/VAR223 )
);
VAR83 \VAR270/VAR1 (
.VAR95(\VAR270/VAR171 ),
.VAR267(\VAR270/VAR110 ),
.VAR228(\VAR270/VAR162 )
);
VAR122 \VAR270/VAR304 (
.VAR95(\VAR270/VAR223 ),
.VAR135(VAR239[16]),
.VAR18(\VAR270/VAR103 ),
.VAR228(\VAR270/VAR238 )
);
VAR83 \VAR270/VAR273 (
.VAR95(\VAR270/VAR223 ),
.VAR267(\VAR270/VAR103 ),
.VAR228(\VAR270/VAR298 )
);
VAR122 \VAR270/VAR136 (
.VAR95(\VAR270/VAR238 ),
.VAR135(VAR239[17]),
.VAR18(\VAR270/VAR72 ),
.VAR228(\VAR270/VAR203 )
);
VAR83 \VAR270/VAR78 (
.VAR95(\VAR270/VAR238 ),
.VAR267(\VAR270/VAR72 ),
.VAR228(\VAR270/VAR45 )
);
VAR122 \VAR270/VAR212 (
.VAR95(\VAR270/VAR203 ),
.VAR135(VAR239[18]),
.VAR18(\VAR270/VAR199 ),
.VAR228(\VAR270/VAR87 )
);
VAR83 \VAR270/VAR68 (
.VAR95(\VAR270/VAR203 ),
.VAR267(\VAR270/VAR199 ),
.VAR228(\VAR270/VAR67 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR113 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR192 ),
.VAR249(\VAR270/VAR241 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR96 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR64 ),
.VAR249(\VAR270/VAR143 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR174 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR202 ),
.VAR249(\VAR270/VAR305 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR213 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR276 ),
.VAR249(\VAR270/VAR61 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR52 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR287 ),
.VAR249(\VAR270/VAR180 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR236 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR162 ),
.VAR249(\VAR270/VAR286 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR231 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR298 ),
.VAR249(\VAR270/VAR262 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR16 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR45 ),
.VAR249(\VAR270/VAR256 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR14 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR67 ),
.VAR249(\VAR270/VAR129 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR275 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR36 ),
.VAR249(\VAR270/VAR35 )
);
VAR122 \VAR270/VAR118 (
.VAR95(\VAR270/VAR56 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR128 ),
.VAR228(\VAR270/VAR31 )
);
VAR83 \VAR270/VAR93 (
.VAR95(\VAR270/VAR56 ),
.VAR267(\VAR270/VAR128 ),
.VAR228(\VAR270/VAR51 )
);
VAR83 \VAR270/VAR142 (
.VAR95(\VAR270/VAR235 ),
.VAR267(\VAR270/VAR121 ),
.VAR228(\VAR270/VAR140 )
);
VAR122 \VAR270/VAR151 (
.VAR95(\VAR270/VAR235 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR121 ),
.VAR228(\VAR186/VAR55 )
);
VAR122 \VAR270/VAR288 (
.VAR95(\VAR270/VAR31 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR291 ),
.VAR228(\VAR270/VAR255 )
);
VAR83 \VAR270/VAR38 (
.VAR95(\VAR270/VAR31 ),
.VAR267(\VAR270/VAR291 ),
.VAR228(\VAR270/VAR155 )
);
VAR122 \VAR270/VAR69 (
.VAR95(\VAR270/VAR255 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR9 ),
.VAR228(\VAR270/VAR100 )
);
VAR83 \VAR270/VAR292 (
.VAR95(\VAR270/VAR255 ),
.VAR267(\VAR270/VAR9 ),
.VAR228(\VAR270/VAR152 )
);
VAR122 \VAR270/VAR49 (
.VAR95(\VAR270/VAR100 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR289 ),
.VAR228(\VAR270/VAR112 )
);
VAR83 \VAR270/VAR285 (
.VAR95(\VAR270/VAR100 ),
.VAR267(\VAR270/VAR289 ),
.VAR228(\VAR270/VAR258 )
);
VAR122 \VAR270/VAR125 (
.VAR95(\VAR270/VAR112 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR281 ),
.VAR228(\VAR270/VAR2 )
);
VAR83 \VAR270/VAR84 (
.VAR95(\VAR270/VAR112 ),
.VAR267(\VAR270/VAR281 ),
.VAR228(\VAR270/VAR284 )
);
VAR122 \VAR270/VAR196 (
.VAR95(\VAR270/VAR2 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR282 ),
.VAR228(\VAR270/VAR60 )
);
VAR83 \VAR270/VAR21 (
.VAR95(\VAR270/VAR2 ),
.VAR267(\VAR270/VAR282 ),
.VAR228(\VAR270/VAR90 )
);
VAR122 \VAR270/VAR271 (
.VAR95(\VAR270/VAR60 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR216 ),
.VAR228(\VAR270/VAR210 )
);
VAR83 \VAR270/VAR82 (
.VAR95(\VAR270/VAR60 ),
.VAR267(\VAR270/VAR216 ),
.VAR228(\VAR270/VAR7 )
);
VAR122 \VAR270/VAR119 (
.VAR95(\VAR270/VAR210 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR175 ),
.VAR228(\VAR270/VAR294 )
);
VAR83 \VAR270/VAR50 (
.VAR95(\VAR270/VAR210 ),
.VAR267(\VAR270/VAR175 ),
.VAR228(\VAR270/VAR187 )
);
VAR122 \VAR270/VAR19 (
.VAR95(\VAR270/VAR294 ),
.VAR135(\VAR270/VAR220 ),
.VAR18(\VAR270/VAR4 ),
.VAR228(\VAR270/VAR235 )
);
VAR83 \VAR270/VAR195 (
.VAR95(\VAR270/VAR294 ),
.VAR267(\VAR270/VAR4 ),
.VAR228(\VAR270/VAR154 )
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR20 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR51 ),
.VAR249(VAR156[10])
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR248 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR155 ),
.VAR249(VAR156[11])
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR159 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR152 ),
.VAR249(VAR156[12])
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR47 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR258 ),
.VAR249(VAR156[13])
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR30 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR284 ),
.VAR249(VAR156[14])
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR77 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR90 ),
.VAR249(VAR156[15])
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR165 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR7 ),
.VAR249(VAR156[16])
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR99 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR187 ),
.VAR249(VAR156[17])
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR230 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR154 ),
.VAR249(VAR156[18])
);
VAR184 #(
.VAR166 ( 1'b0 ))
\VAR270/VAR296 (
.VAR227(clk),
.VAR299(VAR226),
.VAR232(\VAR270/VAR140 ),
.VAR249(VAR156[19])
);
VAR189 \VAR270/VAR222 (
.VAR62(\VAR270/VAR220 )
);
endmodule
module MODULE1 ();
parameter VAR157 = 100000;
parameter VAR244 = 0;
wire VAR147;
wire VAR268;
wire VAR33;
wire VAR219;
tri1 VAR73;
tri (weak1, strong0) VAR132 = VAR73;
wire VAR295;
wire VAR123;
reg VAR224;
reg VAR137;
reg VAR59;
wire VAR245;
wire VAR92;
wire VAR225;
wire VAR43;
wire VAR265;
reg VAR221;
reg VAR272;
reg VAR44;
reg VAR12;
reg VAR278;
reg VAR6 = 0;
reg VAR149 = 0 ;
reg VAR146 = 0;
reg VAR58 = 0;
reg VAR257 = 1'VAR169;
reg VAR108 = 1'VAR169;
reg VAR290 = 1'VAR169;
reg VAR198 = 1'VAR169;
assign (weak1, weak0) VAR147 = VAR224;
assign (weak1, weak0) VAR268 = VAR137;
assign (weak1, weak0) VAR219 = VAR59; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai_0.v | 2,424 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR10 ,
VAR1 ,
VAR7 ,
VAR11 ,
VAR9,
VAR12,
VAR3 ,
VAR6
);
output VAR4 ;
input VAR2 ;
input VAR10 ;
input VAR1 ;
input VAR7 ;
input VAR11 ;
input VAR9;
input VAR12;
input VAR3 ;
input VAR6 ;
VAR8 VAR5 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR4 ,
VAR2,
VAR10,
VAR1,
VAR7,
VAR11
);
output VAR4 ;
input VAR2;
input VAR10;
input VAR1;
input VAR7;
input VAR11;
supply1 VAR9;
supply0 VAR12;
supply1 VAR3 ;
supply0 VAR6 ;
VAR8 VAR5 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR11(VAR11)
);
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/oq_regs_ctrl.v | 34,251 | module MODULE1
parameter VAR6 = 13,
parameter VAR10 = 8,
parameter VAR126 = 8,
parameter VAR29 = VAR51(VAR126),
parameter VAR81 = 17,
parameter VAR116 = VAR51(VAR81),
parameter VAR12 = 2048/VAR10, parameter VAR13 = 60/VAR10 + 1,
parameter VAR101 = VAR51((2**VAR6)/VAR13),
parameter VAR35 = 11,
parameter VAR121 = VAR35-VAR51(VAR10)
)
(
output reg [VAR126-1:0] enable,
input VAR31,
input VAR44,
input [VAR15-1:0] VAR67,
input [VAR116-1:0] addr,
input [VAR29-1:0] VAR50,
output reg VAR130,
output reg [VAR15-1:0] VAR92,
output reg VAR159,
output reg [VAR29-1:0] VAR43,
output reg [VAR29-1:0] VAR49,
output reg VAR33,
input VAR77,
output reg VAR69,
output reg [VAR15-1:0] VAR74,
input [VAR15-1:0] VAR146,
output reg VAR52,
input VAR144,
output reg VAR95,
output reg [VAR15-1:0] VAR41,
input [VAR15-1:0] VAR11,
output reg VAR155,
input VAR93,
output reg VAR70,
output reg [VAR15-1:0] VAR68,
input [VAR15-1:0] VAR132,
output reg VAR96,
input VAR48,
output reg VAR72,
output reg [VAR15-1:0] VAR80,
input [VAR15-1:0] VAR9,
output reg VAR145,
input VAR1,
output reg VAR78,
output reg [VAR15-1:0] VAR28,
input [VAR15-1:0] VAR138,
output reg VAR120,
input VAR105,
output reg VAR154,
output reg [VAR15-1:0] VAR100,
input [VAR15-1:0] VAR119,
output reg VAR150,
input VAR36,
output reg VAR27,
output reg [VAR15-1:0] VAR57,
input [VAR15-1:0] VAR55,
output reg VAR127,
input VAR23,
output reg VAR152,
output reg [VAR15-1:0] VAR42,
input [VAR15-1:0] VAR63,
output reg VAR3,
input VAR94,
output reg VAR115,
output reg [VAR15-1:0] VAR124,
input [VAR15-1:0] VAR140,
output reg VAR54,
input VAR46,
output reg VAR87,
output reg [VAR15-1:0] VAR5,
input [VAR15-1:0] VAR109,
output reg VAR22,
input VAR89,
output reg VAR38,
output reg [VAR15-1:0] VAR90,
input [VAR15-1:0] VAR64,
output reg VAR75,
input VAR153,
output reg VAR125,
output reg [VAR15-1:0] VAR114,
input [VAR15-1:0] VAR102,
output reg VAR53,
input VAR14,
output reg VAR30,
output reg [VAR15-1:0] VAR85,
input [VAR15-1:0] VAR73,
output reg VAR16,
input VAR157,
output reg VAR84,
output reg [VAR15-1:0] VAR17,
input [VAR15-1:0] VAR45,
output reg VAR133,
input VAR66,
output reg VAR129,
output reg [VAR15-1:0] VAR91,
input [VAR15-1:0] VAR136,
output reg VAR25,
input VAR62,
output reg VAR139,
output reg [VAR15-1:0] VAR106,
input [VAR15-1:0] VAR39,
input clk,
input reset
);
function integer VAR51;
input integer VAR122;
begin
VAR51=0;
while(2**VAR51<VAR122) begin
VAR51=VAR51+1;
end
end
endfunction
localparam VAR79 = VAR21(0, VAR126);
localparam VAR58 = VAR71(1, VAR126);
localparam VAR104 = VAR21(0, VAR126) -
localparam VAR34 = 0;
localparam VAR128 = 1;
localparam VAR148 = 2;
localparam VAR143 = 3;
localparam VAR103 = 4;
reg [2:0] state;
reg VAR56;
reg [VAR29-1:0] VAR98;
reg [VAR6-1:0] VAR108;
reg [VAR6-1:0] VAR99;
reg [VAR15-1:0] VAR59;
reg VAR151;
reg [VAR15-1:0] VAR107;
reg [VAR15-1:0] VAR137;
reg VAR158;
reg VAR24;
reg VAR26;
reg VAR111;
reg VAR118;
reg VAR147;
reg VAR160;
reg VAR18;
reg VAR86;
reg VAR61;
reg VAR65;
reg VAR135;
reg VAR149;
reg VAR88;
wire VAR110;
wire VAR156;
wire VAR83;
assign VAR156 = VAR77 ||
VAR144 ||
VAR93 ||
VAR48 ||
VAR1 ||
VAR105 ||
VAR36 ||
VAR23 ||
VAR94 ||
VAR46 ||
VAR89 ||
VAR153 ||
VAR14 ||
VAR157 ||
VAR66 ||
VAR62;
assign VAR110 = VAR67[VAR2];
always @(posedge clk)
begin
if (reset) begin
state <= VAR34;
VAR98 <= 'h0;
VAR108 <= 0;
VAR99 <= VAR79;
VAR151 <= 1'b0;
enable <= {VAR126{1'b0}};
VAR56 <= 1'b0;
VAR159 <= 1'b0;
VAR43 <= 'h0;
end
else begin
case (state)
VAR34 : begin
if (VAR98 == VAR126 - 1) begin
state <= VAR128;
enable <= {VAR126{1'b1}};
end
else
VAR98 <= VAR98 + 'h1;
VAR108 <= VAR108 + VAR58;
VAR99 <= VAR99 + VAR58;
end
VAR128 : begin
if (VAR31 && !VAR151) begin
VAR130 <= 1'b0;
if (addr == VAR97) begin
VAR151 <= !VAR44 && VAR110;
if (!VAR44) begin
enable[VAR50] <= VAR67[VAR112] &&
!VAR110;
if (VAR110) begin
state <= VAR148;
VAR159 <= 1'b1;
VAR43 <= VAR50;
VAR56 <= VAR67[VAR112];
VAR158 <= 1'b0;
VAR24 <= 1'b0;
end
end
VAR130 <= VAR44 || !VAR110;
VAR92 <= VAR59;
end
else begin
VAR151 <= 1'b1;
end
end else if (VAR151) begin
if (VAR156) begin
VAR151 <= 1'b0;
VAR130 <= 1'b1;
VAR92 <= VAR59;
end
else if (!VAR31) begin
VAR151 <= 1'b0;
end
end
else begin
VAR130 <= 1'b0;
end
end
VAR148 : begin
if ((VAR23 && VAR94) ||
(VAR23 && !VAR3) ||
(!VAR127 && VAR94)) begin
state <= VAR143;
end
if (VAR23) begin
VAR107 <= VAR63;
end
if (VAR94) begin
VAR137 <= VAR140;
end
VAR159 <= 1'b0;
VAR26 <= 1'b0;
VAR111 <= 1'b0;
VAR118 <= 1'b0;
VAR147 <= 1'b0;
VAR160 <= 1'b0;
VAR18 <= 1'b0;
VAR86 <= 1'b0;
VAR61 <= 1'b0;
VAR65 <= 1'b0;
VAR135 <= 1'b0;
VAR149 <= 1'b0;
VAR88 <= 1'b0;
VAR158 <= VAR23 || VAR158;
VAR24 <= VAR94 || VAR24;
end
VAR143 : begin
if (!VAR53 &&
!VAR16 &&
!VAR133 &&
!VAR54 &&
!VAR22) begin
state <= VAR103;
enable[VAR43] <= VAR56;
VAR151 <= 1'b0;
VAR130 <= 1'b1;
VAR92 <= VAR59;
end
VAR26 <= VAR77 ||
VAR26;
VAR111 <= VAR144 ||
VAR111;
VAR118 <= VAR93 ||
VAR118;
VAR147 <= VAR48 ||
VAR147;
VAR160 <= VAR1 ||
VAR160;
VAR18 <= VAR105 ||
VAR18;
VAR86 <= VAR36 ||
VAR86;
VAR61 <= VAR14 ||
VAR61;
VAR65 <= VAR157 ||
VAR65;
VAR135 <= VAR66 ||
VAR135;
VAR149 <= VAR46 ||
VAR149;
VAR88 <= VAR89 ||
VAR88;
end
VAR103 : begin
state <= VAR128;
end
endcase
end
end
always @*
begin
VAR49 = VAR50;
VAR33 = 1'b0;
VAR52 = 1'b0;
VAR155 = 1'b0;
VAR96 = 1'b0;
VAR145 = 1'b0;
VAR120 = 1'b0;
VAR150 = 1'b0;
VAR75 = 1'b0;
VAR53 = 1'b0;
VAR16 = 1'b0;
VAR133 = 1'b0;
VAR127 = 1'b0;
VAR3 = 1'b0;
VAR54 = 1'b0;
VAR22 = 1'b0;
VAR25 = 1'b0;
VAR69 = !VAR44;
VAR95 = !VAR44;
VAR70 = !VAR44;
VAR72 = !VAR44;
VAR78 = !VAR44;
VAR154 = !VAR44;
VAR27 = !VAR44;
VAR152 = !VAR44;
VAR115 = !VAR44;
VAR87 = 1'b0;
VAR38 = 1'b0;
VAR125 = !VAR44;
VAR30 = 1'b0;
VAR84 = 1'b0;
VAR129 = 1'b0;
VAR139 = !VAR44;
VAR74 = VAR67;
VAR41 = VAR67;
VAR68 = VAR67;
VAR80 = VAR67;
VAR28 = VAR67;
VAR100 = VAR67;
VAR57 = VAR67;
VAR42 = VAR67;
VAR124 = VAR67;
VAR5 = VAR67;
VAR90 = VAR67;
VAR114 = VAR67;
VAR85 = VAR67;
VAR17 = VAR67;
VAR91 = VAR67;
VAR106 = VAR67;
case (state)
VAR34 : begin
VAR49 = VAR98;
VAR74 = 'h0;
VAR41 = 'h0;
VAR68 = 'h0;
VAR80 = 'h0;
VAR28 = 'h0;
VAR100 = 'h0;
VAR57 = 'h0;
VAR114 = VAR123;
VAR85 = 1'b0;
VAR17 = VAR104;
VAR91 = 'h0;
VAR42 = VAR99;
VAR124 = VAR108;
VAR5 = VAR108;
VAR90 = VAR108;
VAR106 = 'h0;
VAR69 = 1'b1;
VAR95 = 1'b1;
VAR70 = 1'b1;
VAR72 = 1'b1;
VAR78 = 1'b1;
VAR154 = 1'b1;
VAR27 = 1'b1;
VAR125 = 1'b1;
VAR30 = 1'b1;
VAR84 = 1'b1;
VAR129 = 1'b1;
VAR152 = 1'b1;
VAR115 = 1'b1;
VAR87 = 1'b1;
VAR38 = 1'b1;
VAR139 = 1'b1;
VAR33 = 1'b1;
VAR52 = 1'b1;
VAR155 = 1'b1;
VAR96 = 1'b1;
VAR145 = 1'b1;
VAR120 = 1'b1;
VAR150 = 1'b1;
VAR75 = 1'b1;
VAR53 = 1'b1;
VAR16 = 1'b1;
VAR133 = 1'b1;
VAR127 = 1'b1;
VAR3 = 1'b1;
VAR54 = 1'b1;
VAR22 = 1'b1;
VAR25 = 1'b1;
end
VAR128 : begin
if (!VAR151 || VAR156 || !VAR31) begin
VAR33 = 1'b0;
VAR52 = 1'b0;
VAR155 = 1'b0;
VAR96 = 1'b0;
VAR145 = 1'b0;
VAR120 = 1'b0;
VAR150 = 1'b0;
VAR127 = 1'b0;
VAR3 = 1'b0;
VAR54 = 1'b0;
VAR22 = 1'b0;
VAR75 = 1'b0;
VAR53 = 1'b0;
VAR16 = 1'b0;
VAR133 = 1'b0;
VAR25 = 1'b0;
end
else begin
VAR33 = addr == VAR82;
VAR52 = addr == VAR20;
VAR155 = addr == VAR117;
VAR96 = addr == VAR113;
VAR145 = addr == VAR4;
VAR120 = addr == VAR37;
VAR150 = addr == VAR131;
VAR127 = addr == VAR60;
VAR3 = addr == VAR141;
VAR54 = addr == VAR47;
VAR22 = addr == VAR19;
VAR75 = addr == VAR76;
VAR53 = addr == VAR8;
VAR16 = addr == VAR142;
VAR133 = addr == VAR40;
VAR25 = addr == VAR32;
end
end
VAR148 : begin
VAR127 = !VAR158 && !VAR23;
VAR3 = !VAR24 && !VAR94;
VAR152 = 1'b0;
VAR115 = 1'b0;
end
VAR143 : begin
VAR85 = 1'b0;
VAR17 = VAR107 - VAR137 ;
VAR91 = 'h0;
VAR5 = VAR137;
VAR90 = VAR137;
VAR74 = 'h0;
VAR41 = 'h0;
VAR68 = 'h0;
VAR80 = 'h0;
VAR28 = 'h0;
VAR100 = 'h0;
VAR57 = 'h0;
VAR30 = 1'b1;
VAR84 = 1'b1;
VAR129 = 1'b1;
VAR87 = 1'b1;
VAR38 = 1'b1;
VAR69 = 1'b1;
VAR95 = 1'b1;
VAR70 = 1'b1;
VAR72 = 1'b1;
VAR78 = 1'b1;
VAR154= 1'b1;
VAR27 = 1'b1;
VAR53 = !VAR61 && !VAR14;
VAR16 = !VAR65 && !VAR157;
VAR133 = !VAR135 && !VAR66;
VAR54 = !VAR149 && !VAR46;
VAR22 = !VAR88 && !VAR89;
VAR33 = !VAR26 &&
!VAR77;
VAR52 = !VAR111 &&
!VAR144;
VAR155 = !VAR118 &&
!VAR93;
VAR96 = !VAR147 &&
!VAR48;
VAR145 = !VAR160 &&
!VAR1;
VAR120 = !VAR18 &&
!VAR105;
VAR150 = !VAR86 &&
!VAR36;
end
endcase
end
always @*
begin
case (addr)
default : VAR59 = 32'VAR134 VAR7;
endcase
end
endmodule | mit |
intelligenttoasters/CPC2.0 | FPGA/rtl/template.v | 1,517 | module MODULE1 (
);
endmodule | gpl-3.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/fpoint_hw_qsys.v | 282,773 | module MODULE1
(
VAR66,
VAR7,
VAR77,
VAR88,
VAR80,
VAR83) ;
input VAR66;
input VAR7;
input VAR77;
input [31:0] VAR88;
input [31:0] VAR80;
output [31:0] VAR83;
tri0 VAR66;
tri1 VAR7;
reg VAR55;
reg VAR33;
reg VAR29;
reg VAR79;
reg VAR22;
reg VAR28;
reg VAR25;
reg VAR37;
reg [9:0] VAR76;
reg [9:0] VAR26;
reg [9:0] VAR5;
reg VAR78;
reg VAR30;
reg VAR36;
reg [23:0] VAR85;
reg [8:0] VAR72;
reg [9:0] VAR47;
reg [9:0] VAR63;
reg [8:0] VAR86;
reg [8:0] VAR89;
reg [7:0] VAR12;
reg VAR23;
reg VAR68;
reg VAR15;
reg VAR59;
reg VAR57;
reg VAR69;
reg VAR51;
reg VAR45;
reg VAR18;
reg VAR13;
reg VAR74;
reg VAR11;
reg VAR65;
reg VAR20;
reg VAR35;
reg VAR19;
reg VAR71;
reg VAR4;
reg VAR58;
reg VAR50;
reg VAR32;
reg VAR91;
reg VAR1;
reg VAR9;
reg VAR62;
reg [22:0] VAR31;
reg VAR70;
reg [23:0] VAR41;
reg [23:0] VAR42;
reg [24:0] VAR40;
reg VAR90;
reg [0:0] VAR73;
reg [0:0] VAR54;
reg [0:0] VAR64;
reg [0:0] VAR56;
reg [0:0] VAR38;
reg [0:0] VAR49;
reg [0:0] VAR39;
reg [0:0] VAR27;
reg [0:0] VAR10;
reg [0:0] VAR87;
reg VAR53;
wire [8:0] VAR14;
wire [9:0] VAR48;
wire [9:0] VAR44;
wire [24:0] VAR82;
wire [47:0] VAR3;
wire [9:0] VAR21;
wire [7:0] VAR2;
wire [7:0] VAR34;
wire [22:0] VAR8;
wire [7:0] VAR81;
wire [7:0] VAR17;
wire [22:0] VAR43;
wire VAR46;
wire VAR24;
wire [9:0] VAR52;
wire [7:0] VAR84;
wire VAR6;
wire [24:0] VAR60;
wire [7:0] VAR61;
wire [8:0] VAR75;
wire VAR67;
wire VAR16;
wire [22:0] VAR92;
begin
end
begin
end
begin
end | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai.functional.v | 1,514 | module MODULE1 (
VAR6 ,
VAR1,
VAR3,
VAR5,
VAR9,
VAR4
);
output VAR6 ;
input VAR1;
input VAR3;
input VAR5;
input VAR9;
input VAR4;
wire VAR8 ;
wire VAR2;
or VAR11 (VAR8 , VAR3, VAR1 );
nand VAR10 (VAR2, VAR9, VAR5, VAR4, VAR8);
buf VAR7 (VAR6 , VAR2 );
endmodule | apache-2.0 |
joaocarlos/udlx-verilog | rtl/fetch/top_fetch.v | 4,396 | module MODULE1
parameter VAR13 = 20,
parameter VAR6 = 32,
parameter VAR9 = 20'h0
)(
input clk, input VAR4, input en,
input VAR8,
input VAR10, input [VAR13-1:0] VAR11,
output [VAR13-1:0] VAR7, output [VAR13-1:0] VAR12, input VAR2
);
reg [VAR13-1:0] VAR5;
reg [VAR13-1:0] VAR1;
reg [VAR13-1:0] VAR3;
always@
begin
VAR3 = VAR5 + 20'd4;
end
assign VAR12 = VAR5;
always@(posedge clk or negedge VAR4) begin
if(!VAR4) begin
VAR5 <= VAR9;
end
else if (VAR2) begin
VAR5 <= VAR9;
end
else if((!VAR8)&en) begin
VAR5 <= VAR1;
end
end
assign VAR7 = VAR5;
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.functional.pp.v | 1,867 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR6,
VAR10,
VAR4 ,
VAR5
);
output VAR8 ;
input VAR12 ;
input VAR6;
input VAR10;
input VAR4 ;
input VAR5 ;
wire VAR7 ;
wire VAR1;
not VAR9 (VAR7 , VAR12 );
VAR2 VAR3 (VAR1, VAR7, VAR6, VAR10);
buf VAR11 (VAR8 , VAR1 );
endmodule | apache-2.0 |
lvd2/zxevo | fpga/base_trdemu/trunk/z80/zmem.v | 9,807 | module MODULE1(
input wire VAR32,
input wire VAR14,
input wire VAR68, input wire VAR20,
input wire VAR13, input wire VAR7, input wire VAR31, input wire VAR60,
input wire [15:0] VAR9,
input wire [ 7:0] VAR47, output wire [ 7:0] VAR6,
output wire VAR74,
input wire VAR17,
input wire VAR70,
input wire VAR64,
input wire VAR59,
input wire VAR21,
input wire VAR77,
input wire [ 1:0] VAR29,
input wire VAR63, input wire VAR49, input wire VAR2, input wire VAR71,
input wire [ 7:0] VAR12, input wire [ 7:0] VAR19, input wire [ 7:0] VAR54, input wire [ 7:0] VAR40,
input wire VAR38, input wire VAR50,
input wire VAR33,
input wire VAR30,
input wire VAR34,
input wire VAR5,
output reg [ 4:0] VAR41, output wire VAR76,
output wire VAR24,
output wire VAR48,
output wire VAR80,
output wire VAR69,
output wire [20:0] VAR28,
output wire [ 7:0] VAR23,
output wire VAR39,
input wire [15:0] VAR26,
input wire VAR58,
input wire VAR66,
output wire VAR15
);
wire [1:0] VAR53;
reg [7:0] VAR72;
reg VAR22;
reg VAR57;
wire VAR10;
wire VAR51, VAR44, VAR65;
wire VAR16, VAR18;
wire VAR55;
wire VAR79;
reg VAR11;
reg VAR81;
reg VAR62;
reg VAR35;
reg VAR25;
wire VAR27;
wire VAR8,VAR36;
wire VAR73;
reg VAR78,VAR52;
assign VAR53[1:0] = VAR9[15:14];
always @*
case( VAR53 )
2'b00: begin
VAR72 = VAR12;
VAR22 = VAR63;
VAR57 = VAR38;
end
2'b01: begin
VAR72 = VAR19;
VAR22 = VAR49;
VAR57 = VAR50;
end
2'b10: begin
VAR72 = VAR54;
VAR22 = VAR2;
VAR57 = VAR33;
end
2'b11: begin
VAR72 = VAR40;
VAR22 = VAR71;
VAR57 = VAR30;
end
endcase
always @*
begin
VAR41[4:0] = VAR72[4:0];
end
assign VAR24 = VAR77 | VAR64 | (~VAR34) | VAR57;
assign VAR76 = VAR21 | VAR64;
assign VAR48 = VAR22;
assign VAR27 = (~VAR64) && (~VAR22) && VAR70;
assign VAR36 = VAR27 & (~VAR21);
assign VAR8 = (VAR27 & (~VAR77)) & (~VAR57);
always @(posedge VAR32)
if( VAR60 && (!VAR15) )
begin
VAR78 <= VAR36;
VAR52 <= VAR8;
end
assign VAR73 = ( VAR36 & (~VAR78) ) | ( VAR8 & (~VAR52) );
assign VAR74 = (~VAR64) & (~VAR21) & (~VAR22);
wire VAR75;
reg [15:1] VAR45;
reg VAR37;
reg [15:0] VAR4;
wire VAR61;
reg [15:1] VAR56;
reg VAR43;
reg [15:0] VAR42;
wire VAR3;
wire [15:0] VAR67;
assign VAR75 = (VAR9[15:1] == VAR45[15:1]);
assign VAR61 = (VAR9[15:1] == VAR56[15:1]);
assign VAR3 = (VAR75 && VAR37) || (VAR61 && VAR43);
assign VAR67 = (VAR61 && VAR43) ? VAR42 : VAR4;
always @(posedge VAR32)
if( VAR20 )
VAR62 <= VAR64 | (~VAR70);
assign VAR10 = ( !VAR3 || VAR65 ) && VAR20 && VAR62 && (!VAR22) && (!VAR64) && VAR70;
assign VAR51 = (~VAR64) && (~VAR17);
assign VAR44 = (~VAR64) && (~VAR21);
assign VAR65 = (~VAR64) && VAR21 && VAR70 && (!VAR57);
assign VAR55 = VAR10 && ( (!VAR58) || VAR51 || VAR44 );
assign VAR79 = VAR65 ? (!VAR58) : VAR11;
always @(posedge VAR32, negedge VAR14)
if( !VAR14 )
VAR11 <= 1'b0;
else begin
if( VAR58 && VAR60 )
VAR11 <= 1'b0;
end
else if( VAR10 && ( (!VAR60) || (!VAR58) ) && (VAR51 || VAR44) )
VAR11 <= 1'b1;
end
always @(posedge VAR32, negedge VAR14)
if( !VAR14 )
VAR81 <= 1'b0;
else begin
if( VAR81 && ( (VAR51&VAR31) || (VAR44&VAR7) ) )
VAR81 <= 1'b0;
end
else if( VAR58 && VAR60 && VAR80 && (VAR51 || VAR44) )
VAR81 <= 1'b1;
end
assign VAR15 = VAR29[1] ? (VAR55 | VAR79 | VAR81) : (VAR73 && (!VAR58));
assign VAR80 = VAR29[1] ? (VAR35 | VAR10) : VAR73;
assign VAR69 = VAR29[1] ? (VAR10 ? (!VAR65) : VAR25) : VAR36;
always @(posedge VAR32, negedge VAR14)
if( !VAR14 )
VAR35 <= 1'b0;
else if( VAR58 && VAR60 )
VAR35 <= 1'b0;
else if( VAR10 )
VAR35 <= 1'b1;
always @(posedge VAR32)
if( VAR10 )
VAR25 <= !VAR65;
assign VAR39 = VAR9[0];
assign VAR28[20:0] = { VAR72[7:0], VAR9[13:1] };
assign VAR23 = VAR47;
always @* if( VAR66 ) if (VAR17)
VAR42 <= VAR26;
else
VAR4 <= VAR26;
assign VAR6 = VAR39 ? VAR67[7:0] : VAR67[15:8];
wire VAR46;
reg VAR1;
assign VAR46 = (~VAR59);
always @(posedge VAR32)
if( VAR68 )
VAR1 <= VAR46;
always @(posedge VAR32, negedge VAR14)
if( !VAR14 )
begin
VAR37 <= 1'b0;
VAR43 <= 1'b0;
end
else
begin
if( (VAR20 && VAR62 && (!VAR64) && VAR70 && VAR22) ||
(VAR20 && VAR62 && VAR65 ) ||
(VAR46 && (!VAR1) && VAR68 ) ||
(VAR5 ) )
begin
if (VAR65)
begin
if (VAR75)
VAR37 <= 1'b0;
if (VAR61)
VAR43 <= 1'b0;
end
else
begin
VAR43 <= 1'b0;
VAR37 <= 1'b0;
end
end
else if( VAR66 )
begin
if (VAR17)
VAR43 <= 1'b1;
end
else
VAR37 <= 1'b1;
end
end
always @(posedge VAR32)
if( !VAR14 )
begin
end
else if( VAR66 )
begin
if (VAR17)
VAR56[15:1] <= VAR9[15:1];
end
else
VAR45[15:1] <= VAR9[15:1];
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o.functional.v | 1,471 | module MODULE1 (
VAR6 ,
VAR10,
VAR2,
VAR5,
VAR1,
VAR3
);
output VAR6 ;
input VAR10;
input VAR2;
input VAR5;
input VAR1;
input VAR3;
wire VAR4 ;
wire VAR11;
and VAR8 (VAR4 , VAR5, VAR10, VAR2 );
or VAR7 (VAR11, VAR4, VAR3, VAR1);
buf VAR9 (VAR6 , VAR11 );
endmodule | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/Audio_PLL.v | 14,893 | module MODULE1 (
VAR45,
VAR20,
VAR10);
input VAR45;
input VAR20;
output VAR10;
tri0 VAR45;
wire [5:0] VAR23;
wire [0:0] VAR72 = 1'h0;
wire [0:0] VAR64 = VAR23[0:0];
wire VAR10 = VAR64;
wire VAR22 = VAR20;
wire [1:0] VAR95 = {VAR72, VAR22};
VAR11 VAR26 (
.VAR45 (VAR45),
.VAR24 (VAR95),
.clk (VAR23),
.VAR12 (),
.VAR35 (),
.VAR89 ({6{1'b1}}),
.VAR43 (),
.VAR28 (1'b0),
.VAR82 (1'b0),
.VAR59 (),
.VAR81 (),
.VAR71 (),
.VAR14 ({4{1'b1}}),
.VAR84 (1'b1),
.VAR73 (),
.VAR1 (),
.VAR31 (),
.VAR68 (),
.VAR75 (),
.VAR69 (1'b1),
.VAR67 ({4{1'b1}}),
.VAR6 (),
.VAR86 (1'b1),
.VAR88 (1'b1),
.VAR57 (1'b1),
.VAR62 (1'b0),
.VAR65 (1'b0),
.VAR29 (1'b1),
.VAR83 (1'b0),
.VAR40 (),
.VAR49 (),
.VAR91 (1'b0),
.VAR50 (1'b0),
.VAR48 (),
.VAR4 (),
.VAR21 (),
.VAR66 ());
VAR26.VAR27 = 135,
VAR26.VAR94 = 50,
VAR26.VAR44 = 92,
VAR26.VAR87 = "0",
VAR26.VAR77 = "VAR98",
VAR26.VAR7 = 37037,
VAR26.VAR60 = "VAR16 VAR51",
VAR26.VAR33 = "VAR11",
VAR26.VAR47 = "VAR13",
VAR26.VAR3 = "VAR9",
VAR26.VAR32 = "VAR76",
VAR26.VAR46 = "VAR9",
VAR26.VAR92 = "VAR9",
VAR26.VAR17 = "VAR9",
VAR26.VAR18 = "VAR9",
VAR26.VAR25 = "VAR9",
VAR26.VAR30 = "VAR9",
VAR26.VAR38 = "VAR76",
VAR26.VAR80 = "VAR9",
VAR26.VAR2 = "VAR9",
VAR26.VAR15 = "VAR9",
VAR26.VAR56 = "VAR9",
VAR26.VAR42 = "VAR9",
VAR26.VAR100 = "VAR9",
VAR26.VAR58 = "VAR9",
VAR26.VAR97 = "VAR9",
VAR26.VAR63 = "VAR9",
VAR26.VAR39 = "VAR9",
VAR26.VAR70 = "VAR9",
VAR26.VAR8 = "VAR9",
VAR26.VAR41 = "VAR9",
VAR26.VAR78 = "VAR9",
VAR26.VAR34 = "VAR9",
VAR26.VAR53 = "VAR9",
VAR26.VAR79 = "VAR76",
VAR26.VAR93 = "VAR9",
VAR26.VAR19 = "VAR9",
VAR26.VAR54 = "VAR9",
VAR26.VAR36 = "VAR9",
VAR26.VAR96 = "VAR9",
VAR26.VAR99 = "VAR9",
VAR26.VAR55 = "VAR9",
VAR26.VAR61 = "VAR9",
VAR26.VAR101 = "VAR9",
VAR26.VAR52 = "VAR9",
VAR26.VAR90 = "VAR9",
VAR26.VAR74 = "VAR9",
VAR26.VAR37 = "VAR9",
VAR26.VAR5 = "VAR9",
VAR26.VAR85 = "VAR9";
endmodule | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_port_monitor_128.v | 8,208 | module MODULE1 #(
parameter VAR7 = 9'd128,
parameter VAR13 = 512,
parameter VAR26 = (VAR13 - 4),
parameter VAR38 = VAR33((2**VAR33(VAR13))+1),
parameter VAR43 = 1
)
(
input VAR3,
input VAR42,
input [VAR7:0] VAR10, input VAR12, output VAR40,
output [VAR7-1:0] VAR39, output VAR11, input [VAR38-1:0] VAR22,
output VAR1, input VAR20, output VAR29, output [31:0] VAR32, output [30:0] VAR4, output [31:0] VAR17, output VAR2,
input VAR5 );
reg [4:0] VAR30=VAR34, VAR30=VAR34;
reg VAR28=0, VAR28=0;
reg [VAR43-1:0] VAR15={VAR43{1'd0}}, VAR15={VAR43{1'd0}};
reg VAR21=0, VAR21=0;
reg [63:0] VAR25=64'd0, VAR25=64'd0;
reg [31:0] VAR41=0, VAR41=0;
reg [31:0] VAR35=0, VAR35=0;
reg VAR6=0, VAR6=0;
reg VAR23=0, VAR23=0;
reg VAR18=0, VAR18=0;
reg VAR37=0, VAR37=0;
reg VAR36=0, VAR36=0;
reg VAR24=0, VAR24=0;
wire VAR9 = (VAR15[0] & VAR10[VAR7]);
wire VAR27 = (VAR15[0] & !VAR10[VAR7] & VAR30[2]); wire VAR19 = ((VAR6 | (VAR18 & VAR36)) & VAR27);
assign VAR40 = VAR28;
assign VAR39 = VAR10[VAR7-1:0];
assign VAR11 = VAR27;
assign VAR1 = VAR30[1]; assign VAR29 = VAR25[0];
assign VAR4 = VAR25[31:1];
assign VAR32 = VAR25[63:32];
assign VAR17 = VAR41;
assign VAR2 = !VAR30[2];
always @ (posedge VAR42) begin
VAR24 <= (VAR3 ? 1'd0 : VAR24);
end
always @ begin
VAR30 = VAR30;
case (VAR30)
VAR30 = VAR8;
end
VAR30 = ((VAR18 && VAR37) ? VAR14 : VAR31);
end
VAR30 = VAR16;
else if (VAR19 | VAR24)
VAR30 = VAR14;
end
VAR30 = VAR16;
end
VAR30 = VAR34;
end
default: begin
VAR30 = VAR34;
end
endcase
end
always @ (posedge VAR42) begin
VAR28 <= (VAR3 ? 1'd0 : VAR28);
VAR15 <= (VAR3 ? {VAR43{1'd0}} : VAR15);
VAR21 <= (VAR3 ? 1'd0 : VAR21);
VAR25 <= VAR25;
VAR41 <= VAR41;
VAR35 <= VAR35;
VAR6 <= VAR6;
VAR23 <= VAR23;
VAR18 <= VAR18;
VAR37 <= VAR37;
VAR36 <= VAR36;
end
always @ (*) begin
VAR23 = (VAR22 >= VAR26);
VAR15 = ((VAR15<<1) | (VAR28 & !VAR12));
VAR28 = (!VAR30[1] & !VAR9 & !VAR23);
VAR21 = VAR9;
if (VAR9)
VAR25 = VAR10[63:0];
end
else
VAR25 = VAR25;
VAR18 = (VAR32[31:16] == 16'd0);
VAR37 = (VAR32[15:0] == 16'd0);
VAR36 = (VAR32[15:0] <= 16'd4);
VAR41 = (VAR20 ? 0 : VAR41 + (VAR27<<2));
VAR35 = (VAR20 ? 2*(VAR7/32) : VAR35 + (VAR27<<2));
VAR6 = ((VAR35 >= VAR32) && VAR27);
end
endmodule | gpl-3.0 |
DreamSourceLab/DSLogic-hdl | src/uart/uart_top.v | 2,229 | module MODULE1
(
VAR15, reset,
VAR2, VAR9,
VAR1, VAR6,
VAR17, VAR14, VAR10,
VAR11, VAR13,
VAR18
);
input VAR15; input reset; input VAR2; output VAR9; input [7:0] VAR17; input VAR14; output VAR10; output [7:0] VAR1; output VAR6; input [11:0] VAR11; input [15:0] VAR13;
output VAR18;
wire VAR4;
assign VAR18 = VAR4;
VAR5 VAR16
(
.VAR15(VAR15), .reset(reset),
.VAR4(VAR4), .VAR11(VAR11), .VAR13(VAR13)
);
VAR8 VAR7
(
.VAR15(VAR15), .reset(reset),
.VAR4(VAR4), .VAR2(VAR2),
.VAR1(VAR1), .VAR6(VAR6)
);
VAR3 VAR12
(
.VAR15(VAR15), .reset(reset),
.VAR4(VAR4), .VAR17(VAR17), .VAR14(VAR14),
.VAR9(VAR9), .VAR10(VAR10)
);
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.behavioral.v | 2,130 | module MODULE1 (
VAR16 ,
VAR4 ,
VAR2 ,
VAR8 ,
VAR9,
VAR6
);
output VAR16 ;
input VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR9;
input VAR6;
wire VAR12, VAR1 ;
wire VAR12, VAR5 ;
wire VAR7 ;
wire VAR14 ;
wire VAR19;
or VAR18 (VAR7 , VAR2, VAR4 );
and VAR11 (VAR1 , VAR7, VAR8 );
and VAR15 (VAR5 , VAR4, VAR2 );
or VAR10 (VAR14 , VAR5, VAR1 );
VAR17 VAR13 (VAR19, VAR14, VAR9, VAR6);
buf VAR3 (VAR16 , VAR19 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtn/sky130_fd_sc_hs__dlxtn.functional.v | 1,713 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR7 ,
VAR1 ,
VAR13
);
input VAR3 ;
input VAR11 ;
output VAR7 ;
input VAR1 ;
input VAR13;
wire VAR2 VAR5 ;
wire VAR2 VAR4;
wire VAR2 VAR9 ;
wire VAR6 ;
not VAR12 (VAR6 , VAR13 );
VAR10 VAR8 (VAR5 , VAR1, VAR6, VAR3, VAR11);
buf VAR14 (VAR7 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.v | 2,398 | module MODULE2 (
VAR7 ,
VAR6,
VAR1,
VAR11 ,
VAR8 ,
VAR9,
VAR10,
VAR2 ,
VAR4
);
output VAR7 ;
input VAR6;
input VAR1;
input VAR11 ;
input VAR8 ;
input VAR9;
input VAR10;
input VAR2 ;
input VAR4 ;
VAR5 VAR3 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR7 ,
VAR6,
VAR1,
VAR11 ,
VAR8
);
output VAR7 ;
input VAR6;
input VAR1;
input VAR11 ;
input VAR8 ;
supply1 VAR9;
supply0 VAR10;
supply1 VAR2 ;
supply0 VAR4 ;
VAR5 VAR3 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR8(VAR8)
);
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_pc_1/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v | 9,137 | module MODULE1 #
(
parameter VAR60 = "VAR59",
parameter integer VAR63 = 1,
parameter integer VAR2 = 32,
parameter integer VAR4 = 32,
parameter integer VAR8 = 1,
parameter integer VAR47 = 1,
parameter integer VAR46 = 1,
parameter integer VAR36 = 1
)
(
input wire VAR18,
input wire VAR43,
input wire [VAR63-1:0] VAR66,
input wire [VAR2-1:0] VAR28,
input wire [3-1:0] VAR58,
input wire VAR21,
output wire VAR22,
input wire [VAR4-1:0] VAR50,
input wire [VAR4/8-1:0] VAR44,
input wire VAR3,
output wire VAR48,
output wire [VAR63-1:0] VAR55,
output wire [2-1:0] VAR34,
output wire [VAR36-1:0] VAR64, output wire VAR10,
input wire VAR61,
input wire [VAR63-1:0] VAR7,
input wire [VAR2-1:0] VAR68,
input wire [3-1:0] VAR17,
input wire VAR41,
output wire VAR6,
output wire [VAR63-1:0] VAR56,
output wire [VAR4-1:0] VAR54,
output wire [2-1:0] VAR70,
output wire VAR45, output wire [VAR46-1:0] VAR23, output wire VAR49,
input wire VAR9,
output wire [VAR2-1:0] VAR11,
output wire [3-1:0] VAR30,
output wire VAR1,
input wire VAR14,
output wire [VAR4-1:0] VAR42,
output wire [VAR4/8-1:0] VAR24,
output wire VAR40,
input wire VAR33,
input wire [2-1:0] VAR39,
input wire VAR20,
output wire VAR15,
output wire [VAR2-1:0] VAR26,
output wire [3-1:0] VAR37,
output wire VAR13,
input wire VAR71,
input wire [VAR4-1:0] VAR19,
input wire [2-1:0] VAR51,
input wire VAR31,
output wire VAR65
);
wire VAR62;
wire VAR69;
wire [VAR2-1:0] VAR38;
reg VAR5;
reg VAR25;
reg VAR12;
wire VAR16;
wire VAR67;
wire VAR35;
wire VAR57;
reg [1:0] VAR53; always @(posedge VAR18) begin
VAR53 <= {VAR53[0], ~VAR43};
end
assign VAR62 = VAR21 & (VAR8 != 0);
assign VAR69 = VAR41 & (VAR47 != 0);
assign VAR16 = VAR69 & ~VAR12 & ~|VAR53 & ~VAR25;
assign VAR67 = VAR62 & ~VAR12 & ~|VAR53 & ((~VAR5 & ~VAR69) | VAR25);
assign VAR35 = VAR31 & VAR9;
assign VAR57 = VAR20 & VAR61;
always @(posedge VAR18) begin : VAR27
if (|VAR53)
VAR5 <= 1'b0;
end
else if (VAR35)
VAR5 <= 1'b0;
else if (VAR16)
VAR5 <= 1'b1;
end
always @(posedge VAR18) begin : VAR32
if (|VAR53)
VAR25 <= 1'b0;
end
else if (VAR57)
VAR25 <= 1'b0;
else if (VAR67)
VAR25 <= 1'b1;
end
always @(posedge VAR18) begin : VAR52
if (|VAR53)
VAR12 <= 1'b0;
end
else if (VAR35 | VAR57)
VAR12 <= 1'b0;
else if ((VAR67 & VAR14) | (VAR16 & VAR71))
VAR12 <= 1'b1;
end
assign VAR13 = VAR16;
assign VAR6 = VAR71 & VAR16;
assign VAR1 = VAR67;
assign VAR22 = VAR14 & VAR67;
assign VAR65 = VAR9 & VAR5;
assign VAR49 = VAR31 & VAR5;
assign VAR15 = VAR61 & VAR25;
assign VAR10 = VAR20 & VAR25;
assign VAR38 = (VAR16 | (VAR8 == 0)) ? VAR68 : VAR28;
reg [VAR63-1:0] VAR29;
always @(posedge VAR18) begin : VAR72
if (VAR16) VAR29 <= VAR7;
end
else if (VAR67) VAR29 <= VAR66;
end
assign VAR55 = VAR29;
assign VAR56 = VAR29;
assign VAR11 = VAR38;
assign VAR26 = VAR38;
assign VAR48 = VAR33 & ~|VAR53;
assign VAR34 = VAR39;
assign VAR54 = VAR19;
assign VAR70 = VAR51;
assign VAR45 = 1'b1;
assign VAR64 = {VAR36{1'b0}};
assign VAR23 = {VAR46{1'b0}};
assign VAR30 = VAR58;
assign VAR40 = VAR3 & ~|VAR53;
assign VAR42 = VAR50;
assign VAR24 = VAR44;
assign VAR37 = VAR17;
endmodule | mit |
plindstroem/oh | memory/hdl/memory_writemask.v | 1,878 | module MODULE1(
VAR2,
write, VAR1, addr
);
input write;
input [1:0] VAR1;
input [2:0] addr;
output [7:0] VAR2;
reg [7:0] VAR2;
always@*
casez({write, VAR1[1:0],addr[2:0]})
6'b100000 : VAR2[7:0] = 8'b00000001;
6'b100001 : VAR2[7:0] = 8'b00000010;
6'b100010 : VAR2[7:0] = 8'b00000100;
6'b100011 : VAR2[7:0] = 8'b00001000;
6'b100100 : VAR2[7:0] = 8'b00010000;
6'b100101 : VAR2[7:0] = 8'b00100000;
6'b100110 : VAR2[7:0] = 8'b01000000;
6'b100111 : VAR2[7:0] = 8'b10000000;
6'b10100? : VAR2[7:0] = 8'b00000011;
6'b10101? : VAR2[7:0] = 8'b00001100;
6'b10110? : VAR2[7:0] = 8'b00110000;
6'b10111? : VAR2[7:0] = 8'b11000000;
6'b1100?? : VAR2[7:0] = 8'b00001111;
6'b1101?? : VAR2[7:0] = 8'b11110000;
6'b111??? : VAR2[7:0] = 8'b11111111;
default : VAR2[7:0] = 8'b00000000;
endcase
endmodule | gpl-3.0 |
HarmonInstruments/hififo | hdl/sync.v | 1,950 | module MODULE2
(
input VAR2,
input in,
output out
);
reg [2:0] VAR7 = 0;
always @(posedge VAR2)
VAR7 <= {VAR7[1:0], in};
assign out = VAR7[2];
endmodule
module MODULE1
(
input VAR2,
input in,
output reg out = 0
);
reg VAR6 = 0;
always @(posedge VAR2)
begin
VAR6 <= in;
out <= in & ~VAR6;
end
endmodule
module MODULE4
(
input VAR2,
input in,
output reg out = 0
);
parameter VAR9=3;
reg [VAR9-1:0] VAR8 = 0;
always @(posedge VAR2)
begin
if(in)
VAR8 <= 1'b1;
end
else
VAR8 <= VAR8 + (VAR8 != 0);
out <= in | (VAR8 != 0);
end
endmodule
module MODULE3(input VAR2, input in, output out);
wire VAR4;
MODULE2 MODULE2(.VAR2(VAR2), .in(in), .out(VAR4));
MODULE1 MODULE1(.VAR2(VAR2), .in(VAR4), .out(out));
endmodule
module MODULE5 (input VAR11, input VAR10, input in, output out);
parameter VAR9 = 3;
wire VAR3;
MODULE4 #(.VAR9(VAR9)) VAR5
(.VAR2(VAR11), .in(in), .out(VAR3));
MODULE3 MODULE3 (.VAR2(VAR10), .in(VAR3), .out(out));
endmodule | gpl-3.0 |
sirchuckalot/zet | cores/vga/rtl/fml/vga_text_mode_fml.v | 6,480 | module MODULE1 (
input clk,
input rst,
input enable,
output reg [16:1] VAR8,
input [15:0] VAR23,
output VAR6,
input [9:0] VAR30,
input [9:0] VAR7,
input VAR34,
input VAR32,
output VAR1,
input [5:0] VAR19,
input [5:0] VAR3,
input [4:0] VAR40,
input [6:0] VAR22,
output reg [3:0] VAR11,
output VAR35
);
reg [ 6:0] VAR42;
reg [ 4:0] VAR21;
reg [ 6:0] VAR37;
reg [ 6:0] VAR29;
wire [10:0] VAR28;
reg [ 15:0] VAR41;
wire [11:0] VAR24;
wire [ 7:0] VAR25;
reg [ 7:0] VAR31;
reg [ 7:0] VAR33;
reg [15:0] VAR14;
wire VAR5;
reg [7:0] VAR20;
reg [7:0] VAR27;
wire VAR39;
wire VAR9;
wire VAR15;
reg [ 7:0] VAR16;
reg [ 3:0] VAR4;
reg [ 2:0] VAR17;
reg [22:0] VAR13;
reg VAR18;
reg VAR38;
reg VAR10;
wire VAR2;
VAR26 VAR36 (
.clk (clk),
.addr (VAR24),
.VAR12 (VAR25)
);
assign VAR28 = { 4'b0, VAR37 } + { VAR29, 4'b0 };
assign VAR24 = { VAR33, VAR7[3:0] };
assign VAR5 = VAR14[7] | VAR14[15];
assign VAR1 = VAR20[7];
assign VAR35 = VAR27[7];
assign VAR6 = VAR14[2];
assign VAR39 = VAR16[7] ^ VAR10;
assign VAR2 = VAR38 && VAR18;
always @(posedge clk)
if (rst)
begin
VAR42 <= 7'h0;
VAR21 <= 5'h0;
VAR29 <= 7'h0;
VAR37 <= 7'h0;
VAR8 <= 16'h0;
end
else
if (enable)
begin
VAR42 <= VAR30[9:3];
VAR21 <= VAR7[8:4];
VAR29 <= { 2'b00, VAR21 } + { VAR21, 2'b00 };
VAR37 <= VAR42;
VAR8 <= { 3'h0, VAR28, 2'b00 };
end
always @(posedge clk)
if (rst)
begin
VAR18 <= 1'b0;
VAR38 <= 1'b0;
end
else
if (enable)
begin
VAR38 <= (VAR30[9:3] == VAR22[6:0]);
VAR18 <= (VAR7[8:4] == VAR40[4:0])
&& ({2'b00, VAR7[3:0]} >= VAR19)
&& ({2'b00, VAR7[3:0]} <= VAR3);
end
always @(posedge clk)
if (rst)
begin
VAR14 <= 15'b0;
end
else
if (enable)
begin
VAR14 <= { VAR14[14:0], (VAR30[3:0]==3'b0) };
end
always @(posedge clk)
if (enable)
begin
VAR41 <= VAR14[9] ? VAR23[15:0] : VAR41;
end
always @(posedge clk)
if (enable)
begin
if (VAR14[5])
VAR31 <= VAR23[15:8];
end
else
if (VAR14[13])
VAR31 <= VAR41[15:8];
end
always @(posedge clk)
if (enable)
begin
if (VAR14[5])
VAR33 <= VAR23[7:0];
end
else
if (VAR14[13])
VAR33 <= VAR41[7:0];
end
always @(posedge clk)
if (rst)
begin
VAR20 <= 8'b0;
end
else
if (enable)
begin
VAR20 <= { VAR20[6:0], VAR32 };
end
always @(posedge clk)
if (rst)
begin
VAR27 <= 8'b0;
end
else
if (enable)
begin
VAR27 <= { VAR27[6:0], VAR34 };
end
always @(posedge clk)
if (rst)
begin
VAR13 <= 23'h0;
end
else
if (enable)
begin
VAR13 <= (VAR13 + 23'h1);
end
always @(posedge clk)
if (rst)
begin
VAR4 <= 4'b0;
VAR17 <= 3'b0;
VAR16 <= 8'h0;
end
else
if (enable)
begin
if (VAR5)
begin
VAR4 <= VAR31[3:0];
VAR17 <= VAR31[6:4];
VAR10 <= (VAR2 | VAR31[7]) & VAR13[22];
VAR16 <= VAR25;
end
else VAR16 <= { VAR16[6:0], 1'b0 };
end
always @(posedge clk)
if (rst)
begin
VAR11 <= 4'h0;
end
else
if (enable)
begin
VAR11 <= VAR39 ? VAR4 : { 1'b0, VAR17 };
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4bb/sky130_fd_sc_ls__or4bb.behavioral.pp.v | 1,988 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR17 ,
VAR8 ,
VAR9 ,
VAR1,
VAR2,
VAR7 ,
VAR10
);
output VAR13 ;
input VAR4 ;
input VAR17 ;
input VAR8 ;
input VAR9 ;
input VAR1;
input VAR2;
input VAR7 ;
input VAR10 ;
wire VAR15 ;
wire VAR12 ;
wire VAR6;
nand VAR16 (VAR15 , VAR9, VAR8 );
or VAR14 (VAR12 , VAR17, VAR4, VAR15 );
VAR5 VAR11 (VAR6, VAR12, VAR1, VAR2);
buf VAR3 (VAR13 , VAR6 );
endmodule | apache-2.0 |
freecores/eco32 | fpga/src/tmr/tmr.v | 1,753 | module MODULE1(clk, reset,
en, wr, addr,
VAR4, VAR5,
VAR3, irq);
input clk;
input reset;
input en;
input wr;
input [3:2] addr;
input [31:0] VAR4;
output reg [31:0] VAR5;
output VAR3;
output irq;
reg [31:0] counter;
reg [31:0] VAR8;
reg VAR1;
reg VAR7;
reg VAR6;
reg VAR2;
always @(posedge clk) begin
if (VAR1 == 1) begin
counter <= VAR8;
VAR7 <= 0;
end else begin
if (counter == 32'h00000001) begin
counter <= VAR8;
VAR7 <= 1;
end else begin
counter <= counter - 1;
VAR7 <= 0;
end
end
end
always @(posedge clk) begin
if (reset == 1) begin
VAR8 <= 32'hFFFFFFFF;
VAR1 <= 1;
VAR6 <= 0;
VAR2 <= 0;
end else begin
if (VAR7 == 1) begin
VAR6 <= 1;
end else begin
if (en == 1 && wr == 1 && addr[3:2] == 2'b00) begin
VAR6 <= VAR4[0];
VAR2 <= VAR4[1];
end
if (en == 1 && wr == 1 && addr[3:2] == 2'b01) begin
VAR8 <= VAR4;
VAR1 <= 1;
end else begin
VAR1 <= 0;
end
end
end
end
always @(*) begin
case (addr[3:2])
2'b00:
VAR5 = { 28'h0000000, 2'b00, VAR2, VAR6 };
2'b01:
VAR5 = VAR8;
2'b10:
VAR5 = counter;
2'b11:
VAR5 = 32'VAR9;
default:
VAR5 = 32'VAR9;
endcase
end
assign VAR3 = 0;
assign irq = VAR2 & VAR6;
endmodule | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.behavioral.v | 8,908 | module MODULE1( VAR56, VAR14, VAR40, VAR12, VAR34 );
input VAR12, VAR40, VAR56, VAR14;
output VAR34;
reg VAR48;
VAR68 VAR4(.VAR56(VAR56),.VAR14(VAR14),.VAR40(VAR40),.VAR12(VAR12),.VAR34(VAR34),.VAR48(VAR48));
VAR68 VAR84(.VAR56(VAR56),.VAR14(VAR14),.VAR40(VAR40),.VAR12(VAR12),.VAR34(VAR34),.VAR48(VAR48));
not VAR2(VAR63,VAR40);
not VAR73(VAR46,VAR56);
and VAR60(VAR82,VAR46,VAR63);
not VAR43(VAR51,VAR14);
and VAR71(VAR18,VAR51,VAR82);
not VAR70(VAR30,VAR40);
not VAR55(VAR24,VAR56);
and VAR15(VAR81,VAR24,VAR30);
and VAR69(VAR37,VAR14,VAR81);
not VAR38(VAR9,VAR40);
and VAR64(VAR66,VAR56,VAR9);
not VAR44(VAR78,VAR14);
and VAR86(VAR13,VAR78,VAR66);
not VAR3(VAR27,VAR40);
and VAR74(VAR5,VAR56,VAR27);
and VAR75(VAR39,VAR14,VAR5);
not VAR26(VAR72,VAR56);
and VAR79(VAR35,VAR72,VAR40);
not VAR16(VAR28,VAR14);
and VAR57(VAR19,VAR28,VAR35);
not VAR52(VAR80,VAR56);
and VAR77(VAR49,VAR80,VAR40);
and VAR89(VAR29,VAR14,VAR49);
and VAR33(VAR7,VAR56,VAR40);
not VAR58(VAR83,VAR14);
and VAR50(VAR31,VAR83,VAR7);
and VAR1(VAR85,VAR56,VAR40);
and VAR42(VAR36,VAR14,VAR85);
not VAR20(VAR67,VAR56);
not VAR25(VAR22,VAR14);
and VAR87(VAR10,VAR22,VAR67);
not VAR59(VAR17,VAR56);
and VAR54(VAR23,VAR14,VAR17);
not VAR11(VAR6,VAR40);
and VAR53(VAR65,VAR14,VAR6);
not VAR21(VAR45,VAR14);
and VAR8(VAR32,VAR45,VAR40);
not VAR76(VAR47,VAR40);
and VAR88(VAR41,VAR56,VAR47);
and VAR61(VAR62,VAR56,VAR40); | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/altpllpll.v | 15,902 | module MODULE1 (
VAR73,
VAR4,
VAR8);
input VAR73;
output VAR4;
output VAR8;
wire [9:0] VAR99;
wire [0:0] VAR70 = 1'h0;
wire [1:1] VAR66 = VAR99[1:1];
wire [0:0] VAR63 = VAR99[0:0];
wire VAR4 = VAR63;
wire VAR8 = VAR66;
wire VAR51 = VAR73;
wire [1:0] VAR26 = {VAR70, VAR51};
VAR2 VAR37 (
.VAR29 (VAR26),
.clk (VAR99),
.VAR28 (),
.VAR1 (1'b0),
.VAR30 (),
.VAR77 ({6{1'b1}}),
.VAR64 (),
.VAR93 (1'b0),
.VAR107 (1'b0),
.VAR19 (),
.VAR102 (),
.VAR86 (),
.VAR50 ({4{1'b1}}),
.VAR36 (1'b1),
.VAR71 (),
.VAR100 (),
.VAR42 (),
.VAR31 (),
.VAR68 (),
.VAR54 (1'b1),
.VAR33 ({4{1'b1}}),
.VAR114 (),
.VAR60 (1'b1),
.VAR96 (1'b1),
.VAR34 (1'b1),
.VAR6 (1'b0),
.VAR101 (1'b0),
.VAR16 (1'b1),
.VAR17 (1'b0),
.VAR44 (),
.VAR83 (),
.VAR43 (1'b0),
.VAR113 (1'b0),
.VAR49 (),
.VAR46 (),
.VAR48 (),
.VAR56 ());
VAR37.VAR112 = "VAR18",
VAR37.VAR80 = 1,
VAR37.VAR57 = 50,
VAR37.VAR74 = 1,
VAR37.VAR59 = "0",
VAR37.VAR97 = 25,
VAR37.VAR94 = 50,
VAR37.VAR84 = 2,
VAR37.VAR58 = "0",
VAR37.VAR15 = "VAR35",
VAR37.VAR72 = 8000,
VAR37.VAR109 = "VAR91 VAR90",
VAR37.VAR103 = "VAR2",
VAR37.VAR81 = "VAR104",
VAR37.VAR25 = "VAR18",
VAR37.VAR65 = "VAR55",
VAR37.VAR62 = "VAR55",
VAR37.VAR87 = "VAR55",
VAR37.VAR3 = "VAR55",
VAR37.VAR12 = "VAR55",
VAR37.VAR75 = "VAR55",
VAR37.VAR32 = "VAR55",
VAR37.VAR92 = "VAR55",
VAR37.VAR41 = "VAR55",
VAR37.VAR9 = "VAR98",
VAR37.VAR11 = "VAR55",
VAR37.VAR24 = "VAR55",
VAR37.VAR89 = "VAR55",
VAR37.VAR105 = "VAR55",
VAR37.VAR67 = "VAR55",
VAR37.VAR53 = "VAR55",
VAR37.VAR95 = "VAR55",
VAR37.VAR21 = "VAR55",
VAR37.VAR45 = "VAR55",
VAR37.VAR111 = "VAR55",
VAR37.VAR20 = "VAR55",
VAR37.VAR22 = "VAR55",
VAR37.VAR108 = "VAR55",
VAR37.VAR82 = "VAR55",
VAR37.VAR27 = "VAR55",
VAR37.VAR52 = "VAR55",
VAR37.VAR69 = "VAR98",
VAR37.VAR61 = "VAR98",
VAR37.VAR78 = "VAR55",
VAR37.VAR39 = "VAR55",
VAR37.VAR10 = "VAR55",
VAR37.VAR13 = "VAR55",
VAR37.VAR85 = "VAR55",
VAR37.VAR79 = "VAR55",
VAR37.VAR47 = "VAR55",
VAR37.VAR110 = "VAR55",
VAR37.VAR7 = "VAR55",
VAR37.VAR23 = "VAR55",
VAR37.VAR88 = "VAR55",
VAR37.VAR76 = "VAR55",
VAR37.VAR14 = "VAR55",
VAR37.VAR40 = "VAR55",
VAR37.VAR106 = "VAR5",
VAR37.VAR38 = 10;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4b/sky130_fd_sc_hs__or4b.functional.pp.v | 1,880 | module MODULE1 (
VAR12,
VAR3,
VAR9 ,
VAR11 ,
VAR14 ,
VAR10 ,
VAR8
);
input VAR12;
input VAR3;
output VAR9 ;
input VAR11 ;
input VAR14 ;
input VAR10 ;
input VAR8 ;
wire VAR8 VAR15 ;
wire VAR5 ;
wire VAR7;
not VAR1 (VAR15 , VAR8 );
or VAR6 (VAR5 , VAR15, VAR10, VAR14, VAR11 );
VAR2 VAR4 (VAR7, VAR5, VAR12, VAR3);
buf VAR13 (VAR9 , VAR7 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_synth.v | 1,503 | module MODULE1 #(parameter VAR22(VAR20)
, parameter VAR22(VAR7)
, parameter VAR9=0
, parameter VAR8=VAR12(VAR7)
)
(input VAR6
, input VAR3
, input VAR23
, input [VAR8-1:0] VAR15
, input [VAR5(VAR20, 1):0] VAR14
, input VAR4
, input [VAR8-1:0] VAR1
, output logic [VAR5(VAR20, 1):0] VAR2
, input VAR19
, input [VAR8-1:0] VAR16
, output logic [VAR5(VAR20, 1):0] VAR13
);
wire VAR10 = VAR3;
if (VAR20 == 0)
begin: VAR17
wire VAR18 = &{VAR6, VAR23, VAR15, VAR14, VAR4, VAR1, VAR19, VAR16};
assign VAR2 = '0;
assign VAR13 = '0;
end
else
begin: VAR24
logic [VAR20-1:0] VAR21 [VAR7-1:0];
assign VAR13 = VAR21[VAR16];
assign VAR2 = VAR21[VAR1];
VAR11 @(posedge VAR6)
if (VAR23)
begin
VAR21[VAR15] <= VAR14;
end
end
endmodule | bsd-3-clause |
yugr/primogen | src/prio_enc.v | 1,666 | module MODULE1 #(
parameter VAR2 = 4
) (VAR11, VAR9);
localparam VAR7 = 1 << VAR2;
localparam VAR5 = VAR7 - 1;
input [VAR5:0] VAR11;
output reg [VAR2 - 1:0] VAR9;
integer VAR8, VAR6;
reg [VAR5:0] VAR4;
always @* begin
VAR9 = 0;
VAR4 = VAR11;
for (VAR8 = VAR2 - 1; VAR8 >= 0; VAR8 = VAR8 - 1) begin
VAR6 = 1 << VAR8;
if (|(VAR4 >> VAR6))
VAR9[VAR8] = 1;
VAR4 = VAR9[VAR8] ? VAR4 >> VAR6 : VAR4 & ((1'd1 << VAR6) - 1'd1);
end
end
output [VAR2 - 1:0] VAR9;
wire [VAR2*VAR7 - 1:0] VAR1;
assign VAR1[VAR2*VAR7 - 1:(VAR2 - 1)*VAR7] = VAR11;
genvar VAR10, VAR8;
integer VAR3;
generate
for (VAR10 = VAR2 - 1; VAR10 >= 0; VAR10 = VAR10 - 1) begin
assign VAR9[VAR10] = |VAR1[VAR10*VAR7 + 2*(1 << VAR10) - 1:VAR10*VAR7 + (1 << VAR10)];
if (VAR10 > 0) begin
assign VAR1[(VAR10 - 1)*VAR7 + (1 << VAR10) - 1:(VAR10 - 1)*VAR7] = VAR9[VAR10] ? VAR1[VAR10*VAR7 + 2*(1 << VAR10) - 1:VAR10*VAR7 + (1 << VAR10)] : VAR1[VAR10*VAR7 + (1 << VAR10) - 1:VAR10*VAR7];
end
end
endgenerate
output reg [VAR2 - 1:0] VAR9;
integer VAR8;
always @* begin
VAR9 = 0;
for (VAR8 = VAR5; VAR8 >= 0; VAR8 = VAR8 - 1)
if (!VAR9 && VAR11[VAR8])
VAR9 = VAR8;
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b.blackbox.v | 1,307 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2
);
output VAR4 ;
input VAR3 ;
input VAR2;
supply1 VAR6;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
ipcoregarfield/GEM_Project | Verilog_Code_Frame.v | 3,337 | module MODULE1 #(parameter VAR1 = 3, VAR9 = 2)
(
input VAR14, VAR23,
output VAR4
);
localparam VAR15 = VAR1 / VAR9;
localparam VAR24 = VAR1 - VAR9 * VAR15;
localparam VAR17 = VAR9;
localparam VAR18 = VAR17 - VAR24;
localparam VAR10 = VAR24;
localparam VAR13 = VAR18 * VAR15;
localparam VAR12 = VAR10 * (VAR15 + 1);
localparam VAR7 = VAR13 + VAR12;
localparam VAR25 = VAR21(VAR7);
function integer VAR21(input integer VAR19);
begin
VAR21 = 1;
while ( (2 ** VAR21) < VAR19)
begin
VAR21 = VAR21 + 1;
end
end
endfunction
reg[VAR25 - 1:0] counter;
wire VAR11, VAR3;
reg VAR6, VAR8;
reg VAR16;
VAR2 #(.VAR26(VAR15)) VAR5(.VAR14(VAR14), .VAR23(VAR23),.VAR20(VAR6), .VAR4(VAR11));
VAR2 #(.VAR26(VAR15+1)) VAR22(.VAR14(VAR14), .VAR23(VAR23), .VAR20(VAR8), .VAR4(VAR3));
assign VAR4 =(VAR16) ? (VAR11) : (VAR3);
always @
begin
assign VAR8 <= ~VAR6;
end
always @(posedge VAR14 or negedge VAR23)
begin
if (!VAR23)
begin
counter <= 1'h0;
end
else if (counter == VAR7 - 1)
begin
counter <= 1'h0;
end
else
begin
counter <= counter + 1'h1;
end
end
always @(posedge VAR14 or negedge VAR23)
begin
if (!VAR23)
begin
VAR16 <=1'b0;
end
else
begin
VAR16 <= VAR6;
end
end
endmodule | gpl-3.0 |
finnball/igloo | infra/hdl/uart_tx.v | 1,530 | module MODULE1(
input VAR3,
input [VAR2 - 1 : 0] VAR8,
input VAR11,
output VAR5,
output VAR9
);
localparam VAR7 = 3'd0;
localparam VAR10 = 3'd1;
localparam VAR1 = 3'd2;
localparam VAR6 = 3'd3;
reg [2:0] state = VAR7;
reg [2:0] VAR13 = 0;
reg [VAR2 - 1 : 0] VAR4 = 0;
reg VAR12 = 1;
always @ (posedge VAR3)
begin
case (state)
VAR7 :
if (VAR11)
begin
state <= VAR10;
end
VAR10 :
state <= VAR1;
VAR1 :
if (VAR13 == 7)
begin
state <= VAR6;
end
VAR6 :
state <= VAR7;
endcase
end
always @ (posedge VAR3)
begin
if (state == VAR1)
begin
VAR13 <= VAR13 + 1;
end
else
begin
VAR13 <= 0;
end
end
always @ (posedge VAR3)
begin
if (state == VAR10)
begin
VAR4 <= VAR8;
end
else if (state == VAR1)
begin
VAR4 <= VAR4 >> 1;
end
end
assign VAR9 = (state == VAR7) ? 0 : 1;
always @ *
begin
if (state == VAR10)
begin
VAR12 = 0;
end
else if (state == VAR1)
begin
VAR12 = VAR4[0];
end
else if (state == VAR6)
begin
VAR12 = 1;
end
end
assign VAR5 = VAR12;
endmodule | gpl-3.0 |
mshr-h/fibonacci_verilog | fpga/mu500rx/fpga_top.v | 2,409 | module MODULE1
(
input wire VAR2,
input wire VAR32,
input wire clk,
input wire VAR5,
input wire VAR14,
output wire [7:0] VAR15,
output wire [7:0] VAR27,
output wire [7:0] VAR21,
output wire [7:0] VAR4,
output wire [7:0] VAR23,
output wire [7:0] VAR41,
output wire [7:0] VAR24,
output wire [7:0] VAR1,
output wire [8:0] VAR20
);
parameter
VAR17 = 7,
VAR26 = 90;
reg req;
reg [VAR17-1:0] VAR37;
wire ack;
wire [VAR26-1:0] VAR31;
reg [1:0] VAR13 = 0;
reg [1:0] VAR19 = 0;
always @(posedge clk) begin
VAR13 <= {VAR13[0], VAR5};
VAR19 <= {VAR19[0], VAR14};
end
wire VAR29 = (VAR13 == 2'b10);
wire VAR7 = (VAR19 == 2'b10);
always @(posedge clk or negedge VAR2) begin
if(~VAR2)
req <= 0;
end
else if(VAR29) begin
req <= 1;
VAR37 <= 60;
end
else if(VAR7)
req <= 0;
end
VAR40
.VAR17 ( VAR17 ) ,
.VAR26 ( VAR26 )
) VAR42
(
.VAR34 ( VAR2 ) ,
.clk ( clk ) ,
.req ( req ) ,
.VAR37 ( VAR37 ) ,
.ack ( ack ) ,
.VAR31 ( VAR31 )
);
VAR43
VAR43
(
.VAR2 ( VAR2 ),
.VAR22 ( VAR32 ),
.VAR6 ( {3'h0, clk, 3'h0, VAR2, 8'h00} ),
.VAR18 ( {3'h0, VAR5, 3'h0, VAR14, 3'h0, req, 3'h0, ack} ),
.VAR8 ( 0 ) ,
.VAR28 ( VAR37 ) ,
.VAR38 ( VAR31[89:64] ) ,
.VAR9 ( VAR31[63:48] ) ,
.VAR35 ( VAR31[47:32] ) ,
.VAR30 ( VAR31[31:16] ) ,
.VAR12 ( VAR31[15: 0] ) ,
.VAR10 ( 0 ) ,
.VAR3 ( 0 ) ,
.VAR11 ( 0 ) ,
.VAR16 ( 0 ) ,
.VAR33 ( 0 ) ,
.VAR25 ( 0 ) ,
.VAR39 ( 0 ) ,
.VAR15 ( VAR15 ) ,
.VAR27 ( VAR27 ) ,
.VAR21 ( VAR21 ) ,
.VAR4 ( VAR4 ) ,
.VAR23 ( VAR23 ) ,
.VAR41 ( VAR41 ) ,
.VAR24 ( VAR24 ) ,
.VAR1 ( VAR1 ) ,
.VAR36 ( VAR20 )
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn.behavioral.v | 1,312 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR8
);
output VAR7 ;
input VAR3 ;
input VAR8;
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR5 ;
bufif0 VAR6 (VAR7 , VAR3, VAR8 );
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/system_controller/system_controller_xilinx.v | 6,519 | module MODULE1 (
VAR9, VAR26, VAR33,
VAR13, VAR48
) ;
input wire VAR13;
input wire VAR48;
output wire VAR9;
output reg VAR26;
output wire VAR33;
wire VAR28;
VAR61 VAR22(.VAR59(VAR13), .VAR53(VAR28));
wire VAR10;
VAR64 VAR52 (
.VAR14(1'b1),
.VAR53(VAR9), .VAR59(VAR10) );
VAR30 #(
.VAR17("VAR27"),
.VAR56(6.0),
.VAR11(0.0),
.VAR57(10.0),
.VAR5(1),
.VAR4(1),
.VAR15(1),
.VAR63(1),
.VAR49(1),
.VAR42(1),
.VAR39(1.0),
.VAR38(0.5),
.VAR47(0.5),
.VAR23(0.5),
.VAR43(0.5),
.VAR35(0.5),
.VAR46(0.5),
.VAR18(0.5),
.VAR51(0.0),
.VAR50(0.0),
.VAR2(0.0),
.VAR62(0.0),
.VAR21(0.0),
.VAR32(0.0),
.VAR16(0.0),
.VAR40("VAR41"), .VAR45(1),
.VAR8(0.0),
.VAR20("VAR41")
)
VAR31 (
.VAR6(),
.VAR55(),
.VAR24(),
.VAR25(),
.VAR44(),
.VAR7(),
.VAR37(),
.VAR65(),
.VAR29(),
.VAR60(),
.VAR19(),
.VAR10(VAR10),
.VAR12(), .VAR58(VAR58),
.VAR36(VAR28),
.VAR54(1'b0),
.VAR34(VAR48),
.VAR1(VAR9)
);
reg [3:0] VAR3;
assign VAR33 = ~VAR26;
always @(posedge VAR28)
if (VAR48 | ~VAR58) begin
VAR26 <= 1;
VAR3 <= 4'hF;
end else begin
if (VAR58) begin
if (VAR3) begin
VAR3 <= VAR3 - 1;
end else begin
VAR26 <= 0;
end
end
end
endmodule | mit |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkMem_Model.v | 5,585 | module MODULE1(VAR21,
VAR26,
VAR57,
VAR15,
VAR38,
VAR65,
VAR55,
VAR23);
input VAR21;
input VAR26;
input [352 : 0] VAR57;
input VAR15;
output VAR38;
input VAR65;
output [255 : 0] VAR55;
output VAR23;
wire [255 : 0] VAR55;
wire VAR38, VAR23;
wire [255 : 0] VAR29, VAR33;
wire VAR1,
VAR14,
VAR31,
VAR4,
VAR63;
wire [255 : 0] VAR2, VAR66;
wire [63 : 0] VAR39,
VAR27,
VAR19,
VAR34,
VAR16,
VAR58;
wire VAR10;
wire VAR32,
VAR11,
VAR3,
VAR48;
reg [31 : 0] VAR6;
reg [31 : 0] VAR56;
wire VAR41;
assign VAR38 = VAR63 ;
assign VAR32 = VAR63 ;
assign VAR3 = VAR15 ;
assign VAR55 = VAR33 ;
assign VAR23 = VAR31 ;
assign VAR11 = VAR31 ;
assign VAR48 = VAR65 ;
VAR45 #(.VAR67(32'd256), .VAR20(32'd1)) VAR37(.VAR30(VAR26),
.VAR21(VAR21),
.VAR43(VAR29),
.VAR47(VAR4),
.VAR8(VAR14),
.VAR18(VAR1),
.VAR24(VAR33),
.VAR7(VAR63),
.VAR59(VAR31));
VAR64 #(.VAR53("VAR61.VAR25"),
.VAR40(32'd64),
.VAR22(32'd256),
.VAR60(64'd0),
.VAR52(64'd8388607),
.VAR5(1'd0)) VAR17(.VAR21(VAR21),
.VAR12(VAR39),
.VAR62(VAR27),
.VAR13(VAR19),
.VAR51(VAR34),
.VAR42(VAR16),
.VAR36(VAR58),
.VAR43(VAR2),
.VAR44(VAR10),
.VAR35(VAR66),
.VAR54(),
.VAR50(),
.VAR28(),
.VAR9());
assign VAR29 = VAR66 ;
assign VAR4 =
VAR15 &&
VAR41 &&
!VAR57[352] ;
assign VAR14 = VAR65 ;
assign VAR1 = 1'b0 ;
assign VAR39 = VAR57[319:256] ;
assign VAR27 = 64'h0 ;
assign VAR19 = 64'h0 ;
assign VAR34 = 64'h0 ;
assign VAR16 = 64'h0 ;
assign VAR58 = VAR57[319:256] ;
assign VAR2 = VAR57[255:0] ;
assign VAR10 =
VAR15 &&
VAR41 &&
VAR57[352] ;
assign VAR41 =
VAR57[319:256] < 64'h0000000000800000 ;
always@(negedge VAR21)
begin
if (VAR26 != VAR49)
if (VAR15 &&
!VAR41)
begin
VAR6 = VAR46;
end
VAR56 = VAR6 / 32'd10;
if (VAR26 != VAR49)
if (VAR15 &&
!VAR41)
",
VAR56,
VAR57[319:256],
64'h0000000000800000);
if (VAR26 != VAR49)
if (VAR15 &&
!VAR41)
end
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv.functional.pp.v | 1,800 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR10,
VAR9,
VAR6 ,
VAR1
);
output VAR11 ;
input VAR7 ;
input VAR10;
input VAR9;
input VAR6 ;
input VAR1 ;
wire VAR4 ;
wire VAR3;
not VAR12 (VAR4 , VAR7 );
VAR8 VAR2 (VAR3, VAR4, VAR10, VAR9);
buf VAR5 (VAR11 , VAR3 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_ddrx_encoder_40.v | 8,560 | module MODULE1
(
VAR8,
VAR15,
VAR10) ;
input VAR8;
input [31:0] VAR15;
output [38:0] VAR10;
tri0 VAR8;
reg [38:0] VAR7;
wire VAR2;
wire VAR14;
wire [31:0] VAR13;
wire [17:0] VAR5;
wire [9:0] VAR9;
wire [4:0] VAR12;
wire [1:0] VAR11;
wire [0:0] VAR3;
wire [5:0] VAR6;
wire [37:0] VAR1;
wire [38:0] VAR4; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.functional.pp.v | 1,730 | module MODULE1 (
VAR7,
VAR3,
VAR5 ,
VAR8,
VAR11,
VAR2 ,
VAR4
);
output VAR7;
input VAR3;
input VAR5 ;
input VAR8;
input VAR11;
input VAR2 ;
input VAR4 ;
wire VAR10 ;
wire VAR12;
not VAR9 (VAR12 , VAR5 );
VAR1 VAR13 (VAR10 , VAR3, VAR12, , VAR8, VAR11);
and VAR6 (VAR7 , VAR10, VAR5 );
endmodule | apache-2.0 |
sam-falvo/remex | example/rtl/PolarisCPU.v | 7,935 | module MODULE1(
output VAR134,
output VAR72,
output [3:0] VAR19,
output [63:0] VAR15,
output VAR172,
output VAR106,
input VAR13,
input VAR43,
input [31:0] VAR16,
output [63:0] VAR58,
output VAR136,
input VAR112,
input [63:0] VAR56,
output [63:0] VAR74,
output [63:0] VAR20,
output VAR117,
output VAR100,
output VAR29,
output [1:0] VAR107,
output VAR85,
output [11:0] VAR149,
output VAR152,
output VAR6,
input VAR83,
output [63:0] VAR146,
input [63:0] VAR31,
input VAR67,
input VAR38
);
wire VAR156, VAR76;
wire VAR24;
wire VAR125;
wire VAR70;
reg VAR165;
reg rst;
reg [63:0] VAR52, VAR91;
wire [63:0] VAR81, VAR42;
reg [31:0] VAR130;
wire [31:0] VAR96;
reg VAR171, VAR104, VAR2, VAR34, VAR99;
wire VAR163, VAR61, VAR168, VAR103, VAR119;
wire [4:0] VAR157;
wire VAR39, VAR35, VAR84;
wire VAR111, VAR94;
wire [63:0] VAR97, VAR151;
wire VAR89;
reg [63:0] VAR121, VAR155;
wire [63:0] VAR164, VAR87;
wire VAR59, VAR71, VAR73;
wire VAR88, VAR47, VAR143, VAR80, VAR169;
wire [63:0] VAR131, VAR54, VAR128;
wire VAR86;
wire VAR110;
wire VAR25;
wire VAR159;
wire VAR27;
wire VAR63;
wire VAR36;
wire VAR92;
wire VAR148, VAR78;
wire [63:0] VAR82, VAR105;
wire VAR144;
wire VAR116;
wire VAR1;
wire [3:0] VAR98;
wire VAR167;
wire VAR122;
wire VAR129;
wire [63:0] VAR40, VAR147;
wire VAR41;
wire VAR32;
wire VAR68;
wire VAR69;
wire VAR115;
wire VAR53;
wire VAR11;
wire [7:0] VAR57;
reg [7:0] VAR77;
wire VAR4;
wire VAR142;
reg VAR93;
wire VAR21, VAR90, VAR140;
wire VAR7;
reg [63:0] VAR23;
wire [63:0] VAR75;
wire VAR10;
wire VAR22;
wire VAR49, VAR170;
wire VAR3, VAR123;
wire VAR5, VAR138;
wire VAR127, VAR173;
wire VAR160, VAR158;
wire VAR45;
wire VAR51;
wire VAR141;
wire VAR9;
wire VAR14;
wire [63:0] VAR95;
wire [63:0] VAR26;
wire VAR113;
wire VAR153;
wire VAR162;
wire VAR137 = VAR14 | VAR83;
wire [63:0] VAR101 = VAR95 | VAR31;
wire VAR166 = |VAR130[11:7];
wire VAR120 = |VAR130[19:15];
wire [63:0] VAR60 = {59'b0, VAR130[19:15]};
assign VAR152 = VAR160 & VAR166;
assign VAR6 = VAR158 & VAR120;
assign VAR149 = VAR130[31:20];
assign VAR146 = (VAR173 ? VAR151 : 0) |
(VAR51 ? VAR105 : 0) |
(VAR45 ? VAR60 : 0);
wire VAR161 = VAR105[63] ^ VAR116;
assign VAR57 = VAR4 ? {VAR144, ~VAR144, ~VAR161, VAR161, 2'b00, ~VAR1, VAR1} : VAR77;
assign VAR85 = VAR115 & ~VAR130[14];
assign VAR107 = VAR115 ? VAR130[13:12] : 2'b00;
assign VAR100 = VAR68;
assign VAR29 = VAR69;
assign VAR20 = (VAR32 ? VAR105 : 64'd0);
assign VAR74 = (VAR11 ? VAR151 : 0);
assign VAR105 = (VAR167 ? {{32{VAR82[31]}}, VAR82[31:0]} : VAR82);
assign VAR131 = {{52{VAR130[31]}}, VAR130[31:20]};
assign VAR54 = {{52{VAR130[31]}}, VAR130[31:25], VAR130[11:7]};
assign VAR128 = {{51{VAR130[31]}}, VAR130[31], VAR130[7], VAR130[30:25], VAR130[11:8], 1'b0};
assign VAR40 = {{32{VAR130[31]}}, VAR130[31:12], 12'd0};
assign VAR147 = {{43{VAR130[31]}}, VAR130[31], VAR130[19:12], VAR130[20], VAR130[30:21], 1'b0};
assign VAR122 = ~|{VAR59, VAR71, VAR73, VAR9};
assign VAR129 = ~|{VAR88, VAR47, VAR143, VAR142, VAR80, VAR169, VAR141};
assign VAR164 = (VAR73 ? VAR91 : 0) |
(VAR59 ? VAR151 : 0) |
(VAR9 ? VAR101 : 0) |
(VAR122 ? VAR121 : 0);
assign VAR87 =
(VAR88 ? VAR151 : 0) |
(VAR47 ? VAR131 : 0) |
(VAR143 ? VAR54 : 0) |
(VAR142 ? VAR128 : 0) |
(VAR80 ? VAR40 : 0) |
(VAR169 ? VAR147 : 0) |
(VAR141 ? VAR60 : 0) |
(VAR129 ? VAR155 : 0);
assign VAR97 = (VAR111 ? VAR105 : 0) |
(VAR53 ? VAR56 : 0) |
(VAR127 ? VAR101 : 0) |
(VAR94 ? VAR52 : 0);
assign VAR157 = (VAR39 ? VAR130[19:15] : 0) |
(VAR35 ? VAR130[24:20] : 0) |
(VAR84 ? VAR130[11:7] : 0); wire VAR124 = ~|{VAR156,VAR76,VAR86,VAR7,VAR22};
assign VAR81 = (VAR156 ? 64'hFFFFFFFFFFFFFF00 : 64'h0) |
(VAR76 ? VAR52 + 4 : 64'h0) |
(VAR86 ? VAR105 : 64'h0) |
(VAR7 ? VAR26 : 64'h0) |
(VAR22 ? VAR15 : 64'h0) |
(VAR124 ? VAR52 : 64'h0); wire VAR139 = ~VAR41;
assign VAR42 = (VAR41 ? VAR52 : 0) |
(VAR139 ? VAR91 : 0);
assign VAR58 = VAR125 ? VAR52 : 0;
wire VAR126 = ~VAR70;
assign VAR96 = (VAR70 ? VAR16 : 0) |
(VAR126 ? VAR130 : 0);
always @(posedge VAR67) begin
rst <= VAR38;
VAR52 <= VAR81;
VAR91 <= VAR42;
VAR165 <= VAR24;
VAR171 <= VAR163;
VAR104 <= VAR61;
VAR2 <= VAR168;
VAR34 <= VAR103;
VAR99 <= VAR119;
VAR130 <= VAR96;
VAR121 <= VAR164;
VAR155 <= VAR87;
VAR77 <= VAR57;
VAR93 <= VAR72;
end
VAR46 VAR28(
.VAR163(VAR163),
.VAR61(VAR61),
.VAR168(VAR168),
.VAR103(VAR103),
.VAR171(VAR171),
.VAR104(VAR104),
.VAR2(VAR2),
.VAR34(VAR34),
.VAR165(VAR165),
.VAR136(VAR136),
.VAR125(VAR125),
.VAR43(VAR43),
.VAR156(VAR156),
.VAR76(VAR76),
.VAR70(VAR70),
.VAR130(VAR130),
.VAR24(VAR24),
.VAR94(VAR94),
.VAR25(VAR25),
.VAR86(VAR86),
.VAR39(VAR39),
.VAR35(VAR35),
.VAR84(VAR84),
.VAR59(VAR59),
.VAR88(VAR88),
.VAR47(VAR47),
.VAR89(VAR89),
.VAR111(VAR111),
.VAR159(VAR159),
.VAR27(VAR27),
.VAR63(VAR63),
.VAR36(VAR36),
.VAR92(VAR92),
.VAR110(VAR110),
.VAR167(VAR167),
.VAR71(VAR71),
.VAR80(VAR80),
.VAR41(VAR41),
.VAR73(VAR73),
.VAR32(VAR32),
.VAR68(VAR68),
.VAR69(VAR69),
.VAR115(VAR115),
.VAR53(VAR53),
.VAR112(VAR112),
.VAR11(VAR11),
.VAR143(VAR143),
.VAR117(VAR117),
.VAR169(VAR169),
.VAR4(VAR4),
.VAR142(VAR142),
.VAR119(VAR119),
.VAR99(VAR99),
.VAR77(VAR77),
.VAR134(VAR134),
.VAR72(VAR72),
.VAR93(VAR93),
.VAR21(VAR21),
.VAR90(VAR90),
.VAR140(VAR140),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR22(VAR22),
.VAR5(VAR5),
.VAR138(VAR138),
.VAR123(VAR123),
.VAR3(VAR3),
.VAR65(VAR137),
.VAR127(VAR127),
.VAR152(VAR160),
.VAR173(VAR173),
.VAR6(VAR158),
.VAR45(VAR45),
.VAR51(VAR51),
.VAR141(VAR141),
.VAR9(VAR9),
.VAR113(VAR113),
.VAR153(VAR153),
.VAR162(VAR162),
.VAR148(VAR148),
.VAR78(VAR78),
.rst(rst)
);
VAR114 VAR114(
.VAR67(VAR67),
.VAR12(VAR157),
.VAR97(VAR97),
.VAR151(VAR151),
.VAR98({4{VAR89}})
);
alu alu(
.VAR17(VAR121),
.VAR8(VAR155),
.VAR110(VAR110),
.VAR102(VAR25),
.VAR135(VAR159),
.VAR118(VAR27),
.VAR44(VAR63),
.VAR33(VAR36),
.VAR37(VAR92),
.VAR150(VAR148),
.VAR145(VAR78),
.VAR133(VAR82),
.VAR144(VAR144),
.VAR116(VAR116),
.VAR1(VAR1)
);
VAR109 VAR62(
.VAR30(VAR149),
.VAR55(VAR14),
.VAR146(VAR95),
.VAR31(VAR146),
.VAR50(VAR152),
.VAR108(VAR6),
.VAR3(VAR3),
.VAR123(VAR123),
.VAR5(VAR5),
.VAR138(VAR138),
.VAR64(VAR26),
.VAR15(VAR15),
.VAR106(VAR106),
.VAR172(VAR172),
.VAR18(VAR165),
.VAR154(1'b0), .VAR21(VAR21),
.VAR90(VAR90),
.VAR140(VAR140),
.VAR10(VAR10),
.VAR153(VAR153),
.VAR132(VAR91),
.VAR48(VAR52),
.VAR19(VAR19),
.VAR13(VAR13),
.VAR66(VAR113),
.VAR79(VAR162),
.VAR38(VAR38),
.VAR67(VAR67)
);
endmodule | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbp/sky130_fd_sc_hd__dlxbp.blackbox.v | 1,327 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR6 ,
VAR8
);
output VAR7 ;
output VAR3 ;
input VAR6 ;
input VAR8;
supply1 VAR1;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_mult2_virtex4.v | 2,883 | module MODULE1(
input VAR30,
input VAR32,
input [12:0] VAR46,
input [12:0] VAR9,
output [25:0] VAR4
);
VAR37 #(
.VAR12(1), .VAR6(1), .VAR3("VAR15"), .VAR23(0), .VAR27(0), .VAR38(0), .VAR44("VAR43"), .VAR1(0), .VAR48(0), .VAR34(1), .VAR41(0) ) VAR42 (
.VAR45(), .VAR16(VAR4), .VAR36(), .VAR24(VAR46), .VAR31(VAR9), .VAR28(18'd0), .VAR14(48'd0), .VAR10(1'b0), .VAR26(2'd0), .VAR35(VAR32), .VAR11(VAR32), .VAR29(1'b1), .VAR2(1'b1), .VAR17(1'b1), .VAR33(1'b1), .VAR19(1'b1), .VAR20(VAR32), .VAR47(VAR30), .VAR5(7'h35), .VAR40(48'd0), .VAR21(1'b0), .VAR8(1'b0), .VAR13(1'b0), .VAR25(1'b0), .VAR18(1'b0), .VAR22(1'b0), .VAR7(1'b0), .VAR39(1'b0) );
endmodule | lgpl-3.0 |
gbraad/minimig-de1 | rtl/soc/minimig_de2_top.v | 25,024 | module MODULE1 (
input wire VAR118, input wire VAR314, input wire VAR58, input wire VAR150, input wire VAR238, input wire VAR199, output wire VAR49, input wire [ 4-1:0] VAR243, input wire [ 10-1:0] VAR380, output wire [ 7-1:0] VAR354, output wire [ 7-1:0] VAR20, output wire [ 7-1:0] VAR43, output wire [ 7-1:0] VAR177, output wire [ 8-1:0] VAR212, output wire [ 10-1:0] VAR322, output wire VAR309, input wire VAR102, inout wire VAR378, output wire VAR188, inout wire VAR196, inout wire VAR306, inout wire VAR80, inout wire VAR235, output wire VAR377, output wire VAR257, output wire [ 10-1:0] VAR232, output wire [ 10-1:0] VAR176, output wire [ 10-1:0] VAR329, output wire VAR223, output wire VAR45, output wire VAR66, inout wire VAR248, input wire VAR352, inout wire VAR37, output wire VAR74, inout wire VAR178, output wire VAR12, input wire VAR11, output wire VAR284, output wire VAR317, output wire VAR252, inout wire [ 16-1:0] VAR225, output wire [ 18-1:0] VAR25, output wire VAR41, output wire VAR40, output wire VAR231, output wire VAR152, output wire VAR281, inout wire [ 16-1:0] VAR91, output wire [ 12-1:0] VAR370, output wire VAR54, output wire VAR175, output wire VAR365, output wire VAR339, output wire VAR280, output wire VAR191, output wire VAR98, output wire VAR274, output wire VAR216, output wire VAR371, inout wire [ 8-1:0] VAR227, output wire [ 22-1:0] VAR29, output wire VAR202, output wire VAR184, output wire VAR337, output wire VAR123, input wire [ 6-1:0] VAR81, input wire [ 6-1:0] VAR286, output wire VAR83, output wire VAR71 );
wire VAR228;
wire VAR301;
wire VAR282;
wire VAR104;
wire VAR331;
wire VAR261;
wire VAR198;
wire VAR13;
wire VAR22;
wire VAR318;
wire [ 10-1:0] VAR4;
wire VAR273;
wire VAR250;
wire VAR206;
wire VAR207;
wire VAR373;
wire VAR163;
wire VAR293;
wire VAR62;
wire VAR265;
wire VAR78;
wire VAR209;
wire VAR136;
wire [ 22-1:0] VAR324;
wire VAR33;
wire VAR359;
wire [ 4-1:0] VAR341;
wire [ 32-1:0] VAR185;
wire [ 32-1:0] VAR326;
wire VAR170;
wire VAR316;
wire [ 22-1:0] VAR122;
wire VAR57;
wire VAR97;
wire [ 2-1:0] VAR200;
wire [ 16-1:0] VAR42;
wire [ 16-1:0] VAR240;
wire VAR343;
wire VAR19;
wire VAR246;
wire [ 16-1:0] VAR179;
wire [ 16-1:0] VAR173;
wire [ 32-1:0] VAR17;
wire [ 3-1:0] VAR255;
wire VAR47;
wire VAR321;
wire VAR55;
wire VAR108;
wire VAR109;
wire VAR292;
wire VAR368;
wire VAR110;
wire [ 16-1:0] VAR153;
wire VAR266;
wire [ 4-1:0] VAR208;
wire [ 6-1:0] VAR135;
wire VAR332;
wire [ 32-1:0] VAR119;
wire [ 6-1:0] VAR253;
wire VAR256;
wire VAR268;
wire VAR72;
wire [ 32-1:0] VAR269;
wire VAR44;
wire [ 16-1:0] VAR51; wire [ 16-1:0] VAR172; wire [ 22-1:1] VAR9; wire VAR164; wire VAR154; wire VAR219; wire VAR167; wire 15khz; wire VAR270; wire [ 15-1:0] VAR361; wire [ 15-1:0] VAR32; wire VAR186;
wire VAR138;
wire VAR171;
wire VAR86;
wire VAR325;
wire VAR73;
wire VAR296;
wire VAR204;
wire VAR121;
wire [ 24-1:0] VAR233;
wire VAR144;
wire [ 2-1:0] VAR187;
wire [ 16-1:0] VAR14;
wire [ 16-1:0] VAR79;
wire VAR149;
wire VAR353;
wire [ 4-1:0] VAR24;
wire [ 2-1:0] VAR366;
wire [ 2-1:0] VAR3;
wire VAR183;
wire VAR262;
wire [ 16-1:0] VAR68;
wire [ 16-1:0] VAR145;
wire [ 8-1:0] VAR36;
wire [ 8-1:0] VAR92;
wire [ 4-1:0] VAR194;
wire VAR197;
wire VAR142;
wire [ 4-1:0] VAR218;
wire [ 4-1:0] VAR350;
wire [ 4-1:0] VAR106;
wire [ 8-1:0] VAR334;
wire VAR120;
wire VAR264, VAR103, VAR363, VAR35, VAR229, VAR323, VAR242, VAR65, VAR190;
wire VAR312, VAR308, VAR28, VAR254;
VAR290 #(.VAR356(4)) VAR221 (
.clk (VAR282),
.VAR275 ({VAR380[9], VAR380[8], VAR380[7], VAR380[6]}),
.VAR210 ({VAR264, VAR103, VAR363, VAR35})
);
VAR290 #(.VAR356(4)) VAR132 (
.clk (VAR282),
.VAR275 ({VAR243[3], VAR243[2], VAR243[1], VAR243[0]}),
.VAR210 ({VAR312, VAR308, VAR28, VAR254})
);
VAR290 #(.VAR356(5)) VAR245 (
.clk (VAR273),
.VAR275 ({VAR380[5], VAR380[4], VAR380[3], VAR380[2], VAR380[1]}),
.VAR210 ({VAR229, VAR323, VAR242, VAR65, VAR190})
);
VAR290 #(.VAR356(4)) VAR155 (
.clk (VAR273),
.VAR275 ({VAR332, ~VAR246, VAR44, ~VAR353}),
.VAR210 (VAR106)
);
wire [3-1:0] VAR346;
VAR290 #(.VAR356(3)) VAR267 (
.clk (VAR282),
.VAR275 ({VAR380[3], VAR380[2], VAR380[1]}),
.VAR210 (VAR346)
);
assign VAR49 = 1'b1;
assign VAR120 = VAR229;
assign VAR309 = VAR120 ? VAR209 : VAR296;
assign VAR136 = VAR120 ? VAR102 : 1'b1;
assign VAR204 = VAR120 ? 1'b1 : VAR102;
assign VAR284 = VAR194[0];
assign VAR225 = VAR281 ? VAR68 : 16'VAR59;
assign VAR145 = VAR225;
assign VAR371 = 1'b1;
assign VAR216 = VAR104;
assign VAR191 = VAR24[0];
assign VAR54 = VAR366[0];
assign VAR175 = VAR366[1];
assign VAR98 = VAR3[0];
assign VAR274 = VAR3[1];
assign VAR227 = VAR337 ? VAR36 : 8'VAR203;
assign VAR92 = VAR227;
assign VAR83 = VAR186;
assign VAR71 = VAR138;
assign VAR83 = 1'b0;
assign VAR71 = 1'b0;
assign VAR197 = !VAR194[0] ? VAR11 : VAR270;
assign VAR142 = !VAR243[0];
assign VAR218 = {VAR323, VAR242, VAR65, VAR190};
assign VAR228 = VAR118;
assign VAR250 = !VAR380[0];
assign VAR206 = VAR331 & VAR380[0];
assign VAR183 = VAR363;
assign VAR262 = VAR35;
assign 15khz = VAR264;
assign VAR232[5:0] = {VAR232[9:6], VAR232[9:8]};
assign VAR176[5:0] = {VAR176[9:6], VAR176[9:8]};
assign VAR329[5:0] = {VAR329[9:6], VAR329[9:8]};
assign VAR45 = VAR377 && VAR257;
assign VAR223 = 0;
assign VAR66 = VAR282;
VAR38 VAR38 (
.VAR205 (VAR314 ), .VAR142 (VAR142 ), .VAR351 (VAR273 ), .VAR220 (VAR207 ), .VAR373 (VAR373 ), .VAR163 (VAR163 ), .VAR360 (1'b0 ), .VAR218 (VAR218 ), .VAR293 (VAR293 ), .VAR62 (VAR62 ), .VAR265 (VAR265 ), .VAR78 (VAR78 ), .VAR350 (VAR350 ), .VAR106 (VAR106 ), .VAR143 (VAR25 ), .VAR319 (VAR152 ), .VAR215 (VAR231 ), .VAR77 (VAR41 ), .VAR289 (VAR40 ), .VAR85 (VAR281 ), .VAR75 (VAR68 ), .VAR90 (VAR145 ), .VAR6 (VAR29 ), .VAR1 (VAR123 ), .VAR115 (VAR202 ), .VAR362 (VAR337 ), .VAR333 (VAR184 ), .VAR272 (VAR36 ), .VAR241 (VAR92 ), .VAR324 (VAR324 ),
.VAR33 (VAR33 ),
.VAR359 (VAR359 ),
.VAR341 (VAR341 ),
.VAR185 (VAR185 ),
.VAR326 (VAR326 ),
.VAR170 (VAR170 ),
.VAR316 (VAR316 ),
.VAR358 (VAR209 ), .VAR367 (VAR136 ), .VAR99 (VAR194 ), .VAR224 (VAR252 ), .VAR239 (VAR317 ), .VAR127 (VAR197 ) );
VAR87 #(
.VAR162 (22),
.VAR327 (4 ),
.VAR259 (32),
.VAR53 (22),
.VAR139 (2 ),
.VAR304 (16)
) VAR87 (
.VAR169 (VAR273 ),
.VAR230 (VAR324 ),
.VAR112 (VAR33 ),
.VAR60 (VAR359 ),
.VAR213 (VAR341 ),
.VAR300 (VAR185 ),
.VAR63 (VAR326 ),
.VAR335 (VAR170 ),
.VAR295 (VAR316 ),
.VAR147 (VAR261 ),
.VAR165 (VAR122 ),
.VAR76 (VAR57 ),
.VAR349 (VAR97 ),
.VAR299 (VAR200 ),
.VAR294 (VAR42 ),
.VAR18 (VAR240 ),
.VAR166 (VAR343 ),
.VAR133 (VAR19 )
);
assign VAR170 = 1'b1;
assign VAR316 = 1'b0;
assign VAR122 = 22'VAR236;
assign VAR57 = 1'b0;
assign VAR97 = 1'VAR156;
assign VAR200 = 2'VAR330;
assign VAR42 = 16'VAR134;
wire VAR124;
VAR88 VAR88(
.clk (VAR261 ),
.rst (~VAR331 ),
.VAR334 (VAR334 ),
.VAR114 (VAR171 ),
.VAR336 (VAR86 ),
.VAR313 (VAR325 ),
.VAR39 (VAR73 ),
.VAR287 ({VAR293, VAR62, VAR265, VAR78}),
.VAR350 (VAR350 ),
.VAR106 (VAR106 ),
.VAR124 (VAR124),
.VAR159 (VAR354 ),
.VAR125 (VAR20 ),
.VAR16 (VAR43 ),
.VAR30 (VAR177 ),
.VAR214 (VAR212 ),
.VAR161 (VAR322 )
);
VAR61 VAR61 (
.rst (VAR250 ), .VAR205 (VAR228 ), .VAR301 (VAR301 ), .VAR104 (VAR104 ), .VAR282 (VAR282 ), .VAR261 (VAR261 ), .VAR198 (VAR198 ), .VAR13 (VAR13 ), .VAR22 (VAR22 ), .VAR318 (VAR318 ), .VAR4 (VAR4 ), .VAR50 (VAR331 ) );
VAR347 VAR347 (
.clk (VAR282 ), .VAR311 (VAR353 ), .VAR251 (VAR183 ), .VAR160 (VAR262 ), .VAR32 (VAR32 ), .VAR361 (VAR361 ), .VAR283 (VAR178 ), .VAR302 (VAR37 ), .VAR340 (VAR74 ), .VAR297 (VAR12 ), .VAR21 (VAR188 ), .VAR247 (VAR378 ) );
VAR244 VAR372 (
.clk (VAR301 ),
.reset (VAR246 ),
.VAR174 (1'b1 ),
.VAR237 (VAR255 ),
.VAR278 (VAR47 ),
.VAR70 (1'b1 ),
.VAR180 (1'b1 ),
.addr (VAR17 ),
.VAR141 (VAR179 ),
.VAR364 (VAR173 ),
.VAR260 (VAR321 ),
.VAR27 (VAR55 ),
.VAR288 (VAR108 ),
.VAR217 (VAR109 ),
.VAR193 ( ),
.VAR338 ( ),
.VAR140 ( ),
.VAR285 (VAR292 ),
.VAR305 (VAR368 ),
.VAR181 (VAR110 ),
.VAR111 (VAR153 ),
.VAR26 (VAR266 ),
.VAR82 (VAR208[1:0] ),
.VAR135 (VAR135 ),
.VAR137 (VAR119 ),
.VAR182 (VAR253 ),
.VAR131 ( ),
.VAR291 ( ),
.VAR126 (VAR256 ),
.VAR249 (VAR268 ),
.VAR222 (VAR72 ),
.VAR192 (VAR269 )
);
VAR189 VAR113 (
.VAR303 (VAR301 ),
.VAR234 (VAR261 ),
.VAR158 (VAR206 ),
.VAR46 (VAR246 ),
.VAR353 (VAR353 ),
.VAR52 (VAR346[0] ),
.VAR48 (VAR370 ),
.VAR5 (VAR24 ),
.VAR89 (VAR3 ),
.VAR279 (VAR365 ),
.VAR310 (VAR280 ),
.VAR276 (VAR339 ),
.VAR101 (VAR366 ),
.VAR2 (VAR91 ),
.VAR121 (VAR57 ),
.VAR233 ({2'b00, VAR122}),
.VAR144 (VAR97 ),
.VAR187 (VAR200 ),
.VAR14 (VAR42 ),
.VAR79 (VAR240 ),
.VAR149 (VAR343 ),
.VAR348 ({2'b00, VAR9[21:1]}),
.VAR107 (VAR154 ),
.VAR271 (VAR164 ),
.VAR258 (VAR219 ),
.VAR345 (VAR167 ),
.VAR151 (VAR51 ),
.VAR315 (VAR172 ),
.VAR129 (VAR119[24:1] ),
.VAR182 (VAR253 ),
.VAR168 (VAR268 ),
.VAR226 (VAR72 ),
.VAR328 (VAR256 ),
.VAR130 (VAR173 ),
.VAR7 (VAR153 ),
.VAR181 (VAR110 ),
.VAR285 (VAR292 ),
.VAR305 (VAR368 ),
.VAR374 (VAR266 )
);
VAR355 VAR31 (
.VAR56 (VAR17[23:1] ), .VAR201 (VAR179 ), .VAR211 (VAR173 ), .VAR298 (VAR255 ), .VAR307 (VAR321 ), .VAR10 (VAR55 ), .VAR64 (VAR108 ), .VAR375 (VAR109 ), .VAR146 (VAR47 ), .VAR23 (VAR246 ), .VAR157 (VAR261 ), .VAR357 (VAR269 ), .VAR51 (VAR51 ), .VAR172 (VAR172 ), .VAR9 (VAR9[21:1]), .VAR164 (VAR164 ), .VAR154 (VAR154 ), .VAR219 (VAR219 ), .VAR167 (VAR167 ), .VAR142 (VAR373 ), .VAR220 (VAR44 ), .VAR8 (VAR282 ), .clk (VAR261 ), .VAR198 (VAR198 ), .VAR13 (VAR13 ), .VAR22 (VAR22 ), .VAR318 (VAR318 ), .VAR4 (VAR4 ), .VAR117 (VAR204 ), .VAR148 (VAR296 ), .VAR379 (1'b0 ), .VAR95 ( ), .VAR67 (VAR81 ), .VAR105 (VAR286 ), .VAR69 (VAR312 ), .VAR344 (VAR308 ), .15khz (15khz ), .VAR15 (VAR80 ), .VAR84 (VAR235 ), .VAR116 (VAR196 ), .VAR277 (VAR306 ), .VAR76 (VAR194[3:1] ), .VAR369 (VAR11 ), .VAR263 (VAR317 ), .VAR270 (VAR270 ), .VAR376 (VAR252 ), .VAR342 (VAR377 ), .VAR332 (VAR257 ), .VAR195 (VAR232[9:6] ), .VAR100 (VAR176[9:6] ), .VAR96 (VAR329[9:6] ), .VAR93 (VAR186 ), .VAR94 (VAR138 ), .VAR361 (VAR361 ), .VAR32 (VAR32 ), .VAR208 (VAR208 ), .VAR135 (VAR135 ), .VAR34 (VAR332 ), .VAR124 (VAR124 ),
.VAR320 (VAR334 ), .VAR128 ( ), .VAR171 (VAR171 ), .VAR86 (VAR86 ), .VAR325 (VAR325 ), .VAR73 (VAR73 ) );
endmodule | gpl-3.0 |
HarmonInstruments/verilog | sincos/sincos.v | 1,635 | module MODULE1 (input VAR18,
input [25:0] VAR12,
output signed [VAR1-1:0] VAR14, VAR11);
parameter VAR1 = 25;
parameter VAR10 = 1'b1;
reg [23:0] VAR9 = 0;
reg [23:0] VAR13 = 0;
reg VAR15 = 0;
reg VAR19 = 0;
wire [25:0] VAR4 = (VAR10 << (24)) + ~VAR12;
always @ (posedge VAR18) begin
VAR9 <= VAR12[24] ? ~ VAR12[23:0] : VAR12[23:0];
VAR13 <= VAR4[24] ? ~ VAR4[23:0] : VAR4[23:0];
VAR15 <= VAR12[25] ^ VAR12[24];
VAR19 <= VAR4[25] ^ VAR4[24];
end
wire [34:0] VAR16, VAR20;
VAR3 VAR3
(.VAR18(VAR18), .VAR9(VAR9[23:14]), .VAR13(VAR13[23:14]), .VAR8(VAR16), .VAR21(VAR20));
VAR5 #(.VAR17(VAR1)) VAR6
(.VAR18(VAR18), .VAR12(VAR9[13:0]), .VAR22(VAR16), .VAR7(VAR15), .VAR2(VAR14));
VAR5 #(.VAR17(VAR1)) VAR23
(.VAR18(VAR18), .VAR12(VAR13[13:0]), .VAR22(VAR20), .VAR7(VAR19), .VAR2(VAR11));
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3.functional.v | 1,759 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR7,
VAR5
);
output VAR9 ;
input VAR2 ;
input VAR7;
input VAR5;
wire VAR8 ;
wire VAR3;
not VAR4 (VAR8 , VAR2 );
VAR6 VAR1 (VAR3, VAR8, VAR7, VAR5);
buf VAR10 (VAR9 , VAR3 );
endmodule | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/altera_jtag_sld_node.v | 6,698 | module MODULE1 (
VAR73,
VAR40,
VAR78,
VAR54,
VAR61,
VAR77,
VAR6,
VAR25,
VAR27,
VAR45,
VAR4,
VAR37,
VAR55
);
parameter VAR52 = 20;
localparam VAR66 = (1000/VAR52)/2;
localparam VAR29 = 3;
input [VAR29 - 1:0] VAR73;
input VAR40;
output reg [VAR29 - 1:0] VAR78;
output VAR54;
output reg VAR61 = 1'b0;
output VAR77;
output VAR6;
output VAR25;
output VAR27;
output VAR45;
output VAR4;
output VAR37;
output VAR55;
reg VAR69;
reg VAR5;
reg VAR17;
reg VAR48;
reg VAR38;
reg VAR42;
reg [7:0] VAR3;
wire VAR14;
wire [VAR29 - 1:0] VAR1;
always @(VAR14)
VAR61 = VAR14;
always @(VAR1)
VAR78 = VAR1;
VAR74 VAR11 (
.VAR73 (VAR73),
.VAR40 (VAR40),
.VAR61 (VAR14),
.VAR54 (VAR54),
.VAR78 (VAR1),
.VAR6 (VAR6),
.VAR45 (VAR45),
.VAR55 (VAR55),
.VAR4 (VAR4),
.VAR77 (VAR77),
.VAR37 (VAR37),
.VAR25 (VAR25),
.VAR27 (VAR27)
,
.VAR28 (),
.VAR46 (),
.VAR34 (),
.VAR36 (),
.VAR31 (),
.VAR58 (),
.VAR64 (),
.VAR49 (),
.VAR50 (),
.VAR18 (),
.VAR67 (),
.VAR33 (),
.VAR26 (),
.VAR7 (),
.VAR57 (),
.VAR47 (),
.VAR56 ()
);
VAR11.VAR13 = 110,
VAR11.VAR65 = 132,
VAR11.VAR43 = 1,
VAR11.VAR30 = "VAR68",
VAR11.VAR24 = 0,
VAR11.VAR9 = VAR29,
VAR11.VAR59 = "",
VAR11.VAR72 = 0,
VAR11.VAR80 = 0;
localparam VAR63 = 0;
localparam VAR32 = 1;
localparam VAR23 = 2;
localparam VAR21 = 3;
localparam VAR35 = 4;
localparam VAR12 = 5;
always
assign VAR54 = VAR69;
assign VAR77 = VAR17;
assign VAR4 = VAR48;
assign VAR25 = VAR38;
assign VAR37 = VAR42;
task VAR79;
begin
VAR69 = 0;
VAR15;
VAR51;
end
endtask
task VAR15;
begin
VAR78 = VAR63;
VAR22;
end
endtask
task VAR53;
begin
VAR78 = VAR32;
VAR22;
end
endtask
task VAR44;
begin
VAR78 = VAR23;
VAR22;
end
endtask
task VAR8;
begin
VAR78 = VAR21;
VAR22;
end
endtask
task VAR2;
begin
VAR78 = VAR35;
VAR22;
end
endtask
task VAR20;
begin
VAR78 = VAR12;
VAR22;
end
endtask
task VAR16;
begin
{VAR5, VAR17, VAR48, VAR38, VAR42} = 5'b10000;
VAR61 = 1'b0;
@(posedge VAR54);
end
endtask
task VAR41;
begin
{VAR5, VAR17, VAR48, VAR38, VAR42} = 5'b01000;
VAR61 = 1'b0;
@(posedge VAR54);
end
endtask
task VAR19;
begin
{VAR5, VAR17, VAR48, VAR38, VAR42} = 5'b00010;
VAR61 = 1'b0;
@(posedge VAR54);
end
endtask
task VAR10;
begin
{VAR5, VAR17, VAR48, VAR38, VAR42} = 5'b00001;
VAR61 = 1'b0;
@(posedge VAR54);
end
endtask
task VAR22;
begin
VAR51;
@(posedge VAR54);
end
endtask
task VAR51;
begin
{VAR17, VAR48, VAR38, VAR42} = 4'b0000;
end
endtask
task VAR70;
input VAR75;
output reg VAR71;
begin
{VAR17, VAR48, VAR38, VAR42} = 4'b0100;
VAR61 = VAR75;
@(posedge VAR54);
VAR71 = VAR40;
end
endtask
task VAR76;
input [7:0] VAR62;
output reg [7:0] VAR60;
integer VAR39;
reg VAR71;
begin
for (VAR39=0; VAR39<8; VAR39=VAR39+1)
begin
VAR3 = VAR39;
VAR70(VAR62[VAR39], VAR71);
VAR60[VAR39] = VAR71;
end
end
endtask
endmodule | mit |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/Exponential/LUT_Z.v | 3,019 | module MODULE1#(parameter VAR6 = 32, parameter VAR4 = 5) (
input wire VAR2,
input wire VAR5,
input wire [VAR4-1:0] VAR3,
output reg [VAR6-1:0] VAR1
);
always @(posedge VAR2)
if (VAR5)
case (VAR3)
5'b00000: VAR1 <= 32'b10111111101011010101000010110010;
5'b00001: VAR1 <= 32'b10111111011110010001001110010101;
5'b00010: VAR1 <= 32'b10111111000011001001111101010100;
5'b00011: VAR1 <= 32'b10111110100000101100010101111000;
5'b00100: VAR1 <= 32'b10111110000000001010110001001001;
5'b00101: VAR1 <= 32'b10111101100000000010101011000100;
5'b00110: VAR1 <= 32'b10111101100000000010101011000100;
5'b00111: VAR1 <= 32'b10111101000000000000101010101100;
5'b01000: VAR1 <= 32'b10111100100000000000001010101010;
5'b01001: VAR1 <= 32'b10111100000000000000000010101100;
5'b01010: VAR1 <= 32'b10111011100000000000000000101011;
5'b01011: VAR1 <= 32'b10111010110111100011010100111011;
5'b01100: VAR1 <= 32'b10111010011111111111111111110111;
5'b01101: VAR1 <= 32'b10111010000000000000000000000011;
5'b01110: VAR1 <= 32'b10111001011111111111111111010101;
5'b01111: VAR1 <= 32'b10111000111111111111111111010101;
5'b10000: VAR1 <= 32'b10111000111111111111111111010101;
5'b10001: VAR1 <= 32'b10111000100000000000000000000000;
5'b10010: VAR1 <= 32'b10111000100000000000001010011010;
5'b10011: VAR1 <= 32'b10111000100000000000001010011010;
5'b10100: VAR1 <= 32'b10111000000000000000001010011010;
5'b10101: VAR1 <= 32'b10110111100000000000001010011010;
5'b10110: VAR1 <= 32'b10110111100000000000001010011010;
5'b10111: VAR1 <= 32'b10110111000000000000001010011010;
5'b11000: VAR1 <= 32'b10110110011111111010111101001101;
5'b11001: VAR1 <= 32'b10110110011111111010111101001101;
5'b11010: VAR1 <= 32'b10110100000000000000000000000000;
5'b11011: VAR1 <= 32'b10110011100000000000000000000000;
5'b11100: VAR1 <= 32'b10110011000000000000000000000000;
5'b11101: VAR1 <= 32'b10110010100000000000000000000000;
5'b11110: VAR1 <= 32'b10110010000000000000000000000000;
5'b11111: VAR1 <= 32'b10110001100000000000000000000000;
default: VAR1 <= 32'b00000000000000000000000000000000;
endcase
else
VAR1 <= 32'b00000000000000000000000000000000;
endmodule | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/verilog/FIFO_image_filter_img_0_rows_V_channel.v | 3,019 | module MODULE1 (
clk,
VAR22,
VAR19,
VAR18,
VAR24);
parameter VAR9 = 32'd12;
parameter VAR13 = 32'd2;
parameter VAR23 = 32'd3;
input clk;
input [VAR9-1:0] VAR22;
input VAR19;
input [VAR13-1:0] VAR18;
output [VAR9-1:0] VAR24;
reg[VAR9-1:0] VAR10 [0:VAR23-1];
integer VAR25;
always @ (posedge clk)
begin
if (VAR19)
begin
for (VAR25=0;VAR25<VAR23-1;VAR25=VAR25+1)
VAR10[VAR25+1] <= VAR10[VAR25];
VAR10[0] <= VAR22;
end
end
assign VAR24 = VAR10[VAR18];
endmodule
module MODULE2 (
clk,
reset,
VAR14,
VAR17,
VAR1,
VAR6,
VAR5,
VAR8,
VAR20,
VAR2);
parameter VAR12 = "VAR26";
parameter VAR9 = 32'd12;
parameter VAR13 = 32'd2;
parameter VAR23 = 32'd3;
input clk;
input reset;
output VAR14;
input VAR17;
input VAR1;
output[VAR9 - 1:0] VAR6;
output VAR5;
input VAR8;
input VAR20;
input[VAR9 - 1:0] VAR2;
wire[VAR13 - 1:0] VAR4 ;
wire[VAR9 - 1:0] VAR15, VAR21;
reg[VAR13:0] VAR7 = {(VAR13+1){1'b1}};
reg VAR16 = 0, VAR3 = 1;
assign VAR14 = VAR16;
assign VAR5 = VAR3;
assign VAR15 = VAR2;
assign VAR6 = VAR21;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR7 <= ~{VAR13+1{1'b0}};
VAR16 <= 1'b0;
VAR3 <= 1'b1;
end
else begin
if (((VAR1 & VAR17) == 1 & VAR16 == 1) &&
((VAR20 & VAR8) == 0 | VAR3 == 0))
begin
VAR7 <= VAR7 -1;
if (VAR7 == 0)
VAR16 <= 1'b0;
VAR3 <= 1'b1;
end
else if (((VAR1 & VAR17) == 0 | VAR16 == 0) &&
((VAR20 & VAR8) == 1 & VAR3 == 1))
begin
VAR7 <= VAR7 +1;
VAR16 <= 1'b1;
if (VAR7 == VAR23-2)
VAR3 <= 1'b0;
end
end
end
assign VAR4 = VAR7[VAR13] == 1'b0 ? VAR7[VAR13-1:0]:{VAR13{1'b0}};
assign VAR27 = (VAR20 & VAR8) & VAR3;
MODULE1
.VAR9(VAR9),
.VAR13(VAR13),
.VAR23(VAR23))
VAR11 (
.clk(clk),
.VAR22(VAR15),
.VAR19(VAR27),
.VAR18(VAR4),
.VAR24(VAR21));
endmodule | gpl-3.0 |
Elphel/x393_sata | ahci/ahci_dma_rd_fifo.v | 12,103 | module MODULE1#(
parameter VAR31 = 21,
parameter VAR40 = 3
)(
input VAR58,
input VAR46,
input VAR24,
input VAR47,
input [VAR31-1:0] VAR42, input [1:0] VAR65, input VAR21, input [63:0] din,
input VAR50,
input VAR19,
input VAR26, output VAR27,
output reg VAR66, output VAR49, output [31:0] dout,
output VAR25,
input VAR69,
output VAR60 ,output [31:0] VAR5
);
localparam VAR53 = (1<<VAR40); reg [VAR40 : 0] VAR55; reg [VAR40+1:0] VAR4; wire [VAR40+1:0] VAR37; reg [63:16] VAR64; reg [VAR31-3:0] VAR28;
reg VAR48;
wire [2:0] VAR10 = VAR42[1:0] + VAR65;
reg [63:0] VAR2 [0: VAR53 - 1];
reg [3:0] VAR68 [0: VAR53 - 1];
reg [(1<<VAR40)-1:0] VAR56; reg [(1<<VAR40)-1:0] VAR12; wire VAR51;
wire VAR36;
reg [1:0] VAR7;
reg VAR16;
wire [(1<<VAR40)-1:0] VAR32 = {~VAR56[0],VAR56[VAR53-1:1]};
reg VAR45; wire VAR30;
reg VAR22;
reg VAR39; reg [1:0] VAR13;
wire [63:0] VAR1= VAR13[1]?(VAR13[0] ? {din[47:0],VAR64[63:48]} : {din[31:0],VAR64[63:32]}):
(VAR13[0] ? {din[15:0],VAR64[63:16]} : din[63:0]);
wire [3:0] VAR8;
reg [63:0] VAR35;
reg [3:0] VAR17;
reg VAR15;
reg VAR34;
reg [3:0] VAR54;
wire VAR9;
reg VAR59; reg VAR43;
wire VAR41;
assign VAR27 = VAR48 && VAR39 && VAR15;
assign VAR51 = VAR34 && VAR39 && (VAR15 || !VAR48);
assign VAR8 = VAR41? VAR54 : 4'hf;
wire [2:0] VAR18 = VAR55[2:0];
wire [2:0] VAR11 = VAR4[3:1];
wire [VAR40+1:0] VAR29 = VAR4;
wire [63:0] VAR71 = VAR35;
wire [3:0] VAR20 = VAR17;
assign VAR30 = VAR32[VAR37[VAR40:1]] ^ VAR37[VAR40+1];
assign VAR41 = !VAR48 || ((VAR28 == 0) && ((VAR65 == 0) || VAR10[2]));
always @ (posedge VAR47) begin
if (VAR46) VAR16 <= 0;
end
else VAR16 <= VAR58;
if (VAR16) VAR48 <= 0;
else if (VAR21) VAR48 <= 1;
else if (VAR27 && (VAR28 == 0)) VAR48 <= 0;
VAR66 <= VAR48 && VAR27 && (VAR28 == 0);
if (VAR16) VAR34 <= 0;
else if (VAR21) VAR34 <= (VAR65 == 0);
else if (VAR27 || VAR51) VAR34 <= VAR48 && ((VAR28 != 0) || ((VAR65 != 0) && !VAR10[2]));
if (VAR21) VAR28 <= VAR42[VAR31-1:2] + VAR10[2];
else if (VAR27) VAR28 <= VAR28 - 1;
if (VAR21) VAR13 <= VAR65;
if (VAR16) VAR56 <= 0;
else if (VAR51) VAR56 <= {VAR56[VAR53-2:0],~VAR55[VAR40]};
if (VAR16) VAR55 <= 0;
else if (VAR51) VAR55 <= VAR55+1;
VAR39 <= VAR12 [VAR55[VAR40-1:0]] ^ VAR55[VAR40];
if (VAR27) VAR64[63:16] <= din[63:16];
if (VAR51) VAR2[VAR55[VAR40-1:0]] <= VAR1;
if (VAR51) VAR68 [VAR55[VAR40-1:0]] <= VAR8;
if (VAR16) VAR15 <= 0;
else VAR15 <= VAR50 && (VAR19 || !VAR27);
if (VAR21) VAR54 <= {&VAR42[1:0], VAR42[1], |VAR42[1:0], 1'b1};
if (VAR16 || VAR49) VAR59 <= 0;
else if (VAR51 && VAR26 && (((VAR28 == 0) && ((VAR65 == 0) || !VAR26)) || !VAR48)) VAR59 <= 1;
end
assign VAR37 = VAR58 ? 0 : (VAR4 + VAR36);
always @ (posedge VAR24) begin
VAR7 <= {VAR7[0],VAR36};
VAR4 <= VAR37;
end
if (VAR58) VAR12 <= {{(VAR53>>1){1'b0}},{(VAR53>>1){1'b1}}}; else if (VAR36 && VAR4[0]) VAR12 <= {VAR12[VAR53-2:0], ~VAR4[VAR40+1] ^ VAR4[VAR40]};
VAR45 <= VAR56 [VAR37[VAR40:1]] ^ VAR37[VAR40+1];
VAR22 <= VAR30;
if (VAR58) VAR43 <= 0;
else VAR43 <= VAR59;
VAR35 <= VAR2 [VAR37[VAR40:1]];
VAR17 <= VAR68 [VAR37[VAR40:1]];
end
VAR44 VAR70 (
.rst (VAR58), .clk (VAR24), .VAR50 (VAR45), .VAR62(VAR30), .VAR6 (VAR22), .VAR61 (VAR43), .din (VAR4[0]?VAR35[63:32]: VAR35[31:0]), .VAR14 (VAR4[0]?VAR17[3:2]:VAR17[1:0]), .VAR27 (VAR36), .VAR3 (VAR9), .dout (dout), .VAR25 (VAR25), .VAR69 (VAR69), .VAR60 (VAR60) );
VAR33 #(
.VAR57(0)
) VAR23 (
.rst (VAR58), .VAR52 (VAR24), .VAR63 (VAR47), .VAR38 (VAR9), .VAR67 (VAR49), .VAR48() );
assign VAR5 = {
14'b0,
VAR36,
VAR4[4:0],
VAR17[3:0],
VAR45,
VAR30,
VAR22,
VAR43,
VAR9,
VAR25,
VAR69,
VAR60
};
endmodule | gpl-3.0 |
HFoxtail/Mu80 | trunk/ram.v | 2,745 | module MODULE1 (VAR53, VAR26, VAR12, VAR27, VAR13, VAR39, VAR54);
input VAR12;
input [13:0] VAR26;
input [7:0] VAR27;
input VAR13;
input [13:0] VAR53;
output [7:0] VAR39;
output [7:0] VAR54;
tri1 VAR12;
tri0 VAR24;
tri0 VAR68;
wire [7:0] VAR42;
wire [7:0] VAR35;
wire [7:0] VAR39 = VAR42[7:0];
wire [7:0] VAR54 = VAR35[7:0];
VAR41 VAR33 (
.VAR17 (VAR12),
.VAR24 (1'b0),
.VAR68 (VAR13),
.VAR65 (VAR53),
.VAR72 (VAR26),
.VAR45 (16'h0),
.VAR59 (VAR27),
.VAR43 (VAR42),
.VAR40 (VAR35),
.VAR71 (1'b0),
.VAR7 (1'b0),
.VAR4 (1'b0),
.VAR20 (1'b0),
.VAR10 (1'b1),
.VAR9 (1'b1),
.VAR38 (1'b1),
.VAR55 (1'b1),
.VAR36 (1'b1),
.VAR51 (1'b1),
.VAR16 (1'b1),
.VAR63 (),
.VAR8 (1'b1),
.VAR73 (1'b1));
VAR33.VAR11 = "VAR56",
VAR33.VAR70 = "VAR19",
VAR33.VAR66 = "VAR19",
VAR33.VAR25 = "VAR19",
VAR33.VAR48 = "VAR19",
VAR33.VAR32 = "VAR56",
VAR33.VAR31 = "MODULE1.VAR21",
VAR33.VAR28 = "VAR52 VAR69",
VAR33.VAR49 = "VAR41",
VAR33.VAR50 = 16384,
VAR33.VAR15 = 16384,
VAR33.VAR14 = "VAR29",
VAR33.VAR34 = "VAR30",
VAR33.VAR44 = "VAR30",
VAR33.VAR67 = "VAR56",
VAR33.VAR62 = "VAR56",
VAR33.VAR6 = "VAR2",
VAR33.VAR47 = "VAR61",
VAR33.VAR64 = "VAR5",
VAR33.VAR1 = "VAR60",
VAR33.VAR58 = "VAR60",
VAR33.VAR57 = 14,
VAR33.VAR18 = 14,
VAR33.VAR46 = 8,
VAR33.VAR3 = 8,
VAR33.VAR22 = 1,
VAR33.VAR37 = 1,
VAR33.VAR23 = "VAR56";
endmodule | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_sgb/msu.v | 5,556 | module MODULE1(
input VAR35,
input enable,
input [13:0] VAR28,
input [7:0] VAR7,
input VAR5,
input [2:0] VAR15,
input [7:0] VAR16,
output [7:0] VAR8,
input VAR41,
input VAR43,
input VAR23,
output [7:0] VAR11,
output [7:0] VAR45,
output VAR37,
output [31:0] VAR17,
output [15:0] VAR10,
input [5:0] VAR22,
input [5:0] VAR40,
input VAR20,
input [13:0] VAR12,
input VAR6,
output VAR1,
output VAR32,
output VAR4,
output [13:0] VAR44,
output VAR2
);
reg [1:0] VAR36;
always @(posedge VAR35) VAR36 = {VAR36[0], VAR20};
wire VAR33 = (VAR36 == 2'b01);
reg [13:0] VAR42;
wire [13:0] VAR13 = VAR42;
VAR27 VAR42 = 13'b0;
wire [7:0] VAR46;
reg [7:0] VAR18;
reg [2:0] VAR25;
always @(posedge VAR35)
VAR25 <= {VAR25[1:0], VAR6};
wire VAR9 = (VAR25[2:1] == 2'b01);
reg [31:0] VAR24;
assign VAR17 = VAR24;
reg [15:0] VAR31;
assign VAR10 = VAR31;
reg [7:0] VAR21;
assign VAR45 = VAR21;
reg VAR19;
assign VAR37 = VAR19;
reg VAR3;
reg VAR26;
reg VAR39;
reg VAR30;
reg VAR34;
reg VAR14;
reg [2:0] VAR29;
reg [1:0] VAR38; | gpl-2.0 |
DreamIP/GPStudio | support/process/gradient/hdl/matrix_prod.v | 3,861 | module MODULE1(
VAR15,
VAR7,
VAR14,
VAR16,
VAR21,
VAR13,
VAR6,
VAR9,
VAR19,
VAR10,
VAR11,
VAR5,
VAR3
);
parameter VAR8 = 8;
parameter VAR2 = 9;
input VAR15;
input VAR7;
input VAR10;
input VAR11;
input VAR5;
input VAR14;
input [VAR8-1:0] VAR16, VAR21, VAR13, VAR6;
input [VAR2-1:0] VAR9;
input [VAR2-1:0] VAR19;
output [((VAR2 + VAR8)+1):0] VAR3;
reg signed [VAR8:0] VAR17;
reg signed [VAR8:0] VAR18;
reg signed [(VAR2 + VAR8):0] VAR22;
reg signed [(VAR2 + VAR8):0] VAR1;
reg signed [((VAR2 + VAR8)+1):0] VAR20;
wire signed [VAR2-1:0] VAR12;
wire signed [VAR2-1:0] VAR4;
always@(posedge VAR15 or negedge VAR7)
if (VAR7 == 0)
VAR17 <= {(VAR8+1){1'b0}};
else if (VAR10)
VAR17 <= VAR6 - VAR16;
else
VAR17 <= VAR17;
always@(posedge VAR15 or negedge VAR7)
if (VAR7 == 0)
VAR18 <= {(VAR8+1){1'b0}};
else if (VAR10)
VAR18 <= VAR21 - VAR13;
else
VAR18 <= VAR18;
assign VAR12 = VAR9;
assign VAR4 = VAR19;
always@(posedge VAR15 or negedge VAR7)
if (VAR7 == 0)
begin
VAR22 <= {(VAR2 + VAR8 + 1){1'b0}};
VAR1 <= {(VAR2 + VAR8 + 1){1'b0}};
end
else if (VAR11)
begin
VAR22 <= VAR17 * VAR12;
VAR1 <= VAR18 * VAR4;
end
always@(posedge VAR15 or negedge VAR7)
if (VAR7 == 0)
begin
VAR20 <= {((VAR2 + VAR8)+2){1'b0}};
end
else if (VAR5)
begin
VAR20 <= VAR22 + VAR1;
end
assign VAR3 = (VAR20 > 0) ? VAR20 : (~VAR20 + 1'b1);
endmodule | gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/amba_bfm/bfm_ahbslaveext.v | 40,413 | module
MODULE1
(
VAR101
,
VAR133
,
VAR182
,
VAR83
,
VAR93
,
VAR185
,
VAR173
,
VAR267
,
VAR188
,
VAR177
,
VAR255
,
VAR160
,
VAR152
,
VAR59
,
VAR74
,
VAR54
,
VAR159
,
VAR86
,
VAR171
,
VAR11
,
VAR14
,
VAR96
)
;
parameter
VAR79
=
10
;
parameter
VAR229
=
256
;
parameter
VAR113
=
2
;
parameter
VAR281
=
" "
;
parameter
VAR163
=
0
;
parameter
VAR170
=
0
;
parameter
VAR228
=
0
;
parameter
VAR38
=
1
;
parameter
VAR68
=
-
1
;
localparam
VAR176
=
22
;
localparam
VAR211
=
0
;
localparam
VAR271
=
4
;
localparam
VAR261
=
8
;
localparam
VAR161
=
12
;
localparam
VAR144
=
16
;
localparam
VAR81
=
20
;
localparam
VAR65
=
24
;
localparam
VAR155
=
28
;
localparam
VAR128
=
32
;
localparam
VAR226
=
36
;
localparam
VAR216
=
40
;
localparam
VAR264
=
44
;
localparam
VAR43
=
48
;
localparam
VAR114
=
52
;
localparam
VAR66
=
56
;
localparam
VAR5
=
60
;
localparam
VAR164
=
64
;
localparam
VAR45
=
68
;
localparam
VAR70
=
72
;
localparam
VAR269
=
76
;
localparam
VAR44
=
80
;
localparam
VAR27
=
100
;
localparam
VAR283
=
101
;
localparam
VAR32
=
102
;
localparam
VAR125
=
103
;
localparam
VAR287
=
104
;
localparam
VAR67
=
105
;
localparam
VAR10
=
106
;
localparam
VAR95
=
107
;
localparam
VAR166
=
108
;
localparam
VAR153
=
109
;
localparam
VAR276
=
110
;
localparam
VAR225
=
111
;
localparam
VAR69
=
112
;
localparam
VAR273
=
113
;
localparam
VAR172
=
114
;
localparam
VAR88
=
115
;
localparam
VAR180
=
128
;
localparam
VAR183
=
129
;
localparam
VAR3
=
130
;
localparam
VAR274
=
131
;
localparam
VAR24
=
132
;
localparam
VAR272
=
133
;
localparam
VAR181
=
134
;
localparam
VAR102
=
135
;
localparam
VAR230
=
136
;
localparam
VAR58
=
137
;
localparam
VAR100
=
138
;
localparam
VAR174
=
139
;
localparam
VAR98
=
140
;
localparam
VAR115
=
141
;
localparam
VAR218
=
142
;
localparam
VAR169
=
150
;
localparam
VAR145
=
151
;
localparam
VAR138
=
152
;
localparam
VAR107
=
153
;
localparam
VAR127
=
154
;
localparam
VAR199
=
160
;
localparam
VAR186
=
161
;
localparam
VAR202
=
162
;
localparam
VAR280
=
163
;
localparam
VAR108
=
164
;
localparam
VAR175
=
165
;
localparam
VAR112
=
166
;
localparam
VAR25
=
167
;
localparam
VAR142
=
168
;
localparam
VAR219
=
169
;
localparam
VAR42
=
170
;
localparam
VAR120
=
171
;
localparam
VAR23
=
172
;
localparam
VAR205
=
200
;
localparam
VAR195
=
201
;
localparam
VAR184
=
202
;
localparam
VAR204
=
203
;
localparam
VAR250
=
204
;
localparam
VAR239
=
205
;
localparam
VAR243
=
206
;
localparam
VAR262
=
207
;
localparam
VAR84
=
208
;
localparam
VAR80
=
209
;
localparam
VAR110
=
210
;
localparam
VAR104
=
211
;
localparam
VAR249
=
212
;
localparam
VAR187
=
213
;
localparam
VAR222
=
214
;
localparam
VAR192
=
215
;
localparam
VAR52
=
216
;
localparam
VAR209
=
217
;
localparam
VAR1
=
218
;
localparam
VAR119
=
219
;
localparam
VAR39
=
220
;
localparam
VAR196
=
221
;
localparam
VAR139
=
222
;
localparam
VAR60
=
250
;
localparam
VAR279
=
251
;
localparam
VAR53
=
252
;
localparam
VAR103
=
253
;
localparam
VAR2
=
254
;
localparam
VAR92
=
255
;
localparam
VAR263
=
1001
;
localparam
VAR116
=
1002
;
localparam
VAR118
=
1003
;
localparam
VAR214
=
1004
;
localparam
VAR259
=
1005
;
localparam
VAR20
=
1006
;
localparam
VAR130
=
1007
;
localparam
VAR156
=
1008
;
localparam
VAR55
=
1009
;
localparam
VAR234
=
1010
;
localparam
VAR158
=
1011
;
localparam
VAR22
=
1012
;
localparam
VAR238
=
1013
;
localparam
VAR149
=
1014
;
localparam
VAR6
=
1015
;
localparam
VAR240
=
1016
;
localparam
VAR141
=
1017
;
localparam
VAR251
=
1018
;
localparam
VAR62
=
1019
;
localparam
VAR278
=
1020
;
localparam
VAR33
=
1021
;
localparam
VAR122
=
1022
;
localparam
VAR36
=
1023
;
localparam
VAR48
=
0
;
localparam
VAR235
=
1
;
localparam
VAR132
=
2
;
localparam
VAR105
=
3
;
localparam
VAR71
=
4
;
localparam
VAR90
=
5
;
localparam
VAR256
=
6
;
localparam
VAR213
=
7
;
localparam
VAR109
=
8
;
localparam
VAR254
=
0
;
localparam
VAR117
=
1
;
localparam
VAR215
=
2
;
localparam
VAR4
=
3
;
localparam
VAR220
=
4
;
localparam
VAR34
=
32
'VAR207
00000000
;
localparam
VAR197
=
32
'VAR207
00002000
;
localparam
VAR206
=
32
'VAR207
00004000
;
localparam
VAR257
=
32
'VAR207
00006000
;
localparam
VAR210
=
32
'VAR207
00008000
;
localparam
[
1
:
0
]
VAR236
=
0
;
localparam
[
1
:
0
]
VAR8
=
1
;
localparam
[
1
:
0
]
VAR12
=
2
;
localparam
[
1
:
0
]
VAR201
=
3
;
function
integer
VAR233
;
input
[
31
:
0
]
VAR64
;
integer
VAR201
;
begin
VAR201
=
VAR64
;
VAR233
=
VAR201
;
end
endfunction
function
integer
VAR258
;
input
[
31
:
0
]
VAR64
;
integer
VAR64
;
integer
VAR201
;
begin
VAR201
=
VAR64
;
VAR258
=
VAR201
;
end
endfunction
function
integer
VAR85
;
input
[
31
:
0
]
VAR64
;
integer
VAR201
;
begin
VAR201
=
VAR64
;
VAR85
=
VAR201
;
end
endfunction
function
[
31
:
0
]
VAR97
;
input
VAR201
;
integer
VAR201
;
reg
[
31
:
0
]
VAR64
;
begin
VAR64
=
VAR201
;
VAR97
=
VAR64
;
end
endfunction
function
[
31
:
0
]
VAR241
;
input
[
2
:
0
]
VAR140
;
input
[
1
:
0
]
VAR37
;
input
[
31
:
0
]
VAR89
;
input
VAR162
;
integer
VAR162
;
reg
[
31
:
0
]
VAR217
;
reg
VAR73
;
begin
VAR217
=
{
32
{
1
'VAR26
0
}
}
;
case
(
VAR162
)
0
:
begin
case
(
VAR140
)
3
'VAR26
000
:
begin
case
(
VAR37
)
2
'VAR26
00
:
begin
VAR217
[
7
:
0
]
=
VAR89
[
7
:
0
]
;
end
2
'VAR26
01
:
begin
VAR217
[
15
:
8
]
=
VAR89
[
7
:
0
]
;
end
2
'VAR26
10
:
begin
VAR217
[
23
:
16
]
=
VAR89
[
7
:
0
]
;
end
2
'VAR26
11
:
begin
VAR217
[
31
:
24
]
=
VAR89
[
7
:
0
]
;
end
default
:
begin
end
endcase
end
3
'VAR26
001
:
begin
case
(
VAR37
)
2
'VAR26
00
:
begin
VAR217
[
15
:
0
]
=
VAR89
[
15
:
0
]
;
end
2
'VAR26
01
:
begin
VAR217
[
15
:
0
]
=
VAR89
[
15
:
0
]
;
VAR227
(
"VAR208: VAR49 VAR203 VAR194(VAR268 VAR237=01) ? (VAR260)"
)
;
end
2
'VAR26
10
:
begin
VAR217
[
31
:
16
]
=
VAR89
[
15
:
0
]
;
end
2
'VAR26
11
:
begin
VAR217
[
31
:
16
]
=
VAR89
[
15
:
0
]
;
VAR227
(
"VAR208: VAR49 VAR203 VAR194(VAR268 VAR237=11) ? (VAR260)"
)
;
end
default
:
begin
end
endcase
end
3
'VAR26
010
:
begin
VAR217
=
VAR89
;
case
(
VAR37
)
2
'VAR26
00
:
begin
end
2
'VAR26
01
:
begin
VAR227
(
"VAR208: VAR49 VAR203 VAR194(VAR16 VAR237=01) ? (VAR260)"
)
;
end
2
'VAR26
10
:
begin
VAR227
(
"VAR208: VAR49 VAR203 VAR194(VAR16 VAR237=10) ? (VAR260)"
)
;
end
2
'VAR26
11
:
begin
VAR227
(
"VAR208: VAR49 VAR203 VAR194(VAR16 VAR237=11) ? (VAR260)"
)
;
end
default
:
begin
end
endcase
end
default
:
begin
VAR227
(
"VAR157 VAR203 VAR40 VAR135 (VAR167)"
)
;
end
endcase
end
1
:
begin
case
(
VAR140
)
3
'VAR26
000
:
begin
case
(
VAR37
)
2
'VAR26
00
:
begin
VAR217
[
7
:
0
]
=
VAR89
[
7
:
0
]
;
end
2
'VAR26
01
:
begin
VAR217
[
15
:
8
]
=
VAR89
[
7
:
0
]
;
end
2
'VAR26
10
:
begin
VAR217
[
7
:
0
]
=
VAR89
[
7
:
0
]
;
end
2
'VAR26
11
:
begin
VAR217
[
15
:
8
]
=
VAR89
[
7
:
0
]
;
end
default
:
begin
end
endcase
end
3
'VAR26
001
:
begin
VAR217
[
15
:
0
]
=
VAR89
[
15
:
0
]
;
case
(
VAR37
)
2
'VAR26
00
:
begin
end
2
'VAR26
01
:
begin
VAR227
(
"VAR208: VAR49 VAR203 VAR194(VAR268 VAR237=01) ? (VAR260)"
)
;
end
2
'VAR26
10
:
begin
VAR227
(
"VAR208: VAR49 VAR203 VAR194(VAR268 VAR237=10) ? (VAR260)"
)
;
end
2
'VAR26
11
:
begin
VAR227
(
"VAR208: VAR49 VAR203 VAR194(VAR268 VAR237=11) ? (VAR260)"
)
;
end
default
:
begin
end
endcase
end
default
:
begin
VAR227
(
"VAR157 VAR203 VAR40 VAR135 (VAR167)"
)
;
end
endcase
end
2
:
begin
case
(
VAR140
)
3
'VAR26
000
:
begin
VAR217
[
7
:
0
]
=
VAR89
[
7
:
0
]
;
end
default
:
begin
VAR227
(
"VAR157 VAR203 VAR40 VAR135 (VAR167)"
)
;
end
endcase
end
8
:
begin
VAR217
=
VAR89
;
end
default
:
begin
VAR227
(
"VAR231 VAR165 VAR282 (VAR167)"
)
;
end
endcase
VAR241
=
VAR217
;
end
endfunction
function
[
31
:
0
]
VAR266
;
input
[
2
:
0
]
VAR140
;
input
[
1
:
0
]
VAR37
;
input
[
31
:
0
]
VAR89
;
input
VAR162
;
integer
VAR162
;
reg
[
31
:
0
]
VAR217
;
begin
VAR217
=
VAR241
(
VAR140
,
VAR37
,
VAR89
,
VAR162
)
;
VAR266
=
VAR217
;
end
endfunction
function
[
31
:
0
]
VAR168
;
input
[
2
:
0
]
VAR140
;
input
[
1
:
0
]
VAR37
;
input
[
31
:
0
]
VAR89
;
input
VAR162
;
integer
VAR162
;
reg
[
31
:
0
]
VAR217
;
reg
VAR73
;
begin
if
(
VAR162
==
8
)
begin
VAR217
=
VAR89
;
end
else
begin
VAR217
=
0
;
VAR73
=
VAR37
[
1
]
;
case
(
VAR140
)
3
'VAR26
000
:
begin
case
(
VAR37
)
2
'VAR26
00
:
VAR217
[
7
:
0
]
=
VAR89
[
7
:
0
]
;
2
'VAR26
01
:
VAR217
[
7
:
0
]
=
VAR89
[
15
:
8
]
;
2
'VAR26
10
:
VAR217
[
7
:
0
]
=
VAR89
[
23
:
16
]
;
2
'VAR26
11
:
VAR217
[
7
:
0
]
=
VAR89
[
31
:
24
]
;
default
:
begin
end
endcase
end
3
'VAR26
001
:
begin
case
(
VAR73
)
1
'VAR26
0
:
VAR217
[
15
:
0
]
=
VAR89
[
15
:
0
]
;
1
'VAR26
1
:
VAR217
[
15
:
0
]
=
VAR89
[
31
:
16
]
;
default
:
begin
end
endcase
end
3
'VAR26
010
:
begin
VAR217
=
VAR89
;
end
default
:
VAR227
(
"VAR157 VAR203 VAR40 VAR135 (VAR167)"
)
;
endcase
end
VAR168
=
VAR217
;
end
endfunction
function
integer
VAR285
;
input
VAR201
;
integer
VAR201
;
integer
VAR253
;
begin
VAR253
=
VAR201
;
VAR285
=
VAR253
;
end
endfunction
function
integer
VAR106
;
input
VAR140
;
integer
VAR140
;
integer
VAR253
;
begin
case
(
VAR140
)
0
:
begin
VAR253
=
'VAR207
62
;
end
1
:
begin
VAR253
=
'VAR207
68
;
end
2
:
begin
VAR253
=
'VAR207
77
;
end
3
:
begin
VAR253
=
'VAR207
78
;
end
default
:
begin
VAR253
=
'VAR207
3f
;
end
endcase
VAR106
=
VAR253
;
end
endfunction
function
integer
VAR193
;
input
VAR140
;
integer
VAR140
;
input
VAR123
;
integer
VAR123
;
integer
VAR253
;
begin
case
(
VAR140
)
0
:
begin
VAR253
=
1
;
end
1
:
begin
VAR253
=
2
;
end
2
:
begin
VAR253
=
4
;
end
3
:
begin
VAR253
=
VAR123
;
end
default
:
begin
VAR253
=
0
;
end
endcase
VAR193
=
VAR253
;
end
endfunction
function
integer
VAR87
;
input
VAR140
;
integer
VAR140
;
input
VAR270
;
integer
VAR270
;
reg
[
2
:
0
]
VAR253
;
begin
case
(
VAR140
)
0
:
begin
VAR253
=
3
'VAR26
000
;
end
1
:
begin
VAR253
=
3
'VAR26
001
;
end
2
:
begin
VAR253
=
3
'VAR26
010
;
end
3
:
begin
VAR253
=
VAR270
;
end
default
:
begin
VAR253
=
3
'VAR26
VAR63
;
end
endcase
VAR87
=
VAR253
;
end
endfunction
function
integer
VAR242
;
input
VAR224
;
integer
VAR224
;
input
VAR201
;
integer
VAR201
;
input
VAR148
;
integer
VAR148
;
input
VAR136
;
integer
VAR136
;
integer
VAR76
;
reg
[
31
:
0
]
VAR248
;
reg
[
31
:
0
]
VAR77
;
reg
[
31
:
0
]
VAR61
;
integer
VAR13
;
reg
[
63
:
0
]
VAR178
;
localparam
[
31
:
0
]
VAR232
=
0
;
localparam
[
31
:
0
]
VAR72
=
1
;
begin
VAR248
=
VAR201
;
VAR77
=
VAR148
;
VAR13
=
VAR148
;
VAR61
=
{
32
{
1
'VAR26
0
}
}
;
case
(
VAR224
)
VAR263
:
begin
VAR61
=
0
;
end
VAR116
:
begin
VAR61
=
VAR248
+
VAR77
;
end
VAR118
:
begin
VAR61
=
VAR248
-
VAR77
;
end
VAR214
:
begin
VAR178
=
VAR248
*
VAR77
;
VAR61
=
VAR178
[
31
:
0
]
;
end
VAR259
:
begin
VAR61
=
VAR248
/
VAR77
;
end
VAR156
:
begin
VAR61
=
VAR248
&
VAR77
;
end
VAR55
:
begin
VAR61
=
VAR248
|
VAR77
;
end
VAR234
:
begin
VAR61
=
VAR248
^
VAR77
;
end
VAR158
:
begin
VAR61
=
VAR248
^
VAR77
;
end
VAR238
:
begin
if
(
VAR13
==
0
)
begin
VAR61
=
VAR248
;
end
else
begin
VAR61
=
VAR248
>>
VAR13
;
end
end
VAR22
:
begin
if
(
VAR13
==
0
)
begin
VAR61
=
VAR248
;
end
else
begin
VAR61
=
VAR248
<<
VAR13
;
end
end
VAR130
:
begin
VAR178
=
{
VAR232
,
VAR72
}
;
if
(
VAR13
>
0
)
begin
begin
:
VAR50
integer
VAR131
;
for
(
VAR131
=
1
;
VAR131
<=
VAR13
;
VAR131
=
VAR131
+
1
)
begin
VAR178
=
VAR178
[
31
:
0
]
*
VAR248
;
end
end
end
VAR61
=
VAR178
[
31
:
0
]
;
end
VAR149
:
begin
if
(
VAR248
==
VAR77
)
begin
VAR61
=
VAR72
;
end
end
VAR6
:
begin
if
(
VAR248
!=
VAR77
)
begin
VAR61
=
VAR72
;
end
end
VAR240
:
begin
if
(
VAR248
>
VAR77
)
begin
VAR61
=
VAR72
;
end
end
VAR141
:
begin
if
(
VAR248
<
VAR77
)
begin
VAR61
=
VAR72
;
end
end
VAR251
:
begin
if
(
VAR248
>=
VAR77
)
begin
VAR61
=
VAR72
;
end
end
VAR62
:
begin
if
(
VAR248
<=
VAR77
)
begin
VAR61
=
VAR72
;
end
end
VAR20
:
begin
VAR61
=
VAR248
%
VAR77
;
end
VAR278
:
begin
if
(
VAR148
<=
31
)
begin
VAR61
=
VAR248
;
VAR61
[
VAR148
]
=
1
'VAR26
1
;
end
else
begin
VAR227
(
"VAR30 VAR189 VAR31 bit >31 (VAR46)"
)
;
;
end
end
VAR33
:
begin
if
(
VAR148
<=
31
)
begin
VAR61
=
VAR248
;
VAR61
[
VAR148
]
=
1
'VAR26
0
;
end
else
begin
VAR227
(
"VAR30 VAR189 VAR31 bit >31 (VAR46)"
)
;
;
end
end
VAR122
:
begin
if
(
VAR148
<=
31
)
begin
VAR61
=
VAR248
;
VAR61
[
VAR148
]
=
~
VAR61
[
VAR148
]
;
end
else
begin
VAR227
(
"VAR30 VAR189 VAR31 bit >31 (VAR46)"
)
;
;
end
end
VAR36
:
begin
if
(
VAR148
<=
31
)
begin
VAR61
=
0
;
VAR61
[
0
]
=
VAR248
[
VAR148
]
;
end
else
begin
VAR227
(
"VAR30 VAR189 VAR31 bit >31 (VAR46)"
)
;
;
end
end
default
:
begin
VAR227
(
"VAR231 VAR277 VAR7 (VAR46)"
)
;
;
end
endcase
VAR76
=
VAR61
;
if
(
VAR136
>=
4
)
begin
VAR227
(
"VAR245 %VAR41 = %VAR41 (%VAR41) %VAR41"
,
VAR76
,
VAR201
,
VAR224
,
VAR148
)
;
end
VAR242
=
VAR76
;
end
endfunction
function
[
31
:
0
]
VAR9
;
input
[
31
:
0
]
VAR201
;
reg
[
31
:
0
]
VAR78
;
begin
VAR78
=
VAR201
;
VAR78
=
0
;
begin
:
VAR121
integer
VAR131
;
for
(
VAR131
=
0
;
VAR131
<=
31
;
VAR131
=
VAR131
+
1
)
begin
if
(
(
VAR201
[
VAR131
]
)
==
1
'VAR26
1
)
begin
VAR78
[
VAR131
]
=
1
'VAR26
1
;
end
end
end
VAR9
=
VAR78
;
end
endfunction
function
integer
VAR124
;
input
VAR18
;
integer
VAR18
;
input
VAR201
;
integer
VAR201
;
integer
VAR94
;
integer
VAR143
;
begin
VAR143
=
VAR18
/
VAR201
;
VAR94
=
VAR18
-
VAR143
*
VAR201
;
VAR124
=
VAR94
;
end
endfunction
function
integer
VAR47
;
input
VAR18
;
integer
VAR18
;
input
VAR201
;
integer
VAR201
;
integer
VAR94
;
integer
VAR143
;
begin
VAR143
=
VAR18
/
VAR201
;
VAR94
=
VAR18
-
VAR143
*
VAR201
;
VAR47
=
VAR143
;
end
endfunction
function
integer
VAR286
;
input
VAR201
;
integer
VAR201
;
integer
VAR29
;
begin
VAR29
=
0
;
if
(
VAR201
!=
0
)
VAR29
=
1
;
VAR286
=
VAR29
;
end
endfunction
function
integer
VAR111
;
input
VAR56
;
integer
VAR56
;
reg
[
31
:
0
]
VAR191
;
reg
[
31
:
0
]
VAR147
;
reg
VAR200
;
begin
VAR191
=
VAR56
;
VAR200
=
1
'VAR26
1
;
VAR147
[
0
]
=
VAR200
^
VAR191
[
31
]
;
VAR147
[
1
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
0
]
;
VAR147
[
2
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
1
]
;
VAR147
[
3
]
=
VAR191
[
2
]
;
VAR147
[
4
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
3
]
;
VAR147
[
5
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
4
]
;
VAR147
[
6
]
=
VAR191
[
5
]
;
VAR147
[
7
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
6
]
;
VAR147
[
8
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
7
]
;
VAR147
[
9
]
=
VAR191
[
8
]
;
VAR147
[
10
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
9
]
;
VAR147
[
11
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
10
]
;
VAR147
[
12
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
11
]
;
VAR147
[
13
]
=
VAR191
[
12
]
;
VAR147
[
14
]
=
VAR191
[
13
]
;
VAR147
[
15
]
=
VAR191
[
14
]
;
VAR147
[
16
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
15
]
;
VAR147
[
17
]
=
VAR191
[
16
]
;
VAR147
[
18
]
=
VAR191
[
17
]
;
VAR147
[
19
]
=
VAR191
[
18
]
;
VAR147
[
20
]
=
VAR191
[
19
]
;
VAR147
[
21
]
=
VAR191
[
20
]
;
VAR147
[
22
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
21
]
;
VAR147
[
23
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
22
]
;
VAR147
[
24
]
=
VAR191
[
23
]
;
VAR147
[
25
]
=
VAR191
[
24
]
;
VAR147
[
26
]
=
VAR200
^
VAR191
[
31
]
^
VAR191
[
25
]
;
VAR147
[
27
]
=
VAR191
[
26
]
;
VAR147
[
28
]
=
VAR191
[
27
]
;
VAR147
[
29
]
=
VAR191
[
28
]
;
VAR147
[
30
]
=
VAR191
[
29
]
;
VAR147
[
31
]
=
VAR191
[
30
]
;
VAR111
=
VAR147
;
end
endfunction
function
integer
VAR246
;
input
VAR56
;
integer
VAR56
;
input
VAR140
;
integer
VAR140
;
integer
VAR35
;
integer
VAR131
;
reg
[
31
:
0
]
VAR191
;
begin
VAR191
=
VAR56
;
for
(
VAR131
=
31
;
VAR131
>=
VAR140
;
VAR131
=
VAR131
-
1
)
VAR191
[
VAR131
]
=
0
;
VAR35
=
VAR191
;
VAR246
=
VAR35
;
end
endfunction
function
integer
VAR51
;
input
VAR56
;
integer
VAR56
;
input
VAR140
;
integer
VAR140
;
integer
VAR35
;
reg
[
31
:
0
]
VAR191
;
integer
VAR150
;
integer
VAR131
;
begin
case
(
VAR140
)
1
:
begin
VAR150
=
0
;
end
2
:
begin
VAR150
=
1
;
end
4
:
begin
VAR150
=
2
;
end
8
:
begin
VAR150
=
3
;
end
16
:
begin
VAR150
=
4
;
end
32
:
begin
VAR150
=
5
;
end
64
:
begin
VAR150
=
6
;
end
128
:
begin
VAR150
=
7
;
end
256
:
begin
VAR150
=
8
;
end
512
:
begin
VAR150
=
9
;
end
1024
:
begin
VAR150
=
10
;
end
2048
:
begin
VAR150
=
11
;
end
4096
:
begin
VAR150
=
12
;
end
8192
:
begin
VAR150
=
13
;
end
16384
:
begin
VAR150
=
14
;
end
32768
:
begin
VAR150
=
15
;
end
65536
:
begin
VAR150
=
16
;
end
131072
:
VAR150
=
17
;
262144
:
VAR150
=
18
;
524288
:
VAR150
=
19
;
1048576
:
VAR150
=
20
;
2097152
:
VAR150
=
21
;
4194304
:
VAR150
=
22
;
8388608
:
VAR150
=
23
;
16777216
:
VAR150
=
24
;
33554432
:
VAR150
=
25
;
67108864
:
VAR150
=
26
;
134217728
:
VAR150
=
27
;
268435456
:
VAR150
=
28
;
536870912
:
VAR150
=
29
;
1073741824
:
VAR150
=
30
;
default
:
begin
VAR227
(
"VAR21 function VAR265 (VAR46)"
)
;
;
end
endcase
VAR191
=
VAR97
(
VAR56
)
;
if
(
VAR150
<
31
)
begin
for
(
VAR131
=
31
;
VAR131
>=
VAR150
;
VAR131
=
VAR131
-
1
)
VAR191
[
VAR131
]
=
0
;
end
VAR35
=
VAR85
(
VAR191
)
;
VAR51
=
VAR35
;
end
endfunction
function
VAR221
;
input
VAR137
;
integer
VAR137
;
input
VAR212
;
integer
VAR212
;
reg
[
31
:
0
]
VAR154
;
reg
VAR146
;
begin
VAR154
=
VAR212
;
VAR146
=
0
;
case
(
VAR137
)
0
:
begin
if
(
VAR154
[
9
:
0
]
==
10
'VAR26
0000000000
)
begin
VAR146
=
1
;
end
end
1
:
begin
VAR146
=
1
;
end
2
:
begin
end
default
:
begin
VAR227
(
"VAR231 VAR244 VAR129 VAR75 (VAR46)"
)
;
;
end
endcase
VAR221
=
VAR146
;
end
endfunction
localparam
VAR91
=
VAR38
*
1
;
input
VAR101
;
input
VAR133
;
input
VAR182
;
input
VAR83
;
input
[
VAR79
-
1
:
0
]
VAR93
;
input
[
31
:
0
]
VAR185
;
output
[
31
:
0
]
VAR173
;
reg
[
31
:
0
]
VAR173
;
input
VAR267
;
output
VAR188
;
wire
VAR188
;
input
[
1
:
0
]
VAR177
;
input
[
2
:
0
]
VAR255
;
input
[
2
:
0
]
VAR160
;
input
VAR152
;
input
[
3
:
0
]
VAR59
;
output
VAR74
;
wire
VAR74
;
input
VAR54
;
input
VAR159
;
input
VAR86
;
input
[
VAR79
-
1
:
0
]
VAR171
;
inout
[
31
:
0
]
VAR11
;
wire
[
31
:
0
]
VAR11
;
reg
[
31
:
0
]
VAR28
;
output
VAR14
;
wire
VAR14
;
output
VAR96
;
wire
VAR96
;
integer
VAR179
=
VAR68
;
reg
VAR57
;
reg
[
1
:
0
]
VAR284
;
reg
[
2
:
0
]
VAR99
;
reg
[
VAR79
-
1
:
0
]
VAR15
;
reg
VAR190
;
reg
VAR151
;
reg
[
3
:
0
]
VAR252
;
reg
[
2
:
0
]
VAR17
;
reg
VAR198
;
reg
VAR275
;
reg
VAR223
;
reg
VAR82
;
reg
VAR126
;
reg
VAR247
;
wire
[
31
:
0
]
VAR232
;
reg
VAR134
;
assign
VAR232
=
{
32
{
1
'VAR26
0
}
}
;
reg
VAR19
;
begin
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin | gpl-3.0 |
jakubfi/mera400f | src/px.v | 9,567 | module MODULE1(
input VAR76, input VAR106,
input VAR164, input VAR171, output VAR85, output VAR175, output VAR100, output VAR56, output VAR16, output VAR112,
input VAR66, input VAR181, input VAR156, input VAR48, input VAR154, input VAR69, input VAR142, input VAR93, input VAR116, input VAR138, input VAR77, input VAR32, input VAR128, input VAR78, input VAR27, input VAR117, input VAR95, input VAR141, input VAR169, input VAR159, output VAR99,
output reg VAR114, output reg VAR61, output reg VAR153, output reg VAR72, output reg VAR89, output reg VAR126, output reg VAR44, output reg VAR180, output reg VAR122, output reg VAR13, output reg VAR101, output reg VAR25, output reg wr, output reg VAR50, output reg VAR103, output reg VAR80, output reg VAR54, output reg VAR40, output reg VAR53, output reg VAR157, output reg VAR129, output reg VAR162,
input VAR67, output VAR139,
input VAR4, input VAR152, input VAR36, input VAR20, input VAR14, input VAR146,
input VAR35, input VAR165,
input VAR145, input VAR15, input in, input VAR31, input VAR127, input VAR149, input VAR177, input VAR135, input VAR43, input VAR158, output VAR62,
input VAR26, input VAR42, input VAR150, input VAR98, output VAR11, output VAR24, input VAR174, input VAR115, input VAR92,
output VAR121, output VAR133, output VAR104, output VAR104, output VAR105, output VAR39, output VAR160, output VAR166, output VAR86, output VAR79,
output VAR90, output VAR17, output din, output VAR108, output VAR37, output VAR113, output [0:15] VAR1, output [0:15] VAR82,
input VAR74, output VAR57, output VAR124, output VAR143, input VAR59, input VAR45, input VAR68, input VAR178,
output VAR58, input VAR49, input VAR132, input VAR23, output VAR73, output VAR144, output VAR65,
input VAR28, input VAR9, input VAR179, input VAR97, input VAR172, input VAR119, input VAR120, output VAR102, output VAR52, output VAR96, output VAR19 );
parameter VAR75;
parameter VAR8;
parameter VAR170;
parameter VAR60;
parameter VAR12;
always @ (posedge VAR76, posedge VAR106) begin
if (VAR106) begin
{VAR114, VAR61} <= 2'd0;
{VAR122, VAR13, VAR50, wr, VAR25, VAR101, VAR54, VAR80, VAR103} <= 9'd0;
{VAR153, VAR72, VAR89, VAR126, VAR44, VAR180} <= 6'b100000;
{VAR40, VAR53, VAR157, VAR129, VAR162} <= 5'd0;
end else begin
if (VAR112) begin
{VAR114, VAR61} <= {VAR66, VAR181};
{VAR122, VAR13, VAR50, wr, VAR25, VAR101, VAR54, VAR80, VAR103} <= {VAR77, VAR32, VAR128, VAR78, VAR27, VAR117, VAR95, VAR141, VAR169};
{VAR89, VAR126, VAR44, VAR180} <= {VAR142, VAR93, VAR116, VAR138};
{VAR53, VAR157, VAR129, VAR162} <= {VAR134, VAR151, VAR34, VAR91};
end
if (VAR69) VAR72 <= 1'b1;
end
else if (VAR112) VAR72 <= VAR154;
if (VAR48) VAR153 <= 1'b1;
end
else if (VAR112) VAR153 <= VAR156;
if (VAR159) VAR40 <= 1'b1;
end
else if (VAR112) VAR40 <= VAR155;
end
end
assign VAR139 = VAR101 | VAR44 | VAR50 | VAR25;
wire VAR123 = VAR25 | VAR50 | VAR44 | (VAR61 & VAR4);
wire VAR46 = VAR72 | VAR114 | VAR61 | VAR40 | VAR157;
wire VAR107 = VAR180 | wr | VAR103 | VAR80 | VAR53 | VAR129 | VAR162;
wire VAR47 = VAR101 | (VAR153 & VAR67) | VAR126 | VAR13;
wire VAR148 = VAR89 | VAR122 | VAR54;
VAR131 VAR84(
.VAR76(VAR76),
.VAR65(VAR65),
.VAR49(VAR49),
.VAR73(VAR73),
.VAR152(VAR152),
.VAR36(VAR36),
.VAR164(VAR164),
.VAR171(VAR171),
.VAR140(VAR123),
.VAR87(VAR46),
.VAR163(VAR107),
.VAR7(VAR47),
.VAR41(VAR148),
.VAR112(VAR112),
.VAR175(VAR175),
.VAR100(VAR100),
.VAR56(VAR56),
.VAR16(VAR16),
.VAR85(VAR85)
);
wire VAR155 = (VAR173 | VAR145) & VAR98;
wire VAR134 = VAR40 & VAR35;
wire VAR151 = (~VAR35 & VAR165 & VAR40) | (VAR40 & VAR173) | (VAR15 & VAR98) | (VAR53) | (VAR162 & VAR145) | (~VAR62 & ~VAR42 & VAR157) | (VAR157 & VAR62 & ~VAR150);
wire VAR34 = VAR157 & VAR42;
wire VAR91 = VAR129 | (VAR145 & VAR40);
assign VAR79 = VAR16 & VAR40 & VAR145;
assign VAR11 = ~VAR35 & VAR150 & VAR157 & VAR165;
wire VAR18 = VAR165 | VAR173;
wire VAR10 = VAR157 & VAR62;
assign VAR99 = (VAR150 & VAR10) | (VAR162 & ~VAR145);
assign VAR24 = ~VAR145 & VAR162;
assign VAR62 = VAR145 | VAR15;
wire VAR147 = wr | VAR72 | VAR180 | VAR80 | VAR168 | VAR103 | VAR92;
wire VAR110 = VAR157 | VAR92 | VAR80 | VAR180 | VAR103 | VAR168 | (wr & ~VAR111);
assign VAR121 = ~(VAR104 & ~VAR80) & VAR29;
assign VAR133 = (VAR104 & ~VAR80) & VAR29;
assign VAR104 = VAR104 & VAR29;
assign VAR104 = (VAR157 & VAR15) | (VAR103 & VAR174) | (VAR174 & wr) | (VAR115 & VAR147);
assign VAR105 = VAR29 & ~VAR53;
wire VAR111 = in | VAR31;
wire VAR30 = VAR53 | (in & VAR80) | VAR114;
assign VAR90 = VAR30 & VAR29;
wire VAR38 = (VAR31 & VAR80) ^ VAR25;
assign VAR39 = VAR38 & VAR29;
assign VAR17 = VAR109 & VAR29;
wire VAR109 = VAR146 | VAR180 | VAR129 | VAR40 | VAR10 | wr | VAR72 | VAR92;
assign VAR160 = VAR30 | VAR109;
assign VAR166 = VAR110 & VAR29;
assign VAR37 = VAR31 & VAR80 & VAR29;
assign VAR86 = VAR29 & (VAR114 | VAR72 | (VAR111 & wr));
assign VAR113 = VAR29 & VAR127 & VAR80;
wire VAR64 = VAR80 & VAR149;
assign VAR1[0] = VAR29 & (VAR64 & VAR97);
assign VAR1[1:14] = 'd0;
assign VAR1[15] = VAR29 & VAR64;
assign din = VAR29 & VAR64;
wire VAR5 = VAR170 & VAR26 & VAR115 & ~VAR18;
assign VAR108 = VAR29 & VAR25 & ~VAR5;
wire VAR25 = VAR162 | VAR57 | VAR103 | VAR14;
assign VAR57 = VAR157 & VAR18;
wire VAR136 = VAR109 ^ VAR25;
wire VAR168 = VAR14 | VAR146;
assign VAR124 = (wr & VAR177) | VAR74 | VAR11;
wire VAR88;
VAR118 #(.VAR161(2'd2)) VAR137( .clk(VAR76),
.VAR176(VAR124),
.VAR130(VAR88)
);
wire VAR88 = ~VAR88;
assign VAR143 = VAR88 & VAR124 & ~VAR11;
wire VAR83 = VAR85 | VAR100;
wire VAR21 = VAR80 | VAR53 | wr | VAR103 | VAR92 | VAR40 | VAR157 | VAR129 | VAR162 | VAR168 | VAR72 | VAR180 | VAR114;
wire VAR3 = VAR59 | VAR159 | VAR69;
wire VAR71 = VAR45 & wr;
wire VAR22 = VAR56 & VAR25 & VAR68 & VAR135;
wire VAR29, VAR51;
VAR2 #(
.VAR60(VAR60),
.VAR12(VAR12)
) VAR81(
.VAR76(VAR76),
.VAR106(VAR106),
.VAR83(VAR83),
.VAR21(VAR21),
.VAR3(VAR3),
.VAR71(VAR71),
.VAR22(VAR22),
.VAR49(VAR49),
.VAR132(VAR132),
.VAR23(VAR23),
.VAR65(VAR65),
.VAR58(VAR58),
.VAR29(VAR29),
.VAR51(VAR51)
);
assign VAR73 = VAR132 | VAR23;
wire VAR55 = VAR29 & (VAR129 & VAR94);
wire VAR167 = VAR178 & ~VAR75;
reg VAR94;
always @ (posedge VAR76, posedge VAR106) begin
if (VAR106) VAR94 <= 1'b0;
end
else if (VAR112) begin
case ({VAR167, VAR162})
2'b00: VAR94 <= VAR94;
2'b01: VAR94 <= 1'b0;
2'b10: VAR94 <= 1'b1;
2'b11: VAR94 <= ~VAR94;
endcase
end
end
wire VAR173 = VAR94 | VAR167 | VAR43;
wire VAR70 = VAR29 & VAR136;
wire VAR63 = VAR28 & VAR9 & VAR70;
wire VAR125 = VAR6 & VAR8;
always @ (posedge VAR76, negedge VAR70) begin
if (~VAR70) VAR102 <= 1'b0;
end
else if (VAR125) VAR102 <= 1'b1;
else if (VAR175) VAR102 <= VAR63;
end
assign VAR144 = VAR179 | VAR132;
assign VAR52 = VAR175 & VAR179 & VAR109;
assign VAR96 = VAR136 & VAR51;
wire VAR6 = (VAR52 | VAR96) & ~VAR104;
always @ (posedge VAR76) begin
if (VAR106 | VAR20) VAR19 <= 1'b0;
end
else if (VAR6) VAR19 <= 1'b1;
end
assign VAR82[0:8] = 'd0;
assign VAR82[9] = VAR29 & (VAR40 | VAR129 | VAR162);
assign VAR82[10] = VAR29 & (VAR40 | (VAR129 & VAR173) | VAR162);
assign VAR82[11] = 'd0;
assign VAR82[12] = VAR55 & VAR158;
assign VAR82[13] = VAR55 & VAR172;
assign VAR82[14] = VAR55 & VAR119;
assign VAR82[15] = (VAR55 & VAR120) | VAR33;
wire VAR33 = VAR29 & (VAR162 | VAR40);
endmodule | gpl-2.0 |
spike556/HuffmanCode | rtl model/HuffmanCode.v | 16,007 | module MODULE1 (
input clk,
input VAR28,
input [18:0] VAR17,
input [18:0] VAR35,
input [18:0] VAR26,
input [18:0] VAR44,
input [18:0] VAR40,
input [18:0] VAR42,
input [18:0] VAR50,
input [18:0] VAR1,
input [18:0] VAR39,
input [18:0] VAR11,
input VAR65,
output reg VAR37,
output reg [8:0] VAR45,
output reg [3:0] VAR55,
output wire VAR41
);
localparam VAR60 = 2'd0;
localparam VAR49 = 2'd1;
localparam VAR16 = 2'd2;
localparam VAR46 = 2'd3;
reg [1:0] state; reg [1:0] VAR36;
reg [3:0] VAR63;
reg [3:0] VAR54;
reg [3:0] VAR61;
reg [3:0] VAR29;
reg [18:0] VAR2 [0:18];
reg [18:0] VAR27;
reg [18:0] VAR34;
reg [18:0] VAR5;
reg [18:0] VAR21;
reg [18:0] VAR51;
reg [18:0] VAR48;
reg [18:0] VAR8;
reg [18:0] VAR31;
reg [18:0] VAR15;
reg [18:0] VAR24;
reg [18:0] VAR13;
reg [18:0] VAR43;
reg [18:0] VAR25;
reg [18:0] VAR30;
reg [18:0] VAR38;
reg [18:0] VAR23;
wire [18:0] VAR62;
wire [18:0] VAR19;
wire [18:0] VAR4;
wire [18:0] VAR32;
wire [18:0] VAR14;
wire [18:0] VAR57;
wire [18:0] VAR59;
wire [18:0] VAR9;
wire [18:0] VAR52;
wire [18:0] VAR56;
wire [18:0] VAR66;
wire [18:0] VAR7;
wire [18:0] VAR3;
wire [18:0] VAR58;
wire [18:0] VAR12;
wire [18:0] VAR22;
always @(posedge clk or negedge VAR28) begin
if (~VAR28)
VAR37 <= 1'b0;
end
else if (VAR65)
VAR37 <= 1'b1;
else
VAR37 <= 1'b0;
end
always @(posedge clk or negedge VAR28) begin
if (~VAR28) begin
state <= VAR60;
VAR63 <= 4'b0;
VAR61 <= 4'd0;
end else begin
state <= VAR36;
VAR63 <= VAR54;
VAR61 <= VAR29;
end
end
always @(*) begin
case (state)
VAR60: begin
if (VAR65)
VAR36 = VAR49;
end
else
VAR36 = VAR60;
VAR54 = 4'b0;
VAR29 = 4'd0;
end
VAR49: begin
if (VAR63 == 4'd9) begin
VAR36 = VAR16;
VAR54 = 4'd0;
end else begin
VAR36 = VAR49;
VAR54 = VAR63 + 1;
end
VAR29 = 4'd0;
end
VAR16: begin
if (VAR63 == 4'd8) begin
VAR36 = VAR46;
VAR54 = 4'd0;
VAR29 = VAR67[0];
end else begin
VAR36 = VAR16;
VAR54 = VAR63 + 1;
VAR29 = 4'd0;
end
end
VAR46: begin
if (VAR61 == 4'd1) begin
if (VAR63 == 4'd9) begin
VAR36 = VAR60;
VAR54 = 4'd0;
VAR29 = 4'd0;
end else begin
VAR36 = VAR46;
VAR54 = VAR63 + 1;
VAR29 = VAR67[VAR63+1];
end
end
else begin
VAR36 = VAR46;
VAR54 = VAR63;
VAR29 = VAR61 - 1;
end
end
default: begin
VAR36 = state;
VAR54 = VAR63;
VAR29 = VAR61;
end
endcase
end
always @(posedge clk or negedge VAR28) begin
if (~VAR28) begin
VAR27 <= 19'b0;
VAR34 <= 19'b0;
VAR5 <= 19'b0;
VAR21 <= 19'b0;
VAR51 <= 19'b0;
VAR48 <= 19'b0;
VAR8 <= 19'b0;
VAR31 <= 19'b0;
VAR15 <= 19'b0;
VAR24 <= 19'b0;
VAR13 <= 19'b0;
VAR43 <= 19'b0;
VAR25 <= 19'b0;
VAR30 <= 19'b0;
VAR38 <= 19'b0;
VAR23 <= 19'b0;
end
else if (state==VAR49) begin
case(VAR63)
4'd0: begin
VAR27 <= VAR17;
VAR34 <= VAR35;
VAR5 <= VAR26;
VAR21 <= VAR44;
VAR51 <= VAR40;
VAR48 <= VAR42;
VAR8 <= VAR50;
VAR31 <= VAR1;
VAR15 <= VAR39;
VAR24 <= VAR11;
VAR13 <= 19'd255;
VAR43 <= 19'd255;
VAR25 <= 19'd255;
VAR30 <= 19'd255;
VAR38 <= 19'd255;
VAR23 <= 19'd255;
end
4'd1: begin
VAR27 <= {6'b0, 5'd10, VAR62[7:0]+VAR19[7:0]};
VAR34 <= VAR4;
VAR5 <= VAR32;
VAR21 <= VAR14;
VAR51 <= VAR57;
VAR48 <= VAR59;
VAR8 <= VAR9;
VAR31 <= VAR52;
VAR15 <= VAR56;
VAR24 <= 19'd255;
VAR13 <= 19'd255;
VAR43 <= 19'd255;
VAR25 <= 19'd255;
VAR30 <= 19'd255;
VAR38 <= 19'd255;
VAR23 <= 19'd255;
end
4'd2: begin
VAR27 <= {6'b0, 5'd11, VAR62[7:0]+VAR19[7:0]};
VAR34 <= VAR4;
VAR5 <= VAR32;
VAR21 <= VAR14;
VAR51 <= VAR57;
VAR48 <= VAR59;
VAR8 <= VAR9;
VAR31 <= VAR52;
VAR15 <= 19'd255;
VAR24 <= 19'd255;
VAR13 <= 19'd255;
VAR43 <= 19'd255;
VAR25 <= 19'd255;
VAR30 <= 19'd255;
VAR38 <= 19'd255;
VAR23 <= 19'd255;
end
4'd3: begin
VAR27 <= {6'b0, 5'd12, VAR62[7:0]+VAR19[7:0]};
VAR34 <= VAR4;
VAR5 <= VAR32;
VAR21 <= VAR14;
VAR51 <= VAR57;
VAR48 <= VAR59;
VAR8 <= VAR9;
VAR31 <= 19'd255;
VAR15 <= 19'd255;
VAR24 <= 19'd255;
VAR13 <= 19'd255;
VAR43 <= 19'd255;
VAR25 <= 19'd255;
VAR30 <= 19'd255;
VAR38 <= 19'd255;
VAR23 <= 19'd255;
end
4'd4: begin
VAR27 <= {6'b0, 5'd13, VAR62[7:0]+VAR19[7:0]};
VAR34 <= VAR4;
VAR5 <= VAR32;
VAR21 <= VAR14;
VAR51 <= VAR57;
VAR48 <= VAR59;
VAR8 <= 19'd255;
VAR31 <= 19'd255;
VAR15 <= 19'd255;
VAR24 <= 19'd255;
VAR13 <= 19'd255;
VAR43 <= 19'd255;
VAR25 <= 19'd255;
VAR30 <= 19'd255;
VAR38 <= 19'd255;
VAR23 <= 19'd255;
end
4'd5: begin
VAR27 <= {6'b0, 5'd14, VAR62[7:0]+VAR19[7:0]};
VAR34 <= VAR4;
VAR5 <= VAR32;
VAR21 <= VAR14;
VAR51 <= VAR57;
VAR48 <= 19'd255;
VAR8 <= 19'd255;
VAR31 <= 19'd255;
VAR15 <= 19'd255;
VAR24 <= 19'd255;
VAR13 <= 19'd255;
VAR43 <= 19'd255;
VAR25 <= 19'd255;
VAR30 <= 19'd255;
VAR38 <= 19'd255;
VAR23 <= 19'd255;
end
4'd6: begin
VAR27 <= {6'b0, 5'd15, VAR62[7:0]+VAR19[7:0]};
VAR34 <= VAR4;
VAR5 <= VAR32;
VAR21 <= VAR14;
VAR51 <= 19'd255;
VAR48 <= 19'd255;
VAR8 <= 19'd255;
VAR31 <= 19'd255;
VAR15 <= 19'd255;
VAR24 <= 19'd255;
VAR13 <= 19'd255;
VAR43 <= 19'd255;
VAR25 <= 19'd255;
VAR30 <= 19'd255;
VAR38 <= 19'd255;
VAR23 <= 19'd255;
end
4'd7: begin
VAR27 <= {6'b0, 5'd16, VAR62[7:0]+VAR19[7:0]};
VAR34 <= VAR4;
VAR5 <= VAR32;
VAR21 <= 19'd255;
VAR51 <= 19'd255;
VAR48 <= 19'd255;
VAR8 <= 19'd255;
VAR31 <= 19'd255;
VAR15 <= 19'd255;
VAR24 <= 19'd255;
VAR13 <= 19'd255;
VAR43 <= 19'd255;
VAR25 <= 19'd255;
VAR30 <= 19'd255;
VAR38 <= 19'd255;
VAR23 <= 19'd255;
end
4'd8: begin
VAR27 <= {6'b0, 5'd17, VAR62[7:0]+VAR19[7:0]};
VAR34 <= VAR4;
VAR5 <= 19'd255;
VAR21 <= 19'd255;
VAR51 <= 19'd255;
VAR48 <= 19'd255;
VAR8 <= 19'd255;
VAR31 <= 19'd255;
VAR15 <= 19'd255;
VAR24 <= 19'd255;
VAR13 <= 19'd255;
VAR43 <= 19'd255;
VAR25 <= 19'd255;
VAR30 <= 19'd255;
VAR38 <= 19'd255;
VAR23 <= 19'd255;
end
4'd9: begin
VAR27 <= 19'b0;
VAR34 <= 19'b0;
VAR5 <= 19'b0;
VAR21 <= 19'b0;
VAR51 <= 19'b0;
VAR48 <= 19'b0;
VAR8 <= 19'b0;
VAR31 <= 19'b0;
VAR15 <= 19'b0;
VAR24 <= 19'b0;
VAR13 <= 19'b0;
VAR43 <= 19'b0;
VAR25 <= 19'b0;
VAR30 <= 19'b0;
VAR38 <= 19'b0;
VAR23 <= 19'b0;
end
default: begin
VAR27 <= 20'b0;
VAR34 <= 20'b0;
VAR5 <= 20'b0;
VAR21 <= 20'b0;
VAR51 <= 20'b0;
VAR48 <= 20'b0;
VAR8 <= 20'b0;
VAR31 <= 20'b0;
VAR15 <= 20'b0;
VAR24 <= 20'b0;
VAR13 <= 20'b0;
VAR43 <= 20'b0;
VAR25 <= 20'b0;
VAR30 <= 20'b0;
VAR38 <= 20'b0;
VAR23 <= 20'b0;
end
endcase
end
else begin
VAR27 <= 20'b0;
VAR34 <= 20'b0;
VAR5 <= 20'b0;
VAR21 <= 20'b0;
VAR51 <= 20'b0;
VAR48 <= 20'b0;
VAR8 <= 20'b0;
VAR31 <= 20'b0;
VAR15 <= 20'b0;
VAR24 <= 20'b0;
VAR13 <= 20'b0;
VAR43 <= 20'b0;
VAR25 <= 20'b0;
VAR30 <= 20'b0;
VAR38 <= 20'b0;
VAR23 <= 20'b0;
end
end
integer VAR10;
always @(posedge clk or negedge VAR28) begin
if (~VAR28) begin
for (VAR10 = 0; VAR10 < 19; VAR10 = VAR10 + 1) begin
VAR2[VAR10] <= 19'b0;
end
end
else if (state == VAR49) begin
case (VAR63)
4'd0: ;
4'd1: begin
VAR2[VAR62[12:8]] <= {5'd10, 1'd0, VAR62[12:0]};
VAR2[VAR19[12:8]] <= {5'd10, 1'd1, VAR19[12:0]};
end
4'd2: begin
VAR2[VAR62[12:8]] <= {5'd11, 1'd0, VAR62[12:0]};
VAR2[VAR19[12:8]] <= {5'd11, 1'd1, VAR19[12:0]};
end
4'd3: begin
VAR2[VAR62[12:8]] <= {5'd12, 1'd0, VAR62[12:0]};
VAR2[VAR19[12:8]] <= {5'd12, 1'd1, VAR19[12:0]};
end
4'd4: begin
VAR2[VAR62[12:8]] <= {5'd13, 1'd0, VAR62[12:0]};
VAR2[VAR19[12:8]] <= {5'd13, 1'd1, VAR19[12:0]};
end
4'd5: begin
VAR2[VAR62[12:8]] <= {5'd14, 1'd0, VAR62[12:0]};
VAR2[VAR19[12:8]] <= {5'd14, 1'd1, VAR19[12:0]};
end
4'd6: begin
VAR2[VAR62[12:8]] <= {5'd15, 1'd0, VAR62[12:0]};
VAR2[VAR19[12:8]] <= {5'd15, 1'd1, VAR19[12:0]};
end
4'd7: begin
VAR2[VAR62[12:8]] <= {5'd16, 1'd0, VAR62[12:0]};
VAR2[VAR19[12:8]] <= {5'd16, 1'd1, VAR19[12:0]};
end
4'd8: begin
VAR2[VAR62[12:8]] <= {5'd17, 1'd0, VAR62[12:0]};
VAR2[VAR19[12:8]] <= {5'd17, 1'd1, VAR19[12:0]};
end
4'd9: begin
VAR2[VAR62[12:8]] <= {5'd18, 1'd0, VAR62[12:0]};
VAR2[VAR19[12:8]] <= {5'd18, 1'd1, VAR19[12:0]};
VAR2[18] <= {5'd31, 1'd0, 5'd18, VAR62[7:0]+VAR19[7:0]}; end
default: ;
endcase
end
end
VAR20 # (
.VAR64 (5'd19),
.VAR6 (4'd8)
) VAR33 (
.VAR27 (VAR27),
.VAR34 (VAR34),
.VAR5 (VAR5),
.VAR21 (VAR21),
.VAR51 (VAR51),
.VAR48 (VAR48),
.VAR8 (VAR8),
.VAR31 (VAR31),
.VAR15 (VAR15),
.VAR24 (VAR24),
.VAR13 (VAR13),
.VAR43 (VAR43),
.VAR25 (VAR25),
.VAR30 (VAR30),
.VAR38 (VAR38),
.VAR23 (VAR23),
.VAR62 (VAR62),
.VAR19 (VAR19),
.VAR4 (VAR4),
.VAR32 (VAR32),
.VAR14 (VAR14),
.VAR57 (VAR57),
.VAR59 (VAR59),
.VAR9 (VAR9),
.VAR52 (VAR52),
.VAR56 (VAR56),
.VAR66 (VAR66),
.VAR7 (VAR7),
.VAR3 (VAR3),
.VAR58 (VAR58),
.VAR12 (VAR12),
.VAR22 (VAR22)
);
genvar VAR53;
reg [8:0] VAR18 [0:9];
reg [3:0] VAR67 [0:9];
reg [4:0] VAR47 [0:9];
generate
for (VAR53 = 0; VAR53 < 10; VAR53 = VAR53 + 1) begin
always @(posedge clk or negedge VAR28) begin
if (~VAR28) begin
VAR18[VAR53] <= 9'b0;
VAR67[VAR53] <= 4'b0;
VAR47[VAR53] <= 5'b0;
end else if (state == VAR16) begin
case (VAR63)
4'd0: begin
VAR18[VAR53][0] <= VAR2[VAR53][13];
VAR67[VAR53] <= VAR67[VAR53] + 1;
VAR47[VAR53] <= VAR2[VAR53][18:14];
end
4'd1: begin
if (VAR47[VAR53] != 5'd18) begin
VAR18[VAR53][1] <= VAR2[VAR47[VAR53]][13];
VAR67[VAR53] <= VAR67[VAR53] + 1;
VAR47[VAR53] <= VAR2[VAR47[VAR53]][18:14];
end
end
4'd2: begin
if (VAR47[VAR53] != 5'd18) begin
VAR18[VAR53][2] <= VAR2[VAR47[VAR53]][13];
VAR67[VAR53] <= VAR67[VAR53] + 1;
VAR47[VAR53] <= VAR2[VAR47[VAR53]][18:14];
end
end
4'd3: begin
if (VAR47[VAR53] != 5'd18) begin
VAR18[VAR53][3] <= VAR2[VAR47[VAR53]][13];
VAR67[VAR53] <= VAR67[VAR53] + 1;
VAR47[VAR53] <= VAR2[VAR47[VAR53]][18:14];
end
end
4'd4: begin
if (VAR47[VAR53] != 5'd18) begin
VAR18[VAR53][4] <= VAR2[VAR47[VAR53]][13];
VAR67[VAR53] <= VAR67[VAR53] + 1;
VAR47[VAR53] <= VAR2[VAR47[VAR53]][18:14];
end
end
4'd5: begin
if (VAR47[VAR53] != 5'd18) begin
VAR18[VAR53][5] <= VAR2[VAR47[VAR53]][13];
VAR67[VAR53] <= VAR67[VAR53] + 1;
VAR47[VAR53] <= VAR2[VAR47[VAR53]][18:14];
end
end
4'd6: begin
if (VAR47[VAR53] != 5'd18) begin
VAR18[VAR53][6] <= VAR2[VAR47[VAR53]][13];
VAR67[VAR53] <= VAR67[VAR53] + 1;
VAR47[VAR53] <= VAR2[VAR47[VAR53]][18:14];
end
end
4'd7: begin
if (VAR47[VAR53] != 5'd18) begin
VAR18[VAR53][7] <= VAR2[VAR47[VAR53]][13];
VAR67[VAR53] <= VAR67[VAR53] + 1;
VAR47[VAR53] <= VAR2[VAR47[VAR53]][18:14];
end
end
4'd8: begin
if (VAR47[VAR53] != 5'd18) begin
VAR18[VAR53][8] <= VAR2[VAR47[VAR53]][13];
VAR67[VAR53] <= VAR67[VAR53] + 1;
VAR47[VAR53] <= VAR2[VAR47[VAR53]][18:14];
end
end
default: begin
VAR18[VAR53] <= 9'b0;
VAR67[VAR53] <= 4'b0;
VAR47[VAR53] <= 5'b0;
end
endcase
end
end
end
endgenerate
always @(posedge clk or negedge VAR28) begin
if (~VAR28) begin
VAR45 <= 9'd0;
VAR55 <= 4'd0;
end
else begin
if (VAR36 == VAR46) begin
VAR45 <= VAR18[VAR54];
VAR55 <= VAR67[VAR54];
end
else begin
VAR45 <= 9'd0;
VAR55 <= 4'd0;
end
end
end
assign VAR41 = (state == VAR46) ? 1'b1 : 1'b0;
endmodule | gpl-3.0 |
anderson1008/PAB-NOC | RTL/fsmPG.v | 1,967 | module MODULE1 (clk, reset, VAR8, VAR21, VAR7, VAR2, VAR15, VAR16, VAR9, VAR11);
input clk, reset, VAR8, VAR7, VAR2, VAR15;
input [VAR19-1:0] VAR21;
output reg [VAR18-1:0] VAR16;
output reg VAR9;
output reg VAR11;
wire [5:0] VAR12;
reg [4:0] delay;
assign VAR12 [0] = (VAR8 == VAR13) ? 1 : 0; assign VAR12 [1] = (VAR21 < VAR4) ? 1 : 0; assign VAR12 [2] = VAR2;
assign VAR12 [3] = (delay == 0) ? 1 : 0; assign VAR12 [4] = VAR15;
assign VAR12 [5] = VAR7;
always @ (VAR16 or delay) begin
case (VAR16)
; VAR3:
VAR9 = 1'b1;
delay = VAR20;
VAR11 = 1'b1;
delay = delay - 1;
end
delay = delay - 1;
VAR9 = 1'b0;
VAR11 = 1'b0;
end
VAR9 = 1'b0;
default: begin
VAR9 = 1'b0;
VAR11 = 1'b0;
end
endcase
end
always @ (posedge clk or negedge reset) begin
if (~reset)
VAR16 = VAR17;
end
else begin
case (VAR16)
if (VAR12[0]==0 && VAR12[1]==1 && VAR12[5]==1) VAR16 = VAR3;
if (VAR12[2]==1) VAR16 = VAR1;
if ((VAR12[0]==1 && VAR12[5]==1) | (VAR12[1]==0 && VAR12[5]==1)) VAR16 = VAR5;
end
else if (VAR12[4] == 1) VAR16 = VAR6;
end
if (VAR12[3]==1) VAR16 = VAR14;
if (VAR12[3]==1) VAR16 = VAR10;
if (VAR12[2]==0) VAR16 = VAR17;
if (VAR12[4]==0) VAR16 = VAR17;
default:
VAR16 = VAR17;
endcase
end
end
endmodule | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_tag/bsg_tag_client.v | 4,571 | module MODULE1
import VAR26::VAR3;
(
input VAR3 VAR5
, input VAR55
, output VAR44 , output [VAR30-1:0] VAR56
);
localparam VAR58 = 1;
logic VAR2, VAR59, VAR31;
VAR25 @(posedge VAR5.clk)
begin
VAR2 <= VAR5.VAR6;
VAR31 <= VAR5.VAR52;
VAR59 <= VAR2;
end
wire VAR48 = ~VAR2 & VAR31;
wire VAR45 = VAR2;
wire VAR36 = ~VAR2 & ~VAR31;
wire VAR12 = VAR59 & VAR36;
logic [VAR30-1:0] VAR57, VAR34, VAR22, VAR4;
logic VAR54;
if (VAR30 == 1)
begin : VAR24
assign VAR4 = { VAR31 };
end
else
begin : VAR21
assign VAR4 = { VAR31, VAR57[VAR30-1:1] };
end
VAR35 #(.VAR30(VAR30),.VAR33(VAR33)) VAR27
(.VAR8 (VAR57 ) ,.VAR9(VAR4 ) ,.VAR51({ VAR30 {VAR45} }) ,.VAR20 (VAR22)
);
VAR19 #(.VAR30(VAR30), .VAR33(VAR33)) VAR47
(.VAR43(VAR5.clk)
,.VAR40(VAR22)
,.VAR32(VAR57)
);
if (VAR58 > 1)
always @(negedge VAR5.clk)
begin
if (VAR48 & ~(~VAR5.VAR6 & VAR5.VAR52))
VAR16 VAR28 (%VAR41)");
if (~VAR48 & (~VAR5.VAR6 & VAR5.VAR52))
VAR16 VAR17 (%VAR41)");
if (VAR12)
VAR53 %VAR14 (%VAR41)",VAR57);
end
logic VAR46, VAR23;
VAR10 #(.VAR30(1)) VAR7
(.VAR39 (VAR5.clk)
,.VAR49(VAR48)
,.VAR42 (VAR54 ^ VAR12)
,.VAR29 (VAR54)
,.VAR38 (VAR55 )
,.VAR50(VAR23)
);
wire VAR13 = (VAR46 ^ VAR23) & VAR5.en;
logic VAR18, VAR37;
VAR25 @(posedge VAR55)
begin
VAR46 <= VAR23;
VAR18 <= VAR13;
VAR37 <= VAR18;
end
VAR1 #(.VAR30(VAR30),.VAR33(VAR33)) VAR11
(.VAR43(VAR55)
,.VAR15(VAR18)
,.VAR40(VAR57)
,.VAR32(VAR34)
);
assign VAR44 = VAR37 & VAR5.en;
assign VAR56 = VAR34;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22a/sky130_fd_sc_hvl__o22a.blackbox.v | 1,360 | module MODULE1 (
VAR8 ,
VAR7,
VAR9,
VAR2,
VAR1
);
output VAR8 ;
input VAR7;
input VAR9;
input VAR2;
input VAR1;
supply1 VAR6;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/intra/ram_frame_row_32x480.v | 4,130 | module MODULE1 (
VAR4 ,
VAR20 ,
VAR9 ,
VAR19 ,
VAR16 ,
VAR5 ,
VAR17 ,
VAR1 ,
VAR10 ,
VAR6 ,
VAR12 ,
VAR18 ,
VAR3 ,
VAR15
);
parameter VAR8=32;
parameter VAR2=9;
input VAR4; input VAR20; input VAR9; input VAR19; input [VAR2-1:0] VAR16; input [VAR8-1:0] VAR17; output [VAR8-1:0] VAR5;
input VAR1; input VAR10; input VAR6; input VAR12; input [VAR2-1:0] VAR18; input [VAR8-1:0] VAR15; output [VAR8-1:0] VAR3;
reg [VAR8-1:0] VAR7[(1<<VAR2)-1:0];
reg [VAR8-1:0] VAR11;
reg [VAR8-1:0] VAR13;
always @(posedge VAR4) begin
if(!VAR20 && !VAR19)
VAR7[VAR16] <= VAR17;
end
always @(posedge VAR4) begin
if (!VAR20 && VAR19)
VAR11 <= VAR7[VAR16];
end
else
VAR11 <= 'VAR21;
end
assign VAR5 = VAR9 ? 'VAR14 : VAR11;
always @(posedge VAR1) begin
if(!VAR10 && !VAR12)
VAR7[VAR18] <= VAR15;
end
always @(posedge VAR1) begin
if (!VAR10 && VAR12)
VAR13 <= VAR7[VAR18];
end
else
VAR13 <= 'VAR21;
end
assign VAR3 = VAR6 ? 'VAR14 : VAR13;
endmodule | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/or1200_monitor2.v | 3,586 | module MODULE1;
wire [31:0] VAR34;
wire [31:0] VAR17;
wire [31:0] VAR4;
wire [31:0] VAR29;
wire [31:0] VAR23;
wire [31:0] VAR26;
wire [31:0] VAR30;
wire [31:0] VAR25;
wire [31:0] VAR27;
wire [31:0] VAR3;
wire [31:0] VAR9;
wire [31:0] VAR18;
wire [31:0] VAR8;
wire [31:0] VAR16;
wire [31:0] VAR11;
wire [31:0] VAR5;
wire [31:0] VAR2;
wire [31:0] VAR1;
wire [31:0] VAR22;
wire [31:0] VAR35;
wire [31:0] VAR13;
wire [31:0] VAR32;
wire [31:0] VAR10;
wire [31:0] VAR36;
wire [31:0] VAR21;
wire [31:0] VAR15;
wire [31:0] VAR14;
wire [31:0] VAR20;
wire [31:0] VAR33;
wire [31:0] VAR28;
wire [31:0] VAR6;
wire [31:0] VAR24;
assign VAR34 = VAR37.VAR31.VAR19.VAR12.VAR7[32*0+31:32*0];
assign VAR17 = VAR37.VAR31.VAR19.VAR12.VAR7[32*1+31:32*1];
assign VAR4 = VAR37.VAR31.VAR19.VAR12.VAR7[32*2+31:32*2];
assign VAR29 = VAR37.VAR31.VAR19.VAR12.VAR7[32*3+31:32*3];
assign VAR23 = VAR37.VAR31.VAR19.VAR12.VAR7[32*4+31:32*4];
assign VAR26 = VAR37.VAR31.VAR19.VAR12.VAR7[32*5+31:32*5];
assign VAR30 = VAR37.VAR31.VAR19.VAR12.VAR7[32*6+31:32*6];
assign VAR25 = VAR37.VAR31.VAR19.VAR12.VAR7[32*7+31:32*7];
assign VAR27 = VAR37.VAR31.VAR19.VAR12.VAR7[32*8+31:32*8];
assign VAR3 = VAR37.VAR31.VAR19.VAR12.VAR7[32*9+31:32*9];
assign VAR9 = VAR37.VAR31.VAR19.VAR12.VAR7[32*10+31:32*10];
assign VAR18 = VAR37.VAR31.VAR19.VAR12.VAR7[32*11+31:32*11];
assign VAR8 = VAR37.VAR31.VAR19.VAR12.VAR7[32*12+31:32*12];
assign VAR16 = VAR37.VAR31.VAR19.VAR12.VAR7[32*13+31:32*13];
assign VAR11 = VAR37.VAR31.VAR19.VAR12.VAR7[32*14+31:32*14];
assign VAR5 = VAR37.VAR31.VAR19.VAR12.VAR7[32*15+31:32*15];
assign VAR2 = VAR37.VAR31.VAR19.VAR12.VAR7[32*16+31:32*16];
assign VAR1 = VAR37.VAR31.VAR19.VAR12.VAR7[32*17+31:32*17];
assign VAR22 = VAR37.VAR31.VAR19.VAR12.VAR7[32*18+31:32*18];
assign VAR35 = VAR37.VAR31.VAR19.VAR12.VAR7[32*19+31:32*19];
assign VAR13 = VAR37.VAR31.VAR19.VAR12.VAR7[32*20+31:32*20];
assign VAR32 = VAR37.VAR31.VAR19.VAR12.VAR7[32*21+31:32*21];
assign VAR10 = VAR37.VAR31.VAR19.VAR12.VAR7[32*22+31:32*22];
assign VAR36 = VAR37.VAR31.VAR19.VAR12.VAR7[32*23+31:32*23];
assign VAR21 = VAR37.VAR31.VAR19.VAR12.VAR7[32*24+31:32*24];
assign VAR15 = VAR37.VAR31.VAR19.VAR12.VAR7[32*25+31:32*25];
assign VAR14 = VAR37.VAR31.VAR19.VAR12.VAR7[32*26+31:32*26];
assign VAR20 = VAR37.VAR31.VAR19.VAR12.VAR7[32*27+31:32*27];
assign VAR33 = VAR37.VAR31.VAR19.VAR12.VAR7[32*28+31:32*28];
assign VAR28 = VAR37.VAR31.VAR19.VAR12.VAR7[32*29+31:32*29];
assign VAR6 = VAR37.VAR31.VAR19.VAR12.VAR7[32*30+31:32*30];
assign VAR24 = VAR37.VAR31.VAR19.VAR12.VAR7[32*31+31:32*31];
endmodule | gpl-3.0 |
manu3193/TextEditor | SVN/hvsync_generator.v | 2,181 | module MODULE1(
input wire clk,
input wire reset,
output reg VAR4,
output reg VAR7,
output reg [10:0] VAR2,
output reg [10:0] VAR8,
output reg VAR13
);
parameter VAR1 = 11'd800;
parameter VAR16 = 11'd96;
parameter VAR15 = 11'd2;
parameter VAR12 = 11'd525;
parameter VAR3 = 11'd144 ;
parameter VAR14 = 11'd784 ;
parameter VAR5 = 11'd12 ;
parameter VAR6 = 11'd492;
reg VAR11;
reg [10:0] VAR9;
reg [10:0] VAR10;
always @(posedge clk or posedge reset)
begin
if(reset == 1)
VAR9 <= 0;
end
else
begin
if(VAR9 == VAR1 - 1)
begin VAR9<=0;
VAR11 <= 1;
end
else
begin
VAR9<=VAR9+1;
VAR11 <=0;
end
end
end
always @
begin
if(VAR10 < VAR15)
VAR7 = 1;
end
else
VAR7 = 0;
end
always @(posedge clk)
begin
if((VAR9<VAR14) && (VAR9>VAR3) && (VAR10<VAR6) && (VAR10>VAR5))
begin
VAR13 <= 1;
VAR2<= VAR9 - VAR3;
VAR8<= VAR10 - VAR5;
end
else
begin
VAR13 <= 0;
VAR2<=0;
VAR8<=0;
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.v | 2,135 | module MODULE1 (
VAR6,
VAR3,
VAR7 ,
VAR5 ,
VAR8,
VAR2
);
output VAR6;
input VAR3;
input VAR7 ;
input VAR5 ;
input VAR8;
input VAR2;
VAR1 VAR4 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR6,
VAR3,
VAR7 ,
VAR5
);
output VAR6;
input VAR3;
input VAR7 ;
input VAR5 ;
supply1 VAR8;
supply0 VAR2;
VAR1 VAR4 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrbp/sky130_fd_sc_ms__dfrbp.blackbox.v | 1,378 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR3 ,
VAR1 ,
VAR5
);
output VAR4 ;
output VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR5;
supply1 VAR2;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
ThomasLee969/verilog-homework | big_homework/cpu/CPU.v | 2,691 | module MODULE1(reset, clk);
input reset, clk;
reg [31:0] VAR36;
wire [31:0] VAR48;
always @(posedge reset or posedge clk)
if (reset)
VAR36 <= 32'h00000000;
else
VAR36 <= VAR48;
wire [31:0] VAR54;
assign VAR54 = VAR36 + 32'd4;
wire [31:0] VAR20;
VAR40 VAR18(.VAR23(VAR36), .VAR20(VAR20));
wire [1:0] VAR12;
wire [1:0] VAR32;
wire VAR52;
wire VAR37;
wire [1:0] VAR39;
wire [3:0] VAR5;
wire VAR43;
wire VAR16;
wire VAR49;
wire VAR50;
wire VAR1;
wire VAR22;
VAR3 VAR4(
.VAR9(VAR20[31:26]), .VAR28(VAR20[5:0]),
.VAR32(VAR32), .VAR52(VAR52), .VAR22(VAR22), .VAR12(VAR12),
.VAR37(VAR37), .VAR49(VAR49), .VAR39(VAR39),
.VAR50(VAR50), .VAR1(VAR1), .VAR43(VAR43), .VAR16(VAR16), .VAR5(VAR5));
wire [31:0] VAR24, VAR11, VAR25;
wire [4:0] VAR15;
assign VAR15 = (VAR12 == 2'b00)? VAR20[20:16]: (VAR12 == 2'b01)? VAR20[15:11]: 5'b11111;
VAR7 VAR38(.reset(reset), .clk(clk), .VAR22(VAR22),
.VAR34(VAR20[25:21]), .VAR10(VAR20[20:16]), .VAR15(VAR15),
.VAR26(VAR25), .VAR8(VAR24), .VAR30(VAR11));
wire [31:0] VAR33;
assign VAR33 = {VAR43? {16{VAR20[15]}}: 16'h0000, VAR20[15:0]};
wire [31:0] VAR6;
assign VAR6 = VAR16? {VAR20[15:0], 16'h0000}: VAR33;
wire [4:0] VAR13;
wire VAR14;
VAR19 VAR27(.VAR5(VAR5), .VAR28(VAR20[5:0]), .VAR13(VAR13), .VAR14(VAR14));
wire [31:0] VAR2;
wire [31:0] VAR46;
wire [31:0] VAR17;
wire VAR41;
assign VAR2 = VAR50? {17'h00000, VAR20[10:6]}: VAR24;
assign VAR46 = VAR1? VAR6: VAR11;
VAR42 VAR47(.VAR21(VAR2), .VAR53(VAR46), .VAR13(VAR13), .VAR14(VAR14), .out(VAR17), .VAR35(VAR41));
wire [31:0] VAR51;
VAR44 VAR29(.reset(reset), .clk(clk), .VAR23(VAR17), .VAR26(VAR11), .VAR51(VAR51), .VAR37(VAR37), .VAR49(VAR49));
assign VAR25 = (VAR39 == 2'b00)? VAR17: (VAR39 == 2'b01)? VAR51: VAR54;
wire [31:0] VAR31;
assign VAR31 = {VAR54[31:28], VAR20[25:0], 2'b00};
wire [31:0] VAR45;
assign VAR45 = (VAR52 & VAR41)? VAR54 + {VAR6[29:0], 2'b00}: VAR54;
assign VAR48 = (VAR32 == 2'b00)? VAR45: (VAR32 == 2'b01)? VAR31: VAR24;
endmodule | mit |
trevortheblack/NewLondo16 | Verilog/RFT/asl.v | 2,087 | module MODULE1(VAR4, VAR2, VAR6, VAR3, VAR8);
input [31:0] VAR4, VAR2;
input [3:0] VAR6;
output [31:0] VAR3;
input VAR8;
wire VAR7 = |VAR2[31:5];
wire VAR5 = VAR2[4:0];
wire [4:0] VAR1 = (VAR5== 32'b0) ?
( {1'b0, VAR6} + 5'b1) : (VAR5 + {1'b0, VAR6});
assign VAR3 = (VAR7==1'b1) ? 32'b0 : (
(VAR1 == 5'b00000) ? VAR4[31:0] :
(VAR1 == 5'b00001) ? {VAR4[30:0], 01'b0 } :
(VAR1 == 5'b00010) ? {VAR4[29:0], 02'b0 } :
(VAR1 == 5'b00011) ? {VAR4[28:0], 03'b0 } :
(VAR1 == 5'b00100) ? {VAR4[27:0], 04'b0 } :
(VAR1 == 5'b00101) ? {VAR4[26:0], 05'b0 } :
(VAR1 == 5'b00110) ? {VAR4[25:0], 06'b0 } :
(VAR1 == 5'b00111) ? {VAR4[24:0], 07'b0 } :
(VAR1 == 5'b01000) ? {VAR4[23:0], 08'b0 } :
(VAR1 == 5'b01001) ? {VAR4[22:0], 09'b0 } :
(VAR1 == 5'b01010) ? {VAR4[21:0], 10'b0 } :
(VAR1 == 5'b01011) ? {VAR4[20:0], 11'b0 } :
(VAR1 == 5'b01100) ? {VAR4[19:0], 12'b0 } :
(VAR1 == 5'b01101) ? {VAR4[18:0], 13'b0 } :
(VAR1 == 5'b01110) ? {VAR4[17:0], 14'b0 } :
(VAR1 == 5'b01111) ? {VAR4[16:0], 15'b0 } :
(VAR1 == 5'b10000) ? {VAR4[15:0], 16'b0 } :
(VAR1 == 5'b10001) ? {VAR4[14:0], 17'b0 } :
(VAR1 == 5'b10010) ? {VAR4[13:0], 18'b0 } :
(VAR1 == 5'b10011) ? {VAR4[12:0], 19'b0 } :
(VAR1 == 5'b10100) ? {VAR4[11:0], 20'b0 } :
(VAR1 == 5'b10101) ? {VAR4[10:0], 21'b0 } :
(VAR1 == 5'b10110) ? {VAR4[09:0], 22'b0 } :
(VAR1 == 5'b10111) ? {VAR4[08:0], 23'b0 } :
(VAR1 == 5'b11000) ? {VAR4[07:0], 24'b0 } :
(VAR1 == 5'b11001) ? {VAR4[06:0], 25'b0 } :
(VAR1 == 5'b11010) ? {VAR4[05:0], 26'b0 } :
(VAR1 == 5'b11011) ? {VAR4[04:0], 27'b0 } :
(VAR1 == 5'b11100) ? {VAR4[03:0], 28'b0 } :
(VAR1 == 5'b11101) ? {VAR4[02:0], 29'b0 } :
(VAR1 == 5'b11110) ? {VAR4[01:0], 30'b0 } :
(VAR1 == 5'b11111) ? {VAR4[00:0], 31'b0 } : 32'b0);
endmodule | mit |
davidkoltak/tawas-core | ip/enet/rtl/sgmii_fifo.v | 2,795 | module MODULE1
(
input VAR9,
input VAR13,
input VAR4,
input [8:0] VAR22,
input VAR7,
output VAR15,
output [8:0] VAR23,
input VAR20,
output VAR25
);
parameter VAR2 = 32; parameter VAR11 = 12;
reg [5:0] VAR19;
wire VAR26 = (!VAR7 || (VAR19 == VAR11));
always @ (posedge VAR13 or posedge VAR9)
if (VAR9)
VAR19 <= 6'd0;
else if (!VAR7)
VAR19 <= 6'd0;
else if (!VAR26)
VAR19 <= VAR19 + 6'd1;
reg [1:0] VAR5;
reg [5:0] VAR12;
reg [5:0] VAR10;
reg [5:0] VAR8;
reg [1:0] VAR24;
reg [5:0] VAR1;
reg [5:0] VAR17;
reg [5:0] VAR16;
always @ (posedge VAR13)
VAR5 <= (VAR26) ? VAR24 : 2'd0;
always @ (posedge VAR4 or posedge VAR9)
if (VAR9)
VAR24 <= 2'b00;
else
case (VAR5)
2'b00: VAR24 <= 2'b01;
2'b01: VAR24 <= 2'b11;
2'b11: VAR24 <= 2'b10;
default: VAR24 <= 2'b00;
endcase
wire [5:0] VAR18 = (VAR12 == (VAR2 - 1)) ? 6'd0 : VAR12 + 6'd1;
wire VAR14 = (VAR18 == VAR8);
always @ (posedge VAR13 or posedge VAR9)
if (VAR9)
begin
VAR12 <= 6'd0;
VAR10 <= 6'd0;
VAR8 <= 6'd0;
end
else
begin
if (VAR7 && !VAR14)
VAR12 <= VAR18;
case (VAR5)
2'b01: VAR10 <= VAR12;
2'b10: VAR8 <= VAR16;
endcase
end
wire [5:0] VAR6 = (VAR17 == (VAR2 - 1)) ? 6'd0 : VAR17 + 6'd1;
wire VAR3 = (VAR17 == VAR1);
always @ (posedge VAR4 or posedge VAR9)
if (VAR9)
begin
VAR1 <= 6'd0;
VAR17 <= 6'd0;
VAR16 <= 6'd0;
end
else
begin
if (VAR20 && !VAR3)
VAR17 <= VAR6;
case (VAR24)
2'b01: VAR16 <= VAR17;
2'b10: VAR1 <= VAR10;
endcase
end
reg [8:0] VAR21[(VAR2 - 1):0];
always @ (posedge VAR13)
if (VAR7)
VAR21[VAR12] <= VAR22[8:0];
assign VAR15 = VAR14;
assign VAR25 = VAR3;
assign VAR23 = VAR21[VAR17];
endmodule | mit |
MegaShow/college-programming | Homework/Computer Organization and Interfacing/Single Cycle CPU/Single Cycle CPU.srcs/sources_1/new/ControlUnit.v | 7,883 | module MODULE1(
input [5:0] VAR8,
input VAR4,
output reg VAR10,
output reg [1:0] VAR7,
output reg VAR13,
output reg VAR5,
output reg VAR14,
output reg [2:0] VAR11,
output reg VAR2,
output reg VAR6,
output reg VAR9,
output reg VAR12,
output reg VAR3,
output reg VAR1
); | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_pipeline.v | 22,519 | module MODULE1 #(
parameter VAR43 = 128, parameter VAR48 = "VAR50", parameter VAR14 = 1,
parameter VAR15 = (VAR43 == 128) ? 2 : 1, parameter VAR22 = VAR43 / 8 ) (
input [VAR43-1:0] VAR4, input VAR21, output VAR7, input [VAR22-1:0] VAR58, input VAR28, input [3:0] VAR18,
output [VAR43-1:0] VAR2, output VAR24, output VAR29, output VAR10, input VAR52, output VAR32, output [VAR15-1:0] VAR57, output VAR36, output VAR33, output VAR45, input VAR26,
input VAR37, input VAR51, input VAR53 );
reg [VAR43-1:0] VAR20;
reg VAR44;
reg [VAR22-1:0] VAR9;
reg [3:0] VAR49;
reg VAR11;
reg VAR5;
reg VAR31;
reg VAR30;
reg VAR41;
wire VAR19;
reg VAR56;
wire VAR61 = VAR21 && VAR7;
wire VAR60 = VAR61 && VAR28;
generate
if(VAR43 == 128) begin : VAR47
assign VAR2 = {VAR20[31:0],
VAR20[63:32],
VAR20[95:64],
VAR20[127:96]};
end
else if(VAR43 == 64) begin : VAR27
assign VAR2 = {VAR20[31:0], VAR20[63:32]};
end
else begin : VAR46
assign VAR2 = VAR20;
end
endgenerate
assign VAR24 = VAR44 && !VAR31;
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
if(VAR24 && VAR10 && VAR52 && !VAR29) begin
end
else if((VAR31 && VAR29 && VAR10) || !VAR26) begin
end
end
end
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
if(VAR61 && !VAR28) begin
end
else if(VAR61) begin
end
end
end
generate
if(VAR48 == "VAR62") begin : VAR55
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
if(!VAR26)
begin
end
else if(!VAR41 && VAR7) begin
end
end
end
assign VAR19 = VAR56;
end
else begin : VAR34
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
if(VAR30 && !VAR26 && !VAR60)
begin
end
else if(VAR60) begin
end
end
end
assign VAR19 = VAR56 || !VAR26;
end
endgenerate
generate
if(VAR43 == 128) begin : VAR3
wire VAR42 = VAR9[7];
wire VAR16 = VAR9[11];
wire VAR35 = VAR9[15];
assign VAR57[1] = VAR16;
assign VAR57[0] = VAR35 || (VAR42 && !VAR16);
end
else if(VAR43 == 64) begin : VAR8
assign VAR57 = VAR9[7];
end
else begin : VAR25
assign VAR57 = 1'b0;
end
endgenerate
assign VAR29 = VAR11;
assign VAR45 = VAR49[0];
assign VAR36 = VAR49[1];
assign VAR33 = VAR49[2];
assign VAR32 = VAR49[3];
generate
reg VAR6;
if(VAR48 == "VAR50") begin : VAR12
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
end
end
assign VAR10 = VAR6;
assign VAR7 = VAR37;
end
else begin : VAR13
reg [VAR43-1:0] VAR17;
reg VAR1;
reg [VAR22-1:0] VAR39;
reg VAR54;
reg [3:0] VAR59;
reg VAR23;
wire VAR40;
reg VAR38;
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
if(!VAR7) begin
end
else begin
end
end
end
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
if(!VAR40) begin
if(VAR38) begin
end
else begin
end
end
end
end
assign VAR40 = VAR10 && !VAR52;
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
end
end
assign VAR10 = VAR44 && !VAR19;
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
if(VAR41 && !VAR60) begin
end
else if(VAR26) begin
end
else begin
end
end
end
assign VAR7 = VAR5;
end
always @(posedge VAR51) begin
if(VAR53) begin
end
else begin
if(VAR30 && !VAR26 && !VAR60) begin
end
else if(VAR60) begin
end
end
end
endgenerate
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp.functional.pp.v | 1,843 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR15 ,
VAR7,
VAR6 ,
VAR5 ,
VAR14 ,
VAR10
);
output VAR13 ;
input VAR4 ;
input VAR15 ;
input VAR7;
input VAR6 ;
input VAR5 ;
input VAR14 ;
input VAR10 ;
wire VAR8;
wire VAR2 ;
not VAR9 (VAR2 , VAR7 );
VAR3 VAR1 VAR11 (VAR8 , VAR15, VAR4, VAR2, , VAR6, VAR5);
buf VAR12 (VAR13 , VAR8 );
endmodule | apache-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_spram_1024x8.v | 8,581 | module MODULE1(
VAR9, VAR21, VAR15,
clk, rst, VAR13, VAR7, VAR24, addr, VAR3, VAR32
);
parameter VAR16 = 10;
parameter VAR19 = 8;
input VAR9;
input [VAR28 - 1:0] VAR15;
output VAR21;
input clk; input rst; input VAR13; input VAR7; input VAR24; input [VAR16-1:0] addr; input [VAR19-1:0] VAR3; output [VAR19-1:0] VAR32;
assign VAR21 = VAR9;
VAR5 #(VAR19, 1<<VAR16, VAR16) VAR33(
VAR38 VAR33(
VAR5 VAR33(
.VAR9(VAR9),
.VAR21(VAR21),
.VAR15(VAR15),
.VAR14(clk),
.VAR41(~VAR13),
.VAR31(~VAR7),
.VAR17(addr),
.VAR10(VAR3),
.VAR11(~VAR24),
.VAR1(VAR32)
);
VAR36 VAR36(
.VAR37(~VAR7),
.VAR34(),
.VAR44(~VAR24),
.VAR12(),
.VAR42(),
.VAR23(addr),
.VAR30(addr),
.VAR3(VAR3),
.VAR32(VAR32)
);
VAR46 VAR46(
.clk(clk),
.VAR47(addr),
.VAR4(VAR3),
.VAR7(VAR7),
.VAR24(VAR24),
.VAR45(VAR13),
.VAR35(VAR32)
);
VAR49 #(1<<VAR16, VAR16-1, VAR19-1) VAR8(
VAR40 VAR8(
VAR49 VAR8(
.VAR9(VAR9),
.VAR21(VAR21),
.VAR15(VAR15),
.VAR48(clk),
.VAR22(addr),
.VAR25(VAR3),
.VAR31(~VAR7),
.VAR41(~VAR13),
.VAR11(~VAR24),
.VAR39(VAR32)
);
VAR18 VAR6(
.VAR14(clk),
.VAR27(rst),
.VAR29(addr),
.VAR25(VAR3[3:0]),
.VAR2(VAR13),
.VAR43(VAR7),
.VAR20(VAR32[3:0])
);
VAR18 VAR26(
.VAR14(clk),
.VAR27(rst),
.VAR29(addr),
.VAR25(VAR3[7:4]),
.VAR2(VAR13),
.VAR43(VAR7),
.VAR20(VAR32[7:4])
);
wire wr;
assign wr = VAR13 & VAR7; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.pp.symbol.v | 1,200 | module MODULE1 (
input VAR1 ,
input VAR4,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_cnt_lead0_lvl1.v | 1,755 | module MODULE1 (
din,
VAR1,
VAR2,
VAR3
);
input [3:0] din;
output VAR1; output VAR2; output VAR3;
wire VAR1;
wire VAR2;
wire VAR3;
assign VAR1= (!(|din[3:0]));
assign VAR2= (!(|din[3:2]));
assign VAR3= ((!VAR2) && (!din[3]))
|| (VAR2 && (!din[1]));
endmodule | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/add_routing_header.v | 1,579 | module MODULE1
parameter VAR12 = 1)
(input clk, input reset, input VAR9,
input [35:0] VAR7, input VAR5, output VAR8,
output [35:0] VAR6, output VAR4, input VAR10);
reg [1:0] VAR2;
wire [1:0] VAR1 = VAR11;
wire [15:0] VAR3 = VAR7[15:0];
always @(posedge clk)
if(reset)
VAR2 <= VAR12 ? 0 : 1;
else
if(VAR4 & VAR10)
if(VAR6[33])
VAR2 <= VAR12 ? 0 : 1;
else
if(VAR2 != 3)
VAR2 <= VAR2 + 1;
assign VAR6 = (VAR2 == 0) ? {4'b0001, 13'b0, VAR1, 1'b1, VAR3[13:0],2'b00} :
(VAR2 == 1) ? {3'b000, (VAR12 ? 1'b0: 1'b1), VAR7[31:0]} :
VAR7[35:0];
assign VAR8 = VAR10 & (VAR2 != 0);
assign VAR4 = VAR5;
endmodule | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_axis_fifo/address_gray_pipelined.v | 5,149 | module MODULE1 (
input VAR2,
input VAR11,
input VAR27,
output reg VAR14,
output [VAR12-1:0] VAR10,
output [VAR12-1:0] VAR19,
output reg [VAR12:0] VAR4,
input VAR24,
input VAR1,
output reg VAR21,
input VAR17,
output reg VAR3,
output [VAR12-1:0] VAR23,
output reg [VAR12:0] VAR15
);
parameter VAR12 = 4;
reg [VAR12:0] VAR23 = 'h00;
reg [VAR12:0] VAR25;
wire [VAR12:0] VAR8;
reg [VAR12:0] VAR19 = 'h00;
reg [VAR12:0] VAR10;
wire [VAR12:0] VAR26;
assign VAR23 = VAR23[VAR12-1:0];
assign VAR10 = VAR10[VAR12-1:0];
assign VAR19 = VAR19[VAR12-1:0];
always @
begin
if (VAR27 && VAR14)
VAR10 <= VAR19 + 1;
end
else
VAR10 <= VAR19;
end
always @(posedge VAR2)
begin
if (VAR11 == 1'b0) begin
VAR19 <= 'h00;
end else begin
VAR19 <= VAR10;
end
end
VAR18 #(
.VAR28(VAR12 + 1)
) VAR6 (
.VAR13(VAR24),
.VAR16(VAR1),
.VAR9(VAR2),
.VAR20(VAR11),
.VAR7(VAR23),
.VAR5(VAR26)
);
VAR18 #(
.VAR28(VAR12 + 1)
) VAR22 (
.VAR13(VAR2),
.VAR16(VAR11),
.VAR9(VAR24),
.VAR20(VAR1),
.VAR7(VAR19),
.VAR5(VAR8)
);
always @(posedge VAR24)
begin
if (VAR1 == 1'b0) begin
VAR21 <= 1'b1;
VAR3 <= 1'b1;
VAR15 <= 2**VAR12;
end else begin
VAR21 <= (VAR8[VAR12] == VAR25[VAR12] ||
VAR8[VAR12-1:0] != VAR25[VAR12-1:0]);
VAR3 <= VAR8 == VAR25;
VAR15 <= VAR8 - VAR25 + 2**VAR12;
end
end
always @(posedge VAR2)
begin
if (VAR11 == 1'b0) begin
VAR14 <= 1'b0;
VAR4 <= 'h00;
end else begin
VAR14 <= VAR26 != VAR10;
VAR4 <= VAR26 - VAR10;
end
end
endmodule | gpl-3.0 |
CMCammarano/EE-454-Portable-Ultrasound | Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra.v | 10,498 | module MODULE1 (
input clk,
input [1:0] VAR20,
input VAR10,
input ack,
input VAR19,
input VAR4,
output [4095:0] VAR17,
output [7:0] VAR16
);
reg [3:0] VAR9;
reg VAR14;
wire [8191:0] VAR1;
wire [4095:0] VAR6;
wire [4095:0] VAR12;
wire [7:0] VAR15;
wire [7:0] VAR2;
VAR3 VAR5 (
.clk (clk),
.VAR10 (VAR10),
.VAR14 (VAR14),
.VAR1 (VAR1),
.VAR6 (VAR6),
.VAR12 (VAR12),
.VAR15 (VAR15),
.VAR2 (VAR2)
);
reg[4:0] state;
localparam
VAR8 = 5'b00001,
VAR13 = 5'b00010,
VAR18 = 5'b00100,
VAR7 = 5'b01000,
VAR11 = 5'b10000;
assign VAR1 = 8192'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111000001010001000000001100000001100000011000010101000010010001000100010101000101100000100100001001000101100000010100011110000011100001001000001110000010110000000000000111000010010000011000011000000110000001111100011111000111100001010000010101000101100000110100010000000111000000101000011010000000010001000100011001000001000000101000001111000110010000101100010010000101010001100000001010000101110001000100001011000111100000110100010011000110010000101000000001000011010001111100011101000110110000010000011111000001000001011100000111000101100000000100000010000011100000001000000110000011010001011000011011000101100001100100001101000011000001110100011110000111010000010000011010000100000001000100001100000000100000001000000101000101010001111100010110000000000001111100010000000000000001001000001001000011110001100100000100000110100001100000011100000100010001110100011011000110000001100000001101000101100000100100011001000001110001000000000001000100010000111100000111000010100000100100011111000001010000000100000101000000000001011000001111000011110000011100011000000101010000110100011001000001000000101100010111000111000001011000000011000100100001000000010100000000000000011000011101000010100000010000001101000101110001100100001110000001110000000100001100000001110000011000010010000111110000000100000100000110100000110000010111000100100001000100001010000001100000001100000011000100100000010000011101000000110000101000000100000110100000011000010000000001110000000000010011000001110000110000010111000000000001110000011100000101100000000000000101000100110000011100011110000000000000000000001110000000010001100100010001000111010001010000000111000010010000111100010110000100100001010100011111000100100001000000010100000011100000011000000011000010100001100100011110000011100001111000011001000000110001110000001010000001010000111100011000000010110001110100010101000011110000001100011111000110000001111000011111000001100000100100010110000100110001101000011101000011000001011000011001000101000000011100000011000111000001101100001001000000110001001100011100000000010001110000010001000100010000101000000100000000100001110000010100000011100000000100010010000001000000111100001100000110000000011000000010000010010000011000011111000000110001110100000101000010100000011000001011000000110000110000011110000011010000101100000101000000000000111000011111000001000000001000001111000011010000100100000111000000110001100100010010000110110000110100001000000000110000000000000000000001110000010000010001000111010001110100010000000101100000110100010011000111110000011100001010000011110001010000010001000001000000101100000101000001010001111100000010000100000000010000011111000101010000100100010011000000010000000100001011000001110000111000001101000001010000001000001100000010110001010000000110000011010000100100011110000100000001101000011110000100100000000000000101000011110000011100011010000010100000100100010000000111000001101100000010000101010001010000011110000110000001111100001011000100000000001100010111000000110001010000010010000001010001000000000100000001000001010100001101000111000000010000001101000110010000100100010010000010100000100100000000000111000000001100001100000100000001001000000101000101000000010000010010000111010000011000010111000010000001010000001111000001010000111100011100000001100000001100011011000100010001101000010100000011100000011000010011000101100000011000001100000000000001000100011001000000100000110000011011000011010000111100001110000011000001001100011100000010110001110000001001000100010001110000000111000101010000001000010110000111010001000100011010000010110001110100011110000111100001100000010111000011110000111100000111000000000001000100001001000110100000100000001110000100100000011100000110000010000001000100010100000101110001011000010100000011010001000000000001000010000001011000000101000010110001011100010011000100000000011000001111000101010000011100001101000101000000010100000100000000100001000100001010000011000000111000000110000111000000001000000010000010110000010100001100000100100000011000001101000010010000111100001011000111000000100100011010000101010001011100001011000100100001100100000101000111110000110100001100000110000001111000001111000000000000000100001101000110100000011000011100000101100001101100000110000100100001100000000101000101110000101000001100000110000000011100001001000010010000011100011110000101110000000000000000000100000000001000010101000111010000111000000010000101010001111000001001000111100000111000011101000001100000110000011110000001100001010100010111000110110000000000001001000001110001000100001100000101010000010000001000000011100000011000010010000111100001111000000001000010110000110100010110000100110000011100010101000001010001001100001010000011000001111000001100000001010000110000000001000011010000001100011110000101100000010000001001000101010001010100011111000101100000000000011101000110110000101000001111000100010001111000000000000111010001110100011000000111010001111100010001000101100000010000001010000100110001110000000111000010000000110000010100000100010000100100000001000001100001110000000001000000010001110000000001000100100001111000011000000110010001111100011001;
assign VAR17 = VAR6;
always @(posedge VAR20, negedge VAR10) begin
if (!VAR10) begin
VAR9 <= 0;
VAR14 <= 0;
state <= VAR8;
end
else begin
case (state)
VAR8: begin
VAR9 <= 0;
if (ack) begin
state <= VAR13;
end
end
VAR13: begin
VAR9 <= VAR9 + 1;
if (VAR9 >= 9) begin
state <= VAR18;
end
end
VAR18: begin
VAR14 <= 1;
state <= VAR7;
end
VAR7: begin
state <= VAR11;
end
VAR11: begin
if (ack) begin
state <= VAR8;
end
end
endcase
end
end
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.behavioral.pp.v | 1,407 | module MODULE1( VAR9, VAR10, VAR6, VAR5, VAR7, VAR3, VAR4 );
input VAR6, VAR7, VAR10, VAR5;
inout VAR3, VAR4;
output VAR9;
VAR2 VAR8(.VAR9(VAR9),.VAR10(VAR10),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4));
VAR2 VAR1(.VAR9(VAR9),.VAR10(VAR10),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ha/sky130_fd_sc_ls__ha_4.v | 2,184 | module MODULE2 (
VAR10,
VAR9 ,
VAR2 ,
VAR3 ,
VAR7,
VAR8,
VAR1 ,
VAR4
);
output VAR10;
output VAR9 ;
input VAR2 ;
input VAR3 ;
input VAR7;
input VAR8;
input VAR1 ;
input VAR4 ;
VAR6 VAR5 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR10,
VAR9 ,
VAR2 ,
VAR3
);
output VAR10;
output VAR9 ;
input VAR2 ;
input VAR3 ;
supply1 VAR7;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR4 ;
VAR6 VAR5 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
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