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jhennessy/parallella-hw-old | fpga/hdl/axi/axi_elink_if.v | 12,111 | module MODULE1 (
VAR83, VAR65, VAR34, VAR24,
VAR26, VAR21, VAR27,
VAR63, VAR49, VAR20,
VAR53, VAR64, VAR36,
VAR80, VAR99, VAR57,
VAR76, VAR81, VAR87,
VAR39, VAR67, VAR18,
VAR28, VAR82, VAR7,
VAR72, VAR38, VAR45,
VAR85, VAR25, VAR5,
VAR8, VAR55, reset, VAR3, VAR52,
VAR32, VAR58, VAR47,
VAR68, VAR30, VAR22,
VAR70, VAR46, VAR43,
VAR66, VAR15, VAR95,
VAR94, VAR10, VAR56,
VAR88, VAR91, VAR60,
VAR1, VAR98, VAR35,
VAR62, VAR40, VAR11,
VAR29
);
input VAR8;
input VAR55;
input reset;
input VAR3;
input VAR52;
input [1:0] VAR32;
input [3:0] VAR58;
input [31:0] VAR47;
input [31:0] VAR68;
input [31:0] VAR30;
input VAR22;
input VAR70;
input VAR46;
input VAR43;
input [1:0] VAR66;
input [3:0] VAR15;
input [31:0] VAR95;
input [31:0] VAR94;
input [31:0] VAR10;
input VAR56;
input VAR88;
input VAR91;
input VAR60;
input [1:0] VAR1;
input [3:0] VAR98;
input [31:0] VAR35;
input [31:0] VAR62;
input [31:0] VAR40;
input VAR11;
input VAR29;
output VAR83;
output VAR65;
output VAR34;
output VAR24;
output [1:0] VAR26;
output [3:0] VAR21;
output [31:0] VAR27;
output [31:0] VAR63;
output [31:0] VAR49;
output VAR20;
output VAR53;
output VAR64;
output [1:0] VAR36;
output [3:0] VAR80;
output [31:0] VAR99;
output [31:0] VAR57;
output [31:0] VAR76;
output VAR81;
output VAR87;
output VAR39;
output VAR67;
output [1:0] VAR18;
output [3:0] VAR28;
output [31:0] VAR82;
output [31:0] VAR7;
output [31:0] VAR72;
output VAR38;
output VAR45;
output VAR85;
output VAR25;
output [1:0] VAR5;
reg VAR59;
wire VAR89;
wire VAR96;
wire VAR100;
wire VAR84;
wire [1:0] VAR92;
wire [3:0] VAR77;
wire [31:0] VAR74;
wire [31:0] VAR14;
wire [31:0] VAR16;
wire VAR37;
wire VAR78;
wire VAR12;
wire VAR42;
wire [1:0] VAR33;
wire [3:0] VAR17;
wire [31:0] VAR51;
wire [31:0] VAR2;
wire [31:0] VAR6;
wire VAR31;
wire VAR69;
VAR93 VAR93
(
.VAR83 (VAR83),
.VAR65 (VAR65),
.VAR19 (VAR39), .VAR23 (VAR67), .VAR90 (VAR18[1:0]), .VAR50 (VAR28[3:0]), .VAR75 (VAR82[31:0]), .VAR44 (VAR7[31:0]), .VAR79 (VAR72[31:0]), .VAR54 (VAR38), .VAR9 (VAR45), .VAR85 (VAR85),
.VAR25 (VAR25),
.VAR5 (VAR5[1:0]),
.VAR12 (VAR12), .VAR42 (VAR42), .VAR33 (VAR33[1:0]), .VAR17 (VAR17[3:0]), .VAR51 (VAR51[31:0]), .VAR2 (VAR2[31:0]), .VAR6 (VAR6[31:0]), .VAR31 (VAR31), .VAR69 (VAR69), .VAR8 (VAR8),
.VAR55 (VAR55),
.reset (reset),
.VAR101 (VAR91), .VAR97 (VAR60), .VAR4 (VAR1[1:0]), .VAR61 (VAR98[3:0]), .VAR13 (VAR35[31:0]), .VAR48 (VAR62[31:0]), .VAR71 (VAR40[31:0]), .VAR41 (VAR11), .VAR86 (VAR29), .VAR100 (VAR100), .VAR84 (VAR84), .VAR92 (VAR92[1:0]), .VAR77 (VAR77[3:0]), .VAR74 (VAR74[31:0]), .VAR14 (VAR14[31:0]), .VAR16 (VAR16[31:0]), .VAR37 (VAR37), .VAR78 (VAR78));
always @ (posedge VAR8 or posedge reset)
if(reset)
VAR59 <= 1'b0;
else
VAR59 <= ~VAR59;
assign VAR81 = VAR3 & ~VAR59 |
VAR31;
assign VAR87 = VAR3 & ~VAR59 |
VAR69;
assign VAR20 = VAR46 & VAR59 |
VAR31;
assign VAR89 = VAR3 & ~VAR20;
assign VAR100 = VAR3 | VAR46;
assign VAR84 = VAR89 ? VAR52 :
VAR43;
assign VAR92[1:0] = VAR89 ? VAR32[1:0]:
VAR66[1:0];
assign VAR77[3:0] = VAR89 ? VAR58[3:0]:
VAR15[3:0];
assign VAR74[31:0] = VAR89 ? VAR47[31:0]:
VAR95[31:0];
assign VAR14[31:0] = VAR89 ? VAR68[31:0]:
VAR94[31:0];
assign VAR16[31:0] = VAR89 ? VAR30[31:0]:
VAR10[31:0];
assign VAR96 = (VAR51[31:20] == VAR73);
assign VAR53 = VAR12 & VAR96;
assign VAR34 = VAR12 & ~VAR96;
assign VAR64 = VAR42;
assign VAR36[1:0] = VAR33[1:0];
assign VAR80[3:0] = VAR17[3:0];
assign VAR99[31:0] = VAR51[31:0];
assign VAR57[31:0] = VAR2[31:0];
assign VAR76[31:0] = VAR6[31:0];
assign VAR24 = VAR42;
assign VAR26[1:0] = VAR33[1:0];
assign VAR21[3:0] = VAR17[3:0];
assign VAR27[31:0] = VAR51[31:0];
assign VAR63[31:0] = VAR2[31:0];
assign VAR49[31:0] = VAR6[31:0];
assign VAR37 = VAR96 & VAR56 |
~VAR96 & VAR22;
assign VAR78 = VAR96 & VAR88 |
~VAR96 & VAR70;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp_8.v | 2,130 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR4 ,
VAR6,
VAR5,
VAR3 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR8 ;
VAR7 VAR1 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR2 ,
VAR9 ,
VAR4
);
output VAR2 ;
input VAR9 ;
input VAR4;
supply1 VAR6;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR8 ;
VAR7 VAR1 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
hakehuang/pycpld | ips/ip/i2c_master/I2C_wr.v | 10,645 | module MODULE1(
VAR37,VAR14,ack,VAR9,clk,VAR1,VAR42,VAR44
);
input VAR9,VAR1,VAR42,clk;
output VAR14,ack;
inout [7:0] VAR44;
inout VAR37;
reg VAR20,VAR49;
reg[7:0] VAR10;
reg VAR14,ack,VAR50,VAR34,VAR53;
reg VAR48;
reg VAR39;
reg[8:0] VAR5;
reg[9:0] VAR6;
reg VAR36;
reg[6:0] VAR7;
reg[7:0] VAR12;
reg[7:0] VAR19;
reg[7:0] VAR21;
assign VAR37 = (VAR20) ? VAR10[7] : 1'VAR32;
assign VAR44 = (VAR49) ? VAR12 : 8'VAR26;
parameter VAR16 = 10'd32,
VAR30 = 10'd32;
parameter
VAR38 = 10'b0000001,
ready = 10'b0000010,
VAR28 = 11'b0000100,
VAR18 = 11'b0001000,
VAR51 = 11'b0010000,
VAR27 = 11'b0100000,
VAR29 = 11'b1000000;
parameter
VAR3 = 9'b000000001,
VAR45 = 9'b000000010,
VAR35 = 9'b000000100,
VAR15 = 9'b000001000,
VAR52 = 9'b000010000,
VAR13 = 9'b000100000,
VAR54 = 9'b001000000,
VAR17 = 9'b010000000,
VAR43 = 9'b100000000;
parameter
VAR31 = 10'b0000000001,
VAR33 = 10'b0000000010,
VAR40 = 10'b0000000100,
VAR2 = 10'b0000001000,
VAR24 = 10'b0000010000,
VAR11 = 10'b0000100000,
VAR8 = 10'b0001000000,
VAR46 = 10'b0010000000,
VAR23 = 10'b0100000000,
VAR4 = 10'b1000000000;
always @(negedge clk or negedge VAR9) begin
if(!VAR9)
VAR14 <= 1'b0;
end
else
VAR14 <= ~VAR14;
end
always @(posedge clk or negedge VAR9) begin
if(!VAR9)begin
VAR20 <= 1'b0;
ack <= 1'b0;
VAR34 <= 1'b0;
VAR50 <= 1'b0;
VAR53 <= 1'b0;
VAR7 <= VAR38;
VAR39 <= 'h0;
VAR5<= VAR3;
VAR6 <= VAR31;
VAR36 <= 'h0;
VAR19 <= 'h1;
VAR21 <= 'h1;
end
else begin
case(VAR7)
VAR38:begin
VAR49 <= 'h0;
VAR20 <= 'h0;
if(VAR1) begin
VAR50 <= 1'b1;
VAR7 <= ready;
end
else if(VAR42)begin
VAR34 <= 1'b1;
VAR7 <= ready;
end
else begin
VAR50 <= 1'b0;
VAR34 <= 1'b0;
VAR7 <=VAR38;
end
end
ready:begin
VAR53 <= 1'b0;
VAR7 <= VAR28;
end
VAR28:begin
if(VAR53==1'b0)
VAR25;
end
else begin
if(VAR50 == 1'b1)
VAR10 <= {1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0};
end
else
VAR10 <= {1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b1};
VAR53 <= 1'b0;
VAR5 <= VAR45;
VAR7 <= VAR18;
end
end
VAR18:begin
if(VAR53==1'b0)
VAR22;
end
else begin
if(VAR34==1'b1)begin
VAR10 <= 'h0;
VAR20 <= 1'b0;
VAR53 <= 1'b0;
VAR19 <= 1'b1;
VAR7 <= VAR51;
end
else if(VAR50==1'b1)begin
VAR53 <= 1'b0;
VAR7 <= VAR51;
VAR10 <= VAR44;
VAR21 <= 1'b1;
end
end
end
VAR51:begin
if(VAR34==1'b1)begin
if(VAR19 <= VAR30)
VAR47;
end
else begin
VAR7 <= VAR27;
VAR53 <= 1'b0;
end
end
else if(VAR50==1'b1)begin
if(VAR21 <= VAR16)
case(VAR48)
1'b0:begin
if(!VAR14)begin
VAR10 <= VAR44;
VAR20 <= 1'b1;
VAR5<=VAR45;
VAR48 <= 1'b1;
ack <= 1'b0;
end
else
VAR48 <= 1'b0;
end
1'b1:VAR22;
endcase
end
else begin
VAR7 <= VAR27;
VAR48 <= 1'b0;
VAR53 <= 1'b0;
end
end
end
VAR27:begin
if(VAR53 == 1'b0)
VAR41;
end
else begin
ack <= 1'b1;
VAR53 <= 1'b0;
VAR7 <= VAR29;
end
end
VAR29:begin
ack <= 1'b0;
VAR50 <= 1'b0;
VAR34 <= 1'b0;
VAR7 <= VAR38;
end
default:VAR7 <= VAR38;
endcase
end
end
task VAR25;
begin
case(VAR39)
1'b0:begin
if(!VAR14)begin
VAR20 <= 1'b1;
VAR10[7] <= 1'b1;
VAR39 <= 1'b1;
end
else
VAR39 <= 1'b0;
end
1'b1:begin
if(VAR14)begin
VAR53 <= 1'b1;
VAR10[7] <= 1'b0;
VAR39 <= 1'b0;
end
else
VAR39<= 1'b1;
end
endcase
end
endtask
task VAR22;
begin
case(VAR5)
VAR3:begin
if(!VAR14) begin
VAR20 <= 1'b1;
VAR5 <= VAR45;
end
else
VAR5 <= VAR3;
end
VAR45:begin
if(!VAR14) begin
VAR5 <= VAR35;
VAR10 <= VAR10<<1'b1;
end
else
VAR5 <= VAR45;
end
VAR35:begin
if(!VAR14) begin
VAR5 <= VAR15;
VAR10 <= VAR10<<1'b1;
end
else
VAR5 <= VAR35;
end
VAR15:begin
if(!VAR14) begin
VAR5 <= VAR52;
VAR10 <= VAR10<<1'b1;
end
else
VAR5 <= VAR15;
end
VAR52:begin
if(!VAR14) begin
VAR5 <= VAR13;
VAR10 <= VAR10<<1'b1;
end
else
VAR5 <= VAR52;
end
VAR13:begin
if(!VAR14) begin
VAR5 <= VAR54;
VAR10 <= VAR10<<1'b1;
end
else
VAR5 <= VAR13;
end
VAR54:begin
if(!VAR14) begin
VAR5 <= VAR17;
VAR10 <= VAR10<<1'b1;
end
else
VAR5 <= VAR54;
end
VAR17:begin
if(!VAR14) begin
VAR5 <= VAR43;
VAR10 <= VAR10<<1'b1;
end
else
VAR5 <= VAR17;
end
VAR43:begin
if((VAR14 == 1'b0) && (VAR48 == 1'b1) ) begin
VAR20 <= 1'b0;
VAR5 <= VAR3;
VAR48 <= 1'b0;
VAR53 <= 1'b1;
VAR21 <= VAR21 + 1'b1;
ack <= 1'b1;
end
else if(VAR14==0)begin
VAR20 <= 1'b0;
VAR5 <= VAR3;
VAR48 <= 1'b0;
VAR53 <= 1'b1;
VAR21 <= VAR21 + 1'b1;
end
else;
end
endcase
end
endtask
task VAR47;
begin
case(VAR6)
VAR31:begin
VAR6 <= VAR33;
VAR49 <= 1'b0;
ack <= 1'b0;
end
VAR33:begin
if(VAR14)begin
VAR12[7] <= VAR37;
VAR6 <= VAR40;
end
else begin
VAR20 <= 1'b0;
VAR6 <= VAR33;
end
end
VAR40:begin
if(VAR14)begin
VAR12[6] <= VAR37;
VAR6 <= VAR2;
end
else
VAR6 <= VAR40;
end
VAR2:begin
if(VAR14)begin
VAR12[5] <= VAR37;
VAR6 <= VAR24;
end
else
VAR6 <= VAR2;
end
VAR24:begin
if(VAR14)begin
VAR12[4] <= VAR37;
VAR6 <= VAR11;
end
else
VAR6 <= VAR24;
end
VAR11:begin
if(VAR14)begin
VAR12[3] <= VAR37;
VAR6 <= VAR8;
end
else
VAR6 <= VAR11;
end
VAR8:begin
if(VAR14)begin
VAR12[2] <= VAR37;
VAR6 <= VAR46;
end
else
VAR6 <= VAR8;
end
VAR46:begin
if(VAR14)begin
VAR12[1] <= VAR37;
VAR6 <= VAR23;
end
else
VAR6 <= VAR46;
end
VAR23:begin
if(VAR14)begin
VAR12[0] <= VAR37;
VAR6 <= VAR4;
end
else
VAR6 <= VAR23;
end
VAR4:begin
if(VAR19 == VAR30)begin
VAR49 <= 1'b1;
VAR20 <= 1'b1;
VAR6 <= VAR31;
VAR53 <= 1'b1;
VAR10[7] <= 1'b1;
VAR19 <= VAR19 + 1'b1;
ack <= 1'b1;
end
else begin
VAR49 <= 1'b1;
VAR20 <= 1'b1;
VAR6 <= VAR31;
VAR53 <= 1'b1;
VAR10[7] <= 1'b0;
VAR19 <= VAR19 + 1'b1;
ack <= 1'b1;
end
end
default:begin
VAR6 <= VAR31;
end
endcase
end
endtask
task VAR41;
begin
case(VAR36)
1'b0:begin
if(!VAR14)begin
VAR20 <= 1'b1;
VAR36 <= 1'b1;
VAR10[7]<= 1'b0;
end
else
VAR36 <= 1'b0;
end
1'b1:begin
if(VAR14)begin
VAR10[7] <= 1'b1;
VAR53 <= 1'b1;
VAR36 <= 1'b0;
end
else
VAR36 <=1'b1;
end
endcase
end
endtask
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbn/sky130_fd_sc_ls__sdfbbn.functional.v | 2,393 | module MODULE1 (
VAR6 ,
VAR19 ,
VAR21 ,
VAR1 ,
VAR17 ,
VAR15 ,
VAR13 ,
VAR3
);
output VAR6 ;
output VAR19 ;
input VAR21 ;
input VAR1 ;
input VAR17 ;
input VAR15 ;
input VAR13 ;
input VAR3;
wire VAR2 ;
wire VAR4 ;
wire VAR12 ;
wire VAR8 ;
wire VAR16;
not VAR23 (VAR2 , VAR3 );
not VAR7 (VAR4 , VAR13 );
not VAR5 (VAR12 , VAR15 );
VAR20 VAR10 (VAR16, VAR21, VAR1, VAR17 );
VAR9 VAR22 VAR14 (VAR8 , VAR4, VAR2, VAR12, VAR16);
buf VAR11 (VAR6 , VAR8 );
not VAR18 (VAR19 , VAR8 );
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_rxeq_scan.v | 13,367 | module MODULE1 #
(
parameter VAR20 = "VAR40", parameter VAR27 = 1, parameter VAR32 = 22'd3125000 )
(
input VAR46,
input VAR5,
input [ 1:0] VAR33,
input [ 2:0] VAR6,
input VAR41,
input [ 3:0] VAR1,
input [17:0] VAR8,
input VAR24,
input [ 5:0] VAR12,
input [ 5:0] VAR29,
output VAR31,
output [17:0] VAR30,
output VAR22,
output VAR15,
output VAR34
);
reg [ 2:0] VAR2;
reg VAR23;
reg [ 3:0] VAR39;
reg [17:0] VAR25;
reg VAR10;
reg [ 5:0] VAR11;
reg [ 5:0] VAR35;
reg [ 2:0] VAR17;
reg VAR13;
reg [ 3:0] VAR3;
reg [17:0] VAR38;
reg VAR7;
reg [ 5:0] VAR43;
reg [ 5:0] VAR42;
reg VAR28 = 1'd0;
reg VAR16 = 1'd0;
reg [21:0] VAR4 = 22'd0;
reg [17:0] VAR9 = 18'd0;
reg VAR21 = 1'd0;
reg VAR26 = 1'd0;
reg VAR45 = 1'd0;
reg [ 3:0] fsm = 4'd0;
localparam VAR36 = 4'b0001;
localparam VAR18 = 4'b0010;
localparam VAR37 = 4'b0100;
localparam VAR14 = 4'b1000;
localparam VAR44 = (VAR20 == "VAR19") ? 22'd1000 : VAR32;
always @ (posedge VAR46)
begin
if (!VAR5)
begin
VAR2 <= 3'd0;
VAR23 <= 1'd0;
VAR39 <= 4'd0;
VAR25 <= 18'd0;
VAR10 <= 1'd0;
VAR11 <= 6'd0;
VAR35 <= 6'd0;
VAR17 <= 3'd0;
VAR13 <= 1'd0;
VAR3 <= 4'd0;
VAR38 <= 18'd0;
VAR7 <= 1'd0;
VAR43 <= 6'd0;
VAR42 <= 6'd0;
end
else
begin
VAR2 <= VAR6;
VAR23 <= VAR41;
VAR39 <= VAR1;
VAR25 <= VAR8;
VAR10 <= VAR24;
VAR11 <= VAR12;
VAR35 <= VAR29;
VAR17 <= VAR2;
VAR13 <= VAR23;
VAR3 <= VAR39;
VAR38 <= VAR25;
VAR7 <= VAR10;
VAR43 <= VAR11;
VAR42 <= VAR35;
end
end
always @ (posedge VAR46)
begin
if (!VAR5)
begin
fsm <= VAR36;
VAR16 <= 1'd0;
VAR4 <= 22'd0;
VAR9 <= 18'd0;
VAR21 <= 1'd0;
VAR26 <= 1'd0;
VAR45 <= 1'd0;
VAR28 <= 1'd0;
end
else
begin
case (fsm)
VAR36 :
begin
if (VAR13)
begin
fsm <= VAR18;
VAR16 <= 1'd1;
VAR4 <= 22'd0;
VAR9 <= VAR9;
VAR21 <= 1'd0;
VAR26 <= 1'd0;
VAR45 <= 1'd0;
VAR28 <= VAR28;
end
else if (VAR7)
begin
fsm <= VAR37;
VAR16 <= 1'd0;
VAR4 <= 22'd0;
VAR9 <= (VAR27 == 0) ? VAR38 : 18'd4;
VAR21 <= 1'd0;
VAR26 <= (VAR27 == 0) ? 1'd0 : 1'd1;
VAR45 <= 1'd0;
VAR28 <= VAR28;
end
else
begin
fsm <= VAR36;
VAR16 <= 1'd0;
VAR4 <= 22'd0;
VAR9 <= VAR9;
VAR21 <= 1'd0;
VAR26 <= 1'd0;
VAR45 <= 1'd0;
VAR28 <= VAR28;
end
end
VAR18 :
begin
fsm <= (!VAR13) ? VAR36 : VAR18;
VAR16 <= 1'd1;
VAR4 <= 22'd0;
VAR9 <= VAR9;
VAR21 <= 1'd0;
VAR26 <= 1'd0;
VAR45 <= 1'd0;
VAR28 <= VAR28;
end
VAR37 :
begin
if ((VAR28 == 1'd0) && (VAR33 == 2'd2))
begin
fsm <= VAR14;
VAR16 <= 1'd0;
VAR4 <= 22'd0;
VAR9 <= VAR9;
VAR21 <= 1'd0;
VAR26 <= VAR26;
VAR45 <= 1'd0;
VAR28 <= VAR28;
end
else
begin
fsm <= (VAR4 == VAR44) ? VAR14 : VAR37;
VAR16 <= 1'd0;
VAR4 <= VAR4 + 1'd1;
VAR9 <= VAR9;
VAR21 <= 1'd0;
VAR26 <= VAR26;
VAR45 <= 1'd0;
VAR28 <= VAR28;
end
end
VAR14 :
begin
if (!VAR7)
begin
fsm <= VAR36;
VAR16 <= 1'd0;
VAR4 <= 22'd0;
VAR9 <= VAR9;
VAR21 <= 1'd0;
VAR26 <= VAR26;
VAR45 <= 1'd0;
VAR28 <= (VAR33 == 2'd3) ? 1'd0 : VAR28 + 1'd1;
end
else
begin
fsm <= VAR14;
VAR16 <= 1'd0;
VAR4 <= 22'd0;
VAR9 <= VAR9;
VAR21 <= 1'd1;
VAR26 <= VAR26;
VAR45 <= (VAR28 == 1'd1) || (VAR33 == 2'd3);
VAR28 <= VAR28;
end
end
default :
begin
fsm <= VAR36;
VAR16 <= 1'd0;
VAR4 <= 22'd0;
VAR9 <= 18'd0;
VAR21 <= 1'd0;
VAR26 <= 1'd0;
VAR45 <= 1'd0;
VAR28 <= 1'd0;
end
endcase
end
end
assign VAR31 = VAR16;
assign VAR30 = VAR9;
assign VAR22 = VAR21;
assign VAR15 = VAR26;
assign VAR34 = VAR45;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv.pp.blackbox.v | 1,259 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR2,
VAR1,
VAR3 ,
VAR6
);
output VAR4 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Instructions/Instructions_stub.v | 1,278 | module MODULE1(VAR1, VAR3, VAR2)
;
input VAR1;
input [9:0]VAR3;
output [799:0]VAR2;
endmodule | gpl-3.0 |
hmdgharb/5-Staged-MIPS-Pipeline | IF_STAGE.v | 1,045 | module MODULE1(
input clk,
input rst,
input VAR25,
input [5:0] VAR8,
input VAR4,
input VAR27,
output [7:0] VAR26,
output [15:0] VAR18
);
wire[7:0] VAR15;
wire[7:0] VAR21;
wire[7:0] VAR17;
wire[7:0] VAR14;
wire[7:0] VAR36;
wire[1:0] VAR2;
assign VAR2 = {VAR27, VAR4};
VAR5 VAR9(
.VAR7(VAR8),
.VAR12(VAR36)
);
VAR16 VAR19(
.VAR24(clk),
.reset(rst),
.VAR6(VAR25),
.in(VAR15),
.out(VAR21)
);
VAR34 VAR13(
.VAR35(VAR21),
.VAR1(8'b00000001),
.out(VAR17)
);
VAR34 VAR23(
.VAR35(VAR36),
.VAR1(VAR17),
.out(VAR14)
);
VAR3#(8) VAR10(
.VAR29(VAR2),
.VAR30(),
.VAR22(VAR36),
.VAR28(VAR14),
.VAR32(VAR17),
.VAR11(VAR15)
);
VAR31#(256) VAR33(
.reset(rst),
.addr(VAR21),
.VAR20(VAR18)
);
assign VAR26 = VAR21;
endmodule | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/yf32/shifter.v | 5,040 | module MODULE1 (VAR10, VAR13, VAR20, VAR17);
input [31:0] VAR10;
input [ 4:0] VAR13;
input [ 1:0] VAR20;
output [31:0] VAR17;
wire [31: 0] VAR2 ;
wire [31: 0] VAR12 ;
wire [31: 0] VAR19 ;
wire [31: 0] VAR11 ;
wire [31: 0] VAR16;
wire [31: 0] VAR7 ;
wire [31: 0] VAR15 ;
wire [31: 0] VAR1 ;
wire [31: 0] VAR4 ;
wire [31: 0] VAR5;
wire [31:16] VAR9 ;
assign VAR9 = (VAR20 == VAR18 &
VAR10[31]) ? 16'b1111111111111111 : 16'b0000000000000000;
assign VAR2 = (VAR13[0]) ? {VAR10 [30:0], 1'b0} :VAR10;
assign VAR12 = (VAR13[1]) ? {VAR2[29:0], 2'b0} :VAR2;
assign VAR19 = (VAR13[2]) ? {VAR12[27:0], 4'b0} :VAR12;
assign VAR11 = (VAR13[3]) ? {VAR19[23:0], 8'b0} :VAR19;
assign VAR16 = (VAR13[4]) ? {VAR11[15:0], 16'b0} :VAR11;
assign VAR7 = (VAR13[0]) ? {VAR9[31], VAR10[31:1]}:VAR10;
assign VAR15 = (VAR13[1]) ? {VAR9[31:30],VAR7[31: 2]}: VAR7;
assign VAR1 = (VAR13[2]) ? {VAR9[31:28],VAR15[31: 4]}: VAR15;
assign VAR4 = (VAR13[3]) ? {VAR9[31:24],VAR1[31: 8]}: VAR1;
assign VAR5 = (VAR13[4]) ? {VAR9[31:16],VAR4[31:16]}: VAR4;
reg [31:0] VAR17;
always @(VAR20 or VAR16 or VAR5) begin
case(VAR20) VAR21 : VAR17 = VAR16;
default : VAR17 = VAR8;
endcase
end
wire [31:0] VAR17;
assign VAR17 = (VAR20 == VAR21) ? VAR16:{32{1'VAR3}};
assign VAR17 = (VAR20 == VAR14 |
VAR20 == VAR18) ? VAR5:{32{1'VAR3}};
assign VAR17 = (VAR20 == VAR6) ? VAR8 : {32{1'VAR3}} ;
endmodule | mit |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_sw_pio.v | 1,867 | module MODULE1 (
address,
clk,
VAR3,
VAR4,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 9: 0] VAR3;
input VAR4;
wire VAR2;
wire [ 9: 0] VAR5;
wire [ 9: 0] VAR6;
reg [ 31: 0] VAR1;
assign VAR2 = 1;
assign VAR6 = {10 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR4)
begin
if (VAR4 == 0)
VAR1 <= 0;
end
else if (VAR2)
VAR1 <= {32'b0 | VAR6};
end
assign VAR5 = VAR3;
endmodule | gpl-2.0 |
jkff90/design | avlst_n_to_1.v | 1,820 | module MODULE1 #(
parameter VAR15 = 8,
parameter VAR11 = 16,
)(
input VAR8,
input VAR2,
output VAR5,
input VAR12,
input [VAR15*VAR11-1:0] VAR14,
input VAR4,
output VAR3,
output [VAR11-1:0] VAR10
);
reg ready;
reg valid;
reg [VAR11-1:0] VAR6;
reg [VAR11-1:0] buffer [0:VAR15-1];
assign VAR5 = read;
assign VAR3 = valid;
assign VAR10 = VAR6;
reg VAR9;
always@(posedge VAR8, posedge VAR2) begin
if(VAR2 == 1'b1)
VAR9 <= 1'b0;
end
else
if(VAR12 == 1'b1)
VAR9 <= 1'b1;
if(VAR16 == 3'h7)
end
genvar VAR1;
generate
for(VAR1=0; VAR1<VAR15; VAR1++) begin : VAR7
always@(posedge VAR8, posedge VAR2) begin
if(VAR2 == 1'b1)
buffer[VAR1] <= {VAR11{1'b0}};
end
else begin
if(VAR12 == 1'b1)
buffer[VAR1] <= VAR14[(VAR1+1)*VAR11-1:VAR1*VAR11];
end
end
end
endgenerate
always@(posedge VAR8, posedge VAR2) begin
if(VAR2 == 1'b1) begin
valid <= 1'b0;
end
valid <= VAR9 &
end
always@(posedge VAR8, posedge VAR2) begin
if(VAR2 == 1'b1) begin
VAR6 <= {VAR11{1'b0}};
end
VAR6 <= buffer[VAR16];
end
reg [2:0] VAR16;
always@(posedge VAR8, posedge VAR2) begin
if(VAR2 == 1'b1)
VAR16 <= 3'h0;
end
else begin
if(VAR4 == 1'b1 && VAR13 == 1'b1)
VAR16 <= VAR16+3'h1;
end
end
endmodule | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_2/zynq_design_1_processing_system7_0_2_stub.v | 5,382 | module MODULE1(VAR3, VAR53,
VAR61, VAR10, VAR11, VAR1,
VAR52, VAR29, VAR37, VAR15,
VAR39, VAR59, VAR13, VAR48, VAR30,
VAR36, VAR51, VAR55, VAR27,
VAR42, VAR35, VAR65, VAR20, VAR58,
VAR41, VAR12, VAR66, VAR62, VAR8,
VAR19, VAR32, VAR44, VAR33, VAR18,
VAR4, VAR45, VAR57, VAR63,
VAR56, VAR9, VAR47, VAR7, VAR43,
VAR60, VAR22, VAR23, VAR28, VAR21, VAR54, VAR16, VAR34,
VAR24, VAR26, VAR38, VAR40, VAR25, VAR14, VAR6, VAR68, VAR64,
VAR31, VAR5, VAR67, VAR49, VAR17, VAR46, VAR2, VAR50)
;
output VAR3;
output VAR53;
output VAR61;
output [1:0]VAR10;
output VAR11;
input VAR1;
output VAR52;
output VAR29;
output VAR37;
output VAR15;
output VAR39;
output VAR59;
output [11:0]VAR13;
output [11:0]VAR48;
output [11:0]VAR30;
output [1:0]VAR36;
output [1:0]VAR51;
output [2:0]VAR55;
output [1:0]VAR27;
output [1:0]VAR42;
output [2:0]VAR35;
output [2:0]VAR65;
output [2:0]VAR20;
output [31:0]VAR58;
output [31:0]VAR41;
output [31:0]VAR12;
output [3:0]VAR66;
output [3:0]VAR62;
output [3:0]VAR8;
output [3:0]VAR19;
output [3:0]VAR32;
output [3:0]VAR44;
output [3:0]VAR33;
input VAR18;
input VAR4;
input VAR45;
input VAR57;
input VAR63;
input VAR56;
input VAR9;
input [11:0]VAR47;
input [11:0]VAR7;
input [1:0]VAR43;
input [1:0]VAR60;
input [31:0]VAR22;
output VAR23;
output VAR28;
inout [53:0]VAR21;
inout VAR54;
inout VAR16;
inout VAR34;
inout VAR24;
inout VAR26;
inout VAR38;
inout VAR40;
inout VAR25;
inout VAR14;
inout [2:0]VAR6;
inout [14:0]VAR68;
inout VAR64;
inout VAR31;
inout [3:0]VAR5;
inout [31:0]VAR67;
inout [3:0]VAR49;
inout [3:0]VAR17;
inout VAR46;
inout VAR2;
inout VAR50;
endmodule | mit |
aap/pdp6 | verilog/memif_d.v | 1,569 | module MODULE1(
input wire clk,
input wire reset,
input wire [1:0] VAR9,
input wire VAR5,
input wire VAR13,
input wire [31:0] VAR6,
output reg [31:0] VAR4,
output wire VAR2,
output wire [31:0] VAR17,
output reg VAR15,
output reg VAR1,
output wire [63:0] VAR7,
input wire [63:0] VAR11,
input wire VAR18
);
reg [31:0] addr;
reg [63:0] word;
assign VAR17 = addr;
assign VAR7 = word;
wire VAR3, VAR12;
VAR10 VAR16(clk, reset, VAR5, VAR3);
VAR10 VAR14(clk, reset, VAR13, VAR12);
reg VAR8;
wire req = (VAR3|VAR12) & VAR9 == 2'h2;
assign VAR2 = req | VAR8;
always @(posedge clk or negedge reset) begin
if(~reset) begin
VAR15 <= 0;
VAR1 <= 0;
VAR8 <= 0;
addr <= 0;
word <= 0;
end else begin
if(VAR3) begin
case(VAR9)
2'h0: addr <= VAR6[31:0];
2'h1: word[31:0] <= VAR6[31:0];
2'h2: word[63:32] <= VAR6[31:0];
endcase
end
if(req) begin
VAR8 <= 1;
if(VAR5)
VAR15 <= 1;
end
else if(VAR13)
VAR1 <= 1;
end
if(VAR15 & ~VAR18) begin
VAR15 <= 0;
VAR8 <= 0;
end
if(VAR1 & ~VAR18) begin
VAR1 <= 0;
VAR8 <= 0;
word <= VAR11;
end
end
end
always @(*) begin
case(VAR9)
2'h1: VAR4 <= word[31:0];
2'h2: VAR4 <= word[63:32];
default: VAR4 <= 32'b0;
endcase
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo_0.v | 2,318 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR5 ,
VAR6,
VAR2,
VAR4,
VAR10 ,
VAR1
);
output VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR6;
input VAR2;
input VAR4;
input VAR10 ;
input VAR1 ;
VAR8 VAR9 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3 ,
VAR7 ,
VAR5 ,
VAR6
);
output VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR6;
supply1 VAR2;
supply0 VAR4;
supply1 VAR10 ;
supply0 VAR1 ;
VAR8 VAR9 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50.functional.v | 1,343 | module MODULE1 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
wire VAR5;
buf VAR4 (VAR5, VAR2 );
buf VAR1 (VAR3 , VAR5 );
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/clk_gen_83M.v | 7,435 | module MODULE1
( input VAR17,
output VAR72,
output VAR83,
output VAR23,
input VAR77,
output VAR2
);
VAR21 VAR30
(.VAR89 (VAR27),
.VAR70 (VAR17));
wire [15:0] VAR34;
wire VAR64;
wire VAR28;
wire VAR43;
wire VAR37;
wire VAR66;
wire VAR56;
wire VAR58;
wire VAR3;
wire VAR54;
wire VAR82;
wire VAR26;
wire VAR42;
wire VAR11;
wire VAR24;
wire VAR68;
VAR59
.VAR69 ("VAR29"),
.VAR48 ("VAR29"),
.VAR63 ("VAR22"),
.VAR1 ("VAR29"),
.VAR7 (1),
.VAR73 (40.000),
.VAR45 (0.000),
.VAR25 ("VAR29"),
.VAR19 (6.000),
.VAR47 (0.000),
.VAR49 (0.500),
.VAR81 ("VAR29"),
.VAR8 (12),
.VAR46 (0.000),
.VAR13 (0.500),
.VAR38 ("VAR29"),
.VAR36 (12),
.VAR44 (180.000),
.VAR87 (0.500),
.VAR53 ("VAR29"),
.VAR67 (40.000),
.VAR62 (0.010))
VAR55
(.VAR12 (VAR43),
.VAR33 (VAR66),
.VAR20 (VAR16),
.VAR61 (VAR56),
.VAR72 (VAR86),
.VAR51 (VAR58),
.VAR83 (VAR71),
.VAR57 (VAR3),
.VAR23 (VAR54),
.VAR15 (VAR82),
.VAR76 (VAR26),
.VAR80 (VAR42),
.VAR50 (VAR11),
.VAR18 (VAR37),
.VAR17 (VAR27),
.VAR39 (1'b0),
.VAR9 (1'b1),
.VAR60 (7'h0),
.VAR6 (1'b0),
.VAR32 (1'b0),
.VAR35 (16'h0),
.VAR41 (VAR34),
.VAR10 (VAR64),
.VAR75 (1'b0),
.VAR84 (1'b0),
.VAR40 (1'b0),
.VAR79 (1'b0),
.VAR88 (VAR28),
.VAR2 (VAR2),
.VAR14 (VAR68),
.VAR31 (VAR24),
.VAR78 (1'b0),
.VAR52 (VAR77));
VAR5 VAR85
(.VAR89 (VAR37),
.VAR70 (VAR43));
VAR5 VAR74
(.VAR89 (VAR72),
.VAR70 (VAR16));
VAR5 VAR4
(.VAR89 (VAR83),
.VAR70 (VAR86));
VAR5 VAR65
(.VAR89 (VAR23),
.VAR70 (VAR71));
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/example_design/PIO_TO_CTRL.v | 3,734 | module MODULE1 #(
parameter VAR6 = 1
) (
input clk,
input VAR5,
input VAR2,
input VAR3,
input VAR4,
output reg VAR1
);
reg VAR7;
always @ ( posedge clk ) begin
if (!VAR5 )
begin
end
else
begin
if (!VAR7 && VAR2)
end
else if (VAR3)
end
end
always @ ( posedge clk ) begin
if (!VAR5 )
begin
end
else
begin
if ( VAR4 && !VAR7)
end
else
end
end
endmodule | lgpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi/bench/verilog/spi_slave_model.v | 3,637 | module MODULE1 (rst, VAR5, VAR7, VAR1, VAR4);
input rst; input VAR5; input VAR7; input VAR1; output VAR4;
reg VAR4;
reg VAR2; reg VAR6; reg [31:0] VAR3;
parameter VAR8 = 1;
always @(posedge(VAR7 && !VAR2) or negedge(VAR7 && VAR2) or rst)
begin
if (rst)
VAR3 <= #VAR8 32'b0;
end
else if (!VAR5)
VAR3 <= #VAR8 {VAR3[30:0], VAR1};
end
always @(posedge(VAR7 && !VAR6) or negedge(VAR7 && VAR6))
begin
VAR4 <= #VAR8 VAR3[31];
end
endmodule | gpl-2.0 |
manu3193/ControladorElevadorTDD | Divisor_Frecuencia.v | 4,046 | module MODULE1 (
input VAR3, output VAR1
);
reg[31:0] VAR2 = 0; reg VAR1=0;
always @(posedge VAR3)
begin
if (VAR2 == 50000000-1) begin
VAR1 <= ~VAR1;
VAR2 <=0;
end
else
begin
VAR2 <= VAR2 + 1; end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0n/sky130_fd_sc_lp__inputiso0n.behavioral.pp.v | 1,760 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR1,
VAR2 ,
VAR7 ,
VAR4 ,
VAR11
);
output VAR5 ;
input VAR10 ;
input VAR1;
input VAR2 ;
input VAR7 ;
input VAR4 ;
input VAR11 ;
wire VAR6;
and VAR8 (VAR6, VAR10, VAR1 );
VAR9 VAR3 (VAR5 , VAR6, VAR2, VAR7);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v | 1,881 | module MODULE1 #(parameter VAR9(VAR24)
, parameter VAR9(VAR12)
, parameter VAR19=VAR13(VAR12,1)
)
(input VAR14
, input VAR4
, input [VAR19-1:0] VAR5
, input [VAR24-1:0] VAR21
, input [VAR19-1:0] VAR23
, output logic [VAR24-1:0] VAR16
);
logic [VAR19-1:0][VAR24-1:0] VAR6;
wire VAR7 = VAR4;
for (genvar VAR2 = 0; VAR2 < VAR12; VAR2++)
begin : VAR3
VAR20
VAR10
(.VAR17(VAR14)
,.VAR11(VAR5[VAR2])
,.VAR1(VAR21)
,.VAR15(VAR6[VAR2])
);
end
VAR18
,.VAR12(VAR19)
)
VAR8
(.VAR1(VAR6)
,.VAR22(VAR23)
,.VAR15(VAR16)
);
begin
begin
end | bsd-3-clause |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/uart/uart_rx.v | 3,407 | module MODULE1 (
input wire clk,
input wire reset,
output wire VAR25,
output reg VAR12,
output reg [VAR19] VAR4,
input wire VAR2
);
reg [VAR18] state;
reg [VAR23] VAR6;
reg [VAR5] VAR17;
assign VAR25 = (state != VAR20) ? VAR24 : VAR1;
always @(posedge clk or VAR11 reset) begin
if (reset == VAR7) begin
VAR12 <= VAR1;
VAR4 <= VAR14'h0;
state <= VAR20;
VAR6 <= VAR8 / 2;
VAR17 <= VAR15'h0;
end else begin
case (state)
if (VAR2 == VAR10) begin
state <= VAR22;
end
VAR12 <= VAR1;
end
if (VAR6 == {VAR13{1'b0}}) begin
case (VAR17)
state <= VAR20;
VAR17 <= VAR16;
VAR6 <= VAR8 / 2;
if (VAR2 == VAR21) begin
VAR12 <= VAR24;
end
end
default : begin
VAR4 <= {VAR2, VAR4[VAR9:VAR3+1]};
VAR17 <= VAR17 + 1'b1;
VAR6 <= VAR8;
end
endcase
end else begin
VAR6 <= VAR6 - 1'b1;
end
end
endcase
end
end
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b.functional.pp.v | 1,969 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR2 ,
VAR1,
VAR11,
VAR7 ,
VAR9
);
output VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR1;
input VAR11;
input VAR7 ;
input VAR9 ;
wire VAR15 ;
wire VAR5 ;
wire VAR12;
not VAR10 (VAR15 , VAR8 );
and VAR3 (VAR5 , VAR15, VAR2 );
VAR4 VAR13 (VAR12, VAR5, VAR1, VAR11);
buf VAR14 (VAR6 , VAR12 );
endmodule | apache-2.0 |
ineganov/bare_system | hard/datapath.v | 14,890 | module MODULE1 ( input VAR141,
input VAR114,
input VAR112,
input VAR56,
input VAR47, input VAR37, input VAR32, input VAR65, input [1:0] VAR119, input VAR85, input VAR44, input VAR105, input VAR134, input VAR79, input VAR39, input VAR18, input VAR118, input VAR30, input VAR21, input [6:0] VAR42, input [1:0] VAR4, input [1:0] VAR127, input [1:0] VAR60,
output [5:0] VAR11, output [5:0] VAR131, output [4:0] VAR93,
output [29:0] VAR9,
input [31:0] VAR36,
output VAR87,
output [ 3:0] VAR101,
output [29:0] VAR12,
output [31:0] VAR133,
input [31:0] VAR28 );
wire [31:0] VAR3, VAR102, VAR6, VAR7, VAR123, VAR57;
wire [31:0] VAR66, VAR88, VAR71, VAR16, VAR135, VAR68, VAR25,
VAR137, VAR59;
wire [4:0] VAR17, VAR132, VAR138;
wire VAR92, VAR136, VAR58, VAR15, VAR48;
wire [31:0] VAR104, VAR62, VAR115, VAR73,
VAR55, VAR22, VAR10, VAR72, VAR139,
VAR97, VAR45, VAR1;
wire [6:0] VAR100;
wire [4:0] VAR130, VAR106, VAR74, VAR122, VAR128;
wire [1:0] VAR120, VAR117, VAR31;
wire VAR108, VAR150, VAR83, VAR142,
VAR78, VAR63, VAR126, VAR46;
wire [31:0] VAR98, VAR109, VAR90;
wire [4:0] VAR34;
wire [1:0] VAR144;
wire VAR35, VAR103, VAR121, VAR148;
wire [31:0] VAR38, VAR113;
wire VAR75, VAR70;
assign VAR57 = VAR123 + 4;
assign VAR58 = VAR15 | VAR48;
assign VAR9 = VAR123[31:2];
wire [1:0] VAR95 = VAR118 ? 2'b11 :
VAR30 ? 2'b10 :
VAR136 ? 2'b01 :
2'b00 ;
VAR145 VAR111( VAR95,
VAR57, VAR3, VAR6, VAR102, VAR7 );
VAR99 VAR64(VAR141, VAR112, ~VAR58 & VAR56, VAR7, VAR123 );
VAR99 #(64) VAR8(VAR141, VAR112, ~VAR58 & VAR56,
{ VAR36,
VAR57 },
{ VAR66,
VAR88 });
assign VAR11 = VAR66[31:26];
assign VAR131 = VAR66 [5:0];
assign VAR93 = VAR66[20:16];
assign VAR132 = VAR66[25:21];
assign VAR138 = VAR66[20:16];
VAR76 VAR54(.VAR141 (VAR114 ),
.VAR49 (VAR75 ),
.VAR94 (VAR132 ), .VAR84 (VAR138 ), .VAR81 (VAR17 ), .VAR91 (VAR135 ), .VAR40 (VAR71 ), .VAR89 (VAR16 ));
VAR52 VAR96(VAR127, VAR66[15:0], VAR68);
VAR41 VAR53(VAR68, VAR25);
wire VAR67 = (VAR132 != 0) && (VAR132 == VAR34) && VAR35;
wire VAR5 = (VAR138 != 0) && (VAR138 == VAR34) && VAR35;
VAR86 VAR26(VAR67, VAR71, VAR98, VAR137 );
VAR86 VAR29(VAR5, VAR16, VAR98, VAR59 );
wire VAR51 = VAR44 | VAR105 | VAR134 |
VAR79 | VAR39 | VAR18 |
VAR118 | VAR30;
assign VAR48 = (VAR132 != 0) & VAR51 &
((VAR108 & ((VAR130 == VAR132) |
(VAR130 == VAR138) )) |
(VAR121 & ((VAR34 == VAR132) | (VAR34 == VAR138) )));
assign VAR3 = VAR25 + VAR88;
assign VAR102 = {VAR88[31:28], VAR66[25:0], 2'b00};
assign VAR6 = VAR137;
wire VAR140 = (VAR137 == VAR59);
wire VAR82 = (VAR137 == 0);
assign VAR136 = ( (VAR44 & VAR140) |
(VAR105 & ~VAR140) |
(VAR134 & ( VAR137[31] | VAR82)) | (VAR79 & VAR137[31] ) | (VAR39 & ~VAR137[31] ) | (VAR18 & (~VAR137[31] & ~VAR82)) );
assign VAR92 = VAR118 | VAR30 | VAR39 | VAR79;
VAR99 #(168) VAR149(VAR141, VAR112 | VAR58, VAR56,
{ VAR47, VAR37, VAR65, VAR119, VAR32, VAR85, VAR92, VAR21, VAR42, VAR4, VAR60, VAR71, VAR16, VAR132, VAR138, VAR66[15:11], VAR66[10:06], VAR68, VAR88 },
{ VAR108, VAR150, VAR46, VAR31, VAR83, VAR142, VAR63, VAR78, VAR100, VAR120, VAR117, VAR115,
VAR73,
VAR106,
VAR74,
VAR122,
VAR128,
VAR62,
VAR104 });
VAR145 #(5) VAR19( VAR120,
VAR74,
VAR122,
5'd31, 5'd31, VAR130);
wire [1:0] VAR80 = ((VAR106 != 0) && (VAR106 == VAR34) && VAR35) ? 2'b10 :
((VAR106 != 0) && (VAR106 == VAR17) && VAR75) ? 2'b01 :
2'b00;
wire [1:0] VAR20 = ((VAR74 != 0) && (VAR74 == VAR34) && VAR35) ? 2'b10 :
((VAR74 != 0) && (VAR74 == VAR17) && VAR75) ? 2'b01 :
2'b00;
assign VAR15 = VAR83 & ((VAR132 == VAR74) |
(VAR138 == VAR74) );
VAR145 VAR50(VAR80, VAR115, VAR135, VAR98, VAR115, VAR55 );
VAR145 VAR27(VAR20, VAR73, VAR135, VAR98, VAR73, VAR22 );
VAR86 VAR2( VAR63,
VAR55,
VAR104,
VAR10 );
VAR145 VAR43( {VAR63, VAR78},
VAR22, VAR62, 32'd4, 32'd4, VAR72 );
alu alu(VAR100, VAR10, VAR72, VAR128, VAR45, VAR126);
wire [63:0] VAR146 = VAR55 * VAR22;
VAR99 #( 64) VAR69(VAR141, VAR112, VAR142 & VAR56, VAR146, {VAR139, VAR97});
VAR145 VAR23( VAR117,
VAR45,
VAR139, VAR97, 32'VAR13, VAR1 );
VAR99 #( 75) VAR143(VAR141, VAR112, VAR56,
{ VAR108, VAR150, VAR46, VAR31, VAR83, VAR1, VAR22, VAR130 },
{ VAR35,
VAR103,
VAR148,
VAR144,
VAR121,
VAR98,
VAR109,
VAR34 });
assign VAR87 = VAR103;
assign VAR12 = VAR98[31:2];
VAR110 VAR107( .VAR124 ( VAR98[1:0] ),
.VAR14 ( VAR109 ),
.VAR24 ( VAR148 ),
.VAR125 ( VAR144 ),
.VAR129 ( VAR101 ),
.VAR116( VAR133 ));
VAR147 VAR61( .VAR124 ( VAR98[1:0] ),
.VAR14 ( VAR28 ),
.VAR24 ( VAR148 ),
.VAR125 ( VAR144 ),
.VAR116( VAR90));
VAR99 #( 71) VAR77(VAR141, VAR112, VAR56,
{ VAR35, VAR121, VAR98, VAR90, VAR34},
{ VAR75, VAR70, VAR38, VAR113, VAR17} );
VAR86 VAR33( VAR70,
VAR38, VAR113, VAR135);
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o.behavioral.pp.v | 2,032 | module MODULE1 (
VAR10 ,
VAR15 ,
VAR12 ,
VAR2 ,
VAR3 ,
VAR17,
VAR14,
VAR6 ,
VAR5
);
output VAR10 ;
input VAR15 ;
input VAR12 ;
input VAR2 ;
input VAR3 ;
input VAR17;
input VAR14;
input VAR6 ;
input VAR5 ;
wire VAR4 ;
wire VAR8 ;
wire VAR13;
and VAR16 (VAR4 , VAR15, VAR12 );
or VAR1 (VAR8 , VAR4, VAR3, VAR2 );
VAR11 VAR7 (VAR13, VAR8, VAR17, VAR14);
buf VAR9 (VAR10 , VAR13 );
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/dac_buf.v | 9,164 | module MODULE1 (
VAR32,
VAR55,
VAR56,
VAR11,
VAR27,
VAR59);
input VAR32;
input [7:0] VAR55;
input [8:0] VAR56;
input [10:0] VAR11;
input VAR27;
output [31:0] VAR59;
tri1 VAR32;
tri0 VAR27;
wire [31:0] VAR2;
wire [31:0] VAR59 = VAR2[31:0];
VAR1 VAR26 (
.VAR5 (VAR11),
.VAR10 (VAR56),
.VAR25 (VAR32),
.VAR57 (VAR55),
.VAR52 (VAR27),
.VAR39 (VAR2),
.VAR13 (1'b0),
.VAR9 (1'b0),
.VAR43 (1'b0),
.VAR15 (1'b0),
.VAR14 (1'b1),
.VAR8 (1'b1),
.VAR53 (1'b1),
.VAR20 (1'b1),
.VAR41 (1'b1),
.VAR49 (1'b1),
.VAR45 (1'b1),
.VAR48 ({32{1'b1}}),
.VAR4 (),
.VAR19 (),
.VAR36 (1'b1),
.VAR42 (1'b1),
.VAR54 (1'b0));
VAR26.VAR17 = "VAR51",
VAR26.VAR40 = "VAR16",
VAR26.VAR22 = "VAR35",
VAR26.VAR12 = "VAR35",
VAR26.VAR44 = "VAR35",
VAR26.VAR37 = "VAR30 VAR34 VAR6",
VAR26.VAR33 = "VAR1",
VAR26.VAR50 = 2048,
VAR26.VAR38 = 512,
VAR26.VAR46 = "VAR28",
VAR26.VAR58 = "VAR51",
VAR26.VAR29 = "VAR16",
VAR26.VAR23 = "VAR60",
VAR26.VAR31 = "VAR18",
VAR26.VAR24 = 11,
VAR26.VAR3 = 9,
VAR26.VAR7 = 8,
VAR26.VAR47 = 32,
VAR26.VAR21 = 1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.v | 2,226 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR10 ,
VAR5 ,
VAR7,
VAR9,
VAR8 ,
VAR4
);
output VAR3 ;
output VAR6 ;
input VAR10 ;
input VAR5 ;
input VAR7;
input VAR9;
input VAR8 ;
input VAR4 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR3 ,
VAR6,
VAR10,
VAR5
);
output VAR3 ;
output VAR6;
input VAR10;
input VAR5 ;
supply1 VAR7;
supply0 VAR9;
supply1 VAR8 ;
supply0 VAR4 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
HFoxtail/Mu80 | trunk/video.v | 2,285 | module MODULE1(
input wire VAR15,
input wire [7:0] VAR11,
output reg [13:0] addr,
output reg [4:0] VAR8,
output reg [5:0] VAR2,
output reg [4:0] VAR12,
output reg VAR14,
output reg VAR10
);
reg [9:0] VAR1;
reg [9:0] VAR7;
reg [7:0] VAR5;
reg [7:0] VAR6;
reg [7:0] VAR3;
wire [9:0] VAR13 = VAR1 - 8'd48;
wire [9:0] VAR9 = VAR7 - 8'd48;
wire VAR4 = VAR3[ 3'h7 ^ VAR13[3:1] ];
always @(posedge VAR15) begin
if (VAR1 == 10'd800) begin
VAR1 <= 1'b0;
VAR7 <= (VAR7 == 10'd525) ? 1'b0 : (VAR7 + 1'b1);
end else VAR1 <= VAR1 + 1'b1;
VAR14 <= (VAR1 >= 10'd656 && VAR1 <= 10'd751); VAR10 <= (VAR7 >= 10'd490 && VAR7 <= 10'd492);
if (VAR1 < 10'd640 && VAR7 < 10'd480) begin
if (VAR1 >= 64 && VAR1 < 576 && VAR7 >= 48 && VAR7 < 432) begin
VAR8 <= VAR4? 1'b0 : 5'h0F; VAR2 <= VAR4? 1'b0 : 6'h1F;
VAR12 <= VAR4? 1'b0 : 5'h0F;
end else begin VAR8 <= 5'h0F; VAR2 <= 6'h1F; VAR12 <= 5'h0F; end
end else begin VAR8 <= 1'b0; VAR2 <= 1'b0; VAR12 <= 1'b0; end
case (VAR13[3:0])
4'h0: begin addr <= {2'b10, VAR9[8:1], VAR13[8:4]}; end
4'h1: begin addr <= {5'b10110, VAR9[8:4], VAR13[8:4]}; VAR6 <= VAR11; end
4'hF: begin VAR5 <= VAR11; VAR3 <= VAR6; end
endcase
end
endmodule | gpl-3.0 |
drom/quark | v/tail_offset.v | 3,858 | module MODULE1 (VAR21, VAR24, VAR59, VAR12, VAR44, VAR54, VAR3, VAR67, VAR32, VAR16, VAR41, VAR36, VAR46, VAR10, VAR6, VAR66, VAR51);
input [63:0] VAR21;
output [3:0] VAR24, VAR59, VAR12, VAR44, VAR54, VAR3, VAR67, VAR32, VAR16, VAR41, VAR36, VAR46, VAR10, VAR6, VAR66, VAR51;
reg [3:0] VAR24, VAR23, VAR52, VAR68, VAR76, VAR82, VAR49, VAR48, VAR27, VAR55, VAR61, VAR86, VAR2, VAR83, VAR30, VAR34;
reg [3:0] VAR70, VAR60, VAR37, VAR47, VAR17, VAR39, VAR57, VAR9, VAR31, VAR74, VAR26, VAR69, VAR84, VAR80, VAR75, VAR11;
reg [3:0] VAR59, VAR13, VAR12, VAR44, VAR81, VAR8, VAR72, VAR38, VAR54, VAR3, VAR67, VAR32, VAR78, VAR43, VAR65, VAR33, VAR16, VAR41, VAR36, VAR46;
wire [3:0] VAR22, VAR4, VAR50, VAR20, VAR18, VAR42, VAR64, VAR63, VAR25, VAR62, VAR53, VAR15, VAR77, VAR45;
VAR35 VAR5 (.VAR21(VAR60), .VAR71(VAR22));
VAR35 VAR7 (.VAR21(VAR37), .VAR71(VAR4));
VAR35 VAR40 (.VAR21(VAR47), .VAR71(VAR50));
VAR35 VAR79 (.VAR21(VAR17), .VAR71(VAR20));
VAR35 VAR85 (.VAR21(VAR39), .VAR71(VAR18));
VAR35 VAR56 (.VAR21(VAR57), .VAR71(VAR42));
VAR35 VAR73 (.VAR21(VAR9), .VAR71(VAR64));
VAR35 VAR14 (.VAR21(VAR31), .VAR71(VAR63));
VAR35 VAR58 (.VAR21(VAR74), .VAR71(VAR25));
VAR35 VAR1 (.VAR21(VAR26), .VAR71(VAR62));
VAR35 VAR19 (.VAR21(VAR69), .VAR71(VAR53));
VAR35 VAR28 (.VAR21(VAR84), .VAR71(VAR15));
VAR35 VAR29 (.VAR21(VAR80), .VAR71(VAR77));
always @ (VAR21) { VAR11, VAR75, VAR80, VAR84, VAR69, VAR26, VAR74, VAR31, VAR9, VAR57, VAR39, VAR17, VAR47, VAR37, VAR60, VAR70 } = VAR21;
always @ ( VAR24, VAR23, VAR52, VAR68, VAR76, VAR82, VAR49, VAR48, VAR27, VAR55, VAR61, VAR86 )
begin
VAR59 = VAR23 + VAR24;
VAR13 = VAR68 + VAR52;
VAR12 = VAR52 + VAR59;
VAR44 = VAR13 + VAR59;
VAR81 = VAR82 + VAR76;
VAR8 = VAR48 + VAR49;
VAR72 = VAR49 + VAR81;
VAR38 = VAR8 + VAR81;
VAR54 = VAR76 + VAR44;
VAR3 = VAR81 + VAR44;
VAR67 = VAR72 + VAR44;
VAR32 = VAR38 + VAR44;
VAR78 = VAR55 + VAR27;
VAR43 = VAR86 + VAR61;
VAR65 = VAR61 + VAR78;
VAR33 = VAR43 + VAR78;
VAR16 = VAR27 + VAR32;
VAR41 = VAR78 + VAR32;
VAR36 = VAR65 + VAR32;
VAR46 = VAR33 + VAR32;;
end
endmodule | mit |
mlab-upenn/pvs | hdl_harness/clock_transmitter.v | 3,692 | module MODULE1
(
VAR12,
VAR2,
counter,
VAR27,
VAR14,
VAR15,
VAR1
);
input VAR12;
input VAR2;
input [31:0] counter;
input [7:0] VAR27;
input VAR14;
output VAR15;
output VAR1;
parameter VAR7 = 0;
parameter VAR9 = 1;
parameter VAR22 = 2;
parameter VAR17 = 3;
parameter VAR19 = 4;
reg[3:0] state = 4'd0;
reg[7:0] VAR3 = 8'd0;
reg[3:0] VAR5 = 4'd0;
reg VAR25 = 1'b0;
reg VAR29 = 1'b0;
reg [7:0] VAR18 = 8'd0;
reg [31:0] VAR6 = 8'd0;
wire VAR13;
reg VAR26 = 1'b0;
wire VAR24;
wire VAR20;
VAR28 VAR8
(
.clk(VAR12),
.VAR21(VAR26),
.pulse(VAR13)
);
always @(posedge VAR2) begin
case(state)
VAR7:
begin
VAR25 <= VAR14 & !VAR29;
if (VAR18 == 8'd0) VAR18 <= VAR27;
state <= (VAR25) ? VAR9 : VAR7;
VAR6 <= (VAR25) ? counter : 32'd0;
VAR5 <= 4'd0;
VAR29 <= VAR25;
end
VAR9:
begin
VAR26 <= (VAR5 < 4'd5);
VAR3 <= (VAR5 == 4'd0) ? VAR18 :
(VAR5 == 4'd1) ? VAR6[7:0] :
(VAR5 == 4'd2) ? VAR6[15:8] :
(VAR5 == 4'd3) ? VAR6[23:16] :
(VAR5 == 4'd4) ? VAR6[31:24] :
8'b0;
state <= (VAR5 < 4'd5) ? VAR22 : VAR19;
end
VAR22:
begin
state <= (VAR24) ? VAR22 : VAR17;
VAR26 <= 0;
end
VAR17:
begin
VAR5 <= VAR5 + 4'b1;
state <= VAR9;
end
VAR19:
begin
state <= VAR7;
VAR18 <= 8'b0;
end
endcase
end
VAR16 VAR4
(
.clk(VAR12),
.VAR23(VAR13),
.VAR11(VAR3),
.VAR15(VAR20),
.VAR10(VAR24)
);
assign VAR1 = (state == VAR19);
reg VAR15;
always @(posedge VAR12)
VAR15 <= (VAR24) ? VAR20 : 1'b1;
endmodule | gpl-3.0 |
robinsonb5/SegaToCD32 | SegaToCD32.cydsn/CD32Shifter/CD32Shifter.v | 7,121 | module MODULE1 (
output VAR9,
output VAR46,
output VAR31,
input VAR38,
input VAR33,
input VAR48
);
localparam VAR12=3'b000;
localparam VAR42=3'b001;
localparam VAR19=3'b010;
localparam VAR28=3'b011;
reg[2:0] VAR40;
localparam VAR10=2'b00;
localparam VAR27=2'b01;
localparam VAR36=2'b11;
reg[1:0] VAR18;
wire VAR35;
assign VAR35=VAR33;
wire VAR43;
assign VAR43=VAR48;
wire VAR25;
wire VAR15;
assign VAR31 = VAR15;
assign VAR9 = VAR35 ? VAR25 : 1'b1;
assign VAR46 = ((VAR18!=VAR10) | VAR15==1'b0);
always @(posedge VAR38)
begin
if(VAR18==VAR10)
begin
VAR18<=VAR10;
VAR40<=VAR19;
if(VAR35==1'b0 && VAR43==1'b0)
begin
VAR18<=VAR27;
end
end
else if(VAR18==VAR27)
begin
VAR40<=VAR42;
if(VAR43==1'b1)
begin
VAR18<=VAR36;
VAR40<=VAR12;
end
if(VAR35==1'b1)
VAR18<=VAR10;
end
else if(VAR18==VAR36)
begin
VAR40<=VAR42;
if(VAR43==1'b0)
begin
VAR18<=VAR27;
end
if(VAR35==1'b1)
VAR18<=VAR10;
end
else
VAR18<=VAR10;
end
VAR8 #(.VAR24(
{
8'hFF, 8'hFF,
8'hFF, 8'hFF,
1'h0, VAR16, VAR49,
10'h00, VAR23,VAR39,
}
)) VAR29(
.reset(1'b0),
.clk(VAR38),
.VAR30(VAR40),
.VAR32(1'b0),
.VAR44(1'b0),
.VAR34(1'b0),
.VAR22(1'b0),
.VAR3(1'b0),
.VAR26(1'b0),
.VAR17(),
.VAR2(),
.VAR41(),
.VAR14(),
.VAR4(),
.VAR20(),
.VAR37(VAR25), .VAR11(),
.VAR45(),
.VAR7(),
.VAR6(),
.VAR5(VAR15),
.VAR21(),
.VAR1(),
.VAR47(),
.VAR13()
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv_8.v | 2,052 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR5,
VAR1,
VAR6 ,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR6 ;
input VAR4 ;
VAR2 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR5;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR4 ;
VAR2 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/image_filter_mul_8ns_24ns_31_3.v | 1,411 | module MODULE1(clk, VAR5, VAR12, VAR10, VAR7);
input clk;
input VAR5;
input[8 - 1 : 0] VAR12; input[24 - 1 : 0] VAR10; output[31 - 1 : 0] VAR7;
reg [8 - 1 : 0] VAR11;
reg [24 - 1 : 0] VAR1;
wire [31 - 1 : 0] VAR9;
reg [31 - 1 : 0] VAR8;
assign VAR7 = VAR8;
assign VAR9 = VAR11 * VAR1;
always @ (posedge clk) begin
if (VAR5) begin
VAR11 <= VAR12;
VAR1 <= VAR10;
VAR8 <= VAR9;
end
end
endmodule
module MODULE2(
clk,
reset,
VAR5,
VAR14,
VAR4,
dout);
parameter VAR3 = 32'd1;
parameter VAR2 = 32'd1;
parameter VAR13 = 32'd1;
parameter VAR6 = 32'd1;
parameter VAR16 = 32'd1;
input clk;
input reset;
input VAR5;
input[VAR13 - 1:0] VAR14;
input[VAR6 - 1:0] VAR4;
output[VAR16 - 1:0] dout;
MODULE1 VAR15(
.clk( clk ),
.VAR5( VAR5 ),
.VAR12( VAR14 ),
.VAR10( VAR4 ),
.VAR7( dout ));
endmodule | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/011J1G2/hdl/j1soc.v | 4,224 | module MODULE1#(
parameter VAR41 = "../VAR26/VAR30/VAR6.VAR11" )
(VAR22, VAR19,
VAR5, VAR32,
VAR43, VAR20,VAR8,VAR15,VAR46,VAR27, VAR47,VAR9);
input VAR5, VAR32;
output VAR22;
output VAR19;
input VAR20;
output VAR43;
output VAR15;
output VAR8;
output VAR46;
input VAR27;
output VAR14;
input VAR42;
wire VAR24; wire VAR28; wire [15:0] VAR3; reg [15:0] VAR17; wire [15:0] VAR37;
reg [1:8]VAR38;
wire [15:0] VAR31;
wire [15:0] VAR40;
wire VAR49; wire [15:0] VAR51;
wire [15:0] VAR21;
wire [15:0] VAR2;
wire [15:0] VAR1;
VAR6 #(VAR41) VAR7(VAR5, VAR32, VAR17, VAR24, VAR28, VAR3, VAR37);
VAR39 VAR50 (.clk(VAR5), .rst(VAR32), .din(VAR37), .VAR38(VAR38[5]), .addr(VAR3[3:0]), .rd(VAR24), .wr(VAR28), .dout(VAR31) );
VAR16 VAR45 (.clk(VAR5), .rst(VAR32), .din(VAR37), .VAR38(VAR38[6]), .addr(VAR3[3:0]), .rd(VAR24), .wr(VAR28), .dout(VAR40));
VAR18 VAR23 (.clk(VAR5), .rst(VAR32), .din(VAR37), .VAR38(VAR38[7]), .addr(VAR3[3:0]), .rd(VAR24), .wr(VAR28), .dout(VAR49), .VAR22(VAR22), .VAR19(VAR19));
VAR12 VAR44 (.clk(VAR5), .rst(VAR32), .din(VAR37), .VAR38(VAR38[8]), .addr(VAR3[3:0]), .rd(VAR24), .wr(VAR28), .dout(VAR21), .VAR22(VAR43), .VAR52(VAR20));
VAR33 VAR29 (.clk(VAR5), .rst(VAR32), .din(VAR37), .VAR38(VAR38[3]), .addr(VAR3[3:0]), .rd(VAR24), .wr(VAR28), .dout(VAR2),.VAR15(VAR15),. VAR8(VAR8),. VAR46(VAR34),.VAR27(VAR27) );
VAR4 VAR35 (.clk(VAR5), .rst(VAR32), .din(VAR37), .VAR38(VAR38[1]), .addr(VAR3[3:0]), .rd(VAR24), .wr(VAR28), .dout(VAR2),.VAR15(VAR15),. VAR8(VAR8),. VAR47(VAR47),.VAR9(VAR9) );
VAR48 VAR13 ( .clk(VAR5) , .rst(VAR32) , .din(VAR37) , .VAR38(VAR38[2]) , .addr(VAR3[3:0]) , .rd(VAR24) , .wr(VAR28), .dout(VAR1), .VAR14(VAR14), .VAR42(VAR42) )
VAR36 VAR25(.clk(VAR5), .din(VAR37), .VAR38(VAR38[9]), .addr(VAR3[7:0]), .rd(VAR24), .wr(VAR28), .dout(VAR51));
always @*
begin
case (VAR3[15:8])
8'h63: VAR38= 8'b10000000; 8'h64: VAR38= 8'b01000000; 8'h65: VAR38= 8'b00100000; 8'h66: VAR38= 8'b00010000; 8'h67: VAR38= 8'b00001000; 8'h68: VAR38= 8'b00000100; 8'h69: VAR38= 8'b00000010; 8'h70: VAR38= 8'b00000001; default: VAR38= 8'b0000000;
endcase
end
always @*
begin
case (VAR38)
8'b10000000: VAR17 = VAR10;
8'b01000000: VAR17 = VAR1;
8'b00100000: VAR17 = VAR2;
8'b00010000: VAR17 = VAR21;
8'b00001000: VAR17 = VAR31;
8'b00000100: VAR17 = VAR40;
8'b00000010: VAR17 = VAR49;
8'b00000001: VAR17 = VAR51;
default: VAR17 = 16'h0666;
endcase
end
endmodule | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_sram_cs.v | 1,884 | module MODULE1 (
address,
clk,
VAR4,
VAR5,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input VAR4;
input VAR5;
wire VAR1;
wire VAR2;
wire VAR6;
reg [ 31: 0] VAR3;
assign VAR1 = 1;
assign VAR6 = {1 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR5)
begin
if (VAR5 == 0)
VAR3 <= 0;
end
else if (VAR1)
VAR3 <= {32'b0 | VAR6};
end
assign VAR2 = VAR4;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp.behavioral.pp.v | 3,037 | module MODULE1 (
VAR4 ,
VAR28 ,
VAR12 ,
VAR30 ,
VAR17 ,
VAR29 ,
VAR33,
VAR1 ,
VAR7 ,
VAR9 ,
VAR31
);
output VAR4 ;
output VAR28 ;
input VAR12 ;
input VAR30 ;
input VAR17 ;
input VAR29 ;
input VAR33;
input VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR31 ;
wire VAR23 ;
wire VAR10 ;
wire VAR8 ;
reg VAR26 ;
wire VAR3 ;
wire VAR6 ;
wire VAR19 ;
wire VAR18;
wire VAR32 ;
wire VAR22 ;
wire VAR11 ;
wire VAR15 ;
wire VAR16 ;
wire VAR27 ;
wire VAR21 ;
not VAR25 (VAR10 , VAR18 );
VAR5 VAR14 (VAR8, VAR3, VAR6, VAR19 );
VAR20 VAR13 (VAR23 , VAR8, VAR32, VAR10, VAR26, VAR1, VAR7);
assign VAR22 = ( VAR1 === 1'b1 );
assign VAR11 = ( ( VAR18 === 1'b1 ) && VAR22 );
assign VAR15 = ( ( VAR19 === 1'b0 ) && VAR11 );
assign VAR16 = ( ( VAR19 === 1'b1 ) && VAR11 );
assign VAR27 = ( ( VAR3 !== VAR6 ) && VAR11 );
assign VAR21 = ( ( VAR33 === 1'b1 ) && VAR22 );
buf VAR24 (VAR4 , VAR23 );
not VAR2 (VAR28 , VAR23 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp.blackbox.v | 1,262 | module MODULE1 (
VAR4 ,
VAR6,
VAR3
);
output VAR4 ;
input VAR6;
input VAR3 ;
supply1 VAR5;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.pp.symbol.v | 1,359 | module MODULE1 (
input VAR1 ,
output VAR7 ,
input VAR5,
input VAR6 ,
input VAR4 ,
input VAR2 ,
input VAR3
);
endmodule | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/altera_reset_controller.v | 12,017 | module MODULE1
parameter VAR72 = 6,
parameter VAR63 = 0,
parameter VAR45 = 0,
parameter VAR16 = 0,
parameter VAR44 = 0,
parameter VAR12 = 0,
parameter VAR62 = 0,
parameter VAR64 = 0,
parameter VAR17 = 0,
parameter VAR48 = 0,
parameter VAR78 = 0,
parameter VAR65 = 0,
parameter VAR35 = 0,
parameter VAR22 = 0,
parameter VAR49 = 0,
parameter VAR13 = 0,
parameter VAR60 = 0,
parameter VAR4 = "VAR67",
parameter VAR15 = 2,
parameter VAR54 = 0,
parameter VAR46 = 3,
parameter VAR66 = 11,
parameter VAR55 = 4,
parameter VAR7 = 0
)
(
input VAR8,
input VAR30,
input VAR25,
input VAR74,
input VAR53,
input VAR10,
input VAR38,
input VAR26,
input VAR19,
input VAR40,
input VAR75,
input VAR58,
input VAR47,
input VAR6,
input VAR11,
input VAR21,
input VAR79,
input VAR71,
input VAR14,
input VAR20,
input VAR61,
input VAR69,
input VAR70,
input VAR28,
input VAR80,
input VAR68,
input VAR59,
input VAR31,
input VAR34,
input VAR27,
input VAR73,
input VAR52,
input clk,
output reg VAR32,
output reg VAR9
);
localparam VAR36 = (VAR4 == "VAR67");
localparam VAR29 = 3;
localparam VAR33 = VAR29 + VAR46;
localparam VAR5 = VAR46 > VAR55 ? VAR46 : VAR55;
localparam VAR42 = (VAR29 > VAR5) ?
VAR66 + 1 :
(
(VAR66 > VAR5)?
VAR66 + (VAR5 - VAR29 + 1) + 1 :
VAR66 + VAR55 + VAR46 - VAR29 + 2
);
localparam VAR2 = VAR55 + 1;
wire VAR43;
wire VAR76;
wire VAR56;
wire VAR37;
reg [VAR33: 0] VAR77;
reg [VAR42-1: 0] VAR23;
reg VAR57;
reg VAR50;
assign VAR43 = (
VAR8 |
VAR30 |
VAR25 |
VAR74 |
VAR53 |
VAR10 |
VAR38 |
VAR26 |
VAR19 |
VAR40 |
VAR75 |
VAR58 |
VAR47 |
VAR6 |
VAR11 |
VAR21
);
assign VAR76 = (
( (VAR63 == 1) ? VAR79 : 1'b0) |
( (VAR45 == 1) ? VAR71 : 1'b0) |
( (VAR16 == 1) ? VAR14 : 1'b0) |
( (VAR44 == 1) ? VAR20 : 1'b0) |
( (VAR12 == 1) ? VAR61 : 1'b0) |
( (VAR62 == 1) ? VAR69 : 1'b0) |
( (VAR64 == 1) ? VAR70 : 1'b0) |
( (VAR17 == 1) ? VAR28 : 1'b0) |
( (VAR48 == 1) ? VAR80 : 1'b0) |
( (VAR78 == 1) ? VAR68 : 1'b0) |
( (VAR65 == 1) ? VAR59 : 1'b0) |
( (VAR35 == 1) ? VAR31 : 1'b0) |
( (VAR22 == 1) ? VAR34 : 1'b0) |
( (VAR49 == 1) ? VAR27 : 1'b0) |
( (VAR13 == 1) ? VAR73 : 1'b0) |
( (VAR60 == 1) ? VAR52 : 1'b0)
);
generate if (VAR4 == "none" && (VAR54==0)) begin
assign VAR56 = VAR43;
assign VAR37 = VAR76;
end else begin
VAR24
.VAR39 (VAR15),
.VAR36(VAR54? 1'b1 : VAR36)
)
VAR3
(
.clk (clk),
.VAR1 (VAR43),
.VAR32 (VAR56)
);
VAR24
.VAR39 (VAR15),
.VAR36(0)
)
VAR51
(
.clk (clk),
.VAR1 (VAR76),
.VAR32 (VAR37)
);
end
endgenerate
generate if ( ( (VAR54 == 0) && (VAR7==0) )|
( (VAR7 == 1) && (VAR4 != "VAR67") ) ) begin
always @* begin
VAR32 = VAR56;
VAR9 = VAR37;
end
end else if ( (VAR54 == 0) && (VAR7==1) ) begin
wire VAR18;
VAR24
.VAR39 (VAR15+1),
.VAR36(0)
)
VAR41
(
.clk (clk),
.VAR1 (VAR56),
.VAR32 (VAR18)
);
always @* begin
VAR32 = VAR18;
VAR9 = VAR37;
end
end
else begin
begin
begin
begin
begin
begin
end
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o.pp.blackbox.v | 1,428 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR1 ,
VAR8 ,
VAR4 ,
VAR2 ,
VAR7,
VAR6,
VAR3 ,
VAR10
);
output VAR9 ;
input VAR5 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR7;
input VAR6;
input VAR3 ;
input VAR10 ;
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_obc1/main.v | 23,107 | module MODULE1(
output [22:0] VAR173,
output VAR116,
input VAR62,
output VAR250,
input VAR268,
output [21:0] VAR173,
output VAR349,
output VAR32,
output VAR277,
output VAR93,
output VAR141,
input VAR82,
input VAR256,
input [23:0] VAR30,
input VAR246,
input VAR52,
input VAR121,
inout [7:0] VAR244,
input VAR162,
input VAR103,
output VAR232,
output VAR266,
output VAR216,
input VAR111,
input [7:0] VAR19,
input VAR91,
input VAR251,
inout [15:0] VAR245,
output VAR158,
output VAR156,
output VAR247,
output VAR36,
inout [7:0] VAR295,
output [18:0] VAR135,
output VAR351,
output VAR229,
input VAR6,
inout VAR94,
input VAR10,
input VAR24,
output VAR13,
output VAR99,
output VAR197,
output VAR236,
input [3:0] VAR159,
inout VAR353,
inout VAR155
);
wire VAR333;
wire [7:0] VAR27;
wire [7:0] VAR37;
wire [7:0] VAR104;
wire [31:0] VAR106;
wire [2:0] VAR51;
wire [23:0] VAR317;
wire [2:0] VAR332;
wire [23:0] VAR55;
wire [23:0] VAR293;
wire [7:0] VAR298;
wire [1:0] VAR114;
wire [10:0] VAR281;
wire [10:0] VAR154;
wire [10:0] VAR190;
wire [2:0] VAR57;
wire [8:0] VAR326;
wire [7:0] VAR140;
wire [7:0] VAR74;
wire [31:0] VAR45;
wire [15:0] VAR85;
wire [13:0] VAR338;
wire [13:0] VAR129;
wire [7:0] VAR127;
wire [7:0] VAR23;
wire [5:0] VAR300;
wire [5:0] VAR269;
wire [15:0] VAR33;
wire VAR5 = VAR33[5];
wire [23:0] VAR314;
wire VAR153;
wire [7:0] VAR71;
wire [7:0] VAR22;
wire [13:0] VAR43;
wire VAR128;
wire VAR67;
wire VAR352;
wire [2:0] VAR344;
wire [10:0] VAR29;
wire [8:0] VAR157;
wire [7:0] VAR107;
wire [7:0] VAR118;
reg [7:0] VAR80 = 8'b11111111;
reg [7:0] VAR206 = 8'b11111111;
reg [7:0] VAR316 = 8'b11111111;
reg [7:0] VAR70 = 8'b11111111;
reg [7:0] VAR302 = 8'b00000000;
reg [7:0] VAR296 = 8'b11111111;
reg [7:0] VAR138 = 8'b11111111;
reg [23:0] VAR126 [6:0];
reg [7:0] VAR21 [6:0];
reg [7:0] VAR271 [4:0];
reg VAR249 = 1;
reg VAR58 = 0;
reg VAR299 = 0;
wire [23:0] VAR325 = (VAR126[5] & VAR126[4]);
wire [7:0] VAR225 = (VAR21[5] & VAR21[4]);
wire [7:0] VAR220 = (VAR271[3] & VAR271[2]);
wire VAR174 = VAR246 & VAR52 & ~VAR162;
wire VAR87 = (VAR138[6:1] == 6'b000011);
wire VAR320 = (VAR80[6:1] == 6'b111110);
wire VAR200 = (VAR80[6:1] == 6'b000001);
wire VAR102 = (VAR206[7:1] == (({VAR325[22], VAR325[15:0]} == 17'h02100) ? 7'b1110000 : 7'b1000000));
wire VAR286 = (VAR206[6:1] == 6'b000001);
wire VAR240 = (VAR316[6:1] == 6'b111110);
wire VAR346 = (VAR316[6:1] == 6'b000001);
wire VAR243 = (VAR70[6:1] == 6'b000001);
wire VAR280 = (VAR302[6:1] == 6'b000001);
wire VAR347 = (VAR302[6:1] == 6'b111110);
wire VAR54 = VAR70[2] & VAR70[1];
wire VAR202 = VAR316[2] & VAR316[1];
wire VAR324 = VAR316[5] & VAR316[4];
wire VAR31 = VAR202 | VAR324;
wire VAR177 = VAR302[2] & VAR302[1];
wire VAR79 = VAR80[2] & VAR80[1];
wire VAR47 = VAR206[2] & VAR206[1];
wire VAR117 = (VAR296[5] & VAR296[4]);
reg [7:0] VAR238;
always @(posedge VAR333) begin
if(~VAR202) VAR238 <= VAR244;
end
else if(~VAR54) VAR238 <= VAR220;
end
wire VAR46;
wire VAR307 = (VAR87 | VAR299) & ~VAR46;
wire VAR335;
assign VAR311=0;
always @(posedge VAR333) begin
VAR299 <= 1'b0;
if(VAR280) VAR299 <= ~VAR335;
end
always @(posedge VAR333) begin
VAR138 <= {VAR138[6:0], VAR174};
VAR80 <= {VAR80[6:0], VAR91};
VAR206 <= {VAR206[6:0], VAR251};
VAR316 <= {VAR316[6:0], VAR246};
VAR70 <= {VAR70[6:0], VAR52};
VAR302 <= {VAR302[6:0], VAR162};
VAR296 <= {VAR296[6:0], VAR121};
VAR126[6] <= VAR126[5];
VAR126[5] <= VAR126[4];
VAR126[4] <= VAR126[3];
VAR126[3] <= VAR126[2];
VAR126[2] <= VAR126[1];
VAR126[1] <= VAR126[0];
VAR126[0] <= VAR30;
VAR21[6] <= VAR21[5];
VAR21[5] <= VAR21[4];
VAR21[4] <= VAR21[3];
VAR21[3] <= VAR21[2];
VAR21[2] <= VAR21[1];
VAR21[1] <= VAR21[0];
VAR21[0] <= VAR19;
VAR271[4] <= VAR271[3];
VAR271[3] <= VAR271[2];
VAR271[2] <= VAR271[1];
VAR271[1] <= VAR271[0];
VAR271[0] <= VAR244;
end
VAR112 VAR28(
.VAR148(VAR333),
.VAR159(VAR159),
.VAR155(VAR155),
.VAR109(VAR109),
.VAR213(VAR213),
.VAR291(VAR291),
.VAR298(VAR298),
.VAR151(VAR151),
.VAR88(VAR88),
.VAR281(VAR281),
.VAR154(VAR154),
.VAR214(VAR214),
.VAR65(VAR65),
.VAR267(VAR29),
.VAR168(VAR344)
);
assign VAR46 = (VAR213 && (VAR114 == 2'b00));
VAR131 VAR342(
.VAR134(VAR333),
.VAR63(VAR111),
.VAR254(VAR99),
.VAR341(VAR197),
.VAR4(VAR236),
.VAR258(VAR114==2'b01 ? VAR291 : 1'b1),
.VAR274(VAR190),
.VAR234(VAR298),
.VAR2(VAR2),
.VAR122(VAR140),
.VAR40(VAR339),
.VAR120(VAR57),
.VAR204(VAR288),
.VAR34(VAR96),
.reset(VAR290),
.VAR188(VAR326)
);
VAR89 VAR322 (
.VAR134(VAR333),
.enable(VAR212),
.VAR274(VAR338),
.VAR234(VAR298),
.VAR227(VAR114==2'b10 ? VAR291 : 1'b1),
.VAR275(VAR325[2:0]),
.VAR330(VAR127),
.VAR69(VAR23),
.VAR139(VAR240),
.VAR194(VAR346),
.VAR147(VAR243),
.VAR328(VAR74),
.VAR17(VAR140),
.VAR199(VAR339),
.VAR260(VAR45),
.VAR35(VAR85),
.VAR92(VAR300),
.VAR348(VAR269),
.VAR143(VAR209),
.VAR294(VAR129),
.VAR223(VAR146),
.VAR128(VAR128),
.VAR67(VAR67),
.VAR352(VAR352),
.VAR43(VAR43),
.VAR235(VAR235)
);
VAR86 VAR261(
.clk(VAR333),
.VAR125(VAR6),
.VAR60(VAR94),
.VAR226(VAR10),
.VAR219(VAR24),
.VAR221(VAR207),
.VAR20(VAR192),
.VAR76(VAR27),
.VAR163(VAR37),
.VAR289(VAR68),
.VAR124(VAR276),
.VAR222(VAR104),
.VAR169(VAR106),
.VAR97(VAR51)
);
VAR145 VAR345 (
.clk(VAR333),
.enable(VAR152),
.VAR292(VAR71),
.VAR49(VAR22),
.VAR11(VAR325[12:0]),
.VAR147(VAR243)
);
reg [7:0] VAR178;
wire [7:0] VAR73;
wire [31:0] VAR323;
wire [7:0] VAR59;
wire [2:0] VAR285;
VAR257 VAR340(
.clk(VAR333),
.VAR312(VAR111),
.VAR221(VAR207),
.VAR20(VAR192),
.VAR76(VAR27),
.VAR163(VAR37),
.VAR72(VAR332),
.VAR331(VAR3),
.VAR210(VAR178),
.VAR343(VAR73),
.VAR106(VAR106),
.VAR51(VAR51),
.VAR149(VAR104),
.VAR260(VAR317),
.VAR259(VAR55),
.VAR133(VAR293),
.VAR109(VAR109),
.VAR213(VAR213),
.VAR151(VAR151),
.VAR298(VAR298),
.VAR291(VAR291),
.VAR114(VAR114),
.VAR88(VAR88),
.VAR281(VAR281),
.VAR154(VAR154),
.VAR214(VAR214),
.VAR65(VAR65),
.VAR123(VAR190),
.VAR2(VAR2),
.VAR175(VAR96),
.VAR66(VAR290),
.VAR57(VAR57),
.VAR288(VAR288),
.VAR105(VAR326),
.VAR321(VAR338),
.VAR160(VAR74),
.VAR284(VAR300),
.VAR8(VAR269),
.VAR209(VAR209),
.VAR185(VAR140),
.VAR132(VAR45),
.VAR164(VAR85),
.VAR161(VAR129),
.VAR9(VAR146),
.VAR189(VAR33),
.VAR110(VAR211),
.VAR142(VAR167),
.VAR137(VAR13),
.VAR279(VAR297),
.VAR195(VAR157),
.VAR319(VAR241),
.VAR18(VAR107),
.VAR237(VAR118),
.VAR144(VAR285),
.VAR263(VAR323),
.VAR313(VAR90)
);
address VAR50(
.VAR148(VAR333),
.VAR332(VAR332),
.VAR33(VAR33),
.VAR325(VAR325), .VAR225(VAR225),
.VAR117(VAR117),
.VAR173(VAR314), .VAR335(VAR335),
.VAR309(VAR309),
.VAR42(VAR42),
.VAR115(VAR115),
.VAR55(VAR55),
.VAR293(VAR293),
.VAR212(VAR212),
.VAR119(VAR119),
.VAR166(VAR166),
.VAR152(VAR152),
.VAR315(VAR315),
.VAR48(VAR48),
.VAR310(VAR310),
.VAR193(VAR193),
.VAR150(VAR150),
.VAR100(VAR100)
);
reg VAR253 = 0;
reg [4:0] VAR218 = 0;
reg VAR184 = 0;
parameter VAR77 = 5'b00001;
parameter VAR182 = 5'b00010;
parameter VAR61 = 5'b00100;
parameter VAR329 = 5'b01000;
parameter VAR308 = 5'b10000;
parameter VAR7 = 17'd96000;
parameter VAR283 = 4'd8;
reg [4:0] VAR318;
VAR171 VAR318 = VAR77;
assign VAR127 = VAR238;
assign VAR71 = VAR238;
VAR78 VAR196(
.clk(VAR333),
.VAR325(VAR325),
.VAR225(VAR225),
.VAR244(VAR244),
.VAR58(VAR58),
.VAR280(VAR280),
.VAR239(VAR243),
.VAR95(VAR240),
.VAR315(VAR315),
.VAR48(VAR48),
.VAR310(VAR310),
.VAR193(VAR193),
.VAR150(VAR150),
.VAR100(VAR100),
.VAR253(VAR253),
.VAR184(VAR184),
.VAR172(VAR285),
.VAR227(VAR90),
.VAR108(VAR323),
.VAR49(VAR59),
.VAR233(VAR233),
.VAR255(VAR255)
);
wire [7:0] VAR44;
parameter VAR265 = 4'b0001;
parameter VAR201 = 4'b0010;
parameter VAR83 = 4'b0100;
parameter VAR208 = 4'b1000;
reg [7:0] VAR304;
reg VAR14;
reg [2:0] VAR303;
reg [1:0] VAR187;
VAR171 VAR304 = 8'h55;
VAR171 VAR14 = 0;
VAR171 VAR187 = 2'b01;
VAR171 VAR303 = 3'b000;
reg [7:0] VAR215 = 0;
reg VAR1 = 0;
reg VAR179 = 0;
wire [3:0] VAR198 = VAR33[10:7];
wire [3:0] VAR334 = (VAR244[3:0] > VAR198) ? VAR198 : VAR244[3:0];
wire VAR306 = VAR33[6];
wire VAR337 = VAR166 & (VAR306 | ~(&VAR198));
wire VAR301 = {VAR325[22], VAR325[15:0]} == 17'h04200;
wire VAR113 = {VAR325[22], VAR325[15:0]} == 17'h04016;
always @(posedge VAR333) begin
VAR1 <= VAR179;
end
always @(posedge VAR333) begin
if(VAR243 & VAR301) begin
VAR184 <= VAR244[0];
end
end
always @(posedge VAR333) begin
if(VAR243 & VAR113) begin
VAR253 <= 1'b1;
VAR218 <= 5'h0;
end
if(VAR240 & VAR113) begin
VAR218 <= VAR218 + 1;
if(&VAR218[3:0]) begin
VAR253 <= 1'b0;
end
end
end
assign VAR244 = (VAR119 & ~VAR79 & ~VAR14) ? VAR304
:(VAR337 & ~VAR47 & VAR1) ? VAR215
:((~VAR202 ^ (VAR14 & VAR119 & ~VAR79))
& ~(VAR337 & ~VAR47 & ~VAR1 & ~VAR42 & ~VAR115))
? (VAR212 ? VAR23
:VAR152 ? VAR22
:(VAR233 & ~VAR5) ? VAR59
:((VAR255 | VAR5) & VAR315) ? VAR44
:(VAR153 ? VAR245[7:0] : VAR245[15:8])) : 8'VAR230;
reg [3:0] VAR26;
reg VAR231 = 0;
reg VAR186 = 0;
reg [23:0] VAR270;
reg VAR165;
VAR171 VAR165 = 1'b1;
assign VAR13 = VAR165;
wire VAR228 = |(VAR318 & VAR329);
wire VAR287 = |(VAR318 & (VAR329 | VAR308));
wire VAR41 = |(VAR318 & (VAR182 | VAR61));
wire VAR130 = VAR287 | VAR41;
VAR39 VAR350(
.VAR256(VAR256),
.VAR15(VAR333),
.VAR305(VAR16),
.VAR84(VAR311)
);
assign VAR173 = (VAR46) ? VAR317[23:1] : VAR130 ? VAR270[23:1] : VAR314[23:1];
assign VAR153 = (VAR46) ? VAR317[0] : VAR130 ? VAR270[0] : VAR314[0];
assign VAR116 = 1'b0;
assign VAR250 = 1'b0;
VAR183 VAR176 (
.VAR136(VAR333), .VAR264(VAR243 & ((VAR255 | VAR5) & VAR315)), .VAR181(VAR325[8:0]), .VAR273(VAR244), .VAR203(VAR44), .VAR282(VAR333), .VAR272(VAR241), .VAR56(VAR157), .VAR53(VAR107), .VAR262(VAR118) );
VAR278 VAR336(
.VAR64(VAR256),
.VAR38(VAR333),
.VAR12(VAR16),
.VAR101(VAR311)
);
wire VAR242;
assign VAR242 = (VAR46) ? VAR317[1] : VAR130 ? VAR270[1] : VAR314[1];
assign VAR173 = (VAR46) ? VAR317[23:2] : VAR130 ? VAR270[23:2] : VAR314[23:2];
assign VAR153 = (VAR46) ? VAR317[0] : VAR130 ? VAR270[0] : VAR314[0];
assign VAR277 = 1'b1;
assign VAR349 = VAR242;
assign VAR32 = ~VAR242;
VAR183 VAR176 (
.VAR327(VAR333), .VAR224(VAR243 & ((VAR255 | VAR5) & VAR315)), .VAR81(VAR325[8:0]), .VAR180(VAR244), .VAR191(VAR44), .VAR75(VAR241), .VAR248(VAR157), .VAR170(VAR107), .VAR25(VAR118) );
assign VAR158 = 1'b0;
reg[17:0] VAR252;
VAR171 VAR252 = 0;
always @(posedge VAR333) begin
if(VAR211) begin
VAR231 <= 1'b1;
VAR165 <= 1'b0;
VAR270 <= VAR317;
end else if(VAR167) begin
VAR186 <= 1'b1;
VAR165 <= 1'b0;
VAR270 <= VAR317;
end else if(VAR318 & (VAR61 | VAR308)) begin
VAR231 <= 1'b0;
VAR186 <= 1'b0;
VAR165 <= 1'b1;
end
end
always @(posedge VAR333) begin
if(~VAR302[1]) VAR252 <= VAR252 + 1;
end
else VAR252 <= 17'h0;
end
always @(posedge VAR333) begin
VAR58 <= 1'b0;
if(VAR302[1]) begin
VAR249 <= 1'b0;
if(VAR249) VAR58 <= 1'b1;
end
else if(VAR252 > VAR7) VAR249 <= 1'b1;
end
always @(posedge VAR333) begin
end
if(VAR249 & VAR302[1]) VAR318 <= VAR77; else
case(VAR318)
VAR77: begin
VAR318 <= VAR77;
if(VAR307 | VAR249) begin
if(VAR231) begin
VAR318 <= VAR182;
VAR26 <= VAR283;
end else if(VAR186) begin
VAR318 <= VAR329;
VAR26 <= VAR283;
end
end
end
VAR182: begin
VAR318 <= VAR182;
VAR26 <= VAR26 - 1;
if(VAR26 == 0) VAR318 <= VAR61;
VAR178 <= (VAR153 ? VAR245[7:0] : VAR245[15:8]);
end
VAR329: begin
VAR318 <= VAR329;
VAR26 <= VAR26 - 1;
if(VAR26 == 0) VAR318 <= VAR308;
end
VAR61, VAR308: begin
VAR318 <= VAR77;
end
endcase
end
always @(posedge VAR333) begin
case(VAR187)
VAR208: begin
VAR187 <= VAR208;
if(VAR87) begin
VAR14 <= 1'b1;
VAR187 <= VAR265;
end
end
VAR265: begin
VAR187 <= VAR265;
if(VAR320 & VAR119) begin
VAR303 <= 3'b001;
VAR187 <= VAR201;
end
end
VAR201: begin
VAR187 <= VAR201;
VAR303 <= VAR303 - 1;
if(VAR303 == 3'b000) begin
VAR187 <= VAR83;
VAR304 <= {VAR244[7:5], VAR297, VAR244[3:0]};
end
end
VAR83: begin
VAR187 <= VAR208;
VAR14 <= 1'b0;
end
endcase
end
reg [3:0] VAR217 = 0;
reg [3:0] VAR98 = 0;
always @(posedge VAR333) begin
if(VAR87) VAR179 <= 1'b0;
end
else if(VAR102 & VAR166) begin
if(VAR306 & VAR244[7]) begin
VAR179 <= 1'b1;
VAR215 <= {VAR244[7], 3'b010, VAR217}; end else if (VAR306 && VAR244 == 8'h00 && VAR215[7]) begin
VAR179 <= 1'b1;
VAR215 <= {1'b1, 3'b111, VAR217}; end else if (VAR306 && VAR244[3:0] < 4'h8 && VAR98 > 4'hd) begin
VAR179 <= 1'b1;
VAR215 <= {VAR244[7], 3'b011, 4'h0}; end else if (VAR306 | ~(&VAR198)) begin
VAR217 <= VAR334;
VAR98 <= VAR244[3:0];
if (~(&VAR198) && VAR244[3:0] > VAR198) begin
VAR179 <= 1'b1;
VAR215 <= {VAR244[7], 3'b100, VAR334}; end
end
end
end
reg VAR205;
always @(posedge VAR333) begin
VAR205<= VAR3;
end
assign VAR245[7:0] = VAR153
?(VAR46 ? (!VAR205 ? VAR73 : 8'VAR230)
: (VAR335 & ~VAR54) ? VAR244
: VAR287 ? VAR73 : 8'VAR230
)
:8'VAR230;
assign VAR245[15:8] = VAR153 ? 8'VAR230
:(VAR46 ? (!VAR205 ? VAR73 : 8'VAR230)
: (VAR335 & ~VAR54) ? VAR244
: VAR287 ? VAR73
: 8'VAR230
);
assign VAR156 = VAR46
?VAR3
: (VAR335 & VAR115 & VAR177) ? VAR54
: VAR228 ? 1'b0
: 1'b1;
assign VAR247 = VAR153;
assign VAR36 = ~VAR153;
assign VAR266 = VAR152 & ~(VAR31 & VAR54) ? 1'b0 :
VAR212 & ~(VAR31 & VAR54) ? 1'b0 :
VAR315 & ~(VAR31 & VAR54) ? ~(VAR255 | VAR5) :
(VAR119 & !VAR79) ? 1'b0 :
(VAR337 & ~VAR47) ? 1'b0 :
VAR301 ? VAR54
: ((VAR42 & VAR117)
|(!VAR42 & !VAR309 & !VAR115)
|(VAR31 & VAR54)
);
assign VAR216 = (~VAR202 | (~VAR79 & (VAR119)))
? (1'b1 ^ (VAR14 & VAR119 & ~VAR79)
^ (VAR337 & ~VAR47 & ~VAR1 & ~VAR42 & ~VAR115))
: ((~VAR47 & VAR337) ? VAR1
: 1'b0);
assign VAR232 = 1'b0;
endmodule | gpl-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_addr_arbiter.v | 13,806 | module MODULE1 #
(
parameter VAR37 = "none",
parameter integer VAR39 = 1,
parameter integer VAR56 = 1,
parameter integer VAR66 = 1,
parameter integer VAR11 = 1,
parameter [VAR39*32-1:0] VAR23 = {VAR39{32'h00000000}}
)
(
input wire VAR22,
input wire VAR43,
input wire [VAR39*VAR11-1:0] VAR32,
input wire [VAR39*VAR66-1:0] VAR34,
input wire [VAR39-1:0] VAR18,
input wire [VAR39-1:0] VAR48,
output wire [VAR39-1:0] VAR60,
output wire [VAR11-1:0] VAR24,
output wire [VAR66-1:0] VAR35,
output wire [VAR56-1:0] VAR21,
output wire VAR64,
input wire VAR42,
input wire [VAR66-1:0] VAR29
);
function [VAR39-1:0] VAR50
(
input integer VAR38
);
reg [VAR39-1:0] VAR17;
integer VAR47;
begin
VAR17 = 0;
for (VAR47=0; VAR47 < VAR39; VAR47=VAR47+1) begin
VAR17[VAR47] = (VAR23[VAR47*32+:32] != 0);
end
VAR50 = VAR17;
end
endfunction
function [3:0] VAR72
(
input [15:0] VAR36
);
begin
VAR72[0] = |(VAR36 & 16'b1010101010101010);
VAR72[1] = |(VAR36 & 16'b1100110011001100);
VAR72[2] = |(VAR36 & 16'b1111000011110000);
VAR72[3] = |(VAR36 & 16'b1111111100000000);
end
endfunction
localparam [VAR39-1:0] VAR9 = VAR50(0);
reg VAR3;
reg [VAR39-1:0] VAR28;
reg [VAR39-1:0] VAR27;
reg [VAR39-1:0] VAR14;
reg [VAR39-1:0] VAR71;
reg VAR7;
reg VAR15;
reg VAR63;
reg [VAR39-1:0] VAR57;
reg [VAR39-1:0] VAR61;
reg [VAR56-1:0] VAR49;
reg [VAR56-1:0] VAR45;
reg [4:0] VAR74;
wire [VAR39-1:0] VAR4;
reg [15:0] VAR16;
reg [VAR56-1:0] VAR26;
reg [VAR39*VAR39-1:0] VAR44;
reg [VAR39*VAR39-1:0] VAR55;
reg VAR25;
wire [VAR39-1:0] VAR46;
wire [VAR56-1:0] VAR52;
reg VAR30;
integer VAR47;
wire [VAR39-1:0] VAR53;
reg [VAR56-1:0] VAR54;
reg [VAR66-1:0] VAR1;
wire [VAR66-1:0] VAR59;
reg [VAR11-1:0] VAR41;
wire [VAR11-1:0] VAR68;
genvar VAR20;
assign VAR64 = VAR3;
assign VAR60 = VAR28;
assign VAR21 = VAR54;
assign VAR24 = VAR41;
assign VAR35 = VAR1;
generate
if (VAR39>1) begin : VAR19
always @(posedge VAR22) begin
if (VAR43) begin
VAR27 <= 0;
end else begin
VAR27 <= VAR53 | ~VAR18; end
end
for (VAR20=0; VAR20<VAR39; VAR20=VAR20+1) begin : VAR69
assign VAR53[VAR20] = VAR48[VAR20] & (|(VAR34[VAR20*VAR66+:VAR66] & ~VAR29));
end
assign VAR46 = VAR63 ? VAR61 : VAR16;
assign VAR52 = VAR63 ? VAR45 : VAR26;
always @(posedge VAR22) begin
if (VAR43) begin
VAR3 <= 0;
VAR28 <= 0;
VAR14 <= 0;
VAR7 <= 1'b0;
VAR54 <= 0;
VAR71 <= {1'b1, {VAR39-1{1'b0}}};
VAR1 <= 0;
end else begin
VAR28 <= 0;
if (VAR3) begin
if (VAR42) begin VAR3 <= 1'b0;
VAR14 <= 0;
VAR7 <= 1'b0;
end
end else if (VAR7) begin
VAR3 <= 1'b1;
VAR28 <= VAR14; end else begin
if ((VAR63 | VAR25) & ~VAR30) begin
if (|(VAR46 & VAR53)) begin
VAR14 <= VAR46;
VAR54 <= VAR52;
VAR7 <= 1'b1;
if (~VAR63) begin
VAR71 <= VAR16;
end
VAR1 <= VAR59;
end
end
end
end
end
always @ * begin : VAR31
integer VAR65;
VAR15 = 1'b0;
VAR30 = 1'b0;
VAR57 = 0;
VAR49 = 0;
VAR74 = 0;
for (VAR65=0; VAR65 < VAR39; VAR65=VAR65+1) begin
if (VAR9[VAR65] & VAR18[VAR65] & VAR27[VAR65]) begin
if ({1'b0, VAR23[VAR65*32+:4]} > VAR74) begin
VAR74[0+:4] = VAR23[VAR65*32+:4];
if (VAR28[VAR65]) begin
VAR15 = 1'b0;
VAR30 = 1'b1;
VAR57 = 0;
VAR49 = 0;
end else begin
VAR15 = 1'b1;
VAR57 = 1'b1 << VAR65;
VAR49 = VAR65;
end
end
end
end
VAR63 = VAR15;
VAR61 = VAR57;
VAR45 = VAR49;
end
assign VAR4 = ~VAR9 & VAR18 & ~VAR28 & VAR27;
always @ * begin : VAR10
integer VAR70, VAR75, VAR73;
VAR16 = 0;
for (VAR70=0;VAR70<VAR39;VAR70=VAR70+1) begin
VAR73 = (VAR70>0) ? (VAR70-1) : (VAR39-1);
VAR44[VAR70*VAR39] = VAR71[VAR73];
VAR55[VAR70*VAR39] = ~VAR4[VAR73];
for (VAR75=1;VAR75<VAR39;VAR75=VAR75+1) begin
VAR73 = (VAR70-VAR75 > 0) ? (VAR70-VAR75-1) : (VAR39+VAR70-VAR75-1);
VAR44[VAR70*VAR39+VAR75] = VAR44[VAR70*VAR39+VAR75-1] | (VAR71[VAR73] & VAR55[VAR70*VAR39+VAR75-1]);
if (VAR75 < VAR39-1) begin
VAR55[VAR70*VAR39+VAR75] = VAR55[VAR70*VAR39+VAR75-1] & ~VAR4[VAR73];
end
end
VAR16[VAR70] = VAR4[VAR70] & VAR44[(VAR70+1)*VAR39-1];
end
VAR26 = VAR72(VAR16);
VAR25 = |(VAR16);
end
VAR58 #
(
.VAR37 ("VAR8"),
.VAR51 (VAR39),
.VAR5 (VAR56),
.VAR13 (VAR11)
) VAR6
(
.VAR67 (VAR54),
.VAR2 (VAR32),
.VAR62 (VAR68),
.VAR33 (1'b1)
);
VAR58 #
(
.VAR37 ("VAR8"),
.VAR51 (VAR39),
.VAR5 (VAR56),
.VAR13 (VAR66)
) VAR40
(
.VAR67 (VAR52),
.VAR2 (VAR34),
.VAR62 (VAR59),
.VAR33 (1'b1)
);
always @(posedge VAR22) begin
if (VAR43) begin
VAR41 <= 0;
end else if (~VAR3) begin
VAR41 <= VAR68;
end
end
end else begin : VAR12
assign VAR53 = VAR48 & |(VAR34 & ~VAR29);
always @ (posedge VAR22) begin
if (VAR43) begin
VAR3 <= 1'b0;
VAR28 <= 1'b0;
VAR54 <= 0;
end else begin
VAR28 <= 1'b0;
if (VAR3) begin
if (VAR42) begin
VAR3 <= 1'b0;
end
end else if (VAR18[0] & VAR53[0] & ~VAR28) begin
VAR3 <= 1'b1;
VAR28 <= 1'b1;
VAR1 <= VAR34;
end
end
end
always @(posedge VAR22) begin
if (VAR43) begin
VAR41 <= 0;
end else if (~VAR3) begin
VAR41 <= VAR32;
end
end
end endgenerate
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/of_pre_fifo.v | 8,233 | module MODULE1 #
(
parameter VAR9 = 100, parameter VAR12 = 4, parameter VAR29 = 32 )
(
input clk, input rst, input VAR31, input VAR30, input [VAR29-1:0] din, output VAR25, output [VAR29-1:0] dout );
localparam VAR33
= (VAR12 == 2) ? 1 :
((VAR12 == 3) || (VAR12 == 4)) ? 2 :
(((VAR12 == 5) || (VAR12 == 6) ||
(VAR12 == 7) || (VAR12 == 8)) ? 3 : 'VAR6);
integer VAR4;
reg [VAR29-1:0] VAR15[0:VAR12-1];
reg VAR7;
reg VAR20;
reg [VAR33-1:0] VAR21;
reg [VAR33-1:0] VAR26;
wire [VAR33-1:0] VAR18;
wire [VAR33-1:0] VAR22;
wire [VAR29-1:0] VAR13;
wire VAR32;
task VAR14;
input rd;
input wr;
reg [2:0] VAR1;
reg [2:0] VAR11;
begin
casez ({rd, wr, VAR7, VAR20})
4'b0100: begin
end
4'b0110: begin
end
4'b1000: begin
end
4'b1001: begin
end
4'b1100: begin
end
4'b1101: begin
end
default: begin
end
endcase
end
endtask
assign dout = VAR7 ? din : VAR13;
assign VAR25 = (!VAR7 || VAR30);
always @(posedge clk)
if (rst) begin
end else begin
casez ({VAR7, VAR20, VAR31, VAR30})
4'VAR27: begin
end
4'VAR10: begin
end
4'VAR16: begin
end
4'b0010, 4'b0110, 4'b1000, 4'b1001, 4'b1010: ; 4'b0111: begin
VAR2("VAR8 %VAR24 @%VAR19 VAR17 VAR5 VAR3 and VAR28 write VAR23 in!",
);
end
default: begin
end
endcase
end
assign VAR32 = VAR30 & ((!VAR7 & !VAR31)|(!VAR20 & VAR31));
always @ (posedge clk)
begin
if (VAR32)
end
assign VAR13 = VAR15 [VAR21];
assign VAR18 = (VAR21 + 1'b1)%VAR12;
always @ (posedge clk)
begin
if (rst)
begin
VAR21 <= 'b0;
end
else if ((!VAR7) & (!VAR31))
begin
VAR21 <= VAR18;
end
end
always @ (posedge clk)
begin
if (rst)
begin
VAR7 <= 1'b1;
end
else if (VAR7 & !VAR20 & VAR31 & VAR30)
begin
VAR7 <= 1'b0;
end
else if (!VAR7 & !VAR20 & !VAR31 & !VAR30)
begin
VAR7 <= (VAR18 == VAR26);
end
end
assign VAR22 = (VAR26 + 1'b1)%VAR12;
always @ (posedge clk)
begin
if (rst)
begin
VAR26 <= 'b0;
end
else if ( (VAR30) & ( (!VAR7 & !VAR31) | (!VAR20 & VAR31) ) )
begin
VAR26 <= VAR22;
end
end
always @ (posedge clk)
begin
if (rst)
begin
VAR20 <= 1'b0;
end
else if (!VAR7 & VAR20 & !VAR31 & !VAR30)
begin
VAR20 <= 1'b0;
end
else if (!VAR7 & !VAR20 & VAR31 & VAR30)
begin
VAR20 <= (VAR22 == VAR21);
end
end
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.symbol.v | 1,426 | module MODULE1 (
output VAR4
);
supply0 VAR3;
supply0 VAR1 ;
supply1 VAR2 ;
supply1 VAR5;
endmodule | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/L1/Cache_Control.v | 8,716 | module MODULE1(
input [29:0] VAR31,
input [3:0] VAR13,
input VAR27,
output VAR2,
input VAR5,
output VAR15,
output [29:0] VAR36,
output VAR7,
output VAR38,
input VAR1,
output [3:0] VAR37,
output [6:0] VAR18,
output [3:0] VAR45,
input VAR43,
output VAR12,
output VAR32,
input VAR30,
input [18:0] VAR8,
output VAR17,
output VAR34,
input VAR25,
input VAR24,
input [7:0] VAR20,
output VAR33,
output VAR41,
input [7:0] VAR40,
output VAR35,
output VAR4,
input VAR6,
input VAR22,
output VAR19,
output VAR21
);
parameter VAR16 = 4'b0000;
parameter VAR44 = 4'b0001;
parameter VAR29 = 4'b0010;
parameter VAR14 = 4'b0011;
parameter VAR42 = 4'b0100;
parameter VAR26 = 4'b0101;
parameter VAR39 = 4'b0110;
parameter VAR23 = 4'b1000;
parameter VAR28 = 4'b1010;
reg [3:0] VAR11 ;
reg [3:0] VAR3 ;
wire VAR9;
wire [14:0] VAR10;
assign VAR9 = VAR27 || (|VAR13) || VAR5 ;
assign VAR10 = (VAR11 == VAR26 || VAR11 == VAR39) ?
VAR8 : VAR31[29:11];
assign VAR2 = VAR24;
assign VAR15 = (VAR11 == VAR28) ? 1'b1 : 1'b0;
assign VAR36 = {VAR10, VAR37, 7'h0};
assign VAR7 = (VAR11 == VAR26) ? 1'b1 : 1'b0;
assign VAR38 = (VAR11 == VAR14) ? 1'b1 : 1'b0;
assign VAR21 = (VAR11 == VAR14 && VAR1);
assign VAR37 = ((VAR11 == VAR23) || ((VAR11 == VAR26 || VAR11 == VAR39) &&
VAR5)) ? VAR40 : VAR31[10:7];
assign VAR18 = VAR31[6:0];
assign VAR45 = (VAR11 == VAR44 && VAR24) ? VAR13 : 4'b0000;
assign VAR12 = (VAR11 == VAR44 && (|VAR13)) ? 1'b1 : 1'b0;
assign VAR32 = ((VAR11 == VAR44 && (|VAR13) && VAR24) || (VAR11 == VAR42 &&
~VAR1)) ? 1'b1 : 1'b0;
assign VAR34 = (VAR11 == VAR42 && ~VAR1) ? 1'b1 : 1'b0;
assign VAR17 = (VAR11 == VAR42 && ~VAR1) ? 1'b1 : 1'b0;
assign VAR33 = (VAR22 || VAR11 == VAR44) ? 1'b1 : 1'b0;
assign VAR41 = (VAR11 == VAR16) ? 1'b1 : 1'b0;
assign VAR35 = (VAR11 == VAR16) ? 1'b1 : 1'b0;
assign VAR4 = ((VAR5 && VAR11 == VAR39 && ~VAR1) ||
(VAR11 == VAR23 && ~VAR43)) ? 1'b1 : 1'b0;
assign VAR19 = (VAR11 == VAR28) ? 1'b1: 1'b0;
always@ ( posedge VAR6 ) begin
VAR11 = VAR3;
end
always@ ( VAR11, VAR9, VAR1, VAR24, VAR43,
VAR20, VAR25, VAR30, VAR5,
VAR40, VAR22) begin
VAR3 = VAR11 ;
case ( VAR11 )
VAR16 : begin
VAR3 = (~VAR25 && ~VAR30) ? VAR44 : VAR16;
end
VAR44 : begin VAR3 = (VAR22) ? VAR16 : (VAR9) ? (VAR5) ? VAR23 : (VAR24) ? VAR11 : (VAR43) ?
VAR26 : VAR14 : VAR11;
end
VAR29 : begin
VAR3 = (VAR22) ? VAR16 : VAR11;
end
VAR14 : begin
VAR3 = (VAR22) ? VAR16 : ( VAR1 ) ? VAR42 : VAR11;
end
VAR42 : begin
VAR3 = (VAR22) ? VAR16 : ( ~VAR1 ) ? VAR44 :
VAR11;
end
VAR26 : begin
VAR3 = (VAR22) ? VAR16 : ( VAR1 ) ? VAR39 : VAR11;
end
VAR39 : begin
VAR3 = (VAR22) ? VAR16 : ( ~VAR1 ) ? (VAR5) ?
VAR23 : VAR14 : VAR11;
end
VAR23 : begin
VAR3 = (VAR22) ? VAR16 : ( VAR40 == 8'b00010000 ) ? VAR28 : ( VAR43 ) ?
VAR26 : VAR11 ;
end
VAR28 : begin
VAR3 = (VAR22) ? VAR16 : ( ~VAR5 ) ? VAR16 : VAR11;
end
default : begin
VAR3 = (VAR22) ? VAR16 : VAR44;
end
endcase
end
endmodule | lgpl-3.0 |
Jawanga/ece385final | finalproject/synthesis/submodules/finalproject_cpu_jtag_debug_module_tck.v | 8,421 | module MODULE1 (
VAR24,
VAR27,
VAR26,
VAR11,
VAR17,
VAR37,
VAR14,
VAR35,
VAR20,
VAR1,
VAR23,
VAR28,
VAR12,
VAR29,
VAR2,
VAR6,
VAR8,
VAR5,
VAR16,
VAR21,
VAR4,
VAR22,
VAR34,
VAR40,
VAR15,
VAR3,
VAR31,
VAR7,
VAR19,
VAR33,
VAR25
)
;
output [ 1: 0] VAR31;
output VAR7;
output [ 37: 0] VAR19;
output VAR33;
output VAR25;
input [ 31: 0] VAR24;
input [ 31: 0] VAR27;
input VAR26;
input VAR11;
input VAR17;
input VAR37;
input VAR14;
input [ 1: 0] VAR35;
input VAR20;
input VAR1;
input VAR23;
input VAR28;
input VAR12;
input VAR29;
input VAR2;
input VAR6;
input [ 35: 0] VAR8;
input VAR5;
input [ 6: 0] VAR16;
input VAR21;
input VAR4;
input VAR22;
input VAR34;
input VAR40;
input VAR15;
input VAR3;
reg [ 2: 0] VAR9 ;
wire VAR39;
reg [ 1: 0] VAR31;
wire VAR7;
wire VAR10;
reg [ 37: 0] VAR19 ;
wire VAR33;
wire VAR25;
wire VAR18;
wire VAR36;
always @(posedge VAR29)
begin
if (VAR40)
case (VAR35)
2'b00: begin
VAR19[35] <= VAR39;
VAR19[34] <= VAR1;
VAR19[33] <= VAR12;
VAR19[32 : 1] <= VAR24;
VAR19[0] <= VAR10;
end
2'b01: begin
VAR19[35 : 0] <= VAR8;
VAR19[37] <= VAR5;
VAR19[36] <= VAR6;
end
2'b10: begin
VAR19[37] <= VAR34;
VAR19[36] <= VAR37;
VAR19[35] <= VAR17;
VAR19[34] <= VAR11;
VAR19[33] <= VAR26;
VAR19[32 : 1] <= VAR27;
VAR19[0] <= VAR22;
end
2'b11: begin
VAR19[15 : 2] <= VAR16;
VAR19[1] <= VAR4;
VAR19[0] <= VAR21;
end
endcase if (VAR15)
case (VAR9)
3'b000: begin
VAR19 <= {VAR2, VAR19[37 : 2], VAR2};
end
3'b001: begin
VAR19 <= {VAR2, VAR19[37 : 9], VAR2, VAR19[7 : 1]};
end
3'b010: begin
VAR19 <= {VAR2, VAR19[37 : 17], VAR2, VAR19[15 : 1]};
end
3'b011: begin
VAR19 <= {VAR2, VAR19[37 : 33], VAR2, VAR19[31 : 1]};
end
3'b100: begin
VAR19 <= {VAR2, VAR19[37], VAR2, VAR19[35 : 1]};
end
3'b101: begin
VAR19 <= {VAR2, VAR19[37 : 1]};
end
default: begin
VAR19 <= {VAR2, VAR19[37 : 2], VAR2};
end
endcase if (VAR3)
case (VAR35)
2'b00: begin
VAR9 <= 3'b100;
end
2'b01: begin
VAR9 <= 3'b101;
end
2'b10: begin
VAR9 <= 3'b101;
end
2'b11: begin
VAR9 <= 3'b010;
end
endcase end
assign VAR25 = VAR19[0];
assign VAR33 = VAR20;
assign VAR18 = VAR7;
VAR32 VAR38
(
.clk (VAR29),
.din (VAR14),
.dout (VAR39),
.VAR28 (VAR18)
);
assign VAR36 = VAR7;
VAR32 VAR30
(
.clk (VAR29),
.din (VAR23),
.dout (VAR10),
.VAR28 (VAR36)
);
always @(posedge VAR29 or negedge VAR7)
begin
if (VAR7 == 0)
VAR31 <= 2'b0;
end
else
VAR31 <= {VAR39, VAR10};
end
assign VAR7 = VAR28;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_controller.v | 4,421 | module MODULE1(
clk ,
VAR10 ,
VAR12 ,
VAR13 ,
VAR9 ,
state
);
input clk ;
input VAR10 ;
input VAR12 ;
output reg VAR13 ;
output reg [8:0] VAR9 ;
output reg [2:0] state ;
parameter VAR17 = 3'b000, VAR8 = 3'b001, VAR1 = 3'b011,VAR3 =3'b010;
parameter VAR4 = 3'b110, VAR5 = 3'b111, VAR16 = 3'b101,VAR14 =3'b100;
reg [2:0] VAR7 ;
reg [8:0] VAR15 ;
reg VAR6 ;
reg VAR11 ;
always@* begin
case(state)
VAR8 :VAR15 = 'd384 ;
VAR1 :VAR15 = 'd132 ;
VAR3 :VAR15 = 'd140 ;
VAR4 :VAR15 = 'd68 ;
VAR5 :VAR15 = 'd76 ;
VAR16 :VAR15 = 'd67 ;
VAR14 :VAR15 = 'd384 ;
default :VAR15 = 'd0 ;
endcase
end
always @(posedge clk or negedge VAR10) begin
if(!(VAR10))
VAR9 <= 8'd0;
end
else if(!state)
VAR9 <= 8'd0;
else if(VAR9 == VAR15)
VAR9 <= 8'd0;
else
VAR9 <= VAR9 + 1'b1;
end
always @* begin
case(state)
VAR17:begin
if(VAR12)
VAR7 = VAR8 ;
end
else
VAR7 = VAR17 ;
end
VAR8:begin
if(VAR9 == VAR15)
VAR7 = VAR1 ;
end
else
VAR7 = VAR8 ;
end
VAR1:begin
if(VAR9 == VAR15)
VAR7 = VAR3 ;
end
else
VAR7 = VAR1 ;
end
VAR3:begin
if(VAR9 == VAR15)
VAR7 = VAR4 ;
end
else
VAR7 = VAR3 ;
end
VAR4:begin
if(VAR9 == VAR15)
VAR7 = VAR5 ;
end
else
VAR7 = VAR4 ;
end
VAR5:begin
if(VAR9 == VAR15)
VAR7 = VAR16 ;
end
else
VAR7 = VAR5 ;
end
VAR16:begin
if(VAR9 == VAR15)
VAR7 = VAR14 ;
end
else
VAR7 = VAR16 ;
end
VAR14:begin
if(VAR9 == VAR15)
VAR7 = VAR17 ;
end
else
VAR7 = VAR14 ;
end
endcase
end
always @(posedge clk or negedge VAR10)begin
if(!VAR10)
state <= VAR17 ;
end
else
state <= VAR7 ;
end
wire VAR2 = (state==VAR14)?1'b1:1'b0;
always@(posedge clk or negedge VAR10)begin
if(!VAR10)
VAR13 <= 1'b0 ;
end
else if(VAR7==VAR17)
VAR13 <= VAR2 ;
else
VAR13 <= 1'b0 ;
end
always @* begin
case(state)
VAR1,
VAR3:VAR6 = 1'b1;
default:VAR6 = 1'b0;
endcase
end
always @* begin
case(state)
VAR1,
VAR4:VAR11 = 1'b1;
default:VAR11 = 1'b0;
endcase
end
endmodule | gpl-3.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_csr.v | 18,676 | module MODULE1
(
input VAR52,
input VAR6,
input [11:0] VAR44,
input VAR71,
input [31:0] VAR85,
input [31:0] VAR60,
output reg [31:0] VAR78,
input VAR106,
input VAR34,
input [31:0] VAR33,
input VAR74,
input [11:0] VAR23,
input [31:0] VAR42,
input [31:0] VAR41,
input VAR49,
input VAR116,
output wire [31:0] VAR28,
output wire [31:0] VAR12,
output wire VAR19,
output wire VAR2,
output VAR88
);
wire [31:0] VAR105;
wire [31:0] VAR90;
wire [31:0] VAR64;
wire [31:0] VAR51;
wire [31:0] VAR31;
wire [31:0] VAR104;
reg [31:0] VAR111;
reg [31:0] VAR45;
wire [31:0] VAR16;
reg [31:0] VAR9;
reg [31:0] VAR38;
reg [31:0] VAR20;
reg [31:0] VAR62;
reg [31:0] VAR59;
wire [31:0] VAR99;
wire [31:0] VAR103;
wire [31:0] VAR25;
wire [31:0] VAR8;
wire [31:0] VAR115;
wire [31:0] VAR91;
wire [31:0] VAR55;
reg [63:0] VAR98;
reg [63:0] VAR54;
wire [63:0] VAR21;
wire [63:0] VAR119;
wire [63:0] VAR92;
wire [63:0] VAR57;
wire [63:0] VAR72;
wire [63:0] VAR68;
wire [63:0] VAR37;
wire [63:0] VAR76;
wire [63:0] VAR27;
wire [63:0] VAR63;
wire [63:0] VAR10;
wire [63:0] VAR47;
wire [63:0] VAR56;
wire [63:0] VAR1;
wire [63:0] VAR96;
wire [63:0] VAR50;
wire [63:0] VAR75;
wire [63:0] VAR13;
wire [63:0] VAR108;
wire [63:0] VAR29;
wire [63:0] VAR18;
wire [63:0] VAR77;
wire [63:0] VAR102;
wire [63:0] VAR46;
wire [63:0] VAR109;
wire [63:0] VAR97;
wire [63:0] VAR120;
wire [63:0] VAR94;
wire [63:0] VAR14;
wire [31:0] VAR53;
wire [31:0] VAR61;
wire [31:0] VAR93;
wire [31:0] VAR7;
wire [31:0] VAR43;
wire [31:0] VAR79;
wire [31:0] VAR35;
wire [31:0] VAR40;
wire [31:0] VAR87;
wire [31:0] VAR95;
wire [31:0] VAR26;
wire [31:0] VAR4;
wire [31:0] VAR3;
wire [31:0] VAR69;
wire [31:0] VAR24;
wire [31:0] VAR66;
wire [31:0] VAR80;
wire [31:0] VAR117;
wire [31:0] VAR100;
wire [31:0] VAR39;
wire [31:0] VAR15;
wire [31:0] VAR121;
wire [31:0] VAR101;
wire [31:0] VAR86;
wire [31:0] VAR110;
wire [31:0] VAR65;
wire [31:0] VAR17;
wire [31:0] VAR30;
wire [31:0] VAR5;
wire [31:0] VAR83;
wire [31:0] VAR22;
wire [31:0] VAR112;
wire [31:0] VAR58;
wire [31:0] VAR113;
wire [31:0] VAR67;
wire [31:0] VAR36;
wire [31:0] VAR73;
wire [31:0] VAR48;
wire [31:0] VAR70;
assign VAR105 = 32'd0;
assign VAR90 = 32'd0;
assign VAR64 = 32'd0;
assign VAR51 = 32'd0;
reg [1:0] VAR81;
reg VAR11;
reg VAR114;
always @(posedge VAR6) begin
if(!VAR52) begin
VAR81 <= 0;
VAR11 <= 0;
VAR114 <= 0;
end else begin
if(VAR71 & (VAR44 == 12'h300)) begin
VAR81[1:0] <= VAR85[12:11]; VAR11 <= VAR85[7]; VAR114 <= VAR85[3]; end
end
end assign VAR31 = {19'd0, VAR81[1:0], 3'd0, VAR11, 3'd0, VAR114, 3'd0};
assign VAR104 = {2'b01, 4'b0000, 26'b00000000000001000000010000};
always @(posedge VAR6) begin
if(!VAR52) begin
VAR45 <= 0;
VAR111 <= 0;
end else begin
if(VAR71 & (VAR44 == 12'h302)) begin
VAR111 <= VAR85;
end
if(VAR71 & (VAR44 == 12'h303)) begin
VAR45 <= VAR85;
end
end
end
reg VAR82, VAR118, VAR89;
always @(posedge VAR6) begin
if(!VAR52) begin
VAR82 <= 0;
VAR118 <= 0;
VAR89 <= 0;
end else begin
if(VAR71 & (VAR44 == 12'h304)) begin
VAR82 <= VAR85[11]; VAR118 <= VAR85[7]; VAR89 <= VAR85[3]; end
end
end assign VAR16 = {20'd0, VAR82, 3'd0, VAR118, 3'd0, VAR89, 3'd0};
always @(posedge VAR6) begin
if(!VAR52) begin
VAR9 <= 0;
end else begin
if(VAR71 & (VAR44 == 12'h305)) begin
VAR9 <= VAR85;
end
end
end
assign VAR28 = VAR9;
always @(posedge VAR6) begin
if(!VAR52) begin
VAR38 <= 0;
end else begin
if(VAR71 & (VAR44 == 12'h340)) begin
VAR38 <= VAR85;
end
end
end
always @(posedge VAR6) begin
if(!VAR52) begin
VAR20 <= 0;
end else begin
if(VAR2) begin
VAR20 <= (VAR41 & {{30{1'b1}},2'b0}) + 32'd4;
end else if(VAR34) begin
VAR20 <= (VAR33 & {{30{1'b1}},2'b0}) + 32'd4;
end else if(VAR74) begin
VAR20 <= (VAR41 & {{30{1'b1}},2'b0});
end else if(VAR71 & (VAR44 == 12'h341)) begin
VAR20 <= (VAR85 & {{30{1'b1}},2'b0});
end
end
end
assign VAR12 = VAR20;
always @(posedge VAR6) begin
if(!VAR52) begin
VAR62 <= 0;
end else begin
if(VAR2) begin
VAR62[31] <= 1'b1;
VAR62[11] <= VAR106;
VAR62[10:8] <= 3'd0;
VAR62[7] <= VAR49;
VAR62[6:4] <= 3'd0;
VAR62[3] <= 1'b0;
VAR62[2:0] <= 3'd0;
end else if(VAR74) begin
VAR62[31] <= 1'b0;
VAR62[11:0] <= VAR23;
end else if(VAR71 & (VAR44 == 12'h342)) begin
VAR62[31] <= VAR85[31];
VAR62[11:0] <= VAR85[11:0];
end
end
end
always @(posedge VAR6) begin
if(!VAR52) begin
VAR59 <= 0;
end else begin
if(VAR74) begin
VAR59 <= (|VAR23[3:0])?VAR41:VAR42;
end else if(VAR71 & (VAR44 == 12'h343)) begin
VAR59 <= VAR85;
end
end
end
reg VAR84, VAR32, VAR107;
always @(posedge VAR6) begin
if(!VAR52) begin
VAR84 <= 0;
VAR32 <= 0;
VAR107 <= 0;
end else begin
if(VAR106) begin
VAR84 <= 1'b1;
end else if(VAR71 & (VAR44 == 12'h344)) begin
VAR84 <= VAR85[11];
end
if(VAR49) begin
VAR32 <= 1'b1;
end else if(VAR71 & (VAR44 == 12'h344)) begin
VAR32 <= VAR85[7];
end
if(VAR34) begin
VAR107 <= 1'b1;
end else if(VAR71 & (VAR44 == 12'h344)) begin
VAR107 <= VAR85[3];
end
end
end assign VAR99 = {20'd0, VAR84, 3'd0, VAR32, 3'd0, VAR107, 3'd0};
assign VAR2 = VAR31[3] & (|(VAR16 & VAR99));
assign VAR19 = |VAR99;
assign VAR103 = 32'd0;
assign VAR25 = 32'd0;
assign VAR8 = 32'd0;
assign VAR115 = 32'd0;
assign VAR91 = 32'd0;
assign VAR55 = 32'd0;
always @(posedge VAR6) begin
if(!VAR52) begin
VAR98 <= 0;
end else begin
if(VAR71 & (VAR44 == 12'hB00)) begin
VAR98[31:0] <= VAR85;
end else if(VAR71 & (VAR44 == 12'hB20)) begin
VAR98[63:32] <= VAR85;
end else begin
VAR98 <= VAR98 + 64'd1;
end
end
end
always @(posedge VAR6) begin
if(!VAR52) begin
VAR54 <= 0;
end else begin
if(VAR71 & (VAR44 == 12'hB02)) begin
VAR54[31:0] <= VAR85;
end else if(VAR71 & (VAR44 == 12'hB20)) begin
VAR54[63:32] <= VAR85;
end else begin
if(VAR116) begin
VAR54 <= VAR54 + 64'd1;
end
end
end
end
assign VAR53 = 32'd0;
assign VAR61 = 32'd0;
assign VAR93 = 32'd0;
assign VAR21 = 64'd0;
assign VAR119 = 64'd0;
assign VAR92 = 64'd0;
assign VAR57 = 64'd0;
assign VAR72 = 64'd0;
assign VAR68 = 64'd0;
assign VAR37 = 64'd0;
assign VAR76 = 64'd0;
assign VAR27 = 64'd0;
assign VAR63 = 64'd0;
assign VAR10 = 64'd0;
assign VAR47 = 64'd0;
assign VAR56 = 64'd0;
assign VAR1 = 64'd0;
assign VAR96 = 64'd0;
assign VAR50 = 64'd0;
assign VAR75 = 64'd0;
assign VAR13 = 64'd0;
assign VAR108 = 64'd0;
assign VAR29 = 64'd0;
assign VAR18 = 64'd0;
assign VAR77 = 64'd0;
assign VAR102 = 64'd0;
assign VAR46 = 64'd0;
assign VAR109 = 64'd0;
assign VAR97 = 64'd0;
assign VAR120 = 64'd0;
assign VAR94 = 64'd0;
assign VAR14 = 64'd0;
assign VAR7 = 32'd0;
assign VAR43 = 32'd0;
assign VAR79 = 32'd0;
assign VAR35 = 32'd0;
assign VAR40 = 32'd0;
assign VAR87 = 32'd0;
assign VAR95 = 32'd0;
assign VAR26 = 32'd0;
assign VAR4 = 32'd0;
assign VAR3 = 32'd0;
assign VAR69 = 32'd0;
assign VAR24 = 32'd0;
assign VAR66 = 32'd0;
assign VAR80 = 32'd0;
assign VAR117 = 32'd0;
assign VAR100 = 32'd0;
assign VAR39 = 32'd0;
assign VAR15 = 32'd0;
assign VAR121 = 32'd0;
assign VAR101 = 32'd0;
assign VAR86 = 32'd0;
assign VAR110 = 32'd0;
assign VAR65 = 32'd0;
assign VAR17 = 32'd0;
assign VAR30 = 32'd0;
assign VAR5 = 32'd0;
assign VAR83 = 32'd0;
assign VAR22 = 32'd0;
assign VAR112 = 32'd0;
assign VAR58 = 32'd0;
assign VAR113 = 32'd0;
assign VAR67 = 32'd0;
assign VAR36 = 32'd0;
assign VAR73 = 32'd0;
assign VAR48 = 32'd0;
assign VAR70 = 32'd0;
always @(*) begin
case(VAR44)
12'hF11: VAR78 <= VAR105;
12'hF12: VAR78 <= VAR90;
12'hF13: VAR78 <= VAR64;
12'hF14: VAR78 <= VAR51;
12'h300: VAR78 <= VAR31;
12'h301: VAR78 <= VAR104;
12'h302: VAR78 <= VAR111;
12'h303: VAR78 <= VAR45;
12'h304: VAR78 <= VAR16;
12'h305: VAR78 <= VAR9;
12'h340: VAR78 <= VAR38;
12'h341: VAR78 <= VAR20;
12'h342: VAR78 <= VAR62;
12'h343: VAR78 <= VAR59;
12'h344: VAR78 <= VAR99;
12'h380: VAR78 <= VAR103;
12'h381: VAR78 <= VAR25;
12'h382: VAR78 <= VAR8;
12'h383: VAR78 <= VAR115;
12'h384: VAR78 <= VAR91;
12'h385: VAR78 <= VAR55;
12'hB00: VAR78 <= VAR98[31:0];
12'hB02: VAR78 <= VAR54[31:0];
12'hB03: VAR78 <= VAR21[31:0];
12'hB04: VAR78 <= VAR119[31:0];
12'hB05: VAR78 <= VAR92[31:0];
12'hB06: VAR78 <= VAR57[31:0];
12'hB07: VAR78 <= VAR72[31:0];
12'hB08: VAR78 <= VAR68[31:0];
12'hB09: VAR78 <= VAR37[31:0];
12'hB0A: VAR78 <= VAR76[31:0];
12'hB0B: VAR78 <= VAR27[31:0];
12'hB0C: VAR78 <= VAR63[31:0];
12'hB0D: VAR78 <= VAR10[31:0];
12'hB0E: VAR78 <= VAR47[31:0];
12'hB0F: VAR78 <= VAR56[31:0];
12'hB10: VAR78 <= VAR1[31:0];
12'hB11: VAR78 <= VAR96[31:0];
12'hB12: VAR78 <= VAR50[31:0];
12'hB13: VAR78 <= VAR75[31:0];
12'hB14: VAR78 <= VAR13[31:0];
12'hB15: VAR78 <= VAR108[31:0];
12'hB16: VAR78 <= VAR29[31:0];
12'hB17: VAR78 <= VAR18[31:0];
12'hB18: VAR78 <= VAR77[31:0];
12'hB19: VAR78 <= VAR102[31:0];
12'hB1A: VAR78 <= VAR46[31:0];
12'hB1B: VAR78 <= VAR109[31:0];
12'hB1C: VAR78 <= VAR97[31:0];
12'hB1D: VAR78 <= VAR120[31:0];
12'hB1E: VAR78 <= VAR94[31:0];
12'hB1F: VAR78 <= VAR14[31:0];
12'hB20: VAR78 <= VAR98[63:32];
12'hB22: VAR78 <= VAR54[63:32];
12'hB23: VAR78 <= VAR21[63:32];
12'hB24: VAR78 <= VAR119[63:32];
12'hB25: VAR78 <= VAR92[63:32];
12'hB26: VAR78 <= VAR57[63:32];
12'hB27: VAR78 <= VAR72[63:32];
12'hB28: VAR78 <= VAR68[63:32];
12'hB29: VAR78 <= VAR37[63:32];
12'hB2A: VAR78 <= VAR76[63:32];
12'hB2B: VAR78 <= VAR27[63:32];
12'hB2C: VAR78 <= VAR63[63:32];
12'hB2D: VAR78 <= VAR10[63:32];
12'hB2E: VAR78 <= VAR47[63:32];
12'hB2F: VAR78 <= VAR56[63:32];
12'hB30: VAR78 <= VAR1[63:32];
12'hB31: VAR78 <= VAR96[63:32];
12'hB32: VAR78 <= VAR50[63:32];
12'hB33: VAR78 <= VAR75[63:32];
12'hB34: VAR78 <= VAR13[63:32];
12'hB35: VAR78 <= VAR108[63:32];
12'hB36: VAR78 <= VAR29[63:32];
12'hB37: VAR78 <= VAR18[63:32];
12'hB38: VAR78 <= VAR77[63:32];
12'hB39: VAR78 <= VAR102[63:32];
12'hB3A: VAR78 <= VAR46[63:32];
12'hB3B: VAR78 <= VAR109[63:32];
12'hB3C: VAR78 <= VAR97[63:32];
12'hB3D: VAR78 <= VAR120[63:32];
12'hB3E: VAR78 <= VAR94[63:32];
12'hB3F: VAR78 <= VAR14[63:32];
12'h320: VAR78 <= VAR53;
12'h321: VAR78 <= VAR61;
12'h322: VAR78 <= VAR93;
12'h323: VAR78 <= VAR7;
12'h324: VAR78 <= VAR43;
12'h325: VAR78 <= VAR79;
12'h326: VAR78 <= VAR35;
12'h327: VAR78 <= VAR40;
12'h328: VAR78 <= VAR87;
12'h329: VAR78 <= VAR95;
12'h32A: VAR78 <= VAR26;
12'h32B: VAR78 <= VAR4;
12'h32C: VAR78 <= VAR3;
12'h32D: VAR78 <= VAR69;
12'h32E: VAR78 <= VAR24;
12'h32F: VAR78 <= VAR66;
12'h330: VAR78 <= VAR80;
12'h331: VAR78 <= VAR117;
12'h332: VAR78 <= VAR100;
12'h333: VAR78 <= VAR39;
12'h334: VAR78 <= VAR15;
12'h335: VAR78 <= VAR121;
12'h336: VAR78 <= VAR101;
12'h337: VAR78 <= VAR86;
12'h338: VAR78 <= VAR110;
12'h339: VAR78 <= VAR65;
12'h33A: VAR78 <= VAR17;
12'h33B: VAR78 <= VAR30;
12'h33C: VAR78 <= VAR5;
12'h33D: VAR78 <= VAR83;
12'h33E: VAR78 <= VAR22;
12'h33F: VAR78 <= VAR112;
12'h7A0: VAR78 <= VAR58;
12'h7A1: VAR78 <= VAR113;
12'h7A2: VAR78 <= VAR67;
12'h7A3: VAR78 <= VAR36;
12'h7B0: VAR78 <= VAR73;
12'h7B1: VAR78 <= VAR48;
12'h7B2: VAR78 <= VAR70;
default: VAR78 <= 32'd0;
endcase
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3.behavioral.v | 1,371 | module MODULE1 (
VAR9,
VAR1,
VAR11,
VAR10
);
output VAR9;
input VAR1;
input VAR11;
input VAR10;
supply1 VAR8;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR6 ;
wire VAR3;
and VAR7 (VAR3, VAR10, VAR1, VAR11 );
buf VAR4 (VAR9 , VAR3 );
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/ciaa_ps2keyboard_map.v | 32,967 | module MODULE1
(
input clk, input VAR21,
input reset, input enable, input [7:0] VAR4, output valid, output [7:0] VAR7, output VAR13, output VAR37, output VAR12, output VAR24, output reg VAR27 = 0, output reg [7:0] VAR29, output reg VAR36, output reg VAR26, output reg [5:0] VAR28, output reg VAR38, output [5:0] VAR39,
output reg [5:0] VAR1
);
localparam VAR3 = 7'h4c;
localparam VAR18 = 7'h4d;
localparam VAR35 = 7'h4f;
localparam VAR16 = 7'h4e;
localparam VAR9 = 7'h0F;
localparam VAR10 = 7'h43;
localparam VAR8 = 7'h5C;
localparam VAR23 = 7'h5D;
reg [15:0] VAR40; reg VAR34; reg VAR17; reg VAR11; wire VAR33;
always @(posedge clk)
if (VAR21) begin
VAR34 <= enable;
end
always @(posedge clk)
if (VAR21) begin
if (reset) begin
VAR17 <= 1'd0;
VAR11 <= 1'd0;
end
else if (VAR34 && VAR40[7] && VAR40[0]) VAR11 <= 1'd1;
end
else if (VAR34 && VAR40[7] && VAR40[1]) VAR17 <= 1'd1;
else if (VAR34 && !(VAR40[7] && VAR40[2])) begin
VAR17 <= 1'd0;
VAR11 <= 1'd0;
end
end
assign VAR33 = VAR27 && ((VAR40[7:0]==VAR35) | (VAR40[7:0]==VAR16) | (VAR40[7:0]==VAR3) | (VAR40[7:0]==VAR18) | VAR40[14] | VAR40[13]);
assign valid = VAR40[15] & (~VAR40[9] | ~VAR27) & VAR34 && !VAR33;
assign VAR13 = VAR40[14] && !VAR27;
assign VAR37 = VAR40[13] && !VAR27;
assign VAR12 = VAR40[12];
assign VAR24 = VAR40[11];
assign VAR7[7:0] = {VAR17, VAR40[6:0]};
always @(posedge clk) begin
if (VAR21) begin
if (reset)
VAR29[7:0] <= 8'd0;
end
else if (VAR34 && (VAR40[8] || VAR40[15]))
VAR29[7:0] <= {VAR17, VAR40[6:0]};
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset)
VAR38 <= 1'b0;
end
else if (VAR34 && VAR40[8] && VAR40[7:0]==8'h6F)
VAR38 <= ~VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (VAR34 && VAR40[10] && ~VAR17)
VAR27 <= ~VAR27;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27 || VAR34 && VAR40[15] && VAR40[7:0]==VAR35 && !VAR17)
VAR28[0] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR16)
VAR28[0] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27 || VAR34 && VAR40[15] && VAR40[7:0]==VAR16 && !VAR17)
VAR28[1] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR35)
VAR28[1] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27 || VAR34 && VAR40[15] && VAR40[7:0]==VAR3 && !VAR17)
VAR28[2] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR18)
VAR28[2] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27 || VAR34 && VAR40[15] && VAR40[7:0]==VAR18 && !VAR17)
VAR28[3] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR3)
VAR28[3] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27)
VAR28[4] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[14] )
VAR28[5] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27)
VAR36 <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR8)
VAR36 <= VAR17;
end
end
always @(posedge clk)
if (VAR21) begin
VAR34 <= enable;
end
always @(posedge clk)
if (VAR21) begin
if (reset) begin
VAR17 <= 1'd0;
VAR11 <= 1'd0;
end
else if (VAR34 && VAR40[7] && VAR40[0]) VAR11 <= 1'd1;
end
else if (VAR34 && VAR40[7] && VAR40[1]) VAR17 <= 1'd1;
else if (VAR34 && !(VAR40[7] && VAR40[2])) begin
VAR17 <= 1'd0;
VAR11 <= 1'd0;
end
end
assign VAR33 = VAR27 && ((VAR40[7:0]==VAR35) | (VAR40[7:0]==VAR16) | (VAR40[7:0]==VAR3) | (VAR40[7:0]==VAR18) | VAR40[14] | VAR40[13]);
assign valid = VAR40[15] & (~VAR40[9] | ~VAR27) & VAR34 && !VAR33;
assign VAR13 = VAR40[14] && !VAR27;
assign VAR37 = VAR40[13] && !VAR27;
assign VAR12 = VAR40[12];
assign VAR24 = VAR40[11];
assign VAR7[7:0] = {VAR17, VAR40[6:0]};
always @(posedge clk) begin
if (VAR21) begin
if (reset)
VAR29[7:0] <= 8'd0;
end
else if (VAR34 && (VAR40[8] || VAR40[15]))
VAR29[7:0] <= {VAR17, VAR40[6:0]};
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset)
VAR38 <= 1'b0;
end
else if (VAR34 && VAR40[8] && VAR40[7:0]==8'h6F)
VAR38 <= ~VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (VAR34 && VAR40[10] && ~VAR17)
VAR27 <= ~VAR27;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27 || VAR34 && VAR40[15] && VAR40[7:0]==VAR35 && !VAR17)
VAR28[0] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR16)
VAR28[0] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27 || VAR34 && VAR40[15] && VAR40[7:0]==VAR16 && !VAR17)
VAR28[1] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR35)
VAR28[1] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27 || VAR34 && VAR40[15] && VAR40[7:0]==VAR3 && !VAR17)
VAR28[2] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR18)
VAR28[2] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27 || VAR34 && VAR40[15] && VAR40[7:0]==VAR18 && !VAR17)
VAR28[3] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR3)
VAR28[3] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27)
VAR28[4] <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[14] )
VAR28[5] <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27)
VAR36 <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR8)
VAR36 <= VAR17;
end
end
always @(posedge clk) begin
if (VAR21) begin
if (reset || !VAR27)
VAR26 <= 1'b1;
end
else if (VAR34 && VAR40[15] && VAR40[7:0]==VAR23)
VAR26 <= VAR17;
end
end
reg VAR19, VAR2, VAR32, VAR30;
assign VAR39[5:0] = {2'b11, VAR19, VAR2, VAR32, VAR30};
localparam VAR5 = 8'h3f;localparam VAR14 = 8'h3e;localparam VAR25 = 8'h3d;localparam VAR20 = 8'h2f;localparam VAR6 = 8'h2d;localparam VAR31 = 8'h1f;localparam VAR22 = 8'h1e;localparam VAR15 = 8'h1d;
always @ (posedge clk) begin
if (VAR21) begin
if (reset || !VAR27) begin
VAR19 <= 1'b0;
VAR2 <= 1'b0;
VAR32 <= 1'b0;
VAR30 <= 1'b0;
end else if (VAR34 && VAR40[15]) begin
VAR19 <= 1'b0;
VAR2 <= 1'b0;
VAR32 <= 1'b0;
VAR30 <= 1'b0;
case (VAR40[7:0])
VAR5,
VAR14,
VAR25: VAR19 <= !VAR17;
VAR31,
VAR22,
VAR15: VAR2 <= !VAR17;
endcase
case (VAR40[7:0])
VAR5,
VAR20,
VAR31: VAR30 <= !VAR17;
VAR25,
VAR6,
VAR15: VAR32 <= !VAR17;
endcase
end
end
end
always @(posedge clk) begin
if (VAR21) begin
if (enable)
begin
case({VAR11,VAR4[7:0]}) 9'h000: VAR40[15:0] <= 16'h0000;
9'h001: VAR40[15:0] <= 16'h8058; 9'h002: VAR40[15:0] <= 16'h0000;
9'h003: VAR40[15:0] <= 16'h8054; 9'h004: VAR40[15:0] <= 16'h8052; 9'h005: VAR40[15:0] <= 16'h8050; 9'h006: VAR40[15:0] <= 16'h8051; 9'h007: VAR40[15:0] <= 16'h0169; 9'h008: VAR40[15:0] <= 16'h0000;
9'h009: VAR40[15:0] <= 16'h8059; 9'h00a: VAR40[15:0] <= 16'h8057; 9'h00b: VAR40[15:0] <= 16'h8055; 9'h00c: VAR40[15:0] <= 16'h8053; 9'h00d: VAR40[15:0] <= 16'h8042; 9'h00e: VAR40[15:0] <= 16'h8000; 9'h00f: VAR40[15:0] <= 16'h0000;
9'h010: VAR40[15:0] <= 16'h0000;
9'h011: VAR40[15:0] <= 16'ha064; 9'h012: VAR40[15:0] <= 16'h8060; 9'h013: VAR40[15:0] <= 16'h0000;
9'h014: VAR40[15:0] <= 16'hc063; 9'h015: VAR40[15:0] <= 16'h8010; 9'h016: VAR40[15:0] <= 16'h8001; 9'h017: VAR40[15:0] <= 16'h0000;
9'h018: VAR40[15:0] <= 16'h0000;
9'h019: VAR40[15:0] <= 16'h0000;
9'h01a: VAR40[15:0] <= 16'h8031; 9'h01b: VAR40[15:0] <= 16'h8021; 9'h01c: VAR40[15:0] <= 16'h8020; 9'h01d: VAR40[15:0] <= 16'h8011; 9'h01e: VAR40[15:0] <= 16'h8002; 9'h01f: VAR40[15:0] <= 16'h0000;
9'h020: VAR40[15:0] <= 16'h0000;
9'h021: VAR40[15:0] <= 16'h8033; 9'h022: VAR40[15:0] <= 16'h8032; 9'h023: VAR40[15:0] <= 16'h8022; 9'h024: VAR40[15:0] <= 16'h8012; 9'h025: VAR40[15:0] <= 16'h8004; 9'h026: VAR40[15:0] <= 16'h8003; 9'h027: VAR40[15:0] <= 16'h0000;
9'h028: VAR40[15:0] <= 16'h0000;
9'h029: VAR40[15:0] <= 16'h8040; 9'h02a: VAR40[15:0] <= 16'h8034; 9'h02b: VAR40[15:0] <= 16'h8023; 9'h02c: VAR40[15:0] <= 16'h8014; 9'h02d: VAR40[15:0] <= 16'h8013; 9'h02e: VAR40[15:0] <= 16'h8005; 9'h02f: VAR40[15:0] <= 16'h0000;
9'h030: VAR40[15:0] <= 16'h0000;
9'h031: VAR40[15:0] <= 16'h8036; 9'h032: VAR40[15:0] <= 16'h8035; 9'h033: VAR40[15:0] <= 16'h8025; 9'h034: VAR40[15:0] <= 16'h8024; 9'h035: VAR40[15:0] <= 16'h8015; 9'h036: VAR40[15:0] <= 16'h8006; 9'h037: VAR40[15:0] <= 16'h0000;
9'h038: VAR40[15:0] <= 16'h0000;
9'h039: VAR40[15:0] <= 16'h0000;
9'h03a: VAR40[15:0] <= 16'h8037; 9'h03b: VAR40[15:0] <= 16'h8026; 9'h03c: VAR40[15:0] <= 16'h8016; 9'h03d: VAR40[15:0] <= 16'h8007; 9'h03e: VAR40[15:0] <= 16'h8008; 9'h03f: VAR40[15:0] <= 16'h0000;
9'h040: VAR40[15:0] <= 16'h0000;
9'h041: VAR40[15:0] <= 16'h8038; 9'h042: VAR40[15:0] <= 16'h8027; 9'h043: VAR40[15:0] <= 16'h8017; 9'h044: VAR40[15:0] <= 16'h8018; 9'h045: VAR40[15:0] <= 16'h800a; 9'h046: VAR40[15:0] <= 16'h8009; 9'h047: VAR40[15:0] <= 16'h0000;
9'h048: VAR40[15:0] <= 16'h0000;
9'h049: VAR40[15:0] <= 16'h8039; 9'h04a: VAR40[15:0] <= 16'h803a; 9'h04b: VAR40[15:0] <= 16'h8028; 9'h04c: VAR40[15:0] <= 16'h8029; 9'h04d: VAR40[15:0] <= 16'h8019; 9'h04e: VAR40[15:0] <= 16'h800b; 9'h04f: VAR40[15:0] <= 16'h0000;
9'h050: VAR40[15:0] <= 16'h0000;
9'h051: VAR40[15:0] <= 16'h0000;
9'h052: VAR40[15:0] <= 16'h802a; 9'h053: VAR40[15:0] <= 16'h0000;
9'h054: VAR40[15:0] <= 16'h801a; 9'h055: VAR40[15:0] <= 16'h800c; 9'h056: VAR40[15:0] <= 16'h0000;
9'h057: VAR40[15:0] <= 16'h0000;
9'h058: VAR40[15:0] <= 16'h8862; 9'h059: VAR40[15:0] <= 16'h8061; 9'h05a: VAR40[15:0] <= 16'h8044; 9'h05b: VAR40[15:0] <= 16'h801b; 9'h05c: VAR40[15:0] <= 16'h0000;
9'h05d: VAR40[15:0] <= 16'h802B; 9'h05e: VAR40[15:0] <= 16'h0000;
9'h05f: VAR40[15:0] <= 16'h0000;
9'h060: VAR40[15:0] <= 16'h0000;
9'h061: VAR40[15:0] <= 16'h8030; 9'h062: VAR40[15:0] <= 16'h0000;
9'h063: VAR40[15:0] <= 16'h0000;
9'h064: VAR40[15:0] <= 16'h0000;
9'h065: VAR40[15:0] <= 16'h0000;
9'h066: VAR40[15:0] <= 16'h8041; 9'h067: VAR40[15:0] <= 16'h0000;
9'h068: VAR40[15:0] <= 16'h0000;
9'h069: VAR40[15:0] <= 16'h821d; 9'h06a: VAR40[15:0] <= 16'h0000;
9'h06b: VAR40[15:0] <= 16'h822d; 9'h06c: VAR40[15:0] <= 16'h823d; 9'h06d: VAR40[15:0] <= 16'h0000;
9'h06e: VAR40[15:0] <= 16'h0000;
9'h06f: VAR40[15:0] <= 16'h0000;
9'h070: VAR40[15:0] <= 16'h820f; 9'h071: VAR40[15:0] <= 16'h823c; 9'h072: VAR40[15:0] <= 16'h821e; 9'h073: VAR40[15:0] <= 16'h822e; 9'h074: VAR40[15:0] <= 16'h822f; 9'h075: VAR40[15:0] <= 16'h823e; 9'h076: VAR40[15:0] <= 16'h8045; 9'h077: VAR40[15:0] <= 16'h0400; 9'h078: VAR40[15:0] <= 16'h0000; 9'h079: VAR40[15:0] <= 16'h825e; 9'h07a: VAR40[15:0] <= 16'h821f; 9'h07b: VAR40[15:0] <= 16'h824a; 9'h07c: VAR40[15:0] <= 16'h825d; 9'h07d: VAR40[15:0] <= 16'h823f; 9'h07e: VAR40[15:0] <= 16'h0169; 9'h07f: VAR40[15:0] <= 16'h0000;
9'h080: VAR40[15:0] <= 16'h0000;
9'h081: VAR40[15:0] <= 16'h0000;
9'h082: VAR40[15:0] <= 16'h0000;
9'h083: VAR40[15:0] <= 16'h8056; 9'h084: VAR40[15:0] <= 16'h0000;
9'h085: VAR40[15:0] <= 16'h0000;
9'h086: VAR40[15:0] <= 16'h0000;
9'h087: VAR40[15:0] <= 16'h0000;
9'h088: VAR40[15:0] <= 16'h0000;
9'h089: VAR40[15:0] <= 16'h0000;
9'h08a: VAR40[15:0] <= 16'h0000;
9'h08b: VAR40[15:0] <= 16'h0000;
9'h08c: VAR40[15:0] <= 16'h0000;
9'h08d: VAR40[15:0] <= 16'h0000;
9'h08e: VAR40[15:0] <= 16'h0000;
9'h08f: VAR40[15:0] <= 16'h0000;
9'h090: VAR40[15:0] <= 16'h0000;
9'h091: VAR40[15:0] <= 16'h0000;
9'h092: VAR40[15:0] <= 16'h0000;
9'h093: VAR40[15:0] <= 16'h0000;
9'h094: VAR40[15:0] <= 16'h0000;
9'h095: VAR40[15:0] <= 16'h0000;
9'h096: VAR40[15:0] <= 16'h0000;
9'h097: VAR40[15:0] <= 16'h0000;
9'h098: VAR40[15:0] <= 16'h0000;
9'h099: VAR40[15:0] <= 16'h0000;
9'h09a: VAR40[15:0] <= 16'h0000;
9'h09b: VAR40[15:0] <= 16'h0000;
9'h09c: VAR40[15:0] <= 16'h0000;
9'h09d: VAR40[15:0] <= 16'h0000;
9'h09e: VAR40[15:0] <= 16'h0000;
9'h09f: VAR40[15:0] <= 16'h0000;
9'h0a0: VAR40[15:0] <= 16'h0000;
9'h0a1: VAR40[15:0] <= 16'h0000;
9'h0a2: VAR40[15:0] <= 16'h0000;
9'h0a3: VAR40[15:0] <= 16'h0000;
9'h0a4: VAR40[15:0] <= 16'h0000;
9'h0a5: VAR40[15:0] <= 16'h0000;
9'h0a6: VAR40[15:0] <= 16'h0000;
9'h0a7: VAR40[15:0] <= 16'h0000;
9'h0a8: VAR40[15:0] <= 16'h0000;
9'h0a9: VAR40[15:0] <= 16'h0000;
9'h0aa: VAR40[15:0] <= 16'h0000;
9'h0ab: VAR40[15:0] <= 16'h0000;
9'h0ac: VAR40[15:0] <= 16'h0000;
9'h0ad: VAR40[15:0] <= 16'h0000;
9'h0ae: VAR40[15:0] <= 16'h0000;
9'h0af: VAR40[15:0] <= 16'h0000;
9'h0b0: VAR40[15:0] <= 16'h0000;
9'h0b1: VAR40[15:0] <= 16'h0000;
9'h0b2: VAR40[15:0] <= 16'h0000;
9'h0b3: VAR40[15:0] <= 16'h0000;
9'h0b4: VAR40[15:0] <= 16'h0000;
9'h0b5: VAR40[15:0] <= 16'h0000;
9'h0b6: VAR40[15:0] <= 16'h0000;
9'h0b7: VAR40[15:0] <= 16'h0000;
9'h0b8: VAR40[15:0] <= 16'h0000;
9'h0b9: VAR40[15:0] <= 16'h0000;
9'h0ba: VAR40[15:0] <= 16'h0000;
9'h0bb: VAR40[15:0] <= 16'h0000;
9'h0bc: VAR40[15:0] <= 16'h0000;
9'h0bd: VAR40[15:0] <= 16'h0000;
9'h0be: VAR40[15:0] <= 16'h0000;
9'h0bf: VAR40[15:0] <= 16'h0000;
9'h0c0: VAR40[15:0] <= 16'h0000;
9'h0c1: VAR40[15:0] <= 16'h0000;
9'h0c2: VAR40[15:0] <= 16'h0000;
9'h0c3: VAR40[15:0] <= 16'h0000;
9'h0c4: VAR40[15:0] <= 16'h0000;
9'h0c5: VAR40[15:0] <= 16'h0000;
9'h0c6: VAR40[15:0] <= 16'h0000;
9'h0c7: VAR40[15:0] <= 16'h0000;
9'h0c8: VAR40[15:0] <= 16'h0000;
9'h0c9: VAR40[15:0] <= 16'h0000;
9'h0ca: VAR40[15:0] <= 16'h0000;
9'h0cb: VAR40[15:0] <= 16'h0000;
9'h0cc: VAR40[15:0] <= 16'h0000;
9'h0cd: VAR40[15:0] <= 16'h0000;
9'h0ce: VAR40[15:0] <= 16'h0000;
9'h0cf: VAR40[15:0] <= 16'h0000;
9'h0d0: VAR40[15:0] <= 16'h0000;
9'h0d1: VAR40[15:0] <= 16'h0000;
9'h0d2: VAR40[15:0] <= 16'h0000;
9'h0d3: VAR40[15:0] <= 16'h0000;
9'h0d4: VAR40[15:0] <= 16'h0000;
9'h0d5: VAR40[15:0] <= 16'h0000;
9'h0d6: VAR40[15:0] <= 16'h0000;
9'h0d7: VAR40[15:0] <= 16'h0000;
9'h0d8: VAR40[15:0] <= 16'h0000;
9'h0d9: VAR40[15:0] <= 16'h0000;
9'h0da: VAR40[15:0] <= 16'h0000;
9'h0db: VAR40[15:0] <= 16'h0000;
9'h0dc: VAR40[15:0] <= 16'h0000;
9'h0dd: VAR40[15:0] <= 16'h0000;
9'h0de: VAR40[15:0] <= 16'h0000;
9'h0df: VAR40[15:0] <= 16'h0000;
9'h0e0: VAR40[15:0] <= 16'h0081; 9'h0e1: VAR40[15:0] <= 16'h0000;
9'h0e2: VAR40[15:0] <= 16'h0000;
9'h0e3: VAR40[15:0] <= 16'h0000;
9'h0e4: VAR40[15:0] <= 16'h0000;
9'h0e5: VAR40[15:0] <= 16'h0000;
9'h0e6: VAR40[15:0] <= 16'h0000;
9'h0e7: VAR40[15:0] <= 16'h0000;
9'h0e8: VAR40[15:0] <= 16'h0000;
9'h0e9: VAR40[15:0] <= 16'h0000;
9'h0ea: VAR40[15:0] <= 16'h0000;
9'h0eb: VAR40[15:0] <= 16'h0000;
9'h0ec: VAR40[15:0] <= 16'h0000;
9'h0ed: VAR40[15:0] <= 16'h0000;
9'h0ee: VAR40[15:0] <= 16'h0000;
9'h0ef: VAR40[15:0] <= 16'h0000;
9'h0f0: VAR40[15:0] <= 16'h0082; 9'h0f1: VAR40[15:0] <= 16'h0000;
9'h0f2: VAR40[15:0] <= 16'h0000;
9'h0f3: VAR40[15:0] <= 16'h0000;
9'h0f4: VAR40[15:0] <= 16'h0000;
9'h0f5: VAR40[15:0] <= 16'h0000;
9'h0f6: VAR40[15:0] <= 16'h0000;
9'h0f7: VAR40[15:0] <= 16'h0000;
9'h0f8: VAR40[15:0] <= 16'h0000;
9'h0f9: VAR40[15:0] <= 16'h0000;
9'h0fa: VAR40[15:0] <= 16'h0084; 9'h0fb: VAR40[15:0] <= 16'h0000;
9'h0fc: VAR40[15:0] <= 16'h0000;
9'h0fd: VAR40[15:0] <= 16'h0000;
9'h0fe: VAR40[15:0] <= 16'h0000;
9'h0ff: VAR40[15:0] <= 16'h0000;
9'h100: VAR40[15:0] <= 16'h0000;
9'h101: VAR40[15:0] <= 16'h0000;
9'h102: VAR40[15:0] <= 16'h0000;
9'h103: VAR40[15:0] <= 16'h0000;
9'h104: VAR40[15:0] <= 16'h0000;
9'h105: VAR40[15:0] <= 16'h0000;
9'h106: VAR40[15:0] <= 16'h0000;
9'h107: VAR40[15:0] <= 16'h0000;
9'h108: VAR40[15:0] <= 16'h0000;
9'h109: VAR40[15:0] <= 16'h0000;
9'h10a: VAR40[15:0] <= 16'h0000;
9'h10b: VAR40[15:0] <= 16'h0000;
9'h10c: VAR40[15:0] <= 16'h0000;
9'h10d: VAR40[15:0] <= 16'h0000;
9'h10e: VAR40[15:0] <= 16'h0000;
9'h10f: VAR40[15:0] <= 16'h0000;
9'h110: VAR40[15:0] <= 16'h0000;
9'h111: VAR40[15:0] <= 16'h9065; 9'h112: VAR40[15:0] <= 16'h0000;
9'h113: VAR40[15:0] <= 16'h0000;
9'h114: VAR40[15:0] <= 16'h0000;
9'h115: VAR40[15:0] <= 16'h0000;
9'h116: VAR40[15:0] <= 16'h0000;
9'h117: VAR40[15:0] <= 16'h0000;
9'h118: VAR40[15:0] <= 16'h0000;
9'h119: VAR40[15:0] <= 16'h0000;
9'h11a: VAR40[15:0] <= 16'h0000;
9'h11b: VAR40[15:0] <= 16'h0000;
9'h11c: VAR40[15:0] <= 16'h0000;
9'h11d: VAR40[15:0] <= 16'h0000;
9'h11e: VAR40[15:0] <= 16'h0000;
9'h11f: VAR40[15:0] <= 16'h8066; 9'h120: VAR40[15:0] <= 16'h0000;
9'h121: VAR40[15:0] <= 16'h0000;
9'h122: VAR40[15:0] <= 16'h0000;
9'h123: VAR40[15:0] <= 16'h0000;
9'h124: VAR40[15:0] <= 16'h0000;
9'h125: VAR40[15:0] <= 16'h0000;
9'h126: VAR40[15:0] <= 16'h0000;
9'h127: VAR40[15:0] <= 16'h8067; 9'h128: VAR40[15:0] <= 16'h0000;
9'h129: VAR40[15:0] <= 16'h0000;
9'h12a: VAR40[15:0] <= 16'h0000;
9'h12b: VAR40[15:0] <= 16'h0000;
9'h12c: VAR40[15:0] <= 16'h0000;
9'h12d: VAR40[15:0] <= 16'h0000;
9'h12e: VAR40[15:0] <= 16'h0000;
9'h12f: VAR40[15:0] <= 16'h8067; 9'h130: VAR40[15:0] <= 16'h0000;
9'h131: VAR40[15:0] <= 16'h0000;
9'h132: VAR40[15:0] <= 16'h0000;
9'h133: VAR40[15:0] <= 16'h0000;
9'h134: VAR40[15:0] <= 16'h0000;
9'h135: VAR40[15:0] <= 16'h0000;
9'h136: VAR40[15:0] <= 16'h0000;
9'h137: VAR40[15:0] <= 16'h0000;
9'h138: VAR40[15:0] <= 16'h0000;
9'h139: VAR40[15:0] <= 16'h0000;
9'h13a: VAR40[15:0] <= 16'h0000;
9'h13b: VAR40[15:0] <= 16'h0000;
9'h13c: VAR40[15:0] <= 16'h0000;
9'h13d: VAR40[15:0] <= 16'h0000;
9'h13e: VAR40[15:0] <= 16'h0000;
9'h13f: VAR40[15:0] <= 16'h0000;
9'h140: VAR40[15:0] <= 16'h0000;
9'h141: VAR40[15:0] <= 16'h0000;
9'h142: VAR40[15:0] <= 16'h0000;
9'h143: VAR40[15:0] <= 16'h0000;
9'h144: VAR40[15:0] <= 16'h0000;
9'h145: VAR40[15:0] <= 16'h0000;
9'h146: VAR40[15:0] <= 16'h0000;
9'h147: VAR40[15:0] <= 16'h0000;
9'h148: VAR40[15:0] <= 16'h0000;
9'h149: VAR40[15:0] <= 16'h0000;
9'h14a: VAR40[15:0] <= 16'h825c; 9'h14b: VAR40[15:0] <= 16'h0000;
9'h14c: VAR40[15:0] <= 16'h0000;
9'h14d: VAR40[15:0] <= 16'h0000;
9'h14e: VAR40[15:0] <= 16'h0000;
9'h14f: VAR40[15:0] <= 16'h0000;
9'h150: VAR40[15:0] <= 16'h0000;
9'h151: VAR40[15:0] <= 16'h0000;
9'h152: VAR40[15:0] <= 16'h0000;
9'h153: VAR40[15:0] <= 16'h0000;
9'h154: VAR40[15:0] <= 16'h0000;
9'h155: VAR40[15:0] <= 16'h0000;
9'h156: VAR40[15:0] <= 16'h0000;
9'h157: VAR40[15:0] <= 16'h0000;
9'h158: VAR40[15:0] <= 16'h0000;
9'h159: VAR40[15:0] <= 16'h0000;
9'h15a: VAR40[15:0] <= 16'h8243; 9'h15b: VAR40[15:0] <= 16'h0000;
9'h15c: VAR40[15:0] <= 16'h0000;
9'h15d: VAR40[15:0] <= 16'h0000;
9'h15e: VAR40[15:0] <= 16'h0000;
9'h15f: VAR40[15:0] <= 16'h0000;
9'h160: VAR40[15:0] <= 16'h0000;
9'h161: VAR40[15:0] <= 16'h0000;
9'h162: VAR40[15:0] <= 16'h0000;
9'h163: VAR40[15:0] <= 16'h0000;
9'h164: VAR40[15:0] <= 16'h0000;
9'h165: VAR40[15:0] <= 16'h0000;
9'h166: VAR40[15:0] <= 16'h0000;
9'h167: VAR40[15:0] <= 16'h0000;
9'h168: VAR40[15:0] <= 16'h0000;
9'h169: VAR40[15:0] <= 16'h016B; 9'h16a: VAR40[15:0] <= 16'h0000;
9'h16b: VAR40[15:0] <= 16'h804f; 9'h16c: VAR40[15:0] <= 16'h016A; 9'h16d: VAR40[15:0] <= 16'h0000;
9'h16e: VAR40[15:0] <= 16'h0000;
9'h16f: VAR40[15:0] <= 16'h0000;
9'h170: VAR40[15:0] <= 16'h805f; 9'h171: VAR40[15:0] <= 16'h8046; 9'h172: VAR40[15:0] <= 16'h804d; 9'h173: VAR40[15:0] <= 16'h0000;
9'h174: VAR40[15:0] <= 16'h804e; 9'h175: VAR40[15:0] <= 16'h804c; 9'h176: VAR40[15:0] <= 16'h0000;
9'h177: VAR40[15:0] <= 16'h0000;
9'h178: VAR40[15:0] <= 16'h0000;
9'h179: VAR40[15:0] <= 16'h0000;
9'h17a: VAR40[15:0] <= 16'h016D; 9'h17b: VAR40[15:0] <= 16'h0000;
9'h17c: VAR40[15:0] <= 16'h016E; 9'h17d: VAR40[15:0] <= 16'h016C; 9'h17e: VAR40[15:0] <= 16'h016F; 9'h17f: VAR40[15:0] <= 16'h0000;
9'h180: VAR40[15:0] <= 16'h0000;
9'h181: VAR40[15:0] <= 16'h0000;
9'h182: VAR40[15:0] <= 16'h0000;
9'h183: VAR40[15:0] <= 16'h0000;
9'h184: VAR40[15:0] <= 16'h0000;
9'h185: VAR40[15:0] <= 16'h0000;
9'h186: VAR40[15:0] <= 16'h0000;
9'h187: VAR40[15:0] <= 16'h0000;
9'h188: VAR40[15:0] <= 16'h0000;
9'h189: VAR40[15:0] <= 16'h0000;
9'h18a: VAR40[15:0] <= 16'h0000;
9'h18b: VAR40[15:0] <= 16'h0000;
9'h18c: VAR40[15:0] <= 16'h0000;
9'h18d: VAR40[15:0] <= 16'h0000;
9'h18e: VAR40[15:0] <= 16'h0000;
9'h18f: VAR40[15:0] <= 16'h0000;
9'h190: VAR40[15:0] <= 16'h0000;
9'h191: VAR40[15:0] <= 16'h0000;
9'h192: VAR40[15:0] <= 16'h0000;
9'h193: VAR40[15:0] <= 16'h0000;
9'h194: VAR40[15:0] <= 16'h0000;
9'h195: VAR40[15:0] <= 16'h0000;
9'h196: VAR40[15:0] <= 16'h0000;
9'h197: VAR40[15:0] <= 16'h0000;
9'h198: VAR40[15:0] <= 16'h0000;
9'h199: VAR40[15:0] <= 16'h0000;
9'h19a: VAR40[15:0] <= 16'h0000;
9'h19b: VAR40[15:0] <= 16'h0000;
9'h19c: VAR40[15:0] <= 16'h0000;
9'h19d: VAR40[15:0] <= 16'h0000;
9'h19e: VAR40[15:0] <= 16'h0000;
9'h19f: VAR40[15:0] <= 16'h0000;
9'h1a0: VAR40[15:0] <= 16'h0000;
9'h1a1: VAR40[15:0] <= 16'h0000;
9'h1a2: VAR40[15:0] <= 16'h0000;
9'h1a3: VAR40[15:0] <= 16'h0000;
9'h1a4: VAR40[15:0] <= 16'h0000;
9'h1a5: VAR40[15:0] <= 16'h0000;
9'h1a6: VAR40[15:0] <= 16'h0000;
9'h1a7: VAR40[15:0] <= 16'h0000;
9'h1a8: VAR40[15:0] <= 16'h0000;
9'h1a9: VAR40[15:0] <= 16'h0000;
9'h1aa: VAR40[15:0] <= 16'h0000;
9'h1ab: VAR40[15:0] <= 16'h0000;
9'h1ac: VAR40[15:0] <= 16'h0000;
9'h1ad: VAR40[15:0] <= 16'h0000;
9'h1ae: VAR40[15:0] <= 16'h0000;
9'h1af: VAR40[15:0] <= 16'h0000;
9'h1b0: VAR40[15:0] <= 16'h0000;
9'h1b1: VAR40[15:0] <= 16'h0000;
9'h1b2: VAR40[15:0] <= 16'h0000;
9'h1b3: VAR40[15:0] <= 16'h0000;
9'h1b4: VAR40[15:0] <= 16'h0000;
9'h1b5: VAR40[15:0] <= 16'h0000;
9'h1b6: VAR40[15:0] <= 16'h0000;
9'h1b7: VAR40[15:0] <= 16'h0000;
9'h1b8: VAR40[15:0] <= 16'h0000;
9'h1b9: VAR40[15:0] <= 16'h0000;
9'h1ba: VAR40[15:0] <= 16'h0000;
9'h1bb: VAR40[15:0] <= 16'h0000;
9'h1bc: VAR40[15:0] <= 16'h0000;
9'h1bd: VAR40[15:0] <= 16'h0000;
9'h1be: VAR40[15:0] <= 16'h0000;
9'h1bf: VAR40[15:0] <= 16'h0000;
9'h1c0: VAR40[15:0] <= 16'h0000;
9'h1c1: VAR40[15:0] <= 16'h0000;
9'h1c2: VAR40[15:0] <= 16'h0000;
9'h1c3: VAR40[15:0] <= 16'h0000;
9'h1c4: VAR40[15:0] <= 16'h0000;
9'h1c5: VAR40[15:0] <= 16'h0000;
9'h1c6: VAR40[15:0] <= 16'h0000;
9'h1c7: VAR40[15:0] <= 16'h0000;
9'h1c8: VAR40[15:0] <= 16'h0000;
9'h1c9: VAR40[15:0] <= 16'h0000;
9'h1ca: VAR40[15:0] <= 16'h0000;
9'h1cb: VAR40[15:0] <= 16'h0000;
9'h1cc: VAR40[15:0] <= 16'h0000;
9'h1cd: VAR40[15:0] <= 16'h0000;
9'h1ce: VAR40[15:0] <= 16'h0000;
9'h1cf: VAR40[15:0] <= 16'h0000;
9'h1d0: VAR40[15:0] <= 16'h0000;
9'h1d1: VAR40[15:0] <= 16'h0000;
9'h1d2: VAR40[15:0] <= 16'h0000;
9'h1d3: VAR40[15:0] <= 16'h0000;
9'h1d4: VAR40[15:0] <= 16'h0000;
9'h1d5: VAR40[15:0] <= 16'h0000;
9'h1d6: VAR40[15:0] <= 16'h0000;
9'h1d7: VAR40[15:0] <= 16'h0000;
9'h1d8: VAR40[15:0] <= 16'h0000;
9'h1d9: VAR40[15:0] <= 16'h0000;
9'h1da: VAR40[15:0] <= 16'h0000;
9'h1db: VAR40[15:0] <= 16'h0000;
9'h1dc: VAR40[15:0] <= 16'h0000;
9'h1dd: VAR40[15:0] <= 16'h0000;
9'h1de: VAR40[15:0] <= 16'h0000;
9'h1df: VAR40[15:0] <= 16'h0000;
9'h1e0: VAR40[15:0] <= 16'h0081; 9'h1e1: VAR40[15:0] <= 16'h0000;
9'h1e2: VAR40[15:0] <= 16'h0000;
9'h1e3: VAR40[15:0] <= 16'h0000;
9'h1e4: VAR40[15:0] <= 16'h0000;
9'h1e5: VAR40[15:0] <= 16'h0000;
9'h1e6: VAR40[15:0] <= 16'h0000;
9'h1e7: VAR40[15:0] <= 16'h0000;
9'h1e8: VAR40[15:0] <= 16'h0000;
9'h1e9: VAR40[15:0] <= 16'h0000;
9'h1ea: VAR40[15:0] <= 16'h0000;
9'h1eb: VAR40[15:0] <= 16'h0000;
9'h1ec: VAR40[15:0] <= 16'h0000;
9'h1ed: VAR40[15:0] <= 16'h0000;
9'h1ee: VAR40[15:0] <= 16'h0000;
9'h1ef: VAR40[15:0] <= 16'h0000;
9'h1f0: VAR40[15:0] <= 16'h0082; 9'h1f1: VAR40[15:0] <= 16'h0000;
9'h1f2: VAR40[15:0] <= 16'h0000;
9'h1f3: VAR40[15:0] <= 16'h0000;
9'h1f4: VAR40[15:0] <= 16'h0000;
9'h1f5: VAR40[15:0] <= 16'h0000;
9'h1f6: VAR40[15:0] <= 16'h0000;
9'h1f7: VAR40[15:0] <= 16'h0000;
9'h1f8: VAR40[15:0] <= 16'h0000;
9'h1f9: VAR40[15:0] <= 16'h0000;
9'h1fa: VAR40[15:0] <= 16'h0084; 9'h1fb: VAR40[15:0] <= 16'h0000;
9'h1fc: VAR40[15:0] <= 16'h0000;
9'h1fd: VAR40[15:0] <= 16'h0000;
9'h1fe: VAR40[15:0] <= 16'h0000;
9'h1ff: VAR40[15:0] <= 16'h0000;
endcase
end
end
end
endmodule | gpl-3.0 |
asicguy/gplgpu | hdl/hbi/hbi_lut_u.v | 21,645 | module MODULE1
(
input VAR4,
input [7:0] VAR5,
output reg [9:0] VAR3,
output reg [9:0] VAR2
);
reg [7:0] VAR1;
always @(posedge VAR4) begin
case(VAR5)
8'd0: VAR3 <= 10'h244;
8'd1: VAR3 <= 10'h248;
8'd2: VAR3 <= 10'h24B;
8'd3: VAR3 <= 10'h24F;
8'd4: VAR3 <= 10'h252;
8'd5: VAR3 <= 10'h256;
8'd6: VAR3 <= 10'h259;
8'd7: VAR3 <= 10'h25D;
8'd8: VAR3 <= 10'h260;
8'd9: VAR3 <= 10'h264;
8'd10: VAR3 <= 10'h267;
8'd11: VAR3 <= 10'h26A;
8'd12: VAR3 <= 10'h26E;
8'd13: VAR3 <= 10'h271;
8'd14: VAR3 <= 10'h275;
8'd15: VAR3 <= 10'h278;
8'd16: VAR3 <= 10'h27C;
8'd17: VAR3 <= 10'h27F;
8'd18: VAR3 <= 10'h283;
8'd19: VAR3 <= 10'h286;
8'd20: VAR3 <= 10'h28A;
8'd21: VAR3 <= 10'h28D;
8'd22: VAR3 <= 10'h291;
8'd23: VAR3 <= 10'h294;
8'd24: VAR3 <= 10'h298;
8'd25: VAR3 <= 10'h29B;
8'd26: VAR3 <= 10'h29E;
8'd27: VAR3 <= 10'h2A2;
8'd28: VAR3 <= 10'h2A5;
8'd29: VAR3 <= 10'h2A9;
8'd30: VAR3 <= 10'h2AC;
8'd31: VAR3 <= 10'h2B0;
8'd32: VAR3 <= 10'h2B3;
8'd33: VAR3 <= 10'h2B7;
8'd34: VAR3 <= 10'h2BA;
8'd35: VAR3 <= 10'h2BE;
8'd36: VAR3 <= 10'h2C1;
8'd37: VAR3 <= 10'h2C5;
8'd38: VAR3 <= 10'h2C8;
8'd39: VAR3 <= 10'h2CC;
8'd40: VAR3 <= 10'h2CF;
8'd41: VAR3 <= 10'h2D2;
8'd42: VAR3 <= 10'h2D6;
8'd43: VAR3 <= 10'h2D9;
8'd44: VAR3 <= 10'h2DD;
8'd45: VAR3 <= 10'h2E0;
8'd46: VAR3 <= 10'h2E4;
8'd47: VAR3 <= 10'h2E7;
8'd48: VAR3 <= 10'h2EB;
8'd49: VAR3 <= 10'h2EE;
8'd50: VAR3 <= 10'h2F2;
8'd51: VAR3 <= 10'h2F5;
8'd52: VAR3 <= 10'h2F9;
8'd53: VAR3 <= 10'h2FC;
8'd54: VAR3 <= 10'h300;
8'd55: VAR3 <= 10'h303;
8'd56: VAR3 <= 10'h306;
8'd57: VAR3 <= 10'h30A;
8'd58: VAR3 <= 10'h30D;
8'd59: VAR3 <= 10'h311;
8'd60: VAR3 <= 10'h314;
8'd61: VAR3 <= 10'h318;
8'd62: VAR3 <= 10'h31B;
8'd63: VAR3 <= 10'h31F;
8'd64: VAR3 <= 10'h322;
8'd65: VAR3 <= 10'h326;
8'd66: VAR3 <= 10'h329;
8'd67: VAR3 <= 10'h32D;
8'd68: VAR3 <= 10'h330;
8'd69: VAR3 <= 10'h334;
8'd70: VAR3 <= 10'h337;
8'd71: VAR3 <= 10'h33A;
8'd72: VAR3 <= 10'h33E;
8'd73: VAR3 <= 10'h341;
8'd74: VAR3 <= 10'h345;
8'd75: VAR3 <= 10'h348;
8'd76: VAR3 <= 10'h34C;
8'd77: VAR3 <= 10'h34F;
8'd78: VAR3 <= 10'h353;
8'd79: VAR3 <= 10'h356;
8'd80: VAR3 <= 10'h35A;
8'd81: VAR3 <= 10'h35D;
8'd82: VAR3 <= 10'h361;
8'd83: VAR3 <= 10'h364;
8'd84: VAR3 <= 10'h367;
8'd85: VAR3 <= 10'h36B;
8'd86: VAR3 <= 10'h36E;
8'd87: VAR3 <= 10'h372;
8'd88: VAR3 <= 10'h375;
8'd89: VAR3 <= 10'h379;
8'd90: VAR3 <= 10'h37C;
8'd91: VAR3 <= 10'h380;
8'd92: VAR3 <= 10'h383;
8'd93: VAR3 <= 10'h387;
8'd94: VAR3 <= 10'h38A;
8'd95: VAR3 <= 10'h38E;
8'd96: VAR3 <= 10'h391;
8'd97: VAR3 <= 10'h395;
8'd98: VAR3 <= 10'h398;
8'd99: VAR3 <= 10'h39B;
8'd100: VAR3 <= 10'h39F;
8'd101: VAR3 <= 10'h3A2;
8'd102: VAR3 <= 10'h3A6;
8'd103: VAR3 <= 10'h3A9;
8'd104: VAR3 <= 10'h3AD;
8'd105: VAR3 <= 10'h3B0;
8'd106: VAR3 <= 10'h3B4;
8'd107: VAR3 <= 10'h3B7;
8'd108: VAR3 <= 10'h3BB;
8'd109: VAR3 <= 10'h3BE;
8'd110: VAR3 <= 10'h3C2;
8'd111: VAR3 <= 10'h3C5;
8'd112: VAR3 <= 10'h3C9;
8'd113: VAR3 <= 10'h3CC;
8'd114: VAR3 <= 10'h3CF;
8'd115: VAR3 <= 10'h3D3;
8'd116: VAR3 <= 10'h3D6;
8'd117: VAR3 <= 10'h3DA;
8'd118: VAR3 <= 10'h3DD;
8'd119: VAR3 <= 10'h3E1;
8'd120: VAR3 <= 10'h3E4;
8'd121: VAR3 <= 10'h3E8;
8'd122: VAR3 <= 10'h3EB;
8'd123: VAR3 <= 10'h3EF;
8'd124: VAR3 <= 10'h3F2;
8'd125: VAR3 <= 10'h3F6;
8'd126: VAR3 <= 10'h3F9;
8'd127: VAR3 <= 10'h3FD;
8'd128: VAR3 <= 10'h000;
8'd129: VAR3 <= 10'h003;
8'd130: VAR3 <= 10'h007;
8'd131: VAR3 <= 10'h00A;
8'd132: VAR3 <= 10'h00E;
8'd133: VAR3 <= 10'h011;
8'd134: VAR3 <= 10'h015;
8'd135: VAR3 <= 10'h018;
8'd136: VAR3 <= 10'h01C;
8'd137: VAR3 <= 10'h01F;
8'd138: VAR3 <= 10'h023;
8'd139: VAR3 <= 10'h026;
8'd140: VAR3 <= 10'h02A;
8'd141: VAR3 <= 10'h02D;
8'd142: VAR3 <= 10'h031;
8'd143: VAR3 <= 10'h034;
8'd144: VAR3 <= 10'h037;
8'd145: VAR3 <= 10'h03B;
8'd146: VAR3 <= 10'h03E;
8'd147: VAR3 <= 10'h042;
8'd148: VAR3 <= 10'h045;
8'd149: VAR3 <= 10'h049;
8'd150: VAR3 <= 10'h04C;
8'd151: VAR3 <= 10'h050;
8'd152: VAR3 <= 10'h053;
8'd153: VAR3 <= 10'h057;
8'd154: VAR3 <= 10'h05A;
8'd155: VAR3 <= 10'h05E;
8'd156: VAR3 <= 10'h061;
8'd157: VAR3 <= 10'h065;
8'd158: VAR3 <= 10'h068;
8'd159: VAR3 <= 10'h06B;
8'd160: VAR3 <= 10'h06F;
8'd161: VAR3 <= 10'h072;
8'd162: VAR3 <= 10'h076;
8'd163: VAR3 <= 10'h079;
8'd164: VAR3 <= 10'h07D;
8'd165: VAR3 <= 10'h080;
8'd166: VAR3 <= 10'h084;
8'd167: VAR3 <= 10'h087;
8'd168: VAR3 <= 10'h08B;
8'd169: VAR3 <= 10'h08E;
8'd170: VAR3 <= 10'h092;
8'd171: VAR3 <= 10'h095;
8'd172: VAR3 <= 10'h099;
8'd173: VAR3 <= 10'h09C;
8'd174: VAR3 <= 10'h09F;
8'd175: VAR3 <= 10'h0A3;
8'd176: VAR3 <= 10'h0A6;
8'd177: VAR3 <= 10'h0AA;
8'd178: VAR3 <= 10'h0AD;
8'd179: VAR3 <= 10'h0B1;
8'd180: VAR3 <= 10'h0B4;
8'd181: VAR3 <= 10'h0B8;
8'd182: VAR3 <= 10'h0BB;
8'd183: VAR3 <= 10'h0BF;
8'd184: VAR3 <= 10'h0C2;
8'd185: VAR3 <= 10'h0C6;
8'd186: VAR3 <= 10'h0C9;
8'd187: VAR3 <= 10'h0CC;
8'd188: VAR3 <= 10'h0D0;
8'd189: VAR3 <= 10'h0D3;
8'd190: VAR3 <= 10'h0D7;
8'd191: VAR3 <= 10'h0DA;
8'd192: VAR3 <= 10'h0DE;
8'd193: VAR3 <= 10'h0E1;
8'd194: VAR3 <= 10'h0E5;
8'd195: VAR3 <= 10'h0E8;
8'd196: VAR3 <= 10'h0EC;
8'd197: VAR3 <= 10'h0EF;
8'd198: VAR3 <= 10'h0F3;
8'd199: VAR3 <= 10'h0F6;
8'd200: VAR3 <= 10'h0FA;
8'd201: VAR3 <= 10'h0FD;
8'd202: VAR3 <= 10'h100;
8'd203: VAR3 <= 10'h104;
8'd204: VAR3 <= 10'h107;
8'd205: VAR3 <= 10'h10B;
8'd206: VAR3 <= 10'h10E;
8'd207: VAR3 <= 10'h112;
8'd208: VAR3 <= 10'h115;
8'd209: VAR3 <= 10'h119;
8'd210: VAR3 <= 10'h11C;
8'd211: VAR3 <= 10'h120;
8'd212: VAR3 <= 10'h123;
8'd213: VAR3 <= 10'h127;
8'd214: VAR3 <= 10'h12A;
8'd215: VAR3 <= 10'h12E;
8'd216: VAR3 <= 10'h131;
8'd217: VAR3 <= 10'h134;
8'd218: VAR3 <= 10'h138;
8'd219: VAR3 <= 10'h13B;
8'd220: VAR3 <= 10'h13F;
8'd221: VAR3 <= 10'h142;
8'd222: VAR3 <= 10'h146;
8'd223: VAR3 <= 10'h149;
8'd224: VAR3 <= 10'h14D;
8'd225: VAR3 <= 10'h150;
8'd226: VAR3 <= 10'h154;
8'd227: VAR3 <= 10'h157;
8'd228: VAR3 <= 10'h15B;
8'd229: VAR3 <= 10'h15E;
8'd230: VAR3 <= 10'h162;
8'd231: VAR3 <= 10'h165;
8'd232: VAR3 <= 10'h168;
8'd233: VAR3 <= 10'h16C;
8'd234: VAR3 <= 10'h16F;
8'd235: VAR3 <= 10'h173;
8'd236: VAR3 <= 10'h176;
8'd237: VAR3 <= 10'h17A;
8'd238: VAR3 <= 10'h17D;
8'd239: VAR3 <= 10'h181;
8'd240: VAR3 <= 10'h184;
8'd241: VAR3 <= 10'h188;
8'd242: VAR3 <= 10'h18B;
8'd243: VAR3 <= 10'h18F;
8'd244: VAR3 <= 10'h192;
8'd245: VAR3 <= 10'h196;
8'd246: VAR3 <= 10'h199;
8'd247: VAR3 <= 10'h19C;
8'd248: VAR3 <= 10'h1A0;
8'd249: VAR3 <= 10'h1A3;
8'd250: VAR3 <= 10'h1A7;
8'd251: VAR3 <= 10'h1AA;
8'd252: VAR3 <= 10'h1AE;
8'd253: VAR3 <= 10'h1B1;
8'd254: VAR3 <= 10'h1B5;
8'd255: VAR3 <= 10'h1B8;
endcase
case(VAR5)
8'd0: VAR2 <= 10'h353;
8'd1: VAR2 <= 10'h355;
8'd2: VAR2 <= 10'h356;
8'd3: VAR2 <= 10'h357;
8'd4: VAR2 <= 10'h359;
8'd5: VAR2 <= 10'h35A;
8'd6: VAR2 <= 10'h35C;
8'd7: VAR2 <= 10'h35D;
8'd8: VAR2 <= 10'h35E;
8'd9: VAR2 <= 10'h360;
8'd10: VAR2 <= 10'h361;
8'd11: VAR2 <= 10'h362;
8'd12: VAR2 <= 10'h364;
8'd13: VAR2 <= 10'h365;
8'd14: VAR2 <= 10'h366;
8'd15: VAR2 <= 10'h368;
8'd16: VAR2 <= 10'h369;
8'd17: VAR2 <= 10'h36A;
8'd18: VAR2 <= 10'h36C;
8'd19: VAR2 <= 10'h36D;
8'd20: VAR2 <= 10'h36E;
8'd21: VAR2 <= 10'h370;
8'd22: VAR2 <= 10'h371;
8'd23: VAR2 <= 10'h372;
8'd24: VAR2 <= 10'h374;
8'd25: VAR2 <= 10'h375;
8'd26: VAR2 <= 10'h377;
8'd27: VAR2 <= 10'h378;
8'd28: VAR2 <= 10'h379;
8'd29: VAR2 <= 10'h37B;
8'd30: VAR2 <= 10'h37C;
8'd31: VAR2 <= 10'h37D;
8'd32: VAR2 <= 10'h37F;
8'd33: VAR2 <= 10'h380;
8'd34: VAR2 <= 10'h381;
8'd35: VAR2 <= 10'h383;
8'd36: VAR2 <= 10'h384;
8'd37: VAR2 <= 10'h385;
8'd38: VAR2 <= 10'h387;
8'd39: VAR2 <= 10'h388;
8'd40: VAR2 <= 10'h389;
8'd41: VAR2 <= 10'h38B;
8'd42: VAR2 <= 10'h38C;
8'd43: VAR2 <= 10'h38D;
8'd44: VAR2 <= 10'h38F;
8'd45: VAR2 <= 10'h390;
8'd46: VAR2 <= 10'h391;
8'd47: VAR2 <= 10'h393;
8'd48: VAR2 <= 10'h394;
8'd49: VAR2 <= 10'h396;
8'd50: VAR2 <= 10'h397;
8'd51: VAR2 <= 10'h398;
8'd52: VAR2 <= 10'h39A;
8'd53: VAR2 <= 10'h39B;
8'd54: VAR2 <= 10'h39C;
8'd55: VAR2 <= 10'h39E;
8'd56: VAR2 <= 10'h39F;
8'd57: VAR2 <= 10'h3A0;
8'd58: VAR2 <= 10'h3A2;
8'd59: VAR2 <= 10'h3A3;
8'd60: VAR2 <= 10'h3A4;
8'd61: VAR2 <= 10'h3A6;
8'd62: VAR2 <= 10'h3A7;
8'd63: VAR2 <= 10'h3A8;
8'd64: VAR2 <= 10'h3AA;
8'd65: VAR2 <= 10'h3AB;
8'd66: VAR2 <= 10'h3AC;
8'd67: VAR2 <= 10'h3AE;
8'd68: VAR2 <= 10'h3AF;
8'd69: VAR2 <= 10'h3B0;
8'd70: VAR2 <= 10'h3B2;
8'd71: VAR2 <= 10'h3B3;
8'd72: VAR2 <= 10'h3B5;
8'd73: VAR2 <= 10'h3B6;
8'd74: VAR2 <= 10'h3B7;
8'd75: VAR2 <= 10'h3B9;
8'd76: VAR2 <= 10'h3BA;
8'd77: VAR2 <= 10'h3BB;
8'd78: VAR2 <= 10'h3BD;
8'd79: VAR2 <= 10'h3BE;
8'd80: VAR2 <= 10'h3BF;
8'd81: VAR2 <= 10'h3C1;
8'd82: VAR2 <= 10'h3C2;
8'd83: VAR2 <= 10'h3C3;
8'd84: VAR2 <= 10'h3C5;
8'd85: VAR2 <= 10'h3C6;
8'd86: VAR2 <= 10'h3C7;
8'd87: VAR2 <= 10'h3C9;
8'd88: VAR2 <= 10'h3CA;
8'd89: VAR2 <= 10'h3CB;
8'd90: VAR2 <= 10'h3CD;
8'd91: VAR2 <= 10'h3CE;
8'd92: VAR2 <= 10'h3CF;
8'd93: VAR2 <= 10'h3D1;
8'd94: VAR2 <= 10'h3D2;
8'd95: VAR2 <= 10'h3D4;
8'd96: VAR2 <= 10'h3D5;
8'd97: VAR2 <= 10'h3D6;
8'd98: VAR2 <= 10'h3D8;
8'd99: VAR2 <= 10'h3D9;
8'd100: VAR2 <= 10'h3DA;
8'd101: VAR2 <= 10'h3DC;
8'd102: VAR2 <= 10'h3DD;
8'd103: VAR2 <= 10'h3DE;
8'd104: VAR2 <= 10'h3E0;
8'd105: VAR2 <= 10'h3E1;
8'd106: VAR2 <= 10'h3E2;
8'd107: VAR2 <= 10'h3E4;
8'd108: VAR2 <= 10'h3E5;
8'd109: VAR2 <= 10'h3E6;
8'd110: VAR2 <= 10'h3E8;
8'd111: VAR2 <= 10'h3E9;
8'd112: VAR2 <= 10'h3EA;
8'd113: VAR2 <= 10'h3EC;
8'd114: VAR2 <= 10'h3ED;
8'd115: VAR2 <= 10'h3EE;
8'd116: VAR2 <= 10'h3F0;
8'd117: VAR2 <= 10'h3F1;
8'd118: VAR2 <= 10'h3F3;
8'd119: VAR2 <= 10'h3F4;
8'd120: VAR2 <= 10'h3F5;
8'd121: VAR2 <= 10'h3F7;
8'd122: VAR2 <= 10'h3F8;
8'd123: VAR2 <= 10'h3F9;
8'd124: VAR2 <= 10'h3FB;
8'd125: VAR2 <= 10'h3FC;
8'd126: VAR2 <= 10'h3FD;
8'd127: VAR2 <= 10'h3FF;
8'd128: VAR2 <= 10'h000;
8'd129: VAR2 <= 10'h001;
8'd130: VAR2 <= 10'h003;
8'd131: VAR2 <= 10'h004;
8'd132: VAR2 <= 10'h005;
8'd133: VAR2 <= 10'h007;
8'd134: VAR2 <= 10'h008;
8'd135: VAR2 <= 10'h009;
8'd136: VAR2 <= 10'h00B;
8'd137: VAR2 <= 10'h00C;
8'd138: VAR2 <= 10'h00D;
8'd139: VAR2 <= 10'h00F;
8'd140: VAR2 <= 10'h010;
8'd141: VAR2 <= 10'h012;
8'd142: VAR2 <= 10'h013;
8'd143: VAR2 <= 10'h014;
8'd144: VAR2 <= 10'h016;
8'd145: VAR2 <= 10'h017;
8'd146: VAR2 <= 10'h018;
8'd147: VAR2 <= 10'h01A;
8'd148: VAR2 <= 10'h01B;
8'd149: VAR2 <= 10'h01C;
8'd150: VAR2 <= 10'h01E;
8'd151: VAR2 <= 10'h01F;
8'd152: VAR2 <= 10'h020;
8'd153: VAR2 <= 10'h022;
8'd154: VAR2 <= 10'h023;
8'd155: VAR2 <= 10'h024;
8'd156: VAR2 <= 10'h026;
8'd157: VAR2 <= 10'h027;
8'd158: VAR2 <= 10'h028;
8'd159: VAR2 <= 10'h02A;
8'd160: VAR2 <= 10'h02B;
8'd161: VAR2 <= 10'h02C;
8'd162: VAR2 <= 10'h02E;
8'd163: VAR2 <= 10'h02F;
8'd164: VAR2 <= 10'h031;
8'd165: VAR2 <= 10'h032;
8'd166: VAR2 <= 10'h033;
8'd167: VAR2 <= 10'h035;
8'd168: VAR2 <= 10'h036;
8'd169: VAR2 <= 10'h037;
8'd170: VAR2 <= 10'h039;
8'd171: VAR2 <= 10'h03A;
8'd172: VAR2 <= 10'h03B;
8'd173: VAR2 <= 10'h03D;
8'd174: VAR2 <= 10'h03E;
8'd175: VAR2 <= 10'h03F;
8'd176: VAR2 <= 10'h041;
8'd177: VAR2 <= 10'h042;
8'd178: VAR2 <= 10'h043;
8'd179: VAR2 <= 10'h045;
8'd180: VAR2 <= 10'h046;
8'd181: VAR2 <= 10'h047;
8'd182: VAR2 <= 10'h049;
8'd183: VAR2 <= 10'h04A;
8'd184: VAR2 <= 10'h04B;
8'd185: VAR2 <= 10'h04D;
8'd186: VAR2 <= 10'h04E;
8'd187: VAR2 <= 10'h050;
8'd188: VAR2 <= 10'h051;
8'd189: VAR2 <= 10'h052;
8'd190: VAR2 <= 10'h054;
8'd191: VAR2 <= 10'h055;
8'd192: VAR2 <= 10'h056;
8'd193: VAR2 <= 10'h058;
8'd194: VAR2 <= 10'h059;
8'd195: VAR2 <= 10'h05A;
8'd196: VAR2 <= 10'h05C;
8'd197: VAR2 <= 10'h05D;
8'd198: VAR2 <= 10'h05E;
8'd199: VAR2 <= 10'h060;
8'd200: VAR2 <= 10'h061;
8'd201: VAR2 <= 10'h062;
8'd202: VAR2 <= 10'h064;
8'd203: VAR2 <= 10'h065;
8'd204: VAR2 <= 10'h066;
8'd205: VAR2 <= 10'h068;
8'd206: VAR2 <= 10'h069;
8'd207: VAR2 <= 10'h06A;
8'd208: VAR2 <= 10'h06C;
8'd209: VAR2 <= 10'h06D;
8'd210: VAR2 <= 10'h06F;
8'd211: VAR2 <= 10'h070;
8'd212: VAR2 <= 10'h071;
8'd213: VAR2 <= 10'h073;
8'd214: VAR2 <= 10'h074;
8'd215: VAR2 <= 10'h075;
8'd216: VAR2 <= 10'h077;
8'd217: VAR2 <= 10'h078;
8'd218: VAR2 <= 10'h079;
8'd219: VAR2 <= 10'h07B;
8'd220: VAR2 <= 10'h07C;
8'd221: VAR2 <= 10'h07D;
8'd222: VAR2 <= 10'h07F;
8'd223: VAR2 <= 10'h080;
8'd224: VAR2 <= 10'h081;
8'd225: VAR2 <= 10'h083;
8'd226: VAR2 <= 10'h084;
8'd227: VAR2 <= 10'h085;
8'd228: VAR2 <= 10'h087;
8'd229: VAR2 <= 10'h088;
8'd230: VAR2 <= 10'h089;
8'd231: VAR2 <= 10'h08B;
8'd232: VAR2 <= 10'h08C;
8'd233: VAR2 <= 10'h08E;
8'd234: VAR2 <= 10'h08F;
8'd235: VAR2 <= 10'h090;
8'd236: VAR2 <= 10'h092;
8'd237: VAR2 <= 10'h093;
8'd238: VAR2 <= 10'h094;
8'd239: VAR2 <= 10'h096;
8'd240: VAR2 <= 10'h097;
8'd241: VAR2 <= 10'h098;
8'd242: VAR2 <= 10'h09A;
8'd243: VAR2 <= 10'h09B;
8'd244: VAR2 <= 10'h09C;
8'd245: VAR2 <= 10'h09E;
8'd246: VAR2 <= 10'h09F;
8'd247: VAR2 <= 10'h0A0;
8'd248: VAR2 <= 10'h0A2;
8'd249: VAR2 <= 10'h0A3;
8'd250: VAR2 <= 10'h0A4;
8'd251: VAR2 <= 10'h0A6;
8'd252: VAR2 <= 10'h0A7;
8'd253: VAR2 <= 10'h0A9;
8'd254: VAR2 <= 10'h0AA;
8'd255: VAR2 <= 10'h0AB;
endcase
end
endmodule | gpl-3.0 |
cpulabs/mist1032isa | src/core/execute/execute_jump.v | 6,502 | module MODULE1(
input wire VAR42,
input wire VAR2,
input wire VAR21,
input wire VAR15,
input wire VAR24,
input wire VAR25,
input wire VAR12,
input wire VAR40,
input wire VAR6,
input wire VAR16,
input wire VAR19,
input wire VAR39,
input wire [31:0] VAR8,
input wire VAR28,
input wire VAR44,
input wire VAR3,
input wire VAR30, input wire VAR7, input wire VAR23,
input wire [31:0] VAR14,
input wire VAR4,
input wire VAR20,
input wire VAR36,
input wire [31:0] VAR9,
input wire VAR1,
output wire VAR18,
output wire VAR27,
output wire VAR5,
output wire [31:0] VAR17,
output wire VAR13,
output wire VAR22,
output wire VAR43,
output wire VAR34,
output wire VAR26,
output wire VAR32
);
wire VAR33 = VAR30 || VAR7;
reg VAR45;
reg VAR41;
reg VAR35;
always@(posedge VAR42 or negedge VAR2)begin
if(!VAR2)begin
VAR45 <= 1'b0;
VAR41 <= 1'b0;
VAR35 <= 1'b0;
end
else if(VAR21 || VAR15 || VAR40)begin
VAR45 <= 1'b0;
VAR41 <= 1'b0;
VAR35 <= 1'b0;
end
else begin
if(VAR6)begin
if(!VAR1)begin
if(VAR16 && VAR19)begin VAR45 <= VAR28;
VAR41 <= VAR44;
VAR35 <= VAR33;
end
else begin
VAR45 <= 1'b0;
VAR41 <= 1'b0;
VAR35 <= 1'b0;
end
end
end
else begin
VAR45 <= 1'b0;
VAR41 <= 1'b0;
VAR35 <= 1'b0;
end
end
end
reg [31:0] VAR29;
always@(posedge VAR42 or negedge VAR2)begin
if(!VAR2)begin
VAR29 <= 32'h0;
end
else if(VAR21 || VAR15 || VAR40)begin
VAR29 <= 32'h0;
end
else begin
if(VAR6)begin
if(!VAR1)begin
if(VAR16)begin
if(VAR19)begin
if(VAR7 || VAR23)begin
VAR29 <= VAR14;
end
else if(VAR30)begin
VAR29 <= VAR8;
end
end
else if(VAR39) begin
VAR29 <= VAR9;
end
end
else begin
VAR29 <= 32'h0;
end
end
end
else begin
VAR29 <= 32'h0;
end
end
end
reg VAR46;
reg VAR31;
always@(posedge VAR42 or negedge VAR2)begin
if(!VAR2)begin
VAR46 <= 1'b0;
VAR31 <= 1'b0;
end
else if(VAR21 || VAR15 || VAR40)begin
VAR46 <= 1'b0;
VAR31 <= 1'b0;
end
else begin
if(VAR6)begin
if(!VAR1)begin
if(VAR16 && VAR19)begin VAR46 <= VAR30 || VAR7;
VAR31 <= VAR23;
end
else begin
VAR46 <= 1'b0;
VAR31 <= 1'b0;
end
end
end
else begin
VAR46 <= 1'b0;
VAR31 <= 1'b0;
end
end
end
reg VAR11;
always@(posedge VAR42 or negedge VAR2)begin
if(!VAR2)begin
VAR11 <= 1'b0;
end
else if(VAR21 || VAR15 || VAR40)begin
VAR11 <= 1'b0;
end
else begin
if(VAR6)begin
if(!VAR1)begin
if(VAR16 && VAR19)begin VAR11 <= VAR3;
end
else begin
VAR11 <= 1'b0;
end
end
end
else begin
VAR11 <= 1'b0;
end
end
end
reg VAR37;
reg VAR38;
reg VAR10;
always@(posedge VAR42 or negedge VAR2)begin
if(!VAR2)begin
VAR37 <= 1'b0;
VAR38 <= 1'b0;
VAR10 <= 1'b0;
end
else if(VAR21 || VAR15 || VAR40)begin
VAR37 <= 1'b0;
VAR38 <= 1'b0;
VAR10 <= 1'b0;
end
else begin
if(VAR6)begin
if(!VAR1)begin
if(VAR16 && VAR39)begin VAR37 <= VAR4;
VAR38 <= VAR20;
VAR10 <= VAR36;
end
else begin
VAR37 <= 1'b0;
VAR38 <= 1'b0;
VAR10 <= 1'b0;
end
end
end
else begin
VAR37 <= 1'b0;
VAR38 <= 1'b0;
VAR10 <= 1'b0;
end
end
end
assign VAR18 = VAR45;
assign VAR27 = VAR41;
assign VAR5 = VAR35;
assign VAR17 = VAR29;
assign VAR13 = VAR11;
assign VAR22 = VAR46;
assign VAR43 = VAR31;
assign VAR34 = VAR37;
assign VAR26 = VAR38;
assign VAR32 = VAR10;
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ba/sky130_fd_sc_lp__o21ba_1.v | 2,316 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR4 ,
VAR9,
VAR1,
VAR5,
VAR8 ,
VAR10
);
output VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR9;
input VAR1;
input VAR5;
input VAR8 ;
input VAR10 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODULE1 (
VAR2 ,
VAR6 ,
VAR4 ,
VAR9
);
output VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR9;
supply1 VAR1;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR10 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule | apache-2.0 |
jameshegarty/rigel | platform/camera/vsrc/MMIO_slave.v | 8,994 | module MODULE1(
input VAR15,
input VAR111,
output VAR12,
input [31:0] VAR110,
input [11:0] VAR78,
output VAR81,
input VAR93,
input [31:0] VAR97,
input [11:0] VAR96,
output VAR34,
input VAR10,
output [11:0] VAR48,
input VAR65,
output [1:0] VAR49,
output VAR86,
output [31:0] VAR56,
output [11:0] VAR88,
output VAR3,
input VAR36,
output [1:0] VAR31,
output VAR101,
input [31:0] VAR14,
output VAR44,
input [3:0] VAR21,
input VAR50,
output [31:0] VAR102,
output [31:0] VAR7,
output [31:0] VAR5,
output [31:0] VAR106,
output [31:0] VAR94,
output [31:0] VAR28,
output [31:0] VAR46,
output [31:0] VAR89,
output [31:0] VAR105,
input [31:0] VAR99,
input [31:0] VAR39,
input [31:0] VAR68,
input [31:0] VAR72,
output reg VAR13,
input [17:0] VAR66,
input VAR54,
output reg VAR60,
input [17:0] VAR6,
input VAR67,
output VAR73
);
assign VAR12 = VAR15;
wire [31:0] VAR22;
wire VAR114;
wire VAR4;
wire [31:0] VAR109;
wire VAR51;
wire VAR107;
wire VAR33;
reg [1:0] VAR42;
wire VAR71;
reg [31:0] VAR62;
wire VAR90;
reg [1:0] VAR53;
wire VAR98;
wire [31:0] VAR113;
wire VAR58;
wire [3:0] VAR37;
wire VAR8;
wire VAR29;
assign VAR29 = 1;
VAR47 VAR16(
.VAR76(VAR12),
.VAR19(VAR111),
.VAR110(VAR110),
.VAR78(VAR78),
.VAR81(VAR81),
.VAR93(VAR93),
.VAR97(VAR97),
.VAR96(VAR96),
.VAR34(VAR34),
.VAR10(VAR10),
.VAR48(VAR48),
.VAR65(VAR65),
.VAR49(VAR49),
.VAR86(VAR86),
.VAR56(VAR56),
.VAR88(VAR88),
.VAR3(VAR3),
.VAR36(VAR36),
.VAR31(VAR31),
.VAR101(VAR101),
.VAR14(VAR14),
.VAR44(VAR44),
.VAR21(VAR21),
.VAR50(VAR50),
.VAR40(VAR22),
.VAR43(VAR114),
.VAR61(VAR4),
.VAR20(VAR109),
.VAR59(VAR51),
.VAR9(VAR107),
.VAR112(VAR33),
.VAR32(VAR42),
.VAR108(VAR71),
.VAR55(VAR62),
.VAR52(VAR90),
.VAR75(VAR53),
.VAR35(VAR98),
.VAR80(VAR113),
.VAR77(VAR58),
.VAR64(VAR37),
.VAR11(VAR8)
);
parameter VAR83 = VAR83;
parameter [31:0] VAR69 = 32'h70000000;
parameter VAR100 = 32;
localparam VAR84 = VAR95(VAR83);
reg [VAR100-1:0] VAR85[VAR83-1:0];
parameter VAR30 = 0, VAR2 = 1;
parameter VAR63 = 2'b00, VAR38 = 2'b10;
reg VAR104;
wire [VAR84-1:0] VAR79;
assign VAR79 = VAR22[VAR84+1:2];
assign VAR87 = {VAR22[31:(2+VAR84)], {VAR84{1'b0}}, VAR22[1:0]} == VAR69;
assign VAR114 = (VAR104 == VAR30);
assign VAR98 = (VAR104 == VAR2);
wire VAR24;
assign VAR24 = (VAR91==VAR2) && VAR58 && (VAR17==VAR23(0));
VAR74(VAR15, VAR13, 0, VAR24)
reg [31:0] VAR82;
reg [31:0] VAR26;
always @(posedge VAR15 or negedge VAR111) begin
if (!VAR111) begin
VAR82 <= 32'h0;
VAR26[12:0] <= 0;
end
else if (VAR54) begin
VAR82 <= {14'h0,VAR66[17:0]};
VAR26 <= VAR26 + 1'b1;
end
end
wire VAR18;
assign VAR18 = (VAR91==VAR2) && VAR58 && (VAR17==VAR23(1));
VAR74(VAR15, VAR60, 0, VAR18)
reg [31:0] VAR27;
reg [31:0] VAR25;
always @(posedge VAR15 or negedge VAR111) begin
if (!VAR111) begin
VAR27 <= 32'h0;
VAR25[12:0] <= 0;
end
else if (VAR67) begin
VAR27 <= {14'h0,VAR6[17:0]};
VAR25 <= VAR25 + 1'b1;
end
end
reg [31:0] VAR103;
always @(*) begin
case(VAR79)
default : VAR103 = VAR85[VAR79];
endcase
end
assign VAR102 = VAR85[VAR102 ];
assign VAR7 = VAR85[VAR23(0) ];
assign VAR5 = VAR85[VAR23(1) ];
assign VAR106 = VAR85[VAR41(0) ];
assign VAR94 = VAR85[VAR57(0) ];
assign VAR28 = VAR85[VAR41(1) ];
assign VAR46 = VAR85[VAR57(1) ];
assign VAR89 = VAR85[VAR41(2) ];
assign VAR105 = VAR85[VAR57(2) ];
always @(posedge VAR15) begin
if(VAR111 == 0) begin
VAR104 <= VAR30;
end else case(VAR104)
VAR30: begin
if(VAR4) begin
VAR53 <= VAR87 ? VAR63 : VAR38;
VAR62 <= VAR103;
VAR104 <= VAR2;
end
end
VAR2: begin
if(VAR90)
VAR104 <= VAR30;
end
endcase
end
reg VAR91;
reg [VAR84-1:0] VAR17;
reg VAR45;
reg VAR70;
wire [VAR84-1:0] VAR1;
assign VAR1 = VAR109[VAR84+1:2];
assign VAR92 = {VAR22[31:(2+VAR84)], {VAR84{1'b0}}, VAR109[1:0]} == VAR69;
assign VAR51 = (VAR91 == VAR30);
assign VAR58 = (VAR91 == VAR2) && !VAR45;
assign VAR71 = (VAR91 == VAR2) && !VAR70;
always @(posedge VAR15) begin
if(VAR111 == 0) begin
VAR91 <= VAR30;
VAR45 <= 0;
VAR70 <= 0;
end else case(VAR91)
VAR30: begin
if(VAR107) begin
VAR42 <= VAR92 ? VAR63 : VAR38;
VAR17 <= VAR1;
VAR91 <= VAR2;
VAR45 <= 0;
VAR70 <= 0;
end
end
VAR2: begin
VAR85[0] <= 0;
if (VAR58) begin
VAR85[VAR17] <= VAR113;
end
if((VAR45 || VAR8) && (VAR70 || VAR33)) begin
VAR45 <= 0;
VAR70 <= 0;
VAR91 <= VAR30;
end
else if (VAR8) begin
VAR45 <= 1;
end
else if (VAR33) begin
VAR70 <= 1;
end
end
endcase
end
reg VAR115;
always @(posedge VAR15) begin
if (VAR111 == 0)
VAR115 <= VAR30;
end
else case(VAR115)
VAR30:
if (VAR8 && VAR58 && VAR17 == 2'b00)
VAR115 <= VAR2;
VAR2:
if (VAR29)
VAR115 <= VAR30;
endcase
end
assign VAR73 = 0;
endmodule | mit |
prernaa/CPUVerilog | mem_wb.v | 2,140 | module MODULE1(clk, VAR8, VAR4,
VAR20, VAR12, VAR10, VAR2,
VAR5, VAR25, VAR11, VAR1, VAR17, VAR26,
VAR9, VAR21,
VAR16, VAR7,
VAR27, VAR22
);
input clk;
input VAR8;
input VAR4;
input VAR20;
input [3:0] VAR12;
input [15:0] VAR10;
input [15:0] VAR2;
input [15:0] VAR16;
input VAR27;
input VAR9;
output VAR21;
output VAR5;
output VAR25;
output VAR26;
output [3:0] VAR11;
output [15:0] VAR1;
output [15:0] VAR17;
output [15:0] VAR7;
output VAR22;
reg VAR14;
reg VAR13;
reg [3:0] VAR3;
reg [15:0] VAR23;
reg [15:0] VAR18;
reg VAR15;
reg VAR19;
reg [15:0] VAR24;
reg VAR6;
always @ (posedge clk)
begin
VAR14 <= VAR4;
VAR13 <= VAR20;
VAR3 <= VAR12;
VAR23 <= VAR10;
VAR15 <= VAR8;
VAR18 <= VAR2;
VAR19 <= VAR9;
VAR24 <= VAR16;
VAR6 <= VAR27;
end
assign VAR5 = VAR14;
assign VAR25 = VAR13;
assign VAR11 = VAR3;
assign VAR1 = VAR23;
assign VAR26 = VAR15;
assign VAR17 = VAR18;
assign VAR21 = VAR19;
assign VAR7 = VAR24;
assign VAR22 = VAR6;
endmodule | mit |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/generic_baseblocks_v2_1/da89d453/hdl/verilog/generic_baseblocks_v2_1_carry.v | 4,334 | module MODULE1 #
(
parameter VAR7 = "VAR3"
)
(
input wire VAR9,
input wire VAR2,
input wire VAR4,
output wire VAR6
);
generate
if ( VAR7 == "VAR11" ) begin : VAR13
assign VAR6 = (VAR9 & VAR2) | (VAR4 & ~VAR2);
end else begin : VAR1
VAR10 VAR12
(
.VAR5 (VAR6),
.VAR8 (VAR9),
.VAR4 (VAR4),
.VAR2 (VAR2)
);
end
endgenerate
endmodule | gpl-3.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_hps_0.v | 31,602 | module MODULE1 #(
parameter VAR47 = 2,
parameter VAR101 = 2
) (
output wire VAR118, input wire VAR119, input wire VAR43, input wire VAR124, input wire [27:0] VAR115, input wire VAR126, input wire [7:0] VAR100, input wire [31:0] VAR26, input wire [3:0] VAR165, input wire [2:0] VAR59, input wire [1:0] VAR145, input wire [1:0] VAR127, input wire [3:0] VAR138, input wire [2:0] VAR69, input wire VAR97, output wire VAR51, input wire [4:0] VAR7, input wire [7:0] VAR56, input wire [63:0] VAR173, input wire [7:0] VAR89, input wire VAR22, input wire VAR21, output wire VAR133, output wire [7:0] VAR168, output wire [1:0] VAR109, output wire VAR151, input wire VAR12, input wire [7:0] VAR39, input wire [31:0] VAR68, input wire [3:0] VAR70, input wire [2:0] VAR186, input wire [1:0] VAR1, input wire [1:0] VAR40, input wire [3:0] VAR108, input wire [2:0] VAR14, input wire VAR36, output wire VAR144, input wire [4:0] VAR50, output wire [7:0] VAR24, output wire [63:0] VAR147, output wire [1:0] VAR84, output wire VAR44, output wire VAR163, input wire VAR140, input wire VAR75, output wire [11:0] VAR167, output wire [20:0] VAR60, output wire [3:0] VAR160, output wire [2:0] VAR192, output wire [1:0] VAR32, output wire [1:0] VAR61, output wire [3:0] VAR93, output wire [2:0] VAR141, output wire VAR15, input wire VAR72, output wire [11:0] VAR110, output wire [31:0] VAR79, output wire [3:0] VAR94, output wire VAR10, output wire VAR66, input wire VAR77, input wire [11:0] VAR91, input wire [1:0] VAR96, input wire VAR149, output wire VAR107, output wire [11:0] VAR134, output wire [20:0] VAR193, output wire [3:0] VAR3, output wire [2:0] VAR41, output wire [1:0] VAR122, output wire [1:0] VAR112, output wire [3:0] VAR187, output wire [2:0] VAR74, output wire VAR175, input wire VAR30, input wire [11:0] VAR166, input wire [31:0] VAR38, input wire [1:0] VAR177, input wire VAR37, input wire VAR183, output wire VAR128, input wire VAR125, output wire [11:0] VAR85, output wire [29:0] VAR17, output wire [3:0] VAR82, output wire [2:0] VAR20, output wire [1:0] VAR98, output wire [1:0] VAR143, output wire [3:0] VAR190, output wire [2:0] VAR5, output wire VAR95, input wire VAR178, output wire [11:0] VAR42, output wire [63:0] VAR169, output wire [7:0] VAR90, output wire VAR146, output wire VAR63, input wire VAR9, input wire [11:0] VAR57, input wire [1:0] VAR117, input wire VAR180, output wire VAR137, output wire [11:0] VAR35, output wire [29:0] VAR2, output wire [3:0] VAR182, output wire [2:0] VAR92, output wire [1:0] VAR111, output wire [1:0] VAR99, output wire [3:0] VAR76, output wire [2:0] VAR19, output wire VAR73, input wire VAR120, input wire [11:0] VAR33, input wire [63:0] VAR171, input wire [1:0] VAR6, input wire VAR139, input wire VAR123, output wire VAR81, input wire [31:0] VAR29, input wire [31:0] VAR58, output wire [14:0] VAR150, output wire [2:0] VAR181, output wire VAR49, output wire VAR18, output wire VAR25, output wire VAR142, output wire VAR102, output wire VAR54, output wire VAR154, output wire VAR176, inout wire [31:0] VAR55, inout wire [3:0] VAR148, inout wire [3:0] VAR34, output wire VAR86, output wire [3:0] VAR161, input wire VAR52, output wire VAR83, output wire VAR129, output wire VAR48, output wire VAR116, output wire VAR104, input wire VAR152, inout wire VAR106, output wire VAR114, input wire VAR158, output wire VAR189, input wire VAR185, input wire VAR13, input wire VAR67, input wire VAR45, inout wire VAR174, inout wire VAR136, inout wire VAR105, inout wire VAR27, output wire VAR157, output wire VAR80, inout wire VAR65, inout wire VAR23, inout wire VAR131, output wire VAR4, inout wire VAR46, inout wire VAR159, inout wire VAR132, inout wire VAR31, inout wire VAR172, inout wire VAR113, inout wire VAR78, inout wire VAR164, inout wire VAR11, inout wire VAR88, input wire VAR179, output wire VAR8, input wire VAR28, input wire VAR191, output wire VAR64, output wire VAR155, input wire VAR135, output wire VAR121, input wire VAR62, output wire VAR16, inout wire VAR153, inout wire VAR103, inout wire VAR156, inout wire VAR87, inout wire VAR184, inout wire VAR71, inout wire VAR170, inout wire VAR130, inout wire VAR188, inout wire VAR53, inout wire VAR162 );
generate
if (VAR47 != 2)
begin
begin | gpl-2.0 |
azonenberg/openfpga | hdl/xc2c-model/ConfigurableEdgeLatch.v | 3,129 | module MODULE1(
VAR3, clk, VAR7, VAR1, VAR6, VAR2
);
input wire VAR3;
input wire clk;
output wire VAR6;
input wire VAR7;
input wire VAR1;
input wire VAR2;
reg VAR4;
always @ begin
if(!clk)
VAR5 <= VAR3;
if(VAR7)
VAR5 <= VAR1;
end
assign VAR6 = VAR2 ? VAR4 : VAR5;
endmodule | lgpl-2.1 |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/sd_crc_16.v | 1,434 | module MODULE1(VAR6, VAR1, VAR4, VAR5, VAR3);
input VAR6; input VAR1;
input VAR4; input VAR5; output reg [15:0] VAR3;
wire VAR2;
assign VAR2 = VAR6 ^ VAR3[15];
always @(posedge VAR4 or posedge VAR5) begin
if (VAR5) begin
VAR3 = 0;
end
else begin
if (VAR1==1) begin
VAR3[15] = VAR3[14];
VAR3[14] = VAR3[13];
VAR3[13] = VAR3[12];
VAR3[12] = VAR3[11] ^ VAR2;
VAR3[11] = VAR3[10];
VAR3[10] = VAR3[9];
VAR3[9] = VAR3[8];
VAR3[8] = VAR3[7];
VAR3[7] = VAR3[6];
VAR3[6] = VAR3[5];
VAR3[5] = VAR3[4] ^ VAR2;
VAR3[4] = VAR3[3];
VAR3[3] = VAR3[2];
VAR3[2] = VAR3[1];
VAR3[1] = VAR3[0];
VAR3[0] = VAR2;
end
end
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a_2.v | 2,428 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR3 ,
VAR9 ,
VAR5 ,
VAR8 ,
VAR10,
VAR11,
VAR1 ,
VAR4
);
output VAR2 ;
input VAR7 ;
input VAR3 ;
input VAR9 ;
input VAR5 ;
input VAR8 ;
input VAR10;
input VAR11;
input VAR1 ;
input VAR4 ;
VAR6 VAR12 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR2 ,
VAR7,
VAR3,
VAR9,
VAR5,
VAR8
);
output VAR2 ;
input VAR7;
input VAR3;
input VAR9;
input VAR5;
input VAR8;
supply1 VAR10;
supply0 VAR11;
supply1 VAR1 ;
supply0 VAR4 ;
VAR6 VAR12 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule | apache-2.0 |
plindstroem/oh | xilibs/hdl/ISERDESE2.v | 3,518 | module MODULE1 (
VAR30, VAR39, VAR32, VAR2, VAR9, VAR33, VAR31, VAR45, VAR27, VAR34, VAR16,
VAR11, VAR44, VAR47, VAR24, VAR22, VAR8, VAR25, VAR7, VAR36,
VAR41, VAR19, VAR29, VAR28, VAR35, VAR5, VAR4, VAR12
);
parameter VAR43 = 0; parameter VAR20 = 0; parameter VAR21 = 0; parameter VAR46 = 0; parameter VAR1 = 0; parameter VAR26 = 0; parameter VAR38 = 0; parameter VAR42 = 0; parameter VAR13 = 0; parameter VAR23 = 0; parameter VAR37 = 0; parameter VAR6 = 0; parameter VAR17 = 0; parameter VAR3 = 0; parameter VAR14 = 0; parameter VAR10 = 0; parameter VAR18 = 0;
input VAR11; input VAR44; input VAR47; input VAR24; input VAR22; input VAR8; input VAR25; input VAR7; input VAR36; input VAR41; input VAR19; input VAR29; input VAR28; input VAR35; input VAR5; input VAR4; input VAR12;
output VAR30; output VAR39; output VAR32;
output VAR2;
output VAR9;
output VAR33;
output VAR31;
output VAR45;
output VAR27; output VAR34; output VAR16;
reg [3:0] VAR40;
reg [3:0] VAR15;
reg VAR39;
reg VAR32;
reg VAR2;
reg VAR9;
reg VAR33;
reg VAR31;
reg VAR45;
reg VAR27;
always @ (posedge VAR24)
VAR15[3:0] <= {VAR15[2:0],VAR7};
always @ (negedge VAR24)
VAR40[3:0] <= {VAR40[2:0],VAR7};
always @ (posedge VAR8)
begin
VAR39 <= VAR15[0];
VAR32 <= VAR40[0];
VAR2 <= VAR15[1];
VAR9 <= VAR40[1];
VAR33 <= VAR15[2];
VAR31 <= VAR40[2];
VAR45 <= VAR15[3];
VAR27 <= VAR40[3];
end
assign VAR30=VAR7;
assign VAR34=1'b0;
assign VAR16=1'b0;
endmodule | gpl-3.0 |
mcoughli/root_of_trust | experiments/secure_filesystem/secure_filesystem_hls/solution1/syn/verilog/filesystem_encrypbkb.v | 1,969 | module MODULE1 (VAR18, VAR8, VAR14, VAR4, VAR11, VAR19, VAR3, VAR15, VAR1, VAR9, clk);
parameter VAR20 = 128;
parameter VAR10 = 5;
parameter VAR2 = 32;
input[VAR10-1:0] VAR18;
input VAR8;
input[VAR20-1:0] VAR14;
input VAR4;
output reg[VAR20-1:0] VAR11;
input[VAR10-1:0] VAR19;
input VAR3;
input[VAR20-1:0] VAR15;
input VAR1;
output reg[VAR20-1:0] VAR9;
input clk;
reg [VAR20-1:0] VAR12[0:VAR2-1];
always @(posedge clk)
begin
if (VAR8)
begin
if (VAR4)
begin
VAR12[VAR18] <= VAR14;
VAR11 <= VAR14;
end
else
VAR11 <= VAR12[VAR18];
end
end
always @(posedge clk)
begin
if (VAR3)
begin
if (VAR1)
begin
VAR12[VAR19] <= VAR15;
VAR9 <= VAR15;
end
else
VAR9 <= VAR12[VAR19];
end
end
endmodule
module MODULE2(
reset,
clk,
VAR6,
VAR8,
VAR4,
VAR14,
VAR11,
VAR7,
VAR3,
VAR1,
VAR15,
VAR9);
parameter VAR13 = 32'd128;
parameter VAR17 = 32'd32;
parameter VAR5 = 32'd5;
input reset;
input clk;
input[VAR5 - 1:0] VAR6;
input VAR8;
input VAR4;
input[VAR13 - 1:0] VAR14;
output[VAR13 - 1:0] VAR11;
input[VAR5 - 1:0] VAR7;
input VAR3;
input VAR1;
input[VAR13 - 1:0] VAR15;
output[VAR13 - 1:0] VAR9;
MODULE1 VAR16(
.clk( clk ),
.VAR18( VAR6 ),
.VAR8( VAR8 ),
.VAR14( VAR14 ),
.VAR4( VAR4 ),
.VAR11( VAR11 ),
.VAR19( VAR7 ),
.VAR3( VAR3 ),
.VAR15( VAR15 ),
.VAR1( VAR1 ),
.VAR9( VAR9 ));
endmodule | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_jesd_align/util_jesd_align.v | 3,275 | module MODULE1 (
VAR7,
VAR9,
VAR1,
VAR3,
VAR8);
parameter VAR10 = 2;
input VAR7;
input [ 3:0] VAR9;
input [((VAR10*32)-1):0] VAR1;
output [((VAR10* 1)-1):0] VAR3;
output [((VAR10*32)-1):0] VAR8;
genvar VAR2;
generate
for (VAR2 = 0; VAR2 < VAR10; VAR2 = VAR2 + 1) begin: VAR5
VAR4 VAR6 (
.VAR7 (VAR7),
.VAR9 (VAR9),
.VAR1 (VAR1[VAR2*32+31:VAR2*32]),
.VAR3 (VAR3[VAR2]),
.VAR8 (VAR8[VAR2*32+31:VAR2*32]));
end
endgenerate
endmodule | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_hcmd_cq.v | 8,265 | module MODULE1 # (
parameter VAR10 = 128,
parameter VAR3 = 36
)
(
input VAR60,
input VAR87,
output [6:0] VAR31,
input [19:0] VAR91,
input [VAR3-1:2] VAR55,
input [7:0] VAR37,
output [7:0] VAR68,
output [7:0] VAR33,
output [7:0] VAR38,
output [7:0] VAR44,
output [7:0] VAR61,
output [7:0] VAR83,
output [7:0] VAR95,
output [7:0] VAR57,
output [7:0] VAR85,
input [7:0] VAR34,
input [7:0] VAR21,
input [7:0] VAR75,
input [7:0] VAR20,
input [7:0] VAR23,
input [7:0] VAR72,
input [7:0] VAR76,
input [7:0] VAR46,
input [7:0] VAR1,
output VAR70,
output [6:0] VAR13,
output VAR26,
output [7:0] VAR6,
output [11:2] VAR63,
output [VAR3-1:2] VAR51,
input VAR58,
input VAR73,
output [VAR10-1:0] VAR43,
input VAR64,
input VAR81,
input [34:0] VAR27,
input [34:0] VAR42,
output VAR29,
input VAR45,
input VAR7,
input [3:0] VAR32,
input [3:0] VAR77,
input [3:0] VAR36,
input [3:0] VAR92,
input [3:0] VAR25,
input [3:0] VAR14,
input [3:0] VAR48,
input [3:0] VAR11,
input [8:0] VAR86,
input [8:0] VAR50,
input [8:0] VAR69,
input [7:0] VAR88,
input [7:0] VAR22,
input [7:0] VAR8,
input [7:0] VAR54,
input [7:0] VAR65,
input [7:0] VAR41,
input [7:0] VAR19,
input [7:0] VAR16,
input [VAR3-1:2] VAR93,
input [VAR3-1:2] VAR39,
input [VAR3-1:2] VAR40,
input [VAR3-1:2] VAR30,
input [VAR3-1:2] VAR82,
input [VAR3-1:2] VAR47,
input [VAR3-1:2] VAR96,
input [VAR3-1:2] VAR52,
input VAR4,
input [34:0] VAR24,
input [34:0] VAR2,
output VAR28
);
wire VAR56;
wire [34:0] VAR9;
wire VAR15;
VAR59
VAR12(
.clk (VAR60),
.VAR79 (VAR87),
.VAR89 (VAR81),
.VAR66 (VAR27),
.VAR67 (VAR42),
.VAR5 (VAR29),
.VAR71 (),
.VAR49 (VAR56),
.VAR94 (VAR9),
.VAR18 (VAR15),
.VAR35 (VAR45),
.VAR74 (VAR87),
.VAR98 (VAR4),
.VAR84 (VAR24),
.VAR17 (VAR2),
.VAR62 (VAR28)
);
VAR97 # (
.VAR10 (VAR10)
)
VAR80(
.VAR60 (VAR60),
.VAR87 (VAR87),
.VAR78 (VAR56),
.VAR90 (VAR9),
.VAR53 (VAR15),
.VAR31 (VAR31),
.VAR91 (VAR91),
.VAR32 (VAR32),
.VAR77 (VAR77),
.VAR36 (VAR36),
.VAR92 (VAR92),
.VAR25 (VAR25),
.VAR14 (VAR14),
.VAR48 (VAR48),
.VAR11 (VAR11),
.VAR86 (VAR86),
.VAR50 (VAR50),
.VAR69 (VAR69),
.VAR37 (VAR37),
.VAR88 (VAR88),
.VAR22 (VAR22),
.VAR8 (VAR8),
.VAR54 (VAR54),
.VAR65 (VAR65),
.VAR41 (VAR41),
.VAR19 (VAR19),
.VAR16 (VAR16),
.VAR55 (VAR55),
.VAR93 (VAR93),
.VAR39 (VAR39),
.VAR40 (VAR40),
.VAR30 (VAR30),
.VAR82 (VAR82),
.VAR47 (VAR47),
.VAR96 (VAR96),
.VAR52 (VAR52),
.VAR68 (VAR68),
.VAR33 (VAR33),
.VAR38 (VAR38),
.VAR44 (VAR44),
.VAR61 (VAR61),
.VAR83 (VAR83),
.VAR95 (VAR95),
.VAR57 (VAR57),
.VAR85 (VAR85),
.VAR34 (VAR34),
.VAR21 (VAR21),
.VAR75 (VAR75),
.VAR20 (VAR20),
.VAR23 (VAR23),
.VAR72 (VAR72),
.VAR76 (VAR76),
.VAR46 (VAR46),
.VAR1 (VAR1),
.VAR70 (VAR70),
.VAR13 (VAR13),
.VAR26 (VAR26),
.VAR6 (VAR6),
.VAR63 (VAR63),
.VAR51 (VAR51),
.VAR58 (VAR58),
.VAR73 (VAR73),
.VAR43 (VAR43),
.VAR64 (VAR64)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3/sky130_fd_sc_hd__nand3.symbol.v | 1,280 | module MODULE1 (
input VAR6,
input VAR8,
input VAR3,
output VAR5
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v | 13,701 | module MODULE1 (VAR51, VAR55, VAR49, VAR44, VAR22, VAR45, VAR53,
VAR38, VAR11, VAR26, VAR10, VAR32, VAR17,
VAR48, VAR43, VAR59, VAR13,
VAR31, VAR18, VAR23, VAR20,
VAR7, VAR42, VAR8
);
input VAR51;
input VAR55;
input VAR49;
input VAR44;
input [7:0] VAR22;
input VAR45;
input VAR53;
input VAR38;
input VAR11;
input VAR26;
input [47:0]VAR10;
input VAR32;
input VAR17;
input VAR48;
input VAR43;
input VAR59;
input VAR13;
input VAR31;
input VAR7;
input VAR42;
output VAR18;
output VAR23;
output VAR20;
output VAR8;
reg VAR18;
reg VAR20; reg VAR54; reg VAR46; reg VAR50; reg [2:0] VAR2;
reg [4:0] VAR36;
reg [15:0] VAR41;
reg [15:0] VAR1;
reg VAR23;
reg VAR27;
reg VAR5;
reg VAR3;
reg [15:0] VAR16;
reg VAR29;
reg [5:0] VAR35;
wire [47:0] VAR15; wire [15:0] VAR19; wire VAR12; wire VAR4; wire VAR30; wire VAR37; wire VAR28; wire VAR58; wire VAR39; wire VAR56; wire VAR25; wire VAR33; wire VAR14; wire VAR21; wire VAR9; wire VAR47; wire VAR40; wire VAR6; wire VAR24; wire VAR52; wire VAR57; wire VAR34;
assign VAR15 = 48'h0180C2000001;
assign VAR19 = 16'h8808;
always @ (posedge VAR55 or posedge VAR44)
begin
if(VAR44)
VAR20 <= 1'b0;
end
else
if(VAR46 & VAR30)
VAR20 <= VAR22[7:0] == VAR15[47:40] | VAR22[7:0] == VAR10[47:40];
else
if(VAR46 & VAR37)
VAR20 <= (VAR22[7:0] == VAR15[39:32] | VAR22[7:0] == VAR10[39:32]) & VAR20;
else
if(VAR46 & VAR28)
VAR20 <= (VAR22[7:0] == VAR15[31:24] | VAR22[7:0] == VAR10[31:24]) & VAR20;
else
if(VAR46 & VAR58)
VAR20 <= (VAR22[7:0] == VAR15[23:16] | VAR22[7:0] == VAR10[23:16]) & VAR20;
else
if(VAR46 & VAR39)
VAR20 <= (VAR22[7:0] == VAR15[15:8] | VAR22[7:0] == VAR10[15:8]) & VAR20;
else
if(VAR46 & VAR56)
VAR20 <= (VAR22[7:0] == VAR15[7:0] | VAR22[7:0] == VAR10[7:0]) & VAR20;
else
if(VAR26)
VAR20 <= 1'b0;
end
always @ (posedge VAR55 or posedge VAR44 )
begin
if(VAR44)
VAR54 <= 1'b0;
end
else
if(VAR46 & VAR25)
VAR54 <= VAR25 & (VAR22[7:0] == VAR19[15:8]);
else
if(VAR46 & VAR33)
VAR54 <= VAR33 & (VAR22[7:0] == VAR19[7:0]) & VAR54;
else
if(VAR26)
VAR54 <= 1'b0;
end
always @ (posedge VAR55 or posedge VAR44 )
begin
if(VAR44)
VAR50 <= 1'b0;
end
else
if(VAR9)
VAR50 <= 1'b0;
else
begin
if(VAR46 & VAR14)
VAR50 <= VAR14 & VAR22[7:0] == 8'h00;
if(VAR46 & VAR21)
VAR50 <= VAR21 & VAR22[7:0] == 8'h01 & VAR50;
end
end
always @ (posedge VAR55 or posedge VAR44 )
begin
if(VAR44)
VAR27 <= 1'b0;
end
else
if(VAR26)
VAR27 <= 1'b0;
else
if(VAR9 & VAR54 & VAR50 & VAR20)
VAR27 <= 1'b1;
end
always @ (posedge VAR55 or posedge VAR44 )
begin
if(VAR44)
VAR41[15:0] <= 16'h0;
end
else
if(VAR53)
VAR41[15:0] <= 16'h0;
else
begin
if(VAR46 & VAR9)
VAR41[15:8] <= VAR22[7:0];
if(VAR46 & VAR47)
VAR41[7:0] <= VAR22[7:0];
end
end
always @ (posedge VAR55 or posedge VAR44 )
begin
if(VAR44)
VAR46 <= 1'b1;
end
else
if(VAR40)
VAR46 <= 1'b0;
else
if(VAR26)
VAR46 <= 1'b1;
end
always @ (posedge VAR55 or posedge VAR44 )
begin
if(VAR44)
VAR1[15:0] <= 16'h0;
end
else
if(VAR46 & VAR27 & VAR40)
VAR1[15:0] <= VAR41[15:0];
else
if(VAR26)
VAR1[15:0] <= 16'h0;
end
always @ (posedge VAR55 or posedge VAR44)
begin
if(VAR44)
VAR2 <= 3'h0;
end
else
if(VAR45 & VAR38)
VAR2 <= 3'h0;
else
if(VAR45 & ~VAR38 & ~VAR2[2])
VAR2 <= VAR2 + 3'd1;
end
assign VAR12 = VAR38;
assign VAR4 = VAR45 & VAR46 & ~VAR40 &
(~VAR32 | VAR32 & VAR2[2]);
always @ (posedge VAR55 or posedge VAR44)
begin
if(VAR44)
VAR36[4:0] <= 5'h0;
end
else
if(VAR12)
VAR36[4:0] <= 5'h0;
else
if(VAR4)
VAR36[4:0] <= VAR36[4:0] + 5'd1;
end
assign VAR30 = VAR45 & VAR36[4:0] == 5'h0;
assign VAR37 = VAR45 & VAR36[4:0] == 5'h1;
assign VAR28 = VAR45 & VAR36[4:0] == 5'h2;
assign VAR58 = VAR45 & VAR36[4:0] == 5'h3;
assign VAR39 = VAR45 & VAR36[4:0] == 5'h4;
assign VAR56 = VAR45 & VAR36[4:0] == 5'h5;
assign VAR25 = VAR45 & VAR36[4:0] == 5'h0C;
assign VAR33 = VAR45 & VAR36[4:0] == 5'h0D;
assign VAR14 = VAR45 & VAR36[4:0] == 5'h0E;
assign VAR21 = VAR45 & VAR36[4:0] == 5'h0F;
assign VAR9 = VAR45 & VAR36[4:0] == 5'h10;
assign VAR47 = VAR45 & VAR36[4:0] == 5'h11;
assign VAR40 = VAR45 & VAR36[4:0] == 5'h12 & VAR46;
assign VAR8 = VAR26 & VAR27 & VAR13 & VAR59 & VAR11;
assign VAR6 = VAR34 & |VAR16;
always @ (posedge VAR55 or posedge VAR44)
begin
if(VAR44)
VAR16[15:0] <= 16'h0;
end
else
if(VAR8)
VAR16[15:0] <= VAR1[15:0];
else
if(VAR6)
VAR16[15:0] <= VAR16[15:0] - 16'd1;
end
assign VAR24 = ~(|VAR16[15:0]);
always @ (posedge VAR51 or posedge VAR49)
begin
if(VAR49)
begin
VAR5 <= 1'b1;
VAR3 <= 1'b1;
end
else
begin
VAR5 <= VAR24;
VAR3 <= VAR5;
end
end
always @ (posedge VAR51 or posedge VAR49)
begin
if(VAR49)
VAR18 <= 1'b0;
end
else
if((VAR17 | VAR48 | ~VAR31) & ~VAR43)
VAR18 <= VAR11 & ~VAR3;
end
always @ (posedge VAR55 or posedge VAR44)
begin
if(VAR44)
VAR29 <= 1'b0;
end
else
if(|VAR16[15:0] & VAR11)
VAR29 <= ~VAR29;
else
VAR29 <= 1'b0;
end
assign VAR52 = VAR44;
assign VAR57 = VAR18 & VAR11 & VAR29;
always @ (posedge VAR55 or posedge VAR44)
begin
if(VAR44)
VAR35[5:0] <= 6'h0;
end
else
if(VAR52)
VAR35[5:0] <= 6'h0;
else
if(VAR57)
VAR35[5:0] <= VAR35[5:0] + 6'd1;
end
assign VAR34 = &VAR35[5:0] & VAR57;
always @ (posedge VAR55 or posedge VAR44)
begin
if(VAR44)
VAR23 <= 1'b0;
end
else
if(VAR7 & VAR42 | VAR23 & (~VAR42))
VAR23 <= 1'b0;
else
if(VAR9 & VAR54 & VAR50)
VAR23 <= 1'b1;
end
endmodule | gpl-2.0 |
ultraembedded/altor32 | rtl/peripheral/uart.v | 9,016 | module MODULE1
(
VAR13,
VAR24,
VAR11,
VAR5,
VAR7,
VAR19,
VAR1,
VAR21,
VAR8,
VAR14,
VAR10
);
parameter [31:0] VAR15 = 278;
input VAR13 ;
input VAR24 ;
input [7:0] VAR19 ;
output [7:0] VAR21 ;
input VAR1 ;
input VAR8 ;
output VAR11 ;
output VAR5 ;
output VAR7 ;
input VAR14 ;
output VAR10 ;
parameter VAR4 = VAR15;
parameter VAR2 = (VAR4 / 2);
reg [7:0] VAR6;
reg VAR17;
reg VAR9;
reg [3:0] VAR18;
integer VAR3;
reg [7:0] VAR12;
reg VAR10;
reg VAR20;
reg [7:0] VAR21;
reg [3:0] VAR23;
integer VAR22;
reg [7:0] VAR16;
reg VAR5;
reg VAR7;
always @ (posedge VAR24 or posedge VAR13 )
begin
if (VAR24 == 1'b1)
VAR20 <= 1'b1;
end
else
VAR20 <= VAR14;
end
always @ (posedge VAR13 or posedge VAR24 )
begin
if (VAR24 == 1'b1)
begin
VAR23 <= 0;
VAR22 <= 0;
VAR5 <= 1'b0;
VAR16 <= 8'h00;
VAR21 <= 8'h00;
VAR7 <= 1'b0;
end
else
begin
if (VAR8 == 1'b1)
VAR5 <= 1'b0;
if (VAR22 != 0)
VAR22 <= (VAR22 - 1);
end
else
begin
if (VAR23 == 0)
begin
VAR7 <= 1'b0;
if (VAR20 == 1'b0)
begin
VAR22 <= VAR2;
VAR23 <= 1;
end
end
else if (VAR23 == 1)
begin
if (VAR20 == 1'b0)
begin
VAR22 <= VAR4;
VAR23 <= VAR23 + 1'b1;
VAR16 <= 8'h00;
end
else
begin
VAR23 <= 0;
end
end
else if (VAR23 == 10)
begin
if (VAR20 == 1'b1)
begin
VAR22 <= 0;
VAR23 <= 0;
VAR21 <= VAR16;
VAR5 <= 1'b1;
end
else
begin
VAR22 <= VAR4;
VAR23 <= 0;
VAR7 <= 1'b1;
end
end
else
begin
VAR16[7] <= VAR20;
VAR16[6:0]<= VAR16[7:1];
VAR22 <= VAR4;
VAR23 <= VAR23 + 1'b1;
end
end
end
end
always @ (posedge VAR13 or posedge VAR24 )
begin
if (VAR24 == 1'b1)
begin
VAR3 <= 0;
VAR18 <= 0;
VAR9 <= 1'b0;
VAR10 <= 1'b1;
VAR12 <= 8'h00;
VAR6 <= 8'h00;
VAR17 <= 1'b0;
end
else
begin
if (VAR1 == 1'b1)
begin
VAR6 <= VAR19;
VAR17 <= 1'b1;
end
if (VAR3 != 0)
VAR3 <= (VAR3 - 1);
end
else
begin
if (VAR18 == 0)
begin
VAR9 <= 1'b0;
if (VAR17 == 1'b1)
begin
VAR12 <= VAR6;
VAR9 <= 1'b1;
VAR10 <= 1'b0;
VAR17 <= 1'b0;
VAR18 <= 1;
VAR3 <= VAR4;
end
end
else if (VAR18 == 9)
begin
VAR10 <= 1'b1;
VAR18 <= 0;
VAR3 <= VAR4;
end
else
begin
VAR10 <= VAR12[0];
VAR12[6:0]<= VAR12[7:1];
VAR18 <= VAR18 + 1'b1;
VAR3 <= VAR4;
end
end
end
end
assign VAR11 = (VAR9 | VAR17 | VAR1);
endmodule | lgpl-3.0 |
jameshegarty/rigel | platform/camera2.0/vsrc/DramReaderBuf.v | 4,591 | module MODULE1(
input VAR40,
input VAR28,
output VAR39,
output reg VAR8,
input VAR14,
output reg [31:0] VAR1,
output [1:0] VAR42,
output [3:0] VAR11,
output [1:0] VAR19,
input VAR21,
output VAR38,
input VAR6,
input [63:0] VAR16,
input [1:0] VAR22,
input VAR18,
output reg VAR24,
input [31:0] VAR9,
input [31:0] VAR2,
output [1:0] VAR43,
input VAR3,
output VAR44,
output [63:0] dout
);
assign VAR39 = VAR40;
assign VAR11 = 4'b1111;
assign VAR19 = 2'b11;
assign VAR42 = 2'b01;
wire VAR41;
wire VAR4;
wire VAR10;
wire [63:0] VAR49;
reg [31:0] VAR27;
reg [31:0] VAR36;
VAR13(VAR40, VAR27, 0, VAR18 && VAR24 ? VAR2 : VAR27)
VAR13(VAR40, VAR36, 0, VAR18 && VAR24 ? VAR9 : VAR36)
wire VAR46;
assign VAR46 = (VAR1 + 128)==(VAR27+VAR36);
localparam VAR12 = 0, VAR34 = 1, VAR5=2;
reg [1:0] VAR30;
assign VAR43 = VAR30;
always @(posedge VAR40 or negedge VAR28) begin
if (!VAR28) begin
VAR30 <= VAR12;
VAR1 <= 0;
VAR8 <= 0;
VAR24 <= 0;
end
else begin
VAR8 <= 0;
VAR24 <= 0;
case(VAR30)
VAR12 : begin
VAR24 <= 1;
if (VAR18) begin
VAR1 <= VAR2;
VAR30 <= VAR34;
end
end
VAR34 : begin
if (VAR41 && VAR14) begin
VAR30 <= VAR5 ;
VAR8 <= 1 ;
end
end
VAR5: begin
if (VAR26 == VAR35) begin
VAR1 <= VAR1 + 128; VAR30 <= VAR46 ? VAR12 : VAR34 ;
end
end
endcase
end
end
localparam VAR35=0, VAR31=1;
reg [3:0] VAR25;
reg VAR26;
assign VAR38 = (VAR26 == VAR31) && VAR4;
always @(posedge VAR40 or negedge VAR28) begin
if (VAR28 == 0) begin
VAR26 <= VAR35;
VAR25 <= 0;
end else case(VAR26)
VAR35: begin
if (VAR30==VAR34 && VAR41 && VAR14) begin
VAR25 <= 4'd15;
VAR26 <= VAR31;
end
end
VAR31: begin
if (VAR21 && VAR4) begin
if(VAR25 == 4'h0) begin
VAR26 <= VAR35;
end
VAR25 <= VAR25 - 1'b1; end
end
endcase
end
wire [8:0] VAR7;
wire [8:0] VAR47;
wire VAR48;
wire VAR20;
assign VAR49 = VAR16;
assign VAR10 = VAR21 && (VAR26 == VAR31);
assign VAR41 = (VAR47 < 9'd450);
assign VAR4 = !VAR48;
VAR23 VAR33 (
.rst(!VAR28), .VAR15(VAR40), .VAR37(VAR40), .din(VAR49[63:0]), .VAR45(VAR10), .VAR17(VAR3), .dout(dout[63:0]), .VAR29(VAR48), .VAR32(VAR20), .VAR7(VAR7[8:0]), .VAR47(VAR47[8:0]) );
assign VAR44 = !VAR20;
endmodule : MODULE1 | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_wdog.v | 11,018 | module MODULE1(
input VAR69,
input reset,
input VAR52,
input [31:0] VAR124,
output [31:0] VAR94,
input VAR131,
input [31:0] VAR21,
output [31:0] VAR73,
input VAR19,
input [31:0] VAR98,
output [31:0] VAR55,
input VAR10,
input [15:0] VAR72,
output [15:0] VAR121,
input VAR41,
input [15:0] VAR34,
output [15:0] VAR50,
input VAR104,
input [31:0] VAR57,
output [31:0] VAR118,
input VAR135,
input [31:0] VAR108,
output [31:0] VAR91,
output VAR35,
input VAR127,
output VAR101
);
wire [3:0] VAR44;
wire VAR15;
wire VAR46;
wire VAR93;
wire VAR60;
wire VAR23;
wire VAR95;
wire VAR103;
wire VAR51;
wire VAR84;
wire VAR97;
wire VAR70;
wire VAR13;
wire VAR9;
wire VAR137;
wire VAR30;
wire VAR112;
reg [3:0] VAR47;
reg [31:0] VAR39;
wire [3:0] VAR58;
wire VAR79;
reg [15:0] VAR7;
reg [31:0] VAR33;
wire [15:0] VAR66;
reg VAR132;
reg [31:0] VAR63;
reg VAR115;
reg [31:0] VAR78;
wire VAR90;
wire VAR14;
wire VAR85;
wire VAR38;
wire VAR102;
wire VAR24;
wire VAR99;
wire VAR8;
wire VAR40;
wire VAR106;
wire VAR42;
wire VAR107;
wire VAR129;
wire VAR4;
wire VAR5;
wire VAR114;
wire VAR22;
reg [4:0] VAR2;
reg [31:0] VAR89;
wire [4:0] VAR100;
wire [5:0] VAR83;
reg [25:0] VAR54;
reg [31:0] VAR126;
wire VAR65;
wire [26:0] VAR113;
wire [26:0] VAR49;
wire [30:0] VAR92;
wire VAR64;
wire [32:0] VAR128;
wire [27:0] VAR32;
wire [32:0] VAR71;
wire [27:0] VAR88;
wire [30:0] VAR139;
wire [15:0] VAR75;
wire VAR53;
wire VAR105;
wire VAR12;
wire VAR27;
wire VAR81;
reg VAR43;
reg [31:0] VAR20;
wire VAR86;
wire VAR68;
wire VAR11;
wire [32:0] VAR1;
wire [27:0] VAR31;
wire VAR67;
wire VAR130;
wire VAR74;
reg VAR62;
reg [31:0] VAR119;
wire VAR120;
wire VAR36;
wire VAR29;
wire VAR17;
wire VAR59;
wire VAR76;
wire VAR138;
wire VAR111;
wire [4:0] VAR117;
wire [8:0] VAR110;
wire [2:0] VAR56;
wire [11:0] VAR26;
wire [2:0] VAR3;
wire [3:0] VAR28;
wire [4:0] VAR48;
wire [12:0] VAR80;
wire [16:0] VAR116;
wire [28:0] VAR61;
wire VAR37;
wire VAR134;
wire VAR96;
wire VAR125;
wire VAR122;
wire VAR109;
wire VAR136;
VAR45 VAR77 (
.VAR69(VAR97),
.reset(VAR70),
.VAR133(VAR13),
.VAR123(VAR9),
.VAR18(VAR137)
);
VAR45 VAR82 (
.VAR69(VAR14),
.reset(VAR85),
.VAR133(VAR38),
.VAR123(VAR102),
.VAR18(VAR24)
);
VAR45 VAR6 (
.VAR69(VAR40),
.reset(VAR106),
.VAR133(VAR42),
.VAR123(VAR107),
.VAR18(VAR129)
);
VAR45 VAR25 (
.VAR69(VAR29),
.reset(VAR17),
.VAR133(VAR59),
.VAR123(VAR76),
.VAR18(VAR138)
);
VAR45 VAR16 (
.VAR69(VAR96),
.reset(VAR125),
.VAR133(VAR122),
.VAR123(VAR109),
.VAR18(VAR136)
);
assign VAR94 = {{3'd0}, VAR61};
assign VAR73 = {{1'd0}, VAR92};
assign VAR55 = 32'h0;
assign VAR121 = VAR75;
assign VAR50 = VAR7;
assign VAR118 = 32'h0;
assign VAR91 = {{31'd0}, VAR30};
assign VAR35 = VAR37;
assign VAR101 = VAR109;
assign VAR44 = VAR124[3:0];
assign VAR15 = VAR104 | VAR41;
assign VAR46 = VAR15 | VAR10;
assign VAR93 = VAR46 | VAR19;
assign VAR60 = VAR93 | VAR131;
assign VAR23 = VAR60 | VAR52;
assign VAR95 = VAR108 == 32'h51f15e;
assign VAR103 = VAR23 == 1'h0;
assign VAR51 = VAR95 & VAR103;
assign VAR84 = VAR135 | VAR23;
assign VAR97 = VAR69;
assign VAR70 = reset;
assign VAR13 = VAR51;
assign VAR137 = VAR84;
assign VAR30 = VAR9;
assign VAR112 = VAR52 & VAR30;
assign VAR58 = VAR112 ? VAR44 : VAR47;
assign VAR79 = VAR41 & VAR30;
assign VAR66 = VAR79 ? VAR34 : VAR7;
assign VAR90 = VAR124[12];
assign VAR14 = VAR69;
assign VAR85 = reset;
assign VAR38 = VAR90;
assign VAR24 = VAR112;
assign VAR99 = VAR102;
assign VAR8 = VAR124[13];
assign VAR40 = VAR69;
assign VAR106 = reset;
assign VAR42 = VAR8;
assign VAR129 = VAR112;
assign VAR4 = VAR107;
assign VAR5 = VAR115 == 1'h0;
assign VAR114 = VAR4 & VAR5;
assign VAR22 = VAR99 | VAR114;
assign VAR100 = {{4'd0}, VAR22};
assign VAR83 = VAR2 + VAR100;
assign VAR65 = VAR83[5];
assign VAR113 = VAR54 + 26'h1;
assign VAR49 = VAR65 ? VAR113 : {{1'd0}, VAR54};
assign VAR92 = {VAR54,VAR2};
assign VAR64 = VAR131 & VAR30;
assign VAR128 = {1'h0,VAR21};
assign VAR32 = VAR128[32:5];
assign VAR71 = VAR64 ? VAR128 : {{27'd0}, VAR83};
assign VAR88 = VAR64 ? VAR32 : {{1'd0}, VAR49};
assign VAR139 = VAR92 >> VAR47;
assign VAR75 = VAR139[15:0];
assign VAR53 = VAR75 >= VAR7;
assign VAR105 = VAR30 & VAR104;
assign VAR12 = VAR57 == 32'hd09f00d;
assign VAR27 = VAR105 & VAR12;
assign VAR81 = VAR124[9];
assign VAR86 = VAR112 ? VAR81 : VAR43;
assign VAR68 = VAR43 & VAR53;
assign VAR11 = VAR27 | VAR68;
assign VAR1 = VAR11 ? 33'h0 : VAR71;
assign VAR31 = VAR11 ? 28'h0 : VAR88;
assign VAR67 = VAR124[28];
assign VAR130 = VAR67 | VAR53;
assign VAR74 = VAR112 | VAR53;
assign VAR120 = VAR74 ? VAR130 : VAR62;
assign VAR36 = VAR124[8];
assign VAR29 = VAR69;
assign VAR17 = reset;
assign VAR59 = VAR36;
assign VAR138 = VAR112;
assign VAR111 = VAR76;
assign VAR117 = {VAR111,4'h0};
assign VAR110 = {VAR117,VAR47};
assign VAR56 = {2'h0,VAR43};
assign VAR26 = {VAR56,VAR110};
assign VAR3 = {2'h0,VAR4};
assign VAR28 = {VAR3,VAR99};
assign VAR48 = {VAR62,4'h0};
assign VAR80 = {VAR48,8'h0};
assign VAR116 = {VAR80,VAR28};
assign VAR61 = {VAR116,VAR26};
assign VAR37 = VAR62;
assign VAR134 = VAR111 & VAR53;
assign VAR96 = VAR69;
assign VAR125 = reset;
assign VAR122 = 1'h1;
assign VAR136 = VAR134;
integer VAR87; | apache-2.0 |
cthulhuology/avm | alu.v | 2,573 | module MODULE1 (
input VAR6,
input [7:0] VAR2,
input [VAR4-1:0] VAR8,
input [VAR4-1:0] VAR1,
output [VAR4-1:0] VAR7,
output [VAR4-1:0] VAR3);
reg [VAR4-1:0] VAR8;
reg [VAR4-1:0] VAR1;
reg [VAR4*2-1:0] VAR5;
assign VAR7 = VAR8;
assign VAR3 = VAR1;
always @(posedge VAR6) begin
case(VAR2)
8'b00000100:
VAR8 <= - VAR8;
8'b00000101:
VAR8 <= VAR1 + VAR8;
8'b00000110:
begin
VAR5 = VAR1 * VAR8;
VAR8 <= VAR5[VAR4-1:0];
VAR1 <= VAR5[(VAR4*2)-1:VAR4];
end
8'b00000111:
begin
VAR8 <= VAR1 / VAR8;
VAR1 <= VAR1 % VAR8;
end
8'b00001000:
VAR8 <= ~ VAR8;
8'b00001001:
VAR8 <= VAR1 & VAR8;
8'b00001010:
VAR8 <= VAR1 | VAR8;
8'b00001011:
VAR8 <= VAR1 ^ VAR8;
default:
VAR8 <= VAR8;
endcase
end
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv.behavioral.v | 1,321 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR8;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR6 ;
wire VAR9;
not VAR2 (VAR9, VAR4 );
buf VAR1 (VAR3 , VAR9 );
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/amber23/a23_alu.v | 7,595 | module MODULE1 (
input [31:0] VAR32,
input [31:0] VAR2,
input VAR36,
input VAR31,
input [8:0] VAR1,
output [31:0] VAR26,
output [3:0] VAR9 );
wire [31:0] VAR28, VAR10, VAR13;
wire [31:0] VAR24, VAR15, VAR3;
wire [31:0] VAR30, VAR6;
wire [31:0] VAR16, VAR22;
wire [32:0] VAR19;
wire VAR34;
wire VAR33;
wire [1:0] VAR14;
wire VAR12;
wire [3:0] VAR8;
wire VAR18;
wire VAR7;
wire VAR37;
wire VAR25;
assign { VAR34, VAR33, VAR14, VAR12, VAR8 } = VAR1;
assign VAR28 = (VAR34 ) ? VAR2 : VAR32 ;
assign VAR10 = (VAR34 ) ? VAR32 : VAR2 ;
assign VAR13 = (VAR33 ) ? ~VAR10 : VAR10 ;
assign VAR18 = (VAR14==2'd0 ) ? 1'd0 :
(VAR14==2'd1 ) ? 1'd1 :
VAR31 ;
assign VAR7 = (VAR12==1'd0 ) ? VAR25 :
VAR36 ;
assign VAR37 = VAR8 == 4'd1 &&
( (!VAR28[31] && !VAR13[31] && VAR19[31]) ||
(VAR28[31] && VAR13[31] && !VAR19[31]) );
VAR5 #(.VAR35(33))
VAR11 #(.VAR35(33))
VAR20(
.VAR29 ( {1'd0,VAR28} ),
.VAR17 ( {1'd0,VAR13} ),
.VAR23 ( VAR18 ),
.VAR21 ( 1'd0 ),
.VAR4 ( VAR19 ),
.VAR27 ( )
);
assign VAR19 = { 1'd0,VAR28} + {1'd0,VAR13} + {32'd0,VAR18};
assign VAR25 = VAR19[32];
assign VAR24 = VAR28 & VAR13;
assign VAR15 = VAR28 | VAR13;
assign VAR3 = VAR28 ^ VAR13;
assign VAR16 = {24'd0, VAR13[7:0]};
assign VAR22 = {16'd0, VAR13[15:0]};
assign VAR30 = {{24{VAR13[7]}}, VAR13[7:0]};
assign VAR6 = {{16{VAR13[15]}}, VAR13[15:0]};
assign VAR26 = VAR8 == 4'd0 ? VAR13 :
VAR8 == 4'd1 ? VAR19[31:0] :
VAR8 == 4'd2 ? VAR22 :
VAR8 == 4'd3 ? VAR16 :
VAR8 == 4'd4 ? VAR6 :
VAR8 == 4'd5 ? VAR30 :
VAR8 == 4'd6 ? VAR3 :
VAR8 == 4'd7 ? VAR15 :
VAR24 ;
assign VAR9 = { VAR26[31], |VAR26 == 1'd0, VAR7, VAR37 };
endmodule | gpl-3.0 |
CospanDesign/vivado-ip-cores | ip/axi_lite_i2c/sources_1/i2c_master_bit_ctrl.v | 20,675 | module MODULE1 (
input clk, input rst, input VAR25, input VAR50,
input [15:0] VAR8,
input [ 3:0] VAR31, output reg VAR5, output reg VAR27, output reg VAR6,
input din,
output reg dout = 0,
input VAR11, output VAR21, output reg VAR14, input VAR9, output VAR44, output reg VAR7 );
reg [ 1:0] VAR10, VAR16; reg [ 2:0] VAR30, VAR40; reg VAR39, VAR49; reg VAR20, VAR33; reg VAR29; reg VAR23; reg VAR48; reg VAR38; reg [15:0] VAR52; reg [13:0] VAR18;
reg [5:0] VAR46;
always @(posedge clk)
VAR29 <= VAR14;
always @(posedge clk or negedge VAR25)
if (!VAR25) VAR38 <= 1'b0;
else VAR38 <= (VAR14 & ~VAR29 & ~VAR39) | (VAR38 & ~VAR39);
wire VAR26 = VAR20 & ~VAR39 & VAR14;
always @(posedge clk or negedge VAR25)
if (~VAR25)
begin
VAR52 <= 16'h0;
VAR48 <= 1'b1;
end
else if (rst || ~|VAR52 || !VAR50 || VAR26)
begin
VAR52 <= VAR8;
VAR48 <= 1'b1;
end
else if (VAR38)
begin
VAR52 <= VAR52;
VAR48 <= 1'b0;
end
else
begin
VAR52 <= VAR52 - 16'h1;
VAR48 <= 1'b0;
end
always @(posedge clk or negedge VAR25)
if (!VAR25)
begin
VAR10 <= 2'b00;
VAR16 <= 2'b00;
end
else if (rst)
begin
VAR10 <= 2'b00;
VAR16 <= 2'b00;
end
else
begin
VAR10 <= {VAR10[0],VAR11};
VAR16 <= {VAR16[0],VAR9};
end
always @(posedge clk or negedge VAR25)
if (!VAR25 ) VAR18 <= 14'h0;
else if (rst || !VAR50 ) VAR18 <= 14'h0;
else if (~|VAR18) VAR18 <= VAR8 >> 2; else VAR18 <= VAR18 -1;
always @(posedge clk or negedge VAR25)
if (!VAR25)
begin
VAR30 <= 3'b111;
VAR40 <= 3'b111;
end
else if (rst)
begin
VAR30 <= 3'b111;
VAR40 <= 3'b111;
end
else if (~|VAR18)
begin
VAR30 <= {VAR30[1:0],VAR10[1]};
VAR40 <= {VAR40[1:0],VAR16[1]};
end
always @(posedge clk or negedge VAR25)
if (~VAR25)
begin
VAR39 <= 1'b1;
VAR49 <= 1'b1;
VAR20 <= 1'b1;
VAR33 <= 1'b1;
end
else if (rst)
begin
VAR39 <= 1'b1;
VAR49 <= 1'b1;
VAR20 <= 1'b1;
VAR33 <= 1'b1;
end
else
begin
VAR39 <= &VAR30[2:1] | &VAR30[1:0] | (VAR30[2] & VAR30[0]);
VAR49 <= &VAR40[2:1] | &VAR40[1:0] | (VAR40[2] & VAR40[0]);
VAR20 <= VAR39;
VAR33 <= VAR49;
end
reg VAR43;
reg VAR13;
always @(posedge clk or negedge VAR25)
if (~VAR25)
begin
VAR43 <= 1'b0;
VAR13 <= 1'b0;
end
else if (rst)
begin
VAR43 <= 1'b0;
VAR13 <= 1'b0;
end
else
begin
VAR43 <= ~VAR49 & VAR33 & VAR39;
VAR13 <= VAR49 & ~VAR33 & VAR39;
end
always @(posedge clk or negedge VAR25)
if (!VAR25) VAR27 <= 1'b0;
else if (rst ) VAR27 <= 1'b0;
else VAR27 <= (VAR43 | VAR27) & ~VAR13;
reg VAR28;
always @(posedge clk or negedge VAR25)
if (~VAR25)
VAR28 <= 1'b0;
else if (rst)
VAR28 <= 1'b0;
else if (VAR48)
VAR28 <= VAR31 == VAR19;
always @(posedge clk or negedge VAR25)
if (~VAR25)
VAR6 <= 1'b0;
else if (rst)
VAR6 <= 1'b0;
else
VAR6 <= (VAR23 & ~VAR49 & VAR7) | (|VAR46 & VAR13 & ~VAR28);
always @(posedge clk)
if (VAR39 & ~VAR20) dout <= VAR49;
parameter VAR45 = 0;
parameter VAR22 = 1;
parameter VAR36 = 2;
parameter VAR35 = 3;
parameter VAR37 = 4;
parameter VAR4 = 5;
parameter VAR32 = 6;
parameter VAR34 = 7;
parameter VAR2 = 8;
parameter VAR15 = 9;
parameter VAR51 = 10;
parameter VAR24 = 11;
parameter VAR47 = 12;
parameter VAR12 = 13;
parameter VAR42 = 14;
parameter VAR1 = 15;
parameter VAR3 = 16;
parameter VAR17 = 17;
always @(posedge clk or negedge VAR25)
if (!VAR25)
begin
VAR46 <= VAR45;
VAR5 <= 1'b0;
VAR14 <= 1'b1;
VAR7 <= 1'b1;
VAR23 <= 1'b0;
end
else if (rst | VAR6)
begin
VAR46 <= VAR45;
VAR5 <= 1'b0;
VAR14 <= 1'b1;
VAR7 <= 1'b1;
VAR23 <= 1'b0;
end
else
begin
VAR5 <= 1'b0;
if (VAR48)
case (VAR46) VAR45:
begin
case (VAR31) VAR41: VAR46 <= VAR22;
default: VAR46 <= VAR45;
endcase
VAR14 <= VAR14; VAR7 <= VAR7; VAR23 <= 1'b0; end
VAR22:
begin
VAR46 <= VAR36;
VAR14 <= VAR14; VAR7 <= 1'b1; VAR23 <= 1'b0; end
VAR36:
begin
VAR46 <= VAR35;
VAR14 <= 1'b1; VAR7 <= 1'b1; VAR23 <= 1'b0; end
VAR35:
begin
VAR46 <= VAR37;
VAR14 <= 1'b1; VAR7 <= 1'b0; VAR23 <= 1'b0; end
VAR37:
begin
VAR46 <= VAR4;
VAR14 <= 1'b1; VAR7 <= 1'b0; VAR23 <= 1'b0; end
VAR4:
begin
VAR46 <= VAR45;
VAR5 <= 1'b1;
VAR14 <= 1'b0; VAR7 <= 1'b0; VAR23 <= 1'b0; end
VAR32:
begin
VAR46 <= VAR34;
VAR14 <= 1'b0; VAR7 <= 1'b0; VAR23 <= 1'b0; end
VAR34:
begin
VAR46 <= VAR2;
VAR14 <= 1'b1; VAR7 <= 1'b0; VAR23 <= 1'b0; end
VAR2:
begin
VAR46 <= VAR15;
VAR14 <= 1'b1; VAR7 <= 1'b0; VAR23 <= 1'b0; end
VAR15:
begin
VAR46 <= VAR45;
VAR5 <= 1'b1;
VAR14 <= 1'b1; VAR7 <= 1'b1; VAR23 <= 1'b0; end
VAR51:
begin
VAR46 <= VAR24;
VAR14 <= 1'b0; VAR7 <= 1'b1; VAR23 <= 1'b0; end
VAR24:
begin
VAR46 <= VAR47;
VAR14 <= 1'b1; VAR7 <= 1'b1; VAR23 <= 1'b0; end
VAR47:
begin
VAR46 <= VAR12;
VAR14 <= 1'b1; VAR7 <= 1'b1; VAR23 <= 1'b0; end
VAR12:
begin
VAR46 <= VAR45;
VAR5 <= 1'b1;
VAR14 <= 1'b0; VAR7 <= 1'b1; VAR23 <= 1'b0; end
VAR42:
begin
VAR46 <= VAR1;
VAR14 <= 1'b0; VAR7 <= din; VAR23 <= 1'b0; end
VAR1:
begin
VAR46 <= VAR3;
VAR14 <= 1'b1; VAR7 <= din; VAR23 <= 1'b0; end
VAR3:
begin
VAR46 <= VAR17;
VAR14 <= 1'b1; VAR7 <= din;
VAR23 <= 1'b1; end
VAR17:
begin
VAR46 <= VAR45;
VAR5 <= 1'b1;
VAR14 <= 1'b0; VAR7 <= din;
VAR23 <= 1'b0; end
endcase
end
assign VAR21 = 1'b0;
assign VAR44 = 1'b0;
endmodule | mit |
ptracton/wb_soc_template | rtl/ZIP/rtl/busdelay.v | 6,251 | module MODULE1(VAR22,
VAR9, VAR23, VAR4, VAR26, VAR28, VAR5,
VAR27, VAR18, VAR6, VAR12,
VAR29, VAR7, VAR13, VAR17,VAR2,VAR11,
VAR24, VAR19, VAR16, VAR1);
parameter VAR20=32, VAR30=32, VAR31 = 0;
input wire VAR22;
input wire VAR9, VAR23, VAR4;
input wire [(VAR20-1):0] VAR26;
input wire [(VAR30-1):0] VAR28;
input wire [(VAR30/8-1):0] VAR5;
output reg VAR27;
output wire VAR18;
output reg [(VAR30-1):0] VAR6;
output wire VAR12;
output reg VAR29, VAR7, VAR13;
output reg [(VAR20-1):0] VAR17;
output reg [(VAR30-1):0] VAR2;
output reg [(VAR30/8-1):0] VAR11;
input wire VAR24;
input wire VAR19;
input wire [(VAR30-1):0] VAR16;
input wire VAR1;
generate
if (VAR31 != 0)
begin
reg VAR15, VAR3, VAR25, VAR21;
reg [(VAR20-1):0] VAR10;
reg [(VAR30-1):0] VAR32;
reg [(VAR30/8-1):0] VAR14;
VAR8 VAR29 = 1'b0;
VAR8 VAR25= 1'b0;
VAR8 VAR15 = 1'b0;
always @(posedge VAR22)
begin
VAR29 <= (VAR9);
if (!VAR19)
begin
VAR3 <= VAR4;
VAR10 <= VAR26;
VAR32 <= VAR28;
VAR14 <= VAR5;
if (VAR15)
begin
VAR13 <= VAR3;
VAR17 <= VAR10;
VAR2 <= VAR32;
VAR11 <= VAR14;
VAR7 <= 1'b1;
end else begin
VAR13 <= VAR4;
VAR17 <= VAR26;
VAR2 <= VAR28;
VAR11 <= VAR5;
VAR7 <= VAR23;
end
VAR15 <= 1'b0;
end else if (!VAR7)
begin
VAR13 <= VAR4;
VAR17 <= VAR26;
VAR2 <= VAR28;
VAR11 <= VAR5;
VAR7 <= VAR23;
end else if ((!VAR15)&&(!VAR18))
begin
VAR3 <= VAR4;
VAR10 <= VAR26;
VAR32 <= VAR28;
VAR14 <= VAR5;
VAR15 <= VAR23;
end
if (!VAR9)
begin
VAR7 <= 1'b0;
VAR15 <= 1'b0;
end
VAR27 <= (VAR24)&&(VAR9)&&(VAR29);
VAR6 <= VAR16;
VAR21 <= (VAR1)&&(VAR9)&&(VAR29);
end
assign VAR18 = VAR15;
assign VAR12 = VAR21;
end else begin
VAR8 VAR29 = 1'b0;
VAR8 VAR7 = 1'b0;
always @(posedge VAR22)
VAR29 <= VAR9;
always @(posedge VAR22)
if (!VAR18)
VAR7 <= ((VAR9)&&(VAR23));
always @(posedge VAR22)
if (!VAR18)
VAR13 <= VAR4;
always @(posedge VAR22)
if (!VAR18)
VAR17<= VAR26;
always @(posedge VAR22)
if (!VAR18)
VAR2 <= VAR28;
always @(posedge VAR22)
if (!VAR18)
VAR11 <= VAR5;
always @(posedge VAR22)
VAR27 <= (VAR24)&&(VAR29)&&(VAR9);
always @(posedge VAR22)
VAR6 <= VAR16;
assign VAR18 = ((VAR19)&&(VAR7)); assign VAR12 = VAR1;
end endgenerate
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai.behavioral.v | 1,530 | module MODULE1 (
VAR5 ,
VAR9,
VAR10,
VAR3
);
output VAR5 ;
input VAR9;
input VAR10;
input VAR3;
supply1 VAR13;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR4 ;
wire VAR11 ;
wire VAR12;
or VAR1 (VAR11 , VAR10, VAR9 );
nand VAR8 (VAR12, VAR3, VAR11 );
buf VAR2 (VAR5 , VAR12 );
endmodule | apache-2.0 |
P3Stor/P3Stor | pcie/IP core/gc_command_fifo.v | 13,466 | module MODULE1(
clk,
rst,
din,
VAR20,
VAR152,
dout,
VAR258,
VAR305,
VAR392,
VAR285
);
input clk;
input rst;
input [28 : 0] din;
input VAR20;
input VAR152;
output [28 : 0] dout;
output VAR258;
output VAR305;
output [4 : 0] VAR392;
output VAR285;
VAR23 #(
.VAR95(0),
.VAR174(0),
.VAR220(0),
.VAR4(0),
.VAR102(0),
.VAR58(0),
.VAR3(0),
.VAR106(32),
.VAR197(1),
.VAR321(1),
.VAR337(1),
.VAR248(64),
.VAR99(4),
.VAR21(1),
.VAR301(0),
.VAR325(1),
.VAR62(64),
.VAR185(4),
.VAR299(8),
.VAR22(4),
.VAR211(4),
.VAR29(4),
.VAR91(0),
.VAR252(1),
.VAR394(0),
.VAR100(5),
.VAR159("VAR94"),
.VAR114(29),
.VAR363(1),
.VAR393(32),
.VAR2(64),
.VAR282(32),
.VAR196(64),
.VAR27(2),
.VAR85("0"),
.VAR187(29),
.VAR351(0),
.VAR215(1),
.VAR370(0),
.VAR316(0),
.VAR283(0),
.VAR101(0),
.VAR345(0),
.VAR54(0),
.VAR158(0),
.VAR362("VAR138"),
.VAR367(1),
.VAR33(0),
.VAR18(0),
.VAR155(0),
.VAR143(0),
.VAR384(0),
.VAR330(0),
.VAR50(0),
.VAR173(0),
.VAR47(0),
.VAR249(0),
.VAR317(0),
.VAR123(0),
.VAR151(0),
.VAR391(0),
.VAR126(1),
.VAR25(0),
.VAR346(0),
.VAR74(0),
.VAR309(1),
.VAR358(0),
.VAR184(0),
.VAR170(0),
.VAR120(0),
.VAR336(0),
.VAR108(0),
.VAR297(0),
.VAR267(0),
.VAR61(0),
.VAR41(0),
.VAR98(0),
.VAR234(0),
.VAR293(0),
.VAR89(0),
.VAR251(0),
.VAR400(0),
.VAR44(0),
.VAR375(0),
.VAR207(1),
.VAR191(0),
.VAR245(0),
.VAR203(0),
.VAR53(0),
.VAR169(0),
.VAR277(0),
.VAR238(0),
.VAR34(0),
.VAR349(1),
.VAR190(1),
.VAR79(1),
.VAR181(1),
.VAR127(1),
.VAR307(1),
.VAR36(0),
.VAR386(0),
.VAR183(2),
.VAR272("VAR94"),
.VAR261(1),
.VAR212(0),
.VAR80(0),
.VAR115(0),
.VAR228(1),
.VAR290("512x36"),
.VAR217(4),
.VAR135(1022),
.VAR281(1022),
.VAR208(1022),
.VAR356(1022),
.VAR81(1022),
.VAR278(1022),
.VAR364(5),
.VAR280(0),
.VAR15(5),
.VAR304(5),
.VAR223(5),
.VAR385(5),
.VAR209(5),
.VAR311(5),
.VAR214(5),
.VAR412(1023),
.VAR202(1023),
.VAR250(1023),
.VAR254(1023),
.VAR72(1023),
.VAR239(1023),
.VAR11(4),
.VAR145(1),
.VAR125(5),
.VAR320(5),
.VAR315(5),
.VAR28(5),
.VAR139(5),
.VAR339(5),
.VAR140(0),
.VAR188(5),
.VAR256(16),
.VAR402(1),
.VAR318(4),
.VAR69(0),
.VAR368(0),
.VAR371(0),
.VAR64(0),
.VAR313(0),
.VAR129(0),
.VAR5(0),
.VAR241(2),
.VAR350(0),
.VAR162(0),
.VAR195(0),
.VAR96(0),
.VAR93(1),
.VAR113(0),
.VAR355(0),
.VAR230(0),
.VAR353(0),
.VAR31(0),
.VAR88(0),
.VAR257(0),
.VAR229(0),
.VAR67(0),
.VAR289(1),
.VAR26(0),
.VAR292(0),
.VAR109(0),
.VAR388(0),
.VAR186(5),
.VAR73(16),
.VAR35(1024),
.VAR1(16),
.VAR319(1024),
.VAR369(16),
.VAR167(1024),
.VAR8(16),
.VAR377(1),
.VAR84(4),
.VAR242(10),
.VAR268(4),
.VAR219(10),
.VAR104(4),
.VAR180(10),
.VAR210(4),
.VAR348(1),
.VAR221(0)
)
VAR354 (
.VAR329(clk),
.VAR136(rst),
.VAR308(din),
.VAR182(VAR20),
.VAR260(VAR152),
.VAR107(dout),
.VAR265(VAR258),
.VAR409(VAR305),
.VAR303(VAR392),
.VAR60(VAR285),
.VAR177(),
.VAR110(),
.VAR194(),
.VAR357(),
.VAR90(),
.VAR273(),
.VAR324(),
.VAR399(),
.VAR179(),
.VAR269(),
.VAR296(),
.VAR243(),
.VAR401(),
.VAR302(),
.VAR408(),
.VAR189(),
.VAR198(),
.VAR373(),
.VAR37(),
.VAR30(),
.VAR70(),
.VAR118(),
.VAR328(),
.VAR157(),
.VAR341(),
.VAR105(),
.VAR361(),
.VAR49(),
.VAR322(),
.VAR116(),
.VAR279(),
.VAR178(),
.VAR46(),
.VAR83(),
.VAR240(),
.VAR134(),
.VAR253(),
.VAR78(),
.VAR271(),
.VAR192(),
.VAR415(),
.VAR77(),
.VAR144(),
.VAR32(),
.VAR19(),
.VAR48(),
.VAR7(),
.VAR343(),
.VAR366(),
.VAR9(),
.VAR338(),
.VAR246(),
.VAR63(),
.VAR133(),
.VAR406(),
.VAR13(),
.VAR68(),
.VAR121(),
.VAR262(),
.VAR340(),
.VAR300(),
.VAR56(),
.VAR237(),
.VAR111(),
.VAR172(),
.VAR326(),
.VAR270(),
.VAR410(),
.VAR122(),
.VAR39(),
.VAR359(),
.VAR40(),
.VAR389(),
.VAR86(),
.VAR291(),
.VAR103(),
.VAR142(),
.VAR153(),
.VAR10(),
.VAR235(),
.VAR45(),
.VAR218(),
.VAR327(),
.VAR232(),
.VAR141(),
.VAR411(),
.VAR347(),
.VAR382(),
.VAR166(),
.VAR224(),
.VAR381(),
.VAR92(),
.VAR137(),
.VAR365(),
.VAR310(),
.VAR82(),
.VAR332(),
.VAR43(),
.VAR295(),
.VAR397(),
.VAR119(),
.VAR165(),
.VAR413(),
.VAR148(),
.VAR42(),
.VAR17(),
.VAR193(),
.VAR213(),
.VAR342(),
.VAR87(),
.VAR132(),
.VAR275(),
.VAR55(),
.VAR247(),
.VAR414(),
.VAR97(),
.VAR6(),
.VAR24(),
.VAR263(),
.VAR227(),
.VAR255(),
.VAR160(),
.VAR286(),
.VAR395(),
.VAR117(),
.VAR404(),
.VAR383(),
.VAR405(),
.VAR284(),
.VAR344(),
.VAR146(),
.VAR407(),
.VAR288(),
.VAR201(),
.VAR294(),
.VAR66(),
.VAR226(),
.VAR200(),
.VAR130(),
.VAR128(),
.VAR131(),
.VAR199(),
.VAR403(),
.VAR75(),
.VAR398(),
.VAR266(),
.VAR274(),
.VAR206(),
.VAR390(),
.VAR335(),
.VAR298(),
.VAR14(),
.VAR168(),
.VAR204(),
.VAR205(),
.VAR59(),
.VAR333(),
.VAR378(),
.VAR161(),
.VAR334(),
.VAR154(),
.VAR12(),
.VAR233(),
.VAR176(),
.VAR16(),
.VAR150(),
.VAR276(),
.VAR231(),
.VAR175(),
.VAR171(),
.VAR396(),
.VAR222(),
.VAR57(),
.VAR216(),
.VAR149(),
.VAR38(),
.VAR379(),
.VAR331(),
.VAR387(),
.VAR323(),
.VAR374(),
.VAR360(),
.VAR76(),
.VAR244(),
.VAR287(),
.VAR236(),
.VAR259(),
.VAR65(),
.VAR52(),
.VAR51(),
.VAR376(),
.VAR124(),
.VAR380(),
.VAR112(),
.VAR352(),
.VAR306(),
.VAR156(),
.VAR372(),
.VAR71(),
.VAR147(),
.VAR164(),
.VAR163(),
.VAR264(),
.VAR225(),
.VAR314(),
.VAR312()
);
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.behavioral.v | 1,098 | module MODULE1( VAR3, VAR2 );
input VAR3;
output VAR2;
VAR4 VAR5(.VAR3(VAR3),.VAR2(VAR2));
VAR4 VAR1(.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.functional.v | 1,838 | module MODULE1( VAR3, VAR19, VAR8, VAR7, VAR1, VAR17, VAR2 );
input VAR1, VAR17, VAR2, VAR8, VAR19, VAR3;
output VAR7;
wire VAR12;
not VAR14( VAR12, VAR1 );
wire VAR18;
not VAR23( VAR18, VAR17 );
wire VAR24;
not VAR5( VAR24, VAR2 );
wire VAR20;
and VAR4( VAR20, VAR12, VAR18, VAR24 );
wire VAR10;
not VAR9( VAR10, VAR8 );
wire VAR16;
not VAR21( VAR16, VAR19 );
wire VAR15;
not VAR22( VAR15, VAR3 );
wire VAR6;
and VAR13( VAR6, VAR10, VAR16, VAR15 );
or VAR11( VAR7, VAR20, VAR6 );
endmodule | apache-2.0 |
sirchuckalot/zet | cores/speaker/wm8731/speaker_i2c_controller.v | 4,169 | module MODULE1 (
VAR12,
VAR2, VAR13, VAR10, VAR5, VAR9, VAR14, VAR4, VAR1
);
input VAR12;
input [23:0]VAR10;
input VAR5;
input VAR1;
input VAR14;
inout VAR13;
output VAR2;
output VAR9;
output VAR4;
reg VAR17;
reg VAR3;
reg VAR9;
reg [23:0]VAR7;
reg [5:0]VAR11;
wire VAR2=VAR3 | ( ((VAR11 >= 4) & (VAR11 <=30))? ~VAR12 :1'b0 );
wire VAR13=VAR17?1'VAR15:1'b0 ;
reg VAR6,VAR8,VAR16;
wire VAR4=VAR6 | VAR8 |VAR16;
always @(posedge VAR12)begin
if (VAR1)
VAR11 <= 6'b111111;
end
else
begin
if (!VAR5)
VAR11 <= 6'd0;
end
else
if (VAR11 < 6'b111111) VAR11 <= VAR11 + 6'b1;
end
end
always @(posedge VAR12)
begin
if (VAR1)
begin
VAR3 <= 1'b1;
VAR17 <= 1'b1;
VAR6 <= 1'b0;
VAR8 <= 1'b0;
VAR16 <= 1'b0;
VAR9 <= 1'b1;
end
else
case (VAR11)
6'd0:
begin
VAR6 <= 1'b0;
VAR8 <= 1'b0;
VAR16 <= 1'b0;
VAR9 <= 1'b0;
VAR17 <= 1'b1;
VAR3 <= 1'b1;
end
6'd1:
begin
VAR7 <= VAR10;
VAR17 <= 1'b0;
end
6'd2: VAR3 <= 1'b0;
6'd3: VAR17 <= VAR7[23];
6'd4 : VAR17<=VAR7[22];
6'd5 : VAR17<=VAR7[21];
6'd6 : VAR17<=VAR7[20];
6'd7 : VAR17<=VAR7[19];
6'd8 : VAR17<=VAR7[18];
6'd9 : VAR17<=VAR7[17];
6'd10 : VAR17<=VAR7[16];
6'd11 : VAR17<=1'b1;
6'd12 : begin VAR17<=VAR7[15]; VAR6<=VAR13; end
6'd13 : VAR17<=VAR7[14];
6'd14 : VAR17<=VAR7[13];
6'd15 : VAR17<=VAR7[12];
6'd16 : VAR17<=VAR7[11];
6'd17 : VAR17<=VAR7[10];
6'd18 : VAR17<=VAR7[9];
6'd19 : VAR17<=VAR7[8];
6'd20 : VAR17<=1'b1;
6'd21 : begin VAR17<=VAR7[7]; VAR8<=VAR13; end
6'd22 : VAR17<=VAR7[6];
6'd23 : VAR17<=VAR7[5];
6'd24 : VAR17<=VAR7[4];
6'd25 : VAR17<=VAR7[3];
6'd26 : VAR17<=VAR7[2];
6'd27 : VAR17<=VAR7[1];
6'd28 : VAR17<=VAR7[0];
6'd29 : VAR17<=1'b1;
6'd30 : begin VAR17<=1'b0; VAR3<=1'b0; VAR16<=VAR13; end
6'd31 : VAR3<=1'b1;
6'd32 : begin VAR17<=1'b1; VAR9<=1; end
endcase
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrbp/sky130_fd_sc_hs__dfrbp.symbol.v | 1,387 | module MODULE1 (
input VAR3 ,
output VAR4 ,
output VAR2 ,
input VAR6,
input VAR5
);
supply1 VAR1;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.v | 2,463 | module MODULE2 (
VAR6 ,
VAR10,
VAR7,
VAR1 ,
VAR3 ,
VAR5,
VAR4,
VAR9 ,
VAR8
);
output VAR6 ;
input VAR10;
input VAR7;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR4;
input VAR9 ;
input VAR8 ;
VAR11 VAR2 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR6 ,
VAR10,
VAR7,
VAR1 ,
VAR3
);
output VAR6 ;
input VAR10;
input VAR7;
input VAR1 ;
input VAR3 ;
supply1 VAR5;
supply0 VAR4;
supply1 VAR9 ;
supply0 VAR8 ;
VAR11 VAR2 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/swrvr_clib.v | 21,511 | module MODULE5 (din, clk, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= din[VAR25-1:0] ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= (VAR13) ? VAR16[VAR25-1:0] : din[VAR25-1:0] ;
assign VAR9[VAR25-1:0] = VAR21[VAR25-1:0] ;
endmodule
module MODULE8 (din, clk, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= (VAR13) ? VAR16[VAR25-1:0] : din[VAR25-1:0] ;
assign VAR9[VAR25-1:0] = VAR21[VAR25-1:0] ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= din[VAR25-1:0] ;
assign VAR9={VAR25{1'b0}};
endmodule
module MODULE7 (din, clk, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= din[VAR25-1:0] ;
endmodule
module MODULE6 (din, clk, rst, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input rst ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= ((rst) ? {VAR25{1'b0}} : din[VAR25-1:0] );
always @ (posedge clk)
VAR21[VAR25-1:0] <= VAR13 ? VAR16[VAR25-1:0] : ((rst) ? {VAR25{1'b0}} : din[VAR25-1:0] );
assign VAR9[VAR25-1:0] = VAR21[VAR25-1:0] ;
endmodule
module MODULE14 (din, clk, VAR2, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input VAR2 ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= VAR2 ? din[VAR25-1:0] : {VAR25{1'b0}};
always @ (posedge clk)
VAR21[VAR25-1:0] <= VAR2 ? ((VAR13) ? VAR16[VAR25-1:0] : din[VAR25-1:0] ) : {VAR25{1'b0}};
assign VAR9[VAR25-1:0] = VAR21[VAR25-1:0] ;
endmodule
module MODULE22 (din, clk, rst, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input rst ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= rst ? {VAR25{1'b0}} : din[VAR25-1:0];
endmodule
module MODULE28 (din, clk, VAR2, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input VAR2 ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= VAR2 ? din[VAR25-1:0] : {VAR25{1'b0}};
endmodule
module MODULE12 (din, en, clk, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input en ; input clk ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= ((en) ? din[VAR25-1:0] : VAR21[VAR25-1:0]) ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= (VAR13) ? VAR16[VAR25-1:0] : ((en) ? din[VAR25-1:0] : VAR21[VAR25-1:0]) ;
assign VAR9[VAR25-1:0] = VAR21[VAR25-1:0] ;
endmodule
module MODULE19 (din, en, clk, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input en ; input clk ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= en ? din[VAR25-1:0] : VAR21[VAR25-1:0];
endmodule
module MODULE17 (din, rst, en, clk, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input en ; input rst ; input clk ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= (rst ? {VAR25{1'b0}} : ((en) ? din[VAR25-1:0] : VAR21[VAR25-1:0])) ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= VAR13 ? VAR16[VAR25-1:0] : (rst ? {VAR25{1'b0}} : ((en) ? din[VAR25-1:0] : VAR21[VAR25-1:0])) ;
assign VAR9[VAR25-1:0] = VAR21[VAR25-1:0] ;
endmodule
module MODULE3 (din, VAR2, en, clk, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input en ; input VAR2 ; input clk ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= (VAR2 ? ((en) ? din[VAR25-1:0] : VAR21[VAR25-1:0]) : {VAR25{1'b0}}) ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= VAR13 ? VAR16[VAR25-1:0] : (VAR2 ? ((en) ? din[VAR25-1:0] : VAR21[VAR25-1:0]) : {VAR25{1'b0}}) ;
assign VAR9[VAR25-1:0] = VAR21[VAR25-1:0] ;
endmodule
module MODULE25 (din, rst, en, clk, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input en ; input rst ; input clk ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= rst ? {VAR25{1'b0}} : ((en) ? din[VAR25-1:0] : VAR21[VAR25-1:0]);
endmodule
module MODULE10 (din, VAR2, en, clk, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input en ; input VAR2 ; input clk ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= VAR2 ? ((en) ? din[VAR25-1:0] : VAR21[VAR25-1:0]) : {VAR25{1'b0}} ;
endmodule
module MODULE16 (din, clk, rst, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input rst ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk or posedge rst)
VAR21[VAR25-1:0] <= rst ? {VAR25{1'b0}} : din[VAR25-1:0];
always @ (posedge clk or posedge rst)
VAR21[VAR25-1:0] <= rst ? {VAR25{1'b0}} : ((VAR13) ? VAR16[VAR25-1:0] : din[VAR25-1:0] );
assign VAR9[VAR25-1:0] = VAR21[VAR25-1:0] ;
endmodule
module MODULE23 (din, clk, VAR2, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input VAR2 ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk or negedge VAR2)
VAR21[VAR25-1:0] <= (!VAR2) ? {VAR25{1'b0}} : din[VAR25-1:0];
always @ (posedge clk or negedge VAR2)
VAR21[VAR25-1:0] <= (!VAR2) ? {VAR25{1'b0}} : ((VAR13) ? VAR16[VAR25-1:0] : din[VAR25-1:0] );
assign VAR9[VAR25-1:0] = VAR21[VAR25-1:0] ;
endmodule
module MODULE9 (din, clk, VAR2, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input VAR2 ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21;
always @ (posedge clk or negedge VAR2)
VAR21[VAR25-1:0] <= ~VAR2 ? {VAR25{1'b0}} : ({VAR25{VAR2}} & din[VAR25-1:0]);
endmodule
module MODULE1 (dout, VAR7, VAR20, VAR22, VAR11) ;
parameter VAR25 = 1;
output [VAR25-1:0] dout;
input [VAR25-1:0] VAR7;
input [VAR25-1:0] VAR20;
input VAR22;
input VAR11;
reg [VAR25-1:0] dout ;
constraint VAR14 (VAR10 ({VAR11,VAR22}));
wire [1:0] sel = {VAR11, VAR22};
always @ (VAR22 or VAR11 or VAR7 or VAR20)
case ({VAR11,VAR22}) 2'b01 : dout = VAR7 ;
2'b10 : dout = VAR20 ;
2'b11 : dout = {VAR25{1'VAR8}} ;
2'b00 : dout = {VAR25{1'VAR8}} ;
default : dout = {VAR25{1'VAR8}};
endcase
endmodule
module MODULE21 (dout, VAR7, VAR20, VAR23, VAR22, VAR11, VAR12) ;
parameter VAR25 = 1;
output [VAR25-1:0] dout;
input [VAR25-1:0] VAR7;
input [VAR25-1:0] VAR20;
input [VAR25-1:0] VAR23;
input VAR22;
input VAR11;
input VAR12;
reg [VAR25-1:0] dout ;
constraint VAR6 (VAR10 ({VAR12,VAR11,VAR22}));
wire [2:0] sel = {VAR12,VAR11,VAR22};
always @ (VAR22 or VAR11 or VAR12 or VAR7 or VAR20 or VAR23)
case ({VAR12,VAR11,VAR22})
3'b001 : dout = VAR7 ;
3'b010 : dout = VAR20 ;
3'b100 : dout = VAR23 ;
3'b000 : dout = {VAR25{1'VAR8}} ;
3'b011 : dout = {VAR25{1'VAR8}} ;
3'b101 : dout = {VAR25{1'VAR8}} ;
3'b110 : dout = {VAR25{1'VAR8}} ;
3'b111 : dout = {VAR25{1'VAR8}} ;
default : dout = {VAR25{1'VAR8}};
endcase
endmodule
module MODULE2 (dout, VAR7, VAR20, VAR23, VAR26, VAR22, VAR11, VAR12, VAR4) ;
parameter VAR25 = 1;
output [VAR25-1:0] dout;
input [VAR25-1:0] VAR7;
input [VAR25-1:0] VAR20;
input [VAR25-1:0] VAR23;
input [VAR25-1:0] VAR26;
input VAR22;
input VAR11;
input VAR12;
input VAR4;
reg [VAR25-1:0] dout ;
constraint VAR17 (VAR10 ({VAR4,VAR12,VAR11,VAR22}));
wire [3:0] sel = {VAR4,VAR12,VAR11,VAR22};
always @ (VAR22 or VAR11 or VAR12 or VAR4 or VAR7 or VAR20 or VAR23 or VAR26)
case ({VAR4,VAR12,VAR11,VAR22})
4'b0001 : dout = VAR7 ;
4'b0010 : dout = VAR20 ;
4'b0100 : dout = VAR23 ;
4'b1000 : dout = VAR26 ;
4'b0000 : dout = {VAR25{1'VAR8}} ;
4'b0011 : dout = {VAR25{1'VAR8}} ;
4'b0101 : dout = {VAR25{1'VAR8}} ;
4'b0110 : dout = {VAR25{1'VAR8}} ;
4'b0111 : dout = {VAR25{1'VAR8}} ;
4'b1001 : dout = {VAR25{1'VAR8}} ;
4'b1010 : dout = {VAR25{1'VAR8}} ;
4'b1011 : dout = {VAR25{1'VAR8}} ;
4'b1100 : dout = {VAR25{1'VAR8}} ;
4'b1101 : dout = {VAR25{1'VAR8}} ;
4'b1110 : dout = {VAR25{1'VAR8}} ;
4'b1111 : dout = {VAR25{1'VAR8}} ;
default : dout = {VAR25{1'VAR8}};
endcase
endmodule
module MODULE11 (in);
parameter VAR25 = 1;
input [VAR25-1:0] in;
wire VAR3;
assign VAR3 = | in;
endmodule
module MODULE15 (out) ;
parameter VAR25 = 1;
output [VAR25-1:0] out;
assign out = {VAR25{1'b0}};
endmodule
module MODULE24 (clk, VAR5, VAR19, VAR1);
output clk;
input VAR5, VAR19, VAR1;
reg VAR15;
always @ (VAR5 or VAR19 or VAR1)
if (!VAR5) VAR15 = !VAR19 | !VAR1;
assign clk = VAR15 & VAR5;
endmodule
module MODULE27 (din, clk, VAR24, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input VAR24 ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= VAR24 ? din[VAR25-1:0] : {VAR25{1'b1}};
endmodule
module MODULE13 (din, clk, VAR24, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input VAR24 ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk or negedge VAR24)
VAR21[VAR25-1:0] <= ~VAR24 ? {VAR25{1'b1}} : ({VAR25{~VAR24}} | din[VAR25-1:0]);
endmodule
module MODULE26 (din, clk, rst, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input rst ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= rst ? {VAR25{1'b1}} : din[VAR25-1:0];
endmodule
module MODULE4 (din, clk, rst, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input rst;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk or posedge rst)
VAR21[VAR25-1:0] <= rst ? {VAR25{1'b0}} : din[VAR25-1:0];
endmodule
module MODULE20 (din, clk, rst, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ; input rst;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk or posedge rst)
VAR21[VAR25-1:0] <= rst ? {VAR25{1'b1}} : din[VAR25-1:0];
endmodule
module MODULE18 (din, VAR18, rst, VAR21);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input VAR18 ; input rst ;
output [VAR25-1:0] VAR21 ;
reg [VAR25-1:0] VAR21 ;
always @ (negedge VAR18 or posedge rst)
VAR21[VAR25-1:0] <= rst ? {VAR25{1'b1}} : din[VAR25-1:0];
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111o/sky130_fd_sc_ls__a2111o.functional.pp.v | 2,070 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR9 ,
VAR13 ,
VAR7 ,
VAR11 ,
VAR1,
VAR16,
VAR18 ,
VAR12
);
output VAR3 ;
input VAR8 ;
input VAR9 ;
input VAR13 ;
input VAR7 ;
input VAR11 ;
input VAR1;
input VAR16;
input VAR18 ;
input VAR12 ;
wire VAR15 ;
wire VAR4 ;
wire VAR10;
and VAR6 (VAR15 , VAR8, VAR9 );
or VAR5 (VAR4 , VAR7, VAR13, VAR15, VAR11 );
VAR2 VAR17 (VAR10, VAR4, VAR1, VAR16);
buf VAR14 (VAR3 , VAR10 );
endmodule | apache-2.0 |
jmacneal/Design-Project | Display/Audio_Controller/Altera_UP_Audio_Bit_Counter.v | 3,924 | module MODULE1 (
clk,
reset,
VAR6,
VAR1,
VAR8,
VAR3,
VAR4
);
parameter VAR5 = 5'd31;
input clk;
input reset;
input VAR6;
input VAR1;
input VAR8;
input VAR3;
output reg VAR4;
wire VAR2;
reg [4:0] VAR7;
always @(posedge clk)
begin
if (reset == 1'b1)
VAR7 <= 5'h00;
end
else if (VAR2 == 1'b1)
VAR7 <= VAR5;
else if ((VAR1 == 1'b1) && (VAR7 != 5'h00))
VAR7 <= VAR7 - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR4 <= 1'b0;
end
else if (VAR2 == 1'b1)
VAR4 <= 1'b1;
else if ((VAR1 == 1'b1) && (VAR7 == 5'h00))
VAR4 <= 1'b0;
end
assign VAR2 = VAR8 |
VAR3;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp.behavioral.pp.v | 1,788 | module MODULE1 (
VAR14 ,
VAR5 ,
VAR11 ,
VAR3,
VAR9,
VAR10 ,
VAR8
);
output VAR14 ;
input VAR5 ;
input VAR11 ;
input VAR3;
input VAR9;
input VAR10 ;
input VAR8 ;
wire VAR15 ;
reg VAR4 ;
wire VAR7 ;
wire VAR1;
wire VAR2 ;
VAR13 VAR12 (VAR15 , VAR7, VAR1, VAR4, VAR3, VAR9);
assign VAR2 = ( VAR3 === 1'b1 );
buf VAR6 (VAR14 , VAR15 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.v | 2,329 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR2 ,
VAR4,
VAR10 ,
VAR8 ,
VAR7 ,
VAR1
);
output VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR4;
input VAR10 ;
input VAR8 ;
input VAR7 ;
input VAR1 ;
VAR9 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR6 ,
VAR5 ,
VAR2 ,
VAR4
);
output VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR4;
supply1 VAR10;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR1 ;
VAR9 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/atr_controller16.v | 2,660 | module MODULE1
(input VAR2, input VAR7,
input [5:0] VAR15, input [1:0] VAR19, input [15:0] VAR14, output [15:0] VAR11,
input VAR17, input VAR5, input VAR16, output reg VAR13,
input VAR6, input VAR8,
output [31:0] VAR4);
reg [3:0] state;
reg [31:0] VAR1 [0:15];
wire [3:0] VAR12 = { (VAR19[1] & VAR15[1]), (VAR19[0] & VAR15[1]),
(VAR19[1] & ~VAR15[1]), (VAR19[0] & ~VAR15[1]) };
always @(posedge VAR2)
if(VAR17 & VAR5 & VAR16)
begin
if(VAR12[3])
VAR1[VAR15[5:2]][31:24] <= VAR14[15:8];
if(VAR12[2])
VAR1[VAR15[5:2]][23:16] <= VAR14[7:0];
if(VAR12[1])
VAR1[VAR15[5:2]][15:8] <= VAR14[15:8];
if(VAR12[0])
VAR1[VAR15[5:2]][7:0] <= VAR14[7:0];
end
assign VAR11 = 16'd0;
always @(posedge VAR2)
VAR13 <= VAR5 & VAR16 & ~VAR13;
assign VAR4 = VAR1[state];
localparam VAR9 = 4'd0;
localparam VAR10 = 4'd1;
localparam VAR3 = 4'd2;
localparam VAR18 = 4'd3;
always @(posedge VAR2)
if(VAR7)
state <= VAR9;
else
case ({VAR6,VAR8})
2'b00 : state <= VAR9;
2'b01 : state <= VAR10;
2'b10 : state <= VAR3;
2'b11 : state <= VAR18;
endcase
endmodule | gpl-2.0 |
nyaxt/dmix | mpemu.v | 2,155 | module MODULE2(
input wire clk,
input wire [23:0] VAR2,
input wire [23:0] VAR3,
output wire [27:0] VAR10);
VAR6 VAR6(
.clk(clk),
.VAR17(VAR2),
.VAR4(VAR3),
.VAR9(VAR10));
reg [23:0] VAR1[4:0];
reg [23:0] VAR7[4:0];
always @(posedge clk) begin
VAR1[0] <= VAR2;
VAR1[1] <= VAR1[0];
VAR1[2] <= VAR1[1];
VAR1[3] <= VAR1[2];
VAR1[4] <= VAR1[3];
VAR7[0] <= VAR3;
VAR7[1] <= VAR7[0];
VAR7[2] <= VAR7[1];
VAR7[3] <= VAR7[2];
VAR7[4] <= VAR7[3];
end
wire [23:0] VAR8 = VAR1[4];
wire [23:0] VAR5 = VAR7[4];
wire [46:0] VAR12 = (VAR8) * (VAR5);
assign VAR10 = VAR12[46:19];
endmodule
module MODULE1(
input wire clk,
input wire [23:0] VAR2,
input wire [31:0] VAR13,
output wire [31:0] VAR10);
VAR11 VAR11(
.clk(clk),
.VAR17(VAR2),
.VAR4(VAR13),
.VAR9(VAR10));
reg [23:0] VAR1[6:0];
reg [31:0] VAR7[6:0];
always @(posedge clk) begin
VAR1[0] <= VAR2;
VAR1[1] <= VAR1[0];
VAR1[2] <= VAR1[1];
VAR1[3] <= VAR1[2];
VAR1[4] <= VAR1[3];
VAR1[5] <= VAR1[4];
VAR1[6] <= VAR1[5];
VAR7[0] <= VAR13;
VAR7[1] <= VAR7[0];
VAR7[2] <= VAR7[1];
VAR7[3] <= VAR7[2];
VAR7[4] <= VAR7[3];
VAR7[5] <= VAR7[4];
VAR7[6] <= VAR7[5];
end
wire [23:0] VAR8 = VAR1[5];
wire [31:0] VAR5 = VAR7[5];
wire signed [32:0] VAR15 = {1'b0, VAR7[5]};
wire [23:0] VAR14 = VAR1[6];
wire [31:0] VAR16 = VAR7[6];
wire signed [55:0] VAR12 = (VAR8) * (VAR15);
assign VAR10 = VAR12[55:24];
endmodule | mit |
lynxis/lpc_sniffer | top.v | 3,052 | module MODULE1 #(parameter VAR60 = 33000000, parameter VAR1 = 921600)
(
input [3:0] VAR59,
input VAR36,
input VAR11,
input VAR40,
input VAR68,
input VAR15,
input VAR61,
output VAR52,
output VAR31,
output VAR51,
output VAR35,
output VAR26,
output VAR65,
output VAR21);
wire reset;
wire [3:0] VAR59;
wire [3:0] VAR23;
wire [31:0] VAR20;
wire [7:0] VAR38;
wire VAR33;
wire [47:0] VAR6;
wire [47:0] VAR70;
wire VAR67;
wire VAR7;
wire VAR17;
wire VAR10;
wire VAR69;
wire [47:0] VAR27;
wire VAR62;
wire [7:0] VAR22;
wire VAR3;
wire VAR53;
wire VAR64;
wire VAR48;
wire VAR14;
wire VAR43;
VAR49 VAR32(.VAR66(VAR68),
.VAR5(VAR14),
.VAR39(VAR43));
VAR19 VAR63(
.VAR43(VAR43),
.VAR30(VAR14),
.reset(reset));
VAR16 VAR55(
.VAR59(VAR59),
.VAR36(VAR36),
.VAR11(VAR11),
.VAR40(VAR48),
.reset(reset),
.VAR34(VAR23),
.VAR45(VAR20),
.VAR24(VAR38),
.VAR9(VAR33),
.VAR42(VAR67));
VAR2 #(.VAR29(48))
VAR44(
.VAR12(VAR6),
.VAR25(VAR67),
.reset(reset),
.VAR30(VAR14),
.VAR13(VAR70),
.VAR8(VAR17));
assign VAR6[47:16] = VAR20;
assign VAR6[15:8] = VAR38;
assign VAR6[7:5] = 0;
assign VAR6[4] = VAR33;
assign VAR6[3:0] = VAR23;
VAR41 #(.VAR29(10), .VAR37(48))
VAR56 (
.reset(reset),
.VAR30(VAR14),
.VAR17(VAR17),
.VAR7(VAR7),
.VAR27(VAR27),
.VAR70(VAR70),
.VAR10(VAR10),
.VAR69(VAR69));
VAR47 VAR58(
.reset(reset),
.VAR30(VAR14),
.VAR50(VAR10),
.VAR7(VAR7),
.VAR27(VAR27),
.VAR3(VAR3),
.VAR62(VAR62),
.VAR22(VAR22));
wire [1:0] state;
VAR46 VAR57 (
.VAR27(VAR22),
.VAR7(VAR3),
.reset(reset),
.ready(VAR62),
.VAR52(VAR52),
.VAR15(VAR15),
.state(state),
.VAR30(VAR14));
assign VAR31 = VAR14;
VAR18 VAR54(
.reset(reset),
.VAR30(VAR14),
.VAR4(VAR65),
.VAR28(VAR64));
assign VAR64 = VAR23 == 4'b0100;
assign VAR51 = 0;
assign VAR35 = 0;
assign VAR26 = 1;
assign VAR48 = 1;
assign VAR21 = VAR69;
endmodule | gpl-3.0 |
Fairyland0902/BlockyRoads | src/BlockyRoads/x7segbc.v | 3,227 | module MODULE1(
input wire clk,
input wire [31:0] VAR1,
output reg [ 6:0] VAR2,
output reg [ 7:0] VAR6,
output wire VAR8
);
wire [ 2:0] VAR5;
reg [ 4:0] VAR4;
wire [ 7:0] VAR7;
reg [19:0] VAR3;
assign VAR8 = 1;
assign VAR5 = VAR3[19:17];
assign VAR7[7] = VAR1[31] | VAR1[30] | VAR1[29] | VAR1[28];
assign VAR7[6] = VAR1[31] | VAR1[30] | VAR1[29] | VAR1[28] |
VAR1[27] | VAR1[26] | VAR1[25] | VAR1[24];
assign VAR7[5] = VAR1[31] | VAR1[30] | VAR1[29] | VAR1[28] |
VAR1[27] | VAR1[26] | VAR1[25] | VAR1[24] |
VAR1[23] | VAR1[22] | VAR1[21] | VAR1[20];
assign VAR7[4] = VAR1[31] | VAR1[30] | VAR1[29] | VAR1[28] |
VAR1[27] | VAR1[26] | VAR1[25] | VAR1[24] |
VAR1[23] | VAR1[22] | VAR1[21] | VAR1[20] |
VAR1[19] | VAR1[18] | VAR1[17] | VAR1[16];
assign VAR7[3] = VAR1[31] | VAR1[30] | VAR1[29] | VAR1[28] |
VAR1[27] | VAR1[26] | VAR1[25] | VAR1[24] |
VAR1[23] | VAR1[22] | VAR1[21] | VAR1[20] |
VAR1[19] | VAR1[18] | VAR1[17] | VAR1[16] |
VAR1[15] | VAR1[14] | VAR1[13] | VAR1[12];
assign VAR7[2] = VAR1[31] | VAR1[30] | VAR1[29] | VAR1[28] |
VAR1[27] | VAR1[26] | VAR1[25] | VAR1[24] |
VAR1[23] | VAR1[22] | VAR1[21] | VAR1[20] |
VAR1[19] | VAR1[18] | VAR1[17] | VAR1[16] |
VAR1[15] | VAR1[14] | VAR1[13] | VAR1[12] |
VAR1[11] | VAR1[10] | VAR1[ 9] | VAR1[ 8];
assign VAR7[1] = VAR1[31] | VAR1[30] | VAR1[29] | VAR1[28] |
VAR1[27] | VAR1[26] | VAR1[25] | VAR1[24] |
VAR1[23] | VAR1[22] | VAR1[21] | VAR1[20] |
VAR1[19] | VAR1[18] | VAR1[17] | VAR1[16] |
VAR1[15] | VAR1[14] | VAR1[13] | VAR1[12] |
VAR1[11] | VAR1[10] | VAR1[ 9] | VAR1[ 8] |
VAR1[ 7] | VAR1[ 6] | VAR1[ 5] | VAR1[ 4];
assign VAR7[0] = 1;
always @*
case (VAR5)
0: VAR4 = {1'b0, VAR1[ 3: 0]};
1: VAR4 = {1'b0, VAR1[ 7: 4]};
2: VAR4 = {1'b0, VAR1[11: 8]};
3: VAR4 = {1'b0, VAR1[15:12]};
4: VAR4 = 5'b10000;
5: VAR4 = 5'b10001;
6: VAR4 = 5'b10010;
7: VAR4 = 5'b10011;
default: VAR4 = {1'b0, VAR1[ 3: 0]};
endcase
always @*
case (VAR4)
0: VAR2 = 7'b1000000;
1: VAR2 = 7'b1111001;
2: VAR2 = 7'b0100100;
3: VAR2 = 7'b0110000;
4: VAR2 = 7'b0011001;
5: VAR2 = 7'b0010010;
6: VAR2 = 7'b0000010;
7: VAR2 = 7'b1111000;
8: VAR2 = 7'b0000000;
9: VAR2 = 7'b0010000;
'hA: VAR2 = 7'b0001000;
'hB: VAR2 = 7'b0000011;
'hC: VAR2 = 7'b1000110;
'hD: VAR2 = 7'b0100001;
'hE: VAR2 = 7'b0000110;
'hF: VAR2 = 7'b0001110;
'h10: VAR2 = 7'b0001011; 'h11: VAR2 = 7'b0010000; 'h12: VAR2 = 7'b1111001; 'h13: VAR2 = 7'b0001001; endcase
always @*
begin
VAR6 = 8'b11111111;
if (VAR7[VAR5] == 1)
VAR6[VAR5] = 0;
end
always @ (posedge clk)
begin
VAR3 <= VAR3 + 1;
end
endmodule | mit |
chebykinn/university | circuitry/lab3/src/hdl/mem_stage.v | 1,805 | module MODULE1 (
input clk,
input rst,
input VAR7,
input VAR18,
input [31:0] VAR8,
input [31:0] VAR12,
input [4:0] VAR4,
input VAR11,
input VAR9,
input VAR16,
output reg [4:0] VAR2,
output reg VAR17,
output reg VAR1,
output reg [31:0] VAR15,
output reg [31:0] VAR6,
output VAR5,
output VAR14,
output [31:0] VAR13,
output [31:0] VAR10,
input [31:0] VAR3
);
assign VAR5 = VAR7;
assign VAR14 = VAR18;
assign VAR13 = VAR8;
assign VAR10 = VAR12;
always @(posedge clk) begin
if (rst)
begin
VAR2 <= 0;
VAR17 <= 0;
VAR1 <= 0;
VAR15 <= 0;
VAR6 <= 0;
end
else
begin
VAR2 <= VAR4;
VAR17 <= VAR11;
VAR1 <= VAR9;
VAR15 <= VAR3;
VAR6 <= VAR8;
end
end
endmodule | mit |
esonghori/TinyGarbled | circuit_synthesis/mips/Bus_Mux.v | 2,209 | module MODULE1
(
VAR15,
VAR10,
VAR12,
VAR9,
VAR2,
VAR5,
VAR6,
VAR11,
VAR4,
VAR3,
VAR8,
VAR14,
VAR13,
VAR7,
VAR1
);
input [15:0] VAR15;
input [31:0] VAR10;
input [1:0] VAR12;
output [31:0] VAR9;
reg [31:0] VAR9;
input [31:0] VAR2;
input [1:0] VAR5;
output [31:0] VAR6;
reg [31:0] VAR6;
input [31:0] VAR11;
input [31:0] VAR4;
input [31:2] VAR3;
input [31:2] VAR8;
input [2:0] VAR14;
output [31:0] VAR13;
reg [31:0] VAR13;
input [2:0] VAR7;
output VAR1;
reg VAR1;
always@(*)
begin
VAR9<=32'b0;
VAR6<=32'b0;
VAR13<=32'b0;
VAR1<=0;
case(VAR12)
VAR9<=VAR10;
VAR9<={27'b0,VAR15[10:6]};
VAR9<={VAR3,2'b0};
default:
VAR9<=32'b0;
endcase
case(VAR5)
VAR6<=VAR2;
VAR6<={16'b0,VAR15};
VAR6<={{16{VAR15[15]}},VAR15};
VAR6<={14'b0,VAR15,2'b0};
default:
VAR6<=32'b0;
endcase
case(VAR14)
VAR13<=32'b0;
VAR13<=VAR11;
VAR13<=VAR11;
VAR13<=VAR11;
VAR13<=VAR4;
VAR13<={VAR3,2'b0};
VAR13<={VAR8,2'b0};
VAR13<={VAR15,16'b0};
VAR13<=VAR10;
default:
VAR13<=32'b0;
endcase
case(VAR7)
VAR1<=(VAR11[31])?1:0;
VAR1<=(VAR11[31])?1:(VAR11==32'b0)?1:0;
VAR1<=(VAR11==32'b0)?1:0;
VAR1<=(VAR11==32'b0)?0:1;
VAR1<=(VAR11[31])?0:1;
VAR1<=(VAR11[31])?0:(VAR11==32'b0)?0:1;
VAR1<=1;
VAR1<=0;
default:
VAR1<=0;
endcase
end
endmodule | gpl-3.0 |
jbelloncastro/amber_arm | hw/vlog/system/uart.v | 36,620 | module MODULE1 #(
parameter VAR70 = 32,
parameter VAR104 = 4
)(
input VAR21,
input [31:0] VAR55,
input [VAR104-1:0] VAR125,
input VAR102,
output [VAR70-1:0] VAR68,
input [VAR70-1:0] VAR82,
input VAR38,
input VAR7,
output VAR73,
output VAR44,
output VAR119,
input VAR72, output VAR30, output VAR48, input VAR18
);
localparam [3:0] VAR77 = 4'd0,
VAR25 = 4'd1,
VAR33 = 4'd2,
VAR98 = 4'd3,
VAR84 = 4'd4,
VAR3 = 4'd5,
VAR78 = 4'd6,
VAR26 = 4'd7,
VAR85 = 4'd8,
VAR17 = 4'd9,
VAR34 = 4'd10,
VAR43 = 4'd11,
VAR93 = 4'd12;
localparam [3:0] VAR99 = 4'd0,
VAR86 = 4'd1,
VAR60 = 4'd2,
VAR15 = 4'd3,
VAR19 = 4'd4,
VAR88 = 4'd5,
VAR63 = 4'd6,
VAR56 = 4'd7,
VAR65 = 4'd8,
VAR22 = 4'd9,
VAR53 = 4'd10,
VAR115 = 4'd11,
VAR69 = 4'd12;
localparam VAR83 = 24'h3fffff;
localparam real VAR16 = VAR111;
localparam real VAR118 = 1200.0 / VAR120 ; else
localparam real VAR118 = 800.0 / VAR120 ; VAR9
localparam real VAR97 = 1000000000 / VAR16; localparam real VAR114 = ( VAR97 * 12 ); localparam real VAR1 = 1000 / VAR118; localparam real VAR31 = VAR114 / VAR1;
localparam real VAR41 = VAR31 / 12;
localparam [9:0] VAR101 = VAR41;
localparam [9:0] VAR100 = VAR31;
localparam [9:0] VAR101 = 30;
localparam [9:0] VAR100 = 360;
localparam [9:0] VAR126 = VAR100 - 11*VAR101;
localparam [9:0] VAR42 = VAR101-2;
localparam [9:0] VAR8 = VAR101/2 - 4;
reg VAR123 = 'd0;
reg VAR80 = 'd0;
reg [23:0] VAR49 = 'd0;
wire VAR108;
reg [7:0] VAR79 [0:15];
wire VAR75;
wire VAR122;
wire VAR110;
wire VAR6;
wire VAR81;
wire VAR76;
reg [4:0] VAR94 = 'd0;
reg [4:0] VAR95 = 'd0;
reg [4:0] VAR14 = 'd0; reg VAR71 = 'd0;
reg [7:0] VAR52 [0:15];
reg VAR40 = 1'd1;
reg VAR109 = 1'd0;
wire VAR66; reg [4:0] VAR35 = 'd0; wire VAR128;
wire VAR57;
wire VAR87;
wire VAR39;
reg [4:0] VAR90 = 'd0;
reg [4:0] VAR124 = 'd0;
wire [7:0] VAR37;
reg [3:0] VAR11 = VAR77;
reg VAR89 = 1'd1;
reg VAR24 = 'd0;
reg [9:0] VAR116 = 'd0;
reg [7:0] VAR107 = 'd0;
reg [3:0] VAR2 = VAR99;
wire VAR59;
reg VAR10 = 'd0;
reg [9:0] VAR92 = 'd0;
reg VAR23 = 'd0;
reg [4:0] VAR96 = 5'h1f;
reg [3:0] VAR62 = 4'hf;
reg [7:0] VAR106 = 'd0; reg [7:0] VAR105 = 'd0; reg [7:0] VAR29 = 'd0; reg [7:0] VAR5 = 'd0; reg [7:0] VAR58 = 'd0;
reg [31:0] VAR54 = 'd0;
wire VAR113;
wire VAR36;
reg VAR103 = 'd0;
wire [31:0] VAR51;
integer VAR28;
assign VAR113 = VAR7 && VAR102 && !VAR103;
assign VAR36 = VAR7 && !VAR102 && !VAR73;
always @( posedge VAR21 )
VAR103 <= VAR36;
assign VAR44 = 1'd0;
assign VAR73 = VAR7 && ( VAR113 || VAR103 );
generate
if (VAR70 == 128)
begin : VAR45
assign VAR51 = VAR55[3:2] == 2'd3 ? VAR82[127:96] :
VAR55[3:2] == 2'd2 ? VAR82[ 95:64] :
VAR55[3:2] == 2'd1 ? VAR82[ 63:32] :
VAR82[ 31: 0] ;
assign VAR68 = {4{VAR54}};
end
else
begin : VAR46
assign VAR51 = VAR82;
assign VAR68 = VAR54;
end
endgenerate
assign VAR87 = VAR36 && VAR55[15:0] == VAR47;
assign VAR57 = VAR128 && !VAR109;
assign VAR39 = VAR87 && !VAR40;
assign VAR66 = VAR35 >= 5'd8;
always @ ( posedge VAR21 )
begin
if ( VAR108 )
begin
if ( VAR57 )
begin
VAR52[VAR90[3:0]] <= VAR107;
VAR90 <= VAR90 + 1'd1;
end
if ( VAR39 )
begin
VAR124 <= VAR124 + 1'd1;
end
if ( VAR57 && !VAR39 )
VAR35 <= VAR35 + 1'd1;
end
else if ( VAR39 && !VAR57 )
VAR35 <= VAR35 - 1'd1;
VAR109 <= VAR90 == {~VAR124[4], VAR124[3:0]};
VAR40 <= VAR90 == VAR124;
if ( VAR40 || VAR87 )
VAR49 <= 'd0;
end
else if ( VAR49 != VAR83 )
VAR49 <= VAR49 + 1'd1;
end
else begin
VAR49 <= 'd0;
if ( VAR128 )
begin
VAR52[0] <= VAR107;
VAR40 <= 1'd0;
VAR109 <= 1'd1;
end
else if ( VAR87 )
begin
VAR40 <= 1'd1;
VAR109 <= 1'd0;
end
end
end
always @ ( posedge VAR21 )
begin
if ( VAR113 && VAR55[15:0] == VAR4 )
VAR123 <= 1'd0;
end
else if ( VAR108 )
VAR123 <= VAR110 && VAR58[5];
else
VAR123 <= VAR122 && VAR58[5];
end
always @ ( posedge VAR21 )
if (VAR108)
VAR80 <= VAR66 || VAR49 == VAR83;
else
VAR80 <= VAR109;
assign VAR119 = ( VAR123 & VAR58[5] ) | ( VAR80 & VAR58[4] ) ;
assign VAR108 = VAR105[4];
assign VAR30 = VAR89;
assign VAR75 = VAR108 ? VAR14 >= 5'd16 : VAR71;
assign VAR122 = VAR108 ? VAR14 == 5'd00 : !VAR71;
assign VAR110 = VAR14 <= 5'd8;
assign VAR37 = VAR108 ? VAR79[VAR95[3:0]] : VAR79[0] ;
assign VAR6 = VAR113 && VAR55[15:0] == VAR47;
assign VAR81 = VAR6 && !VAR75;
assign VAR76 = VAR11 == VAR93 && VAR24 == 1'd1 && !VAR122;
always @( posedge VAR21 )
begin
if ( VAR108 )
begin
if ( VAR81 )
begin
VAR79[VAR94[3:0]] <= VAR51[7:0];
VAR94 <= VAR94 + 1'd1;
end
if ( VAR76 )
VAR95 <= VAR95 + 1'd1;
if (VAR81 && !VAR76)
VAR14 <= VAR14 + 1'd1;
end
else if (VAR76 && !VAR81)
VAR14 <= VAR14 - 1'd1;
end
else
begin
VAR94 <= 'd0;
VAR95 <= 'd0;
VAR14 <= 'd0;
if ( VAR81 )
begin
VAR79[0] <= VAR51[7:0];
VAR71 <= 1'd1;
end
else if ( VAR76 )
VAR71 <= 1'd0;
end
end
always @( posedge VAR21 )
VAR62 <= {VAR62[2:0], VAR72};
always @( posedge VAR21 )
if (( VAR116 == (VAR126-1) && VAR11 == VAR43 ) ||
( VAR116 == (VAR101-1) && VAR11 != VAR43 ) )
begin
VAR116 <= 'd0;
VAR24 <= 1'd1;
end
else
begin
VAR116 <= VAR116 + 1'd1;
VAR24 <= 1'd0;
end
always @( posedge VAR21 )
if ( VAR24 )
case ( VAR11 )
VAR77 :
begin
VAR89 <= 1'd1;
if ( VAR62[3:1] == 3'b000 && !VAR122 )
VAR11 <= VAR25;
end
VAR25 :
begin
VAR89 <= 1'd0;
VAR11 <= VAR33;
end
VAR33 :
begin
VAR89 <= VAR37[0];
VAR11 <= VAR98;
end
VAR98 :
begin
VAR89 <= VAR37[1];
VAR11 <= VAR84;
end
VAR84 :
begin
VAR89 <= VAR37[2];
VAR11 <= VAR3;
end
VAR3 :
begin
VAR89 <= VAR37[3];
VAR11 <= VAR78;
end
VAR78 :
begin
VAR89 <= VAR37[4];
VAR11 <= VAR26;
end
VAR26 :
begin
VAR89 <= VAR37[5];
VAR11 <= VAR85;
end
VAR85 :
begin
VAR89 <= VAR37[6];
VAR11 <= VAR17;
end
VAR17 :
begin
VAR89 <= VAR37[7];
VAR11 <= VAR34;
end
VAR34 :
begin
VAR89 <= 1'd1;
VAR11 <= VAR43;
end
VAR43 :
begin
VAR89 <= 1'd1;
VAR11 <= VAR93;
end
VAR93 :
begin
VAR89 <= 1'd1;
VAR11 <= VAR77;
end
default :
begin
VAR89 <= 1'd1;
end
endcase
assign VAR48 = ~VAR10;
assign VAR128 = VAR2 == VAR69 && VAR92 == 10'd0;
always @( posedge VAR21 )
if ( VAR23 )
VAR92 <= 'd0;
else
VAR92 <= VAR92 + 1'd1;
always @( posedge VAR21 )
VAR96[4:0] <= {VAR96[3:0], VAR18};
assign VAR59 = VAR96[4:3] == 2'b11 && VAR96[1:0] == 2'b00;
always @( posedge VAR21 )
case ( VAR2 )
VAR99 :
if ( VAR109 )
VAR10 <= 1'd0;
else
begin
VAR2 <= VAR86;
VAR10 <= 1'd1;
VAR23 <= 1'd1;
VAR107 <= 'd0;
end
VAR86 :
if ( VAR59 )
begin
VAR2 <= VAR15;
VAR23 <= 1'd1;
end
else
VAR23 <= 1'd0;
VAR15 :
VAR2 <= VAR60;
VAR60 :
if ( VAR92 == VAR8 )
begin
VAR2 <= VAR19;
VAR23 <= 1'd1;
end
else
VAR23 <= 1'd0;
VAR19 :
if ( VAR92 == VAR42 )
begin
VAR2 <= VAR88;
VAR23 <= 1'd1;
VAR107[0] <= VAR18;
end
else
VAR23 <= 1'd0;
VAR88 :
if ( VAR92 == VAR42 )
begin
VAR2 <= VAR63;
VAR23 <= 1'd1;
VAR107[1] <= VAR18;
end
else
VAR23 <= 1'd0;
VAR63 :
if ( VAR92 == VAR42 )
begin
VAR2 <= VAR56;
VAR23 <= 1'd1;
VAR107[2] <= VAR18;
end
else
VAR23 <= 1'd0;
VAR56 :
if ( VAR92 == VAR42 )
begin
VAR2 <= VAR65;
VAR23 <= 1'd1;
VAR107[3] <= VAR18;
end
else
VAR23 <= 1'd0;
VAR65 :
if ( VAR92 == VAR42 )
begin
VAR2 <= VAR22;
VAR23 <= 1'd1;
VAR107[4] <= VAR18;
end
else
VAR23 <= 1'd0;
VAR22 :
if ( VAR92 == VAR42 )
begin
VAR2 <= VAR53;
VAR23 <= 1'd1;
VAR107[5] <= VAR18;
end
else
VAR23 <= 1'd0;
VAR53 :
if ( VAR92 == VAR42 )
begin
VAR2 <= VAR115;
VAR23 <= 1'd1;
VAR107[6] <= VAR18;
end
else
VAR23 <= 1'd0;
VAR115 :
if ( VAR92 == VAR42 )
begin
VAR2 <= VAR69;
VAR23 <= 1'd1;
VAR107[7] <= VAR18;
end
else
VAR23 <= 1'd0;
VAR69 :
if ( VAR92 == VAR42 ) begin
VAR2 <= VAR99;
VAR23 <= 1'd1;
end
else
VAR23 <= 1'd0;
default :
begin
VAR2 <= VAR99;
end
endcase
always @( posedge VAR21 )
if ( VAR113 )
case ( VAR55[15:0] )
VAR32: VAR106 <= VAR51[7:0];
VAR112: VAR105 <= VAR51[7:0];
VAR50: VAR29 <= VAR51[7:0];
VAR74: VAR5 <= VAR51[7:0];
VAR127: VAR58 <= VAR51[7:0];
endcase
always @( posedge VAR21 )
if ( VAR36 )
case ( VAR55[15:0] )
VAR121: VAR54 <= 32'h0d;
VAR12: VAR54 <= 32'hf0;
VAR64: VAR54 <= 32'h05;
VAR117: VAR54 <= 32'hb1;
VAR61: VAR54 <= 32'h10;
VAR20: VAR54 <= 32'h10;
VAR27: VAR54 <= 32'h04;
VAR67: VAR54 <= 32'h00;
VAR47: if ( VAR108 )
VAR54 <= {24'd0, VAR52[VAR124[3:0]]};
else
VAR54 <= {24'd0, VAR52[0]};
VAR32: VAR54 <= VAR106; VAR112: VAR54 <= VAR105; VAR50: VAR54 <= VAR29; VAR74: VAR54 <= VAR5; VAR127: VAR54 <= VAR58;
VAR13: VAR54 <= {VAR122, VAR109, VAR75, VAR40, !VAR122, 1'd1, 1'd1, !VAR62[3] };
VAR91: VAR54 <= {5'd0,
1'd0, VAR123, VAR80, 1'd0 };
default: VAR54 <= 32'h00c0ffee;
endcase
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin | lgpl-3.0 |
peteasa/oh | src/common/hdl/oh_iddr.v | 1,317 | module MODULE1 #(parameter VAR2 = 1 )
(
input clk, input VAR5, input [VAR2-1:0] din, output reg [VAR2-1:0] VAR1, output reg [VAR2-1:0] VAR4 );
reg [VAR2-1:0] VAR6;
reg [VAR2-1:0] VAR3;
always @ (posedge clk)
if(VAR5)
VAR6[VAR2-1:0] <= din[VAR2-1:0];
always @ (negedge clk)
VAR3[VAR2-1:0] <= din[VAR2-1:0];
always @ (posedge clk)
begin
VAR1[VAR2-1:0] <= VAR6[VAR2-1:0];
VAR4[VAR2-1:0] <= VAR3[VAR2-1:0];
end
endmodule | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/ACA_II_N16_Q4_syn.v | 2,977 | module MODULE1 ( VAR76, VAR4, VAR67 );
input [15:0] VAR76;
input [15:0] VAR4;
output [16:0] VAR67;
wire VAR72, VAR50, VAR14, VAR52, VAR73, VAR25, VAR70, VAR13, VAR63, VAR71, VAR51, VAR53, VAR23, VAR47,
VAR16, VAR24, VAR22, VAR84, VAR75, VAR3, VAR54, VAR69, VAR9, VAR36, VAR41, VAR7, VAR48;
VAR18 VAR66 ( .VAR46(VAR4[7]), .VAR32(VAR76[7]), .VAR44(VAR4[6]), .VAR82(VAR76[6]), .VAR85(VAR52)
);
VAR18 VAR79 ( .VAR46(VAR4[9]), .VAR32(VAR76[9]), .VAR44(VAR4[8]), .VAR82(VAR76[8]), .VAR85(VAR70)
);
VAR18 VAR59 ( .VAR46(VAR4[11]), .VAR32(VAR76[11]), .VAR44(VAR4[10]), .VAR82(VAR76[10]), .VAR85(
VAR23) );
VAR62 VAR68 ( .VAR43(VAR76[0]), .VAR60(VAR4[0]), .VAR85(VAR9) );
VAR10 VAR5 ( .VAR43(VAR76[3]), .VAR60(VAR4[3]), .VAR85(VAR24) );
VAR10 VAR81 ( .VAR43(VAR76[5]), .VAR60(VAR4[5]), .VAR85(VAR51) );
VAR10 VAR86 ( .VAR43(VAR76[7]), .VAR60(VAR4[7]), .VAR85(VAR50) );
VAR10 VAR31 ( .VAR43(VAR76[9]), .VAR60(VAR4[9]), .VAR85(VAR73) );
VAR10 VAR40 ( .VAR43(VAR76[11]), .VAR60(VAR4[11]), .VAR85(VAR13) );
VAR10 VAR42 ( .VAR43(VAR76[13]), .VAR60(VAR4[13]), .VAR85(VAR47) );
VAR18 VAR33 ( .VAR46(VAR4[13]), .VAR32(VAR76[13]), .VAR44(VAR4[12]), .VAR82(VAR76[12]), .VAR85(
VAR41) );
VAR18 VAR19 ( .VAR46(VAR4[3]), .VAR32(VAR76[3]), .VAR44(VAR4[2]), .VAR82(VAR76[2]), .VAR85(VAR71)
);
VAR18 VAR80 ( .VAR46(VAR4[5]), .VAR32(VAR76[5]), .VAR44(VAR4[4]), .VAR82(VAR76[4]), .VAR85(VAR72)
);
VAR83 VAR15 ( .VAR57(VAR76[0]), .VAR55(VAR4[0]), .VAR44(VAR9), .VAR85(VAR67[0]) );
VAR17 VAR65 ( .VAR57(VAR76[5]), .VAR55(VAR4[5]), .VAR44(VAR72), .VAR85(VAR54) );
VAR10 VAR56 ( .VAR43(VAR14), .VAR60(VAR50), .VAR85(VAR67[7]) );
VAR17 VAR27 ( .VAR57(VAR76[7]), .VAR55(VAR4[7]), .VAR44(VAR52), .VAR85(VAR3) );
VAR10 VAR49 ( .VAR43(VAR25), .VAR60(VAR73), .VAR85(VAR67[9]) );
VAR17 VAR20 ( .VAR57(VAR76[9]), .VAR55(VAR4[9]), .VAR44(VAR70), .VAR85(VAR75) );
VAR10 VAR64 ( .VAR43(VAR63), .VAR60(VAR13), .VAR85(VAR67[11]) );
VAR17 VAR6 ( .VAR57(VAR76[3]), .VAR55(VAR4[3]), .VAR44(VAR71), .VAR85(VAR69) );
VAR10 VAR26 ( .VAR43(VAR53), .VAR60(VAR51), .VAR85(VAR67[5]) );
VAR17 VAR58 ( .VAR57(VAR76[11]), .VAR55(VAR4[11]), .VAR44(VAR23), .VAR85(VAR84) );
VAR10 VAR78 ( .VAR43(VAR16), .VAR60(VAR47), .VAR85(VAR67[13]) );
VAR10 VAR30 ( .VAR43(VAR22), .VAR60(VAR24), .VAR85(VAR67[3]) );
VAR2 VAR74 ( .VAR43(VAR4[12]), .VAR60(VAR76[12]), .VAR77(VAR84), .VAR29(VAR16), .VAR28(VAR67[12]) );
VAR2 VAR1 ( .VAR43(VAR76[10]), .VAR60(VAR4[10]), .VAR77(VAR75), .VAR29(VAR63), .VAR28(VAR67[10]) );
VAR2 VAR8 ( .VAR43(VAR76[8]), .VAR60(VAR4[8]), .VAR77(VAR3), .VAR29(VAR25), .VAR28(VAR67[8]) );
VAR2 VAR12 ( .VAR43(VAR76[6]), .VAR60(VAR4[6]), .VAR77(VAR54), .VAR29(VAR14), .VAR28(VAR67[6]) );
VAR2 VAR45 ( .VAR43(VAR76[4]), .VAR60(VAR4[4]), .VAR77(VAR69), .VAR29(VAR53), .VAR28(VAR67[4]) );
VAR2 VAR35 ( .VAR43(VAR76[1]), .VAR60(VAR4[1]), .VAR77(VAR9), .VAR29(VAR36), .VAR28(VAR67[1]) );
VAR2 VAR38 ( .VAR43(VAR76[2]), .VAR60(VAR4[2]), .VAR77(VAR36), .VAR29(VAR22), .VAR28(VAR67[2]) );
VAR17 VAR37 ( .VAR57(VAR76[13]), .VAR55(VAR4[13]), .VAR44(VAR41), .VAR85(VAR7) );
VAR2 VAR11 ( .VAR43(VAR76[14]), .VAR60(VAR4[14]), .VAR77(VAR7), .VAR29(VAR48), .VAR28(VAR67[14]) );
VAR2 VAR34 ( .VAR43(VAR76[15]), .VAR60(VAR4[15]), .VAR77(VAR48), .VAR29(VAR67[16]), .VAR28(VAR67[15]) );
VAR39 ("VAR21.VAR61");
endmodule | gpl-3.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,581 | module MODULE1 (
clk,
reset,
VAR2,
VAR1,
VAR4,
VAR13,
VAR10,
VAR7
);
parameter VAR12 = 1;
parameter VAR11 = 8;
parameter VAR5 = 1;
localparam VAR16 = VAR12 * VAR11;
input clk;
input reset;
output VAR2;
input VAR1;
input [VAR16-1:0] VAR4;
input VAR13;
output VAR10;
output [VAR16-1:0] VAR7;
reg VAR6;
reg VAR8;
reg [VAR16-1:0] VAR3;
reg [VAR16-1:0] VAR15;
assign VAR10 = VAR8;
assign VAR7 = VAR15;
generate if (VAR5 == 1)
begin : VAR9
assign VAR2 = !VAR6;
always @(posedge clk, posedge reset) begin
if (reset) begin
VAR3 <= {VAR16{1'b0}};
VAR15 <= {VAR16{1'b0}};
end else begin
if (~VAR6)
VAR3 <= VAR4;
if (~VAR8 || (VAR13 && VAR10)) begin
if (VAR6)
VAR15 <= VAR3;
end
else
VAR15 <= VAR4;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR6 <= 1'b0;
VAR8 <= 1'b0;
end else begin
if (~VAR6 & ~VAR8) begin
if (VAR1) begin
VAR8 <= 1'b1;
end
end
if (VAR8 & ~VAR6) begin
if (VAR1 & ~VAR13) begin
VAR6 <= 1'b1;
end
if (~VAR1 & VAR13) begin
VAR8 <= 1'b0;
end
end
if (VAR8 & VAR6) begin
if (VAR13) begin
VAR6 <= 1'b0;
end
end end
end
end
else
begin : VAR14
assign VAR2 = (~VAR8) | VAR13;
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR15 <= 'b0;
VAR8 <= 1'b0;
end
else begin
if (VAR2) begin
VAR15 <= VAR4;
VAR8 <= VAR1;
end
end
end
end
endgenerate
endmodule | gpl-2.0 |
marmolejo/zet | cores/csrbrg/rtl/csrbrg.v | 1,941 | module MODULE1(
input VAR4,
input VAR11,
input [3:1] VAR6,
input [15:0] VAR15,
output reg [15:0] VAR1,
input VAR7,
input VAR2,
input VAR3,
output reg VAR14,
output reg [2:0] VAR13,
output reg VAR17,
output reg [15:0] VAR8,
input [15:0] VAR12
);
always @(posedge VAR4) begin
VAR1 <= VAR12;
end
reg VAR5;
always @(posedge VAR4) begin
VAR13 <= VAR6[3:1];
VAR17 <= VAR5;
VAR8 <= VAR15;
end
reg [1:0] state;
reg [1:0] VAR18;
parameter VAR16 = 2'd0;
parameter VAR19 = 2'd1;
parameter VAR9 = 2'd2;
parameter VAR10 = 2'd3;
always @(posedge VAR4) begin
if(VAR11)
state <= VAR16;
end
else
state <= VAR18;
end
always @(*) begin
VAR18 = state;
VAR14 = 1'b0;
VAR5 = 1'b0;
case(state)
VAR16: begin
if(VAR7 & VAR2) begin
VAR5 = VAR3;
if(VAR3)
VAR18 = VAR10;
end
else
VAR18 = VAR19;
end
end
VAR19: VAR18 = VAR9;
VAR9: VAR18 = VAR10;
VAR10: begin
VAR14 = 1'b1;
VAR18 = VAR16;
end
endcase
end
endmodule | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/request_arb.v | 29,320 | module MODULE1 (
input VAR59,
input VAR205,
input VAR238,
output VAR109,
input [31:VAR201] VAR98,
input [31:VAR75] VAR202,
input [VAR124-1:0] VAR69,
input VAR212,
input VAR143,
output reg VAR188,
input enable,
input VAR211,
input VAR81,
input VAR99,
input VAR105,
input VAR223,
output [31:0] VAR213,
output [ 7:0] VAR147,
output [ 2:0] VAR134,
output [ 1:0] VAR30,
output [ 2:0] VAR133,
output [ 3:0] VAR274,
output VAR186,
input VAR180,
output [VAR275-1:0] VAR233,
output [(VAR275/8)-1:0] VAR268,
input VAR279,
output VAR254,
output VAR248,
input VAR245,
input [ 1:0] VAR120,
output VAR13,
input VAR123,
output VAR107,
output [31:0] VAR115,
output [ 7:0] VAR44,
output [ 2:0] VAR195,
output [ 1:0] VAR121,
output [ 2:0] VAR144,
output [ 3:0] VAR264,
input [VAR116-1:0] VAR68,
output VAR25,
input VAR277,
input [ 1:0] VAR224,
input VAR177,
output VAR82,
input VAR267,
input [VAR116-1:0] VAR221,
input [0:0] VAR32,
output VAR210,
input VAR50,
input VAR255,
output VAR265,
output [VAR275-1:0] VAR77,
output VAR157,
output VAR40,
input VAR230,
input VAR127,
input [VAR116-1:0] VAR240,
output VAR10,
input VAR103,
output VAR286,
input VAR9,
input VAR36,
output VAR49,
output [VAR275-1:0] VAR117,
output VAR57,
output VAR217,
output [VAR11-1:0] VAR87,
output [VAR11-1:0] VAR111,
output [VAR11-1:0] VAR282,
output [VAR11-1:0] VAR208,
output [VAR11-1:0] VAR29,
output [VAR11-1:0] VAR24,
output [VAR11-1:0] VAR67,
output [VAR11-1:0] VAR281,
output [7:0] VAR63
);
parameter VAR116 = 64;
parameter VAR275 = 64;
parameter VAR124 = 24;
parameter VAR201 = VAR184(VAR275/8);
parameter VAR75 = VAR184(VAR116/8);
parameter VAR150 = VAR22;
parameter VAR285 = VAR175;
parameter VAR161 = 1;
parameter VAR214 = 1;
parameter VAR17 = 1;
parameter VAR152 = 0;
parameter VAR114 = 0;
parameter VAR169 = 128;
parameter VAR148 = 4;
parameter VAR11 = VAR184(VAR148 * 2);
localparam VAR22 = 0;
localparam VAR236 = 1;
localparam VAR175 = 2;
localparam VAR93 = 32 - VAR201;
localparam VAR139 = 32 - VAR75;
localparam VAR153 = VAR116 < VAR275 ?
VAR275 : VAR116;
parameter VAR76 = VAR184(VAR169);
localparam VAR90 = VAR76 - VAR75;
localparam VAR219 = VAR76 - VAR201;
localparam VAR31 = VAR124 - VAR76;
reg [0:2**VAR11-1] VAR108;
wire VAR4;
wire [VAR11-1:0] VAR48;
wire [VAR11-1:0] VAR261;
wire VAR33;
wire VAR249;
wire VAR276;
wire VAR269;
wire VAR137;
wire VAR15;
wire VAR189;
wire VAR80;
wire VAR172;
wire VAR146;
wire VAR118;
wire VAR149;
wire VAR198;
wire VAR258;
wire VAR260;
wire VAR272;
wire VAR54;
wire VAR65;
wire VAR51;
wire VAR247;
wire VAR28;
wire VAR256;
wire VAR270;
wire VAR56;
wire VAR280;
wire [VAR93-1:0] VAR200;
wire [VAR219-1:0] VAR27;
wire [VAR201-1:0] VAR130;
wire VAR106;
wire VAR199;
wire VAR101;
wire VAR232;
wire [1:0] VAR3;
wire VAR244;
wire [VAR11-1:0] VAR225;
wire [VAR11-1:0] VAR160;
wire VAR234;
wire VAR64;
wire [VAR275-1:0] VAR52;
wire VAR246;
wire VAR94;
wire [VAR275-1:0] VAR72;
wire VAR170;
wire VAR1;
wire [VAR153-1:0] VAR173;
wire VAR193;
wire VAR7;
wire VAR12;
wire VAR53;
wire [VAR139-1:0] VAR176;
wire [VAR90-1:0] VAR166;
wire VAR122;
wire VAR206;
wire VAR138;
wire VAR283;
wire [1:0] VAR8;
wire [VAR11-1:0] VAR196;
wire [VAR11-1:0] VAR70;
wire VAR209;
wire VAR23;
wire [VAR116-1:0] VAR74;
wire VAR20;
wire VAR113;
wire [VAR116-1:0] VAR34;
wire VAR235;
wire VAR14;
wire [VAR153-1:0] VAR35;
wire VAR125;
wire VAR119;
wire VAR2;
wire VAR178 = 1'b1;
wire [1:0] VAR263;
wire VAR62;
assign VAR87 = VAR225;
assign VAR208 = VAR160;
assign VAR29 = VAR196;
assign VAR281 = VAR70;
assign VAR276 = ~VAR249 && ~VAR33 && VAR48 != VAR261;
reg VAR179;
reg VAR66;
always @(posedge VAR59)
begin
if (VAR205 == 1'b0) begin
VAR66 <= 1'b0;
end else begin
if (enable) begin
if (~VAR269 && ~VAR137 &&
VAR261 == VAR48 && ~VAR249 && ~VAR33 &&
VAR65 && VAR28 && VAR119)
VAR66 <= 1'b1;
end else begin
VAR66 <= 1'b0;
end
end
end
always @(posedge VAR59)
begin
if (VAR205 == 1'b0) begin
VAR179 <= 1'b0;
end else begin
if (VAR66 == 1'b0)
VAR179 <= 1'b0;
end
else if (VAR249 && VAR33)
VAR179 <= 1'b1;
end
end
assign VAR63 = {VAR66, VAR179, VAR249, VAR33, VAR119,
VAR276, VAR269, VAR137};
always @(posedge VAR59)
begin
VAR108[VAR48] <= VAR4;
end
always @(posedge VAR59)
begin
if (VAR205 == 1'b0) begin
VAR188 <= 1'b0;
end else begin
VAR188 <= VAR2 & VAR178 & VAR62;
end
end
generate if (VAR161) begin
wire VAR185;
if (VAR285 == VAR22) begin
assign VAR185 = VAR223;
end else begin
assign VAR185 = VAR205;
end
reg [2:0] VAR262 = 3'b111;
assign VAR7 = ~VAR262[2];
always @(negedge VAR185 or posedge VAR193) begin
if (VAR185 == 1'b0)
VAR262 <= 3'b111;
end
else
VAR262 <= {VAR262[1:0], 1'b0};
end
end else begin
assign VAR7 = VAR205;
end endgenerate
generate if (VAR17) begin
wire VAR287;
if (VAR150 == VAR22) begin
assign VAR287 = VAR99;
end else begin
assign VAR287 = VAR205;
end
reg [2:0] VAR190 = 3'b111;
assign VAR270 = ~VAR190[2];
always @(negedge VAR287 or posedge VAR256) begin
if (VAR287 == 1'b0)
VAR190 <= 3'b111;
end
else
VAR190 <= {VAR190[1:0], 1'b0};
end
end else begin
assign VAR270 = VAR205;
end endgenerate
generate if (VAR150 == VAR22) begin
assign VAR256 = VAR81;
wire [VAR11-1:0] VAR142;
wire [VAR11-1:0] VAR110;
wire VAR242 = VAR108[VAR110];
wire VAR85 = VAR108[VAR142];
wire VAR154 = VAR108[VAR160];
assign VAR111 = VAR110;
assign VAR282 = VAR142;
VAR167 #(
.VAR11(VAR11),
.VAR229(VAR275),
.VAR164(VAR219),
.VAR89(VAR201)
) VAR84 (
.VAR278(VAR81),
.VAR100(VAR270),
.enable(VAR15),
.VAR179(VAR189),
.VAR211(VAR80),
.VAR238(VAR56),
.VAR109(VAR280),
.VAR141(VAR200),
.VAR86(VAR27),
.VAR126(VAR130),
.VAR187(VAR199),
.VAR16(VAR101),
.VAR151(VAR3),
.VAR5(VAR244),
.VAR48(VAR225),
.VAR261(VAR160),
.VAR276(VAR172),
.VAR78(VAR146),
.VAR168(VAR142),
.VAR91(VAR110),
.VAR181(VAR242),
.VAR218(VAR85),
.VAR95(VAR154),
.VAR26(VAR234),
.VAR289(VAR64),
.VAR284(VAR52),
.VAR180(VAR180),
.VAR186(VAR186),
.VAR213(VAR213),
.VAR147(VAR147),
.VAR134(VAR134),
.VAR30(VAR30),
.VAR133(VAR133),
.VAR274(VAR274),
.VAR279(VAR279),
.VAR254(VAR254),
.VAR233(VAR233),
.VAR268(VAR268),
.VAR248(VAR248),
.VAR245(VAR245),
.VAR120(VAR120),
.VAR13(VAR13)
);
end else begin
assign VAR186 = 1'b0;
assign VAR213 = 'h00;
assign VAR147 = 'h00;
assign VAR134 = 'h00;
assign VAR30 = 'h00;
assign VAR133 = 'h00;
assign VAR274 = 'h00;
assign VAR254 = 1'b0;
assign VAR233 = 'h00;
assign VAR268 = 'h00;
assign VAR248 = 1'b0;
assign VAR13 = 1'b0;
end
if (VAR150 == VAR236) begin
assign VAR256 = VAR50;
wire [VAR11-1:0] VAR168;
wire VAR218 = VAR108[VAR168];
wire VAR95 = VAR108[VAR160];
assign VAR111 = 'h00;
assign VAR282 = VAR168;
VAR158 #(
.VAR11(VAR11),
.VAR37(VAR275),
.VAR164(VAR219)
) VAR192 (
.VAR177(VAR50),
.VAR112(VAR270),
.enable(VAR15),
.VAR179(VAR189),
.VAR238(VAR56),
.VAR109(VAR280),
.VAR86(VAR27),
.VAR212(VAR106),
.VAR187(VAR199),
.VAR16(VAR101),
.VAR151(VAR3),
.VAR5(VAR244),
.VAR48(VAR225),
.VAR261(VAR160),
.VAR168(VAR168),
.VAR276(VAR172),
.VAR78(VAR146),
.VAR19(VAR40),
.VAR218(VAR218),
.VAR95(VAR95),
.VAR26(VAR234),
.VAR289(VAR64),
.VAR284(VAR52),
.VAR265(VAR265),
.VAR255(VAR255),
.VAR77(VAR77),
.VAR157(VAR157)
);
end else begin
assign VAR265 = 1'b0;
assign VAR77 = 'h00;
end
if (VAR150 == VAR175) begin
assign VAR256 = VAR9;
wire [VAR11-1:0] VAR168;
wire VAR218 = VAR108[VAR168];
wire VAR95 = VAR108[VAR160];
assign VAR111 = 'h00;
assign VAR282 = VAR168;
VAR231 #(
.VAR11(VAR11),
.VAR259(VAR275),
.VAR164(VAR219)
) VAR243 (
.clk(VAR9),
.VAR92(VAR270),
.enable(VAR15),
.VAR179(VAR189),
.VAR238(VAR56),
.VAR109(VAR280),
.VAR86(VAR27),
.VAR187(VAR199),
.VAR16(VAR101),
.VAR151(VAR3),
.VAR5(VAR244),
.VAR48(VAR225),
.VAR261(VAR160),
.VAR168(VAR168),
.VAR276(VAR172),
.VAR78(VAR146),
.VAR218(VAR218),
.VAR95(VAR95),
.VAR26(VAR234),
.VAR289(VAR64),
.VAR284(VAR52),
.en(VAR36),
.valid(VAR49),
.dout(VAR117),
.VAR273(VAR57),
.VAR19(VAR217)
);
end else begin
assign VAR49 = 1'b0;
assign VAR117 = 'h0;
assign VAR57 = 1'b0;
end endgenerate
generate if (VAR285 == VAR22) begin
assign VAR193 = VAR105;
wire [VAR11-1:0] VAR174;
wire [VAR11-1:0] VAR241;
wire VAR47 = VAR108[VAR241];
wire VAR155 = VAR108[VAR174];
assign VAR24 = VAR241;
assign VAR67 = VAR174;
VAR220 #(
.VAR11(VAR11),
.VAR229(VAR116),
.VAR164(VAR90),
.VAR89(VAR75)
) VAR162 (
.VAR278(VAR105),
.VAR100(VAR7),
.VAR211(VAR198),
.enable(VAR118),
.VAR179(VAR149),
.VAR276(VAR258),
.VAR78(VAR260),
.VAR238(VAR12),
.VAR109(VAR53),
.VAR141(VAR176),
.VAR86(VAR166),
.VAR187(VAR206),
.VAR16(VAR138),
.VAR151(VAR8),
.VAR48(VAR196),
.VAR261(VAR70),
.VAR91(VAR241),
.VAR168(VAR174),
.VAR181(VAR47),
.VAR218(VAR155),
.VAR26(VAR209),
.VAR289(VAR23),
.VAR284(VAR74),
.VAR123(VAR123),
.VAR107(VAR107),
.VAR115(VAR115),
.VAR44(VAR44),
.VAR195(VAR195),
.VAR121(VAR121),
.VAR144(VAR144),
.VAR264(VAR264),
.VAR25(VAR25),
.VAR277(VAR277),
.VAR68(VAR68),
.VAR224(VAR224)
);
end else begin
assign VAR107 = 1'b0;
assign VAR115 = 'h00;
assign VAR44 = 'h00;
assign VAR195 = 'h00;
assign VAR121 = 'h00;
assign VAR264 = 'h00;
assign VAR144 = 'h00;
assign VAR25 = 1'b0;
end
if (VAR285 == VAR236) begin
assign VAR193 = VAR177;
wire VAR61 = VAR108[VAR70];
assign VAR24 = 'h00;
assign VAR67 = 'h00;
assign VAR206 = 1'b0;
assign VAR8 = 2'b0;
VAR250 #(
.VAR11(VAR11),
.VAR37(VAR116),
.VAR164(VAR90)
) VAR228 (
.VAR177(VAR177),
.VAR112(VAR7),
.enable(VAR118),
.VAR179(VAR149),
.VAR276(VAR258),
.VAR78(VAR260),
.VAR238(VAR12),
.VAR109(VAR53),
.VAR86(VAR166),
.VAR143(VAR122),
.VAR48(VAR196),
.VAR261(VAR70),
.VAR188(VAR61),
.VAR26(VAR209),
.VAR289(VAR23),
.VAR284(VAR74),
.VAR267(VAR267),
.VAR82(VAR82),
.VAR221(VAR221),
.VAR32(VAR32),
.VAR210(VAR210)
);
end else begin
assign VAR82 = 1'b0;
end
if (VAR285 == VAR175) begin
assign VAR193 = VAR230;
wire VAR61 = VAR108[VAR70];
assign VAR24 = 'h00;
assign VAR67 = 'h00;
assign VAR206 = 1'b0;
assign VAR8 = 2'b0;
VAR171 #(
.VAR11(VAR11),
.VAR259(VAR116),
.VAR164(VAR90)
) VAR182 (
.clk(VAR230),
.VAR92(VAR7),
.enable(VAR118),
.VAR179(VAR149),
.VAR276(VAR258),
.VAR78(VAR260),
.VAR238(VAR12),
.VAR109(VAR53),
.VAR86(VAR166),
.VAR143(VAR122),
.VAR48(VAR196),
.VAR261(VAR70),
.VAR188(VAR61),
.VAR26(VAR209),
.VAR289(VAR23),
.VAR284(VAR74),
.en(VAR127),
.din(VAR240),
.VAR207(VAR10),
.sync(VAR103),
.VAR19(VAR286)
);
end else begin
assign VAR10 = 1'b0;
assign VAR286 = 1'b0;
end endgenerate
VAR140 #(
.VAR60(VAR11),
.VAR39(VAR161)
) VAR136 (
.VAR45(VAR193),
.VAR83(VAR7),
.in(VAR48),
.out(VAR196)
);
VAR140 #(
.VAR60(VAR11),
.VAR39(VAR214)
) VAR104 (
.VAR45(VAR256),
.VAR83(VAR270),
.in(VAR70),
.out(VAR225)
);
VAR140 #(
.VAR60(VAR11),
.VAR39(VAR17)
) VAR21 (
.VAR45(VAR59),
.VAR83(VAR205),
.in(VAR160),
.out(VAR261)
);
VAR194 #(
.VAR253(VAR116),
.VAR266(VAR114),
.VAR132(VAR114)
) VAR71 (
.clk(VAR193),
.VAR92(VAR7),
.VAR135(VAR209),
.VAR129(VAR23),
.VAR165(VAR74),
.VAR97(VAR20),
.VAR96(VAR113),
.VAR73(VAR34)
);
VAR191 #(
.VAR163(VAR116),
.VAR183(VAR153)
) VAR159 (
.clk(VAR193),
.VAR92(VAR7 & VAR118),
.VAR145(VAR20),
.VAR88(VAR113),
.VAR252(VAR34),
.VAR18(VAR235),
.VAR222(VAR14),
.VAR271(VAR35)
);
VAR251 #(
.VAR259(VAR153),
.VAR288(VAR184(VAR169 / (VAR153 / 8) * VAR148)),
.VAR203(VAR214)
) VAR41 (
.VAR177(VAR193),
.VAR112(VAR7),
.VAR267(VAR235),
.VAR82(VAR14),
.VAR221(VAR35),
.VAR239(VAR125),
.VAR50(VAR256),
.VAR215(VAR270),
.VAR265(VAR170),
.VAR255(VAR1),
.VAR77(VAR173)
);
VAR191 #(
.VAR163(VAR153),
.VAR183(VAR275)
) VAR257 (
.clk(VAR256),
.VAR92(VAR270 & VAR15),
.VAR145(VAR170),
.VAR88(VAR1),
.VAR252(VAR173),
.VAR18(VAR246),
.VAR222(VAR94),
.VAR271(VAR72)
);
wire VAR234;
wire VAR64;
wire [VAR275-1:0] VAR52;
VAR194 #(
.VAR253(VAR275),
.VAR266(VAR152)
) VAR55 (
.clk(VAR256),
.VAR92(VAR270),
.VAR135(VAR246),
.VAR129(VAR94),
.VAR165(VAR72),
.VAR97(VAR234),
.VAR96(VAR64),
.VAR73(VAR52)
);
VAR194 #(
.VAR253(VAR275),
.VAR266(VAR152),
.VAR132(VAR152)
) VAR58 (
.clk(VAR256),
.VAR92(VAR270),
.VAR135(VAR234),
.VAR129(VAR64),
.VAR165(VAR52),
.VAR97(VAR234),
.VAR96(VAR64),
.VAR73(VAR52)
);
reg VAR238 = 1'b0;
wire VAR109;
always @(posedge VAR59)
begin
if (VAR205 == 1'b0) begin
VAR238 <= 1'b0;
end else begin
if (VAR238 == 1'b1 && VAR109 == 1'b1) begin
VAR238 <= 1'b0;
end else if (VAR238 == 1'b1 && VAR179 == 1'b1) begin
VAR238 <= 1'b1;
end
end
end
assign VAR109 = VAR109 & VAR238 & enable;
VAR6 #(
.VAR43(3)
) VAR79 (
.clk(VAR59),
.VAR92(VAR205),
.VAR145(VAR238),
.VAR88(VAR109),
.VAR18({
VAR42,
VAR272,
VAR51
}),
.VAR222({
VAR128,
VAR54,
VAR247
})
);
VAR251 #(
.VAR259(VAR93 + VAR219 + VAR201 + 1),
.VAR288(0),
.VAR203(VAR17)
) VAR237 (
.VAR177(VAR59),
.VAR112(VAR205),
.VAR267(VAR272),
.VAR82(VAR54),
.VAR239(VAR65),
.VAR221({
VAR98,
VAR69[VAR76-1:VAR201],
VAR69[VAR201-1:0],
VAR212
}),
.VAR50(VAR256),
.VAR215(VAR270),
.VAR265(VAR56),
.VAR255(VAR280),
.VAR77({
VAR200,
VAR27,
VAR130,
VAR106
})
);
VAR251 #(
.VAR259(VAR139 + VAR90 + 1),
.VAR288(0),
.VAR203(VAR161)
) VAR204 (
.VAR177(VAR59),
.VAR112(VAR205),
.VAR267(VAR51),
.VAR82(VAR247),
.VAR239(VAR28),
.VAR221({
VAR202,
VAR69[VAR76-1:VAR75],
VAR143
}),
.VAR50(VAR193),
.VAR215(VAR7),
.VAR265(VAR12),
.VAR255(VAR53),
.VAR77({
VAR176,
VAR166,
VAR122
})
);
VAR251 #(
.VAR259(3),
.VAR288(0),
.VAR203(VAR17)
) VAR227 (
.VAR177(VAR256),
.VAR112(VAR270),
.VAR267(VAR199),
.VAR82(VAR101),
.VAR239(VAR232),
.VAR221(VAR244),
.VAR50(VAR59),
.VAR215(VAR205),
.VAR265(VAR2),
.VAR255(VAR178),
.VAR77(VAR62)
);
assign VAR283 = 1'b1;
assign VAR138 = 1'b1;
VAR102 #(
.VAR11(VAR11),
.VAR226(VAR31)
) VAR46 (
.VAR59(VAR59),
.VAR205(VAR205),
.VAR48(VAR48),
.VAR261(VAR261),
.VAR238(VAR42),
.VAR109(VAR128),
.VAR131(VAR69[VAR124-1:VAR76]),
.enable(VAR66),
.VAR211(VAR211),
.VAR188(VAR4)
);
VAR140 #(
.VAR60(3),
.VAR39(VAR17)
) VAR156 (
.VAR45(VAR256),
.VAR83(VAR270),
.in({VAR66, VAR211, VAR276}),
.out({VAR15, VAR80, VAR172})
);
VAR140 #(
.VAR60(2),
.VAR39(VAR17)
) VAR38 (
.VAR45(VAR59),
.VAR83(VAR205),
.in({VAR189 | ~VAR232, VAR146}),
.out({VAR249, VAR269})
);
VAR140 #(
.VAR60(3),
.VAR39(VAR161)
) VAR197 (
.VAR45(VAR193),
.VAR83(VAR7),
.in({VAR66, VAR211, VAR276}),
.out({VAR118, VAR198, VAR258})
);
VAR140 #(
.VAR60(3),
.VAR39(VAR161)
) VAR216 (
.VAR45(VAR59),
.VAR83(VAR205),
.in({VAR149 | ~VAR283, VAR260, VAR125}),
.out({VAR33, VAR137, VAR119})
);
endmodule | gpl-3.0 |
alexforencich/verilog-ethernet | example/ML605/fpga_sgmii/rtl/fpga.v | 10,653 | module MODULE1 (
input wire VAR17,
input wire VAR157,
input wire reset,
input wire VAR72,
input wire VAR52,
input wire VAR143,
input wire VAR181,
input wire VAR50,
input wire [7:0] VAR177,
output wire VAR88,
output wire VAR28,
output wire VAR165,
output wire VAR5,
output wire VAR111,
output wire [7:0] VAR131,
input wire VAR152,
input wire VAR42,
output wire VAR4,
output wire VAR134,
input wire VAR120,
input wire VAR35,
output wire VAR11,
output wire VAR106,
input wire VAR128,
input wire VAR31,
output wire VAR132
);
wire VAR29;
wire VAR108;
wire VAR66;
wire VAR145;
wire VAR46 = reset;
wire VAR10;
wire VAR67;
VAR8
VAR186(
.VAR61(VAR17),
.VAR100(VAR157),
.VAR135(VAR29)
);
VAR44 #(
.VAR136("VAR184"),
.VAR178(8),
.VAR127(0.5),
.VAR118(0),
.VAR83(1),
.VAR103(0.5),
.VAR112(0),
.VAR102(1),
.VAR160(0.5),
.VAR91(0),
.VAR155(1),
.VAR48(0.5),
.VAR138(0),
.VAR22(1),
.VAR25(0.5),
.VAR173(0),
.VAR192(1),
.VAR37(0.5),
.VAR21(0),
.VAR3(1),
.VAR139(0.5),
.VAR80(0),
.VAR55(5),
.VAR151(0),
.VAR12(1),
.VAR164(0.100),
.VAR117(5.0),
.VAR130("VAR153"),
.VAR57("VAR153")
)
VAR45 (
.VAR30(VAR29),
.VAR68(VAR67),
.VAR58(VAR46),
.VAR87(1'b0),
.VAR126(VAR108),
.VAR9(),
.VAR78(),
.VAR125(),
.VAR77(),
.VAR85(),
.VAR60(),
.VAR89(),
.VAR96(),
.VAR171(),
.VAR26(),
.VAR71(VAR67),
.VAR99(),
.VAR75(VAR10)
);
VAR167
VAR14 (
.VAR61(VAR108),
.VAR135(VAR66)
);
VAR51 #(
.VAR182(4)
)
VAR123 (
.clk(VAR66),
.rst(~VAR10),
.out(VAR145)
);
wire VAR150;
wire VAR113;
wire VAR92;
wire VAR32;
wire VAR162;
wire [7:0] VAR183;
wire VAR180;
wire VAR43;
wire VAR137;
wire VAR148;
wire VAR95;
wire [7:0] VAR34;
wire VAR56;
wire VAR6;
wire VAR64;
wire VAR15;
VAR104 #(
.VAR65(13),
.VAR182(4),
.VAR76(125000)
)
VAR59 (
.clk(VAR66),
.rst(VAR145),
.in({VAR72,
VAR52,
VAR143,
VAR181,
VAR50,
VAR177}),
.out({VAR150,
VAR113,
VAR92,
VAR32,
VAR162,
VAR183})
);
VAR73 #(
.VAR65(2),
.VAR182(2)
)
VAR40 (
.clk(VAR66),
.in({VAR128,
VAR31}),
.out({VAR6,
VAR64})
);
assign VAR88 = VAR180;
assign VAR28 = VAR43;
assign VAR165 = VAR137;
assign VAR5 = VAR148;
assign VAR111 = VAR95;
assign VAR106 = VAR56;
assign VAR132 = VAR15;
wire VAR70;
wire VAR39;
wire VAR172;
wire [7:0] VAR187;
wire VAR53;
wire VAR1;
wire [7:0] VAR149;
wire VAR33;
wire VAR16;
wire VAR133;
wire VAR84;
wire VAR142;
VAR69
VAR27 (
.VAR119 (1'b0),
.VAR61 (VAR120),
.VAR100 (VAR35),
.VAR135 (VAR133),
.VAR97 ()
);
VAR167
VAR175 (
.VAR61 (VAR84),
.VAR135 (VAR142)
);
assign VAR70 = VAR142;
VAR51 #(
.VAR182(4)
)
VAR191 (
.clk(VAR70),
.rst(VAR145),
.out(VAR39)
);
wire [15:0] VAR86;
wire VAR82 = VAR86[0];
wire VAR110 = VAR86[1];
wire VAR24 = VAR86[2];
wire VAR170 = VAR86[3];
wire VAR109 = VAR86[4];
wire VAR116 = VAR86[5];
wire VAR174 = VAR86[6];
wire VAR47 = VAR86[7];
wire [1:0] VAR147 = VAR86[9:8];
wire [1:0] VAR168 = VAR86[11:10];
wire VAR129 = VAR86[12];
wire VAR20 = VAR86[13];
wire [1:0] VAR62 = VAR86[15:14];
wire [4:0] VAR2;
assign VAR2[4] = 1'b1; assign VAR2[3] = 1'b0; assign VAR2[2] = 1'b0; assign VAR2[1] = 1'b0; assign VAR2[0] = 1'b0;
wire [15:0] VAR122;
assign VAR122[15] = 1'b1; assign VAR122[14] = 1'b1; assign VAR122[13:12] = 2'b01; assign VAR122[11:10] = 2'b10; assign VAR122[9] = 1'b0; assign VAR122[8:7] = 2'b00; assign VAR122[6] = 1'b0; assign VAR122[5] = 1'b0; assign VAR122[4:1] = 4'b0000; assign VAR122[0] = 1'b1;
VAR163
VAR159 (
.VAR156 (VAR133),
.VAR19 (VAR66),
.VAR23 (VAR4),
.VAR49 (VAR134),
.VAR93 (VAR152),
.VAR141 (VAR42),
.VAR81 (VAR84),
.VAR98 (VAR142),
.VAR179 (VAR145),
.VAR36 (),
.VAR90 (),
.VAR176 (VAR172),
.VAR146 (VAR187),
.VAR105 (VAR53),
.VAR166 (VAR1),
.VAR54 (VAR149),
.VAR121 (VAR33),
.VAR161 (VAR16),
.VAR38 (),
.VAR189 (VAR2),
.VAR41 (),
.VAR114 (VAR122),
.VAR124 (1'b0),
.VAR158 (9'd50),
.VAR18 (VAR168 != 2'b10),
.VAR13 (VAR168 == 2'b01),
.VAR101 (VAR86),
.reset (VAR145),
.VAR190 (1'b1)
);
assign VAR131 = VAR177[7] ? (VAR177[6] ? VAR86[15:8] : VAR86[7:0]) : VAR34;
VAR74
VAR79 (
.VAR115(VAR66),
.VAR188(VAR145),
.VAR72(VAR150),
.VAR52(VAR113),
.VAR143(VAR92),
.VAR181(VAR32),
.VAR50(VAR162),
.VAR177(VAR183),
.VAR88(VAR180),
.VAR28(VAR43),
.VAR165(VAR137),
.VAR5(VAR148),
.VAR111(VAR95),
.VAR131(VAR34),
.VAR140(VAR70),
.VAR107(VAR39),
.VAR63(VAR172),
.VAR144(VAR149),
.VAR169(VAR33),
.VAR154(VAR16),
.VAR7(VAR187),
.VAR185(VAR53),
.VAR94(VAR1),
.VAR11(VAR11),
.VAR106(VAR56),
.VAR128(VAR6),
.VAR31(VAR64),
.VAR132(VAR15)
);
endmodule | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s0_mult_cell.v | 6,320 | module MODULE1 (
VAR6,
VAR48,
clk,
VAR27,
VAR53
)
;
output [ 31: 0] VAR53;
input [ 31: 0] VAR6;
input [ 31: 0] VAR48;
input clk;
input VAR27;
wire [ 31: 0] VAR53;
wire [ 31: 0] VAR46;
wire [ 15: 0] VAR11;
wire VAR50;
assign VAR50 = ~VAR27;
VAR2 VAR45
(
.VAR37 (VAR50),
.VAR9 (clk),
.VAR56 (VAR6[15 : 0]),
.VAR51 (VAR48[15 : 0]),
.VAR18 (1'b1),
.VAR25 (VAR46)
);
VAR45.VAR31 = "VAR7",
VAR45.VAR28 = "VAR24",
VAR45.VAR14 = "VAR42",
VAR45.VAR1 = "VAR24",
VAR45.VAR30 = "VAR24",
VAR45.VAR4 = "VAR43",
VAR45.VAR29 = "VAR21",
VAR45.VAR36 = "VAR2",
VAR45.VAR23 = "VAR16",
VAR45.VAR19 = "VAR10",
VAR45.VAR8 = "VAR7",
VAR45.VAR41 = 1,
VAR45.VAR22 = "VAR24",
VAR45.VAR12 = "VAR15",
VAR45.VAR33 = "VAR15",
VAR45.VAR40 = "VAR15",
VAR45.VAR44 = "VAR15",
VAR45.VAR39 = "VAR35",
VAR45.VAR13 = "VAR35",
VAR45.VAR32 = "VAR3",
VAR45.VAR17 = "VAR10",
VAR45.VAR49 = "VAR10",
VAR45.VAR47 = "VAR7",
VAR45.VAR54 = "VAR7",
VAR45.VAR5 = "VAR24",
VAR45.VAR20 = "VAR24",
VAR45.VAR52 = 16,
VAR45.VAR34 = 16,
VAR45.VAR55 = 32;
VAR2 VAR26
(
.VAR37 (VAR50),
.VAR9 (clk),
.VAR56 (VAR6[31 : 16]),
.VAR51 (VAR48[15 : 0]),
.VAR18 (1'b1),
.VAR25 (VAR11)
);
VAR26.VAR31 = "VAR7",
VAR26.VAR28 = "VAR24",
VAR26.VAR14 = "VAR42",
VAR26.VAR1 = "VAR24",
VAR26.VAR30 = "VAR24",
VAR26.VAR4 = "VAR43",
VAR26.VAR29 = "VAR21",
VAR26.VAR36 = "VAR2",
VAR26.VAR23 = "VAR16",
VAR26.VAR19 = "VAR10",
VAR26.VAR8 = "VAR7",
VAR26.VAR41 = 1,
VAR26.VAR22 = "VAR24",
VAR26.VAR12 = "VAR15",
VAR26.VAR33 = "VAR15",
VAR26.VAR40 = "VAR15",
VAR26.VAR44 = "VAR15",
VAR26.VAR39 = "VAR35",
VAR26.VAR13 = "VAR35",
VAR26.VAR32 = "VAR3",
VAR26.VAR17 = "VAR10",
VAR26.VAR49 = "VAR10",
VAR26.VAR47 = "VAR7",
VAR26.VAR54 = "VAR7",
VAR26.VAR5 = "VAR24",
VAR26.VAR20 = "VAR24",
VAR26.VAR52 = 16,
VAR26.VAR34 = 16,
VAR26.VAR55 = 16;
assign VAR53 = {VAR46[31 : 16] +
VAR11,
VAR46[15 : 0]};
endmodule | gpl-2.0 |
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