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google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3b/sky130_fd_sc_hs__and3b.functional.pp.v | 1,888 | module MODULE1 (
VAR14,
VAR1,
VAR7 ,
VAR6 ,
VAR2 ,
VAR8
);
input VAR14;
input VAR1;
output VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR8 ;
wire VAR11 ;
wire VAR3 ;
wire VAR9;
not VAR10 (VAR11 , VAR6 );
and VAR12 (VAR3 , VAR8, VAR11, VAR2 );
VAR13 VAR5 (VAR9, VAR3, VAR14, VAR1);
buf VAR4 (VAR7 , VAR9 );
endmodule | apache-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_1/affine_block_ieee754_fp_adder_subtractor_0_1_stub.v | 1,397 | module MODULE1(VAR2, VAR3, VAR1)
;
input [31:0]VAR2;
input [31:0]VAR3;
output [31:0]VAR1;
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.behavioral.pp.v | 1,179 | module MODULE1( VAR7, VAR2, VAR4, VAR1 );
input VAR7;
inout VAR4, VAR1;
output VAR2;
VAR3 VAR5(.VAR7(VAR7),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1));
VAR3 VAR6(.VAR7(VAR7),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
asicguy/gplgpu | hdl/de3d/de3d_reg.v | 52,531 | module MODULE1
(
input VAR413, input VAR335, input [31:0] VAR173, input [8:2] VAR112, input [8:2] VAR326, input VAR440, input [3:0] VAR421, input VAR121, input VAR134, input VAR281, input VAR428, input VAR152, input [1:0] VAR433, input VAR368,
input VAR401,
output [351:0] VAR140, output [351:0] VAR435, output [351:0] VAR87, output reg VAR79, output reg VAR390, output reg VAR3, output VAR403, output VAR251,
output reg [209:0] VAR77, output reg [27:0] VAR41, output reg [11:0] VAR99, output reg [20:0] VAR254, output reg [20:0] VAR36, output reg [11:0] VAR359, output reg [31:0] VAR45, output reg [31:0] VAR215, output reg [31:0] VAR166, output reg [31:0] VAR262, output reg [23:0] VAR362, output reg [23:0] VAR119, output reg [31:0] VAR16, output reg [31:0] VAR418, output reg [31:0] VAR431, output reg [31:0] VAR24, output reg [23:0] VAR98, output reg [17:0] VAR236, output reg VAR378,
output reg [31:0] VAR307 );
parameter
VAR404 = 7'b0010010, VAR27 = 7'b0010100, VAR336 = 7'b1011010, VAR211 = 7'b0010101, VAR301 = 7'b0110100, VAR358 = 7'b0110101, VAR177 = 7'b0110110, VAR260 = 7'b0110111, VAR351 = 7'b0111000, VAR37 = 7'b0111001, VAR360 = 7'b0111010, VAR386 = 7'b0111011, VAR406 = 7'b0111100, VAR149 = 7'b0111101, VAR419 = 7'b0001110, VAR296 = 7'b0001111, VAR172 = 7'b1000000, VAR200 = 7'b1000110, VAR313 = 7'b1000111, VAR374 = 7'b1001000, VAR284 = 7'b1001001, VAR89 = 7'b1001010, VAR324 = 7'b1001011, VAR49 = 7'b1001100, VAR345 = 7'b1001101, VAR328 = 7'b1001110, VAR21 = 7'b1001111, VAR244 = 7'b1010000, VAR146 = 7'b1010001, VAR263 = 7'b1010010, VAR287 = 7'b1010011, VAR71 = 7'b1010100, VAR53 = 7'b1010101, VAR361 = 7'b1010110, VAR186 = 7'b1010111, VAR436 = 7'b1011000, VAR153 = 7'b1011001, VAR90 = 7'b1011011, VAR9 = 7'b1011100, VAR62 = 7'b1011101, VAR234 = 7'b1011110, VAR310 = 7'b1011111, VAR162 = 7'b1100000, VAR155 = 7'b1100001, VAR82 = 7'b1100010, VAR400 = 7'b1100011, VAR304 = 7'b1100100, VAR159 = 7'b1100101, VAR379 = 7'b1100110, VAR334 = 7'b1100111, VAR19 = 7'b1101000, VAR120 = 7'b1101001, VAR12 = 7'b1101010, VAR56 = 7'b1101011, VAR113 = 7'b1101100, VAR106 = 7'b1101101, VAR331 = 7'b1101110, VAR209 = 7'b1101111, VAR218 = 7'b1110000, VAR145 = 7'b1110001, VAR167 = 7'b1110010, VAR184 = 7'b1110011, VAR364 = 7'b1110100, VAR316 = 7'b1110101, VAR178 = 7'b1110110, VAR322 = 7'b1110111, VAR201 = 7'b1111000,
VAR84 = 4'b1000, VAR118 = 4'b1001;
wire [31:0] VAR415;
wire [31:0] VAR64;
wire [31:0] VAR227;
wire [31:0] VAR148; wire [31:0] VAR154;
wire [31:0] VAR416;
wire VAR66;
wire VAR289;
wire VAR396;
wire VAR147;
wire VAR308;
wire VAR198;
reg [351:0] VAR237; reg [351:0] VAR143; reg [351:0] VAR408;
reg [20:0] VAR188;
reg [20:0] VAR91;
reg [20:0] VAR398;
reg [20:0] VAR28;
reg [20:0] VAR181;
reg [20:0] VAR70;
reg [20:0] VAR61;
reg [20:0] VAR8;
reg [20:0] VAR163;
reg [20:0] VAR318;
reg [31:0] VAR329;
reg [7:0] VAR135; reg [7:0] VAR241; reg [7:0] VAR290;
reg [3:0] VAR380; reg [3:0] VAR253; reg VAR305; reg VAR18; reg VAR193; reg VAR54; reg [2:0] VAR375; reg VAR111;
reg VAR366;
reg VAR347;
reg [2:0] VAR286;
reg [31:0] VAR39;
reg VAR410;
reg [27:0] VAR7;
reg [11:0] VAR315;
reg [11:0] VAR299;
reg [31:0] VAR31;
reg [31:0] VAR136;
reg [31:0] VAR443;
reg [31:0] VAR357;
reg [23:0] VAR280;
reg [23:0] VAR348;
reg [31:0] VAR50;
reg [31:0] VAR391;
reg [31:0] VAR103;
reg [3:0] VAR355;
reg [3:0] VAR25;
wire VAR11;
wire [23:0] VAR259;
wire [17:0] VAR275;
wire VAR385;
wire [351:0] VAR339;
wire [351:0] VAR394;
wire [351:0] VAR265;
wire VAR427;
wire VAR342;
wire VAR194;
wire [31:0] VAR369;
wire [31:0] VAR327;
wire [31:0] VAR205;
wire [31:0] VAR423;
wire [31:0] VAR160;
wire [31:0] VAR72;
wire [31:0] VAR126;
wire [31:0] VAR337;
wire [31:0] VAR341;
wire [31:0] VAR372;
wire [31:0] VAR297;
wire [31:0] VAR40;
wire [31:0] VAR4;
wire [31:0] VAR10;
wire [31:0] VAR202;
wire [31:0] VAR238;
wire [31:0] VAR382;
wire [31:0] VAR230;
reg [209:0] VAR30; reg [31:0] VAR169; reg [31:0] VAR51; reg [27:0] VAR105; reg [11:0] VAR245; reg [20:0] VAR74; reg [11:0] VAR232; reg [31:0] VAR107; reg [31:0] VAR247; reg [23:0] VAR214; reg [23:0] VAR32; reg [31:0] VAR174; reg [31:0] VAR141; reg [31:0] VAR424; reg [23:0] VAR266;
reg [17:0] VAR93;
reg [31:0] VAR210;
reg [1:0] VAR55;
reg [351:0] VAR80; reg [351:0] VAR158; reg [351:0] VAR434;
assign VAR403 = VAR174[28]; wire VAR267 = (VAR355 == VAR84);
wire VAR407 = (VAR355 == VAR118);
wire VAR441 = (VAR25 == VAR84);
wire VAR116 = (VAR25 == VAR118);
wire VAR272 = VAR407 | VAR267;
wire VAR34;
wire VAR69 = VAR407 & ~VAR50[28];
assign VAR251 = (VAR25 == VAR84);
assign VAR385 = ~(VAR34 ^ VAR50[22]);
assign VAR11 = VAR407 & VAR50[23];
assign VAR259[15:0] = {VAR241,VAR135};
assign VAR259[23:16] = VAR290;
assign VAR275[10:0] = {VAR193,VAR18,VAR305, VAR253,VAR380};
assign VAR275[17:11] = {VAR111,VAR366,VAR347,VAR54,VAR375};
reg [31:0] VAR320; reg [8:2] VAR242; reg VAR240; reg [3:0] VAR370; reg VAR249;
always @(posedge VAR335) begin
VAR320 <= VAR173;
VAR242 <= VAR112;
VAR240 <= VAR440;
VAR370 <= VAR421;
VAR249 <= VAR121;
end
always @(posedge VAR335, negedge VAR413)
if(!VAR413) VAR355 <= 4'h0;
else if(VAR240 && !VAR249 && !VAR370[0] &&
((VAR242==VAR404) || (VAR242==VAR336) || (VAR242==VAR27)))
VAR355 <= VAR320[3:0];
assign {VAR34, VAR265, VAR394, VAR339}
= VAR340(VAR408, VAR143, VAR237, VAR69, VAR267);
assign VAR415 = (~VAR412) ? 32'h3f800000 : VAR216;
assign VAR64 = (~VAR412) ? 32'h3f800000 : VAR258;
assign VAR227 = (~VAR412) ? 32'h3f800000 : VAR381;
always @*
case(VAR242)
VAR334, VAR379, VAR159, VAR304: VAR329 = VAR415;
VAR209, VAR331, VAR106, VAR113: VAR329 = VAR64;
VAR178, VAR316, VAR364, VAR322: VAR329 = VAR227;
default: VAR329 = 32'h3f800000; endcase
VAR187 VAR392
(VAR329, VAR320[31:0], VAR148);
VAR405 VAR273
(1'b1,VAR320[31:0], {2'b00,{6{VAR50[21] & VAR272}},24'h0}, VAR154);
assign VAR416 = VAR154;
always @(posedge VAR335, negedge VAR413)
if(!VAR413) begin
VAR391 <= 32'h0;
VAR50 <= 32'h0;
VAR347 <= 0;
VAR366 <= 0;
VAR111 <= 0;
VAR410 <= 0;
{VAR253,VAR380} <= 8'h0;
{VAR193, VAR18,VAR305} <= 3'h0;
{VAR54, VAR375} <= 4'h0;
VAR50 <= 32'h0;
VAR391 <= 32'h0;
VAR299 <= 12'h0;
VAR315 <= 12'h0;
VAR7 <= 28'h0;
VAR318 <= 21'h0;
VAR163 <= 21'h0;
VAR8 <= 21'h0;
VAR61 <= 21'h0;
VAR70 <= 21'h0;
VAR181 <= 21'h0;
VAR28 <= 21'h0;
VAR398 <= 21'h0;
VAR91 <= 21'h0;
VAR188 <= 21'h0;
VAR36 <= 21'h0;
VAR31 <= 32'h0;
VAR136 <= 32'h0;
VAR443 <= 32'h0;
VAR135 <= 8'h0;
VAR241 <= 8'h0;
VAR290 <= 8'h0;
VAR357 <= 32'h0;
VAR280 <= 24'h0;
VAR348 <= 24'h0;
VAR103 <= 24'h0;
VAR39 <= 32'h0;
VAR161 <= 352'h0;
VAR277 <= 352'h0;
VAR128 <= 352'h0;
end else begin
if (~VAR412) begin
VAR216 <= 32'h3f800000;
VAR258 <= 32'h3f800000;
VAR381 <= 32'h3f800000;
end
if (!VAR249 && VAR240) begin
if(VAR242==VAR90) begin
if(!VAR370[0]){VAR253,VAR380} <= VAR320[7:0];
if(!VAR370[1]){VAR193, VAR18,VAR305} <= VAR320[10:8];
if(!VAR370[2]) {VAR54, VAR375} <= VAR320[19:16];
if(!VAR370[3]) {VAR111,VAR366,VAR347} <= VAR320[26:24];
end
if(VAR242==VAR9) begin
if (!VAR370[0]) VAR50[7:0] <= VAR320[7:0];
if (!VAR370[1]) VAR50[15:8] <= VAR320[15:8];
if (!VAR370[2]) VAR50[23:16] <= VAR320[23:16];
if (!VAR370[3]) VAR50[31:24] <= VAR320[31:24];
end
if(VAR242==VAR62) begin
if (!VAR370[0]) VAR391[7:0] <= VAR320[7:0];
if (!VAR370[1]) VAR391[15:8] <= VAR320[15:8];
if (!VAR370[2]) VAR391[23:16] <= VAR320[23:16];
if (!VAR370[3]) VAR391[31:24] <= VAR320[31:24];
end
if(VAR242==VAR419) begin
if(!VAR370[0])VAR299[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR299[11:4] <= VAR320[15:8];
end
if(VAR242==VAR296) begin
if(!VAR370[0])VAR315[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR315[11:4] <= VAR320[15:8];
end
if(VAR242==VAR172) begin
if(!VAR370[0])VAR7[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR7[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR7[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR7[27:20] <= VAR320[31:24];
end
if(VAR242==VAR301) begin
if(!VAR370[0])VAR318[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR318[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR318[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR318[20] <= VAR320[24];
end
if(VAR242==VAR358) begin
if(!VAR370[0])VAR163[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR163[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR163[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR163[20] <= VAR320[24];
end
if(VAR242==VAR177) begin
if(!VAR370[0])VAR8[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR8[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR8[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR8[20] <= VAR320[24];
end
if(VAR242==VAR260) begin
if(!VAR370[0])VAR61[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR61[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR61[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR61[20] <= VAR320[24];
end
if(VAR242==VAR351) begin
if(!VAR370[0])VAR70[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR70[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR70[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR70[20] <= VAR320[24];
end
if(VAR242==VAR37) begin
if(!VAR370[0])VAR181[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR181[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR181[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR181[20] <= VAR320[24];
end
if(VAR242==VAR360) begin
if(!VAR370[0])VAR28[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR28[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR28[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR28[20] <= VAR320[24];
end
if(VAR242==VAR386) begin
if(!VAR370[0])VAR398[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR398[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR398[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR398[20] <= VAR320[24];
end
if(VAR242==VAR406) begin
if(!VAR370[0])VAR91[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR91[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR91[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR91[20] <= VAR320[24];
end
if(VAR242==VAR149) begin
if(!VAR370[0])VAR188[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR188[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR188[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR188[20] <= VAR320[24];
end
if(VAR242==VAR200) begin
if(!VAR370[0])VAR36[3:0] <= VAR320[7:4];
if(!VAR370[1])VAR36[11:4] <= VAR320[15:8];
if(!VAR370[2])VAR36[19:12] <= VAR320[23:16];
if(!VAR370[3])VAR36[20] <= VAR320[24];
end
if(VAR242==VAR313) begin
if(!VAR370[0])VAR31[7:0] <= VAR320[7:0];
if(!VAR370[1])VAR31[15:8] <= VAR320[15:8];
if(!VAR370[2])VAR31[23:16] <= VAR320[23:16];
if(!VAR370[3])VAR31[31:24] <= VAR320[31:24];
end
if(VAR242==VAR374) begin
if(!VAR370[0])VAR136[7:0] <= VAR320[7:0];
if(!VAR370[1])VAR136[15:8] <= VAR320[15:8];
if(!VAR370[2])VAR136[23:16] <= VAR320[23:16];
if(!VAR370[3])VAR136[31:24] <= VAR320[31:24];
end
if(VAR242==VAR284) begin
if(!VAR370[0])VAR443[7:0] <= VAR320[7:0];
if(!VAR370[1])VAR443[15:8] <= VAR320[15:8];
if(!VAR370[2])VAR443[23:16] <= VAR320[23:16];
if(!VAR370[3])VAR443[31:24] <= VAR320[31:24];
end
if(VAR242==VAR89) begin
if(!VAR370[0])VAR135 <= VAR320[7:0];
if(!VAR370[1])VAR241 <= VAR320[15:8];
if(!VAR370[2])VAR290 <= VAR320[23:16];
end
if(VAR242==VAR324) begin
if(!VAR370[0])VAR357[7:0] <= VAR320[7:0];
if(!VAR370[1])VAR357[15:8] <= VAR320[15:8];
if(!VAR370[2])VAR357[23:16] <= VAR320[23:16];
if(!VAR370[3])VAR357[31:24] <= VAR320[31:24];
end
if(VAR242==VAR436) begin
if(!VAR370[0])VAR280[7:0] <= VAR320[7:0];
if(!VAR370[1])VAR280[15:8] <= VAR320[15:8];
if(!VAR370[2])VAR280[23:16] <= VAR320[23:16];
end
if(VAR242==VAR153) begin
if(!VAR370[0])VAR348[7:0] <= VAR320[7:0];
if(!VAR370[1])VAR348[15:8] <= VAR320[15:8];
if(!VAR370[2])VAR348[23:16] <= VAR320[23:16];
end
if(VAR242==VAR201) begin
if(!VAR370[0])VAR103[7:0] <= VAR320[7:0];
if(!VAR370[1])VAR103[15:8] <= VAR320[15:8];
if(!VAR370[2])VAR103[23:16] <= VAR320[23:16];
if(!VAR370[3])VAR103[31:24] <= VAR320[31:24];
end
if (VAR242==VAR234) begin
if (!VAR370[0]) VAR39[7:0] <= VAR320[7:0];
if (!VAR370[1]) VAR39[15:8] <= VAR320[15:8];
if (!VAR370[2]) VAR39[23:16] <= VAR320[23:16];
if (!VAR370[3]) VAR39[31:24] <= VAR320[31:24];
end
if (VAR242==VAR310) begin if (!VAR370[0]) VAR23 <= VAR416[7:0];
if (!VAR370[1]) VAR189 <= VAR416[15:8];
if (!VAR370[2]) VAR317 <= VAR416[23:16];
if (!VAR370[3]) VAR373 <= VAR416[31:24];
end
if (VAR242==VAR162) begin if (!VAR370[0]) VAR60 <= VAR416[7:0];
if (!VAR370[1]) VAR191 <= VAR416[15:8];
if (!VAR370[2]) VAR294 <= VAR416[23:16];
if (!VAR370[3]) VAR365 <= VAR416[31:24];
end
if (VAR242==VAR155) begin if (!VAR370[0]) VAR65 <= VAR416[7:0];
if (!VAR370[1]) VAR321 <= VAR416[15:8];
if (!VAR370[2]) VAR402 <= VAR416[23:16];
if (!VAR370[3]) VAR252 <= VAR416[31:24];
end
if (VAR242==VAR82) begin if (!VAR370[0]) VAR212 <= VAR320[7:0];
if (!VAR370[1]) VAR52 <= VAR320[15:8];
if (!VAR370[2]) VAR123 <= VAR320[23:16];
if (!VAR370[3]) VAR330 <= VAR320[31:24];
end
if (VAR242==VAR400) begin if(~&VAR370[3:0]) VAR410 <= 1'b0;
if (!VAR370[0]) VAR432 <= VAR320[7:0];
if (!VAR370[1]) VAR114 <= VAR320[15:8];
if (!VAR370[2]) VAR261 <= VAR320[23:16];
if (!VAR370[3]) VAR57 <= VAR320[31:24];
end
if (VAR242==VAR304) begin if (!VAR370[0]) VAR383 <= VAR320[7:0];
if (!VAR370[1]) VAR48 <= VAR320[15:8];
if (!VAR370[2]) VAR270 <= VAR320[23:16];
if (!VAR370[3]) VAR104 <= VAR320[31:24];
end
if (VAR242==VAR159) begin if (!VAR370[0]) VAR131 <= VAR148[7:0];
if (!VAR370[1]) VAR395 <= VAR148[15:8];
if (!VAR370[2]) VAR26 <= VAR148[23:16];
if (!VAR370[3]) VAR17 <= VAR148[31:24];
end
if (VAR242==VAR379) begin if (!VAR370[0]) VAR233 <= VAR148[7:0];
if (!VAR370[1]) VAR68 <= VAR148[15:8];
if (!VAR370[2]) VAR183 <= VAR148[23:16];
if (!VAR370[3]) VAR35 <= VAR148[31:24];
end
if (VAR242==VAR334) begin if (!VAR370[0]) VAR295 <= VAR416[7:0];
if (!VAR370[1]) VAR110 <= VAR416[15:8];
if (!VAR370[2]) VAR292 <= VAR416[23:16];
if (!VAR370[3]) VAR42 <= VAR416[31:24];
end
if (VAR242==VAR19) begin if (!VAR370[0]) VAR204 <= VAR416[7:0];
if (!VAR370[1]) VAR256 <= VAR416[15:8];
if (!VAR370[2]) VAR338 <= VAR416[23:16];
if (!VAR370[3]) VAR425 <= VAR416[31:24];
end
if (VAR242==VAR120) begin if (!VAR370[0]) VAR349 <= VAR320[7:0];
if (!VAR370[1]) VAR185 <= VAR320[15:8];
if (!VAR370[2]) VAR343 <= VAR320[23:16];
if (!VAR370[3]) VAR353 <= VAR320[31:24];
end
if (VAR242==VAR12) begin if (!VAR370[0]) VAR352 <= VAR416[7:0];
if (!VAR370[1]) VAR157 <= VAR416[15:8];
if (!VAR370[2]) VAR43 <= VAR416[23:16];
if (!VAR370[3]) VAR377 <= VAR416[31:24];
end
if (VAR242==VAR56) begin if(~&VAR370[3:0]) VAR410 <= 1'b0;
if (!VAR370[0]) VAR13 <= VAR320[7:0];
if (!VAR370[1]) VAR92 <= VAR320[15:8];
if (!VAR370[2]) VAR20 <= VAR320[23:16];
if (!VAR370[3]) VAR29 <= VAR320[31:24];
end
if (VAR242==VAR113) begin if (!VAR370[0]) VAR127 <= VAR320[7:0];
if (!VAR370[1]) VAR344 <= VAR320[15:8];
if (!VAR370[2]) VAR274 <= VAR320[23:16];
if (!VAR370[3]) VAR81 <= VAR320[31:24];
end
if (VAR242==VAR106) begin if (!VAR370[0]) VAR363 <= VAR148[7:0];
if (!VAR370[1]) VAR309 <= VAR148[15:8];
if (!VAR370[2]) VAR224 <= VAR148[23:16];
if (!VAR370[3]) VAR130 <= VAR148[31:24];
end
if (VAR242==VAR331) begin if (!VAR370[0]) VAR192 <= VAR148[7:0];
if (!VAR370[1]) VAR414 <= VAR148[15:8];
if (!VAR370[2]) VAR76 <= VAR148[23:16];
if (!VAR370[3]) VAR139 <= VAR148[31:24];
end
if (VAR242==VAR209) begin if (!VAR370[0]) VAR176 <= VAR416[7:0];
if (!VAR370[1]) VAR175 <= VAR416[15:8];
if (!VAR370[2]) VAR411 <= VAR416[23:16];
if (!VAR370[3]) VAR388 <= VAR416[31:24];
end
if (VAR242==VAR218) begin if (!VAR370[0]) VAR15 <= VAR416[7:0];
if (!VAR370[1]) VAR133 <= VAR416[15:8];
if (!VAR370[2]) VAR422 <= VAR416[23:16];
if (!VAR370[3]) VAR250 <= VAR416[31:24];
end
if (VAR242==VAR145) begin if (!VAR370[0]) VAR332 <= VAR320[7:0];
if (!VAR370[1]) VAR22 <= VAR320[15:8];
if (!VAR370[2]) VAR268 <= VAR320[23:16];
if (!VAR370[3]) VAR371 <= VAR320[31:24];
end
if (VAR242==VAR167) begin if (!VAR370[0]) VAR312 <= VAR320[7:0];
if (!VAR370[1]) VAR197 <= VAR320[15:8];
if (!VAR370[2]) VAR276 <= VAR320[23:16];
if (!VAR370[3]) VAR132 <= VAR320[31:24];
end
if (VAR242==VAR184) begin if(~&VAR370[3:0]) VAR410 <= 1'b0;
if (!VAR370[0]) VAR257 <= VAR320[7:0];
if (!VAR370[1]) VAR164 <= VAR320[15:8];
if (!VAR370[2]) VAR302 <= VAR320[23:16];
if (!VAR370[3]) VAR6 <= VAR320[31:24];
end
if (VAR242==VAR364) begin if (!VAR370[0]) VAR73 <= VAR320[7:0];
if (!VAR370[1]) VAR222 <= VAR320[15:8];
if (!VAR370[2]) VAR182 <= VAR320[23:16];
if (!VAR370[3]) VAR229 <= VAR320[31:24];
end
if (VAR242==VAR316) begin if (!VAR370[0]) VAR409 <= VAR148[7:0];
if (!VAR370[1]) VAR231 <= VAR148[15:8];
if (!VAR370[2]) VAR206 <= VAR148[23:16];
if (!VAR370[3]) VAR199 <= VAR148[31:24];
end
if (VAR242==VAR178) begin
if (!VAR370[0]) VAR96 <= VAR148[7:0];
if (!VAR370[1]) VAR168 <= VAR148[15:8];
if (!VAR370[2]) VAR269 <= VAR148[23:16];
if (!VAR370[3]) VAR356 <= VAR148[31:24];
end
if (VAR242==VAR49) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR57 <= VAR320[7:0];
if (!VAR370[1]) VAR333 <= VAR320[15:8];
if (!VAR370[2]) VAR278 <= VAR320[23:16];
if (!VAR370[3]) VAR325 <= VAR320[31:24];
end
if (VAR242==VAR345) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR261 <= VAR320[7:0];
if (!VAR370[1]) VAR239 <= VAR320[15:8];
if (!VAR370[2]) VAR319 <= VAR320[23:16];
if (!VAR370[3]) VAR303 <= VAR320[31:24];
end
if (VAR242==VAR328) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR114 <= VAR320[7:0];
if (!VAR370[1]) VAR144 <= VAR320[15:8];
if (!VAR370[2]) VAR129 <= VAR320[23:16];
if (!VAR370[3]) VAR95 <= VAR320[31:24];
end
if (VAR242==VAR21) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR432 <= VAR320[7:0];
if (!VAR370[1]) VAR420 <= VAR320[15:8];
if (!VAR370[2]) VAR156 <= VAR320[23:16];
if (!VAR370[3]) VAR59 <= VAR320[31:24];
end
if (VAR242==VAR244) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR29 <= VAR320[7:0];
if (!VAR370[1]) VAR346 <= VAR320[15:8];
if (!VAR370[2]) VAR217 <= VAR320[23:16];
if (!VAR370[3]) VAR86 <= VAR320[31:24];
end
if (VAR242==VAR146) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR20 <= VAR320[7:0];
if (!VAR370[1]) VAR246 <= VAR320[15:8];
if (!VAR370[2]) VAR125 <= VAR320[23:16];
if (!VAR370[3]) VAR437 <= VAR320[31:24];
end
if (VAR242==VAR263) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR92 <= VAR320[7:0];
if (!VAR370[1]) VAR235 <= VAR320[15:8];
if (!VAR370[2]) VAR100 <= VAR320[23:16];
if (!VAR370[3]) VAR219 <= VAR320[31:24];
end
if (VAR242==VAR287) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR13 <= VAR320[7:0];
if (!VAR370[1]) VAR442 <= VAR320[15:8];
if (!VAR370[2]) VAR439 <= VAR320[23:16];
if (!VAR370[3]) VAR5 <= VAR320[31:24];
end
if (VAR242==VAR71) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR6 <= VAR320[7:0];
if (!VAR370[1]) VAR306 <= VAR320[15:8];
if (!VAR370[2]) VAR288 <= VAR320[23:16];
if (!VAR370[3]) VAR117 <= VAR320[31:24];
end
if (VAR242==VAR53) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR302 <= VAR320[7:0];
if (!VAR370[1]) VAR264 <= VAR320[15:8];
if (!VAR370[2]) VAR88 <= VAR320[23:16];
if (!VAR370[3]) VAR75 <= VAR320[31:24];
end
if (VAR242==VAR361) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR164 <= VAR320[7:0];
if (!VAR370[1]) VAR228 <= VAR320[15:8];
if (!VAR370[2]) VAR1 <= VAR320[23:16];
if (!VAR370[3]) VAR429 <= VAR320[31:24];
end
if (VAR242==VAR186) begin
if(~&VAR370) VAR410 <= 1'b1;
if (!VAR370[0]) VAR257 <= VAR320[7:0];
if (!VAR370[1]) VAR14 <= VAR320[15:8];
if (!VAR370[2]) VAR142 <= VAR320[23:16];
if (!VAR370[3]) VAR122 <= VAR320[31:24];
end
end end
always @(posedge VAR134, negedge VAR281)
if(!VAR281) begin
VAR25 <= 4'h0;
VAR174 <= 32'h0;
VAR141 <= 32'h0; end else if(VAR428 & (VAR267 | VAR407)) begin
VAR25 <= VAR355;
VAR174 <= VAR50; VAR141 <= VAR391; end else if(VAR401 & !(VAR267 | VAR407)) begin
VAR25 <= 4'h0;
VAR174 <= 32'h0;
VAR141 <= 32'h0; end
always @(posedge VAR134, negedge VAR281)
if(!VAR281) begin
VAR210 <= 32'h0; VAR80 <= 352'h0; VAR158 <= 352'h0; VAR434 <= 352'h0; VAR79 <= 1'b0;
VAR390 <= 1'b0; VAR30 <= 210'h0;
VAR105 <= 28'h0; VAR245 <= 12'h0; VAR74 <= 21'h0; VAR232 <= 12'h0; VAR169 <= 32'h0; VAR51 <= 32'h0; VAR107 <= 32'h0; VAR247 <= 32'h0; VAR214 <= 24'h0; VAR32 <= 24'h0; VAR424 <= 32'h0; VAR3 <= 1'b0; VAR266 <= 24'h0;
VAR93 <= 18'h0;
end else if(VAR428) begin
VAR210 <= VAR39; VAR80 <= VAR339; VAR158 <= VAR394; VAR434 <= VAR265; VAR79 <= VAR385;
VAR390 <= VAR410; VAR30 <= {VAR188, VAR91, VAR398, VAR28, VAR181,
VAR70, VAR61, VAR8, VAR163, VAR318};
VAR105 <= VAR7; VAR245 <= VAR315; VAR74 <= VAR36; VAR232 <= VAR299; VAR169 <= VAR31; VAR51 <= VAR136; VAR107 <= VAR443; VAR247 <= VAR357; VAR214 <= VAR280; VAR32 <= VAR348; VAR424 <= VAR103; VAR3 <= VAR11; VAR266 <= VAR259;
VAR93 <= VAR275;
end
always @*
casex ({VAR271, VAR433[0]})
2'b10: VAR55 = 2'b11; 2'b11: VAR55 = 2'b10; default: VAR55 = 2'b00;
endcase
assign VAR369 = VAR223;
assign VAR327 = VAR350;
assign VAR205 = VAR46;
assign VAR427 = |(VAR369[30:0]);
assign VAR342 = |(VAR327[30:0]);
assign VAR194 = |(VAR205[30:0]);
assign VAR372 = (VAR427) ? {VAR369[31], (VAR369[30:26] + VAR55), VAR369[25:0]} : 32'h0;
assign VAR297 = (VAR342) ? {VAR327[31], (VAR327[30:26] + VAR55), VAR327[25:0]} : 32'h0;
assign VAR40 = (VAR194) ? {VAR205[31], (VAR205[30:26] + VAR55), VAR205[25:0]} : 32'h0;
assign VAR423 = VAR397;
assign VAR160 = VAR291;
assign VAR72 = VAR195;
assign VAR126 = VAR220;
assign VAR337 = VAR33;
assign VAR341 = VAR225;
assign VAR66 = |VAR423[30:0];
assign VAR289 = |VAR160[30:0];
assign VAR396 = |VAR72[30:0];
assign VAR147 = |VAR126[30:0];
assign VAR308 = |VAR337[30:0];
assign VAR198 = |VAR341[30:0];
assign VAR4 = (VAR279 & VAR66) ? {VAR423[31], (VAR423[30:23] + VAR78), VAR423[22:0]} : VAR423;
assign VAR10 = (VAR279 & VAR289) ? {VAR160[31], (VAR160[30:23] + VAR293), VAR160[22:0]} : VAR160;
assign VAR202 = (VAR279 & VAR396) ? {VAR72[31], (VAR72[30:23] + VAR78), VAR72[22:0]} : VAR72;
assign VAR238 = (VAR279 & VAR147) ? {VAR126[31], (VAR126[30:23] + VAR293), VAR126[22:0]} : VAR126;
assign VAR382 = (VAR279 & VAR308) ? {VAR337[31], (VAR337[30:23] + VAR78), VAR337[22:0]} : VAR337;
assign VAR230 = (VAR279 & VAR198) ? {VAR341[31], (VAR341[30:23] + VAR293), VAR341[22:0]} : VAR341;
assign VAR140 = {VAR80[351:192], VAR10, VAR4, VAR80[127:96], VAR372, VAR80[63:0]}; assign VAR435 = {VAR158[351:192], VAR238, VAR202, VAR158[127:96], VAR297, VAR158[63:0]}; assign VAR87 = {VAR434[351:192], VAR230, VAR382, VAR434[127:96], VAR40, VAR434[63:0]};
always @(posedge VAR134, negedge VAR281)
if(!VAR281) begin
VAR16 <= 32'h0;
VAR418 <= 32'h0;
VAR378 <= 1'b0;
end
else if(VAR152 & (VAR441 | VAR116)) begin
VAR16 <= VAR174; VAR418 <= VAR141; VAR378 <= 1'b1;
end
else if(~VAR368 & ~VAR441 & ~VAR116) begin
VAR16 <= 32'h0;
VAR418 <= 32'h0; VAR378 <= 1'b0;
end
always @(posedge VAR134, negedge VAR281)
if(!VAR281) begin
VAR24 <= 32'h0;
VAR77 <= 210'h0;
VAR41 <= 28'h0;
VAR99 <= 12'h0;
VAR254 <= 21'h0;
VAR359 <= 12'h0;
VAR45 <= 32'h0;
VAR215 <= 32'h0;
VAR166 <= 32'h0;
VAR262 <= 32'h0;
VAR362 <= 24'h0;
VAR119 <= 24'h0;
VAR431 <= 32'h0;
VAR98 <= 24'h0;
VAR236 <= 18'h0;
end else if(VAR152) begin
VAR24 <= VAR210;
VAR77 <= VAR30;
VAR41 <= VAR105;
VAR99 <= VAR245;
VAR254 <= VAR74;
VAR359 <= VAR232;
VAR45 <= VAR169;
VAR215 <= VAR51;
VAR166 <= VAR107;
VAR262 <= VAR247;
VAR362 <= VAR214;
VAR119 <= VAR32;
VAR431 <= VAR424;
VAR98 <= VAR266;
VAR236 <= VAR93;
end
always @* begin
VAR307 = 32'h0;
case(VAR326)
VAR419: VAR307[11:0] = {VAR299[11:4], VAR299[3:0]};
VAR296: VAR307[11:0] = {VAR315[11:4], VAR315[3:0]};
VAR172: VAR307 = VAR7;
VAR301: VAR307[20:0] = VAR318;
VAR358: VAR307[20:0] = VAR163;
VAR177: VAR307[20:0] = VAR8;
VAR260: VAR307[20:0] = VAR61;
VAR351: VAR307[20:0] = VAR70;
VAR37: VAR307[20:0] = VAR181;
VAR360: VAR307[20:0] = VAR28;
VAR386: VAR307[20:0] = VAR398;
VAR406: VAR307[20:0] = VAR91;
VAR149: VAR307[20:0] = VAR188;
VAR200: VAR307[24:4] = VAR36;
VAR313: VAR307 = VAR31;
VAR374: VAR307 = VAR136;
VAR284: VAR307 = VAR443;
VAR89: VAR307[23:0] = {VAR290, VAR241, VAR135};
VAR324: VAR307[31:0] = VAR357;
VAR436: VAR307[23:0] = VAR280;
VAR153: VAR307[23:0] = VAR348;
VAR201: VAR307[31:0] = VAR103;
VAR234: VAR307[31:0] = VAR39;
VAR310: VAR307[31:0] = VAR179; VAR162: VAR307[31:0] = VAR47; VAR155: VAR307[31:0] = VAR208; VAR82: VAR307[31:0] = VAR216; VAR400: VAR307[31:0] = {VAR57, VAR261, VAR114, VAR432}; VAR304: VAR307[31:0] = VAR314; VAR159: VAR307[31:0] = VAR58; VAR379: VAR307[31:0] = VAR417; VAR334: VAR307[31:0] = VAR101; VAR19: VAR307[31:0] = VAR180; VAR120: VAR307[31:0] = VAR389; VAR12: VAR307[31:0] = VAR258; VAR56: VAR307[31:0] = {VAR29, VAR20, VAR92, VAR13}; VAR113: VAR307[31:0] = VAR138; VAR106: VAR307[31:0] = VAR83; VAR331: VAR307[31:0] = VAR97; VAR209: VAR307[31:0] = VAR203; VAR218: VAR307[31:0] = VAR67; VAR145: VAR307[31:0] = VAR376; VAR167: VAR307[31:0] = VAR381; VAR184: VAR307[31:0] = {VAR6, VAR302, VAR164, VAR257}; VAR364: VAR307[31:0] = VAR63; VAR316: VAR307[31:0] = VAR430; VAR178: VAR307[31:0] = VAR226; VAR49: VAR307[31:0] = VAR102;
VAR345: VAR307[31:0] = VAR190;
VAR328: VAR307[31:0] = VAR285;
VAR21: VAR307[31:0] = VAR207;
VAR244: VAR307[31:0] = VAR426;
VAR146: VAR307[31:0] = VAR85;
VAR263: VAR307[31:0] = VAR2;
VAR287: VAR307[31:0] = VAR108;
VAR71: VAR307[31:0] = VAR255;
VAR53: VAR307[31:0] = VAR150;
VAR361: VAR307[31:0] = VAR137;
VAR186: VAR307[31:0] = VAR323;
default: VAR307 = 32'h0;
endcase
end
function [1056:0] VAR340;
input [351:0] VAR243; input [351:0] VAR283; input [351:0] VAR367; input VAR115; input VAR38;
reg [351:0] VAR438;
reg [351:0] VAR94;
reg [351:0] VAR109;
reg VAR44; reg VAR282; reg VAR300; reg VAR248;
begin
VAR282 = VAR124(VAR399, VAR165);
VAR300 = VAR124(VAR165, VAR213);
VAR248 = VAR124(VAR399, VAR213);
casex ({VAR282,VAR300,VAR248})
3'b000, 3'b001, 3'b110: VAR44 = 1;
3'b010: VAR44 = 0;
3'b011: VAR44 = 1;
3'b100: VAR44 = 0;
3'b101: VAR44 = 1;
3'b111: VAR44 = 0;
endcase
casex ({VAR38,VAR115,VAR282,VAR300,VAR248})
5'b01000, 5'b01001, 5'b01110: begin VAR438 = VAR243; VAR94 = VAR283; VAR109 = VAR367; end
5'b01010: begin VAR438 = VAR283; VAR94 = VAR243; VAR109 = VAR367; end
5'b01011: begin VAR438 = VAR283; VAR94 = VAR367; VAR109 = VAR243; end
5'b01100: begin VAR438 = VAR243; VAR94 = VAR367; VAR109 = VAR283; end
5'b01101: begin VAR438 = VAR367; VAR94 = VAR243; VAR109 = VAR283; end
5'VAR384,5'b01111: begin VAR438 = VAR367; VAR94 = VAR283; VAR109 = VAR243; end
5'VAR393: begin VAR438 = VAR283; VAR94 = VAR283; VAR109 = VAR243; end
default: begin VAR438 = 352'h0; VAR94 = 352'h0; VAR109 = 352'h0; end
endcase
VAR340 = {VAR44, VAR109, VAR94, VAR438};
end
endfunction
function VAR124;
input [31:0] VAR311; input [31:0] VAR354; begin
casex({VAR311[31],VAR354[31], (VAR311[30:23] < VAR354[30:23]), (VAR311[30:23] == VAR354[30:23]), (VAR311[22:0] < VAR354[22:0])})
5'VAR151: VAR124 = 1; 5'VAR387: VAR124 = 0; 5'VAR298: VAR124 = 1; 5'VAR171: VAR124 = 0; 5'b00011: VAR124 = 1; 5'b00010: VAR124 = 0; 5'VAR170: VAR124 = 0; 5'VAR196: VAR124 = 1; 5'b11011: VAR124 = 0; 5'b11010: VAR124 = 1; endcase
end
endfunction
always @* begin
if (VAR428) begin
end end VAR221
endmodule | gpl-3.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/soc_system_button_pio.v | 3,739 | module MODULE1 (
address,
VAR10,
clk,
VAR5,
VAR14,
VAR2,
VAR4,
irq,
VAR15
)
;
output irq;
output [ 31: 0] VAR15;
input [ 1: 0] address;
input VAR10;
input clk;
input [ 1: 0] VAR5;
input VAR14;
input VAR2;
input [ 31: 0] VAR4;
wire VAR1;
reg [ 1: 0] VAR9;
reg [ 1: 0] VAR6;
wire [ 1: 0] VAR11;
reg [ 1: 0] VAR3;
wire VAR12;
wire [ 1: 0] VAR8;
wire irq;
reg [ 1: 0] VAR7;
wire [ 1: 0] VAR13;
reg [ 31: 0] VAR15;
assign VAR1 = 1;
assign VAR13 = ({2 {(address == 0)}} & VAR11) |
({2 {(address == 2)}} & VAR7) |
({2 {(address == 3)}} & VAR3);
always @(posedge clk or negedge VAR14)
begin
if (VAR14 == 0)
VAR15 <= 0;
end
else if (VAR1)
VAR15 <= {32'b0 | VAR13};
end
assign VAR11 = VAR5;
always @(posedge clk or negedge VAR14)
begin
if (VAR14 == 0)
VAR7 <= 0;
end
else if (VAR10 && ~VAR2 && (address == 2))
VAR7 <= VAR4[1 : 0];
end
assign irq = |(VAR3 & VAR7);
assign VAR12 = VAR10 && ~VAR2 && (address == 3);
always @(posedge clk or negedge VAR14)
begin
if (VAR14 == 0)
VAR3[0] <= 0;
end
else if (VAR1)
if (VAR12 && VAR4[0])
VAR3[0] <= 0;
else if (VAR8[0])
VAR3[0] <= -1;
end
always @(posedge clk or negedge VAR14)
begin
if (VAR14 == 0)
VAR3[1] <= 0;
end
else if (VAR1)
if (VAR12 && VAR4[1])
VAR3[1] <= 0;
else if (VAR8[1])
VAR3[1] <= -1;
end
always @(posedge clk or negedge VAR14)
begin
if (VAR14 == 0)
begin
VAR9 <= 0;
VAR6 <= 0;
end
else if (VAR1)
begin
VAR9 <= VAR11;
VAR6 <= VAR9;
end
end
assign VAR8 = ~VAR9 & VAR6;
endmodule | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai.blackbox.v | 1,334 | module MODULE1 (
VAR5 ,
VAR4,
VAR7,
VAR8
);
output VAR5 ;
input VAR4;
input VAR7;
input VAR8;
supply1 VAR1;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_asg_ch.v | 9,132 | module MODULE1 #(
parameter VAR41 = 14,
parameter VAR20 = 32
)(
output reg [ 14-1: 0] VAR36 , input VAR39 , input VAR34 , input VAR28 , input VAR50 , input [ 3-1: 0] VAR23 , output VAR21 ,
input VAR11 , input [ 14-1: 0] VAR9 , input [ 14-1: 0] VAR42 , output reg [ 14-1: 0] VAR5 , output reg [VAR41-1: 0] VAR15 ,
input [VAR41+16-1: 0] VAR49 , input [VAR41+16-1: 0] VAR31 , input [VAR41+16-1: 0] VAR7 , input VAR27 , input VAR6 , input VAR43 , input [ 14-1: 0] VAR33 , input [ 14-1: 0] VAR8 , input VAR56 , input [ VAR20-1: 0] VAR22 , input [ 16-1: 0] VAR40 , input [ 32-1: 0] VAR24 , input VAR38 ,
input VAR13 , input [VAR41-1:0] VAR3
);
reg [ 14-1: 0] VAR29 [0:(1<<VAR41)-1] ;
reg [ 14-1: 0] VAR32 ;
reg [ 14-1: 0] VAR16 ;
reg [ VAR41-1: 0] VAR2 ;
reg [VAR41+16-1: 0] VAR45 ; reg [VAR41+16-1: 0] VAR25 ; wire [VAR41+17-1: 0] VAR26 ; wire [VAR41+17-1: 0] VAR54 ;
wire VAR55;
reg [ 28-1: 0] VAR12 ;
reg [ 15-1: 0] VAR48 ;
always @(posedge VAR39)
begin
VAR15 <= VAR45[16+VAR41-1:16];
VAR2 <= (VAR13 == 1'b1) ? VAR3 : VAR45[VAR41+15:16];
VAR32 <= VAR29[VAR2] ;
VAR16 <= VAR32 ; end
always @(posedge VAR39)
if (VAR11) VAR29[VAR9] <= VAR42[14-1:0] ;
always @(posedge VAR39)
begin
VAR12 <= (VAR16) * ({1'b0,VAR33}) ;
VAR48 <= (VAR12[28-1:13]) + (VAR8) ;
if (VAR56) VAR36 <= 14'h0;
end
else VAR36 <= ^VAR48[15-1:15-2] ? {VAR48[15-1], {13{~VAR48[15-1]}}} : VAR48[13:0];
end
reg VAR30 ;
wire VAR52 ;
wire VAR47 ;
reg [ 32-1: 0] VAR44 ;
reg [ 16-1: 0] VAR51 ;
reg [ 32-1: 0] VAR10 ;
reg [ 8-1: 0] VAR1 ;
reg VAR53 ;
reg VAR4 ;
wire VAR18 ;
reg VAR46 ;
always @(posedge VAR39) begin
if (VAR34 == 1'b0) begin
VAR44 <= {VAR20{1'b0}} ;
VAR51 <= 16'h0 ;
VAR10 <= 32'h0 ;
VAR1 <= 8'h0 ;
VAR53 <= 1'b0 ;
VAR4 <= 1'b0 ;
VAR30 <= 1'b0 ;
VAR25 <= {VAR41+16{1'b0}} ;
VAR46 <= 1'b0 ;
end
else begin
if (VAR53 || (VAR1 == 8'd124))
VAR1 <= 8'h0 ;
end
else
VAR1 <= VAR1 + 8'h1 ;
if (VAR27 || VAR53)
VAR10 <= VAR24 ;
end
else if (|VAR10 && (VAR1 == 8'd124))
VAR10 <= VAR10 - 32'h1 ;
if (VAR30 && !VAR53)
VAR51 <= VAR40 ;
else if (!VAR38 && (|VAR51 && VAR4 && (VAR18 && !VAR53)))
VAR51 <= VAR51 - 16'h1 ;
else if (VAR38 && ((!VAR50 && VAR23==3'd2) || (VAR50 && VAR23==3'd3)))
VAR51 <= 16'h0 ;
VAR25 <= VAR45;
VAR46 <= VAR18; if (VAR18)
VAR44 <= VAR22 ;
else if (!VAR46 && |VAR44 && ({1'b0,VAR25} > {1'b0,VAR45}))
VAR44 <= VAR44 - 32'h1 ;
case (VAR23)
3'd1 : VAR30 <= VAR28 ; 3'd2 : VAR30 <= VAR52 ; 3'd3 : VAR30 <= VAR47 ; 3'd4 : VAR30 <= VAR50 ; 3'd5 : VAR30 <= 1'b1 ;
default : VAR30 <= 1'b0 ;
endcase
if (VAR18 && !VAR27)
VAR53 <= 1'b1 ;
else if (VAR27 || ((VAR44==32'h1) && ~VAR55) )
VAR53 <= 1'b0 ;
if (VAR18 && !VAR27)
VAR4 <= 1'b1 ;
else if (VAR27 || (VAR51==16'h0))
VAR4 <= 1'b0 ;
end
end
assign VAR18 = (!VAR4 && VAR30) || (VAR4 && |VAR51 && (VAR10 == 32'h0)) ;
assign VAR54 = VAR26 - {1'b0,VAR49} - 1;
assign VAR55 = VAR54[VAR41+16];
always @(posedge VAR39)
if (VAR34 == 1'b0) begin
VAR45 <= {VAR41+16{1'b0}};
end else begin
if (VAR27 || (VAR18 && !VAR53)) VAR45 <= VAR7;
end
else if (VAR53) begin
end
if (~VAR55) VAR45 <= VAR43 ? VAR54 : VAR7; else VAR45 <= VAR26[VAR41+16-1:0]; end
end
assign VAR26 = VAR45 + VAR31;
assign VAR21 = (!VAR4 && VAR30) | (~VAR55);
reg [ 3-1: 0] VAR17 ;
reg [ 2-1: 0] VAR19 ;
reg [ 2-1: 0] VAR37 ;
reg [ 20-1: 0] VAR35 ;
reg [ 20-1: 0] VAR14 ;
always @(posedge VAR39) begin
if (VAR34 == 1'b0) begin
VAR17 <= 3'h0 ;
VAR19 <= 2'h0 ;
VAR37 <= 2'h0 ;
VAR35 <= 20'h0 ;
VAR14 <= 20'h0 ;
end
else begin
VAR17 <= {VAR17[1:0],VAR50} ;
if ((VAR35 == 20'h0) && (VAR17[1] && !VAR17[2]))
end
VAR35 <= 20'd62500 ; else if (VAR35 != 20'h0)
VAR35 <= VAR35 - 20'd1 ;
if ((VAR14 == 20'h0) && (!VAR17[1] && VAR17[2]))
end
VAR14 <= 20'd62500 ; else if (VAR14 != 20'h0)
VAR14 <= VAR14 - 20'd1 ;
VAR19[1] <= VAR19[0] ;
if (VAR35 == 20'h0)
VAR19[0] <= VAR17[1] ;
VAR37[1] <= VAR37[0] ;
if (VAR14 == 20'h0)
VAR37[0] <= VAR17[1] ;
end
end
assign VAR52 = (VAR19 == 2'b01) ;
assign VAR47 = (VAR37 == 2'b10) ;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o_0.v | 2,348 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR11 ,
VAR5 ,
VAR6 ,
VAR1,
VAR9,
VAR7 ,
VAR10
);
output VAR4 ;
input VAR2 ;
input VAR11 ;
input VAR5 ;
input VAR6 ;
input VAR1;
input VAR9;
input VAR7 ;
input VAR10 ;
VAR8 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR4 ,
VAR2,
VAR11,
VAR5,
VAR6
);
output VAR4 ;
input VAR2;
input VAR11;
input VAR5;
input VAR6;
supply1 VAR1;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR10 ;
VAR8 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/VGA_Display.v | 1,667 | module MODULE1(VAR6, VAR2, VAR10, VAR11, VAR7, VAR9, VAR13, VAR3);
input [9:0] VAR6, VAR11;
input [8:0] VAR2, VAR10, VAR7;
output reg VAR9, VAR13, VAR3;
always @(*) begin
if( (VAR6 < 10'd640) && (VAR2 < 10'd480) )
begin
if( (VAR6 > VAR8) && (VAR6 < VAR8 + VAR4) &&
(VAR2 > VAR10) && (VAR2 < (VAR10 + VAR12)) ||
(VAR6 > VAR11) && (VAR6 < (VAR11 + VAR5)) &&
(VAR2 > VAR7) && (VAR2 < (VAR7 + VAR1))
)
begin
VAR9 <= 1'b0;
VAR13 <= 1'b0;
VAR3 <= 1'b1;
end
else
begin
VAR9 <= 1'b1;
VAR13 <= 1'b1;
VAR3 <= 1'b1;
end
end
else
begin
VAR9 <= 1'b0;
VAR13 <= 1'b0;
VAR3 <= 1'b0;
end
end
endmodule | mit |
Octoate/CPCCartridge | emulation/acid.v | 2,027 | module MODULE1(VAR8, VAR1, VAR7, VAR3, VAR6);
input VAR8;
input [7:0]VAR1;
input VAR7;
input VAR3;
output [7:0]VAR6;
wire VAR8;
reg [16:0]VAR2 = 17'h1FFFF;
wire [16:0]VAR4;
wire [16:0]VAR5;
assign VAR4 = 17'h13596 ^ (VAR1[0] ? 17'h0000c : 0)
^ (VAR1[1] ? 17'h06000 : 0)
^ (VAR1[2] ? 17'h000c0 : 0)
^ (VAR1[3] ? 17'h00030 : 0)
^ (VAR1[4] ? 17'h18000 : 0)
^ (VAR1[5] ? 17'h00003 : 0)
^ (VAR1[6] ? 17'h00600 : 0)
^ (VAR1[7] ? 17'h01800 : 0);
assign VAR5 = 17'h0C820 ^ (VAR1[0] ? 17'h00004 : 0)
^ (VAR1[1] ? 17'h06000 : 0)
^ (VAR1[2] ? 17'h00080 : 0)
^ (VAR1[3] ? 17'h00020 : 0)
^ (VAR1[4] ? 17'h08000 : 0)
^ (VAR1[5] ? 17'h00000 : 0)
^ (VAR1[6] ? 17'h00000 : 0)
^ (VAR1[7] ? 17'h00800 : 0);
always@(negedge VAR8)
begin
if (VAR3) begin
if (!VAR7 && ((VAR2 | 17'h00100) == VAR4))
begin
VAR2 <= (VAR2 ^ VAR5) >> 1;
VAR2[16] <= VAR2[0] ^ VAR2[9] ^ VAR2[12] ^ VAR2[16] ^ VAR5[0]; end
else
begin
VAR2 <= VAR2 >> 1;
VAR2[16] <= VAR2[0] ^ VAR2[9] ^ VAR2[12] ^ VAR2[16];
end
end
else
begin
VAR2 <= 17'h1FFFF;
end
end
assign VAR6 = VAR2[7:0];
endmodule | mit |
google/bbcpu | shl8.v | 1,185 | module MODULE1(
input [7 : 0] VAR1,
input [2 : 0] VAR3,
output [7 : 0] VAR2,
output VAR4);
assign {VAR4, VAR2} = (VAR3 == 3'b000) ? {1'b0, VAR1} :
(VAR3 == 3'b001) ? {VAR1[7 : 0], {1'b0}}:
(VAR3 == 3'b010) ? {VAR1[6 : 0], {2'b0}}:
(VAR3 == 3'b011) ? {VAR1[5 : 0], {3'b0}}:
(VAR3 == 3'b100) ? {VAR1[4 : 0], {4'b0}}:
(VAR3 == 3'b101) ? {VAR1[3 : 0], {5'b0}}:
(VAR3 == 3'b110) ? {VAR1[2 : 0], {6'b0}}:
{VAR1[1 : 0], {7'b0}};
endmodule | apache-2.0 |
SymbiFlow/yosys | techlibs/intel/cyclone10lp/cells_arith.v | 2,704 | module MODULE1(
module 80alteraa10gxalu (VAR28, VAR23, VAR22, VAR17, VAR9, VAR15, VAR1);
parameter VAR7 = 0;
parameter VAR30 = 0;
parameter VAR8 = 1;
parameter VAR5 = 1;
parameter VAR19 = 1;
input [VAR8-1:0] VAR28;
input [VAR5-1:0] VAR23;
output [VAR19-1:0] VAR9, VAR15;
input VAR22, VAR17;
output VAR1;
wire VAR11 = VAR19 <= 4;
wire [VAR19-1:0] VAR35, VAR16;
\pos #(.VAR7(VAR7), .VAR8(VAR8), .VAR19(VAR19)) VAR13 (.VAR28(VAR28), .VAR15(VAR35));
\pos #(.VAR7(VAR30), .VAR8(VAR5), .VAR19(VAR19)) VAR4 (.VAR28(VAR23), .VAR15(VAR16));
wire [VAR19-1:0] VAR31 = VAR35;
wire [VAR19-1:0] VAR21 = VAR17 ? ~VAR16 : VAR16;
wire [VAR19+1:0] VAR24;
wire [VAR19+1:0] VAR27 = {VAR24, VAR22};
VAR14 #(.VAR6(16'b0000000010101010), .VAR10("VAR32")) VAR29 (.VAR26(VAR24[0]), .VAR20(VAR27[0]), .VAR34(1'b1), .VAR33(1'b1), .VAR36(1'b1));
genvar VAR18;
generate for (VAR18 = 0; VAR18 < VAR19; VAR18 = VAR18 + 1) begin: VAR3
if(VAR18==VAR19-1) begin
VAR14 #(.VAR6(16'b1111000011100000), .VAR10("VAR32")) VAR2 (.VAR12(VAR24[VAR19]), .VAR20(1'b1), .VAR34(1'b1), .VAR33(1'b1), .VAR36(1'b1), .VAR32(VAR27[VAR19]));
assign VAR1 = VAR24[VAR19];
end
else
VAR14 #(.VAR6(16'b1001011011101000), .VAR10("VAR32")) VAR25 (.VAR12(VAR15[VAR18]), .VAR26(VAR24[VAR18+1]), .VAR20(VAR31[VAR18]), .VAR34(VAR21[VAR18]), .VAR33(1'b1), .VAR36(1'b1), .VAR32(VAR27[VAR18+1]));
end: VAR3
endgenerate
assign VAR9 = VAR31 ^ VAR21;
endmodule | isc |
saiedhk/WhirlpoolHashEngine | whirlpool_wcipher_sbox.v | 3,849 | module MODULE1 (
output reg [7:0 ] VAR3,
input [7:0 ] VAR7
);
reg [3:0] VAR2, VAR8, VAR4;
wire [3:0] VAR5, VAR6, VAR1;
always @*
begin
case (VAR7[3:0])
4'h0: VAR2 = 4'hF;
4'h1: VAR2 = 4'h0;
4'h2: VAR2 = 4'hD;
4'h3: VAR2 = 4'h7;
4'h4: VAR2 = 4'hB;
4'h5: VAR2 = 4'hE;
4'h6: VAR2 = 4'h5;
4'h7: VAR2 = 4'hA;
4'h8: VAR2 = 4'h9;
4'h9: VAR2 = 4'h2;
4'hA: VAR2 = 4'hC;
4'hB: VAR2 = 4'h1;
4'hC: VAR2 = 4'h3;
4'hD: VAR2 = 4'h4;
4'hE: VAR2 = 4'h8;
4'hF: VAR2 = 4'h6;
endcase
end
always @*
begin
case (VAR7[7:4])
4'h0: VAR8 = 4'h1;
4'h1: VAR8 = 4'hB;
4'h2: VAR8 = 4'h9;
4'h3: VAR8 = 4'hC;
4'h4: VAR8 = 4'hD;
4'h5: VAR8 = 4'h6;
4'h6: VAR8 = 4'hF;
4'h7: VAR8 = 4'h3;
4'h8: VAR8 = 4'hE;
4'h9: VAR8 = 4'h8;
4'hA: VAR8 = 4'h7;
4'hB: VAR8 = 4'h4;
4'hC: VAR8 = 4'hA;
4'hD: VAR8 = 4'h2;
4'hE: VAR8 = 4'h5;
4'hF: VAR8 = 4'h0;
endcase
end
always @*
begin
case (VAR5[3:0])
4'h0: VAR4 = 4'h7;
4'h1: VAR4 = 4'hC;
4'h2: VAR4 = 4'hB;
4'h3: VAR4 = 4'hD;
4'h4: VAR4 = 4'hE;
4'h5: VAR4 = 4'h4;
4'h6: VAR4 = 4'h9;
4'h7: VAR4 = 4'hF;
4'h8: VAR4 = 4'h6;
4'h9: VAR4 = 4'h3;
4'hA: VAR4 = 4'h8;
4'hB: VAR4 = 4'hA;
4'hC: VAR4 = 4'h2;
4'hD: VAR4 = 4'h5;
4'hE: VAR4 = 4'h1;
4'hF: VAR4 = 4'h0;
endcase
end
assign VAR5[3:0] = { VAR2[3]^VAR8[3] , VAR2[2]^VAR8[2] , VAR2[1]^VAR8[1] , VAR2[0]^VAR8[0] };
assign VAR6[3:0] = { VAR2[3]^VAR4[3] , VAR2[2]^VAR4[2] , VAR2[1]^VAR4[1] , VAR2[0]^VAR4[0] };
assign VAR1[3:0] = { VAR4[3]^VAR8[3] , VAR4[2]^VAR8[2] , VAR4[1]^VAR8[1] , VAR4[0]^VAR8[0] };
always @*
begin
case (VAR6[3:0])
4'h0: VAR3[3:0] = 4'hF;
4'h1: VAR3[3:0] = 4'h0;
4'h2: VAR3[3:0] = 4'hD;
4'h3: VAR3[3:0] = 4'h7;
4'h4: VAR3[3:0] = 4'hB;
4'h5: VAR3[3:0] = 4'hE;
4'h6: VAR3[3:0] = 4'h5;
4'h7: VAR3[3:0] = 4'hA;
4'h8: VAR3[3:0] = 4'h9;
4'h9: VAR3[3:0] = 4'h2;
4'hA: VAR3[3:0] = 4'hC;
4'hB: VAR3[3:0] = 4'h1;
4'hC: VAR3[3:0] = 4'h3;
4'hD: VAR3[3:0] = 4'h4;
4'hE: VAR3[3:0] = 4'h8;
4'hF: VAR3[3:0] = 4'h6;
endcase
end
always @*
begin
case (VAR1[3:0])
4'h0: VAR3[7:4] = 4'h1;
4'h1: VAR3[7:4] = 4'hB;
4'h2: VAR3[7:4] = 4'h9;
4'h3: VAR3[7:4] = 4'hC;
4'h4: VAR3[7:4] = 4'hD;
4'h5: VAR3[7:4] = 4'h6;
4'h6: VAR3[7:4] = 4'hF;
4'h7: VAR3[7:4] = 4'h3;
4'h8: VAR3[7:4] = 4'hE;
4'h9: VAR3[7:4] = 4'h8;
4'hA: VAR3[7:4] = 4'h7;
4'hB: VAR3[7:4] = 4'h4;
4'hC: VAR3[7:4] = 4'hA;
4'hD: VAR3[7:4] = 4'h2;
4'hE: VAR3[7:4] = 4'h5;
4'hF: VAR3[7:4] = 4'h0;
endcase
end
endmodule | mit |
VerticalResearchGroup/miaow | src/verilog/rtl/fetch/wavegrp_info.v | 1,845 | module MODULE1 (
VAR14,
VAR7,
VAR10,
VAR16,
VAR4,
VAR5,
VAR8,
VAR17,
VAR2,
clk,
rst
);
input clk;
input rst;
input VAR14;
input [14:0] VAR7;
input [3:0] VAR10;
input [5:0] VAR16;
input [5:0] VAR8;
input VAR4;
input [5:0] VAR5;
output [5:0] VAR17;
output [3:0] VAR2;
reg [5:0] VAR17;
reg [3:0] VAR2;
reg [879:0] VAR3;
reg [39:0] VAR13;
reg VAR6;
reg [21:0] VAR12;
wire [879:0] VAR11;
VAR9 #(22) VAR1[39:0] (
VAR3, VAR13, VAR11, clk, rst
);
integer VAR15;
always @ begin
VAR13 = 40'b0;
VAR3 = VAR11;
if(VAR4) begin
VAR3[(VAR5*22)+21-:22] = 22'd0;
VAR13[VAR5] = 1'b1;
end
if (VAR14) begin
if(VAR6 == 1'b1) begin
VAR3[(VAR16*22)+21-:22] = VAR12;
VAR13[VAR16] = 1'b1;
end
else begin
VAR3[(VAR16*22)+21-:22] = {
1'b1, VAR7[14-:11], VAR16, VAR10
};
VAR13[VAR16] = 1'b1;
end
end
end
always @(VAR8 or VAR11)
begin
VAR17 = VAR11[(VAR8*22)+9-:6];
VAR2 = VAR11[(VAR8*22)+3-:4];
end
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3.behavioral.v | 1,405 | module MODULE1 (
VAR8,
VAR7
);
output VAR8;
input VAR7;
supply1 VAR3;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR6 ;
wire VAR2;
buf VAR5 (VAR2, VAR7 );
buf VAR4 (VAR8 , VAR2 );
endmodule | apache-2.0 |
alanachtenberg/CSCE-350 | Project 2/RegisterFile.v | 1,631 | module MODULE1(VAR10, VAR9, VAR8, VAR5, VAR7, VAR1, VAR4, VAR3, VAR6);
output [31:0] VAR10;
output [31:0] VAR9;
input [31:0] VAR8;
input [4:0] VAR5, VAR7, VAR1;
input VAR4, VAR3, VAR6;
reg [31:0] VAR2 [0:31];
always @(posedge VAR6)
begin
VAR2[0]=0;
VAR2[1]=0;
VAR2[2]=0;
VAR2[3]=0;
VAR2[4]=0;
VAR2[5]=0;
VAR2[6]=0;
VAR2[7]=0;
VAR2[8]=0;
VAR2[9]=0;
VAR2[10]=0;
VAR2[11]=0;
VAR2[12]=0;
VAR2[13]=0;
VAR2[14]=0;
VAR2[15]=0;
VAR2[16]=0;
VAR2[17]=0;
VAR2[18]=0;
VAR2[19]=0;
VAR2[20]=0;
VAR2[21]=0;
VAR2[22]=0;
VAR2[23]=0;
VAR2[24]=0;
VAR2[25]=0;
VAR2[26]=0;
VAR2[27]=0;
VAR2[28]=0;
VAR2[29]=0;
VAR2[30]=0;
VAR2[31]=0;
end
assign VAR10 =VAR2[VAR5];
assign VAR9 =VAR2[VAR7];
always @(negedge VAR3)
begin
if(VAR4)
begin
VAR2[VAR1] = VAR8;
end
end
always @ (VAR4 or VAR8)
begin
end
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.functional.v | 1,264 | module MODULE1( VAR9, VAR5, VAR8, VAR4 );
input VAR8, VAR9, VAR4;
output VAR5;
wire VAR10;
not VAR7( VAR10, VAR8 );
wire VAR11;
not VAR12( VAR11, VAR9 );
wire VAR3;
and VAR6( VAR3, VAR10, VAR11 );
wire VAR13;
not VAR1( VAR13, VAR4 );
or VAR2( VAR5, VAR3, VAR13 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b.symbol.v | 1,337 | module MODULE1 (
input VAR7,
input VAR2 ,
input VAR6 ,
input VAR5 ,
output VAR8
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.behavioral.pp.v | 1,187 | module MODULE1( VAR1, VAR3, VAR2, VAR4 );
input VAR1;
inout VAR2, VAR4;
output VAR3;
VAR6 VAR5(.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4));
VAR6 VAR7(.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2/sky130_fd_sc_hd__mux2.behavioral.v | 1,604 | module MODULE1 (
VAR3 ,
VAR6,
VAR8,
VAR9
);
output VAR3 ;
input VAR6;
input VAR8;
input VAR9 ;
supply1 VAR5;
supply0 VAR4;
supply1 VAR11 ;
supply0 VAR2 ;
wire VAR12;
VAR10 VAR1 (VAR12, VAR6, VAR8, VAR9 );
buf VAR7 (VAR3 , VAR12);
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/hps_sdram_p0_altdqdqs.v | 6,959 | module MODULE1 (
VAR29,
VAR26,
VAR93,
VAR83,
VAR54,
VAR42,
VAR57,
VAR12,
VAR10,
VAR86,
VAR69,
VAR71,
VAR33,
VAR3,
VAR52,
VAR92,
VAR7,
VAR84,
VAR60,
VAR19,
VAR89,
VAR30,
VAR13,
VAR27,
VAR56,
VAR31,
VAR79,
VAR44,
VAR73,
VAR75,
VAR65,
VAR14,
VAR47,
VAR24,
VAR51,
VAR43,
VAR25,
VAR8
);
input [7-1:0] VAR8;
input VAR29;
input VAR26;
input VAR93;
input VAR83;
input VAR54;
input [3:0] VAR42;
input VAR57;
output VAR12;
inout [8-1:0] VAR10;
input [2*8-1:0] VAR86;
inout VAR69;
input [2-1:0] VAR71;
inout VAR33;
input [2-1:0] VAR3;
output [2 * 2 * 8-1:0] VAR52;
output VAR92;
input [2 * 2 * 8-1:0] VAR7;
input [2 * 2 * 1-1:0] VAR84;
output [1-1:0] VAR60;
input [16-1:0] VAR19;
input [16-1:0] VAR89;
input VAR30;
input VAR13;
input VAR27;
input [8-1:0] VAR56;
input [1-1:0] VAR31;
input VAR79;
input VAR44;
input [2-1:0] VAR73;
input [2-1:0] VAR75;
input [4:0] VAR65;
input VAR14;
output VAR47;
input [2-1:0] VAR24;
input [2-1:0] VAR51;
input VAR43;
input VAR25;
parameter VAR81 = "";
VAR9 VAR40 (
.VAR29( VAR29),
.VAR26 (VAR26),
.VAR93( VAR93),
.VAR83( VAR83),
.VAR54 (VAR54),
.VAR42(VAR42),
.VAR57( VAR57),
.VAR12 (VAR12),
.VAR10( VAR10),
.VAR86( VAR86),
.VAR69( VAR69),
.VAR71( VAR71),
.VAR33( VAR33),
.VAR3( VAR3),
.VAR52( VAR52),
.VAR92( VAR92),
.VAR7( VAR7),
.VAR84( VAR84),
.VAR60( VAR60),
.VAR19( VAR19),
.VAR89( VAR89),
.VAR30( VAR30),
.VAR13( VAR13),
.VAR27( VAR27),
.VAR56( VAR56),
.VAR31( VAR31),
.VAR79( VAR79),
.VAR44( VAR44),
.VAR73(VAR73),
.VAR75(VAR75),
.VAR65(VAR65),
.VAR14(VAR14),
.VAR47(VAR47),
.VAR24(VAR24),
.VAR51(VAR51),
.VAR43(VAR43),
.VAR25(VAR25),
.VAR8(VAR8)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3.pp.symbol.v | 1,357 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR5 ,
input VAR2,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/tdc_s3/tdc_s3.v | 2,181 | module MODULE1 #(
parameter VAR11 = 16'h0000,
parameter VAR21 = 16'h0000,
parameter VAR8 = 4,
parameter VAR16 = 4'b0100,
parameter VAR7 = 16,
parameter VAR23 = 1,
parameter VAR36 = 1
)(
input wire VAR30,
input wire [VAR7-1:0] VAR22,
inout wire [7:0] VAR3,
input wire VAR17,
input wire VAR10,
input wire VAR6,
input wire VAR29,
input wire VAR34,
input wire VAR15, input wire VAR31,
output wire VAR2,
input wire VAR19,
output wire VAR28,
input wire VAR35,
output wire VAR26,
output wire [31:0] VAR20,
input wire VAR12,
input wire VAR24,
input wire [15:0] VAR13
);
wire VAR5, VAR33;
wire [VAR7-1:0] VAR14;
wire [7:0] VAR9;
wire [7:0] VAR18;
VAR25 #(
.VAR11(VAR11),
.VAR21(VAR21),
.VAR7(VAR7)
) VAR27 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR22(VAR22),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR33(VAR33),
.VAR14(VAR14),
.VAR9(VAR9),
.VAR18(VAR18)
);
VAR1 #(
.VAR16(VAR16),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR23(VAR23),
.VAR36(VAR36)
) VAR37 (
.VAR30(VAR30),
.VAR17(VAR17),
.VAR22(VAR14),
.VAR32(VAR9),
.VAR6(VAR5),
.VAR10(VAR33),
.VAR4(VAR18),
.VAR29(VAR29),
.VAR34(VAR34),
.VAR15(VAR15),
.VAR31(VAR31),
.VAR2(VAR2),
.VAR19(VAR19),
.VAR28(VAR28),
.VAR35(VAR35),
.VAR26(VAR26),
.VAR20(VAR20),
.VAR12(VAR12),
.VAR24(VAR24),
.VAR13(VAR13)
);
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3.pp.blackbox.v | 1,317 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR4,
VAR2,
VAR3 ,
VAR5
);
output VAR1 ;
input VAR6 ;
input VAR4;
input VAR2;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_dpram_32x32.v | 14,103 | module MODULE1(
VAR130, VAR141, VAR48, VAR13, VAR128, VAR110,
VAR105, VAR126, VAR56, VAR80, VAR2, VAR135
);
parameter VAR39 = 5;
parameter VAR100 = 32;
input VAR130; input VAR141; input VAR48; input VAR13; input [VAR39-1:0] VAR128; output [VAR100-1:0] VAR110; input VAR105; input VAR126; input VAR56; input VAR80; input [VAR39-1:0] VAR2; input [VAR100-1:0] VAR135;
VAR146 #(VAR100, 1<<VAR39, VAR39) VAR1(
VAR146 VAR1(
.VAR107(VAR110),
.VAR130(VAR130),
.VAR15(~VAR48),
.VAR164(1'b1),
.VAR75(VAR128),
.VAR165(32'h00000000),
.VAR125(~VAR13),
.VAR47(),
.VAR105(VAR105),
.VAR137(~VAR56),
.VAR161(~VAR80),
.VAR71(VAR2),
.VAR118(VAR135),
.VAR77(1'b1)
);
VAR167 VAR167(
.VAR80(~VAR109),
.VAR103(),
.VAR22(~VAR121),
.VAR154(),
.VAR29(),
.VAR92(addr),
.VAR85(addr),
.VAR84(VAR84),
.VAR163(VAR163)
);
VAR170 VAR170(
.VAR159(VAR110),
.VAR136(),
.VAR60(VAR128),
.VAR62(32'h00000000),
.VAR30(1'b0),
.VAR52(VAR13),
.VAR131(VAR48),
.VAR112(VAR130),
.VAR40(VAR2),
.VAR12(VAR135),
.VAR122(VAR80),
.VAR119(1'b1),
.VAR111(VAR56),
.VAR96(VAR105)
);
VAR155 #(1<<VAR39, VAR39-1, VAR100-1) VAR127(
VAR155 VAR127(
.VAR129(VAR130),
.VAR65(~VAR48),
.VAR41(1'b1),
.VAR169(~VAR13),
.VAR54({1'b0, VAR128}),
.VAR147(32'h00000000),
.VAR34(VAR110),
.VAR171(VAR105),
.VAR6(~VAR56),
.VAR49(~VAR56),
.VAR133(1'b1),
.VAR97({1'b0, VAR2}),
.VAR31(VAR135),
.VAR151()
);
VAR44 #(1<<VAR39, VAR39-1, VAR100-1) VAR127(
VAR44 VAR127(
.VAR4(VAR130),
.VAR94(~VAR48),
.VAR23(~VAR13),
.VAR113(VAR128),
.VAR98(VAR110),
.VAR46(VAR105),
.VAR124(~VAR56),
.VAR38(VAR2),
.VAR67(VAR135)
);
reg [4:0] VAR78;
always @(posedge VAR130 or VAR123 VAR141)
if (VAR141 == VAR9)
VAR78 <= 5'b00000;
else if (VAR48)
VAR78 <= VAR128;
VAR7 VAR24 (
.VAR145(VAR110[7:0]),
.VAR42(),
.VAR114(VAR2),
.VAR55(VAR135[7:0]),
.VAR5(VAR78),
.VAR157(VAR105),
.VAR90(VAR80)
);
VAR7 VAR108 (
.VAR145(VAR110[15:8]),
.VAR42(),
.VAR114(VAR2),
.VAR55(VAR135[15:8]),
.VAR5(VAR78),
.VAR157(VAR105),
.VAR90(VAR80)
);
VAR7 VAR28 (
.VAR145(VAR110[23:16]),
.VAR42(),
.VAR114(VAR2),
.VAR55(VAR135[23:16]),
.VAR5(VAR78),
.VAR157(VAR105),
.VAR90(VAR80)
);
VAR7 VAR134 (
.VAR145(VAR110[31:24]),
.VAR42(),
.VAR114(VAR2),
.VAR55(VAR135[31:24]),
.VAR5(VAR78),
.VAR157(VAR105),
.VAR90(VAR80)
);
VAR45 VAR140(
.VAR112(VAR130),
.VAR74(1'b0),
.VAR148({3'b000, VAR128}),
.VAR116(16'h0000),
.VAR36(VAR48),
.VAR30(1'b0),
.VAR149(VAR110[15:0]),
.VAR96(VAR105),
.VAR18(1'b0),
.VAR26({3'b000, VAR2}),
.VAR87(VAR135[15:0]),
.VAR106(VAR56),
.VAR122(VAR80),
.VAR93()
);
VAR45 VAR160(
.VAR112(VAR130),
.VAR74(1'b0),
.VAR148({3'b000, VAR128}),
.VAR116(16'h0000),
.VAR36(VAR48),
.VAR30(1'b0),
.VAR149(VAR110[31:16]),
.VAR96(VAR105),
.VAR18(1'b0),
.VAR26({3'b000, VAR2}),
.VAR87(VAR135[31:16]),
.VAR106(VAR56),
.VAR122(VAR80),
.VAR93()
);
VAR104 VAR158(
.VAR112(VAR130),
.VAR57(1'b0),
.VAR148({4'b0000, VAR128}),
.VAR116(32'h00000000),
.VAR20(4'h0),
.VAR36(VAR48),
.VAR30(1'b0),
.VAR149(VAR110),
.VAR81(),
.VAR96(VAR105),
.VAR33(1'b0),
.VAR26({4'b0000, VAR2}),
.VAR87(VAR135),
.VAR95(4'h0),
.VAR106(VAR56),
.VAR122(VAR80),
.VAR93(),
.VAR101()
);
VAR43 VAR50 (
.VAR3 (VAR128),
.VAR11 (VAR48),
.VAR70 (VAR2),
.VAR138 (VAR17),
.VAR21 (VAR56),
.VAR69 (VAR80),
.VAR61 (1'b0),
.VAR10 (1'b0),
.VAR89 (VAR130),
.VAR117 (VAR105),
.VAR99 (VAR168),
.VAR59 (VAR135),
.VAR107 (VAR110),
.VAR47 (VAR73)
);
VAR50.VAR142 = VAR100,
VAR50.VAR86 = VAR39,
VAR50.VAR63 = VAR100,
VAR50.VAR152 = VAR100,
VAR50.VAR37 = VAR39,
VAR50.VAR91 = VAR100,
VAR50.VAR120 = VAR100,
VAR50.VAR8 = VAR39,
VAR50.VAR143 = VAR100,
VAR50.VAR58 = VAR100,
VAR50.VAR156 = VAR39,
VAR50.VAR76 = VAR100,
VAR50.VAR19 = "VAR162",
VAR50.VAR82 = "VAR162",
VAR50.VAR72 = "VAR162",
VAR50.VAR32 = "VAR166",
VAR50.VAR150 = "VAR166",
VAR50.VAR14 = "VAR166",
VAR50.VAR16 = "VAR25",
VAR50.VAR88 = "VAR25",
VAR50.VAR153 = "VAR25",
VAR50.VAR139 = "VAR25",
VAR50.VAR51 = "VAR35",
VAR50.VAR53 = "VAR35",
VAR50.VAR115 = "VAR35",
VAR50.VAR27 = "VAR68",
VAR50.VAR66 = "VAR83=VAR132";
reg [VAR100-1:0] VAR102 [(1<<VAR39)-1:0]; reg [VAR39-1:0] VAR64;
assign VAR110 = (VAR13) ? VAR102[VAR64] : {VAR100{1'b0}};
always @(posedge VAR130 or VAR123 VAR141)
if (VAR141 == VAR9)
VAR64 <= {VAR39{1'b0}};
else if (VAR48)
VAR64 <= VAR128;
always @(posedge VAR105)
if (VAR56 && VAR80)
VAR102[VAR2] <= VAR135;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.functional.pp.v | 2,082 | module MODULE1 (
VAR17 ,
VAR10 ,
VAR2 ,
VAR8 ,
VAR4 ,
VAR19 ,
VAR12,
VAR3,
VAR13 ,
VAR14
);
output VAR17 ;
output VAR10 ;
input VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR19 ;
input VAR12;
input VAR3;
input VAR13 ;
input VAR14 ;
wire VAR9 ;
wire VAR15;
VAR16 VAR11 (VAR15, VAR8, VAR4, VAR19 );
VAR5 VAR7 VAR1 (VAR9 , VAR15, VAR2, , VAR12, VAR3);
buf VAR6 (VAR17 , VAR9 );
not VAR18 (VAR10 , VAR9 );
endmodule | apache-2.0 |
Elphel/x393_sata | ahci/ahci_fsm.v | 38,602 | module MODULE1
(
input VAR2, input VAR120, input VAR81, input VAR5,
input VAR169,
input VAR65,
input [17:0] VAR12, input VAR17, input VAR237,
input [1:0] VAR87, output VAR99, input VAR178, output VAR161, input VAR271, output VAR188, output VAR131, output VAR263,
output VAR258, output VAR89, input VAR72,
output VAR145, output VAR59,
input VAR20, input VAR75, input VAR121,
output VAR94, output VAR239, output VAR205, output VAR71, output VAR214, output VAR171, output VAR126, output VAR4, output VAR112, output VAR202, output VAR90, output VAR189, input VAR150,
output VAR139, output VAR62, output VAR38, output VAR269, output VAR137,
output VAR180, output VAR281, output VAR193, output VAR140,
output VAR254, output VAR276, output VAR218, output VAR216, input [3:0] VAR54,
input [3:0] VAR133, input VAR262, output VAR109,
output VAR95,
output VAR42, input VAR240,
output VAR176, input VAR57, input VAR22, output VAR206, input VAR234,
input VAR170, output VAR67,
input VAR184, input [7:0] VAR148, input [7:0] VAR60,
output VAR247,
output VAR80,
output VAR13,
output VAR8,
output VAR125,
output VAR153,
output VAR275, input VAR272, input VAR102, input VAR259, input VAR27, input VAR160,
output VAR48, output VAR203,
output VAR167, output VAR146,
output VAR158, output VAR212, output VAR242,
output VAR68, output VAR50, output VAR14, output VAR46,
output VAR198, output VAR142, input VAR10, input VAR261, input [7:0] VAR104, input VAR251, input VAR215, input VAR159, input VAR91, input VAR141,
output VAR3, output VAR84, output VAR264, output VAR61, input VAR257,
output VAR6, input VAR201, input [ 2:0] VAR40,
input VAR39, input VAR250, input VAR76, input VAR204, input VAR179, input VAR128, input VAR101,
output reg [ 9:0] VAR138
);
localparam VAR100 = 11'h002;
localparam VAR191 = 11'h004;
localparam VAR224 = 11'h006;
localparam VAR93 = 11'h008;
wire VAR73 = VAR104[7];
wire VAR43 = VAR104[3];
wire VAR107 = VAR104[0];
reg [ 9:0] VAR210;
wire VAR177; reg [ 9:0] VAR15;
reg [ 9:0] VAR9;
wire [17:0] VAR18;
reg VAR246;
reg [2:0] VAR37;
wire VAR238;
reg VAR213; reg VAR236; reg VAR123;
reg [1:0] VAR115; reg VAR74; wire VAR243 = (|VAR192) ? VAR52 : (VAR177 & VAR115[1]);
wire VAR113 = VAR272 ||
VAR257 ||
(VAR175 && VAR178) ||
VAR234 ||
VAR129; reg VAR228; reg VAR267;
wire VAR220 = VAR18[16]; wire VAR255 = VAR18[17];
wire VAR92 = !VAR236 && VAR213 && VAR238;
reg [1:0] VAR192; reg VAR265; wire VAR129 = (VAR271 && VAR101) || VAR121;
wire VAR52 = !VAR74 && VAR192[0] && ((VAR213 && !VAR72 && !VAR123) || VAR115[0]); reg VAR175; reg [1:0] VAR106; reg VAR181; wire VAR11 = !VAR2 && !VAR246 && (VAR87 != VAR106);
reg VAR211;
wire VAR200 = (VAR255 && VAR213 && VAR238 && !VAR220) ||
(VAR123 && VAR228 && VAR211);
wire VAR223 = !VAR200 && !VAR115[0];
reg VAR98; wire VAR24;
assign VAR238 = (VAR74 || (VAR213 && !VAR72 && !VAR123) || VAR115[0]) && !VAR192[0]; assign VAR89 = VAR37[0];
assign VAR139 = VAR181 && (VAR106 == 0); assign VAR62 = VAR181 && (VAR106 != 0); assign VAR38 = 0; assign VAR269 = 0; assign VAR137 = 0;
assign VAR180 = VAR181 && (VAR106 == 0); assign VAR281 = VAR181 && (VAR106 == 1); assign VAR193 = VAR181 && (VAR106 == 2); assign VAR140 = VAR181 && (VAR106 == 3);
assign VAR254 = VAR181 && (VAR106 == 0); assign VAR218 = VAR181 && (VAR106 != 0);
assign VAR71 = 0; assign VAR214 = VAR181;
always @ (posedge VAR169) begin
if (VAR65) VAR210 <= 0;
end
else if (VAR17) VAR210 <= VAR12[ 9:0];
else if (VAR237) VAR210 <= VAR210 + 1;
end
always @ (posedge VAR120) begin
if (VAR2 || VAR42 || VAR24) VAR98 <= 0;
end
else if (VAR3) VAR98 <= 1;
end
always @ (posedge VAR120) begin
if (VAR2) VAR15 <= (VAR81 || VAR5) ? (VAR81? VAR100:VAR191) : VAR127;
end
else if (VAR192[0]) VAR15 <= VAR265? VAR93 : VAR224;
else if (VAR115[0] && (!VAR177 || !VAR115[1])) VAR15 <= VAR18[9:0];
VAR246 <= VAR2;
VAR267 <= VAR113; VAR228 <= VAR267; VAR37 <= {VAR37[1:0], VAR243 | (VAR246 & ~VAR2)};
if (VAR37[0]) VAR9 <= VAR15;
else if (VAR238) VAR9 <= VAR9 + 1;
if (VAR37[0]) VAR138 <= VAR15;
if (VAR2) VAR213 <= 0;
else if (VAR37[2]) VAR213 <= 1;
else if (VAR255 && VAR238) VAR213 <= 0;
if (VAR2) VAR236 <= 0;
else if (|VAR192) VAR236 <= 1;
else if (VAR37[2]) VAR236 <= 0;
if (VAR213 && VAR238) VAR211 <= VAR255;
if (VAR2 || VAR243 || VAR236) VAR115 <= 0;
else if (VAR200) VAR115 <= 1;
else VAR115 <= {VAR115[0],VAR115[0]};
if (VAR2) VAR74 <= 0;
else VAR74 <= |VAR37[1:0];
if (VAR2) VAR123 <= 0;
else if (VAR92) VAR123 <= VAR220;
else if (VAR228) VAR123 <= 0;
if (VAR2) VAR265 <= 0;
else if (VAR121) VAR265 <= 1;
else if (VAR129) VAR265 <= 0;
if (VAR2) VAR192 <= 0;
else VAR192 <= {VAR192[0], (VAR129 | VAR192[0]) & ~VAR52};
if (VAR2 || VAR178) VAR175 <= 0;
else if (VAR99) VAR175 <= 1;
if (VAR246 && !VAR2 && !VAR81 && !VAR5) VAR106 <= 0;
else if (VAR11) VAR106 <= VAR87;
VAR181 <= VAR11;
end
VAR280 #(
.VAR55(1),
.VAR241(4),
.VAR248(4)
) VAR53 (
.VAR187 (VAR120), .VAR117 (VAR9), .VAR156 (VAR238), .VAR44 (VAR238), .VAR105 (VAR18), .VAR26 (VAR169), .VAR119 (VAR210), .VAR270 (VAR237), .VAR19 (4'hf), .VAR151 (VAR12) );
VAR163 VAR278 (
.clk (VAR120), .enable (VAR92), .VAR207 (VAR18[10:0]), .VAR77 (VAR171), .VAR147 (VAR189), .VAR124 (VAR126), .VAR70 (VAR202), .VAR225 (VAR239), .VAR136 (VAR205), .VAR103 (VAR90), .VAR79 (VAR112), .VAR233 (VAR94), .VAR152 (VAR4), .VAR56 (VAR258), .VAR235 (VAR59), .VAR122 (VAR145), .VAR114 (VAR42), .VAR132 (VAR276), .VAR219 (VAR216), .VAR282 (VAR109), .VAR21 (VAR95), .VAR154 (VAR48), .VAR155 (VAR203), .VAR29 (VAR167), .VAR45 (VAR146), .VAR208 (VAR158), .VAR96 (VAR212), .VAR149 (VAR242), .VAR244 (VAR68), .VAR277 (VAR50), .VAR245 (VAR14), .VAR256 (VAR46), .VAR97 (VAR198), .VAR30 (VAR142), .VAR36 (VAR67), .VAR172 (VAR6), .VAR35 (VAR206), .VAR25 (VAR176), .VAR217 (VAR161), .VAR69 (VAR99), .VAR182 (VAR188), .VAR130 (VAR131), .VAR16 (VAR263), .VAR168 (VAR24), .VAR78 (VAR3), .VAR58 (VAR61), .VAR231 (VAR84), .VAR199 (VAR264), .VAR83 (VAR153), .VAR221 (VAR247), .VAR268 (VAR275), .VAR157 (VAR80), .VAR232 (VAR13), .VAR66 (VAR8), .VAR164 (VAR125) );
VAR162 VAR227 (
.clk (VAR120), .VAR209 (VAR223), .sel (VAR18[17:10]), .VAR85 (VAR177), .VAR230 (VAR75 && !VAR73 &&!VAR43), .VAR226 (VAR240 && !VAR98), .VAR47 (VAR201 && VAR141 && VAR76 ), .VAR197 (VAR201 && VAR141), .VAR88 (!VAR75 && (VAR148 == VAR190)), .VAR32 (!VAR91 && !VAR128), .VAR28 (VAR179 && VAR215), .VAR173 (VAR262 && (VAR133 == 4)), .VAR266 (VAR262 && (VAR133 == 1)), .VAR166 (VAR54 != 3), .VAR222 (VAR54 == 1), .VAR33 (!VAR10), .VAR174 (VAR102), .VAR253 (VAR259), .VAR260 (VAR27), .VAR273 (VAR160), .VAR31 (VAR170), .VAR41 (VAR184 && (VAR148 == VAR190)), .VAR135 (VAR184 && (VAR148 == VAR135)), .VAR110 (VAR184), .VAR194 (((VAR148 == VAR190) || (VAR148 == VAR82)) && !VAR73 && !VAR43), .VAR63 ( VAR148 == VAR190), .VAR249 ( VAR148 == VAR51), .VAR143 ( VAR148 == VAR134), .VAR279 ( VAR148 == VAR23), .VAR195 (( VAR148 == VAR186) && (|VAR60)), .VAR118 (( VAR148 == VAR186)), .VAR108 ( VAR148 == VAR82), .VAR64 (!VAR73 &&!VAR43), .VAR229 ( VAR107), .VAR7 (VAR251), .VAR196 (VAR159), .VAR183 (!VAR91), .VAR49 (VAR261), .VAR144 (VAR141 && !VAR22), .VAR116 (VAR261 && VAR141 &&!VAR22), .VAR86 (VAR128 && VAR204), .VAR1 (VAR204), .VAR185 (VAR250), .VAR274 (VAR39), .VAR111 (VAR40[1]), .VAR252 (VAR40[0]), .VAR34 (VAR57), .VAR165 (VAR40[2]) );
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.v | 2,284 | module MODULE2 (
VAR7 ,
VAR5,
VAR4,
VAR2 ,
VAR3 ,
VAR1,
VAR6
);
output VAR7 ;
input VAR5;
input VAR4;
input VAR2 ;
input VAR3 ;
input VAR1;
input VAR6;
VAR9 VAR8 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7 ,
VAR5,
VAR4,
VAR2 ,
VAR3
);
output VAR7 ;
input VAR5;
input VAR4;
input VAR2 ;
input VAR3 ;
supply1 VAR1;
supply0 VAR6;
VAR9 VAR8 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.functional.v | 1,676 | module MODULE1( VAR7, VAR18, VAR16, VAR20, VAR14, VAR15 );
input VAR14, VAR15, VAR18, VAR7, VAR20;
output VAR16;
wire VAR9;
not VAR13( VAR9, VAR14 );
wire VAR12;
not VAR6( VAR12, VAR15 );
wire VAR8;
and VAR4( VAR8, VAR9, VAR12 );
wire VAR21;
not VAR1( VAR21, VAR18 );
wire VAR3;
not VAR5( VAR3, VAR7 );
wire VAR10;
and VAR19( VAR10, VAR21, VAR3 );
wire VAR2;
not VAR17( VAR2, VAR20 );
or VAR11( VAR16, VAR8, VAR10, VAR2 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_1.behavioral.pp.v | 1,239 | module MODULE1( VAR2, VAR6, VAR3, VAR8, VAR7 );
input VAR2, VAR6;
inout VAR8, VAR7;
output VAR3;
VAR5 VAR1(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7));
VAR5 VAR4(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp.functional.pp.v | 1,863 | module MODULE1 (
VAR9 ,
VAR13 ,
VAR7 ,
VAR10,
VAR2 ,
VAR12 ,
VAR5 ,
VAR15
);
output VAR9 ;
input VAR13 ;
input VAR7 ;
input VAR10;
input VAR2 ;
input VAR12 ;
input VAR5 ;
input VAR15 ;
wire VAR6;
wire VAR8;
not VAR1 (VAR8 , VAR10 );
VAR4 VAR3 VAR14 (VAR6 , VAR7, VAR13, VAR8, , VAR2, VAR12);
buf VAR11 (VAR9 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2_8.v | 2,086 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR2 ,
VAR1,
VAR5,
VAR9 ,
VAR6
);
output VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR9 ;
input VAR6 ;
VAR3 VAR4 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR8,
VAR7,
VAR2
);
output VAR8;
input VAR7;
input VAR2;
supply1 VAR1;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR6 ;
VAR3 VAR4 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
sorgelig/ZX_Spectrum-128K_MIST | sys/sd_card.v | 15,244 | module MODULE1 (
input VAR59,
output [31:0] VAR11,
output reg VAR56,
output reg VAR55,
input VAR41,
input VAR51,
output VAR42,
output VAR27,
input VAR8,
input [31:0] VAR29,
output reg VAR1 = 0,
input [7:0] VAR63,
input VAR36,
output [7:0] VAR74,
input [8:0] VAR57,
input VAR19,
input VAR31,
input VAR5,
input VAR43,
output reg VAR25
);
wire [31:0] VAR4 = { 1'b1, VAR27, 6'h0, 9'h1f, 15'h0 }; wire [7:0] VAR46 = 8'hfe;
localparam VAR32=4;
localparam VAR54 = 2'd0;
localparam VAR66 = 2'd1;
localparam VAR49 = 2'd2;
localparam VAR62 = 2'd3;
reg [1:0] VAR35 = VAR54;
localparam VAR70 = 3'd0;
localparam VAR18 = 3'd1;
localparam VAR61 = 3'd2;
localparam VAR30 = 3'd3;
localparam VAR17 = 3'd4;
localparam VAR10 = 3'd5;
localparam VAR45 = 3'd6;
reg [2:0] VAR58 = VAR70;
reg VAR2 = 1'b0; reg [6:0] VAR13;
reg VAR39;
reg [7:0] VAR48 = 8'h00;
reg [2:0] VAR67 = 3'd0; reg [3:0] VAR71= 4'd15;
reg [39:0] VAR6;
assign VAR11 = VAR27?VAR6[39:8]:{9'd0, VAR6[39:17]};
reg [7:0] VAR47;
reg [7:0] VAR9, VAR44, VAR15, VAR22;
reg [3:0] VAR3;
reg [8:0] VAR37;
wire [7:0] VAR72;
reg [7:0] VAR16;
reg VAR26;
MODULE2 #(8, 9) VAR40
(
.VAR23 (VAR59),
.VAR64 (VAR57),
.VAR68 (VAR63),
.VAR20 (VAR36 & VAR41),
.VAR52 (VAR74),
.VAR7 (VAR59),
.VAR73 (VAR37),
.VAR34 (VAR16),
.VAR12 (VAR26),
.VAR14 (VAR72)
);
wire [7:0] VAR53 = 8'h05;
reg [7:0] VAR50;
assign VAR42 = VAR75;
reg VAR75 = 1;
reg [4:0] VAR76;
reg [7:0] VAR69;
reg[255:0] VAR65;
wire VAR21 = VAR50[0];
assign VAR27 = VAR19 && VAR21;
always @(posedge VAR59) begin
reg VAR38;
if (VAR36 & VAR51) begin
if (VAR57 == 32) begin
VAR50 <= VAR63;
VAR75 <= 0;
end
else VAR65[(31-VAR57) << 3 +:8] <= VAR63;
end
VAR69 <= VAR65[(31-VAR76) << 3 +:8];
VAR38 <= VAR8;
if (~VAR38 & VAR8) begin
if (VAR27)
VAR65[69:48] <= {9'd0, VAR29[31:19] };
end
else begin
VAR65[49:47] <= 3'd7; VAR65[73:62] <= VAR29[29:18]; end
end
end
always@(posedge VAR59) begin
reg VAR60;
reg [5:0] ack;
ack <= {ack[4:0], VAR41};
if(ack[5:4] == 'b01) { VAR56, VAR55 } <= 2'b00;
if(ack[5:4] == 'b10) VAR1 <= 0;
VAR26 <= 0;
if (VAR26) VAR37 <= VAR37 + 1'd1;
VAR60 <= VAR5;
if(VAR31 == 0 && VAR60 && ~VAR5) begin
VAR25 <= 1'b1;
if(VAR71 == 5+VAR32) begin
VAR25 <= VAR47[~VAR67];
if(VAR67 == 7) begin
if((VAR48 == 8'h49)||(VAR48 == 8'h4a))
VAR35 <= VAR49;
if(VAR48 == 8'h51) begin
VAR35 <= VAR66; VAR56 <= 1; VAR1 <= 1;
end
end
end
else if((VAR3 > 0) && (VAR71 == 5+VAR32+1))
VAR25 <= VAR9[~VAR67];
end
else if((VAR3 > 1) && (VAR71 == 5+VAR32+2))
VAR25 <= VAR44[~VAR67];
end
else if((VAR3 > 2) && (VAR71 == 5+VAR32+3))
VAR25 <= VAR15[~VAR67];
else if((VAR3 > 3) && (VAR71 == 5+VAR32+4))
VAR25 <= VAR22[~VAR67];
else
VAR25 <= 1'b1;
case(VAR35)
VAR54: ;
VAR66: begin
VAR37 <= 0;
if(~VAR1 && (VAR67 == 7))
VAR35 <= VAR49;
end
VAR49: begin
VAR25 <= VAR46[~VAR67];
if(VAR67 == 7) begin
VAR35 <= VAR62; VAR76 <= (VAR48 == 8'h4a) ? 5'h0 : 5'h10;
end
end
VAR62: begin
if(VAR48 == 8'h51) VAR25 <= VAR72[~VAR67];
end
else if(VAR48 == 8'h49) begin VAR25 <= VAR69[~VAR67];
end
else if(VAR48 == 8'h4a) VAR25 <= VAR69[~VAR67];
else
VAR25 <= 1'b1;
if(VAR67 == 7) begin
if((VAR48 == 8'h51) && &VAR37) VAR35 <= VAR54;
end
else if(((VAR48 == 8'h49)||(VAR48 == 8'h4a)) && VAR76[3:0] == 4'h0f) VAR35 <= VAR54;
else begin
VAR37 <= VAR37 + 1'd1;
VAR76<= VAR76+ 1'd1;
end
end
end
endcase
if(VAR58 == VAR10)
VAR25 <= VAR53[~VAR67];
if(VAR58 == VAR45)
VAR25 <= 1'b0;
end
if(VAR31 == 1) begin
VAR67 <= 3'd0;
end else if (~VAR60 & VAR5) begin
VAR67 <= VAR67 + 3'd1;
if(VAR67 != 7)
VAR13[6:0] <= { VAR13[5:0], VAR43 };
end
else begin
if(VAR71 != 15)
VAR71 <= VAR71 + 4'd1;
if((VAR71 > 5) && (VAR58 == VAR70) &&
(VAR35 == VAR54) && VAR13[6:5] == 2'b01) begin
VAR71 <= 4'd0;
VAR48 <= { VAR13, VAR43};
VAR39 <= (VAR48 == 8'h77);
end
if(VAR71 == 0) VAR6[39:32] <= { VAR13, VAR43};
if(VAR71 == 1) VAR6[31:24] <= { VAR13, VAR43};
if(VAR71 == 2) VAR6[23:16] <= { VAR13, VAR43};
if(VAR71 == 3) VAR6[15:8] <= { VAR13, VAR43};
if(VAR71 == 4) VAR6[7:0] <= { VAR13, VAR43};
if(VAR71 == 5) begin
VAR47 <= 8'h04; VAR3 <= 4'd0;
if(VAR48 == 8'h40) begin
VAR2 <= 1'b1;
VAR47 <= 8'h01; end
else if(VAR2) begin
case(VAR48)
8'h41: VAR47 <= 8'h00;
8'h48: begin
VAR47 <= 8'h01; VAR9 <= 8'h00;
VAR44 <= 8'h00;
VAR15 <= { 4'b0, VAR6[19:16] };
VAR22 <= VAR6[15:8];
VAR3 <= 4'd4;
end
8'h49: VAR47 <= 8'h00;
8'h4a: VAR47 <= 8'h00;
8'h50:
if(VAR6[39:8] == 32'd512)
end
VAR47 <= 8'h00; else
VAR47 <= 8'h40;
8'h51: VAR47 <= 8'h00;
8'h58: begin
VAR47 <= 8'h00; VAR58 <= VAR18; end
8'h69: if(VAR39) begin
VAR47 <= 8'h00; end
8'h77: VAR47 <= 8'h01;
8'h7a: begin
VAR47 <= 8'h00;
VAR9 <= VAR4[31:24]; VAR44 <= VAR4[23:16];
VAR15 <= VAR4[15:8];
VAR22 <= VAR4[7:0];
VAR3 <= 4'd4;
end
endcase
end
end
case(VAR58)
VAR70: ;
VAR18:
if({ VAR13, VAR43} == 8'hfe ) begin
VAR58 <= VAR61;
VAR37 <= 9'd0;
end
VAR61: begin
VAR26 <= 1'b1;
VAR16 <= { VAR13, VAR43 };
if(&VAR37)
VAR58 <= VAR30;
end
VAR30:
VAR58 <= VAR17;
VAR17:
VAR58 <= VAR10;
VAR10: begin
VAR58 <= VAR45;
VAR55 <= 1; VAR1 <= 1;
end
VAR45:
if(~VAR1)
VAR58 <= VAR70;
default: ;
endcase
end
end
end
endmodule
module MODULE2 #(parameter VAR24=8, VAR33=9)
(
input VAR23,
input [VAR33-1:0] VAR64,
input [VAR24-1:0] VAR68,
input VAR20,
output reg [VAR24-1:0] VAR52,
input VAR7,
input [VAR33-1:0] VAR73,
input [VAR24-1:0] VAR34,
input VAR12,
output reg [VAR24-1:0] VAR14
);
reg [VAR24-1:0] VAR28[0:(1<<VAR33)-1];
always @(posedge VAR23) begin
VAR52 <= VAR28[VAR64];
if(VAR20) begin
VAR52 <= VAR68;
VAR28[VAR64] <= VAR68;
end
end
always @(posedge VAR7) begin
VAR14 <= VAR28[VAR73];
if(VAR12) begin
VAR14 <= VAR34;
VAR28[VAR73] <= VAR34;
end
end
endmodule | gpl-2.0 |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/pipe.v | 6,782 | module MODULE1 (in,out,VAR5,reset);
output out;
input in; input VAR5; input reset;
reg out;
reg o1; reg o2; reg o3; reg o4; reg o5; reg o6; reg o7; reg VAR2; reg VAR3; reg o10; reg o11; reg o12; reg o13; reg o14;
reg o15; reg o16; reg o17; reg VAR7; reg VAR1; reg o20; reg o21; reg o22; reg o23; reg o24; reg o25; reg o26; reg o27; reg VAR4; reg VAR6; reg o30; reg o31;
always @(posedge VAR5)
begin
if(reset)
o1 = 1'd0;
end
else
o1 = in;
end
always @(posedge VAR5)
begin
if(reset)
o2 = 1'd0;
end
else
o2 = o1;
end
always @(posedge VAR5)
begin
if(reset)
o3 = 1'd0;
end
else
o3 = o2;
end
always @(posedge VAR5)
begin
if(reset)
o4 = 1'd0;
end
else
o4 = o3;
end
always @(posedge VAR5)
begin
if(reset)
o5 = 1'd0;
end
else
o5 = o4;
end
always @(posedge VAR5)
begin
if(reset)
o6 = 1'd0;
end
else
o6 = o5;
end
always @(posedge VAR5)
begin
if(reset)
o7 = 1'd0;
end
else
o7 = o6;
end
always @(posedge VAR5)
begin
if(reset)
VAR2 = 1'd0;
end
else
VAR2 = o7;
end
always @(posedge VAR5)
begin
if(reset)
VAR3 = 1'd0;
end
else
VAR3 = VAR2;
end
always @(posedge VAR5)
begin
if(reset)
o10 = 1'd0;
end
else
o10 = VAR3;
end
always @(posedge VAR5)
begin
if(reset)
o11 = 1'd0;
end
else
o11 = o10;
end
always @(posedge VAR5)
begin
if(reset)
o12 = 1'd0;
end
else
o12 = o11;
end
always @(posedge VAR5)
begin
if(reset)
o13 = 1'd0;
end
else
o13 = o12;
end
always @(posedge VAR5)
begin
if(reset)
o14 = 1'd0;
end
else
o14 = o13;
end
always @(posedge VAR5)
begin
if(reset)
o15 = 1'd0;
end
else
o15 = o14;
end
always @(posedge VAR5)
begin
if(reset)
o16 = 1'd0;
end
else
o16 = o15;
end
always @(posedge VAR5)
begin
if(reset)
o17 = 1'd0;
end
else
o17 = o16;
end
always @(posedge VAR5)
begin
if(reset)
VAR7 = 1'd0;
end
else
VAR7 = o17;
end
always @(posedge VAR5)
begin
if(reset)
VAR1 = 1'd0;
end
else
VAR1 = VAR7;
end
always @(posedge VAR5)
begin
if(reset)
o20 = 1'd0;
end
else
o20 = VAR1;
end
always @(posedge VAR5)
begin
if(reset)
o21 = 1'd0;
end
else
o21 = o20;
end
always @(posedge VAR5)
begin
if(reset)
o22 = 1'd0;
end
else
o22 = o21;
end
always @(posedge VAR5)
begin
if(reset)
o23 = 1'd0;
end
else
o23 = o22;
end
always @(posedge VAR5)
begin
if(reset)
o24 = 1'd0;
end
else
o24 = o23;
end
always @(posedge VAR5)
begin
if(reset)
o25 = 1'd0;
end
else
o25 = o24;
end
always @(posedge VAR5)
begin
if(reset)
o26 = 1'd0;
end
else
o26 = o25;
end
always @(posedge VAR5)
begin
if(reset)
o27 = 1'd0;
end
else
o27 = o26;
end
always @(posedge VAR5)
begin
if(reset)
VAR4 = 1'd0;
end
else
VAR4 = o27;
end
always @(posedge VAR5)
begin
if(reset)
VAR6 = 1'd0;
end
else
VAR6 = VAR4;
end
always @(posedge VAR5)
begin
if(reset)
o30 = 1'd0;
end
else
o30 = VAR6;
end
always @(posedge VAR5)
begin
if(reset)
o31 = 1'd0;
end
else
o31 = o30;
end
always @(posedge VAR5)
begin
if(reset)
out = 1'd0;
end
else
out = o31;
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor3/sky130_fd_sc_ms__xor3.functional.v | 1,310 | module MODULE1 (
VAR2,
VAR7,
VAR6,
VAR1
);
output VAR2;
input VAR7;
input VAR6;
input VAR1;
wire VAR4;
xor VAR3 (VAR4, VAR7, VAR6, VAR1 );
buf VAR5 (VAR2 , VAR4 );
endmodule | apache-2.0 |
neale/CS-program | 474-VLSI/Lab_4/frame_rate_bb.v | 12,125 | module MODULE1 (
VAR4,
VAR2,
VAR3,
VAR1);
input VAR4;
output VAR2;
output VAR3;
output VAR1;
endmodule | unlicense |
ShirmanXia/EE469SPRING16 | lab4/db/ip/nios_system/submodules/nios_system_nios2_qsys_0_jtag_debug_slave_sysclk.v | 7,084 | module MODULE1 (
clk,
VAR5,
VAR15,
VAR10,
VAR27,
VAR23,
VAR2,
VAR14,
VAR24,
VAR21,
VAR11,
VAR13,
VAR30,
VAR7,
VAR8,
VAR12,
VAR26,
VAR1,
VAR33
)
;
output [ 37: 0] VAR23;
output VAR2;
output VAR14;
output VAR24;
output VAR21;
output VAR11;
output VAR13;
output VAR30;
output VAR7;
output VAR8;
output VAR12;
output VAR26;
output VAR1;
output VAR33;
input clk;
input [ 1: 0] VAR5;
input [ 37: 0] VAR15;
input VAR10;
input VAR27;
reg VAR6 ;
reg [ 1: 0] VAR29 ;
reg [ 37: 0] VAR23 ;
reg VAR20 ;
reg VAR31 ;
reg VAR32 ;
wire VAR22;
wire VAR18;
wire VAR2;
wire VAR14;
wire VAR24;
wire VAR21;
wire VAR11;
wire VAR13;
wire VAR30;
wire VAR7;
wire VAR8;
wire VAR12;
wire VAR26;
wire VAR1;
wire VAR33;
wire VAR19;
wire VAR16;
reg VAR25 ;
assign VAR19 = 1'b1;
VAR4 VAR9
(
.clk (clk),
.din (VAR10),
.dout (VAR22),
.VAR28 (VAR19)
);
assign VAR16 = 1'b1;
VAR4 VAR17
(
.clk (clk),
.din (VAR27),
.dout (VAR18),
.VAR28 (VAR16)
);
always @(posedge clk)
begin
VAR31 <= VAR22;
VAR25 <= VAR22 & ~VAR31;
VAR6 <= VAR25;
VAR32 <= VAR18;
VAR20 <= VAR18 & ~VAR32;
end
assign VAR21 = VAR6 && (VAR29 == 2'b00) &&
~VAR23[35] && VAR23[34];
assign VAR1 = VAR6 && (VAR29 == 2'b00) &&
~VAR23[35] && ~VAR23[34];
assign VAR11 = VAR6 && (VAR29 == 2'b00) &&
VAR23[35];
assign VAR30 = VAR6 && (VAR29 == 2'b01) &&
~VAR23[37] &&
VAR23[36];
assign VAR33 = VAR6 && (VAR29 == 2'b01) &&
~VAR23[37] &&
~VAR23[36];
assign VAR7 = VAR6 && (VAR29 == 2'b01) &&
VAR23[37];
assign VAR2 = VAR6 && (VAR29 == 2'b10) &&
~VAR23[36] &&
VAR23[37];
assign VAR8 = VAR6 && (VAR29 == 2'b10) &&
~VAR23[36] &&
~VAR23[37];
assign VAR14 = VAR6 && (VAR29 == 2'b10) &&
VAR23[36] && ~VAR23[35] &&
VAR23[37];
assign VAR12 = VAR6 && (VAR29 == 2'b10) &&
VAR23[36] && ~VAR23[35] &&
~VAR23[37];
assign VAR24 = VAR6 && (VAR29 == 2'b10) &&
VAR23[36] && VAR23[35] &&
VAR23[37];
assign VAR26 = VAR6 && (VAR29 == 2'b10) &&
VAR23[36] && VAR23[35] &&
~VAR23[37];
assign VAR13 = VAR6 && (VAR29 == 2'b11) &&
VAR23[15];
always @(posedge clk)
begin
if (VAR20)
VAR29 <= VAR5;
if (VAR25)
VAR23 <= VAR15;
end
endmodule | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/coeff_ram.v | 1,524 | module MODULE1 (input VAR1, input [3:0] VAR3, output reg [15:0] VAR2);
always @(posedge VAR1)
case (VAR3)
4'd0 : VAR2 <= -16'd16;
4'd1 : VAR2 <= 16'd74;
4'd2 : VAR2 <= -16'd254;
4'd3 : VAR2 <= 16'd669;
4'd4 : VAR2 <= -16'd1468;
4'd5 : VAR2 <= 16'd2950;
4'd6 : VAR2 <= -16'd6158;
4'd7 : VAR2 <= 16'd20585;
4'd8 : VAR2 <= 16'd20585;
4'd9 : VAR2 <= -16'd6158;
4'd10 : VAR2 <= 16'd2950;
4'd11 : VAR2 <= -16'd1468;
4'd12 : VAR2 <= 16'd669;
4'd13 : VAR2 <= -16'd254;
4'd14 : VAR2 <= 16'd74;
4'd15 : VAR2 <= -16'd16;
default : VAR2 <= 16'd0;
endcase
endmodule | gpl-2.0 |
masc-ucsc/cmpe220fall16 | rtl/dctlb.v | 6,484 | module MODULE1(
input clk
,input reset
,input VAR16
,output VAR3
,input VAR1 VAR17
,input VAR15
,output VAR45
,input VAR35 VAR52
,input VAR4
,output VAR13
,input VAR48 VAR19
,output VAR49
,input VAR55
,output VAR53 VAR42
,output VAR12
,input VAR7
,output VAR53 VAR63
,output VAR14
,input VAR5
,output VAR23 VAR8
,input VAR10
,output VAR31
,input VAR18 VAR40
,input VAR39
,output VAR57
,input VAR22 VAR6
,output VAR62
,input VAR59
,output VAR50 VAR29
,output VAR41
,input VAR26
,output VAR20 VAR46
);
assign VAR14 = 1'b0;
assign VAR62 = 1'b0;
assign VAR41 = 1'b0;
VAR53 VAR64;
logic VAR9, VAR58;
VAR61 begin
if(VAR16) begin
VAR64.VAR34 = VAR17.VAR34;
VAR64.VAR21 = 1'b0;
VAR64.VAR11 = 1'b0;
VAR64.VAR56 = 3'b000;
VAR64.VAR33 = VAR17.VAR43[22:12];
VAR64.VAR28 = VAR17.VAR43[14:12];
VAR58 = VAR16;
VAR3 = VAR9;
VAR13 = 1'b0;
end else if(VAR4 & ~VAR19.VAR54) begin
VAR64.VAR34 = 'b0;
VAR64.VAR21 = 1'b1;
VAR64.VAR11 = 1'b1;
VAR64.VAR56 = 3'b000;
VAR64.VAR33 = VAR19.VAR43[22:12];
VAR64.VAR28 = VAR19.VAR43[14:12];
VAR58 = VAR4;
VAR13 = 1'b0; VAR3 = VAR9; end else begin
VAR58 = 1'b0;
end
end
VAR37 #(.VAR30(VAR38(VAR53))) VAR36(
.clk(clk)
,.reset(reset)
,.VAR51(VAR58)
,.VAR25(VAR9)
,.din(VAR64)
,.VAR32(VAR49)
,.VAR60(VAR55)
,.VAR27(VAR42)
);
VAR53 VAR24;
logic VAR47, VAR44;
VAR61 begin
if(VAR15) begin
VAR24.VAR34 = VAR52.VAR34;
VAR24.VAR21 = 1'b0;
VAR24.VAR11 = 1'b0;
VAR24.VAR56 = 3'b000;
VAR24.VAR33 = VAR52.VAR43[22:12];
VAR24.VAR28 = VAR52.VAR43[14:12];
VAR44 = VAR15;
VAR45 = VAR47;
VAR13 = 1'b0;
end else if(VAR16 & VAR4 & ~VAR19.VAR54) begin
VAR24.VAR34 = 'b0;
VAR24.VAR21 = 1'b1;
VAR24.VAR11 = 1'b1;
VAR24.VAR56 = 3'b000;
VAR24.VAR33 = VAR19.VAR43[22:12];
VAR24.VAR28 = VAR19.VAR43[14:12];
VAR44 = VAR4;
VAR13 = 1'b0; VAR45 = VAR47; end else begin
VAR44 = 1'b0;
end
end
VAR37 #(.VAR30(VAR38(VAR53))) VAR2(
.clk(clk)
,.reset(reset)
,.VAR51(VAR44)
,.VAR25(VAR47)
,.din(VAR24)
,.VAR32(VAR12)
,.VAR60(VAR7)
,.VAR27(VAR63)
);
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_ic_tag.v | 5,770 | module MODULE1(
clk, rst,
VAR17, VAR8, VAR14,
addr, en, VAR16, VAR1, VAR2, VAR20
);
parameter VAR13 = VAR10;
parameter VAR4 = VAR9;
input clk;
input rst;
input VAR17;
input [VAR11 - 1:0] VAR14;
output VAR8;
input [VAR4-1:0] addr;
input en;
input VAR16;
input [VAR13-1:0] VAR1;
output VAR2;
output [VAR13-2:0] VAR20;
assign VAR20 = {VAR13-1{1'b0}};
assign VAR2 = 1'b0;
assign VAR8 = VAR17;
VAR5 VAR19(
VAR6 VAR19(
VAR7 VAR19(
.VAR17(VAR17),
.VAR8(VAR8),
.VAR14(VAR14),
.clk(clk),
.rst(rst),
.VAR12(en),
.VAR16(VAR16),
.VAR3(1'b1),
.addr(addr),
.VAR18(VAR1),
.VAR15({VAR20, VAR2})
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.functional.v | 1,869 | module MODULE1 (
VAR9 ,
VAR14,
VAR4,
VAR8 ,
VAR5,
VAR15
);
output VAR9 ;
output VAR14;
input VAR4;
input VAR8 ;
input VAR5;
input VAR15;
wire VAR3 ;
wire VAR2;
VAR10 VAR7 (VAR2, VAR8, VAR5, VAR15 );
VAR6 VAR13 VAR12 (VAR3 , VAR2, VAR4 );
buf VAR1 (VAR9 , VAR3 );
not VAR11 (VAR14 , VAR3 );
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/ETAII_N16_Q8_syn.v | 4,563 | module MODULE4 ( VAR34, VAR62, VAR71, VAR77, VAR58 );
input [8:0] VAR34;
input [8:0] VAR62;
output [8:0] VAR77;
input VAR71;
output VAR58;
wire VAR49, VAR54, VAR50, VAR70, VAR46, VAR15, VAR3, VAR38;
VAR51 VAR25 ( .VAR34(VAR34[3]), .VAR62(VAR62[3]), .VAR28(VAR50) );
VAR80 VAR4 ( .VAR44(VAR34[1]), .VAR53(VAR62[1]), .VAR69(VAR62[0]), .VAR66(VAR34[0]), .VAR28(VAR49) );
VAR40 VAR32 ( .VAR33(VAR62[1]), .VAR23(VAR34[1]), .VAR69(VAR49), .VAR28(VAR54) );
VAR8 VAR43 ( .VAR44(VAR62[2]), .VAR53(VAR34[2]), .VAR69(VAR62[2]), .VAR48(VAR54), .VAR66(VAR34[2]), .VAR5(
VAR54), .VAR28(VAR70) );
VAR64 VAR45 ( .VAR69(VAR70), .VAR48(VAR50), .VAR33(VAR34[3]), .VAR23(VAR62[3]), .VAR28(VAR46) );
VAR39 VAR2 ( .VAR34(VAR34[4]), .VAR62(VAR62[4]), .VAR65(VAR46), .VAR58(VAR15), .VAR13(VAR77[4]) );
VAR39 VAR27 ( .VAR34(VAR34[5]), .VAR62(VAR62[5]), .VAR65(VAR15), .VAR58(VAR3), .VAR13(VAR77[5]) );
VAR39 VAR79 ( .VAR34(VAR34[6]), .VAR62(VAR62[6]), .VAR65(VAR3), .VAR58(VAR38), .VAR13(VAR77[6]) );
VAR39 VAR61 ( .VAR34(VAR34[7]), .VAR62(VAR62[7]), .VAR65(VAR38), .VAR58(VAR77[8]), .VAR13(VAR77[7]) );
VAR35 ("VAR14.VAR73");
endmodule
module MODULE3 ( VAR34, VAR62, VAR71, VAR77, VAR58 );
input [7:0] VAR34;
input [7:0] VAR62;
output [7:0] VAR77;
input VAR71;
output VAR58;
wire VAR76, VAR75, VAR74, VAR49, VAR54, VAR50, VAR70, VAR46, VAR15;
VAR6 VAR25 ( .VAR34(VAR62[7]), .VAR62(VAR70), .VAR28(VAR77[7]) );
VAR51 VAR4 ( .VAR34(VAR34[3]), .VAR62(VAR62[3]), .VAR28(VAR74) );
VAR64 VAR32 ( .VAR69(VAR49), .VAR48(VAR74), .VAR33(VAR34[3]), .VAR23(VAR62[3]), .VAR28(VAR46) );
VAR67 VAR43 ( .VAR34(VAR34[5]), .VAR62(VAR62[5]), .VAR71(VAR54), .VAR58(VAR15), .VAR13(VAR77[5]) );
VAR16 VAR45 ( .VAR34(VAR34[7]), .VAR62(VAR50), .VAR28(VAR70) );
VAR80 VAR2 ( .VAR44(VAR34[1]), .VAR53(VAR62[1]), .VAR69(VAR62[0]), .VAR66(VAR34[0]), .VAR28(VAR76) );
VAR29 VAR27 ( .VAR33(VAR62[1]), .VAR23(VAR34[1]), .VAR69(VAR76), .VAR28(VAR75) );
VAR8 VAR79 ( .VAR44(VAR62[2]), .VAR53(VAR34[2]), .VAR69(VAR62[2]), .VAR48(VAR75), .VAR66(VAR34[2]), .VAR5(
VAR75), .VAR28(VAR49) );
VAR39 VAR61 ( .VAR34(VAR34[4]), .VAR62(VAR62[4]), .VAR65(VAR46), .VAR58(VAR54), .VAR13(VAR77[4]) );
VAR39 VAR10 ( .VAR34(VAR34[6]), .VAR62(VAR62[6]), .VAR65(VAR15), .VAR58(VAR50), .VAR13(VAR77[6]) );
VAR35 ("VAR14.VAR73");
endmodule
module MODULE2 ( VAR34, VAR62, VAR71, VAR77, VAR58 );
input [7:0] VAR34;
input [7:0] VAR62;
output [7:0] VAR77;
input VAR71;
output VAR58;
wire VAR76, VAR75, VAR74, VAR49, VAR54, VAR50, VAR70, VAR46, VAR15;
VAR52 VAR25 ( .VAR34(VAR34[3]), .VAR62(VAR62[3]), .VAR28(VAR74) );
VAR64 VAR4 ( .VAR69(VAR49), .VAR48(VAR74), .VAR33(VAR34[3]), .VAR23(VAR62[3]), .VAR28(VAR70) );
VAR40 VAR32 ( .VAR33(VAR62[1]), .VAR23(VAR34[1]), .VAR69(VAR76), .VAR28(VAR75) );
VAR80 VAR43 ( .VAR44(VAR34[1]), .VAR53(VAR62[1]), .VAR69(VAR62[0]), .VAR66(VAR34[0]), .VAR28(VAR76) );
VAR8 VAR45 ( .VAR44(VAR62[2]), .VAR53(VAR34[2]), .VAR69(VAR62[2]), .VAR48(VAR75), .VAR66(VAR34[2]), .VAR5(
VAR75), .VAR28(VAR49) );
VAR68 VAR2 ( .VAR34(VAR34[7]), .VAR62(VAR54), .VAR28(VAR50) );
VAR16 VAR27 ( .VAR34(VAR62[7]), .VAR62(VAR50), .VAR28(VAR77[7]) );
VAR39 VAR79 ( .VAR34(VAR34[4]), .VAR62(VAR62[4]), .VAR65(VAR70), .VAR58(VAR46), .VAR13(VAR77[4]) );
VAR39 VAR61 ( .VAR34(VAR34[5]), .VAR62(VAR62[5]), .VAR65(VAR46), .VAR58(VAR15), .VAR13(VAR77[5]) );
VAR39 VAR10 ( .VAR34(VAR34[6]), .VAR62(VAR62[6]), .VAR65(VAR15), .VAR58(VAR54), .VAR13(VAR77[6]) );
VAR35 ("VAR14.VAR73");
endmodule
module MODULE1 ( VAR57, VAR42, VAR12 );
input [15:0] VAR57;
input [15:0] VAR42;
output [16:0] VAR12;
wire VAR41, VAR59, VAR9, VAR30, VAR47, VAR56,
VAR36, VAR19,
VAR55, VAR72,
VAR31, VAR22,
VAR7, VAR26,
VAR78, VAR24;
MODULE4 MODULE1 ( .VAR34({1'b0, VAR57[15:8]}), .VAR62({1'b0,
VAR42[15:8]}), .VAR71(1'b0), .VAR77({VAR12[16:12], VAR47,
VAR56, VAR36, VAR19}) );
MODULE3 MODULE2 ( .VAR34(VAR57[11:4]), .VAR62(VAR42[11:4]), .VAR71(1'b0), .VAR77({VAR12[11:8], VAR55, VAR72,
VAR31, VAR22}) );
MODULE2 MODULE3 ( .VAR34(VAR57[7:0]), .VAR62(VAR42[7:0]), .VAR71(1'b0),
.VAR77({VAR12[7:4], VAR7, VAR26,
VAR78, VAR24}) );
VAR6 VAR21 ( .VAR34(VAR57[3]), .VAR62(VAR30), .VAR28(VAR12[3]) );
VAR1 VAR37 ( .VAR34(VAR57[0]), .VAR62(VAR42[0]), .VAR28(VAR41) );
VAR60 VAR11 ( .VAR33(VAR57[0]), .VAR23(VAR42[0]), .VAR69(VAR41), .VAR28(VAR12[0]) );
VAR39 VAR17 ( .VAR34(VAR57[1]), .VAR62(VAR42[1]), .VAR65(VAR41), .VAR58(VAR59), .VAR13(VAR12[1]) );
VAR39 VAR25 ( .VAR34(VAR57[2]), .VAR62(VAR42[2]), .VAR65(VAR59), .VAR58(VAR9), .VAR13(VAR12[2]) );
VAR16 VAR4 ( .VAR34(VAR42[3]), .VAR62(VAR9), .VAR28(VAR30) );
VAR35 ("VAR14.VAR73");
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a.behavioral.v | 1,968 | module MODULE1 (
VAR11 ,
VAR13 ,
VAR10 ,
VAR9 ,
VAR7 ,
VAR2 ,
VAR16,
VAR3
);
output VAR11 ;
input VAR13 ;
input VAR10 ;
input VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR16;
input VAR3;
wire VAR7 VAR14 ;
wire VAR6 ;
wire VAR5;
or VAR1 (VAR14 , VAR10, VAR13 );
and VAR8 (VAR6 , VAR9, VAR7, VAR14, VAR2 );
VAR4 VAR12 (VAR5, VAR6, VAR16, VAR3);
buf VAR15 (VAR11 , VAR5 );
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/enet_if/v7_enet_top.v | 4,011 | module MODULE1(
input VAR36,
input VAR14,
input VAR25,
output VAR42,
output [7:0] VAR19,
output VAR49,
output VAR16,
output VAR28,
input [7:0] VAR5,
input VAR24,
input VAR21,
input VAR38,
input VAR48,
input VAR43,
input VAR10,
input VAR53, input VAR23, output VAR35, output VAR20, input VAR37, input VAR3,
output VAR2,
output VAR44,
output VAR1,
input VAR32,
output VAR26,
output VAR11,
input VAR34, input VAR22, input [31:0] VAR12, input [31:0] VAR18, input [31:0] VAR46, input [31:0] VAR39, output [31:0] VAR52, output [31:0] VAR31, output VAR51, output VAR29,
output VAR15,
output VAR30,
output [255:0] VAR40,
output [31:0] VAR45,
output [31:0] VAR4,
output [31:0] VAR50,
input [255:0] VAR41,
input VAR27,
input VAR8,
input VAR9
);
VAR7 VAR33
(
.VAR17(VAR36),
.VAR25(VAR25),
.VAR42(VAR42),
.VAR53(VAR53),
.VAR23(VAR23),
.VAR35(VAR35),
.VAR20(VAR20),
.VAR37(VAR37),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR44(VAR44),
.VAR6(VAR32),
.VAR13(VAR1),
.VAR11(VAR11),
.VAR47(VAR26),
.VAR34(VAR34),
.VAR22(VAR22),
.VAR12(VAR12),
.VAR18(VAR18),
.VAR46(VAR46),
.VAR39(VAR39),
.VAR52(VAR52),
.VAR31(VAR31),
.VAR51(VAR51),
.VAR29(VAR29),
.VAR15(VAR15),
.VAR30(VAR30),
.VAR40(VAR40),
.VAR45(VAR45),
.VAR4(VAR4),
.VAR50(VAR50),
.VAR41(VAR41),
.VAR27(VAR27),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb_1.v | 2,323 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR10,
VAR7,
VAR5 ,
VAR9
);
output VAR2 ;
input VAR4 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR10;
input VAR7;
input VAR5 ;
input VAR9 ;
VAR11 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR2 ,
VAR4,
VAR8,
VAR1 ,
VAR6
);
output VAR2 ;
input VAR4;
input VAR8;
input VAR1 ;
input VAR6 ;
supply1 VAR10;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR9 ;
VAR11 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/col_mach.v | 18,166 | module MODULE1 #
(
parameter VAR113 = 100,
parameter VAR20 = 3,
parameter VAR92 = "8",
parameter VAR114 = 12,
parameter VAR51 = 4,
parameter VAR34 = 8,
parameter VAR79 = 1,
parameter VAR115 = 0,
parameter VAR36 = 8,
parameter VAR86 = "VAR7",
parameter VAR131 = "VAR73",
parameter VAR76 = "VAR73",
parameter VAR106 = 31,
parameter VAR57 = 2,
parameter VAR88 = 0,
parameter VAR61 = 6,
parameter VAR85 = 4,
parameter VAR4 = 4,
parameter VAR66 = 2,
parameter VAR72 = 16
)
(
VAR8, VAR28, VAR14, VAR119,
VAR63, VAR74, VAR99, VAR41,
VAR78, VAR127, VAR60, VAR130, VAR3,
VAR55, VAR44, VAR105,
clk, rst, VAR103, VAR48, VAR81, VAR110,
VAR107, VAR95, VAR101, VAR12,
VAR1, VAR49, VAR102, VAR117
);
input clk;
input rst;
input VAR103;
output reg VAR8 = 1'b0;
generate
if ((VAR57 == 1) && ((VAR92 == "8") || (VAR86 == "VAR7")))
begin : VAR121
reg [1:0] VAR100;
wire [1:0] VAR53 = {VAR103, VAR100[1]};
always @(VAR100 or VAR103)
VAR8 = VAR103 || |VAR100;
end
if (((VAR57 == 2) && ((VAR92 == "8") || (VAR86 == "VAR7")))
|| ((VAR57 == 1) && ((VAR92 == "4") || (VAR86 == "VAR18"))))
begin : VAR124
always @(VAR103) VAR8 = VAR103;
end
endgenerate
reg [1:0] VAR33 = 2'b0;
reg [1:0] VAR10 = 2'b0;
input VAR48;
wire VAR25;
generate
if (VAR79 == 2) begin : VAR35
always @(VAR48 or VAR33 or rst or VAR103) begin
if (rst) VAR10 = 2'b0;
end
else begin
VAR10 = VAR33;
if (VAR103) VAR10 = 2'b1;
end
else if (|VAR33 && (VAR33 != {VAR48, 1'b1}))
VAR10 = VAR33 + 2'b1;
end
else VAR10 = 2'b0;
end
end
assign VAR25 = VAR48 ? (VAR33 == 2'b11) : VAR33[0];
end
else begin : VAR97
always @(VAR48 or rst or VAR103)
VAR10[0] = rst ? 1'b0 : VAR103 && VAR48;
assign VAR25 = VAR48 ? VAR33[0] : 1'b1;
end
endgenerate
reg [VAR79-1:0] VAR111 = {VAR79{1'b0}};
generate
if ((VAR88 == 1) || (VAR115 == 1)) begin : VAR94
always @(posedge clk) VAR111 <=
end
endgenerate
output wire [VAR79-1:0] VAR28;
assign VAR28 = (VAR115 == 1)
? VAR111[VAR79-1:0]
: (VAR131 == "VAR73")
? VAR33[VAR79-1:0]
: VAR10[VAR79-1:0];
input [VAR66:0] VAR81;
reg VAR75;
wire VAR119 = (VAR88 == 0)
? ((VAR103 || |VAR33) && VAR81[VAR66])
: ((VAR75 || |VAR111) && VAR81[VAR66]);
output wire [VAR36-1:0] VAR14;
assign VAR14 = {VAR36{VAR119}};
output wire VAR119;
assign VAR119 = (VAR115 == 1)
? ((VAR75 || |VAR111) && VAR81[VAR66])
: ((VAR103 || |VAR33) && VAR81[VAR66]);
input [VAR34-1:0] VAR110;
output wire [VAR34-1:0] VAR63;
generate
if (VAR115 == 1) begin : VAR67
reg [VAR34-1:0] VAR64;
always @(posedge clk) VAR64 <=
assign VAR63 = VAR64;
end
else begin : VAR70
assign VAR63 = VAR110;
end
endgenerate
wire VAR108 = (VAR103 || |VAR33) && ~VAR81[VAR66];
output wire [VAR36-1:0] VAR74;
assign VAR74 = {VAR36{VAR108}};
function integer VAR104 (input integer VAR80); begin
VAR80 = VAR80 - 1;
for (VAR104=1; VAR80>1; VAR104=VAR104+1)
VAR80 = VAR80 >> 1;
end
endfunction
localparam VAR15 = 1;
localparam VAR71 = VAR61 - 2;
localparam VAR29 = VAR4 - 2;
localparam VAR40 = VAR104(VAR71 + 1);
reg [VAR40-1:0] VAR47;
reg [VAR40-1:0] VAR42;
always @(VAR47 or VAR108 or rst or VAR119) begin
if (rst) VAR42 = {VAR40{1'b0}};
end
else begin
VAR42 = VAR47;
if (VAR119)
VAR42 = VAR29[VAR40-1:0];
end
else
if (VAR108)
VAR42 = VAR71[VAR40-1:0];
else
if (|VAR47)
VAR42 = VAR47 - VAR15[VAR40-1:0];
end end
localparam VAR22 = VAR85 - 2;
localparam VAR120 = VAR104(VAR22 + 1);
reg [VAR120-1:0] VAR31;
reg [VAR120-1:0] VAR11;
always @(VAR31 or rst or VAR119) begin
if (rst) VAR11 = {VAR120{1'b0}};
end
else begin
VAR11 = VAR31;
if (VAR119)
VAR11 = VAR22[VAR120-1:0];
end
else
if (|VAR31)
VAR11 = VAR31 - VAR15[VAR120-1:0];
end
end
wire VAR96 = (VAR42 != {VAR40{1'b0}});
reg VAR123;
output wire VAR99;
assign VAR99 = VAR103 || VAR119 || VAR123;
wire VAR125 = (VAR11 != {VAR120{1'b0}});
reg VAR77;
output wire VAR41;
assign VAR41 = VAR103 || VAR119 || VAR77;
input VAR107;
output wire VAR78;
output reg [VAR106-1:0] VAR127;
output reg VAR60;
output reg VAR130;
output reg VAR3;
output reg [VAR34-1:0] VAR55;
output reg [VAR79-1:0] VAR44;
output reg VAR105;
input VAR95;
input [VAR34-1:0] VAR101;
input VAR12;
input [VAR66-1:0] VAR1;
input [VAR20-1:0] VAR49;
input [VAR72-1:0] VAR102;
input [VAR72-1:0] VAR117;
wire [11:0] VAR16;
assign VAR16[10:0] = {VAR117[11], VAR117[9:0]};
assign VAR16[11] = VAR72 >= 14 ? VAR117[13] : 0;
wire [VAR114-1:0] VAR83 = VAR16[VAR114-1:0];
localparam VAR39 = VAR106-VAR79;
localparam VAR93 = 1 +
1 +
VAR34 +
VAR79 +
((VAR76 == "VAR73") ? 0 : 1+VAR39);
localparam VAR62 = (VAR93/6);
localparam VAR89 = VAR93 % 6;
localparam VAR27 = VAR62 + ((VAR89 == 0 ) ? 0 : 1);
localparam VAR50 = (VAR27*6);
generate
begin : VAR112
wire [VAR39:0] VAR23;
if (VAR51 == 1)
assign VAR23 = {VAR12, VAR49, VAR102, VAR83};
end
else
assign VAR23 = {VAR12,
VAR1,
VAR49,
VAR102,
VAR83};
wire [VAR93-1:0] VAR19;
if (VAR76 == "VAR73")
assign VAR19 = {VAR25,
VAR95,
VAR101,
VAR33[VAR79-1:0]};
else
assign VAR19 = {VAR25,
VAR95,
VAR101,
VAR33[VAR79-1:0],
VAR23};
wire [VAR50-1:0] VAR58;
reg [VAR50-1:0] VAR109;
if (VAR89 == 0)
assign VAR58 = VAR19;
else
assign VAR58 = {{6-VAR89{1'b0}}, VAR19};
wire [VAR50-1:0] VAR90;
reg [4:0] VAR6;
reg [4:0] VAR32;
wire [4:0] VAR30 = rst ? 5'b0 : VAR108
? (VAR6 + 5'b1)
: VAR6;
reg [4:0] VAR43;
wire [4:0] VAR37 = rst ? 5'b0 : VAR107
? (VAR43 + 5'b1)
: VAR43;
genvar VAR122;
for (VAR122=0; VAR122<VAR27; VAR122=VAR122+1) begin : VAR98
VAR82
.VAR132(64'h0000000000000000),
.VAR52(64'h0000000000000000),
.VAR56(64'h0000000000000000)
) VAR126 (
.VAR13(VAR90[((VAR122*6)+4)+:2]),
.VAR2(VAR90[((VAR122*6)+2)+:2]),
.VAR91(VAR90[((VAR122*6)+0)+:2]),
.VAR69(),
.VAR5(VAR109[((VAR122*6)+4)+:2]),
.VAR65(VAR109[((VAR122*6)+2)+:2]),
.VAR68(VAR109[((VAR122*6)+0)+:2]),
.VAR9(2'b0),
.VAR116(VAR37),
.VAR84(VAR37),
.VAR118(VAR37),
.VAR46(VAR32),
.VAR21(1'b1),
.VAR59(clk)
);
end
reg [VAR50-1:0] VAR17;
if (VAR76 == "VAR73") begin
reg VAR45;
always @(VAR107 or VAR17) begin
{VAR3,
VAR45,
VAR55,
VAR44} = VAR17[VAR93-1:0];
VAR127 = {VAR106{1'b0}};
VAR105 = VAR107 && ~VAR45;
VAR60 = 1'b0;
VAR130 = 1'b0;
end
assign VAR78 = 1'b0;
end
else begin
wire VAR129;
wire VAR45;
wire [VAR34-1:0] VAR128;
wire [VAR79-1:0] VAR24;
wire [VAR106-1:0] VAR38;
assign {VAR129,
VAR45,
VAR128,
VAR24,
VAR78,
VAR38[VAR79+:VAR39]} =
{VAR17[VAR93-1:0]};
assign VAR38[0+:VAR79] = VAR24;
wire VAR87 = VAR107 && ~(VAR45 || VAR78);
always @(posedge clk) VAR105 <= VAR87;
wire VAR26 = VAR107 && ~VAR45;
wire VAR54 = VAR107 && ~VAR45 && VAR78;
end
end
endgenerate
endmodule | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/open_cores/verilog/processed_files/output/cordic.v | 13,262 | module MODULE2 ( VAR35,
VAR38,
VAR21);
input [4-1:0] VAR35;
input [16:0] VAR38;
output [16:0] VAR21;
reg [16:0] VAR21;
always @ (VAR38 or VAR35) begin
case (VAR35)
0: begin
VAR21[16-0:0] = VAR38[16: 0];
end
1: begin
VAR21[16-1:0] = VAR38[16: 1];
VAR21[16:16-1+1] = 1'b0;
end
2: begin
VAR21[16-2:0] = VAR38[16: 2];
VAR21[16:16-2+1] = 2'b0;
end
3: begin
VAR21[16-3:0] = VAR38[16: 3];
VAR21[16:16-3+1] = 3'b0;
end
4: begin
VAR21[16-4:0] = VAR38[16: 4];
VAR21[16:16-4+1] = 4'b0;
end
5: begin
VAR21[16-5:0] = VAR38[16: 5];
VAR21[16:16-5+1] = 5'b0;
end
6: begin
VAR21[16-6:0] = VAR38[16: 6];
VAR21[16:16-6+1] = 6'b0;
end
7: begin
VAR21[16-7:0] = VAR38[16: 7];
VAR21[16:16-7+1] = 7'b0;
end
8: begin
VAR21[16-8:0] = VAR38[16: 8];
VAR21[16:16-8+1] = 8'b0;
end
9: begin
VAR21[16-9:0] = VAR38[16: 9];
VAR21[16:16-9+1] = 9'b0;
end
10: begin
VAR21[16-10:0] = VAR38[16:10];
VAR21[16:16-10+1] = 10'b0;
end
11: begin
VAR21[16-11:0] = VAR38[16:11];
VAR21[16:16-11+1] = 11'b0;
end
12: begin
VAR21[16-12:0] = VAR38[16:12];
VAR21[16:16-12+1] = 12'b0;
end
13: begin
VAR21[16-13:0] = VAR38[16:13];
VAR21[16:16-13+1] = 13'b0;
end
14: begin
VAR21[16-14:0] = VAR38[16:14];
VAR21[16:16-14+1] = 14'b0;
end
15: begin
VAR21[16-15:0] = VAR38[16:15];
VAR21[16:16-15+1] = 15'b0;
end
endcase
end
endmodule
module MODULE1 ( clk,
rst,
VAR3,
VAR6,
VAR10,
VAR31,
VAR7,
VAR42,
VAR14,
VAR32,
VAR4);
input clk;
input rst;
input VAR3;
input [4-1:0] VAR6;
input [16:0] VAR10;
input [16:0] VAR31;
input [16:0] VAR7;
input [16:0] VAR42;
output [16:0] VAR14;
output [16:0] VAR32;
output [16:0] VAR4;
reg [16:0] VAR39;
reg [16:0] VAR16;
reg [16:0] VAR19;
wire [16:0] VAR1;
wire [16:0] VAR15;
MODULE2 MODULE2(VAR6,VAR31,VAR1);
MODULE2 MODULE3(VAR6,VAR7,VAR15);
always @ (posedge clk)
if (rst) begin
VAR39 <= 0;
VAR16 <= 0;
VAR19 <= 0;
end else begin
if (VAR3) begin
VAR39 <= VAR31;
VAR16 <= VAR7;
VAR19 <= VAR42;
end else if (
VAR42 < 0
) begin
VAR39 <= VAR31 + VAR15; VAR16 <= VAR7 - VAR1; VAR19 <= VAR42 + VAR10;
end else begin
VAR39 <= VAR31 - VAR15; VAR16 <= VAR7 + VAR1; VAR19 <= VAR42 - VAR10;
end
end
assign VAR14 = VAR39;
assign VAR32 = VAR16;
assign VAR4 = VAR19;
endmodule
module MODULE3 ( clk,
rst,
VAR3,
VAR31,
VAR7,
VAR40,
VAR14,
VAR32,
VAR27);
input clk;
input rst;
input VAR3;
input [16:0] VAR31;
input [16:0] VAR7;
input [16:0] VAR40;
output [16:0] VAR14;
output [16:0] VAR32;
output [16:0] VAR27;
wire [16:0] VAR2;
wire [16:0] VAR13;
wire [16:0] VAR25;
wire [16:0] VAR34;
wire [16:0] VAR20;
wire [16:0] VAR22;
wire [16:0] VAR5;
wire [16:0] VAR28;
wire [16:0] VAR11;
wire [16:0] VAR18;
wire [16:0] VAR37;
wire [16:0] VAR36;
wire [16:0] VAR12;
wire [16:0] VAR23;
wire [16:0] VAR33;
wire [16:0] VAR24;
reg [16:0] VAR17;
assign VAR2 = 17'd25735 ; assign VAR13 = 17'd15192; assign VAR25 = 17'd8027; assign VAR34 = 17'd4075; assign VAR20 = 17'd2045; assign VAR22 = 17'd1024; assign VAR5 = 17'd512; assign VAR28 = 17'd256; assign VAR11 = 17'd128; assign VAR18 = 17'd64; assign VAR37 = 17'd32; assign VAR36 = 17'd16; assign VAR12 = 17'd8; assign VAR23 = 17'd4; assign VAR33 = 17'd2; assign VAR24 = 17'd1;
reg [4:0] VAR6;
always @ (VAR6 or VAR2 or VAR13 or VAR25 or VAR34 or VAR20 or VAR22 or VAR5 or VAR28 or VAR11 or VAR18 or VAR37 or VAR36 or VAR12 or VAR23 or VAR33 or VAR24) begin
case (VAR6)
'd0:VAR17 = VAR2;
'd1:VAR17 = VAR13;
'd2:VAR17 = VAR25;
'd3:VAR17 = VAR34;
'd4:VAR17 = VAR20;
'd5:VAR17 = VAR22;
'd6:VAR17 = VAR5;
'd7:VAR17 = VAR28;
'd8:VAR17 = VAR11;
'd9:VAR17 = VAR18;
'd10:VAR17 = VAR37;
'd11:VAR17 = VAR36;
'd12:VAR17 = VAR12;
'd13:VAR17 = VAR23;
'd14:VAR17 = VAR33;
default:VAR17 = VAR24;
endcase
end
wire [16:0] VAR30,VAR8,VAR9;
assign VAR30 = VAR3 ? VAR31 : VAR14;
assign VAR8 = VAR3 ? VAR7 : VAR32;
assign VAR9 = VAR3 ? VAR40 : VAR27;
always @ (posedge clk or posedge VAR3)
if (VAR3) VAR6 <= 0;
end
else VAR6 <= VAR6 + 1;
MODULE1 VAR29 (clk,rst,VAR3,VAR6,VAR17,VAR30,VAR8,VAR9,VAR14,VAR32,VAR27);
endmodule | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/acl_stall_free_sink.v | 5,207 | module MODULE1
parameter integer VAR44 = 32,
parameter integer VAR46 = 32,
parameter integer VAR47 = 1,
parameter integer VAR18 = 1
)
(
input logic VAR38,
input logic VAR3,
input logic [VAR44-1:0] VAR28,
output logic [VAR44-1:0] VAR10,
input logic VAR14,
output logic VAR6,
input logic VAR5,
output logic VAR16,
output logic [VAR46-VAR2+VAR8:0] VAR26,
output logic [VAR47-1:0] VAR11,
input logic VAR34,
input logic VAR36
);
reg [VAR46-VAR2:0] VAR48;
reg [VAR44-1:0] VAR30;
localparam VAR7 = VAR25(VAR46);
localparam VAR42 = 1 << VAR7;
reg [VAR7:0] counter;
reg [VAR47-1:0] VAR35;
wire VAR29;
wire VAR20;
wire VAR41;
wire [VAR44-1:0] VAR33;
wire VAR13;
assign VAR16 = counter[VAR7] | (!VAR35[0]) | VAR13;
assign VAR29 = VAR41 & ~VAR20;
assign VAR26 = {VAR48, VAR14};
assign VAR11 = VAR35;
always @(posedge VAR38 or negedge VAR3)
begin
if (!VAR3)
begin
VAR35 <= {{(VAR47 - 1){1'b0}},1'b1};
end
else
begin
VAR35 <= {VAR35,VAR35[VAR47-1]};
end
end
reg[VAR45(VAR18):0] VAR17;
reg[VAR45(VAR18):0] VAR4;
always @(posedge VAR38 or negedge VAR3)
begin
if (!VAR3) begin
VAR17 <= 0;
VAR4 <= 0;
end else begin
if (VAR35[0]) begin
VAR17 <= (VAR14 && VAR36) ? VAR17 : (VAR17 == (VAR18 - 1) ? 0 : (VAR17 + 1));
end
if (VAR14) begin
VAR4 <= VAR4 + VAR34 - VAR36;
end
end
end
assign VAR13 = (VAR17 >= (VAR4 > 0 ? VAR4 : 1));
always @(posedge VAR38 or negedge VAR3)
begin
if (!VAR3)
begin
VAR48 <= {(VAR46-VAR2-1){1'b0}};
counter <= {(VAR7+1){1'b0}};
VAR30 <= 'VAR24;
end
else
begin
VAR48 <= { VAR48[VAR46-(VAR2+1):0], VAR14 };
counter <= counter + VAR14 - VAR29;
VAR30 <= VAR28;
end
end
VAR23 #(
.VAR44(VAR44),
.VAR37(VAR42)
)
VAR19 (
.VAR38(VAR38),
.VAR3(VAR3),
.VAR28(VAR30),
.VAR10(VAR33),
.VAR15(VAR48[VAR46-VAR2]),
.VAR6(VAR41),
.VAR5(VAR20)
);
VAR21 #(
.VAR9(VAR44)
) VAR27 (
.clk(VAR38),
.reset(~VAR3),
.VAR40(VAR33),
.VAR43(VAR41),
.VAR22(VAR20),
.VAR1(VAR10),
.VAR12(VAR6),
.VAR39(VAR5)
);
function integer VAR25;
input [31:0] VAR31;
integer VAR32;
begin
VAR32 = VAR31;
for(VAR25 = 0; VAR32 > 0; VAR25 = VAR25 + 1)
VAR32 = VAR32 >> 1;
end
endfunction
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai.behavioral.v | 1,610 | module MODULE1 (
VAR1 ,
VAR9,
VAR6,
VAR8,
VAR4,
VAR5
);
output VAR1 ;
input VAR9;
input VAR6;
input VAR8;
input VAR4;
input VAR5;
supply1 VAR13;
supply0 VAR11;
supply1 VAR2 ;
supply0 VAR14 ;
wire VAR10 ;
wire VAR7;
or VAR15 (VAR10 , VAR6, VAR9 );
nand VAR12 (VAR7, VAR4, VAR8, VAR5, VAR10);
buf VAR3 (VAR1 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.symbol.v | 1,367 | module MODULE1 (
input VAR7,
input VAR6,
input VAR3,
input VAR9,
output VAR1
);
supply1 VAR8;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.symbol.v | 1,338 | module MODULE1 (
input VAR8 ,
output VAR7 ,
output VAR5,
input VAR2
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.pp.blackbox.v | 1,412 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR3,
VAR7 ,
VAR6 ,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR3;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_bitplanes.v | 9,116 | module MODULE1
(
input clk, input VAR34,
input reset,
input VAR15, input VAR18,
input VAR3,
input [8:1] VAR35, input [15:0] VAR23, input [48-1:0] VAR2, input VAR36, input VAR50, input [8:0] VAR45, output [8:1] VAR12 );
parameter VAR20 = 9'h102;
parameter VAR43 = 9'h110;
parameter VAR44 = 9'h112;
parameter VAR26 = 9'h114;
parameter VAR5 = 9'h116;
parameter VAR24 = 9'h118;
parameter VAR37 = 9'h11a;
parameter VAR31 = 9'h11c;
parameter VAR51 = 9'h11e;
parameter VAR32 = 9'h1fc;
reg [15:0] VAR46; reg [15:0] VAR29; reg [63:0] VAR39; reg [63:0] VAR14; reg [63:0] VAR1; reg [63:0] VAR38; reg [63:0] VAR7; reg [63:0] VAR27; reg [63:0] VAR19; reg [63:0] VAR10; reg VAR13;
reg [7:0] VAR28; reg [7:0] VAR9;
reg [7:0] VAR40;
reg [7:0] VAR25;
reg [7:0] VAR8; reg [7:0] VAR41; reg [7:0] VAR30; reg [7:0] VAR21;
always @(VAR45)
case (VAR45[3:2])
2'b00 : VAR28 = 8'b00000000;
2'b01 : VAR28 = 8'b00110000;
2'b10 : VAR28 = 8'b00100000;
2'b11 : VAR28 = 8'b00010000;
endcase
always @(VAR45)
case (VAR45[4:3])
2'b00 : VAR9 = 8'b00000000;
2'b01 : VAR9 = 8'b01100000;
2'b10 : VAR9 = 8'b01000000;
2'b11 : VAR9 = 8'b00100000;
endcase
always @(VAR45)
case (VAR45[5:4])
2'b00 : VAR40 = 8'b00000000;
2'b01 : VAR40 = 8'b11000000;
2'b10 : VAR40 = 8'b10000000;
2'b11 : VAR40 = 8'b01000000;
endcase
always @ (posedge clk) begin
if (VAR34) begin
if (VAR13) VAR25 <= (VAR29[1:0] == 2'b00) ? VAR28 : (VAR29[1:0] == 2'b11) ? VAR40 : VAR9;
end
end
always @(posedge clk)
if (VAR34) begin
if (VAR13)
VAR8 <= {VAR46[11:10],VAR46[3:0],VAR46[9:8]};
end
always @(posedge clk)
if (VAR34) begin
VAR30 <= VAR8 + VAR25;
end
always @(posedge clk)
if (VAR34) begin
if (VAR13)
VAR41 <= {VAR46[15:14],VAR46[7:4],VAR46[13:12]};
end
always @(posedge clk)
if (VAR34) begin
VAR21 <= VAR41 + VAR25;
end
always @(posedge clk)
if (VAR34) begin
if (reset)
VAR46 <= 16'h3300;
if ((VAR35[8:1] == VAR20[8:1]))
VAR46 <= VAR3 ? VAR23[15:0] : {2'b00,2'b11,2'b00,2'b11,VAR23[7:0]};
end
always @ (posedge clk) begin
if (VAR34) begin
if (reset)
VAR29 <= 16'h0000;
end
else if (VAR3 && (VAR35[8:1] == VAR32[8:1]))
VAR29 <= VAR23;
end
end
reg [47:0] VAR33=0;
always @ (*) begin
case (VAR29[1:0])
2'b11 : VAR33[47:0] = VAR2[47:0];
2'b10,
2'b01 : VAR33[47:0] = {VAR2[47:32], 32'h00000000};
default : VAR33[47:0] = 48'h000000000000;
endcase
end
always @(posedge clk)
if (VAR34) begin
if (VAR35[8:1] == VAR43[8:1])
VAR39 <= {VAR23,VAR33};
end
always @(posedge clk)
if (VAR34) begin
if (VAR35[8:1] == VAR44[8:1])
VAR14 <= {VAR23,VAR33};
end
always @(posedge clk)
if (VAR34) begin
if (VAR35[8:1] == VAR26[8:1])
VAR1 <= {VAR23,VAR33};
end
always @(posedge clk)
if (VAR34) begin
if (VAR35[8:1] == VAR5[8:1])
VAR38 <= {VAR23,VAR33};
end
always @(posedge clk)
if (VAR34) begin
if (VAR35[8:1] == VAR24[8:1])
VAR7 <= {VAR23,VAR33};
end
always @(posedge clk)
if (VAR34) begin
if (VAR35[8:1] == VAR37[8:1])
VAR27 <= {VAR23,VAR33};
end
always @(posedge clk)
if (VAR34) begin
if (VAR35[8:1] == VAR31[8:1])
VAR19 <= {VAR23,VAR33};
end
always @(posedge clk)
if (VAR34) begin
if (VAR35[8:1] == VAR51[8:1])
VAR10 <= {VAR23,VAR33};
end
always @(posedge clk)
if (VAR34) begin
VAR13 <= VAR35[8:1] == VAR43[8:1] ? 1'b1 : 1'b0;
end
VAR42 VAR47
(
.clk(clk),
.VAR34(VAR34),
.VAR15(VAR15),
.VAR18(VAR18),
.VAR13(VAR13),
.VAR36(VAR36),
.VAR50(VAR50),
.VAR29(VAR29[1:0]),
.VAR23(VAR39),
.VAR16(VAR30),
.out(VAR12[1])
);
VAR42 VAR6
(
.clk(clk),
.VAR34(VAR34),
.VAR15(VAR15),
.VAR18(VAR18),
.VAR13(VAR13),
.VAR36(VAR36),
.VAR50(VAR50),
.VAR29(VAR29[1:0]),
.VAR23(VAR14),
.VAR16(VAR21),
.out(VAR12[2])
);
VAR42 VAR11
(
.clk(clk),
.VAR34(VAR34),
.VAR15(VAR15),
.VAR18(VAR18),
.VAR13(VAR13),
.VAR36(VAR36),
.VAR50(VAR50),
.VAR29(VAR29[1:0]),
.VAR23(VAR1),
.VAR16(VAR30),
.out(VAR12[3])
);
VAR42 VAR22
(
.clk(clk),
.VAR34(VAR34),
.VAR15(VAR15),
.VAR18(VAR18),
.VAR13(VAR13),
.VAR36(VAR36),
.VAR50(VAR50),
.VAR29(VAR29[1:0]),
.VAR23(VAR38),
.VAR16(VAR21),
.out(VAR12[4])
);
VAR42 VAR49
(
.clk(clk),
.VAR34(VAR34),
.VAR15(VAR15),
.VAR18(VAR18),
.VAR13(VAR13),
.VAR36(VAR36),
.VAR50(VAR50),
.VAR29(VAR29[1:0]),
.VAR23(VAR7),
.VAR16(VAR30),
.out(VAR12[5])
);
VAR42 VAR48
(
.clk(clk),
.VAR34(VAR34),
.VAR15(VAR15),
.VAR18(VAR18),
.VAR13(VAR13),
.VAR36(VAR36),
.VAR50(VAR50),
.VAR29(VAR29[1:0]),
.VAR23(VAR27),
.VAR16(VAR21),
.out(VAR12[6])
);
VAR42 VAR17
(
.clk(clk),
.VAR34(VAR34),
.VAR15(VAR15),
.VAR18(VAR18),
.VAR13(VAR13),
.VAR36(VAR36),
.VAR50(VAR50),
.VAR29(VAR29[1:0]),
.VAR23(VAR19),
.VAR16(VAR30),
.out(VAR12[7])
);
VAR42 VAR4
(
.clk(clk),
.VAR34(VAR34),
.VAR15(VAR15),
.VAR18(VAR18),
.VAR13(VAR13),
.VAR36(VAR36),
.VAR50(VAR50),
.VAR29(VAR29[1:0]),
.VAR23(VAR10),
.VAR16(VAR21),
.out(VAR12[8])
);
endmodule | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/16-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_dqs_found_cal_hr.v | 51,690 | module MODULE1 #
(
parameter VAR60 = 100, parameter VAR122 = 2, parameter VAR26 = 5, parameter VAR106 = "0",
parameter VAR102 = 5, parameter VAR66 = "VAR135", parameter VAR112 = 1, parameter VAR71 = 3, parameter VAR108 = 8, parameter VAR111 = 8, parameter VAR117 = "VAR58", parameter VAR99 = "VAR74", parameter VAR134 = 3, parameter VAR49 = 3, parameter VAR142 = 12, parameter VAR19 = 3, parameter VAR92 = 4'b1111,
parameter VAR15 = 4'b0000,
parameter VAR87 = 4'b0000,
parameter VAR55 = 4'b0000,
parameter VAR24 = 4'b0000,
parameter VAR30 = 4'hc,
parameter VAR6 = 4'hf,
parameter VAR103 = 4'hf,
parameter VAR86 = 4'hf,
parameter VAR91 = 4'hf
)
(
input clk,
input rst,
input VAR53,
input VAR105,
input VAR77,
input VAR1,
input [VAR142-1:0] VAR73,
output reg [VAR19-1:0] VAR61,
output [5:0] VAR146,
output [5:0] VAR43,
output [5:0] VAR25,
output VAR17,
output VAR85,
output reg VAR59,
output [6*VAR112-1:0] VAR78,
output [6*VAR112-1:0] VAR115,
output [6*VAR112-1:0] VAR32,
output reg VAR38,
output reg VAR63,
output [6*VAR112-1:0] VAR69,
output [6*VAR112-1:0] VAR84,
output [6*VAR112-1:0] VAR121,
input [8:0] VAR62,
output VAR90,
output VAR114,
output [VAR49-1:0] VAR137,
output reg VAR40,
output reg VAR126,
output [255:0] VAR136
);
localparam VAR138 = (VAR106 == "VAR148-1") ? VAR26 - 1 : 0;
localparam VAR75 = (VAR117 == "VAR58") ? VAR102 + VAR138 + 1 : VAR102 + VAR138;
localparam VAR116 = 13;
localparam VAR140 = (VAR99 == "VAR74") ? 7 : 1;
localparam [19:0] VAR96 = {(VAR91[3] & VAR24[3]),
(VAR91[2] & VAR24[2]),
(VAR91[1] & VAR24[1]),
(VAR91[0] & VAR24[0]),
(VAR86[3] & VAR55[3]),
(VAR86[2] & VAR55[2]),
(VAR86[1] & VAR55[1]),
(VAR86[0] & VAR55[0]),
(VAR103[3] & VAR87[3]),
(VAR103[2] & VAR87[2]),
(VAR103[1] & VAR87[1]),
(VAR103[0] & VAR87[0]),
(VAR6[3] & VAR15[3]),
(VAR6[2] & VAR15[2]),
(VAR6[1] & VAR15[1]),
(VAR6[0] & VAR15[0]),
(VAR30[3] & VAR92[3]),
(VAR30[2] & VAR92[2]),
(VAR30[1] & VAR92[1]),
(VAR30[0] & VAR92[0])};
localparam VAR35 = 4'h0;
localparam VAR20 = 4'h1;
localparam VAR145 = 4'h2;
localparam VAR37 = 4'h3;
localparam VAR123 = 4'h4;
localparam VAR31 = 4'h5;
localparam VAR119 = 4'h6;
localparam VAR128 = 4'h7;
localparam VAR110 = 4'h8;
localparam VAR129 = 4'h9;
localparam VAR21 = 4'hA;
localparam VAR42 = 4'hB;
localparam VAR8 = 4'hC;
localparam VAR2 = 4'hD;
localparam VAR68 = 4'hE;
localparam VAR97 = 4'hF;
integer VAR118,VAR65,VAR101,VAR13,VAR52,VAR34,VAR82,VAR33;
reg VAR3;
reg [6*VAR19-1:0] VAR47[0:VAR112-1];
reg VAR149;
reg VAR127;
reg VAR48;
reg [VAR142-1:0] VAR130;
reg [VAR142-1:0] VAR18;
reg [VAR142-1:0] VAR4;
reg VAR70;
reg VAR72;
reg VAR50;
reg VAR95;
reg VAR57;
reg VAR23;
reg [1:0] VAR41;
reg [2:0 ] VAR29[0:VAR112-1];
reg [5:0 ] VAR16[0:VAR112-1];
reg [6*VAR19-1:0] VAR104[0:VAR112-1];
reg [6*VAR19-1:0] VAR54[0:VAR112-1];
reg [VAR19-1:0] VAR124;
reg [VAR19-1:0] VAR131;
reg [10*VAR19-1:0] VAR141;
reg VAR147;
wire [4*VAR19-1:0] VAR44;
reg [VAR19-1:0] VAR133;
reg [VAR19-1:0] VAR88;
reg [VAR19-1:0] VAR100;
reg [VAR19-1:0] VAR36;
reg [VAR19-1:0] VAR67;
reg VAR144;
reg [VAR49-1:0] VAR10;
reg [3:0] VAR28;
reg VAR76;
reg VAR79;
reg VAR89;
reg VAR139;
reg [5:0] VAR5;
reg [5:0] VAR56;
reg [5:0] VAR12;
reg VAR98;
reg VAR64;
reg VAR93;
reg VAR46;
reg [5:0] VAR11;
reg [5:0] VAR80;
reg [5:0] VAR51;
reg [3:0] VAR22;
assign VAR136[5:0] = VAR11;
assign VAR136[11:6] = VAR80;
assign VAR136[12] = VAR93;
assign VAR136[13] = VAR46;
assign VAR136[14] = VAR76;
assign VAR17 = VAR149;
assign VAR85 = VAR48;
generate
genvar VAR109;
if (VAR19 == 3) begin for (VAR109 = 0; VAR109 < VAR112; VAR109 = VAR109 + 1) begin: VAR120
assign VAR78[6*VAR109+:6] = VAR104[VAR109][5:0];
assign VAR115[6*VAR109+:6] = VAR104[VAR109][11:6];
assign VAR32[6*VAR109+:6] = VAR104[VAR109][17:12];
assign VAR69[6*VAR109+:6] = VAR54[VAR109][5:0];
assign VAR84[6*VAR109+:6] = VAR54[VAR109][11:6];
assign VAR121[6*VAR109+:6] = VAR54[VAR109][17:12];
end
end else if (VAR19 == 2) begin for (VAR109 = 0; VAR109 < VAR112; VAR109 = VAR109 + 1) begin: VAR120
assign VAR78[6*VAR109+:6] = VAR104[VAR109][5:0];
assign VAR115[6*VAR109+:6] = VAR104[VAR109][11:6];
assign VAR32[6*VAR109+:6] = 'd0;
assign VAR69[6*VAR109+:6] = VAR54[VAR109][5:0];
assign VAR84[6*VAR109+:6] = VAR54[VAR109][11:6];
assign VAR121[6*VAR109+:6] = 'd0;
end
end else begin for (VAR109 = 0; VAR109 < VAR112; VAR109 = VAR109 + 1) begin: VAR120
assign VAR78[6*VAR109+:6] = VAR104[VAR109][5:0];
assign VAR115[6*VAR109+:6] = 'd0;
assign VAR32[6*VAR109+:6] = 'd0;
assign VAR69[6*VAR109+:6] = VAR54[VAR109][5:0];
assign VAR84[6*VAR109+:6] = 'd0;
assign VAR121[6*VAR109+:6] = 'd0;
end
end
endgenerate
generate
if (VAR19 == 3) begin assign VAR146 = (~VAR50) ? VAR47[VAR41][0+:6] :
VAR104[VAR41][0+:6];
assign VAR43 = (~VAR50) ? VAR47[VAR41][6+:6] :
VAR104[VAR41][6+:6];
assign VAR25 = (~VAR50) ? VAR47[VAR41][12+:6] :
VAR104[VAR41][12+:6];
end else if (VAR19 == 2) begin assign VAR146 = (~VAR50) ? VAR47[VAR41][0+:6] :
VAR104[VAR41][0+:6];
assign VAR43 = (~VAR50) ? VAR47[VAR41][6+:6] :
VAR104[VAR41][6+:6];
assign VAR25 = 'd0;
end else begin
assign VAR146 = (~VAR50) ? VAR47[VAR41][0+:6] :
VAR104[VAR41][0+:6];
assign VAR43 = 'd0;
assign VAR25 = 'd0;
end
endgenerate
assign VAR90 = VAR70;
assign VAR137 = VAR10;
generate
if ((VAR142 == 4) || (VAR142 == 8) || (VAR142 == 12))
assign VAR44 = VAR4;
end
else if ((VAR142 == 7) || (VAR142 == 11))
assign VAR44 = {1'b0, VAR4};
end
else if ((VAR142 == 6) || (VAR142 == 10))
assign VAR44 = {2'b00, VAR4};
end
else if ((VAR142 == 5) || (VAR142 == 9))
assign VAR44 = {3'b000, VAR4};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (VAR118 = 0; VAR118 < VAR19; VAR118 = VAR118 + 1) begin: VAR27
end
end else if (VAR105) begin
for (VAR52 = 0; VAR52 < VAR19; VAR52 = VAR52 +1) begin: VAR45
(!VAR96[4*VAR52+1] | VAR44[4*VAR52+1]) &
(!VAR96[4*VAR52+2] | VAR44[4*VAR52+2]) &
(!VAR96[4*VAR52+3] | VAR44[4*VAR52+3]);
(VAR96[4*VAR52+1] & VAR44[4*VAR52+1]) |
(VAR96[4*VAR52+2] & VAR44[4*VAR52+2]) |
(VAR96[4*VAR52+3] & VAR44[4*VAR52+3]);
end
end
end
always @(posedge clk) begin
end
always @(posedge clk) begin
if (rst || (VAR22 == 'd0))
end
else if (VAR77 && (VAR22 > 'd0))
end
assign VAR114 = VAR76;
always @(posedge clk) begin
end
always @(posedge clk) begin
if(rst)begin
end else begin
case (VAR28)
VAR35: begin
if (VAR23) begin
if (VAR99 == "VAR143") begin
end else begin
end
end
end
VAR37: begin
if (~(|VAR100) && VAR139) begin
if (|VAR5)
end
else if (VAR98)
end
else
end
end
VAR20: begin
end
VAR145: begin
end
VAR123: begin
end
VAR31: begin
if (VAR10 == VAR49-1)
end
VAR119: begin
if (VAR10 != VAR49-1) begin
end else if (VAR10 == VAR49-1) begin
end
end
VAR128: begin
end
VAR110: begin
if (VAR77 && (VAR22 == 'd1))
end
else
end
VAR129: begin
if (VAR77 && ~(&VAR133)) begin
if (~VAR93 && (VAR12 == 'd63)) begin
end else if (~VAR93 && (VAR12 > 'd30) && (VAR51 > 'd29)) begin
end else if (~VAR93 || (VAR93 && (VAR51 < 'd30) && (VAR12 <= 'd32))) begin
if ((VAR12 == 'd12) || (VAR12 == 'd24)) begin
end else
end else if (VAR93 && (VAR12 > 'd32) && (VAR12 < 'd63) && (VAR51 < 'd30)) begin
if ((VAR12 == 'd36) || (VAR12 == 'd48) || (VAR12 == 'd60)) begin
end else
end else if (VAR93 && (VAR12 == 'd63)) begin
if (VAR51 < 'd30) begin
end else begin
end
end else begin
end
end else if (VAR77 && (&VAR133)) begin
if ((VAR12 == 'd12) || (VAR12 == 'd24) || (VAR12 == 'd36) ||
(VAR12 == 'd48) || (VAR12 == 'd60)) begin
end else if (VAR12 < 'd63) begin
end else begin
if (~VAR93 || (VAR11 > 'd33))
end
else
end
end
end
VAR21: begin
if (VAR1) begin
end
end
VAR42: begin
if ((VAR10 == VAR49-1) && (VAR5 > 'd0))
end
else if ((VAR10 == VAR49-1) && (VAR56 > 'd0))
end
VAR8: begin
if (VAR10 != VAR49-1) begin
end else if (VAR10 == VAR49-1) begin
if ((VAR56 > 'd0) || (VAR5 > 'd0))
end
else begin
if ((VAR5 == 'd0) && ~VAR64)
end
else
end
end
end
VAR2: begin
end
VAR68: begin
end
VAR97: begin
if (&VAR133) begin
end
end
endcase
end
end
always@(posedge clk)
always @(posedge clk) begin
if (rst)
end
else if (VAR70)
end
else if (VAR149)
end
always @(posedge clk) begin
if (rst || (|VAR124))
end
else if (&VAR133) begin
if (VAR41 == VAR112-1)
end
else
end
end
always @(posedge clk) begin
if (rst ||
(VAR70 && (VAR41 == VAR112-1)))
end
else if (&VAR133 && ~(&VAR88))
end
else
end
always @(posedge clk) begin
end
always @(posedge clk) begin
if (rst)
end
else if (&VAR133 && (VAR41 == VAR112-1) && VAR72 &&
(VAR28 == VAR97))
end
else
end
generate
if (VAR19 == 3) begin
always @(posedge clk) begin
if (rst || VAR131[0] || VAR144)
end
else if ((VAR105 && ~VAR3) ||
(VAR36[0] && ~VAR133[0]) ||
(VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst || VAR131[1] || VAR144)
end
else if ((VAR105 && ~VAR3) ||
(VAR36[1] && ~VAR133[1]) ||
(VAR47[VAR41][6+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst || VAR131[2] || VAR144)
end
else if ((VAR105 && ~VAR3) ||
(VAR36[2] && ~VAR133[2]) ||
(VAR47[VAR41][12+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst || VAR144)
end
else if (VAR124[0])
else if (~VAR36[0] && ~VAR133[0])
end
always @(posedge clk) begin
if (rst || VAR144)
end
else if (VAR124[1])
else if (~VAR36[1] && ~VAR133[1])
end
always @(posedge clk) begin
if (rst || VAR144)
end
else if (VAR124[2])
else if (~VAR36[2] && ~VAR133[2])
end
always @(posedge clk) begin
if (rst || VAR149)
end
else if ((VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)) &&
~VAR133[0])
else
end
always @(posedge clk) begin
if (rst || VAR149)
end
else if ((VAR47[VAR41][6+:6] > (VAR26 + VAR138 + VAR116 - 1)) &&
~VAR133[1])
else
end
always @(posedge clk) begin
if (rst || VAR149)
end
else if ((VAR47[VAR41][12+:6] > (VAR26 + VAR138 + VAR116 - 1)) &&
~VAR133[2])
else
end
always @(posedge clk) begin
if (rst)
end
else if (~VAR133[0] && (VAR141[0+:10] == VAR134) &&
(VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst)
end
else if (~VAR133[1] && (VAR141[10+:10] == VAR134) &&
(VAR47[VAR41][6+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst)
end
else if (~VAR133[2] && (VAR141[20+:10] == VAR134) &&
(VAR47[VAR41][12+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst) begin
for (VAR34 = 0; VAR34 < VAR112; VAR34 = VAR34 + 1) begin: VAR94
end
end else if ((VAR127 && ~VAR70) ||
(VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
else if (VAR3 && ~VAR133[0] &&
(VAR77 && (VAR22 == 'd1)) && ~VAR70 && ~VAR144)
VAR47[VAR41][0+:6]
end
always @(posedge clk) begin
if (rst) begin
for (VAR82 = 0; VAR82 < VAR112; VAR82 = VAR82 + 1) begin: VAR132
end
end else if ((VAR127 && ~VAR70) ||
(VAR47[VAR41][6+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
else if (VAR3 && ~VAR133[1] &&
(VAR77 && (VAR22 == 'd1)) && ~VAR70 && ~VAR144)
VAR47[VAR41][6+:6]
end
always @(posedge clk) begin
if (rst) begin
for (VAR33 = 0; VAR33 < VAR112; VAR33 = VAR33 + 1) begin: VAR125
end
end else if ((VAR127 && ~VAR70) ||
(VAR47[VAR41][12+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
else if (VAR3 && ~VAR133[2] &&
(VAR77 && (VAR22 == 'd1)) && ~VAR70 && ~VAR144)
VAR47[VAR41][12+:6]
end
end else if (VAR19 == 2) begin
always @(posedge clk) begin
if (rst || VAR131[0] || VAR144)
end
else if ((VAR105 && ~VAR3) ||
(VAR36[0] && ~VAR133[0]) ||
(VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst || VAR131[1] || VAR144)
end
else if ((VAR105 && ~VAR3) ||
(VAR36[1] && ~VAR133[1]) ||
(VAR47[VAR41][6+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst || VAR144)
end
else if (VAR124[0])
else if (~VAR36[0] && ~VAR133[0])
end
always @(posedge clk) begin
if (rst || VAR144)
end
else if (VAR124[1])
else if (~VAR36[1] && ~VAR133[1])
end
always @(posedge clk) begin
if (rst || VAR149)
end
else if ((VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)) &&
~VAR133[0])
else
end
always @(posedge clk) begin
if (rst || VAR149)
end
else if ((VAR47[VAR41][6+:6] > (VAR26 + VAR138 + VAR116 - 1)) &&
~VAR133[1])
else
end
always @(posedge clk) begin
if (rst)
end
else if (~VAR133[0] && (VAR141[0+:10] == VAR134) &&
(VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst)
end
else if (~VAR133[1] && (VAR141[10+:10] == VAR134) &&
(VAR47[VAR41][6+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst) begin
for (VAR34 = 0; VAR34 < VAR112; VAR34 = VAR34 + 1) begin: VAR14
end
end else if ((VAR127 && ~VAR70) ||
(VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
else if (VAR3 && ~VAR133[0] &&
(VAR77 && (VAR22 == 'd1)) && ~VAR70 && ~VAR144)
VAR47[VAR41][0+:6]
end
always @(posedge clk) begin
if (rst) begin
for (VAR82 = 0; VAR82 < VAR112; VAR82 = VAR82 + 1) begin: VAR9
end
end else if ((VAR127 && ~VAR70) ||
(VAR47[VAR41][6+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
else if (VAR3 && ~VAR133[1] &&
(VAR77 && (VAR22 == 'd1)) && ~VAR70 && ~VAR144)
VAR47[VAR41][6+:6]
end
end else begin
always @(posedge clk) begin
if (rst) begin
for (VAR65 = 0; VAR65 < VAR112; VAR65 = VAR65 + 1) begin: VAR7
end
end else if ((VAR127 && ~VAR70) ||
(VAR47[VAR41] > (VAR26 + VAR138 + VAR116 - 1)))
end
else if (VAR3 && ~VAR133[0] &&
(VAR77 && (VAR22 == 'd1)) && ~VAR70 && ~VAR144)
VAR47[VAR41]
end
always @(posedge clk) begin
if (rst || VAR131[0] || VAR144)
end
else if ((VAR105 && ~VAR3) ||
(VAR36[0] && ~VAR133[0]) ||
(VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
always @(posedge clk) begin
if (rst || VAR144)
end
else if (VAR124[0])
else if (~VAR36[0] && ~VAR133[0])
end
always @(posedge clk) begin
if (rst || VAR149)
end
else if ((VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)) &&
~VAR133[0])
else
end
always @(posedge clk) begin
if (rst)
end
else if (~VAR133[0] && (VAR141[0+:10] == VAR134) &&
(VAR47[VAR41][0+:6] > (VAR26 + VAR138 + VAR116 - 1)))
end
end
endgenerate
always @(posedge clk) begin
if (rst)
end
else if (VAR79)
else
end
generate
genvar VAR39;
genvar VAR107;
for (VAR39 = 0; VAR39 < VAR112; VAR39 = VAR39 + 1) begin: VAR113
reg [5:0] VAR81 [VAR112-1:0];
if (VAR19 == 3) begin
always @ begin
case (VAR29[VAR39])
3'b000: VAR81[VAR39] = VAR104[VAR39][5:0];
3'b001: VAR81[VAR39] = VAR104[VAR39][11:6];
3'b010: VAR81[VAR39] = 'd0;
default: VAR81[VAR39] = 'd0;
endcase
end
end else begin
always @(*) begin
case (VAR29[VAR39])
3'b000: VAR81[VAR39] = VAR104[VAR39][5:0];
3'b001: VAR81[VAR39] = 'd0;
3'b010: VAR81[VAR39] = 'd0;
default: VAR81[VAR39] = 'd0;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst)
end
else begin
3'b000: if ( | VAR96[3:0])
if (VAR16[VAR39] < VAR81[VAR39])
end
else
3'b001: if ( | VAR96[7:4])
if (VAR16[VAR39] < VAR81[VAR39])
end
else
3'b010: if ( | VAR96[11:8])
if (VAR16[VAR39] < VAR81[VAR39])
end
else
default:
endcase
end
end
always @(posedge clk)
if (rst) begin
end
else begin
end
for (VAR107 = 0; VAR107 < VAR19; VAR107 = VAR107 + 1) begin: VAR83
always @(posedge clk) begin
if (rst) begin
end
else begin
if (VAR70 && ~VAR72) begin
end
end
end
else if (VAR23 ) begin
end
end
end
end
end
end
endgenerate
always @(posedge clk) begin
end
endmodule | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_input_if.v | 10,789 | module MODULE1
VAR55 = 64,
VAR66 = 8,
VAR38 = 33,
VAR28 = 3,
VAR49 = 1,
VAR5 = 2,
VAR24 = "VAR19"
)
(
VAR60,
VAR34,
VAR85,
VAR29,
VAR52,
VAR4,
VAR68,
VAR67,
VAR13,
VAR65,
VAR11,
VAR43,
VAR7,
VAR44,
VAR50,
VAR1,
VAR27,
VAR53,
VAR56,
VAR76,
VAR42,
VAR74,
VAR10,
VAR8,
VAR70,
VAR57,
VAR72,
VAR82,
VAR47,
VAR20,
VAR79,
VAR58,
VAR77,
VAR46,
VAR32,
VAR9,
VAR45,
VAR12,
VAR54,
VAR25,
VAR83,
VAR39,
VAR80,
VAR3,
VAR2,
VAR41,
VAR23,
VAR31,
VAR51,
VAR48,
VAR78,
VAR26,
VAR33,
VAR21,
VAR37,
VAR75,
VAR36,
VAR73,
VAR86,
VAR18,
VAR81,
VAR35,
VAR17,
VAR6,
VAR61,
VAR16,
VAR64,
VAR14,
VAR63,
VAR59,
VAR71,
VAR69,
VAR22,
VAR15
);
localparam VAR84 = 0;
localparam VAR30 = 1;
output VAR60;
input [VAR38-1:0] VAR29;
input VAR34;
input VAR85;
input [VAR28-1:0] VAR52;
input [VAR66 - 1 : 0] VAR4;
input VAR68;
input VAR67;
input VAR13;
output VAR65;
input VAR11;
input [VAR55-1:0] VAR43;
input [VAR55/8-1:0] VAR7;
input VAR44;
input VAR50;
input [VAR66-1:0] VAR1;
input VAR27;
output VAR53;
output [VAR55-1:0] VAR56;
output VAR76;
output VAR42;
output VAR74;
output [VAR66-1:0] VAR10;
output [VAR66-1:0] VAR8;
output VAR70;
input VAR57;
output VAR72;
output [VAR38-1:0] VAR82;
output VAR47;
output VAR20;
output VAR79;
output [VAR28-1:0] VAR58;
output VAR77;
output VAR46;
output [VAR66-1:0] VAR32;
output [VAR55-1:0] VAR12;
output [VAR55/8-1:0] VAR54;
output VAR25;
input VAR9;
output [VAR66-1:0] VAR45;
input [VAR55-1:0] VAR83;
input VAR39;
input VAR80;
input [VAR66-1:0]VAR3;
input VAR2;
input VAR41;
input VAR23;
input [VAR49-1:0] VAR31;
input VAR51;
input VAR48;
input [VAR49-1:0] VAR78;
input VAR26;
input [VAR49-1:0] VAR33;
output VAR21;
output VAR37;
output VAR75;
output VAR36;
output VAR73;
input [VAR5 - 1 : 0] VAR86;
input [VAR66 - 1 : 0] VAR35;
input [VAR5 - 1 : 0] VAR18;
input [VAR5 - 1 : 0] VAR81;
output VAR17;
output [VAR49-1:0] VAR6;
output VAR61;
output VAR16;
output [VAR49-1:0] VAR64;
output VAR14;
output [VAR49-1:0] VAR63;
input VAR59;
input VAR71;
input VAR69;
input VAR22;
input VAR15;
wire VAR77;
wire [VAR38-1:0] VAR82;
wire VAR20;
wire VAR47;
wire VAR79;
wire VAR57;
wire VAR72;
wire VAR60;
wire VAR46;
wire [VAR28-1:0] VAR58;
wire [VAR5 - 1 : 0] VAR86;
wire [VAR66 - 1 : 0] VAR35;
wire [VAR5 - 1 : 0] VAR18;
wire [VAR5 - 1 : 0] VAR81;
wire VAR17;
wire [VAR49-1:0] VAR6;
wire VAR61;
wire VAR16;
wire [VAR49-1:0] VAR64;
wire VAR14;
wire VAR69;
wire VAR65;
wire [VAR55-1:0] VAR12;
wire VAR25;
wire [VAR55/8-1:0] VAR54;
wire [VAR66-1:0] VAR45;
wire VAR53;
wire [VAR55-1:0] VAR56;
wire VAR76;
wire VAR42;
wire VAR74;
wire [VAR66-1:0] VAR10;
wire [VAR66-1:0] VAR8;
wire VAR70;
assign VAR77 = VAR68;
assign VAR82 = VAR29;
assign VAR79 = VAR13;
assign VAR58 = VAR52;
assign VAR46 = VAR67;
assign VAR32 = VAR4;
assign VAR17 = VAR23;
assign VAR6 = VAR31;
assign VAR61 = VAR51;
assign VAR16 = VAR48;
assign VAR64 = VAR78;
assign VAR14 = VAR26;
assign VAR63 = VAR33;
assign VAR21 = VAR59;
assign VAR37 = VAR71;
assign VAR75 = VAR69;
assign VAR36 = VAR22;
assign VAR73 = VAR15;
assign VAR12 = VAR43;
assign VAR54 = VAR7;
assign VAR25 = VAR11;
assign VAR45 = VAR1;
assign VAR10 = VAR3;
assign VAR76 = VAR80;
assign VAR53 = VAR39;
assign VAR42 = VAR2;
assign VAR74 = VAR41;
assign VAR56 = VAR83;
assign VAR8 = (VAR70) ? VAR35 : {VAR66{1'b0}};
assign VAR60 = ~VAR57 & VAR73;
assign VAR65 = ~VAR9 & VAR73;
assign VAR20 = ~VAR85 & VAR34 & VAR73;
assign VAR47 = VAR85 & VAR34 & VAR73;
assign VAR72 = VAR34 & VAR73;
generate
begin : VAR62
if (VAR24 == "VAR40")
begin
assign VAR70 = VAR86 [VAR84] & ~(VAR18[VAR84]|VAR81[VAR84]);
end
else
begin
assign VAR70 = VAR86 [VAR30] & ~(VAR18[VAR30]|VAR81[VAR30]);
end
end
endgenerate
endmodule | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/aceusb/rtl/aceusb.v | 3,068 | module MODULE1(
input VAR24,
input VAR17,
input [31:0] VAR2,
input [31:0] VAR1,
output [31:0] VAR4,
input VAR19,
input VAR9,
input VAR10,
output reg VAR32,
output [6:0] VAR21,
inout [15:0] VAR29,
output VAR35,
output VAR11,
input VAR37,
output VAR15,
input VAR14,
output VAR3,
output VAR7,
input VAR20
);
wire VAR13;
wire VAR12;
wire VAR25;
reg VAR26;
reg [5:0] VAR23;
reg [15:0] VAR34;
always @(posedge VAR24) begin
if(VAR26) begin
VAR23 <= VAR2[7:2];
VAR34 <= VAR1[15:0];
end
end
VAR41 VAR8(
.VAR37(VAR37),
.rst(VAR17),
.VAR42(VAR23),
.VAR33(VAR34),
.do(VAR4[15:0]),
.read(VAR13),
.write(VAR12),
.ack(VAR25),
.VAR21(VAR21),
.VAR29(VAR29),
.VAR35(VAR35),
.VAR11(VAR11),
.VAR15(VAR15),
.VAR14(VAR14),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR20(VAR20)
);
assign VAR4[31:16] = 16'h0000;
reg VAR27;
reg VAR22;
wire VAR43;
VAR18 VAR30(
.VAR38(VAR24),
.VAR39(VAR27),
.VAR6(VAR37),
.VAR5(VAR13)
);
VAR18 VAR36(
.VAR38(VAR24),
.VAR39(VAR22),
.VAR6(VAR37),
.VAR5(VAR12)
);
VAR18 VAR16(
.VAR38(VAR37),
.VAR39(VAR25),
.VAR6(VAR24),
.VAR5(VAR43)
);
reg state;
reg VAR31;
parameter VAR40 = 1'd0;
parameter VAR28 = 1'd1;
always @(posedge VAR24) begin
if(VAR17)
state <= VAR40;
end
else
state <= VAR31;
end
always @(*) begin
VAR26 = 1'b0;
VAR32 = 1'b0;
VAR27 = 1'b0;
VAR22 = 1'b0;
VAR31 = state;
case(state)
VAR40: begin
if(VAR19 & VAR9) begin
VAR26 = 1'b1;
if(VAR10)
VAR22 = 1'b1;
end
else
VAR27 = 1'b1;
VAR31 = VAR28;
end
end
VAR28: begin
if(VAR43) begin
VAR32 = 1'b1;
VAR31 = VAR40;
end
end
endcase
end
endmodule | lgpl-3.0 |
bigeagle/riffa | fpga/riffa_hdl/rx_port_64.v | 15,824 | module MODULE1 #(
parameter VAR40 = 9'd64,
parameter VAR41 = 1024,
parameter VAR117 = 512,
parameter VAR107 = 2, parameter VAR155 = VAR32((VAR40/32)+1),
parameter VAR50 = VAR32((2**VAR32(VAR41))+1),
parameter VAR67 = VAR32((2**VAR32(VAR117))+1)
)
(
input VAR28,
input VAR128,
input [2:0] VAR60,
output VAR51, input [31:0] VAR36, input VAR54, input VAR168, input VAR212,
output VAR163, input [31:0] VAR169, input VAR202, input VAR62, input VAR17,
output [VAR40-1:0] VAR182, output VAR130, input VAR121, input VAR207, output VAR206,
input [31:0] VAR68, input VAR125, input VAR95, output [31:0] VAR75, output VAR184, input VAR179,
output VAR119, input VAR161, output [1:0] VAR84, output [63:0] VAR187, output [9:0] VAR120,
input [VAR40-1:0] VAR160, input [VAR155-1:0] VAR4, input VAR143, input VAR196, input [VAR40-1:0] VAR137, input [VAR155-1:0] VAR19, input VAR59, input VAR189, input [VAR40-1:0] VAR203, input [VAR155-1:0] VAR201, input VAR173, input VAR172,
input VAR13, output VAR76, input VAR24, output VAR89, output [31:0] VAR39, output [30:0] VAR35, output [VAR40-1:0] VAR91, output VAR122, input VAR99 );
wire [VAR40-1:0] VAR88;
wire VAR97;
wire VAR37;
wire VAR49;
wire VAR38;
wire VAR191;
wire [VAR40-1:0] VAR115;
wire VAR10;
wire VAR30;
wire VAR57;
wire VAR53;
wire VAR103;
wire [VAR40-1:0] VAR180;
wire VAR77;
wire VAR14;
wire VAR85;
wire VAR31;
wire VAR102;
wire VAR145;
wire VAR149;
wire [VAR40-1:0] VAR131;
wire VAR73;
wire VAR16;
wire VAR47;
wire [VAR40-1:0] VAR159;
wire [VAR67-1:0] VAR176;
wire VAR193;
wire [VAR67-1:0] VAR108;
wire VAR162;
wire [63:0] VAR165;
wire [9:0] VAR106;
wire VAR72;
wire [63:0] VAR22;
wire [9:0] VAR52;
wire VAR153;
wire VAR188;
wire VAR170;
wire VAR27;
wire VAR113;
wire VAR104;
wire [63:0] VAR70;
wire [31:0] VAR18;
wire VAR141;
wire VAR166;
wire [63:0] VAR61;
wire [9:0] VAR33;
wire VAR7;
wire VAR83;
wire VAR114;
wire VAR105;
wire VAR186;
wire [31:0] VAR65;
wire [30:0] VAR110;
wire [31:0] VAR136;
reg [4:0] VAR93=0;
reg VAR134=0;
assign VAR206 = (VAR14 & VAR85);
always @ (posedge VAR28) begin
VAR134 <= VAR93[4];
if (VAR128)
VAR93 <= 5'b11111;
end
else
VAR93 <= (VAR93<<1);
end
VAR194 VAR164 (
.VAR28(VAR28),
.VAR128(VAR134),
.VAR200(VAR160),
.VAR208(VAR4),
.VAR209(VAR143),
.VAR158(VAR196),
.VAR25(VAR38),
.VAR142(VAR88),
.VAR79(VAR97),
.VAR96(VAR37),
.VAR178(VAR49),
.VAR124(VAR191)
);
VAR194 VAR174 (
.VAR28(VAR28),
.VAR128(VAR134),
.VAR200(VAR137),
.VAR208(VAR19),
.VAR209(VAR59),
.VAR158(VAR189),
.VAR25(VAR53),
.VAR142(VAR115),
.VAR79(VAR10),
.VAR96(VAR30),
.VAR178(VAR57),
.VAR124(VAR103)
);
VAR194 VAR86 (
.VAR28(VAR28),
.VAR128(VAR134),
.VAR200(VAR203),
.VAR208(VAR201),
.VAR209(VAR173),
.VAR158(VAR172),
.VAR25(VAR31),
.VAR142(VAR180),
.VAR79(VAR77),
.VAR96(VAR14),
.VAR178(VAR85),
.VAR124(VAR102)
);
VAR152 #(.VAR185(VAR40), .VAR197(VAR41)) VAR11 (
.VAR66(VAR28),
.VAR147(VAR134 | (VAR7 & VAR184) | VAR141),
.VAR20(VAR97),
.VAR71(VAR88),
.VAR112(),
.VAR139(VAR13),
.VAR92(VAR134 | (VAR7 & VAR184) | VAR141),
.VAR111(VAR145),
.VAR90(VAR131),
.VAR82(VAR149)
);
VAR55 #(.VAR185(VAR40), .VAR197(VAR117), .VAR81(1)) VAR12 (
.VAR128(VAR134 | VAR73),
.VAR28(VAR28),
.VAR20(VAR10),
.VAR71(VAR115),
.VAR129(),
.VAR111(VAR16),
.VAR90(VAR159),
.VAR6(VAR47),
.VAR21(VAR176)
);
VAR55 #(.VAR185(VAR40), .VAR197(VAR117), .VAR81(1)) VAR144 (
.VAR128(VAR134 | VAR193),
.VAR28(VAR28),
.VAR20(VAR77),
.VAR71(VAR180),
.VAR129(),
.VAR111(VAR121),
.VAR90(VAR182),
.VAR6(VAR130),
.VAR21(VAR108)
);
VAR42 #(.VAR181(VAR40), .VAR190(VAR117), .VAR107(VAR107)) VAR175 (
.VAR28(VAR28),
.VAR128(VAR134),
.VAR60(VAR60),
.VAR154(VAR141),
.VAR133(VAR51),
.VAR69(VAR36),
.VAR80(VAR54),
.VAR1(VAR168),
.VAR199(VAR212),
.VAR29(VAR176),
.VAR8(VAR53),
.VAR5(VAR103),
.VAR109(VAR73),
.VAR119(VAR162),
.VAR64(VAR165),
.VAR140(VAR106),
.VAR161(VAR27 & VAR153),
.VAR204(VAR30)
);
VAR42 #(.VAR181(VAR40), .VAR190(VAR117), .VAR107(VAR107)) VAR26 (
.VAR28(VAR28),
.VAR128(VAR134),
.VAR60(VAR60),
.VAR154(VAR207),
.VAR133(VAR163),
.VAR69(VAR169),
.VAR80(VAR202),
.VAR1(VAR62),
.VAR199(VAR17),
.VAR29(VAR108),
.VAR8(VAR31),
.VAR5(VAR102),
.VAR109(VAR193),
.VAR119(VAR72),
.VAR64(VAR22),
.VAR140(VAR52),
.VAR161(VAR27 & VAR188),
.VAR204(VAR14)
);
VAR98 VAR48 (
.VAR128(VAR134),
.VAR28(VAR28),
.VAR210(VAR162),
.VAR123(VAR106),
.VAR135(VAR165),
.VAR94(VAR153),
.VAR87(VAR72),
.VAR45(VAR52),
.VAR148(VAR22),
.VAR126(VAR188),
.VAR213(VAR166),
.VAR58(VAR33),
.VAR23(VAR61),
.VAR132(VAR170),
.VAR119(VAR119),
.VAR161(VAR161),
.VAR84(VAR84),
.VAR187(VAR187),
.VAR120(VAR120),
.VAR156(VAR27)
);
VAR100 #(.VAR40(VAR40)) VAR195 (
.VAR28(VAR28),
.VAR128(VAR134 | VAR141),
.VAR69(VAR159),
.VAR138(VAR47),
.VAR157(VAR16),
.VAR3(VAR113),
.VAR6(),
.VAR171(VAR104),
.VAR101(VAR70),
.VAR9(VAR18)
);
VAR43 #(.VAR40(VAR40), .VAR190(VAR41), .VAR107(VAR107)) VAR78 (
.VAR28(VAR28),
.VAR128(VAR134),
.VAR60(VAR60),
.VAR68(VAR68),
.VAR125(VAR125),
.VAR95(VAR95),
.VAR75(VAR75),
.VAR184(VAR184),
.VAR34(VAR7),
.VAR179(VAR179),
.VAR167(VAR38),
.VAR151(VAR191),
.VAR119(VAR166),
.VAR64(VAR61),
.VAR140(VAR33),
.VAR161(VAR27 & VAR170),
.VAR146(VAR4),
.VAR204(VAR37),
.VAR46(VAR49),
.VAR44(VAR30),
.VAR206(VAR57),
.VAR15(VAR70),
.VAR198(VAR18),
.VAR150(VAR113),
.VAR63(VAR104),
.VAR207(VAR141),
.VAR76(VAR83),
.VAR39(VAR65),
.VAR89(VAR186),
.VAR35(VAR110),
.VAR118(VAR114),
.VAR192(VAR105),
.VAR205(VAR136)
);
VAR211 #(.VAR40(VAR40)) VAR56 (
.VAR128(VAR134),
.VAR28(VAR28),
.VAR177(VAR83),
.VAR74(VAR114),
.VAR183(VAR105),
.VAR2(VAR186),
.VAR140(VAR65),
.VAR116(VAR110),
.VAR127(VAR136),
.VAR90(VAR131),
.VAR82(VAR149),
.VAR111(VAR145),
.VAR13(VAR13),
.VAR76(VAR76),
.VAR24(VAR24),
.VAR89(VAR89),
.VAR39(VAR39),
.VAR35(VAR35),
.VAR91(VAR91),
.VAR122(VAR122),
.VAR99(VAR99)
);
endmodule | bsd-3-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/io_queues/ethernet_mac/src/tx_queue.v | 12,827 | module MODULE1
parameter VAR29 = 64,
parameter VAR67 = VAR29/8,
parameter VAR77 = 0,
parameter VAR18 = 'hff
)
(input [VAR29-1:0] VAR4,
input [VAR67-1:0] VAR16,
input VAR45,
output VAR40,
input VAR71,
output reg VAR33,
output [7:0] VAR41,
output VAR54,
output VAR61,
input VAR55,
output VAR17,
output reg VAR59,
output reg [11:0] VAR39,
output reg [9:0] VAR78,
input reset,
input clk,
input VAR62
);
function integer VAR14;
input integer VAR43;
begin
VAR14=0;
while(2**VAR14<VAR43) begin
VAR14=VAR14+1;
end
end
endfunction
parameter VAR57 = VAR14(VAR67);
parameter VAR5 = 1;
parameter VAR68 = 2;
parameter VAR37 = 4;
parameter VAR73 = 8;
parameter VAR24 = 16;
localparam VAR70 = 7;
wire [VAR29+VAR67-1:0] VAR48;
wire VAR64;
reg VAR22;
wire VAR30;
wire VAR23;
reg VAR65;
reg VAR76; reg [VAR57-1:0] VAR46; reg VAR13;
reg VAR20;
reg [4:0] VAR42, VAR15;
reg VAR58;
reg VAR32;
reg VAR50;
reg [VAR70-1:0] VAR12;
wire VAR34;
wire VAR3;
wire [9:0] VAR63;
reg VAR19;
reg VAR10;
reg VAR75;
generate
if(VAR29==32) begin: VAR8
VAR49 VAR6
(
.VAR69 ( reset ),
.VAR38 ( VAR48 ),
.VAR66 ( VAR62 ),
.VAR72 ( VAR22 ),
.VAR53 ( clk ),
.VAR27 ( VAR3 ),
.VAR31 ( {VAR64,VAR41} ),
.VAR52 ( VAR30 ),
.VAR74 ( ),
.VAR63 ( VAR63 ) );
end
else if(VAR29==64) begin: VAR26
VAR60 VAR6 (
.VAR69 ( reset ),
.VAR38 ( VAR48 ),
.VAR66 ( VAR62 ),
.VAR72 ( VAR22 ),
.VAR53 ( clk ),
.VAR27 ( VAR3 ),
.VAR31 ( {VAR64,VAR41} ),
.VAR52 ( VAR30 ),
.VAR74 ( ),
.VAR63 ( VAR63 )
);
end
endgenerate
VAR7 VAR1
(.VAR28 (VAR59),
.VAR51 (clk),
.VAR9(VAR44),
.VAR11 (VAR62),
.VAR25 (reset),
.VAR47 (VAR65));
VAR7 VAR36
(.VAR28 (VAR76),
.VAR51 (VAR62),
.VAR9(VAR17),
.VAR11 (clk),
.VAR25 (VAR65),
.VAR47 (reset));
reg VAR21;
always @(posedge clk) begin
if (reset) VAR21 <= 1;
end
else if (VAR65) VAR21 <= 0;
end
always @(posedge VAR62) VAR65 <= VAR21;
generate
if (VAR77) begin
reg VAR2;
always @(posedge clk) begin
if (reset)
VAR2 <= 1'b0;
end
else if (VAR45) begin
if (VAR2 && |VAR16)
VAR2 <= 1'b0;
end
else if (!VAR2 && !(|VAR16))
VAR2 <= 1'b1;
end
end
assign VAR3 = VAR45 && (!(|VAR16) || VAR2);
always @(posedge clk) begin
VAR59 <= reset ? 0 : VAR45 && (|VAR16) && VAR2;
if (reset) begin
VAR39 <= 'h0;
VAR78 <= 'h0;
end
else if (VAR45 && !VAR2) begin
if (VAR16 == VAR18) begin
VAR39 <= VAR4[VAR56 +: 16];
VAR78 <= VAR4[VAR35 +: 16];
end
end
end
end else begin
assign VAR3 = VAR45;
always @(posedge clk) begin
VAR59 <= reset ? 0 : VAR45 && (|VAR16);
end
begin | mit |
alexforencich/xfcp | lib/wb/rtl/wb_dp_ram.v | 4,811 | module MODULE1 #
(
parameter VAR11 = 32, parameter VAR29 = 16, parameter VAR28 = (VAR11/8) )
(
input wire VAR12,
input wire [VAR29-1:0] VAR27, input wire [VAR11-1:0] VAR4, output wire [VAR11-1:0] VAR13, input wire VAR8, input wire [VAR28-1:0] VAR7, input wire VAR15, output wire VAR33, input wire VAR26,
input wire VAR20,
input wire [VAR29-1:0] VAR18, input wire [VAR11-1:0] VAR19, output wire [VAR11-1:0] VAR25, input wire VAR1, input wire [VAR28-1:0] VAR23, input wire VAR32, output wire VAR31, input wire VAR3 );
parameter VAR21 = VAR29 - VAR10(VAR28);
parameter VAR22 = VAR28;
parameter VAR9 = VAR11/VAR22;
reg [VAR11-1:0] VAR5 = {VAR11{1'b0}};
reg VAR30 = 1'b0;
reg [VAR11-1:0] VAR2 = {VAR11{1'b0}};
reg VAR14 = 1'b0;
reg [VAR11-1:0] VAR6[(2**VAR21)-1:0];
wire [VAR21-1:0] VAR34 = VAR27 >> (VAR29 - VAR21);
wire [VAR21-1:0] VAR24 = VAR18 >> (VAR29 - VAR21);
assign VAR13 = VAR5;
assign VAR33 = VAR30;
assign VAR25 = VAR2;
assign VAR31 = VAR14;
integer VAR16, VAR17; | mit |
olajep/oh | src/adi/hdl/library/common/ad_csc_1.v | 3,508 | module MODULE1 #(
parameter VAR14 = 16) (
input clk,
input [VAR5:0] sync,
input [23:0] VAR4,
input [16:0] VAR6,
input [16:0] VAR27,
input [16:0] VAR22,
input [24:0] VAR11,
output [VAR5:0] VAR3,
output [ 7:0] VAR24);
localparam VAR5 = VAR14 - 1;
wire [24:0] VAR23;
wire [24:0] VAR12;
wire [24:0] VAR9;
wire [VAR5:0] VAR16;
VAR25 #(.VAR14(1)) VAR20 (
.clk (clk),
.VAR19 (VAR6),
.VAR28 (VAR4[23:16]),
.VAR7 (VAR23),
.VAR17 (1'd0),
.VAR26 ());
VAR25 #(.VAR14(1)) VAR2 (
.clk (clk),
.VAR19 (VAR27),
.VAR28 (VAR4[15:8]),
.VAR7 (VAR12),
.VAR17 (1'd0),
.VAR26 ());
VAR25 #(.VAR14(VAR14)) VAR10 (
.clk (clk),
.VAR19 (VAR22),
.VAR28 (VAR4[7:0]),
.VAR7 (VAR9),
.VAR17 (sync),
.VAR26 (VAR16));
VAR8 #(.VAR14(VAR14)) VAR18 (
.clk (clk),
.VAR13 (VAR23),
.VAR21 (VAR12),
.VAR1 (VAR9),
.VAR15 (VAR11),
.VAR7 (VAR24),
.VAR17 (VAR16),
.VAR26 (VAR3));
endmodule | mit |
bbrown1867/ObjectTracking | hw/common/fixed_point/qdiv.v | 3,342 | module MODULE1 #(
parameter VAR7 = 15,
parameter VAR1 = 32
)
(
input [VAR1-1:0] VAR11,
input [VAR1-1:0] VAR2,
input VAR9,
input VAR18,
output [VAR1-1:0] VAR3,
output VAR10,
output VAR13
);
reg [2*VAR1+VAR7-3:0] VAR12; reg [VAR1-1:0] VAR14; reg [VAR1-2+VAR7:0] VAR16; reg [2*VAR1+VAR7-3:0] VAR5;
reg [VAR1-1:0] VAR17;
reg VAR15; reg VAR6; reg VAR8;
VAR4 VAR15 = 1'b1; VAR4 VAR8 = 1'b0; VAR4 VAR6 = 1'b0;
VAR4 VAR12 = 0;
VAR4 VAR14 = 0;
VAR4 VAR16 = 0;
VAR4 VAR5 = 0;
VAR4 VAR17 = 0;
assign VAR3[VAR1-2:0] = VAR14[VAR1-2:0]; assign VAR3[VAR1-1] = VAR6; assign VAR10 = VAR15;
assign VAR13 = VAR8;
always @( posedge VAR18 ) begin
if( VAR15 && VAR9 ) begin VAR15 <= 1'b0; VAR17 <= VAR1+VAR7-1; VAR12 <= 0; VAR16 <= 0; VAR5 <= 0; VAR8 <= 1'b0;
VAR16[VAR1+VAR7-2:VAR7] <= VAR11[VAR1-2:0]; VAR5[2*VAR1+VAR7-3:VAR1+VAR7-1] <= VAR2[VAR1-2:0];
VAR6 <= VAR11[VAR1-1] ^ VAR2[VAR1-1]; end
else if(!VAR15) begin
VAR5 <= VAR5 >> 1; VAR17 <= VAR17 - 1;
if(VAR16 >= VAR5) begin
VAR12[VAR17] <= 1'b1; VAR16 <= VAR16 - VAR5; end
if(VAR17 == 0) begin
VAR15 <= 1'b1; VAR14 <= VAR12; if (VAR12[2*VAR1+VAR7-3:VAR1]>0)
VAR8 <= 1'b1;
end
else
VAR17 <= VAR17 - 1;
end
end
endmodule | mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_auto_pc_1/synth/triangle_intersect_auto_pc_1.v | 15,750 | module MODULE1 (
VAR74,
VAR26,
VAR40,
VAR57,
VAR54,
VAR34,
VAR21,
VAR38,
VAR53,
VAR106,
VAR29,
VAR23,
VAR30,
VAR104,
VAR82,
VAR22,
VAR42,
VAR55,
VAR92,
VAR32,
VAR56,
VAR45,
VAR96,
VAR49,
VAR75,
VAR2,
VAR24,
VAR77,
VAR15,
VAR17,
VAR93,
VAR25,
VAR63,
VAR73,
VAR98,
VAR33,
VAR19,
VAR91,
VAR97,
VAR44,
VAR84,
VAR69,
VAR109,
VAR10,
VAR60,
VAR52,
VAR65,
VAR81,
VAR78,
VAR7,
VAR87,
VAR72,
VAR102,
VAR58,
VAR100,
VAR86,
VAR16,
VAR62,
VAR76,
VAR101,
VAR48,
VAR5,
VAR41,
VAR9,
VAR95,
VAR6,
VAR43,
VAR14,
VAR37,
VAR13,
VAR83,
VAR59,
VAR71,
VAR12,
VAR64,
VAR46,
VAR66,
VAR108,
VAR61
);
input wire VAR74;
input wire VAR26;
input wire [1 : 0] VAR40;
input wire [31 : 0] VAR57;
input wire [7 : 0] VAR54;
input wire [2 : 0] VAR34;
input wire [1 : 0] VAR21;
input wire [0 : 0] VAR38;
input wire [3 : 0] VAR53;
input wire [2 : 0] VAR106;
input wire [3 : 0] VAR29;
input wire [3 : 0] VAR23;
input wire VAR30;
output wire VAR104;
input wire [63 : 0] VAR82;
input wire [7 : 0] VAR22;
input wire VAR42;
input wire VAR55;
output wire VAR92;
output wire [1 : 0] VAR32;
output wire [1 : 0] VAR56;
output wire VAR45;
input wire VAR96;
input wire [1 : 0] VAR49;
input wire [31 : 0] VAR75;
input wire [7 : 0] VAR2;
input wire [2 : 0] VAR24;
input wire [1 : 0] VAR77;
input wire [0 : 0] VAR15;
input wire [3 : 0] VAR17;
input wire [2 : 0] VAR93;
input wire [3 : 0] VAR25;
input wire [3 : 0] VAR63;
input wire VAR73;
output wire VAR98;
output wire [1 : 0] VAR33;
output wire [63 : 0] VAR19;
output wire [1 : 0] VAR91;
output wire VAR97;
output wire VAR44;
input wire VAR84;
output wire [1 : 0] VAR69;
output wire [31 : 0] VAR109;
output wire [3 : 0] VAR10;
output wire [2 : 0] VAR60;
output wire [1 : 0] VAR52;
output wire [1 : 0] VAR65;
output wire [3 : 0] VAR81;
output wire [2 : 0] VAR78;
output wire [3 : 0] VAR7;
output wire VAR87;
input wire VAR72;
output wire [1 : 0] VAR102;
output wire [63 : 0] VAR58;
output wire [7 : 0] VAR100;
output wire VAR86;
output wire VAR16;
input wire VAR62;
input wire [1 : 0] VAR76;
input wire [1 : 0] VAR101;
input wire VAR48;
output wire VAR5;
output wire [1 : 0] VAR41;
output wire [31 : 0] VAR9;
output wire [3 : 0] VAR95;
output wire [2 : 0] VAR6;
output wire [1 : 0] VAR43;
output wire [1 : 0] VAR14;
output wire [3 : 0] VAR37;
output wire [2 : 0] VAR13;
output wire [3 : 0] VAR83;
output wire VAR59;
input wire VAR71;
input wire [1 : 0] VAR12;
input wire [63 : 0] VAR64;
input wire [1 : 0] VAR46;
input wire VAR66;
input wire VAR108;
output wire VAR61;
VAR99 #(
.VAR70("VAR3"),
.VAR88(1),
.VAR27(0),
.VAR4(0),
.VAR18(2),
.VAR79(32),
.VAR47(64),
.VAR31(1),
.VAR28(1),
.VAR80(0),
.VAR107(1),
.VAR105(1),
.VAR50(1),
.VAR103(1),
.VAR39(1),
.VAR68(2)
) VAR1 (
.VAR74(VAR74),
.VAR26(VAR26),
.VAR40(VAR40),
.VAR57(VAR57),
.VAR54(VAR54),
.VAR34(VAR34),
.VAR21(VAR21),
.VAR38(VAR38),
.VAR53(VAR53),
.VAR106(VAR106),
.VAR29(VAR29),
.VAR23(VAR23),
.VAR51(1'VAR11),
.VAR30(VAR30),
.VAR104(VAR104),
.VAR112(2'VAR11),
.VAR82(VAR82),
.VAR22(VAR22),
.VAR42(VAR42),
.VAR36(1'VAR11),
.VAR55(VAR55),
.VAR92(VAR92),
.VAR32(VAR32),
.VAR56(VAR56),
.VAR90(),
.VAR45(VAR45),
.VAR96(VAR96),
.VAR49(VAR49),
.VAR75(VAR75),
.VAR2(VAR2),
.VAR24(VAR24),
.VAR77(VAR77),
.VAR15(VAR15),
.VAR17(VAR17),
.VAR93(VAR93),
.VAR25(VAR25),
.VAR63(VAR63),
.VAR111(1'VAR11),
.VAR73(VAR73),
.VAR98(VAR98),
.VAR33(VAR33),
.VAR19(VAR19),
.VAR91(VAR91),
.VAR97(VAR97),
.VAR85(),
.VAR44(VAR44),
.VAR84(VAR84),
.VAR69(VAR69),
.VAR109(VAR109),
.VAR10(VAR10),
.VAR60(VAR60),
.VAR52(VAR52),
.VAR65(VAR65),
.VAR81(VAR81),
.VAR78(VAR78),
.VAR8(),
.VAR7(VAR7),
.VAR35(),
.VAR87(VAR87),
.VAR72(VAR72),
.VAR102(VAR102),
.VAR58(VAR58),
.VAR100(VAR100),
.VAR86(VAR86),
.VAR89(),
.VAR16(VAR16),
.VAR62(VAR62),
.VAR76(VAR76),
.VAR101(VAR101),
.VAR20(1'VAR11),
.VAR48(VAR48),
.VAR5(VAR5),
.VAR41(VAR41),
.VAR9(VAR9),
.VAR95(VAR95),
.VAR6(VAR6),
.VAR43(VAR43),
.VAR14(VAR14),
.VAR37(VAR37),
.VAR13(VAR13),
.VAR110(),
.VAR83(VAR83),
.VAR67(),
.VAR59(VAR59),
.VAR71(VAR71),
.VAR12(VAR12),
.VAR64(VAR64),
.VAR46(VAR46),
.VAR66(VAR66),
.VAR94(1'VAR11),
.VAR108(VAR108),
.VAR61(VAR61)
);
endmodule | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s1_jtag_debug_module_tck.v | 8,218 | module MODULE1 (
VAR28,
VAR24,
VAR37,
VAR3,
VAR39,
VAR27,
VAR6,
VAR21,
VAR36,
VAR19,
VAR9,
VAR1,
VAR20,
VAR11,
VAR23,
VAR8,
VAR10,
VAR22,
VAR35,
VAR30,
VAR12,
VAR32,
VAR31,
VAR15,
VAR7,
VAR38,
VAR29,
VAR17,
VAR25,
VAR34,
VAR26
)
;
output [ 1: 0] VAR29;
output VAR17;
output [ 37: 0] VAR25;
output VAR34;
output VAR26;
input [ 31: 0] VAR28;
input [ 31: 0] VAR24;
input VAR37;
input VAR3;
input VAR39;
input VAR27;
input VAR6;
input [ 1: 0] VAR21;
input VAR36;
input VAR19;
input VAR9;
input VAR1;
input VAR20;
input VAR11;
input VAR23;
input VAR8;
input [ 35: 0] VAR10;
input VAR22;
input [ 6: 0] VAR35;
input VAR30;
input VAR12;
input VAR32;
input VAR31;
input VAR15;
input VAR7;
input VAR38;
reg [ 2: 0] VAR2 ;
wire VAR13;
reg [ 1: 0] VAR29;
wire VAR17;
wire VAR16;
reg [ 37: 0] VAR25 ;
wire VAR34;
wire VAR26;
wire VAR18;
wire VAR14;
always @(posedge VAR11)
begin
if (VAR15)
case (VAR21)
2'b00: begin
VAR25[35] <= VAR13;
VAR25[34] <= VAR19;
VAR25[33] <= VAR20;
VAR25[32 : 1] <= VAR28;
VAR25[0] <= VAR16;
end
2'b01: begin
VAR25[35 : 0] <= VAR10;
VAR25[37] <= VAR22;
VAR25[36] <= VAR8;
end
2'b10: begin
VAR25[37] <= VAR31;
VAR25[36] <= VAR27;
VAR25[35] <= VAR39;
VAR25[34] <= VAR3;
VAR25[33] <= VAR37;
VAR25[32 : 1] <= VAR24;
VAR25[0] <= VAR32;
end
2'b11: begin
VAR25[15 : 2] <= VAR35;
VAR25[1] <= VAR12;
VAR25[0] <= VAR30;
end
endcase if (VAR7)
case (VAR2)
3'b000: begin
VAR25 <= {VAR23, VAR25[37 : 2], VAR23};
end
3'b001: begin
VAR25 <= {VAR23, VAR25[37 : 9], VAR23, VAR25[7 : 1]};
end
3'b010: begin
VAR25 <= {VAR23, VAR25[37 : 17], VAR23, VAR25[15 : 1]};
end
3'b011: begin
VAR25 <= {VAR23, VAR25[37 : 33], VAR23, VAR25[31 : 1]};
end
3'b100: begin
VAR25 <= {VAR23, VAR25[37], VAR23, VAR25[35 : 1]};
end
3'b101: begin
VAR25 <= {VAR23, VAR25[37 : 1]};
end
default: begin
VAR25 <= {VAR23, VAR25[37 : 2], VAR23};
end
endcase if (VAR38)
case (VAR21)
2'b00: begin
VAR2 <= 3'b100;
end
2'b01: begin
VAR2 <= 3'b101;
end
2'b10: begin
VAR2 <= 3'b101;
end
2'b11: begin
VAR2 <= 3'b010;
end
endcase end
assign VAR26 = VAR25[0];
assign VAR34 = VAR36;
assign VAR18 = VAR17;
VAR4 VAR40
(
.clk (VAR11),
.din (VAR6),
.dout (VAR13),
.VAR1 (VAR18)
);
assign VAR14 = VAR17;
VAR4 VAR5
(
.clk (VAR11),
.din (VAR9),
.dout (VAR16),
.VAR1 (VAR14)
);
always @(posedge VAR11 or negedge VAR17)
begin
if (VAR17 == 0)
VAR29 <= 2'b0;
end
else
VAR29 <= {VAR13, VAR16};
end
assign VAR17 = VAR1;
endmodule | gpl-2.0 |
acapola/opendev | sfr_gen/trng_apbif.v | 6,896 | module MODULE1 (
output reg VAR36,
output reg VAR35,
output reg VAR22,
output reg VAR10,
output reg [32-1:0] VAR27,
output reg [32-1:0] VAR8,
output reg [32-1:0] VAR30,
output reg [128-1:0] VAR29,
output reg [32-1:0] VAR7,
input wire VAR31,
input wire VAR19,
input wire [32-1:0] VAR24,
input wire VAR18,
output reg VAR26,
input wire VAR32,
input wire VAR13,
input wire VAR12,
input wire VAR15,
input wire [11:0] VAR5,
input wire VAR33,
input wire VAR14,
input wire [3:0] VAR17,
input wire [31:0] VAR20,
output reg [31:0] VAR25,
output reg VAR9,
output reg VAR16
);
wire [32-1:0] VAR6 = {{28{1'b0}}
,VAR10
,VAR22
,VAR35
,VAR36
};
wire VAR23 = VAR15 & (VAR5 < 36);
assign VAR16 = 1'b0;
assign VAR9 = 1'b1;
wire VAR3 = VAR23 & VAR33 & VAR14 & VAR13;
wire VAR21 = VAR23 & ~VAR14;
wire VAR11 = VAR21 & ~VAR33;
wire VAR4 = VAR21 & VAR33;
reg [9:0] VAR2;
always @(posedge VAR32) if(VAR13) VAR2 <= VAR5[11:2];
reg VAR28;always @(posedge VAR32) begin
VAR28 <= VAR13 & VAR11;
end
reg [31:0] VAR34;
always @* begin
if(VAR28) VAR25 = VAR34;
end
reg VAR1;
always @* VAR26 = VAR28 & VAR1;
always @* begin
VAR34 = 32'hDEADBEEF;
{VAR1} = {1{1'b0}};
if (VAR21) begin
case(VAR2)
0: VAR34 = VAR6;
1: begin
VAR34 = VAR27;
VAR1 = 1'b1;
end
2: VAR34 = VAR8;
3: VAR34 = VAR30;
4: VAR34 = VAR29[0*32+:32];
5: VAR34 = VAR29[1*32+:32];
6: VAR34 = VAR29[2*32+:32];
7: VAR34 = VAR29[3*32+:32];
8: VAR34 = VAR7;
endcase
end
end
always @(posedge VAR32 or negedge VAR12) begin
if(~VAR12) begin
VAR36 <= 0;
VAR35 <= 0;
VAR22 <= 0;
VAR10 <= 0;
VAR27 <= 0;
VAR8 <= 0;
VAR30 <= 0;
VAR29 <= 0;
VAR7 <= 0;
end else begin
if(VAR3) begin
case(VAR2)
0: begin
if (VAR17[0]) VAR36 <= VAR20[0*8+0+:1];
if (VAR17[0]) VAR22 <= VAR20[0*8+2+:1];
if (VAR17[0]) VAR10 <= VAR20[0*8+3+:1];
end
1: begin
end
2: begin
if (VAR17[0]) VAR8[0*8+:8] <= VAR20[0*8+:8];
if (VAR17[1]) VAR8[1*8+:8] <= VAR20[1*8+:8];
if (VAR17[2]) VAR8[2*8+:8] <= VAR20[2*8+:8];
if (VAR17[3]) VAR8[3*8+:8] <= VAR20[3*8+:8];
end
3: begin
if (VAR17[0]) VAR30[0*8+:8] <= VAR20[0*8+:8];
if (VAR17[1]) VAR30[1*8+:8] <= VAR20[1*8+:8];
if (VAR17[2]) VAR30[2*8+:8] <= VAR20[2*8+:8];
if (VAR17[3]) VAR30[3*8+:8] <= VAR20[3*8+:8];
end
4: begin
if (VAR17[0]) VAR29[0*32+0*8+:8] <= VAR20[0*8+:8];
if (VAR17[1]) VAR29[0*32+1*8+:8] <= VAR20[1*8+:8];
if (VAR17[2]) VAR29[0*32+2*8+:8] <= VAR20[2*8+:8];
if (VAR17[3]) VAR29[0*32+3*8+:8] <= VAR20[3*8+:8];
end
5: begin
if (VAR17[0]) VAR29[1*32+0*8+:8] <= VAR20[0*8+:8];
if (VAR17[1]) VAR29[1*32+1*8+:8] <= VAR20[1*8+:8];
if (VAR17[2]) VAR29[1*32+2*8+:8] <= VAR20[2*8+:8];
if (VAR17[3]) VAR29[1*32+3*8+:8] <= VAR20[3*8+:8];
end
6: begin
if (VAR17[0]) VAR29[2*32+0*8+:8] <= VAR20[0*8+:8];
if (VAR17[1]) VAR29[2*32+1*8+:8] <= VAR20[1*8+:8];
if (VAR17[2]) VAR29[2*32+2*8+:8] <= VAR20[2*8+:8];
if (VAR17[3]) VAR29[2*32+3*8+:8] <= VAR20[3*8+:8];
end
7: begin
if (VAR17[0]) VAR29[3*32+0*8+:8] <= VAR20[0*8+:8];
if (VAR17[1]) VAR29[3*32+1*8+:8] <= VAR20[1*8+:8];
if (VAR17[2]) VAR29[3*32+2*8+:8] <= VAR20[2*8+:8];
if (VAR17[3]) VAR29[3*32+3*8+:8] <= VAR20[3*8+:8];
end
8: begin
if (VAR17[0]) VAR7[0*8+:8] <= VAR20[0*8+:8];
if (VAR17[1]) VAR7[1*8+:8] <= VAR20[1*8+:8];
if (VAR17[2]) VAR7[2*8+:8] <= VAR20[2*8+:8];
if (VAR17[3]) VAR7[3*8+:8] <= VAR20[3*8+:8];
end
endcase
end else begin end
if (VAR19) VAR35 <= VAR31;
if (VAR18) VAR27 <= VAR24;
end
end
endmodule | mit |
mda-ut/SubZero | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/power_management.v | 1,811 | module MODULE1 (
output reg VAR5,
output reg [2:0] sel,
output VAR9,
input ack,
input VAR6,
input VAR1,
input clk
);
reg [9:0] VAR2;
reg [3:0] VAR7;
reg [15:0] VAR8;
reg VAR10;
always @(posedge clk)
if (VAR1 == 1'd0)
begin
VAR5 <= 1'b0;
sel <= 3'b111;
VAR2 = 10'd0;
VAR10 = 1'b0;
VAR7 = VAR3;
VAR8 = VAR4;
end
else
begin
VAR5 <= 1'b1;
if (!VAR10)
VAR2 <= VAR2 + 10'd1;
if (ack)
VAR10 <= 1'b0;
if (!VAR10 && VAR2 == 10'd0)
begin
if (VAR7 != 4'd0)
VAR7 <= VAR7 - 4'd1;
if (VAR8 != 16'd0)
VAR8 <= VAR8 - 16'd1;
if (sel == 3'd6)
begin
sel <= 3'b000;
end
else
sel <= sel + 3'b001;
end
if (&VAR2 && !(&sel)
&& ((VAR6 == 1'b0 && sel[0] == 1'b0 && VAR8 == 6'd0)
|| (VAR6 == 1'b1 && sel[0] == 1'b1 && VAR7 == 20'd0)))
begin
VAR10 <= 1'd1;
end
end
assign VAR9 = VAR10;
endmodule | mit |
unihd-cag/openhmc | rtl/hmc_controller/openhmc_top.v | 25,571 | module MODULE1 #(
parameter VAR72 = 4, parameter VAR41 = 2, parameter VAR64 = VAR72*128, parameter VAR172 = 3, parameter VAR184 = 2**VAR172, parameter VAR218 = VAR72*16, parameter VAR108 = 64, parameter VAR138 = 64, parameter VAR31 = 4, parameter VAR59 = 8, parameter VAR166 = 10, parameter VAR80 = 1, parameter VAR14 = 1, parameter VAR202 = 1, parameter VAR185 = 1, parameter VAR167 = 1, parameter VAR53 = 0, parameter VAR79 = 1, parameter VAR150 = 5, parameter VAR60 = 0, parameter VAR104 = 1, parameter VAR158 = 1,
parameter VAR86 = 1 ) (
input wire VAR2, input wire VAR110, input wire VAR97, input wire VAR160,
input wire VAR165,
output wire VAR76,
input wire [VAR64-1:0] VAR36,
input wire [VAR218-1:0] VAR177,
output wire VAR47,
input wire VAR129,
output wire [VAR64-1:0] VAR179,
output wire [VAR218-1:0] VAR191,
output wire [VAR64-1:0] VAR173, input wire [VAR64-1:0] VAR148, output wire [VAR184-1:0] VAR89, output wire [VAR184-1:0] VAR159, input wire VAR100, input wire VAR65, output wire VAR193,
output wire VAR211,
output wire VAR94,
input wire VAR11,
input wire VAR70,
input wire [VAR31-1:0] VAR126,
output wire [VAR138-1:0] VAR146,
output wire VAR140,
output wire VAR7,
input wire VAR118,
input wire VAR84,
input wire [VAR108-1:0] VAR99
);
localparam VAR75 = (VAR72 == 2) ? 6 :
(VAR72 == 4) ? 7 :
8;
localparam VAR91 = 48;
localparam VAR91 = 64;
wire [4*VAR72-1:0] VAR120;
assign VAR191 = {{VAR218-(4*VAR72){1'b0}}, VAR120};
wire VAR35;
assign VAR76 = ~VAR35;
wire VAR134;
assign VAR47 = ~VAR134;
wire [VAR64-1:0] VAR44;
wire VAR139;
wire VAR151;
wire VAR181;
wire [3*VAR72-1:0] VAR106;
wire [VAR64-1:0] VAR162;
wire VAR199;
wire VAR113;
wire [4*VAR72-1:0] VAR204;
wire VAR174;
wire VAR137;
wire VAR197;
wire [7:0] VAR61;
wire [7:0] VAR149;
wire [VAR75-1:0]VAR145;
wire [VAR41:0] VAR189;
wire [VAR41:0] VAR200;
wire VAR67;
wire VAR112;
wire VAR178;
wire [VAR91-1:0] VAR54;
wire [VAR91-1:0] VAR214;
wire [VAR91-1:0] VAR58;
wire [VAR91-1:0] VAR28;
wire [VAR91-1:0] VAR93;
wire VAR21;
wire [2:0] VAR128;
wire [1:0] VAR209;
wire [VAR166-1:0]VAR123;
wire [VAR59-1:0]VAR157;
wire VAR147;
wire [VAR184-1:0] VAR95;
wire [VAR184-1:0] VAR34;
wire VAR168;
wire VAR39;
wire VAR198;
wire VAR122;
wire [VAR184-1:0] VAR33;
wire [VAR184-1:0] VAR180;
wire [VAR59-1:0]VAR136;
wire VAR207;
wire [4:0] VAR17;
wire [4:0] VAR40;
wire VAR62;
assign VAR193 = VAR168;
wire VAR109;
wire [VAR59-1:0] VAR208;
generate
if(VAR167==1) begin : VAR30
assign VAR122 = VAR109;
end else begin : VAR37
assign VAR122 = 1'b0;
end
if(VAR53==1) begin : VAR66
assign VAR136 = {VAR59{1'b0}};
end else begin : VAR52
assign VAR136 = VAR208;
end
endgenerate
assign VAR159 = (VAR202==1) ? {VAR184{1'b0}} : VAR33;
generate
if(VAR60==0) begin : VAR153
VAR45 #(
.VAR64(VAR64+(VAR72*3)),
.VAR135(16)
) VAR115 (
.VAR190(VAR2),
.VAR78(VAR110),
.VAR176(VAR97),
.VAR3(VAR160),
.din({VAR177[(VAR72*3)-1:0],VAR36}),
.VAR141(VAR165 && VAR76),
.VAR16(VAR35),
.VAR42(),
.dout({VAR106,VAR44}),
.VAR23(VAR139),
.VAR154(VAR151),
.VAR188(VAR181)
);
end else begin : VAR50
VAR132 #(
.VAR64(VAR64+(VAR72*3))
) VAR12(
.clk(VAR110),
.VAR24(VAR160),
.din({VAR177[(VAR72*3)-1:0],VAR36}),
.VAR141(VAR165 && VAR76),
.VAR16(VAR35),
.VAR42(),
.dout({VAR106,VAR44}),
.VAR23(VAR139),
.VAR154(VAR151),
.VAR188(VAR181)
);
VAR15 #(
.VAR64(VAR64+(VAR72*3)),
.VAR135(4)
) VAR88(
.clk(VAR110),
.VAR24(VAR160),
.din({VAR177[(VAR72*3)-1:0],VAR36}),
.VAR141(VAR165 && VAR76),
.VAR16(VAR35),
.VAR42(),
.dout({VAR106,VAR44}),
.VAR23(VAR139),
.VAR154(VAR151),
.VAR188(VAR181)
);
end
endgenerate
VAR215 #(
.VAR41(VAR41),
.VAR72(VAR72),
.VAR184(VAR184),
.VAR91(VAR91),
.VAR80(VAR80),
.VAR75(VAR75),
.VAR59(VAR59),
.VAR166(VAR166),
.VAR104(VAR104),
.VAR86(VAR86),
.VAR53(VAR53)
) VAR56(
.clk(VAR110),
.VAR24(VAR160),
.VAR127(VAR173),
.VAR94(VAR94),
.VAR11(VAR11),
.VAR196(VAR44),
.VAR27(VAR106[VAR72-1:0]),
.VAR48(VAR106[(2*VAR72)-1:1*VAR72]),
.VAR26(VAR106[(3*VAR72)-1:(2*VAR72)]),
.VAR142(VAR151),
.VAR175(VAR181),
.VAR46(VAR139),
.VAR87(VAR174),
.VAR131(VAR137),
.VAR119(VAR197),
.VAR186(VAR61),
.VAR13(VAR149),
.VAR216(VAR145),
.VAR96(VAR189),
.VAR206(VAR200),
.VAR67(VAR67),
.VAR18(VAR214),
.VAR32(VAR58),
.VAR98(VAR28),
.VAR112(VAR112),
.VAR178(VAR178),
.VAR107(VAR128==3'b010),
.VAR212(VAR21),
.VAR102(VAR147),
.VAR209(VAR209),
.VAR123(VAR123),
.VAR157(VAR157),
.VAR155(VAR39),
.VAR198(VAR198),
.VAR122(VAR122),
.VAR136(VAR136),
.VAR40(VAR40),
.VAR62(VAR62)
);
VAR55 #(
.VAR41(VAR41),
.VAR72(VAR72),
.VAR172(VAR172),
.VAR91(VAR91),
.VAR104(VAR104),
.VAR59(VAR59),
.VAR75(VAR75),
.VAR150(VAR150),
.VAR202(VAR202),
.VAR14(VAR14),
.VAR185(VAR185),
.VAR158(VAR158),
.VAR53(VAR53),
.VAR79(VAR79)
) VAR169 (
.clk(VAR110),
.VAR24(VAR160),
.VAR143(VAR148),
.VAR89(VAR89),
.VAR164(VAR65),
.VAR152(VAR162),
.VAR73(VAR113),
.VAR192(VAR199),
.VAR194(VAR204),
.VAR183(VAR174),
.VAR161(VAR137),
.VAR111(VAR197),
.VAR114(VAR61),
.VAR101(VAR149),
.VAR103(VAR145),
.VAR195(VAR189),
.VAR8(VAR200),
.VAR54(VAR54),
.VAR163(VAR93),
.VAR21(VAR21),
.VAR128(VAR128),
.VAR116(~VAR11),
.VAR147(VAR147),
.VAR95(VAR95),
.VAR34(VAR34),
.VAR180(VAR180),
.VAR33(VAR33),
.VAR122(VAR122),
.VAR207(VAR207),
.VAR17(VAR17)
);
generate
if(VAR60==0) begin : VAR144
VAR45 #(
.VAR64(VAR64+(VAR72*4)),
.VAR135(16)
) VAR210(
.VAR190(VAR110),
.VAR78(VAR2),
.VAR176(VAR160),
.VAR3(VAR97),
.din({VAR204,VAR162}),
.VAR141(VAR199),
.VAR16(),
.VAR42(VAR113),
.dout({VAR120,VAR179}),
.VAR23(VAR47 && VAR129),
.VAR154(VAR134),
.VAR188()
);
end else begin : VAR105
VAR132 #(
.VAR64(VAR64+(VAR72*4))
) VAR81(
.clk(VAR110),
.VAR24(VAR160),
.din({VAR204,VAR162}),
.VAR141(VAR199),
.VAR16(),
.VAR42(VAR113),
.dout({VAR120,VAR179}),
.VAR23(VAR47 && VAR129),
.VAR154(VAR134),
.VAR188()
);
VAR15 #(
.VAR64(VAR64+(VAR72*4)),
.VAR135(4)
) VAR203(
.clk(VAR110),
.VAR24(VAR160),
.din({VAR204,VAR162}),
.VAR141(VAR199),
.VAR16(),
.VAR42(VAR113),
.dout({VAR120,VAR179}),
.VAR23(VAR47 && VAR129),
.VAR154(VAR134),
.VAR188()
);
end
endgenerate
VAR6 #(
.VAR184(VAR184),
.VAR104(VAR104),
.VAR59(VAR59),
.VAR166(VAR166),
.VAR91(VAR91),
.VAR108(VAR108),
.VAR31(VAR31),
.VAR138(VAR138)
) VAR51 (
.VAR24(VAR160),
.clk(VAR110),
.address(VAR126),
.VAR10(VAR146),
.VAR130(VAR140),
.VAR85(VAR7),
.VAR90(VAR118),
.VAR25(VAR84),
.VAR68(VAR99),
.VAR170(VAR21),
.VAR69(~VAR21),
.VAR125(~VAR11),
.VAR117(VAR70),
.VAR121(VAR100),
.VAR20(VAR65),
.VAR83(VAR207),
.VAR74(VAR123),
.VAR4(VAR157),
.VAR187(VAR33),
.VAR43(VAR180),
.VAR201(VAR34),
.VAR29(VAR95),
.VAR213(VAR147),
.VAR38(VAR128),
.VAR9(VAR209),
.VAR133(VAR58),
.VAR77(VAR214),
.VAR1(VAR28),
.VAR217(VAR54),
.VAR71(VAR93),
.VAR182(VAR67),
.VAR63(VAR197),
.VAR171(VAR112),
.VAR124(VAR178),
.VAR19(VAR211),
.VAR156(VAR168),
.VAR22(VAR39),
.VAR92(VAR198),
.VAR5(VAR109),
.VAR57(VAR62),
.VAR82(VAR208),
.VAR205(VAR17),
.VAR49(VAR40)
);
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v | 2,329 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR9 ,
VAR8,
VAR6 ,
VAR7 ,
VAR2 ,
VAR10
);
output VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR8;
input VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR10 ;
VAR5 VAR3 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR1 ,
VAR4 ,
VAR9 ,
VAR8
);
output VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR8;
supply1 VAR6;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR10 ;
VAR5 VAR3 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlxtp/sky130_fd_sc_lp__srdlxtp.behavioral.v | 1,907 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR3 ,
VAR15
);
output VAR11 ;
input VAR7 ;
input VAR3 ;
input VAR15;
supply1 VAR16;
supply1 VAR5 ;
supply0 VAR2 ;
supply1 VAR6 ;
supply0 VAR8 ;
wire VAR4 ;
wire VAR9;
wire VAR14 ;
reg VAR13 ;
wire VAR12 ;
VAR17 VAR10 (VAR4 , VAR14, VAR9, VAR15, VAR13, VAR16, VAR2, VAR5);
assign VAR12 = ( VAR15 === 1'b1 );
bufif1 VAR1 (VAR11 , VAR4, VAR5 );
endmodule | apache-2.0 |
lbl-cal/StanfordNoC | router/src/vcr_op_ctrl_mac.v | 13,182 | module MODULE1
(clk, reset, VAR38, VAR66, VAR27, VAR42,
VAR52, VAR31, VAR85, VAR61, VAR98, VAR14,
VAR76, VAR53, VAR77, VAR46, VAR81, VAR97,
VAR107);
parameter VAR95 = 32;
parameter VAR113 = 2;
parameter VAR32 = 2;
localparam VAR22 = VAR113 * VAR32;
parameter VAR54 = 1;
localparam VAR60 = VAR22 * VAR54;
localparam VAR87 = VAR8(VAR60);
parameter VAR58 = 5;
parameter VAR23 = VAR4;
parameter VAR118 = VAR96;
parameter VAR110 = 1;
localparam VAR41
= (VAR118 == VAR96) ? (1 + VAR87) :
-1;
parameter VAR109 = 1;
localparam VAR13 = VAR109 ? 1 : 0;
localparam VAR9
= (VAR23 == VAR114) ?
(1 + VAR87 + 1 + 1) :
(VAR23 == VAR101) ?
(1 + VAR87 + 1) :
(VAR23 == VAR4) ?
(1 + VAR87 + 1) :
-1;
parameter VAR88 = 64;
localparam VAR44
= VAR13 + VAR9 + VAR88;
parameter VAR62 = VAR63;
parameter VAR24 = VAR25;
parameter VAR12 = 0;
parameter VAR48 = VAR35;
localparam VAR90
= VAR110 && (VAR48 == VAR20);
parameter VAR18 = 1;
parameter VAR49 = VAR117;
input clk;
input reset;
input [0:VAR41-1] VAR38;
input VAR66;
input [0:VAR60-1] VAR27;
input [0:VAR60*VAR58-1] VAR42;
input [0:VAR60*VAR60-1] VAR52;
input VAR31;
input VAR85;
input [0:VAR58-1] VAR61;
input [0:VAR60-1] VAR98;
input VAR14;
input VAR76;
input [0:VAR88-1] VAR53;
output [0:VAR44-1] VAR77;
wire [0:VAR44-1] VAR77;
output [0:VAR60-1] VAR46;
wire [0:VAR60-1] VAR46;
output [0:VAR60-1] VAR81;
wire [0:VAR60-1] VAR81;
output [0:VAR60-1] VAR97;
wire [0:VAR60-1] VAR97;
output VAR107;
wire VAR107;
wire VAR50;
wire VAR29;
assign VAR29 = VAR50;
wire VAR80;
wire [0:VAR60-1] VAR3;
VAR33
.VAR118(VAR118),
.VAR49(VAR49))
VAR10
(.clk(clk),
.reset(reset),
.VAR7(VAR29),
.VAR38(VAR38),
.VAR17(VAR80),
.VAR56(VAR3));
wire VAR65;
wire VAR72, VAR39;
assign VAR72 = VAR85;
VAR103
.VAR49(VAR49))
VAR39
(.clk(clk),
.reset(reset),
.VAR7(VAR65),
.VAR99(VAR72),
.VAR28(VAR39));
assign VAR65 = VAR31 | VAR39;
wire VAR40, VAR93;
assign VAR40 = VAR85 ? VAR14 : VAR93;
VAR103
.VAR49(VAR49))
VAR93
(.clk(clk),
.reset(1'b0),
.VAR7(VAR31),
.VAR99(VAR40),
.VAR28(VAR93));
wire VAR82, VAR15;
assign VAR82 = VAR85 ? VAR76 : VAR15;
VAR103
.VAR49(VAR49))
VAR15
(.clk(clk),
.reset(1'b0),
.VAR7(VAR31),
.VAR99(VAR82),
.VAR28(VAR15));
wire [0:VAR60-1] VAR47;
wire VAR34;
generate
if(VAR18)
assign VAR34 = VAR39 & (|VAR47);
else
assign VAR34 = VAR39;
endgenerate
wire VAR64;
assign VAR64 = VAR39 | VAR80;
wire [0:VAR60-1] VAR43;
wire [0:VAR60-1] VAR45;
wire [0:VAR60*2-1] VAR102;
VAR30
.VAR95(VAR95),
.VAR118(VAR118),
.VAR110(VAR110),
.VAR73(VAR24),
.VAR90(VAR90),
.VAR12(VAR12),
.VAR49(VAR49))
VAR69
(.clk(clk),
.reset(reset),
.VAR7(VAR64),
.VAR116(VAR34),
.VAR14(VAR93),
.VAR76(VAR15),
.VAR47(VAR47),
.VAR80(VAR80),
.VAR3(VAR3),
.VAR50(VAR50),
.VAR43(VAR43),
.VAR46(VAR46),
.VAR81(VAR81),
.VAR45(VAR45),
.VAR59(VAR102));
genvar VAR67;
generate
for(VAR67 = 0; VAR67 < VAR60; VAR67 = VAR67 + 1)
begin:VAR106
wire VAR37;
assign VAR37 = VAR27[VAR67];
wire [0:VAR58-1] VAR83;
assign VAR83 = VAR42[VAR67*VAR58:(VAR67+1)*VAR58-1];
wire [0:VAR60-1] VAR100;
assign VAR100 = VAR52[VAR67*VAR60:(VAR67+1)*VAR60-1];
wire VAR1;
assign VAR1 = VAR3[VAR67];
wire VAR57;
assign VAR57 = VAR43[VAR67];
wire VAR105;
assign VAR105 = VAR81[VAR67];
wire VAR71;
assign VAR71 = VAR45[VAR67];
wire VAR16;
wire VAR111;
VAR6
.VAR58(VAR58),
.VAR18(VAR18),
.VAR48(VAR48),
.VAR49(VAR49))
VAR68
(.clk(clk),
.reset(reset),
.VAR66(VAR66),
.VAR37(VAR37),
.VAR83(VAR83),
.VAR100(VAR100),
.VAR31(VAR31),
.VAR85(VAR85),
.VAR61(VAR61),
.VAR98(VAR98),
.VAR116(VAR39),
.VAR76(VAR15),
.VAR16(VAR16),
.VAR111(VAR111),
.VAR105(VAR105),
.VAR71(VAR71),
.VAR57(VAR57));
assign VAR47[VAR67] = VAR16;
assign VAR97[VAR67] = VAR111;
end
endgenerate
wire VAR78;
generate
if(VAR18)
assign VAR78 = 1'b0;
else
assign VAR78 = VAR39 & ~|VAR47;
endgenerate
wire VAR19;
VAR21
VAR74
(.VAR11(VAR47),
.VAR92(VAR19));
wire VAR2;
assign VAR2 = VAR39 & VAR19;
wire VAR26;
assign VAR26 = VAR39;
VAR91
.VAR23(VAR23),
.VAR109(VAR109),
.VAR88(VAR88),
.VAR49(VAR49))
VAR94
(.clk(clk),
.reset(reset),
.VAR7(VAR26),
.VAR79(VAR34),
.VAR112(VAR93),
.VAR36(VAR15),
.VAR75(VAR53),
.VAR89(VAR47),
.VAR77(VAR77));
always @(posedge clk)
begin
if(VAR78)
if(VAR2)
end
generate
if(VAR62 != VAR84)
begin
wire [0:2+VAR60*2-1] VAR55, VAR70;
assign VAR55 = {VAR78,
VAR2,
VAR102};
VAR104
.VAR51(VAR62),
.VAR49(VAR49))
VAR86
(.clk(clk),
.reset(reset),
.VAR7(1'b1),
.VAR115(VAR55),
.VAR108(VAR70));
assign VAR107 = |VAR70;
end
else
assign VAR107 = 1'VAR5;
endgenerate
endmodule | bsd-2-clause |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_auto_pc_2/synth/tutorial_auto_pc_2.v | 13,148 | module MODULE1 (
VAR25,
VAR62,
VAR21,
VAR22,
VAR91,
VAR92,
VAR74,
VAR89,
VAR54,
VAR100,
VAR79,
VAR48,
VAR57,
VAR70,
VAR4,
VAR7,
VAR60,
VAR105,
VAR47,
VAR40,
VAR16,
VAR44,
VAR68,
VAR1,
VAR82,
VAR24,
VAR18,
VAR93,
VAR96,
VAR85,
VAR109,
VAR114,
VAR38,
VAR8,
VAR31,
VAR112,
VAR43,
VAR35,
VAR29,
VAR19,
VAR36,
VAR80,
VAR17,
VAR58,
VAR113,
VAR106,
VAR83,
VAR12,
VAR66,
VAR95,
VAR110,
VAR65,
VAR61,
VAR78,
VAR10,
VAR77,
VAR32,
VAR81,
VAR37
);
input wire VAR25;
input wire VAR62;
input wire [11 : 0] VAR21;
input wire [31 : 0] VAR22;
input wire [3 : 0] VAR91;
input wire [2 : 0] VAR92;
input wire [1 : 0] VAR74;
input wire [1 : 0] VAR89;
input wire [3 : 0] VAR54;
input wire [2 : 0] VAR100;
input wire [3 : 0] VAR79;
input wire VAR48;
output wire VAR57;
input wire [11 : 0] VAR70;
input wire [31 : 0] VAR4;
input wire [3 : 0] VAR7;
input wire VAR60;
input wire VAR105;
output wire VAR47;
output wire [11 : 0] VAR40;
output wire [1 : 0] VAR16;
output wire VAR44;
input wire VAR68;
input wire [11 : 0] VAR1;
input wire [31 : 0] VAR82;
input wire [3 : 0] VAR24;
input wire [2 : 0] VAR18;
input wire [1 : 0] VAR93;
input wire [1 : 0] VAR96;
input wire [3 : 0] VAR85;
input wire [2 : 0] VAR109;
input wire [3 : 0] VAR114;
input wire VAR38;
output wire VAR8;
output wire [11 : 0] VAR31;
output wire [31 : 0] VAR112;
output wire [1 : 0] VAR43;
output wire VAR35;
output wire VAR29;
input wire VAR19;
output wire [31 : 0] VAR36;
output wire [2 : 0] VAR80;
output wire VAR17;
input wire VAR58;
output wire [31 : 0] VAR113;
output wire [3 : 0] VAR106;
output wire VAR83;
input wire VAR12;
input wire [1 : 0] VAR66;
input wire VAR95;
output wire VAR110;
output wire [31 : 0] VAR65;
output wire [2 : 0] VAR61;
output wire VAR78;
input wire VAR10;
input wire [31 : 0] VAR77;
input wire [1 : 0] VAR32;
input wire VAR81;
output wire VAR37;
VAR108 #(
.VAR30("VAR75"),
.VAR111(2),
.VAR15(1),
.VAR63(0),
.VAR73(12),
.VAR46(32),
.VAR64(32),
.VAR23(1),
.VAR2(1),
.VAR41(0),
.VAR104(1),
.VAR107(1),
.VAR69(1),
.VAR102(1),
.VAR76(1),
.VAR42(2)
) VAR88 (
.VAR25(VAR25),
.VAR62(VAR62),
.VAR21(VAR21),
.VAR22(VAR22),
.VAR91(VAR91),
.VAR92(VAR92),
.VAR74(VAR74),
.VAR89(VAR89),
.VAR54(VAR54),
.VAR100(VAR100),
.VAR53(4'VAR5),
.VAR79(VAR79),
.VAR26(1'VAR5),
.VAR48(VAR48),
.VAR57(VAR57),
.VAR70(VAR70),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR60(VAR60),
.VAR52(1'VAR5),
.VAR105(VAR105),
.VAR47(VAR47),
.VAR40(VAR40),
.VAR16(VAR16),
.VAR97(),
.VAR44(VAR44),
.VAR68(VAR68),
.VAR1(VAR1),
.VAR82(VAR82),
.VAR24(VAR24),
.VAR18(VAR18),
.VAR93(VAR93),
.VAR96(VAR96),
.VAR85(VAR85),
.VAR109(VAR109),
.VAR9(4'VAR5),
.VAR114(VAR114),
.VAR11(1'VAR5),
.VAR38(VAR38),
.VAR8(VAR8),
.VAR31(VAR31),
.VAR112(VAR112),
.VAR43(VAR43),
.VAR35(VAR35),
.VAR13(),
.VAR29(VAR29),
.VAR19(VAR19),
.VAR103(),
.VAR36(VAR36),
.VAR45(),
.VAR27(),
.VAR28(),
.VAR67(),
.VAR14(),
.VAR80(VAR80),
.VAR50(),
.VAR3(),
.VAR20(),
.VAR17(VAR17),
.VAR58(VAR58),
.VAR34(),
.VAR113(VAR113),
.VAR106(VAR106),
.VAR59(),
.VAR6(),
.VAR83(VAR83),
.VAR12(VAR12),
.VAR51(12'VAR98),
.VAR66(VAR66),
.VAR39(1'VAR5),
.VAR95(VAR95),
.VAR110(VAR110),
.VAR71(),
.VAR65(VAR65),
.VAR33(),
.VAR56(),
.VAR72(),
.VAR86(),
.VAR94(),
.VAR61(VAR61),
.VAR90(),
.VAR101(),
.VAR55(),
.VAR78(VAR78),
.VAR10(VAR10),
.VAR87(12'VAR98),
.VAR77(VAR77),
.VAR32(VAR32),
.VAR84(1'VAR49),
.VAR99(1'VAR5),
.VAR81(VAR81),
.VAR37(VAR37)
);
endmodule | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_data_pipeline.v | 7,324 | module MODULE1
parameter VAR29 = 128,
parameter VAR21 = 1,
parameter VAR12 = 1,
parameter VAR28 = 256,
parameter VAR6 = 10,
parameter VAR31 = "VAR26"
)
(
input VAR19,
input VAR15,
input VAR27,
input [VAR29-1:0] VAR24,
input VAR17,
input [VAR33(VAR29/32)-1:0] VAR32,
input VAR23,
input [VAR33(VAR29/32)-1:0] VAR25,
output VAR1,
input [(VAR29/32)-1:0] VAR18,
output [VAR29-1:0] VAR7,
output [(VAR29/32)-1:0] VAR36,
output VAR3,
output [(VAR29/32)-1:0] VAR4
);
wire VAR20;
wire VAR34;
wire VAR11;
wire [VAR29-1:0] VAR9;
wire [(VAR29/32)-1:0] VAR5;
wire [(VAR29/32)-1:0] VAR30;
VAR16
.VAR12 (0),
.VAR21 (VAR21),
.VAR29 (VAR29),
.VAR31 (VAR31))
VAR2
(
.VAR1 (VAR1),
.VAR7 (VAR9),
.VAR35 (VAR20),
.VAR3 (VAR11),
.VAR4 (VAR30),
.VAR36 (VAR5),
.VAR24 (VAR24[VAR29-1:0]),
.VAR27 (VAR27),
.VAR17 (VAR17),
.VAR32 (VAR32[VAR33(VAR29/32)-1:0]),
.VAR23 (VAR23),
.VAR25 (VAR25[VAR33(VAR29/32)-1:0]),
.VAR13 (VAR34),
.VAR19 (VAR19),
.VAR15 (VAR15));
VAR8
.VAR12 (VAR12),
.VAR21 (1),
.VAR6 (VAR6),
.VAR28 (VAR28),
.VAR29 (VAR29))
VAR22
(
.VAR1 (VAR34),
.VAR7 (VAR7[VAR29-1:0]),
.VAR3 (VAR3),
.VAR4 (VAR4[(VAR29/32)-1:0]),
.VAR36 (VAR36[(VAR29/32)-1:0]),
.VAR24 (VAR9),
.VAR27 (VAR20),
.VAR17 (VAR11),
.VAR14 (VAR30),
.VAR10 (VAR5),
.VAR18 (VAR18),
.VAR19 (VAR19),
.VAR15 (VAR15));
endmodule | gpl-3.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v | 28,427 | module MODULE1 (
VAR104,
VAR11,
VAR84,
VAR207,
VAR235,
VAR120,
VAR155,
VAR198,
VAR151,
VAR173,
VAR5,
VAR160,
VAR187,
VAR204,
VAR47,
VAR115,
VAR199,
VAR244,
VAR40,
VAR79,
VAR98,
VAR183,
VAR61,
VAR177,
VAR221,
VAR184,
VAR253,
VAR188,
VAR95,
VAR257,
VAR234,
VAR7,
VAR27,
VAR174,
VAR90,
VAR197,
VAR82,
VAR156,
VAR162,
VAR42,
VAR167,
VAR18,
VAR141,
VAR172,
VAR225,
VAR6,
VAR239,
VAR3,
VAR20,
VAR107,
VAR213,
VAR214,
VAR77,
VAR48,
VAR186,
VAR242,
VAR128,
VAR144,
VAR64,
VAR161,
VAR44,
VAR150,
VAR132,
VAR189,
VAR125,
VAR51,
VAR223,
VAR55,
VAR166,
VAR66,
VAR219,
VAR147,
VAR220,
VAR34,
VAR175,
VAR217,
VAR218,
VAR9,
VAR233,
VAR37,
VAR137,
VAR249,
VAR100,
VAR93,
VAR135,
VAR46,
VAR31,
VAR238,
VAR73,
VAR133,
VAR92,
VAR54,
VAR121,
VAR28,
VAR15,
VAR170,
VAR146,
VAR43,
VAR32,
VAR159,
VAR102,
VAR236,
VAR212,
VAR57,
VAR10,
VAR70,
VAR153,
VAR110,
VAR111,
VAR80,
VAR191,
VAR113,
VAR230,
VAR208,
VAR36,
VAR87,
VAR19,
VAR169,
VAR86,
VAR226,
VAR52,
VAR75,
VAR112
);
parameter VAR67 = "";
parameter VAR62 = "false";
parameter VAR241 = "";
parameter VAR101 = "";
parameter VAR227 = "";
parameter VAR243 = "";
parameter VAR29 = "";
parameter VAR210 = "";
parameter VAR14 = "";
parameter VAR168 = "";
parameter VAR229 = "";
parameter VAR4 = "";
parameter VAR222 = "";
parameter VAR192 = "";
parameter VAR178 = "";
parameter VAR88 = "";
parameter VAR193 = "";
parameter VAR91 = "";
parameter VAR69 = "";
parameter VAR63 = "";
parameter VAR231 = "";
parameter VAR165 = "";
parameter VAR205 = "";
parameter VAR58 = "";
parameter VAR81 = "";
parameter VAR106 = "";
parameter VAR232 = "";
parameter VAR35 = "";
parameter VAR105 = "";
parameter VAR129 = "";
parameter VAR103 = "";
localparam VAR216 = 4;
localparam VAR124 = 0;
localparam VAR114 = "true";
input VAR104; input VAR11; input VAR120; output VAR84; output VAR207; output VAR235;
input [VAR241-1:0] VAR155;
input [VAR101-1:0] VAR198;
input [19:0] VAR151;
input [2:0] VAR173;
input [1:0] VAR5;
input [1:0] VAR160;
input [0:0] VAR47;
input [1:0] VAR199;
input [0:0] VAR187;
input [0:0] VAR204;
input [0:0] VAR115;
input [0:0] VAR244;
input [4:0] VAR40;
output [3:0] VAR253;
output [4:0] VAR188;
input [79:0] VAR98; input [4:0] VAR79; input [9:0] VAR183;
output [79:0] VAR61; input [4:0] VAR177; input [4:0] VAR221; output [0:0] VAR184;
output VAR95; output VAR257;
input [15:0] VAR27; input VAR234;
output [31:0] VAR197;
output VAR90;
input VAR7;
input [31:0] VAR174;
input [7:0] VAR82;
input [7:0] VAR156;
input [7:0] VAR162;
input [7:0] VAR42;
input [7:0] VAR167;
input [7:0] VAR18;
input [23:0] VAR141;
input [7:0] VAR172;
input [7:0] VAR225;
input [7:0] VAR6;
input [7:0] VAR239;
input [15:0] VAR3;
input [7:0] VAR20;
input [7:0] VAR107;
input [63:0] VAR213;
input [11:0] VAR214;
input [3:0] VAR77;
input [3:0] VAR48;
input [7:0] VAR186;
input [3:0] VAR242;
input [7:0] VAR128;
input [19:0] VAR144;
output [179:0] VAR64;
input [179:0] VAR161;
input [89:0] VAR44;
input [19:0] VAR150;
input [9:0] VAR132;
input [19:0] VAR189;
input [9:0] VAR125;
input [4:0] VAR51;
input [9:0] VAR223;
input [9:0] VAR55;
input [9:0] VAR166;
output [4:0] VAR66;
input [24:0] VAR219;
input [9:0] VAR147;
input [7:0] VAR220;
input [3:0] VAR34;
input [3:0] VAR175;
input [3:0] VAR217;
output [4:0] VAR218;
output [3:0] VAR9;
output VAR233;
output VAR37;
output [VAR227-1:0] VAR137;
output [VAR243-1:0] VAR249;
output [VAR29-1:0] VAR100;
output [VAR210-1:0] VAR93;
output [VAR168-1:0] VAR135;
output [VAR222-1:0] VAR46;
output [VAR222-1:0] VAR31;
output [VAR222-1:0] VAR238;
output VAR73;
inout [VAR192-1:0] VAR133;
output [VAR4-1:0] VAR92;
output [VAR14-1:0] VAR54;
output [VAR14-1:0] VAR121;
inout [VAR229-1:0] VAR28;
inout [VAR229-1:0] VAR15;
output VAR170;
output VAR146;
input VAR43;
input [VAR178-1:0] VAR32;
input [VAR178-1:0] VAR159;
input [VAR192-1:0] VAR102;
input [VAR4-1:0] VAR236;
input [0:0] VAR212;
output [VAR178-1:0] VAR57;
output VAR10;
output VAR70;
output VAR153;
input VAR110; input VAR111; input VAR80; input VAR191; input VAR36; input VAR87;
input VAR19;
input VAR169;
input VAR86;
input VAR226;
input VAR113;
input VAR230;
input VAR208;
output VAR52;
output VAR75;
input [VAR193-1:0] VAR112;
wire [179:0] VAR39;
wire [4:0] VAR211;
wire [63:0] VAR256;
wire [11:0] VAR126;
wire [3:0] VAR164;
wire [3:0] VAR228;
wire [7:0] VAR134;
wire [3:0] VAR83;
wire [7:0] VAR209;
wire [19:0] VAR41;
wire [179:0] VAR116;
wire [89:0] VAR240;
wire [9:0] VAR136;
wire [9:0] VAR202;
wire [4:0] VAR108;
wire [4:0] VAR251;
wire [4:0] VAR200;
wire [9:0] VAR94;
wire [9:0] VAR140;
wire [9:0] VAR122;
wire [24:0] VAR60;
wire [9:0] VAR30;
wire [19:0] VAR145;
wire [7:0] VAR26;
wire [3:0] VAR23;
wire [3:0] VAR78;
wire [3:0] VAR148;
wire VAR96;
wire [VAR216-1:0] VAR152;
wire VAR85;
wire VAR65;
wire VAR170;
wire VAR146;
wire VAR245;
localparam VAR59 = 7'b1111111;
localparam VAR196 = VAR59;
localparam VAR118 = 1'b1;
localparam VAR50 = {VAR196, VAR118};
generate
if (VAR62 != "true") begin
reg [VAR105-1:0] VAR203 ;
always @(posedge VAR110)
VAR203 <= VAR50;
end
endgenerate
generate
if (VAR62 != "true") begin
VAR97 VAR252(
.VAR110 (VAR110),
.VAR80 (VAR80),
.VAR19 (VAR19),
.VAR169 (VAR169),
.VAR86 (VAR86),
.VAR185 (VAR226),
.VAR170 (VAR170),
.VAR146 (VAR146),
.VAR96 (VAR96),
.VAR120 (VAR120),
.VAR104 (VAR104),
.VAR11 (VAR11),
.VAR207 (VAR207),
.VAR152 (VAR152),
.VAR85 (VAR85),
.VAR65 (VAR65),
.VAR245 (VAR245)
);
end else begin
VAR97 VAR252(
.VAR110 (VAR110),
.VAR80 (VAR80),
.VAR19 (VAR19),
.VAR169 (VAR169),
.VAR86 (VAR86),
.VAR185 (VAR226),
.VAR170 (VAR170),
.VAR146 (VAR146),
.VAR96 (VAR96),
.VAR120 (VAR120),
.VAR104 (VAR104),
.VAR11 (VAR11),
.VAR207 (VAR207),
.VAR152 (VAR152),
.VAR85 (VAR85),
.VAR65 (VAR65),
.VAR245 (VAR245)
);
end
endgenerate
assign VAR10 = VAR169;
assign VAR153 = VAR65;
assign VAR52 = VAR87;
assign VAR75 = VAR120;
wire VAR190;
wire VAR1;
wire VAR49;
wire VAR179;
VAR195 # (
.VAR193 (VAR193),
.VAR124 (VAR124),
.VAR114 (VAR114),
.VAR62 (VAR62)
) VAR255 (
.VAR33 (VAR208),
.VAR89 (VAR36),
.VAR8 (VAR113),
.VAR112 (VAR112),
.VAR190 (VAR190),
.VAR1 (VAR1),
.VAR49 (VAR49),
.VAR179 (VAR179)
);
assign VAR70 = VAR190;
assign VAR235 = VAR152;
VAR149 VAR21 (
.VAR110 (VAR190),
.VAR86 (VAR1),
.VAR120 (VAR120),
.VAR80 (VAR49),
.VAR104 (VAR104),
.VAR11 (VAR11),
.VAR153 (VAR153),
.VAR84 (VAR84),
.VAR213 (VAR213),
.VAR214 (VAR214),
.VAR77 (VAR77),
.VAR48 (VAR48),
.VAR186 (VAR186),
.VAR242 (VAR242),
.VAR128 (VAR128),
.VAR144 (VAR144),
.VAR64 (VAR64),
.VAR161 (VAR161),
.VAR44 (VAR44),
.VAR150 (VAR150),
.VAR132 (VAR132),
.VAR189 (VAR189),
.VAR125 (VAR125),
.VAR51 (VAR51),
.VAR223 (VAR223),
.VAR55 (VAR55),
.VAR166 (VAR166),
.VAR66 (VAR66),
.VAR219 (VAR219),
.VAR147 (VAR147),
.VAR220 (VAR220),
.VAR34 (VAR34),
.VAR175 (VAR175),
.VAR217 (VAR217),
.VAR218 (VAR218),
.VAR9 (VAR9),
.VAR233 (VAR233),
.VAR37 (VAR37),
.VAR39 (VAR39),
.VAR211 (VAR211),
.VAR2 (VAR256),
.VAR171 (VAR126),
.VAR201 (VAR164),
.VAR17 (VAR228),
.VAR12 (VAR134),
.VAR181 (),
.VAR24 (VAR209),
.VAR41 (VAR41),
.VAR116 (VAR116),
.VAR240 (VAR240),
.VAR53 (),
.VAR136 (VAR136),
.VAR202 (VAR202),
.VAR108 (VAR108),
.VAR251 (VAR251),
.VAR200 (VAR200),
.VAR94 (VAR94),
.VAR140 (VAR140),
.VAR122 (VAR122),
.VAR60 (VAR60),
.VAR30 (VAR30),
.VAR145 (VAR145),
.VAR127 (VAR26),
.VAR250 (VAR23),
.VAR139 (VAR78),
.VAR254 (VAR148),
.VAR151 (VAR151),
.VAR173 (VAR173),
.VAR257 (VAR257),
.VAR95 (VAR95),
.VAR47 (VAR47),
.VAR5 (VAR5),
.VAR160 (VAR160),
.VAR183 (VAR183),
.VAR40 (VAR40),
.VAR244 (VAR244),
.VAR199 (VAR199),
.VAR187 (VAR187),
.VAR61 (VAR61),
.VAR177 (VAR177),
.VAR221 (VAR221),
.VAR184 (VAR184),
.VAR188 (VAR188),
.VAR115 (VAR115),
.VAR98 (VAR98),
.VAR79 (VAR79),
.VAR204 (VAR204),
.VAR253 (VAR253),
.VAR27 (VAR27),
.VAR234 (VAR234),
.VAR197 (VAR197),
.VAR13 (VAR146),
.VAR90 (VAR90),
.VAR7 (VAR7),
.VAR174 (VAR174),
.VAR82 (VAR82),
.VAR156 (VAR156),
.VAR162 (VAR162),
.VAR42 (VAR42),
.VAR167 (VAR167),
.VAR18 (VAR18),
.VAR141 (VAR141),
.VAR172 (VAR172),
.VAR225 (VAR225),
.VAR6 (VAR6),
.VAR239 (VAR239),
.VAR3 (VAR3),
.VAR20 (VAR20),
.VAR107 (VAR107),
.VAR237 ()
);
VAR117 #(
.VAR67(VAR67),
.VAR232(VAR232),
.VAR241(VAR241),
.VAR101(VAR101),
.VAR227(VAR227),
.VAR243(VAR243),
.VAR154(VAR29),
.VAR210(VAR210),
.VAR14(VAR14),
.VAR168(VAR168),
.VAR229(VAR229),
.VAR4(VAR4),
.VAR222(VAR222),
.VAR192(VAR192),
.VAR178(VAR178),
.VAR88(VAR88),
.VAR193(VAR193),
.VAR124(VAR124),
.VAR114(VAR114),
.VAR62(VAR62)
) VAR25 (
.VAR85 (VAR85),
.VAR152 (VAR152[1]),
.VAR155 (VAR155),
.VAR198 (VAR198),
.VAR256 (VAR256),
.VAR126 (VAR126),
.VAR209 (VAR209),
.VAR134 (VAR134),
.VAR26 (VAR26),
.VAR148 (VAR148),
.VAR23 (VAR23),
.VAR164 (VAR164),
.VAR228 (VAR228),
.VAR78 (VAR78),
.VAR180 (VAR137),
.VAR74 (VAR249),
.VAR68 (VAR100),
.VAR143 (VAR93),
.VAR38 (VAR135),
.VAR142 (VAR46),
.VAR248 (VAR31),
.VAR131 (VAR238),
.VAR45 (VAR73),
.VAR110 (VAR110),
.VAR191 (VAR191),
.VAR230 (VAR230),
.VAR208 (VAR208),
.VAR86 (VAR86),
.VAR1 (VAR1),
.VAR113 (VAR113),
.VAR36 (VAR36),
.VAR19 (VAR19),
.VAR80 (VAR179),
.VAR119 (VAR133),
.VAR16 (VAR92),
.VAR157 (VAR54),
.VAR76 (VAR121),
.VAR28 (VAR28),
.VAR15 (VAR15),
.VAR112 (VAR112),
.VAR185 (VAR226),
.VAR43 (VAR43),
.VAR32 (VAR32),
.VAR159 (VAR159),
.VAR102 (VAR102),
.VAR236 (VAR236),
.VAR212 (VAR212[0]),
.VAR41 (VAR41),
.VAR116 (VAR116),
.VAR30 (VAR30),
.VAR145 (VAR145),
.VAR136 (VAR136),
.VAR122 (VAR122),
.VAR108 (VAR108),
.VAR251 (VAR251),
.VAR200 (VAR200),
.VAR140 (VAR140),
.VAR60 (VAR60),
.VAR211 (VAR211),
.VAR39 (VAR39),
.VAR94 (VAR94),
.VAR202 (VAR202),
.VAR240 (VAR240),
.VAR57 (VAR57)
);
generate
if (VAR62 != "true") begin
reg VAR158 ;
always @(posedge VAR110)
VAR158 <= ~VAR158;
reg VAR71 ;
always @(posedge VAR111)
VAR71 <= ~VAR71;
reg VAR176 ;
always @(posedge VAR86)
VAR176 <= ~VAR176;
reg VAR206 ;
always @(posedge VAR226)
VAR206 <= ~VAR206;
end
endgenerate
function integer VAR99;
input integer VAR72;
begin
VAR72 = VAR72 - 1;
for (VAR99 = 0; VAR72 > 0; VAR99 = VAR99 + 1)
VAR72 = VAR72 >> 1;
end
endfunction
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tap/sky130_fd_sc_ls__tap.pp.symbol.v | 1,217 | module MODULE1 (
input VAR1 ,
input VAR2,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_arb_select.v | 26,779 | module MODULE1 #
(
parameter VAR14 = 100,
parameter VAR116 = "VAR142",
parameter VAR117 = "1T",
parameter VAR21 = 11,
parameter VAR8 = 3,
parameter VAR166 = "8",
parameter VAR122 = 4,
parameter VAR82 = 5,
parameter VAR112 = 5,
parameter VAR161 = 31,
parameter VAR78 = 8,
parameter VAR4 = "VAR95",
parameter VAR164 = "VAR142",
parameter VAR91 = "VAR142",
parameter VAR19 = 4,
parameter VAR99 = 2,
parameter VAR81 = 1,
parameter VAR52 = "VAR113",
parameter VAR60 = 2,
parameter VAR66 = 1,
parameter VAR103 = 15,
parameter VAR17 = 2,
parameter VAR59 = 63,
parameter VAR156 = 16,
parameter VAR129 = "40",
parameter VAR148 = "120",
parameter VAR83 = 8'b00000101,
parameter VAR74 = 8'b00001010
)
(
output wire VAR155,
output wire [VAR17-1:0] VAR6,
output wire [VAR8-1:0] VAR98,
output wire [VAR156-1:0] VAR154,
output wire VAR85,
output wire VAR30,
output wire VAR75,
output wire [VAR156-1:0] VAR58,
output wire [VAR78-1:0] VAR138,
output wire [VAR78-1:0] VAR46,
output wire [VAR99-1:0] VAR55,
output wire [VAR99-1:0] VAR5,
output wire [VAR99-1:0] VAR44,
output wire [VAR99*VAR156-1:0] VAR79,
output wire [VAR99*VAR8-1:0] VAR56,
output wire [VAR122*VAR81*VAR99-1:0] VAR89,
output wire [1:0] VAR118,
output wire [VAR99-1:0] VAR168,
output wire [3:0] VAR31,
output wire [3:0] VAR88,
output [2:0] VAR152,
output wire [5:0] VAR144,
output wire [5:0] VAR147,
output wire [5:0] VAR111,
output wire [1:0] VAR64,
output wire [VAR17-1:0] VAR143,
input clk,
input rst,
input VAR119,
input [VAR103:0] VAR53,
input [VAR21:0] VAR157,
input [VAR19-1:0] VAR150,
input [VAR19-1:0] VAR153,
input [VAR19-1:0] VAR25,
input [VAR19-1:0] VAR146,
input [VAR19-1:0] VAR16,
input [VAR59:0] VAR61,
input [VAR19-1:0] VAR134,
input VAR141,
input VAR159,
input VAR39,
input VAR41,
input [VAR17-1:0] VAR130,
input [VAR19-1:0] VAR73,
input [VAR19-1:0] VAR48,
input [VAR19-1:0] VAR71,
input [VAR59:0] VAR93,
input [VAR59:0] VAR120,
input [VAR161:0] VAR42,
input [VAR19-1:0] VAR151,
input [VAR19-1:0] VAR108,
input [6*VAR66-1:0] VAR3,
input [6*VAR66-1:0] VAR2,
input [6*VAR66-1:0] VAR104,
input [5:0] VAR167,
input [VAR19-1:0] VAR165,
input VAR24,
input [7:0] VAR67,
input [7:0] VAR115,
input VAR27,
input VAR77,
input VAR10,
input VAR38,
input VAR125,
input VAR50,
input VAR32,
input VAR36,
input VAR135,
input VAR63,
input VAR26,
input VAR96,
input VAR62
);
localparam VAR124 = VAR17 + VAR8 + VAR156 + 1 + 1 + 1;
reg VAR110;
reg VAR45 = 1'b0;
reg [VAR124-1:0] VAR123 = {VAR124 {1'b0}};
reg [VAR124-1:0] VAR51 = {VAR124 {1'b0}};
reg [5:0] VAR7;
reg [5:0] VAR57;
reg [5:0] VAR101;
assign VAR31[0] = (VAR39 || VAR41) & VAR141;
assign VAR31[2] = 1'b0;
reg VAR40;
reg VAR92;
generate
if(VAR52 == "VAR113")begin
always @(posedge clk)
begin
if (rst)
VAR40 = 1'b1;
end
else
VAR40 = VAR92;
end
always @(*)
begin
VAR92 = 1'b1;
if (VAR39 & VAR141)
VAR92 = 1'b0;
end
else if (VAR40==1'b0)
begin
if (VAR41 & VAR141)
VAR92 = 1'b1;
end
else
VAR92 = 1'b0;
end
end
end
endgenerate
assign VAR88 = 4'b0;
assign VAR152[0] = VAR135;
assign VAR152[1] = VAR116 == "VAR12" ?
VAR135 && VAR45 :
VAR135 && VAR110;
assign VAR152[2] = ~VAR135;
always @(VAR3 or VAR2 or VAR104) begin
VAR7 = VAR3[5:0];
VAR57 = VAR2[5:0];
VAR101 = VAR104[5:0];
end
generate
if(VAR116 == "VAR12") begin : VAR34
assign VAR144 = ~VAR135 ?
6'b0 :
VAR45 ?
VAR7 + VAR167 :
VAR99 == 2 ?
VAR112 - 2 + VAR167 :
VAR112 + 2 + VAR167;
assign VAR147 = ~VAR135 ?
6'b0 :
VAR45 ?
VAR57 + VAR167 :
VAR99 == 2 ?
VAR112 - 2 + VAR167 :
VAR112 + 2 + VAR167;
assign VAR111 = ~VAR135 ?
6'b0 :
VAR45 ?
VAR101 + VAR167 :
VAR99 == 2 ?
VAR112 - 2 + VAR167 :
VAR112 + 2 + VAR167;
end
else begin : VAR105
assign VAR144 = ~VAR135 ?
6'b0 :
VAR110 ?
VAR7 + VAR167 :
VAR99 == 2 ?
VAR112 - 2 + VAR167 :
VAR112 + 2 + VAR167;
assign VAR147 = ~VAR135 ?
6'b0 :
VAR110 ?
VAR57 + VAR167 :
VAR99 == 2 ?
VAR112 - 2 + VAR167 :
VAR112 + 2 + VAR167;
assign VAR111 = ~VAR135 ?
6'b0 :
VAR110 ?
VAR101 + VAR167 :
VAR99 == 2 ?
VAR112 - 2 + VAR167 :
VAR112 + 2 + VAR167;
end
endgenerate
assign VAR64 = VAR167[1:0];
integer VAR13;
reg [VAR124-1:0] VAR49;
generate
begin : VAR65
wire [VAR124-1:0] VAR100 =
{VAR130, VAR51[15+:(VAR8+VAR156-11)],
1'b0, VAR51[3+:10], (VAR159 ? 3'b110 : VAR41 ? 3'b111 : 3'b001)
};
always @(VAR146 or VAR141 or VAR100
or VAR157 or VAR153 or VAR53 or VAR150
or VAR61 or VAR51 or VAR134 or rst)
begin
VAR49 = rst
? {VAR17{1'b0}}
: VAR141
? VAR100
: VAR51;
for (VAR13=0; VAR13<VAR19; VAR13=VAR13+1)
if (VAR146[VAR13])
VAR49 = {VAR53[(VAR17*VAR13)+:VAR17],
VAR157[(VAR8*VAR13)+:VAR8],
VAR61[(VAR156*VAR13)+:VAR156],
VAR150[VAR13],
VAR153[VAR13],
VAR134[VAR13]};
end
if (VAR117 == "2T" && VAR99 == 2)
end endgenerate
reg [VAR124-1:0] VAR43;
generate
if((VAR99 == 4) && (VAR117 != "2T")) begin : VAR121
reg [VAR124-1:0] VAR127 = {VAR124 {1'b0}};
always @(VAR16 or VAR157 or VAR153 or VAR53 or VAR150
or VAR61 or VAR127 or VAR134 or rst)
begin
VAR43 = rst
? {VAR17{1'b0}}
: VAR127;
for (VAR13=0; VAR13<VAR19; VAR13=VAR13+1)
if (VAR16[VAR13])
VAR43 = {VAR53[(VAR17*VAR13)+:VAR17],
VAR157[(VAR8*VAR13)+:VAR8],
VAR61[(VAR156*VAR13)+:VAR156],
VAR150[VAR13],
VAR153[VAR13],
VAR134[VAR13]};
end
end endgenerate
reg [VAR124-1:0] VAR94;
generate
begin : VAR149
reg VAR106;
reg VAR20;
reg VAR132;
reg VAR68;
reg VAR22;
reg VAR69;
reg [VAR156-1:0] VAR163;
reg [VAR156-1:0] VAR87;
reg [VAR78-1:0] VAR136;
reg [VAR78-1:0] VAR145;
always @(VAR120 or VAR123 or VAR145
or VAR20 or VAR68 or VAR87
or VAR69 or VAR151 or VAR71 or VAR157
or VAR42 or VAR73
or VAR53 or VAR93 or VAR48 or VAR25
or rst or VAR45)
begin
VAR106 = ~rst && VAR20;
VAR94 = {(rst ? {VAR17{1'b0}}
: VAR123[(VAR124-1)-:VAR17]),
((rst && VAR91 != "VAR142")
? {VAR124-3-VAR17{1'b0}}
: VAR123[3+:(VAR124-3-VAR17)]),
(rst ? 3'b0 : VAR123[2:0])};
VAR132 = VAR68;
VAR22 = rst ? 1'b0 : VAR69;
VAR163 = VAR87;
VAR110 = VAR45;
VAR136 = VAR145;
for (VAR13=0; VAR13<VAR19; VAR13=VAR13+1)
if (VAR151[VAR13]) begin
VAR106 = VAR73[VAR13];
VAR94 = {VAR53[(VAR17*VAR13)+:VAR17],
VAR157[(VAR8*VAR13)+:VAR8],
VAR120[(VAR156*VAR13)+:VAR156],
1'b1,
1'b0,
VAR71[VAR13]};
VAR132 = VAR25[VAR13] && VAR71[VAR13];
VAR22 = VAR48[VAR13];
VAR163 = VAR93[(VAR156*VAR13)+:VAR156];
VAR110 = VAR71[VAR13];
VAR136 =
VAR42[(VAR78*VAR13)+:VAR78];
end
end
if (VAR164 == "VAR142") begin : VAR76
assign VAR46 = VAR136;
end
else begin : VAR84
reg [VAR78-1:0] VAR70;
reg [VAR78-1:0] VAR80;
always @(VAR80 or VAR108
or VAR42) begin
VAR70 = VAR80;
for (VAR13=0; VAR13<VAR19; VAR13=VAR13+1)
if (VAR108[VAR13])
VAR70 =
VAR42[(VAR78*VAR13)+:VAR78];
end
always @(posedge clk) VAR80 <=
assign VAR46 = VAR70;
end
always @(posedge clk) VAR145 <=
if (VAR91 != "VAR142" || VAR116 == "VAR12") begin
end
if(VAR116 == "VAR12") begin
assign VAR155 = VAR20;
assign VAR6 = VAR123[3+VAR156+VAR8+:VAR17];
assign VAR98 = VAR123[3+VAR156+:VAR8];
assign VAR154 = VAR123[3+:VAR156];
assign VAR85 = VAR68;
assign VAR30 = VAR45;
assign VAR75 = VAR69;
assign VAR58 = VAR87;
assign VAR138 = VAR145;
end
else begin
assign VAR155 = VAR106;
assign VAR6 = VAR94[3+VAR156+VAR8+:VAR17];
assign VAR98 = VAR94[3+VAR156+:VAR8];
assign VAR154 = VAR94[3+:VAR156];
assign VAR85 = VAR132;
assign VAR30 = VAR110;
assign VAR75 = VAR22;
assign VAR58 = VAR163;
assign VAR138 = VAR136;
end
end endgenerate
reg [VAR124-1:0] VAR109 = {VAR124{1'b1}};
reg VAR107;
always @(VAR27 or VAR77 or VAR49 or VAR51 or VAR94 or VAR123 or VAR92 or VAR40 ) begin
VAR109 = {VAR124{1'b1}};
if (VAR27) VAR109 = VAR49;
if (VAR27 && VAR116 == "VAR12" && VAR99 == 2) VAR109 = VAR51;
if (VAR77) VAR109 = VAR94;
if (VAR77 && VAR116 == "VAR12") VAR109 = VAR123;
if (VAR27) VAR107 = VAR92;
end
else VAR107 = VAR40 ;
end
reg [VAR124-1:0] VAR33 = {VAR124{1'b1}};
generate
if ((VAR99 == 2) || (VAR99 == 4))
always @(VAR10 or VAR38 or VAR49 or VAR94 or VAR43) begin
VAR33 = {VAR124{1'b1}};
if (VAR10) VAR33 = VAR49;
if (VAR38) VAR33 = VAR94;
end
endgenerate
reg [VAR124-1:0] VAR15 = {VAR124{1'b1}};
reg [VAR124-1:0] VAR97 = {VAR124{1'b1}};
generate
if (VAR99 == 4)
always @(VAR125 or VAR50 or VAR32 or VAR36 or VAR49 or VAR94 or VAR43) begin
VAR15 = {VAR124{1'b1}};
VAR97 = {VAR124{1'b1}};
if (VAR125) VAR15 = VAR49;
if (VAR50) VAR15 = VAR94;
if (VAR32) VAR15 = VAR43;
if (VAR36) VAR97 = VAR94;
end
endgenerate
wire [VAR17-1:0] VAR47;
assign {VAR47, VAR56[VAR8-1:0], VAR79[VAR156-1:0], VAR55[0], VAR5[0], VAR44[0]} = VAR109;
wire [VAR17-1:0] VAR86;
assign {VAR86, VAR56[2*VAR8-1:VAR8], VAR79[2*VAR156-1:VAR156], VAR55[1], VAR5[1], VAR44[1]} = VAR33;
wire [VAR17-1:0] VAR160;
wire [VAR17-1:0] VAR18;
generate
if(VAR99 == 4) begin
assign {VAR160, VAR56[3*VAR8-1:2*VAR8], VAR79[3*VAR156-1:2*VAR156], VAR55[2], VAR5[2], VAR44[2]} = VAR15;
assign {VAR18, VAR56[4*VAR8-1:3*VAR8], VAR79[4*VAR156-1:3*VAR156], VAR55[3], VAR5[3], VAR44[3]} =
VAR97;
end
endgenerate
generate
if(VAR52 == "VAR113")begin
assign VAR168[0] = VAR107;
assign VAR168[1] = VAR92;
if(VAR99 == 4) begin
assign VAR168[2] = VAR92;
assign VAR168[3] = VAR92;
end
end
endgenerate
localparam VAR28 = {VAR81{1'b1}};
wire [(VAR122*VAR81)-1:0] VAR37 =
{{VAR122{1'b0}},VAR28};
assign VAR89[VAR122*VAR81 -1 :0 ] =
{(~(VAR37 << (VAR81*VAR47)) | {VAR122*VAR81{~VAR63}})};
assign VAR89[2*VAR122*VAR81 -1 : VAR122*VAR81 ] =
{(~(VAR37 << (VAR81*VAR86)) | {VAR122*VAR81{~VAR26}})};
generate
if(VAR99 == 4) begin
assign VAR89[3*VAR122*VAR81 -1 :2*VAR122*VAR81 ] =
{(~(VAR37 << (VAR81*VAR160)) | {VAR122*VAR81{~VAR96}})};
assign VAR89[4*VAR122*VAR81 -1 :3*VAR122*VAR81 ] =
{(~(VAR37 << (VAR81*VAR18)) | {VAR122*VAR81{~VAR62}})};
end
endgenerate
reg [VAR17-1:0] VAR139;
reg [VAR17-1:0] VAR29;
always @(VAR165
or VAR29 or VAR24 or VAR53 or rst) begin
if (rst) VAR139 = {VAR17{1'b0}};
end
else begin
VAR139 = VAR29;
if (VAR24)
for (VAR13=0; VAR13<VAR19; VAR13=VAR13+1)
if (VAR165[VAR13]) VAR139 = VAR53[(VAR17*VAR13)+:VAR17];
end
end
assign VAR143 = VAR139;
wire [VAR122-1:0] VAR162 = VAR37 << VAR6;
wire VAR126 = (VAR60 == 1) ? |(VAR162 & VAR67)
: (VAR67[2] & VAR67[0]) ?
|(VAR162[VAR122-1:0] & {VAR67[2],
VAR67[0]}) : (VAR67[0])?
VAR162[0] : 1'b0;
wire VAR131 = VAR116 == "VAR12" ?
VAR126 && VAR45 :
VAR126 && VAR110;
wire VAR140 = VAR116 == "VAR12" ?
VAR126 && ~VAR45 :
VAR126 && ~VAR110;
reg [1:0] VAR102 = 2'b0;
reg[1:0] VAR11;
always @(VAR67) begin
VAR11 = 2'b0;
for (VAR13=0; VAR13<8; VAR13=VAR13+1)
if (~VAR11[1])
if (VAR67[VAR13] == 1'b1) VAR11 =
VAR11 + 2'b1;
end
wire VAR90 = (VAR4 == "VAR95") ? ~VAR131 : VAR140;
assign VAR31[1] = VAR90 & VAR135;
generate
if (VAR60 > 1) begin : VAR133
wire VAR158 = (VAR115[3] & VAR115[1])?
|({VAR162[VAR11+1],
VAR162[VAR11]}) :
(VAR115[1]) ? VAR162[VAR11] :1'b0;
wire VAR128 = VAR116 == "VAR12" ?
VAR158 && VAR45 :
VAR158 && VAR110;
wire VAR137 = VAR116 == "VAR12" ?
VAR158 && ~VAR45 :
VAR158 && ~VAR110;
wire VAR9 = (VAR4 == "VAR95") ? ~VAR128 : VAR137;
assign VAR31[3] = VAR9 & VAR135;
end else begin
assign VAR31[3] = 1'b0;
end endgenerate
generate
if(VAR52 == "VAR113")begin
reg[1:0] VAR23 ;
reg[1:0] VAR72 ;
reg[1:0] VAR54 ;
always@(posedge clk) begin
end
if((VAR99 == 4) && (VAR60 > 1 )) begin:VAR1
assign VAR118[0] = VAR31[1] | VAR23[0] | VAR72[0];
assign VAR118[1] = VAR31[3] | VAR23[1] | VAR72[1];
end else if(VAR99 == 4) begin:VAR35
assign VAR118[0] = VAR31[1] | VAR23[0] ;
assign VAR118[1] = VAR31[3] | VAR23[1] ;
end else if(VAR99 == 2) begin:VAR114
assign VAR118[0] = VAR31[1] | VAR23[0] | VAR72[0] | VAR54[0] ;
assign VAR118[1] = VAR31[3] | VAR23[1] | VAR72[1] | VAR54[1] ;
end
end
endgenerate
endmodule | mit |
mcgodfrey/i2c-eeprom | i2c_master.v | 5,191 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR7,
input wire [7:0] VAR16,
input wire [6:0] VAR17,
input wire VAR12,
input wire [7:0] VAR11,
output reg [7:0] VAR3,
output reg VAR26,
output reg VAR4,
inout wire VAR9,
output wire VAR25
);
localparam VAR22 = 0;
localparam VAR28 = 1;
localparam VAR20 = 2;
localparam VAR8 = 3;
localparam VAR14 = 4;
localparam VAR29 = 5;
localparam VAR5 = 6;
localparam VAR15 = 7;
localparam VAR27 = 8;
localparam VAR13 = 1;
localparam VAR1 = 0;
localparam VAR6 = 0;
reg [5:0] state;
reg [7:0] VAR19; reg [6:0] addr;
reg [7:0] VAR2;
reg [7:0] VAR24;
reg VAR21;
reg VAR23 = 0;
reg VAR18;
assign VAR9 = ((VAR18)==0) ? 1'b0 : 1'VAR10;
assign VAR25 = (VAR23 == 0) ? 1'b1 : ~clk;
always @(negedge clk) begin
if (reset == 1) begin
VAR23 <= 0;
end else begin
if ((state == VAR22) || (state == VAR28) || (state == VAR27)) begin
VAR23 <= 0;
end
else begin
VAR23 <= 1;
end
if (state == VAR14) begin
if (0) begin
state <= VAR22;
end
end
end
end
always @(posedge clk) begin
if (reset == 1) begin
state <= VAR22;
VAR18 <= 1;
VAR19 <= 8'd0;
addr <= 0;
VAR2 <= 0;
VAR24 <= 0;
VAR21 <= 0;
VAR26 <= 0;
VAR4 <= 0;
end
else begin
case(state)
VAR22: begin VAR18 <= 1;
if (VAR7) begin
state <= VAR28;
end end
VAR28: begin state <= VAR20;
VAR18 <= 0; addr <= VAR17;
VAR24 <= VAR16;
VAR21 <= VAR12;
if (VAR12 == VAR1) begin
VAR26 <= 1; end
VAR19 <= 6; end
VAR20: begin VAR18 <= addr[VAR19];
if (VAR19 == 0) begin
state <= VAR8;
end
else begin
VAR19 <= VAR19 - 1'b1;
end
end
VAR8: begin VAR18 <= VAR21;
state <= VAR14;
end
VAR14: begin
VAR18 <= 1;
VAR26 <= 0;
if (VAR24 == 0) begin
if (VAR7 == 1) begin
VAR18 <= 1;
state <= VAR28;
end else begin
VAR18 <= 1; state <= VAR27;
end
end else begin
if (VAR21 == VAR1) begin
VAR2 <= VAR11; VAR19 <= 7; state <= VAR5;
end else begin
VAR19 <= 7; state <= VAR15;
end end
end
VAR5: begin
VAR18 <= VAR2[VAR19];
if (VAR24 > 0) begin
VAR26 <= 1; end
if (VAR19 == 0) begin
state <= VAR14;
VAR24 <= VAR24 - 1'b1;
end
else begin
VAR19 <= VAR19 - 1'b1;
end
end
VAR15: begin
VAR2[VAR19] <= VAR9;
if (VAR19 == 0) begin
state <= VAR14;
VAR3[7:1] <= VAR2[7:1];
VAR3[0] <= VAR9;
VAR4 <= 1;
VAR24 <= VAR24 - 1'b1;
end
else begin
VAR19 <= VAR19 - 1'b1;
VAR4 <= 0;
end
end
VAR27: begin
VAR18 <= 1;
state <= VAR22;
end
endcase
end end
endmodule | mit |
efabless/openlane | designs/BM64/src/BM64.v | 27,558 | module MODULE1 #(
parameter VAR30 = 256 )(
input VAR21, input VAR22,
input VAR10, input [(VAR30 - 1):0] VAR20, input [(VAR30 - 1):0] VAR7, output reg VAR3, output reg [((2*VAR30) - 1):0] VAR28 );
localparam VAR8 = ((VAR30 + 1)/4);
reg [4:0] VAR4; reg [4:0] VAR25; reg VAR12; reg [(VAR30 + 3):0] VAR1; wire [(VAR30 + 3):0] VAR9, VAR15, VAR18, VAR11; reg VAR14, VAR5, VAR23; reg VAR19, VAR26, VAR13; wire [(VAR30 + 3):0] VAR6; reg [(VAR30 + 3):0] VAR27, VAR2; reg VAR29, VAR24; wire [(VAR30 + 3):0] VAR16, VAR31; reg [((2*VAR30) + 3):0] VAR17;
always @(posedge VAR22)
begin
if(VAR21)
VAR4 <= 0;
end
else if(VAR10)
VAR4 <= VAR8;
else if(|VAR4)
VAR4 <= (VAR4 - 1);
end
always @(posedge VAR22)
begin
if(VAR21)
VAR1 <= 0;
end
else if(VAR10)
VAR1 <= {{4{VAR20[(VAR30 - 1)]}}, VAR20};
end
assign VAR9 = {VAR1, 3'b0};
assign VAR15 = {VAR1, 2'b0};
assign VAR18 = {VAR1, 1'b0};
assign VAR11 = VAR1;
always @
begin
case(VAR25)
5'b00000 : {VAR14, VAR5, VAR23} <= 3'b000; 5'b00001 : {VAR14, VAR5, VAR23} <= 3'b000; 5'b00010 : {VAR14, VAR5, VAR23} <= 3'b000; 5'b00011 : {VAR14, VAR5, VAR23} <= 3'b000; 5'b00100 : {VAR14, VAR5, VAR23} <= 3'b000; 5'b00101 : {VAR14, VAR5, VAR23} <= 3'b001; 5'b00110 : {VAR14, VAR5, VAR23} <= 3'b001; 5'b00111 : {VAR14, VAR5, VAR23} <= 3'b001; 5'b01000 : {VAR14, VAR5, VAR23} <= 3'b001; 5'b01001 : {VAR14, VAR5, VAR23} <= 3'b001; 5'b01010 : {VAR14, VAR5, VAR23} <= 3'b001; 5'b01011 : {VAR14, VAR5, VAR23} <= 3'b001; 5'b01100 : {VAR14, VAR5, VAR23} <= 3'b001; 5'b01101 : {VAR14, VAR5, VAR23} <= 3'b011; 5'b01110 : {VAR14, VAR5, VAR23} <= 3'b011; 5'b01111 : {VAR14, VAR5, VAR23} <= 3'b011; 5'b10000 : {VAR14, VAR5, VAR23} <= 3'b111; 5'b10001 : {VAR14, VAR5, VAR23} <= 3'b111; 5'b10010 : {VAR14, VAR5, VAR23} <= 3'b111; 5'b10011 : {VAR14, VAR5, VAR23} <= 3'b101; 5'b10100 : {VAR14, VAR5, VAR23} <= 3'b101; 5'b10101 : {VAR14, VAR5, VAR23} <= 3'b101; 5'b10110 : {VAR14, VAR5, VAR23} <= 3'b101; 5'b10111 : {VAR14, VAR5, VAR23} <= 3'b101; 5'b11000 : {VAR14, VAR5, VAR23} <= 3'b101; 5'b11001 : {VAR14, VAR5, VAR23} <= 3'b101; 5'b11010 : {VAR14, VAR5, VAR23} <= 3'b101; 5'b11011 : {VAR14, VAR5, VAR23} <= 3'b000; 5'b11100 : {VAR14, VAR5, VAR23} <= 3'b000; 5'b11101 : {VAR14, VAR5, VAR23} <= 3'b000; 5'b11110 : {VAR14, VAR5, VAR23} <= 3'b000; 5'b11111 : {VAR14, VAR5, VAR23} <= 3'b000; default : {VAR14, VAR5, VAR23} <= 3'b000; endcase
end
always @
begin
case({VAR14, VAR5, VAR23})
3'b001 : {VAR29, VAR27} <= {1'b0, VAR15};
3'b011 : {VAR29, VAR27} <= {1'b0, VAR9};
3'b101 : {VAR29, VAR27} <= {1'b1, ~VAR15};
3'b111 : {VAR29, VAR27} <= {1'b1, ~VAR9};
default : {VAR29, VAR27} <= 0;
endcase
end
always @(*)
begin
case({VAR19, VAR26, VAR13})
3'b001 : {VAR24, VAR2} <= {1'b0, VAR11};
3'b011 : {VAR24, VAR2} <= {1'b0, VAR18};
3'b101 : {VAR24, VAR2} <= {1'b1, ~VAR11};
3'b111 : {VAR24, VAR2} <= {1'b1, ~VAR18};
default : {VAR24, VAR2} <= 0;
endcase
end
assign VAR16 = VAR6 + VAR27 + VAR29;
assign VAR31 = VAR16 + VAR2 + VAR24;
always @(posedge VAR22)
begin
if(VAR21)
VAR17 <= 0;
end
else if(VAR10)
VAR17 <= VAR7;
else if(|VAR4) VAR17 <= {{4{VAR31[(VAR30 + 3)]}}, VAR31, VAR17[(VAR30 - 1):4]};
end
always @(posedge VAR22)
begin
if(VAR21)
VAR12 <= 0;
end
else if(VAR10)
VAR12 <= 0;
else if(|VAR4)
VAR12 <= VAR17[3];
end
always @(posedge VAR22)
begin
if(VAR21)
VAR28 <= 0;
end
else if(VAR4 == 1)
VAR28 <= {VAR31, VAR17[(VAR30 - 1):4]};
end
always @(posedge VAR22)
begin
if(VAR21)
VAR3 <= 0;
end
else
VAR3 <= (VAR4 == 1);
end
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo_pacer.v | 1,279 | module MODULE1
(input clk,
input reset,
input [7:0] VAR6,
input enable,
input VAR13, output VAR11,
output VAR9, input VAR5,
output VAR2, VAR3);
wire VAR4;
VAR8 VAR7 (.VAR12(clk), .reset(reset), .enable(enable),
.VAR6(VAR6), .VAR14(1), .VAR10(VAR4));
wire VAR1 = VAR13 & VAR5;
assign VAR11 = VAR1 & VAR4;
assign VAR9 = VAR11;
assign VAR2 = VAR4 & ~VAR13;
assign VAR3 = VAR4 & ~VAR5;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1.blackbox.v | 1,323 | module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/cabac_mn_1p_16x64.v | 2,971 | module MODULE1(
clk ,
VAR5 ,
VAR8 ,
VAR16
);
parameter VAR24 = 'd0;
input clk ; input VAR5 ; input [5:0] VAR8 ;
output [15:0] VAR16 ;
VAR32 #(.VAR18(6), .VAR6(16))
VAR25(
.clk (clk ),
.VAR3 (~VAR5 ),
.VAR20 (~VAR5 ),
.VAR23 (VAR8 ),
.VAR29 (VAR16 )
);
generate
if(VAR24 == 'd0) begin: VAR4
VAR12 #(
.VAR22 ("VAR2.VAR17" )
)VAR21(
.address (VAR8 ),
.VAR9 (clk ),
.VAR28 (VAR16 )
);
end
else if(VAR24 == 'd1) begin: VAR31
VAR12 #(
.VAR22 ("VAR1.VAR17" )
)VAR13(
.address (VAR8 ),
.VAR9 (clk ),
.VAR28 (VAR16 )
);
end
else if(VAR24 == 'd2) begin: VAR26
VAR12 #(
.VAR22 ("VAR10.VAR17" )
)VAR14(
.address (VAR8 ),
.VAR9 (clk ),
.VAR28 (VAR16 )
);
end
else if(VAR24 == 'd3) begin: VAR27
VAR12 #(
.VAR22 ("VAR15.VAR17" )
)VAR30(
.address (VAR8 ),
.VAR9 (clk ),
.VAR28 (VAR16 )
);
end
else if(VAR24 == 'd4) begin: VAR11
VAR12 #(
.VAR22 ("VAR7.VAR17" )
)VAR19(
.address (VAR8 ),
.VAR9 (clk ),
.VAR28 (VAR16 )
);
end
endgenerate
endmodule | gpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/crc_ccitt.v | 1,212 | module MODULE1
(input clk, input rst, input [7:0] VAR8, input VAR6, output [15:0] VAR7);
wire [15:0] VAR10;
wire [15:0] VAR9 = (rst ? VAR1 : VAR10);
VAR4 #(16) VAR5(.VAR2(clk), .rst(1'b0), .en(VAR6 | rst), .VAR8(VAR9), .VAR3(VAR7));
assign VAR10[0] = VAR7[8] ^ VAR7[12] ^ VAR8[0] ^ VAR8[4];
assign VAR10[1] = VAR7[9] ^ VAR7[13] ^ VAR8[1] ^ VAR8[5];
assign VAR10[2] = VAR7[10] ^ VAR7[14] ^ VAR8[2] ^ VAR8[6];
assign VAR10[3] = VAR7[11] ^ VAR7[15] ^ VAR8[3] ^ VAR8[7];
assign VAR10[4] = VAR7[12] ^ VAR8[4];
assign VAR10[5] = VAR7[8] ^ VAR7[12] ^ VAR7[13] ^ VAR8[0] ^ VAR8[4] ^ VAR8[5];
assign VAR10[6] = VAR7[9] ^ VAR7[13] ^ VAR7[14] ^ VAR8[1] ^ VAR8[5] ^ VAR8[6];
assign VAR10[7] = VAR7[10] ^ VAR7[14] ^ VAR7[15] ^ VAR8[2] ^ VAR8[6] ^ VAR8[7];
assign VAR10[8] = VAR7[0] ^ VAR7[11] ^ VAR7[15] ^ VAR8[3] ^ VAR8[7];
assign VAR10[9] = VAR7[1] ^ VAR7[12] ^ VAR8[4];
assign VAR10[10] = VAR7[2] ^ VAR7[13] ^ VAR8[5];
assign VAR10[11] = VAR7[3] ^ VAR7[14] ^ VAR8[6];
assign VAR10[12] = VAR7[4] ^ VAR7[8] ^ VAR7[12] ^ VAR7[15] ^ VAR8[0] ^ VAR8[4] ^ VAR8[7];
assign VAR10[13] = VAR7[5] ^ VAR7[9] ^ VAR7[13] ^ VAR8[1] ^ VAR8[5];
assign VAR10[14] = VAR7[6] ^ VAR7[10] ^ VAR7[14] ^ VAR8[2] ^ VAR8[6];
assign VAR10[15] = VAR7[7] ^ VAR7[11] ^ VAR7[15] ^ VAR8[3] ^ VAR8[7];
endmodule | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,761 | module MODULE1
parameter VAR14 = 8,
VAR28 = 8,
VAR5 = 0,
VAR1 = 0,
VAR45 = 1,
VAR18 = 0,
VAR11 = 1,
VAR12 = 2,
VAR38 = 2,
VAR10 = 1,
VAR6 = VAR14 / VAR28,
VAR31 = VAR40(VAR6)
)
(
input VAR33,
input VAR42,
input VAR43,
input VAR15,
output VAR25,
input VAR22,
input [VAR14 - 1 : 0] VAR17,
input [VAR45 - 1 : 0] VAR2,
input [VAR11 - 1 : 0] VAR4,
input VAR44,
input VAR21,
input [(VAR31 ? (VAR31 - 1) : 0) : 0] VAR35,
input VAR30,
output VAR39,
output [VAR14 - 1 : 0] VAR20,
output [VAR45 - 1 : 0] VAR36,
output [VAR11 - 1 : 0] VAR16,
output VAR8,
output VAR32,
output [(VAR31 ? (VAR31 - 1) : 0) : 0] VAR3
);
localparam VAR9 = (VAR5) ? 2 + VAR31 : 0;
localparam VAR23 = (VAR1) ? VAR45 : 0;
localparam VAR26 = (VAR18) ? VAR11 : 0;
localparam VAR7 = VAR14 +
VAR9 +
VAR23 +
VAR31 +
VAR26;
wire [VAR7 - 1: 0] VAR37;
wire [VAR7 - 1: 0] VAR13;
assign VAR37[VAR14 - 1 : 0] = VAR17;
generate
if (VAR9) begin
assign VAR37[
VAR14 + VAR9 - 1 :
VAR14
] = {VAR44, VAR21};
end
if (VAR1) begin
assign VAR37[
VAR14 + VAR9 + VAR23 - 1 :
VAR14 + VAR9
] = VAR2;
end
if (VAR31) begin
assign VAR37[
VAR14 + VAR9 + VAR23 + VAR31 - 1 :
VAR14 + VAR9 + VAR23
] = VAR35;
end
if (VAR18) begin
assign VAR37[
VAR14 + VAR9 + VAR23 + VAR31 + VAR26 - 1 :
VAR14 + VAR9 + VAR23 + VAR31
] = VAR4;
end
endgenerate
VAR19
.VAR6 (1),
.VAR28 (VAR7),
.VAR24 (VAR12),
.VAR34 (VAR38),
.VAR10 (VAR10)
) VAR27 (
.VAR33 (VAR33 ),
.VAR42 (VAR42 ),
.VAR25 (VAR25 ),
.VAR22 (VAR22 ),
.VAR17 (VAR37 ),
.VAR43 (VAR43 ),
.VAR15 (VAR15 ),
.VAR30 (VAR30 ),
.VAR39 (VAR39 ),
.VAR20 (VAR13 )
);
assign VAR20 = VAR13[VAR14 - 1 : 0];
generate
if (VAR5) begin
assign {VAR8, VAR32} =
VAR13[VAR14 + VAR9 - 1 : VAR14];
end else begin
assign {VAR8, VAR32} = 2'b0;
end
if (VAR1) begin
assign VAR36 = VAR13[
VAR14 + VAR9 + VAR23 - 1 :
VAR14 + VAR9
];
end else begin
assign VAR36 = 1'b0;
end
if (VAR31) begin
assign VAR3 = VAR13[
VAR14 + VAR9 + VAR23 + VAR31 - 1 :
VAR14 + VAR9 + VAR23
];
end else begin
assign VAR3 = 1'b0;
end
if (VAR18) begin
assign VAR16 = VAR13[
VAR14 + VAR9 + VAR23 + VAR31 + VAR26 - 1 :
VAR14 + VAR9 + VAR23 + VAR31
];
end else begin
assign VAR16 = 1'b0;
end
endgenerate
function integer VAR40;
input integer VAR29;
integer VAR41;
begin
VAR41 = 1;
VAR40 = 0;
while (VAR41 < VAR29) begin
VAR40 = VAR40 + 1;
VAR41 = VAR41 << 1;
end
end
endfunction
endmodule | gpl-2.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/lab3_hps_0_hps_io.v | 10,876 | module MODULE1 (
output wire [14:0] VAR2, output wire [2:0] VAR23, output wire VAR44, output wire VAR51, output wire VAR46, output wire VAR26, output wire VAR67, output wire VAR60, output wire VAR38, output wire VAR32, inout wire [31:0] VAR64, inout wire [3:0] VAR47, inout wire [3:0] VAR34, output wire VAR48, output wire [3:0] VAR15, input wire VAR22, output wire VAR65, output wire VAR29, output wire VAR31, output wire VAR25, output wire VAR37, input wire VAR24, inout wire VAR55, output wire VAR59, input wire VAR68, output wire VAR21, input wire VAR35, input wire VAR30, input wire VAR62, input wire VAR6, inout wire VAR18, inout wire VAR8, inout wire VAR36, inout wire VAR49, output wire VAR4, output wire VAR19, inout wire VAR7, inout wire VAR33, inout wire VAR61, output wire VAR17, inout wire VAR5, inout wire VAR45, inout wire VAR12, inout wire VAR43, inout wire VAR10, inout wire VAR50, inout wire VAR66, inout wire VAR63, inout wire VAR42, inout wire VAR28, input wire VAR9, output wire VAR58, input wire VAR20, input wire VAR3, output wire VAR39, output wire VAR57, input wire VAR13, output wire VAR14, output wire VAR52, output wire VAR11, input wire VAR1, output wire VAR41, input wire VAR27, output wire VAR54, inout wire VAR16, inout wire VAR56 );
VAR40 VAR53 (
.VAR2 (VAR2), .VAR23 (VAR23), .VAR44 (VAR44), .VAR51 (VAR51), .VAR46 (VAR46), .VAR26 (VAR26), .VAR67 (VAR67), .VAR60 (VAR60), .VAR38 (VAR38), .VAR32 (VAR32), .VAR64 (VAR64), .VAR47 (VAR47), .VAR34 (VAR34), .VAR48 (VAR48), .VAR15 (VAR15), .VAR22 (VAR22), .VAR65 (VAR65), .VAR29 (VAR29), .VAR31 (VAR31), .VAR25 (VAR25), .VAR37 (VAR37), .VAR24 (VAR24), .VAR55 (VAR55), .VAR59 (VAR59), .VAR68 (VAR68), .VAR21 (VAR21), .VAR35 (VAR35), .VAR30 (VAR30), .VAR62 (VAR62), .VAR6 (VAR6), .VAR18 (VAR18), .VAR8 (VAR8), .VAR36 (VAR36), .VAR49 (VAR49), .VAR4 (VAR4), .VAR19 (VAR19), .VAR7 (VAR7), .VAR33 (VAR33), .VAR61 (VAR61), .VAR17 (VAR17), .VAR5 (VAR5), .VAR45 (VAR45), .VAR12 (VAR12), .VAR43 (VAR43), .VAR10 (VAR10), .VAR50 (VAR50), .VAR66 (VAR66), .VAR63 (VAR63), .VAR42 (VAR42), .VAR28 (VAR28), .VAR9 (VAR9), .VAR58 (VAR58), .VAR20 (VAR20), .VAR3 (VAR3), .VAR39 (VAR39), .VAR57 (VAR57), .VAR13 (VAR13), .VAR14 (VAR14), .VAR52 (VAR52), .VAR11 (VAR11), .VAR1 (VAR1), .VAR41 (VAR41), .VAR27 (VAR27), .VAR54 (VAR54), .VAR16 (VAR16), .VAR56 (VAR56) );
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211o/sky130_fd_sc_ls__a211o.functional.v | 1,443 | module MODULE1 (
VAR6 ,
VAR10,
VAR3,
VAR9,
VAR5
);
output VAR6 ;
input VAR10;
input VAR3;
input VAR9;
input VAR5;
wire VAR8 ;
wire VAR2;
and VAR1 (VAR8 , VAR10, VAR3 );
or VAR7 (VAR2, VAR8, VAR5, VAR9);
buf VAR4 (VAR6 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai.functional.v | 1,475 | module MODULE1 (
VAR5 ,
VAR9,
VAR1,
VAR10,
VAR8,
VAR2
);
output VAR5 ;
input VAR9;
input VAR1;
input VAR10;
input VAR8;
input VAR2;
wire VAR7 ;
wire VAR4;
or VAR11 (VAR7 , VAR8, VAR10, VAR1, VAR9 );
nand VAR3 (VAR4, VAR2, VAR7 );
buf VAR6 (VAR5 , VAR4 );
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/MySource/adaloop.v | 3,145 | module MODULE1(
input VAR11,
input rst,
output VAR48,
output VAR36,
output reg [15:0] VAR38,
output reg [15:0] VAR57,
input [13:0] VAR60,
input [13:0] VAR50,
input VAR40,
output VAR21,
output VAR66,
output VAR56,
output VAR2,
output [3:0] VAR13,
output VAR4
);
VAR52 VAR22(
.VAR26(VAR11),
.VAR53(~rst),
.VAR55(VAR37),
.VAR67(VAR54),
.VAR58(VAR48),
.VAR27(VAR4),
.VAR20(VAR61)
);
assign VAR36=1'b0;
reg VAR29=1'b0;
always @ (posedge VAR4)begin
VAR29<=rst;
end
reg [24:0] VAR34;
always @ (posedge VAR4 or negedge VAR29)begin
if(!VAR29)
VAR34<=25'd0;
end
else
VAR34<=VAR34+1'b1;
end
wire VAR42=VAR34[9];
wire VAR1=VAR34[24];
VAR6 VAR6(
.VAR66 (VAR18 ),
.VAR56 (VAR45 ),
.rst (VAR29 ),
.clk (VAR42 ),
.VAR44 (VAR51 )
);
wire [2:0] VAR46; VAR59 VAR59(
.VAR66 (VAR14 ),
.VAR56 (VAR10 ),
.rst (VAR51 ),
.clk (VAR42 ),
.VAR44 (VAR30),
.VAR46 (VAR46 )
);
assign VAR2 = ~VAR51;
assign VAR21 = VAR42;
assign VAR66 = !VAR51 ? VAR18 : VAR14;
assign VAR56 = !VAR51 ? VAR45 : VAR10;
wire VAR8; reg [12:0] addr;
always @ (posedge VAR37 or negedge VAR29)begin
if(!VAR29)
addr<=13'd8191;
end
else if(!VAR8)
addr<=addr+1'b1;
else
addr<=addr+2'd2;
end
wire [31:0] VAR15;
VAR39 VAR39(
.VAR35 (VAR37 ),
.VAR5 (addr ),
.VAR43 (VAR15)
);
wire [31:0] VAR33;
wire [11:0] VAR32;
VAR31 VAR12(
.clk (VAR37 ),
.VAR25 (1'b1 ),
.VAR49 (VAR32 ),
.VAR24 (VAR33[31:16] ),
.VAR23 (VAR33[15:0] )
);
wire [3:0] sel;
reg [31:0] VAR49;
always @ (posedge VAR37 or negedge VAR29)begin
if(!VAR29)begin
VAR49<=32'd0;
end
else begin
case(sel)
4'b0000:VAR49<=32'd0;
4'b0001:VAR49<=VAR33;
4'b0010:VAR49<=VAR15;
endcase
end
end
always @ (posedge VAR37 or negedge VAR29)begin
if(!VAR29)begin
VAR38<=16'd0;
VAR57<=16'd0;
end
else begin
{VAR38,VAR57}<=VAR49;
end
end
assign VAR13[3]=VAR2 ; assign VAR13[2]=VAR51 ; assign VAR13[1]=VAR30 ; assign VAR13[0]=VAR61 ;
wire [35:0] VAR47,VAR65;
VAR64 VAR41(.VAR47(VAR47),.VAR65(VAR65));
VAR16 VAR17
(
.VAR63(VAR54),
.VAR3(VAR47),
.VAR19({
VAR60, 2'd0, VAR50, 2'd0, VAR38, VAR57 })
);
wire [31:0] VAR9;
VAR62 VAR7 (.VAR3(VAR65),.VAR9(VAR9));
assign sel =VAR9[3:0];
assign VAR32 =VAR9[15:4];
assign VAR46 =VAR9[18:16];
assign VAR8 =VAR9[19];
assign VAR28 =VAR9[31];
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_clock_io.v | 4,866 | module MODULE1 #
(
parameter VAR15 = 100, parameter VAR9 = 2, parameter VAR8 = "VAR2", parameter VAR1 = "VAR13", parameter VAR6 = 300.0, parameter VAR5 = "VAR16" )
(
input VAR10, input clk, input rst, output [VAR9-1:0] VAR12, output [VAR9-1:0] VAR4 );
generate
genvar VAR3;
for (VAR3 = 0; VAR3 < VAR9; VAR3 = VAR3 + 1) begin: VAR14
VAR11 #
(
.VAR15 (VAR15),
.VAR8 (VAR8),
.VAR1 (VAR1),
.VAR6 (VAR6),
.VAR5 (VAR5)
)
VAR7
(
.VAR10 (VAR10),
.clk (clk),
.rst (rst),
.VAR12 (VAR12[VAR3]),
.VAR4 (VAR4[VAR3])
);
end
endgenerate
endmodule | lgpl-3.0 |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/config_controller/I2C_Controller.v | 2,607 | module MODULE1 (
input VAR2,
input VAR10,
input [31:0] VAR3, input VAR4, output VAR7, inout VAR5, output reg VAR6, output VAR12 );
reg VAR9;
reg VAR14;
reg [31:0]VAR11;
reg [6:0]VAR13;
assign VAR7 = VAR14 | ( ((VAR13 >= 4) & (VAR13 <= 39))? ~VAR2 : 1'b0);
assign VAR5 = VAR9 ? 1'VAR15 : 1'b0;
reg VAR1,VAR8,VAR16,VAR17;
assign VAR12 = VAR1 | VAR8 |VAR16 |VAR17;
always @(negedge VAR10 or posedge VAR2 ) begin
if (!VAR10) VAR13=6'b111111;
end
else begin
if (VAR4==0)
VAR13=0;
end
else
if (VAR13 < 41) VAR13[6:0] = VAR13[6:0] + 7'd1;
end
end
always @(negedge VAR10 or posedge VAR2 ) begin
if (!VAR10) begin VAR14=1;VAR9=1; VAR1=0;VAR8=0;VAR16=0;VAR17=0; VAR6=1; end
else
case (VAR13)
6'd0 : begin VAR1=0 ;VAR8=0 ;VAR16=0 ;VAR17=0 ; VAR6=0; VAR9=1; VAR14=1;end
6'd1 : begin VAR11=VAR3;VAR9=0;end
6'd2 : VAR14=0;
6'd3 : VAR9=VAR11[31];
6'd4 : VAR9=VAR11[30];
6'd5 : VAR9=VAR11[29];
6'd6 : VAR9=VAR11[28];
6'd7 : VAR9=VAR11[27];
6'd8 : VAR9=VAR11[26];
6'd9 : VAR9=VAR11[25];
6'd10 : VAR9=VAR11[24];
6'd11 : VAR9=1'b1;
6'd12 : begin VAR9=VAR11[23]; VAR1=VAR5; end
6'd13 : VAR9=VAR11[22];
6'd14 : VAR9=VAR11[21];
6'd15 : VAR9=VAR11[20];
6'd16 : VAR9=VAR11[19];
6'd17 : VAR9=VAR11[18];
6'd18 : VAR9=VAR11[17];
6'd19 : VAR9=VAR11[16];
6'd20 : VAR9=1'b1;
6'd21 : begin VAR9=VAR11[15]; VAR8=VAR5; end
6'd22 : VAR9=VAR11[14];
6'd23 : VAR9=VAR11[13];
6'd24 : VAR9=VAR11[12];
6'd25 : VAR9=VAR11[11];
6'd26 : VAR9=VAR11[10];
6'd27 : VAR9=VAR11[9];
6'd28 : VAR9=VAR11[8];
6'd29 : VAR9=1'b1;
6'd30 : begin VAR9=VAR11[7]; VAR16=VAR5; end
6'd31 : VAR9=VAR11[6];
6'd32 : VAR9=VAR11[5];
6'd33 : VAR9=VAR11[4];
6'd34 : VAR9=VAR11[3];
6'd35 : VAR9=VAR11[2];
6'd36 : VAR9=VAR11[1];
6'd37 : VAR9=VAR11[0];
6'd38 : VAR9=1'b1;
6'd39 : begin VAR9=1'b0; VAR14=1'b0; VAR17=VAR5; end
6'd40 : VAR14=1'b1;
6'd41 : begin VAR9=1'b1; VAR6=1; end
endcase
end
endmodule | gpl-3.0 |
JakeMercer/mac | MAC/rtl/mac/rx/rx_sm.v | 6,638 | module MODULE1 #(
parameter VAR24 = 3'h0,
parameter VAR51 = 3'h1,
parameter VAR15 = 3'h2,
parameter VAR41 = 3'h3,
parameter VAR53 = 3'h4,
parameter VAR37 = 3'h5,
parameter VAR9 = 12
)(
input reset,
input VAR40,
input VAR48,
input [7:0] VAR26,
input VAR12,
output wire [7:0] VAR25,
input wire VAR7,
input wire VAR43,
output wire VAR36,
output wire VAR42,
output wire [VAR9-1:0] VAR10,
input wire VAR8,
input wire [VAR9-1:0] VAR13,
output reg VAR28,
output wire VAR18
);
localparam VAR1 = 32'hC704DD7B;
localparam VAR5 = 32'h04C11DB7;
localparam VAR47 = 32'hFFFFFFFF;
localparam VAR57 = 1518;
localparam VAR21 = 64;
wire [VAR9:0] VAR32;
wire [VAR9-1:0] VAR29;
reg [VAR9-1:0] VAR38;
reg VAR49;
reg VAR30;
reg VAR2;
reg [2:0] state;
reg [2:0] VAR33;
reg [15:0] VAR3;
reg [15:0] VAR22;
reg VAR44;
reg VAR54;
reg VAR14;
reg VAR20;
reg VAR35;
wire [31:0] VAR58;
reg [39:0] VAR16;
always @ (posedge reset or posedge VAR40)
if (reset)
state <= VAR24;
else
state <= VAR33;
always @ (*)
case (state)
VAR24:
if (VAR48 && VAR26 == 8'h55)
VAR33 = VAR51;
else
VAR33 = VAR24;
VAR51:
if (!VAR48)
VAR33 = VAR37;
else if (VAR12)
VAR33 = VAR53;
else if (VAR26 == 8'hd5)
VAR33 = VAR15;
else if (VAR26 == 8'h55)
VAR33 = VAR51;
else
VAR33 = VAR53;
VAR15:
if (!VAR48 && !VAR14 && !VAR54 && VAR58 == VAR1)
VAR33 = VAR41;
else if ((!VAR48 && (VAR14 || VAR54)) || (!VAR48 && VAR58 != VAR1))
VAR33 = VAR37;
else if (VAR18)
VAR33 = VAR53;
else if (VAR12 || VAR54)
VAR33 = VAR53;
else
VAR33 = VAR15;
VAR53:
if (!VAR48)
VAR33 = VAR37;
else
VAR33 = VAR53;
VAR41:
VAR33 = VAR24;
VAR37:
VAR33 = VAR24;
default:
VAR33 = VAR24;
endcase
always @(posedge VAR40 or posedge reset)
begin
if (reset)
begin
VAR16 <= 32'h00000000;
end
else if (state == VAR24)
begin
VAR16 <= 32'h00000000;
end
else
begin
VAR16[39-:8] <= VAR16[31-:8];
VAR16[31-:8] <= VAR16[23-:8];
VAR16[23-:8] <= VAR16[15-:8];
VAR16[15-:8] <= VAR16[7-:8];
VAR16[7-:8] <= VAR26;
end
end
always @ ( state or VAR32 )
begin
if (VAR32 && state == VAR41)
begin
VAR28 <= 1;
end
else if (!VAR32)
begin
VAR28 <= 0;
end
end
always @ (posedge VAR40 or posedge reset)
if (reset)
VAR22 <= 0;
else if (state == VAR15)
VAR22 = VAR22 + 1;
else
VAR22 = 0;
always @ (VAR22 or state)
if (VAR22 > 4 && state == VAR15 && VAR33 == VAR15)
VAR44 = 1;
else
VAR44 = 0;
always @(VAR22)
if (VAR22 == 5)
VAR49 = 1;
else
VAR49 = 0;
always @(state or VAR33)
if (state == VAR15 && VAR33 != VAR15)
VAR30 = 1;
else
VAR30 = 0;
always @(state)
if (state == VAR37)
VAR2 = 1;
else
VAR2 = 0;
always @(state)
if (state == VAR15)
VAR35 = 1;
else
VAR35 = 0;
always @(state or VAR33)
if (state == VAR51 && VAR33 == VAR15)
begin
VAR20 <= 1;
VAR38 <= VAR29;
end
else
VAR20 = 0;
always @ (posedge VAR40 or posedge reset)
if (reset)
VAR3 <= 0;
else if (state == VAR15)
VAR3 = VAR3 + 1;
else
VAR3 = 0;
always @ (VAR3)
if (VAR3 < VAR21)
VAR14 = 1;
else
VAR14 = 0;
always @ (VAR3)
if (VAR3 > VAR57)
VAR54 = 1;
else
VAR54 = 0;
VAR34 #( .VAR23(VAR5),
.VAR59(8),
.VAR31(32),
.VAR6(VAR47))
VAR19(
.reset(reset),
.VAR40(VAR40),
.VAR46(VAR20),
.VAR16(VAR26),
.VAR35(VAR35),
.VAR58(VAR58)
);
VAR52 #(
.VAR59 (8),
.VAR9 (VAR9)
)
VAR4 (
.reset(reset),
.VAR55(VAR32),
.VAR45(VAR18),
.VAR39(VAR16[39-:8]),
.VAR11(VAR49),
.VAR50(VAR30),
.VAR17(VAR40),
.VAR27(VAR44),
.VAR29(VAR29),
.VAR56(VAR2),
.VAR38(VAR38),
.VAR25(VAR25),
.VAR36(VAR36),
.VAR42(VAR42),
.VAR7(VAR7),
.VAR43(VAR43),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR13(VAR13)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp.functional.v | 1,984 | module MODULE1 (
VAR19,
VAR8 ,
VAR15,
VAR4
);
output VAR19;
input VAR8 ;
input VAR15;
input VAR4 ;
wire VAR18 ;
wire VAR11 ;
wire VAR17 ;
wire VAR10 ;
wire VAR6 ;
wire VAR14 ;
wire VAR5;
wire VAR2 ;
not VAR7 (VAR11 , VAR18 );
not VAR12 (VAR17 , VAR4 );
nor VAR9 (VAR2, VAR15, VAR8 );
VAR16 VAR3 VAR1 (VAR18 , VAR2, VAR17 );
and VAR13 (VAR19 , VAR11, VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_pwrgood_pp_g/sky130_fd_sc_ls__udp_pwrgood_pp_g.symbol.v | 1,285 | module MODULE1 (
input VAR1 ,
output VAR3,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp.blackbox.v | 1,455 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR10 ,
VAR11
);
output VAR6 ;
output VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR10 ;
input VAR11;
supply1 VAR3;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/cabac_neighbour_2p_12x128.v | 2,485 | module MODULE1(
clk ,
VAR18 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR14 ,
VAR1
);
input clk ; input VAR18 ; input [6:0] VAR7 ; input VAR3 ; input [6:0] VAR2 ; input [11:0] VAR14 ;
output [11:0] VAR1 ;
VAR9 #(.VAR13(7), .VAR16(12))
VAR11 (
.VAR10 ( clk ),
.VAR8 ( ~VAR18 ),
.VAR15 ( VAR7 ),
.VAR6 ( VAR1 ),
.VAR12 ( clk ),
.VAR4 ( ~VAR3 ),
.VAR19 ( ~VAR3 ),
.VAR17 ( VAR2 ),
.VAR5 ( VAR14 )
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai.symbol.v | 1,410 | module MODULE1 (
input VAR6,
input VAR4,
input VAR7,
input VAR3,
input VAR10,
output VAR2
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
drichmond/riffa | fpga/altera/de5/DE5QGen3x4If128/hdl/DE5QGen3x4If128.v | 17,194 | module MODULE1
parameter VAR164 = 4,
parameter VAR195 = 128,
parameter VAR88 = 256,
parameter VAR77 = 5
)
(
output [7:0] VAR155,
input VAR82,
input VAR173,
input [VAR164-1:0] VAR152,
output [VAR164-1:0] VAR89,
input VAR184
);
wire VAR131;
wire VAR85;
wire [3:0] VAR199;
wire [31:0] VAR64;
wire [52:0] VAR80;
wire [0:0] VAR83;
wire [0:0] VAR94;
wire [0:0] VAR73;
wire [0:0] VAR113;
wire [0:0] VAR63;
wire VAR9;
wire [VAR195-1:0] VAR14;
wire [0:0] VAR84;
wire [0:0] VAR47;
wire [0:0] VAR185;
wire [0:0] VAR96;
wire VAR69;
wire [VAR195-1:0] VAR180;
wire [0:0] VAR189;
wire VAR81;
wire VAR90;
wire VAR67;
wire VAR101;
wire VAR172;
wire VAR130;
wire VAR102;
wire VAR46;
wire VAR123;
wire VAR198;
wire VAR2;
wire VAR8;
wire [7:0] VAR44;
wire [7:0] VAR36;
wire VAR58;
wire VAR147;
wire VAR140;
wire VAR61;
wire VAR110;
wire VAR35;
wire VAR65;
wire VAR78;
wire [3:0] VAR182;
wire VAR161;
wire [3:0] VAR22;
wire [4:0] VAR128;
wire VAR174;
wire [1:0] VAR99;
wire VAR154;
wire [7:0] VAR156;
wire [11:0] VAR203;
assign VAR81 = VAR90;
assign VAR123 = VAR173;
assign VAR2 = VAR173;
assign VAR67 = VAR173;
assign VAR101 = VAR130;
assign VAR8 = 1'b0;
assign VAR198 = 1'b0;
assign VAR85 = VAR82;
assign VAR131 = VAR82;
assign VAR155[7:0] = 8'hff;
VAR170
VAR190
(
.VAR50 (VAR83[0:0]),
.VAR143 (VAR94[0:0]),
.VAR113 (VAR113[0:0]),
.VAR63 (VAR63[0:0]),
.VAR14 (VAR14[127:0]),
.VAR69 (VAR69),
.VAR148 (VAR172),
.VAR186 (VAR130),
.VAR136 (VAR199[3:0]),
.VAR52 (VAR64[31:0]),
.VAR42 (VAR80[52:0]),
.VAR54 (VAR90),
.VAR114 (VAR89[0]),
.VAR71 (VAR89[1]),
.VAR31 (VAR89[2]),
.VAR187 (VAR89[3]),
.VAR158 (VAR46),
.VAR134 (VAR58),
.VAR48 (VAR147),
.VAR116 (VAR140),
.VAR150 (VAR61),
.VAR72 (VAR110),
.VAR160 (VAR35),
.VAR100 (VAR65),
.VAR192 (VAR78),
.VAR97 (VAR182),
.VAR104 (VAR161),
.VAR106 (VAR22),
.VAR153 (VAR128),
.VAR119 (VAR174),
.VAR34 (VAR99),
.VAR20 (VAR154),
.VAR144 (VAR156),
.VAR45 (VAR203),
.VAR9 (VAR9),
.VAR141 (VAR84[0:0]),
.VAR167 (VAR47[0:0]),
.VAR96 (VAR96[0:0]),
.VAR189 (VAR189[0:0]),
.VAR180 (VAR180[127:0]),
.VAR126 (VAR101),
.VAR176 (VAR131),
.VAR191 (VAR85),
.VAR60 (VAR67),
.VAR32 (VAR2),
.VAR92 (VAR81),
.VAR57 (VAR8),
.VAR198 (VAR198),
.VAR123 (VAR123),
.VAR201 (VAR81),
.VAR135 (VAR152[0]),
.VAR21 (VAR152[1]),
.VAR91 (VAR152[2]),
.VAR18 (VAR152[3]),
.VAR4 (VAR102),
.VAR28 (VAR58),
.VAR75 (VAR147),
.VAR95 (VAR140),
.VAR138 (VAR61),
.VAR79 (VAR110),
.VAR55 (VAR35),
.VAR16 (VAR65),
.VAR39 (VAR78),
.VAR193 (VAR182),
.VAR66 (VAR161),
.VAR137 (VAR22),
.VAR171 (VAR128),
.VAR7 (VAR174),
.VAR70 (VAR99),
.VAR15 (VAR154),
.VAR175 (VAR156),
.VAR118 (VAR203));
wire VAR139;
wire [VAR3-1:0] VAR121;
wire [VAR3-1:0] VAR51;
wire [VAR3-1:0] VAR115;
wire [VAR3-1:0] VAR5;
wire [(VAR3*32)-1:0] VAR43;
wire [(VAR3*31)-1:0] VAR177;
wire [(VAR3*VAR195)-1:0] VAR125;
wire [VAR3-1:0] VAR127;
wire [VAR3-1:0] VAR53;
wire [VAR3-1:0] VAR200;
wire [VAR3-1:0] VAR11;
wire [VAR3-1:0] VAR194;
wire [VAR3-1:0] VAR23;
wire [(VAR3*32)-1:0] VAR38;
wire [(VAR3*31)-1:0] VAR59;
wire [(VAR3*VAR195)-1:0] VAR109;
wire [VAR3-1:0] VAR105;
wire [VAR3-1:0] VAR129;
wire VAR17;
wire VAR159;
wire VAR196;
wire VAR181;
assign VAR196 = VAR172;
assign VAR181 = VAR81;
assign VAR159 = VAR81;
assign VAR17 = VAR139;
VAR30
.VAR77 (VAR77),
.VAR3 (VAR3),
.VAR195 (VAR195),
.VAR88 (VAR88))
VAR162
(
.VAR157 (VAR9),
.VAR62 (VAR180[VAR195-1:0]),
.VAR74 (VAR96[0:0]),
.VAR49 (VAR47[0:0]),
.VAR68 (VAR84[0:0]),
.VAR112 (VAR189[0:0]),
.VAR33 (VAR102),
.VAR179 (VAR139),
.VAR146 (VAR51[VAR3-1:0]),
.VAR183 (VAR5[VAR3-1:0]),
.VAR29 (VAR43[(VAR3*VAR142)-1:0]),
.VAR25 (VAR177[(VAR3*VAR76)-1:0]),
.VAR188 (VAR125[(VAR3*VAR195)-1:0]),
.VAR86 (VAR127[VAR3-1:0]),
.VAR149 (VAR194[VAR3-1:0]),
.VAR40 (VAR129[VAR3-1:0]),
.VAR133 (VAR14[VAR195-1:0]),
.VAR12 (VAR94[0:0]),
.VAR87 (VAR83[0:0]),
.VAR111 (VAR113[0:0]),
.VAR37 (VAR63[0:0]),
.VAR145 (VAR69),
.VAR165 (VAR64[VAR166-1:0]),
.VAR163 (VAR199[VAR120-1:0]),
.VAR108 (VAR80[VAR103-1:0]),
.VAR122 (VAR156[VAR124-1:0]),
.VAR6 (VAR203[VAR27-1:0]),
.VAR107 (VAR46),
.VAR19 (VAR81),
.VAR41 (VAR172),
.VAR169 (VAR121[VAR3-1:0]),
.VAR24 (VAR115[VAR3-1:0]),
.VAR56 (VAR53[VAR3-1:0]),
.VAR10 (VAR200[VAR3-1:0]),
.VAR151 (VAR11[VAR3-1:0]),
.VAR98 (VAR23[VAR3-1:0]),
.VAR117 (VAR38[(VAR3*VAR142)-1:0]),
.VAR132 (VAR59[(VAR3*VAR76)-1:0]),
.VAR26 (VAR109[(VAR3*VAR195)-1:0]),
.VAR93 (VAR105[VAR3-1:0]));
genvar VAR178;
generate
for (VAR178 = 0; VAR178 < VAR3; VAR178 = VAR178 + 1) begin : VAR168
VAR1
.VAR195(VAR195)
)
VAR202
(
.VAR13(VAR159),
.VAR197(VAR17), .VAR169(VAR121[VAR178]),
.VAR146(VAR51[VAR178]),
.VAR24(VAR115[VAR178]),
.VAR183(VAR5[VAR178]),
.VAR29(VAR43[VAR142*VAR178 +:VAR142]),
.VAR25(VAR177[VAR76*VAR178 +:VAR76]),
.VAR188(VAR125[VAR195*VAR178 +:VAR195]),
.VAR86(VAR127[VAR178]),
.VAR56(VAR53[VAR178]),
.VAR10(VAR200[VAR178]),
.VAR151(VAR11[VAR178]),
.VAR149(VAR194[VAR178]),
.VAR98(VAR23[VAR178]),
.VAR117(VAR38[VAR142*VAR178 +:VAR142]),
.VAR132(VAR59[VAR76*VAR178 +:VAR76]),
.VAR26(VAR109[VAR195*VAR178 +:VAR195]),
.VAR93(VAR105[VAR178]),
.VAR40(VAR129[VAR178])
);
end
endgenerate
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s.behavioral.v | 1,441 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR2;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR8 ;
wire VAR3;
buf VAR7 (VAR3, VAR4 );
buf VAR6 (VAR1 , VAR3 );
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_registers.v | 36,445 | module MODULE1( VAR233, VAR218, VAR195, VAR223, VAR206, VAR41, VAR142,
VAR107, VAR199, VAR258, VAR246, VAR86,
VAR257, VAR247, VAR198, VAR133, VAR115,
VAR280, VAR158, VAR37, VAR279, VAR57, VAR289,
VAR205, VAR7, VAR127, VAR272, VAR75,
VAR249, VAR153, VAR29, VAR62, VAR36, VAR162,
VAR256, VAR220, VAR160, VAR2,
VAR26, VAR155, VAR40, VAR78, VAR164,
VAR240, VAR150, VAR114, VAR48, VAR110,
VAR121, VAR156, VAR72, VAR73,
VAR300, VAR288, VAR260, VAR297,
VAR105, VAR43, VAR242, VAR182, VAR109, VAR1,
VAR184,
VAR263, VAR16, VAR49, VAR5
);
input [31:0] VAR233;
input [7:0] VAR218;
input VAR195;
input [3:0] VAR223;
input VAR206;
input VAR41;
input VAR72;
input VAR73;
input VAR300;
input [15:0] VAR288;
output [31:0] VAR142;
reg [31:0] VAR142;
output VAR107;
output VAR199;
output VAR258;
output VAR246;
output VAR86;
output VAR257;
output VAR247;
output VAR198;
output VAR133;
output VAR115;
output VAR280;
output VAR158;
output VAR37;
output VAR279;
output VAR57;
output VAR289;
output [31:0] VAR105;
output [31:0] VAR43;
input VAR205;
input VAR7;
input VAR127;
input VAR272;
input VAR75;
output [6:0] VAR249;
output [6:0] VAR153;
output [6:0] VAR29;
output [15:0] VAR62;
output [15:0] VAR36;
output [3:0] VAR162;
output [5:0] VAR256;
output VAR220;
output VAR160;
output VAR2;
output VAR26;
output [7:0] VAR155;
output VAR40;
output VAR78;
output VAR164;
output [4:0] VAR240;
output [4:0] VAR150;
output [15:0]VAR114;
input VAR48;
input VAR110;
input VAR121;
output [47:0]VAR156;
output [7:0] VAR260;
output VAR297;
output [15:0]VAR242;
output VAR182;
input VAR109;
input VAR1;
input VAR263;
input VAR16;
input VAR49;
input VAR5;
input [31:0] VAR184;
reg VAR6;
reg VAR161;
reg VAR183;
reg VAR295;
reg VAR81;
reg VAR171;
reg VAR196;
reg VAR299;
reg VAR283, VAR119, VAR255;
reg VAR170;
reg VAR68, VAR290;
reg VAR284;
reg VAR268, VAR126, VAR147;
reg VAR192;
reg VAR90;
reg VAR122;
reg VAR229;
wire [3:0] VAR180 = VAR223 & {4{VAR195}};
wire VAR163 = (|VAR223) & ~VAR195;
wire VAR28 = (VAR218 == VAR84 );
wire VAR245 = (VAR218 == VAR210 );
wire VAR168 = (VAR218 == VAR93 );
wire VAR273 = (VAR218 == VAR191 );
wire VAR271 = (VAR218 == VAR261 );
wire VAR214 = (VAR218 == VAR204 );
wire VAR24 = (VAR218 == VAR99 );
wire VAR185 = (VAR218 == VAR236 );
wire VAR266 = (VAR218 == VAR53 );
wire VAR25 = (VAR218 == VAR166 );
wire VAR230 = (VAR218 == VAR194 );
wire VAR188 = (VAR218 == VAR4 );
wire VAR98 = (VAR218 == VAR96 );
wire VAR270 = (VAR218 == VAR91 );
wire VAR244 = (VAR218 == VAR14 );
wire VAR15 = (VAR218 == VAR178 );
wire VAR275 = (VAR218 == VAR207 );
wire VAR117 = (VAR218 == VAR100 );
wire VAR34 = (VAR218 == VAR79 );
wire VAR123 = (VAR218 == VAR97 );
wire VAR54 = (VAR218 == VAR167 );
wire [2:0] VAR221;
wire [0:0] VAR215;
wire [0:0] VAR35;
wire [0:0] VAR92;
wire [0:0] VAR211;
wire [0:0] VAR197;
wire [3:0] VAR129;
wire [2:0] VAR250;
wire [0:0] VAR143;
wire [1:0] VAR231;
wire [0:0] VAR173;
wire [1:0] VAR137;
wire [1:0] VAR66;
wire VAR50;
wire [3:0] VAR71;
wire [1:0] VAR226;
wire [3:0] VAR56;
wire [3:0] VAR13;
wire [2:0] VAR20;
wire [0:0] VAR227;
assign VAR221[0] = VAR180[0] & VAR28;
assign VAR221[1] = VAR180[1] & VAR28;
assign VAR221[2] = VAR180[2] & VAR28;
assign VAR215[0] = VAR180[0] & VAR245;
assign VAR35[0] = VAR180[0] & VAR168;
assign VAR92[0] = VAR180[0] & VAR273;
assign VAR211[0] = VAR180[0] & VAR271;
assign VAR197[0] = VAR180[0] & VAR214;
assign VAR129[0] = VAR180[0] & VAR24;
assign VAR129[1] = VAR180[1] & VAR24;
assign VAR129[2] = VAR180[2] & VAR24;
assign VAR129[3] = VAR180[3] & VAR24;
assign VAR250[0] = VAR180[0] & VAR185;
assign VAR250[1] = 1'b0; assign VAR250[2] = VAR180[2] & VAR185;
assign VAR143[0] = VAR180[0] & VAR266;
assign VAR231[0] = VAR180[0] & VAR25;
assign VAR231[1] = VAR180[1] & VAR25;
assign VAR173[0] = VAR180[0] & VAR230;
assign VAR137[0] = VAR180[0] & VAR188;
assign VAR137[1] = VAR180[1] & VAR188;
assign VAR66[0] = VAR180[0] & VAR98;
assign VAR66[1] = VAR180[1] & VAR98;
assign VAR50 = VAR300;
assign VAR71[0] = VAR180[0] & VAR270;
assign VAR71[1] = VAR180[1] & VAR270;
assign VAR71[2] = VAR180[2] & VAR270;
assign VAR71[3] = VAR180[3] & VAR270;
assign VAR226[0] = VAR180[0] & VAR244;
assign VAR226[1] = VAR180[1] & VAR244;
assign VAR56[0] = VAR180[0] & VAR15;
assign VAR56[1] = VAR180[1] & VAR15;
assign VAR56[2] = VAR180[2] & VAR15;
assign VAR56[3] = VAR180[3] & VAR15;
assign VAR13[0] = VAR180[0] & VAR275;
assign VAR13[1] = VAR180[1] & VAR275;
assign VAR13[2] = VAR180[2] & VAR275;
assign VAR13[3] = VAR180[3] & VAR275;
assign VAR20[0] = VAR180[0] & VAR117;
assign VAR20[1] = VAR180[1] & VAR117;
assign VAR20[2] = VAR180[2] & VAR117;
assign VAR227[0] = VAR180[0] & VAR54 & (VAR233<='h80);
wire [31:0] VAR269;
wire [31:0] VAR134;
wire [31:0] VAR103;
wire [31:0] VAR203;
wire [31:0] VAR67;
wire [31:0] VAR175;
wire [31:0] VAR177;
wire [31:0] VAR151;
wire [31:0] VAR251;
wire [31:0] VAR187;
wire [31:0] VAR274;
wire [31:0] VAR82;
wire [31:0] VAR148;
wire [31:0] VAR282;
wire [31:0] VAR287;
wire [31:0] VAR112;
wire [31:0] VAR87;
wire [31:0] VAR58;
wire [31:0] VAR32;
wire [31:0] VAR239;
wire [31:0] VAR176;
wire [31:0] VAR291;
VAR237 #(VAR130, VAR76) VAR23
(
.VAR233 (VAR233[VAR130 - 1:0]),
.VAR142 (VAR269[VAR130 - 1:0]),
.VAR180 (VAR221[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR286, VAR144) VAR51
(
.VAR233 (VAR233[VAR286 + 7:8]),
.VAR142 (VAR269[VAR286 + 7:8]),
.VAR180 (VAR221[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR74, VAR243) VAR222
(
.VAR233 (VAR233[VAR74 + 15:16]),
.VAR142 (VAR269[VAR74 + 15:16]),
.VAR180 (VAR221[2]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR269[31:VAR74 + 16] = 0;
VAR237 #(VAR292, VAR61) VAR47
(
.VAR233 (VAR233[VAR292 - 1:0]),
.VAR142 (VAR103[VAR292 - 1:0]),
.VAR180 (VAR35[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR103[31:VAR292] = 0;
VAR237 #(VAR172, VAR190) VAR293
(
.VAR233 (VAR233[VAR172 - 1:0]),
.VAR142 (VAR203[VAR172 - 1:0]),
.VAR180 (VAR92[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR203[31:VAR172] = 0;
VAR237 #(VAR141, VAR296) VAR235
(
.VAR233 (VAR233[VAR141 - 1:0]),
.VAR142 (VAR67[VAR141 - 1:0]),
.VAR180 (VAR211[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR67[31:VAR141] = 0;
VAR237 #(VAR135, VAR52) VAR22
(
.VAR233 (VAR233[VAR135 - 1:0]),
.VAR142 (VAR175[VAR135 - 1:0]),
.VAR180 (VAR197[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR175[31:VAR135] = 0;
VAR237 #(VAR59, VAR106) VAR128
(
.VAR233 (VAR233[VAR59 - 1:0]),
.VAR142 (VAR177[VAR59 - 1:0]),
.VAR180 (VAR129[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR38, VAR45) VAR200
(
.VAR233 (VAR233[VAR38 + 7:8]),
.VAR142 (VAR177[VAR38 + 7:8]),
.VAR180 (VAR129[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR11, VAR94) VAR169
(
.VAR233 (VAR233[VAR11 + 15:16]),
.VAR142 (VAR177[VAR11 + 15:16]),
.VAR180 (VAR129[2]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR31, VAR8) VAR201
(
.VAR233 (VAR233[VAR31 + 23:24]),
.VAR142 (VAR177[VAR31 + 23:24]),
.VAR180 (VAR129[3]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR248, VAR209) VAR33
(
.VAR233 (VAR233[VAR248 - 1:0]),
.VAR142 (VAR151[VAR248 - 1:0]),
.VAR180 (VAR250[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR217, VAR252) VAR19
(
.VAR233 (VAR233[VAR217 + 15:16]),
.VAR142 (VAR151[VAR217 + 15:16]),
.VAR180 (VAR250[2]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR151[15:VAR248] = 0;
assign VAR151[31:VAR217 + 16] = 0;
VAR237 #(VAR186, VAR95) VAR298
(
.VAR233 (VAR233[VAR186 - 1:0]),
.VAR142 (VAR58[VAR186 - 1:0]),
.VAR180 (VAR227[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR58[31:VAR186] = 0;
VAR237 #(VAR145, VAR116) VAR132
(
.VAR233 (VAR233[VAR145 - 1:0]),
.VAR142 (VAR251[VAR145 - 1:0]),
.VAR180 (VAR143[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR251[31:VAR145] = 0;
VAR237 #(VAR278, VAR146) VAR262
(
.VAR233 (VAR233[VAR278 - 1:0]),
.VAR142 (VAR187[VAR278 - 1:0]),
.VAR180 (VAR231[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR65, VAR44) VAR159
(
.VAR233 (VAR233[VAR65 + 7:8]),
.VAR142 (VAR187[VAR65 + 7:8]),
.VAR180 (VAR231[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR187[31:VAR65 + 8] = 0;
VAR237 #(1, 0) VAR241
(
.VAR233 (VAR233[0]),
.VAR142 (VAR274[0]),
.VAR180 (VAR173[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(1, 0) VAR21
(
.VAR233 (VAR233[1]),
.VAR142 (VAR274[1]),
.VAR180 (VAR173[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (VAR73)
);
VAR237 #(1, 0) VAR259
(
.VAR233 (VAR233[2]),
.VAR142 (VAR274[2]),
.VAR180 (VAR173[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (VAR72)
);
assign VAR274[31:VAR131] = 29'h0;
VAR237 #(VAR125, VAR234) VAR17
(
.VAR233 (VAR233[VAR125 - 1:0]),
.VAR142 (VAR82[VAR125 - 1:0]),
.VAR180 (VAR137[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR238, VAR154) VAR294
(
.VAR233 (VAR233[VAR238 + 7:8]),
.VAR142 (VAR82[VAR238 + 7:8]),
.VAR180 (VAR137[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR82[7:VAR125] = 0;
assign VAR82[31:VAR238 + 8] = 0;
VAR237 #(VAR69, VAR120) VAR281
(
.VAR233 (VAR233[VAR69 - 1:0]),
.VAR142 (VAR148[VAR69 - 1:0]),
.VAR180 (VAR66[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR152, VAR89) VAR264
(
.VAR233 (VAR233[VAR152 + 7:8]),
.VAR142 (VAR148[VAR152 + 7:8]),
.VAR180 (VAR66[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR148[31:VAR152 + 8] = 0;
VAR237 #(VAR189, VAR179) VAR232
(
.VAR233 (VAR288[VAR189-1:0]),
.VAR142 (VAR282[VAR189-1:0]),
.VAR180 (VAR50), .VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR282[31:VAR189] = 0;
VAR237 #(VAR101, VAR124) VAR219
(
.VAR233 (VAR233[VAR101 - 1:0]),
.VAR142 (VAR112[VAR101 - 1:0]),
.VAR180 (VAR71[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR193, VAR85) VAR253
(
.VAR233 (VAR233[VAR193 + 7:8]),
.VAR142 (VAR112[VAR193 + 7:8]),
.VAR180 (VAR71[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR254, VAR118) VAR165
(
.VAR233 (VAR233[VAR254 + 15:16]),
.VAR142 (VAR112[VAR254 + 15:16]),
.VAR180 (VAR71[2]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR224, VAR9) VAR212
(
.VAR233 (VAR233[VAR224 + 23:24]),
.VAR142 (VAR112[VAR224 + 23:24]),
.VAR180 (VAR71[3]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR216, VAR104) VAR213
(
.VAR233 (VAR233[VAR216 - 1:0]),
.VAR142 (VAR87[VAR216 - 1:0]),
.VAR180 (VAR226[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR63, VAR149) VAR108
(
.VAR233 (VAR233[VAR63 + 7:8]),
.VAR142 (VAR87[VAR63 + 7:8]),
.VAR180 (VAR226[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
assign VAR87[31:VAR63 + 8] = 0;
VAR237 #(VAR276, VAR265) VAR39
(
.VAR233 (VAR233[VAR276 - 1:0]),
.VAR142 (VAR32[VAR276 - 1:0]),
.VAR180 (VAR56[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR208, VAR30) VAR136
(
.VAR233 (VAR233[VAR208 + 7:8]),
.VAR142 (VAR32[VAR208 + 7:8]),
.VAR180 (VAR56[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR277, VAR113) VAR42
(
.VAR233 (VAR233[VAR277 + 15:16]),
.VAR142 (VAR32[VAR277 + 15:16]),
.VAR180 (VAR56[2]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR60, VAR228) VAR55
(
.VAR233 (VAR233[VAR60 + 23:24]),
.VAR142 (VAR32[VAR60 + 23:24]),
.VAR180 (VAR56[3]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR225, VAR18) VAR10
(
.VAR233 (VAR233[VAR225 - 1:0]),
.VAR142 (VAR239[VAR225 - 1:0]),
.VAR180 (VAR13[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR88, VAR267) VAR202
(
.VAR233 (VAR233[VAR88 + 7:8]),
.VAR142 (VAR239[VAR88 + 7:8]),
.VAR180 (VAR13[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR157, VAR102) VAR46
(
.VAR233 (VAR233[VAR157 + 15:16]),
.VAR142 (VAR239[VAR157 + 15:16]),
.VAR180 (VAR13[2]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR12, VAR27) VAR174
(
.VAR233 (VAR233[VAR12 + 23:24]),
.VAR142 (VAR239[VAR12 + 23:24]),
.VAR180 (VAR13[3]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR285, VAR181) VAR139
(
.VAR233 (VAR233[VAR285 - 1:0]),
.VAR142 (VAR176[VAR285 - 1:0]),
.VAR180 (VAR20[0]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR80, VAR111) VAR70
(
.VAR233 (VAR233[VAR80 + 7:8]),
.VAR142 (VAR176[VAR80 + 7:8]),
.VAR180 (VAR20[1]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (1'b0)
);
VAR237 #(VAR3, VAR64) VAR77 (
.VAR233 (VAR233[VAR3 + 15:16]),
.VAR142 (VAR176[VAR3 + 15:16]),
.VAR180 (VAR20[2]),
.VAR206 (VAR206),
.VAR41 (VAR41),
.VAR140 (VAR109)
);
assign VAR176[31:VAR3 + 16] = 0;
always @ (VAR218 or VAR163 or VAR269 or VAR134 or
VAR103 or VAR203 or VAR67 or VAR175 or
VAR177 or VAR151 or VAR251 or VAR187 or
VAR274 or VAR82 or VAR148 or VAR282 or
VAR287 or VAR112 or VAR87 or VAR58 or
VAR32 or VAR239 or VAR176
)
begin
if(VAR163) begin
case(VAR218)
default: VAR142=32'h0;
endcase
end
else
VAR142=32'h0;
end
assign VAR107 = VAR269[16];
assign VAR199 = VAR269[15];
assign VAR258 = VAR269[14];
assign VAR246 = VAR269[13];
assign VAR86 = VAR269[12];
assign VAR257 = VAR269[10];
assign VAR247 = VAR269[9];
assign VAR198 = VAR269[8];
assign VAR133 = VAR269[7];
assign VAR115 = VAR269[6];
assign VAR280 = VAR269[5];
assign VAR158 = VAR269[4];
assign VAR37 = VAR269[3];
assign VAR279 = VAR269[2];
assign VAR57 = VAR269[1] & (VAR58>0); assign VAR289 = VAR269[0] & (VAR58<'h80);
assign VAR249[6:0] = VAR203[6:0];
assign VAR153[6:0] = VAR67[6:0];
assign VAR29[6:0] = VAR175[6:0];
assign VAR62[15:0] = VAR177[31:16];
assign VAR36[15:0] = VAR177[15:0];
assign VAR162[3:0] = VAR151[19:16];
assign VAR256[5:0] = VAR151[5:0];
assign VAR220 = VAR251[2];
assign VAR160 = VAR251[1];
assign VAR2 = VAR251[0];
assign VAR26 = VAR187[8];
assign VAR155[7:0] = VAR187[7:0];
assign VAR40 = VAR274[2];
assign VAR78 = VAR274[1];
assign VAR164 = VAR274[0];
assign VAR240[4:0] = VAR82[12:8];
assign VAR150[4:0] = VAR82[4:0];
assign VAR114[15:0] = VAR148[15:0];
assign VAR287[31:VAR83] = 0;
assign VAR287[2] = VAR48 ;
assign VAR287[1] = VAR110 ;
assign VAR287[0] = VAR121 ;
assign VAR156[31:0] = VAR112[31:0];
assign VAR156[47:32] = VAR87[15:0];
assign VAR43[31:0] = VAR239;
assign VAR105[31:0] = VAR32;
assign VAR260[7:0] = VAR58[7:0];
assign VAR242[15:0] = VAR176[15:0];
assign VAR182 = VAR176[16];
always @ (posedge VAR16 or posedge VAR41)
begin
if(VAR41)
VAR299 <= 1'b0;
end
else
if(VAR1 & VAR263 & VAR220)
VAR299 <= 1'b1;
else
if(VAR290)
VAR299 <= 1'b0;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR283 <= 1'b0;
end
else
VAR283 <= VAR299;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR119 <= 1'b0;
end
else
VAR119 <= VAR283;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR255 <= 1'b0;
end
else
VAR255 <= VAR119;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR170 <= 1'b0;
end
else
VAR170 <= VAR119 & ~VAR255;
end
always @ (posedge VAR16 or posedge VAR41)
begin
if(VAR41)
VAR68 <= 1'b0;
end
else
VAR68 <= VAR119;
end
always @ (posedge VAR16 or posedge VAR41)
begin
if(VAR41)
VAR290 <= 1'b0;
end
else
VAR290 <= VAR283;
end
always @ (posedge VAR49 or posedge VAR41)
begin
if(VAR41)
VAR284 <= 1'b0;
end
else
if(VAR5 & VAR160)
VAR284 <= 1'b1;
else
if(VAR122 & (~VAR229))
VAR284 <= 1'b0;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR268 <= 1'b0;
end
else
VAR268 <= VAR284;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR126 <= 1'b0;
end
else
VAR126 <= VAR268;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR147 <= 1'b0;
end
else
VAR147 <= VAR126;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR192 <= 1'b0;
end
else
VAR192 <= VAR126 & ~VAR147;
end
always @ (posedge VAR49 or posedge VAR41)
begin
if(VAR41)
VAR90 <= 1'b0;
end
else
VAR90 <= VAR126;
end
always @ (posedge VAR49 or posedge VAR41)
begin
if(VAR41)
VAR122 <= 1'b0;
end
else
VAR122 <= VAR90;
end
always @ (posedge VAR49 or posedge VAR41)
begin
if(VAR41)
VAR229 <= 1'b0;
end
else
VAR229 <= VAR122;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR6 <= 1'b0;
end
else
if(VAR205)
VAR6 <= 1'b1;
else
if(VAR215[0] & VAR233[0])
VAR6 <= 1'b0;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR161 <= 1'b0;
end
else
if(VAR7)
VAR161 <= 1'b1;
else
if(VAR215[0] & VAR233[1])
VAR161 <= 1'b0;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR183 <= 1'b0;
end
else
if(VAR127)
VAR183 <= 1'b1;
else
if(VAR215[0] & VAR233[2])
VAR183 <= 1'b0;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR295 <= 1'b0;
end
else
if(VAR272)
VAR295 <= 1'b1;
else
if(VAR215[0] & VAR233[3])
VAR295 <= 1'b0;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR81 <= 1'b0;
end
else
if(VAR75)
VAR81 <= 1'b1;
else
if(VAR215[0] & VAR233[4])
VAR81 <= 1'b0;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR171 <= 1'b0;
end
else
if(VAR170)
VAR171 <= 1'b1;
else
if(VAR215[0] & VAR233[5])
VAR171 <= 1'b0;
end
always @ (posedge VAR206 or posedge VAR41)
begin
if(VAR41)
VAR196 <= 1'b0;
end
else
if(VAR192)
VAR196 <= 1'b1;
else
if(VAR215[0] & VAR233[6])
VAR196 <= 1'b0;
end
assign VAR297 = VAR6 & VAR103[0] |
VAR161 & VAR103[1] |
VAR183 & VAR103[2] |
VAR295 & VAR103[3] |
VAR81 & VAR103[4] |
VAR171 & VAR103[5] |
VAR196 & VAR103[6] ;
assign VAR134 = {{(32-VAR138){1'b0}}, VAR196, VAR171, VAR81, VAR295, VAR183, VAR161, VAR6};
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b.functional.pp.v | 1,956 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR8 ,
VAR9,
VAR15,
VAR7 ,
VAR4
);
output VAR10 ;
input VAR1 ;
input VAR8 ;
input VAR9;
input VAR15;
input VAR7 ;
input VAR4 ;
wire VAR3 ;
wire VAR6 ;
wire VAR11;
not VAR5 (VAR3 , VAR8 );
or VAR2 (VAR6 , VAR3, VAR1 );
VAR13 VAR14 (VAR11, VAR6, VAR9, VAR15);
buf VAR12 (VAR10 , VAR11 );
endmodule | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/niosII_system_onchip_memory2_0.v | 3,064 | module MODULE1 (
address,
VAR26,
VAR17,
clk,
VAR9,
reset,
VAR28,
write,
VAR12,
VAR2
)
;
parameter VAR20 = "MODULE1.VAR10";
output [ 31: 0] VAR2;
input [ 11: 0] address;
input [ 3: 0] VAR26;
input VAR17;
input clk;
input VAR9;
input reset;
input VAR28;
input write;
input [ 31: 0] VAR12;
wire VAR22;
wire [ 31: 0] VAR2;
wire VAR33;
assign VAR33 = VAR17 & write;
assign VAR22 = VAR9 & ~VAR28;
VAR34 VAR23
(
.VAR13 (address),
.VAR3 (VAR26),
.VAR1 (clk),
.VAR22 (VAR22),
.VAR4 (VAR12),
.VAR15 (VAR2),
.VAR29 (VAR33)
);
VAR23.VAR14 = VAR20,
VAR23.VAR6 = "VAR34",
VAR23.VAR18 = 4096,
VAR23.VAR5 = 4096,
VAR23.VAR30 = "VAR31",
VAR23.VAR7 = "VAR16",
VAR23.VAR8 = "VAR21",
VAR23.VAR32 = "VAR19",
VAR23.VAR27 = 32,
VAR23.VAR24 = 4,
VAR23.VAR25 = 12;
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/m32632/ICACHE_SM.v | 11,997 | module MODULE1 ( VAR90, VAR25, VAR102, VAR91, VAR41, VAR53, VAR73 , VAR96 , VAR91, VAR80, VAR5, VAR47, VAR74, VAR94, VAR83,
VAR75, VAR92, VAR26, VAR71, VAR63, VAR39, VAR6, VAR97 );
input VAR90;
input VAR25;
input VAR102;
input [23:0] VAR91; input [27:4] VAR41;
input [27:12] VAR53,VAR73;
input [1:0] VAR96;
input [23:0] VAR91; input VAR80;
input VAR5;
input VAR47; input VAR74;
input VAR94; input VAR83;
output [23:0] VAR75;
output VAR92;
output VAR26;
output VAR71;
output VAR63;
output [11:7] VAR39;
output [2:0] VAR6;
output VAR97;
reg [27:4] VAR21;
reg [7:0] VAR48,VAR2;
reg VAR66;
reg [2:0] counter;
reg [1:0] VAR79,VAR40;
reg [35:0] VAR49;
reg [8:0] VAR18,VAR62;
reg [1:0] state;
reg VAR77;
reg VAR45;
reg VAR55;
wire [7:0] VAR59,VAR37;
wire VAR68,VAR20;
wire VAR32,VAR24;
wire VAR28,VAR11;
wire VAR51,VAR19;
wire VAR35;
wire VAR22;
wire [23:0] VAR46;
wire [8:0] VAR85;
wire [7:0] VAR67,VAR87;
wire VAR10,VAR13;
wire VAR99,VAR38;
wire VAR82;
always @(posedge VAR90) VAR66 <= VAR102 & VAR96[0]; always @(posedge VAR90) VAR21 <= VAR41;
assign VAR59 = VAR91[7:0];
assign VAR37 = VAR91[15:8];
assign VAR32 = VAR59[VAR21[6:4]];
assign VAR24 = VAR37[VAR21[6:4]];
assign VAR68 = ( VAR53 == VAR21[27:12] ); assign VAR20 = ( VAR73 == VAR21[27:12] );
assign VAR28 = VAR32 & VAR68;
assign VAR11 = VAR24 & VAR20;
assign VAR51 = (VAR28 | VAR11) & ~VAR96[1] & VAR66;
assign VAR92 = (VAR28 | VAR11) & VAR66;
assign VAR19 = (VAR28 | VAR11) & ~VAR96[1] & VAR96[0];
assign VAR82 = VAR96[0] & ~VAR94;
always @(posedge VAR90)
if (!VAR82) VAR79 <= 2'b00;
else
VAR79 <= VAR79 + {1'b0,VAR22};
always @(posedge VAR90)
if (!VAR82) VAR40 <= 2'b00;
else
VAR40 <= VAR40 + {1'b0,VAR45};
always @(posedge VAR90)
begin
if (VAR22 && (VAR79 == 2'b00)) VAR49[8:0] <= {VAR21[11:4],VAR11};
if (VAR22 && (VAR79 == 2'b01)) VAR49[17:9] <= {VAR21[11:4],VAR11};
if (VAR22 && (VAR79 == 2'b10)) VAR49[26:18] <= {VAR21[11:4],VAR11};
if (VAR22 && (VAR79 == 2'b11)) VAR49[35:27] <= {VAR21[11:4],VAR11};
end
always @(VAR49 or VAR40)
case (VAR40)
2'b00 : VAR18 = VAR49[8:0];
2'b01 : VAR18 = VAR49[17:9];
2'b10 : VAR18 = VAR49[26:18];
2'b11 : VAR18 = VAR49[35:27];
endcase
always @(VAR49 or VAR79) case (VAR79)
2'b01 : VAR62 = VAR49[8:0];
2'b10 : VAR62 = VAR49[17:9];
2'b11 : VAR62 = VAR49[26:18];
2'b00 : VAR62 = VAR49[35:27];
endcase
assign VAR35 = counter[2] & (VAR62 == {VAR21[11:4],VAR11});
assign VAR22 = VAR51 & ~VAR35;
always @(posedge VAR90)
casex ({VAR82,VAR22,VAR45,counter})
6'VAR12 : counter <= 3'b000;
6'VAR31 : counter <= counter;
6'VAR9 : counter <= counter;
6'b110000 : counter <= 3'b100;
6'VAR56 : counter <= (counter[1:0] == 2'b11) ? 3'b111 : {counter[2],(counter[1:0] + 2'b01)}; 6'VAR4 : counter <= (counter[1:0] == 2'b00) ? 3'b000 : {counter[2],(counter[1:0] + 2'b11)};
default : counter <= counter;
endcase
always @(posedge VAR90) VAR55 <= ~VAR47;
assign VAR99 = (~VAR80 | VAR5) & VAR83;
always @(posedge VAR90) casex ({VAR25,VAR55,counter[2],VAR99,VAR38,VAR26,VAR10})
7'VAR88 : state <= 2'b00;
7'VAR29 : state <= 2'b00;
7'VAR81 : state <= 2'b10; 7'VAR98 : state <= 2'b11; 7'VAR76 : state <= 2'b10; 7'VAR57 : state <= 2'b00; 7'VAR61 : state <= 2'b11; 7'VAR30 : state <= 2'b00;
7'VAR93 : state <= 2'b10;
7'VAR7 : state <= 2'b11;
default : state <= 2'b00;
endcase
assign VAR26 = state[1]; assign VAR10 = state[0];
assign VAR97 = state[1] & ~VAR83;
assign VAR38 = (counter[1:0] == 2'b00) & VAR45;
assign VAR13 = VAR26 & VAR10;
always @(posedge VAR90) VAR77 <= VAR26;
assign VAR71 = ~(VAR26 | VAR77);
always @(posedge VAR90) VAR45 <= VAR26 & ~VAR10 & ~VAR45;
assign VAR63 = VAR45 | (VAR74 & VAR19);
assign VAR46 = VAR10 ? VAR91 : VAR91;
assign VAR85 = VAR10 ? {VAR21[11:4],VAR11} : VAR18;
assign VAR39 = VAR85[8:4];
always @(VAR85)
case (VAR85[3:1])
3'h0 : VAR2 = 8'hFE;
3'h1 : VAR2 = 8'hFD;
3'h2 : VAR2 = 8'hFB;
3'h3 : VAR2 = 8'hF7;
3'h4 : VAR2 = 8'hEF;
3'h5 : VAR2 = 8'hDF;
3'h6 : VAR2 = 8'hBF;
3'h7 : VAR2 = 8'h7F;
endcase
assign VAR67 = VAR85[0] ? VAR46[7:0] : (VAR46[7:0] & VAR2);
assign VAR87 = VAR85[0] ? (VAR46[15:8] & VAR2) : VAR46[15:8];
assign VAR75 = {VAR46[23:16],VAR87,VAR67};
assign VAR6 = {VAR55,VAR13,~(counter[2:1] == 2'b11)};
endmodule
module MODULE2 ( VAR90, VAR25, VAR44, VAR84, VAR36, VAR34, VAR16, VAR42, VAR86,
VAR58, VAR1, VAR33, VAR23, VAR100,
VAR95, VAR52, VAR14, VAR17, VAR5, VAR64, VAR60, VAR15, VAR8, VAR50 );
input VAR90;
input VAR25;
input VAR44;
input VAR84; input VAR36;
input VAR34,VAR16;
input VAR42;
input VAR86;
input VAR58;
input VAR1,VAR33;
input VAR23;
input VAR100;
output reg VAR95,VAR52;
output VAR14;
output VAR17;
output VAR5;
output VAR64;
output VAR60;
output VAR15;
output reg VAR8,VAR50;
reg [3:0] VAR89;
reg VAR72;
reg VAR65;
reg VAR54;
wire VAR70;
wire VAR69;
wire VAR27;
wire VAR78;
assign VAR27 = VAR16 | VAR54;
always @( VAR42 or VAR100 or VAR44 or VAR70 or VAR34 or VAR27 or VAR95 or VAR86 ) casex ({VAR42,VAR100,VAR44,VAR70,VAR34,VAR27,VAR95,VAR86})
8'VAR43 : VAR89 = 4'b0100; 8'VAR101 : VAR89 = 4'b0001;
8'VAR3 : VAR89 = 4'b1010; default : VAR89 = 4'b0;
endcase
assign VAR14 = VAR89[0]; assign VAR69 = VAR89[1];
assign VAR17 = VAR89[2]; assign VAR78 = VAR89[3];
assign VAR64 = VAR34 & VAR16;
always @(posedge VAR90 or negedge VAR25)
if (!VAR25) VAR65 <= 1'b0;
else VAR65 <= (VAR78 & ~VAR54) | (VAR65 & ~VAR84);
assign VAR60 = VAR65 & VAR58 & VAR84;
always @(posedge VAR90) VAR54 <= VAR65 & VAR84;
assign VAR15 = VAR54;
always @(posedge VAR90) if (VAR69) VAR95 <= 1'b1;
else
VAR95 <= VAR95 & ~VAR84 & VAR25;
always @(posedge VAR90)
begin
end
if (VAR14) VAR52 <= VAR42; else VAR52 <= VAR52 & ~VAR36 & VAR25;
end
assign VAR70 = VAR52 | VAR72;
always @(posedge VAR90) VAR72 <= VAR42 & VAR36;
assign VAR5 = VAR44 ? VAR72 : (VAR42 & VAR34 & VAR27);
always @(posedge VAR90) VAR8 <= VAR1; always @(posedge VAR90) if (VAR1) VAR50 <= VAR33;
endmodule | gpl-3.0 |
mithro/HDMI2USB | hdl/hdmi/chnlbond.v | 5,717 | module MODULE1 (
input wire clk,
input wire [9:0] VAR16,
input wire VAR31,
input wire VAR35,
input wire VAR23,
input wire VAR4,
input wire VAR32,
output reg VAR6,
output reg [9:0] VAR11
);
parameter VAR5 = 10'b1101010100;
parameter VAR25 = 10'b0010101011;
parameter VAR20 = 10'b0101010100;
parameter VAR7 = 10'b1010101011;
wire VAR14;
assign VAR14 = VAR35 & VAR23 & VAR31;
reg [3:0] VAR21, VAR30;
reg VAR26;
always @ (posedge clk) begin
VAR26 <=VAR14;
end
always @ (posedge clk) begin
if(VAR14)
VAR21 <=VAR21 + 1'b1;
end
else
VAR21 <=4'h0;
end
wire [9:0] VAR29;
VAR13 #(.VAR15(10))
VAR27 (
.VAR2(VAR16),
.VAR12(VAR21),
.VAR28(VAR30),
.VAR8(VAR26),
.VAR17(clk),
.VAR33(),
.VAR18(VAR29));
always @ (posedge clk) begin
VAR11 <=VAR29;
end
reg VAR24, VAR10; reg VAR1; always @ (posedge clk) begin
VAR24 <=((VAR11 == VAR5) || (VAR11 == VAR25) || (VAR11 == VAR20) || (VAR11 == VAR7));
VAR10 <=VAR24;
VAR1 <=!VAR10 & VAR24;
end
wire VAR3;
reg VAR9;
always @ (posedge clk) begin
if(!VAR14)
VAR9 <=1'b0;
end
else if(VAR1)
VAR9 <=1'b1;
end
assign VAR3 = VAR9 & VAR1;
always @ (posedge clk) begin
if(!VAR14)
VAR6 <=1'b0;
end
else if(VAR3)
VAR6 <=1'b1;
end
reg VAR34;
reg VAR19;
always @ (posedge clk) begin
VAR34 <=VAR14;
VAR19 <=VAR14 & !VAR34;
end
reg VAR22 = 1'b0;
always @ (posedge clk) begin
if(VAR19 || (VAR4 & VAR32 & VAR6))
VAR22 <=1'b1;
end
else if(VAR3 && !(VAR4 & VAR32 & VAR6))
VAR22 <=1'b0;
end
always @ (posedge clk) begin
if(!VAR14)
VAR30 <=4'h0;
end
else if(VAR22)
VAR30 <=VAR30 + 1'b1;
end
endmodule | bsd-2-clause |
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