repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_rxcounters.v | 8,423 | module MODULE1 (VAR18, VAR23, VAR3, VAR15, VAR35, VAR29, VAR1, VAR11,
VAR20, VAR22, VAR36, VAR26, VAR19, VAR4, VAR17, VAR14,
VAR32, VAR37, VAR21,VAR13,VAR10,VAR12, VAR2,
VAR28, VAR16, VAR31, VAR24, VAR34
);
parameter VAR27 = 1;
input VAR18;
input VAR23;
input VAR3;
input VAR35;
input [1:0] VAR29;
input VAR20;
input VAR15;
input VAR1;
input VAR22;
input VAR11;
input VAR26;
input VAR17;
input [15:0] VAR19;
input VAR4;
output VAR14; output [3:0] VAR36; output VAR32; output VAR37; output VAR21; output VAR13; output VAR10; output VAR12; output VAR2; output VAR28; output VAR16; output VAR31; output VAR24; output [15:0] VAR34;
wire VAR5;
wire VAR30;
wire VAR6;
wire VAR7;
wire VAR33;
reg [15:0] VAR8;
reg [3:0] VAR36;
reg [4:0] VAR25;
wire [15:0] VAR9;
assign VAR5 = VAR3 & (VAR35 & VAR20 | VAR29[0] & VAR24);
assign VAR30 = ~VAR5 & VAR3 &
(VAR11 | VAR35 | VAR15 & ~VAR26 |
VAR29[1] & ~VAR33 & ~(VAR22 & |VAR36)
);
always @ (posedge VAR18 or posedge VAR23)
begin
if(VAR23)
VAR8[15:0] <= #VAR27 16'h0;
end
else
begin
if(VAR5)
VAR8[15:0] <= #VAR27 16'h0;
end
else
if(VAR30)
VAR8[15:0] <= #VAR27 VAR8[15:0] + 1'b1;
end
end
assign VAR9 = VAR8 + 3'h4;
assign VAR34 = VAR22? VAR9 : VAR8;
assign VAR32 = VAR8 == 16'h0;
assign VAR37 = VAR8 == 16'h1;
assign VAR21 = VAR8 == 16'h2;
assign VAR13 = VAR8 == 16'h3;
assign VAR10 = VAR8 == 16'h4;
assign VAR12 = VAR8 == 16'h5;
assign VAR2 = VAR8 == 16'h6;
assign VAR28 = VAR8 == 16'h7;
assign VAR16 = VAR8 > 16'h2;
assign VAR31 = VAR8 < 16'h7;
assign VAR33 = VAR8 == 16'hffff;
assign VAR24 = VAR8 == VAR19[15:0] & ~VAR17;
assign VAR6 = VAR35 & VAR3 & VAR20 | VAR1;
assign VAR7 = ~VAR6 & (VAR1 | VAR15 | VAR11 | VAR35) & ~VAR14;
always @ (posedge VAR18 or posedge VAR23)
begin
if(VAR23)
VAR25[4:0] <= #VAR27 5'h0;
end
else
begin
if(VAR6)
VAR25[4:0] <= #VAR27 5'h0;
end
else
if(VAR7)
VAR25[4:0] <= #VAR27 VAR25[4:0] + 1'b1;
end
end
assign VAR14 = (VAR25[4:0] == 5'h18) | VAR4;
always @ (posedge VAR18 or posedge VAR23)
begin
if(VAR23)
VAR36[3:0] <= #VAR27 4'h0;
end
else
begin
if(VAR36[3:0] == 4'h9)
VAR36[3:0] <= #VAR27 4'h0;
end
else
if(VAR22 & VAR35)
VAR36[3:0] <= #VAR27 4'h1;
else
if(VAR22 & (|VAR36[3:0]))
VAR36[3:0] <= #VAR27 VAR36[3:0] + 1'b1;
end
end
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbp/sky130_fd_sc_lp__dfbbp.symbol.v | 1,467 | module MODULE1 (
input VAR8 ,
output VAR4 ,
output VAR5 ,
input VAR9,
input VAR7 ,
input VAR6
);
supply1 VAR1;
supply0 VAR10;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/edfxbp/sky130_fd_sc_lp__edfxbp.pp.symbol.v | 1,447 | module MODULE1 (
input VAR3 ,
output VAR9 ,
output VAR5 ,
input VAR8 ,
input VAR1 ,
input VAR7 ,
input VAR2,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp.behavioral.pp.v | 2,334 | module MODULE1 (
VAR16 ,
VAR21,
VAR13 ,
VAR18 ,
VAR19 ,
VAR4 ,
VAR2 ,
VAR8
);
output VAR16 ;
input VAR21;
input VAR13 ;
input VAR18 ;
input VAR19 ;
input VAR4 ;
input VAR2 ;
input VAR8 ;
wire VAR15 ;
reg VAR12 ;
wire VAR10 ;
wire VAR14 ;
wire VAR17 ;
wire VAR20;
wire VAR11 ;
wire VAR7 ;
wire VAR5 ;
wire VAR1 ;
not VAR9 (VAR15 , VAR20 );
VAR3 VAR22 (VAR11 , VAR10, VAR14, VAR15, VAR12, VAR19, VAR4);
assign VAR7 = ( VAR19 === 1'b1 );
assign VAR5 = ( VAR7 && ( VAR20 === 1'b1 ) );
assign VAR1 = ( VAR7 && ( VAR21 === 1'b1 ) );
buf VAR6 (VAR16 , VAR11 );
endmodule | apache-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_one_db_load/solution1/impl/verilog/contact_discoverybkb.v | 1,801 | module MODULE1 (VAR8, VAR6, VAR4, VAR3, VAR10, VAR12, VAR9, VAR11, clk);
parameter VAR7 = 8;
parameter VAR5 = 13;
parameter VAR1 = 8192;
input[VAR5-1:0] VAR8;
input VAR6;
input[VAR7-1:0] VAR4;
input VAR3;
output reg[VAR7-1:0] VAR10;
input[VAR5-1:0] VAR12;
input VAR9;
output reg[VAR7-1:0] VAR11;
input clk;
reg [VAR7-1:0] VAR2[0:VAR1-1];
begin
begin
begin
end
begin
begin | gpl-3.0 |
tvelliott/dsp_ice | firmware/fpga/src/fpga_top.v | 30,044 | module MODULE1 (
input clk,
output VAR38,
output VAR220,
output VAR10,
output VAR62,
output VAR148,
output VAR208,
output VAR156,
input VAR75,
output VAR31,
input VAR224,
input VAR49,
output VAR40,
input VAR203,
output VAR152,
output VAR216,
input VAR26,
input VAR200,
input VAR53,
input VAR240,
input VAR32,
input VAR83,
input VAR141,
input VAR201,
input VAR93,
input VAR12,
input VAR173,
input VAR118,
output VAR144,
input VAR50,
input VAR154,
input VAR101,
input VAR17,
output VAR36,
input VAR25,
input VAR44,
output VAR163,
input VAR212,
output VAR66,
output VAR147,
input VAR241,
input VAR130,
input VAR18,
input VAR129,
input VAR157,
input VAR233,
input VAR195,
input VAR217,
input VAR137,
input VAR42,
input VAR114,
input VAR37,
input VAR149,
input VAR15,
input VAR81,
input VAR92,
input VAR19,
input VAR160,
input VAR227,
input VAR21,
input VAR225,
input VAR16,
input VAR6,
input VAR229,
input VAR191,
input VAR4,
input VAR2,
inout VAR161,
inout VAR94,
inout VAR151,
inout VAR150,
inout VAR205,
inout VAR169,
inout VAR175,
inout VAR174,
inout VAR143,
inout VAR24,
inout VAR107,
inout VAR165,
inout VAR84,
inout VAR166,
inout VAR179,
inout VAR99,
input VAR71,
input VAR120,
input VAR45,
output VAR219,
input VAR9,
input VAR39,
input VAR3,
input VAR105,
input VAR188,
input VAR237
);
reg VAR51;
assign VAR51 = VAR75;
reg VAR104;
assign VAR104 = VAR9;
assign VAR38 = !VAR9;
reg VAR145;
reg VAR68;
VAR112 VAR207 (
.VAR181(clk),
.VAR164(VAR145)
);
reg [15:0] VAR90;
reg [15:0] VAR59;
wire VAR136;
wire VAR238;
wire VAR30;
wire VAR159;
wire VAR198;
wire VAR221;
reg VAR124;
reg [7:0] VAR138;
wire [7:0] VAR113;
wire VAR23;
wire VAR170;
reg VAR185;
VAR115 VAR56 (
.clk(VAR145),
.rst(VAR124),
.VAR140(VAR136),
.VAR184(VAR30),
.VAR218(VAR238),
.VAR55(VAR185),
.VAR54(VAR138),
.VAR196(VAR113),
.VAR202(VAR23),
.VAR122(VAR170)
);
reg [15:0] VAR106;
reg [15:0] VAR1;
wire VAR210;
wire VAR177;
wire VAR142;
wire VAR235;
wire VAR110;
wire VAR121;
reg VAR70;
reg [7:0] VAR214;
wire [7:0] VAR132;
wire VAR77;
wire VAR61;
reg VAR85;
VAR115 VAR100 (
.clk(VAR145),
.rst(VAR70),
.VAR140(VAR210),
.VAR184(VAR142),
.VAR218(VAR177),
.VAR55(VAR85),
.VAR54(VAR214),
.VAR196(VAR132),
.VAR202(VAR77),
.VAR122(VAR61)
);
localparam VAR116 = 16; localparam VAR172 = 8192;
reg [VAR116-1:0] VAR197=VAR172;
reg [VAR116-1:0] VAR167=0;
reg [31:0] VAR171=0;
wire [VAR116-1:0] VAR103;
wire [VAR116-1:0] VAR65;
VAR139 VAR64 (
.VAR230(VAR145),
.VAR41(VAR103),
.VAR215(VAR65),
.VAR194(VAR197),
.VAR162(VAR167),
.VAR171(VAR171)
);
reg [15:0] VAR46;
reg VAR183;
reg signed [15:0] VAR133;
reg signed [15:0] VAR34;
reg signed [15:0] VAR228;
reg signed [15:0] VAR74;
reg signed [15:0] VAR7;
reg signed [15:0] VAR58;
reg signed [15:0] VAR8;
reg signed [15:0] VAR155;
reg signed [20:0] VAR87;
reg signed [20:0] VAR29;
reg [31:0] VAR63;
reg [31:0] VAR11;
reg [31:0] VAR226;
reg [31:0] VAR78;
reg [31:0] VAR111;
reg [31:0] VAR82;
reg [31:0] VAR43;
reg [31:0] VAR88;
reg [3:0] VAR204;
reg [15:0] VAR28=0;
reg [15:0] VAR182=0;
reg [15:0] VAR52=0;
reg [15:0] VAR117=0;
reg [15:0] VAR109=0;
reg [15:0] VAR128=0;
reg [15:0] VAR178=0;
reg [15:0] VAR119=0; reg [15:0] VAR123=0;
reg [15:0] VAR72=0;
reg [15:0] VAR5=16'h0000;
reg VAR95=0;
wire VAR239;
assign VAR239 = VAR213[1];
reg [2:0] VAR80;
reg signed [15:0] VAR206=0; reg signed [15:0] VAR234=0;
reg [12:0] VAR153=13'h000;
reg [15:0] VAR102;
reg [15:0] VAR135=0;
reg signed [15:0] VAR189 = 16'h0000;
reg signed [15:0] VAR127 = 16'h0000;
reg VAR146; reg [3:0] VAR97;
reg signed [15:0] VAR27;
reg [3:0] VAR222;
reg VAR67; reg VAR125; reg VAR131;
reg signed [20:0] VAR87;
reg signed [20:0] VAR29;
reg signed [15:0] VAR186;
reg signed [15:0] VAR79;
reg signed [15:0] VAR213=0;
reg VAR95;
assign VAR95 = VAR213[0];
localparam VAR199=3;
reg [VAR199-1:0] VAR232;
reg [VAR199-1:0] VAR89;
wire VAR60;
assign VAR60 = (VAR222==4'd1);
reg [15:0] VAR102;
reg [15:0] VAR135;
reg [15:0] VAR98;
reg [12:0] VAR153;
reg [12:0] VAR223;
VAR211 delay(
.clk(VAR145), .VAR60(VAR60),
.addr(VAR153[12:0]),
.VAR135(VAR98),
.VAR102(VAR102)
);
localparam VAR236 = 3;
localparam VAR33 = 24;
reg [VAR236+VAR33-1:0] counter = 1;
reg [VAR236-1:0] VAR190;
wire [15:0] addr;
wire [15:0] VAR180;
reg [15:0] VAR48;
reg [15:0] VAR54;
reg [15:0] VAR76;
wire VAR57;
wire VAR231;
wire VAR69; reg VAR86; wire VAR134;
wire VAR126;
wire VAR108;
wire VAR187;
wire VAR35;
wire VAR13;
wire [11:0] VAR47;
reg [15:0] VAR209;
wire VAR22;
VAR73 #(
.VAR14(6'VAR158 101001),
.VAR193(1'VAR158 0)
) VAR176 [15:0] (
.VAR168({VAR99,VAR179,VAR166,VAR84,VAR165,VAR107,VAR24,VAR143,VAR174,VAR175,VAR169,VAR205,VAR150,VAR151,VAR94,VAR161}),
.VAR96(!VAR57),
.VAR91(VAR48),
.VAR20(VAR180)
);
always @(posedge VAR104 && !VAR69) begin
VAR232 <= VAR232<<1;
if(!VAR134) begin
VAR76 <= VAR180<<1; VAR223 <= VAR180<<1;
end
else if(!VAR57) begin
case(VAR76[15:8])
8'h00: begin
case(VAR76[7:0])
8'h00: begin
VAR48 <= VAR90;
end
8'h02: begin
VAR48 <= VAR138;
end
8'h04: begin
VAR48 <= VAR113; end
8'h06: begin
VAR48 <= VAR59;
end
8'h08: begin
VAR48 <= VAR106;
end
8'h0a: begin
VAR48 <= VAR214;
end
8'h0c: begin
VAR48 <= VAR132; end
8'h0e: begin
VAR48 <= VAR1;
end
8'h10: begin
VAR48 <= VAR209;
end
default : begin
VAR48 <= 16'h0000;
end
endcase
end
8'h10: begin
case(VAR76[7:0])
8'h00: begin
VAR48 <= VAR213;
end
8'h02: begin
VAR48 <= VAR186;
end
8'h04: begin
VAR48 <= VAR79;
end
8'h06: begin
VAR48 <= VAR28;
end
8'h08: begin
VAR48 <= VAR182;
end
8'h0a: begin
VAR48 <= VAR52;
end
8'h0c: begin
VAR48 <= VAR117;
end
8'h0e: begin
VAR48 <= VAR109;
end
8'h10: begin
VAR48 <= VAR128;
end
8'h12: begin
VAR48 <= VAR178;
end
8'h14: begin
VAR48 <= VAR123;
end
8'h16: begin
VAR48 <= VAR72;
end
default : begin
VAR48 <= 16'h0000;
end
endcase
end
8'hd0: begin
VAR48 <= VAR102;
end
8'he0: begin
VAR48 <= VAR102;
end
8'hf0: begin
case(VAR76[7:0])
8'h00: begin
VAR48 <= VAR46; end
default : begin
VAR48 <= 16'h0000;
end
endcase
end
default : begin
VAR48 <= 16'h0000;
end
endcase
end
else if(!VAR231) begin
case(VAR76[15:8])
8'h00: begin
case(VAR76[7:0])
8'h00: begin
{VAR90[15:3],VAR90[0]} <= {VAR180[15:3],VAR180[0]};
end
8'h02: begin
VAR138 <= VAR180;
end
8'h04: begin
end
8'h06: begin
VAR59 <= VAR180;
end
8'h08: begin
{VAR106[15:3],VAR106[0]} <= {VAR180[15:3],VAR180[0]};
end
8'h0a: begin
VAR214 <= VAR180;
end
8'h0c: begin
end
8'h0e: begin
VAR1 <= VAR180;
end
endcase
end
8'h10: begin
case(VAR76[7:0])
8'h00: begin
VAR213 <= VAR180;
end
8'h02: begin
VAR186 <= VAR180;
end
8'h04: begin
VAR79 <= VAR180;
end
8'h06: begin
VAR28 <= VAR180;
end
8'h08: begin
VAR182 <= VAR180;
end
8'h0a: begin
VAR52 <= VAR180;
end
8'h0c: begin
VAR117 <= VAR180;
end
8'h0e: begin
VAR109 <= VAR180;
end
8'h10: begin
VAR128 <= VAR180;
end
8'h12: begin
VAR178 <= VAR180;
end
8'h14: begin
VAR123 <= VAR180;
end
8'h16: begin
VAR72 <= VAR180;
end
endcase
end
8'hd0: begin
VAR135 <= VAR180;
VAR232[VAR199-1:0] <= {VAR199{1'b1}};
end
8'he0: begin
VAR135 <= VAR180;
VAR232[VAR199-1:0] <= {VAR199{1'b1}};
end
default: begin
end
endcase
end
end
always @(posedge VAR145) begin
if(!VAR51) begin
end else begin
VAR90[1] <= VAR23;
VAR90[2] <= VAR170;
VAR185 <= VAR90[0];
VAR106[1] <= VAR77;
VAR106[2] <= VAR61;
VAR85 <= VAR106[0];
counter <= counter + 1;
VAR13 <= counter[2];
if( counter[2:0]==3'b110 && VAR69) begin
VAR209 <= VAR47*16;
end
if( counter%16==0 ) begin
VAR190 <= counter >> VAR33;
end else begin
VAR190 <= 0;
end
VAR204 <= VAR204+1;
case(VAR204)
4'b0000:
begin
if(VAR95==1'b1) begin
VAR87 <= VAR206*16;
VAR29 <= VAR234*16;
end else begin
VAR87 <= (VAR133 + VAR228 + VAR7 + VAR8 + VAR189*16 );
VAR29 <= (VAR34 + VAR74 + VAR58 + VAR155 + VAR127*16 );
end
end
4'b0001:
begin
VAR63 <= VAR63 + (18'h35*VAR28*16);
case(VAR72[1:0])
2'b00:
begin
VAR133 <= VAR103; VAR192
end
2'b01:
begin
VAR133 <= VAR63[31:16]; end
2'b10:
begin
if(VAR63[31]) begin
VAR133 <= 16'h7fff; end else begin
VAR133 <= 16'h8000; end
end
2'b11:
begin
if(VAR28!=16'h0000) begin
VAR133 <= VAR46; end else begin
VAR133 <= 16'h0000;
end
end
endcase
end
4'b0010:
begin
VAR171 <= VAR11;
end
4'b0011:
begin
VAR11 <= VAR11 + (18'h35*VAR182*16);
case(VAR72[3:2])
2'b00:
begin
VAR34 <= VAR103; VAR192
end
2'b01:
begin
VAR34 <= VAR11[31:16]; end
2'b10:
begin
if(VAR11[31]) begin
VAR34 <= 16'h7fff; end else begin
VAR34 <= 16'h8000;
end
end
2'b11:
begin
if(VAR182!=16'h0000) begin
VAR34 <= VAR46; end else begin
VAR34 <= 16'h0000;
end
end
endcase
end
4'b0100:
begin
VAR171 <= VAR226;
end
4'b0101:
begin
VAR226 <= VAR226 + (18'h35*VAR52*16);
case(VAR72[5:4])
2'b00:
begin
VAR228 <= VAR103; VAR192
end
2'b01:
begin
VAR228 <= VAR226[31:16]; end
2'b10:
begin
if(VAR226[31]) begin
VAR228 <= 16'h7fff; end else begin
VAR228 <= 16'h8000;
end
end
2'b11:
begin
if(VAR52!=16'h0000) begin
VAR228 <= VAR46; end else begin
VAR228 <= 16'h0000;
end
end
endcase
end
4'b0110:
begin
VAR171 <= VAR78;
end
4'b0111:
begin
VAR78 <= VAR78 + (18'h35*VAR117*16);
case(VAR72[7:6])
2'b00:
begin
VAR74 <= VAR103; VAR192
end
2'b01:
begin
VAR74 <= VAR78[31:16]; end
2'b10:
begin
if(VAR78[31]) begin
VAR74 <= 16'h7fff; end else begin
VAR74 <= 16'h8000;
end
end
2'b11:
begin
if(VAR117!=16'h0000) begin
VAR74 <= VAR46; end else begin
VAR74 <= 16'h0000;
end
end
endcase
end
4'b1000:
begin
VAR171 <= VAR111;
end
4'b1001:
begin
VAR111 <= VAR111 + (18'h35*VAR109*16);
case(VAR72[9:8])
2'b00:
begin
VAR7 <= VAR103; VAR192
end
2'b01:
begin
VAR7 <= VAR111[31:16]; end
2'b10:
begin
if(VAR111[31]) begin
VAR7 <= 16'h7fff; end else begin
VAR7 <= 16'h8000;
end
end
2'b11:
begin
if(VAR109!=16'h0000) begin
VAR7 <= VAR46; end else begin
VAR7 <= 16'h0000;
end
end
endcase
end
4'b1010:
begin
VAR171 <= VAR82;
end
4'b1011:
begin
VAR82 <= VAR82 + (18'h35*VAR128*16);
case(VAR72[11:10])
2'b00:
begin
VAR58 <= VAR103; VAR192
end
2'b01:
begin
VAR58 <= VAR82[31:16]; end
2'b10:
begin
if(VAR82[31]) begin
VAR58 <= 16'h7fff; end else begin
VAR58 <= 16'h8000;
end
end
2'b11:
begin
if(VAR128!=16'h0000) begin
VAR58 <= VAR46; end else begin
VAR58 <= 16'h0000;
end
end
endcase
end
4'b1100:
begin
VAR171 <= VAR43;
end
4'b1101:
begin
VAR43 <= VAR43 + (18'h35*VAR178*16);
case(VAR72[13:12])
2'b00:
begin
VAR8 <= VAR103; VAR192
end
2'b01:
begin
VAR8 <= VAR43[31:16]; end
2'b10:
begin
if(VAR43[31]) begin
VAR8 <= 16'h7fff; end else begin
VAR8 <= 16'h8000;
end
end
2'b11:
begin
if(VAR178!=16'h0000) begin
VAR8 <= VAR46; end else begin
VAR8 <= 16'h0000;
end
end
endcase
end
4'b1110:
begin
VAR171 <= VAR88;
end
4'b1111:
begin
VAR88 <= VAR88 + (18'h35*VAR123*16);
VAR171 <= VAR63;
case(VAR72[15:14])
2'b00:
begin
VAR155 <= VAR103; VAR192
end
2'b01:
begin
VAR155 <= VAR88[31:16]; end
2'b10:
begin
if(VAR88[31]) begin
VAR155 <= 16'h7fff; end else begin
VAR155 <= 16'h8000;
end
end
2'b11:
begin
if(VAR123!=16'h0000) begin
VAR155 <= VAR46; end else begin
VAR155 <= 16'h0000;
end
end
endcase
end
endcase
VAR146 <= ~VAR146;
if(counter[10]==0) begin
VAR183 <= !(VAR46[15]^VAR46[3]);
VAR46 <= { VAR46[14:0], VAR183 };
end
VAR97 <= VAR97+1;
VAR98 <= { VAR87[20:13], VAR29[20:13] };
if(VAR95==1'b1) begin
VAR87 <= VAR186*16;
VAR29 <= VAR79*16;
end
if( VAR97==0 ) begin
VAR125 <= ~VAR125;
if(VAR125) begin
if(VAR222==4'd2) begin
VAR80 <= VAR80+1;
if(VAR80==0) begin
VAR153 <= VAR153+1;
end
end
if(VAR222==4'd4) begin
if(VAR95) begin
VAR86 <= VAR131; end
if(VAR239==1'b1 ) begin
VAR189[15:8] <= VAR102[15:8];
VAR127[15:8] <= VAR102[7:0];
end else begin
VAR189[15:0] <= 16'h0000;
VAR127[15:0] <= 16'h0000;
end
end
if(VAR222==4'd0) begin VAR131 <= ~VAR131;
if(VAR131) begin
VAR27 <= (VAR87)>>5 ;
end else begin
VAR27 <= (VAR29)>>5;
end
end
VAR67 <= VAR27[15-VAR222];
VAR222 <= VAR222+1;
end
end
end
end
assign {VAR220, VAR10} = ~VAR190;
assign VAR156 = VAR146;
assign VAR62 = VAR67;
assign VAR148 = VAR125;
assign VAR208 = VAR131;
assign VAR71 = VAR57;
assign VAR120 = VAR231;
assign VAR45 = VAR69;
assign VAR219 = VAR86;
assign VAR39 = VAR134;
assign VAR3 = VAR126;
assign VAR105 = VAR187;
assign VAR188 = VAR108;
assign VAR237 = VAR35;
assign VAR31 = VAR124;
assign VAR224 = VAR198;
assign VAR136 = VAR49;
assign VAR40 = !VAR59[0]; assign VAR26 = VAR159;
assign VAR216 = VAR238;
assign VAR152 = VAR30;
assign VAR203 = VAR221;
assign VAR36 = VAR70;
assign VAR25 = VAR110;
assign VAR210 = VAR44;
assign VAR163 = !VAR1[0]; assign VAR241 = VAR235;
assign VAR147 = VAR177;
assign VAR66 = VAR142;
assign VAR212 = VAR121;
assign VAR124 = VAR51;
assign VAR70 = VAR51;
assign VAR13 = VAR144;
assign VAR22 = VAR17;
assign VAR47 = { VAR141, VAR53, VAR201, VAR240, VAR93, VAR32, VAR12, VAR50, VAR173, VAR154, VAR118, VAR101 };
endmodule | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_p_src_rows_V_channel.v | 3,019 | module MODULE1 (
clk,
VAR12,
VAR27,
VAR24,
VAR13);
parameter VAR23 = 32'd12;
parameter VAR6 = 32'd2;
parameter VAR5 = 32'd3;
input clk;
input [VAR23-1:0] VAR12;
input VAR27;
input [VAR6-1:0] VAR24;
output [VAR23-1:0] VAR13;
reg[VAR23-1:0] VAR18 [0:VAR5-1];
integer VAR21;
always @ (posedge clk)
begin
if (VAR27)
begin
for (VAR21=0;VAR21<VAR5-1;VAR21=VAR21+1)
VAR18[VAR21+1] <= VAR18[VAR21];
VAR18[0] <= VAR12;
end
end
assign VAR13 = VAR18[VAR24];
endmodule
module MODULE2 (
clk,
reset,
VAR14,
VAR9,
VAR25,
VAR26,
VAR15,
VAR2,
VAR11,
VAR7);
parameter VAR22 = "VAR17";
parameter VAR23 = 32'd12;
parameter VAR6 = 32'd2;
parameter VAR5 = 32'd3;
input clk;
input reset;
output VAR14;
input VAR9;
input VAR25;
output[VAR23 - 1:0] VAR26;
output VAR15;
input VAR2;
input VAR11;
input[VAR23 - 1:0] VAR7;
wire[VAR6 - 1:0] VAR16 ;
wire[VAR23 - 1:0] VAR3, VAR10;
reg[VAR6:0] VAR20 = {(VAR6+1){1'b1}};
reg VAR8 = 0, VAR1 = 1;
assign VAR14 = VAR8;
assign VAR15 = VAR1;
assign VAR3 = VAR7;
assign VAR26 = VAR10;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR20 <= ~{VAR6+1{1'b0}};
VAR8 <= 1'b0;
VAR1 <= 1'b1;
end
else begin
if (((VAR25 & VAR9) == 1 & VAR8 == 1) &&
((VAR11 & VAR2) == 0 | VAR1 == 0))
begin
VAR20 <= VAR20 -1;
if (VAR20 == 0)
VAR8 <= 1'b0;
VAR1 <= 1'b1;
end
else if (((VAR25 & VAR9) == 0 | VAR8 == 0) &&
((VAR11 & VAR2) == 1 & VAR1 == 1))
begin
VAR20 <= VAR20 +1;
VAR8 <= 1'b1;
if (VAR20 == VAR5-2)
VAR1 <= 1'b0;
end
end
end
assign VAR16 = VAR20[VAR6] == 1'b0 ? VAR20[VAR6-1:0]:{VAR6{1'b0}};
assign VAR4 = (VAR11 & VAR2) & VAR1;
MODULE1
.VAR23(VAR23),
.VAR6(VAR6),
.VAR5(VAR5))
VAR19 (
.clk(clk),
.VAR12(VAR3),
.VAR27(VAR4),
.VAR24(VAR16),
.VAR13(VAR10));
endmodule | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_wb.v | 10,015 | module MODULE1( VAR11, VAR14, rst, VAR6, VAR17, VAR7,
VAR3, VAR31, VAR27, VAR20,
VAR8, VAR22, VAR34, VAR12, VAR19, VAR2,
VAR29, VAR35, VAR13, VAR28);
input VAR11, VAR14;
input rst;
input [VAR9:0] VAR6;
input [31:0] VAR17;
output [31:0] VAR7;
output VAR3;
input VAR31;
input VAR27;
input VAR20;
output [VAR9:0] VAR8;
output [31:0] VAR22;
input [31:0] VAR34;
output VAR12;
output VAR19;
input VAR2;
output VAR29;
output VAR35;
input [31:0] VAR13;
output [31:0] VAR28;
parameter [5:0] VAR10 = 6'b000001,
VAR16 = 6'b000010,
VAR4 = 6'b000100,
VAR33 = 6'b001000,
VAR15 = 6'b010000,
VAR23 = 6'b100000;
reg [5:0] state, VAR18;
reg VAR25;
reg VAR24, VAR30, VAR21, VAR32;
reg VAR12;
reg VAR29, VAR1;
reg VAR19;
reg VAR3;
reg [31:0] VAR7;
assign VAR8 = VAR6;
assign VAR22 = VAR17;
assign VAR28 = VAR17;
always @(posedge VAR11)
if( VAR5 ) VAR7 <= VAR13;
else VAR7 <= VAR34;
always @(posedge VAR14)
VAR25 <= VAR27 & VAR20;
always @(posedge VAR11)
VAR30 <= VAR24;
always @(posedge VAR11)
VAR3 <= VAR30 & !VAR32 & !VAR3;
always @(posedge VAR11)
VAR21 <= VAR30;
always @(posedge VAR11)
VAR32 <= VAR21;
assign VAR35 = VAR1;
always @(posedge VAR14 or negedge rst)
always @(posedge VAR14)
if(rst) state <= VAR10;
else state <= VAR18;
always @(state or VAR25 or VAR6 or VAR2 or VAR31)
begin
VAR18 = state;
VAR19 = 1'b0;
VAR12 = 1'b0;
VAR24 = 1'b0;
VAR29 = 1'b0;
VAR1 = 1'b0;
case(state) VAR10:
begin
if(VAR25 && VAR26 && VAR31)
begin
VAR19 = 1'b1;
VAR12 = 1'b1;
VAR18 = VAR16;
end
if(VAR25 && VAR26 && !VAR31)
begin
VAR19 = 1'b1;
VAR18 = VAR4;
end
if(VAR25 && VAR5 && VAR31)
begin
VAR1 = 1'b1;
VAR18 = VAR33;
end
if(VAR25 && VAR5 && !VAR31)
begin
VAR29 = 1'b1;
VAR18 = VAR33;
end
end
VAR16:
begin
if(!VAR2)
begin
VAR19 = 1'b1;
VAR12 = 1'b1;
end
else
begin
VAR24 = 1'b1;
VAR18 = VAR15;
end
end
VAR4:
begin
if(!VAR2)
begin
VAR19 = 1'b1;
end
else
begin
VAR24 = 1'b1;
VAR18 = VAR15;
end
end
VAR33:
begin
VAR24 = 1'b1;
VAR18 = VAR15;
end
VAR15:
begin
VAR18 = VAR23;
end
VAR23:
begin
VAR18 = VAR10;
end
endcase
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3.symbol.v | 1,322 | module MODULE1 (
input VAR4,
output VAR6
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv.behavioral.pp.v | 1,766 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1,
VAR6,
VAR10 ,
VAR2
);
output VAR4 ;
input VAR3 ;
input VAR1;
input VAR6;
input VAR10 ;
input VAR2 ;
wire VAR7 ;
wire VAR9;
not VAR5 (VAR7 , VAR3 );
VAR11 VAR8 (VAR9, VAR7, VAR1, VAR6);
buf VAR12 (VAR4 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb.pp.blackbox.v | 1,357 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR9 ,
VAR6 ,
VAR2 ,
VAR7,
VAR1,
VAR8 ,
VAR4
);
output VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR6 ;
input VAR2 ;
input VAR7;
input VAR1;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn.pp.blackbox.v | 1,478 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR8 ,
VAR3 ,
VAR5 ,
VAR9,
VAR4 ,
VAR7 ,
VAR2 ,
VAR10
);
output VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR3 ;
input VAR5 ;
input VAR9;
input VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR10 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.behavioral.pp.v | 1,246 | module MODULE1( VAR2, VAR5, VAR6, VAR4, VAR1 );
input VAR2, VAR5;
inout VAR4, VAR1;
output VAR6;
VAR7 VAR3(.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1));
VAR7 VAR8(.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b_1.v | 2,189 | module MODULE2 (
VAR6 ,
VAR3 ,
VAR7 ,
VAR8,
VAR4,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR8;
input VAR4;
input VAR1 ;
input VAR2 ;
VAR9 VAR5 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6 ,
VAR3 ,
VAR7
);
output VAR6 ;
input VAR3 ;
input VAR7;
supply1 VAR8;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR2 ;
VAR9 VAR5 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule | apache-2.0 |
ZiCog/xoro | rtl/uartTx.v | 4,133 | module MODULE2 (
input VAR9,
output VAR22,
input clk,
input VAR19);
reg VAR16;
assign VAR22 = (VAR9 && (! VAR16));
always @ (posedge clk or negedge VAR19) begin
if (!VAR19) begin
VAR16 <= 1'b0;
end else begin
VAR16 <= VAR9;
end
end
endmodule
module MODULE1 (
input wire clk,
input wire VAR19,
input wire VAR12,
output wire VAR13,
output wire VAR6
);
wire VAR1;
reg [3:0] VAR25;
MODULE2 VAR2(
.clk(clk),
.VAR19(VAR19),
.VAR9(VAR12),
.VAR22(VAR1)
);
MODULE2 VAR11(
.clk(clk),
.VAR19(VAR19),
.VAR9(VAR24),
.VAR22(VAR13)
);
assign VAR24 = VAR25[3];
assign VAR6 = VAR24;
always @ (posedge clk or negedge VAR19) begin
if (!VAR19) begin
VAR25 <= 7;
end else begin
if (VAR1) begin
VAR25 <= VAR25 - 1;
end
end
end
endmodule
module MODULE3 (
input wire clk,
input wire VAR19,
input wire enable,
input wire VAR17,
output wire VAR20,
input wire VAR21,
input wire [3:0] VAR5,
input wire [31:0] VAR8,
input wire [31:0] VAR3,
output wire [31:0] VAR10,
input wire VAR12,
output wire VAR6,
output reg VAR23 );
reg [7:0] VAR15;
reg [7:0] buffer;
reg [7:0] state;
reg [3:0] VAR4;
reg VAR7; reg VAR14;
wire VAR24;
MODULE1 VAR18(
.clk(clk),
.VAR19(VAR19),
.VAR12(VAR12),
.VAR13(VAR13),
.VAR6(VAR6)
);
always @ (posedge clk or negedge VAR19) begin
if (!VAR19) begin
state <= 0;
buffer <= 0;
VAR7 <= 1;
VAR15 <= 0;
VAR23 <= 1;
VAR4 <= 0;
VAR14 <= 0;
end else begin
if (VAR17 & enable) begin
if ((VAR5[0] == 1) && (VAR7 == 1)) begin
buffer <= VAR8[7:0];
VAR7 <= 0;
end
VAR14 <= 1;
end else begin
VAR14 <= 0;
end
if (VAR13) begin
case (state)
0 : begin
if (VAR7 == 0) begin
VAR15 <= buffer;
VAR7 <= 1;
VAR4 <= 8;
VAR23 <= 0;
state <= 1;
end
end
1 : begin
if (VAR4 > 0) begin
VAR23 <= VAR15[0];
VAR4 <= VAR4 - 4'd1;
VAR15 <= VAR15 >> 1;
end else begin
VAR23 <= 1;
state <= 2;
end
end
2 : begin
VAR23 <= 1;
state <= 0;
end
default : ;
endcase
end
end
end
assign VAR10 = enable ? VAR7 : 1'b0;
assign VAR20 = enable ? VAR14 : 1'b0;
endmodule | mit |
cfangmeier/VFPIX-telescope-Code | utils/apc128_pattern_generator/step_curve_short.v | 4,253 | module MODULE1
(
input clk,
input [15:0]VAR18,
output reg VAR26,
output VAR9,
output VAR13,
output VAR22,
output reg VAR16,
output VAR20,
output reg VAR12,
output reg VAR17,
output reg VAR15,
output reg VAR11,
output VAR25,
output VAR4,
output reg VAR2,
output reg VAR23,
output VAR21,
output [15:0]VAR3,
output [15:0]VAR19,
output [15:0]VAR14,
output [15:0]VAR7,
input VAR8
);
reg [31:0]counter;
reg [7:0]VAR5;
reg [15:0]VAR24;
assign VAR9=0;
assign VAR25=0;
assign VAR4=1;
assign VAR20=0;
assign VAR13=1;
assign VAR22=0;
assign VAR21=1;
assign VAR7=16'VAR10;
assign VAR3=16'VAR1;
assign VAR14=16'VAR6;
assign VAR19=16'VAR1;
always @(posedge clk) begin
if(VAR8 == 1) begin
counter <= 0;
VAR5 <= 0;
VAR24 <= 0;
end
else begin
if(VAR5 == 0) begin
if(counter == 0) begin
VAR26 <= 1;
VAR2 <= 0;
VAR23 <= 0;
VAR17 <= 0;
VAR12 <= 1;
VAR15 <= 1;
VAR11 <= 1;
VAR16 <= 1;
end
if(counter == 2) begin
VAR2 <= 1;
VAR23 <= 1;
end
if(counter == 5) begin
VAR2 <= 0;
VAR23 <= 0;
end
if(counter == 9) begin
if(VAR24 == 0) begin
VAR5 <= (VAR5 + 1) % 5;
VAR24 <= 0;
end
else begin
VAR24 <= VAR24 + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(VAR5 == 1) begin
if(counter == 0) begin
VAR26 <= 0;
VAR2 <= 0;
VAR23 <= 0;
VAR17 <= 0;
VAR12 <= 1;
VAR15 <= 1;
VAR11 <= 1;
VAR16 <= 1;
end
if(counter == 0) begin
if(VAR24 == VAR18-1) begin
VAR5 <= (VAR5 + 1) % 5;
VAR24 <= 0;
end
else begin
VAR24 <= VAR24 + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(VAR5 == 2) begin
if(counter == 0) begin
VAR26 <= 0;
VAR2 <= 0;
VAR23 <= 0;
VAR17 <= 0;
VAR12 <= 1;
VAR15 <= 1;
VAR11 <= 1;
VAR16 <= 0;
end
if(counter == 2) begin
VAR17 <= 1;
end
if(counter == 4) begin
VAR12 <= 0;
end
if(counter == 8) begin
VAR15 <= 0;
VAR11 <= 0;
end
if(counter == 11) begin
VAR12 <= 1;
VAR15 <= 1;
end
if(counter == 12) begin
VAR15 <= 0;
end
if(counter == 13) begin
VAR12 <= 0;
end
if(counter == 13) begin
if(VAR24 == 0) begin
VAR5 <= (VAR5 + 1) % 5;
VAR24 <= 0;
end
else begin
VAR24 <= VAR24 + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(VAR5 == 3) begin
if(counter == 0) begin
VAR26 <= 0;
VAR2 <= 0;
VAR23 <= 0;
VAR17 <= 1;
VAR12 <= 0;
VAR15 <= 0;
VAR11 <= 1;
VAR16 <= 1;
end
if(counter == 21) begin
VAR11 <= 0;
end
if(counter == 22) begin
VAR15 <= 1;
end
if(counter == 23) begin
VAR15 <= 0;
end
if(counter == 23) begin
if(VAR24 == 126) begin
VAR5 <= (VAR5 + 1) % 5;
VAR24 <= 0;
end
else begin
VAR24 <= VAR24 + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(VAR5 == 4) begin
if(counter == 0) begin
VAR26 <= 1;
VAR2 <= 0;
VAR23 <= 0;
VAR17 <= 1;
VAR12 <= 0;
VAR15 <= 0;
VAR11 <= 0;
VAR16 <= 1;
end
if(counter == 0) begin
if(VAR24 == 299) begin
VAR5 <= (VAR5 + 1) % 5;
VAR24 <= 0;
end
else begin
VAR24 <= VAR24 + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
end
end
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/source/endpoint_blk_plus_v1_14.v | 19,614 | module MODULE1 # (
parameter VAR100 = "VAR169",
parameter VAR32 = 0,
parameter VAR109 = 1,
parameter VAR168 = 1,
parameter VAR155 = 0,
parameter VAR121 = 64,
parameter VAR204 = 8,
parameter VAR149 = 4,
parameter VAR129 = 7,
parameter VAR50 = 8,
parameter VAR179 = 12,
parameter VAR95 = 32,
parameter VAR193 = 10,
parameter VAR191 = 48,
parameter VAR163 = 8,
parameter VAR134 = 5,
parameter VAR153 = 3,
parameter VAR78 = 16,
parameter VAR74 = 1024,
parameter VAR107 = 32'h000010EE,
parameter VAR59 = VAR107[15 : 0],
parameter VAR28 = 16'h4243,
parameter VAR145 = 8'h02,
parameter VAR148 = 24'h050000,
parameter VAR3 = 32'hFF000000,
parameter VAR183 = 32'hFFFF0000,
parameter VAR165 = 32'h00000000,
parameter VAR140 = 32'h00000000,
parameter VAR20 = 32'h00000000,
parameter VAR122 = 32'h00000000,
parameter VAR17 = 32'h00000000,
parameter VAR70 = 32'h000010EE,
parameter VAR136 = 32'h00000007,
parameter VAR42 = VAR70[15 : 0],
parameter VAR62 = VAR136[15 : 0],
parameter VAR102 = 32'hFFF00001,
parameter VAR38 = 5'b00000,
parameter VAR23 = 0,
parameter VAR60 = 4'b0000,
parameter VAR6 = 4'h1,
parameter VAR137 = 2'b00,
parameter VAR119 = 8'h00,
parameter VAR54 = 0,
parameter VAR39 = 0,
parameter VAR94 = 0,
parameter VAR33 = 3'b111,
parameter VAR57 = 3'b111,
parameter VAR141 = 1,
parameter VAR85 = 2'b01,
parameter VAR24 = 3'b010,
parameter VAR56 = 3'b111,
parameter VAR138 = 3'b111,
parameter VAR125 = 2'b01,
parameter VAR58 = 6'b1,
parameter VAR205 = 4'b1,
parameter VAR14 = 16'h0204,
parameter VAR11 = 16'h060d,
parameter VAR71 = 4'b0000,
parameter VAR43 = 0,
parameter VAR131 = 0,
parameter VAR2 = 0,
parameter VAR199 = 0,
parameter VAR1 = 0,
parameter VAR18 = 5'h0,
parameter VAR22 = 0,
parameter VAR77 = 0,
parameter VAR67 = 3'b000,
parameter VAR68 = 0,
parameter VAR98 = 0,
parameter VAR83 = 3'b010,
parameter VAR177 = 8'h0,
parameter VAR63 = 8'h0,
parameter VAR9 = 8'h0,
parameter VAR113 = 8'h0,
parameter VAR91 = 8'h0,
parameter VAR48 = 8'h0,
parameter VAR10 = 8'h0,
parameter VAR194 = 8'h0,
parameter VAR159 = 8'h0,
parameter VAR93 = 8'h0,
parameter VAR123 = 8'h0,
parameter VAR80 = 8'h0,
parameter VAR154 = 8'h0,
parameter VAR87 = 8'h0,
parameter VAR30 = 8'h0,
parameter VAR120 = 8'h0,
parameter VAR69 = 0,
parameter VAR35 = 0,
parameter VAR184 = "VAR203",
parameter VAR158 = 8,
parameter VAR51 = 8,
parameter VAR26 = 0,
parameter VAR7 = "VAR203",
parameter VAR116 = "VAR203",
parameter VAR105 = 3'b100,
parameter VAR103 = 3'b100,
parameter VAR115 = 3'b111,
parameter VAR124 = 0,
parameter VAR41 = 0
)
(
output [VAR109-1 : 0] VAR172,
output [VAR109-1 : 0] VAR151,
input [VAR109-1 : 0] VAR143,
input [VAR109-1 : 0] VAR180,
output VAR81,
output VAR36,
output VAR197,
input [VAR121-1 : 0] VAR117,
input [VAR204-1 : 0] VAR45,
input VAR12,
input VAR181,
input VAR196,
output VAR47,
output VAR173,
input VAR166,
input VAR139,
output [VAR149-1:0] VAR126,
output [VAR121-1 : 0] VAR133,
output [VAR204-1 : 0] VAR44,
output VAR178,
output VAR25,
output VAR135,
output VAR31,
input VAR29,
output VAR111,
input VAR92,
output [VAR129-1 : 0] VAR190,
output [VAR50-1 : 0] VAR157,
output [VAR179-1 : 0] VAR90,
output [VAR50-1 : 0] VAR40,
output [VAR179-1 : 0] VAR182,
input VAR96,
output [VAR95-1 : 0] VAR162,
output VAR192,
input [VAR95-1 : 0] VAR174,
input [VAR95/8-1 : 0] VAR128,
input [VAR193-1 : 0] VAR201,
input VAR188,
input VAR106,
input VAR156,
input VAR8,
input VAR72,
input VAR55,
input VAR118,
input VAR4,
input VAR132,
input [VAR191-1 : 0] VAR86,
output VAR200,
input VAR144,
input VAR66,
output VAR176,
input VAR53,
input [7 : 0] VAR198,
output [7 : 0] VAR61,
output [2 : 0] VAR19,
output VAR5,
output VAR171,
input VAR189,
output [2 : 0] VAR147,
input VAR73,
output [VAR163-1 : 0] VAR13,
output [VAR134-1 : 0] VAR34,
output [VAR153-1 : 0] VAR101,
input [63 : 0] VAR79,
output [VAR78-1 : 0] VAR202,
output [VAR78-1 : 0] VAR195,
output [VAR78-1 : 0] VAR21,
output [VAR78-1 : 0] VAR76,
output [VAR78-1 : 0] VAR89,
output [VAR78-1 : 0] VAR46,
input VAR15,
input VAR64,
output VAR114,
input VAR167
);
wire [1*16-1 : 0] VAR75;
wire [1-1 : 0] VAR112;
VAR187 #(
.VAR32 ( VAR32),
.VAR152 ( VAR168),
.VAR82 ( VAR155),
.VAR59 ( VAR59),
.VAR28 ( VAR28),
.VAR145 ( VAR145),
.VAR148 ( VAR148),
.VAR3 ( VAR3),
.VAR183 ( VAR183),
.VAR165 ( VAR165),
.VAR140 ( VAR140),
.VAR20 ( VAR20),
.VAR122 ( VAR122),
.VAR17 ( VAR17),
.VAR42 ( VAR42),
.VAR62 ( VAR62),
.VAR102 ( VAR102),
.VAR38 ( VAR38),
.VAR23 ( VAR23),
.VAR60 ( VAR60),
.VAR6 ( VAR6),
.VAR137 ( VAR137),
.VAR119 ( VAR119),
.VAR54 ( VAR54),
.VAR39 ( VAR39),
.VAR94 ( VAR94),
.VAR33 ( VAR33),
.VAR57 ( VAR57),
.VAR141 ( VAR141),
.VAR85 ( VAR85),
.VAR24 ( VAR24),
.VAR56 ( VAR56),
.VAR138 ( VAR138),
.VAR125 ( VAR125),
.VAR58 ( VAR58),
.VAR205 ( VAR205),
.VAR2 ( VAR2),
.VAR199 ( VAR199),
.VAR184 ( VAR184),
.VAR158 ( VAR158),
.VAR51 ( VAR51),
.VAR26 ( VAR26),
.VAR164 ( VAR7),
.VAR18 ( VAR18),
.VAR22 ( VAR22),
.VAR77 ( VAR77),
.VAR67 ( VAR67),
.VAR68 ( VAR68),
.VAR98 ( VAR98),
.VAR83 ( VAR83),
.VAR16 ( VAR71[2:0]),
.VAR127 ( VAR71[3]),
.VAR177 ( VAR177),
.VAR63 ( VAR63),
.VAR9 ( VAR9),
.VAR113 ( VAR113),
.VAR91 ( VAR91),
.VAR48 ( VAR48),
.VAR10 ( VAR10),
.VAR194 ( VAR194),
.VAR159 ( VAR159),
.VAR93 ( VAR93),
.VAR123 ( VAR123),
.VAR80 ( VAR80),
.VAR154 ( VAR154),
.VAR87 ( VAR87),
.VAR30 ( VAR30),
.VAR120 ( VAR120),
.VAR116 ( VAR116),
.VAR41 ( VAR41)
)
VAR97 (
.VAR172 ( VAR172),
.VAR151 ( VAR151),
.VAR143 ( VAR143),
.VAR180 ( VAR180),
.VAR146(VAR146),
.VAR150(VAR150),
.VAR160(VAR160),
.VAR110(VAR110),
.VAR130(VAR130),
.VAR185(VAR185),
.VAR84(VAR84),
.VAR175 ( VAR105),
.VAR49 ( VAR105),
.VAR52 ( VAR103),
.VAR170 ( VAR103),
.VAR37 ( VAR115),
.VAR186 ( VAR115),
.VAR27 ( 1'b0),
.VAR108 ( 0),
.VAR142 ( 0),
.VAR88 ( 0),
.VAR65 ( 0),
.VAR104 ( VAR75),
.VAR99 ( VAR112),
.VAR81 ( VAR81),
.VAR36 ( VAR36),
.VAR197 ( VAR197),
.VAR117 ( VAR117),
.VAR45 ( VAR45),
.VAR12 ( VAR12),
.VAR181 ( VAR181),
.VAR196 ( VAR196),
.VAR47 ( VAR47),
.VAR173 ( VAR173),
.VAR166 ( VAR166),
.VAR139 ( VAR139),
.VAR126 ( VAR126),
.VAR133 ( VAR133),
.VAR44 ( VAR44),
.VAR178 ( VAR178),
.VAR25 ( VAR25),
.VAR135 ( VAR135),
.VAR31 ( VAR31),
.VAR29 ( VAR29),
.VAR111 ( VAR111),
.VAR92 ( VAR92),
.VAR190 ( VAR190),
.VAR157 ( VAR157),
.VAR90 ( VAR90),
.VAR40 ( VAR40),
.VAR182 ( VAR182),
.VAR96 ( VAR96),
.VAR162 ( VAR162),
.VAR192 ( VAR192),
.VAR174 ( VAR174),
.VAR128 ( VAR128),
.VAR201 ( VAR201),
.VAR188 ( VAR188),
.VAR106 ( VAR106),
.VAR156 ( VAR156),
.VAR8 ( VAR8),
.VAR72 ( VAR72),
.VAR55 ( VAR55),
.VAR118 ( VAR118),
.VAR4 ( VAR4),
.VAR132 ( VAR132),
.VAR144 ( VAR144),
.VAR86 ( VAR86),
.VAR200 ( VAR200),
.VAR66 ( VAR66),
.VAR176 ( VAR176),
.VAR53 ( VAR53),
.VAR198 ( VAR198),
.VAR61 ( VAR61),
.VAR19 ( VAR19),
.VAR5 ( VAR5),
.VAR161 ( 1'b1),
.VAR171 ( VAR171),
.VAR189 ( VAR189),
.VAR147 ( VAR147),
.VAR73 ( VAR73),
.VAR13 ( VAR13),
.VAR34 ( VAR34),
.VAR101 ( VAR101),
.VAR79 ( VAR79),
.VAR202 ( VAR202),
.VAR195 ( VAR195),
.VAR21 ( VAR21),
.VAR76 ( VAR76),
.VAR89 ( VAR89),
.VAR46 ( VAR46),
.VAR64 ( VAR64),
.VAR114 ( VAR114),
.VAR167 ( VAR167),
.VAR15 ( VAR15)
);
endmodule | lgpl-3.0 |
CospanDesign/nysa-verilog | verilog/generic/graycounter.v | 1,162 | module MODULE1
(output reg [VAR1-1:0] VAR2,
input wire en, input wire rst,
input wire clk);
reg [VAR1-1:0] VAR4;
always @ (posedge clk)
if (rst) begin
VAR4 <= {VAR1{1'VAR3 0}} + 1; VAR2 <= {VAR1{1'VAR3 0}}; end
else if (en) begin
VAR4 <= VAR4 + 1;
VAR2 <= {VAR4[VAR1-1],
VAR4[VAR1-2:0] ^ VAR4[VAR1-1:1]};
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2.behavioral.v | 1,604 | module MODULE1 (
VAR11 ,
VAR10,
VAR3,
VAR6
);
output VAR11 ;
input VAR10;
input VAR3;
input VAR6 ;
supply1 VAR7;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR1 ;
wire VAR5;
VAR9 VAR2 (VAR5, VAR10, VAR3, VAR6 );
buf VAR12 (VAR11 , VAR5);
endmodule | apache-2.0 |
spike556/HuffmanCode | rtl model/sortnet/SortX8.v | 2,922 | module MODULE1 # (
parameter VAR27 = 18,
parameter VAR18 = 8
)(
input [VAR27-1:0] VAR9,
input [VAR27-1:0] VAR19,
input [VAR27-1:0] VAR7,
input [VAR27-1:0] VAR24,
input [VAR27-1:0] VAR23,
input [VAR27-1:0] VAR37,
input [VAR27-1:0] VAR30,
input [VAR27-1:0] VAR2,
output wire [VAR27-1:0] VAR38,
output wire [VAR27-1:0] VAR33,
output wire [VAR27-1:0] VAR42,
output wire [VAR27-1:0] VAR13,
output wire [VAR27-1:0] VAR14,
output wire [VAR27-1:0] VAR22,
output wire [VAR27-1:0] VAR46,
output wire [VAR27-1:0] VAR32
);
wire [VAR27-1:0] VAR21;
wire [VAR27-1:0] VAR44;
wire [VAR27-1:0] VAR47;
wire [VAR27-1:0] VAR10;
wire [VAR27-1:0] VAR8;
wire [VAR27-1:0] VAR29;
wire [VAR27-1:0] VAR1;
wire [VAR27-1:0] VAR45;
wire [VAR27-1:0] VAR16;
wire [VAR27-1:0] VAR31;
wire [VAR27-1:0] VAR25;
wire [VAR27-1:0] VAR6;
wire [VAR27-1:0] VAR20;
wire [VAR27-1:0] VAR12;
wire [VAR27-1:0] VAR4;
wire [VAR27-1:0] VAR17;
VAR11 # (
.VAR27 (VAR27),
.VAR18(VAR18)
) VAR35 (
.VAR9 (VAR9),
.VAR19 (VAR19),
.VAR7 (VAR7),
.VAR24 (VAR24),
.VAR38 (VAR21),
.VAR33 (VAR44),
.VAR42 (VAR47),
.VAR13 (VAR10)
);
VAR11 # (
.VAR27 (VAR27),
.VAR18(VAR18)
) VAR34 (
.VAR9 (VAR23),
.VAR19 (VAR37),
.VAR7 (VAR30),
.VAR24 (VAR2),
.VAR38 (VAR8),
.VAR33 (VAR29),
.VAR42 (VAR1),
.VAR13 (VAR45)
);
VAR26 # (
.VAR27 (VAR27),
.VAR18(VAR18)
) VAR41 (
.VAR43(VAR21),
.VAR36(VAR45),
.VAR38(VAR16),
.VAR33(VAR31)
);
VAR26 # (
.VAR27 (VAR27),
.VAR18(VAR18)
) VAR39 (
.VAR43(VAR44),
.VAR36(VAR1),
.VAR38(VAR25),
.VAR33(VAR6)
);
VAR26 # (
.VAR27 (VAR27),
.VAR18(VAR18)
) VAR15 (
.VAR43(VAR47),
.VAR36(VAR29),
.VAR38(VAR20),
.VAR33(VAR12)
);
VAR26 # (
.VAR27 (VAR27),
.VAR18(VAR18)
) VAR3 (
.VAR43(VAR10),
.VAR36(VAR8),
.VAR38(VAR4),
.VAR33(VAR17)
);
VAR28 # (
.VAR27 (VAR27),
.VAR18(VAR18)
) VAR40 (
.VAR9 (VAR16),
.VAR19 (VAR25),
.VAR7 (VAR20),
.VAR24 (VAR4),
.VAR38 (VAR38),
.VAR33 (VAR33),
.VAR42 (VAR42),
.VAR13 (VAR13)
);
VAR28 # (
.VAR27 (VAR27),
.VAR18(VAR18)
) VAR5 (
.VAR9 (VAR17),
.VAR19 (VAR12),
.VAR7 (VAR6),
.VAR24 (VAR31),
.VAR38 (VAR14),
.VAR33 (VAR22),
.VAR42 (VAR46),
.VAR13 (VAR32)
);
endmodule | gpl-3.0 |
rongcuid/lots-of-subleq-cpus | Subleq Pipelined/src/BRAM.v | 1,083 | module MODULE1(
clk, VAR8, en, addr, VAR3, VAR6
);
parameter VAR2 = 8, VAR5 = 1024, VAR1 = 10;
input wire clk;
input wire VAR8;
input wire en;
input wire [VAR2-1:0] VAR3;
output reg [VAR2-1:0] VAR6;
reg [VAR2-1:0] VAR7 [0:VAR5-1];
always @ (posedge clk) begin
if (en) begin
if (VAR8) begin
VAR7[addr] <= VAR3;
VAR6 <= VAR4;
end
else begin
VAR6 <= VAR7[addr];
end
end
end
endmodule | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_8c_v1_00_a/hdl/verilog/cf_adc_if.v | 9,015 | module MODULE1 (
VAR67,
VAR38,
VAR21,
VAR70,
VAR87,
VAR35,
VAR25,
VAR15,
VAR56,
VAR8,
VAR7,
VAR16,
VAR60,
VAR50,
VAR3,
VAR79);
input VAR67;
input VAR38;
input [ 7:0] VAR21;
input [ 7:0] VAR70;
input VAR87;
input VAR35;
output VAR25;
output VAR15;
output [63:0] VAR56;
output VAR8;
output [ 7:0] VAR7;
output [ 7:0] VAR16;
input VAR60;
input [ 7:0] VAR50;
output VAR3;
output [143:0] VAR79;
reg VAR15 = 'd0;
reg VAR36 = 'd0;
reg [ 5:0] VAR76 = 'd0;
reg [ 5:0] VAR62 = 'd0;
reg [11:0] VAR33 = 'd0;
reg [ 3:0] VAR58 = 'd0;
reg [63:0] VAR56 = 'd0;
reg [ 4:0] VAR13 = 'd0;
reg VAR8 = 'd0;
wire VAR10;
wire [11:0] VAR82;
wire [11:0] VAR34[7:0];
wire VAR23;
wire VAR74;
wire [ 5:0] VAR28;
wire VAR42;
wire VAR32;
genvar VAR31;
assign VAR3 = VAR36;
assign VAR79[143:128] = {4'd0, VAR33};
assign VAR79[127:112] = {4'd0, VAR34[7]};
assign VAR79[111: 96] = {4'd0, VAR34[6]};
assign VAR79[ 95: 80] = {4'd0, VAR34[5]};
assign VAR79[ 79: 64] = {4'd0, VAR34[4]};
assign VAR79[ 63: 48] = {4'd0, VAR34[3]};
assign VAR79[ 47: 32] = {4'd0, VAR34[2]};
assign VAR79[ 31: 16] = {4'd0, VAR34[1]};
assign VAR79[ 15: 0] = {4'd0, VAR34[0]};
assign VAR10 = (VAR33 == VAR82) ? ~VAR36 : VAR36;
assign VAR82 = {VAR62, VAR76};
always @(posedge VAR25) begin
VAR15 <= 1'b1;
VAR36 <= ~VAR36;
VAR76 <= VAR28;
VAR62 <= VAR76;
if (VAR36 == 1'b1) begin
VAR33 <= VAR82;
end
case (VAR33)
12'b111111000000: VAR58 <= 4'h0;
12'b011111100000: VAR58 <= 4'h1;
12'b001111110000: VAR58 <= 4'h2;
12'b000111111000: VAR58 <= 4'h3;
12'b000011111100: VAR58 <= 4'h4;
12'b000001111110: VAR58 <= 4'h5;
12'b000000111111: VAR58 <= 4'h6;
12'b100000011111: VAR58 <= 4'h7;
12'b110000001111: VAR58 <= 4'h8;
12'b111000000111: VAR58 <= 4'h9;
12'b111100000011: VAR58 <= 4'ha;
12'b111110000001: VAR58 <= 4'hb;
default: VAR58 <= 4'hf;
endcase
if (VAR36 == 1'b1) begin
VAR56[63:48] <= {4'd0, VAR34[7]};
VAR56[47:32] <= {4'd0, VAR34[6]};
VAR56[31:16] <= {4'd0, VAR34[5]};
VAR56[15: 0] <= {4'd0, VAR34[4]};
end else begin
VAR56[63:48] <= {4'd0, VAR34[3]};
VAR56[47:32] <= {4'd0, VAR34[2]};
VAR56[31:16] <= {4'd0, VAR34[1]};
VAR56[15: 0] <= {4'd0, VAR34[0]};
end
if (VAR10 == 1'b1) begin
VAR13 <= 5'h10;
end else if (VAR13[4] == 1'b1) begin
VAR13 <= VAR13 + 1'b1;
end
VAR8 <= VAR13[4];
end
generate
for (VAR31 = 0; VAR31 <= 7; VAR31 = VAR31 + 1) begin : VAR83
VAR51 VAR27 (
.VAR21 (VAR21[VAR31]),
.VAR70 (VAR70[VAR31]),
.VAR32 (VAR32),
.VAR25 (VAR25),
.VAR93 (VAR23),
.VAR36 (VAR36),
.VAR58 (VAR58),
.VAR7 (VAR7[VAR31]),
.VAR16 (VAR16[VAR31]),
.VAR56 (VAR34[VAR31]),
.VAR50 (VAR50[VAR31]));
end
endgenerate
VAR4 #(.VAR57(1'b1)) VAR81 (
.VAR94 (1'b1),
.VAR40 (1'b0),
.VAR59 (VAR60),
.VAR72 (VAR25),
.VAR85 (VAR23));
VAR89 VAR30 (
.VAR75 (VAR87),
.VAR69 (VAR35),
.VAR22 (VAR74));
VAR18 # (
.VAR54 ("VAR11"),
.VAR61 (6),
.VAR39 ("VAR88"),
.VAR37 ("VAR73"),
.VAR77 ("VAR73"),
.VAR52 (2),
.VAR9 ("VAR73"),
.VAR80 ("VAR49"),
.VAR29 ("VAR68"))
VAR48 (
.VAR24 (VAR28[0]),
.VAR14 (VAR28[1]),
.VAR2 (VAR28[2]),
.VAR71 (VAR28[3]),
.VAR66 (VAR28[4]),
.VAR1 (VAR28[5]),
.VAR78 (),
.VAR20 (),
.VAR26 (1'b0),
.VAR92 (1'b1),
.VAR86 (1'b1),
.VAR12 (VAR32),
.VAR43 (~VAR32),
.VAR55 (VAR25),
.VAR40 (VAR74),
.VAR5 (1'b0),
.VAR64 (VAR23),
.VAR65 (1'b0),
.VAR91 (1'b0),
.VAR45 (1'b0),
.VAR19 (1'b0),
.VAR90 (1'b0),
.VAR53 (1'b0),
.VAR22 ());
VAR17 VAR46 (
.VAR75 (VAR67),
.VAR69 (VAR38),
.VAR22 (VAR42));
VAR6 VAR63 (
.VAR75 (VAR42),
.VAR22 (VAR32));
VAR44 #( .VAR47 ("3")) VAR84 (
.VAR41 (1'b0),
.VAR94 (1'b1),
.VAR75 (VAR42),
.VAR22 (VAR25));
endmodule | mit |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/phyIniCommand0.v | 1,133 | module MODULE1
(
input [(VAR4-1):0] VAR3,
input [(VAR1-1):0] addr,
input VAR6, clk,
output [(VAR4-1):0] VAR2
);
reg [VAR4-1:0] VAR7[2**VAR1-1:0];
reg [VAR1-1:0] VAR5;
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o.functional.pp.v | 2,231 | module MODULE1 (
VAR10 ,
VAR11,
VAR2,
VAR4 ,
VAR6 ,
VAR3,
VAR9,
VAR8 ,
VAR5
);
output VAR10 ;
input VAR11;
input VAR2;
input VAR4 ;
input VAR6 ;
input VAR3;
input VAR9;
input VAR8 ;
input VAR5 ;
wire VAR13 ;
wire VAR16 ;
wire VAR15 ;
wire VAR12;
and VAR17 (VAR13 , VAR4, VAR6 );
nor VAR18 (VAR16 , VAR11, VAR2 );
or VAR1 (VAR15 , VAR16, VAR13 );
VAR19 VAR7 (VAR12, VAR15, VAR3, VAR9);
buf VAR14 (VAR10 , VAR12 );
endmodule | apache-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/lib/xs6_addsub_n.v | 5,193 | module MODULE1 #(
parameter VAR19=32
)(
input [VAR19-1:0] VAR54,
input [VAR19-1:0] VAR14,
input VAR51,
input VAR33,
output [VAR19-1:0] VAR46,
output VAR4
);
wire [7:0] VAR10;
wire [47:0] VAR49, VAR36;
wire [47:0] out;
assign VAR10 = {VAR33, 1'd0, VAR51, 1'd0, 2'd3, 2'd3 };
assign VAR49 = {{48-VAR19{1'd0}}, VAR54};
assign VAR36 = {{48-VAR19{1'd0}}, VAR14};
assign VAR46 = out[VAR19-1:0];
assign VAR4 = out[VAR19];
VAR52 #(
.VAR39 ( 0 ),
.VAR27 ( 0 ),
.VAR42 ( 0 ),
.VAR37 ( 0 ),
.VAR50 ( 0 ),
.VAR41 ( 0 ),
.VAR45 ( 0 ),
.VAR40 ( 0 ),
.VAR11 ( 0 ),
.VAR2 ( 0 ),
.VAR24 ("VAR31" ),
.VAR30 ( "VAR35" )
)
VAR28 (
.VAR43 ( ),
.VAR15 ( ),
.VAR5 ( ),
.VAR44 ( ),
.VAR26 ( out ),
.VAR6 ( ),
.VAR17 ( 1'd0 ),
.VAR55 ( VAR36[35:18] ),
.VAR23 ( VAR36[17:00] ),
.VAR25 ( VAR49 ),
.VAR48 ( {6'd0, VAR36[47:36]} ),
.VAR3 ( 1'd0 ), .VAR47 ( VAR10 ),
.VAR22 ( 48'd0 ),
.VAR32 ( 1'd1 ),
.VAR21 ( 1'd1 ),
.VAR9 ( 1'd1 ),
.VAR13 ( 1'd1 ),
.VAR53 ( 1'd1 ),
.VAR29 ( 1'd1 ),
.VAR12 ( 1'd1 ),
.VAR16 ( 1'd1 ),
.VAR56 ( 1'd0 ),
.VAR34 ( 1'd0 ),
.VAR18 ( 1'd0 ),
.VAR7 ( 1'd0 ),
.VAR20 ( 1'd0 ),
.VAR1 ( 1'd0 ),
.VAR38 ( 1'd0 ),
.VAR8 ( 1'd0 )
);
endmodule | gpl-2.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab04/lab04/Code/CPU/Regs.v | 1,167 | module MODULE1(input clk,
input rst,
input [4:0] VAR2,
input [4:0] VAR5,
input [4:0] VAR6,
input [31:0]VAR3,
input VAR4,
output [31:0] VAR8,
output [31:0] VAR7
);
reg [31:0] register [1:31]; integer VAR1;
assign VAR8 = (VAR2 == 0)? 0 : register[VAR2]; assign VAR7 = (VAR5 == 0)? 0 : register[VAR5];
always @(posedge clk or posedge rst)
begin
if (rst==1) begin for (VAR1=1; VAR1<32; VAR1=VAR1+1)
register[VAR1] <= 0; end
else begin
if ((VAR6 != 0) && (VAR4 == 1)) register[VAR6] <= VAR3;
end
end
endmodule | gpl-3.0 |
migajv/mips_pipeline | verilog/alu.v | 2,037 | module MODULE1(
input [5:0] VAR15,
input [5:0] VAR25,
input [31:0] VAR23, VAR16,
output reg [31:0] out,
output VAR7);
wire VAR9;
wire [1:0] VAR6;
wire VAR20;
wire VAR21;
wire VAR8;
wire [1:0] VAR5;
wire VAR11;
wire VAR10;
VAR24 VAR14(.VAR19(VAR6),
.VAR9 (VAR9),
.VAR20 (VAR20),
.VAR8 (VAR8),
.VAR5 (VAR5[1:0]),
.VAR21 (VAR21),
.VAR10 (VAR10),
.VAR11 (VAR11),
.VAR25 (VAR25[5:0]));
wire [3:0] VAR13;
VAR4 VAR1(.VAR5(VAR5),
.VAR13 (VAR13[3:0]),
.VAR15 (VAR15[5:0]));
wire [31:0] VAR22;
wire [31:0] VAR2;
wire VAR17;
wire VAR18;
wire VAR12;
wire VAR3;
assign VAR7 = (0 == out);
assign VAR22 = VAR23 - VAR16;
assign VAR2 = VAR23 + VAR16;
assign VAR17 = (VAR23[31] == VAR16[31] && VAR2[31] != VAR23[31]) ? 1 : 0;
assign VAR18 = (VAR23[31] == VAR16[31] && VAR22[31] != VAR23[31]) ? 1 : 0;
assign VAR12 = (VAR13 == 4'b0010) ? VAR17 : VAR18;
assign VAR3 = VAR18 ? ~(VAR23[31]) : VAR23[31];
always @(*) begin
case (VAR13)
4'b0010: out <= VAR2; 4'b0000: out <= VAR23 & VAR16; 4'b1100: out <= ~(VAR23 | VAR16); 4'b0001: out <= VAR23 | VAR16; 4'b0111: out <= {{31{1'b0}}, VAR3}; 4'b0110: out <= VAR22; 4'b1101: out <= VAR23 ^ VAR16; default: out <= 0;
endcase
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3.blackbox.v | 1,260 | module MODULE1 (
VAR7,
VAR1,
VAR4,
VAR6
);
output VAR7;
input VAR1;
input VAR4;
input VAR6;
supply1 VAR8;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.functional.pp.v | 2,018 | module MODULE1 (
VAR18,
VAR1 ,
VAR9,
VAR12 ,
VAR14,
VAR11,
VAR15 ,
VAR16
);
output VAR18;
input VAR1 ;
input VAR9;
input VAR12 ;
input VAR14;
input VAR11;
input VAR15 ;
input VAR16 ;
wire VAR7 ;
wire VAR2 ;
wire VAR6 ;
wire VAR8;
not VAR3 (VAR2 , VAR7 );
not VAR13 (VAR6 , VAR12 );
nor VAR10 (VAR8, VAR9, VAR1 );
VAR5 VAR4 (VAR7 , VAR8, VAR6, , VAR14, VAR11);
and VAR17 (VAR18 , VAR2, VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp.symbol.v | 1,346 | module MODULE1 (
input VAR8 ,
input VAR5 ,
input VAR6,
output VAR1
);
supply1 VAR3;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
jameshegarty/rigel | platform/camera1x/vsrc/axi_master_read_stub.v | 1,411 | module MODULE1(
output VAR9,
output VAR8,
input VAR1,
output [31:0] VAR3,
output [1:0] VAR11,
output [3:0] VAR5,
output [1:0] VAR4,
input VAR6,
output VAR2,
input VAR10,
input [63:0] VAR12,
input [1:0] VAR7
);
assign VAR9 = 1'b0;
assign VAR8 = 1'b0;
assign VAR3 = 32'b0;
assign VAR11 = 2'b0;
assign VAR5 = 4'b0;
assign VAR4 = 2'b0;
assign VAR2 = 1'b0;
endmodule : MODULE1 | mit |
zhangly/azpr_cpu | rtl/io/uart/rtl/uart_rx.v | 2,668 | module MODULE1 (
input wire clk, input wire reset,
output wire VAR4, output reg VAR8, output reg [VAR5] VAR3,
input wire VAR21 );
reg [VAR19] state; reg [VAR10] VAR1; reg [VAR23] VAR18;
assign VAR4 = (state != VAR17) ? VAR9 : VAR20;
always @(posedge clk or VAR15 reset) begin
if (reset == VAR12) begin
VAR8 <= VAR20;
VAR3 <= VAR14'h0;
state <= VAR17;
VAR1 <= VAR7 / 2;
VAR18 <= VAR11'h0;
end else begin
case (state)
end
VAR8 <= VAR20;
end
if (VAR1 == {VAR22{1'b0}}) begin
case (VAR18)
VAR18 <= VAR6;
VAR1 <= VAR7 / 2;
if (VAR21 == VAR2) begin
VAR8 <= VAR9;
end
end
default : begin VAR3 <= {VAR21, VAR3[VAR16:VAR13+1]};
VAR18 <= VAR18 + 1'b1;
VAR1 <= VAR7;
end
endcase
end else begin VAR1 <= VAR1 - 1'b1;
end
end
endcase
end
end
endmodule | mit |
rkrajnc/minimig-mist | lib/io/generic_input.v | 1,843 | module MODULE1 #(
parameter VAR5 = 1, parameter VAR1 = 10, parameter VAR2 = 1'b0, parameter VAR7 = 0 )(
output wire [ VAR5-1:0] VAR3
);
reg [ VAR5-1:0] state = {VAR5{VAR2}};
assign VAR3 = state;
task VAR10;
input [ VAR5-1:0] VAR4;
begin
if (VAR7) );
state <= VAR2 ? VAR4 & state : VAR4 | state;
end
endtask
task VAR8;
input [ VAR5-1:0] VAR4;
begin
if (VAR7) );
state <= VAR2 ? VAR4 | state : VAR4 & state;
end
endtask
task VAR9;
input [ VAR5-1:0] VAR4;
begin
if (VAR7) );
state = VAR4 ^ state;
if (VAR7) );
state = VAR4 ^ state;
end
endtask
task VAR6;
input [ VAR5-1:0] VAR4;
begin
if (VAR7) );
state = VAR4 ^ state;
end
endtask
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapmet1/sky130_fd_sc_ms__tapmet1.blackbox.v | 1,223 | module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_clk_edgelogic.v | 2,398 | module MODULE1(
VAR15, VAR14,
clk, VAR5, VAR11, VAR9,
VAR12, VAR7
);
input clk;
input VAR7;
input VAR5;
input VAR11;
input VAR9;
input VAR12;
output VAR15;
output VAR14;
wire VAR17 = VAR7 ? ~clk : clk;
VAR10 #(1) VAR1(
.din(VAR12),
.VAR4(VAR2),
.clk(VAR17),
.VAR6(VAR5), .VAR3(VAR15), .VAR13(VAR11));
wire VAR8 = VAR9 & VAR2;
wire VAR16 = VAR2 ? ~VAR8 : VAR8;
assign VAR14 = clk ? VAR8 : VAR16;
endmodule | gpl-2.0 |
amrmorsey/Digital-Design-Project | sbox1.v | 3,551 | module MODULE1(
VAR2,
VAR3
);
input [6:1] VAR2;
output reg [4:1] VAR3;
wire [6:1] VAR1;
assign VAR1 = {VAR2[6], VAR2[1], VAR2[5 : 2]};
always @(VAR1)
begin
case (VAR1)
6'b000000: VAR3 <= 4'd14;
6'b000001: VAR3 <= 4'd4;
6'b000010: VAR3 <= 4'd13;
6'b000011: VAR3 <= 4'd1;
6'b000100: VAR3 <= 4'd2;
6'b000101: VAR3 <= 4'd15;
6'b000110: VAR3 <= 4'd11;
6'b000111: VAR3 <= 4'd8;
6'b001000: VAR3 <= 4'd3;
6'b001001: VAR3 <= 4'd10;
6'b001010: VAR3 <= 4'd6;
6'b001011: VAR3 <= 4'd12;
6'b001100: VAR3 <= 4'd5;
6'b001101: VAR3 <= 4'd9;
6'b001110: VAR3 <= 4'd0;
6'b001111: VAR3 <= 4'd7;
6'b010000: VAR3 <= 4'd0;
6'b010001: VAR3 <= 4'd15;
6'b010010: VAR3 <= 4'd7;
6'b010011: VAR3 <= 4'd4;
6'b010100: VAR3 <= 4'd14;
6'b010101: VAR3 <= 4'd2;
6'b010110: VAR3 <= 4'd13;
6'b010111: VAR3 <= 4'd1;
6'b011000: VAR3 <= 4'd10;
6'b011001: VAR3 <= 4'd6;
6'b011010: VAR3 <= 4'd12;
6'b011011: VAR3 <= 4'd11;
6'b011100: VAR3 <= 4'd9;
6'b011101: VAR3 <= 4'd5;
6'b011110: VAR3 <= 4'd3;
6'b011111: VAR3 <= 4'd8;
6'b100000: VAR3 <= 4'd4;
6'b100001: VAR3 <= 4'd1;
6'b100010: VAR3 <= 4'd14;
6'b100011: VAR3 <= 4'd8;
6'b100100: VAR3 <= 4'd13;
6'b100101: VAR3 <= 4'd6;
6'b100110: VAR3 <= 4'd2;
6'b100111: VAR3 <= 4'd11;
6'b101000: VAR3 <= 4'd15;
6'b101001: VAR3 <= 4'd12;
6'b101010: VAR3 <= 4'd9;
6'b101011: VAR3 <= 4'd7;
6'b101100: VAR3 <= 4'd3;
6'b101101: VAR3 <= 4'd10;
6'b101110: VAR3 <= 4'd5;
6'b101111: VAR3 <= 4'd0;
6'b110000: VAR3 <= 4'd15;
6'b110001: VAR3 <= 4'd12;
6'b110010: VAR3 <= 4'd8;
6'b110011: VAR3 <= 4'd2;
6'b110100: VAR3 <= 4'd4;
6'b110101: VAR3 <= 4'd9;
6'b110110: VAR3 <= 4'd1;
6'b110111: VAR3 <= 4'd7;
6'b111000: VAR3 <= 4'd5;
6'b111001: VAR3 <= 4'd11;
6'b111010: VAR3 <= 4'd3;
6'b111011: VAR3 <= 4'd14;
6'b111100: VAR3 <= 4'd10;
6'b111101: VAR3 <= 4'd0;
6'b111110: VAR3 <= 4'd6;
6'b111111: VAR3 <= 4'd13;
default: VAR3 <= 4'd0;
endcase
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2_lp2.v | 2,102 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR6 ,
VAR1,
VAR9,
VAR5 ,
VAR7
);
output VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR1;
input VAR9;
input VAR5 ;
input VAR7 ;
VAR3 VAR2 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR4,
VAR8,
VAR6
);
output VAR4;
input VAR8;
input VAR6;
supply1 VAR1;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR7 ;
VAR3 VAR2 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
Kumikomi/openreroc_accelsensor | hardware/src/MPU_accel_controller.v | 12,919 | module MODULE1(
input clk,
input reset,
output reg [15:0] VAR3, output reg [15:0] VAR19, output reg [15:0] VAR1,
output VAR52, output VAR38, output VAR47, input VAR20, output reg VAR17
);
parameter VAR25 = 0,
VAR44 = 1,
VAR11 = 2,
VAR13 = 3,
VAR31 = 4,
VAR45 = 5,
VAR33 = 6,
VAR40 = 7,
VAR12 = 8,
VAR8 = 9,
VAR21 = 10,
VAR16 = 11,
VAR49 = 12,
VAR36 = 13,
VAR28 = 14,
VAR9 = 15,
VAR15 = 16,
VAR4 = 17;
wire VAR32; wire [7:0] VAR22;
reg [31:0] VAR37 = 0; parameter VAR35 = 32'd1000000;
reg [4:0] state;
reg [5:0] VAR41;
reg [6:0] VAR5; reg [7:0] VAR51; reg VAR26; reg VAR7 = 0; reg [7:0] VAR48; reg [7:0] VAR10; reg [7:0] VAR39;
reg [7:0] VAR6;
VAR29 VAR29(
.clk(clk),
.rst(reset),
.VAR27(VAR5),
.VAR42(VAR51),
.VAR46(VAR22), .VAR34(VAR26),
.VAR14(VAR7),
.VAR2(VAR32),
.VAR52(VAR52), .VAR38(VAR38), .VAR47(VAR47), .VAR20(VAR20) );
always@ (posedge clk)
begin
if(reset)
state <= 0;
end
else
begin
case(state)
0:if(VAR32 == 0) state <= 1; 1: state <= 2; 2:if(VAR32 == 0) state <= 16; 16:state <= 17; 17:if(VAR32 == 0) state <= 18; 18:state <= 19;
19:state <= 20; 20:if(VAR32 == 0) state <= 3;
3:if(VAR32 == 0)state <= 4; 4:if(VAR41 == 6 && VAR32 == 0) state <= 5; 5:if(VAR41 == 12 && VAR32 == 0) state <= 6; 6:if(VAR41 == 18 && VAR32 == 0) state <= 10;
10:if(VAR37 == VAR35) state <= 3;
default state <= 0;
endcase
end
end
always@ (posedge clk)
begin
if(reset)
begin
VAR3 <= 0;
VAR19 <= 0;
VAR1 <= 0;
VAR5 <= 0;
VAR51 <= 0;
VAR26 <= 1; VAR7 <= 0;
VAR41 <= 0;
VAR17 <= 0;
end
else
begin
case (state)
0:begin VAR3 <= 0;
VAR19 <= 0;
VAR1 <= 0;
VAR48 <= 0;
VAR10 <= 0;
VAR39 <= 0;
VAR5 <= 0;
VAR51 <= 0;
VAR7 <= 0;
VAR41 <= 0;
VAR37 <= 0;
VAR17 <= 0;
end
1:begin VAR7 <= 1;
VAR26 <= 0; VAR5 <= 8'h6B;
VAR51 <= 8'h00;
end
2:begin VAR7 <= 0;
end
16:begin VAR7 <= 1;
VAR26 <= 1; VAR5 <= 8'h75; end
17:begin VAR7 <= 0;
end
18:begin VAR6 <= VAR22;
end
19:begin VAR7 <= 1;
VAR26 <= 0; VAR5 <= 8'h37; VAR51 <= 8'h02;
end
20:begin VAR7 <= 0;
end
3:begin VAR17 <= 0;
VAR48 <= 0;
VAR10 <= 0;
VAR39 <= 0;
VAR41 <= 0;
VAR37 <= 0;
end
4:begin case(VAR41)
VAR25:begin
if(VAR32 == 0) begin
VAR7 <= 1;
VAR26 <= 1;
VAR5 <= VAR30; VAR41 <= VAR41 + 1;
end
end
VAR44:begin
VAR7 <= 0;
if(VAR32 == 0) VAR41 <= VAR41 + 1;
end
VAR11:begin
VAR48 <= VAR22;
VAR41 <= VAR41 + 1;
end
VAR13:begin
if(VAR32 == 0) begin
VAR7 <= 1;
VAR26 <= 1;
VAR5 <= VAR24; VAR41 <= VAR41 + 1;
end
end
VAR31:begin
VAR7 <= 0;
if(VAR32 == 0) VAR41 <= VAR41 + 1;
end
VAR45:begin
VAR3 <= {VAR22,VAR48};
VAR41 <= VAR41 + 1;
end
endcase
end
5:begin case(VAR41)
VAR33:begin
if(VAR32 == 0) begin
VAR7 <= 1;
VAR26 <= 1;
VAR5 <= VAR23; VAR41 <= VAR41 + 1;
end
end
VAR40:begin
VAR7 <= 0;
if(VAR32 == 0) VAR41 <= VAR41 + 1;
end
VAR12:begin
VAR10 <= VAR22;
VAR41 <= VAR41 + 1;
end
VAR8:begin
if(VAR32 == 0) begin
VAR7 <= 1;
VAR26 <= 1;
VAR5 <= VAR18; VAR41 <= VAR41 + 1;
end
end
VAR21:begin
VAR7 <= 0;
if(VAR32 == 0) VAR41 <= VAR41 + 1;
end
VAR16:begin
VAR19 <= {VAR22,VAR10};
VAR41 <= VAR41 + 1;
end
endcase
end
6:begin case(VAR41)
VAR49:begin
if(VAR32 == 0) begin
VAR7 <= 1;
VAR26 <= 1;
VAR5 <= VAR43; VAR41 <= VAR41 + 1;
end
end
VAR36:begin
VAR7 <= 0;
if(VAR32 == 0) VAR41 <= VAR41 + 1;
end
VAR28:begin
VAR39 <= VAR22;
VAR41 <= VAR41 + 1;
end
VAR9:begin
if(VAR32 == 0) begin
VAR7 <= 1;
VAR26 <= 1;
VAR5 <= VAR50; VAR41 <= VAR41 + 1;
end
end
VAR15:begin
VAR7 <= 0;
if(VAR32 == 0) VAR41 <= VAR41 + 1;
end
VAR4:begin
VAR1 <= {VAR22,VAR39};
VAR41 <= VAR41 + 1;
end
endcase
end
10:begin if(VAR37 == (VAR35 -1000)) begin
VAR17 <= 1;
VAR37 <= VAR37 + 1;
end
else begin
VAR37 <= VAR37 + 1;
end
end
endcase
end
end
endmodule | bsd-3-clause |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_backend_frame_fifo.v | 18,582 | module MODULE1 (
VAR44, VAR37,
VAR43, VAR6,
VAR61, VAR50,
VAR48, VAR58, VAR30, VAR29, VAR38, VAR32,
VAR59,
VAR16,
VAR35, VAR42,
VAR34, VAR49 );
output [15:0] VAR44; output VAR37;
output[VAR23:0] VAR43; output VAR6;
input VAR61; input VAR50;
input [VAR25:0] VAR48; input [VAR25:0] VAR58; input [VAR26:0] VAR30; input VAR29; input VAR38; input VAR32;
input VAR59;
input [2:0] VAR16;
input [15:0] VAR35; input VAR42;
input VAR34; input [VAR51:0] VAR49;
parameter VAR17 = 2'h0,
VAR65 = 2'h3;
wire VAR14 = (VAR16 == 3'b000);
wire VAR47 = (VAR16 == 3'b001);
wire VAR27 = (VAR16 == 3'b010);
wire VAR28 = (VAR16 == 3'b011);
wire VAR53 = ~(VAR28 | VAR27 |
VAR47 | VAR14);
reg [1:0] VAR60;
wire [1:0] VAR36;
wire VAR56;
wire VAR22;
reg VAR9;
reg VAR54;
wire [15:0] VAR2;
reg VAR10;
wire VAR20 = VAR34 &
(VAR36 != VAR65) & ~((VAR36 == (VAR65-1)) & VAR56);
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR10 <= 1'h0;
else VAR10 <= VAR20;
reg [VAR51:0] VAR45;
reg [VAR51:0] VAR5;
reg [VAR25:0] VAR11;
wire VAR18 = VAR10 & VAR56;
wire [VAR25:0] VAR57 = VAR32 ? VAR58 : VAR48;
wire VAR13 = VAR18 & (VAR11==(VAR57-{{VAR25{1'b0}}, 1'b1}));
wire [VAR23*3:0] VAR31 = {{VAR23*3-VAR26{1'b0}}, VAR30};
wire [VAR23*3:0] VAR41 = {{VAR23*3-VAR25{1'b0}}, VAR48};
wire [VAR51:0] VAR3 = ~VAR34 ? VAR49 :
VAR13 ? VAR5 :
VAR45 ;
wire [VAR51:0] VAR64 = VAR3
+ (VAR31[VAR51:0] & {VAR51+1{VAR34 ? 1'b0 : VAR29}})
+ (VAR41[VAR51:0] & {VAR51+1{VAR34 ? (~VAR29 & (VAR32 ^ VAR13)) : VAR38}})
- (VAR41[VAR51:0] & {VAR51+1{VAR34 ? ( VAR29 & (VAR32 ^ VAR13)) : VAR29}})
+ ({{VAR51{1'b0}}, 1'b1} & {VAR51+1{VAR34 ? (~VAR38 & ~(VAR32 ^ VAR13)) : 1'b0 }})
- ({{VAR51{1'b0}}, 1'b1} & {VAR51+1{VAR34 ? ( VAR38 & ~(VAR32 ^ VAR13)) : VAR38}});
wire VAR4 = ~VAR34 | VAR13;
wire VAR7 = VAR4 | VAR18;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR5 <= {VAR51+1{1'b0}};
else if (VAR4) VAR5 <= VAR64;
wire [VAR51:0] VAR52 = VAR7 ? VAR64 : VAR45;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR45 <= {VAR51+1{1'b0}};
else VAR45 <= VAR52;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR11 <= {VAR25+1{1'b0}};
else if (~VAR34) VAR11 <= {VAR25+1{1'b0}};
else if (VAR13) VAR11 <= {VAR25+1{1'b0}};
else if (VAR18) VAR11 <= VAR11 + {{VAR25{1'b0}}, 1'b1};
assign VAR43 = ({VAR23+1{VAR14 }} & VAR45[VAR23+4:4]) |
({VAR23+1{VAR47 }} & VAR45[VAR23+3:3]) |
({VAR23+1{VAR27 }} & VAR45[VAR23+2:2]) |
({VAR23+1{VAR28 }} & VAR45[VAR23+1:1]) |
({VAR23+1{VAR53}} & VAR45[VAR23+0:0]) ;
wire [VAR23:0] VAR21 = ({VAR23+1{VAR14 }} & VAR52[VAR23+4:4]) |
({VAR23+1{VAR47 }} & VAR52[VAR23+3:3]) |
({VAR23+1{VAR27 }} & VAR52[VAR23+2:2]) |
({VAR23+1{VAR28 }} & VAR52[VAR23+1:1]) |
({VAR23+1{VAR53}} & VAR52[VAR23+0:0]) ;
reg VAR55;
wire VAR33 = (VAR43 != VAR21);
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR55 <= 1'h0;
else if (~VAR34) VAR55 <= 1'h1;
else if (VAR18) VAR55 <= VAR33;
assign VAR6 = VAR55 ? ~VAR10 : 1'b1;
assign VAR56 = VAR55 ? VAR42 : VAR10;
reg [15:0] VAR24;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR24 <= 16'h0000;
else if (VAR54) VAR24 <= VAR35;
wire [15:0] VAR40 = VAR54 ? VAR35 : VAR24;
wire [3:0] VAR1 = ({4{VAR14}} & {VAR45[3:0] }) |
({4{VAR47}} & {VAR45[2:0], 1'b0 }) |
({4{VAR27}} & {VAR45[1:0], 2'b00 }) |
({4{VAR28}} & {VAR45[0], 3'b000 }) ;
reg [3:0] VAR12;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR12 <= 4'h0;
else if (VAR18) VAR12 <= VAR1;
wire [15:0] VAR66 = (VAR40 >> VAR12);
assign VAR2 = ({16{VAR14 }} & {8'h00, 7'b0000000, VAR66[0] }) |
({16{VAR47 }} & {8'h00, 6'b000000 , VAR66[1:0]}) |
({16{VAR27 }} & {8'h00, 4'b0000 , VAR66[3:0]}) |
({16{VAR28 }} & {8'h00, VAR66[7:0]}) |
({16{VAR53}} & { VAR66[15:0] }) ;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR9 <= 1'b0;
else VAR9 <= VAR56;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR54 <= 1'b0;
else VAR54 <= VAR42;
wire VAR39 = VAR9 & (VAR60 != VAR65);
wire VAR19 = VAR22 & (VAR60 != VAR17);
assign VAR36 = ~VAR34 ? VAR17 : (VAR39 & VAR19) ? VAR60 : VAR39 ? VAR60 + 2'h1 : VAR19 ? VAR60 - 2'h1 : VAR60;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR60 <= VAR17;
else VAR60 <= VAR36;
reg [1:0] VAR15;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR15 <= 2'h0;
else if (~VAR34) VAR15 <= 2'h0;
else if (VAR39)
begin
if (VAR15==(VAR65-1)) VAR15 <= 2'h0;
end
else VAR15 <= VAR15 + 2'h1;
end
reg [15:0] VAR8 [0:2];
always @(posedge VAR61 or posedge VAR50)
if (VAR50)
begin
VAR8[0] <= 16'h0000;
VAR8[1] <= 16'h0000;
VAR8[2] <= 16'h0000;
end
else if (VAR39)
begin
VAR8[VAR15] <= VAR2;
end
reg [1:0] VAR63;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR63 <= 2'h0;
else if (~VAR34) VAR63 <= 2'h0;
else if (VAR19)
begin
if (VAR63==(VAR65-1)) VAR63 <= 2'h0;
end
else VAR63 <= VAR63 + 2'h1;
end
reg VAR46;
wire VAR62 = ~VAR34 ? 1'h0 :
VAR19 ? 1'b1 : VAR46;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR46 <= 1'h0;
else VAR46 <= VAR62;
reg [15:0] VAR44;
always @(posedge VAR61 or posedge VAR50)
if (VAR50) VAR44 <= 16'h0000;
else if (VAR19) VAR44 <= VAR8[VAR63];
assign VAR37 = VAR62 & (VAR60 != VAR17);
assign VAR22 = ~VAR34 |
~VAR46 |
((VAR60 != VAR17) & VAR59);
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn.pp.symbol.v | 1,341 | module MODULE1 (
input VAR6 ,
output VAR4 ,
input VAR1,
input VAR2 ,
input VAR3 ,
input VAR7 ,
input VAR5
);
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/DRSCFIFO_288x16_withCount.v | 2,701 | module MODULE1
(
input VAR5 ,
input VAR3 ,
input [287:0] VAR8 ,
input VAR4 ,
output VAR7 ,
output [287:0] VAR13 ,
input VAR15 ,
output VAR16 ,
output [3:0] VAR1
);
VAR9
VAR14
(
.clk (VAR5 ),
.VAR11 (VAR3 ),
.din (VAR8 ),
.VAR6 (VAR4 ),
.VAR12 (VAR7 ),
.dout (VAR13 ),
.VAR17 (VAR15 ),
.VAR10 (VAR16 ),
.VAR2 (VAR1 )
);
endmodule | gpl-3.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_auto_pc_0/synth/dma_loopback_auto_pc_0.v | 13,324 | module MODULE1 (
VAR20,
VAR72,
VAR23,
VAR73,
VAR87,
VAR69,
VAR100,
VAR3,
VAR107,
VAR48,
VAR95,
VAR86,
VAR105,
VAR27,
VAR114,
VAR49,
VAR47,
VAR43,
VAR18,
VAR26,
VAR113,
VAR4,
VAR68,
VAR56,
VAR108,
VAR91,
VAR67,
VAR59,
VAR2,
VAR101,
VAR14,
VAR71,
VAR7,
VAR21,
VAR83,
VAR33,
VAR53,
VAR31,
VAR98,
VAR30,
VAR62,
VAR51,
VAR96,
VAR77,
VAR17,
VAR54,
VAR78,
VAR8,
VAR1,
VAR16,
VAR44,
VAR25,
VAR63,
VAR52,
VAR40,
VAR10,
VAR13,
VAR76,
VAR19,
VAR102
);
input wire VAR20;
input wire VAR72;
input wire [11 : 0] VAR23;
input wire [31 : 0] VAR73;
input wire [7 : 0] VAR87;
input wire [2 : 0] VAR69;
input wire [1 : 0] VAR100;
input wire [0 : 0] VAR3;
input wire [3 : 0] VAR107;
input wire [2 : 0] VAR48;
input wire [3 : 0] VAR95;
input wire [3 : 0] VAR86;
input wire VAR105;
output wire VAR27;
input wire [31 : 0] VAR114;
input wire [3 : 0] VAR49;
input wire VAR47;
input wire VAR43;
output wire VAR18;
output wire [11 : 0] VAR26;
output wire [1 : 0] VAR113;
output wire VAR4;
input wire VAR68;
input wire [11 : 0] VAR56;
input wire [31 : 0] VAR108;
input wire [7 : 0] VAR91;
input wire [2 : 0] VAR67;
input wire [1 : 0] VAR59;
input wire [0 : 0] VAR2;
input wire [3 : 0] VAR101;
input wire [2 : 0] VAR14;
input wire [3 : 0] VAR71;
input wire [3 : 0] VAR7;
input wire VAR21;
output wire VAR83;
output wire [11 : 0] VAR33;
output wire [31 : 0] VAR53;
output wire [1 : 0] VAR31;
output wire VAR98;
output wire VAR30;
input wire VAR62;
output wire [31 : 0] VAR51;
output wire [2 : 0] VAR96;
output wire VAR77;
input wire VAR17;
output wire [31 : 0] VAR54;
output wire [3 : 0] VAR78;
output wire VAR8;
input wire VAR1;
input wire [1 : 0] VAR16;
input wire VAR44;
output wire VAR25;
output wire [31 : 0] VAR63;
output wire [2 : 0] VAR52;
output wire VAR40;
input wire VAR10;
input wire [31 : 0] VAR13;
input wire [1 : 0] VAR76;
input wire VAR19;
output wire VAR102;
VAR35 #(
.VAR93("VAR37"),
.VAR22(2),
.VAR36(0),
.VAR82(0),
.VAR79(12),
.VAR84(32),
.VAR57(32),
.VAR97(1),
.VAR29(1),
.VAR55(0),
.VAR111(1),
.VAR64(1),
.VAR24(1),
.VAR103(1),
.VAR65(1),
.VAR92(2)
) VAR66 (
.VAR20(VAR20),
.VAR72(VAR72),
.VAR23(VAR23),
.VAR73(VAR73),
.VAR87(VAR87),
.VAR69(VAR69),
.VAR100(VAR100),
.VAR3(VAR3),
.VAR107(VAR107),
.VAR48(VAR48),
.VAR95(VAR95),
.VAR86(VAR86),
.VAR38(1'VAR106),
.VAR105(VAR105),
.VAR27(VAR27),
.VAR5(12'VAR15),
.VAR114(VAR114),
.VAR49(VAR49),
.VAR47(VAR47),
.VAR61(1'VAR106),
.VAR43(VAR43),
.VAR18(VAR18),
.VAR26(VAR26),
.VAR113(VAR113),
.VAR34(),
.VAR4(VAR4),
.VAR68(VAR68),
.VAR56(VAR56),
.VAR108(VAR108),
.VAR91(VAR91),
.VAR67(VAR67),
.VAR59(VAR59),
.VAR2(VAR2),
.VAR101(VAR101),
.VAR14(VAR14),
.VAR71(VAR71),
.VAR7(VAR7),
.VAR58(1'VAR106),
.VAR21(VAR21),
.VAR83(VAR83),
.VAR33(VAR33),
.VAR53(VAR53),
.VAR31(VAR31),
.VAR98(VAR98),
.VAR42(),
.VAR30(VAR30),
.VAR62(VAR62),
.VAR50(),
.VAR51(VAR51),
.VAR74(),
.VAR70(),
.VAR85(),
.VAR6(),
.VAR88(),
.VAR96(VAR96),
.VAR90(),
.VAR75(),
.VAR80(),
.VAR77(VAR77),
.VAR17(VAR17),
.VAR81(),
.VAR54(VAR54),
.VAR78(VAR78),
.VAR32(),
.VAR94(),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR12(12'VAR15),
.VAR16(VAR16),
.VAR60(1'VAR106),
.VAR44(VAR44),
.VAR25(VAR25),
.VAR110(),
.VAR63(VAR63),
.VAR46(),
.VAR39(),
.VAR41(),
.VAR28(),
.VAR11(),
.VAR52(VAR52),
.VAR112(),
.VAR104(),
.VAR89(),
.VAR40(VAR40),
.VAR10(VAR10),
.VAR99(12'VAR15),
.VAR13(VAR13),
.VAR76(VAR76),
.VAR109(1'VAR9),
.VAR45(1'VAR106),
.VAR19(VAR19),
.VAR102(VAR102)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tap/sky130_fd_sc_lp__tap.behavioral.v | 1,152 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b.behavioral.pp.v | 1,924 | module MODULE1 (
VAR5 ,
VAR12 ,
VAR9 ,
VAR1,
VAR8,
VAR4 ,
VAR15
);
output VAR5 ;
input VAR12 ;
input VAR9 ;
input VAR1;
input VAR8;
input VAR4 ;
input VAR15 ;
wire VAR6 ;
wire VAR10 ;
wire VAR14;
not VAR7 (VAR6 , VAR9 );
or VAR2 (VAR10 , VAR6, VAR12 );
VAR13 VAR11 (VAR14, VAR10, VAR1, VAR8);
buf VAR3 (VAR5 , VAR14 );
endmodule | apache-2.0 |
julioamerico/prj_crc_ip | src/rtl/crc_ip.v | 2,615 | module MODULE1
(
output [31:0] VAR23,
output VAR14,
output VAR2,
input [31:0] VAR33,
input [31:0] VAR19,
input [ 2:0] VAR26,
input [ 1:0] VAR31,
input VAR1,
input VAR18,
input VAR15,
input VAR32,
input VAR20
);
wire [31:0] VAR34;
wire [31:0] VAR3;
wire [31:0] VAR8;
wire [ 7:0] VAR21;
wire VAR17;
wire VAR9;
wire [31:0] VAR5;
wire [ 1:0] VAR10;
wire [ 1:0] VAR7;
wire [ 1:0] VAR30;
wire VAR6;
wire VAR22;
wire VAR27;
wire VAR25;
wire VAR12;
wire VAR28;
VAR11 VAR16
(
.VAR23 ( VAR23 ),
.VAR14 ( VAR14 ),
.VAR2 ( VAR2 ),
.VAR5 ( VAR5 ),
.VAR10 ( VAR10 ),
.VAR7 ( VAR7 ),
.VAR30 ( VAR30 ),
.VAR6 ( VAR6 ),
.VAR22 ( VAR22 ),
.VAR27 ( VAR27 ),
.VAR25 ( VAR25 ),
.VAR12 ( VAR12 ),
.VAR28 ( VAR28 ),
.VAR24 ( VAR24 ),
.VAR33 ( VAR33 ),
.VAR19 ( VAR19 ),
.VAR26 ( VAR26 ),
.VAR31 ( VAR31 ),
.VAR1 ( VAR1 ),
.VAR18 ( VAR18 ),
.VAR15 ( VAR15 ),
.VAR32 ( VAR32 ),
.VAR20 ( VAR20 ),
.VAR34 ( VAR34 ),
.VAR3 ( VAR3 ),
.VAR8 ( VAR8 ),
.VAR21 ( VAR21 ),
.VAR17 ( VAR17 ),
.VAR9 ( VAR9 )
);
VAR29 VAR4
(
.VAR34 ( VAR34 ),
.VAR3 ( VAR3 ),
.VAR8 ( VAR8 ),
.VAR21 ( VAR21 ),
.VAR17 ( VAR17 ),
.VAR9 ( VAR9 ),
.VAR5 ( VAR5 ),
.VAR10 ( VAR10 ),
.VAR7 ( VAR7 ),
.VAR30 ( VAR30 ),
.VAR6 ( VAR6 ),
.VAR22 ( VAR22 ),
.VAR27 ( VAR27 ),
.VAR25 ( VAR25 ),
.VAR12 ( VAR12 ),
.VAR28 ( VAR28 ),
.VAR24 ( VAR24 ),
.clk ( VAR20 ),
.VAR13 ( VAR32 )
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi.functional.v | 1,551 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR9 ,
VAR4
);
output VAR2 ;
input VAR5 ;
input VAR9 ;
input VAR4;
wire VAR6 ;
wire VAR11 ;
wire VAR8;
not VAR7 (VAR6 , VAR4 );
and VAR10 (VAR11 , VAR5, VAR9 );
nor VAR1 (VAR8, VAR6, VAR11 );
buf VAR3 (VAR2 , VAR8 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v | 8,157 | module MODULE1 #
(
parameter VAR46 = 100,
parameter VAR4 = 33,
parameter VAR36 = 3,
parameter VAR12 = 12,
parameter VAR10 = 2,
parameter VAR15 = 16,
parameter VAR44 = 4,
parameter VAR38 = "VAR54"
)
(
VAR33, VAR37, VAR32, VAR40, VAR19, VAR7, VAR51, VAR43, VAR20,
VAR34, VAR50, VAR11,
rst, clk, VAR17, VAR25, VAR14, VAR22, VAR48,
VAR52, VAR23, VAR27, VAR28, VAR2
);
input rst;
input clk;
input VAR17;
input VAR25;
input VAR14;
wire VAR57 = VAR17 && ~VAR25 && ~VAR14;
reg VAR30;
reg VAR41;
output wire VAR33;
assign VAR33 = VAR30;
input [VAR4-1:0] VAR22;
input [2:0] VAR48;
input VAR52;
input VAR23;
input VAR27;
reg [VAR4-1:0] VAR9;
reg [VAR4-1:0] VAR8;
reg [2:0] VAR56;
reg [2:0] VAR45;
reg VAR3;
reg VAR1;
reg VAR13;
reg VAR58;
reg VAR5;
reg VAR47;
wire [VAR4-1:0] VAR49 = ({VAR4{VAR30}} & VAR22) | ({VAR4{VAR41}} & VAR9);
wire [VAR4-1:0] VAR31 = ({VAR4{VAR30}} & VAR9) | ({VAR4{VAR41}} & VAR8);
wire [2:0] VAR26 = ({3{VAR30}} & VAR48) | ({3{VAR41}} & VAR56);
wire [2:0] VAR53 = ({3{VAR30}} & VAR56) | ({3{VAR41}} & VAR45);
wire VAR24 = (VAR30 & VAR52) | (VAR41 & VAR3);
wire VAR42 = (VAR30 & VAR3) | (VAR41 & VAR1);
wire VAR39 = (VAR30 & VAR23) | (VAR41 & VAR13);
wire VAR55 = (VAR30 & VAR13) | (VAR41 & VAR58);
wire VAR18 = ~rst && ((VAR30 & VAR27 )| (VAR41 & VAR5));
wire VAR21 = ~rst && ((VAR30 & VAR5 )| (VAR41 & VAR47));
always @(posedge clk) begin
end
wire VAR16 = VAR47 && VAR30;
output wire VAR37;
assign VAR37 = VAR16;
output wire [VAR10-1:0] VAR32;
output wire [VAR36-1:0] VAR40;
output wire [VAR15-1:0] VAR19;
output wire [VAR12-1:0] VAR7;
output wire VAR51;
output wire [2:0] VAR43;
output wire VAR20;
assign VAR7 = ({VAR12{VAR30}} & VAR9[0+:VAR12]) |
({VAR12{VAR41}} & VAR8[0+:VAR12]);
generate
begin
if (VAR38 == "VAR29")
begin
assign VAR19 = ({VAR15{VAR30}} & VAR9[VAR12+VAR36+:VAR15]) |
({VAR15{VAR41}} & VAR8[VAR12+VAR36+:VAR15]);
assign VAR40 = ({VAR36{VAR30}} & VAR9[VAR12+:VAR36]) |
({VAR36{VAR41}} & VAR8[VAR12+:VAR36]);
end
else
begin
assign VAR19 = ({VAR15{VAR30}} & VAR9[VAR12+:VAR15]) |
({VAR15{VAR41}} & VAR8[VAR12+:VAR15]);
assign VAR40 = ({VAR36{VAR30}} & VAR9[VAR12+VAR15+:VAR36]) |
({VAR36{VAR41}} & VAR8[VAR12+VAR15+:VAR36]);
end
end
endgenerate
assign VAR32 = (VAR44 == 1)
? 1'b0
: (({VAR10{VAR30}} & VAR9[VAR12+VAR15+VAR36+:VAR10]) |
({VAR10{VAR41}} & VAR8[VAR12+VAR15+VAR36+:VAR10]));
assign VAR51 = (VAR30 & VAR3) | (VAR41 & VAR1);
assign VAR43 = ({3{VAR30}} & VAR56) | ({3{VAR41}} & VAR45);
assign VAR20 = (VAR30 & VAR13) | (VAR41 & VAR58);
wire VAR6 = VAR16 && VAR30;
wire rd = VAR45[1:0] == 2'b01;
wire wr = VAR45[1:0] == 2'b00;
wire VAR35 = VAR45[1:0] == 2'b11;
wire write = wr || VAR35;
output wire VAR34;
assign VAR34 = VAR6 && rd;
output wire VAR50;
assign VAR50 = VAR6 && write;
input [3:0] VAR28;
input [3:0] VAR2;
output wire [3:0] VAR11;
assign VAR11 = ~write ? VAR2 : VAR28;
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o.behavioral.v | 1,705 | module MODULE1 (
VAR11 ,
VAR3,
VAR9,
VAR5 ,
VAR6
);
output VAR11 ;
input VAR3;
input VAR9;
input VAR5 ;
input VAR6 ;
supply1 VAR10;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR14 ;
wire VAR12 ;
wire VAR13 ;
wire VAR16;
and VAR7 (VAR12 , VAR5, VAR6 );
nor VAR1 (VAR13 , VAR3, VAR9 );
or VAR15 (VAR16, VAR13, VAR12);
buf VAR4 (VAR11 , VAR16 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15.pp.blackbox.v | 1,309 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR4,
VAR3,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s.symbol.v | 1,322 | module MODULE1 (
input VAR1,
output VAR4
);
supply1 VAR2;
supply0 VAR3;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_top.v | 14,194 | module MODULE1 (
VAR17,
VAR10,
interrupt,
VAR15,
VAR91,
VAR18,
VAR2,
VAR69,
VAR64,
VAR88,
VAR3,
VAR81,
VAR70,
VAR104,
VAR60,
VAR87,
VAR34,
VAR101,
VAR98,
VAR56,
VAR74,
VAR6,
VAR29,
VAR61,
VAR31,
VAR67,
VAR45,
VAR48,
VAR97,
VAR71,
VAR75,
VAR50,
VAR68,
VAR62,
VAR102,
VAR40,
VAR85,
VAR52,
VAR38,
VAR109,
VAR82,
VAR108,
VAR72,
VAR8,
VAR107,
VAR57,
VAR54,
VAR100
);
input VAR17; input VAR10;
input [VAR76] interrupt; VAR39
input [VAR46] VAR15; input VAR91; VAR39
input [VAR46] VAR18; input VAR2; input VAR69; input VAR64; VAR39
input [VAR46] VAR88; input VAR3; input VAR81; input VAR70;
input [VAR46] VAR104; input [VAR46] VAR60; input [VAR12] VAR87; input VAR34; input [VAR13] VAR101; input [VAR32] VAR98; input VAR56; input VAR74; input VAR6;
output VAR29; wire VAR29;
output [VAR51] VAR61; reg [VAR51] VAR61;
output [VAR46] VAR31; wire [VAR46] VAR31;
output [VAR46] VAR67; wire [VAR46] VAR67;
output [VAR46] VAR45; wire [VAR46] VAR45;
output [VAR46] VAR48; wire [VAR46] VAR48;
output VAR97; wire VAR97;
output [VAR12] VAR71; wire [VAR12] VAR71;
output VAR75; wire VAR75;
output VAR50; wire VAR50;
output [VAR13] VAR68; wire [VAR13] VAR68;
output VAR62; wire VAR62;
output [VAR32] VAR102; wire [VAR32] VAR102;
output [VAR46] VAR40; wire [VAR46] VAR40;
output [VAR46] VAR85; wire [VAR46] VAR85;
output VAR52; wire VAR52;
output [VAR12] VAR38; wire [VAR12] VAR38;
output VAR109; wire VAR109;
output VAR82; wire VAR82;
output [VAR13] VAR108; wire [VAR13] VAR108;
output VAR72; wire VAR72;
output [VAR32] VAR8; wire [VAR32] VAR8;
output VAR107; wire VAR107;
output VAR57; wire VAR57;
output VAR54; wire VAR54;
output [VAR46] VAR100; wire [VAR46] VAR100;
wire [VAR36] VAR23;
wire [VAR36] VAR26;
wire VAR35;
wire [2:0] VAR24;
wire [2:0] VAR66;
wire VAR65;
wire VAR83;
wire [VAR103] VAR7; wire VAR42; wire VAR11; wire [VAR27] VAR86; wire VAR89; VAR58 VAR90
wire VAR59; VAR39
VAR94 VAR30 (
.VAR17 (VAR17),
.VAR33 (VAR14),
.VAR10 (VAR10),
.interrupt (interrupt),
.VAR15 (VAR15),
.VAR91 (VAR91),
.VAR96 (VAR65),
.VAR35 (VAR35),
.VAR26 (VAR26),
.VAR66 (VAR66),
.VAR18 (VAR18),
.VAR2 (VAR2),
.VAR69 (VAR69),
.VAR64 (VAR64),
.VAR88 (VAR88),
.VAR3 (VAR3),
.VAR81 (VAR81),
.VAR70 (VAR70),
.VAR7 (VAR7),
.VAR42 (VAR42),
.VAR11 (VAR11),
.VAR86 (VAR86),
.VAR89 (VAR89),
.VAR59 (VAR59),
.VAR23 (VAR23),
.VAR24 (VAR24),
.VAR29 (VAR29),
.VAR61 (VAR61),
.VAR31 (VAR31),
.VAR67 (VAR67),
.VAR45 (VAR45),
.VAR48 (VAR48),
.VAR97 (VAR97),
.VAR71 (VAR71),
.VAR75 (VAR75),
.VAR50 (VAR50),
.VAR68 (VAR68),
.VAR62 (VAR62),
.VAR102 (VAR102),
.VAR40 (VAR40),
.VAR85 (VAR85),
.VAR52 (VAR52),
.VAR38 (VAR38),
.VAR109 (VAR109),
.VAR82 (VAR82),
.VAR108 (VAR108),
.VAR72 (VAR72),
.VAR8 (VAR8)
);
wire VAR28;
wire [VAR46] VAR55;
VAR77 VAR20 (.VAR17 (VAR17),
.VAR10 (VAR10),
.VAR9 (VAR6 & VAR104[13]),
.VAR25 (VAR34),
.VAR53 (VAR87),
.VAR79 (VAR60),
.VAR95 (VAR104),
.VAR7 (VAR7),
.VAR86 (VAR86),
.VAR89 (VAR89),
.VAR59 (VAR59),
.VAR42 (VAR42),
.VAR11 (VAR11),
.VAR106 (VAR28),
.VAR19 (VAR55));
assign VAR28 = 0;
assign VAR55 = 0;
wire VAR47;
wire [VAR46] VAR21;
assign VAR107 = VAR104[13] ? VAR28 : VAR47;
assign VAR100 = VAR104[13] ? VAR55 : VAR21;
VAR92 VAR44 (
.VAR17 (VAR17),
.VAR10 (VAR10),
.VAR63 (VAR104),
.VAR99 (VAR6 & ~VAR104[13]),
.VAR105 (VAR74 & ~VAR104[13]),
.VAR1 (VAR34),
.VAR78 (VAR87),
.VAR80 (VAR60),
.VAR93 (VAR101),
.VAR4 (VAR98),
.VAR84 (VAR56),
.VAR37 (VAR54),
.VAR73 (VAR57),
.VAR111 (VAR47),
.VAR43 (VAR21)
);
VAR110 VAR110 (
.VAR49 (VAR23),
.VAR5 (VAR24),
.VAR41 (VAR35),
.VAR16 (VAR26),
.VAR22 (VAR66),
.VAR65 (VAR65),
.VAR83 (VAR83)
);
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o.functional.v | 2,043 | module MODULE1 (
VAR5,
VAR16,
VAR4 ,
VAR9 ,
VAR11 ,
VAR8 ,
VAR15
);
input VAR5;
input VAR16;
output VAR4 ;
input VAR9 ;
input VAR11 ;
input VAR8 ;
input VAR15 ;
wire VAR15 VAR7 ;
wire VAR15 VAR14 ;
wire VAR1 ;
wire VAR17;
and VAR3 (VAR7 , VAR8, VAR15 );
and VAR10 (VAR14 , VAR9, VAR11 );
or VAR13 (VAR1 , VAR14, VAR7 );
VAR12 VAR6 (VAR17, VAR1, VAR5, VAR16);
buf VAR2 (VAR4 , VAR17 );
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/export/export_master.v | 1,870 | module MODULE1 (
clk,
reset,
address,
read,
VAR24,
VAR13,
write,
VAR22,
VAR3,
VAR2,
VAR12,
VAR21,
VAR10,
VAR18,
VAR4,
VAR16,
VAR6,
VAR15,
VAR14,
VAR1,
VAR7,
VAR17,
interrupt,
VAR5
);
parameter VAR11 = 4;
parameter VAR19 = 32;
parameter VAR23 = 32;
parameter VAR8 = 1;
localparam VAR9 = VAR11 * 8;
localparam VAR20 = VAR19 - VAR23;
input clk;
input reset;
input [VAR23-1:0] address;
input read;
output [VAR9-1:0] VAR24;
output VAR13;
input write;
input [VAR9-1:0] VAR22;
input [VAR8-1:0] VAR3;
input VAR21;
input [VAR11-1:0] VAR2;
output VAR12;
output interrupt;
output [VAR19-1:0] VAR10;
output VAR18;
input [VAR9-1:0] VAR4;
input VAR16;
output VAR6;
output [VAR9-1:0] VAR15;
output [VAR8-1:0] VAR14;
output VAR1;
output [VAR11-1:0] VAR7;
input VAR17;
input VAR5;
assign VAR10 = address << VAR20;
assign VAR18 = read;
assign VAR24 = VAR4;
assign VAR13 = VAR16;
assign VAR6 = write;
assign VAR15 = VAR22;
assign VAR14 = VAR3;
assign VAR1 = VAR21;
assign VAR7 = VAR2;
assign interrupt = VAR5;
assign VAR12 = VAR17;
endmodule | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/float_mega/float_cmp/float_cmp.v | 16,491 | module MODULE1
(
VAR38,
VAR31,
VAR82,
VAR61,
VAR53,
VAR10) ;
output VAR38;
output VAR31;
input VAR82;
input VAR61;
input [31:0] VAR53;
input [31:0] VAR10;
tri1 VAR82;
reg VAR67;
reg VAR77;
wire VAR20;
wire VAR55;
wire VAR52;
wire VAR39;
wire VAR70;
wire VAR68;
wire VAR48;
wire VAR45;
wire VAR27;
wire VAR72;
wire VAR16;
wire VAR49;
wire VAR84;
wire VAR15;
wire VAR2;
wire [30:0] VAR62;
wire VAR26;
wire VAR59;
wire VAR6;
wire VAR1;
wire VAR54;
wire VAR78;
wire [30:0] VAR46;
wire VAR34;
wire VAR8;
wire VAR23;
wire VAR36;
wire VAR37;
wire [7:0] VAR75;
wire VAR11;
wire VAR24;
wire [7:0] VAR47;
wire [3:0] VAR73;
wire [3:0] VAR51;
wire VAR76;
wire VAR30;
wire VAR4;
wire [3:0] VAR56;
wire [3:0] VAR42;
wire VAR18;
wire VAR87;
wire VAR40;
wire VAR71;
wire VAR60;
wire [7:0] VAR5;
wire VAR80;
wire VAR7;
wire [7:0] VAR33;
wire [2:0] VAR69;
wire [3:0] VAR41;
wire VAR32;
wire VAR35;
wire VAR65;
wire VAR79;
wire VAR57;
wire VAR22;
wire VAR50;
wire VAR3;
wire VAR58;
wire VAR29;
wire VAR44;
wire [1:0] VAR64;
wire [1:0] VAR83;
wire [1:0] VAR21;
wire [22:0] VAR13;
wire [1:0] VAR9;
wire [1:0] VAR14;
wire [1:0] VAR19;
wire [22:0] VAR17;
wire VAR25;
wire VAR28;
wire VAR63;
wire VAR85;
wire VAR43;
wire VAR81;
wire VAR66;
wire VAR12;
wire VAR74;
wire VAR86; | apache-2.0 |
eecsninja/duinocube-core | common/collision_table.v | 3,419 | module MODULE1(clk, reset,
VAR26, VAR5, VAR13,
wr, VAR23, addr, VAR14, VAR28);
input clk; input reset;
input VAR26; input [VAR9-1:0] VAR5; input [VAR21-1:0] VAR13;
input wr; input [1:0] VAR23; input [VAR9-1:0] addr; input [VAR29-1:0] VAR14; output [VAR29-1:0] VAR28;
assign VAR28 = VAR18 ? VAR33 :
(VAR1 ? VAR12[VAR10] : 0);
wire VAR1 = (addr >= VAR2) &
(addr < VAR2 + VAR11);
wire [VAR9-1:0] VAR10 = addr - VAR2;
wire VAR30 = reset | (wr & (addr == VAR22));
reg [VAR29-1:0] VAR12[VAR11-1:0];
genvar VAR24;
generate
for (VAR24 = 0; VAR24 < VAR11; VAR24 = VAR24 + 1) begin : VAR27
always @ (posedge VAR30 or posedge clk) begin
if (VAR30)
VAR12[VAR24] <= 0;
end
else if (VAR26 & VAR5 / VAR29 == VAR24)
VAR12[VAR24][VAR5 % VAR29] <= 1;
end
end
endgenerate
wire VAR18 = (addr >= VAR32) &
(addr < VAR32 + VAR3);
wire [VAR29-1:0] VAR33;
VAR17 VAR16(
.VAR8(clk),
.VAR15(VAR26),
.VAR19(VAR5[0] ? 'b10 : 'b01),
.VAR31(VAR5 / 2),
.VAR25({VAR13[VAR20-1:0], VAR13[VAR20-1:0]}),
.VAR6(0), .VAR4(addr - VAR32),
.VAR7(VAR33));
endmodule | gpl-3.0 |
MeshSr/onetswitch45 | ons45-app52-ref_ofshw/vivado/onets_7045_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/output_queues.v | 10,926 | module MODULE1
parameter VAR111=VAR41/8,
parameter VAR43 = 2,
parameter VAR24 = 4,
parameter VAR80 = 8)
( output [VAR41-1:0] VAR115,
output [VAR111-1:0] VAR73,
input VAR97,
output VAR103,
output [VAR41-1:0] VAR91,
output [VAR111-1:0] VAR38,
input VAR26,
output VAR29,
output [VAR41-1:0] VAR9,
output [VAR111-1:0] VAR110,
input VAR77,
output VAR83,
output [VAR41-1:0] VAR49,
output [VAR111-1:0] VAR127,
input VAR61,
output VAR108,
output [VAR41-1:0] VAR60,
output [VAR111-1:0] VAR87,
input VAR50,
output VAR81,
output [VAR41-1:0] VAR22,
output [VAR111-1:0] VAR64,
output VAR25,
input VAR5,
output [VAR41-1:0] VAR123,
output [VAR111-1:0] VAR11,
output VAR100,
input VAR119,
output [VAR41-1:0] VAR102,
output [VAR111-1:0] VAR51,
output VAR28,
input VAR52,
input [VAR41-1:0] VAR8,
input [VAR111-1:0] VAR106,
output VAR42,
input VAR82,
input [31:0] VAR23 ,
input [31:0] VAR104 ,
input VAR116 ,
input VAR112 ,
output VAR4 ,
output [31:0] VAR69 ,
input clk,
input reset);
wire VAR95;
assign VAR42=!VAR95;
wire [VAR41-1:0]VAR113;
wire [VAR111-1:0]VAR92;
wire [7:0]VAR63;
wire [VAR41-1:0]VAR31[7:0];
wire [VAR111-1:0]VAR36[7:0];
wire [7:0]VAR66;
wire [7:0]VAR53;
reg [7:0]VAR98;
assign VAR102=VAR31[7];
assign VAR123=VAR31[6];
assign VAR22=VAR31[5];
assign VAR60=VAR31[4];
assign VAR49=VAR31[3];
assign VAR9=VAR31[2];
assign VAR91=VAR31[1];
assign VAR115=VAR31[0];
assign VAR51=VAR36[7];
assign VAR11=VAR36[6];
assign VAR64=VAR36[5];
assign VAR87=VAR36[4];
assign VAR127=VAR36[3];
assign VAR110=VAR36[2];
assign VAR38=VAR36[1];
assign VAR73=VAR36[0];
assign VAR28=VAR53[7];
assign VAR100=VAR53[6];
assign VAR25=VAR53[5];
assign VAR81=VAR53[4];
assign VAR108=VAR53[3];
assign VAR83=VAR53[2];
assign VAR29=VAR53[1];
assign VAR103=VAR53[0];
assign VAR66[7]=VAR52;
assign VAR66[6]=VAR119;
assign VAR66[5]=VAR5;
assign VAR66[4]=VAR50;
assign VAR66[3]=VAR61;
assign VAR66[2]=VAR77;
assign VAR66[1]=VAR26;
assign VAR66[0]=VAR97;
wire [5:0]VAR124;
wire [5:0]VAR33;
wire [5:0]VAR34;
wire [5:0]VAR78;
wire [5:0]VAR45;
wire [5:0]VAR84;
wire [5:0]VAR70[7:0];
wire [31:0]VAR76[7:0];
wire [5:0]VAR7[7:0];
wire [5:0]VAR17=VAR70[0] ;
wire [5:0]VAR15=VAR70[1] ;
wire [5:0]VAR14=VAR70[2] ;
wire [5:0]VAR101=VAR70[3] ;
wire [5:0]VAR79=VAR70[4] ;
wire [5:0]VAR54=VAR70[5] ;
wire [5:0]VAR109=VAR70[6] ;
wire [5:0]VAR44=VAR70[7] ;
wire [31:0]VAR30=VAR76[0] ;
wire [31:0]VAR40=VAR76[1] ;
wire [31:0]VAR90=VAR76[2] ;
wire [31:0]VAR125=VAR76[3] ;
wire [31:0]VAR94=VAR76[4] ;
wire [31:0]VAR16=VAR76[5] ;
wire [31:0]VAR47=VAR76[6] ;
wire [31:0]VAR39=VAR76[7] ;
wire [5:0]VAR96=VAR7[0] ;
wire [5:0]VAR72=VAR7[1] ;
wire [5:0]VAR114=VAR7[2] ;
wire [5:0]VAR85=VAR7[3] ;
wire [5:0]VAR99=VAR7[4] ;
wire [5:0]VAR1=VAR7[5] ;
wire [5:0]VAR27=VAR7[6] ;
wire [5:0]VAR126=VAR7[7] ;
VAR93 VAR93
(
.VAR23 (VAR23),
.VAR104 (VAR104),
.VAR116 (VAR116),
.VAR112 (VAR112),
.VAR4 (VAR4),
.VAR69 (VAR69),
.VAR124(VAR124),
.VAR33(VAR33),
.VAR34(VAR34),
.VAR78(VAR78),
.VAR45(VAR45),
.VAR84(VAR84),
.clk(clk),
.reset(reset),
.VAR17 (VAR17),
.VAR15 (VAR15),
.VAR14 (VAR14),
.VAR101 (VAR101),
.VAR79 (VAR79),
.VAR54 (VAR54),
.VAR109 (VAR109),
.VAR44 (VAR44),
.VAR117 (VAR30),
.VAR71 (VAR40),
.VAR6 (VAR90),
.VAR67 (VAR125),
.VAR55 (VAR94),
.VAR105 (VAR16),
.VAR88 (VAR47),
.VAR12 (VAR39),
.VAR96 (VAR96),
.VAR72 (VAR72),
.VAR114 (VAR114),
.VAR85 (VAR85),
.VAR99 (VAR99),
.VAR1 (VAR1),
.VAR27 (VAR27),
.VAR126 (VAR126)
);
generate
genvar VAR58;
for(VAR58=0; VAR58<8; VAR58=VAR58+1) begin:VAR3
VAR48
.VAR41(VAR41),
.VAR111(VAR111),
.VAR65(VAR58),
.VAR56(VAR56)
)VAR37
(
.clk (clk ),
.reset (reset ),
.VAR8 (VAR113 ),
.VAR106 (VAR92 ),
.VAR42 (VAR63[VAR58] ),
.VAR82 (VAR98[VAR58] ),
.VAR31 (VAR31[VAR58]),
.VAR36 (VAR36[VAR58]),
.VAR66 (VAR66[VAR58] ),
.VAR53 (VAR53[VAR58] ),
.VAR124(VAR124),
.VAR33(VAR33),
.VAR34(VAR34),
.VAR78(VAR78),
.VAR45(VAR45),
.VAR84(VAR84),
.VAR70 (VAR70[VAR58] ),
.VAR76 (VAR76[VAR58] ),
.VAR7 (VAR7[VAR58] )
);
end
endgenerate
reg [7:0]VAR18;
reg VAR122;
reg [7:0] VAR62;
reg [7:0]VAR20;
VAR68 #(.VAR35(VAR41+VAR111),.VAR32(4))
VAR19
( .din ({VAR106, VAR8}), .VAR46 (VAR82), .VAR2 (VAR122), .dout ({VAR92, VAR113}),
.VAR10 (),
.VAR59 (),
.VAR107 (VAR95),
.VAR120 (VAR74),
.reset (reset),
.clk (clk)
);
localparam VAR121=1;
localparam VAR57=2;
localparam VAR89=3;
localparam VAR118=4;
reg [2:0]VAR75,VAR21;
always@(posedge clk)
if(reset) VAR75<=0;
else VAR75<=VAR21;
always@(*)
begin
VAR21=0;
case(VAR75)
VAR121:
if(VAR82 && VAR106==VAR13) VAR21=VAR57;
end
else VAR21=VAR121;
VAR57:
if(VAR82 && VAR106==0) VAR21=VAR89;
else VAR21=VAR57;
VAR89:
if(VAR82 && VAR106!=0) VAR21=VAR118;
else VAR21=VAR89;
VAR118:VAR21=VAR121;
default:VAR21=VAR121;
endcase
end
always@(posedge clk)
if(reset)
VAR62<=0;
else if(VAR75==VAR121 && VAR82 && VAR106==VAR13)
VAR62<=VAR8[VAR86 + 8 - 1:VAR86];
else if(VAR75==VAR118)
VAR62<=0;
always@(posedge clk)
if(reset) VAR122<=0;
else VAR122<=VAR82;
always@(posedge clk)
if(reset) VAR98<=0;
else if(VAR122) VAR98<= VAR62;
else VAR98<=0;
endmodule | lgpl-2.1 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_fetchvertex.v | 5,691 | module MODULE1(
input VAR28,
input VAR7,
input VAR31,
output reg VAR16,
output [31:0] VAR30,
output [2:0] VAR48,
output VAR57,
output reg VAR49,
input VAR38,
input [31:0] VAR29,
input [6:0] VAR47,
input [6:0] VAR20,
input [28:0] VAR4,
input signed [11:0] VAR43,
input signed [11:0] VAR52,
input [10:0] VAR33,
input [10:0] VAR50,
output reg VAR17,
input VAR35,
output reg signed [17:0] VAR42,
output reg signed [17:0] VAR39,
output reg signed [17:0] VAR34,
output reg signed [17:0] VAR54,
output reg signed [17:0] VAR2,
output reg signed [17:0] VAR10,
output reg signed [17:0] VAR8,
output reg signed [17:0] VAR26,
output reg signed [11:0] VAR3,
output reg signed [11:0] VAR15
);
assign VAR48 = 3'd0;
assign VAR57 = VAR49;
reg [28:0] VAR56;
reg [1:0] VAR5;
reg VAR51;
reg VAR9;
reg VAR6;
parameter VAR11 = 2'd0;
parameter VAR40 = 2'd1;
parameter VAR25 = 2'd2;
parameter VAR44 = 2'd3;
reg VAR36;
assign VAR30 = {VAR56, VAR36, 2'b00};
always @(posedge VAR28) begin
if(VAR38) begin
if(VAR36) begin
case(VAR5)
VAR11: VAR39 <= VAR29[17:0];
VAR40: VAR54 <= VAR29[17:0];
VAR25: VAR10 <= VAR29[17:0];
VAR44: VAR26 <= VAR29[17:0];
endcase
end else begin
case(VAR5)
VAR11: VAR42 <= VAR29[17:0];
VAR40: VAR34 <= VAR29[17:0];
VAR25: VAR2 <= VAR29[17:0];
VAR44: VAR8 <= VAR29[17:0];
endcase
end
end
if(VAR6) begin
VAR42 <= VAR34;
VAR39 <= VAR54;
VAR2 <= VAR8;
VAR10 <= VAR26;
end
end
always @(posedge VAR28) begin
if(VAR7) begin
VAR49 <= 1'b0;
VAR9 <= 1'b0;
VAR36 <= 1'b0;
end else begin
VAR49 <= 1'b0;
VAR9 <= 1'b0;
if(VAR51 & ~VAR9) begin
VAR49 <= 1'b1;
if(VAR38) begin
VAR36 <= ~VAR36;
if(VAR36) begin
VAR9 <= 1'b1;
VAR49 <= 1'b0;
end
end
end
end
end
reg VAR12;
reg VAR45;
reg VAR19;
reg VAR46;
reg VAR14;
reg [6:0] VAR23;
reg [6:0] VAR55;
always @(posedge VAR28) begin
if(VAR12) begin
VAR3 = VAR43 - {1'b0, VAR33};
VAR15 = VAR52 - {1'b0, VAR50};
VAR23 = 7'd0;
VAR55 = 7'd0;
end else begin
case({VAR45, VAR19})
2'b10: begin
VAR3 = VAR3 + {1'b0, VAR33};
VAR23 = VAR23 + 7'd1;
end
2'b01: begin
VAR3 = VAR43 - {1'b0, VAR33};
VAR23 = 7'd0;
end
default:;
endcase
case({VAR46, VAR14})
2'b10: begin
VAR15 = VAR15 + {1'b0, VAR50};
VAR55 = VAR55 + 7'd1;
end
2'b01: begin
VAR15 = VAR15 - {1'b0, VAR50};
VAR55 = VAR55 - 7'd1;
end
default:;
endcase
end
VAR56 = VAR4 + {VAR55, VAR23};
end
reg [2:0] state;
reg [2:0] VAR24;
parameter VAR18 = 3'd0;
parameter VAR1 = 3'd1;
parameter VAR22 = 3'd2;
parameter VAR21 = 3'd3;
parameter VAR32 = 3'd4;
parameter VAR13 = 3'd5;
parameter VAR41 = 3'd6;
always @(posedge VAR28) begin
if(VAR7)
state <= VAR18;
end
else
state <= VAR24;
end
wire VAR27 = VAR23 == VAR47;
wire VAR53 = VAR55 == VAR20;
always @(*) begin
VAR5 = 2'VAR37;
VAR51 = 1'b0;
VAR6 = 1'b0;
VAR12 = 1'b0;
VAR45 = 1'b0;
VAR19 = 1'b0;
VAR46 = 1'b0;
VAR14 = 1'b0;
VAR16 = 1'b1;
VAR17 = 1'b0;
VAR24 = state;
case(state)
VAR18: begin
VAR16 = 1'b0;
VAR12 = 1'b1;
if(VAR31)
VAR24 = VAR1;
end
VAR1: begin
VAR5 = VAR11;
VAR51 = 1'b1;
if(VAR9) begin
VAR46 = 1'b1;
VAR24 = VAR21;
end
end
VAR21: begin
VAR5 = VAR25;
VAR51 = 1'b1;
if(VAR9) begin
VAR45 = 1'b1;
VAR14 = 1'b1;
VAR24 = VAR22;
end
end
VAR22: begin
VAR5 = VAR40;
VAR51 = 1'b1;
if(VAR9) begin
VAR46 = 1'b1;
VAR24 = VAR32;
end
end
VAR32: begin
VAR5 = VAR44;
VAR51 = 1'b1;
if(VAR9)
VAR24 = VAR13;
end
VAR13: begin
VAR17 = 1'b1;
if(VAR35)
VAR24 = VAR41;
end
VAR41: begin
if(VAR27) begin
if(VAR53)
VAR24 = VAR18;
end
else begin
VAR19 = 1'b1;
VAR24 = VAR1;
end
end else begin
VAR45 = 1'b1;
VAR14 = 1'b1;
VAR6 = 1'b1;
VAR24 = VAR22;
end
end
endcase
end
endmodule | lgpl-3.0 |
cliffordwolf/picorv32 | scripts/quartus/system.v | 2,834 | module MODULE1 (
input clk,
input VAR19,
output VAR11,
output reg [7:0] VAR18,
output reg VAR6
);
parameter VAR7 = 0;
parameter VAR12 = 4096;
wire VAR9;
wire VAR13;
reg VAR3;
wire [31:0] VAR4;
wire [31:0] VAR8;
wire [3:0] VAR2;
reg [31:0] VAR14;
wire VAR5;
wire VAR20;
wire [31:0] VAR1;
wire [31:0] VAR10;
wire [3:0] VAR15;
VAR17 VAR16 (
.clk (clk ),
.VAR19 (VAR19 ),
.VAR11 (VAR11 ),
.VAR9 (VAR9 ),
.VAR13 (VAR13 ),
.VAR3 (VAR3 ),
.VAR4 (VAR4 ),
.VAR8 (VAR8 ),
.VAR2 (VAR2 ),
.VAR14 (VAR14 ),
.VAR5 (VAR5 ),
.VAR20(VAR20),
.VAR1 (VAR1 ),
.VAR10(VAR10),
.VAR15(VAR15)
);
reg [31:0] memory [0:VAR12-1]; | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3b/sky130_fd_sc_ls__or3b.blackbox.v | 1,291 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR7 ,
VAR2
);
output VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR2;
supply1 VAR3;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
jotego/jt12 | hdl/jt12_pg_sum.v | 1,585 | module MODULE1 (
input [ 3:0] VAR6,
input [19:0] VAR5,
input VAR1,
input signed [5:0] VAR4,
input [16:0] VAR2,
output reg [19:0] VAR7,
output reg [ 9:0] VAR9
);
reg [16:0] VAR8;
reg [19:0] VAR3;
always @(*) begin
VAR8 = VAR2 + {{11{VAR4[5]}},VAR4};
VAR3 = ( VAR6==4'd0 ) ? {4'b0,VAR8[16:1]} : ({3'd0,VAR8} * VAR6);
VAR7 = VAR1 ? 20'd0 : (VAR5 + { VAR3});
VAR9 = VAR7[19:10];
end
endmodule MODULE1 | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_qp.v | 2,263 | module MODULE1(
clk ,
VAR5 ,
VAR4 ,
VAR2 ,
VAR3 ,
VAR1 ,
VAR7
);
input clk ;
input VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR1 ;
output VAR7 ;
reg VAR7 ;
wire VAR6 = !(VAR4 ||VAR2 ||VAR3 );
always@(posedge clk or negedge VAR5) begin
if(!VAR5)
VAR7 <= 1'b0 ;
end
else if(VAR6) VAR7 <= VAR1 ; else
VAR7 <= 1'b0 ;
end
endmodule | gpl-3.0 |
travisg/cpu | rtl/cpu/nopipeline/alu.v | 1,840 | module MODULE1(
input [3:0] VAR1,
input [31:0] VAR2,
input [31:0] VAR4,
output reg [31:0] VAR5
);
always @(VAR1 or VAR2 or VAR4)
begin
case (VAR1)
4'b0000: VAR5 = VAR2 + VAR4;
4'b0001: VAR5 = VAR2 - VAR4;
4'b0010: VAR5 = VAR4 - VAR2;
4'b0011: VAR5 = VAR2 & VAR4;
4'b0100: VAR5 = VAR2 | VAR4;
4'b0101: VAR5 = VAR2 ^ VAR4;
4'b0110: VAR5 = VAR2 << VAR4;
4'b0111: VAR5 = VAR2 >> VAR4;
4'b1000: VAR5 = VAR2 >>> VAR4;
4'b1001: VAR5 = VAR4;
4'b1010: VAR5 = { 16'd0, VAR4[15:0] };
4'b1011: VAR5 = VAR2 | (VAR4 << 16);
4'b1100: VAR5 = VAR2 < VAR4;
4'b1101: VAR5 = VAR2 <= VAR4;
4'b1110: VAR5 = VAR2 == VAR4;
4'b1111: VAR5 = 32'VAR3;
endcase
end
endmodule | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_reset.v | 4,521 | module MODULE1(
VAR13,
VAR23,
VAR9,
VAR32,
VAR39,
VAR38,
VAR21,
VAR1,
VAR31,
VAR17,
VAR15,
VAR22,
VAR35,
VAR3,
VAR37,
VAR12,
VAR27,
VAR34,
VAR25,
VAR2
);
parameter VAR5 = "";
parameter VAR7 = 1;
input VAR13;
input VAR23;
input VAR9;
input VAR32;
input VAR39;
input VAR38;
input VAR21;
output VAR1;
output VAR31;
input [VAR5-1:0] VAR17;
input VAR15;
input VAR22;
input VAR35;
output VAR3;
output VAR37;
output [VAR7-1:0] VAR12;
output VAR27;
output VAR34;
output VAR25;
output [VAR5-1:0] VAR2;
wire VAR11 ;
wire VAR33 ;
wire [VAR5-1:0] VAR8;
assign VAR33 = VAR11 & VAR13;
assign VAR2 = VAR8;
assign VAR11 = VAR15 & VAR22 & VAR35;
VAR10 VAR16(
.VAR6 (VAR11),
.clk (VAR23),
.VAR30 (VAR12)
);
VAR10 VAR18(
.VAR6 (VAR11),
.clk (VAR23),
.VAR30 ({VAR3, VAR37})
);
VAR10 VAR36(
.VAR6 (VAR11),
.clk (VAR9),
.VAR30 (VAR27)
);
VAR10 VAR40(
.VAR6 (VAR11),
.clk (VAR32),
.VAR30 (VAR34)
);
VAR10 VAR19(
.VAR6 (VAR11),
.clk (VAR39),
.VAR30 (VAR25)
);
VAR10 VAR14(
.VAR6 (VAR11),
.clk (VAR38),
.VAR30 (VAR1)
);
VAR10 VAR20(
.VAR6 (VAR11),
.clk (VAR21),
.VAR30 (VAR31)
);
generate
genvar VAR24;
for (VAR24=0; VAR24<VAR5; VAR24=VAR24+1)
begin: VAR29
VAR10 #(
.VAR4(15),
.VAR26(1)
)
VAR28(
.VAR6 (VAR33),
.clk (VAR17[VAR24]),
.VAR30 (VAR8[VAR24])
);
end
endgenerate
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211oi/sky130_fd_sc_hs__a211oi.pp.symbol.v | 1,347 | module MODULE1 (
input VAR2 ,
input VAR4 ,
input VAR6 ,
input VAR1 ,
output VAR3 ,
input VAR7,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a222oi/sky130_fd_sc_hd__a222oi.pp.symbol.v | 1,427 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR5 ,
input VAR2 ,
input VAR3 ,
input VAR1 ,
output VAR11 ,
input VAR9 ,
input VAR10,
input VAR4,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22ai/sky130_fd_sc_ls__o22ai_1.v | 2,352 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR4 ,
VAR10 ,
VAR2 ,
VAR1,
VAR5,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR8 ;
input VAR6 ;
VAR11 VAR9 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3 ,
VAR7,
VAR4,
VAR10,
VAR2
);
output VAR3 ;
input VAR7;
input VAR4;
input VAR10;
input VAR2;
supply1 VAR1;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR6 ;
VAR11 VAR9 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi.symbol.v | 1,349 | module MODULE1 (
input VAR3,
input VAR1,
input VAR6,
output VAR5
);
supply1 VAR8;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
elegabriel/myzju | junior1/CA/LAB/lab1/single_cpu/alt_ctl.v | 1,474 | module MODULE1(VAR1,VAR2,VAR3
);
input [5:0] VAR1,VAR2;
output reg [4:0] VAR3;
always @*
begin
case(VAR1)
6'b001000 : begin
case(VAR2)
6'b100000 : VAR3 = 0; 6'b100010 : VAR3 = 1; 6'b100100 : VAR3 = 2; 6'b100101 : VAR3 = 3; 6'b100110 : VAR3 = 4; 6'b101010 : VAR3 = 5; 6'b000000 : VAR3 = 6; 6'b000100 : VAR3 = 7; 6'b000011 : VAR3 = 8; 6'b000111 : VAR3 = 9; 6'b000010 : VAR3 = 10; 6'b000110 : VAR3 = 11; 6'b000001 : VAR3 = 12; 6'b000010 : VAR3 = 13; 6'b011011 : VAR3 = 14; default : VAR3 = 0;
endcase
end
6'b000000 : VAR3 = 0;
6'b000001 : VAR3 = 1;
6'b000010 : VAR3 = 2;
6'b000011 : VAR3 = 3;
6'b000100 : VAR3 = 5;
6'b000101 : VAR3 = 14;
6'b001001 : VAR3 = 1;
6'b001010 : VAR3 = 13; default : VAR3 = 0;
endcase
end
endmodule | gpl-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/i2s_out.v | 2,030 | module MODULE1(
input VAR1,
input reset,
input[15:0] VAR4,
input[15:0] VAR3,
output VAR7,
output VAR6,
output reg VAR5);
reg [3:0] VAR2;
begin
begin
begin
end
begin
begin
end
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o.blackbox.v | 1,418 | module MODULE1 (
VAR3 ,
VAR6,
VAR1,
VAR7 ,
VAR2
);
output VAR3 ;
input VAR6;
input VAR1;
input VAR7 ;
input VAR2 ;
supply1 VAR5;
supply0 VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.behavioral.pp.v | 2,036 | module MODULE1 (
VAR3 ,
VAR17 ,
VAR8 ,
VAR15 ,
VAR13 ,
VAR9,
VAR5,
VAR16 ,
VAR11
);
output VAR3 ;
input VAR17 ;
input VAR8 ;
input VAR15 ;
input VAR13 ;
input VAR9;
input VAR5;
input VAR16 ;
input VAR11 ;
wire VAR4 ;
wire VAR7 ;
wire VAR6;
or VAR12 (VAR4 , VAR8, VAR17 );
and VAR14 (VAR7 , VAR4, VAR15, VAR13 );
VAR1 VAR10 (VAR6, VAR7, VAR9, VAR5);
buf VAR2 (VAR3 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp.pp.blackbox.v | 1,420 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3 ,
VAR7 ,
VAR4 ,
VAR1 ,
VAR10,
VAR9,
VAR5 ,
VAR8
);
output VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR10;
input VAR9;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/nes_clkgen.v | 3,154 | module MODULE1 (
input clk,
input rst,
output VAR32,
output VAR45,
output VAR38
);
wire VAR52;
wire VAR61;
wire VAR5;
wire VAR28;
wire VAR48;
wire VAR9;
wire VAR44;
wire VAR50;
wire VAR6;
VAR7 #(
.VAR41 ("VAR2"),
.VAR12 ("VAR42"),
.VAR37 ("VAR58"),
.VAR19 (1),
.VAR26 (18),
.VAR14 (0.000),
.VAR54 (9),
.VAR10 (180.00),
.VAR10 (0.00),
.VAR60 (0.500),
.VAR51 (9),
.VAR36 (0.500),
.VAR27 (20.000),
.VAR49 (0.010)
) VAR23 (
.VAR31 (VAR52),
.VAR33 (clk),
.VAR15 (VAR32),
.VAR39 (rst),
.VAR42 (VAR61),
.VAR24 (VAR5),
.VAR34 (VAR28),
.VAR43 (VAR48),
.VAR21 (VAR9),
.VAR46 (VAR44),
.VAR47 (VAR50)
);
VAR1 VAR17 (
.VAR40(VAR5),
.VAR35(VAR45)
);
VAR1 VAR16 (
.VAR40 (VAR61),
.VAR35 (VAR52)
);
VAR1 VAR29 (
.VAR40(VAR28),
.VAR35(VAR6)
);
VAR56 #(
.VAR4 ("VAR53"), .VAR25 (1'b0), .VAR8 ("VAR18") ) VAR20 (
.VAR55 (VAR38),
.VAR22 (VAR6),
.VAR13 (~VAR6),
.VAR11 (1'b1),
.VAR57 (1'b1),
.VAR30 (1'b0),
.VAR3 (1'b0),
.VAR59 (1'b0)
);
endmodule | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/iface/ip/Write_Master/write_burst_control.v | 12,411 | module MODULE1 (
clk,
reset,
VAR1,
VAR6,
VAR43,
VAR14,
VAR12,
ready,
valid,
VAR38,
VAR48,
VAR28,
VAR11,
VAR36,
VAR42,
VAR17,
VAR37,
VAR49,
VAR30,
VAR18,
VAR35,
VAR19,
VAR46,
VAR26
);
parameter VAR21 = 1; parameter VAR29 = 3;
parameter VAR41 = 4;
parameter VAR9 = 2;
parameter VAR22 = 32;
parameter VAR33 = 32;
parameter VAR23 = 5;
parameter VAR34 = 1; localparam VAR32 = (VAR29 == 1)? 1: (VAR29-1);
input clk;
input reset;
input VAR1;
input VAR6;
input [VAR33-1:0] VAR43;
input VAR14;
input VAR12;
input ready;
input valid;
input VAR38;
input [VAR22-1:0] VAR48;
input VAR28;
input [VAR29-1:0] VAR11; input [VAR23:0] VAR36; input VAR42; input VAR17;
input VAR37;
input VAR49;
output wire [VAR22-1:0] VAR30;
output wire VAR18;
output wire [VAR29-1:0] VAR35;
output wire VAR19; output wire VAR46; output wire VAR26;
reg [VAR22-1:0] VAR25;
reg [VAR29-1:0] VAR10; wire VAR39;
wire VAR27;
wire VAR16; wire VAR8; wire VAR3;
wire VAR7; wire VAR5;
wire VAR13; wire [VAR29-1:0] VAR15;
wire [VAR29-1:0] VAR31;
wire VAR20;
wire VAR47;
wire VAR45;
wire [3:0] VAR4;
reg [VAR29-1:0] VAR24;
reg [VAR29-1:0] VAR44;
reg VAR40;
wire [VAR32-1:0] VAR2;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
VAR40 <= 0;
end
else
begin
if ((VAR40 == 1) & (VAR36 == 0))
begin
VAR40 <= 0;
end
else if ((VAR12 == 1) & (ready == 1) & (valid == 1))
begin
VAR40 <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
VAR25 <= 0;
end
else if (VAR5 == 1)
begin
VAR25 <= (VAR7 == 1)? (VAR48 + VAR41) : VAR48;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
VAR10 <= 0;
end
else
if ((VAR5 == 1) & (VAR1 == 0) & (VAR6 == 0)) begin
VAR10 <= VAR24;
end
else if (VAR27 == 1)
begin
VAR10 <= VAR10 - 1'b1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
VAR44 <= 0;
end
else if (VAR5 == 1)
begin
VAR44 <= VAR24;
end
end
assign VAR39 = (VAR10 == 0); assign VAR27 = (VAR39 == 0) & (VAR42 == 0);
assign VAR2 = VAR48[VAR32+VAR9-1:VAR9];
assign VAR13 = (VAR17 == 1) | (VAR37 == 1) | (VAR49 == 1) | (VAR38 == 1) |
((VAR34 == 1) & (VAR39 == 1) & (VAR2 != 0)) | ((VAR34 == 1) & (VAR39 == 0) & (VAR2 != (VAR11 - 1))); assign VAR20 = ((VAR43 >> VAR9) < VAR11) & (VAR14 == 0) & (VAR13 == 0);
assign VAR47 = ((VAR43 >> VAR9) < VAR11) & (VAR14 == 1) & (VAR13 == 0); assign VAR45 = (VAR47 == 0) & (VAR14 == 1) & (VAR40 == 1) & (VAR36 < VAR11) & (VAR13 == 0);
assign VAR15 = (VAR43 >> VAR9) & {(VAR29-1){1'b1}};
assign VAR31 = (VAR36 & {(VAR29-1){1'b1}});
assign VAR16 = (VAR13 == 1) | ((VAR36 >= VAR15) & (VAR20 == 1)) |
((VAR36 >= VAR15) & (VAR47 == 1)) |
((VAR36 >= VAR31) & (VAR45 == 1)) |
(VAR36 >= VAR11);
assign VAR8 = (VAR43 >= (VAR11 << VAR9)) & (VAR13 == 0) & ( ((VAR36 > VAR15) & (VAR20 == 1)) |
((VAR36 > VAR15) & (VAR47 == 1)) |
((VAR36 > VAR31) & (VAR45 == 1)) |
(VAR36 > VAR11) );
assign VAR3 = (VAR28 == 1) & (VAR39 == 1) & (VAR16 == 1); assign VAR7 = (VAR28 == 1) & (VAR10 == 1) & (VAR42 == 0) & (VAR8 == 1); assign VAR5 = (VAR7 == 1) | (VAR3 == 1);
assign VAR4 = {VAR45, VAR47, VAR20, VAR13};
always @ (VAR15 or VAR31 or VAR11 or VAR4)
begin
case (VAR4)
4'b0001 : VAR24 = 1;
4'b0010 : VAR24 = VAR15;
4'b0100 : VAR24 = VAR15;
4'b1000 : VAR24 = VAR31;
default : VAR24 = VAR11;
endcase
end
generate
if (VAR21 == 1)
begin
assign VAR30 = VAR25;
assign VAR35 = VAR44;
assign VAR18 = (VAR39 == 0);
assign VAR19 = (VAR39 == 1);
assign VAR46 = (VAR1 == 1) & (VAR39 == 1); assign VAR26 = (VAR6 == 1) & (VAR39 == 1); end
else
begin
assign VAR30 = VAR48;
assign VAR35 = 1; assign VAR18 = VAR28;
assign VAR19 = 0;
assign VAR46 = VAR1;
assign VAR26 = VAR6;
end
endgenerate
endmodule | mit |
orbancedric/DeepGate | other/Mojo Projects/Mojo-SDRAM/src/avr_interface.v | 2,141 | module MODULE1(
input clk,
input rst,
input VAR9,
output VAR10,
input VAR28,
input VAR18,
input VAR2,
output [3:0] VAR24,
output VAR4,
input VAR45,
input [3:0] VAR26,
output VAR40,
output [9:0] VAR35,
output [3:0] VAR8,
input [7:0] VAR33,
input VAR13,
output VAR11,
input VAR17,
output [7:0] VAR31,
output VAR32
);
wire ready;
wire VAR1 = !ready;
wire VAR34;
wire [7:0] VAR16;
wire VAR21;
wire VAR43;
reg VAR39, VAR3;
reg [9:0] VAR41, VAR23;
reg VAR42, VAR19;
reg [3:0] VAR5, VAR12;
VAR27 VAR27 (
.clk(clk),
.rst(rst),
.VAR9(VAR9),
.ready(ready)
);
VAR47 VAR47 (
.clk(clk),
.rst(VAR1),
.VAR22(VAR2),
.VAR37(VAR28),
.VAR48(VAR43),
.VAR38(VAR18),
.VAR15(VAR34),
.din(8'hff),
.dout(VAR16)
);
VAR30 #(.VAR7(100), .VAR46(7)) VAR30 (
.clk(clk),
.rst(VAR1),
.VAR45(VAR45),
.VAR14(VAR31),
.VAR25(VAR32)
);
VAR6 #(.VAR7(100), .VAR46(7)) VAR6 (
.clk(clk),
.rst(VAR1),
.VAR4(VAR21),
.VAR29(VAR17),
.VAR36(VAR11),
.VAR14(VAR33),
.VAR25(VAR13)
);
assign VAR40 = VAR19;
assign VAR35 = VAR23;
assign VAR8 = VAR12;
assign VAR24 = ready ? VAR26 : 4'VAR20;
assign VAR10 = ready && !VAR2 ? VAR43 : 1'VAR44;
assign VAR4 = ready ? VAR21 : 1'VAR44;
always @(*) begin
VAR39 = VAR3;
VAR41 = VAR23;
VAR42 = 1'b0;
VAR5 = VAR12;
if (VAR2) begin
VAR39 = 1'b0;
end
if (VAR34) begin
if (VAR3 == 1'b0) begin
VAR41[7:0] = VAR16;
VAR39 = 1'b1;
end else begin
VAR41[9:8] = VAR16[1:0];
VAR5 = VAR16[7:4];
VAR39 = 1'b1;
VAR42 = 1'b1;
end
end
end
always @(posedge clk) begin
if (VAR1) begin
VAR3 <= 1'b0;
VAR23 <= 10'b0;
VAR19 <= 1'b0;
end else begin
VAR3 <= VAR39;
VAR23 <= VAR41;
VAR19 <= VAR42;
end
VAR12 <= VAR5;
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi_1.v | 2,312 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR5 ,
VAR10 ,
VAR8 ,
VAR3 ,
VAR1,
VAR2
);
output VAR7 ;
input VAR9 ;
input VAR5 ;
input VAR10 ;
input VAR8 ;
input VAR3 ;
input VAR1;
input VAR2;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR7 ,
VAR9,
VAR5,
VAR10,
VAR8,
VAR3
);
output VAR7 ;
input VAR9;
input VAR5;
input VAR10;
input VAR8;
input VAR3;
supply1 VAR1;
supply0 VAR2;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
alonso193/proyecto1 | Pruebas/DMA_SD/DMA.v | 2,794 | module MODULE1(
VAR6 , reset , VAR5 , VAR8 , VAR10 , VAR2
);
input VAR6,reset,VAR5,VAR8;
output VAR10,VAR2;
wire VAR6,reset,VAR5,VAR8;
reg VAR10,VAR2;
parameter VAR1 = 3
;
parameter VAR9 = 2'b00,VAR4 = 2'b01,VAR3 = 2'b10, VAR11 = 2'b11;
reg [VAR1-1:0] state ; wire [VAR1-1:0] VAR12 ;
assign VAR12 = VAR7(state, VAR5, VAR8);
function [VAR1-1:0] VAR7;
input [VAR1-1:0] state ;
input VAR5 ;
input VAR8 ;
case(state)
VAR9 : if (VAR5 == 1'b1) begin
VAR7 = VAR9;
end else if (VAR8 == 1'b1) begin
VAR7= VAR4;
end else begin
VAR7 = VAR3;
end
VAR4 : if (VAR5 == 1'b1) begin
VAR7 = VAR11;
end else begin
VAR7 = VAR9;
end
VAR3 : if (VAR8 == 1'b1) begin
VAR7 = VAR3;
end else begin
VAR7 = VAR11;
end
VAR11 : if(VAR5 == 1'b1) begin
VAR7 = VAR9;
end else begin
VAR7 = VAR11;
end
endcase
endfunction
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.behavioral.pp.v | 1,383 | module MODULE1( VAR9, VAR8, VAR7, VAR1, VAR2, VAR6, VAR10 );
input VAR1, VAR7, VAR8, VAR9;
inout VAR6, VAR10;
output VAR2;
VAR3 VAR5(.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7),.VAR1(VAR1),.VAR2(VAR2),.VAR6(VAR6),.VAR10(VAR10));
VAR3 VAR4(.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7),.VAR1(VAR1),.VAR2(VAR2),.VAR6(VAR6),.VAR10(VAR10)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i.pp.blackbox.v | 1,317 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR2,
VAR4,
VAR5 ,
VAR3
);
output VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR2;
input VAR4;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai.pp.blackbox.v | 1,393 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR5 ,
VAR7 ,
VAR1 ,
VAR9,
VAR8,
VAR2 ,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR9;
input VAR8;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
efabless/openlane | designs/jpeg_encoder/src/dct.v | 9,323 | module MODULE1(
clk,
VAR9,
rst,
VAR11,
din,
VAR1, VAR27, VAR65, VAR88, VAR75, VAR36, VAR31, VAR17,
VAR97, VAR70, VAR39, VAR94, VAR81, VAR46, VAR55, VAR50,
VAR66, VAR69, VAR34, VAR56, VAR10, VAR87, VAR63, VAR93,
VAR49, VAR62, VAR71, VAR96, VAR45, VAR15, VAR73, VAR42,
VAR38, VAR33, VAR30, VAR2, VAR78, VAR44, VAR91, VAR83,
VAR16, VAR76, VAR85, VAR82, VAR58, VAR13, VAR74, VAR5,
VAR40, VAR6, VAR32, VAR23, VAR24, VAR18, VAR51, VAR14,
VAR7, VAR37, VAR21, VAR4, VAR59, VAR41, VAR57, VAR28,
VAR89
);
parameter VAR67 = 11;
parameter VAR79 = 8;
parameter VAR25 = 12;
input clk;
input VAR9;
input rst;
input VAR11; input [VAR79:1] din;
output [VAR25:1]
VAR1, VAR27, VAR65, VAR88, VAR75, VAR36, VAR31, VAR17,
VAR97, VAR70, VAR39, VAR94, VAR81, VAR46, VAR55, VAR50,
VAR66, VAR69, VAR34, VAR56, VAR10, VAR87, VAR63, VAR93,
VAR49, VAR62, VAR71, VAR96, VAR45, VAR15, VAR73, VAR42,
VAR38, VAR33, VAR30, VAR2, VAR78, VAR44, VAR91, VAR83,
VAR16, VAR76, VAR85, VAR82, VAR58, VAR13, VAR74, VAR5,
VAR40, VAR6, VAR32, VAR23, VAR24, VAR18, VAR51, VAR14,
VAR7, VAR37, VAR21, VAR4, VAR59, VAR41, VAR57, VAR28;
output VAR89; reg VAR89;
reg VAR19, VAR12, VAR48, VAR68, VAR22;
reg [VAR79:1] VAR47;
reg [5:0] VAR64;
wire VAR3 = &VAR64;
always @(posedge clk or negedge rst)
if (~rst)
VAR64 <= 6'h0;
else if (VAR9)
if(VAR11)
VAR64 <= 6'h0;
else if(~VAR3)
VAR64 <= VAR64 + 6'h1;
always @(posedge clk or negedge rst)
if (~rst)
begin
VAR19 <= 1'b0;
VAR12 <= 1'b0;
VAR48 <= 1'b0;
VAR47 <= 0;
VAR89 <= 1'b0;
VAR68 <= 1'b1;
VAR22 <= 1'b1;
end
else if (VAR9)
begin
VAR19 <= VAR11;
VAR12 <= VAR19;
VAR48 <= VAR12;
VAR47 <= din;
VAR68 <= VAR3;
VAR22 <= VAR68;
VAR89 <= VAR68 & ~VAR22;
end
VAR29 #(VAR67, VAR79, 3'h0)
VAR53 (
.clk(clk),
.VAR9(VAR9),
.VAR48(VAR48),
.VAR72(VAR64[2:0]),
.VAR92(VAR64[5:3]),
.VAR47(VAR47),
.VAR8(VAR1), .VAR61(VAR27), .VAR54(VAR65), .VAR35(VAR88), .VAR90(VAR75), .VAR26(VAR36), .VAR86(VAR31), .VAR84(VAR17) );
VAR29 #(VAR67, VAR79, 3'h1)
VAR60 (
.clk(clk),
.VAR9(VAR9),
.VAR48(VAR48),
.VAR72(VAR64[2:0]),
.VAR92(VAR64[5:3]),
.VAR47(VAR47),
.VAR8(VAR97), .VAR61(VAR70), .VAR54(VAR39), .VAR35(VAR94), .VAR90(VAR81), .VAR26(VAR46), .VAR86(VAR55), .VAR84(VAR50) );
VAR29 #(VAR67, VAR79, 3'h2)
VAR20 (
.clk(clk),
.VAR9(VAR9),
.VAR48(VAR48),
.VAR72(VAR64[2:0]),
.VAR92(VAR64[5:3]),
.VAR47(VAR47),
.VAR8(VAR66), .VAR61(VAR69), .VAR54(VAR34), .VAR35(VAR56), .VAR90(VAR10), .VAR26(VAR87), .VAR86(VAR63), .VAR84(VAR93) );
VAR29 #(VAR67, VAR79, 3'h3)
VAR77 (
.clk(clk),
.VAR9(VAR9),
.VAR48(VAR48),
.VAR72(VAR64[2:0]),
.VAR92(VAR64[5:3]),
.VAR47(VAR47),
.VAR8(VAR49), .VAR61(VAR62), .VAR54(VAR71), .VAR35(VAR96), .VAR90(VAR45), .VAR26(VAR15), .VAR86(VAR73), .VAR84(VAR42) );
VAR29 #(VAR67, VAR79, 3'h4)
VAR43 (
.clk(clk),
.VAR9(VAR9),
.VAR48(VAR48),
.VAR72(VAR64[2:0]),
.VAR92(VAR64[5:3]),
.VAR47(VAR47),
.VAR8(VAR38), .VAR61(VAR33), .VAR54(VAR30), .VAR35(VAR2), .VAR90(VAR78), .VAR26(VAR44), .VAR86(VAR91), .VAR84(VAR83) );
VAR29 #(VAR67, VAR79, 3'h5)
VAR95 (
.clk(clk),
.VAR9(VAR9),
.VAR48(VAR48),
.VAR72(VAR64[2:0]),
.VAR92(VAR64[5:3]),
.VAR47(VAR47),
.VAR8(VAR16), .VAR61(VAR76), .VAR54(VAR85), .VAR35(VAR82), .VAR90(VAR58), .VAR26(VAR13), .VAR86(VAR74), .VAR84(VAR5) );
VAR29 #(VAR67, VAR79, 3'h6)
VAR52 (
.clk(clk),
.VAR9(VAR9),
.VAR48(VAR48),
.VAR72(VAR64[2:0]),
.VAR92(VAR64[5:3]),
.VAR47(VAR47),
.VAR8(VAR40), .VAR61(VAR6), .VAR54(VAR32), .VAR35(VAR23), .VAR90(VAR24), .VAR26(VAR18), .VAR86(VAR51), .VAR84(VAR14) );
VAR29 #(VAR67, VAR79, 3'h7)
VAR80 (
.clk(clk),
.VAR9(VAR9),
.VAR48(VAR48),
.VAR72(VAR64[2:0]),
.VAR92(VAR64[5:3]),
.VAR47(VAR47),
.VAR8(VAR7), .VAR61(VAR37), .VAR54(VAR21), .VAR35(VAR4), .VAR90(VAR59), .VAR26(VAR41), .VAR86(VAR57), .VAR84(VAR28) );
endmodule | apache-2.0 |
toomij/DE2Labs | Lab2/lab2_part5.v | 3,988 | module MODULE5 (VAR5, VAR1, VAR43, VAR45, VAR40, VAR8, VAR57, VAR60, VAR2, VAR63, VAR22);
input [17:0] VAR5;
output [8:0] VAR43, VAR1;
output [0:6] VAR45, VAR40, VAR8, VAR57, VAR60, VAR2, VAR63, VAR22;
assign VAR43[8:0] = VAR5[8:0];
assign VAR60 = 7'b1111111;
MODULE8 VAR46 (VAR5[15:12], VAR45);
MODULE8 VAR53 (VAR5[11:8], VAR40);
MODULE8 VAR13 (VAR5[7:4], VAR8);
MODULE8 VAR42 (VAR5[3:0], VAR57);
wire VAR10, VAR31, VAR36, VAR64;
MODULE6 VAR12 (VAR5[3:0], VAR10);
MODULE6 VAR38 (VAR5[7:4], VAR31);
MODULE6 VAR24 (VAR5[11:8], VAR36);
MODULE6 VAR20 (VAR5[15:12], VAR64);
assign VAR1[8] = VAR10 | VAR31 | VAR36 | VAR64;
wire MODULE1, MODULE6, MODULE2;
wire [4:0] VAR7;
MODULE7 VAR55 (VAR5[0], VAR5[8], VAR5[16], VAR7[0], MODULE1);
MODULE7 VAR15 (VAR5[1], VAR5[9], MODULE1, VAR7[1], MODULE6);
MODULE7 VAR11 (VAR5[2], VAR5[10], MODULE6, VAR7[2], MODULE2);
MODULE7 VAR48 (VAR5[3], VAR5[11], MODULE2, VAR7[3], VAR7[4]);
assign VAR1[3:0] = VAR7[3:0];
wire VAR59;
wire [3:0] VAR56, VAR17;
MODULE4 VAR62 (VAR7[4:0], VAR59);
MODULE3 VAR30 (VAR7[3:0], VAR56);
MODULE1 VAR52 (VAR59, VAR7[3:0], VAR56, VAR17);
MODULE8 VAR4 (VAR17, VAR22);
wire MODULE9, MODULE12, VAR47;
wire [4:0] VAR34;
MODULE7 VAR29 (VAR5[4], VAR5[12], VAR59, VAR34[0], MODULE9);
MODULE7 VAR49 (VAR5[5], VAR5[13], MODULE9, VAR34[1], MODULE12);
MODULE7 VAR28 (VAR5[6], VAR5[14], MODULE12, VAR34[2], VAR47);
MODULE7 VAR19 (VAR5[7], VAR5[15], VAR47, VAR34[3], VAR34[4]);
assign VAR1[7:4] = VAR34[3:0];
wire VAR27;
wire [3:0] VAR54, VAR23;
MODULE4 VAR32 (VAR34[4:0], VAR27);
MODULE3 VAR25 (VAR34[3:0], VAR54);
MODULE1 VAR58 (VAR27, VAR34[3:0], VAR54, VAR23);
MODULE2 VAR37 (VAR27, VAR2);
MODULE8 VAR50 (VAR23, VAR63);
endmodule
module MODULE7 (VAR67, VAR6, VAR16, VAR18, VAR21);
input VAR67, VAR6, VAR16;
output VAR21, VAR18;
wire VAR26;
assign VAR26 = VAR67 ^ VAR6;
assign VAR18 = VAR26 ^ VAR16;
assign VAR21 = (VAR6 & ~VAR26) | (VAR26 & VAR16);
endmodule
module MODULE8 (VAR3, VAR66);
input [3:0] VAR3;
output [0:6] VAR66;
assign VAR66[0] = ((~VAR3[3] & ~VAR3[2] & ~VAR3[1] & VAR3[0]) | (~VAR3[3] & VAR3[2] & ~VAR3[1] & ~VAR3[0]));
assign VAR66[1] = ((~VAR3[3] & VAR3[2] & ~VAR3[1] & VAR3[0]) | (~VAR3[3] & VAR3[2] & VAR3[1] & ~VAR3[0]));
assign VAR66[2] = (~VAR3[3] & ~VAR3[2] & VAR3[1] & ~VAR3[0]);
assign VAR66[3] = ((~VAR3[3] & ~VAR3[2] & ~VAR3[1] & VAR3[0]) | (~VAR3[3] & VAR3[2] & ~VAR3[1] & ~VAR3[0]) | (~VAR3[3] & VAR3[2] & VAR3[1] & VAR3[0]) | (VAR3[3] & ~VAR3[2] & ~VAR3[1] & VAR3[0]));
assign VAR66[4] = ~((~VAR3[2] & ~VAR3[0]) | (VAR3[1] & ~VAR3[0]));
assign VAR66[5] = ((~VAR3[3] & ~VAR3[2] & ~VAR3[1] & VAR3[0]) | (~VAR3[3] & ~VAR3[2] & VAR3[1] & ~VAR3[0]) | (~VAR3[3] & ~VAR3[2] & VAR3[1] & VAR3[0]) | (~VAR3[3] & VAR3[2] & VAR3[1] & VAR3[0]));
assign VAR66[6] = ((~VAR3[3] & ~VAR3[2] & ~VAR3[1] & VAR3[0]) | (~VAR3[3] & ~VAR3[2] & ~VAR3[1] & ~VAR3[0]) | (~VAR3[3] & VAR3[2] & VAR3[1] & VAR3[0]));
endmodule
module MODULE6 (VAR41, VAR61);
input [3:0] VAR41;
output VAR61;
assign VAR61 = (VAR41[3] & (VAR41[2] | VAR41[1]));
endmodule
module MODULE4 (VAR41, VAR61);
input [4:0] VAR41;
output VAR61;
assign VAR61 = VAR41[4] | ((VAR41[3] & VAR41[2]) | (VAR41[3] & VAR41[1]));
endmodule
module MODULE3 (VAR41, VAR33);
input [3:0] VAR41;
output [3:0] VAR33;
assign VAR33[0] = VAR41[0];
assign VAR33[1] = ~VAR41[1];
assign VAR33[2] = (~VAR41[3] & ~VAR41[1]) | (VAR41[2] & VAR41[1]);
assign VAR33[3] = (~VAR41[3] & VAR41[1]);
endmodule
module MODULE2 (VAR61, VAR66);
input VAR61;
output [0:6] VAR66;
assign VAR66[0] = VAR61;
assign VAR66[1:2] = 2'b00;
assign VAR66[3:5] = {3{VAR61}};
assign VAR66[6] = 1;
endmodule
module MODULE1 (VAR18, VAR51, VAR41, VAR9);
input VAR18;
input [3:0] VAR51, VAR41;
output [3:0] VAR9;
assign VAR9 = ({4{~VAR18}} & VAR51) | ({4{VAR18}} & VAR41);
endmodule | gpl-2.0 |
mbus/mbus | mbus/verilog/no_pwr_gating_ben/mbus_ctrl_layer_wrapper.Ben.v | 3,225 | module MODULE1
(
input VAR16,
input VAR54,
input VAR4,
input VAR51,
output VAR12,
output VAR48,
input [VAR39-1:0] VAR40,
input [VAR45-1:0] VAR52,
input VAR41,
input VAR43,
input VAR31,
output VAR36,
output [VAR39:0] VAR46,
output [VAR45:0] VAR57,
output VAR2,
input VAR3,
output VAR19,
output VAR10,
output VAR38,
output VAR25,
output VAR5,
input VAR29
);
parameter VAR6 = 20'haaaaa;
wire VAR20;
wire VAR17;
wire VAR53;
wire VAR30;
wire VAR27;
wire VAR13;
VAR44 #(.VAR6(VAR6)) VAR33
(
.VAR16 (VAR16),
.VAR4 (VAR4),
.VAR54 (VAR54),
.VAR12 (VAR20),
.VAR51 (VAR51),
.VAR48 (VAR17),
.VAR40 (VAR40),
.VAR52 (VAR52),
.VAR41 (VAR41),
.VAR43 (VAR43),
.VAR31 (VAR31),
.VAR36 (VAR36),
.VAR46 (VAR46),
.VAR57 (VAR57),
.VAR2 (VAR2),
.VAR3 (VAR3),
.VAR19 (VAR19),
.VAR10 (VAR10),
.VAR38 (VAR38),
.VAR25 (VAR25),
.VAR5 (VAR5),
.VAR29 (VAR29),
.VAR8 (20'h05fff),
.VAR18 (1'b0),
.VAR15 (),
.VAR7 (),
.VAR22 (),
.VAR1 (),
.VAR32 (VAR30), .VAR42 (VAR27),
.VAR9 (VAR13),
.VAR14()
);
VAR56 VAR50
(
.VAR4 (VAR4),
.VAR35 (1'b0),
.VAR47 (VAR17),
.VAR26 (VAR20),
.VAR48 (VAR48),
.VAR12 (VAR12),
.VAR32 (VAR53)
);
VAR23 VAR28
(
.VAR54 (VAR54),
.VAR4 (VAR4),
.VAR55 (1'b0),
.VAR37 (1'b0),
.VAR11 (VAR13),
.VAR34 (1'b0),
.VAR24 (1'b0),
.VAR15 (1'b0),
.VAR49 (VAR53),
.VAR21 (VAR30),
.VAR42 (VAR27)
);
endmodule | apache-2.0 |
ayaovi/yoda | DEA/UART_Sender.v | 3,070 | module MODULE1 #(
parameter VAR3 = 5,
parameter VAR8 = 5'd29 )(
input VAR13,
input VAR5,
input [7:0]VAR16,
input VAR4,
output reg VAR1,
output reg VAR2 );
reg VAR10;
reg [ 7:0]VAR12;
reg [VAR3-1:0]VAR11;
reg [ 2:0]VAR14;
reg [1:0]VAR6;
localparam VAR9 = 2'b00;
localparam VAR17 = 2'b01;
localparam VAR15 = 2'b11;
localparam VAR18 = 2'b10;
reg VAR7;
always @(posedge VAR13) begin
VAR7 <= VAR5;
if(VAR7) begin
VAR1 <= 1'b0;
VAR2 <= 1'b1;
VAR10 <= 0;
VAR11 <= 0;
VAR14 <= 0;
VAR6 <= VAR9;
end else begin
VAR10 <= VAR4;
if(~|VAR11) begin
case(VAR6)
VAR9: begin
if(VAR10) begin
VAR11 <= VAR8;
VAR14 <= 3'd7;
{VAR12, VAR2} <= {VAR16, 1'b0};
VAR1 <= 1'b1;
VAR6 <= VAR17;
end
end
VAR17: begin
VAR11 <= VAR8;
{VAR12[6:0], VAR2} <= VAR12;
if(~|VAR14) VAR6 <= VAR15;
VAR14 <= VAR14 - 1'b1;
end
VAR15: begin
VAR2 <= 1'b1;
VAR11 <= VAR8;
VAR6 <= VAR18;
end
VAR18: begin
if(~VAR10) begin
VAR1 <= 1'b0;
VAR11 <= 0;
VAR6 <= VAR9;
end
end
default:;
endcase
end else begin
VAR11 <= VAR11 - 1'b1;
end
end
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.v | 2,461 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR12,
VAR6,
VAR11 ,
VAR9
);
output VAR1 ;
input VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR12;
input VAR6;
input VAR11 ;
input VAR9 ;
VAR10 VAR3 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR1 ,
VAR4,
VAR5,
VAR7,
VAR2,
VAR8
);
output VAR1 ;
input VAR4;
input VAR5;
input VAR7;
input VAR2;
input VAR8;
supply1 VAR12;
supply0 VAR6;
supply1 VAR11 ;
supply0 VAR9 ;
VAR10 VAR3 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2/sky130_fd_sc_hd__and2_4.v | 2,086 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR5 ,
VAR1,
VAR8,
VAR9 ,
VAR6
);
output VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR1;
input VAR8;
input VAR9 ;
input VAR6 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR2,
VAR4,
VAR5
);
output VAR2;
input VAR4;
input VAR5;
supply1 VAR1;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR6 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.pp.blackbox.v | 1,269 | module MODULE1 (
VAR7,
VAR5,
VAR6 ,
VAR2,
VAR3,
VAR1 ,
VAR4
);
output VAR7;
input VAR5;
input VAR6 ;
input VAR2;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.behavioral.pp.v | 1,316 | module MODULE1( VAR9, VAR4, VAR7, VAR1, VAR8, VAR6 );
input VAR9, VAR4, VAR7;
inout VAR8, VAR6;
output VAR1;
VAR2 VAR5(.VAR9(VAR9),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR6(VAR6));
VAR2 VAR3(.VAR9(VAR9),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR6(VAR6)); | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/ball_absolute.v | 2,288 | module MODULE1(clk, reset, VAR12, VAR25, VAR13);
input clk;
input reset;
output VAR12, VAR25;
output [2:0] VAR13;
wire VAR17;
wire [8:0] VAR2;
wire [8:0] VAR20;
reg [8:0] VAR21; reg [8:0] VAR7;
reg [8:0] VAR22 = -2; reg [8:0] VAR16 = 2;
localparam VAR9 = 128; localparam VAR1 = 128;
localparam VAR19 = 4;
VAR11 VAR26(
.clk(clk),
.reset(reset),
.VAR12(VAR12),
.VAR25(VAR25),
.VAR17(VAR17),
.VAR2(VAR2),
.VAR20(VAR20)
);
always @(posedge VAR25 or posedge reset)
begin
if (reset) begin
VAR7 <= VAR1;
VAR21 <= VAR9;
end else begin
VAR21 <= VAR21 + VAR22;
VAR7 <= VAR7 + VAR16;
end
end
always @(posedge VAR6)
begin
VAR16 <= -VAR16;
end
always @(posedge VAR5)
begin
VAR22 <= -VAR22;
end
wire [8:0] VAR10 = VAR2 - VAR21;
wire [8:0] VAR15 = VAR20 - VAR7;
wire VAR23 = VAR10 < VAR19;
wire VAR14 = VAR15 < VAR19;
wire VAR8 = VAR23 && VAR14;
wire VAR6 = VAR7 >= 240 - VAR19;
wire VAR5 = VAR21 >= 256 - VAR19;
wire VAR4 = (((VAR2&7)==0) && ((VAR20&7)==0));
wire VAR18 = VAR17 && (VAR23 | VAR8);
wire VAR24 = VAR17 && (VAR4 | VAR8);
wire VAR3 = VAR17 && (VAR14 | VAR8);
assign VAR13 = {VAR3,VAR24,VAR18};
endmodule | gpl-3.0 |
olajep/oh | src/mio/hdl/mrx_protocol.v | 2,864 | module MODULE1 (
VAR10, VAR9,
VAR4, VAR12, VAR17, VAR2, VAR18, VAR6
);
parameter VAR7 = 104; parameter VAR21 = 8; parameter VAR20 = VAR14(2*VAR7/VAR21);
input VAR4; input VAR12;
input [7:0] VAR17; input VAR2;
input VAR18; input [2*VAR21-1:0] VAR6;
output VAR10; output [VAR7-1:0] VAR9;
reg [2:0] VAR19;
reg [VAR20-1:0] VAR1;
reg VAR10;
wire VAR11;
wire VAR13;
always @ (posedge VAR4 or negedge VAR12)
if(!VAR12)
VAR19[2:0] <= VAR15;
else
case (VAR19[2:0])
default: VAR19[2:0] <= 'b0;
endcase
always @ (posedge VAR4)
if((VAR19[2:0]==VAR15) | VAR13)
VAR1[VAR20-1:0] <= VAR17[VAR20-1:0];
else if(VAR19[2:0]==VAR3)
VAR1[VAR20-1:0] <= VAR1[VAR20-1:0] - 1'b1;
assign VAR13 = (VAR1[VAR20-1:0]==1'b1) & (VAR19[2:0]==VAR3);
assign VAR11 = (VAR19[2:0]==VAR3);
always @ (posedge VAR4 or negedge VAR12)
if(!VAR12)
VAR10 <= 'b0;
else
VAR10 <= VAR13;
VAR5 #(.VAR7(VAR7),
.VAR8(2*VAR21))
VAR16 ( .dout (VAR9[VAR7-1:0]),
.clk (VAR4),
.din (VAR6[2*VAR21-1:0]),
.VAR2 (VAR2),
.VAR11 (VAR11)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor3/sky130_fd_sc_lp__xor3.behavioral.v | 1,406 | module MODULE1 (
VAR10,
VAR9,
VAR2,
VAR3
);
output VAR10;
input VAR9;
input VAR2;
input VAR3;
supply1 VAR8;
supply0 VAR5;
supply1 VAR11 ;
supply0 VAR7 ;
wire VAR4;
xor VAR6 (VAR4, VAR9, VAR2, VAR3 );
buf VAR1 (VAR10 , VAR4 );
endmodule | apache-2.0 |
gigglesninja/digital-system-design | Lab4/ipcore_dir/mult12x12l3.v | 8,071 | module MODULE2 (
clk, VAR5, VAR52, VAR64
);
input clk;
output [23 : 0] VAR5;
input [11 : 0] VAR52;
input [11 : 0] VAR64;
wire \VAR22/VAR8 ;
wire \VAR22/VAR36 ;
wire \VAR65/VAR66<34>VAR34 ;
wire \VAR65/VAR66<33>VAR34 ;
wire \VAR65/VAR66<32>VAR34 ;
wire \VAR65/VAR66<31>VAR34 ;
wire \VAR65/VAR66<30>VAR34 ;
wire \VAR65/VAR66<29>VAR34 ;
wire \VAR65/VAR66<28>VAR34 ;
wire \VAR65/VAR66<27>VAR34 ;
wire \VAR65/VAR66<26>VAR34 ;
wire \VAR65/VAR66<25>VAR34 ;
wire \VAR65/VAR66<24>VAR34 ;
wire \VAR65/VAR66<23>VAR34 ;
wire \VAR65/VAR47<17>VAR34 ;
wire \VAR65/VAR47<16>VAR34 ;
wire \VAR65/VAR47<15>VAR34 ;
wire \VAR65/VAR47<14>VAR34 ;
wire \VAR65/VAR47<13>VAR34 ;
wire \VAR65/VAR47<12>VAR34 ;
wire \VAR65/VAR47<11>VAR34 ;
wire \VAR65/VAR47<10>VAR34 ;
wire \VAR65/VAR47<9>VAR34 ;
wire \VAR65/VAR47<8>VAR34 ;
wire \VAR65/VAR47<7>VAR34 ;
wire \VAR65/VAR47<6>VAR34 ;
wire \VAR65/VAR47<5>VAR34 ;
wire \VAR65/VAR47<4>VAR34 ;
wire \VAR65/VAR47<3>VAR34 ;
wire \VAR65/VAR47<2>VAR34 ;
wire \VAR65/VAR47<1>VAR34 ;
wire \VAR65/VAR47<0>VAR34 ;
VAR55 #(
.VAR48 ( 1 ),
.VAR33 ( 1 ),
.VAR29 ( "VAR15" ),
.VAR44 ( 1 ))
\VAR22/VAR24 (
.VAR19(\VAR22/VAR8 ),
.VAR62(\VAR22/VAR8 ),
.VAR51(\VAR22/VAR8 ),
.VAR42(clk),
.VAR38(\VAR22/VAR36 ),
.VAR14(\VAR22/VAR36 ),
.VAR59(\VAR22/VAR36 ),
.VAR35({VAR52[11], VAR52[11], VAR52[11], VAR52[11], VAR52[11], VAR52[11], VAR52[11], VAR52[10], VAR52[9], VAR52[8], VAR52[7], VAR52[6], VAR52[5], VAR52[4], VAR52[3], VAR52[2], VAR52[1], VAR52[0]}),
.VAR37({VAR64[11], VAR64[11], VAR64[11], VAR64[11], VAR64[11], VAR64[11], VAR64[11], VAR64[10], VAR64[9], VAR64[8], VAR64[7], VAR64[6], VAR64[5], VAR64[4], VAR64[3], VAR64[2], VAR64[1], VAR64[0]}),
.VAR58({\VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 ,
\VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 ,
\VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 ,
\VAR22/VAR36 , \VAR22/VAR36 , \VAR22/VAR36 }),
.VAR49({VAR5[23], \VAR65/VAR66<34>VAR34 , \VAR65/VAR66<33>VAR34 ,
\VAR65/VAR66<32>VAR34 , \VAR65/VAR66<31>VAR34 , \VAR65/VAR66<30>VAR34 ,
\VAR65/VAR66<29>VAR34 , \VAR65/VAR66<28>VAR34 , \VAR65/VAR66<27>VAR34 ,
\VAR65/VAR66<26>VAR34 , \VAR65/VAR66<25>VAR34 , \VAR65/VAR66<24>VAR34 ,
\VAR65/VAR66<23>VAR34 , VAR5[22], VAR5[21], VAR5[20], VAR5[19], VAR5[18], VAR5[17], VAR5[16], VAR5[15], VAR5[14], VAR5[13], VAR5[12], VAR5[11], VAR5[10], VAR5[9], VAR5[8]
, VAR5[7], VAR5[6], VAR5[5], VAR5[4], VAR5[3], VAR5[2], VAR5[1], VAR5[0]}),
.VAR30({\VAR65/VAR47<17>VAR34 , \VAR65/VAR47<16>VAR34 ,
\VAR65/VAR47<15>VAR34 , \VAR65/VAR47<14>VAR34 ,
\VAR65/VAR47<13>VAR34 , \VAR65/VAR47<12>VAR34 ,
\VAR65/VAR47<11>VAR34 , \VAR65/VAR47<10>VAR34 ,
\VAR65/VAR47<9>VAR34 , \VAR65/VAR47<8>VAR34 ,
\VAR65/VAR47<7>VAR34 , \VAR65/VAR47<6>VAR34 ,
\VAR65/VAR47<5>VAR34 , \VAR65/VAR47<4>VAR34 ,
\VAR65/VAR47<3>VAR34 , \VAR65/VAR47<2>VAR34 ,
\VAR65/VAR47<1>VAR34 , \VAR65/VAR47<0>VAR34 })
);
VAR25 \VAR22/VAR10 (
.VAR49(\VAR22/VAR8 )
);
VAR45 \VAR22/VAR2 (
.VAR32(\VAR22/VAR36 )
);
endmodule
module MODULE1 ();
parameter VAR57 = 100000;
parameter VAR53 = 0;
wire VAR60;
wire VAR3;
wire VAR28;
wire VAR7;
tri1 VAR9;
tri (weak1, strong0) VAR39 = VAR9;
wire VAR26;
wire VAR16;
reg VAR1;
reg VAR46;
reg VAR21;
wire VAR20;
wire VAR50;
wire VAR13;
wire VAR61;
wire VAR23;
reg VAR17;
reg VAR27;
reg VAR6;
reg VAR63;
reg VAR54;
reg VAR12 = 0;
reg VAR31 = 0 ;
reg VAR4 = 0;
reg VAR11 = 0;
reg VAR41 = 1'VAR43;
reg VAR18 = 1'VAR43;
reg VAR40 = 1'VAR43;
reg VAR56 = 1'VAR43;
assign (weak1, weak0) VAR60 = VAR1;
assign (weak1, weak0) VAR3 = VAR46;
assign (weak1, weak0) VAR7 = VAR21; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o_2.v | 2,402 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR11 ,
VAR5 ,
VAR3 ,
VAR10 ,
VAR4 ,
VAR7,
VAR6
);
output VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR10 ;
input VAR4 ;
input VAR7;
input VAR6;
VAR8 VAR2 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1 ,
VAR9,
VAR11,
VAR5,
VAR3,
VAR10,
VAR4
);
output VAR1 ;
input VAR9;
input VAR11;
input VAR5;
input VAR3;
input VAR10;
input VAR4;
supply1 VAR7;
supply0 VAR6;
VAR8 VAR2 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
joaocarlos/udlx-verilog | rtl/execute/branch_control.v | 2,421 | module MODULE1
parameter VAR10 = 32,
parameter VAR3 = 6,
parameter VAR15 = 25
)
(
input VAR11,
input VAR4,
input VAR14,
input VAR5,
input VAR12,
input [VAR3-1:0] VAR6,
input [VAR10-1:0] VAR7,
input [VAR10-1:0] VAR2,
input [VAR15-1:0] VAR13,
output VAR8,
output [VAR3-1:0] VAR17
);
wire [VAR10-1:0] VAR16;
wire [VAR10-1:0] VAR9;
wire [VAR3-1:0] VAR1;
assign VAR1 = {VAR13,{2{1'b0}}};
assign VAR8 = VAR11 | (VAR5 & VAR12);
assign VAR9 = VAR14? VAR7 : VAR6 + ({VAR2,{2{1'b0}}}) + 4;
assign VAR16 = VAR4 ? VAR7 : VAR1;
assign VAR17 = VAR11 ? VAR16 : VAR9;
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfstp/sky130_fd_sc_ms__sdfstp.functional.pp.v | 2,163 | module MODULE1 (
VAR14 ,
VAR10 ,
VAR16 ,
VAR19 ,
VAR11 ,
VAR2,
VAR6 ,
VAR18 ,
VAR1 ,
VAR15
);
output VAR14 ;
input VAR10 ;
input VAR16 ;
input VAR19 ;
input VAR11 ;
input VAR2;
input VAR6 ;
input VAR18 ;
input VAR1 ;
input VAR15 ;
wire VAR9 ;
wire VAR4 ;
wire VAR17;
not VAR8 (VAR4 , VAR2 );
VAR20 VAR13 (VAR17, VAR16, VAR19, VAR11 );
VAR5 VAR12 VAR7 (VAR9 , VAR17, VAR10, VAR4, , VAR6, VAR18);
buf VAR3 (VAR14 , VAR9 );
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/xcv_glbl.v | 3,292 | module MODULE1 ();
wire VAR2;
wire VAR1;
wire VAR4;
wire VAR3;
endmodule | gpl-3.0 |
masc-ucsc/cmpe220fall16 | rtl/ram_2port_fast.v | 1,717 | module MODULE1 #(parameter VAR16 = 64, VAR21=128, VAR25=0) (
input clk
,input reset
,input VAR24
,output VAR17
,input [VAR29(VAR21)-1:0] VAR14
,input [VAR16-1:0] VAR9
,input VAR33
,output VAR18
,input [VAR29(VAR21)-1:0] VAR6
,output VAR4
,input VAR12
,output [VAR16-1:0] VAR20
);
logic [VAR16-1:0] VAR2;
logic [VAR16-1:0] VAR3;
VAR27
VAR1 (
.VAR13 (VAR14)
,.VAR7 (VAR24)
,.VAR28 (VAR9)
,.VAR5 (VAR3)
,.VAR32 (VAR6)
,.VAR10 (1'b0) ,.VAR31 ('b0)
,.VAR30 (VAR2)
);
assign VAR17 = 0;
VAR19 #(.VAR21(VAR16)) VAR26 (
.clk (clk),
.reset (reset),
.din (VAR2),
.VAR11 (VAR33),
.VAR8 (VAR18),
.VAR23 (VAR20),
.VAR22 (VAR4),
.VAR15 (VAR12)
);
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/start_for_Loop_lotde.v | 3,003 | module MODULE2 (
clk,
VAR26,
VAR7,
VAR21,
VAR13);
parameter VAR15 = 32'd1;
parameter VAR4 = 32'd2;
parameter VAR23 = 32'd4;
input clk;
input [VAR15-1:0] VAR26;
input VAR7;
input [VAR4-1:0] VAR21;
output [VAR15-1:0] VAR13;
reg[VAR15-1:0] VAR12 [0:VAR23-1];
integer VAR1;
always @ (posedge clk)
begin
if (VAR7)
begin
for (VAR1=0;VAR1<VAR23-1;VAR1=VAR1+1)
VAR12[VAR1+1] <= VAR12[VAR1];
VAR12[0] <= VAR26;
end
end
assign VAR13 = VAR12[VAR21];
endmodule
module MODULE1 (
clk,
reset,
VAR2,
VAR20,
VAR22,
VAR8,
VAR9,
VAR11,
VAR24,
VAR25);
parameter VAR6 = "VAR14";
parameter VAR15 = 32'd1;
parameter VAR4 = 32'd2;
parameter VAR23 = 32'd4;
input clk;
input reset;
output VAR2;
input VAR20;
input VAR22;
output[VAR15 - 1:0] VAR8;
output VAR9;
input VAR11;
input VAR24;
input[VAR15 - 1:0] VAR25;
wire[VAR4 - 1:0] VAR10 ;
wire[VAR15 - 1:0] VAR16, VAR3;
wire VAR19;
reg[VAR4:0] VAR18 = {(VAR4+1){1'b1}};
reg VAR17 = 0, VAR5 = 1;
assign VAR2 = VAR17;
assign VAR9 = VAR5;
assign VAR16 = VAR25;
assign VAR8 = VAR3;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR18 <= ~{VAR4+1{1'b0}};
VAR17 <= 1'b0;
VAR5 <= 1'b1;
end
else begin
if (((VAR22 & VAR20) == 1 & VAR17 == 1) &&
((VAR24 & VAR11) == 0 | VAR5 == 0))
begin
VAR18 <= VAR18 - 1;
if (VAR18 == 0)
VAR17 <= 1'b0;
VAR5 <= 1'b1;
end
else if (((VAR22 & VAR20) == 0 | VAR17 == 0) &&
((VAR24 & VAR11) == 1 & VAR5 == 1))
begin
VAR18 <= VAR18 + 1;
VAR17 <= 1'b1;
if (VAR18 == VAR23 - 2)
VAR5 <= 1'b0;
end
end
end
assign VAR10 = VAR18[VAR4] == 1'b0 ? VAR18[VAR4-1:0]:{VAR4{1'b0}};
assign VAR19 = (VAR24 & VAR11) & VAR5;
MODULE2
.VAR15(VAR15),
.VAR4(VAR4),
.VAR23(VAR23))
VAR27 (
.clk(clk),
.VAR26(VAR16),
.VAR7(VAR19),
.VAR21(VAR10),
.VAR13(VAR3));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o_1.v | 2,469 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR11 ,
VAR4 ,
VAR12 ,
VAR7 ,
VAR3,
VAR1,
VAR8 ,
VAR5
);
output VAR2 ;
input VAR9 ;
input VAR11 ;
input VAR4 ;
input VAR12 ;
input VAR7 ;
input VAR3;
input VAR1;
input VAR8 ;
input VAR5 ;
VAR6 VAR10 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR2 ,
VAR9,
VAR11,
VAR4,
VAR12,
VAR7
);
output VAR2 ;
input VAR9;
input VAR11;
input VAR4;
input VAR12;
input VAR7;
supply1 VAR3;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR5 ;
VAR6 VAR10 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR7(VAR7)
);
endmodule | apache-2.0 |
dries007/Basys3 | FPGA-Z/FPGA-Z.srcs/sources_1/ip/FontROM/FontROM_stub.v | 1,170 | module MODULE1(VAR1, VAR2)
;
input [13:0]VAR1;
output [0:0]VAR2;
endmodule | mit |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.