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google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p.behavioral.pp.v | 2,075 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR5 ,
VAR7,
VAR15 ,
VAR1 ,
VAR11,
VAR16 ,
VAR6
);
output VAR3 ;
input VAR12 ;
input VAR5 ;
input VAR7;
input VAR15 ;
input VAR1 ;
input VAR11;
input VAR16 ;
input VAR6 ;
wire VAR2 ;
wire VAR4;
wire VAR9 ;
VAR17 VAR13 (VAR2 , VAR12, VAR15, VAR1 );
VAR17 VAR14 (VAR4, VAR5, VAR7, VAR1 );
or VAR10 (VAR9 , VAR5, VAR12 );
VAR17 VAR8 (VAR3 , VAR9, VAR7, VAR1);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/diode/sky130_fd_sc_ms__diode.behavioral.v | 1,177 | module MODULE1 (
VAR2
);
input VAR2;
supply1 VAR5;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b.functional.pp.v | 2,018 | module MODULE1 (
VAR4 ,
VAR10 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR11,
VAR14,
VAR7 ,
VAR2
);
output VAR4 ;
input VAR10 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR11;
input VAR14;
input VAR7 ;
input VAR2 ;
wire VAR1 ;
wire VAR13 ;
wire VAR15;
not VAR5 (VAR1 , VAR10 );
nand VAR6 (VAR13 , VAR8, VAR9, VAR3, VAR1 );
VAR16 VAR17 (VAR15, VAR13, VAR11, VAR14);
buf VAR12 (VAR4 , VAR15 );
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/wb_master.v | 6,108 | module MODULE1(VAR7, VAR12, VAR8, VAR30,
VAR13, VAR17, VAR1, VAR22, VAR28, VAR29, VAR27, VAR6, VAR25, VAR15);
input VAR7;
input VAR12;
input [3:0] VAR8;
output [3:0] VAR30;
input VAR13;
output [31:0] VAR17;
output VAR1;
input [31:0] VAR22;
output [31:0] VAR28;
input VAR29;
input VAR27;
output [3:0] VAR6;
output VAR25;
output VAR15;
reg [31:0] VAR17;
reg [3:0] VAR6;
reg VAR1;
reg VAR25;
reg VAR15;
reg [31:0] VAR28;
wire [15:0] VAR11; reg [31:0] VAR31[0:7];
reg [31:0] VAR24[0:7];
reg VAR4;
integer VAR19;
integer address;
integer VAR20;
integer VAR5;
integer VAR26;
assign VAR11 = 16'b1010101010101010;
function [1:0] VAR32;
input [31:0] VAR16;
begin
casex (VAR16[31:29])
3'b000: VAR32 = VAR11[15:14];
3'b001: VAR32 = VAR11[13:12];
3'b010: VAR32 = VAR11[11:10];
3'b011: VAR32 = VAR11[9:8];
3'b100: VAR32 = VAR11[7:6];
3'b101: VAR32 = VAR11[5:4];
3'b110: VAR32 = VAR11[3:2];
3'b111: VAR32 = VAR11[1:0];
3'VAR3: VAR32 = 2'VAR14;
endcase end
endfunction
always @(posedge VAR7 or posedge VAR12)
begin
if (VAR12)
begin
VAR4 = 1'b0;
end
end
task rd;
input [31:0] VAR16;
output [31:0] VAR21;
begin
VAR19 = 1;
address = VAR16;
VAR5 = 255;
VAR26 = 0;
VAR4 <= 1;
@(posedge VAR7);
while (~VAR1)
@(posedge VAR7);
while (VAR1)
@(posedge VAR7);
VAR21 = VAR20;
end
endtask
task wr;
input [31:0] VAR16;
input [31:0] VAR10;
input [3:0] sel;
begin
VAR19 = 1;
address = VAR16;
VAR5 = sel;
VAR26 = 1;
VAR20 = VAR10;
VAR4 <= 1;
@(posedge VAR7);
while (~VAR1)
@(posedge VAR7);
while (VAR1)
@(posedge VAR7);
end
endtask
task VAR23;
input [31:0] VAR16;
input VAR18;
output [31:0] VAR21;
begin
VAR26 = 0;
VAR19 = VAR18;
address = VAR16;
VAR4 <= 1;
@(posedge VAR7);
while (~(VAR13 & VAR25))
@(posedge VAR7);
VAR21 = VAR20;
end
endtask
task VAR9;
input [31:0] VAR16;
input [31:0] VAR10;
input [3:0] sel;
input VAR18;
begin
VAR26 = 1;
VAR19 = VAR18;
address = VAR16;
VAR20 = VAR10;
VAR5 = sel;
VAR4 <= 1;
@(posedge VAR7);
while (~(VAR13 & VAR25))
@(posedge VAR7);
end
endtask
task VAR2;
input [31:0] VAR16;
input [31:0] VAR10;
input [3:0] sel;
output [31:0] VAR21;
begin
VAR26 = 0;
VAR19 = 0;
address = VAR16;
VAR4 <= 1;
@(posedge VAR7);
while (~(VAR13 & VAR25))
@(posedge VAR7);
VAR21 = VAR20;
VAR26 = 1;
address = VAR16;
VAR5 = sel;
VAR4 <= 1;
VAR20 <= VAR10;
VAR19 <= 1;
@(posedge VAR7);
while (~(VAR13 & VAR25))
@(posedge VAR7);
end
endtask
always @(posedge VAR7)
begin
if (VAR12)
VAR17 <= 32'h00000000;
end
else
VAR17 <= address;
end
always @(posedge VAR7)
begin
if (VAR12 | VAR29 | VAR27)
VAR1 <= 1'b0;
end
else if ((VAR19 == 1) & VAR13)
VAR1 <= 1'b0;
else if (VAR4 | VAR1) begin
VAR1 <= 1'b1;
VAR4 <= 1'b0;
end
end
always @(posedge VAR7)
begin
if (VAR12 | VAR29 | VAR27)
VAR25 <= 1'b0;
end
else if (VAR25 & VAR13)
VAR25 <= 1'b0;
else if (VAR4 | VAR25)
VAR25 <= 1'b1;
end
always @(posedge VAR7)
begin
if (VAR26 == 0) begin
VAR6 <= 4'b1111;
if (VAR25 & VAR13)
VAR20 <= VAR22;
end
else begin
case (VAR32(address))
2'b00: begin
VAR6 <= {3'b000, VAR5[0]};
VAR28 <= {VAR20[7:0], VAR20[7:0], VAR20[7:0], VAR20[7:0]};
end
2'b01: begin
VAR6 <= {2'b00, VAR5[1:0]};
VAR28 <= {VAR20[15:0], VAR20[15:0]};
end
2'b10: begin
VAR6 <= VAR5;
VAR28 <= VAR20;
end
endcase
end
end
always @(posedge VAR7)
begin
if (VAR12)
VAR15 <= 1'b0;
end
else if (VAR4)
VAR15 <= VAR26;
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22a/sky130_fd_sc_hvl__o22a.functional.v | 1,515 | module MODULE1 (
VAR1 ,
VAR10,
VAR6,
VAR3,
VAR11
);
output VAR1 ;
input VAR10;
input VAR6;
input VAR3;
input VAR11;
wire VAR5 ;
wire VAR4 ;
wire VAR7;
or VAR12 (VAR5 , VAR6, VAR10 );
or VAR9 (VAR4 , VAR11, VAR3 );
and VAR8 (VAR7, VAR5, VAR4);
buf VAR2 (VAR1 , VAR7 );
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/wb_conmax/wb_conmax_rf.v | 11,883 | module MODULE1(
VAR43, VAR39,
VAR23, VAR21, VAR35, VAR1, VAR4, VAR42,
VAR13, VAR38, VAR46, VAR8,
VAR19, VAR28, VAR29, VAR17, VAR3, VAR45,
VAR33, VAR6, VAR7, VAR26,
VAR2, VAR15, VAR20, VAR16, VAR24, VAR36, VAR31, VAR22,
VAR44, VAR34, VAR41, VAR27, VAR14, VAR9, VAR12, VAR30
);
parameter [3:0] VAR32 = 4'hf;
parameter VAR37 = 32; parameter VAR11 = 32; parameter VAR10 = VAR37 / 8;
input VAR43, VAR39;
input [VAR37-1:0] VAR23;
output [VAR37-1:0] VAR21;
input [VAR11-1:0] VAR35;
input [VAR10-1:0] VAR1;
input VAR4;
input VAR42;
input VAR13;
output VAR38;
output VAR46;
output VAR8;
input [VAR37-1:0] VAR19;
output [VAR37-1:0] VAR28;
output [VAR11-1:0] VAR29;
output [VAR10-1:0] VAR17;
output VAR3;
output VAR45;
output VAR33;
input VAR6;
input VAR7;
input VAR26;
output [15:0] VAR2;
output [15:0] VAR15;
output [15:0] VAR20;
output [15:0] VAR16;
output [15:0] VAR24;
output [15:0] VAR36;
output [15:0] VAR31;
output [15:0] VAR22;
output [15:0] VAR44;
output [15:0] VAR34;
output [15:0] VAR41;
output [15:0] VAR27;
output [15:0] VAR14;
output [15:0] VAR9;
output [15:0] VAR12;
output [15:0] VAR30;
reg [15:0] VAR2, VAR15, VAR20, VAR16, VAR24, VAR36;
reg [15:0] VAR31, VAR22, VAR44, VAR34, VAR41, VAR27;
reg [15:0] VAR14, VAR9, VAR12, VAR30;
wire VAR40;
reg [15:0] VAR5;
reg VAR25;
reg VAR18;
assign VAR40 = VAR42 & VAR13 & (VAR35[VAR11-5:VAR11-8] == VAR32);
always @(posedge VAR43)
VAR18 <= VAR40 & VAR4 & !VAR18;
always @(posedge VAR43)
VAR25 <= VAR40 & !VAR25;
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR2 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd0) ) VAR2 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR15 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd1) ) VAR15 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR20 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd2) ) VAR20 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR16 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd3) ) VAR16 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR24 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd4) ) VAR24 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR36 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd5) ) VAR36 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR31 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd6) ) VAR31 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR22 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd7) ) VAR22 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR44 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd8) ) VAR44 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR34 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd9) ) VAR34 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR41 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd10) ) VAR41 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR27 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd11) ) VAR27 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR14 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd12) ) VAR14 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR9 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd13) ) VAR9 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR12 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd14) ) VAR12 <= VAR23[15:0];
always @(posedge VAR43 or posedge VAR39)
if(VAR39) VAR30 <= 16'h0;
else
if(VAR18 & (VAR35[5:2] == 4'd15) ) VAR30 <= VAR23[15:0];
always @(posedge VAR43)
if(!VAR40) VAR5 <= 16'h0;
else
case(VAR35[5:2])
4'd0: VAR5 <= VAR2;
4'd1: VAR5 <= VAR15;
4'd2: VAR5 <= VAR20;
4'd3: VAR5 <= VAR16;
4'd4: VAR5 <= VAR24;
4'd5: VAR5 <= VAR36;
4'd6: VAR5 <= VAR31;
4'd7: VAR5 <= VAR22;
4'd8: VAR5 <= VAR44;
4'd9: VAR5 <= VAR34;
4'd10: VAR5 <= VAR41;
4'd11: VAR5 <= VAR27;
4'd12: VAR5 <= VAR14;
4'd13: VAR5 <= VAR9;
4'd14: VAR5 <= VAR12;
4'd15: VAR5 <= VAR30;
endcase
assign VAR29 = VAR35;
assign VAR17 = VAR1;
assign VAR28 = VAR23;
assign VAR45 = VAR40 ? 1'b0 : VAR42;
assign VAR33 = VAR13;
assign VAR3 = VAR4;
assign VAR21 = VAR40 ? { {VAR11-16{1'b0}}, VAR5} : VAR19;
assign VAR38 = VAR40 ? VAR25 : VAR6;
assign VAR46 = VAR40 ? 1'b0 : VAR7;
assign VAR8 = VAR40 ? 1'b0 : VAR26;
endmodule | gpl-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/altera_up_audio_out_serializer.v | 7,591 | module MODULE1 (
clk,
reset,
VAR7,
VAR17,
VAR32,
VAR23,
VAR8,
VAR22,
VAR30,
VAR34,
VAR18,
VAR5,
VAR27
);
parameter VAR2 = 15;
input clk;
input reset;
input VAR7;
input VAR17;
input VAR32;
input VAR23;
input [VAR2: 0] VAR8;
input VAR22;
input [VAR2: 0] VAR30;
input VAR34;
output reg [ 7: 0] VAR18;
output reg [ 7: 0] VAR5;
output reg VAR27;
wire VAR36;
wire VAR6;
wire VAR29;
wire VAR15;
wire VAR10;
wire VAR21;
wire [ 6: 0] VAR9;
wire [ 6: 0] VAR26;
wire [VAR2: 0] VAR13;
wire [VAR2: 0] VAR3;
reg VAR12;
reg [VAR2: 0] VAR4;
always @(posedge clk)
begin
if (reset == 1'b1)
VAR18 <= 8'h00;
end
else
VAR18 <= 8'h80 - {VAR10,VAR9};
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR5 <= 8'h00;
end
else
VAR5 <= 8'h80 - {VAR21,VAR26};
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR27 <= 1'b0;
end
else
VAR27 <= VAR4[VAR2];
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR12 <= 1'b0;
end
else if (VAR36)
VAR12 <= 1'b1;
else if (VAR6)
VAR12 <= 1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
VAR4 <= 'h0;
end
else if (VAR36)
VAR4 <= VAR13;
else if (VAR6)
VAR4 <= VAR3;
else if (VAR32 | VAR23)
VAR4 <= 'h0;
else if (VAR17)
VAR4 <=
{VAR4[(VAR2 - 1):0], 1'b0};
end
assign VAR36 = VAR32 &
~VAR29 &
~VAR15;
assign VAR6 = VAR23 &
VAR12;
VAR19 VAR1(
.clk (clk),
.reset (reset),
.VAR11 (VAR22 & ~VAR10),
.VAR24 (VAR8),
.VAR35 (VAR36),
.VAR31 (VAR29),
.VAR16 (VAR10),
.VAR14 (VAR9),
.VAR33 (VAR13)
);
VAR1.VAR2 = VAR2,
VAR1.VAR25 = 128,
VAR1.VAR20 = 6;
VAR19 VAR28(
.clk (clk),
.reset (reset),
.VAR11 (VAR34 & ~VAR21),
.VAR24 (VAR30),
.VAR35 (VAR6),
.VAR31 (VAR15),
.VAR16 (VAR21),
.VAR14 (VAR26),
.VAR33 (VAR3)
);
VAR28.VAR2 = VAR2,
VAR28.VAR25 = 128,
VAR28.VAR20 = 6;
endmodule | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/altera/ad_xcvr_rx_rst.v | 10,035 | module MODULE1 (
VAR3,
VAR43,
VAR41,
VAR17,
VAR21,
VAR42,
VAR38,
VAR20,
VAR33,
VAR4);
parameter VAR24 = 4;
parameter VAR2 = 8;
parameter VAR18 = 8;
parameter VAR26 = 5;
parameter VAR12 = 12;
localparam VAR22 = 4'h0;
localparam VAR32 = 4'h1;
localparam VAR1 = 4'h2;
localparam VAR6 = 4'h3;
localparam VAR19 = 4'h4;
localparam VAR27 = 4'h5;
localparam VAR25 = 4'h6;
localparam VAR35 = 4'h7;
localparam VAR23 = 4'h8;
localparam VAR36 = 4'h9;
localparam VAR37 = 4'ha;
localparam VAR11 = 4'hb;
input VAR3;
input VAR43;
input VAR41;
input VAR17;
input [VAR24-1:0] VAR21;
input [VAR24-1:0] VAR42;
output [VAR24-1:0] VAR38;
output [VAR24-1:0] VAR20;
output VAR33;
output [ 3:0] VAR4;
reg [ 2:0] VAR28 = 'd0;
reg VAR30 = 'd0;
reg [VAR2:0] VAR14 = 'd0;
reg [VAR18:0] VAR10 = 'd0;
reg [VAR26:0] VAR13 = 'd0;
reg [VAR12:0] VAR29 = 'd0;
reg [ 3:0] VAR4 = 'd0;
reg [VAR24-1:0] VAR38 = 'd0;
reg [VAR24-1:0] VAR20 = 'd0;
reg VAR33 = 'd0;
wire VAR8;
wire VAR40;
wire VAR7;
wire VAR9;
wire VAR31;
wire VAR5;
wire VAR15;
wire VAR34;
wire VAR16;
wire VAR39;
assign VAR8 = ~(VAR43 & VAR41 & VAR17);
always @(posedge VAR3) begin
VAR28 <= {VAR28[1:0], VAR8};
VAR30 <= VAR28[2];
end
assign VAR40 = | VAR21;
assign VAR7 = ~VAR40;
assign VAR9 = VAR14[VAR2];
always @(posedge VAR3) begin
if (VAR7 == 1'd0) begin
VAR14 <= 'd0;
end else if (VAR14[VAR2] == 1'b0) begin
VAR14 <= VAR14 + 1'b1;
end
end
assign VAR31 = | VAR42;
assign VAR5 = VAR10[VAR18];
always @(posedge VAR3) begin
if (VAR31 == 1'd0) begin
VAR10 <= 'd0;
end else if (VAR10[VAR18] == 1'b0) begin
VAR10 <= VAR10 + 1'b1;
end
end
assign VAR15 = | VAR38;
assign VAR34 = VAR13[VAR26];
always @(posedge VAR3) begin
if (VAR15 == 1'd0) begin
VAR13 <= 'd0;
end else if (VAR13[VAR26] == 1'b0) begin
VAR13 <= VAR13 + 1'b1;
end
end
assign VAR16 = | VAR20;
assign VAR39 = VAR29[VAR12];
always @(posedge VAR3) begin
if (VAR16 == 1'd0) begin
VAR29 <= 'd0;
end else if (VAR29[VAR12] == 1'b0) begin
VAR29 <= VAR29 + 1'b1;
end
end
always @(posedge VAR3) begin
if (VAR30 == 1'b1) begin
VAR4 <= VAR22;
end else begin
case (VAR4)
VAR22: begin
VAR4 <= VAR32;
end
VAR32: begin
if ((VAR9 == 1'b1) && (VAR34 == 1'b1)) begin
VAR4 <= VAR1;
end else begin
VAR4 <= VAR32;
end
end
VAR1: begin
VAR4 <= VAR6;
end
VAR6: begin
VAR4 <= VAR19;
end
VAR19: begin
VAR4 <= VAR27;
end
VAR27: begin
VAR4 <= VAR25;
end
VAR25: begin
if ((VAR5 == 1'b1) && (VAR39 == 1'b1)) begin
VAR4 <= VAR35;
end else begin
VAR4 <= VAR25;
end
end
VAR35: begin
VAR4 <= VAR23;
end
VAR23: begin
VAR4 <= VAR36;
end
VAR36: begin
VAR4 <= VAR37;
end
VAR37: begin
VAR4 <= VAR11;
end
VAR11: begin
VAR4 <= VAR11;
end
default: begin
VAR4 <= VAR22;
end
endcase
end
end
always @(posedge VAR3) begin
if (VAR4 == VAR22) begin
VAR38 <= {{VAR24{1'b1}}};
end else if (VAR4 == VAR27) begin
VAR38 <= {{VAR24{1'b0}}};
end
if (VAR4 == VAR22) begin
VAR20 <= {{VAR24{1'b1}}};
end else if (VAR4 == VAR37) begin
VAR20 <= {{VAR24{1'b0}}};
end
if (VAR4 == VAR11) begin
VAR33 <= 1'b1;
end else begin
VAR33 <= 1'b0;
end
end
endmodule | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/request_generator.v | 3,740 | module MODULE1 (
input VAR2,
input VAR4,
output [VAR14-1:0] VAR11,
input [VAR14-1:0] VAR9,
input VAR12,
output reg VAR6,
input [VAR3-1:0] VAR15,
input enable,
input VAR7,
output VAR8
);
parameter VAR14 = 3;
parameter VAR3 = 17;
reg [VAR3-1:0] VAR5 = 'h00;
reg [VAR14-1:0] VAR1;
wire [VAR14-1:0] VAR13 = VAR10(VAR1);
assign VAR8 = VAR5 == 'h00;
assign VAR11 = VAR1;
always @(posedge VAR2)
begin
if (VAR4 == 1'b0) begin
VAR5 <= 'h00;
VAR1 <= 'h0;
VAR6 <= 1'b1;
end else if (enable == 1'b0) begin
VAR6 <= 1'b1;
end else begin
if (VAR6) begin
if (VAR12 && enable) begin
VAR5 <= VAR15;
VAR6 <= 1'b0;
end
end else if (VAR9 != VAR13 && ~VAR7) begin
if (VAR8)
VAR6 <= 1'b1;
VAR5 <= VAR5 - 1'b1;
VAR1 <= VAR13;
end
end
end
endmodule | gpl-3.0 |
maijohnson/comp3601_blue_15s2 | AudioController/duration_lut.v | 1,350 | module MODULE1 (input [3:0] VAR8, output [15:0] VAR10);
parameter
VAR1 = 16'd48000, VAR3 = 16'd24000, VAR13 = 16'd18000, VAR6 = 16'd12000, VAR4 = 16'd9000, VAR9 = 16'd6000, VAR12 = 16'd4500, VAR5 = 16'd3000, VAR7 = 16'd2000, VAR11 = 16'd1500, VAR2 = 16'd1000;
assign VAR10 = (VAR8 == 4'd1) ? VAR11 :
(VAR8 == 4'd2) ? VAR7 :
(VAR8 == 4'd3) ? VAR5 :
(VAR8 == 4'd4) ? VAR12 :
(VAR8 == 4'd5) ? VAR9 :
(VAR8 == 4'd6) ? VAR4 :
(VAR8 == 4'd7) ? VAR6 :
(VAR8 == 4'd8) ? VAR13 :
(VAR8 == 4'd9) ? VAR3 :
(VAR8 == 4'd10) ? VAR1 :
VAR2 ;
endmodule | mit |
eSedano/vrudy | rtl/dpth_br_cnd.v | 3,345 | module MODULE1 (
input wire VAR2,
output wire VAR5,
output wire [2:0] VAR3,
output reg VAR4
);
always @(*)
begin: VAR1
case (VAR3)
3'b000:
VAR4 = 1'b1;
3'b001:
VAR4 = VAR2;
3'b010:
VAR4 = VAR5;
3'b011:
VAR4 = VAR5 | VAR2;
3'b100:
VAR4 = 1'b0;
3'b101:
VAR4 = ~VAR2;
3'b110:
VAR4 = ~VAR5;
3'b111:
VAR4 = ~(VAR5 | VAR2);
endcase
end
endmodule | mit |
SiLab-Bonn/basil | basil/firmware/modules/spi/spi_core.v | 7,199 | module MODULE1 #(
parameter VAR33 = 16,
parameter VAR31 = 16
) (
input wire VAR11,
input wire VAR82,
input wire [VAR33-1:0] VAR74,
input wire [7:0] VAR57,
input wire VAR55,
input wire VAR50,
output reg [7:0] VAR41,
input wire VAR61,
output wire VAR40,
input wire VAR23,
output reg VAR63,
input wire VAR56,
output reg VAR81,
output reg VAR36
);
localparam VAR62 = 2;
reg [7:0] VAR9 [15:0];
wire VAR67;
wire VAR68;
assign VAR67 = VAR82 || VAR68;
localparam VAR4 = 8*VAR31;
always @(posedge VAR11) begin
if(VAR67) begin
VAR9[0] <= 0;
VAR9[1] <= 0;
VAR9[2] <= 0;
VAR9[3] <= VAR4[7:0]; VAR9[4] <= VAR4[15:8]; VAR9[5] <= 4; VAR9[6] <= 0; VAR9[7] <= 0; VAR9[8] <= 0; VAR9[9] <= 1; VAR9[10] <= 0; VAR9[11] <= 0; VAR9[12] <= 0; VAR9[13] <= 0; end
else if(VAR50 && VAR74 < 16)
VAR9[VAR74[3:0]] <= VAR57;
end
reg [7:0] VAR70;
reg [7:0] VAR59;
wire VAR29;
assign VAR68 = (VAR74==0 && VAR50);
assign VAR29 = (VAR74==1 && VAR50);
wire [15:0] VAR66;
assign VAR66 = {VAR9[4],VAR9[3]};
wire [7:0] VAR60;
assign VAR60 = VAR9[2];
reg VAR53;
wire [31:0] VAR30;
assign VAR30 = {VAR9[8], VAR9[7], VAR9[6], VAR9[5]};
wire [31:0] VAR64;
assign VAR64 = {VAR9[12], VAR9[11], VAR9[10], VAR9[9]};
wire VAR78;
assign VAR78 = VAR9[13][0];
reg [7:0] VAR37;
always @(posedge VAR11) begin
if(VAR55) begin
if(VAR74 == 0)
VAR37 <= VAR62;
end
else if(VAR74 == 1)
VAR37 <= {7'b0, VAR53};
end
else if(VAR74 == 13)
VAR37 <= {7'b0, VAR78};
else if(VAR74 == 14)
VAR37 <= VAR31[7:0];
else if(VAR74 == 15)
VAR37 <= VAR31[15:8];
else if (VAR74 < 16)
VAR37 <= VAR9[VAR74[3:0]];
end
end
reg [VAR33-1:0] VAR44;
always @(posedge VAR11) begin
if(VAR55) begin
VAR44 <= VAR74;
end
end
always @ begin
for(VAR51=0;VAR51<8;VAR51=VAR51+1) begin
VAR10[VAR51] = VAR57[7-VAR51];
VAR70[VAR51] = VAR35[7-VAR51];
VAR59[VAR51] = VAR48[7-VAR51];
end
end
wire VAR14;
VAR79 VAR72(
.VAR26(VAR11),
.VAR32(VAR61),
.VAR75(VAR35),
.VAR18(VAR14),
.VAR76(VAR50 && VAR74 >=16 && VAR74 < 16+VAR31),
.VAR46(1'b0),
.VAR12(VAR45),
.VAR6(VAR65),
.VAR20(VAR10),
.VAR22(1'b0)
);
wire [10:0] VAR25;
assign VAR25 = (VAR74-16-VAR31);
wire [13:0] VAR38;
assign VAR38 = VAR34-1;
reg VAR47;
VAR79 VAR43(
.VAR26(VAR11),
.VAR32(VAR61),
.VAR75(VAR48),
.VAR18(),
.VAR76(1'b0),
.VAR46(VAR47),
.VAR12(VAR25),
.VAR6(VAR38),
.VAR20(VAR10),
.VAR22(VAR23)
);
wire VAR49;
wire VAR39;
VAR42 VAR80 (.VAR2(VAR11), .VAR19(VAR67), .VAR54(VAR61), .VAR77(VAR39));
assign VAR49 = VAR39 || VAR82;
wire VAR58;
VAR42 VAR3 (.VAR2(VAR11), .VAR19(VAR29), .VAR54(VAR61), .VAR77(VAR58));
wire VAR17;
reg [2:0] VAR8;
always @(posedge VAR61) begin
VAR8[0] <= VAR56;
VAR8[1] <= VAR8[0];
VAR8[2] <= VAR8[1];
end
assign VAR17 = !VAR8[2] & VAR8[1];
wire [32:0] VAR69;
assign VAR69 = VAR66 + VAR30;
reg [31:0] VAR28;
wire VAR71;
assign VAR71 = (VAR34 == VAR69 && (VAR64==0 || VAR28 < VAR64));
reg VAR73;
always @(posedge VAR61)
VAR73 <= VAR71;
always @(posedge VAR61)
if (VAR49)
VAR47 <= 0;
else if(VAR58 || (VAR17 && VAR78) || VAR73)
VAR47 <= 1;
else if(VAR34 == VAR66)
VAR47 <= 0;
always @(posedge VAR61)
if (VAR49)
VAR34 <= 0;
else if(VAR58 || (VAR17 && VAR78))
VAR34 <= 1;
else if(VAR34 == VAR69)
VAR34 <= 0;
else if(VAR73)
VAR34 <= 1;
else if(VAR34 != 0)
VAR34 <= VAR34 + 1;
always @(posedge VAR61)
if (VAR49 || VAR58 || (VAR17 && VAR78))
VAR28 <= 1;
else if(VAR34 == VAR69)
VAR28 <= VAR28 + 1;
reg [1:0] VAR15;
always @(posedge VAR61) begin
VAR15[0] <= VAR47;
VAR15[1] <= VAR15[0];
end
always @(posedge VAR61)
VAR36 <= (VAR15[1]==1 && VAR15[0]==0);
wire VAR1 = VAR34 == VAR69 && VAR28 >= VAR64;
wire VAR16, VAR24;
VAR42 VAR5 (.VAR2(VAR61), .VAR19(VAR1), .VAR54(VAR11), .VAR77(VAR16));
VAR42 VAR52 (.VAR2(VAR61), .VAR19(VAR17), .VAR54(VAR11), .VAR77(VAR24));
always @(posedge VAR11)
if(VAR67)
VAR53 <= 1;
else if(VAR29 || (VAR24 && VAR78))
VAR53 <= 0;
else if(VAR16)
VAR53 <= 1;
VAR21 VAR7(.VAR27(VAR61), .enable(VAR81), .VAR13(VAR40));
always @(negedge VAR61)
VAR63 <= VAR14 & VAR47;
always @(negedge VAR61)
VAR81 <= VAR47;
endmodule | bsd-3-clause |
AbhishekShah212/School_Projects | ELEN232/pset6/CLA_Adder.v | 1,624 | module MODULE1 (
input [3:0] VAR17,
input [3:0] VAR14,
input VAR1,
output [3:0] VAR11,
output VAR10
);
wire [2:0] VAR8;
wire [2:0] VAR3;
wire [3:0] VAR5;
assign VAR8[0] = VAR17[0] & (VAR14[0] ^ VAR1);
assign VAR3[0] = VAR17[0] ^ (VAR14[0] ^ VAR1);
assign VAR8[1] = VAR17[1] & VAR14[1] ^ VAR1;
assign VAR3[1] = VAR17[1] ^ (VAR14[1] ^ VAR1);
assign VAR8[2] = VAR17[2] & (VAR14[2] ^ VAR1);
assign VAR3[2] = VAR17[2] ^ (VAR14[2] ^ VAR1);
assign VAR5[0] = VAR1;
assign VAR5[1] = VAR8[0] | VAR3[0] & VAR1;
assign VAR5[2] = VAR8[1] | VAR3[1] & (VAR8[0] | VAR3[0] & VAR1);
assign VAR5[3] = VAR8[2] | VAR3[2] & (VAR8[1] | VAR3[1] & (VAR8[0] | VAR3[0] & VAR1));
VAR15 VAR7 (
.VAR17(VAR17[0]),
.VAR14(VAR14[0] ^ VAR1),
.VAR5(VAR5[0]),
.VAR4(VAR11[0])
);
VAR15 VAR19 (
.VAR17(VAR17[1]),
.VAR14(VAR14[1] ^ VAR1),
.VAR5(VAR5[1]),
.VAR4(VAR11[1])
);
VAR15 VAR9 (
.VAR17(VAR17[2]),
.VAR14(VAR14[2] ^ VAR1),
.VAR5(VAR5[2]),
.VAR4(VAR11[2])
);
VAR15 VAR12 (
.VAR17(VAR17[3]),
.VAR14(VAR14[3] ^ VAR1),
.VAR5(VAR5[3]),
.VAR4(VAR11[3])
);
VAR6 VAR18 (
.VAR16(VAR17[3]),
.VAR2(VAR14[3]),
.VAR1(VAR1),
.VAR13(VAR11[3]),
.VAR10(VAR10)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o.pp.symbol.v | 1,431 | module MODULE1 (
input VAR10 ,
input VAR3 ,
input VAR8 ,
input VAR4 ,
input VAR9 ,
output VAR2 ,
input VAR6 ,
input VAR7,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
cliffordwolf/yosys | techlibs/ice40/abc9_model.v | 3,612 | module \VAR11 (
output VAR14,
output VAR15,
input VAR5, VAR2,
input VAR4,
input VAR1, VAR9
);
parameter VAR10 = 0;
parameter VAR18 = 0;
wire VAR12 = VAR18 ? VAR4 : VAR9;
VAR16 VAR17 (
.VAR1(VAR5),
.VAR3(VAR2),
.VAR4(VAR4),
.VAR14(VAR14)
);
VAR13 #(
.VAR6(VAR10)
) VAR8 (
.VAR1(VAR1),
.VAR3(VAR5),
.VAR7(VAR2),
.VAR9(VAR12),
.VAR15(VAR15)
); | isc |
jotego/jt12 | hdl/jt12_pg_inc.v | 1,687 | module MODULE1 (
input [ 2:0] VAR1,
input [10:0] VAR4,
input signed [8:0] VAR5,
output reg [16:0] VAR2
);
reg [11:0] VAR3;
always @(*) begin
VAR3 = {VAR4,1'b0} + {{3{VAR5[8]}},VAR5};
case ( VAR1 )
3'd0: VAR2 = { 7'd0, VAR3[11:2] };
3'd1: VAR2 = { 6'd0, VAR3[11:1] };
3'd2: VAR2 = { 5'd0, VAR3[11:0] };
3'd3: VAR2 = { 4'd0, VAR3, 1'd0 };
3'd4: VAR2 = { 3'd0, VAR3, 2'd0 };
3'd5: VAR2 = { 2'd0, VAR3, 3'd0 };
3'd6: VAR2 = { 1'd0, VAR3, 4'd0 };
3'd7: VAR2 = { VAR3, 5'd0 };
endcase
end
endmodule MODULE1 | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbn/sky130_fd_sc_ms__sdfbbn.pp.blackbox.v | 1,558 | module MODULE1 (
VAR6 ,
VAR11 ,
VAR3 ,
VAR2 ,
VAR10 ,
VAR5 ,
VAR8 ,
VAR12,
VAR4 ,
VAR9 ,
VAR7 ,
VAR1
);
output VAR6 ;
output VAR11 ;
input VAR3 ;
input VAR2 ;
input VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR12;
input VAR4 ;
input VAR9 ;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
sabertazimi/hust-lab | digitalLogic/design/clock_design/src/bcd_to_segment.v | 1,085 | module MODULE1
(
input [3:0] VAR1,
output reg [7:0] VAR2
);
always @(VAR1) begin
case (VAR1)
4'b0000: VAR2 <= 8'b11000000; 4'b0001: VAR2 <= 8'b11111001; 4'b0010: VAR2 <= 8'b10100100; 4'b0011: VAR2 <= 8'b10110000; 4'b0100: VAR2 <= 8'b10011001; 4'b0101: VAR2 <= 8'b10010010; 4'b0110: VAR2 <= 8'b10000010; 4'b0111: VAR2 <= 8'b11111000; 4'b1000: VAR2 <= 8'b10000000; 4'b1001: VAR2 <= 8'b10010000; 4'b1010: VAR2 <= 8'b01111111; default: VAR2 <= 8'b11111111; endcase
end
endmodule | mit |
mammenx/pegasus | wxp/dgn/rtl/l2/mac/peg_l2_fcs_gen.v | 3,233 | module MODULE1 #(
parameter VAR6 = 8,
parameter VAR2 = 32'd0
)
(
input clk,
input VAR5,
input VAR10,
input VAR3,
input [VAR6-1:0] VAR7,
output [31:0] VAR8
);
reg [31:0] VAR9;
genvar VAR1;
always@(posedge clk, negedge VAR5)
begin
if(~VAR5)
begin
VAR9 <= VAR2;
end
else
begin
if(VAR10)
begin
VAR9 <= VAR2;
end
else if(VAR3)
begin
VAR9 <= VAR4(VAR7,VAR9);
end
end
end
generate
for(VAR1=0; VAR1<32; VAR1++)
begin
assign VAR8[VAR1] = ~VAR9[31-VAR1];
end
endgenerate
endmodule | gpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_dc2.v | 8,036 | module MODULE1 (
VAR23,
VAR16
);
parameter VAR8 = 16'h000C;
parameter VAR17 = 16'h001E;
parameter VAR19 = 16'h0400;
parameter VAR14 = 16'h0500;
parameter VAR5 = 16'h0088; parameter VAR4 = 16'h0019; parameter VAR3 = 16'h00C6;
parameter VAR1 = 16'h0019;
parameter VAR15 = 16'h0432;
parameter VAR11 = 16'h0011;
parameter VAR24 = 16'h0000;
parameter VAR7 = 16'h0000;
parameter VAR9 = 16'h0008;
parameter VAR10 = 16'h0000;
parameter VAR18 = 16'h0001;
parameter VAR20 = 16'h040C;
parameter VAR6 = 16'h0129;
parameter VAR26 = 16'h0608;
parameter VAR2 = 16'h00B0;
parameter VAR22 = 16'h00CF;
parameter VAR21 = 16'h00CF;
parameter VAR25 = 16'h00B0;
parameter VAR12 = 16'h000B;
input [ 4: 0] VAR23;
output [35: 0] VAR16;
reg [31: 0] VAR13;
assign VAR16 = {VAR13[31:24], 1'b0,
VAR13[23:16], 1'b0,
VAR13[15: 8], 1'b0,
VAR13[ 7: 0], 1'b0};
always @(*)
begin
case (VAR23)
0 : VAR13 <= {8'hBA, 8'h01, VAR8};
1 : VAR13 <= {8'hBA, 8'h02, VAR17};
2 : VAR13 <= {8'hBA, 8'h03, VAR19};
3 : VAR13 <= {8'hBA, 8'h04, VAR14};
4 : VAR13 <= {8'hBA, 8'h05, VAR5};
5 : VAR13 <= {8'hBA, 8'h06, VAR4};
6 : VAR13 <= {8'hBA, 8'h07, VAR3};
7 : VAR13 <= {8'hBA, 8'h08, VAR1};
8 : VAR13 <= {8'hBA, 8'h09, VAR15};
9 : VAR13 <= {8'hBA, 8'h0A, VAR11};
10 : VAR13 <= {8'hBA, 8'h0B, VAR24};
11 : VAR13 <= {8'hBA, 8'h0C, VAR7};
12 : VAR13 <= {8'hBA, 8'h0D, VAR9};
13 : VAR13 <= {8'hBA, 8'h1F, VAR10};
14 : VAR13 <= {8'hBA, 8'h20, VAR18};
15 : VAR13 <= {8'hBA, 8'h21, VAR20};
16 : VAR13 <= {8'hBA, 8'h22, VAR6};
17 : VAR13 <= {8'hBA, 8'h23, VAR26};
18 : VAR13 <= {8'hBA, 8'h2B, VAR2};
19 : VAR13 <= {8'hBA, 8'h2C, VAR22};
20 : VAR13 <= {8'hBA, 8'h2D, VAR21};
21 : VAR13 <= {8'hBA, 8'h2E, VAR25};
22 : VAR13 <= {8'hBA, 8'hC8, VAR12};
default : VAR13 <= 32'h00000000;
endcase
end
endmodule | mit |
alexforencich/verilog-ethernet | example/fb2CG/fpga_10g/rtl/fpga.v | 23,060 | module MODULE1 (
input wire VAR42,
output wire VAR261,
output wire VAR312,
output wire VAR267,
output wire [1:0] VAR194,
output wire [1:0] VAR280,
input wire [1:0] VAR163,
output wire VAR41,
output wire VAR209,
input wire VAR292,
input wire VAR109,
output wire VAR90,
output wire VAR72,
input wire VAR164,
input wire VAR28,
output wire VAR295,
output wire VAR79,
input wire VAR124,
input wire VAR149,
output wire VAR193,
output wire VAR237,
input wire VAR210,
input wire VAR199,
input wire VAR169,
input wire VAR116,
input wire VAR70,
output wire VAR136,
output wire VAR94,
input wire VAR85,
output wire VAR54,
output wire VAR65,
input wire VAR38,
input wire VAR115,
output wire VAR314,
output wire VAR34,
input wire VAR52,
input wire VAR204,
output wire VAR4,
output wire VAR236,
input wire VAR186,
input wire VAR56,
output wire VAR14,
output wire VAR234,
input wire VAR227,
input wire VAR281,
input wire VAR325,
input wire VAR37,
input wire VAR69,
output wire VAR220,
output wire VAR33,
input wire VAR75
);
wire VAR17;
wire VAR198;
wire VAR131;
wire VAR7;
wire VAR105;
wire VAR39;
wire VAR73 = !VAR163[0] || !VAR163[1];
wire VAR161;
wire VAR36;
VAR217
VAR119 (
.VAR153(VAR42),
.VAR110(VAR17)
);
VAR87 #(
.VAR157("VAR299"),
.VAR324(8),
.VAR221(0.5),
.VAR154(0),
.VAR195(1),
.VAR288(0.5),
.VAR294(0),
.VAR127(1),
.VAR182(0.5),
.VAR137(0),
.VAR214(1),
.VAR3(0.5),
.VAR27(0),
.VAR268(1),
.VAR208(0.5),
.VAR150(0),
.VAR113(1),
.VAR334(0.5),
.VAR9(0),
.VAR111(1),
.VAR329(0.5),
.VAR326(0),
.VAR32(20),
.VAR126(0),
.VAR269(1),
.VAR342(0.010),
.VAR191(20.000),
.VAR142("VAR190"),
.VAR290("VAR190")
)
VAR211 (
.VAR228(VAR17),
.VAR15(VAR36),
.VAR266(VAR73),
.VAR188(1'b0),
.VAR151(VAR198),
.VAR244(),
.VAR57(),
.VAR58(),
.VAR177(),
.VAR296(),
.VAR64(),
.VAR171(),
.VAR91(),
.VAR162(),
.VAR88(),
.VAR275(VAR36),
.VAR336(),
.VAR258(VAR161)
);
VAR217
VAR5 (
.VAR153(VAR198),
.VAR110(VAR131)
);
VAR179 #(
.VAR59(4)
)
VAR276 (
.clk(VAR131),
.rst(~VAR161),
.out(VAR7)
);
wire [7:0] VAR249;
wire [7:0] VAR130;
wire [15:0] VAR197;
assign VAR197[0] = VAR249[0];
assign VAR197[1] = VAR130[0];
assign VAR197[2] = VAR249[1];
assign VAR197[3] = VAR130[1];
assign VAR197[4] = VAR249[2];
assign VAR197[5] = VAR130[2];
assign VAR197[6] = VAR249[3];
assign VAR197[7] = VAR130[3];
assign VAR197[8] = VAR249[4];
assign VAR197[9] = VAR130[4];
assign VAR197[10] = VAR249[5];
assign VAR197[11] = VAR130[5];
assign VAR197[12] = VAR249[6];
assign VAR197[13] = VAR130[6];
assign VAR197[14] = VAR249[7];
assign VAR197[15] = VAR130[7];
VAR264 #(
.VAR141(16),
.VAR120(1),
.VAR128(31)
)
VAR47 (
.clk(VAR131),
.rst(VAR7),
.VAR240(VAR197),
.VAR82(VAR261),
.VAR89(VAR312),
.VAR338(VAR267)
);
assign VAR136 = 1'b1;
assign VAR94 = 1'b0;
wire VAR46;
wire VAR304;
wire [63:0] VAR22;
wire [7:0] VAR165;
wire VAR53;
wire VAR66;
wire [63:0] VAR78;
wire [7:0] VAR20;
wire VAR24;
wire VAR337;
wire [63:0] VAR271;
wire [7:0] VAR100;
wire VAR118;
wire VAR270;
wire [63:0] VAR225;
wire [7:0] VAR263;
wire VAR277;
wire VAR273;
wire [63:0] VAR31;
wire [7:0] VAR10;
wire VAR283;
wire VAR265;
wire [63:0] VAR226;
wire [7:0] VAR245;
wire VAR340;
wire VAR121;
wire [63:0] VAR309;
wire [7:0] VAR272;
wire VAR308;
wire VAR302;
wire [63:0] VAR62;
wire [7:0] VAR254;
assign VAR105 = VAR46;
assign VAR39 = VAR304;
wire VAR160;
wire VAR223;
wire VAR180;
wire VAR305;
wire VAR322;
wire VAR101;
wire VAR107;
wire VAR289;
VAR256 VAR311 (
.VAR153 (VAR169),
.VAR61 (VAR116),
.VAR92 (1'b0),
.VAR110 (VAR101),
.VAR257 (VAR107)
);
VAR8 VAR319 (
.VAR95 (VAR322),
.VAR74 (1'b1),
.VAR286 (1'b0),
.VAR133 (1'b1),
.VAR192 (3'd0),
.VAR153 (VAR107),
.VAR110 (VAR289)
);
wire VAR341;
VAR179 #(
.VAR59(4)
)
VAR219 (
.clk(VAR289),
.rst(VAR7),
.out(VAR341)
);
wire VAR11;
wire VAR86;
wire VAR339;
VAR196 #(
.VAR205(1)
)
VAR251 (
.VAR247(VAR131),
.VAR287(VAR341),
.VAR159(VAR322),
.VAR315(VAR101),
.VAR239(VAR11),
.VAR332(VAR86),
.VAR102(VAR339),
.VAR230(1'b0),
.VAR178(),
.VAR63(1'b0),
.VAR222(1'b0),
.VAR45(VAR41),
.VAR260(VAR209),
.VAR323(VAR292),
.VAR21(VAR109),
.VAR117(VAR46),
.VAR242(VAR304),
.VAR167(VAR22),
.VAR248(VAR165),
.VAR83(VAR53),
.VAR93(VAR66),
.VAR98(VAR78),
.VAR173(VAR20),
.VAR218(),
.VAR335(),
.VAR316(),
.VAR44(),
.VAR71(VAR160),
.VAR301(),
.VAR229(),
.VAR215()
);
VAR196 #(
.VAR205(0)
)
VAR259 (
.VAR247(VAR131),
.VAR287(VAR341),
.VAR159(),
.VAR315(1'b0),
.VAR239(),
.VAR332(),
.VAR102(),
.VAR230(VAR11),
.VAR178(),
.VAR63(VAR86),
.VAR222(VAR339),
.VAR45(VAR90),
.VAR260(VAR72),
.VAR323(VAR164),
.VAR21(VAR28),
.VAR117(VAR24),
.VAR242(VAR337),
.VAR167(VAR271),
.VAR248(VAR100),
.VAR83(VAR118),
.VAR93(VAR270),
.VAR98(VAR225),
.VAR173(VAR263),
.VAR218(),
.VAR335(),
.VAR316(),
.VAR44(),
.VAR71(VAR223),
.VAR301(),
.VAR229(),
.VAR215()
);
VAR196 #(
.VAR205(0)
)
VAR35 (
.VAR247(VAR131),
.VAR287(VAR341),
.VAR159(),
.VAR315(1'b0),
.VAR239(),
.VAR332(),
.VAR102(),
.VAR230(VAR11),
.VAR178(),
.VAR63(VAR86),
.VAR222(VAR339),
.VAR45(VAR295),
.VAR260(VAR79),
.VAR323(VAR124),
.VAR21(VAR149),
.VAR117(VAR277),
.VAR242(VAR273),
.VAR167(VAR31),
.VAR248(VAR10),
.VAR83(VAR283),
.VAR93(VAR265),
.VAR98(VAR226),
.VAR173(VAR245),
.VAR218(),
.VAR335(),
.VAR316(),
.VAR44(),
.VAR71(VAR180),
.VAR301(),
.VAR229(),
.VAR215()
);
VAR196 #(
.VAR205(0)
)
VAR122 (
.VAR247(VAR131),
.VAR287(VAR341),
.VAR159(),
.VAR315(1'b0),
.VAR239(),
.VAR332(),
.VAR102(),
.VAR230(VAR11),
.VAR178(),
.VAR63(VAR86),
.VAR222(VAR339),
.VAR45(VAR193),
.VAR260(VAR237),
.VAR323(VAR210),
.VAR21(VAR199),
.VAR117(VAR340),
.VAR242(VAR121),
.VAR167(VAR309),
.VAR248(VAR272),
.VAR83(VAR308),
.VAR93(VAR302),
.VAR98(VAR62),
.VAR173(VAR254),
.VAR218(),
.VAR335(),
.VAR316(),
.VAR44(),
.VAR71(VAR305),
.VAR301(),
.VAR229(),
.VAR215()
);
assign VAR220 = 1'b1;
assign VAR33 = 1'b0;
wire VAR13;
wire VAR184;
wire [63:0] VAR43;
wire [7:0] VAR297;
wire VAR155;
wire VAR284;
wire [63:0] VAR262;
wire [7:0] VAR84;
wire VAR313;
wire VAR246;
wire [63:0] VAR2;
wire [7:0] VAR174;
wire VAR129;
wire VAR203;
wire [63:0] VAR212;
wire [7:0] VAR274;
wire VAR49;
wire VAR40;
wire [63:0] VAR300;
wire [7:0] VAR16;
wire VAR331;
wire VAR76;
wire [63:0] VAR25;
wire [7:0] VAR202;
wire VAR23;
wire VAR114;
wire [63:0] VAR30;
wire [7:0] VAR172;
wire VAR138;
wire VAR143;
wire [63:0] VAR145;
wire [7:0] VAR291;
wire VAR96;
wire VAR158;
wire VAR48;
wire VAR328;
wire VAR327;
wire VAR125;
wire VAR170;
wire VAR135;
VAR256 VAR148 (
.VAR153 (VAR325),
.VAR61 (VAR37),
.VAR92 (1'b0),
.VAR110 (VAR125),
.VAR257 (VAR170)
);
VAR8 VAR18 (
.VAR95 (VAR327),
.VAR74 (1'b1),
.VAR286 (1'b0),
.VAR133 (1'b1),
.VAR192 (3'd0),
.VAR153 (VAR170),
.VAR110 (VAR135)
);
wire VAR80;
VAR179 #(
.VAR59(4)
)
VAR282 (
.clk(VAR135),
.rst(VAR7),
.out(VAR80)
);
wire VAR231;
wire VAR200;
wire VAR187;
VAR196 #(
.VAR205(1)
)
VAR134 (
.VAR247(VAR131),
.VAR287(VAR80),
.VAR159(VAR327),
.VAR315(VAR125),
.VAR239(VAR231),
.VAR332(VAR200),
.VAR102(VAR187),
.VAR230(1'b0),
.VAR178(),
.VAR63(1'b0),
.VAR222(1'b0),
.VAR45(VAR54),
.VAR260(VAR65),
.VAR323(VAR38),
.VAR21(VAR115),
.VAR117(VAR13),
.VAR242(VAR184),
.VAR167(VAR43),
.VAR248(VAR297),
.VAR83(VAR155),
.VAR93(VAR284),
.VAR98(VAR262),
.VAR173(VAR84),
.VAR218(),
.VAR335(),
.VAR316(),
.VAR44(),
.VAR71(VAR96),
.VAR301(),
.VAR229(),
.VAR215()
);
VAR196 #(
.VAR205(0)
)
VAR330 (
.VAR247(VAR131),
.VAR287(VAR80),
.VAR159(),
.VAR315(1'b0),
.VAR239(),
.VAR332(),
.VAR102(),
.VAR230(VAR231),
.VAR178(),
.VAR63(VAR200),
.VAR222(VAR187),
.VAR45(VAR314),
.VAR260(VAR34),
.VAR323(VAR52),
.VAR21(VAR204),
.VAR117(VAR313),
.VAR242(VAR246),
.VAR167(VAR2),
.VAR248(VAR174),
.VAR83(VAR129),
.VAR93(VAR203),
.VAR98(VAR212),
.VAR173(VAR274),
.VAR218(),
.VAR335(),
.VAR316(),
.VAR44(),
.VAR71(VAR158),
.VAR301(),
.VAR229(),
.VAR215()
);
VAR196 #(
.VAR205(0)
)
VAR60 (
.VAR247(VAR131),
.VAR287(VAR80),
.VAR159(),
.VAR315(1'b0),
.VAR239(),
.VAR332(),
.VAR102(),
.VAR230(VAR231),
.VAR178(),
.VAR63(VAR200),
.VAR222(VAR187),
.VAR45(VAR4),
.VAR260(VAR236),
.VAR323(VAR186),
.VAR21(VAR56),
.VAR117(VAR49),
.VAR242(VAR40),
.VAR167(VAR300),
.VAR248(VAR16),
.VAR83(VAR331),
.VAR93(VAR76),
.VAR98(VAR25),
.VAR173(VAR202),
.VAR218(),
.VAR335(),
.VAR316(),
.VAR44(),
.VAR71(VAR48),
.VAR301(),
.VAR229(),
.VAR215()
);
VAR196 #(
.VAR205(0)
)
VAR318 (
.VAR247(VAR131),
.VAR287(VAR80),
.VAR159(),
.VAR315(1'b0),
.VAR239(),
.VAR332(),
.VAR102(),
.VAR230(VAR231),
.VAR178(),
.VAR63(VAR200),
.VAR222(VAR187),
.VAR45(VAR14),
.VAR260(VAR234),
.VAR323(VAR227),
.VAR21(VAR281),
.VAR117(VAR23),
.VAR242(VAR114),
.VAR167(VAR30),
.VAR248(VAR172),
.VAR83(VAR138),
.VAR93(VAR143),
.VAR98(VAR145),
.VAR173(VAR291),
.VAR218(),
.VAR335(),
.VAR316(),
.VAR44(),
.VAR71(VAR328),
.VAR301(),
.VAR229(),
.VAR215()
);
assign VAR130[0] = VAR160;
assign VAR130[1] = VAR223;
assign VAR130[2] = VAR180;
assign VAR130[3] = VAR305;
assign VAR130[4] = VAR96;
assign VAR130[5] = VAR158;
assign VAR130[6] = VAR48;
assign VAR130[7] = VAR328;
VAR279
VAR12 (
.clk(VAR105),
.rst(VAR39),
.VAR249(VAR249),
.VAR194(VAR194),
.VAR280(VAR280),
.VAR252(VAR46),
.VAR303(VAR304),
.VAR238(VAR22),
.VAR97(VAR165),
.VAR139(VAR53),
.VAR77(VAR66),
.VAR185(VAR78),
.VAR176(VAR20),
.VAR68(VAR24),
.VAR99(VAR337),
.VAR104(VAR271),
.VAR168(VAR100),
.VAR285(VAR118),
.VAR123(VAR270),
.VAR183(VAR225),
.VAR19(VAR263),
.VAR250(VAR277),
.VAR213(VAR273),
.VAR152(VAR31),
.VAR333(VAR10),
.VAR50(VAR283),
.VAR278(VAR265),
.VAR140(VAR226),
.VAR320(VAR245),
.VAR81(VAR340),
.VAR166(VAR121),
.VAR243(VAR309),
.VAR189(VAR272),
.VAR307(VAR308),
.VAR235(VAR302),
.VAR224(VAR62),
.VAR67(VAR254),
.VAR306(VAR13),
.VAR26(VAR184),
.VAR144(VAR43),
.VAR108(VAR297),
.VAR253(VAR155),
.VAR106(VAR284),
.VAR175(VAR262),
.VAR6(VAR84),
.VAR103(VAR313),
.VAR55(VAR246),
.VAR232(VAR2),
.VAR51(VAR174),
.VAR293(VAR129),
.VAR298(VAR203),
.VAR112(VAR212),
.VAR132(VAR274),
.VAR317(VAR49),
.VAR216(VAR40),
.VAR241(VAR300),
.VAR233(VAR16),
.VAR206(VAR331),
.VAR181(VAR76),
.VAR147(VAR25),
.VAR156(VAR202),
.VAR1(VAR23),
.VAR310(VAR114),
.VAR321(VAR30),
.VAR255(VAR172),
.VAR207(VAR138),
.VAR146(VAR143),
.VAR201(VAR145),
.VAR29(VAR291)
);
endmodule | mit |
kylemsguy/FPGA-Litecoin-Miner | experimental/DE2-115-SLOWSIXTEEN/ltcminer.v | 7,404 | module MODULE1 (VAR15); else
module MODULE1 (VAR15, VAR52);
parameter VAR67 = VAR67;
parameter VAR67 = 25;
parameter VAR3 = VAR3;
parameter VAR3 = 1;
function integer VAR11; input integer VAR54;
begin
VAR54 = VAR54-1;
for (VAR11=0; VAR54>0; VAR11=VAR11+1)
VAR54 = VAR54>>1;
end
endfunction
parameter VAR27 = VAR27; else
parameter VAR27 = 12 - VAR11(VAR3); VAR45
localparam VAR5 = 8;
input VAR15;
output reg [7:0]VAR52; VAR45
wire VAR58;
VAR22 #(.VAR67(VAR67)) VAR61 (VAR15, VAR58);
assign VAR58 = VAR15;
reg [255:0] VAR60 = 256'd0;
reg [255:0] VAR57 = 256'd0;
reg [127:0] VAR55 = 128'd0;
reg [255:0] VAR60 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg [255:0] VAR57 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
reg [127:0] VAR55 = 128'h0000318f7e71441b141fe951b2b0c7df; VAR45
reg [31:0] VAR16 = 31'h000007ff;
wire [31:0]VAR39;
wire [31:0] VAR35;
wire VAR47 = 1'b0; wire [VAR3*32-1:0] VAR17;
wire [VAR3-1:0] VAR49;
wire VAR10 = VAR58;
generate
genvar VAR28;
for (VAR28 = 0; VAR28 < VAR3; VAR28 = VAR28 + 1)
begin: VAR26
wire [31:0] VAR42;
wire [3:0] VAR63 = VAR28;
wire VAR66;
wire VAR38, VAR20, VAR64, VAR12, VAR68;
wire [VAR5-1:0] VAR56;
wire [VAR5-1:0] VAR13;
wire [3:0] VAR51;
VAR53 #(.VAR5(VAR5)) VAR65
(.VAR58(VAR58), .VAR10(VAR10), .VAR60(VAR60), .VAR57(VAR57), .VAR55(VAR55), .VAR16(VAR16),
.VAR70({VAR63}), .VAR35(VAR42), .VAR39(VAR17[(VAR28+1)*32-1:VAR28*32]),
.VAR49(VAR49[VAR28]), .VAR47(VAR47),
.VAR56(VAR56), .VAR13(VAR13), .VAR38(VAR38), .VAR20(VAR20),
.VAR64(VAR64), .VAR12(VAR12), .VAR68(VAR68));
VAR43 #(.VAR27(VAR27), .VAR5(VAR5)) VAR18
(.VAR58(VAR58), .reset(VAR64), .din(VAR56), .dout(VAR13),
.VAR1(VAR68), .VAR33(VAR12), .VAR23(VAR38), .VAR34(VAR20) );
if (VAR28==0)
assign VAR35 = VAR42;
end endgenerate
reg [VAR3-1:0]VAR41 = 0;
reg [VAR11(VAR3)+1:0] VAR7 = 0;
reg [VAR3*32-1:0] VAR48 = 0;
assign VAR39 = VAR48[31:0];
reg [VAR3-1:0] VAR40 = 0;
always @(posedge VAR10)
begin
VAR41 <= (VAR41 & ~VAR40) | VAR49;
if (VAR7 == VAR3-1)
VAR7 <= 0;
end
else
VAR7 <= VAR7 + 1'd1;
if (VAR41[VAR7])
begin
VAR48 <= VAR17 >> VAR7*32;
VAR40[VAR7] <= 1;
end
else
begin
VAR40 <= 0;
end
end
wire [255:0] VAR32;
wire [255:0] VAR24;
wire [127:0] VAR50; wire [31:0] VAR14;
VAR44 # (.VAR21(0), .VAR59(256), .VAR6("VAR4")) VAR36(.VAR30(), .VAR37(VAR32));
VAR44 # (.VAR21(0), .VAR59(256), .VAR6("VAR29")) VAR62(.VAR30(), .VAR37(VAR24));
VAR44 # (.VAR21(0), .VAR59(128), .VAR6("VAR46")) VAR31(.VAR30(), .VAR37(VAR50));
VAR44 # (.VAR21(0), .VAR59(32), .VAR6("VAR69")) VAR19(.VAR30(), .VAR37(VAR14));
always @ (posedge VAR10)
begin
VAR60 <= VAR32;
VAR57 <= VAR24;
VAR55 <= VAR50;
VAR16 <= VAR14;
end
VAR44 # (.VAR21(32), .VAR59(0), .VAR6("VAR9")) VAR2 (.VAR30(VAR39), .VAR37());
VAR44 # (.VAR21(32), .VAR59(0), .VAR6("VAR8")) VAR25 (.VAR30(VAR35), .VAR37());
always @(posedge VAR10) begin
end
VAR52 <= ~VAR35[15:8]; else
VAR52 <= VAR35[15:8];
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtn/sky130_fd_sc_lp__sdfrtn.symbol.v | 1,508 | module MODULE1 (
input VAR7 ,
output VAR10 ,
input VAR6,
input VAR8 ,
input VAR9 ,
input VAR4
);
supply1 VAR5;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_regslice.v | 5,444 | module MODULE1
parameter VAR19 = 64,
parameter VAR14 = 64,
parameter VAR2 = 3 ,
parameter VAR9 = 2
)
(
input [VAR19-1:0 ] din ,
output [VAR19-1:0 ] dout ,
output [VAR19-1:0 ] VAR10 ,
input [VAR14-1:0] VAR8 ,
output [VAR14-1:0] VAR13 ,
output VAR15 ,
output reg VAR4,
output VAR11 ,
input clk ,
input reset
);
reg [VAR19-1:0] VAR3 [0:VAR2-1];
reg [VAR14-1:0] VAR5 [0:VAR9-1];
reg [VAR2-1:0] VAR12 ;
reg [VAR9-1:0] VAR17 ;
integer VAR18;
wire VAR6 = (din != VAR3[VAR2-1]);
wire VAR7 = (VAR8 != VAR5[VAR9-1]);
always @(posedge clk)
begin
if(reset)
begin
for(VAR18 = 0; VAR18 <VAR2 ; VAR18 = VAR18 + 1)
VAR3[VAR18] <= 0;
for(VAR18 = 0; VAR18 <VAR9 ; VAR18 = VAR18 + 1)
VAR5[VAR18] <= 0;
VAR17 <= 0;
VAR12 <= 0;
end
else
begin
VAR3[VAR2-1] <= din;
VAR5[VAR9-1] <= VAR8;
VAR12[VAR2-1] <= VAR6;
VAR17[VAR9-1] <= VAR7;
for(VAR18 = 0; VAR18 <VAR2-1 ; VAR18 = VAR18 + 1)
VAR3[VAR18] <= VAR3[VAR18+1];
for(VAR18 = 0; VAR18 <VAR2-1 ; VAR18 = VAR18 + 1)
VAR12[VAR18] <= VAR12[VAR18+1];
for(VAR18 = 0; VAR18 <VAR9-1 ; VAR18 = VAR18 + 1)
VAR5[VAR18] <= VAR5[VAR18+1];
for(VAR18 = 0; VAR18 <VAR9-1 ; VAR18 = VAR18 + 1)
VAR17[VAR18] <= VAR17[VAR18+1];
VAR4 <= VAR15;
end
end
generate
if (VAR2 > 1) begin : VAR1
assign VAR10 = VAR3[1];
end else begin : VAR16
assign VAR10 = 0;
end
endgenerate
assign dout = VAR3[0];
assign VAR13 = VAR5[0];
assign VAR15 = (VAR17 == 0) && (VAR7==0);
assign VAR11 = (VAR12 == 0) && (VAR12 == 0);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.pp.symbol.v | 1,230 | module MODULE1 (
input VAR2 ,
input VAR1 ,
output VAR4 ,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr.behavioral.v | 1,493 | module MODULE1 (
VAR8,
VAR1
);
output VAR8;
input VAR1;
supply1 VAR9 ;
supply0 VAR3 ;
supply1 VAR4;
supply1 VAR6 ;
supply0 VAR10 ;
wire VAR7;
buf VAR5 (VAR7, VAR1 );
buf VAR2 (VAR8 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.v | 2,686 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR9 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR2 ,
VAR4,
VAR8 ,
VAR10
);
output VAR3 ;
output VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR11 ;
input VAR1 ;
input VAR2 ;
input VAR4;
input VAR8 ;
input VAR10 ;
VAR12 VAR5 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODULE1 (
VAR3 ,
VAR7 ,
VAR9 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR2 ,
VAR4
);
output VAR3 ;
output VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR11 ;
input VAR1 ;
input VAR2 ;
input VAR4;
supply1 VAR8;
supply0 VAR10;
VAR12 VAR5 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn_0.v | 2,150 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR4,
VAR6,
VAR3,
VAR9 ,
VAR5
);
output VAR7 ;
input VAR2 ;
input VAR4;
input VAR6;
input VAR3;
input VAR9 ;
input VAR5 ;
VAR8 VAR1 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7 ,
VAR2 ,
VAR4
);
output VAR7 ;
input VAR2 ;
input VAR4;
supply1 VAR6;
supply0 VAR3;
supply1 VAR9 ;
supply0 VAR5 ;
VAR8 VAR1 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.functional.v | 1,664 | module MODULE1( VAR13, VAR17, VAR9, VAR1, VAR16, VAR11 );
input VAR1, VAR9, VAR13, VAR17, VAR11;
output VAR16;
wire VAR21;
not VAR20( VAR21, VAR9 );
wire VAR22;
not VAR14( VAR22, VAR13 );
wire VAR7;
and VAR10( VAR7, VAR21, VAR22 );
wire VAR6;
not VAR12( VAR6, VAR17 );
wire VAR2;
and VAR8( VAR2, VAR21, VAR6 );
wire VAR3;
and VAR5( VAR3, VAR6, VAR13 );
or VAR15( VAR4, VAR7, VAR2, VAR3 );
VAR23( VAR18, 1'b0, 1'b0, VAR1, VAR4, VAR11 );
not VAR19( VAR16, VAR18 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a.behavioral.pp.v | 2,156 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR6 ,
VAR15 ,
VAR9 ,
VAR19,
VAR8,
VAR13 ,
VAR18
);
output VAR1 ;
input VAR10 ;
input VAR6 ;
input VAR15 ;
input VAR9 ;
input VAR19;
input VAR8;
input VAR13 ;
input VAR18 ;
wire VAR11 ;
wire VAR17 ;
wire VAR7 ;
wire VAR3;
or VAR2 (VAR11 , VAR6, VAR10 );
or VAR14 (VAR17 , VAR9, VAR15 );
and VAR12 (VAR7 , VAR11, VAR17 );
VAR4 VAR16 (VAR3, VAR7, VAR19, VAR8);
buf VAR5 (VAR1 , VAR3 );
endmodule | apache-2.0 |
vkchettimada/aayudha | mojo/src/serial_tx.v | 2,895 | module MODULE1 #(
parameter VAR18 = 50
)(
input clk,
input rst,
output VAR5,
input VAR11,
output VAR3,
input [7:0] VAR20,
input VAR15
);
parameter VAR10 = VAR16(VAR18);
localparam VAR13 = 2;
localparam VAR17 = 2'd0,
VAR27 = 2'd1,
VAR24 = 2'd2,
VAR22 = 2'd3;
reg [VAR10-1:0] VAR25, VAR8;
reg [2:0] VAR9, VAR1;
reg [7:0] VAR14, VAR21;
reg [VAR13-1:0] VAR4, VAR7 = VAR17;
reg VAR6, VAR19;
reg VAR23, VAR12;
reg VAR2, VAR26;
assign VAR5 = VAR19;
assign VAR3 = VAR12;
always @(*) begin
VAR2 = VAR11;
VAR25 = VAR8;
VAR9 = VAR1;
VAR14 = VAR21;
VAR4 = VAR7;
VAR23 = VAR12;
case (VAR7)
VAR17: begin
if (VAR26) begin
VAR23 = 1'b1;
VAR6 = 1'b1;
end else begin
VAR23 = 1'b0;
VAR6 = 1'b1;
VAR9 = 3'b0;
VAR25 = 1'b0;
if (VAR15) begin
VAR14 = VAR20;
VAR4 = VAR27;
VAR23 = 1'b1;
end
end
end
VAR27: begin
VAR23 = 1'b1;
VAR25 = VAR8 + 1'b1;
VAR6 = 1'b0;
if (VAR8 == VAR18 - 1) begin
VAR25 = 1'b0;
VAR4 = VAR24;
end
end
VAR24: begin
VAR23 = 1'b1;
VAR6 = VAR21[VAR1];
VAR25 = VAR8 + 1'b1;
if (VAR8 == VAR18 - 1) begin
VAR25 = 1'b0;
VAR9 = VAR1 + 1'b1;
if (VAR1 == 7) begin
VAR4 = VAR22;
end
end
end
VAR22: begin
VAR23 = 1'b1;
VAR6 = 1'b1;
VAR25 = VAR8 + 1'b1;
if (VAR8 == VAR18 - 1) begin
VAR4 = VAR17;
end
end
default: begin
VAR4 = VAR17;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
VAR7 <= VAR17;
VAR19 <= 1'b1;
end else begin
VAR7 <= VAR4;
VAR19 <= VAR6;
end
VAR26 <= VAR2;
VAR21 <= VAR14;
VAR1 <= VAR9;
VAR8 <= VAR25;
VAR12 <= VAR23;
end
endmodule | mit |
cr88192/bgbtech_bjx1core | smalltst/compdec/FbNtMod_0.v | 17,924 | module MODULE1(VAR84, reset, VAR57,
VAR14, VAR39, VAR40, VAR24, VAR97);
input VAR84;
input reset;
output[3:0] VAR57;
input[39:0] VAR14;
inout[31:0] VAR39;
input VAR40;
input VAR24;
output VAR97;
reg[7:0] VAR110[31:0];
reg VAR50; reg[31:0] VAR88; wire VAR19;
assign VAR97 = (VAR40 && VAR19) ? VAR50 : 1'VAR29;
assign VAR39 = (VAR40 && VAR19) ? VAR88 : 32'VAR49;
assign VAR19 = (VAR14[39:16]==24'hA0A000);
reg[3:0] VAR82; reg[3:0] VAR83; reg[3:0] VAR75; reg[7:0] VAR67; reg[7:0] VAR66; reg VAR78;
reg[21:0] VAR70; reg[21:0] VAR91;
reg[12:0] VAR25; reg[12:0] VAR79;
reg[10:0] VAR102; reg[10:0] VAR92;
reg[2:0] VAR13;
reg[2:0] VAR30;
reg[2:0] VAR104;
reg[2:0] VAR10;
reg[1:0] VAR51;
reg[1:0] VAR63;
reg[4:0] VAR99;
reg[4:0] VAR26;
reg[4:0] VAR31;
reg[15:0] VAR28;
reg[15:0] VAR71;
reg[15:0] VAR107;
reg[15:0] VAR12;
reg[15:0] VAR48;
reg[15:0] VAR15;
reg[15:0] VAR56;
reg[15:0] VAR74;
reg[15:0] VAR54;
reg[15:0] VAR21;
reg[17:0] VAR93;
reg[15:0] VAR86;
reg[15:0] VAR101;
reg[9:0] VAR34;
reg[9:0] VAR33;
reg[9:0] VAR45;
reg[9:0] VAR61;
reg[9:0] VAR46;
reg[7:0] VAR52;
reg[7:0] VAR6;
reg[7:0] VAR72;
reg[7:0] VAR22;
reg[7:0] VAR80;
reg[7:0] VAR106;
assign VAR57 = VAR82;
reg[13:0] VAR17; reg[13:0] VAR68;
reg[13:0] VAR42; reg[3:0] VAR85;
reg[13:0] VAR41; reg[3:0] VAR36;
reg[31:0] VAR53[0:4095]; reg[31:0] VAR59[0:4095]; reg[31:0] VAR87[0:1023]; reg[31:0] VAR105[0:1023];
reg[31:0] VAR103[7:0]; reg VAR90;
reg VAR73;
reg[31:0] VAR64;
reg[31:0] VAR37;
reg[31:0] VAR44;
reg[31:0] VAR16;
reg[31:0] VAR95;
reg[9:0] VAR60;
reg[9:0] VAR32;
reg[9:0] VAR96;
reg[9:0] VAR5;
reg[9:0] VAR76;
reg[9:0] VAR4;
reg[9:0] VAR2;
reg[9:0] VAR81;
reg[9:0] VAR108;
reg[9:0] VAR38;
reg[9:0] VAR94;
reg[9:0] VAR23;
reg[9:0] VAR9;
reg[9:0] VAR47;
reg[9:0] VAR98;
reg[9:0] VAR65;
reg[7:0] VAR43;
reg[7:0] VAR77;
reg[7:0] VAR11;
reg[7:0] VAR20;
reg[7:0] VAR58;
reg[7:0] VAR18;
reg[7:0] VAR27;
reg[7:0] VAR1;
reg[7:0] VAR100;
reg[7:0] VAR3;
reg[7:0] VAR8;
reg[7:0] VAR109;
reg[1:0] VAR62;
reg[1:0] VAR89;
reg[31:0] VAR69;
reg[31:0] VAR7;
reg VAR35;
reg VAR55;
begin
begin
begin
end
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
begin
end
begin
end
begin
end
begin | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/bsg_source_sync_channel_control_slave.v | 12,877 | module MODULE1 #( parameter VAR39(VAR13 )
, VAR29 = "VAR5")
( input VAR45
, input VAR43
, output reg VAR1
, output VAR48
, output [VAR13+1-1:0] VAR18
, input [VAR13+1-1:0] VAR40
, input VAR28
, output VAR23
, output VAR32
, output logic VAR12
, input VAR27 , output VAR31
, output VAR49
);
wire [4:0] VAR4;
wire VAR52;
wire [(((VAR13+1)>>1)<<1)-1:0] VAR47
= { ((VAR13+1) >> 1) { (2'b10) } };
if (VAR13 >= 4)
assign VAR4 = { VAR40[(VAR13)-:5] };
else
assign VAR4 = { VAR40[(VAR13)-:4], 1'b0};
if (VAR13 <= 4)
assign VAR52 = 1'b0;
else
assign VAR52
= | ( VAR47[VAR13+1-VAR44(VAR4)-1:0]
^ VAR40[VAR13+1-VAR44(VAR4)-1:0]
);
typedef enum logic [3:0] { VAR16
, VAR8
, VAR42
, VAR30
, VAR24
, VAR25
, VAR36
, VAR41
}
VAR6;
VAR6 VAR26, VAR17;
always @(posedge VAR45)
if (VAR43)
VAR17 <= VAR16;
else
VAR17 <= VAR26;
VAR7
begin
VAR26 = VAR17;
if (VAR17 == VAR16) begin
unique casez (VAR4)
5'b0?111: VAR26 = VAR41; 5'b01?10: VAR26 = VAR41; 5'b01011: VAR26 = VAR41; 5'b01101: VAR26 = VAR41; 5'b11111: VAR26 = VAR41;
5'b00100: VAR26 = VAR8;
5'b00101: VAR26 = VAR42;
5'b00010: VAR26 = VAR30;
5'b00011: VAR26 = VAR24;
5'b00110:
begin
VAR26 = VAR52 ? VAR36 : VAR25;
end
5'b0100?: VAR26 = VAR36;
default: VAR26 = VAR30;
endcase
end end
localparam VAR20 = 24;
localparam VAR10 = VAR22(VAR20,(VAR13+1)*2+1);
logic [VAR10-1:0] VAR51, VAR15;
logic [7:0] VAR11, VAR3;
logic [VAR13+1-1:0] VAR34, VAR53;
logic VAR33, VAR2;
assign VAR18 = VAR34;
assign VAR48 = VAR33;
logic VAR9;
VAR21 @(posedge VAR45)
begin
VAR9 <= VAR43;
VAR1 <= ~VAR43
& (VAR26 == VAR41)
& (VAR17 == VAR16);
VAR33 <= VAR2;
if (VAR43 ^ VAR9)
begin
VAR51 <= VAR10 ' (0);
VAR34 <= { (VAR13+1) {1'b0} };
end
else
begin
VAR51 <= VAR15;
VAR34 <= VAR53;
end
if (VAR17 == VAR16)
end
VAR11 <= 8'b10100101; else
VAR11 <= VAR3;
end
always @(VAR17)
begin
VAR38("## VAR19 %VAR46 VAR50 state %VAR35 with VAR40 %VAR14"
,VAR17.VAR37, VAR40);
end
begin
begin
begin
begin
begin | bsd-3-clause |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_int_mult64s.v | 5,288 | module MODULE1 (
enable,
VAR11,
VAR4,
VAR9,
VAR1);
parameter VAR2 = 64;
parameter VAR10 = 64;
localparam VAR6 = VAR2 < 64 ? VAR2 + 1 : VAR2;
localparam VAR12 = VAR10 < 64 ? VAR10 + 1 : VAR10;
input enable;
input VAR11;
input [VAR6 - 1 : 0] VAR4;
input [VAR12 - 1 : 0] VAR9;
output reg [63:0] VAR1;
reg [VAR6 - 1 : 0] VAR5;
reg [VAR12 - 1 : 0] VAR8;
reg [VAR6 - 1 : 0] VAR7;
reg [VAR12 - 1 : 0] VAR3;
always@(posedge VAR11)
begin
if (enable)
begin
VAR1 <= VAR7 * VAR3;
VAR5 <= VAR4;
VAR8 <= VAR9;
VAR7 <= VAR5;
VAR3 <= VAR8;
end
end
endmodule | mit |
MarcoVogt/basil | firmware/modules/fast_spi_rx/fast_spi_rx.v | 1,704 | module MODULE1
parameter VAR6 = 16'h0000,
parameter VAR12 = 16'h0000,
parameter VAR7 = 16,
parameter VAR14 = 4'b0001
)(
input wire VAR27,
input wire [VAR7-1:0] VAR20,
inout wire [7:0] VAR5,
input wire VAR25,
input wire VAR3,
input wire VAR21,
input wire VAR1,
input wire VAR19,
input wire VAR4,
input wire VAR13,
output wire VAR22,
output wire [31:0] VAR24
);
wire VAR11, VAR26;
wire [VAR7-1:0] VAR8;
wire [7:0] VAR9;
wire [7:0] VAR2;
VAR18 #( .VAR6(VAR6), .VAR12(VAR12), .VAR7(VAR7) ) VAR17
(
.VAR21(VAR21),
.VAR3(VAR3),
.VAR20(VAR20),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR26(VAR26),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2)
);
VAR23
.VAR7(VAR7),
.VAR14(VAR14)
) VAR16
(
.VAR27(VAR27),
.VAR25(VAR25),
.VAR20(VAR8),
.VAR10(VAR9),
.VAR21(VAR11),
.VAR3(VAR26),
.VAR15(VAR2),
.VAR1(VAR1),
.VAR19(VAR19),
.VAR4(VAR4),
.VAR13(VAR13),
.VAR22(VAR22),
.VAR24(VAR24)
);
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd/sky130_fd_sc_ms__tapvgnd.functional.v | 1,097 | module MODULE1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi.pp.blackbox.v | 1,405 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR2 ,
VAR5,
VAR9,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR5;
input VAR9;
input VAR8 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.v | 2,298 | module MODULE1 (
VAR5,
VAR7 ,
VAR3 ,
VAR2 ,
VAR8 ,
VAR9 ,
VAR6
);
input VAR5;
input VAR7 ;
input VAR3 ;
output VAR2 ;
output VAR8 ;
input VAR9 ;
input VAR6 ;
VAR4 VAR1 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR5,
VAR7 ,
VAR3 ,
VAR2 ,
VAR8
);
input VAR5;
input VAR7 ;
input VAR3 ;
output VAR2 ;
output VAR8 ;
supply1 VAR9;
supply0 VAR6;
VAR4 VAR1 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule | apache-2.0 |
azonenberg/antikernel-ipcores | graphics/display/SSD1306.v | 19,053 | module MODULE1 #(
parameter VAR14 = "VAR7" ) (
input wire clk, input wire[15:0] VAR2,
output reg VAR12 = 0, output reg VAR15 = 1, output reg VAR9 = 1,
output wire VAR8, output wire VAR4,
output reg VAR13 = 1,
output reg VAR11 = 0,
input wire VAR17, input wire VAR6, input wire VAR5,
output wire ready,
output reg VAR10 = 0, output reg[8:0] VAR1 = 0,
input wire[7:0] VAR3,
output reg VAR16 = 0 ); | bsd-3-clause |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/bd_0/ip/ip_4/synth/bd_c3fe_slot_0_b_0.v | 4,558 | module MODULE1 (
VAR68,
VAR57,
dout
);
input wire [0 : 0] VAR68;
input wire [0 : 0] VAR57;
output wire [1 : 0] dout;
VAR18 #(
.VAR54(1),
.VAR59(1),
.VAR36(1),
.VAR17(1),
.VAR10(1),
.VAR48(1),
.VAR39(1),
.VAR65(1),
.VAR41(1),
.VAR67(1),
.VAR31(1),
.VAR62(1),
.VAR23(1),
.VAR2(1),
.VAR14(1),
.VAR8(1),
.VAR33(1),
.VAR55(1),
.VAR50(1),
.VAR32(1),
.VAR64(1),
.VAR3(1),
.VAR1(1),
.VAR9(1),
.VAR7(1),
.VAR43(1),
.VAR6(1),
.VAR19(1),
.VAR61(1),
.VAR46(1),
.VAR27(1),
.VAR21(1),
.VAR47(2),
.VAR45(2)
) VAR29 (
.VAR68(VAR68),
.VAR57(VAR57),
.VAR25(1'VAR69),
.VAR22(1'VAR69),
.VAR44(1'VAR69),
.VAR40(1'VAR69),
.VAR56(1'VAR69),
.VAR51(1'VAR69),
.VAR28(1'VAR69),
.VAR42(1'VAR69),
.VAR58(1'VAR69),
.VAR53(1'VAR69),
.VAR30(1'VAR69),
.VAR49(1'VAR69),
.VAR26(1'VAR69),
.VAR15(1'VAR69),
.VAR13(1'VAR69),
.VAR60(1'VAR69),
.VAR16(1'VAR69),
.VAR37(1'VAR69),
.VAR24(1'VAR69),
.VAR34(1'VAR69),
.VAR5(1'VAR69),
.VAR4(1'VAR69),
.VAR35(1'VAR69),
.VAR66(1'VAR69),
.VAR38(1'VAR69),
.VAR63(1'VAR69),
.VAR20(1'VAR69),
.VAR12(1'VAR69),
.VAR11(1'VAR69),
.VAR52(1'VAR69),
.dout(dout)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi.behavioral.v | 1,572 | module MODULE1 (
VAR9 ,
VAR5,
VAR13,
VAR4,
VAR8,
VAR6
);
output VAR9 ;
input VAR5;
input VAR13;
input VAR4;
input VAR8;
input VAR6;
supply1 VAR11;
supply0 VAR15;
supply1 VAR14 ;
supply0 VAR7 ;
wire VAR2 ;
wire VAR12;
and VAR1 (VAR2 , VAR5, VAR13, VAR4, VAR8 );
nor VAR3 (VAR12, VAR6, VAR2 );
buf VAR10 (VAR9 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_1.v | 2,163 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3,
VAR7,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR2 ;
input VAR3;
input VAR7;
input VAR6 ;
input VAR8 ;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR3;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR8 ;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a_2.v | 2,348 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR6 ,
VAR4 ,
VAR10 ,
VAR7,
VAR1,
VAR9 ,
VAR11
);
output VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR4 ;
input VAR10 ;
input VAR7;
input VAR1;
input VAR9 ;
input VAR11 ;
VAR8 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11)
);
endmodule
module MODULE2 (
VAR3 ,
VAR5,
VAR6,
VAR4,
VAR10
);
output VAR3 ;
input VAR5;
input VAR6;
input VAR4;
input VAR10;
supply1 VAR7;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR11 ;
VAR8 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10)
);
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/usb_tx_data.v | 1,724 | module MODULE1
(input VAR5,
input [7:0] VAR25,
input VAR34,
output [7:0] VAR7,
output VAR8);
localparam VAR30 = 4'd0;
localparam VAR33 = 4'd1;
localparam VAR28 = 4'd2;
localparam VAR23 = 4'd3;
localparam VAR24 = 4'd4;
localparam VAR31 = 4'd5;
localparam VAR3=4, VAR27=5;
reg [VAR27+VAR3-1:0] VAR18;
wire [VAR3-1:0] state;
wire [VAR3-1:0] VAR2 = VAR18[VAR3+VAR27-1:VAR27];
VAR10 #(VAR3) VAR1
(.VAR5(VAR5), .rst(1'b0), .en(1'b1), .VAR25(VAR2), .VAR29(state));
wire [7:0] VAR12;
d1 #(8) VAR17(.VAR5(VAR5), .VAR25(VAR25), .VAR29(VAR12));
wire [15:0] VAR4;
wire VAR19;
VAR15 VAR16
(.VAR5(VAR5), .VAR25(VAR12), .VAR34(VAR19), .rst(state == VAR30), .VAR4(VAR4));
wire [1:0] VAR13;
wire [7:0] VAR32;
VAR6 #(.VAR14(8), .VAR9(2)) VAR20
(.VAR25({VAR4, VAR12, 8'b10000000}),
.sel(VAR13),
.VAR11(VAR32));
wire [7:0] VAR35 = VAR22 ? VAR32 : 8'h0;
always @* begin
case (state)
VAR30:
if (VAR34) VAR18 = { VAR33 , 5'b00001 };
end
else VAR18 = { VAR30 , 5'b00000 };
VAR33: VAR18 = { VAR28 , 5'b00011 };
VAR28:
if (~VAR34) VAR18 = { VAR24, 5'b01011 };
else VAR18 = { VAR28 , 5'b01011 };
VAR24: VAR18 = { VAR23, 5'b00101 };
VAR23: VAR18 = { VAR31 , 5'b00111 };
VAR31: VAR18 = { VAR30 , 5'b00110 };
default: VAR18 = { VAR30 , 5'b00000 };
endcase
end
wire VAR22 = VAR18[0];
assign VAR13 = VAR18[2:1];
assign VAR19 = VAR18[3];
d1 #(8) VAR26 (.VAR5(VAR5), .VAR25(VAR35 ), .VAR29(VAR7 ));
d1 VAR21(.VAR5(VAR5), .VAR25(VAR22), .VAR29(VAR8));
endmodule | apache-2.0 |
CospanDesign/vivado-ip-cores | ip/axi_on_screen_display/console_osd.v | 16,230 | (VAR56 <= 2) ? 1 : \
(VAR56 <= 4) ? 2 : \
(VAR56 <= 8) ? 3 : \
(VAR56 <= 16) ? 4 : \
(VAR56 <= 32) ? 5 : \
(VAR56 <= 64) ? 6 : \
(VAR56 <= 128) ? 7 : \
(VAR56 <= 256) ? 8 : \
(VAR56 <= 512) ? 9 : \
(VAR56 <= 1024) ? 10: \
(VAR56 <= 2048) ? 11 : \
(VAR56 <= 4096) ? 12 : \
-1
module MODULE1 #(
parameter VAR6 = 12,
parameter VAR111 = 480,
parameter VAR73 = 272,
parameter VAR47 = VAR111 * VAR73,
parameter VAR61 = (VAR31(VAR111) + 1),
parameter VAR122 = 24,
parameter VAR93 = 5,
parameter VAR1 = 7
)(
input clk,
input rst,
input VAR110,
input [VAR122 - 1: 0] VAR116,
input [VAR122 - 1: 0] VAR126,
input VAR83,
input [31:0] VAR84,
input VAR81,
input [7:0] VAR55,
output VAR4,
input VAR54,
input VAR121,
input [2:0] VAR106,
input VAR24,
input VAR11,
input VAR75,
input [31:0] VAR103,
input [31:0] VAR77,
input [31:0] VAR19,
input [31:0] VAR33,
input VAR80,
input VAR68,
output VAR57,
input VAR89,
output [23:0] VAR104,
output [VAR122: 0] VAR76, input VAR109,
output [3:0] VAR112,
output [15:0] VAR12
);
localparam VAR23 = 0;
localparam VAR7 = 1;
localparam VAR46 = 2;
localparam VAR21= 3;
localparam VAR82 = 4;
localparam VAR9 = 5;
localparam VAR51 = 6;
localparam VAR5 = 7;
localparam VAR66 = VAR93 + 1;
localparam VAR100 = VAR1 + 1;
localparam VAR15 = VAR93 * VAR100;
localparam VAR35 = VAR111 / VAR66;
localparam VAR63 = VAR73 / VAR100;
localparam VAR22 = VAR35 * VAR63;
reg [3:0] state;
wire [1:0] VAR65;
reg [1:0] VAR72;
wire [23:0] VAR28;
reg VAR10;
reg [7:0] VAR114;
reg VAR49;
wire [VAR122:0] VAR102;
reg VAR48;
wire VAR71;
reg [VAR122 - 1: 0] VAR124;
reg [31:0] VAR43;
reg [23:0] VAR101;
reg [23:0] VAR119;
wire VAR27;
wire VAR74;
wire [23:0] VAR13;
wire [(VAR66 - 1):0] VAR108[0: ((1 << VAR100) - 1)];
wire VAR98;
wire [7:0] VAR45;
wire [VAR15 - 1: 0] VAR117;
reg [VAR100 - 1:0] VAR32;
reg [VAR66 - 1:0] VAR88;
reg [23:0] VAR128;
reg VAR40;
wire VAR69;
wire VAR60;
wire [31: 0] VAR86 = VAR93;
wire [31: 0] VAR64 = VAR66;
wire [31: 0] VAR90 = VAR1;
wire [31: 0] VAR17 = VAR100;
wire [31: 0] VAR30 = VAR47;
wire [5:0] VAR2;
wire [5:0] VAR41;
wire [5:0] VAR58;
wire [5:0] VAR94;
wire [5:0] VAR91;
wire [5:0] VAR78;
wire [5:0] VAR85;
wire [5:0] VAR20;
assign VAR12 = VAR43[15:0];
assign VAR69 = (VAR101 >= VAR103) && (VAR101 <= VAR77) &&
(VAR119 >= VAR19) && (VAR119 <= VAR33);
assign VAR27 = (VAR119 < VAR19) || (VAR119 > VAR33);
assign VAR74= (VAR101 < VAR103) || (VAR101 > VAR77);
assign VAR112 = state;
VAR62 #(
.VAR92 (VAR122 + 1 ), .VAR3 (VAR61 )
)VAR50 (
.reset (rst || VAR68 ),
.VAR97 (clk ),
.VAR59 (VAR65 ),
.VAR42 (VAR72 ),
.VAR79 (VAR28 ),
.VAR53 (VAR10 ),
.VAR25 (VAR102 ),
.VAR96 (VAR60 ),
.VAR120 (VAR80 ),
.VAR44 (VAR109 ),
.VAR115 (VAR57 ),
.VAR105 (VAR89 ),
.VAR127 (VAR104 ),
.VAR107 (VAR76 )
);
VAR29#(
.VAR6 (VAR6 ),
.VAR93 (VAR66 ),
.VAR1 (VAR100 ),
.VAR35 (VAR35 ),
.VAR63 (VAR63 ),
.VAR22 (VAR35 * VAR63)
)VAR67 (
.clk (clk ),
.rst (rst ),
.VAR121 (VAR121 ),
.VAR54 (VAR54 ),
.VAR106 (VAR106 ),
.VAR81 (VAR81 ),
.VAR55 (VAR55 ),
.VAR4 (VAR4 ),
.VAR113 (VAR40 ),
.VAR95 (VAR49 ),
.VAR123 (VAR98 ),
.VAR125 (VAR45 ),
.VAR24 (VAR24 ),
.VAR11 (VAR11 ),
.VAR75 (VAR75 )
);
VAR38 #(
.VAR92 (40 ),
.VAR87 (8 ),
.VAR18 ("VAR16.VAR99" ),
.VAR37 (256 )
) VAR118 (
.clk (clk ),
.rst (rst ),
.en (1'b1 ),
.VAR39 (1'b0 ),
.VAR26 (8'h00 ),
.VAR8 (40'h0 ),
.VAR70 (VAR114 ), .VAR14 (VAR117 )
);
assign VAR102[23:0] = VAR13;
assign VAR102[24] = VAR48;
generate
genvar VAR52;
genvar VAR56;
for (VAR52 = 0; VAR52 < VAR100; VAR52 = VAR52 + 1) begin: VAR36
for (VAR56 = 0; VAR56 < VAR66; VAR56 = VAR56 + 1) begin: VAR34
if (VAR56 < VAR93) begin
assign VAR108[VAR52][VAR56] = VAR117[(((VAR93 - 1) - VAR56) * 8) + VAR52];
end
else begin
assign VAR108[VAR52][VAR56] = 0;
end
end
end
endgenerate
assign VAR13 = (!VAR69) ? VAR126:
(VAR108[VAR32][VAR88]) ?
VAR116 :
VAR126;
assign VAR2 = VAR108[0];
assign VAR41 = VAR108[1];
assign VAR58 = VAR108[2];
assign VAR94 = VAR108[3];
assign VAR91 = VAR108[4];
assign VAR78 = VAR108[5];
assign VAR85 = VAR108[6];
assign VAR20 = VAR108[7];
always @ (posedge clk) begin
VAR10 <= 0;
VAR40 <= 0;
if (rst) begin
state <= VAR23;
VAR72 <= 2'b00;
VAR48 <= 0;
VAR124 <= 0;
VAR43 <= 0;
VAR88 <= 0;
VAR32 <= 0;
VAR128 <= 0;
VAR114 <= 0;
VAR49 <= 0;
VAR101 <= 0;
VAR119<= 0;
end
else begin
if ((VAR65 > 0) && (VAR72 == 0)) begin
if (VAR65[0]) begin
VAR72[0] <= 1;
end
else begin
VAR72[1] <= 1;
end
end
case (state)
VAR23: begin
VAR43 <= 0;
VAR88 <= 0;
VAR32 <= 0;
VAR48 <= 0;
if (VAR110 && VAR72 && VAR60) begin
VAR40 <= 1;
VAR119<= 0;
VAR128 <= 0;
VAR48 <= 1;
state <= VAR7;
end
end
VAR7: begin
VAR128 <= 0;
VAR101 <= 0;
if (VAR72) begin
if (VAR27 || (VAR43 >= VAR47)) begin
state <= VAR46;
end
else begin
state <= VAR21;
end
end
end
VAR46: begin
if (VAR43 >= VAR47) begin
if (VAR101 > 0) begin
VAR72 <= 0;
end
VAR43 <= 0;
state <= VAR23;
end
else if (VAR101 >= VAR111) begin
VAR119<= VAR119 + 1;
VAR72 <= 0;
state <= VAR7;
end
else begin
VAR43 <= VAR43 + 1;
VAR101 <= VAR101 + 1;
VAR124 <= VAR13;
VAR10 <= 1;
end
end
VAR21: begin
if ((VAR101 < VAR111) && !VAR69 && VAR74)begin
VAR43 <= VAR43 + 1;
VAR101 <= VAR101 + 1;
VAR124 <= VAR13;
VAR10 <= 1;
end
else if (VAR101 >= (VAR111 - 1)) begin
if (VAR32 < (VAR100 - 1)) begin
VAR32 <= VAR32 + 1;
end
else begin
VAR32 <= 0;
end
state <= VAR7;
VAR72 <= 0;
VAR119<= VAR119 + 1;
end
else begin
state <= VAR82;
end
end
VAR82: begin
VAR49 <= 1;
VAR88 <= 0;
if (VAR98) begin
VAR49 <= 0;
VAR114 <= VAR45; state <= VAR9;
end
end
VAR9: begin
state <= VAR51;
end
VAR51: begin
VAR43 <= VAR43 + 1;
VAR101 <= VAR101 + 1;
VAR124 <= VAR13;
VAR10 <= 1;
state <= VAR5;
end
VAR5: begin
if (VAR88 < (VAR66 - 1)) begin
VAR10 <= 1;
VAR124 <= VAR13;
VAR43 <= VAR43 + 1;
VAR88 <= VAR88 + 1;
VAR101 <= VAR101 + 1;
end
else begin
if (VAR128 >= (VAR35 - 1)) begin
state <= VAR21;
end
else begin
VAR128 <= VAR128 + 1;
state <= VAR82;
end
end
end
endcase
if ((VAR10 == 1) && VAR48) begin
VAR48 <= 0;
end
end
end
endmodule | mit |
peteasa/oh | src/elink/hdl/etx_clocks.v | 8,409 | module MODULE1 (
VAR100, VAR50, VAR28, VAR18, VAR111, VAR87,
VAR51, VAR112, VAR35,
VAR126, VAR124, VAR120
);
parameter VAR73 = 100;
parameter VAR26 = 300;
parameter VAR8 = 600;
parameter VAR98 = 90; parameter VAR132 = VAR143;
parameter VAR86 = 4; else
parameter VAR86 = 8; VAR39
parameter VAR19 = 12; localparam real VAR25 = 1000.000000 / VAR73;
localparam integer VAR68 = VAR19 * VAR73 / VAR26;
localparam integer VAR142 = VAR19 * VAR73 / VAR8;
input VAR126; input VAR124;
input VAR120;
output VAR100; output VAR50; output VAR28;
output VAR18, VAR111;
output VAR87; output VAR51; output VAR112; output VAR35;
wire VAR62;
wire VAR83;
wire VAR101;
wire VAR4;
wire VAR42;
wire VAR52;
wire VAR12;
wire VAR94;
wire VAR95;
wire VAR97;
wire VAR36;
reg VAR88;
reg VAR38;
wire VAR55;
wire VAR58;
wire VAR99;
wire VAR60;
reg [VAR86:0] VAR107 = 'b0; reg VAR71;
reg [2:0] VAR144;
reg [1:0] VAR48;
reg [1:0] VAR130;
always @ (posedge VAR120)
begin
VAR107[VAR86-1:0] <= VAR107[VAR86-1:0]+1'b1;
VAR71 <= ~(|VAR107[VAR86-1:0]);
end
always @ (posedge VAR120)
begin
VAR88 <= VAR36;
VAR38 <= VAR88;
end
always @ (posedge VAR120 or negedge VAR126)
if(!VAR126)
VAR144[2:0] <= VAR106;
else if(VAR71)
case(VAR144[2:0])
if(~VAR124)
VAR144[2:0] <= VAR41;
if(VAR38)
VAR144[2:0] <= VAR30;
VAR144[2:0] <= VAR79;
VAR144[2:0] <= VAR15;
if(VAR38)
VAR144[2:0] <= VAR69;
if(VAR124)
VAR144[2:0] <= VAR106;
endcase
assign VAR99 = (VAR144[2:0]==VAR106) |
(VAR144[2:0]==VAR30) |
(VAR144[2:0]==VAR79)
;
assign VAR112 = (VAR144[2:0]==VAR79) |
(VAR144[2:0]==VAR15) |
(VAR144[2:0]==VAR69);
assign VAR58 = ~(VAR144[2:0] != VAR69);
assign VAR35 = (VAR144[2:0] == VAR69);
VAR92 VAR49 ( .VAR131 (VAR51),
.clk (VAR100),
.VAR54 (VAR58));
VAR92 VAR29 ( .VAR131 (VAR87),
.clk (VAR28),
.VAR54 (VAR58));
generate
if(VAR132=="VAR84")
begin
VAR72
.VAR74("VAR37"),
.VAR136(VAR19),
.VAR7(0.0),
.VAR128(VAR25),
.VAR117(VAR142), .VAR2(VAR68), .VAR85(VAR68), .VAR113(VAR68*4), .VAR103(128), .VAR77(128), .VAR133(128), .VAR34(0.5),
.VAR56(0.5),
.VAR90(0.5),
.VAR57(0.5),
.VAR16(0.5),
.VAR23(0.5),
.VAR141(0.5),
.VAR114(0.0),
.VAR119(0.0),
.VAR13(VAR98),
.VAR123(0.0),
.VAR129(0.0),
.VAR5(0.0),
.VAR80(0.0),
.VAR1(1.0),
.VAR91(0.01),
.VAR59("VAR63")
) VAR9
(
.VAR75(VAR83),
.VAR110(),
.VAR118(VAR42),
.VAR82(),
.VAR21(VAR52), .VAR67(),
.VAR66(VAR60),
.VAR20(),
.VAR70(),
.VAR64(),
.VAR93(),
.VAR24(1'b0),
.VAR61(VAR99), .VAR32(VAR94),
.VAR44(VAR94), .VAR76(), .VAR43(VAR120), .VAR3(1'b0),
.VAR138(1'b1),
.VAR14(7'b0),
.VAR45(1'b0),
.VAR102(1'b0),
.VAR134(16'b0),
.VAR121(1'b0),
.VAR81(),
.VAR104(),
.VAR122(VAR36), .VAR137(1'b0),
.VAR135(1'b0),
.VAR65(),
.VAR139(1'b0),
.VAR146(),
.VAR10()
);
VAR127 VAR140 (.VAR11(VAR42), .VAR6(VAR100)); VAR127 VAR96 (.VAR11(VAR60),.VAR6(VAR28)); VAR127 VAR47 (.VAR11(VAR52), .VAR6(VAR50));
VAR89 VAR115(.VAR6(VAR101), .VAR11(VAR83));
VAR145 #(.VAR40 ("VAR33"), .VAR31("VAR147"))
VAR108 (
.VAR125 (VAR4),
.VAR78 (VAR101),
.VAR105 (1'b1),
.VAR109 (1'b1),
.VAR17 (1'b0),
.VAR27 (1'b0),
.VAR22 (1'b0));
VAR116 VAR53 (.VAR6 (VAR18),
.VAR46 (VAR111),
.VAR11 (VAR4)
);
end else
begin
assign VAR18 = VAR120;
assign VAR111 = VAR120;
assign VAR100 = VAR120;
assign VAR28 = VAR120;
assign VAR50 = VAR120;
end
endgenerate
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b.behavioral.pp.v | 2,015 | module MODULE1 (
VAR12 ,
VAR9 ,
VAR14 ,
VAR6 ,
VAR15,
VAR8,
VAR11 ,
VAR5
);
output VAR12 ;
input VAR9 ;
input VAR14 ;
input VAR6 ;
input VAR15;
input VAR8;
input VAR11 ;
input VAR5 ;
wire VAR7 ;
wire VAR13 ;
wire VAR10;
nor VAR2 (VAR7 , VAR9, VAR14 );
and VAR3 (VAR13 , VAR6, VAR7 );
VAR4 VAR1 (VAR10, VAR13, VAR15, VAR8);
buf VAR16 (VAR12 , VAR10 );
endmodule | apache-2.0 |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v | 1,158 | module MODULE1
VAR10 = 32,
VAR1 = 32,
VAR6 = 32,
VAR8 = 16, VAR9 = 32,
VAR2 = 8,
VAR7 = 1,
VAR3 = 8,
VAR5 = 1,
VAR4 = 1
) (
);
endmodule | mit |
Pylonight/MIPS-CPU | cpu/Control_Unit.v | 11,144 | module MODULE1(
output reg VAR5,
output reg VAR59,
output reg VAR57,
output reg VAR56,
output reg VAR31,
output reg VAR69,
output reg VAR6,
output reg [3 : 0] VAR13,
output reg [2 : 0] VAR21,
output reg [7 : 0] VAR10,
output reg VAR73,
output reg VAR70,
output reg [1 : 0] VAR17,
output reg VAR7,
output reg VAR66,
output reg [1 : 0] VAR18,
output reg [4 : 0] VAR15,
output reg VAR49,
output reg VAR33,
input clk,
input [15 : 0] VAR47,
input rst,
output reg [2 : 0] state,
output reg [5 : 0] VAR41
);
reg [2 : 0] VAR12;
parameter
VAR52 = 1,
VAR34 = 2,
VAR28 = 3,
VAR39 = 4,
VAR43 = 5,
VAR45 = 6,
VAR4 = 7,
VAR42 = 8,
VAR64 = 9,
VAR27 = 10,
VAR8 = 11,
VAR46 = 12,
VAR9 = 13,
VAR63 = 14,
VAR67 = 15,
VAR25 = 16,
VAR16 = 17,
VAR62 = 18,
VAR48 = 19,
VAR2 = 20,
VAR71 = 21,
VAR38 = 22,
VAR35 = 23,
VAR50 = 24,
VAR37 = 25,
VAR23 = 26,
VAR24 = 27,
VAR60 = 28,
VAR58 = 29,
VAR54 = 30,
VAR51 = 31,
VAR65 = 32,
VAR19 = 33,
VAR68 = 34,
VAR11 = 35,
VAR20 = 36,
VAR14 = 37,
VAR30 = 38,
VAR72 = 39,
VAR29 = 40,
VAR74 = 41,
VAR40 = 42,
VAR61 = 43,
VAR26 = 44,
VAR44 = 45;
parameter
VAR1 = 0,
VAR32 = 1,
VAR3 = 2,
VAR36 = 3,
VAR22 = 4,
VAR55 = 5,
VAR53 = 6;
always @(VAR47 or rst) begin
if (rst == 0)
begin
VAR41 = 0;
end
else
begin
case (VAR47[15 : 11])
5'b01001: VAR41 = VAR52;
5'b01000: VAR41 = VAR34;
5'b00000: VAR41 = VAR28;
5'b00010: VAR41 = VAR4;
5'b00100: VAR41 = VAR42;
5'b00101: VAR41 = VAR64;
5'b01110: VAR41 = VAR9;
5'b11111: VAR41 = VAR63;
5'b01101: VAR41 = VAR62;
5'b10011: VAR41 = VAR48;
5'b10010: VAR41 = VAR2;
5'b01111: VAR41 = VAR35;
5'b00001: VAR41 = VAR60;
5'b01010: VAR41 = VAR19;
5'b01011: VAR41 = VAR11;
5'b11011: VAR41 = VAR74;
5'b11010: VAR41 = VAR61;
5'b10000: VAR41 = VAR44;
5'b00110: case (VAR47[1 : 0])
2'b00: VAR41 = VAR54;
2'b11: VAR41 = VAR20;
2'b10: VAR41 = VAR30;
endcase
5'b01100: case (VAR47[10 : 8])
3'b011: VAR41 = VAR39;
3'b000: VAR41 = VAR27;
3'b001: VAR41 = VAR8;
3'b100: VAR41 = VAR37;
3'b010: VAR41 = VAR40;
endcase
5'b11100: case (VAR47[1 : 0])
2'b01: VAR41 = VAR43;
2'b11: VAR41 = VAR29;
endcase
5'b11101: case (VAR47[4 : 0])
5'b01100: VAR41 = VAR45;
5'b01010: VAR41 = VAR46;
5'b01011: VAR41 = VAR23;
5'b01111: VAR41 = VAR24;
5'b01101: VAR41 = VAR58;
5'b00100: VAR41 = VAR51;
5'b00010: VAR41 = VAR65;
5'b00011: VAR41 = VAR68;
5'b00111: VAR41 = VAR14;
5'b00110: VAR41 = VAR72;
5'b01110: VAR41 = VAR26;
5'b00000: case (VAR47[7 : 5])
3'b110: VAR41 = VAR67;
3'b000: VAR41 = VAR25;
3'b001: VAR41 = VAR16;
3'b010: VAR41 = VAR38;
endcase
endcase
5'b11110: case (VAR47[7 : 0])
8'b00000000: VAR41 = VAR71;
8'b00000001: VAR41 = VAR50;
endcase
endcase
end
end
always @(posedge clk or negedge rst)
begin
if (rst == 0)
begin
state <= VAR1;
end
else
begin
state <= VAR12;
end
end
always @(state)
begin
case (state)
VAR1:
begin
VAR5 = 0;
VAR59 = 0;
VAR57 = 0;
VAR56 = 0;
VAR31 = 0;
VAR69 = 0;
VAR6 = 0;
VAR13 = 4'b0;
VAR21 = 3'b0;
VAR10 = 8'b0;
VAR73 = 0;
VAR70 = 0;
VAR17 = 2'b0;
VAR7 = 0;
VAR66 = 0;
VAR18 = 2'b0;
VAR15 = 5'b0;
VAR49 = 0;
VAR33 = 0;
VAR12 = VAR32;
end
VAR32:
begin
VAR49 = 0;
VAR73 = 0;
VAR6 = 0;
VAR59 = 0;
VAR12 = VAR3;
VAR57 = 1;
VAR5 = 1;
end
VAR3:
begin
VAR57 = 0;
VAR5 = 0;
if (VAR41 == VAR44)
begin
VAR12 = VAR53;
end
else
begin
VAR12 = VAR36;
end
case (VAR41)
VAR52,
VAR34,
VAR42,
VAR64,
VAR9,
VAR67,
VAR25,
VAR48,
VAR50,
VAR19,
VAR11: VAR10 = {1'b0, VAR47[10 : 8], 4'b0};
VAR35,
VAR37,
VAR24,
VAR54,
VAR20,
VAR30: VAR10 = {1'b0, VAR47[7 : 5], 4'b0};
VAR28,
VAR39,
VAR2: VAR10 = 8'b11110000;
VAR43,
VAR45,
VAR46,
VAR58,
VAR51,
VAR65,
VAR68,
VAR14,
VAR72,
VAR29,
VAR74,
VAR26: VAR10 = {1'b0, VAR47[10 : 8], 1'b0, VAR47[7 : 5]};
VAR4,
VAR63,
VAR62,
VAR38,
VAR60: VAR10 = 8'b00000000;
VAR16: VAR10 = 8'b00100000;
VAR71: VAR10 = 8'b11010000;
VAR23: VAR10 = {4'b0000, 1'b0, VAR47[7 : 5]};
VAR40: VAR10 = 8'b11110010;
VAR61: VAR10 = {4'b1111, 1'b0, VAR47[7 : 5]};
VAR27,
VAR8: VAR10 = 8'b11100000;
endcase
case (VAR41)
VAR52,
VAR28,
VAR39,
VAR42,
VAR64,
VAR27,
VAR8,
VAR9,
VAR2,
VAR19,
VAR11,
VAR40,
VAR61: VAR21 = 0;
VAR34: VAR21 = 1;
VAR4: VAR21 = 2;
VAR63: VAR21 = 3;
VAR62: VAR21 = 4;
VAR48,
VAR74: VAR21 = 5;
VAR54,
VAR20,
VAR30: VAR21 = 6;
endcase
case (VAR41)
VAR52,
VAR34,
VAR28,
VAR39,
VAR43,
VAR45,
VAR46,
VAR9,
VAR67,
VAR25,
VAR16,
VAR48,
VAR2,
VAR71,
VAR35,
VAR50,
VAR37,
VAR23,
VAR24,
VAR58,
VAR54,
VAR51,
VAR65,
VAR19,
VAR68,
VAR11,
VAR20,
VAR14,
VAR30,
VAR72,
VAR29,
VAR74,
VAR40,
VAR61,
VAR26: VAR7 = 0;
VAR4,
VAR42,
VAR64,
VAR27,
VAR8,
VAR38: VAR7 = 1;
endcase
case (VAR41)
VAR43,
VAR45,
VAR46,
VAR23,
VAR58,
VAR51,
VAR65,
VAR68,
VAR14,
VAR72,
VAR29,
VAR26: VAR66 = 0;
VAR52,
VAR34,
VAR28,
VAR39,
VAR4,
VAR42,
VAR64,
VAR27,
VAR8,
VAR9,
VAR63,
VAR62,
VAR48,
VAR2,
VAR54,
VAR19,
VAR11,
VAR20,
VAR30,
VAR74,
VAR40,
VAR61: VAR66 = 1;
endcase
case (VAR41)
VAR67,
VAR25,
VAR16,
VAR71,
VAR38,
VAR35,
VAR50,
VAR37: VAR15 = 0;
VAR63,
VAR62: VAR15 = 1;
VAR52,
VAR34,
VAR28,
VAR39,
VAR43,
VAR4,
VAR42,
VAR64,
VAR27,
VAR8,
VAR48,
VAR2,
VAR74,
VAR40,
VAR61: VAR15 = 2;
VAR23,
VAR29: VAR15 = 3;
VAR45: VAR15 = 4;
VAR58: VAR15 = 5;
VAR24: VAR15 = 6;
VAR26: VAR15 = 7;
VAR46,
VAR9: VAR15 = 8;
VAR51: VAR15 = 9;
VAR72: VAR15 = 10;
VAR54: VAR15 = 11;
VAR68,
VAR11: VAR15 = 12;
VAR14: VAR15 = 13;
VAR30: VAR15 = 14;
VAR20: VAR15 = 15;
VAR65,
VAR19: VAR15 = 16;
endcase
case (VAR41)
VAR42,
VAR27: VAR70 = 0;
VAR64,
VAR8: VAR70 = 1;
endcase
case (VAR41)
VAR42,
VAR64,
VAR27,
VAR8: VAR17 = 2'b10;
VAR4,
VAR63,
VAR67,
VAR25,
VAR16: VAR17 = 2'b11;
default: VAR17 = 2'b00;
endcase
VAR56 = 1;
VAR31 = 1;
VAR69 = 1;
end
VAR36:
begin
VAR56 = 0;
VAR31 = 0;
VAR69 = 0;
VAR12 = VAR22;
VAR33 = 1;
end
VAR22:
begin
VAR33 = 0;
case (VAR41)
VAR4,
VAR42,
VAR64,
VAR27,
VAR8,
VAR74,
VAR40,
VAR61,
VAR25,
VAR16: VAR12 = VAR32;
default: VAR12 = VAR55;
endcase
case (VAR41)
VAR74,
VAR40,
VAR61: VAR49 = 1;
endcase
case (VAR41)
VAR48,
VAR2: VAR73 = 1;
endcase
VAR59 = 1;
case (VAR41)
VAR48,
VAR2: VAR18 = 1;
VAR63,
VAR67: VAR18 = 2;
default: VAR18 = 0;
endcase
case (VAR41)
VAR52,
VAR28,
VAR45,
VAR62,
VAR2,
VAR71,
VAR38,
VAR35,
VAR23,
VAR24,
VAR58,
VAR54,
VAR20,
VAR30,
VAR26: VAR13 = {1'b0, VAR47[10 : 8]};
VAR34,
VAR48,
VAR51,
VAR14,
VAR72: VAR13 = {1'b0, VAR47[7 : 5]};
VAR39,
VAR37: VAR13 = 4'b1111;
VAR43,
VAR29: VAR13 = {1'b0, VAR47[4 : 2]};
VAR46,
VAR9,
VAR65,
VAR19,
VAR68,
VAR11: VAR13 = 4'b1110;
VAR63,
VAR67: VAR13 = 4'b0010;
VAR50: VAR13 = 4'b1101;
endcase
end
VAR55: begin
VAR49 = 0;
VAR73 = 0;
VAR59 = 0;
VAR12 = VAR32;
case (VAR41)
VAR52,
VAR28,
VAR45,
VAR62,
VAR2,
VAR71,
VAR38,
VAR35,
VAR23,
VAR24,
VAR58,
VAR54,
VAR20,
VAR30,
VAR26,
VAR34,
VAR48,
VAR51,
VAR14,
VAR72,
VAR39,
VAR37,
VAR43,
VAR29,
VAR46,
VAR9,
VAR65,
VAR19,
VAR68,
VAR11,
VAR63,
VAR67,
VAR50: VAR6 = 1;
endcase
end
VAR53:
begin
VAR12 = VAR53;
end
endcase
end
endmodule | gpl-2.0 |
kristianpaul/milkyminer | cores/fpgaminer/rtl/serial.v | 3,044 | module MODULE1(clk, VAR13, VAR1, VAR8);
input clk;
input VAR13;
wire VAR7;
wire [7:0] VAR11;
VAR15 VAR2(.clk(clk), .VAR13(VAR13), .VAR7(VAR7), .VAR11(VAR11));
output [255:0] VAR1;
output [255:0] VAR8;
reg [511:0] VAR19;
reg [511:0] VAR9;
reg [6:0] VAR17 = 7'b0000000;
assign VAR1 = VAR9[511:256];
assign VAR8 = VAR9[255:0];
always @(posedge clk)
case (VAR17)
7'b1000000:
begin
VAR9 <= VAR19;
VAR17 <= 0;
end
default:
if(VAR7)
begin
VAR19 <= VAR19 << 8;
VAR19[7:0] <= VAR11;
VAR17 <= VAR17 + 1;
end
endcase
endmodule
module MODULE2 (clk, VAR18, VAR6, VAR16, word);
wire VAR20;
wire VAR4;
reg [7:0] VAR14;
reg VAR5;
reg [3:0] VAR3 = 4'b0000;
assign VAR20 = VAR5;
input clk;
output VAR18;
input [31:0] word;
input VAR16;
output VAR6;
reg [31:0] VAR12;
assign VAR6 = (|VAR3);
always @(posedge clk)
begin
if (!VAR6 && VAR16)
begin
VAR3 <= 4'b1000;
VAR12 <= word;
end
else if (VAR3[3] && ~VAR3[0] && !VAR4)
begin
VAR5 <= 1;
VAR3 <= VAR3 + 1;
VAR14 <= VAR12[31:24];
VAR12 <= (VAR12 << 8);
end
else if (VAR3[3] && VAR3[0])
begin
VAR5 <= 0;
if (!VAR4) VAR3 <= VAR3 + 1;
end
end
VAR21 VAR22(.clk(clk), .VAR18(VAR18), .VAR20(VAR20), .VAR10(VAR14), .VAR4(VAR4));
endmodule | lgpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_lut_tc.v | 2,005 | module MODULE1( VAR1,VAR4,VAR2 );
input [5:0] VAR1 ;
input VAR4 ;
output [4:0] VAR2 ;
reg [4:0] VAR2 ;
wire [5:0] VAR3 = VAR1 + {VAR4,1'b0};
always @(VAR3) begin
case(VAR3)
'd18: VAR2 = 5'd1 ;
'd19: VAR2 = 5'd1 ;
'd20: VAR2 = 5'd1;
'd21: VAR2 = 5'd1;
'd22: VAR2 = 5'd1;
'd23: VAR2 = 5'd1;
'd24: VAR2 = 5'd1;
'd25: VAR2 = 5'd1;
'd26: VAR2 = 5'd1;
'd27: VAR2 = 5'd2;
'd28: VAR2 = 5'd2;
'd29: VAR2 = 5'd2;
'd30: VAR2 = 5'd2;
'd31: VAR2 = 5'd3;
'd32: VAR2 = 5'd3;
'd33: VAR2 = 5'd3;
'd34: VAR2 = 5'd3;
'd35: VAR2 = 5'd4;
'd36: VAR2 = 5'd4;
'd37: VAR2 = 5'd4;
'd38: VAR2 = 5'd5;
'd39: VAR2 = 5'd5;
'd40: VAR2 = 5'd6;
'd41: VAR2 = 5'd6;
'd42: VAR2 = 5'd7;
'd43: VAR2 = 5'd8;
'd44: VAR2 = 5'd9;
'd45: VAR2 = 5'd10;
'd46: VAR2 = 5'd11;
'd47: VAR2 = 5'd13;
'd48: VAR2 = 5'd14;
'd49: VAR2 = 5'd16;
'd50: VAR2 = 5'd18;
'd51: VAR2 = 5'd20;
'd52: VAR2 = 5'd22;
'd53: VAR2 = 5'd24;
default: VAR2 = 5'd0 ;
endcase
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtn/sky130_fd_sc_ls__dfrtn.behavioral.pp.v | 2,391 | module MODULE1 (
VAR17 ,
VAR15 ,
VAR1 ,
VAR2,
VAR11 ,
VAR20 ,
VAR9 ,
VAR12
);
output VAR17 ;
input VAR15 ;
input VAR1 ;
input VAR2;
input VAR11 ;
input VAR20 ;
input VAR9 ;
input VAR12 ;
wire VAR23 ;
wire VAR10 ;
wire VAR6 ;
reg VAR13 ;
wire VAR4 ;
wire VAR16;
wire VAR21 ;
wire VAR5 ;
wire VAR3 ;
wire VAR7 ;
not VAR14 (VAR10 , VAR16 );
not VAR18 (VAR6, VAR21 );
VAR22 VAR8 (VAR23 , VAR4, VAR6, VAR10, VAR13, VAR11, VAR20);
assign VAR5 = ( VAR11 === 1'b1 );
assign VAR3 = ( VAR5 && ( VAR16 === 1'b1 ) );
assign VAR7 = ( VAR5 && ( VAR2 === 1'b1 ) );
buf VAR19 (VAR17 , VAR23 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v | 1,206 | module MODULE1 #(parameter VAR20(VAR8)
,parameter VAR20(VAR14)
,parameter VAR4=0
,parameter VAR6=VAR15(VAR14)
,parameter VAR5=0)
(
input VAR7
,input VAR9
,input VAR10
,input [VAR6-1:0] VAR1
,input [VAR17(VAR8, 1):0] VAR16
,input VAR11
,input [VAR6-1:0] VAR18
,output logic [VAR17(VAR8, 1):0] VAR22
);
wire VAR12 = VAR9;
wire VAR2 = VAR11;
if (VAR8 == 0)
begin: VAR13
wire VAR19 = &{VAR7, VAR1, VAR16, VAR18};
assign VAR22 = '0;
end
else
begin: VAR23
logic [VAR8-1:0] VAR21 [VAR14-1:0];
assign VAR22 = VAR21[VAR18];
VAR3 @(posedge VAR7) begin
if (VAR10) begin
VAR21[VAR1] <= VAR16;
end
end
end
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a.blackbox.v | 1,339 | module MODULE1 (
VAR7 ,
VAR3,
VAR8,
VAR1,
VAR2
);
output VAR7 ;
input VAR3;
input VAR8;
input VAR1;
input VAR2;
supply1 VAR6;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha_1.v | 2,184 | module MODULE1 (
VAR4,
VAR1 ,
VAR7 ,
VAR5 ,
VAR2,
VAR9,
VAR6 ,
VAR8
);
output VAR4;
output VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR2;
input VAR9;
input VAR6 ;
input VAR8 ;
VAR3 VAR10 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4,
VAR1 ,
VAR7 ,
VAR5
);
output VAR4;
output VAR1 ;
input VAR7 ;
input VAR5 ;
supply1 VAR2;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR8 ;
VAR3 VAR10 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
hightoon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/tx_trn_sm.v | 35,135 | module MODULE1(
input clk,
input VAR42,
input VAR87,
output VAR91,
input [63:0] VAR77,
output VAR51,
input VAR83,
input [63:0] VAR94,
output VAR29,
input VAR5,
input [63:0] VAR80,
input VAR18,
output VAR15,
output reg VAR19,
input [63:0] VAR35,
input VAR62,
output reg[11:0] VAR82, input [31:0] VAR7,
output reg [63:0] VAR49,
output reg [7:0] VAR90,
output reg VAR1,
output reg VAR43,
output VAR64,
output VAR20,
input VAR104, input VAR27, output VAR50,
input [2:0] VAR25,
input VAR67, input [12:3] VAR66
);
localparam VAR45 = 21'b000000000000000000000;
localparam VAR47 = 21'b000000000000000000001;
localparam VAR98 = 21'b000000000000000000010;
localparam VAR36 = 21'b000000000000000000100;
localparam VAR72 = 21'b000000000000000001000;
localparam VAR84 = 21'b000000000000000010000;
localparam VAR9 = 21'b000000000000000100000;
localparam VAR31 = 21'b000000000000001000000;
localparam VAR54 = 21'b000000000000010000000;
localparam VAR40 = 21'b000000000000100000000;
localparam VAR85 = 21'b000000000001000000000;
localparam VAR58 = 21'b000000000010000000000;
localparam VAR89 = 21'b000000000100000000000;
localparam VAR57 = 21'b000000001000000000000;
localparam VAR12 = 21'b000000010000000000000;
localparam VAR53 = 21'b000000100000000000000;
localparam VAR63 = 21'b000001000000000000000;
localparam VAR10 = 21'b000010000000000000000;
localparam VAR32 = 21'b000100000000000000000;
localparam VAR3 = 21'b001000000000000000000;
localparam VAR21 = 21'b010000000000000000000;
localparam VAR61 = 21'b100000000000000000000;
localparam VAR26 = 2'b00;
localparam VAR70 = 2'b01;
localparam VAR52 = 2'b10;
reg [1:0] VAR39;
reg VAR56, VAR55,
VAR37;
reg VAR14, VAR24,
VAR81;
reg VAR41, VAR11,
VAR95;
wire VAR103, VAR96;
reg [63:0] VAR33, VAR4; reg [63:0] VAR28, VAR71; reg [63:0] VAR68, VAR16; reg [31:0] VAR97;
reg [9:0] VAR79;
wire [63:0] VAR2;
wire [31:0] VAR106;
wire [1:0] VAR75;
wire [2:0] VAR60;
wire [9:0] VAR93;
wire [1:0] VAR92;
wire [2:0] VAR8;
wire [9:0] VAR105;
reg [20:0] state;
reg [1:0] VAR22;
reg VAR13;
reg [3:0] VAR99 = 4'b1111;
wire VAR38;
reg VAR101;
reg [63:0] VAR17;
reg VAR74;
reg VAR44;
reg VAR6 = 0;
reg VAR30 = 0;
reg VAR76;
reg VAR65;
reg [9:0] VAR73;
reg [9:0] VAR23;
reg [9:0] VAR102;
reg VAR69;
reg VAR88;
wire VAR59;
reg VAR86;
VAR48 VAR46(
.clk(clk),
.rst(VAR44),
.in(VAR86),
.VAR78(VAR59)
);
always@(posedge clk)
VAR86 <= VAR67;
always@(posedge clk) VAR44 <= VAR42;
always@(posedge clk) VAR44 <= ( VAR42 | ((state == VAR45) & VAR87) );
assign VAR91 = VAR44;
assign VAR20 = 1'b1; assign VAR50 = 1'b1;
assign VAR64 = VAR13;
assign VAR2[63:0] = {VAR35[7:0],VAR35[15:8],
VAR35[23:16],VAR35[31:24],
VAR35[39:32],VAR35[47:40],
VAR35[55:48],VAR35[63:56]};
assign VAR106[31:0] = {VAR7[7:0],VAR7[15:8],
VAR7[23:16],VAR7[31:24]};
always@(posedge clk)begin
if(VAR44)begin
VAR55 <= 1'b0;
VAR37 <= 1'b0;
end else begin
VAR55 <= VAR56;
VAR37 <= VAR55;
end
end
assign VAR51 = (VAR55
| VAR56);
always@(posedge clk)begin
if(VAR44)begin
VAR33[63:0] <= 64'h0000000000000000;
end else begin
if(VAR55)begin
VAR33 <= VAR77;
end else begin
VAR33 <= VAR33;
end
end
end
always@(posedge clk)begin
if(VAR44)begin
VAR4[63:0] <= 64'h0000000000000000;
end else begin
if(VAR37)begin
VAR4 <= VAR77;
end else begin
VAR4 <= VAR4;
end
end
end
assign VAR75[1:0] = VAR33[62:61]; assign VAR60[2:0] = VAR33[54:52]; assign VAR93[9:0] = VAR33[41:32];
assign VAR103 = VAR25[1];
always@(posedge clk)begin
if(VAR44)begin
VAR24 <= 1'b0;
VAR81 <= 1'b0;
end else begin
VAR24 <= VAR14;
VAR81 <= VAR24;
end
end
assign VAR29 = (VAR24
| VAR14);
always@(posedge clk)begin
if(VAR44)begin
VAR28[63:0] <= 64'h0000000000000000;
end else begin
if(VAR24)begin
VAR28 <= VAR94;
end else begin
VAR28 <= VAR28;
end
end
end
always@(posedge clk)begin
if(VAR44)begin
VAR71[63:0] <= 64'h0000000000000000;
end else begin
if(VAR81)begin
VAR71 <= VAR94;
end else begin
VAR71 <= VAR71;
end
end
end
assign VAR92[1:0] = VAR28[62:61]; assign VAR8[2:0] = VAR28[54:52]; assign VAR105[9:0] = VAR28[41:32];
assign VAR96 = VAR25[0];
always@(posedge clk)begin
if(VAR44)begin
VAR11 <= 1'b0;
VAR95 <= 1'b0;
end else begin
VAR11 <= VAR41;
VAR95 <= VAR11;
end
end
assign VAR15 = (VAR11
| VAR41);
always@(posedge clk)begin
if(VAR44)begin
VAR68[63:0] <= 64'h0000000000000000;
end else begin
if(VAR11)begin
VAR68 <= VAR80;
end else begin
VAR68 <= VAR68;
end
end
end
always@(posedge clk)begin
if(VAR44)begin
VAR16[63:0] <= 64'h0000000000000000;
end else begin
if(VAR95)begin
VAR16 <= VAR80;
end else begin
VAR16 <= VAR16;
end
end
end
assign VAR100 = VAR25[2];
always@(*)begin case(VAR68[63:57])
7'b0000001: VAR22[1:0] <= 2'b01;
7'b1000000: VAR22[1:0] <= 2'b10;
default: VAR22[1:0] <= 2'b01;
endcase
end
always@(posedge clk)begin
if(VAR44)
VAR79 <= 10'b0000000000;
end
else if (~VAR104)begin
if(state == VAR31)
end
VAR79 <= VAR93>>1; else if(VAR79 != 0)
VAR79 <= VAR79 - 1;
end else
VAR79 <= VAR79;
end
always@(posedge clk)begin
if(VAR44)begin
VAR97[31:0] <= 32'h00000000;
end else if(~VAR104) begin
VAR97[31:0] <= VAR2[31:0];
end
end
always@(posedge clk)begin
if(VAR44)begin
VAR17 <= 64'h0000000000000000;
end else if(~VAR74)begin
VAR17 <= VAR2;
end
end
always@(posedge clk)begin
if(VAR44)
VAR49 <= 0;
end
else if(~VAR104)begin
casex({state,VAR75[0]})
{VAR31,1'VAR34}: begin
VAR49 <= VAR33;
end
{VAR54,1'b0}: begin
if(VAR74) VAR49 <= {VAR4[63:32],VAR17[63:32]};
end
else
VAR49 <= {VAR4[63:32],VAR2[63:32]};
end
{VAR54,1'b1}: begin
VAR49 <= VAR4[63:0];
end
{VAR40,1'b0},{VAR85,1'b0}: begin
if(VAR74) VAR49[63:0] <= {VAR97[31:0],VAR17[63:32]};
end
else if(VAR101)
VAR49[63:0] <= {VAR17[31:0],VAR2[63:32]};
end
else
VAR49[63:0] <= {VAR97[31:0],VAR2[63:32]};
end
{VAR40,1'b1},{VAR85,1'b1}: begin
if(VAR74) VAR49[63:0] <= VAR17[63:0];
end
else
VAR49[63:0] <= VAR2[63:0];
end
{VAR53,1'VAR34}: begin
VAR49 <= VAR28;
end
{VAR63,1'VAR34}: begin
VAR49 <= VAR71;
end
{VAR3,1'VAR34}: begin
VAR49 <= {VAR68[31:0],VAR16[63:32]};
end
{VAR21,1'VAR34}: begin
if (VAR22[1:0] == 2'b10) begin
VAR49 <= {VAR16[31:0],32'h00000000};
end else if (VAR22[1:0] == 2'b01) begin
VAR49 <= {VAR16[31:0],VAR106};
end else begin
VAR49 <= {VAR16[31:0],VAR106};
end
end
default: begin
VAR49 <= 0;
end
endcase
end
end
always@(posedge clk)begin
VAR101 <= VAR74;
VAR74 <= VAR104;
end
always@(posedge clk)begin
if(VAR44)begin
VAR13 <= 1'b1;
VAR1 <= 1'b1;
VAR43 <= 1'b1;
VAR90[7:0] <= 8'b11111111;
VAR19 <= 1'b0;
VAR56 <= 1'b0;
VAR14 <= 1'b0;
VAR41 <= 1'b0;
state <= VAR45;
end else if(VAR104)begin
VAR19 <= 1'b0;
VAR56 <= 1'b0;
VAR14 <= 1'b0;
VAR41 <= 1'b0;
end else begin
case(state)
VAR45: begin
VAR13 <= 1'b1;
VAR1 <= 1'b1;
VAR43 <= 1'b1;
VAR90[7:0] <= 8'b11111111;
VAR19 <= 1'b0;
VAR56 <= 1'b0;
VAR14 <= 1'b0;
VAR41 <= 1'b0;
if (~VAR83)
state <= VAR47;
end
else if (~VAR5)
state <= VAR98;
end
else if (~VAR18)
state <= VAR36;
end
else
state <= VAR45;
end
VAR47: begin
VAR56 <= 1'b1; VAR13 <= 1'b1;
VAR90[7:0] <= 8'b11111111;
VAR43 <= 1'b1;
state <= VAR72;
end
VAR98: begin
VAR14 <= 1'b1; VAR13 <= 1'b1;
VAR90[7:0] <= 8'b11111111;
VAR43 <= 1'b1;
state <= VAR58;
end
VAR36: begin
VAR41 <= 1'b1; VAR13 <= 1'b1;
VAR90[7:0] <= 8'b11111111;
VAR43 <= 1'b1;
state <= VAR57;
end
VAR57: begin VAR41 <= 1'b0;
state <= VAR12;
end
VAR12: begin state <= VAR89;
end
VAR89: begin
VAR82[11:0] <= {VAR68[41:32],2'b00};
if(VAR100) state <= VAR32;
end
else
state <= VAR89;
end
VAR32: begin
state <= VAR3;
end
VAR3: begin VAR1 <= 1'b0;
VAR13 <= 1'b0;
VAR90[7:0] <= 8'b00000000;
state <= VAR21;
end
VAR21: begin VAR13 <= 1'b0;
VAR1 <= 1'b1;
VAR43 <= 1'b0;
state <= VAR45;
end
VAR72: begin
VAR56 <= 1'b0;
VAR19 <= 1'b0;
state <= VAR84;
end
VAR84 : begin VAR56 <= 1'b0;
VAR19 <= 1'b0;
state <= VAR9;
end
VAR9 : begin
VAR43 <= 1'b1;
if(VAR103 & ~VAR62) begin if(VAR75[0] == 0)begin VAR19 <= 1'b1;
end else begin VAR19 <= 1'b0;
end
state <= VAR31;
end else begin
VAR19 <= 1'b0;
state <= VAR9;
end
end
VAR31: begin VAR1 <= 1'b0; VAR43 <= 1'b1;
VAR13 <= 1'b0;
VAR90[7:0] <= 8'b00000000;
VAR19 <= 1'b1;
state <= VAR54;
end
VAR54: begin VAR13 <= 1'b0;
VAR1 <= 1'b1; if (VAR75[0] == 0 && VAR93 <= 10'h004)
VAR19 <= 1'b0;
end
else
VAR19 <= 1'b1;
state <= VAR40;
end
VAR40: begin
VAR13 <= 1'b0;
if(VAR79 != 1)begin
state <= VAR40;
end else begin
state <= VAR85;
end
if(VAR75[0] == 0)begin if(VAR79 <=2)
VAR19 <= 1'b0;
end
else
VAR19 <= 1'b1;
end else begin if(VAR79 <=1)
VAR19 <= 1'b0;
end
else
VAR19 <= 1'b1;
end
end
VAR85: begin
VAR13 <= 1'b0;
VAR43 <= 1'b0; VAR19 <= 1'b0;
VAR56 <= 1'b0;
if(VAR75[0] == 0) VAR90[7:0] <= 8'b00001111;
end
else
VAR90[7:0] <= 8'b00000000;
state <= VAR45;
end
VAR58: begin
VAR14 <= 1'b0;
state <= VAR10;
end
VAR10:begin
if(VAR96)
state <= VAR53;
end
else
state <= VAR10;
end
VAR53: begin VAR1 <= 1'b0; VAR13 <= 1'b0;
VAR90[7:0] <= 8'b00000000;
state <= VAR63;
end
VAR63: begin VAR13 <= 1'b0;
VAR1 <= 1'b1; VAR43 <= 1'b0; if(VAR92[0] == 0) VAR90[7:0] <= 8'b00001111;
end
else
VAR90[7:0] <= 8'b00000000;
state <= VAR61;
end
VAR61 : begin state <= VAR45; end
endcase
end
end
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd.behavioral.pp.v | 1,200 | module MODULE1 (
VAR1,
VAR2,
VAR4 ,
VAR3
);
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
walkthetalk/fsref | ip/window_broadcaster/src/window_broadcaster.v | 3,085 | module MODULE1 #
(
parameter integer VAR54 = 12,
parameter integer VAR30 = 12,
parameter integer VAR36 = 32,
parameter integer VAR58 = 1
)
(
input wire [VAR30-1 : 0] VAR6,
input wire [VAR30-1 : 0] VAR16,
input wire [VAR54-1 : 0] VAR9,
input wire [VAR54-1 : 0] VAR32,
input wire [VAR36-1 : 0] VAR50,
output wire [VAR30-1 : 0] VAR51,
output wire [VAR30-1 : 0] VAR15,
output wire [VAR54-1 : 0] VAR43,
output wire [VAR54-1 : 0] VAR5,
output wire [VAR36-1 : 0] VAR25,
output wire [VAR30-1 : 0] VAR24,
output wire [VAR30-1 : 0] VAR29,
output wire [VAR54-1 : 0] VAR61,
output wire [VAR54-1 : 0] VAR7,
output wire [VAR36-1 : 0] VAR27,
output wire [VAR30-1 : 0] VAR42,
output wire [VAR30-1 : 0] VAR38,
output wire [VAR54-1 : 0] VAR14,
output wire [VAR54-1 : 0] VAR40,
output wire [VAR36-1 : 0] VAR45,
output wire [VAR30-1 : 0] VAR18,
output wire [VAR30-1 : 0] VAR31,
output wire [VAR54-1 : 0] VAR49,
output wire [VAR54-1 : 0] VAR23,
output wire [VAR36-1 : 0] VAR44,
output wire [VAR30-1 : 0] VAR26,
output wire [VAR30-1 : 0] VAR11,
output wire [VAR54-1 : 0] VAR55,
output wire [VAR54-1 : 0] VAR12,
output wire [VAR36-1 : 0] VAR34,
output wire [VAR30-1 : 0] VAR53,
output wire [VAR30-1 : 0] VAR10,
output wire [VAR54-1 : 0] VAR21,
output wire [VAR54-1 : 0] VAR35,
output wire [VAR36-1 : 0] VAR57,
output wire [VAR30-1 : 0] VAR4,
output wire [VAR30-1 : 0] VAR48,
output wire [VAR54-1 : 0] VAR19,
output wire [VAR54-1 : 0] VAR22,
output wire [VAR36-1 : 0] VAR46,
output wire [VAR30-1 : 0] VAR28,
output wire [VAR30-1 : 0] VAR60,
output wire [VAR54-1 : 0] VAR39,
output wire [VAR54-1 : 0] VAR62,
output wire [VAR36-1 : 0] VAR2
);
localparam integer VAR47 = 8;
wire [VAR30-1 : 0] VAR41 [VAR47-1:0];
wire [VAR30-1 : 0] VAR37 [VAR47-1:0];
wire [VAR54-1 : 0] VAR20 [VAR47-1:0];
wire [VAR54-1 : 0] VAR17[VAR47-1:0];
wire [VAR36-1 : 0] VAR3[VAR47-1:0];
assign VAR52 = VAR41 [VAR8]; \
assign VAR56 = VAR37 [VAR8]; \
assign VAR1 = VAR20 [VAR8]; \
assign VAR59 = VAR17[VAR8]; \
assign VAR33 = VAR3[VAR8];
generate
genvar VAR8;
for (VAR8=0; VAR8 < VAR47; VAR8 = VAR8+1) begin: VAR13
if (VAR8 < VAR58) begin
assign VAR41 [VAR8] = VAR6 ;
assign VAR20 [VAR8] = VAR9 ;
assign VAR37 [VAR8] = VAR16 ;
assign VAR17[VAR8] = VAR32;
assign VAR3[VAR8] = VAR50;
end
else begin
assign VAR41 [VAR8] = 0;
assign VAR20 [VAR8] = 0;
assign VAR37 [VAR8] = 0;
assign VAR17[VAR8] = 0;
assign VAR3[VAR8] = 0;
end
end
endgenerate
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3.functional.v | 1,759 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR5,
VAR7
);
output VAR9 ;
input VAR10 ;
input VAR5;
input VAR7;
wire VAR6 ;
wire VAR3;
not VAR2 (VAR6 , VAR10 );
VAR4 VAR8 (VAR3, VAR6, VAR5, VAR7);
buf VAR1 (VAR9 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b.functional.v | 1,409 | module MODULE1 (
VAR8 ,
VAR2,
VAR5 ,
VAR4
);
output VAR8 ;
input VAR2;
input VAR5 ;
input VAR4 ;
wire VAR9 ;
wire VAR7;
not VAR3 (VAR9 , VAR2 );
nand VAR1 (VAR7, VAR5, VAR9, VAR4 );
buf VAR6 (VAR8 , VAR7 );
endmodule | apache-2.0 |
MeshSr/onetswitch20 | ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/op_lut_regs.v | 11,040 | module MODULE1
parameter VAR65 = 4,
parameter VAR13 = 2
)
(
input VAR33,
input VAR69,
input VAR71,
input [VAR6-1:0] VAR85,
input [VAR36-1:0] VAR39,
input [VAR13-1:0] VAR3,
output reg VAR68,
output reg VAR72,
output reg VAR20,
output reg [VAR6-1:0] VAR48,
output reg [VAR36-1:0] VAR22,
output reg [VAR13-1:0] VAR74,
output [VAR65-1:0] VAR59, output reg VAR17, input [VAR7-1:0] VAR25, input VAR4, input [47:0] VAR12, input VAR63,
output [VAR65-1:0] VAR8,
output reg VAR5,
output [VAR7-1:0] VAR45,
output VAR30, output [47:0] VAR51, input VAR29,
input VAR47,
input VAR15,
input clk,
input reset
);
function integer VAR26;
input integer VAR24;
begin
VAR26=0;
while(2**VAR26<VAR24) begin
VAR26=VAR26+1;
end
end
endfunction
parameter VAR70 = 6;
parameter VAR14 = VAR26(VAR70);
parameter VAR83 = 1;
parameter VAR62 = 2;
parameter VAR52 = 4;
parameter VAR46 = 8;
wire [VAR36-1:0] VAR31 [0:VAR70-1];
reg [VAR36-1:0] VAR23 [0:VAR70-1];
wire [VAR36-1:0] VAR57;
wire [VAR14-1:0]addr;
wire [VAR37 - 1:0] VAR11;
wire [VAR6-VAR49-VAR19 - 1:0] VAR56;
wire VAR1;
wire VAR32;
wire [VAR36-1:0] VAR84;
wire [VAR36-1:0] VAR27;
reg [3:0] state, VAR44;
reg [VAR36-1:0] VAR16;
wire [VAR36-1:0] VAR77;
wire [VAR36-1:0] VAR9;
reg [VAR70*VAR36-1:0] VAR73;
wire [VAR70*VAR36-1:0] VAR42;
reg VAR80;
reg [VAR6-1:0] VAR67;
reg [VAR36-1:0] VAR38;
reg [VAR13-1:0] VAR41;
reg VAR28;
reg [VAR6-1:0] VAR75;
reg [VAR36-1:0] VAR18;
reg [VAR13-1:0] VAR58;
reg VAR43;
reg VAR53;
reg VAR50;
reg [VAR6-1:0] VAR76;
reg [VAR36-1:0] VAR40;
reg [VAR13-1:0] VAR66;
assign addr = VAR85[VAR14-1:0];
assign VAR11 = VAR85[VAR19-1:0];
assign VAR56 = VAR85[VAR6 - 1:VAR19];
assign VAR1 = (VAR11<VAR70);
assign VAR32 = VAR56 == VAR54;
assign VAR84 = VAR31[VAR82];
assign VAR27 = VAR31[VAR21];
assign VAR45 = VAR27[VAR7+15:16]; assign VAR30 = VAR27[31]; assign VAR51 = {VAR27, VAR31[VAR82]}; assign VAR8 = VAR31[VAR10];
assign VAR59 = VAR31[VAR2];
assign VAR77 = VAR31[VAR81];
assign VAR9 = VAR31[VAR35];
assign VAR57 = VAR31[addr];
generate
genvar VAR34;
for(VAR34=0; VAR34<VAR70; VAR34=VAR34+1) begin:VAR64
assign VAR42[VAR61(VAR34):VAR79(VAR34)] = VAR23[VAR34];
assign VAR31[VAR34] = VAR73[VAR61(VAR34):VAR79(VAR34)];
end
endgenerate
always @(*) begin
VAR23[VAR21] = VAR27;
VAR23[VAR82] = VAR84;
VAR23[VAR10] = VAR8;
VAR23[VAR2] = VAR59;
VAR23[VAR81] = VAR77 + VAR47;
VAR23[VAR35] = VAR9 + VAR15;
VAR44 = state;
VAR43 = 0;
VAR53 = 0;
VAR50 = 0;
VAR76 = 0;
VAR40 = 0;
VAR66 = 0;
VAR28 = VAR80;
VAR75 = VAR67;
VAR18 = VAR38;
VAR58 = VAR41;
VAR5 = 0;
VAR17 = 0;
case(state)
VAR83: begin
if (VAR33 && VAR32) begin
if (!VAR71 && VAR1) begin
VAR23[addr] = VAR39;
case (addr)
default : VAR44 = VAR46;
endcase
VAR28 = VAR71;
VAR75 = VAR85;
VAR18 = VAR39;
VAR58 = VAR3;
end
else begin
VAR43 = 1'VAR78 1;
VAR53 = 1'VAR78 1;
VAR50 = VAR71;
VAR76 = VAR85;
VAR40 = VAR1 ? VAR57 : 32'VAR55 VAR60;
VAR66 = VAR3;
end
end
else begin
VAR43 = VAR33;
VAR53 = VAR69;
VAR50 = VAR71;
VAR76 = VAR85;
VAR40 = VAR39;
VAR66 = VAR3;
end
end
VAR62: begin
if(VAR29) begin
VAR44 = VAR46;
end
else begin
VAR5 = 1;
end
end
VAR52: begin
if(VAR63) begin
VAR23[VAR21] = {VAR4,
{(15-VAR7){1'b0}},
VAR25,
VAR12[47:32]};
VAR23[VAR82] = VAR12[31:0];
VAR44 = VAR46;
end else begin
VAR17 = 1;
end
end
VAR46: begin
VAR44 = VAR83;
VAR43 = 1'VAR78 1;
VAR53 = 1'VAR78 1;
VAR50 = VAR80;
VAR76 = VAR67;
VAR40 = VAR38;
VAR66 = VAR41;
end
endcase end
always @(posedge clk) begin
if( reset ) begin
VAR68 <= 0;
VAR72 <= 0;
VAR20 <= 0;
VAR48 <= 0;
VAR22 <= 0;
VAR74 <= 0;
VAR80 <= 0;
VAR67 <= 0;
VAR38 <= 0;
VAR41 <= 0;
VAR73 <= {(VAR36*VAR70){1'b0}};
state <= VAR83;
end
else begin
VAR68 <= VAR43;
VAR72 <= VAR53;
VAR20 <= VAR50;
VAR48 <= VAR76;
VAR22 <= VAR40;
VAR74 <= VAR66;
VAR80 <= VAR28;
VAR67 <= VAR75;
VAR38 <= VAR18;
VAR41 <= VAR58;
VAR73 <= VAR42;
state <= VAR44;
end end
endmodule | lgpl-2.1 |
rurume/openrisc_vision_hardware | ISE/or1200_spram_64x14.v | 10,655 | module MODULE1(
VAR53, VAR54, VAR1,
clk, rst, VAR4, VAR2, VAR28, addr, VAR16, VAR52
);
parameter VAR32 = 6;
parameter VAR14 = 14;
input VAR53;
input [VAR6 - 1:0] VAR1;
output VAR54;
input clk; input rst; input VAR4; input VAR2; input VAR28; input [VAR32-1:0] addr; input [VAR14-1:0] VAR16; output [VAR14-1:0] VAR52;
wire [1:0] VAR37;
wire [1:0] VAR37;
assign VAR54 = VAR53;
VAR22 #(VAR14, 1<<VAR32, VAR32) VAR41(
VAR13 VAR41(
VAR22 VAR41(
.VAR53(VAR53),
.VAR54(VAR54),
.VAR1(VAR1),
.VAR5(clk),
.VAR27(~VAR4),
.VAR43(~VAR2),
.VAR24(addr),
.VAR50(VAR16),
.VAR10(~VAR28),
.VAR7(VAR52)
);
VAR31 VAR31(
.VAR3(~VAR2),
.VAR45(),
.VAR9(~VAR28),
.VAR17(),
.VAR8(),
.VAR36(addr),
.VAR20(addr),
.VAR16(VAR16),
.VAR52(VAR52)
);
VAR23 VAR23(
.clk(clk),
.VAR26(addr),
.VAR19(VAR16),
.VAR2(VAR2),
.VAR28(VAR28),
.VAR47(VAR4),
.VAR46(VAR52)
);
VAR18 #(1<<VAR32, VAR32-1, VAR14-1) VAR12(
VAR11 VAR12(
VAR18 VAR12(
.VAR53(VAR53),
.VAR54(VAR54),
.VAR1(VAR1),
.VAR51(clk),
.VAR49(addr),
.VAR34(VAR16),
.VAR43(~VAR2),
.VAR27(~VAR4),
.VAR10(~VAR28),
.VAR42(VAR52)
);
VAR35 VAR44(
.VAR5(clk),
.VAR33(rst),
.VAR40({2'b00, addr}),
.VAR34({2'b00, VAR16[13:0]}),
.VAR21(VAR4),
.VAR30(VAR2),
.VAR39({VAR37, VAR52[13:0]})
);
VAR29 VAR48(
.VAR5(clk),
.VAR25(rst),
.VAR40({4'b0000, addr}),
.VAR34({2'b00, VAR16[13:0]}),
.VAR15(2'b00),
.VAR21(VAR4),
.VAR30(VAR2),
.VAR39({VAR37, VAR52[13:0]}),
.VAR38()
);
wire wr;
assign wr = VAR4 & VAR2; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah.behavioral.v | 1,744 | module MODULE1 (
VAR16,
VAR12 ,
VAR2 ,
VAR7 ,
VAR15
);
output VAR16;
output VAR12 ;
input VAR2 ;
input VAR7 ;
input VAR15 ;
supply1 VAR19;
supply0 VAR20;
supply1 VAR14 ;
supply0 VAR6 ;
wire VAR11;
wire VAR17 ;
wire VAR4 ;
wire VAR13 ;
wire VAR21;
xor VAR1 (VAR11, VAR2, VAR7, VAR15 );
buf VAR5 (VAR12 , VAR11 );
and VAR3 (VAR17 , VAR2, VAR7 );
and VAR8 (VAR4 , VAR2, VAR15 );
and VAR10 (VAR13 , VAR7, VAR15 );
or VAR9 (VAR21, VAR17, VAR4, VAR13);
buf VAR18 (VAR16 , VAR21 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_vuadcol_dp.v | 6,581 | module MODULE1
(
VAR17,
VAR19, VAR16, VAR25, VAR15, VAR4
) ;
input [103:0] VAR19; input [103:0] VAR4;
input [3:0] VAR16; input [3:0] VAR25; input VAR15;
output [25:0] VAR17;
wire [25:0] VAR29;
wire [25:0] VAR14;
wire [25:0] VAR10;
wire [25:0] VAR27;
wire [25:0] VAR28;
wire [25:0] VAR2;
wire [25:0] VAR7;
wire [25:0] VAR26;
wire [25:0] VAR20;
wire [25:0] VAR9;
assign VAR10 = { VAR4[100], VAR4[96], VAR4[92],
VAR4[88], VAR4[84], VAR4[80],
VAR4[76], VAR4[72], VAR4[68],
VAR4[64], VAR4[60], VAR4[56],
VAR4[52], VAR4[48], VAR4[44],
VAR4[40], VAR4[36], VAR4[32],
VAR4[28], VAR4[24], VAR4[20],
VAR4[16], VAR4[12], VAR4[8],
VAR4[4], VAR4[0]};
assign VAR27 = { VAR4[101], VAR4[97], VAR4[93],
VAR4[89], VAR4[85], VAR4[81],
VAR4[77], VAR4[73], VAR4[69],
VAR4[65], VAR4[61], VAR4[57],
VAR4[53], VAR4[49], VAR4[45],
VAR4[41], VAR4[37], VAR4[33],
VAR4[29], VAR4[25], VAR4[21],
VAR4[17], VAR4[13], VAR4[9],
VAR4[5], VAR4[1]};
assign VAR28 = { VAR4[102], VAR4[98], VAR4[94],
VAR4[90], VAR4[86], VAR4[82],
VAR4[78], VAR4[74], VAR4[70],
VAR4[66], VAR4[62], VAR4[58],
VAR4[54], VAR4[50], VAR4[46],
VAR4[42], VAR4[38], VAR4[34],
VAR4[30], VAR4[26], VAR4[22],
VAR4[18], VAR4[14], VAR4[10],
VAR4[6], VAR4[2]};
assign VAR2 = { VAR4[103], VAR4[99], VAR4[95],
VAR4[91], VAR4[87], VAR4[83],
VAR4[79], VAR4[75], VAR4[71],
VAR4[67], VAR4[63], VAR4[59],
VAR4[55], VAR4[51], VAR4[47],
VAR4[43], VAR4[39], VAR4[35],
VAR4[31], VAR4[27], VAR4[23],
VAR4[19], VAR4[15], VAR4[11],
VAR4[7], VAR4[3]};
VAR12 #(26) VAR13 (.dout (VAR29[25:0]),
.VAR5(VAR10[25:0]),
.VAR22(VAR27[25:0]),
.VAR24(VAR28[25:0]),
.VAR23(VAR2[25:0]),
.VAR1(VAR16[0]),
.VAR6(VAR16[1]),
.VAR3(VAR16[2]),
.VAR11(VAR16[3]));
assign VAR7 = { VAR19[100], VAR19[96], VAR19[92],
VAR19[88], VAR19[84], VAR19[80],
VAR19[76], VAR19[72], VAR19[68],
VAR19[64], VAR19[60], VAR19[56],
VAR19[52], VAR19[48], VAR19[44],
VAR19[40], VAR19[36], VAR19[32],
VAR19[28], VAR19[24], VAR19[20],
VAR19[16], VAR19[12], VAR19[8],
VAR19[4], VAR19[0]};
assign VAR26 = { VAR19[101], VAR19[97], VAR19[93],
VAR19[89], VAR19[85], VAR19[81],
VAR19[77], VAR19[73], VAR19[69],
VAR19[65], VAR19[61], VAR19[57],
VAR19[53], VAR19[49], VAR19[45],
VAR19[41], VAR19[37], VAR19[33],
VAR19[29], VAR19[25], VAR19[21],
VAR19[17], VAR19[13], VAR19[9],
VAR19[5], VAR19[1]};
assign VAR20 = { VAR19[102], VAR19[98], VAR19[94],
VAR19[90], VAR19[86], VAR19[82],
VAR19[78], VAR19[74], VAR19[70],
VAR19[66], VAR19[62], VAR19[58],
VAR19[54], VAR19[50], VAR19[46],
VAR19[42], VAR19[38], VAR19[34],
VAR19[30], VAR19[26], VAR19[22],
VAR19[18], VAR19[14], VAR19[10],
VAR19[6], VAR19[2]};
assign VAR9 = { VAR19[103], VAR19[99], VAR19[95],
VAR19[91], VAR19[87], VAR19[83],
VAR19[79], VAR19[75], VAR19[71],
VAR19[67], VAR19[63], VAR19[59],
VAR19[55], VAR19[51], VAR19[47],
VAR19[43], VAR19[39], VAR19[35],
VAR19[31], VAR19[27], VAR19[23],
VAR19[19], VAR19[15], VAR19[11],
VAR19[7], VAR19[3]};
VAR12 #(26) VAR18 (.dout (VAR14[25:0]),
.VAR5(VAR7[25:0]),
.VAR22(VAR26[25:0]),
.VAR24(VAR20[25:0]),
.VAR23(VAR9[25:0]),
.VAR1(VAR25[0]),
.VAR6(VAR25[1]),
.VAR3(VAR25[2]),
.VAR11(VAR25[3]));
VAR8 #(26) VAR21 (.dout (VAR17[25:0]),
.VAR5(VAR29[25:0]),
.VAR22(VAR14[25:0]),
.VAR1(~VAR15),
.VAR6(VAR15));
endmodule | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/ModulosBasicos/PruebasFPGA/divisorprueba/conmutacion.v | 1,067 | module MODULE1
(
input [3:0] VAR1,
input [3:0] VAR2,
input [3:0] VAR5,
input VAR11,
input VAR4,
input VAR3,
input VAR10,
output reg [1:0] VAR8,
output reg [3:0] VAR6
);
reg VAR7;
reg [1:0] VAR9;
begin
begin
begin
end
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
begin | gpl-3.0 |
GLADICOS/UART | rtl/uart_rx.v | 3,543 | module MODULE1#(
parameter integer VAR17 = 12
)
(
input VAR13,
input VAR15,
input VAR7,
input [11:0] VAR9,
output reg [7:0] VAR6,
output reg VAR18,
output VAR16
);
localparam [3:0] VAR11 = 4'b0000,
VAR10 = 4'b0001,
VAR3 = 4'b0010,
VAR14 = 4'b0100,
VAR8 = 4'b1000;
reg [3:0] VAR2;
reg [3:0] VAR12;
reg [VAR17-1:0] VAR5;
reg [3:0] VAR1;
reg VAR4;
assign VAR16 = (VAR2 == VAR8 & VAR5 == 12'd2)?1'b1:1'b0;
always@(*)
begin
VAR12 = VAR2;
case(VAR2)
VAR11:
begin
if(VAR7)
begin
VAR12 = VAR11;
end
else
begin
VAR12 = VAR10;
end
end
VAR10:
begin
if(VAR5 == VAR9 && VAR4 == 1'b0)
begin
VAR12 = VAR3;
end
else if(VAR5 != VAR9)
begin
VAR12 = VAR10;
end
else
begin
VAR12 = VAR11;
end
end
VAR3:
begin
if(VAR5 != VAR9 && VAR1 != 4'b1000)
begin
VAR12 = VAR3;
end
else if(VAR5 == VAR9 && VAR1 != 4'b1000)
begin
VAR12 = VAR3;
end
else if(VAR5 == VAR9 && VAR1 == 4'b1000)
begin
VAR12 = VAR14;
end
end
VAR14:
begin
if(VAR5 != VAR9)
begin
VAR12 = VAR14;
end
else
begin
VAR12 = VAR8;
end
end
VAR8:
begin
if(VAR5 != VAR9)
begin
VAR12 = VAR8;
end
else if(VAR5 == VAR9 && VAR4 == 1'b0)
begin
VAR12 = VAR8;
end
else
begin
VAR12 = VAR11;
end
end
default:
begin
VAR12 = VAR11;
end
endcase
end
always@(posedge VAR13)
begin
if(VAR15)
begin
VAR2 <= VAR11;
VAR5<= {VAR17{1'b0}};
VAR1<= 4'd0;
VAR6<=8'd0;
VAR4<= 1'b1;
end
else
begin
VAR2 <= VAR12;
case(VAR2)
VAR11:
begin
if(VAR7)
begin
VAR5<= {VAR17{1'b0}};
VAR1<= 4'd0;
end
else
begin
VAR5<= VAR5 + 1'b1;
end
end
VAR10:
begin
if(VAR5 == VAR9/2'd2)
begin
VAR4 <= VAR7;
VAR5<= VAR5 + 1'b1;
end
else if(VAR5 < VAR9)
begin
VAR5<= VAR5 + 1'b1;
end
else
begin
VAR5<= {VAR17{1'b0}};
end
end
VAR3:
begin
if(VAR1 != 4'b1000 && VAR5 == VAR9/2'd2)
begin
VAR1<= VAR1+1'b1;
VAR6[VAR1[2:0]]<=VAR7;
VAR5<= VAR5 + 1'b1;
end
else if(VAR5 < VAR9)
begin
VAR5<= VAR5 + 1'b1;
end
else
begin
VAR5<= {VAR17{1'b0}};
end
end
VAR14:
begin
if(VAR5 == VAR9/2'd2)
begin
VAR18 <= VAR7;
VAR5 <= VAR5 + 1'b1;
end
else if(VAR5 < VAR9)
begin
VAR5 <= VAR5 + 1'b1;
end
else
begin
VAR5<= {VAR17{1'b0}};
VAR4 <= 1'b0;
end
end
VAR8:
begin
if(VAR5 == VAR9/2'd2)
begin
VAR4 <= VAR7;
VAR5<= VAR5 + 1'b1;
end
else if(VAR5 < VAR9)
begin
VAR5<= VAR5 + 1'b1;
end
else
begin
VAR5<= {VAR17{1'b0}};
end
VAR1<= 4'd0;
end
default:
begin
VAR1<= 4'd0;
VAR5<= {VAR17{1'b0}};
end
endcase
end
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_mux_4to2/sky130_fd_sc_ms__udp_mux_4to2.symbol.v | 1,327 | module MODULE1 (
input VAR4,
input VAR5,
input VAR2,
input VAR6,
output VAR7 ,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b.functional.v | 1,356 | module MODULE1 (
VAR4 ,
VAR8,
VAR1
);
output VAR4 ;
input VAR8;
input VAR1 ;
wire VAR3 ;
wire VAR6;
not VAR2 (VAR3 , VAR1 );
or VAR5 (VAR6, VAR3, VAR8 );
buf VAR7 (VAR4 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.blackbox.v | 1,441 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR3 ,
VAR6 ,
VAR4,
VAR1 ,
VAR2
);
output VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR6 ;
input VAR4;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.pp.blackbox.v | 1,263 | module MODULE1 (
VAR1,
VAR2,
VAR4 ,
VAR3
);
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/Arty/fpga/rtl/debounce_switch.v | 2,576 | module MODULE1 #(
parameter VAR4=1, parameter VAR2=3, parameter VAR5=125000 )(
input wire clk,
input wire rst,
input wire [VAR4-1:0] in,
output wire [VAR4-1:0] out
);
reg [23:0] VAR1 = 24'd0;
reg [VAR2-1:0] VAR6[VAR4-1:0];
reg [VAR4-1:0] state;
assign out = state;
integer VAR3;
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR1 <= 0;
state <= 0;
for (VAR3 = 0; VAR3 < VAR4; VAR3 = VAR3 + 1) begin
VAR6[VAR3] <= 0;
end
end else begin
if (VAR1 < VAR5) begin
VAR1 <= VAR1 + 24'd1;
end else begin
VAR1 <= 24'd0;
end
if (VAR1 == 24'd0) begin
for (VAR3 = 0; VAR3 < VAR4; VAR3 = VAR3 + 1) begin
VAR6[VAR3] <= {VAR6[VAR3][VAR2-2:0], in[VAR3]};
end
end
for (VAR3 = 0; VAR3 < VAR4; VAR3 = VAR3 + 1) begin
if (|VAR6[VAR3] == 0) begin
state[VAR3] <= 0;
end else if (&VAR6[VAR3] == 1) begin
state[VAR3] <= 1;
end else begin
state[VAR3] <= state[VAR3];
end
end
end
end
endmodule | mit |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkTop_HW_Side.v | 11,128 | module MODULE1(VAR72,
VAR102);
input VAR72;
input VAR102;
reg VAR96;
wire VAR79, VAR20;
reg [11 : 0] VAR106;
wire [11 : 0] VAR104;
wire VAR90;
wire [352 : 0] VAR50;
wire [255 : 0] VAR38;
wire VAR9,
VAR81,
VAR74,
VAR59;
wire [352 : 0] VAR5;
wire [255 : 0] VAR17;
wire [63 : 0] VAR95,
VAR105;
wire [7 : 0] VAR43,
VAR18,
VAR14;
wire [3 : 0] VAR39;
wire VAR108,
VAR36,
VAR98,
VAR33,
VAR100,
VAR60,
VAR61,
VAR7,
VAR101,
VAR80,
VAR94;
wire VAR15,
VAR37,
VAR91,
VAR16,
VAR40,
VAR73,
VAR21,
VAR23,
VAR4,
VAR92,
VAR10,
VAR47;
reg [31 : 0] VAR64;
reg [31 : 0] VAR107;
reg VAR30;
reg VAR63;
reg VAR93;
reg [63 : 0] VAR41;
reg [31 : 0] VAR53;
reg [7 : 0] VAR57;
reg [31 : 0] VAR29;
reg [31 : 0] VAR65;
reg [31 : 0] VAR71;
VAR89 VAR44(.VAR72(VAR72),
.VAR102(VAR102),
.VAR75(VAR50),
.VAR76(VAR9),
.VAR1(VAR81),
.VAR66(VAR74),
.VAR26(VAR38),
.VAR87(VAR59));
VAR84 VAR51(.VAR72(VAR72),
.VAR102(VAR102),
.VAR19(VAR18),
.VAR82(VAR95),
.VAR32(VAR39),
.VAR52(VAR105),
.VAR46(VAR94),
.VAR6(VAR17),
.VAR42(VAR98),
.VAR69(VAR100),
.VAR55(VAR60),
.VAR3(VAR108),
.VAR83(VAR36),
.VAR48(VAR33),
.VAR68(),
.VAR54(VAR5),
.VAR70(VAR101),
.VAR34(VAR80),
.VAR58(VAR43),
.VAR8(VAR61),
.VAR56(VAR7),
.VAR85(VAR14),
.VAR24());
assign VAR73 = VAR14 != 8'd0 ;
assign VAR47 = VAR73 ;
assign VAR40 = !VAR96 ;
assign VAR10 = VAR40 ;
assign VAR16 = VAR61 ;
assign VAR92 = VAR61 ;
assign VAR91 =
VAR106 != 12'd0 || VAR7 ;
assign VAR4 = VAR91 ;
assign VAR15 =
VAR101 &&
VAR74 ;
assign VAR21 =
VAR15 ;
assign VAR37 =
VAR80 &&
VAR59 ;
assign VAR23 =
VAR37 ;
assign VAR79 = 1'd1 ;
assign VAR20 = VAR40 ;
assign VAR104 = VAR106 + 12'd1 ;
assign VAR90 = VAR91 ;
assign VAR50 = VAR5 ;
assign VAR9 =
VAR15 ;
assign VAR81 =
VAR37 ;
assign VAR18 = VAR57 ;
assign VAR95 = 64'd0 ;
assign VAR39 =
VAR63 ?
4'd2 :
(VAR30 ? 4'd1 : 4'd0) ;
assign VAR105 = VAR41 ;
assign VAR94 = VAR93 ;
assign VAR17 = VAR38 ;
assign VAR98 = VAR40 ;
assign VAR100 =
VAR15 ;
assign VAR60 =
VAR37 ;
assign VAR108 = VAR61 ;
assign VAR36 =
VAR4 &&
VAR106 == 12'd0 &&
VAR57 != 8'd0 ;
assign VAR33 = VAR40 ;
always@(posedge VAR72)
begin
if (VAR102 == VAR77)
begin
VAR96 <= VAR103 1'd0;
VAR106 <= VAR103 12'd0;
end
else
begin
if (VAR20)
VAR96 <= VAR103 VAR79;
if (VAR90)
VAR106 <= VAR103 VAR104;
end
end
begin
VAR96 = 1'h0;
VAR106 = 12'hAAA;
end
always@(negedge VAR72)
begin
if (VAR102 != VAR77)
if (VAR47)
begin
VAR64 = VAR45;
end
VAR71 = VAR64 / 32'd10;
if (VAR102 != VAR77)
if (VAR47)
",
VAR71,
VAR14,
VAR14);
if (VAR102 != VAR77)
if (VAR47)
begin
VAR107 = VAR45;
end
VAR65 = VAR107 / 32'd10;
if (VAR102 != VAR77)
if (VAR47)
VAR88({ 32'd0, VAR65 });
if (VAR102 != VAR77)
if (VAR47)
if (VAR102 != VAR77)
if (VAR10)
if (VAR102 != VAR77)
if (VAR10)
if (VAR102 != VAR77)
if (VAR10)
2017-2019 VAR25, VAR28. VAR86 VAR11 VAR62.");
if (VAR102 != VAR77)
if (VAR10)
if (VAR102 != VAR77)
if (VAR10)
begin
VAR30 = ("VAR13");
end
if (VAR102 != VAR77)
if (VAR10)
begin
VAR63 = ("VAR35");
end
if (VAR102 != VAR77)
if (VAR10)
begin
VAR93 = ("VAR97");
end
if (VAR102 != VAR77)
if (VAR10)
begin
VAR41 = VAR22("VAR97");
end
if (VAR102 != VAR77)
if (VAR10)
VAR49("VAR31: VAR78 = %0d, VAR99 = 0x%0h",
VAR93,
VAR41);
if (VAR102 != VAR77)
if (VAR10)
begin
VAR53 = VAR45;
end
VAR29 = VAR53 / 32'd10;
if (VAR102 != VAR77)
if (VAR10) VAR12({ 32'd0, VAR29 });
if (VAR102 != VAR77)
if (VAR61)
("%VAR67", VAR43);
if (VAR102 != VAR77)
if (VAR61) VAR27(32'h80000001);
if (VAR102 != VAR77)
if (VAR4 && VAR106 == 12'd0)
begin
VAR57 = VAR2(8'hAA);
end
end
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a.blackbox.v | 1,373 | module MODULE1 (
VAR3 ,
VAR6,
VAR5,
VAR4,
VAR9,
VAR2
);
output VAR3 ;
input VAR6;
input VAR5;
input VAR4;
input VAR9;
input VAR2;
supply1 VAR10;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21o/sky130_fd_sc_hs__a21o.functional.v | 1,913 | module MODULE1 (
VAR10,
VAR6,
VAR11 ,
VAR12 ,
VAR8 ,
VAR3
);
input VAR10;
input VAR6;
output VAR11 ;
input VAR12 ;
input VAR8 ;
input VAR3 ;
wire VAR2 ;
wire VAR14 ;
wire VAR4;
and VAR7 (VAR2 , VAR12, VAR8 );
or VAR9 (VAR14 , VAR2, VAR3 );
VAR13 VAR5 (VAR4, VAR14, VAR10, VAR6);
buf VAR1 (VAR11 , VAR4 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_ecl_eccctl.v | 10,186 | module MODULE1 (
VAR67, VAR55, VAR101,
VAR93, VAR25, VAR52,
VAR94, VAR81, VAR35,
VAR37, VAR5, VAR34,
VAR53, VAR71, VAR105,
VAR36, VAR64, VAR77,
clk, VAR29, VAR65, VAR99, VAR43,
VAR31, VAR90, VAR79, VAR4,
VAR16, VAR73,
VAR62, VAR104, VAR17, VAR27,
VAR24, VAR7, VAR96, VAR72,
VAR30, VAR50, VAR63,
VAR66, VAR38, VAR33,
VAR85, VAR86
) ;
input clk;
input VAR29;
input VAR65;
input VAR99;
input VAR43;
input VAR31;
input VAR90;
input VAR79;
input VAR4;
input VAR16;
input VAR73;
input VAR62;
input VAR104;
input VAR17;
input VAR27;
input [4:0] VAR24;
input [4:0] VAR7;
input [4:0] VAR96;
input [2:0] VAR72;
input [7:0] VAR30;
input VAR50;
input VAR63;
input VAR66;
input VAR38;
input VAR33;
input [1:0] VAR85;
input VAR86;
output VAR67;
output VAR55;
output VAR101;
output VAR93;
output VAR25;
output VAR52;
output VAR94;
output VAR81;
output VAR35;
output VAR37;
output VAR5;
output [4:0] VAR34;
output VAR53;
output VAR71;
output [7:0] VAR105;
output [7:0] VAR36;
output VAR64;
output VAR77;
wire VAR75;
wire VAR78;
wire VAR56;
wire VAR95;
wire VAR13;
wire VAR61;
wire VAR6;
wire VAR106;
wire VAR68;
wire [2:0] VAR12;
wire [2:0] VAR19;
wire [1:0] VAR91;
wire VAR8;
wire VAR9;
wire VAR2;
wire VAR97;
wire VAR41;
wire VAR103;
wire [4:0] VAR42;
wire VAR59;
wire VAR3;
wire VAR98;
wire VAR22;
wire VAR57;
wire VAR51;
wire VAR23;
wire VAR14;
wire VAR40;
wire VAR39;
assign VAR35 = VAR51 & VAR104 & VAR33;
assign VAR37 = VAR23 & VAR17 & VAR33;
assign VAR5 = VAR14 & VAR27 & VAR33;
VAR1 VAR80(.din(VAR16), .clk(clk),
.VAR69(VAR51), .VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR20(.din(VAR73), .clk(clk),
.VAR69(VAR23), .VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR21(.din(VAR62), .clk(clk),
.VAR69(VAR14), .VAR29(VAR29), .VAR76(), .VAR45());
assign VAR40 = VAR79 & ~VAR86;
assign VAR39 = VAR4 & ~VAR86;
assign VAR2 = (VAR99 | VAR31 | VAR40);
assign VAR97 = (VAR43 | VAR90 | VAR39);
assign VAR103 = (VAR97 |
VAR2 & VAR63); assign VAR41 = VAR2 & ~VAR63;
VAR1 VAR84(.din(VAR41), .clk(clk), .VAR69(VAR81),
.VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR100(.din(VAR103), .clk(clk), .VAR69(VAR71),
.VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR102(.din(VAR38), .clk(clk), .VAR69(VAR70), .VAR29(VAR29), .VAR76(), .VAR45());
assign VAR67 = VAR71 & VAR70;
assign VAR53 = VAR81 & ~VAR71;
assign VAR105[7:5] = (~VAR42[4] & ~VAR42[3])? {1'b0,VAR91[1:0]}: VAR19[2:0];
assign VAR105[4:0] = VAR42[4:0];
assign VAR75 = VAR99;
assign VAR78 = ~VAR99 & VAR31;
assign VAR56 = ~(VAR99 | VAR31);
VAR1 VAR54(.din(VAR75), .clk(clk), .VAR69(VAR95),
.VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR74(.din(VAR78), .clk(clk), .VAR69(VAR13),
.VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR58(.din(VAR56), .clk(clk), .VAR69(VAR61),
.VAR29(VAR29), .VAR76(), .VAR45());
assign VAR6 = VAR95 | VAR65;
assign VAR106 = VAR13 & ~VAR65;
assign VAR68 = VAR61 & ~VAR65;
assign VAR55 = ~VAR6;
assign VAR101 = ~VAR106;
assign VAR93 = ~VAR68;
VAR89 #(5) VAR18(.dout(VAR34[4:0]),
.VAR44(VAR24[4:0]),
.VAR88(VAR7[4:0]),
.VAR87(VAR96[4:0]),
.VAR11(VAR6),
.VAR47(VAR106),
.VAR82(VAR68));
assign VAR25 = VAR3 | (VAR59 & ~VAR22 & ~VAR57);
assign VAR52 = (VAR22 & ~VAR3) | (VAR98 & ~VAR3 & ~VAR59 & ~VAR57);
assign VAR94 = ~(VAR25 | VAR52);
VAR89 #(5) VAR26(.dout(VAR42[4:0]),
.VAR44(VAR24[4:0]),
.VAR88(VAR7[4:0]),
.VAR87(VAR96[4:0]),
.VAR11(VAR25),
.VAR47(VAR52),
.VAR82(VAR94));
VAR1 #(3) VAR60(.din(VAR72[2:0]), .clk(clk), .VAR69(VAR12[2:0]),
.VAR29(VAR29), .VAR76(), .VAR45());
VAR1 #(3) VAR46(.din(VAR12[2:0]), .clk(clk), .VAR69(VAR19[2:0]),
.VAR29(VAR29), .VAR76(), .VAR45());
VAR1 #(2) VAR83(.din(VAR85[1:0]), .clk(clk), .VAR69(VAR91[1:0]),
.VAR29(VAR29), .VAR76(), .VAR45());
VAR89 VAR15(.dout(VAR77),
.VAR44(VAR59),
.VAR88(VAR98),
.VAR87(~VAR57),
.VAR11(VAR25),
.VAR47(VAR52),
.VAR82(VAR94));
assign VAR8 = VAR66 & VAR50;
assign VAR36 = ~(VAR30[7:0] & {8{VAR8}});
VAR1 VAR28(.din(VAR8), .clk(clk), .VAR69(VAR9),
.VAR29(VAR29), .VAR76(), .VAR45());
assign VAR64 = VAR9;
VAR1 VAR49(.din(VAR43), .clk(clk), .VAR69(VAR3), .VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR10(.din(VAR99), .clk(clk), .VAR69(VAR59), .VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR92(.din(VAR90), .clk(clk), .VAR69(VAR22), .VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR32(.din(VAR31), .clk(clk), .VAR69(VAR98), .VAR29(VAR29), .VAR76(), .VAR45());
VAR1 VAR48(.din(VAR39), .clk(clk), .VAR69(VAR57), .VAR29(VAR29), .VAR76(), .VAR45());
endmodule | gpl-2.0 |
thinkoco/de1_soc_opencl | de10_nano_sharedonly_hdmi/ip/i2c/I2C_WRITE_WDATA.v | 2,365 | module MODULE1 (
input VAR13 ,
input VAR4,
input VAR7,
input [15:0] VAR12,
input [7:0] VAR10,
input VAR14,
output reg VAR15,
output reg VAR6,
output reg VAR2,
output reg [7:0] VAR8 ,
output reg [7:0] VAR11,
output reg [7:0] VAR3,
output reg VAR9,
input [7:0] VAR5 );
reg [8:0]VAR16 ;
reg [7:0]VAR1 ;
always @( negedge VAR13 or posedge VAR4 )begin
if (!VAR13 ) VAR8 <=0;
end
else
case (VAR8)
0: begin VAR15 <=1;
VAR6 <=1;
VAR9 <=0;
VAR11 <=0;
VAR2 <=1;
VAR3 <=0;
if (VAR7) VAR8 <=30 ; end
1: begin VAR8 <=2 ;
{ VAR15, VAR6 } <= 2'b01;
VAR16 <= {VAR10 ,1'b1 }; end
2: begin VAR8 <=3 ;
{ VAR15, VAR6 } <= 2'b00;
end
3: begin
VAR8 <=4 ;
{ VAR15, VAR16 } <= { VAR16 ,1'b0 };
end
4: begin
VAR8 <=5 ;
VAR6 <= 1'b1 ;
VAR11 <= VAR11 +1 ;
end
5: begin
VAR6 <= 1'b0 ;
if (VAR11==9) begin
if ( VAR3 == VAR5 ) VAR8 <= 6 ;
end
else begin
VAR11 <=0 ;
VAR8 <= 2 ;
if ( VAR3 ==0 ) begin VAR3 <=1 ; VAR16 <= {VAR12[15:8] ,1'b1 }; end
else if ( VAR3 ==1 ) begin VAR3 <=2 ; VAR16 <= {VAR12[7:0] ,1'b1 }; end
end
if (VAR14 ) VAR9 <=1 ;
end
else VAR8 <= 2;
end
6: begin VAR8 <=7 ;
{ VAR15, VAR6 } <= 2'b00;
end
7: begin VAR8 <=8 ;
{ VAR15, VAR6 } <= 2'b01;
end
8: begin VAR8 <=9 ;
{ VAR15, VAR6 } <= 2'b11;
end
9: begin
VAR8 <= 30;
VAR15 <=1;
VAR6 <=1;
VAR11 <=0;
VAR2 <=1;
VAR3 <=0;
end
30: begin
if (!VAR7) VAR8 <=31;
end
31: begin VAR2<=0;
VAR9<=0;
VAR8 <=1;
end
endcase
end
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_sb.v | 6,640 | module MODULE1(
clk, rst,
VAR24, VAR36, VAR19, VAR29, VAR25, VAR7, VAR20,
VAR11, VAR33, VAR31,
VAR28, VAR15, VAR12, VAR27, VAR38, VAR40, VAR16,
VAR37, VAR2, VAR1
);
parameter VAR17 = VAR18;
parameter VAR10 = VAR18;
input clk; input rst;
input [VAR17-1:0] VAR24; input [VAR10-1:0] VAR36; input VAR19; input VAR29; input VAR25; input VAR20; input [3:0] VAR7; output [VAR17-1:0] VAR11; output VAR33; output VAR31;
output [VAR17-1:0] VAR28; output [VAR10-1:0] VAR15; output VAR12; output VAR27; output VAR38; output VAR16; output [3:0] VAR40; input [VAR17-1:0] VAR37; input VAR2; input VAR1;
wire [4+VAR17+VAR10-1:0] VAR22; wire [4+VAR17+VAR10-1:0] VAR5; wire VAR26;
wire VAR39;
wire VAR41;
wire VAR9;
wire VAR4;
reg VAR13;
reg VAR3;
assign VAR22 = {VAR7, VAR24, VAR36};
assign {VAR40, VAR28, VAR15} = VAR4 ? VAR5 : {VAR7, VAR24, VAR36};
assign VAR26 = VAR19 & VAR29 & VAR25 & ~VAR41 & ~VAR3;
assign VAR39 = ~VAR13;
assign VAR11 = VAR37;
assign VAR33 = VAR4 ? VAR3 : VAR2;
assign VAR31 = VAR4 ? 1'b0 : VAR1; assign VAR12 = VAR4 ? VAR13 : VAR19;
assign VAR27 = VAR4 ? VAR13 : VAR29;
assign VAR38 = VAR4 ? 1'b1 : VAR25;
assign VAR16 = VAR4 ? 1'b0 : VAR20;
assign VAR4 = ~VAR9 | (VAR9 & VAR13);
VAR35 VAR35 (
.VAR34(clk),
.VAR23(rst),
.VAR21(VAR22),
.VAR30(VAR26),
.VAR6(VAR39),
.VAR32(VAR5),
.VAR14(VAR41),
.VAR8(VAR9)
);
always @(posedge clk or posedge rst)
if (rst)
VAR13 <= 1'b0;
else if (VAR2)
VAR13 <= 1'b0;
else if (VAR4 | VAR26)
VAR13 <= 1'b1;
always @(posedge clk or posedge rst)
if (rst)
VAR3 <= 1'b0;
else if (VAR26)
VAR3 <= 1'b1;
else
VAR3 <= 1'b0;
assign VAR28 = VAR24;
assign VAR15 = VAR36;
assign VAR12 = VAR19;
assign VAR27 = VAR29;
assign VAR38 = VAR25;
assign VAR16 = VAR20;
assign VAR40 = VAR7;
assign VAR11 = VAR37;
assign VAR33 = VAR2;
assign VAR31 = VAR1;
endmodule | gpl-2.0 |
Xilinx/PYNQ | boards/ip/color_swap_1.1/color_swap.v | 1,426 | module MODULE1(
VAR10,
VAR6,
VAR5,
VAR2,
VAR1,
VAR8,
VAR3,
VAR4
);
parameter VAR7 = "VAR12";
parameter VAR13 = "VAR9";
input VAR10;
output VAR6;
input VAR3;
output VAR4;
input [23:0]VAR5;
output [23:0]VAR2;
input VAR1;
output VAR8;
wire [23:0]VAR11;
assign VAR6 = VAR10;
assign VAR4 = VAR3;
assign VAR8 = VAR1;
if (VAR7 == "VAR12")
assign VAR11[23:0] = {VAR5[23:16],VAR5[15:8],VAR5[7:0]};
else if (VAR7 == "VAR9")
assign VAR11[23:0] = {VAR5[23:16],VAR5[7:0],VAR5[15:8]};
if (VAR13 == "VAR12")
assign VAR2[23:0] = {VAR11[23:16],VAR11[15:8],VAR11[7:0]};
else if (VAR13 == "VAR9")
assign VAR2[23:0] = {VAR11[23:16],VAR11[7:0],VAR11[15:8]};
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufinv/sky130_fd_sc_hd__bufinv.symbol.v | 1,272 | module MODULE1 (
input VAR1,
output VAR2
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222o/sky130_fd_sc_ms__a222o.pp.symbol.v | 1,419 | module MODULE1 (
input VAR10 ,
input VAR7 ,
input VAR5 ,
input VAR11 ,
input VAR3 ,
input VAR9 ,
output VAR6 ,
input VAR2 ,
input VAR4,
input VAR1,
input VAR8
);
endmodule | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/picosoc_wrappers/picosoc_wrap.v | 1,405 | module MODULE1 (
input clk,
output VAR21,
input VAR8,
input [15:0] VAR3,
output [15:0] VAR2
);
wire VAR16;
VAR13 VAR18 (.VAR24(clk), .VAR7(VAR16));
reg [5:0] VAR5 = 0;
wire VAR22 = &VAR5;
always @(posedge VAR16) begin
VAR5 <= VAR5 + !VAR22;
end
wire VAR19;
reg VAR23;
wire [3:0] VAR15;
wire [31:0] VAR20;
wire [31:0] VAR4;
reg [31:0] VAR12;
reg [31:0] VAR6;
assign VAR2 = VAR6[15:0];
always @(posedge VAR16) begin
if (!VAR22) begin
VAR6 <= 0;
end else begin
VAR23 <= 0;
if (VAR19 && !VAR23 && VAR20[31:24] == 8'VAR14 03) begin
VAR23 <= 1;
VAR12 <= {VAR3, VAR6[15:0]};
if (VAR15[0]) VAR6[ 7: 0] <= VAR4[ 7: 0];
if (VAR15[1]) VAR6[15: 8] <= VAR4[15: 8];
if (VAR15[2]) VAR6[23:16] <= VAR4[23:16];
if (VAR15[3]) VAR6[31:24] <= VAR4[31:24];
end
end
end
VAR1 VAR17 (
.clk (VAR16),
.VAR22 (VAR22 ),
.VAR10 (VAR21),
.VAR26 (VAR8),
.VAR25 (1'b0 ),
.VAR11 (1'b0 ),
.VAR9 (1'b0 ),
.VAR19 (VAR19 ),
.VAR23 (VAR23 ),
.VAR15 (VAR15 ),
.VAR20 (VAR20 ),
.VAR4 (VAR4 ),
.VAR12 (VAR12 )
);
endmodule | isc |
sabertazimi/hust-lab | architecture/design/fpga/src/led_unit.v | 1,985 | module MODULE1
(
input VAR3,
input [(VAR4-1):0] VAR7,
output reg [7:0] VAR6,
output reg [7:0] VAR1
);
reg [2:0] VAR5; wire [(VAR4*2)-1:0] VAR2; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isobufsrc/sky130_fd_sc_lp__isobufsrc.functional.pp.v | 2,044 | module MODULE1 (
VAR13 ,
VAR14,
VAR9 ,
VAR4 ,
VAR2 ,
VAR6 ,
VAR15
);
output VAR13 ;
input VAR14;
input VAR9 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR15 ;
wire VAR5 ;
wire VAR12 ;
wire VAR10;
not VAR7 (VAR5 , VAR14 );
and VAR3 (VAR12 , VAR5, VAR9 );
VAR8 VAR11 (VAR10, VAR12, VAR4, VAR2, VAR14);
buf VAR1 (VAR13 , VAR10 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/alt_mem_ddrx_ecc_encoder.v | 10,443 | module MODULE1 #
( parameter
VAR25 = 40,
VAR28 = 8,
VAR11 = 0,
VAR12 = 7,
VAR10 = 7,
VAR31 = 1
)
(
VAR15,
VAR17,
VAR14,
VAR22,
VAR26,
VAR4,
VAR20,
VAR21,
VAR9
);
localparam VAR24 = (VAR25 > 8) ? (VAR25 - VAR28) : (VAR25);
input VAR15;
input VAR17;
input [VAR12 - 1 : 0] VAR14;
input [VAR10 - 1 : 0] VAR22;
input [VAR31 - 1 : 0] VAR26;
input [VAR25 - 1 : 0] VAR4;
input [VAR28 - 1 : 0] VAR20;
input VAR21;
output [VAR25 - 1 : 0] VAR9;
reg [VAR25 - 1 : 0] VAR2;
reg [VAR25 - 1 : 0] VAR8;
reg [VAR28 - 1 : 0] VAR27;
reg VAR23;
reg [VAR25 - 1 : 0] VAR1;
reg [VAR25 - 1 : 0] VAR9;
reg [VAR25 - 1 : 0] VAR7;
wire [VAR24 - 1 : 0] VAR29;
wire [VAR25 - 1 : 0] VAR16;
generate
genvar VAR19;
for (VAR19 = 0;VAR19 < VAR25;VAR19 = VAR19 + 1)
begin : VAR5
always @
begin
VAR1 = VAR16;
end
generate
if (VAR25 <= 8)
begin
always @
begin
VAR7 [VAR24 - 1 : 0] = VAR1 [VAR24 - 1 : 0];
if (VAR23)
begin
VAR7 [VAR25 - 1 : VAR24] = VAR27;
end
else
begin
VAR7 [VAR25 - 1 : VAR24] = VAR1 [VAR25 - 1 : VAR24];
end
end
end
endgenerate
always @
begin
VAR8 = VAR4;
VAR27 = VAR20;
VAR23 = VAR21;
end
end
endgenerate
generate
begin
if (VAR24 == 8 && VAR25 > 8) begin
wire [39 : 0] VAR1;
assign VAR1 [39] = 1'b0;
assign VAR16 [VAR24 - 1 : 0] = VAR1 [31 : 0];
assign VAR16 [VAR25 - 1 : VAR24] = VAR1 [39 : 32];
VAR13 #
(
.VAR11 (VAR11 )
)
VAR32
(
.clk (VAR15 ),
.VAR18 (VAR17 ),
.VAR3 ({24'd0, VAR29} ),
.VAR6 (VAR1 [38 : 0])
);
end
else if (VAR24 == 16)
begin
wire [39 : 0] VAR1;
assign VAR1 [39] = 1'b0;
assign VAR16 [VAR24 - 1 : 0] = VAR1 [31 : 0];
assign VAR16 [VAR25 - 1 : VAR24] = VAR1 [39 : 32];
VAR13 #
(
.VAR11 (VAR11 )
)
VAR32
(
.clk (VAR15 ),
.VAR18 (VAR17 ),
.VAR3 ({16'd0, VAR29} ),
.VAR6 (VAR1 [38 : 0])
);
end
else if (VAR24 == 32)
begin
assign VAR16 [39] = 1'b0;
VAR13 #
(
.VAR11 (VAR11 )
)
VAR32
(
.clk (VAR15 ),
.VAR18 (VAR17 ),
.VAR3 (VAR29 ),
.VAR6 (VAR16 [38 : 0])
);
end
else if (VAR24 == 64)
begin
VAR30 #
(
.VAR11 (VAR11)
)
VAR32
(
.clk (VAR15 ),
.VAR18 (VAR17 ),
.VAR3 (VAR29 ),
.VAR6 (VAR16 )
);
end
end
endgenerate
endmodule | lgpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/primitives.v | 7,338 | module MODULE5(VAR15,VAR13,VAR20,out);
parameter VAR1=8'b00000000;
input VAR20,VAR13,VAR15;
output reg out;
integer VAR10;
wire [2:0] VAR18;
VAR4 VAR2(VAR20 , VAR18[0]);
VAR4 VAR8(VAR13 , VAR18[1]);
VAR4 VAR11(VAR15 , VAR18[2]);
always@(VAR18[0], VAR18[1], VAR18[2])
begin
VAR10 = {VAR18[2], VAR18[1], VAR18[0]};
out = VAR1[VAR10];
end
endmodule
module MODULE4(VAR19,VAR15,VAR13,VAR20,out);
parameter VAR1=16'b0000000000000000;
input VAR20,VAR13,VAR15,VAR19;
output reg out;
integer VAR10;
wire [3:0] VAR18;
VAR4 VAR2(VAR20 , VAR18[0]);
VAR4 VAR8(VAR13 , VAR18[1]);
VAR4 VAR11(VAR15 , VAR18[2]);
VAR4 VAR12(VAR19 , VAR18[3]);
always@(VAR18[0], VAR18[1], VAR18[2], VAR18[3])
begin
VAR10 = {VAR18[3], VAR18[2], VAR18[1], VAR18[0]};
out = VAR1[VAR10];
end
endmodule
module MODULE1(VAR9,VAR19,VAR15,VAR13,VAR20,out);
parameter VAR1=32'b00000000000000000000000000000000;
input VAR20,VAR13,VAR15,VAR19,VAR9;
output reg out;
integer VAR10 = 0;
wire [4:0] VAR18;
VAR4 VAR2(VAR20 , VAR18[0]);
VAR4 VAR8(VAR13 , VAR18[1]);
VAR4 VAR11(VAR15 , VAR18[2]);
VAR4 VAR12(VAR19 , VAR18[3]);
VAR4 VAR5(VAR9 , VAR18[4]);
always@(VAR18[0], VAR18[1], VAR18[2], VAR18[3], VAR18[4])
begin
VAR10 = {VAR18[4], VAR18[3], VAR18[2], VAR18[1], VAR18[0]};
out = VAR1[VAR10];
end
endmodule
module MODULE3(VAR7,VAR9,VAR19,VAR15,VAR13,VAR20,out);
parameter VAR1=64'b0000000000000000000000000000000000000000000000000000000000000000;
input VAR20,VAR13,VAR15,VAR19,VAR9,VAR7;
output reg out;
integer VAR10;
wire [5:0] VAR18;
VAR4 VAR2(VAR20 , VAR18[0]);
VAR4 VAR8(VAR13 , VAR18[1]);
VAR4 VAR11(VAR15 , VAR18[2]);
VAR4 VAR12(VAR19 , VAR18[3]);
VAR4 VAR5(VAR9 , VAR18[4]);
VAR4 VAR14(VAR7 , VAR18[5]);
always@(VAR18[0], VAR18[1], VAR18[2], VAR18[3], VAR18[4], VAR18[5])
begin
VAR10 = {VAR18[5], VAR18[4], VAR18[3], VAR18[2], VAR18[1], VAR18[0]};
out = VAR1[VAR10];
end
endmodule
module MODULE2(VAR17,VAR7,VAR9,VAR19,VAR15,VAR13,VAR20,out);
parameter VAR1=128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
input VAR20,VAR13,VAR15,VAR19,VAR9,VAR7,VAR17;
output reg out;
integer VAR10;
wire [6:0] VAR18;
VAR4 VAR2(VAR20 , VAR18[0]);
VAR4 VAR8(VAR13 , VAR18[1]);
VAR4 VAR11(VAR15 , VAR18[2]);
VAR4 VAR12(VAR19 , VAR18[3]);
VAR4 VAR5(VAR9 , VAR18[4]);
VAR4 VAR14(VAR7 , VAR18[5]);
VAR4 VAR22(VAR17 , VAR18[6]);
always@(VAR18[0], VAR18[1], VAR18[2], VAR18[3], VAR18[4], VAR18[5], VAR18[6])
begin
VAR10 = {VAR18[6],VAR18[5],VAR18[4], VAR18[3], VAR18[2], VAR18[1], VAR18[0]};
out = VAR1[VAR10];
end
endmodule
module MODULE6(VAR21,VAR16,VAR23,VAR6,VAR3);
input VAR21,VAR16,VAR23,VAR6;
output reg VAR3 = 1'b0;
begin
begin
end
begin
begin
begin
begin
begin
begin
begin | mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_register_slice_v2_1/353278bf/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v | 18,630 | module MODULE1 #
(
parameter VAR55 = "VAR126",
parameter VAR86 = 0,
parameter integer VAR90 = 4,
parameter integer VAR12 = 32,
parameter integer VAR137 = 32,
parameter integer VAR36 = 0,
parameter integer VAR58 = 1,
parameter integer VAR143 = 1,
parameter integer VAR149 = 1,
parameter integer VAR68 = 1,
parameter integer VAR106 = 1,
parameter integer VAR131 = 0,
parameter integer VAR124 = 0,
parameter integer VAR11 = 0,
parameter integer VAR135 = 0,
parameter integer VAR32 = 0
)
(
input wire VAR42,
input wire VAR25,
input wire [VAR90-1:0] VAR132,
input wire [VAR12-1:0] VAR39,
input wire [((VAR86 == 1) ? 4 : 8)-1:0] VAR147,
input wire [3-1:0] VAR46,
input wire [2-1:0] VAR28,
input wire [((VAR86 == 1) ? 2 : 1)-1:0] VAR17,
input wire [4-1:0] VAR104,
input wire [3-1:0] VAR93,
input wire [4-1:0] VAR51,
input wire [4-1:0] VAR119,
input wire [VAR58-1:0] VAR1,
input wire VAR121,
output wire VAR81,
input wire [VAR90-1:0] VAR98,
input wire [VAR137-1:0] VAR22,
input wire [VAR137/8-1:0] VAR53,
input wire VAR66,
input wire [VAR149-1:0] VAR148,
input wire VAR107,
output wire VAR113,
output wire [VAR90-1:0] VAR37,
output wire [2-1:0] VAR57,
output wire [VAR106-1:0] VAR145,
output wire VAR129,
input wire VAR75,
input wire [VAR90-1:0] VAR120,
input wire [VAR12-1:0] VAR82,
input wire [((VAR86 == 1) ? 4 : 8)-1:0] VAR102,
input wire [3-1:0] VAR60,
input wire [2-1:0] VAR76,
input wire [((VAR86 == 1) ? 2 : 1)-1:0] VAR33,
input wire [4-1:0] VAR92,
input wire [3-1:0] VAR71,
input wire [4-1:0] VAR88,
input wire [4-1:0] VAR8,
input wire [VAR143-1:0] VAR59,
input wire VAR105,
output wire VAR48,
output wire [VAR90-1:0] VAR15,
output wire [VAR137-1:0] VAR43,
output wire [2-1:0] VAR2,
output wire VAR4,
output wire [VAR68-1:0] VAR18,
output wire VAR34,
input wire VAR41,
output wire [VAR90-1:0] VAR61,
output wire [VAR12-1:0] VAR5,
output wire [((VAR86 == 1) ? 4 : 8)-1:0] VAR111,
output wire [3-1:0] VAR118,
output wire [2-1:0] VAR97,
output wire [((VAR86 == 1) ? 2 : 1)-1:0] VAR96,
output wire [4-1:0] VAR69,
output wire [3-1:0] VAR21,
output wire [4-1:0] VAR110,
output wire [4-1:0] VAR89,
output wire [VAR58-1:0] VAR72,
output wire VAR78,
input wire VAR125,
output wire [VAR90-1:0] VAR65,
output wire [VAR137-1:0] VAR27,
output wire [VAR137/8-1:0] VAR31,
output wire VAR47,
output wire [VAR149-1:0] VAR112,
output wire VAR14,
input wire VAR95,
input wire [VAR90-1:0] VAR50,
input wire [2-1:0] VAR9,
input wire [VAR106-1:0] VAR73,
input wire VAR19,
output wire VAR80,
output wire [VAR90-1:0] VAR26,
output wire [VAR12-1:0] VAR109,
output wire [((VAR86 == 1) ? 4 : 8)-1:0] VAR63,
output wire [3-1:0] VAR67,
output wire [2-1:0] VAR128,
output wire [((VAR86 == 1) ? 2 : 1)-1:0] VAR127,
output wire [4-1:0] VAR70,
output wire [3-1:0] VAR115,
output wire [4-1:0] VAR87,
output wire [4-1:0] VAR140,
output wire [VAR143-1:0] VAR144,
output wire VAR13,
input wire VAR7,
input wire [VAR90-1:0] VAR94,
input wire [VAR137-1:0] VAR38,
input wire [2-1:0] VAR6,
input wire VAR84,
input wire [VAR68-1:0] VAR74,
input wire VAR24,
output wire VAR138
);
wire reset;
localparam VAR114 = (VAR86 == 0) ? 1 : 0;
wire [VAR116-1:0] VAR130;
wire [VAR116-1:0] VAR20;
wire [VAR85-1:0] VAR141;
wire [VAR85-1:0] VAR54;
wire [VAR30-1:0] VAR146;
wire [VAR30-1:0] VAR150;
wire [VAR40-1:0] VAR101;
wire [VAR40-1:0] VAR136;
wire [VAR3-1:0] VAR91;
wire [VAR3-1:0] VAR23;
assign reset = ~VAR25;
VAR49 #(
.VAR86 ( VAR86 ) ,
.VAR90 ( VAR90 ) ,
.VAR12 ( VAR12 ) ,
.VAR137 ( VAR137 ) ,
.VAR36 ( VAR36 ) ,
.VAR114 ( VAR114 ) ,
.VAR58 ( VAR58 ) ,
.VAR143 ( VAR143 ) ,
.VAR149 ( VAR149 ) ,
.VAR68 ( VAR68 ) ,
.VAR106 ( VAR106 ) ,
.VAR16 ( VAR116 ) ,
.VAR79 ( VAR85 ) ,
.VAR133 ( VAR30 ) ,
.VAR62 ( VAR40 ) ,
.VAR64 ( VAR3 )
)
VAR108 (
.VAR132 ( VAR132 ) ,
.VAR39 ( VAR39 ) ,
.VAR147 ( VAR147 ) ,
.VAR46 ( VAR46 ) ,
.VAR28 ( VAR28 ) ,
.VAR17 ( VAR17 ) ,
.VAR104 ( VAR104 ) ,
.VAR93 ( VAR93 ) ,
.VAR119 ( VAR119 ) ,
.VAR1 ( VAR1 ) ,
.VAR51 ( VAR51 ) ,
.VAR98 ( VAR98 ) ,
.VAR22 ( VAR22 ) ,
.VAR53 ( VAR53 ) ,
.VAR66 ( VAR66 ) ,
.VAR148 ( VAR148 ) ,
.VAR37 ( VAR37 ) ,
.VAR57 ( VAR57 ) ,
.VAR145 ( VAR145 ) ,
.VAR120 ( VAR120 ) ,
.VAR82 ( VAR82 ) ,
.VAR102 ( VAR102 ) ,
.VAR60 ( VAR60 ) ,
.VAR76 ( VAR76 ) ,
.VAR33 ( VAR33 ) ,
.VAR92 ( VAR92 ) ,
.VAR71 ( VAR71 ) ,
.VAR8 ( VAR8 ) ,
.VAR59 ( VAR59 ) ,
.VAR88 ( VAR88 ) ,
.VAR15 ( VAR15 ) ,
.VAR43 ( VAR43 ) ,
.VAR2 ( VAR2 ) ,
.VAR4 ( VAR4 ) ,
.VAR18 ( VAR18 ) ,
.VAR130 ( VAR130 ) ,
.VAR141 ( VAR141 ) ,
.VAR146 ( VAR146 ) ,
.VAR101 ( VAR101 ) ,
.VAR91 ( VAR91 )
);
VAR83 # (
.VAR55 ( VAR55 ) ,
.VAR45 ( VAR116 ) ,
.VAR44 ( VAR131 )
)
VAR29 (
.VAR123(VAR42),
.VAR122(reset),
.VAR139(VAR130),
.VAR35(VAR121),
.VAR77(VAR81),
.VAR100(VAR20),
.VAR103(VAR78),
.VAR10(VAR125)
);
VAR83 # (
.VAR55 ( VAR55 ) ,
.VAR45 ( VAR85 ) ,
.VAR44 ( VAR124 )
)
VAR56 (
.VAR123(VAR42),
.VAR122(reset),
.VAR139(VAR141),
.VAR35(VAR107),
.VAR77(VAR113),
.VAR100(VAR54),
.VAR103(VAR14),
.VAR10(VAR95)
);
VAR83 # (
.VAR55 ( VAR55 ) ,
.VAR45 ( VAR30 ) ,
.VAR44 ( VAR11 )
)
VAR134 (
.VAR123(VAR42),
.VAR122(reset),
.VAR139(VAR150),
.VAR35(VAR19),
.VAR77(VAR80),
.VAR100(VAR146),
.VAR103(VAR129),
.VAR10(VAR75)
);
VAR83 # (
.VAR55 ( VAR55 ) ,
.VAR45 ( VAR40 ) ,
.VAR44 ( VAR135 )
)
VAR99 (
.VAR123(VAR42),
.VAR122(reset),
.VAR139(VAR101),
.VAR35(VAR105),
.VAR77(VAR48),
.VAR100(VAR136),
.VAR103(VAR13),
.VAR10(VAR7)
);
VAR83 # (
.VAR55 ( VAR55 ) ,
.VAR45 ( VAR3 ) ,
.VAR44 ( VAR32 )
)
VAR142 (
.VAR123(VAR42),
.VAR122(reset),
.VAR139(VAR23),
.VAR35(VAR24),
.VAR77(VAR138),
.VAR100(VAR91),
.VAR103(VAR34),
.VAR10(VAR41)
);
VAR117 #(
.VAR86 ( VAR86 ) ,
.VAR90 ( VAR90 ) ,
.VAR12 ( VAR12 ) ,
.VAR137 ( VAR137 ) ,
.VAR36 ( VAR36 ) ,
.VAR114 ( VAR114 ) ,
.VAR58 ( VAR58 ) ,
.VAR143 ( VAR143 ) ,
.VAR149 ( VAR149 ) ,
.VAR68 ( VAR68 ) ,
.VAR106 ( VAR106 ) ,
.VAR16 ( VAR116 ) ,
.VAR79 ( VAR85 ) ,
.VAR133 ( VAR30 ) ,
.VAR62 ( VAR40 ) ,
.VAR64 ( VAR3 )
)
VAR52 (
.VAR20 ( VAR20 ) ,
.VAR54 ( VAR54 ) ,
.VAR150 ( VAR150 ) ,
.VAR136 ( VAR136 ) ,
.VAR23 ( VAR23 ) ,
.VAR61 ( VAR61 ) ,
.VAR5 ( VAR5 ) ,
.VAR111 ( VAR111 ) ,
.VAR118 ( VAR118 ) ,
.VAR97 ( VAR97 ) ,
.VAR96 ( VAR96 ) ,
.VAR69 ( VAR69 ) ,
.VAR21 ( VAR21 ) ,
.VAR89 ( VAR89 ) ,
.VAR72 ( VAR72 ) ,
.VAR110 ( VAR110 ) ,
.VAR65 ( VAR65 ) ,
.VAR27 ( VAR27 ) ,
.VAR31 ( VAR31 ) ,
.VAR47 ( VAR47 ) ,
.VAR112 ( VAR112 ) ,
.VAR50 ( VAR50 ) ,
.VAR9 ( VAR9 ) ,
.VAR73 ( VAR73 ) ,
.VAR26 ( VAR26 ) ,
.VAR109 ( VAR109 ) ,
.VAR63 ( VAR63 ) ,
.VAR67 ( VAR67 ) ,
.VAR128 ( VAR128 ) ,
.VAR127 ( VAR127 ) ,
.VAR70 ( VAR70 ) ,
.VAR115 ( VAR115 ) ,
.VAR140 ( VAR140 ) ,
.VAR144 ( VAR144 ) ,
.VAR87 ( VAR87 ) ,
.VAR94 ( VAR94 ) ,
.VAR38 ( VAR38 ) ,
.VAR6 ( VAR6 ) ,
.VAR84 ( VAR84 ) ,
.VAR74 ( VAR74 )
);
endmodule | mit |
peteasa/parallella-fpga | AdaptevaLib/ip_repo/axi_traffic_controller_1.0/hdl/axi_traffic_controller_v1_0_M_AXI.v | 49,083 | module MODULE1 #
(
parameter VAR51 = "VAR16",
parameter VAR28 = "VAR13",
parameter VAR61 = "VAR7",
parameter VAR65 = "VAR3",
parameter VAR42 = 32'hAA000000,
parameter VAR26 = 32'h40000000,
parameter integer VAR62 = 32,
parameter integer VAR41 = 32,
parameter integer VAR46 = 4
)
(
input wire VAR29,
output reg VAR74,
output wire VAR52,
input wire VAR50,
input wire VAR30,
output wire [VAR62-1 : 0] VAR17,
output wire [2 : 0] VAR37,
output wire VAR10,
input wire VAR56,
output wire [VAR41-1 : 0] VAR72,
output wire [VAR41/8-1 : 0] VAR81,
output wire VAR76,
input wire VAR2,
input wire [1 : 0] VAR60,
input wire VAR53,
output wire VAR54,
output wire [VAR62-1 : 0] VAR44,
output wire [2 : 0] VAR34,
output wire VAR14,
input wire VAR64,
input wire [VAR41-1 : 0] VAR20,
input wire [1 : 0] VAR15,
input wire VAR69,
output wire VAR38
);
function integer VAR49 (input integer VAR23);
begin
for(VAR49=0; VAR23>0; VAR49=VAR49+1)
VAR23 = VAR23 >> 1;
end
endfunction
localparam integer VAR70 = VAR49(VAR46-1);
parameter [1:0] VAR9 = 2'b00, VAR75 = 2'b01, VAR78 = 2'b10, VAR1 = 2'b11;
reg [1:0] VAR59;
reg VAR77;
reg VAR6;
reg VAR31;
reg VAR43;
reg VAR22;
reg [VAR62-1 : 0] VAR68;
reg [VAR41-1 : 0] VAR47;
reg [VAR62-1 : 0] VAR80;
wire VAR32;
wire VAR11;
reg VAR24;
reg VAR71;
reg VAR12;
reg VAR40;
reg VAR36;
reg VAR79;
reg VAR63;
reg [VAR70 : 0] VAR39;
reg [VAR70 : 0] VAR33;
reg [VAR41-1 : 0] VAR58;
reg VAR57;
reg VAR35;
reg VAR27;
reg VAR8;
reg VAR19;
reg VAR21;
reg VAR18;
wire VAR55;
reg [31:0]VAR73;
reg [31:0]VAR48;
reg [31:0]VAR66;
reg [31:0]VAR67;
reg VAR5;
reg VAR82;
reg VAR45;
wire VAR25;
reg [31:0] VAR4;
assign VAR25 = (VAR59 == VAR1);
begin
begin
begin
end
begin
begin
begin
end
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
end
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
end
begin
end
begin
end
begin
end
begin
end
begin
end
begin
begin
begin | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi.functional.pp.v | 1,971 | module MODULE1 (
VAR10,
VAR1,
VAR12 ,
VAR15 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR7
);
input VAR10;
input VAR1;
output VAR12 ;
input VAR15 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR7 ;
wire VAR4 VAR3 ;
wire VAR8 ;
wire VAR11;
and VAR13 (VAR3 , VAR15, VAR5, VAR2, VAR4 );
nor VAR16 (VAR8 , VAR7, VAR3 );
VAR14 VAR9 (VAR11, VAR8, VAR10, VAR1);
buf VAR6 (VAR12 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4.blackbox.v | 1,339 | module MODULE1 (
VAR2 ,
VAR7,
VAR8,
VAR10,
VAR5,
VAR4,
VAR3
);
output VAR2 ;
input VAR7;
input VAR8;
input VAR10;
input VAR5;
input VAR4;
input VAR3;
supply1 VAR6;
supply0 VAR11;
supply1 VAR9 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb.pp.blackbox.v | 1,263 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR1,
VAR4,
VAR5 ,
VAR6
);
output VAR3 ;
output VAR2 ;
input VAR1;
input VAR4;
input VAR5 ;
input VAR6 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/ddr1_top.v | 16,045 | module MODULE1 (
VAR29,
VAR121,
VAR104,
VAR108,
VAR46,
VAR79,
VAR71,
VAR56,
VAR16,
VAR60,
VAR37,
VAR97,
VAR52,
VAR14,
VAR39,
VAR32,
VAR77,
VAR119,
VAR67,
VAR1,
VAR102,
VAR66,
VAR47,
VAR100,
VAR4,
VAR112,
VAR103,
VAR18,
VAR10,
VAR33,
VAR9,
VAR55,
VAR83,
VAR78,
VAR23,
VAR12,
VAR6,
VAR88,
VAR107,
VAR13,
VAR96,
VAR57,
VAR80,
VAR2,
VAR91,
VAR82,
VAR19,
VAR118,
VAR44,
VAR5,
VAR120,
VAR69,
VAR61,
VAR63,
VAR43);
input VAR29;
input VAR121;
input VAR104;
input VAR108;
input VAR46;
input VAR56;
input [143:0] VAR16;
input [21:0] VAR97;
input [1:0] VAR52;
input [9:0] VAR14;
input [2:0] VAR39;
input VAR77;
input [143:0] VAR119;
input VAR67;
inout [8:0] VAR66;
inout [71:0] VAR47;
output VAR100;
output VAR4;
output VAR112;
output VAR103;
output VAR18;
output [8:0] VAR10;
output [1:0] VAR33;
output [12:0] VAR9;
output VAR55;
output VAR83;
output VAR78;
output VAR23;
output VAR12;
output VAR6;
output VAR88;
output VAR107;
output VAR13;
output VAR96;
output VAR57;
output VAR80;
output VAR2;
output VAR91;
output VAR82;
output VAR19;
output [7:0] VAR118;
output [7:0] VAR44;
output VAR5;
output VAR120;
output VAR69;
output VAR61;
output VAR63;
output VAR43;
output VAR79;
output VAR71;
output [143:0] VAR60;
output VAR37;
output VAR32;
output VAR1;
output VAR102;
wire VAR17;
wire VAR115;
wire [4:0] VAR89;
wire VAR98;
wire VAR22;
wire VAR24;
wire VAR40;
wire VAR106;
wire VAR72;
wire [7:0] VAR26;
wire [7:0] VAR109;
wire VAR90;
wire VAR31;
wire VAR58;
wire VAR68;
wire VAR85;
wire VAR41;
wire VAR95;
wire VAR53;
wire VAR59;
wire VAR76;
wire VAR11;
wire VAR110;
wire VAR111;
wire VAR64;
wire [71:0] VAR3;
wire VAR75;
wire VAR54;
wire VAR30;
wire VAR114;
wire [8:0] VAR28;
wire [8:0] VAR38;
wire [71:0] VAR113;
wire [71:0] VAR93;
wire VAR86;
wire VAR84;
wire VAR25;
wire [1:0] VAR116;
wire [12:0] VAR45;
wire VAR8;
wire VAR101;
wire VAR81;
wire VAR122;
assign VAR69 = VAR98;
assign VAR61 = VAR22;
assign VAR63 = VAR24;
assign VAR43 = VAR40;
assign VAR5 = VAR106;
assign VAR120 = VAR72;
VAR49 VAR34 (
.VAR104 ( VAR104),
.clk ( VAR106),
.VAR62 ( VAR98),
.VAR35 ( VAR24),
.address ( VAR97),
.VAR99 ( VAR52),
.VAR65 ( VAR14),
.VAR27 ( VAR39),
.VAR77 ( VAR77),
.VAR86 ( VAR86),
.VAR84 ( VAR84),
.VAR25 ( VAR25),
.VAR116 ( VAR116),
.VAR45 ( VAR45),
.VAR8 ( VAR8),
.VAR101 ( VAR101),
.VAR68 ( VAR68),
.VAR85 ( VAR85),
.VAR90 ( VAR90),
.VAR115 ( VAR115),
.VAR81 ( VAR81),
.VAR122 ( VAR122),
.VAR42 ( VAR32),
.VAR7 ( VAR1),
.VAR102 ( VAR102)
);
VAR105 VAR20 (
.VAR16 ( VAR16),
.clk ( VAR106),
.VAR51 ( VAR72),
.reset ( VAR98),
.VAR48 ( VAR22),
.VAR92 ( VAR24),
.VAR87 ( VAR40),
.VAR90 ( VAR90),
.VAR108 ( VAR31),
.VAR46 ( VAR58),
.VAR89 ( VAR89),
.VAR41 ( VAR41),
.VAR95 ( VAR95),
.VAR53 ( VAR53),
.VAR59 ( VAR59),
.VAR76 ( VAR76),
.VAR11 ( VAR11),
.VAR110 ( VAR110),
.VAR111 ( VAR111),
.VAR64 ( VAR64),
.VAR3 ( VAR3),
.VAR75 ( VAR37),
.VAR60 ( VAR60),
.VAR54 ( VAR54),
.VAR30 ( VAR30),
.VAR21 ( VAR114),
.VAR28 ( VAR28),
.VAR38 ( VAR38),
.VAR113 ( VAR113),
.VAR93 ( VAR93)
);
VAR15 VAR70
(
.VAR56 ( VAR56),
.VAR17 ( VAR17),
.VAR119 ( VAR119),
.VAR67 ( VAR67),
.VAR94 ( VAR115),
.VAR50 ( VAR89),
.VAR69 ( VAR98),
.VAR61 ( VAR22),
.VAR63 ( VAR24),
.VAR43 ( VAR40),
.VAR5 ( VAR106),
.VAR120 ( VAR72),
.VAR26 ( VAR26),
.VAR109 ( VAR109 )
);
VAR36 VAR74
(
.VAR29 ( VAR29),
.VAR121 ( VAR121),
.clk ( VAR106),
.VAR51 ( VAR72),
.VAR26 ( VAR26),
.VAR109 ( VAR109),
.VAR86 ( VAR86),
.VAR84 ( VAR84),
.VAR25 ( VAR25),
.VAR8 ( VAR8),
.VAR101 ( VAR101),
.VAR45 ( VAR45),
.VAR116 ( VAR116),
.VAR81 ( VAR81),
.VAR122 ( VAR122),
.VAR85 ( VAR85),
.VAR68 ( VAR68),
.VAR66 ( VAR66),
.VAR47 ( VAR47),
.VAR113 ( VAR113),
.VAR93 ( VAR93),
.VAR54 ( VAR54),
.VAR30 ( VAR30),
.VAR114 ( VAR114),
.VAR28 ( VAR28),
.VAR38 ( VAR38),
.VAR17 ( VAR17),
.VAR55 ( VAR55),
.VAR83 ( VAR83),
.VAR78 ( VAR78),
.VAR23 ( VAR23),
.VAR12 ( VAR12),
.VAR6 ( VAR6),
.VAR88 ( VAR88),
.VAR107 ( VAR107),
.VAR13 ( VAR13),
.VAR96 ( VAR96),
.VAR57 ( VAR57),
.VAR80 ( VAR80),
.VAR2 ( VAR2),
.VAR91 ( VAR91),
.VAR82 ( VAR82),
.VAR19 ( VAR19),
.VAR118 ( VAR118),
.VAR44 ( VAR44),
.VAR112 ( VAR112),
.VAR103 ( VAR103),
.VAR18 ( VAR18),
.VAR33 ( VAR33),
.VAR9 ( VAR9),
.VAR100 ( VAR100),
.VAR4 ( VAR4),
.VAR117 ( VAR31),
.VAR73 ( VAR58),
.VAR108 ( VAR108),
.VAR46 ( VAR46),
.VAR79 ( VAR79),
.VAR71 ( VAR71),
.VAR41 ( VAR41),
.VAR95 ( VAR95),
.VAR53 ( VAR53),
.VAR59 ( VAR59),
.VAR76 ( VAR76),
.VAR11 ( VAR11),
.VAR110 ( VAR110),
.VAR111 ( VAR111),
.VAR64 ( VAR64),
.VAR3 ( VAR3),
.VAR10 ( VAR10)
);
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4.pp.blackbox.v | 1,347 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR9 ,
VAR2,
VAR7,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR9 ;
input VAR2;
input VAR7;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_registers.v | 19,073 | module MODULE1
parameter VAR19 = 0 ,
parameter VAR47 = 0 ,
parameter VAR123 = 32,
parameter VAR158 = 1 ,
parameter VAR21 = 32,
parameter VAR80 = 1 ,
parameter VAR26 = 1 ,
parameter VAR84 = 0 ,
parameter VAR3 = 0 , parameter VAR153 = 0 , parameter VAR122 = 0 ,
parameter VAR112 = 0 ,
parameter VAR57 = 0 ,
parameter VAR105 = 0
) (
input VAR88 ,
input VAR31 ,
input VAR51 ,
input VAR16 ,
input [15:0] VAR50 ,
input [31:0] VAR10 ,
input [9:0] VAR142 ,
input [9:0] VAR2 ,
input VAR160 ,
input VAR8 ,
input VAR13 ,
input [15:0] VAR110 ,
input [15:0] VAR114 ,
output [31:0] VAR5 ,
input [71:0] VAR162 ,
input [71:0] VAR45 ,
input [71:0] VAR75 ,
input VAR78 ,
input VAR83 ,
input VAR91 ,
input VAR67 ,
input VAR53 ,
input VAR148 ,
input VAR166 ,
input VAR36 ,
output VAR144 ,
output VAR9 ,
output VAR66 ,
output VAR55 ,
output reg [9:0] VAR129 ,
output VAR130 ,
output VAR81,
output reg VAR48 ,
output reg VAR28 ,
output reg VAR70 ,
output reg [9:0] VAR92 ,
output VAR87 ,
output VAR52 ,
output [9:0] VAR62 ,
output [9:0] VAR97 ,
output [7:0] VAR6
);
reg [31:0] VAR164 ;
reg [31:0] VAR38 ;
reg [31:0] VAR161 ;
reg [31:0] VAR96 ;
reg [31:0] VAR90 ;
reg [31:0] VAR106;
reg [31:0] VAR124;
reg VAR131 ;
reg VAR65 ;
wire VAR134;
wire VAR37;
reg VAR109;
reg VAR139;
always @(posedge VAR88) begin
VAR109 <= (VAR31) ? VAR51 : 1'b0;
VAR139 <= (VAR31) ? VAR16 : 1'b0;
end
assign VAR134 = ~VAR109 & VAR51;
assign VAR37 = ~VAR139 & VAR16 ;
wire VAR135;
wire VAR15; wire VAR163; wire VAR98;
assign VAR98 = (VAR3 == 1 & VAR153 == 1 ) ? 1'b1 :
(VAR153 == 0 & VAR70 == 1'b1) ? 1'b1 :1'b0;
wire VAR152;
reg VAR167;
reg VAR34;
reg VAR155;
reg VAR22;
reg VAR68;
reg VAR17;
always @(posedge VAR88) begin
if(VAR31 == 1'b0 ) begin
VAR68 <= 1'b0;
VAR17 <= 1'b0;
end else if(VAR3 == 1 & VAR153 == 1)begin
VAR68 <= 1'b1;
VAR17 <= VAR68;
end
end
wire VAR77;
assign VAR77 = ~VAR17 & VAR68;
wire VAR143;
assign VAR143 = (VAR50[0] & VAR10[20] ) | (VAR134);assign VAR15 = (VAR50[0] & VAR10[19] ) | (VAR134 &(VAR3 == 1 & VAR153 == 1) );
assign VAR163 = (VAR50[0] & ~VAR10[19]) | (VAR37 );
reg [9:0] VAR30;
reg [9:0] VAR138;
wire [9:0] VAR25 = (VAR50[0]) ? VAR10[9:0] : VAR30;
wire [9:0] VAR85 = (VAR50[0]) ? VAR10[19:10] : VAR138;
assign VAR62 = VAR142[9:0];
assign VAR97 = VAR2[9:0];
assign VAR135 = VAR160 && VAR8;
wire VAR58 = (VAR143) ? 1'b1 :
(VAR135) ? 1'b0 : VAR48;
wire VAR94 = (VAR15) ? 1'b1 :
(VAR163) ? 1'b0 :
VAR70;
wire [31:0] VAR73 = (VAR50[1]) ? VAR10[31:0] :
VAR164[31:0];
wire [31:0] VAR137 = (VAR50[2]) ?
~VAR10[31:0] & VAR38[31:0] :
VAR38[31:0];
wire [31:0] VAR147 = (VAR50[3]) ? VAR10[31:0] :
VAR161[31:0];
wire [31:0] VAR128 = (VAR50[4]) ? VAR10[31:0] :
VAR96[31:0];
wire [31:0] VAR44 = (VAR50[9]) ? VAR10[31:0] :
VAR90[31:0];
wire [31:0] VAR79 = (VAR50[10]) ? VAR10[31:0] :
VAR106[31:0];
wire [31:0] VAR126 = (VAR50[11]) ? VAR10[31:0] :
VAR124[31:0];
wire [31:0] VAR40 = { ~VAR13 && VAR137[31],
VAR137[30:0] };
wire [31:16] VAR1;
wire [31:0] VAR11 = (VAR143 == 1'b1) ? (32'h0):
(VAR40[31:0] | (VAR161[31:0] & { VAR1[31:16], VAR110[15:0] }));
wire VAR59 = VAR48 && VAR131;
wire VAR7 = VAR48 && VAR65;
always @(posedge VAR88) begin
VAR48 <= (VAR31) ? VAR58 : 1'b0;
VAR131 <= (VAR31) ? VAR48 : 1'b0;
VAR65 <= (VAR31) ? VAR59 : 1'b0;
VAR28 <= (VAR31) ? VAR7 : 1'b0;
VAR164[31:0] <= (VAR31) ? VAR73[31:0] : 32'h0;
VAR38[31:0] <= (VAR31) ? VAR11[31:0] : 32'h0;
VAR161[31:0] <= (VAR31) ? VAR147[31:0] : 32'h80000000;
VAR96[31:0] <= (VAR31) ? VAR128[31:0] : 32'h0;
VAR90[31:0] <= (VAR31) ? VAR44[31:0] : 32'h0;
VAR106[31:0] <= (VAR31) ? VAR79[31:0] : 32'h0;
VAR124[31:0] <= (VAR31) ? VAR126[31:0] : 32'h0;
VAR30[9:0] <= (VAR31) ? VAR25[9:0] : 10'h0;
VAR138[9:0] <= (VAR31) ? VAR85[9:0] : 10'h0;
VAR70 <= (VAR31) ? VAR94 : 1'b0;
end
always @(posedge VAR88) begin
if(VAR31 == 1'b0 ) begin
VAR129[9:0] <= 10'h0 ;
VAR92[9:0] <= 10'h0 ;
end else if(VAR135 == 1'b1) begin
VAR129[9:0] <= 10'h0 ;
VAR92[9:0] <= 10'h0 ;
end else begin
VAR129[9:0] <= VAR97[9:0] ;
VAR92[9:0] <= VAR62[9:0] ;
end
end
assign VAR6 = VAR12; wire VAR116 = (VAR123 == 64);
wire VAR136 = (VAR21 == 64);
wire [3:0] VAR149 = VAR26;
wire VAR63 = (VAR158 != 0);
wire VAR133 = (VAR19 != 0);
wire VAR74 = (VAR47 != 0);
wire VAR72 = 1'b0;
wire [1:0] VAR71 = 2'b00;
wire [2:0] VAR113 = VAR80-1'b1;
wire [31:0] VAR4 = { VAR6[7:0], VAR113[2:0], VAR48, VAR70,19'h0 }; wire [31:0] VAR102 = { 12'h0, VAR164[19:0] };
wire [31:0] VAR27 = VAR38[31:0];
wire [31:0] VAR121 = VAR161[31:0];
wire [31:0] VAR56 = { 16'h0, VAR96[15:0] };
wire VAR49 = 1'b0;
wire [2:0] VAR14;
wire [2:0] VAR154;
generate if(VAR21 == 32) begin : VAR151
assign VAR154 = 3'b000;
end
endgenerate
generate if(VAR21 == 64) begin : VAR76
assign VAR154 = 3'b001;
end
endgenerate
generate if(VAR123 == 32) begin : VAR86
assign VAR14 = 3'b000;
end
endgenerate
generate if(VAR123 == 64) begin : VAR159
assign VAR14 = 3'b001;
end
endgenerate
generate if(VAR123 == 128) begin : VAR107
assign VAR14 = 3'b010;
end
endgenerate
generate if(VAR123 == 256) begin : VAR20
assign VAR14 = 3'b011;
end
endgenerate
generate if(VAR123 == 512) begin : VAR95
assign VAR14 = 3'b100;
end
endgenerate
wire VAR127 = (VAR84 == 1 );
wire VAR82 = (VAR122 == 1 );
wire VAR168 = (VAR112 == 1 );
wire VAR61 = (VAR57 == 1 );
wire VAR146 = (VAR105 == 1 );
wire VAR103 = ~VAR127 && ~VAR82 && ~VAR168 && ~VAR61 && ~VAR146;
wire [31:0] VAR150 = { VAR49 , VAR14 , VAR154 , VAR103 , VAR127 , VAR82 , VAR168 , VAR61 , VAR146, {19 {VAR49}}
};
wire [31:0] VAR125 = { 32'h0 };
wire [31:0] VAR43 = 32'h0;
wire [31:0] VAR141 = 32'h0;
wire [31:0] VAR100 = 32'h0;
wire [31:0] VAR46 = 32'h0;
assign VAR5 =
((VAR114[0]) ? VAR4[31:0] : 32'h0) |
((VAR114[1]) ? VAR102[31:0] : 32'h0) |
((VAR114[2]) ? VAR27[31:0] : 32'h0) |
((VAR114[3]) ? VAR121[31:0] : 32'h0) |
((VAR114[4]) ? VAR56[31:0] : 32'h0) |
((VAR114[5]) ? VAR150[31:0] : 32'h0) |
((VAR114[6]) ? VAR27[31:0] : 32'h0) |
((VAR114[7]) ? VAR125[31:0] : 32'h0) |
((VAR114[8]) ? VAR43[31:0] : 32'h0) |
((VAR114[9]) ? VAR141[31:0] : 32'h0) |
((VAR114[10]) ? VAR100[31:0] : 32'h0) |
((VAR114[11]) ? VAR46[31:0] : 32'h0);
wire [1:0] VAR119 = VAR164[1:0];
wire [1:0] VAR140 = VAR164[3:2];
wire [1:0] VAR39 = VAR164[5:4];
wire [1:0] VAR33 = VAR164[7:6];
wire [1:0] VAR118 = VAR164[9:8];
wire [1:0] VAR108 = VAR164[11:10];
wire [1:0] VAR156 = VAR164[13:12];
wire VAR18 = VAR164[15];
assign VAR55 = VAR164[16];
assign VAR9 = VAR164[17];
assign VAR144 = VAR164[18];
assign VAR66 = VAR164[19];
wire [1:0] VAR99 = VAR96[1:0];
wire [1:0] VAR93 = VAR96[3:2];
wire [1:0] VAR35 = VAR96[5:4];
wire [1:0] VAR89 = VAR96[7:6];
wire [1:0] VAR120 = VAR96[9:8];
wire VAR32 = VAR96[15];
wire [3:0] VAR165;
assign VAR165 = 0;
VAR24
.VAR132 (1 ),
.VAR29 (1 ),
.VAR41(VAR23),
.VAR145 (1 )
)
VAR104
(
.din (VAR58 ),
.dout (VAR81),
.VAR111 (VAR130 ),
.VAR54 (1'b0 ),
.VAR101 ( ),
.VAR69 ( ),
.VAR42 ( ),
.VAR64 ( ),
.clk (VAR88 ),
.reset (~VAR31 )
);
wire VAR60 = VAR18 && (VAR38[15:0] != 16'h0);
wire VAR157 = VAR32 && (VAR38[30:16] != 15'h0);
wire VAR115 = VAR60 || VAR157;
reg VAR117;
always @(posedge VAR88) begin
VAR117 <= (VAR31) ? VAR115 : 1'b0;
end
assign VAR87 = VAR117;
assign VAR52 = VAR38[31];
assign VAR1[31:16] = { VAR135, 7'h0,
3'b000, VAR148,
VAR67, VAR53,
VAR166, VAR36 };
endmodule | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_p_src_cols_V_2_loc_channel.v | 3,043 | module MODULE2 (
clk,
VAR12,
VAR1,
VAR4,
VAR20);
parameter VAR9 = 32'd12;
parameter VAR6 = 32'd2;
parameter VAR10 = 32'd3;
input clk;
input [VAR9-1:0] VAR12;
input VAR1;
input [VAR6-1:0] VAR4;
output [VAR9-1:0] VAR20;
reg[VAR9-1:0] VAR3 [0:VAR10-1];
integer VAR5;
always @ (posedge clk)
begin
if (VAR1)
begin
for (VAR5=0;VAR5<VAR10-1;VAR5=VAR5+1)
VAR3[VAR5+1] <= VAR3[VAR5];
VAR3[0] <= VAR12;
end
end
assign VAR20 = VAR3[VAR4];
endmodule
module MODULE1 (
clk,
reset,
VAR7,
VAR26,
VAR2,
VAR18,
VAR13,
VAR17,
VAR16,
VAR14);
parameter VAR27 = "VAR21";
parameter VAR9 = 32'd12;
parameter VAR6 = 32'd2;
parameter VAR10 = 32'd3;
input clk;
input reset;
output VAR7;
input VAR26;
input VAR2;
output[VAR9 - 1:0] VAR18;
output VAR13;
input VAR17;
input VAR16;
input[VAR9 - 1:0] VAR14;
wire[VAR6 - 1:0] VAR25 ;
wire[VAR9 - 1:0] VAR11, VAR19;
reg[VAR6:0] VAR24 = {(VAR6+1){1'b1}};
reg VAR22 = 0, VAR15 = 1;
assign VAR7 = VAR22;
assign VAR13 = VAR15;
assign VAR11 = VAR14;
assign VAR18 = VAR19;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
VAR24 <= ~{VAR6+1{1'b0}};
VAR22 <= 1'b0;
VAR15 <= 1'b1;
end
else begin
if (((VAR2 & VAR26) == 1 & VAR22 == 1) &&
((VAR16 & VAR17) == 0 | VAR15 == 0))
begin
VAR24 <= VAR24 -1;
if (VAR24 == 0)
VAR22 <= 1'b0;
VAR15 <= 1'b1;
end
else if (((VAR2 & VAR26) == 0 | VAR22 == 0) &&
((VAR16 & VAR17) == 1 & VAR15 == 1))
begin
VAR24 <= VAR24 +1;
VAR22 <= 1'b1;
if (VAR24 == VAR10-2)
VAR15 <= 1'b0;
end
end
end
assign VAR25 = VAR24[VAR6] == 1'b0 ? VAR24[VAR6-1:0]:{VAR6{1'b0}};
assign VAR8 = (VAR16 & VAR17) & VAR15;
MODULE2
.VAR9(VAR9),
.VAR6(VAR6),
.VAR10(VAR10))
VAR23 (
.clk(clk),
.VAR12(VAR11),
.VAR1(VAR8),
.VAR4(VAR25),
.VAR20(VAR19));
endmodule | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/sync_pulse_synchronizer.v | 2,153 | module MODULE1 (
VAR9, VAR13,
VAR7, VAR6, VAR19, VAR12, VAR1
);
output VAR9;
output VAR13;
input VAR7;
input VAR6;
input VAR19;
input VAR12;
input VAR1;
wire VAR17;
wire VAR10;
wire VAR11;
VAR3 VAR15 (
.VAR2 (VAR17),
.VAR13 (VAR10),
.VAR4 (VAR6),
.VAR16 (VAR7),
.VAR1 (VAR1),
.VAR18 (VAR12)
);
VAR8 VAR14 (
.VAR13 (VAR11),
.VAR18 (VAR10),
.VAR4 (VAR6)
);
VAR3 VAR5 (
.VAR2 (VAR9),
.VAR13 (VAR13),
.VAR4 (VAR19),
.VAR16 (VAR17),
.VAR1 (VAR1),
.VAR18 (VAR11)
);
endmodule | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_buf_pdl_odd.v | 5,156 | module MODULE1(
VAR15, VAR30,
VAR10, VAR14,
VAR27, VAR28,
VAR7, VAR22,
VAR24, VAR11,
VAR6, VAR29,
VAR25, VAR17,
VAR8,
VAR4, VAR9,
VAR19, VAR3,
VAR21, VAR13,
VAR16, VAR5,
VAR1, VAR2,
VAR23, VAR12,
VAR26, VAR18,
VAR20
);
output VAR15 ;
output VAR30 ;
output VAR10 ;
output VAR14 ;
output VAR27 ;
output VAR28 ;
output VAR7 ;
output VAR22 ;
output VAR24 ;
output VAR11 ;
output VAR6 ;
output VAR29 ;
output VAR25 ;
output VAR17 ;
output VAR8 ;
input VAR4;
input VAR9;
input VAR19;
input VAR3;
input VAR21;
input VAR13;
input VAR16;
input VAR5;
input VAR1;
input VAR2;
input VAR23;
input VAR12;
input VAR26;
input VAR18;
input VAR20;
assign VAR15 = ~VAR4;
assign VAR30 = ~VAR9;
assign VAR10 = ~VAR19;
assign VAR14 = ~VAR3;
assign VAR27 = ~VAR21;
assign VAR28 = ~VAR13;
assign VAR7 = ~VAR16;
assign VAR22 = ~VAR5;
assign VAR24 = ~VAR1;
assign VAR11 = ~VAR2;
assign VAR6 = ~VAR23;
assign VAR29 = ~VAR12;
assign VAR25 = ~VAR26;
assign VAR17 = ~VAR18;
assign VAR8 = ~VAR20;
endmodule | gpl-2.0 |
crespum/N64-controller-FPGA | n64_readcmd.v | 1,966 | module MODULE1(input wire VAR30,
inout VAR14,
output wire [31:0] VAR20,
output wire VAR16);
wire VAR29; wire VAR18;
wire VAR3;
wire VAR10;
VAR22 #(
.VAR1(6'VAR8 101001),
.VAR11(1'VAR8 1)
) VAR17 (
.VAR21(VAR14),
.VAR13(VAR18),
.VAR9(VAR3),
.VAR4(VAR10)
);
wire VAR31;
VAR23 #(.VAR19(4))
VAR28 (
.VAR15(VAR30),
.VAR12(VAR31)
);
VAR5
VAR24 (
.VAR31(VAR31),
.VAR33(VAR29),
.VAR27(VAR18),
.dout(VAR3)
);
reg VAR32 = 0;
always @(posedge(VAR29)) VAR32 = 1;
wire VAR6 = ~VAR18 & VAR32;
VAR26
VAR7 (
.VAR30(VAR30),
.din(VAR10),
.enable(VAR6),
.VAR20(VAR20),
.VAR16(VAR16)
);
VAR2
VAR25 (
.clk(VAR31),
.VAR33(VAR29)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o_1.v | 2,448 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR11 ,
VAR8 ,
VAR7 ,
VAR4 ,
VAR1,
VAR3,
VAR10 ,
VAR9
);
output VAR2 ;
input VAR5 ;
input VAR11 ;
input VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR3;
input VAR10 ;
input VAR9 ;
VAR12 VAR6 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR2 ,
VAR5,
VAR11,
VAR8,
VAR7,
VAR4
);
output VAR2 ;
input VAR5;
input VAR11;
input VAR8;
input VAR7;
input VAR4;
supply1 VAR1;
supply0 VAR3;
supply1 VAR10 ;
supply0 VAR9 ;
VAR12 VAR6 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
aj-michael/Digital-Systems | hw2problem3/hw2problem3.v | 1,051 | module MODULE1(VAR4, VAR1, VAR3, VAR5, VAR6);
input VAR4, VAR3, VAR5;
output reg VAR1;
output reg [1:0] VAR6;
reg [1:0] VAR2;
parameter VAR8 = 2'b00, VAR7 = 2'b01, VAR9 = 2'b10, VAR10 = 2'b11;
always @ (VAR6)
if (VAR6 == VAR9) VAR1 <= 1;
else VAR1 <= 1;
always @ (posedge VAR5 or negedge VAR3)
if (VAR3 == 0) VAR6 <= VAR8;
else VAR6 <= VAR2;
always @ (VAR6 or VAR4)
case (VAR6)
VAR8: VAR2 <= (VAR4 == 1) ? VAR7 : VAR8;
VAR7: VAR2 <= (VAR4 == 1) ? VAR10 : VAR8;
VAR9: VAR2 <= (VAR4 == 1) ? VAR9 : VAR8;
VAR10: VAR2 <= (VAR4 == 1) ? VAR9 : VAR8;
endcase
endmodule | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/fpu/hardlogic/ode.v | 2,853 | module MODULE1(VAR52,
reset,
select,
VAR13,
VAR54,
VAR22,
VAR43,
VAR45,
VAR21
);
input VAR52;
input reset;
input select;
input [VAR11-1:0] VAR13;
input [VAR11-1:0] VAR54;
input [VAR11-1:0] VAR22;
input [VAR11-1:0] VAR43;
output [VAR11-1:0] VAR45;
output [VAR11-1:0] VAR21;
output [7:0] VAR9;
wire [VAR11-1:0] VAR39;
wire [VAR11-1:0] VAR27;
wire [VAR11-1:0] VAR6;
wire [VAR11-1:0] VAR47;
wire [VAR11-1:0] VAR16;
wire [VAR11-1:0] VAR12;
wire [VAR11-1:0] VAR1;
reg [VAR11-1:0] VAR35;
reg [VAR11-1:0] VAR36;
reg [VAR11-1:0] VAR29;
reg [VAR11-1:0] VAR46;
reg [VAR11-1:0] VAR18;
reg [VAR11-1:0] VAR5;
reg [VAR11-1:0] VAR53;
reg [VAR11-1:0] VAR41;
reg [VAR11-1:0] VAR51;
reg [VAR11-1:0] VAR7;
reg [VAR11-1:0] VAR33;
reg [VAR11-1:0] VAR19;
reg [VAR11-1:0] VAR25;
reg [VAR11-1:0] VAR30;
reg [VAR11-1:0] VAR50;
reg [VAR11-1:0] VAR48;
reg [VAR11-1:0] VAR15;
reg [VAR11-1:0] VAR2;
reg [VAR11-1:0] VAR3;
reg [VAR11-1:0] VAR49;
reg [VAR11-1:0] VAR20;
reg [VAR11-1:0] VAR17;
reg [VAR11-1:0] VAR24;
reg [VAR11-1:0] VAR4;
wire [VAR11-1:0] VAR45;
reg [VAR11-1:0] VAR42;
wire [VAR11-1:0] VAR21;
assign VAR12 = select ? VAR22 : VAR47;
assign VAR1 = select ? VAR43 : VAR35;
wire [7:0] VAR9;
VAR32 VAR28
(
.clk(VAR52),
.VAR23(VAR13),
.VAR26(VAR54),
.out(VAR39),
.VAR14(VAR9)
);
wire [7:0] VAR40;
VAR44 VAR8
(
.clk(VAR52),
.VAR23(VAR1),
.VAR26(VAR12),
.out(VAR27),
.VAR14(VAR40)
);
wire [7:0] VAR37;
VAR32 VAR38
(
.clk(VAR52),
.VAR23(VAR39),
.VAR26(VAR27),
.out(VAR6),
.VAR14(VAR37)
);
wire [7:0] VAR10;
VAR44 VAR55
(
.clk(VAR52),
.VAR23(VAR4),
.VAR26(VAR6),
.out(VAR47),
.VAR14(VAR10)
);
wire [7:0] VAR34;
VAR44 VAR31
(
.clk(VAR52),
.VAR23(VAR13),
.VAR26(VAR1),
.out(VAR16),
.VAR14(VAR34)
);
assign VAR45 = VAR42;
assign VAR21 = VAR19;
always @(posedge VAR52)
begin
VAR42 <= VAR47;
VAR35 <= VAR16;
VAR36 <= VAR35;
VAR29 <= VAR36;
VAR46 <= VAR29;
VAR18 <= VAR46;
VAR5 <= VAR18;
VAR53 <= VAR5;
VAR41 <= VAR53;
VAR51 <= VAR41;
VAR7 <= VAR51;
VAR33 <= VAR7;
VAR19 <= VAR33;
VAR25 <= VAR12;
VAR30 <= VAR25;
VAR50 <= VAR30;
VAR48 <= VAR50;
VAR15 <= VAR48;
VAR2 <= VAR15;
VAR3 <= VAR2;
VAR49 <= VAR3;
VAR20 <= VAR49;
VAR17 <= VAR20;
VAR24 <= VAR17;
VAR4 <= VAR24;
end
endmodule | mit |
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