repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Video_In_video_scaler_0.v | 6,289 | module MODULE1 (
clk,
reset,
VAR34,
VAR27,
VAR19,
VAR1,
VAR13,
VAR29,
VAR28,
VAR17,
VAR5,
VAR10,
VAR3,
VAR35,
VAR30
);
parameter VAR9 = 0; parameter VAR31 = 7; parameter VAR26 = 0;
parameter VAR11 = 9; parameter VAR14 = 7; parameter VAR25 = 640;
parameter VAR7 = 4'b0000;
parameter VAR21 = 4'b0000;
parameter VAR23 = 9; parameter VAR15 = 640; parameter VAR4 = 0;
parameter VAR2 = 0;
input clk;
input reset;
input [VAR31: 0] VAR34;
input VAR27;
input VAR19;
input [VAR26: 0] VAR1;
input VAR13;
input VAR29;
output VAR28;
output [VAR9: 0] VAR17;
output [VAR31: 0] VAR5;
output VAR10;
output VAR3;
output [VAR26: 0] VAR35;
output VAR30;
wire [VAR9: 0] VAR20;
wire [VAR31: 0] VAR6;
wire VAR18;
wire VAR33;
wire VAR12;
wire VAR8;
assign VAR35 = 'h0;
VAR32 VAR36 (
.clk (clk),
.reset (reset),
.VAR34 (VAR34),
.VAR27 (VAR27),
.VAR19 (VAR19),
.VAR13 (VAR13),
.VAR29 (VAR29),
.VAR28 (VAR28),
.VAR17 (VAR17),
.VAR5 (VAR5),
.VAR10 (VAR10),
.VAR3 (VAR3),
.VAR30 (VAR30)
);
VAR36.VAR31 = VAR31,
VAR36.VAR16 = VAR23,
VAR36.VAR22 = VAR15,
VAR36.VAR24 = VAR4;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a.functional.v | 1,459 | module MODULE1 (
VAR4 ,
VAR8,
VAR11,
VAR6,
VAR7,
VAR1
);
output VAR4 ;
input VAR8;
input VAR11;
input VAR6;
input VAR7;
input VAR1;
wire VAR9 ;
wire VAR2;
or VAR3 (VAR9 , VAR11, VAR8, VAR6 );
and VAR5 (VAR2, VAR9, VAR7, VAR1);
buf VAR10 (VAR4 , VAR2 );
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/radio_controller_v1_21_a/hdl/verilog/spi_shift.v | 5,928 | module MODULE1 (clk, rst, VAR12, VAR1, VAR14,
posedge, negedge, VAR15, VAR7,
VAR10, VAR3,
VAR18, VAR9, VAR2, VAR13);
parameter VAR6 = 1;
input clk; input rst; input [4:0] VAR12; input VAR1; input VAR14; input posedge; input negedge; input VAR15; input VAR7; output VAR10; output VAR3; input [17:0] VAR18; output [17:0] VAR9; input VAR2; output VAR13;
reg VAR13;
reg VAR10;
reg [5:0] VAR5; wire [17:0] VAR4; wire [5:0] VAR11; wire [5:0] VAR16; wire VAR17; wire VAR8;
assign VAR4 = VAR18;
assign VAR11 = VAR1 ? {!(|VAR12), VAR12} - VAR5 : VAR5 - {{5{1'b0}},1'b1};
assign VAR16 = VAR1 ? {!(|VAR12), VAR12} - (VAR15 ? VAR5 + {{5{1'b0}},1'b1} : VAR5) :
(VAR15 ? VAR5 : VAR5 - {{5{1'b0}},1'b1});
assign VAR3 = !(|VAR5);
assign VAR17 = (VAR15 ? negedge : posedge) && (!VAR3 || VAR2);
assign VAR8 = (VAR7 ? negedge : posedge) && !VAR3;
always @(posedge clk or posedge rst)
begin
if(rst)
VAR5 <= #VAR6 {6{1'b0}};
end
else
begin
if(VAR10)
VAR5 <= #VAR6 posedge ? (VAR5 - {{5{1'b0}}, 1'b1}) : VAR5;
end
else
VAR5 <= #VAR6 !(|VAR12) ? {1'b1, {5{1'b0}}} : {1'b0, VAR12};
end
end
always @(posedge clk or posedge rst)
begin
if(rst)
VAR10 <= #VAR6 1'b0;
end
else if(VAR14 && ~VAR10)
VAR10 <= #VAR6 1'b1;
else if(VAR10 && VAR3 && posedge)
VAR10 <= #VAR6 1'b0;
end
always @(posedge clk or posedge rst)
begin
if (rst)
VAR13 <= #VAR6 1'b0;
end
else
VAR13 <= #VAR6 (VAR8 || !VAR10) ? VAR4[VAR11[4:0]] : VAR13;
end
endmodule | bsd-2-clause |
sjohann81/hf-risc | devices/controllers/spi_sram_controller/23LC1024.v | 34,394 | module MODULE1 (VAR12, VAR25, VAR6, VAR32, VAR27, VAR21, VAR8);
inout VAR12; input VAR6;
input VAR32;
inout VAR27;
inout VAR21;
input VAR8;
inout VAR25;
reg [07:00] VAR15; reg [07:00] VAR7; reg [31:00] VAR2; reg [07:00] VAR1; reg [16:00] VAR23;
wire VAR17; wire VAR20; wire VAR22; wire VAR10; wire VAR29; wire VAR13; wire VAR18;
reg [01:00] VAR28;
reg [01:00] VAR9;
wire VAR30;
reg [07:00] VAR5 [0:131071];
reg [03:00] VAR19; wire VAR14;
reg VAR33;
wire VAR31; wire VAR24; wire VAR3;
integer VAR11; integer VAR4; integer VAR16; integer VAR26; | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.functional.v | 1,390 | module MODULE1( VAR11, VAR7, VAR4, VAR13, VAR5 );
input VAR5, VAR13, VAR4, VAR11;
output VAR7;
wire VAR1;
not VAR14( VAR1, VAR5 );
wire VAR6;
not VAR8( VAR6, VAR13 );
wire VAR12;
not VAR2( VAR12, VAR4 );
wire VAR9;
not VAR3( VAR9, VAR11 );
or VAR10( VAR7, VAR1, VAR6, VAR12, VAR9 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.functional.pp.v | 1,611 | module MODULE1( VAR16, VAR15, VAR13, VAR14, VAR10, VAR4 );
input VAR15, VAR16, VAR13;
inout VAR10, VAR4;
output VAR14;
wire VAR17;
not VAR5( VAR17, VAR13 );
wire VAR6;
and VAR21( VAR6, VAR17, VAR15, VAR16 );
wire VAR1;
not VAR2( VAR1, VAR16 );
wire VAR7;
and VAR3( VAR7, VAR1, VAR15, VAR13 );
wire VAR11;
not VAR9( VAR11, VAR15 );
wire VAR19;
and VAR18( VAR19, VAR11, VAR16, VAR13 );
wire VAR20;
and VAR12( VAR20, VAR11, VAR1, VAR17 );
or VAR8( VAR14, VAR6, VAR7, VAR19, VAR20 );
endmodule | apache-2.0 |
olofk/oh | common/hdl/synchronizer.v | 1,583 | module MODULE1 (
out,
in, clk, reset
);
parameter VAR1 = 1;
input [VAR1-1:0] in;
input clk;
input reset;
output [VAR1-1:0] out;
reg [VAR1-1:0] VAR2;
reg [VAR1-1:0] out;
always @ (posedge clk or posedge reset)
if(reset)
begin
VAR2[VAR1-1:0] <= {(VAR1){1'b0}};
out[VAR1-1:0] <= {(VAR1){1'b0}};
end
else
begin
VAR2[VAR1-1:0] <= in[VAR1-1:0];
out[VAR1-1:0] <= VAR2[VAR1-1:0];
end
endmodule | gpl-3.0 |
aap/pdp6 | verilog/panel_6.v | 8,794 | module MODULE1(
input wire clk,
input wire reset,
input wire [5:0] VAR25,
input wire VAR27,
input wire VAR13,
input wire [31:0] VAR85,
output reg [31:0] VAR6,
output wire VAR22,
output reg VAR75,
output reg VAR19,
output reg VAR37,
output reg VAR17,
output reg VAR12,
output reg VAR50,
output reg VAR46,
output reg VAR67,
output reg VAR68,
output reg VAR81,
output reg VAR32,
output reg VAR52,
output reg VAR58,
output reg VAR59,
output reg VAR72,
output reg VAR39,
output reg [0:35] VAR44,
output reg [18:35] VAR9,
output reg VAR78,
output reg VAR71,
output reg VAR29,
output reg VAR42,
output reg VAR45,
input wire VAR33,
input wire [0:17] VAR76,
input wire [0:35] VAR16,
input wire [0:35] VAR21,
input wire [0:35] VAR64,
input wire [0:35] VAR2,
input wire [18:35] VAR18,
input wire [18:35] VAR66,
input wire VAR80,
input wire VAR43,
input wire VAR36,
input wire [1:7] VAR41,
input wire [1:7] VAR15,
input wire [1:7] VAR70,
input wire [18:25] VAR20,
input wire [18:25] VAR28,
input wire [18:25] VAR77,
input wire [0:7] VAR34,
input wire [0:7] VAR47,
input wire [0:7] VAR1,
input wire [0:7] VAR26,
input wire [0:7] VAR54,
input wire [0:7] VAR23,
input wire [0:7] VAR57,
input wire [0:7] VAR61,
input wire [0:7] VAR63,
input wire [0:7] VAR14,
input wire [0:7] VAR5,
input wire [0:7] VAR56,
input wire [0:7] VAR49,
input wire [0:7] VAR55,
input wire [7:0] VAR84,
input wire [6:0] VAR73,
output reg VAR79,
output reg VAR3,
output reg VAR8,
input wire [35:0] VAR48,
input wire [6:0] VAR30,
output reg VAR60,
input wire [7:0] VAR83,
input wire [6:0] VAR86,
input wire [0:17] VAR11,
input wire [0:6] VAR10,
input wire [0:9] VAR35,
input wire [0:9] VAR4,
input wire [1:4] VAR51,
input wire [0:2] VAR24,
input wire [0:2] VAR74,
input wire [0:1] VAR7,
input wire [0:8] VAR65,
input wire [0:4] VAR69,
input wire [31:0] VAR53,
input wire [3:0] VAR62,
input wire [7:0] VAR40,
output reg [7:0] VAR31
);
wire VAR82 = VAR62[0];
wire [7:0] VAR38 = { 5'b0, VAR43, VAR80, VAR33 };
always @ begin
case(VAR25)
6'o00: VAR6 <=
{ 20'b0,
VAR33, VAR43, VAR80, VAR58,
VAR46, VAR67, VAR12, VAR50,
VAR37, VAR17, VAR19, VAR75
};
6'o01: VAR6 <= 0;
6'o02: VAR6 <=
{ 22'b0,
VAR59, VAR72,
VAR8, VAR60,
VAR79, VAR3,
VAR52, VAR32, VAR81, VAR68
};
6'o03: VAR6 <= 0;
6'o04: VAR6 <=
{ 26'b0,
VAR45, VAR42,
VAR29, VAR71, VAR78,
1'b0 };
6'o05: VAR6 <= 0;
6'o06: VAR6 <= { 14'b0, VAR44[0:17] };
6'o07: VAR6 <= { 14'b0, VAR44[18:35] };
6'o10: VAR6 <= { 14'b0, VAR9 };
6'o11: VAR6 <= 0; 6'o12: VAR6 <= { 14'b0, VAR76 };
6'o13: VAR6 <= { 14'b0, VAR16[0:17] };
6'o14: VAR6 <= { 14'b0, VAR16[18:35] };
6'o15: VAR6 <= { 14'b0, VAR18 };
6'o16: VAR6 <= { 14'b0, VAR66 };
6'o17: VAR6 <= { 10'b0, VAR41, VAR15, VAR70, VAR36 };
6'o20: VAR6 <= { 14'b0, VAR64[0:17] };
6'o21: VAR6 <= { 14'b0, VAR64[18:35] };
6'o22: VAR6 <= { 14'b0, VAR21[0:17] };
6'o23: VAR6 <= { 14'b0, VAR21[18:35] };
6'o24: VAR6 <= { 14'b0, VAR2[0:17] };
6'o25: VAR6 <= { 14'b0, VAR2[18:35] };
6'o26: VAR6 <= { VAR34, VAR47, VAR1, VAR26 };
6'o27: VAR6 <= { VAR54, VAR23, VAR57, VAR61 };
6'o30: VAR6 <= { VAR63, VAR14, VAR5, VAR56 };
6'o31: VAR6 <= { VAR49, VAR55, 16'b0 };
6'o32: VAR6 <= { 8'b0, VAR77, VAR28, VAR20 };
6'o33: VAR6 <= { VAR84, 2'b0, VAR73 };
6'o34: VAR6 <= { VAR83, 2'b0, VAR86 };
6'o35: VAR6 <= VAR30;
6'o36: VAR6 <= VAR48[35:18];
6'o37: VAR6 <= VAR48[17:0];
6'o40: VAR6 <= VAR11;
6'o41: VAR6 <= { VAR10, VAR4, VAR35 };
6'o42: VAR6 <= { VAR65, VAR51, VAR24,
VAR7, VAR74 };
6'o43: VAR6 <= VAR53;
default: VAR6 <= 0;
endcase
end
assign VAR22 = 0;
always @(posedge clk or negedge reset) begin
if(~reset) begin
VAR75 <= 0;
VAR19 <= 0;
VAR37 <= 0;
VAR17 <= 0;
VAR12 <= 0;
VAR50 <= 0;
VAR46 <= 0;
VAR67 <= 0;
VAR68 <= 0;
VAR81 <= 0;
VAR32 <= 0;
VAR52 <= 0;
VAR79 <= 0;
VAR3 <= 0;
VAR8 <= 0;
VAR60 <= 0;
VAR58 <= 0;
VAR59 <= 0;
VAR72 <= 0;
VAR39 <= 0;
VAR44 <= 0;
VAR9 <= 0;
VAR78 <= 0;
VAR71 <= 0;
VAR29 <= 0;
VAR42 <= 0;
VAR45 <= 0;
end else begin
VAR39 <= VAR82;
if(VAR27) case(VAR25)
6'o00: begin
if(VAR85[0])
{ VAR19, VAR75 } <= 2'b01;
if(VAR85[1])
{ VAR19, VAR75 } <= 2'b10;
if(VAR85[2])
{ VAR37, VAR17 } <= 2'b01;
if(VAR85[3])
{ VAR37, VAR17 } <= 2'b10;
if(VAR85[4])
{ VAR12, VAR50 } <= 2'b01;
if(VAR85[5])
{ VAR12, VAR50 } <= 2'b10;
if(VAR85[6])
{ VAR46, VAR67 } <= 2'b01;
if(VAR85[7])
{ VAR46, VAR67 } <= 2'b10;
if(VAR85[8])
VAR58 <= 1;
end
6'o01: begin
if(VAR85[0] | VAR85[1])
{ VAR19, VAR75 } <= 2'b00;
if(VAR85[2] | VAR85[3])
{ VAR37, VAR17 } <= 2'b00;
if(VAR85[4] | VAR85[5])
{ VAR12, VAR50 } <= 2'b00;
if(VAR85[6] |VAR85[7])
{ VAR46, VAR67 } <= 2'b00;
if(VAR85[8])
VAR58 <= 0;
end
6'o02: begin
if(VAR85[0])
{ VAR81, VAR68 } <= 2'b01;
if(VAR85[1])
{ VAR81, VAR68 } <= 2'b10;
if(VAR85[2])
{ VAR52, VAR32 } <= 2'b01;
if(VAR85[3])
{ VAR52, VAR32 } <= 2'b10;
if(VAR85[4])
{ VAR79, VAR3 } <= 2'b01;
if(VAR85[5])
{ VAR79, VAR3 } <= 2'b10;
if(VAR85[6])
{ VAR60, VAR8 } <= 2'b10;
if(VAR85[7])
{ VAR60, VAR8 } <= 2'b01;
if(VAR85[8])
VAR72 <= 1;
if(VAR85[9])
VAR59 <= 1;
end
6'o03: begin
if(VAR85[0] | VAR85[1])
{ VAR81, VAR68 } <= 2'b00;
if(VAR85[2] | VAR85[3])
{ VAR52, VAR32 } <= 2'b00;
if(VAR85[4] | VAR85[5])
{ VAR79, VAR3 } <= 2'b00;
if(VAR85[6] | VAR85[7])
{ VAR60, VAR8 } <= 2'b00;
if(VAR85[8])
VAR72 <= 0;
if(VAR85[9])
VAR59 <= 0;
end
6'o04: begin
if(VAR85[1])
VAR78 <= 1;
if(VAR85[2])
VAR71 <= 1;
if(VAR85[3])
VAR29 <= 1;
if(VAR85[4])
VAR42 <= 1;
if(VAR85[5])
VAR45 <= 1;
end
6'o05: begin
if(VAR85[1])
VAR78 <= 0;
if(VAR85[2])
VAR71 <= 0;
if(VAR85[3])
VAR29 <= 0;
if(VAR85[4])
VAR42 <= 0;
if(VAR85[5])
VAR45 <= 0;
end
6'o06: VAR44[0:17] <= VAR85;
6'o07: VAR44[18:35] <= VAR85;
6'o10: VAR9 <= VAR85;
endcase
end
end
endmodule | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/CustomPeripherals/pcores/warp_v4_userio_v1_00_a/hdl/verilog/user_logic.v | 14,190 | module MODULE1
(
VAR41,
VAR21,
VAR37,
VAR14,
VAR8,
VAR25, VAR55, VAR6, VAR34, VAR10, VAR11, VAR59, VAR54, VAR57, VAR12 );
parameter VAR3 = 8'h40;
parameter VAR48 = 8'h50;
parameter VAR44 = 8'h40;
parameter VAR22 = 32;
parameter VAR39 = 5;
output [0:7] VAR41;
output VAR21;
output VAR37;
input [0:3] VAR14;
input [0:3] VAR8;
input VAR25;
input VAR55;
input [0 : VAR22-1] VAR6;
input [0 : VAR22/8-1] VAR34;
input [0 : VAR39-1] VAR10;
input [0 : VAR39-1] VAR11;
output [0 : VAR22-1] VAR59;
output VAR54;
output VAR57;
output VAR12;
wire [0:7] VAR31;
wire [0:7] VAR5;
wire [0:7] VAR42;
assign VAR31 = VAR3;
assign VAR5 = VAR48;
assign VAR42 = VAR44;
reg [0 : VAR22-1] VAR16;
reg [0 : VAR22-1] VAR4;
reg [0 : VAR22-1] VAR27;
reg [0 : VAR22-1] VAR58;
reg [0 : VAR22-1] VAR2;
wire [0 : 4] VAR43;
wire [0 : 4] VAR7;
reg [0 : VAR22-1] VAR23;
wire VAR50;
wire VAR63;
integer VAR45, VAR18;
reg [0:3] VAR17;
reg [0:3] VAR29;
reg [0:3] VAR13;
reg [0:3] VAR52;
reg [0:3] VAR60;
reg [0:3] VAR9;
reg [0:3] VAR36;
reg [0:3] VAR56;
reg [0:7] VAR62;
wire [0:7] VAR28;
reg [0:7] VAR26;
wire [0:7] VAR19;
reg [0:7] VAR46;
wire [0:7] VAR33;
wire [0:7] VAR61;
assign VAR41 = VAR16[24:31];
always @( posedge VAR25 )
begin
VAR17 <= (VAR17 << 1) | {3'b0, VAR14[0]};
VAR29 <= (VAR29 << 1) | {3'b0, VAR14[1]};
VAR13 <= (VAR13 << 1) | {3'b0, VAR14[2]};
VAR52 <= (VAR52 << 1) | {3'b0, VAR14[3]};
VAR4[28] <= &VAR17;
VAR4[29] <= &VAR29;
VAR4[30] <= &VAR13;
VAR4[31] <= &VAR52;
VAR60 <= (VAR60 << 1) | {3'b0, VAR8[0]};
VAR9 <= (VAR9 << 1) | {3'b0, VAR8[1]};
VAR36 <= (VAR36 << 1) | {3'b0, VAR8[2]};
VAR56 <= (VAR56 << 1) | {3'b0, VAR8[3]};
VAR4[24] <= &VAR60;
VAR4[25] <= &VAR9;
VAR4[26] <= &VAR36;
VAR4[27] <= &VAR56;
if (VAR2[31] == 1'b1)
begin
case ({VAR27[26], VAR27[28:31]})
5'b00000:
VAR46 <= 8'b11111100;
5'b00001:
VAR46 <= 8'b00011000;
5'b00010:
VAR46 <= 8'b01101110;
5'b00011:
VAR46 <= 8'b00111110;
5'b00100:
VAR46 <= 8'b10011010;
5'b00101:
VAR46 <= 8'b10110110;
5'b00110:
VAR46 <= 8'b11110110;
5'b00111:
VAR46 <= 8'b00011100;
5'b01000:
VAR46 <= 8'b11111110;
5'b01001:
VAR46 <= 8'b10111110;
5'b01010:
VAR46 <= 8'b11011110;
5'b01011:
VAR46 <= 8'b11111110;
5'b01100:
VAR46 <= 8'b11100100;
5'b01101:
VAR46 <= 8'b11111100;
5'b01110:
VAR46 <= 8'b11100110;
5'b01111:
VAR46 <= 8'b11000110;
default:
VAR46 <= 8'b00000000;
endcase
VAR46[7] <= VAR27[27];
end
else
begin
VAR46 <= VAR58[16:23];
end
if (VAR2[30] == 1'b1)
begin
case ({VAR27[18], VAR27[20:23]})
5'b00000:
VAR26 <= 8'b11111100;
5'b00001:
VAR26 <= 8'b00011000;
5'b00010:
VAR26 <= 8'b01101110;
5'b00011:
VAR26 <= 8'b00111110;
5'b00100:
VAR26 <= 8'b10011010;
5'b00101:
VAR26 <= 8'b10110110;
5'b00110:
VAR26 <= 8'b11110110;
5'b00111:
VAR26 <= 8'b00011100;
5'b01000:
VAR26 <= 8'b11111110;
5'b01001:
VAR26 <= 8'b10111110;
5'b01010:
VAR26 <= 8'b11011110;
5'b01011:
VAR26 <= 8'b11111110;
5'b01100:
VAR26 <= 8'b11100100;
5'b01101:
VAR26 <= 8'b11111100;
5'b01110:
VAR26 <= 8'b11100110;
5'b01111:
VAR26 <= 8'b11000110;
default:
VAR26 <= 8'b00000000;
endcase
VAR26[7] <= VAR27[19];
end
else
begin
VAR26 <= VAR58[8:15];
end
if (VAR2[29] == 1'b1)
begin
case ({VAR27[10], VAR27[12:15]})
5'b00000:
VAR62 <= 8'b11111100;
5'b00001:
VAR62 <= 8'b00011000;
5'b00010:
VAR62 <= 8'b01101110;
5'b00011:
VAR62 <= 8'b00111110;
5'b00100:
VAR62 <= 8'b10011010;
5'b00101:
VAR62 <= 8'b10110110;
5'b00110:
VAR62 <= 8'b11110110;
5'b00111:
VAR62 <= 8'b00011100;
5'b01000:
VAR62 <= 8'b11111110;
5'b01001:
VAR62 <= 8'b10111110;
5'b01010:
VAR62 <= 8'b11011110;
5'b01011:
VAR62 <= 8'b11111110;
5'b01100:
VAR62 <= 8'b11100100;
5'b01101:
VAR62 <= 8'b11111100;
5'b01110:
VAR62 <= 8'b11100110;
5'b01111:
VAR62 <= 8'b11000110;
default:
VAR62 <= 8'b00000000;
endcase
VAR62[7] <= VAR27[11];
end
else
begin
VAR62 <= VAR58[0:7];
end
end
assign VAR33 = {VAR46[0], VAR46[6], VAR46[1], VAR46[2], VAR46[7], VAR46[3], VAR46[4], VAR46[5]};
assign VAR19 = {VAR26[0], VAR26[6], VAR26[1], VAR26[2], VAR26[7], VAR26[3], VAR26[4], VAR26[5]};
assign VAR28 = {VAR62[5], VAR62[4], VAR62[3], VAR62[7], VAR62[2], VAR62[1], VAR62[6], VAR62[0]};
assign VAR61 = VAR58[24:31];
assign
VAR43 = VAR11[0:4],
VAR7 = VAR10[0:4],
VAR63 = VAR11[0] || VAR11[1] || VAR11[2] || VAR11[3] || VAR11[4],
VAR50 = VAR10[0] || VAR10[1] || VAR10[2] || VAR10[3] || VAR10[4];
always @( posedge VAR25 )
begin: VAR32
if ( VAR55 == 1 )
begin
VAR16 <= 0;
VAR27 <= 0;
VAR58 <= 0;
VAR2 <= 0;
end
else
case (VAR43)
5'b10000 :
for ( VAR45 = 0; VAR45 <= (VAR22/8)-1; VAR45 = VAR45+1 )
if ( VAR34[VAR45] == 1 )
for ( VAR18 = VAR45*8; VAR18 <= VAR45*8+7; VAR18 = VAR18+1 )
VAR16[VAR18] <= VAR6[VAR18];
5'b00100 :
for ( VAR45 = 0; VAR45 <= (VAR22/8)-1; VAR45 = VAR45+1 )
if ( VAR34[VAR45] == 1 )
for ( VAR18 = VAR45*8; VAR18 <= VAR45*8+7; VAR18 = VAR18+1 )
VAR27[VAR18] <= VAR6[VAR18];
5'b00010 :
for ( VAR45 = 0; VAR45 <= (VAR22/8)-1; VAR45 = VAR45+1 )
if ( VAR34[VAR45] == 1 )
for ( VAR18 = VAR45*8; VAR18 <= VAR45*8+7; VAR18 = VAR18+1 )
VAR58[VAR18] <= VAR6[VAR18];
5'b00001 :
for ( VAR45 = 0; VAR45 <= (VAR22/8)-1; VAR45 = VAR45+1 )
if ( VAR34[VAR45] == 1 )
for ( VAR18 = VAR45*8; VAR18 <= VAR45*8+7; VAR18 = VAR18+1 )
VAR2[VAR18] <= VAR6[VAR18];
default : ;
endcase
end
always @( VAR7 or VAR16 or VAR4 or VAR27 or VAR58 or VAR2 )
begin: VAR20
case ( VAR7 )
5'b10000 : VAR23 <= VAR16;
5'b01000 : VAR23 <= VAR4;
5'b00100 : VAR23 <= VAR27;
5'b00010 : VAR23 <= {VAR62, VAR26, VAR46, VAR61};
5'b00001 : VAR23 <= VAR2;
default : VAR23 <= 0;
endcase
end
assign VAR59 = VAR23;
assign VAR57 = VAR63;
assign VAR54 = VAR50;
assign VAR12 = 0;
VAR35 VAR30 (
.clk(VAR25),
.VAR40(1'b1),
.VAR51(VAR31),
.VAR47(VAR5),
.VAR42(VAR42),
.VAR49(VAR19), .VAR38(VAR28), .VAR24(VAR33),
.VAR15(VAR61),
.reset(VAR55),
.VAR53(VAR37),
.VAR1(VAR21)
);
endmodule | bsd-2-clause |
pavel-demin/red-pitaya-notes | cores/axis_variable_v1_0/axis_variable.v | 1,097 | module MODULE1 #
(
parameter integer VAR6 = 32
)
(
input wire VAR5,
input wire VAR1,
input wire [VAR6-1:0] VAR7,
input wire VAR9,
output wire [VAR6-1:0] VAR8,
output wire VAR10
);
reg [VAR6-1:0] VAR3;
reg VAR2, VAR4;
always @(posedge VAR5)
begin
if(~VAR1)
begin
VAR3 <= {(VAR6){1'b0}};
VAR2 <= 1'b0;
end
else
begin
VAR3 <= VAR7;
VAR2 <= VAR4;
end
end
always @*
begin
VAR4 = VAR2;
if(VAR3 != VAR7)
begin
VAR4 = 1'b1;
end
if(VAR9 & VAR2)
begin
VAR4 = 1'b0;
end
end
assign VAR8 = VAR3;
assign VAR10 = VAR2;
endmodule | mit |
borti4938/sd2snes | verilog/sd2snes_gsu/cheat.v | 12,310 | module MODULE1(
input clk,
input [7:0] VAR34,
input [23:0] VAR38,
input [7:0] VAR67,
input VAR56,
input VAR13,
input VAR52,
input VAR43,
input VAR48,
input VAR2,
input VAR37,
input VAR23,
input VAR20,
input VAR62,
input VAR45,
input VAR60,
input [2:0] VAR57,
input VAR64,
input [31:0] VAR27,
input VAR59,
output [7:0] VAR41,
output VAR53,
output VAR6
);
reg [23:0] VAR69;
always @(posedge clk) VAR69 <= VAR38;
wire VAR30 = VAR43 & VAR56;
reg VAR54 = 0;
reg VAR17 = 0;
reg VAR61 = 0;
reg VAR15 = 0; reg VAR25 = 0;
reg VAR50 = 0;
wire VAR47 = VAR54 & VAR50;
reg VAR51 = 1;
reg VAR31 = 0;
reg VAR55 = 0;
reg VAR35 = 0;
reg VAR46 = 0;
reg [1:0] VAR63 = 2'b10;
reg [4:0] VAR12 = 5'h00;
reg [4:0] VAR32 = 5'h00;
reg [20:0] VAR24 = 21'h1fffff;
reg [29:0] VAR39 = 0;
reg VAR19 = 0;
reg [1:0] VAR18 = 0;
wire VAR44 = |VAR18;
reg [1:0] VAR8 = 2'b10;
wire VAR16 = |VAR8;
reg [23:0] VAR9[5:0];
reg [7:0] VAR33[5:0];
reg [5:0] VAR68;
reg VAR11 = 0;
assign VAR6 = VAR11;
reg [7:0] VAR26 = 0;
reg [7:0] VAR7 = 8'hea;
reg [7:0] VAR29 = 8'h00;
reg [7:0] VAR4 = 8'h00;
reg [15:0] VAR65 = 0;
wire [5:0] VAR14 ={(VAR68[5] & (VAR38 == VAR9[5])),
(VAR68[4] & (VAR38 == VAR9[4])),
(VAR68[3] & (VAR38 == VAR9[3])),
(VAR68[2] & (VAR38 == VAR9[2])),
(VAR68[1] & (VAR38 == VAR9[1])),
(VAR68[0] & (VAR38 == VAR9[0]))};
wire VAR22 = |VAR14;
wire [1:0] VAR58 = {VAR38 == 24'h00FFEA, VAR38 == 24'h00FFEB};
wire [1:0] VAR5 = {VAR38 == 24'h00FFEE, VAR38 == 24'h00FFEF};
wire [1:0] VAR42 = {VAR38 == 24'h00FFFC, VAR38 == 24'h00FFFD};
wire VAR36 = |VAR58;
wire VAR66 = |VAR5;
wire VAR10 = |VAR42;
wire VAR21 = ~|VAR39;
assign VAR41 = VAR14[0] ? VAR33[0]
: VAR14[1] ? VAR33[1]
: VAR14[2] ? VAR33[2]
: VAR14[3] ? VAR33[3]
: VAR14[4] ? VAR33[4]
: VAR14[5] ? VAR33[5]
: VAR58[1] ? 8'h04
: VAR5[1] ? 8'h04
: VAR42[1] ? 8'h6b
: VAR48 ? VAR26
: VAR2 ? VAR7
: VAR23 ? VAR29
: VAR20 ? VAR4
: 8'h2a;
assign VAR53 = (VAR6 & VAR46 & (VAR48 | VAR2 | VAR23 | VAR20))
| (VAR16 & VAR10)
| (VAR54 & VAR22)
| (VAR46 & (((VAR55 & VAR17) & VAR36 & VAR44)
|((VAR35 & VAR61) & VAR66 & VAR44)));
reg [7:0] VAR40 = 0;
reg [2:0] VAR28 = 0;
always @(posedge clk) begin
if(VAR52) begin
VAR28 <= 0;
end else if(VAR56) begin
VAR28 <= VAR28 + 1;
if(VAR28 == 3'b0) begin
VAR40 <= VAR34 - 1;
end else begin
if(VAR34 == VAR40) begin
VAR40 <= VAR40 - 1;
end else begin
VAR28 <= 3'b0;
end
end
end else if(VAR13) begin
VAR28 <= 3'b0;
end
end
always @(posedge clk) begin
if(VAR52) begin
VAR18 <= 2'b00;
end else if(VAR13) begin
if(VAR46
& ((VAR55 & VAR17 & VAR58[1])
|(VAR35 & VAR61 & VAR5[1]))
& VAR28 == 4) begin
VAR18 <= 2'b11;
end else if(|VAR18) begin
VAR18 <= VAR18 - 1;
end
end
end
always @(posedge clk) begin
if(VAR52) begin
VAR8 <= 2'b11;
end else if(VAR60) begin
if(VAR10 & |VAR8) begin
VAR8 <= VAR8 - 1;
end
end
end
reg VAR3 = 1'b0;
reg [6:0] VAR49 = 0;
reg VAR1 = 0;
always @(posedge clk) begin
if(VAR52) begin
VAR11 <= 0;
VAR1 <= 0;
end else begin
if(VAR13) begin
if(VAR46
& ((VAR55 & VAR17 & VAR58[1])
|(VAR35 & VAR61 & VAR5[1]))
& VAR28 == 4) begin
VAR7 <= VAR38[7:0];
VAR11 <= 1;
VAR1 <= 0;
VAR49 <= 0;
end
else if(VAR42[1] & |VAR8) begin
VAR11 <= 1;
VAR1 <= 0;
VAR49 <= 0;
end
end
else if(VAR60) begin
if(VAR1) begin
if(|VAR49) begin
VAR49 <= VAR49 - 1;
end else if(VAR49 == 0) begin
VAR11 <= 0;
VAR1 <= 0;
end
end
end
else if(VAR3) begin
VAR49 <= 7'd72;
VAR1 <= 1;
end
end
end
always @(posedge clk) VAR24 <= VAR24 - 1;
always @(posedge clk) begin
if(VAR24 == 21'b0) begin
VAR12 <= VAR60 & VAR58[1];
VAR32 <= VAR60 & VAR5[1];
if(|VAR12 & |VAR32) begin
VAR51 <= 1'b1;
VAR31 <= 1'b0;
end else if(VAR32 == 5'b0) begin
VAR51 <= 1'b1;
VAR31 <= 1'b0;
end else if(VAR12 == 5'b0) begin
VAR51 <= 1'b0;
VAR31 <= 1'b1;
end
end else begin
if(VAR60 & VAR58[0]) VAR12 <= VAR12 + 1;
if(VAR60 & VAR5[0]) VAR32 <= VAR32 + 1;
end
end
always @(posedge clk) begin
if(VAR60) begin
if(VAR36 | VAR66) VAR63 <= 2'b10;
end
else begin
if (|VAR63) VAR63 <= VAR63 - 1;
if (VAR63 == 2'b00) begin
VAR55 <= VAR51;
VAR35 <= VAR31;
VAR46 <= VAR21;
end
end
end
end
always @(posedge clk) begin
if((VAR6 & VAR30 & ~|VAR38[8:0] & (VAR67 == 8'h85))
| (VAR15 & VAR52)) begin
VAR39 <= 30'd960000000; end else if (|VAR39) begin
VAR39 <= VAR39 - 1;
end
end
always @(posedge clk) begin
if(VAR52) begin
VAR3 <= 1'b0;
end else begin
VAR3 <= 1'b0;
if(VAR6 & VAR30) begin
if(~|VAR38[8:0]) begin
case(VAR67)
8'h82: VAR54 <= 1;
8'h83: VAR54 <= 0;
8'h84: {VAR17, VAR61} <= 2'b00;
endcase
end else if(VAR38[8:0] == 9'h1fd) begin
VAR3 <= 1'b1;
end
end else if(VAR64) begin
if(VAR57 < 6) begin
VAR9[VAR57] <= VAR27[31:8];
VAR33[VAR57] <= VAR27[7:0];
end else if(VAR57 == 6) begin VAR68 <= VAR27[5:0];
end else if(VAR57 == 7) begin {VAR50, VAR25, VAR15, VAR61, VAR17, VAR54}
<= ({VAR50, VAR25, VAR15, VAR61, VAR17, VAR54}
& ~VAR27[13:8])
| VAR27[5:0];
end
end
end
end
always @(posedge clk) begin
if(VAR30) begin
if(VAR38[8:0] == 9'h1f0) begin
VAR65[7:0] <= VAR67;
end else if(VAR38[8:0] == 9'h1f1) begin
VAR65[15:8] <= VAR67;
end
end
end
always @* begin
case(VAR65)
16'h3030: VAR26 = 8'h80;
16'h2070: VAR26 = 8'h81;
16'h10b0: VAR26 = 8'h82;
16'h9030: VAR26 = 8'h83;
16'h5030: VAR26 = 8'h84;
16'h1070: VAR26 = 8'h85;
default: VAR26 = 8'h00;
endcase
end
always @* begin
if(VAR25) begin
if(VAR45) begin
if(VAR26) begin
VAR29 = 8'h30; end else begin
if(VAR47) begin
VAR29 = 8'h3a; end else begin
VAR29 = 8'h3d; end
end
end else begin
if(VAR62) begin
if(VAR47) begin
VAR29 = 8'h3a; end else begin
VAR29 = 8'h3d; end
end else begin
VAR29 = 8'h00; end
end
end else begin
if(VAR47) begin
VAR29 = 8'h3a; end else begin
VAR29 = 8'h3d; end
end
end
always @* begin
if(VAR26 == 8'h81) begin
VAR4 = 8'h0e; end else if(VAR47) begin
VAR4 = 8'h00; end else begin
VAR4 = 8'h03; end
end
endmodule | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ui_top.v | 14,966 | module MODULE1 #
(
parameter VAR79 = 100,
parameter VAR72 = 256,
parameter VAR84 = 32,
parameter VAR10 = 3,
parameter VAR13 = 12,
parameter VAR12 = 5,
parameter VAR66 = 5,
parameter VAR80 = "VAR51",
parameter VAR87 = "VAR51",
parameter VAR68 = "VAR36",
parameter VAR11 = 2,
parameter VAR24 = 4,
parameter VAR52 = "VAR42", parameter VAR33 = 2,
parameter VAR39 = 16,
parameter VAR28 = "VAR9"
)
(
VAR77, VAR6, VAR44, VAR58, VAR56, VAR60, VAR82,
VAR1, VAR54, VAR71, VAR3, VAR47, VAR74, VAR32,
VAR59, VAR81, VAR40,
VAR64, VAR76, VAR31, VAR45, VAR73, VAR43,
VAR8, VAR7,
VAR49, VAR19, VAR26, rst, VAR48,
VAR41, VAR5, VAR15, VAR16, VAR62, clk,
VAR37, VAR35, VAR63, VAR85, VAR57,
VAR53, VAR78, VAR29, VAR30, VAR65, VAR17,
VAR34, VAR4, VAR14, VAR61, VAR46, VAR18,
VAR83, VAR22
);
input VAR34;
localparam VAR55 = VAR33 + VAR10 + VAR39 + VAR13;
localparam VAR25 = (VAR52 == "VAR42") ? VAR12 + 1 : VAR12;
input VAR4;
output wire VAR76;
assign VAR76 = VAR4;
input VAR14;
output wire VAR31;
assign VAR31 = VAR14;
input VAR61;
output wire VAR45;
assign VAR45 = VAR61;
input VAR46;
output wire VAR73;
assign VAR73 = VAR46;
input VAR18;
output wire VAR43;
assign VAR43 = VAR18;
input VAR83;
output wire VAR8;
assign VAR8 = VAR83;
input VAR22;
output wire VAR7;
assign VAR7 = VAR22;
input VAR17; input [VAR55-1:0] VAR65; input [2:0] VAR30; input VAR29; input VAR78; input [2*VAR11-1:0] VAR53; input VAR57; input [VAR72-1:0] VAR85; input VAR63; input [VAR84-1:0] VAR35; input VAR37; input clk; input [2*VAR11-1:0] VAR62; input [VAR72-1:0] VAR16; input [VAR66-1:0] VAR15; input VAR5; input VAR41; input VAR48; input rst; input [VAR66-1:0] VAR26; input VAR19; input VAR49;
output [2*VAR11-1:0] VAR64; output [VAR72-1:0] VAR40; output VAR81; output VAR59; output VAR32; output VAR74; output [VAR10-1:0] VAR47; output [2:0] VAR3; output [VAR13-1:0] VAR71; output [VAR66-1:0]VAR54; output VAR1; output [VAR33-1:0] VAR82; output [2*VAR11-1:0] VAR60; output [VAR39-1:0] VAR56; output VAR58; output VAR44; output [VAR72-1:0] VAR6; output [VAR84-1:0] VAR77;
wire [3:0] VAR2; wire VAR20; wire VAR23; wire VAR27; wire [VAR66-1:0]VAR70; wire VAR88; wire [VAR66-1:0] VAR50; wire VAR89;
generate
if(VAR66 > 4) begin
assign VAR50[VAR66-1:4] = 0;
end
endgenerate
VAR21 #
(
.VAR79 (VAR79),
.VAR55 (VAR55),
.VAR10 (VAR10),
.VAR13 (VAR13),
.VAR66 (VAR66),
.VAR33 (VAR33),
.VAR39 (VAR39),
.VAR24 (VAR24),
.VAR28 (VAR28))
VAR75
(
.VAR32 (VAR32),
.VAR44 (VAR44),
.VAR82 (VAR82[VAR33-1:0]),
.VAR47 (VAR47[VAR10-1:0]),
.VAR56 (VAR56[VAR39-1:0]),
.VAR71 (VAR71[VAR13-1:0]),
.VAR58 (VAR58),
.VAR3 (VAR3[2:0]),
.VAR1 (VAR1),
.VAR23 (VAR23),
.VAR88 (VAR88),
.VAR54 (VAR54),
.rst (rst),
.clk (clk),
.VAR17 (VAR17),
.VAR27 (VAR27),
.VAR89 (VAR89),
.VAR65 (VAR65[VAR55-1:0]),
.VAR30 (VAR30[2:0]),
.VAR57 (VAR57),
.VAR78 (VAR78),
.VAR29 (VAR29),
.VAR50 (VAR50),
.VAR70 (VAR70));
VAR67 #
(
.VAR79 (VAR79),
.VAR72 (VAR72),
.VAR84 (VAR84),
.VAR11 (VAR11),
.VAR80 (VAR80),
.VAR87 (VAR87),
.VAR12 (VAR25))
VAR38
(
.VAR74 (VAR74),
.VAR89 (VAR89),
.VAR50 (VAR50[3:0]),
.VAR6 (VAR6[VAR72-1:0]),
.VAR77 (VAR77[VAR84-1:0]),
.VAR60 (VAR60[2*VAR11-1:0]),
.rst (rst),
.clk (clk),
.VAR85 (VAR85[VAR72-1:0]),
.VAR35 (VAR35[VAR84-1:0]),
.VAR53 (VAR53[2*VAR11-1:0]),
.VAR37 (VAR37),
.VAR63 (VAR63),
.VAR49 (VAR49),
.VAR26 (VAR26[3:0]),
.VAR19 (VAR19),
.VAR88 (VAR88),
.VAR20 (VAR20),
.VAR2 (VAR2));
VAR86 #
(
.VAR79 (VAR79),
.VAR72 (VAR72),
.VAR66 (VAR66),
.VAR11 (VAR11),
.VAR80 (VAR80),
.VAR68 (VAR68))
VAR69
(
.VAR20 (VAR20),
.VAR2 (VAR2),
.VAR59 (VAR59),
.VAR81 (VAR81),
.VAR40 (VAR40[VAR72-1:0]),
.VAR64 (VAR64[2*VAR11-1:0]),
.VAR27 (VAR27),
.VAR70 (VAR70),
.rst (rst),
.clk (clk),
.VAR5 (VAR5),
.VAR15 (VAR15),
.VAR48 (VAR48),
.VAR41 (VAR41),
.VAR16 (VAR16[VAR72-1:0]),
.VAR62 (VAR62[3:0]),
.VAR23 (VAR23));
endmodule | mit |
ShepardSiegel/ocpi | libsrc/hdl/bsv/bram_patch/BRAM1_alt.v | 2,704 | module MODULE1(VAR4,
VAR12,
VAR6,
VAR11,
VAR10,
VAR2
);
parameter VAR13 = 0;
parameter VAR7 = 1;
parameter VAR9 = 1;
parameter VAR5 = 1;
input VAR4;
input VAR12;
input VAR6;
input [VAR7-1:0] VAR11;
input [VAR9-1:0] VAR10;
output [VAR9-1:0] VAR2;
reg [VAR9-1:0] VAR8[0:VAR5-1];
reg [VAR7-1:0] VAR1;
reg [VAR9-1:0] VAR14;
integer VAR3; | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2.behavioral.pp.v | 1,774 | module MODULE1 (
VAR2 ,
VAR12 ,
VAR6 ,
VAR1,
VAR4,
VAR11 ,
VAR3
);
output VAR2 ;
input VAR12 ;
input VAR6 ;
input VAR1;
input VAR4;
input VAR11 ;
input VAR3 ;
wire VAR10 ;
wire VAR7;
or VAR9 (VAR10 , VAR6, VAR12 );
VAR8 VAR5 (VAR7, VAR10, VAR1, VAR4);
buf VAR13 (VAR2 , VAR7 );
endmodule | apache-2.0 |
parallella/oh | common/hdl/oh_ram.v | 2,927 | module MODULE1 # (parameter VAR7 = 104, parameter VAR12 = 32, parameter VAR10 = 1, parameter VAR18= 1, parameter VAR22 = VAR9(VAR12) )
( input VAR4, input VAR29, input [VAR22-1:0] VAR32, output [VAR7-1:0] VAR3, input VAR27, input VAR6, input [VAR22-1:0] VAR21, input [VAR7-1:0] VAR15, input [VAR7-1:0] VAR24, input VAR30, input VAR16, input [VAR7-1:0] VAR8, input [VAR22-1:0] VAR19, input [VAR7-1:0] VAR14, input [VAR7-1:0] VAR28, input VAR25, input VAR2, input VAR17, input VAR20, input [7:0] VAR5, input [7:0] VAR23 );
reg [VAR7-1:0] VAR11 [0:VAR12-1];
wire [VAR7-1:0] VAR1;
wire [VAR22-1:0] VAR26;
integer VAR13;
assign VAR26[VAR22-1:0] = (VAR18==1) ? VAR32[VAR22-1:0] :
VAR21[VAR22-1:0];
always @(posedge VAR27)
for (VAR13=0;VAR13<VAR7;VAR13=VAR13+1)
if (VAR6 & VAR15[VAR13])
VAR11[VAR21[VAR22-1:0]][VAR13] <= VAR24[VAR13];
assign VAR1[VAR7-1:0] = VAR11[VAR26[VAR22-1:0]];
reg [VAR7-1:0] VAR31;
always @ (posedge VAR4)
if(VAR29)
VAR31[VAR7-1:0] <= VAR1[VAR7-1:0];
assign VAR3[VAR7-1:0] = (VAR10==1) ? VAR31[VAR7-1:0] :
VAR1[VAR7-1:0];
endmodule | mit |
gigglesninja/digital-system-design | lab6_timer32/timer32.v | 2,051 | module MODULE1(clk, reset, din, dout, VAR3, VAR4, addr);
input clk, reset, VAR3, VAR4;
input [31:0] din;
output [31:0] dout;
input [1:0] addr;
reg [31:0] out, VAR6, VAR7, period;
reg [2:0] VAR10;
parameter VAR5 = 32'h0000000F; parameter VAR12 = 1'b0;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR7<= VAR9;
period <= VAR5;
end
else begin
if(VAR1) begin
VAR7 <= VAR7 + 1;
end
if(VAR4 & (addr == VAR8) & VAR11)
if(VAR7 == period) begin
VAR7 <= VAR9;
end
if(VAR3 & (addr == VAR2))
period <= din;
if(VAR3 & (addr == VAR8)) begin
end
end
end
always @* begin
out = VAR9;
case(addr)
out = VAR7;
out = period;
out[2:0] = VAR10;
endcase
end
always @* begin
VAR6 = VAR9;
case(VAR4)
1'b1:
VAR6 = out;
endcase
end
assign dout = VAR6;
endmodule | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/JTAGB.v | 1,711 | module MODULE1 (
output VAR4,
output VAR1,
output VAR7,
output VAR8,
output VAR11,
output VAR9,
output VAR3,
output VAR2,
output VAR6,
input VAR10,
input VAR5
) ;
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b.functional.pp.v | 1,988 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR10 ,
VAR1 ,
VAR12 ,
VAR14,
VAR15,
VAR3 ,
VAR9
);
output VAR5 ;
input VAR4 ;
input VAR10 ;
input VAR1 ;
input VAR12 ;
input VAR14;
input VAR15;
input VAR3 ;
input VAR9 ;
wire VAR6 ;
wire VAR2 ;
wire VAR16;
not VAR7 (VAR6 , VAR12 );
nor VAR11 (VAR2 , VAR4, VAR10, VAR1, VAR6 );
VAR13 VAR17 (VAR16, VAR2, VAR14, VAR15);
buf VAR8 (VAR5 , VAR16 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.behavioral.pp.v | 1,164 | module MODULE1( VAR3, VAR6, VAR5, VAR7 );
input VAR3;
inout VAR5, VAR7;
output VAR6;
VAR4 VAR2(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7));
VAR4 VAR1(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_qpll_drp.v | 15,782 | module MODULE1 #
(
parameter VAR47 = "VAR36", parameter VAR51 = 0, parameter VAR60 = 3'd4
)
(
input VAR35,
input VAR12,
input VAR56,
input VAR39,
input VAR53,
input [15:0] VAR22,
input VAR14,
output [ 7:0] VAR43,
output VAR34,
output [15:0] VAR41,
output VAR44,
output VAR1,
output [ 5:0] VAR58,
output [ 6:0] VAR52
);
reg VAR13;
reg VAR57;
reg VAR26;
reg [15:0] VAR59;
reg VAR29;
reg VAR15;
reg VAR24;
reg VAR17;
reg [15:0] VAR49;
reg VAR20;
reg [ 2:0] VAR16 = 3'd0;
reg VAR54 = 1'd0;
reg [ 5:0] VAR9 = 6'd0;
reg [ 7:0] addr = 8'd0;
reg [15:0] VAR45 = 16'd0;
reg VAR46 = 1'd0;
reg [ 6:0] fsm = 7'd1;
localparam VAR40 = 8'h36;
localparam VAR8 = 8'h88;
localparam VAR33 = 8'h35;
localparam VAR30 = 8'h36;
localparam VAR37 = 8'h34;
localparam VAR19 = 16'b1111110000000000; localparam VAR4 = 16'b0000001111111111; localparam VAR23 = 16'b1111011111111111; localparam VAR7 = 16'b1110011111111111;
localparam VAR10 = 16'b0000000000000000; localparam VAR61 = 16'b0000000000000000; localparam VAR6 = 16'b0000000000000000;
localparam VAR2 = 16'b0000000000000000; localparam VAR21 = 16'b0000100000000000; localparam VAR11 = 16'b0000000000000000;
localparam VAR50 = (VAR51 == 2) && (VAR47 == "VAR55") ? 16'b0000000010000000 :
(VAR51 == 1) && (VAR47 == "VAR55") ? 16'b0000000100100000 :
(VAR51 == 0) && (VAR47 == "VAR55") ? 16'b0000000101110000 :
(VAR51 == 2) && (VAR47 == "VAR36") ? 16'b0000000001100000 :
(VAR51 == 1) && (VAR47 == "VAR36") ? 16'b0000000011100000 : 16'b0000000100100000;
localparam VAR62 = (VAR51 == 2) ? 16'b0000000010000000 :
(VAR51 == 1) ? 16'b0000000100100000 : 16'b0000000101110000;
localparam VAR48 = (VAR51 == 2) ? 16'b0000000001100000 :
(VAR51 == 1) ? 16'b0000000011100000 : 16'b0000000100100000;
wire [15:0] VAR28;
wire [15:0] VAR25;
wire [15:0] VAR31;
wire [15:0] VAR3;
localparam VAR27 = 7'b0000001;
localparam VAR18 = 7'b0000010;
localparam VAR63 = 7'b0000100;
localparam VAR5 = 7'b0001000;
localparam VAR32 = 7'b0010000;
localparam VAR38 = 7'b0100000;
localparam VAR42 = 7'b1000000;
always @ (posedge VAR35)
begin
if (!VAR12)
begin
VAR13 <= 1'd0;
VAR57 <= 1'd0;
VAR26 <= 1'd0;
VAR59 <= 16'd0;
VAR29 <= 1'd0;
VAR15 <= 1'd0;
VAR24 <= 1'd0;
VAR17 <= 1'd0;
VAR49 <= 16'd0;
VAR20 <= 1'd0;
end
else
begin
VAR13 <= VAR56;
VAR57 <= VAR39;
VAR26 <= VAR53;
VAR59 <= VAR22;
VAR29 <= VAR14;
VAR15 <= VAR13;
VAR24 <= VAR57;
VAR17 <= VAR26;
VAR49 <= VAR59;
VAR20 <= VAR29;
end
end
assign VAR28 = (VAR24) ? VAR48 : VAR62;
assign VAR25 = VAR10;
assign VAR31 = (VAR15) ? VAR21 : VAR61;
assign VAR3 = (VAR15) ? VAR11 : VAR6;
always @ (posedge VAR35)
begin
if (!VAR12)
begin
addr <= 8'd0;
VAR45 <= 16'd0;
VAR9 <= 6'd0;
end
else
begin
case (VAR16)
3'd0 :
begin
addr <= VAR40;
VAR45 <= (VAR49 & VAR19) | (VAR54 ? VAR28 : VAR50);
VAR9 <= VAR9;
end
3'd1 :
begin
addr <= VAR8;
VAR45 <= VAR49;
if (VAR15)
VAR9 <= VAR49[6:1];
end
else
VAR9 <= VAR9;
end
3'd2 :
begin
addr <= VAR33;
VAR45 <= (VAR49 & VAR4) | {(VAR9 - 6'd1), VAR25[9:0]};
VAR9 <= VAR9;
end
3'd3 :
begin
addr <= VAR30;
VAR45 <= (VAR49 & VAR23) | VAR31;
VAR9 <= VAR9;
end
3'd4 :
begin
addr <= VAR37;
VAR45 <= (VAR49 & VAR7) | VAR3;
VAR9 <= VAR9;
end
default :
begin
addr <= 8'd0;
VAR45 <= 16'd0;
VAR9 <= 6'd0;
end
endcase
end
end
always @ (posedge VAR35)
begin
if (!VAR12)
begin
fsm <= VAR27;
VAR16 <= 3'd0;
VAR54 <= 1'd0;
VAR46 <= 1'd0;
end
else
begin
case (fsm)
VAR27 :
begin
if (VAR17)
begin
fsm <= VAR18;
VAR16 <= 3'd0;
VAR54 <= 1'd0;
VAR46 <= 1'd0;
end
else if ((VAR24 != VAR57) && (VAR47 == "VAR55"))
begin
fsm <= VAR18;
VAR16 <= 3'd0;
VAR54 <= 1'd1;
VAR46 <= 1'd0;
end
else
begin
fsm <= VAR27;
VAR16 <= 3'd0;
VAR54 <= 1'd0;
VAR46 <= 1'd1;
end
end
VAR18 :
begin
fsm <= VAR63;
VAR16 <= VAR16;
VAR54 <= VAR54;
VAR46 <= 1'd0;
end
VAR63 :
begin
fsm <= VAR5;
VAR16 <= VAR16;
VAR54 <= VAR54;
VAR46 <= 1'd0;
end
VAR5 :
begin
fsm <= (VAR20 ? VAR32 : VAR5);
VAR16 <= VAR16;
VAR54 <= VAR54;
VAR46 <= 1'd0;
end
VAR32 :
begin
fsm <= VAR38;
VAR16 <= VAR16;
VAR54 <= VAR54;
VAR46 <= 1'd0;
end
VAR38 :
begin
fsm <= (VAR20 ? VAR42 : VAR38);
VAR16 <= VAR16;
VAR54 <= VAR54;
VAR46 <= 1'd0;
end
VAR42 :
begin
if ((VAR16 == VAR60) || (VAR54 && (VAR16 == 3'd0)))
begin
fsm <= VAR27;
VAR16 <= 3'd0;
VAR54 <= VAR54;
VAR46 <= 1'd0;
end
else
begin
fsm <= VAR18;
VAR16 <= VAR16 + 3'd1;
VAR54 <= VAR54;
VAR46 <= 1'd0;
end
end
default :
begin
fsm <= VAR27;
VAR16 <= 3'd0;
VAR54 <= 1'd0;
VAR46 <= 1'd0;
end
endcase
end
end
assign VAR43 = addr;
assign VAR34 = (fsm == VAR63) || (fsm == VAR32);
assign VAR41 = VAR45;
assign VAR44 = (fsm == VAR32) || (fsm == VAR38);
assign VAR1 = VAR46;
assign VAR58 = VAR9;
assign VAR52 = fsm;
endmodule | lgpl-3.0 |
d16-processor/d16 | verilog/src/mem.v | 2,629 | module MODULE1(
input clk,
input rst,
input en,
input VAR11,
input VAR8,
input VAR6,
input [15:0] addr,
input [15:0] VAR20,
output reg [15:0] VAR4,
output VAR2,
input VAR10,
input [15:0] VAR23,
input [15:0] VAR16,
output reg [15:0] VAR14
);
wire [15:0] VAR3; wire [15:0] VAR9; reg [15:0] VAR19;
reg [1:0] VAR13;
assign VAR2 = 0;
VAR5 VAR22(
.VAR3 (VAR3[15:0]),
.VAR9 (VAR9[15:0]),
.VAR21 (addr[13:0]),
.VAR7 (VAR23[13:0]),
.VAR13 (VAR13[1:0]),
.VAR17 (clk),
.VAR19 (VAR19[15:0]),
.VAR18 (VAR16[15:0]),
.VAR1 (VAR11),
.VAR12 (VAR10));
always @* begin
if(VAR6) begin
if(VAR8) begin
VAR13 <= 2'b10;
end
else begin
VAR13 <= 2'b01;
end
end
else begin
VAR13 <= 2'b11;
end
VAR19 <= VAR20;
end
always @* begin
if(VAR6) begin
if(VAR8)
VAR4 <= {8'b0,VAR3[15:8]};
end
else
VAR4 <= {8'b0,VAR3[7:0]};
end
else begin
VAR4 <= VAR3;
end
end
always @* begin
VAR14 <= VAR9;
end
reg [15:0] VAR15[0:2**16-1]; | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_hdmi_tx/axi_hdmi_tx_alt.v | 8,991 | module MODULE1 (
VAR34,
VAR60,
VAR69,
VAR6,
VAR15,
VAR20,
VAR26,
VAR56,
VAR58,
VAR18,
VAR53,
VAR28,
VAR52,
VAR70,
VAR37,
VAR63,
VAR49,
VAR1,
VAR68,
VAR51,
VAR38,
VAR50,
VAR21,
VAR72,
VAR55,
VAR13,
VAR33,
VAR45,
VAR30,
VAR19,
VAR36,
VAR54,
VAR29,
VAR74,
VAR48,
VAR67,
VAR8,
VAR41,
VAR47,
VAR46,
VAR5,
VAR22,
VAR14,
VAR2,
VAR17,
VAR27,
VAR73,
VAR61,
VAR57,
VAR59,
VAR42,
VAR12,
VAR65,
VAR10,
VAR75,
VAR71,
VAR62,
VAR39,
VAR31);
parameter VAR66 = 0;
parameter VAR7 = 3;
parameter VAR11 = 0;
parameter VAR4 = 0;
parameter VAR16 = 0;
input VAR34;
output VAR60;
output VAR69;
output VAR6;
output VAR15;
output [15:0] VAR20;
output [15:0] VAR26;
output VAR56;
output VAR58;
output VAR18;
output [23:0] VAR53;
output VAR28;
output VAR52;
output VAR70;
output [35:0] VAR37;
input VAR63;
input VAR49;
input [63:0] VAR1;
output VAR68;
input VAR51;
input VAR38;
input [ 3:0] VAR50;
input VAR21;
input VAR72;
input VAR55;
input [13:0] VAR13;
input [(VAR7-1):0] VAR33;
input [ 7:0] VAR45;
input [ 2:0] VAR30;
input [ 1:0] VAR19;
input [ 0:0] VAR36;
input [ 3:0] VAR54;
input [ 2:0] VAR29;
output VAR74;
input VAR48;
input [31:0] VAR67;
input [ 3:0] VAR8;
input VAR41;
output VAR47;
output VAR46;
output [ 1:0] VAR5;
output [(VAR7-1):0] VAR22;
input VAR14;
input VAR2;
input [13:0] VAR17;
input [(VAR7-1):0] VAR27;
input [ 7:0] VAR73;
input [ 2:0] VAR61;
input [ 1:0] VAR57;
input [ 0:0] VAR59;
input [ 3:0] VAR42;
input [ 2:0] VAR12;
output VAR65;
output VAR10;
output [ 1:0] VAR75;
output [31:0] VAR71;
output [(VAR7-1):0] VAR62;
output VAR39;
input VAR31;
wire VAR9;
assign VAR22 = VAR33;
assign VAR62 = VAR27;
assign VAR39 = 1'd0;
VAR35 #(
.VAR66 (VAR66),
.VAR4 (VAR4),
.VAR11 (VAR11),
.VAR16 (VAR16))
VAR24 (
.VAR34 (VAR34),
.VAR60 (VAR60),
.VAR69 (VAR69),
.VAR6 (VAR6),
.VAR15 (VAR15),
.VAR20 (VAR20),
.VAR26 (VAR26),
.VAR56 (VAR56),
.VAR58 (VAR58),
.VAR18 (VAR18),
.VAR53 (VAR53),
.VAR28 (VAR28),
.VAR52 (VAR52),
.VAR70 (VAR70),
.VAR37 (VAR37),
.VAR23 (VAR63),
.VAR43 (VAR9),
.VAR25 (VAR9),
.VAR40 (VAR49),
.VAR64 (VAR1),
.VAR32 (8'hff),
.VAR44 (VAR38),
.VAR3 (VAR68),
.VAR21 (VAR21),
.VAR72 (VAR72),
.VAR55 (VAR55),
.VAR13 ({18'd0, VAR13}),
.VAR74 (VAR74),
.VAR48 (VAR48),
.VAR67 (VAR67),
.VAR8 (VAR8),
.VAR47 (VAR47),
.VAR46 (VAR46),
.VAR5 (VAR5),
.VAR14 (VAR14),
.VAR2 (VAR2),
.VAR17 ({18'd0, VAR17}),
.VAR65 (VAR65),
.VAR10 (VAR10),
.VAR75 (VAR75),
.VAR71 (VAR71),
.VAR31 (VAR31));
endmodule | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_coarse_delay_tuner.v | 2,344 | module MODULE1
(input VAR12
, input [1:0] VAR18
, input VAR24
, input VAR14
, output VAR29
, output VAR5
);
wire [1:0] VAR31;
wire [8:0] VAR6;
assign VAR6[0] = VAR12;
VAR34 VAR32 (.VAR16(VAR6[0]), .VAR17(VAR6[1]) );
VAR34 VAR37 (.VAR16(VAR6[1]), .VAR17(VAR6[2]) );
VAR39 VAR44 (.VAR16(VAR6[1]), .VAR17() );
VAR34 VAR43 (.VAR16(VAR6[2]), .VAR17(VAR6[3]) );
VAR34 VAR9 (.VAR16(VAR6[3]), .VAR17(VAR6[4]) );
VAR39 VAR27 (.VAR16(VAR6[3]), .VAR17() );
VAR34 VAR38 (.VAR16(VAR6[4]), .VAR17(VAR6[5]) );
VAR34 VAR30 (.VAR16(VAR6[5]), .VAR17(VAR6[6]) );
VAR39 VAR23 (.VAR16(VAR6[5]), .VAR17() );
VAR34 VAR36 (.VAR16(VAR6[6]), .VAR17(VAR6[7]) );
VAR34 VAR25 (.VAR16(VAR6[7]), .VAR17(VAR6[8]) );
VAR41 VAR21 ( .VAR15(VAR6[6]) ,.VAR32(VAR6[4]) ,.VAR37(VAR6[2]) ,.VAR43(VAR6[0])
,.VAR19(VAR31[0])
,.VAR42(VAR31[1])
,.VAR17 (VAR29 )
);
wire [1:0] VAR8;
VAR7 VAR2 (.VAR35(VAR8[0]), .VAR3(VAR29), .VAR26(VAR14), .VAR20(VAR31[0]), .VAR40());
VAR22 VAR13 (.VAR15(VAR31[0]),.VAR32(VAR18[0]),.VAR4(VAR24), .VAR28(VAR8[0]));
VAR7 VAR33 (.VAR35(VAR8[1]), .VAR3(VAR29), .VAR26(VAR14), .VAR20(VAR31[1]), .VAR40());
VAR22 VAR11 (.VAR15(VAR31[1]),.VAR32(VAR18[1]),.VAR4(VAR24), .VAR28(VAR8[1]));
VAR10 VAR1 (.VAR16(VAR24), .VAR28(VAR5));
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn.symbol.v | 1,341 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR5
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | ComWithCC3200.v | 1,598 | module MODULE1(
input VAR6,
input VAR1,
output reg VAR8,
input VAR2,
input VAR13,
output reg [7:0] VAR12, output reg VAR10,
output reg [1:0] VAR14,
output reg [5:0] VAR9,
input [7:0] VAR4,
output reg [8:0] VAR11
);
reg [15:0] VAR5;
reg [3:0] VAR7;
reg [7:0] VAR3;
always @(posedge VAR6 or negedge VAR1 ) begin
if(~VAR1) begin
VAR12 <= VAR5[7:0];
VAR14 <= VAR5[15:14];
VAR9 <= VAR5[13:8];
end
else begin
if(VAR11 == 9'd1 ) begin VAR5[15:8] <={VAR5[14:8],VAR2};
end
else if(VAR11 == 9'd2 ) begin VAR5[7:0] <={VAR5[6:0],VAR2} ;
end
end
end
always @(negedge VAR6 or negedge VAR1 ) begin
if(~VAR1) begin
VAR7 <= 8'd0;
VAR3 <=VAR4; end
else begin
if(~VAR13) begin VAR7 <= VAR7 + 1'b1;
VAR8 <= VAR3[7];
VAR3 <= VAR3 <<1;
end
end
end
always @(posedge VAR1 or posedge VAR13) begin
if(VAR13) begin
VAR11 <= 9'd0;
end
else begin
VAR11 <= VAR11 + 1'b1;
end
end
endmodule | mit |
kkalavantavanich/SD2017 | crcGenerator.v | 1,363 | /* VAR13 VAR3 VAR27 VAR11 VAR6 VAR9 VAR17.
* VAR22 VAR29 VAR10 use/VAR2/VAR5 in VAR16 VAR24 VAR4 this VAR8 VAR20 VAR7 VAR23 VAR1.
* VAR14: VAR18:VAR30 1ns / 1ps
module MODULE1
input VAR21,
input clk,
input VAR19,
input enable, input [VAR15:0] VAR28,
output reg [VAR15 - 1:0] VAR26
);
wire VAR12;
assign VAR12 = VAR21 ^ VAR26[VAR15 - 1];
integer VAR25 = 0;
always @ (posedge clk) begin
if (VAR19) begin
VAR26 = 0;
end
else if (enable) begin
for (VAR25 = VAR15 - 1; VAR25 > 0; VAR25 = VAR25 - 1) begin
VAR26[VAR25] = VAR26[VAR25 - 1] ^ (VAR12 & VAR28[VAR25]);
end
VAR26[0] = VAR12;
end
end
endmodule | mit |
alexforencich/xfcp | lib/i2c/rtl/i2c_slave_wbm.v | 16,847 | module MODULE1 #
(
parameter VAR29 = 4,
parameter VAR19 = 32, parameter VAR27 = 32, parameter VAR18 = (VAR19/8) )
(
input wire clk,
input wire rst,
input wire VAR20,
output wire VAR15,
output wire VAR16,
input wire VAR25,
output wire VAR30,
output wire VAR6,
output wire [VAR27-1:0] VAR14, input wire [VAR19-1:0] VAR5, output wire [VAR19-1:0] VAR11, output wire VAR7, output wire [VAR18-1:0] VAR4, output wire VAR22, input wire VAR10, input wire VAR23, output wire VAR28,
output wire VAR3,
output wire VAR24,
output wire VAR9,
input wire enable,
input wire [6:0] VAR12
);
parameter VAR2 = VAR27 - VAR13(VAR18);
parameter VAR26 = VAR18;
parameter VAR21 = VAR19/VAR26;
parameter VAR8 = VAR13(VAR21/8);
parameter VAR1 = VAR27+VAR8;
parameter VAR17 = (VAR1+7)/8; | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_sitofp_double.v | 25,893 | module MODULE1
(
VAR5,
VAR9,
VAR14,
VAR13,
VAR17,
VAR7) ;
input VAR5;
input VAR9;
input VAR14;
input [31:0] VAR13;
input [4:0] VAR17;
output [31:0] VAR7;
tri0 VAR5;
tri1 VAR9;
tri0 VAR14;
reg [1:0] VAR15;
reg [31:0] VAR16;
reg [31:0] VAR3;
reg VAR12;
reg VAR6;
wire [5:0] VAR8;
wire VAR2;
wire [15:0] VAR1;
wire [191:0] VAR11;
wire [4:0] VAR10;
wire [159:0] VAR4; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b.pp.symbol.v | 1,330 | module MODULE1 (
input VAR9 ,
input VAR3 ,
input VAR4 ,
input VAR5 ,
output VAR6 ,
input VAR2 ,
input VAR7,
input VAR8,
input VAR1
);
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/dbsm.v | 5,068 | module MODULE1
(input clk,
input reset,
input VAR9,
output VAR26,
output VAR13,
input VAR19,
output VAR1,
output VAR20,
input VAR24,
output VAR23,
output VAR15,
input VAR7,
input VAR6
);
localparam VAR5 = 0;
localparam VAR17 = 1;
localparam VAR2 = 2;
localparam VAR18 = 3;
reg [1:0] VAR21, VAR22, VAR11;
localparam VAR12 = 0;
localparam VAR16 = 1;
localparam VAR14 = 2;
localparam VAR25 = 3;
wire [1:0] VAR4[0:1];
always @(posedge clk)
if(reset | VAR9)
VAR21 <= VAR5;
else
case(VAR21)
VAR5 :
if(VAR4[0]==VAR12)
VAR21 <= VAR17;
VAR17 :
if(VAR19)
VAR21 <= VAR2;
VAR2 :
if(VAR4[1]==VAR12)
VAR21 <= VAR18;
VAR18 :
if(VAR19)
VAR21 <= VAR5;
endcase
assign VAR26 = (VAR21 == VAR17) | (VAR21 == VAR18);
assign VAR13 = (VAR21 == VAR18);
always @(posedge clk)
if(reset | VAR9)
VAR22 <= VAR5;
else
case(VAR22)
VAR5 :
if(VAR4[0]==VAR16)
VAR22 <= VAR17;
VAR17 :
if(VAR7)
VAR22 <= VAR2;
VAR2 :
if(VAR4[1]==VAR16)
VAR22 <= VAR18;
VAR18 :
if(VAR7)
VAR22 <= VAR5;
endcase
assign VAR23 = (VAR22 == VAR17) | (VAR22 == VAR18);
assign VAR15 = (VAR22 == VAR18);
always @(posedge clk)
if(reset | VAR9)
VAR11 <= VAR5;
else
case(VAR11)
VAR5 :
if(VAR4[0]==VAR14)
VAR11 <= VAR17;
VAR17 :
if(VAR24)
VAR11 <= VAR2;
VAR2 :
if(VAR4[1]==VAR14)
VAR11 <= VAR18;
VAR18 :
if(VAR24)
VAR11 <= VAR5;
endcase
assign VAR1 = (VAR11 == VAR17) | (VAR11 == VAR18);
assign VAR20 = (VAR11 == VAR18);
MODULE2 #(.VAR3(VAR17)) VAR10
(.clk(clk), .reset(reset), .VAR9(VAR9),
.VAR19(VAR19), .VAR7(VAR7), .VAR6(VAR6), .VAR24(VAR24),
.VAR21(VAR21), .VAR22(VAR22), .VAR11(VAR11),
.VAR4(VAR4[0]));
MODULE2 #(.VAR3(VAR18)) VAR8
(.clk(clk), .reset(reset), .VAR9(VAR9),
.VAR19(VAR19), .VAR7(VAR7), .VAR6(VAR6), .VAR24(VAR24),
.VAR21(VAR21), .VAR22(VAR22), .VAR11(VAR11),
.VAR4(VAR4[1]));
endmodule
module MODULE2
(input clk, input reset, input VAR9,
input VAR19, input VAR7, input VAR6, input VAR24,
input [1:0] VAR21, input [1:0] VAR22, input [1:0] VAR11,
output reg [1:0] VAR4);
localparam VAR12 = 0;
localparam VAR16 = 1;
localparam VAR14 = 2;
localparam VAR25 = 3;
always @(posedge clk)
if(reset | VAR9)
VAR4 <= VAR12;
else
case(VAR4)
VAR12 :
if(VAR19 & (VAR21 == VAR3))
VAR4 <= VAR16;
VAR16 :
if(VAR7 & (VAR22 == VAR3))
if(VAR6)
VAR4 <= VAR12;
else
VAR4 <= VAR14;
VAR14 :
if(VAR24 & (VAR11 == VAR3))
VAR4 <= VAR12;
VAR25 :
;
endcase
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v | 3,948 | module MODULE1 # (
parameter VAR7 = "VAR2",
parameter VAR11 = 0
)
(
input wire VAR10,
input wire VAR5,
output VAR3
);
parameter VAR1 = 1;
localparam VAR6 = (VAR7 == "VAR2") ? ((VAR11 == 1) ? 20: (VAR11 == 0) ? 20 : 21) : 2;
reg [7:0] VAR12;
reg [7:0] VAR4;
reg [7:0] VAR9;
wire [23:0] VAR8;
assign VAR8 = {VAR9, VAR4, VAR12};
always @(posedge VAR10 or negedge VAR5) begin
if (!VAR5) begin
end else begin
if (VAR3 != 1'b1) begin
end
end
end
assign VAR3 = VAR8[VAR6];
endmodule | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq_tag_slice.v | 4,255 | module MODULE1(
VAR17,
VAR6, VAR5, VAR8, VAR9, VAR12,
VAR14
);
input VAR6;
input VAR5;
input [VAR3-1:0] VAR8;
input VAR9;
input [VAR3-1:0] VAR12;
input VAR14;
output VAR17;
wire VAR17;
wire [VAR3-1:0] VAR15;
wire [VAR3-1:0] VAR1;
reg VAR18;
reg VAR19;
wire VAR16;
always @ ( VAR17 or VAR15 or VAR8) begin
if(VAR15 == VAR8)
VAR19 = 1'b1;
end
else
VAR19 = VAR17;
end
always @ ( VAR9 or VAR19 or VAR14) begin
if (VAR14)
VAR18 = VAR9;
end
else
VAR18 = VAR19;
end
assign VAR16 = VAR14;
assign VAR1 = VAR12;
VAR10 #(1) VAR4
(.din(VAR18),
.clk(VAR6),
.VAR7(VAR5),
.VAR11(VAR17)
);
VAR13 #(VAR3) VAR2
(.din(VAR1),
.clk(VAR6),
.en(VAR16),
.VAR7(VAR5),
.VAR11(VAR15)
);
endmodule | gpl-2.0 |
egyp7/mor1kx | bench/verilog/mor1kx_monitor.v | 24,926 | module MODULE1 #(parameter VAR11= "../out") ();
integer VAR1 = 0;
integer VAR10 = 0;
integer VAR4 = 0;
wire clk;
parameter VAR7 = 32;
reg VAR9;
VAR3 VAR9 = ("VAR6");
reg VAR2;
VAR3 VAR2 = ("VAR5");
assign clk = VAR12;
reg [63:0] VAR8 = 0 ;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | mpl-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_mul_frac_dp.v | 15,083 | module MODULE1 (
VAR36,
VAR86,
VAR39,
VAR8,
VAR7,
VAR98,
VAR41,
VAR54,
VAR59,
VAR89,
VAR4,
VAR20,
VAR48,
VAR22,
VAR13,
VAR57,
VAR30,
VAR83,
VAR88,
VAR53,
VAR60,
VAR34,
VAR35,
VAR74,
VAR16,
VAR84,
VAR50,
VAR97,
VAR31,
VAR11,
VAR23,
VAR28,
VAR19,
VAR46,
VAR32,
VAR26,
VAR91,
VAR61,
VAR17,
VAR87,
VAR37,
VAR71,
VAR75,
VAR95,
VAR82,
VAR81,
VAR73,
VAR51,
VAR77,
VAR5,
VAR42
);
input [54:0] VAR36; input [54:0] VAR86; input VAR39; input VAR8; input VAR7; input VAR98; input VAR41; input VAR54; input VAR59; input VAR89; input VAR4; input VAR20; input VAR48; input VAR22; input VAR13; input VAR57; input VAR30; input VAR83; input VAR88; input VAR53; input VAR60; input [105:0] VAR34; input [5:0] VAR35; input [6:0] VAR74; input VAR16; input VAR84; input VAR50; input VAR97; input VAR31; input VAR11; input VAR23; input VAR28; input VAR19; input VAR46;
output [52:0] VAR32; output [52:0] VAR26; output [5:0] VAR91; output [5:0] VAR61; output VAR17; output [6:0] VAR87; output VAR37; output VAR71; output [32:0] VAR75; output VAR95; output VAR82; output VAR81; output VAR73; output [51:0] VAR51;
input VAR77; input VAR5; output VAR42;
wire [54:0] VAR56;
wire [54:0] VAR67;
wire [52:0] VAR27;
wire [52:0] VAR32;
wire [52:0] VAR21;
wire [52:0] VAR26;
wire [52:0] VAR18;
wire [5:0] VAR91;
wire [52:0] VAR24;
wire [5:0] VAR61;
wire VAR17;
wire [5:0] VAR90;
wire [5:0] VAR64;
wire [5:0] VAR49;
wire [6:0] VAR87;
wire [168:63] VAR66;
wire [55:0] VAR58;
wire VAR37;
wire VAR71;
wire [168:0] VAR72;
wire [55:0] VAR12;
wire [54:0] VAR14;
wire [54:0] VAR85;
wire [54:0] VAR3;
wire [54:0] VAR94;
wire [54:0] VAR55;
wire [54:0] VAR93;
wire [54:0] VAR33;
wire [54:0] VAR79;
wire [54:33] VAR69;
wire [32:0] VAR75;
wire [54:3] VAR9;
wire [54:0] VAR40;
wire VAR95;
wire VAR82;
wire VAR81;
wire [52:0] VAR62;
wire VAR73;
wire [51:0] VAR10;
wire [51:0] VAR63;
wire [51:0] VAR51;
wire [30:0] VAR65;
wire sel;
assign sel = ~VAR77;
VAR38 VAR80 (
.clk(clk),
.VAR46(VAR46),
.VAR45(VAR19),
.VAR29(sel)
);
VAR92 #(55) VAR15 (
.din (VAR36[54:0]),
.en (VAR39),
.clk (clk),
.VAR6 (VAR56[54:0]),
.VAR77 (VAR77),
.VAR5 (),
.VAR42 ()
);
VAR92 #(55) VAR96 (
.din (VAR86[54:0]),
.en (VAR39),
.clk (clk),
.VAR6 (VAR67[54:0]),
.VAR77 (VAR77),
.VAR5 (),
.VAR42 ()
);
assign VAR27[52:0]= ({53{VAR8}}
& {1'b1, (VAR56[51] || VAR59),
VAR56[50:0]})
| ({53{VAR7}}
& {VAR56[51:0], 1'b0})
| ({53{VAR98}}
& {1'b1, (VAR56[54] || VAR89),
VAR56[53:32], 29'b0})
| ({53{VAR41}}
& {VAR56[54:32], 30'b0})
| ({53{VAR54}}
& 53'h10000000000000);
assign VAR32[52:0]= (~VAR27[52:0]);
assign VAR21[52:0]= ({53{VAR4}}
& {1'b1, (VAR67[51] || VAR57),
VAR67[50:0]})
| ({53{VAR20}}
& {VAR67[51:0], 1'b0})
| ({53{VAR48}}
& {1'b1, (VAR67[54] || VAR30),
VAR67[53:32], 29'b0})
| ({53{VAR22}}
& {VAR67[54:32], 30'b0})
| ({53{VAR13}}
& {1'b1, {23{VAR83}},
{29{VAR88}}});
assign VAR26[52:0]= VAR21[52:0];
assign VAR18[52:0]= ({53{VAR60}}
& {VAR56[54:32], 30'b0})
| ({53{VAR53}}
& {VAR56[51:0], 1'b0});
VAR47 VAR43 (
.din (VAR18[52:0]),
.VAR44 (VAR91[5:0])
);
assign VAR24[52:0]= ({53{VAR60}}
& {VAR67[54:32], 30'b0})
| ({53{VAR53}}
& {VAR67[51:0], 1'b0});
VAR47 VAR1 (
.din (VAR24[52:0]),
.VAR44 (VAR61[5:0])
);
assign VAR17= VAR34[105];
VAR92 #(56) VAR25 (
.din ({{6{VAR35[5]}},
{6{VAR35[4]}},
VAR35[5:0],
VAR74[6:0],
31'h00000000}),
.en (VAR39),
.clk (clk),
.VAR6 ({VAR90[5:0],
VAR64[5:0],
VAR49[5:0],
VAR87[6:0],
VAR65[30:0]}),
.VAR77 (VAR77),
.VAR5 (),
.VAR42 ()
);
assign VAR66[168:63]= VAR34[105:0]
<< {VAR90[0], VAR49[4:0]};
assign VAR58[55:0]= {VAR66[168:114], (|VAR66[113:63])};
assign VAR37= VAR58[54];
assign VAR71= VAR58[55];
assign VAR72[168:0]= { VAR34[105:0], 63'b0} >> VAR49[5:0];
assign VAR12[55:0]= {VAR72[168:114], (|VAR72[113:0])};
assign VAR14[54:0]= ~(({55{(VAR16 && VAR58[55])}}
& VAR58[54:0])
| ({55{(!VAR39)}}
& VAR40[54:0]));
VAR52 #(55) VAR68 (
.din (VAR14[54:0]),
.clk (clk),
.VAR6 (VAR85[54:0]),
.VAR77 (VAR77),
.VAR5 (),
.VAR42 ()
);
assign VAR3[54:0]= ~({55{(VAR16
&& (!VAR58[55]))}}
& {VAR58[53:0], 1'b0});
VAR52 #(55) VAR70 (
.din (VAR3[54:0]),
.clk (clk),
.VAR6 (VAR94[54:0]),
.VAR77 (VAR77),
.VAR5 (),
.VAR42 ()
);
assign VAR55[54:0]= ~({55{(VAR84
&& VAR12[55])}}
& VAR12[54:0]);
VAR52 #(55) VAR2 (
.din (VAR55[54:0]),
.clk (clk),
.VAR6 (VAR93[54:0]),
.VAR77 (VAR77),
.VAR5 (),
.VAR42 ()
);
assign VAR33[54:0]= ~({55{(VAR84
&& (!VAR12[55]))}}
& {VAR12[53:0], 1'b0});
VAR52 #(55) VAR76 (
.din (VAR33[54:0]),
.clk (clk),
.VAR6 (VAR79[54:0]),
.VAR77 (VAR77),
.VAR5 (),
.VAR42 ()
);
assign {VAR69[54:33], VAR75[32:0]} = ~(VAR85[54:0]
& VAR94[54:0]
& VAR93[54:0]
& VAR79[54:0]);
assign VAR9[54:3]= {VAR69[54:33], VAR75[32:3]};
assign VAR40[54:0]= {VAR69[54:33], VAR75[32:0]};
assign VAR95= (|VAR40[2:0]);
assign VAR82= VAR95 || (|VAR40[31:3]);
assign VAR81= VAR82 || (|VAR40[54:32]);
assign VAR62[52:0]= {1'b0, VAR9[54:3]}
+ {23'b0, VAR50, 28'b0, VAR97};
assign VAR73= VAR62[52];
assign VAR10[51:0]= VAR62[51:0];
assign VAR63[51:0]= ({52{VAR31}}
& VAR10[51:0])
| ({52{VAR11}}
& VAR40[54:3])
| ({52{VAR23}}
& {52{VAR28}});
VAR92 #(52) VAR78 (
.din (VAR63[51:0]),
.en (VAR39),
.clk (clk),
.VAR6 (VAR51[51:0]),
.VAR77 (VAR77),
.VAR5 (),
.VAR42 ()
);
endmodule | gpl-3.0 |
fredmorcos/attic | projects/vo-tools/machines/sbn-machine/fast-mul/sbn.v | 3,406 | module MODULE1 (clk, state, VAR17, VAR9, VAR8);
parameter VAR7 = 8; parameter VAR26 = 32;
input clk;
output [2:0] state;
output [VAR7-1:0] VAR17;
output [VAR26-1:0] VAR9, VAR8;
parameter VAR29 = 4 * VAR7;
reg [VAR29-1:0] VAR4[0:((1<<VAR7)-1)];
reg [VAR26-1:0] VAR14[0:((1<<VAR7)-1)];
reg [VAR26-1:0] VAR6, VAR22;
reg [VAR7-1:0] VAR17;
reg [VAR29-1:0] VAR2;
wire [VAR29-1:0] VAR23;
wire [VAR26-1:0] VAR11, VAR19;
wire [VAR7-1:0] addr, VAR16, VAR27, VAR25, VAR3, VAR28;
wire VAR31, VAR21;
reg [1:0] VAR10;
reg [2:0] state, VAR1;
parameter VAR15 = 3'b000;
parameter VAR13 = 3'b001;
parameter VAR5 = 3'b010;
parameter VAR20 = 3'b011;
parameter VAR12 = 3'b100;
parameter VAR30 = 3'b101;
parameter VAR18 = 3'b111;
assign VAR23 = VAR4[VAR17];
assign VAR11 = VAR14[addr];
assign VAR9 = VAR6; assign VAR8 = VAR22;
assign VAR19 = VAR6 - VAR22;
assign VAR31 = VAR19[VAR26-1];
assign VAR16 = VAR17 + 1;
assign VAR27 = VAR2[(4*VAR7-1):(3*VAR7)];
assign VAR25 = VAR2[(3*VAR7-1):(2*VAR7)];
assign VAR3 = VAR2[(2*VAR7-1):VAR7];
assign VAR28 = VAR2[VAR7-1:0];
assign VAR21 = (VAR3 == ~{VAR7{1'b0}}) ? 1 : 0;
assign addr = (VAR10 == 2'b00) ? VAR27 : ((VAR10 == 2'b01) ? VAR25 : VAR3);
integer VAR24;
always @ (posedge clk)
case (state) VAR15: begin
VAR2 <= VAR23;
VAR10 <= 2'b00;
end
VAR13: begin
VAR6 <= VAR11;
VAR10 <= 2'b01;
end
VAR5: begin
VAR22 <= VAR11;
VAR10 <= 2'b10;
end
VAR20: VAR14[addr] <= VAR19;
VAR12: VAR17 <= VAR28;
VAR30: VAR17 <= VAR16;
VAR18: begin
for (VAR24=0; VAR24<16; VAR24=VAR24+1)
end
endcase
always @ (posedge clk)
state <= VAR1;
always @ (state or VAR31 or VAR21)
case (state)
VAR15: VAR1 = VAR13;
VAR13: VAR1 = VAR5;
VAR5: if (VAR21 ) VAR1 = VAR18;
else VAR1 = VAR20;
VAR20: if (VAR31) VAR1 = VAR12;
else VAR1 = VAR30;
default: VAR1 = VAR15;
endcase
begin | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3.pp.symbol.v | 1,357 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR5 ,
input VAR6,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
ppnipuna/EDAC_ASIC_Design | rtl/encoder.v | 1,874 | module MODULE1 #(parameter VAR10 = 128, VAR11 = 9)
(VAR18, VAR2,VAR17, clk,
VAR4, VAR9);
parameter VAR3 = VAR10;
parameter VAR5 = VAR11;
input wire clk, VAR17, VAR2;
input wire [VAR3:1] VAR18;
output reg [VAR3:1] VAR4; output reg [VAR5:1] VAR9;
reg [VAR3:1] VAR1;
reg [VAR5:1] VAR6;
reg VAR13;
always @(posedge clk or negedge VAR17) begin
if(~VAR17) begin
VAR1 <= 'd0;
VAR13 <= 'd0;
VAR4 <= 'd0;
VAR9 <= 'd0;
end
else if(VAR2) begin
VAR13 <= VAR2;
VAR1 <= VAR18;
if(VAR13) begin VAR4 <= VAR1;
VAR9 <= VAR6;
end
end
end
reg [VAR3+VAR5-1:1] VAR12; integer VAR7,VAR15,VAR16,VAR8;
reg VAR14;
always @(VAR1) begin
VAR15 = 1; VAR16 = 1;
while ( (VAR15<VAR3+VAR5) || (VAR16<=VAR3)) begin
if ( VAR15 == ((~VAR15+1)&VAR15)) begin VAR12[VAR15] = 1'b0;
VAR15 = VAR15+1;
end
else begin
VAR12[VAR15] = VAR1[VAR16];
VAR15 = VAR15+1; VAR16 = VAR16+1;
end
end
for(VAR7=1;VAR7<VAR5;VAR7=VAR7+1) begin
VAR8 = 1;
VAR14 = VAR8[VAR7-1] & VAR12[1];
for(VAR8=2;VAR8<(VAR3+VAR5);VAR8=VAR8+1) begin
VAR14 = VAR14 ^ (VAR12[VAR8] & VAR8[VAR7-1]);
end
VAR6[VAR7] = VAR14;
end
VAR6[VAR5] = (^VAR6[VAR5-1:1])^(^VAR12); end
endmodule | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_SRAM_FF_210930.v | 231,432 | module MODULE1 (VAR1, VAR4, VAR7, VAR10, VAR6);
output VAR1;
input VAR4, VAR7, VAR10, VAR6;
wire VAR5, VAR8, VAR11;
wire VAR9, VAR3, VAR2;
not (VAR9, VAR6);
not (VAR11, VAR10);
not (VAR8, VAR7);
and (VAR3, VAR8, VAR11);
not (VAR5, VAR4);
and (VAR2, VAR5, VAR11);
or (VAR1, VAR2, VAR3, VAR9); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbn/sky130_fd_sc_hd__dlrbn.blackbox.v | 1,405 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR9,
VAR1 ,
VAR7
);
output VAR5 ;
output VAR2 ;
input VAR9;
input VAR1 ;
input VAR7 ;
supply1 VAR4;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlrtp/sky130_fd_sc_lp__srdlrtp.symbol.v | 1,440 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR10,
input VAR4 ,
input VAR5
);
supply1 VAR9;
supply1 VAR2 ;
supply0 VAR3 ;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/SHD.v | 25,957 | module MODULE1 #(parameter VAR9 = 200) (
VAR11,
VAR1,
VAR26
);
input [VAR9-1:0] VAR11, VAR1;
reg [(VAR9/2)-1:0] VAR19, VAR8, VAR15, VAR31, VAR10, VAR18, VAR12, VAR16, VAR28, VAR2, VAR4, VAR24;
output reg [7:0] VAR26;
reg [VAR9-1:0] VAR13, VAR30, VAR17, VAR3, VAR25, VAR29, VAR20, VAR14, VAR27, VAR5, VAR6;
integer VAR22, VAR21;
reg [2:0] VAR7 = 3'b101;
reg [7:0] VAR23;
always@* begin
VAR13= VAR1 ^ VAR11;
VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR13[VAR21] || VAR13[VAR21+1])
end
VAR19[VAR22] = 1'b1; else
VAR19[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR23=0;
for (VAR21=0; VAR21<(VAR9/2); VAR21=VAR21+1)
begin
if (VAR19[VAR21]== 1'b1)
VAR23 = VAR23+1;
end
if (VAR23 <= VAR7)
VAR26 = 8'b11111111;
else
begin
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR19[VAR21] && (~VAR19[VAR21+1]) && VAR19[VAR21+2])
VAR19[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR19[VAR21] && (~VAR19[VAR21+1]) && (~VAR19[VAR21+2]) && VAR19[VAR21+3])
begin
VAR19[VAR21+1] = 1'b1;
VAR19[VAR21+2] = 1'b1;
end
end
end
VAR30= VAR1 ^ (VAR11<<2); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR30[VAR21] || VAR30[VAR21+1])
end
VAR8[VAR22] = 1'b1; else
VAR8[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR8[0]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR8[VAR21] && (~VAR8[VAR21+1]) && VAR8[VAR21+2])
VAR8[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR8[VAR21] && (~VAR8[VAR21+1]) && (~VAR8[VAR21+2]) && VAR8[VAR21+3])
begin
VAR8[VAR21+1] = 1'b1;
VAR8[VAR21+2] = 1'b1;
end
end
end
VAR17= VAR1 ^ (VAR11<<4); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR17[VAR21] || VAR17[VAR21+1])
end
VAR15[VAR22] = 1'b1; else
VAR15[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR15[0]=1'b0; VAR15[1]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR15[VAR21] && (~VAR15[VAR21+1]) && VAR15[VAR21+2])
VAR15[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR15[VAR21] && (~VAR15[VAR21+1]) && (~VAR15[VAR21+2]) && VAR15[VAR21+3])
begin
VAR15[VAR21+1] = 1'b1;
VAR15[VAR21+2] = 1'b1;
end
end
end
VAR29= VAR1 ^ (VAR11<<6); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR29[VAR21] || VAR29[VAR21+1])
end
VAR31[VAR22] = 1'b1; else
VAR31[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR31[0]=1'b0; VAR31[1]=1'b0; VAR31[2]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR31[VAR21] && (~VAR31[VAR21+1]) && VAR31[VAR21+2])
VAR31[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR31[VAR21] && (~VAR31[VAR21+1]) && (~VAR31[VAR21+2]) && VAR31[VAR21+3])
begin
VAR31[VAR21+1] = 1'b1;
VAR31[VAR21+2] = 1'b1;
end
end
end
VAR20= VAR1 ^ (VAR11<<8); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR20[VAR21] || VAR20[VAR21+1])
end
VAR10[VAR22] = 1'b1; else
VAR10[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR10[0]=1'b0; VAR10[1]=1'b0; VAR10[2]=1'b0; VAR10[3]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR10[VAR21] && (~VAR10[VAR21+1]) && VAR10[VAR21+2])
VAR10[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR10[VAR21] && (~VAR10[VAR21+1]) && (~VAR10[VAR21+2]) && VAR10[VAR21+3])
begin
VAR10[VAR21+1] = 1'b1;
VAR10[VAR21+2] = 1'b1;
end
end
end
VAR14= VAR1 ^ (VAR11<<10); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR14[VAR21] || VAR14[VAR21+1])
end
VAR18[VAR22] = 1'b1; else
VAR18[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR18[0]=1'b0; VAR18[1]=1'b0; VAR18[2]=1'b0; VAR18[3]=1'b0; VAR18[4]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR18[VAR21] && (~VAR18[VAR21+1]) && VAR18[VAR21+2])
VAR18[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR18[VAR21] && (~VAR18[VAR21+1]) && (~VAR18[VAR21+2]) && VAR18[VAR21+3])
begin
VAR18[VAR21+1] = 1'b1;
VAR18[VAR21+2] = 1'b1;
end
end
end
VAR3= VAR1 ^ (VAR11>>2); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR3[VAR21] || VAR3[VAR21+1])
end
VAR12[VAR22] = 1'b1; else
VAR12[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR12[(VAR9/2)-1]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR12[VAR21] && (~VAR12[VAR21+1]) && VAR12[VAR21+2])
VAR12[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR12[VAR21] && (~VAR12[VAR21+1]) && (~VAR12[VAR21+2]) && VAR12[VAR21+3])
begin
VAR12[VAR21+1] = 1'b1;
VAR12[VAR21+2] = 1'b1;
end
end
end
VAR25= VAR1 ^ (VAR11>>4); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR25[VAR21] || VAR25[VAR21+1])
end
VAR16[VAR22] = 1'b1; else
VAR16[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR16[(VAR9/2)-1]=1'b0; VAR16[(VAR9/2)-2]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR16[VAR21] && (~VAR16[VAR21+1]) && VAR16[VAR21+2])
VAR16[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR16[VAR21] && (~VAR16[VAR21+1]) && (~VAR16[VAR21+2]) && VAR16[VAR21+3])
begin
VAR16[VAR21+1] = 1'b1;
VAR16[VAR21+2] = 1'b1;
end
end
end
VAR27= VAR1 ^ (VAR11>>6); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR27[VAR21] || VAR27[VAR21+1])
end
VAR28[VAR22] = 1'b1; else
VAR28[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR28[(VAR9/2)-1]=1'b0; VAR28[(VAR9/2)-2]=1'b0; VAR28[(VAR9/2)-3]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR28[VAR21] && (~VAR28[VAR21+1]) && VAR28[VAR21+2])
VAR28[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR28[VAR21] && (~VAR28[VAR21+1]) && (~VAR28[VAR21+2]) && VAR28[VAR21+3])
begin
VAR28[VAR21+1] = 1'b1;
VAR28[VAR21+2] = 1'b1;
end
end
end
VAR5= VAR1 ^ (VAR11>>8); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR5[VAR21] || VAR5[VAR21+1])
end
VAR2[VAR22] = 1'b1; else
VAR2[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR2[(VAR9/2)-1]=1'b0; VAR2[(VAR9/2)-2]=1'b0; VAR2[(VAR9/2)-3]=1'b0; VAR2[(VAR9/2)-4]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR2[VAR21] && (~VAR2[VAR21+1]) && VAR2[VAR21+2])
VAR2[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR2[VAR21] && (~VAR2[VAR21+1]) && (~VAR2[VAR21+2]) && VAR2[VAR21+3])
begin
VAR2[VAR21+1] = 1'b1;
VAR2[VAR21+2] = 1'b1;
end
end
end
VAR6= VAR1 ^ (VAR11>>10); VAR22=0;
for (VAR21 = 0; VAR21 < VAR9; VAR21 = VAR21 + 2)
begin
if(VAR6[VAR21] || VAR6[VAR21+1])
end
VAR4[VAR22] = 1'b1; else
VAR4[VAR22] = 1'b0; VAR22=VAR22+1;
end
VAR4[(VAR9/2)-1]=1'b0; VAR4[(VAR9/2)-2]=1'b0; VAR4[(VAR9/2)-3]=1'b0; VAR4[(VAR9/2)-4]=1'b0; VAR4[(VAR9/2)-5]=1'b0;
for (VAR21 = 0; VAR21 < (VAR9/2)-1; VAR21 = VAR21 + 1)
begin
if (VAR21<=(VAR9/2)-3)
begin
if(VAR4[VAR21] && (~VAR4[VAR21+1]) && VAR4[VAR21+2])
VAR4[VAR21+1] = 1'b1;
end
if (VAR21<=(VAR9/2)-4)
begin
if(VAR4[VAR21] && (~VAR4[VAR21+1]) && (~VAR4[VAR21+2]) && VAR4[VAR21+3])
begin
VAR4[VAR21+1] = 1'b1;
VAR4[VAR21+2] = 1'b1;
end
end
end
VAR24= VAR19 & VAR8 & VAR15 & VAR31 & VAR10 & VAR18 & VAR12 & VAR16 & VAR28 & VAR2 & VAR4;
VAR23=0;
for (VAR21 = (VAR9/2)-1; VAR21 >0 ; VAR21 = VAR21 -4)
begin
if (VAR21>3)
begin
case ({VAR24[VAR21],VAR24[VAR21-1],VAR24[VAR21-2],VAR24[VAR21-3]})
4'b0000 : VAR23=VAR23+0;
4'b0101,4'b0110,4'b1001,4'b1010,4'b1011,4'b1101 : VAR23=VAR23+2;
4'b0001,4'b0010,4'b0011,4'b0100,4'b0111,4'b1000,4'b1100,4'b1110,4'b1111 : VAR23=VAR23+1;
endcase
end
end
if (VAR23 <= VAR7)
VAR26 = 8'b11111111;
else
VAR26 = 8'b00000000;
end end
endmodule | gpl-3.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_mux_enc.v | 9,821 | module MODULE1 #
(
parameter VAR23 = "VAR5",
parameter integer VAR33 = 4,
parameter integer VAR31 = 2,
parameter integer VAR27 = 1
)
(
input wire [VAR31-1:0] VAR15,
input wire [VAR33*VAR27-1:0] VAR8,
output wire [VAR27-1:0] VAR37,
input wire VAR36
);
wire [VAR27-1:0] VAR16;
genvar VAR24;
function [VAR27-1:0] VAR32
(
input [VAR31-1:0] VAR13,
input [VAR33*VAR27-1:0] VAR7
);
integer VAR14;
reg [VAR33*VAR27-1:0] VAR6;
begin
VAR6[VAR27-1:0] = {VAR27{(VAR13==0)?1'b1:1'b0}} & VAR7[VAR27-1:0];
for (VAR14=1;VAR14<VAR33;VAR14=VAR14+1) begin : VAR3
VAR6[VAR14*VAR27 +: VAR27] =
VAR6[(VAR14-1)*VAR27 +: VAR27] |
({VAR27{(VAR13==VAR14)?1'b1:1'b0}} & VAR7[VAR14*VAR27 +: VAR27]);
end
VAR32 = VAR6[VAR27*VAR33-1:VAR27*(VAR33-1)];
end
endfunction
function [VAR27-1:0] VAR4
(
input [1:0] VAR13,
input [4*VAR27-1:0] VAR7
);
integer VAR14;
reg [4*VAR27-1:0] VAR6;
begin
VAR6[VAR27-1:0] = {VAR27{(VAR13==0)?1'b1:1'b0}} & VAR7[VAR27-1:0];
for (VAR14=1;VAR14<4;VAR14=VAR14+1) begin : VAR3
VAR6[VAR14*VAR27 +: VAR27] =
VAR6[(VAR14-1)*VAR27 +: VAR27] |
({VAR27{(VAR13==VAR14)?1'b1:1'b0}} & VAR7[VAR14*VAR27 +: VAR27]);
end
VAR4 = VAR6[VAR27*4-1:VAR27*3];
end
endfunction
assign VAR37 = VAR16 & {VAR27{VAR36}};
generate
if ( VAR33 < 2 ) begin : VAR19
assign VAR16 = VAR8;
end else if ( VAR23 == "VAR5" || VAR33 < 5 ) begin : VAR34
assign VAR16 = VAR32(VAR15, VAR8);
end else begin : VAR2
wire [VAR27-1:0] VAR38;
wire [VAR27-1:0] VAR35;
wire [VAR27-1:0] VAR28;
wire [VAR27-1:0] VAR12;
wire [VAR27-1:0] VAR18;
wire [VAR27-1:0] VAR29;
case (VAR33)
1, 5, 9, 13:
assign VAR29 = VAR8[(VAR33-1)*VAR27 +: VAR27];
2, 6, 10, 14:
assign VAR29 = VAR15[0] ?
VAR8[(VAR33-1)*VAR27 +: VAR27] :
VAR8[(VAR33-2)*VAR27 +: VAR27] ;
3, 7, 11, 15:
assign VAR29 = VAR15[1] ?
VAR8[(VAR33-1)*VAR27 +: VAR27] :
(VAR15[0] ?
VAR8[(VAR33-2)*VAR27 +: VAR27] :
VAR8[(VAR33-3)*VAR27 +: VAR27] );
4, 8, 12, 16:
assign VAR29 = VAR15[1] ?
(VAR15[0] ?
VAR8[(VAR33-1)*VAR27 +: VAR27] :
VAR8[(VAR33-2)*VAR27 +: VAR27] ) :
(VAR15[0] ?
VAR8[(VAR33-3)*VAR27 +: VAR27] :
VAR8[(VAR33-4)*VAR27 +: VAR27] );
17:
assign VAR29 = VAR15[1] ?
(VAR15[0] ?
VAR8[15*VAR27 +: VAR27] :
VAR8[14*VAR27 +: VAR27] ) :
(VAR15[0] ?
VAR8[13*VAR27 +: VAR27] :
VAR8[12*VAR27 +: VAR27] );
default:
assign VAR29 = 0;
endcase
case (VAR33)
5, 6, 7, 8: begin
assign VAR38 = VAR4(VAR15[1:0], VAR8[0 +: 4*VAR27]);
for (VAR24 = 0; VAR24 < VAR27 ; VAR24 = VAR24 + 1) begin : VAR25
VAR11 VAR1
(
.VAR20 (VAR38[VAR24]),
.VAR30 (VAR29[VAR24]),
.VAR15 (VAR15[2]),
.VAR37 (VAR16[VAR24])
);
end
end
9, 10, 11, 12: begin
assign VAR28 = VAR4(VAR15[1:0], VAR8[0 +: 4*VAR27]);
assign VAR12 = VAR4(VAR15[1:0], VAR8[4*VAR27 +: 4*VAR27]);
for (VAR24 = 0; VAR24 < VAR27 ; VAR24 = VAR24 + 1) begin : VAR21
VAR11 VAR10
(
.VAR20 (VAR28[VAR24]),
.VAR30 (VAR12[VAR24]),
.VAR15 (VAR15[2]),
.VAR37 (VAR38[VAR24])
);
VAR17 VAR26
(
.VAR20 (VAR38[VAR24]),
.VAR30 (VAR29[VAR24]),
.VAR15 (VAR15[3]),
.VAR37 (VAR16[VAR24])
);
end
end
13,14,15,16: begin
assign VAR28 = VAR4(VAR15[1:0], VAR8[0 +: 4*VAR27]);
assign VAR12 = VAR4(VAR15[1:0], VAR8[4*VAR27 +: 4*VAR27]);
assign VAR18 = VAR4(VAR15[1:0], VAR8[8*VAR27 +: 4*VAR27]);
for (VAR24 = 0; VAR24 < VAR27 ; VAR24 = VAR24 + 1) begin : VAR39
VAR11 VAR10
(
.VAR20 (VAR28[VAR24]),
.VAR30 (VAR12[VAR24]),
.VAR15 (VAR15[2]),
.VAR37 (VAR38[VAR24])
);
VAR11 VAR22
(
.VAR20 (VAR18[VAR24]),
.VAR30 (VAR29[VAR24]),
.VAR15 (VAR15[2]),
.VAR37 (VAR35[VAR24])
);
VAR17 VAR26
(
.VAR20 (VAR38[VAR24]),
.VAR30 (VAR35[VAR24]),
.VAR15 (VAR15[3]),
.VAR37 (VAR16[VAR24])
);
end
end
17: begin
assign VAR28 = VAR15[4] ? VAR8[16*VAR27 +: VAR27] : VAR4(VAR15[1:0], VAR8[0 +: 4*VAR27]); assign VAR12 = VAR4(VAR15[1:0], VAR8[4*VAR27 +: 4*VAR27]);
assign VAR18 = VAR4(VAR15[1:0], VAR8[8*VAR27 +: 4*VAR27]);
for (VAR24 = 0; VAR24 < VAR27 ; VAR24 = VAR24 + 1) begin : VAR9
VAR11 VAR10
(
.VAR20 (VAR28[VAR24]),
.VAR30 (VAR12[VAR24]),
.VAR15 (VAR15[2]),
.VAR37 (VAR38[VAR24])
);
VAR11 VAR22
(
.VAR20 (VAR18[VAR24]),
.VAR30 (VAR29[VAR24]),
.VAR15 (VAR15[2]),
.VAR37 (VAR35[VAR24])
);
VAR17 VAR26
(
.VAR20 (VAR38[VAR24]),
.VAR30 (VAR35[VAR24]),
.VAR15 (VAR15[3]),
.VAR37 (VAR16[VAR24])
);
end
end
default: assign VAR16 = VAR32(VAR15, VAR8);
endcase
end endgenerate
endmodule | gpl-2.0 |
CospanDesign/nysa-sata | rtl/generic/ppfifo.v | 18,948 | module MODULE1
VAR38 = 4
)(
input reset,
input VAR1,
output reg [1:0] VAR21,
input [1:0] VAR62,
output [23:0] VAR54,
input VAR45,
input [VAR25 - 1: 0] VAR13,
output VAR17,
input VAR10,
input VAR12,
output reg VAR60,
input VAR3,
output reg [23:0] VAR11,
output [VAR25 - 1: 0] VAR16,
output VAR32
);
localparam VAR28 = (1 << VAR38);
wire VAR57; wire [VAR38: 0] VAR4; reg [VAR38 - 1: 0]VAR44;
reg VAR49; reg VAR27;
reg [1:0] VAR41;wire [1:0] VAR22;
reg VAR6;
reg [23:0] VAR8[1:0]; reg VAR15[1:0];
reg VAR9; reg [4:0] VAR23;
wire ready;
wire [VAR38: 0] VAR59; reg VAR34;
reg [4:0] VAR31;
reg [VAR38 - 1: 0]VAR66; reg VAR2;
wire [1:0] VAR36;
reg [1:0] VAR18;wire VAR65;
reg [23:0] VAR39[1:0];
reg [1:0] VAR19; reg [1:0] VAR42; reg [1:0] VAR46;
reg VAR20;
reg [1:0] VAR61;
reg VAR50;
reg VAR64; wire [VAR25 - 1: 0] VAR37; reg [VAR25 - 1: 0] VAR47;
assign VAR54 = VAR28;
assign VAR4 = {VAR49, VAR44};
assign VAR57 = !(VAR9 || VAR34);
assign ready = VAR57;
assign VAR59 = {VAR2, VAR66};
assign VAR32 = (VAR8[0] == 0) &&
(VAR8[1] == 0) &&
(VAR21 == 2'b11) &&
(!VAR45);
assign VAR16 = (VAR50) ? VAR37 : VAR47;
VAR33 #(
.VAR25(VAR25),
.VAR38(VAR38 + 1)
) VAR14 (
.VAR43 (VAR1 ),
.VAR55 (VAR27 ), .VAR58 (VAR13 ),
.VAR5 (VAR4 ),
.VAR40 (VAR10 ),
.VAR29 (VAR37 ),
.VAR48 (VAR59 )
);
VAR24 VAR56 (
.rst (reset ),
.VAR7 (VAR41[0] ),
.VAR35 (VAR10 ),
.VAR63 (VAR36[0] )
);
VAR24 VAR26 (
.rst (reset ),
.VAR7 (VAR41[1] ),
.VAR35 (VAR10 ),
.VAR63 (VAR36[1] )
);
VAR24 VAR52 (
.rst (reset ),
.VAR7 (VAR6 ),
.VAR35 (VAR10 ),
.VAR63 (VAR65 )
);
VAR24 VAR51 (
.rst (reset ),
.VAR7 (VAR18[0] ),
.VAR35 (VAR10 ),
.VAR63 (VAR22[0] )
);
VAR24 VAR53 (
.rst (reset ),
.VAR7 (VAR18[1] ),
.VAR35 (VAR10 ),
.VAR63 (VAR22[1] )
);
VAR24 VAR30(
.rst (reset ),
.VAR7 (!VAR60 && !VAR3 ),
.VAR35 (VAR1 ),
.VAR63 (VAR17 )
);
always @ begin
case (VAR62)
2'b00: begin
VAR49 = 1'b0;
end
2'b01: begin
VAR49 = 1'b0;
end
2'b10: begin
VAR49 = 1'b1;
end
default: begin
VAR49 = 1'b0;
end
endcase
end
always @ (*) begin
if (VAR62 > 0 && VAR45) begin
VAR27 = 1'b1;
end
else begin
VAR27 = 1'b0;
end
end
always @ (posedge VAR1) begin
if (reset) begin
VAR9 <= 1;
VAR23 <= 0;
end
else begin
if (VAR9 && (VAR23 < 5'h4)) begin
VAR23 <= VAR23 + 5'h1;
end
else begin
VAR9 <= 0;
end
end
end
always @ (posedge VAR10) begin
if (reset) begin
VAR34 <= 1;
VAR31 <= 0;
end
else begin
if (VAR34 && (VAR31 < 5'h4)) begin
VAR31 <= VAR31 + 5'h1;
end
else begin
VAR34 <= 0;
end
end
end | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221a/sky130_fd_sc_hdll__o221a_1.v | 2,460 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR7 ,
VAR9,
VAR12,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR11 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR7 ;
input VAR9;
input VAR12;
input VAR8 ;
input VAR6 ;
VAR4 VAR2 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR3 ,
VAR11,
VAR1,
VAR10,
VAR5,
VAR7
);
output VAR3 ;
input VAR11;
input VAR1;
input VAR10;
input VAR5;
input VAR7;
supply1 VAR9;
supply0 VAR12;
supply1 VAR8 ;
supply0 VAR6 ;
VAR4 VAR2 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_046.v | 1,515 | module MODULE1 (
VAR9,
VAR14
);
input [31:0] VAR9;
output [31:0]
VAR14;
wire [31:0]
VAR11,
VAR3,
VAR1,
VAR10,
VAR5,
VAR7,
VAR4,
VAR13,
VAR6;
assign VAR11 = VAR9;
assign VAR7 = VAR11 << 4;
assign VAR4 = VAR1 - VAR7;
assign VAR3 = VAR11 << 8;
assign VAR1 = VAR11 + VAR3;
assign VAR6 = VAR5 - VAR13;
assign VAR10 = VAR1 << 5;
assign VAR5 = VAR11 + VAR10;
assign VAR13 = VAR4 << 2;
assign VAR14 = VAR6;
endmodule
module MODULE2(
VAR9,
VAR14,
clk
);
input [31:0] VAR9;
output [31:0] VAR14;
reg [31:0] VAR14;
input clk;
reg [31:0] VAR2;
wire [30:0] VAR12;
always @(posedge clk) begin
VAR2 <= VAR9;
VAR14 <= VAR12;
end
MODULE1 MODULE1(
.VAR9(VAR2),
.VAR14(VAR12)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai_0.v | 2,435 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR12 ,
VAR8 ,
VAR11 ,
VAR9,
VAR7,
VAR6 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR12 ;
input VAR8 ;
input VAR11 ;
input VAR9;
input VAR7;
input VAR6 ;
input VAR3 ;
VAR10 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR4 ,
VAR1,
VAR2,
VAR12,
VAR8,
VAR11
);
output VAR4 ;
input VAR1;
input VAR2;
input VAR12;
input VAR8;
input VAR11;
supply1 VAR9;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR3 ;
VAR10 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR11(VAR11)
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.behavioral.pp.v | 1,164 | module MODULE1( VAR6, VAR4, VAR1, VAR2 );
input VAR6;
inout VAR1, VAR2;
output VAR4;
VAR5 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR2(VAR2));
VAR5 VAR7(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR2(VAR2)); | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/altera/DSP48E1.v | 5,529 | module MODULE1 (
VAR1,
VAR71,
VAR28,
VAR24,
VAR33,
VAR66,
VAR16,
VAR22,
VAR50,
VAR30,
VAR8,
VAR23,
VAR2,
VAR79,
VAR5,
VAR57,
VAR29,
VAR15,
VAR64,
VAR43,
VAR6,
VAR10,
VAR59,
VAR60,
VAR45,
VAR38,
VAR72,
VAR54,
VAR42,
VAR13,
VAR68,
VAR56,
VAR26,
VAR47,
VAR7,
VAR20,
VAR51,
VAR39,
VAR65,
VAR53,
VAR73,
VAR25,
VAR17,
VAR48,
VAR67,
VAR3,
VAR44,
VAR36,
VAR49);
parameter VAR62 = 1;
parameter VAR76 = 1;
parameter VAR19 = 1;
parameter VAR46 = 1;
parameter VAR55 = "VAR27";
parameter VAR34 = "VAR61";
parameter VAR9 = 1;
parameter VAR37 = 1;
parameter VAR70 = "VAR61";
parameter VAR32 = 1;
parameter VAR40 = 1;
parameter VAR78 = 1;
parameter VAR4 = 1;
parameter VAR12 = 1;
parameter VAR77 = 'h3fffffffffff;
parameter VAR21 = 1;
parameter VAR58 = 1;
parameter VAR35 = 0;
parameter VAR11 = 1;
parameter VAR69 = "VAR77";
parameter VAR41 = "VAR35";
parameter VAR75 = 0;
parameter VAR14 = "VAR52";
parameter VAR74 = "VAR31";
parameter VAR18 = "VAR63";
output [29:0] VAR1;
output [17:0] VAR71;
output VAR28;
output [ 3:0] VAR24;
output VAR33;
output VAR66;
output [47:0] VAR16;
output VAR22;
output VAR50;
output [47:0] VAR30;
output VAR8;
input [29:0] VAR23;
input [29:0] VAR2;
input [ 3:0] VAR79;
input [17:0] VAR5;
input [17:0] VAR57;
input [47:0] VAR29;
input VAR15;
input VAR64;
input [ 2:0] VAR43;
input VAR6;
input VAR10;
input VAR59;
input VAR60;
input VAR45;
input VAR38;
input VAR72;
input VAR54;
input VAR42;
input VAR13;
input VAR68;
input VAR56;
input VAR26;
input VAR47;
input [24:0] VAR7;
input [ 4:0] VAR20;
input VAR51;
input [ 6:0] VAR39;
input [47:0] VAR65;
input VAR53;
input VAR73;
input VAR25;
input VAR17;
input VAR48;
input VAR67;
input VAR3;
input VAR44;
input VAR36;
input VAR49;
assign VAR1 = 30'd0;
assign VAR71 = 18'd0;
assign VAR28 = 1'd0;
assign VAR24 = 4'd0;
assign VAR33 = 1'd0;
assign VAR66 = 1'd0;
assign VAR16 = 48'd0;
assign VAR22 = 1'd0;
assign VAR50 = 1'd0;
assign VAR30 = 48'd0;
assign VAR8 = 1'd0;
endmodule | gpl-3.0 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/5445e913f36ad95e/design_1_axi_gpio_0_0_stub.v | 2,335 | module MODULE1(VAR19, VAR17, VAR5,
VAR12, VAR2, VAR8, VAR10, VAR4, VAR11,
VAR13, VAR18, VAR3, VAR1, VAR20, VAR6,
VAR9, VAR21, VAR16, VAR15, VAR7, VAR14)
;
input VAR19;
input VAR17;
input [8:0]VAR5;
input VAR12;
output VAR2;
input [31:0]VAR8;
input [3:0]VAR10;
input VAR4;
output VAR11;
output [1:0]VAR13;
output VAR18;
input VAR3;
input [8:0]VAR1;
input VAR20;
output VAR6;
output [31:0]VAR9;
output [1:0]VAR21;
output VAR16;
input VAR15;
input [3:0]VAR7;
input [3:0]VAR14;
endmodule | mit |
Cognoscan/BoostLogic | verilog/src/buffers/Fifo.v | 1,977 | module MODULE1 #(
parameter VAR4 = 8, parameter VAR8 = 4 )
(
input clk, input rst, input write, input read, input [VAR4-1:0] VAR2, output wire [VAR4-1:0] VAR3, output reg VAR10, output wire VAR6, output wire VAR9 );
reg [VAR4-1:0] memory[2**VAR8-1:0];
reg [VAR8-1:0] VAR5;
wire VAR1;
integer VAR7; | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/SOC/synthesis/submodules/SOC_timer_0.v | 6,661 | module MODULE1 (
address,
VAR19,
clk,
VAR24,
VAR9,
VAR21,
irq,
VAR14
)
;
output irq;
output [ 15: 0] VAR14;
input [ 2: 0] address;
input VAR19;
input clk;
input VAR24;
input VAR9;
input [ 15: 0] VAR21;
wire VAR22;
wire VAR27;
wire VAR1;
reg [ 3: 0] VAR4;
wire VAR28;
reg VAR10;
wire VAR25;
wire [ 31: 0] VAR12;
reg [ 31: 0] VAR29;
reg VAR6;
wire VAR33;
wire VAR2;
reg VAR18;
reg [ 31: 0] VAR31;
wire irq;
reg [ 15: 0] VAR32;
wire VAR16;
reg [ 15: 0] VAR30;
wire VAR11;
wire [ 15: 0] VAR8;
reg [ 15: 0] VAR14;
wire VAR13;
wire VAR17;
wire [ 31: 0] VAR5;
wire VAR26;
wire VAR15;
wire VAR23;
wire VAR3;
wire VAR20;
reg VAR7;
assign VAR22 = 1;
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR31 <= 32'hC34F;
end
else if (VAR10 || VAR18)
if (VAR25 || VAR18)
VAR31 <= VAR12;
else
VAR31 <= VAR31 - 1;
end
assign VAR25 = VAR31 == 0;
assign VAR12 = {VAR32,
VAR30};
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR18 <= 0;
end
else if (VAR22)
VAR18 <= VAR16 || VAR11;
end
assign VAR33 = VAR15;
assign VAR2 = (VAR3 ) ||
(VAR18 ) ||
(VAR25 && ~VAR27 );
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR10 <= 1'b0;
end
else if (VAR22)
if (VAR33)
VAR10 <= -1;
else if (VAR2)
VAR10 <= 0;
end
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR6 <= 0;
end
else if (VAR22)
VAR6 <= VAR25;
end
assign VAR20 = (VAR25) & ~(VAR6);
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR7 <= 0;
end
else if (VAR22)
if (VAR23)
VAR7 <= 0;
else if (VAR20)
VAR7 <= -1;
end
assign irq = VAR7 && VAR1;
assign VAR8 = ({16 {(address == 2)}} & VAR30) |
({16 {(address == 3)}} & VAR32) |
({16 {(address == 4)}} & VAR5[15 : 0]) |
({16 {(address == 5)}} & VAR5[31 : 16]) |
({16 {(address == 1)}} & VAR4) |
({16 {(address == 0)}} & {VAR10,
VAR7});
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR14 <= 0;
end
else if (VAR22)
VAR14 <= VAR8;
end
assign VAR11 = VAR19 && ~VAR9 && (address == 2);
assign VAR16 = VAR19 && ~VAR9 && (address == 3);
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR30 <= 49999;
end
else if (VAR11)
VAR30 <= VAR21;
end
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR32 <= 0;
end
else if (VAR16)
VAR32 <= VAR21;
end
assign VAR17 = VAR19 && ~VAR9 && (address == 4);
assign VAR13 = VAR19 && ~VAR9 && (address == 5);
assign VAR26 = VAR17 || VAR13;
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR29 <= 0;
end
else if (VAR26)
VAR29 <= VAR31;
end
assign VAR5 = VAR29;
assign VAR28 = VAR19 && ~VAR9 && (address == 1);
always @(posedge clk or negedge VAR24)
begin
if (VAR24 == 0)
VAR4 <= 0;
end
else if (VAR28)
VAR4 <= VAR21[3 : 0];
end
assign VAR3 = VAR21[3] && VAR28;
assign VAR15 = VAR21[2] && VAR28;
assign VAR27 = VAR4[1];
assign VAR1 = VAR4;
assign VAR23 = VAR19 && ~VAR9 && (address == 0);
endmodule | gpl-2.0 |
sittner/lcnc-mdsio | vhdl/source/can/can_register_asyn_syn.v | 4,662 | module MODULE1
( VAR4,
VAR1,
VAR3,
clk,
rst,
VAR5
);
parameter VAR6 = 8; parameter VAR2 = 0;
input [VAR6-1:0] VAR4;
input VAR3;
input clk;
input rst;
input VAR5;
output [VAR6-1:0] VAR1;
reg [VAR6-1:0] VAR1;
always @ (posedge clk or posedge rst)
begin
if(rst)
VAR1<=VAR2;
end
else if (VAR5) VAR1<=VAR2;
else if (VAR3) VAR1<=VAR4;
end
endmodule | gpl-3.0 |
merckhung/zet | cores/sdspi/rtl/sdspi.v | 2,639 | module MODULE1 (
output reg VAR13,
input VAR1,
output reg VAR10,
output reg VAR8,
input VAR12,
input VAR18,
input [8:0] VAR6,
output reg [7:0] VAR19,
input VAR16,
input [1:0] VAR3,
input VAR20,
input VAR5,
output reg VAR14
);
wire VAR15;
wire VAR17;
wire VAR2;
reg [7:0] VAR9;
reg VAR4;
reg [7:0] VAR7;
reg [1:0] VAR11;
assign VAR15 = VAR20 & VAR5;
assign VAR17 = !VAR4 & VAR15;
assign VAR2 = VAR17 & VAR16 & VAR3[0];
always @(posedge VAR12)
VAR10 <= VAR18 ? 1'b1
: (VAR11==2'b10 ? (VAR2 ? VAR6[7] : VAR9[7]) : VAR10);
always @(posedge VAR12)
VAR9 <= VAR18 ? 8'hff
: (VAR11==2'b10 ? { (VAR2 ?
VAR6[6:0] : VAR9[6:0]), 1'b1 } : VAR9);
always @(posedge VAR12)
VAR14 <= VAR18 ? 1'b0
: (VAR14 ? 1'b0 : (VAR7[0] && VAR11==2'b00));
always @(posedge VAR12)
VAR7 <= VAR18 ? 8'h0
: (VAR11==2'b10 ? { VAR17, VAR7[7:1] } : VAR7);
always @(posedge VAR12)
VAR4 <= VAR18 ? 1'b0 : (VAR4 ? !VAR7[0] : VAR15 && VAR11==2'b10);
always @(posedge VAR12)
VAR19 <= VAR18 ? 8'h0
: ((VAR15 && VAR11==2'b0) ?
{ VAR19[6:0], VAR1 } : VAR19);
always @(posedge VAR12)
VAR13 <= VAR18 ? 1'b1
: (VAR11[0] ? VAR13 : !(VAR15 & VAR11[1]));
always @(negedge VAR12)
VAR8 <= VAR18 ? 1'b1
: ((VAR15 & VAR16 & VAR3[1]) ? VAR6[8] : VAR8);
always @(posedge VAR12) VAR11 <= VAR11 - 2'd1;
endmodule | gpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_pic.v | 7,273 | module MODULE1(
clk, rst, VAR11, VAR13, VAR15, VAR6, VAR5,
VAR17, VAR12,
VAR19
);
input clk; input rst; input VAR11; input VAR13; input [31:0] VAR15; input [31:0] VAR6; output [31:0] VAR5; output VAR17; output VAR12;
input [VAR3-1:0] VAR19;
reg [VAR3-1:2] VAR20; else
wire [VAR3-1:2] VAR20; VAR16
reg [VAR3-1:0] VAR4; else
wire [VAR3-1:0] VAR4; VAR16
wire VAR14; wire VAR18; wire [VAR3-1:0] VAR2;reg [31:0] VAR5;
assign VAR14 = (VAR11 && (VAR15[VAR9] == VAR1)) ? 1'b1 : 1'b0;
assign VAR18 = (VAR11 && (VAR15[VAR9] == VAR7)) ? 1'b1 : 1'b0;
always @(posedge clk or posedge rst)
if (rst)
VAR20 <= {1'b1, {VAR3-3{1'b0}}};
else if (VAR14 && VAR13) begin
VAR20 <= VAR6[VAR3-1:2];
end
assign VAR20 = (VAR3)'b1;
always @(posedge clk or posedge rst)
if (rst)
VAR4 <= {VAR3{1'b0}};
else if (VAR18 && VAR13) begin
VAR4 <= VAR6[VAR3-1:0] | VAR2;
end else
VAR4 <= VAR4 | VAR2;
assign VAR4 = VAR19;
always @(VAR15 or VAR20 or VAR4)
case (VAR15[VAR9]) VAR10 VAR8
VAR5[VAR3-1:0] = {VAR20, 2'b0};
VAR5[31:VAR3] = {32-VAR3{1'b0}};
end
default: begin
VAR5[VAR3-1:0] = VAR4;
VAR5[31:VAR3] = {32-VAR3{1'b0}};
end
endcase
assign VAR2 = VAR19 & {VAR20, 2'b11};
assign VAR12 = |VAR2;
assign VAR17 = VAR12;
assign VAR12 = VAR19[1] | VAR19[0];
assign VAR17= VAR12;
assign VAR5[VAR3-1:0] = VAR3'b0;
assign VAR5[31:VAR3] = 32-VAR3'b0;
endmodule | gpl-2.0 |
benjaminfjones/fpga-tunes | src/spi_slave.v | 1,596 | module MODULE1(
input clk,
input rst,
input VAR11,
input VAR1,
output VAR19,
input VAR9,
output VAR8,
input [7:0] din,
output [7:0] dout
);
reg VAR12, VAR4;
reg VAR10, VAR3;
reg VAR5, VAR6;
reg VAR21, VAR14;
reg [7:0] VAR2, VAR18;
reg VAR23, VAR13;
reg [2:0] VAR15, VAR16;
reg [7:0] VAR22, VAR20;
reg VAR17, VAR7;
assign VAR19 = VAR7;
assign VAR8 = VAR13;
assign dout = VAR20;
always @(*) begin
VAR10 = VAR11;
VAR12 = VAR1;
VAR17 = VAR7;
VAR5 = VAR9;
VAR21 = VAR6;
VAR2 = VAR18;
VAR23 = 1'b0;
VAR15 = VAR16;
VAR22 = VAR20;
if (VAR3) begin
VAR15 = 3'b0;
VAR2 = din;
VAR17 = VAR18[7];
end else begin
if (!VAR14 && VAR6) begin VAR2 = {VAR18[6:0], VAR4};
VAR15 = VAR16 + 1'b1;
if (VAR16 == 3'b111) begin
VAR22 = {VAR18[6:0], VAR4};
VAR23 = 1'b1;
VAR2 = din;
end
end else if (VAR14 && !VAR6) begin VAR17 = VAR18[7];
end
end
end
always @(posedge clk) begin
if (rst) begin
VAR13 <= 1'b0;
VAR16 <= 3'b0;
VAR20 <= 8'b0;
VAR7 <= 1'b1;
end else begin
VAR13 <= VAR23;
VAR16 <= VAR15;
VAR20 <= VAR22;
VAR7 <= VAR17;
end
VAR6 <= VAR5;
VAR4 <= VAR12;
VAR3 <= VAR10;
VAR18 <= VAR2;
VAR14 <= VAR21;
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn.pp.symbol.v | 1,329 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR7,
input VAR2 ,
input VAR3,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4/sky130_fd_sc_hs__nand4.symbol.v | 1,258 | module MODULE1 (
input VAR1,
input VAR6,
input VAR5,
input VAR2,
output VAR7
);
supply1 VAR3;
supply0 VAR4;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v | 3,253 | module MODULE1 (
input clk,
input VAR4,
input VAR17,
output VAR3,
input VAR14,
input [7:0] VAR2,
input VAR13,
input VAR10,
input [31:0] VAR1,
output reg VAR5,
input VAR15,
output [23:0] VAR8,
output reg VAR18,
input VAR21,
output [31:0] VAR20,
output reg VAR16
);
reg [1:0] VAR11 = 'h00;
reg [31:0] VAR9 = 'h00;
reg [23:0] VAR19 = 'h00;
reg VAR6 = 1'b0;
reg VAR12 = 1'b0;
reg VAR7 = 1'b0;
wire sync;
assign VAR3 = 1'b1;
assign VAR8 = {~VAR19[23],VAR19[22:0]};
assign VAR20 = VAR9;
always @(posedge clk) begin
if (VAR12 == 1'b0 && VAR10 == 1'b1) begin
if (VAR5 | VAR18 | ~VAR17) begin
VAR16 <= 1'b1;
end else begin
VAR9 <= VAR1;
VAR16 <= 1'b0;
end
end else begin
VAR16 <= 1'b0;
end
VAR12 <= VAR10;
end
always @(posedge clk) begin
if (VAR17 == 1'b0) begin
VAR18 <= 1'b0;
VAR5 <= 1'b0;
end else begin
if (VAR6 == 1'b1) begin
VAR18 <= 1'b1;
VAR5 <= 1'b1;
end else begin
if (VAR21 == 1'b1) begin
VAR18 <= 1'b0;
end
if (VAR15 == 1'b1) begin
VAR5 <= 1'b0;
end
end
end
end
always @(posedge clk) begin
VAR6 <= 1'b0;
if (VAR13 == 1'b0) begin
if (VAR14 == 1'b1 && VAR11 == 2'h2) begin
VAR6 <= 1'b1;
end
end else begin
if (VAR14 == 1'b1 && VAR11 == 2'h3 &&
(sync == 1'b1 || VAR7 == 1'b1)) begin
VAR6 <= 1'b1;
end
end
end
always @(posedge clk) begin
if (VAR14 == 1'b1 && VAR11 != 2'h3) begin
VAR19 <= {VAR19[15:0],VAR2};
end
end
always @(posedge clk) begin
if (VAR14 == 1'b1) begin
if (VAR11 == 2'h2 && VAR13 == 1'b0) begin
VAR11 <= 2'h0;
end else begin
VAR11 <= VAR11 + 1'b1;
end
end
end
assign sync = VAR2[3:0] == 'h00 && VAR11 == 'h3;
always @(posedge clk) begin
if (VAR17 == 1'b0) begin
VAR7 <= ~VAR13;
end else begin
if (VAR14 == 1'b1 && sync == 1'b1) begin
VAR7 <= 1'b1;
end
end
end
endmodule | gpl-3.0 |
ak-fau/fpga-cyclone_iv | bemicro/zscale_wrapper.v | 4,354 | module MODULE1 (
input wire clk,
input wire reset,
output wire [7:0] VAR8
);
wire VAR38;
wire [63:0] VAR44;
wire [31:0] VAR9;
wire VAR7;
wire [2:0] VAR47;
wire [2:0] VAR25;
wire [3:0] VAR46;
wire [1:0] VAR17;
wire VAR22;
wire [31:0] VAR59;
wire [31:0] VAR42;
wire VAR18;
wire VAR55;
wire VAR33;
wire VAR39;
wire [31:0] VAR4;
wire VAR36;
wire VAR1;
wire VAR16;
wire [31:0] VAR43;
wire [31:0] VAR28;
wire VAR49;
wire VAR48;
reg VAR58;
reg [31:0] VAR53;
assign VAR8 = VAR53[7:0];
VAR56 VAR31(
.clk(clk),
.reset(reset),
.VAR51(reset),
.VAR21(1'b0),
.VAR29(),
.VAR13(1'b1),
.VAR54(1'b0),
.VAR12(12'h780), .VAR27(64'd0),
.VAR11(1'b1),
.VAR50(VAR38),
.VAR24(VAR44),
.VAR10(1'b1),
.VAR37(),
.VAR40(),
.VAR19(),
.VAR5(1'b0),
.VAR32(),
.VAR15(),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR47(VAR47),
.VAR25(VAR25),
.VAR46(VAR46),
.VAR17(VAR17),
.VAR22(VAR22),
.VAR59(VAR59),
.VAR42(VAR42),
.VAR18(VAR18),
.VAR55(VAR55),
.VAR33(VAR33),
.VAR39(VAR39),
.VAR4(VAR4),
.VAR36(VAR36),
.VAR1(VAR1),
.VAR16(VAR16),
.VAR43(VAR43),
.VAR28(VAR28),
.VAR49(VAR49),
.VAR48(VAR48)
);
assign VAR48 = 1'b0;
assign VAR49 = VAR58;
assign VAR28 = VAR53;
always @(posedge reset or posedge clk)
begin
if (reset)
begin
VAR53 = 32'h80;
VAR58 = 1'b0;
end
else
begin
if (clk)
begin
if (VAR58 && VAR16)
begin
VAR53 = VAR43;
VAR58 = 1'b0;
end
else
if (VAR1 && VAR4 == 32'h80000000)
begin
VAR58 = 1'b1;
end
else
begin
VAR58 = 1'b0;
end
end
end
end
VAR41 VAR2 (
.clk(clk),
.reset(reset),
.VAR3(VAR9),
.VAR34(VAR7),
.VAR35(VAR47),
.VAR6(VAR25),
.VAR14(VAR46),
.VAR57(VAR17),
.VAR60(VAR22),
.VAR20(32'd0),
.VAR52(VAR42),
.VAR45(VAR18),
.VAR30(VAR55),
.VAR23(VAR33),
.VAR26(VAR39)
);
endmodule | bsd-2-clause |
nliu96/openHMC_Altera | src/openhmc_ram.v | 4,109 | module MODULE1 #(
parameter VAR6 = 78, parameter VAR4 = 9, parameter VAR5 = 0
) (
input wire clk,
input wire VAR2,
input wire [VAR6-1:0] VAR1,
input wire [VAR4-1:0] VAR7,
input wire VAR13,
input wire [VAR4-1:0] VAR12,
output wire [VAR6-1:0] VAR3
);
wire [VAR6-1:0] VAR9;
generate
if (VAR5 == 0)
begin
assign VAR3 = VAR9;
end
else
begin
reg [VAR6-1:0] VAR10;
reg VAR11;
assign VAR3 = VAR10;
always @(posedge clk)
begin
VAR11 <= VAR13;
if (VAR11)
VAR10 <= VAR9;
end
end
endgenerate
reg [VAR6-1:0] VAR8 [0:(2**VAR4)-1];
reg [VAR6-1:0] VAR14;
assign VAR9 = VAR14;
always @(posedge clk)
begin
if (VAR2)
VAR8[VAR7] <= VAR1;
end
always @(posedge clk)
begin
if (VAR13)
VAR14 <= VAR8[VAR12];
end
endmodule | lgpl-3.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/ghrd.v | 13,674 | module MODULE1(
output VAR103,
output VAR81,
output VAR89,
input VAR144,
inout [15:0] VAR36,
inout VAR74,
output VAR26,
inout VAR133,
input VAR56,
input VAR150,
input VAR39,
inout [35:0] VAR73,
inout [35:0] VAR105,
inout VAR32,
output [14:0] VAR125,
output [2:0] VAR86,
output VAR142,
output VAR5,
output VAR21,
output VAR136,
output VAR134,
output [3:0] VAR130,
inout [31:0] VAR75,
inout [3:0] VAR24,
inout [3:0] VAR113,
output VAR43,
output VAR47,
output VAR148,
input VAR8,
output VAR61,
output VAR4,
inout VAR2,
output VAR80,
inout VAR145,
input VAR60,
input [3:0] VAR17,
input VAR37,
output [3:0] VAR149,
output VAR99,
inout VAR14,
inout VAR85,
inout VAR131,
inout VAR154,
inout VAR7,
inout VAR46,
inout VAR38,
inout VAR127,
output VAR106,
inout VAR79,
inout [3:0] VAR3,
output VAR88,
input VAR63,
output VAR50,
inout VAR25,
input VAR137,
output VAR115,
input VAR52,
inout [7:0] VAR107,
input VAR55,
input VAR31,
output VAR129,
input [1:0] VAR120,
output [7:0] VAR98,
input [3:0] VAR155
);
wire [1:0] VAR22;
wire [7:0] VAR84;
wire VAR35;
wire [2:0] VAR92;
wire VAR29;
wire VAR30;
wire VAR77;
wire [27:0] VAR112;
assign VAR112 = {{13{1'b0}},VAR155, VAR84, VAR22};
VAR42 VAR72 (
.VAR20 (VAR56 ), .VAR45 (1'b1 ), .VAR18 ( VAR125), .VAR100 ( VAR86), .VAR53 ( VAR136), .VAR49 ( VAR21), .VAR102 ( VAR5), .VAR124 ( VAR134), .VAR62 ( VAR47), .VAR95 ( VAR142), .VAR90 ( VAR61), .VAR65 ( VAR148), .VAR132 ( VAR75), .VAR143 ( VAR113), .VAR123 ( VAR24), .VAR111 ( VAR43), .VAR122 ( VAR130), .VAR96 ( VAR8), .VAR94 ( VAR4), .VAR57 ( VAR149[0] ), .VAR110 ( VAR149[1] ), .VAR66 ( VAR149[2] ), .VAR139 ( VAR149[3] ), .VAR140 ( VAR17[0] ), .VAR101 ( VAR145 ), .VAR12 ( VAR80 ), .VAR33 ( VAR37), .VAR82 ( VAR99), .VAR68 ( VAR60), .VAR109 ( VAR17[1] ), .VAR76 ( VAR17[2] ), .VAR19 ( VAR17[3] ), .VAR146 ( VAR79 ), .VAR147 ( VAR3[0] ), .VAR118 ( VAR3[1] ), .VAR48 ( VAR106 ), .VAR34 ( VAR3[2] ), .VAR128 ( VAR3[3] ), .VAR1 ( VAR107[0] ), .VAR11 ( VAR107[1] ), .VAR83 ( VAR107[2] ), .VAR138 ( VAR107[3] ), .VAR119 ( VAR107[4] ), .VAR58 ( VAR107[5] ), .VAR91 ( VAR107[6] ), .VAR93 ( VAR107[7] ), .VAR104 ( VAR52 ), .VAR15 ( VAR129 ), .VAR135 ( VAR55 ), .VAR108 ( VAR31 ), .VAR6 ( VAR88 ), .VAR44 ( VAR50 ), .VAR59 ( VAR63 ), .VAR117 ( VAR25 ), .VAR158 ( VAR137 ), .VAR16 ( VAR115 ), .VAR10 ( VAR131 ), .VAR97 ( VAR85 ), .VAR51 ( VAR7 ), .VAR28 ( VAR154 ), .VAR40 ( VAR32 ), .VAR27 ( VAR2 ), .VAR64 ( VAR127 ), .VAR78 ( VAR38 ), .VAR71 ( VAR46 ), .VAR54 ( VAR14 ),
.VAR87 (VAR112), .VAR13 (VAR35), .VAR67 (~VAR30), .VAR126 (~VAR77), .VAR152 (~VAR29)
);
VAR69 VAR114 (
.VAR41 (VAR56),
.VAR153 (VAR92)
);
VAR23 VAR116 (
.clk (VAR56),
.VAR157 (VAR35),
.VAR159 (VAR92[0]),
.VAR70 (VAR29)
);
VAR23 VAR141 (
.clk (VAR56),
.VAR157 (VAR35),
.VAR159 (VAR92[1]),
.VAR70 (VAR30)
);
VAR23 VAR121 (
.clk (VAR56),
.VAR157 (VAR35),
.VAR159 (VAR92[2]),
.VAR70 (VAR77)
);
endmodule | mit |
hoangt/multiported-ram | mpram.v | 13,287 | module MODULE1
localparam VAR38 = VAR16(VAR19);
localparam VAR5 = VAR16(VAR12);
localparam VAR31 = VAR40*(VAR12-1);
localparam VAR11 = VAR5*(VAR12+VAR21-1);
localparam VAR13 = (VAR12-1)*(VAR21+1);
localparam VAR17 = ( (VAR13<=VAR31) && (VAR13<=VAR11) ) ? "VAR4" : ( (VAR11<=VAR31) ? "VAR26" : "VAR6" );
localparam VAR30 = ((VAR42!="VAR43")&&(VAR42!="VAR6")&&(VAR42!="VAR22")&&(VAR42!="VAR28")&&(VAR42!="VAR4")) ? VAR17 : VAR42;
localparam VAR24 = VAR32!="VAR15" ; localparam VAR9 = (VAR32=="VAR9")||(VAR32=="VAR2"); localparam VAR2 = VAR32=="VAR2" ;
generate
if (VAR12==1) begin
VAR37 #( .VAR19 (VAR19 ), .VAR40 (VAR40 ), .VAR21(VAR21 ), .VAR36 (VAR2?2:VAR9 ), .VAR8 (VAR8 )) VAR14 ( .clk (clk ), .VAR7 (VAR7 ), .VAR33 (VAR33 ), .VAR18 (VAR18 ), .VAR3 (VAR3 ), .VAR34 (VAR34 )); end
else if (VAR30=="VAR43" ) begin
VAR10 #( .VAR19 (VAR19 ), .VAR40 (VAR40 ), .VAR21(VAR21 ), .VAR12(VAR12 ), .VAR2 (VAR2 ), .VAR8 (VAR8 )) VAR29 ( .clk (clk ), .VAR7 (VAR7 ), .VAR33 (VAR33 ), .VAR18 (VAR18 ), .VAR3 (VAR3 ), .VAR34 (VAR34 )); end
else if (VAR30=="VAR6" ) begin
VAR1 #( .VAR19 (VAR19 ), .VAR40 (VAR40 ), .VAR21(VAR21 ), .VAR12(VAR12 ), .VAR24 (VAR24 ), .VAR9 (VAR9 ), .VAR2 (VAR2 ), .VAR8 (VAR8 )) VAR41 ( .clk (clk ), .VAR7 (VAR7 ), .VAR33 (VAR33 ), .VAR18 (VAR18 ), .VAR3 (VAR3 ), .VAR34 (VAR34 )); end
else if (VAR30=="VAR22") begin
VAR35 #( .VAR19 (VAR19 ), .VAR40 (VAR40 ), .VAR21(VAR21 ), .VAR12(VAR12 ), .VAR2 (VAR2 ), .VAR8 (VAR8 )) VAR39 ( .clk (clk ), .VAR7 (VAR7 ), .VAR33 (VAR33 ), .VAR18 (VAR18 ), .VAR3 (VAR3 ), .VAR34 (VAR34 )); end
else if (VAR30=="VAR28") begin
VAR20 #( .VAR19 (VAR19 ), .VAR40 (VAR40 ), .VAR21(VAR21 ), .VAR12(VAR12 ), .VAR24 (VAR24 ), .VAR9 (VAR9 ), .VAR2 (VAR2 ), .VAR8 (VAR8 )) VAR23 ( .clk (clk ), .VAR7 (VAR7 ), .VAR33 (VAR33 ), .VAR18 (VAR18 ), .VAR3 (VAR3 ), .VAR34 (VAR34 )); end
else begin
VAR25 #( .VAR19 (VAR19 ), .VAR40 (VAR40 ), .VAR21(VAR21 ), .VAR12(VAR12 ), .VAR24 (VAR24 ), .VAR9 (VAR9 ), .VAR2 (VAR2 ), .VAR8 (VAR8 )) VAR27 ( .clk (clk ), .VAR7 (VAR7 ), .VAR33 (VAR33 ), .VAR18 (VAR18 ), .VAR3 (VAR3 ), .VAR34 (VAR34 )); end
endgenerate
endmodule | bsd-3-clause |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/QM_FIR.v | 6,363 | module MODULE1(
VAR3, VAR19, VAR27, VAR2, VAR10, VAR26,
VAR15,
VAR30, VAR4, VAR34, VAR8, VAR36, VAR35, VAR32, VAR13,
VAR16, VAR40, VAR17, VAR38
);
parameter VAR6 = 16;
parameter VAR7 = 8;
parameter VAR11 = 32;
output signed [(VAR6-1):0] VAR3, VAR19, VAR27;
output signed [(VAR6-1):0] VAR2, VAR10, VAR26;
output VAR15;
input VAR30;
input VAR4;
input VAR34;
input signed [(VAR7-1):0] VAR8;
input signed [(VAR7-1):0] VAR36;
input signed [(VAR7-1):0] VAR35;
input signed [(VAR7-1):0] VAR32;
input [6:0] VAR13;
input VAR16;
input [6:0] VAR40;
input [6:0] VAR17;
input [6:0] VAR38;
wire VAR12;
wire signed [(VAR6-1):0] VAR29, VAR31, VAR21;
wire signed [(VAR6-1):0] VAR24, VAR33, VAR28;
VAR39 VAR39
( .clk(VAR30),
.rst(VAR4),
.VAR13(VAR13),
.VAR40(VAR40),
.VAR17(VAR17),
.VAR38(VAR38),
.VAR16(VAR16),
.VAR34(VAR34),
.VAR8(VAR8),
.VAR36(VAR36),
.VAR35(VAR35),
.VAR32(VAR32),
.VAR29(VAR29),
.VAR31(VAR31),
.VAR21(VAR21),
.VAR24(VAR24),
.VAR33(VAR33),
.VAR28(VAR28),
.VAR25(VAR12)
);
VAR9 VAR18
( .VAR30 (VAR30),
.VAR4 (VAR4),
.VAR34 (VAR12),
.VAR20 (VAR29),
.VAR5 (VAR3),
.VAR15 (VAR15)
);
VAR9 VAR1
( .VAR30 (VAR30),
.VAR4 (VAR4),
.VAR34 (VAR12),
.VAR20 (VAR24),
.VAR5 (VAR2)
);
VAR9 VAR23
( .VAR30 (VAR30),
.VAR4 (VAR4),
.VAR34 (VAR12),
.VAR20 (VAR31),
.VAR5 (VAR19)
);
VAR9 VAR22
( .VAR30 (VAR30),
.VAR4 (VAR4),
.VAR34 (VAR12),
.VAR20 (VAR33),
.VAR5 (VAR10)
);
VAR9 VAR14
( .VAR30 (VAR30),
.VAR4 (VAR4),
.VAR34 (VAR12),
.VAR20 (VAR21),
.VAR5 (VAR27)
);
VAR9 VAR37
( .VAR30 (VAR30),
.VAR4 (VAR4),
.VAR34 (VAR12),
.VAR20 (VAR28),
.VAR5 (VAR26)
);
endmodule | gpl-2.0 |
asicguy/gplgpu | hdl/altera_clk_synth/clk_gen_ipll_stim.v | 5,401 | module MODULE1;
reg VAR9;
reg VAR27;
reg VAR15;
reg [1:0] VAR1;
reg VAR13;
reg [1:0] VAR26;
reg VAR4;
reg [2:0] VAR24; reg VAR2;
reg [7:0] VAR8; reg [7:0] VAR7; reg [7:0] VAR16; reg [7:0] VAR5; reg [7:0] VAR11; reg [7:0] VAR20; reg [7:0] VAR22; reg [7:0] VAR12;
wire VAR23;
wire VAR25;
wire VAR21;
wire VAR17;
wire [2:0] VAR6;
wire [3:0] VAR14;
wire [8:0] VAR3;
parameter VAR18 = 26.67;
VAR10 VAR19
(
.VAR9 (VAR9),
.VAR27 (VAR27),
.VAR15 (VAR15),
.VAR1 (VAR1),
.VAR13 (VAR13),
.VAR26 (VAR26),
.VAR4 (VAR4),
.VAR24 (VAR24),
.VAR2 (VAR2),
.VAR8 (VAR8),
.VAR7 (VAR7),
.VAR16 (VAR16),
.VAR5 (VAR5),
.VAR11 (VAR11),
.VAR20 (VAR20),
.VAR22 (VAR22),
.VAR12 (VAR12),
.VAR23 (VAR23),
.VAR25 (VAR25),
.VAR21 (VAR21),
.VAR17 (VAR17)
);
always begin
VAR9 = 0;
VAR15 = 0;
end
VAR9 = 1;
VAR15 = 1;
end
end | gpl-3.0 |
walkthetalk/fsref | ip/s2mm_adv/src/s2mm_adv.v | 5,389 | module MODULE1 #
(
parameter integer VAR67 = 8,
parameter integer VAR46 = 12,
parameter integer VAR5 = 12,
parameter integer VAR63 = 12,
parameter integer VAR4 = 8,
parameter integer VAR35 = 1024,
parameter integer VAR49 = 16,
parameter integer VAR15 = 32,
parameter integer VAR40 = 32
)
(
input wire [VAR46-1:0] VAR16,
input wire [VAR5-1:0] VAR28,
input wire [VAR15-1:0] VAR9,
input wire clk,
input wire VAR71,
input wire VAR53,
output wire VAR75,
input wire VAR74,
input wire [VAR67-1:0] VAR47,
input wire VAR7,
input wire VAR80,
output wire VAR41,
input wire VAR70,
input wire VAR56,
output wire [VAR67+1 : 0] VAR48,
output wire VAR72,
output wire VAR60,
input wire [VAR15-1:0] VAR58,
input wire [VAR40/VAR4*(VAR67+2)-1 : 0] VAR93,
input wire VAR36,
output wire VAR25,
input wire [VAR63-1:0] VAR77,
output wire [VAR15-1 : 0] VAR83,
output wire [7 : 0] VAR12,
output wire [2 : 0] VAR79,
output wire [1 : 0] VAR3,
output wire VAR39,
output wire [3 : 0] VAR62,
output wire [2 : 0] VAR92,
output wire [3 : 0] VAR87,
output wire VAR30,
input wire VAR86,
output wire [VAR40-1 : 0] VAR29,
output wire [VAR40/8-1 : 0] VAR82,
output wire VAR50,
output wire VAR91,
input wire VAR13,
input wire [1 : 0] VAR8,
input wire VAR2,
output wire VAR18,
output reg [31:0] VAR61,
output reg [31:0] VAR89
);
localparam VAR11 = VAR67 - 1;
localparam VAR73 = VAR67 + 1;
localparam VAR44 = VAR67 + 2;
localparam VAR78 = VAR40/VAR4;
function integer VAR59(input integer VAR42);
begin
VAR59 = VAR78-1-VAR42;
end
endfunction
function integer VAR17(input integer VAR42);
begin
VAR17 = VAR42 * VAR44 + VAR67;
end
endfunction
function integer VAR84(input integer VAR42);
begin
VAR84 = VAR42 * VAR44 + VAR73;
end
endfunction
wire VAR64;
assign VAR64 = (VAR71 && VAR53);
assign VAR75 = ~VAR64;
assign VAR48 = {VAR80, VAR7, VAR47};
assign VAR72 = VAR74 && VAR41;
reg VAR90;
assign VAR41 = VAR90;
always @ (posedge clk) begin
if (VAR75)
VAR90 <= 0;
end
else if ( VAR56)
VAR90 <= 0;
else
VAR90 <= 1;
end
wire VAR85;
wire VAR23;
always @ (posedge clk) begin
if (VAR75) begin
VAR61 <= 'hFFFFFFFF;
VAR89 <= 'hFFFFFFFF;
end
else if (VAR72 && VAR7) begin
if (VAR61 == 'hFFFFFFFF) begin
VAR61[15:0] <= VAR85;
VAR61[31:16] <= VAR23;
end
if (VAR89 == 'hFFFFFFFF) begin
VAR89 <= VAR77;
end
end
end
wire [VAR40-1 : 0] VAR76;
generate
genvar VAR42;
for (VAR42 = 0; VAR42 < VAR40/VAR67; VAR42 = VAR42+1) begin: VAR21
assign VAR76[VAR42*VAR4 + VAR11 : VAR42*VAR4]
= VAR93[VAR59(VAR42)*VAR44 + VAR11 : VAR59(VAR42)*VAR44];
end
endgenerate
wire VAR38;
wire VAR54;
VAR45 # (
.VAR63(VAR63),
.VAR49(VAR49),
.VAR15(VAR15),
.VAR40(VAR40),
.VAR46(VAR46),
.VAR5(VAR5),
.VAR78(VAR78)
) VAR26 (
.VAR16(VAR16),
.VAR28(VAR28),
.VAR9(VAR35),
.VAR53(VAR53),
.VAR75(VAR38),
.din(VAR76),
.VAR22(VAR25),
.VAR27(VAR77),
.VAR55(VAR60),
.VAR14(VAR58),
.VAR34(clk),
.VAR6(VAR71),
.VAR81(VAR83),
.VAR43(VAR12),
.VAR88(VAR79),
.VAR66(VAR3),
.VAR51(VAR39),
.VAR33(VAR62),
.VAR10(VAR92),
.VAR20(VAR87),
.VAR37(VAR30),
.VAR31(VAR86),
.VAR52(VAR29),
.VAR57(VAR82),
.VAR69(VAR50),
.VAR1(VAR91),
.VAR32(VAR13),
.VAR24(VAR8),
.VAR68(VAR2),
.VAR19(VAR18),
.VAR65(VAR54),
.VAR85(VAR85),
.VAR23(VAR23)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn.functional.v | 1,218 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR2 ;
input VAR4;
notif0 VAR3 (VAR1 , VAR2, VAR4 );
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_slave_counters.v | 4,646 | module MODULE1 (VAR35, VAR20, VAR38,
VAR16, VAR22, VAR25, VAR10, VAR29, VAR3,
VAR37, VAR8, VAR23, VAR4, VAR19, VAR18, VAR39, VAR11
);
input VAR35; input VAR20; input VAR16; input VAR22; input VAR25; input [1:0] VAR10; input VAR29; input VAR3;
input VAR38;
output [15:0] VAR37; output [15:0] VAR8;
output VAR23;
output VAR4;
output [7: 0] VAR19;
output [7: 0] VAR18;
output VAR39;
output VAR11;
wire VAR39;
wire [3:0] VAR6;
reg [15:0] VAR37;
reg [15:0] VAR8;
reg [3: 0] VAR14;
reg [3: 0] VAR15;
reg [3: 0] VAR33;
reg [7: 0] VAR19;
reg [7: 0] VAR18;
assign VAR6 = 4'd2;
wire VAR31;
wire VAR34;
assign VAR34 = (|VAR10) ;
assign VAR31 = VAR16 | VAR25 ;
always @ (posedge VAR35 or posedge VAR20)
begin
if(VAR20)
VAR8 <= 16'h0;
end
else
begin
if(VAR31)
VAR8 <= 16'h0;
end
else
if(VAR34)
VAR8 <= VAR8 + 16'd1;
end
end
wire VAR40;
wire VAR11;
assign VAR11 = VAR22 | VAR25 | (|VAR10) | VAR29 ;
assign VAR40 = VAR16;
always @ (posedge VAR35 or posedge VAR20)
begin
if(VAR20)
VAR37 <= 16'h0;
end
else
begin
if(VAR40)
VAR37 <= 16'h0;
end
else
if(VAR11)
VAR37 <= VAR37 + 16'd1;
end
end
wire VAR27;
wire VAR13;
assign VAR27 = VAR29 ;
assign VAR13 = |VAR10 ;
assign VAR23 = VAR14[0] ;
always @ (posedge VAR35 or posedge VAR20)
begin
if(VAR20)
VAR14 <= 4'b0;
end
else
begin
if(VAR13)
VAR14 <= 4'b0;
end
else
if(VAR27)
VAR14 <= VAR14 + 4'b0001;
end
end
wire VAR1;
wire VAR24;
assign VAR1 = VAR3 ;
assign VAR24 = VAR16 | VAR22 | VAR25 | (|VAR10) | VAR29;
assign VAR4 = VAR33[0] ;
always @ (posedge VAR35 or posedge VAR20)
begin
if(VAR20)
VAR33 <= 4'b0;
end
else
begin
if(VAR24)
VAR33 <= 4'b0;
end
else
if(VAR1)
VAR33 <= VAR33 + 4'b0001;
end
end
wire VAR26;
wire VAR30;
assign VAR30 = VAR16 | VAR22 | VAR25;
assign VAR26 = VAR21[0];
always @ (posedge VAR35 or posedge VAR20)
begin
if(VAR20)
VAR19 <= 8'b0;
end
else
begin
if(VAR30)
VAR19 <= 8'b0;
end
else
if(VAR26)
VAR19 <= VAR19 + 8'b0001;
end
end
wire VAR32;
wire VAR12;
assign VAR32 = VAR16 | VAR5 | VAR22 | VAR25;
assign VAR12 = VAR2 ;
always @ (posedge VAR35 or posedge VAR20)
begin
if(VAR20)
VAR18[7:0] <= 8'd0;
end
else
begin
if(VAR32)
VAR18[7:0] <= 8'd0;
end
else
if(VAR12)
VAR18[7:0] <= VAR18[7:0] + 8'd1;
end
end
wire VAR7;
wire VAR17;
wire VAR28;
assign VAR7 = VAR9 & VAR22 & VAR38 | VAR25;
assign VAR17 = ~VAR7 & VAR9 &( VAR10[1] & ~VAR28 ) ;
assign VAR39 = VAR36 == 16'd0;
assign VAR28 = VAR36 == 16'hffff;
always @ (posedge VAR35 or posedge VAR20)
begin
if(VAR20)
VAR36[15:0] <= 16'd0;
end
else
begin
if(VAR7)
VAR36[15:0] <= 16'd0;
end
else
if(VAR17)
VAR36[15:0] <= VAR36[15:0] + 16'd1;
end
end
endmodule | gpl-3.0 |
545/Atari7800 | core/ag_6502/trunk/agat7/chip1.v | 1,700 | module MODULE1(
input clk,
input b1,
input VAR21,
input[3:0] VAR6,
input VAR29, VAR23, VAR27,
output[7:0] VAR11,
output VAR14,
output VAR13,
output VAR12,
output VAR10,
output VAR9,
output [3:0]VAR15,
input VAR1, output VAR18, output VAR19, output VAR2, output VAR30,
output VAR5,
output VAR31,
output VAR25,
output VAR26,
output VAR28,
output VAR7,
output VAR22,
input VAR4,
input VAR17
);
assign VAR18 = 0, VAR19 = 0, VAR2 = 0, VAR30 = 0;
assign VAR5 = 1, VAR31 = 1, VAR25 = 0;
assign VAR26 = 1, VAR28 = 1, VAR7 = 1;
assign VAR22 = 0;
wire[4:0] VAR8;
assign {VAR14, VAR13, VAR12, VAR10, VAR9} = VAR8;
wire[1:0] VAR24 = {VAR4, VAR17};
wire[3:0] VAR20 = {0, 0, VAR21, b1};
VAR16 VAR3(clk, VAR20, VAR6, VAR11, VAR15, VAR8, VAR24);
endmodule | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/softusb/rtl/softusb_tx.v | 5,310 | module MODULE1(
input VAR28,
input VAR40,
input [7:0] VAR34,
input VAR41,
output reg VAR17,
output reg VAR6,
output reg VAR12,
output reg VAR10,
input VAR8,
input VAR16
);
reg VAR18;
reg VAR3;
reg VAR37;
always @(posedge VAR28) begin
VAR6 <= VAR18;
VAR12 <= VAR3;
VAR10 <= VAR37;
end
reg VAR19;
reg [4:0] VAR13;
always @(posedge VAR28) begin
if(VAR40) begin
VAR19 <= 1'b0;
VAR13 <= 5'd0;
end else begin
VAR19 <= VAR8 ? (VAR13 == 5'd31) : (VAR13[1:0] == 2'd3);
VAR13 <= VAR13 + 5'd1;
end
end
reg VAR32;
reg VAR23;
reg VAR35;
reg VAR27;
reg [2:0] VAR7;
reg [2:0] VAR20;
reg [6:0] VAR9;
always @(posedge VAR28) begin
if(VAR32) begin
VAR35 <= 1'b1;
VAR20 <= 3'd0;
end else if(VAR19) begin
if(VAR23) begin
VAR35 <= 1'b0;
VAR27 <= VAR34[0];
VAR7 <= 3'd0;
if(VAR34[0])
VAR20 <= VAR20 + 3'd1;
end
else
VAR20 <= 3'd0;
VAR9 <= VAR34[7:1];
end else if(~VAR35) begin
if(VAR20 == 3'd6) begin
VAR20 <= 3'd0;
VAR27 <= 1'b0;
if(VAR7 == 3'd7)
VAR35 <= 1'b1;
end else begin
VAR27 <= VAR9[0];
if(VAR9[0])
VAR20 <= VAR20 + 3'd1;
end
else
VAR20 <= 3'd0;
VAR7 <= VAR7 + 3'd1;
if((VAR7 == 3'd6) & (~VAR9[0] | (VAR20 != 3'd5)))
VAR35 <= 1'b1;
VAR9 <= {1'b0, VAR9[6:1]};
end
end
end
end
reg VAR14;
reg VAR24;
reg VAR4;
always @(posedge VAR28) begin
if(VAR40) begin
VAR37 <= 1'b0;
VAR18 <= ~VAR8;
VAR3 <= VAR8;
end else if(VAR19) begin
if(~VAR14) begin
VAR18 <= ~VAR8;
VAR3 <= VAR8;
end else begin
case({VAR24, VAR4})
2'b00: begin
if(~VAR27) begin
VAR18 <= ~VAR18;
VAR3 <= ~VAR3;
end
end
2'b10: begin
VAR18 <= 1'b0;
VAR3 <= 1'b0;
end
2'b01: begin
VAR18 <= ~VAR8;
VAR3 <= VAR8;
end
default: begin
VAR18 <= 1'VAR29;
VAR3 <= 1'VAR29;
end
endcase
end
VAR37 <= VAR14;
end
end
parameter VAR38 = 3'd0;
parameter VAR36 = 3'd1;
parameter VAR39 = 3'd2;
parameter VAR21 = 3'd3;
parameter VAR2 = 3'd4;
parameter VAR25 = 3'd5;
parameter VAR5 = 3'd6;
parameter VAR1 = 3'd7;
reg [2:0] state;
reg [2:0] VAR11;
always @(posedge VAR28) begin
if(VAR40)
state <= VAR38;
end
else if(VAR19)
state <= VAR11;
end
reg VAR33;
always @(posedge VAR28)
VAR17 <= VAR33 & VAR19;
reg VAR26;
reg VAR15;
reg VAR30;
always @(posedge VAR28) begin
if(VAR40) begin
VAR26 <= 1'b0;
VAR15 <= 1'b1;
end else begin
VAR26 <= VAR41;
if(VAR26 & ~VAR41)
VAR15 <= 1'b0;
if(VAR30)
VAR15 <= 1'b1;
end
end
reg VAR22;
reg VAR31;
always @(posedge VAR28) begin
if(VAR40)
VAR22 <= 1'b0;
end
else begin
if(VAR16)
VAR22 <= 1'b1;
if(VAR31)
VAR22 <= 1'b0;
end
end
always @(*) begin
VAR14 = 1'b0;
VAR32 = 1'b0;
VAR23 = 1'b0;
VAR24 = 1'b0;
VAR4 = 1'b0;
VAR33 = 1'b0;
VAR30 = 1'b0;
VAR31 = 1'b0;
VAR11 = state;
case(state)
VAR38: begin
VAR14 = 1'b0;
if(VAR22)
VAR11 = VAR25;
end
else begin
if(VAR41) begin
VAR23 = 1'b1;
VAR11 = VAR36;
end else
VAR32 = 1'b1;
VAR33 = 1'b1;
end
end
VAR36: begin
VAR14 = 1'b1;
if(VAR35) begin
if(VAR15) begin
VAR23 = 1'b1;
VAR33 = 1'b1;
end else
VAR11 = VAR39;
end
end
VAR39: begin
VAR30 = 1'b1;
VAR32 = 1'b1;
VAR14 = 1'b1;
VAR24 = 1'b1;
VAR11 = VAR21;
end
VAR21: begin
VAR32 = 1'b1;
VAR14 = 1'b1;
VAR24 = 1'b1;
VAR11 = VAR2;
end
VAR2: begin
VAR32 = 1'b1;
VAR14 = 1'b1;
VAR4 = 1'b1;
VAR11 = VAR38;
end
VAR25: begin
VAR32 = 1'b1;
VAR14 = 1'b1;
VAR24 = 1'b1;
VAR11 = VAR5;
end
VAR5: begin
VAR32 = 1'b1;
VAR14 = 1'b1;
VAR24 = 1'b1;
VAR11 = VAR1;
end
VAR1: begin
VAR31 = 1'b1;
VAR32 = 1'b1;
VAR14 = 1'b1;
VAR4 = 1'b1;
VAR11 = VAR38;
end
endcase
end
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3/sky130_fd_sc_hs__nand3.blackbox.v | 1,224 | module MODULE1 (
VAR4,
VAR5,
VAR6,
VAR1
);
output VAR4;
input VAR5;
input VAR6;
input VAR1;
supply1 VAR2;
supply0 VAR3;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | mult16_12_bb.v | 4,101 | module MODULE1 (
VAR1,
VAR2,
VAR3,
VAR4);
input VAR1;
input [15:0] VAR2;
input [15:0] VAR3;
output [31:0] VAR4;
endmodule | mit |
jotego/jt12 | hdl/jt12_eg_step.v | 3,296 | module MODULE1(
input VAR12,
input [ 4:0] VAR13,
input [ 4:0] VAR10,
input [14:0] VAR14,
input VAR9,
input [ 1:0] VAR11,
output VAR15,
output reg VAR7,
output reg [5:0] VAR3,
output reg VAR6
);
reg [6:0] VAR1;
always @
VAR3 = VAR1[6] ? 6'd63 : VAR1[5:0];
reg [2:0] VAR8;
reg [4:0] VAR4;
always @
case( VAR4 )
5'h0: VAR8 = VAR14[14:12];
5'h1: VAR8 = VAR14[13:11];
5'h2: VAR8 = VAR14[12:10];
5'h3: VAR8 = VAR14[11: 9];
5'h4: VAR8 = VAR14[10: 8];
5'h5: VAR8 = VAR14[ 9: 7];
5'h6: VAR8 = VAR14[ 8: 6];
5'h7: VAR8 = VAR14[ 7: 5];
5'h8: VAR8 = VAR14[ 6: 4];
5'h9: VAR8 = VAR14[ 5: 3];
5'ha: VAR8 = VAR14[ 4: 2];
5'hb: VAR8 = VAR14[ 3: 1];
default: VAR8 = VAR14[ 2: 0];
endcase
reg [7:0] VAR2;
always @ begin
VAR6 = VAR8[0] != VAR9;
end
endmodule VAR5 | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v | 123,052 | module MODULE1 #
(
parameter VAR152 = 100,
parameter VAR75 = 2, parameter VAR184 = 3333, parameter VAR36 = 2,
parameter VAR41 = 10,
parameter VAR212 = 1, parameter VAR209 = 64,
parameter VAR179 = 14,
parameter VAR110 = 1,
parameter VAR206 = 1, parameter VAR234 = "VAR57",
parameter VAR147 = "VAR128",
parameter VAR94 = 16'h0000, parameter VAR38 = 12'h000, parameter VAR62 = 3'h0,
parameter VAR200 = "0", parameter VAR141 = "8", parameter VAR67 = "VAR199", parameter VAR203 = 0, parameter VAR151 = 5, parameter VAR176 = 5, parameter VAR44 = 110000, parameter VAR12 = "VAR88", parameter VAR9 = "60", parameter VAR243 = "60", parameter VAR63 = "VAR128", parameter VAR52 = "VAR128", parameter VAR27 = "VAR92", parameter VAR82 = 1, parameter VAR156 = "VAR114", parameter VAR113 = "VAR114" )
(
input clk,
input rst,
input [2:0] VAR225,
input VAR172,
input VAR131,
input VAR22,
input [7:0] VAR119,
input [7:0] VAR236,
output reg VAR241,
input [1:0] VAR187,
output reg [1:0] VAR24,
input VAR87,
output reg VAR80,
input VAR93,
input VAR19,
output [1:0] VAR45,
output reg VAR118,
input VAR104,
input VAR47,
output reg VAR222,
output reg VAR66,
output reg [VAR179-1:0] VAR30,
output reg [VAR179-1:0] VAR166,
output reg [VAR36-1:0] VAR192,
output reg [VAR36-1:0] VAR84,
output reg VAR17,
output reg VAR13,
output reg [VAR206-1:0] VAR89,
output reg [VAR206-1:0] VAR215,
output reg [VAR110*VAR212-1:0] VAR250,
output reg [VAR110*VAR212-1:0] VAR213,
output VAR201,
output reg [VAR110*VAR212-1:0] VAR193,
output reg [VAR110*VAR212-1:0] VAR43,
output reg VAR53,
output reg VAR154,
output reg VAR160,
output reg VAR26,
output reg VAR230,
output reg VAR72,
output reg [4*VAR209-1:0] VAR208,
output reg VAR182,
output reg [0:0] VAR180,
output reg VAR5
);
localparam VAR107 = "40";
localparam VAR232 = "40";
localparam VAR85 = (VAR234 == "VAR57")? 1'b0 :
(VAR141 == "8") ? 1'b0 :
((VAR141 == "4") ? 1'b1 : 1'b0);
localparam VAR161 = VAR184 / VAR75;
localparam VAR99 = 200000;
localparam VAR139 = 500000 + VAR99;
localparam VAR134 = 200000;
localparam VAR28 =
((VAR99+VAR184-1)/VAR184);
localparam VAR108 = (VAR234 == "VAR57") ?
(((VAR139+VAR184-1)/VAR184)) :
(((VAR134+VAR184-1)/VAR184));
localparam VAR95 = 400000;
localparam VAR163 =
((VAR95+VAR184-1)/VAR184)-1;
localparam VAR124 =
(5*VAR161 > VAR44+10000) ?
(((5+VAR75-1)/VAR75)-1)+5 :
(((VAR44+10000+VAR184-1)/VAR184)-1)+5;
localparam VAR50 = 255;
localparam VAR157 = ((15000) % VAR161) ?
(15000/VAR161) + 1 : 15000/VAR161;
localparam VAR60 = 7'b1111111;
localparam VAR101 = 2'b00;
localparam VAR164 = 2'b01;
localparam VAR233 = 2'b10;
localparam VAR245 = 2'b11;
localparam VAR169 = 2'b11;
localparam VAR202 = 8'b00000000;
localparam VAR231 = (VAR110 <= 2) ? 8'b00110001 : 8'b00000001;
localparam VAR211 = 8'b00000010;
localparam VAR207 = 8'b00000011;
localparam VAR210 = 8'b00000100;
localparam VAR239 = 8'b00000101;
localparam VAR54 = (VAR147 == "VAR128") ? VAR176 + 1 : VAR176;
localparam VAR125 = 6'b000000; localparam VAR181 = 6'b000001; localparam VAR8 = 6'b000010; localparam VAR121 = 6'b000011; localparam VAR86 = 6'b000100; localparam VAR252 = 6'b000101; localparam VAR183 = 6'b000110; localparam VAR171 = 6'b000111; localparam VAR98 = 6'b001000; localparam VAR55 = 6'b001001; localparam VAR216 = 6'b001010; localparam VAR168 = 6'b001011; localparam VAR97 = 6'b001100; localparam VAR224 = 6'b001101; localparam VAR18 = 6'b001110; localparam VAR198 = 6'b001111; localparam VAR51 = 6'b010000; localparam VAR170 = 6'b010001; localparam VAR4 = 6'b010010; localparam VAR37 = 6'b010011; localparam VAR105 = 6'b010100; localparam VAR46 = 6'b010101; localparam VAR133 = 6'b010110; localparam VAR120 = 6'b010111; localparam VAR16 = 6'b011000; localparam VAR91 = 6'b011001; localparam VAR251 = 6'b011010; localparam VAR129 = 6'b011011; localparam VAR227 = 6'b011100; localparam VAR194 = 6'b011101; localparam VAR135 = 6'b011110; localparam VAR76 = 6'b011111; localparam VAR35 = 6'b100000; localparam VAR237 = 6'b100001; localparam VAR174 = 6'b100010; localparam VAR218 = 6'b100011; localparam VAR68 = 6'b100100; localparam VAR159 = 6'b100101; localparam VAR15 = 6'b100110; localparam VAR48 = 6'b100111; localparam VAR220 = 6'b101000; localparam VAR173 = 6'b101001; localparam VAR109 = 6'b101010;
reg [1:0] VAR25;
reg [1:0] VAR10;
reg [1:0] VAR11;
reg [6:0] VAR204;
reg VAR142;
reg [7:0] VAR144;
reg VAR74;
reg VAR214;
reg [1:0] VAR247;
reg [3:0] VAR29;
reg [1:0] VAR195;
reg VAR83;
reg VAR61;
reg [7:0] VAR103;
reg [9:0] VAR42;
reg VAR102;
reg [8:0] VAR64;
reg VAR33;
reg VAR3;
reg [7:0] VAR111;
reg VAR2;
reg VAR32;
reg VAR240;
reg [4:0] VAR96;
reg VAR246;
reg VAR59;
reg VAR185;
reg [5:0] VAR228;
reg [5:0] VAR189;
reg [5:0] VAR149;
wire [15:0] VAR244;
wire [15:0] VAR116;
wire [15:0] VAR150;
wire [15:0] VAR58;
reg VAR49;
reg VAR117;
reg [1:0] VAR123 [0:3];
reg [2:0] VAR40 [0:3];
reg VAR249;
reg [15:0] VAR70;
wire VAR175;
reg [VAR110*VAR212-1:0] VAR78;
reg [VAR110*VAR212-1:0] VAR56;
reg [VAR110*VAR212-1:0] VAR130;
reg [VAR110*VAR212-1:0] VAR155;
reg [VAR110*VAR212-1:0] VAR190;
wire VAR34;
reg [15:0] VAR165;
reg VAR162;
reg VAR238;
reg VAR79;
reg VAR23;
reg [VAR179-1:0] VAR188;
reg [VAR36-1:0] VAR136;
reg [15:0] VAR217;
reg [15:0] VAR221;
reg [15:0] VAR73;
wire [1:0] VAR158;
wire VAR6;
wire VAR20;
wire VAR7;
reg VAR137;
wire VAR196;
reg [2:0] VAR112;
reg [1:0] VAR186 [0:3];
reg [2:0] VAR81 [0:3];
reg VAR132;
reg VAR197;
reg VAR90;
reg VAR77;
reg VAR65;
reg [2:0] VAR226;
reg VAR248;
reg VAR31;
always @(posedge VAR117) begin
if (!rst)
end
always @(posedge VAR131) begin
if (!rst && (VAR63 == "VAR128"))
end
always @(posedge VAR187[0]) begin
if (!rst)
end
always @(posedge VAR187[1]) begin
if (!rst)
end
always @(posedge VAR87) begin
if (!rst)
end
always @(posedge VAR104) begin
if (!rst && (VAR52 == "VAR128"))
end
always @(posedge clk)
if (rst) begin
end else begin
if (VAR189 == VAR16)
end
VAR1 VAR14
(
.VAR235 (VAR201),
.VAR21 (clk),
.VAR140 (1'b1),
.VAR178 (VAR246),
.VAR153 (1'b0),
.VAR127 (1'b0)
)
;
generate
if(VAR234 == "VAR57") begin: VAR223
assign VAR244[1:0] = (VAR141 == "8") ? 2'b00 :
(VAR141 == "VAR100") ? 2'b01 :
(VAR141 == "4") ? 2'b10 : 2'b11;
assign VAR244[2] = 1'b0; assign VAR244[3] = (VAR67 == "VAR199") ? 1'b0 : 1'b1;
assign VAR244[6:4] = (VAR151 == 5) ? 3'b001 :
(VAR151 == 6) ? 3'b010 :
(VAR151 == 7) ? 3'b011 :
(VAR151 == 8) ? 3'b100 :
(VAR151 == 9) ? 3'b101 :
(VAR151 == 10) ? 3'b110 :
(VAR151 == 11) ? 3'b111 : 3'b111;
assign VAR244[7] = 1'b0;
assign VAR244[8] = 1'b1; assign VAR244[11:9] = (VAR157 == 5) ? 3'b001 :
(VAR157 == 6) ? 3'b010 :
(VAR157 == 7) ? 3'b011 :
(VAR157 == 8) ? 3'b100 :
(VAR157 == 9) ? 3'b101 :
(VAR157 == 10) ? 3'b101 :
(VAR157 == 11) ? 3'b110 :
(VAR157 == 12) ? 3'b110 : 3'b010;
assign VAR244[12] = 1'b0; assign VAR244[15:13] = 3'b000;
end else if (VAR234 == "VAR242") begin: VAR148 assign VAR244[2:0] = (VAR141 == "8") ? 3'b011 :
(VAR141 == "4") ? 3'b010 : 3'b111;
assign VAR244[3] = (VAR67 == "VAR199") ? 1'b0 : 1'b1;
assign VAR244[6:4] = (VAR151 == 3) ? 3'b011 :
(VAR151 == 4) ? 3'b100 :
(VAR151 == 5) ? 3'b101 :
(VAR151 == 6) ? 3'b110 : 3'b111;
assign VAR244[7] = 1'b0;
assign VAR244[8] = 1'b1; assign VAR244[11:9] = (VAR157 == 2) ? 3'b001 :
(VAR157 == 3) ? 3'b010 :
(VAR157 == 4) ? 3'b011 :
(VAR157 == 5) ? 3'b100 :
(VAR157 == 6) ? 3'b101 : 3'b010;
assign VAR244[15:12]= 4'b0000; end
endgenerate
generate
if(VAR234 == "VAR57") begin: VAR106
assign VAR116[0] = 1'b0; assign VAR116[1] = (VAR12 == "VAR177") ? 1'b0 : 1'b1;
assign VAR116[2] = ((VAR9 == "30") || (VAR9 == "40") ||
(VAR9 == "60")) ? 1'b1 : 1'b0;
assign VAR116[4:3] = (VAR200 == "0") ? 2'b00 :
(VAR200 == "VAR229-1") ? 2'b01 :
(VAR200 == "VAR229-2") ? 2'b10 : 2'b11;
assign VAR116[5] = 1'b0;
assign VAR116[6] = ((VAR9 == "40") || (VAR9 == "120")) ?
1'b1 : 1'b0;
assign VAR116[7] = 1'b0; assign VAR116[8] = 1'b0;
assign VAR116[9] = ((VAR9 == "20") || (VAR9 == "30")) ?
1'b1 : 1'b0;
assign VAR116[10] = 1'b0;
assign VAR116[15:11] = 5'b00000;
end else if (VAR234 == "VAR242") begin: VAR122
assign VAR116[0] = 1'b0; assign VAR116[1] = (VAR12 == "VAR177") ? 1'b1 : 1'b0;
assign VAR116[2] = ((VAR9 == "75") || (VAR9 == "50")) ?
1'b1 : 1'b0;
assign VAR116[5:3] = (VAR200 == "0") ? 3'b000 :
(VAR200 == "1") ? 3'b001 :
(VAR200 == "2") ? 3'b010 :
(VAR200 == "3") ? 3'b011 :
(VAR200 == "4") ? 3'b100 : 3'b111;
assign VAR116[6] = ((VAR9 == "50") ||
(VAR9 == "150")) ? 1'b1 : 1'b0;
assign VAR116[9:7] = 3'b000;
assign VAR116[10] = (VAR27 == "VAR92") ? 1'b0 : 1'b1;
assign VAR116[15:11] = 5'b00000;
end
endgenerate
generate
if(VAR234 == "VAR57") begin: VAR205
assign VAR150[2:0] = 3'b000;
assign VAR150[5:3] = (VAR176 == 5) ? 3'b000 :
(VAR176 == 6) ? 3'b001 :
(VAR176 == 7) ? 3'b010 :
(VAR176 == 8) ? 3'b011 : 3'b111;
assign VAR150[6] = 1'b0;
assign VAR150[7] = 1'b0;
assign VAR150[8] = 1'b0;
assign VAR150[10:9] = 2'b00;
assign VAR150[15:11] = 5'b00000;
end else begin: VAR146
assign VAR150[15:0] = 16'd0;
end
endgenerate
assign VAR58[1:0] = 2'b00;
assign VAR58[2] = 1'b0;
assign VAR58[15:3] = 13'b0000000000000;
assign VAR45 = VAR11;
assign VAR158[0] = (VAR189 == VAR51);
assign VAR158[1] = (VAR189 == VAR37);
assign VAR6 = (VAR189 == VAR109);
assign VAR175 = (VAR189 == VAR218);
assign VAR34 = (((VAR189 == VAR51) ||
(VAR189 == VAR37) ||
(VAR189 == VAR109) ||
(VAR189 == VAR218)) &&
VAR162 &&
!VAR238);
always @(posedge clk) begin
VAR158[0]};
VAR158[1]};
VAR6};
VAR175};
VAR34};
end
always @(posedge clk)
always @(posedge clk)
if (rst) begin
end else begin
if (VAR217[15])
if (VAR221[15])
if (VAR73[15])
if (VAR70[15])
end
always @ (posedge clk)
if (rst)
end
else if (VAR189 == VAR183)
end
else if (VAR96 > 5'd0)
always @(posedge clk)
if (rst || VAR22 || VAR131)
end
else if ((VAR96 == 5'd1) && !VAR241)
always @(posedge clk)
if (rst || VAR22 || VAR131)
end
else if (VAR96 == 5'd14)
always @(posedge clk) begin
VAR31 <= VAR248;
end
always @ (posedge clk) begin
if (rst)
end
else if (VAR22)
end
assign VAR145 = VAR93 | VAR47;
always @(posedge clk)
if (rst) begin
end else begin
if (VAR238)
end
else if (VAR34)
end
always @(posedge clk) begin
case (VAR189)
VAR121,
VAR55,
VAR168,
VAR224,
VAR198,
VAR4,
VAR173,
VAR105,
VAR174,
VAR46,
VAR120,
VAR135,
VAR159,
VAR35:
VAR171:
default:
endcase
end
always @(posedge clk)
always @(posedge clk)
if (rst) begin
end else begin
end
always @(posedge clk)
if (rst)
end
else if (VAR23)
always @(posedge clk)
if (rst) begin
end else begin
if ((VAR156 == "VAR191") ||
(VAR156 == "VAR39")) begin
end else begin
if (VAR234 == "VAR57") begin
if (!VAR33)
VAR33
if (!VAR102)
VAR102
VAR102
end
end
end
always @(posedge clk) begin
end
always @(posedge clk)
if (!VAR102) begin
end else begin
if (!VAR3)
end
always @(posedge clk)
if (!VAR102) begin
end else begin
if (!VAR61)
VAR61
end
always @(posedge clk)
if (VAR189 == VAR86) begin
end else begin
if (!VAR74)
VAR74
end
always @(posedge clk)
if ((VAR189 == VAR125)||
((VAR189 == VAR76)
&& (~VAR117))) begin
end else if (VAR189 == VAR8) begin
end
always @(posedge clk)
if (VAR189 == VAR125)
end
else if (VAR189 == VAR8)
end
else if ((VAR32) &&
(VAR189 == VAR121)&&
(VAR142) && (VAR83))
always @(posedge clk)
if (VAR189 == VAR125)
end
else if ((VAR189 == VAR76) && (~VAR117))
end
else if ((VAR32) &&
(VAR189 == VAR121)&&
(VAR142) && (VAR83))
always @(posedge clk)
if (VAR189 == VAR125) begin
end else if ((VAR189 == VAR76) && (~VAR117)) begin
end
always @(posedge clk)
if (VAR189 == VAR125)
end
else if (VAR189 == VAR68)
always @(posedge clk)
if (rst)begin
end else begin
end
always @(VAR10 or VAR11 or VAR142
or VAR74 or VAR214
or VAR83
or VAR61 or VAR102
or VAR3 or VAR2
or VAR32 or VAR240
or VAR189 or VAR117
or VAR104 or VAR238
or VAR187 or VAR87 or VAR19
or VAR24 or VAR80 or VAR172
or VAR112 or VAR197 or VAR65) begin
VAR228 = VAR189;
case (VAR189)
VAR125:
if (VAR102 && VAR172) begin
if (VAR156 == "VAR39")
if (VAR63 == "VAR128")
VAR228 = VAR183;
end
else if (VAR113 != "VAR167")
VAR228 = VAR97;
end
else
VAR228 = VAR16;
end
else
VAR228 = VAR181;
end
VAR181:
if ((VAR3) && (VAR234 == "VAR57")) begin
if((VAR147 == "VAR128") && ((VAR212 > 1) ||
(VAR110 > 1)))
VAR228 = VAR68;
end
else
VAR228 = VAR8;
end else if ((VAR61) && (VAR234 == "VAR242"))
VAR228 = VAR194;
VAR68:
VAR228 = VAR159;
VAR159:
if (VAR142) begin
if(VAR112 == 3'd5)
VAR228 = VAR8;
end
else
VAR228 = VAR68;
end
VAR8:
VAR228 = VAR121;
VAR121:
if (VAR142) begin
if(&VAR187)
VAR228 = VAR133;
end
else if (VAR83)begin
if(VAR234 == "VAR57")
VAR228 = VAR86;
end
else begin if(VAR32)begin
if (!VAR117 && (VAR11 <= VAR110-1))
VAR228 = VAR15;
end
else
VAR228 = VAR97;
end else
VAR228 = VAR194;
end
end else
VAR228 = VAR8;
end
VAR15:
VAR228 = VAR48;
VAR48:
VAR228 = VAR194;
VAR86:
VAR228 = VAR252;
VAR252:
if (VAR74)
if (!VAR49 && (VAR11 <= VAR110-1))
VAR228 = VAR8;
else if (VAR63 == "VAR128")
VAR228 = VAR183;
else
VAR228 = VAR97;
VAR194:
VAR228 = VAR135;
VAR135:
if (VAR142) begin
if(VAR2)
VAR228 = VAR76;
end
else VAR228 = VAR8;
end
VAR76:
VAR228 = VAR35;
VAR35:
if (VAR142)begin
if(VAR214 && (~VAR117))
VAR228 = VAR8;
end
else if (VAR117)begin
if(VAR25 < (VAR110))
VAR228 = VAR76;
end
else if ((&VAR187) && (VAR52 == "VAR128"))
VAR228 = VAR237;
else
VAR228 = VAR97;
end else VAR228 = VAR76;
end
VAR183:
VAR228 = VAR171;
VAR171:
if (VAR65)
VAR228 = VAR98;
VAR98:
VAR228 = VAR55;
VAR55:
if (VAR142)
VAR228 = VAR216;
VAR216:
VAR228 = VAR168;
VAR168:
if (VAR142) begin
if (~VAR197)
VAR228 = VAR183;
end
else if (VAR113 == "VAR167")
VAR228 = VAR16;
else
VAR228 = VAR97;
end
VAR97:
VAR228 = VAR224;
VAR224:
if (VAR142) begin
if (!VAR187[0] && !VAR24[0])
VAR228 = VAR91;
end
else if (!VAR187[0] && VAR24[0])
VAR228 = VAR251;
else if (!VAR87 && !VAR80)
VAR228 = VAR91;
else if (!VAR87 && VAR80)
VAR228 = VAR251;
else if (!VAR187[1] && !VAR24[1])
VAR228 = VAR91;
else if (!VAR187[1] && VAR24[1])
VAR228 = VAR251;
else
VAR228 = VAR46;
end
VAR18:
if (VAR10 == 2'b11)
VAR228 = VAR198;
VAR198:
if (VAR142)
VAR228 = VAR251;
VAR51:
if (VAR187[0] || VAR238)
VAR228 = VAR46;
VAR220:
if (VAR10 == 2'b11)
VAR228 = VAR173;
VAR173:
if (VAR142)
VAR228 = VAR251;
VAR109:
if (VAR87 || VAR238)
VAR228 = VAR46;
VAR170:
if (VAR10 == 2'b11)
VAR228 = VAR4;
VAR4:
if (VAR142)
VAR228 = VAR251;
VAR37:
if (VAR10 == 2'b01)
VAR228 = VAR105;
VAR105:
if (VAR19)
VAR228 = VAR91;
else if (VAR187[1] || VAR238)
VAR228 = VAR46;
else if (VAR142)
VAR228 = VAR37;
VAR237:
VAR228 = VAR174;
VAR174:
if (VAR142)
VAR228 = VAR251;
VAR218:
if (VAR104 || VAR238)
VAR228 = VAR46;
VAR46:
if (VAR142)
VAR228 = VAR133;
VAR133:
VAR228 = VAR120;
VAR120:
if (VAR142) begin
if ((VAR104 || (VAR52 != "VAR128")) && (&VAR187)
&& ( (VAR240)|| (VAR234 == "VAR242")))
VAR228 = VAR16;
end
else if ((VAR104 || (VAR52 != "VAR128")) && (&VAR187))
VAR228 = VAR8;
else
VAR228 = VAR76;
end
VAR91:
VAR228 = VAR129;
VAR129:
if (!VAR187[0])
VAR228 = VAR18;
else if (!VAR87)
VAR228 = VAR220;
else
VAR228 = VAR170;
VAR251:
VAR228 = VAR227;
VAR227:
if (!VAR187[0])
VAR228 = VAR51;
else if (!VAR87)
VAR228 = VAR109;
else if (!VAR187[1])
VAR228 = VAR37;
else
VAR228 = VAR218;
VAR16:
VAR228 = VAR16;
endcase
end
always @(posedge clk)
if (rst)
else if ((!VAR74 &&
(VAR144 == VAR50) &&
(VAR11 == VAR110-1) && (VAR234 == "VAR57"))
|| ( (VAR189 == VAR121) &&
(VAR32) && (VAR11 == VAR110-1)
&& (VAR83) && (VAR234 == "VAR242")))
always @(posedge clk)
always @(posedge clk)
if (rst)
else if ((VAR189 == VAR121) &&
(VAR11 == VAR110-1) && (&VAR187))
always @(posedge clk)
if (rst || (VAR132 &&
(VAR189==VAR168))
|| ((VAR49 & (~VAR117))
&& (VAR234 == "VAR242"))) begin
end else if (((VAR149 == VAR76) &&
VAR117) )begin
if (VAR11 < VAR110-1)
end
else
end else if ((((VAR189 == VAR252) &&
(VAR144 == VAR50)) ||
((VAR189!=VAR168) &&
(VAR228==VAR168)) &&
(VAR234 == "VAR57")) ||
((VAR189 == VAR15)
&& (VAR234 == "VAR242")) ||
((VAR189 == VAR121) &&
(VAR142)&& (&VAR187)))
begin
if (((~VAR117 || (&VAR187)) &&
(VAR11 != VAR110-1)) ||
(VAR117 && ~(&VAR187) &&
(VAR11 != VAR225 -1)))
end
else
end
always @(posedge clk)begin
if (rst || VAR189 == VAR133)
end
else if (VAR189 == VAR76 && VAR117) begin
if (VAR25 < VAR110)
end
end
always @(posedge clk)
if (rst) begin
end else begin
if (VAR189 == VAR68) begin
end else if (VAR248) begin
if ((VAR147 == "VAR69") && (VAR212 > 1))
end
else begin
end
end else if ((VAR189 == VAR8) ||
(VAR189 == VAR86) ||
(VAR189 == VAR183) ||
(VAR189 == VAR98) ||
(VAR189 == VAR216) ||
(VAR189 == VAR97) ||
(VAR189 == VAR18) ||
(VAR189 == VAR51) ||
(VAR189 == VAR133) ||
(VAR189 == VAR37) ||
(VAR189 == VAR170) ||
(VAR189 == VAR109) ||
(VAR189 == VAR220) ||
(VAR189 == VAR237) ||
(VAR189 == VAR218) ||
(VAR189 == VAR194) ||
(VAR189 == VAR76)) begin
end
end
assign VAR7 = (VAR189 == VAR18) ||
(VAR189 == VAR170) ||
(VAR189 == VAR220);
assign VAR20 = (VAR189 == VAR51) ||
(VAR189 == VAR37) ||
(VAR189 == VAR109) ||
(VAR189 == VAR218);
assign VAR196 = VAR7 | VAR20;
always @(posedge clk)
if (VAR20)
end
else if (VAR7)
end
else
always @(posedge clk)
if (VAR196) begin
if (VAR85)
end
else
end else
always @(posedge clk) begin
end
always @(posedge clk) begin
if (VAR54 <= 4) begin
end else if (VAR54 == 5) begin
end else if (VAR54 == 6) begin
end else if (VAR54 == 7) begin
end else if (VAR54 == 8) begin
end else if (VAR54 == 9) begin
end
end
always @(posedge clk) begin
if (VAR189 == VAR91) begin
end else if (VAR189 == VAR251) begin
end else
end
always @(posedge clk)
always @(posedge clk)
if (VAR72)
end
else if ((VAR189 == VAR125) ||
(VAR189 == VAR18))
end
else if (VAR189 == VAR220)
end
else if (VAR189 == VAR170)
always @(posedge clk)
case (VAR29)
4'b0000, 4'b0001, 4'b0010, 4'b0011:
{VAR209{1'b0}},{VAR209{1'b1}}};
4'b0100, 4'b0110:
{VAR209{1'b1}},{VAR209{1'b1}}};
4'b0101, 4'b0111:
{VAR209{1'b0}},{VAR209{1'b0}}};
4'b1000:
{VAR209/4{4'h0}},{VAR209/4{4'hF}}};
4'b1001:
{VAR209/4{4'hA}},{VAR209/4{4'h5}}};
4'b1010, 4'b1011:
{VAR209/4{4'h0}},{VAR209/4{4'h0}}};
endcase
always @(posedge clk) begin
if ((VAR189 == VAR8) ||
(VAR189 == VAR68) ||
(VAR189 == VAR183) ||
(VAR189 == VAR98) ||
(VAR189 == VAR216) ||
(VAR189 == VAR97) ||
(VAR189 == VAR237) ||
(VAR189 == VAR133) ||
(VAR189 == VAR194) ||
(VAR189 == VAR76))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR189 == VAR8) ||
(VAR189 == VAR68) ||
(VAR189 == VAR183) ||
(VAR189 == VAR98) ||
(VAR189 == VAR216) ||
(VAR189 == VAR76) ||
(VAR196 && VAR249))begin
end else begin
end
end
always @(posedge clk) begin
if ((VAR189 == VAR8) ||
(VAR189 == VAR68) ||
(VAR189 == VAR86) ||
(VAR189 == VAR183) ||
(VAR189 == VAR98) ||
(VAR189 == VAR216) ||
(VAR189 == VAR133) ||
(VAR189 == VAR194)||
(VAR7 && VAR249))begin
end else begin
end
end
generate
genvar VAR126;
for (VAR126 = 0; VAR126 < 4; VAR126 = VAR126 + 1) begin: VAR143
always @(posedge clk) begin
if (rst) begin
end else begin
end
end
end
endgenerate
generate
if (VAR82 == 1) begin: VAR219
always @(posedge clk) begin
case ({VAR119[0],VAR119[1],
VAR119[2],VAR119[3]})
4'b1111: begin
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131 &&
(VAR226==3'd0))) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
VAR190[((VAR11*VAR212)
end
4'b1000: begin
if ((VAR147 == "VAR128") && (VAR212 > 1)) begin
end else begin
end
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131)) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b1100: begin
VAR190[((VAR11*VAR212)
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131 &&
(VAR226==3'd0))) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
default: begin
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131)) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
endcase
end
end else if (VAR82 == 2) begin: VAR138
always @ (posedge clk) begin
case ({VAR119[0],VAR119[1],
VAR236[0],VAR236[1]})
4'b1000: begin
if (VAR248 || (VAR189 == VAR129) ||
(VAR189 == VAR18) ||
(VAR189 == VAR170) ||
(VAR189 == VAR220)) begin
end
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131)) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b0010: begin
if (VAR248 || (VAR189 == VAR129) ||
(VAR189 == VAR18) ||
(VAR189 == VAR170) ||
(VAR189 == VAR220)) begin
end
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131)) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b0011: begin
if (VAR248 || (VAR189 == VAR129) ||
(VAR189 == VAR18) ||
(VAR189 == VAR170) ||
(VAR189 == VAR220)) begin
VAR78[VAR212-1:0]
VAR56[VAR212-1:0]
end
VAR190[(VAR11*VAR212) +: VAR212]
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131 &&
(VAR226==3'd0))) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b1100: begin
if (VAR248 || (VAR189 == VAR129) ||
(VAR189 == VAR18) ||
(VAR189 == VAR170) ||
(VAR189 == VAR220)) begin
end
VAR190[(VAR11*VAR212) +: VAR212]
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131 &&
(VAR226==3'd0))) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
end
end
4'b1010: begin
if (VAR234 == "VAR242")begin
if (VAR11 == 2'b00)begin
VAR78[(0*VAR212) +: VAR212]
VAR78[(1*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
end else begin
VAR78[(0*VAR212) +: VAR212]
VAR78[(1*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
end
end else begin
if (VAR248 || (VAR189 == VAR129) ||
(VAR189 == VAR18) ||
(VAR189 == VAR170) ||
(VAR189 == VAR220)) begin
VAR78[(0*VAR212) +: VAR212]
VAR78[(1*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
end else if ((VAR189 == VAR227) ||
(VAR189 == VAR51) ||
(VAR189 == VAR37) ||
(VAR189 == VAR109)) begin
if (VAR11 == 2'b00) begin
VAR78[(0*VAR212) +: VAR212]
VAR78[(1*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
end else if (VAR11 == 2'b01) begin
VAR78[(0*VAR212) +: VAR212]
VAR78[(1*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
end
end
end
VAR190[(VAR11*VAR212) +: VAR212]
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131 &&
(VAR226==3'd0))) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR9 == "120") ? 3'b010 :
(VAR9 == "20") ? 3'b100 :
(VAR9 == "30") ? 3'b101 :
3'b011;
2'b10;
(VAR9 == "120") ? 3'b010 :
(VAR9 == "20") ? 3'b100 :
(VAR9 == "30") ? 3'b101 :
3'b011;
end
end
4'b1011: begin
(VAR232 == "120") ? 3'b010 :
(VAR232 == "20") ? 3'b100 :
(VAR232 == "30") ? 3'b101 :
3'b011;
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131 &&
(VAR226==3'd0))) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR9 == "120") ? 3'b010 :
(VAR9 == "20") ? 3'b100 :
(VAR9 == "30") ? 3'b101 :
3'b011;
2'b10;
end
if (VAR234 == "VAR242")begin
if (VAR11 == 2'b00)begin
VAR78[(1*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
end else begin
VAR78[(0*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
end
end else begin
if (VAR248 || (VAR189 == VAR129) ||
(VAR189 == VAR18) ||
(VAR189 == VAR170) ||
(VAR189 == VAR220)) begin
if (VAR11[0] == 1'b1) begin
VAR78[(0*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
VAR78[(1*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
end else begin
VAR78[(0*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
VAR78[(2*VAR212) +: VAR212]
VAR56[(2*VAR212) +: VAR212]
end
end else if ((VAR189 == VAR227) ||
(VAR189 == VAR51) ||
(VAR189 == VAR37) ||
(VAR189 == VAR109)) begin
if (VAR11 == 2'b00) begin
VAR78[(2*VAR212) +: VAR212]
VAR56[(2*VAR212) +: VAR212]
end else begin
VAR78[(0*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
end
end
end
VAR190[(VAR11*VAR212) +: VAR212]
end
4'b1110: begin
(VAR107 == "120") ? 3'b010 :
(VAR107 == "20") ? 3'b100 :
(VAR107 == "30") ? 3'b101 :
3'b011;
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131 &&
(VAR226==3'd0))) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR9 == "120") ? 3'b010 :
(VAR9 == "20") ? 3'b100 :
(VAR9 == "30") ? 3'b101 :
3'b011;
2'b10;
end
if (VAR234 == "VAR242")begin
if (VAR11[1] == 1'b1)begin
VAR78[VAR212-1:0]
VAR56[VAR212-1:0]
end else begin
VAR78[(2*VAR212) +: VAR212]
VAR56[(2*VAR212) +: VAR212]
end
end else begin
if (VAR248 || (VAR189 == VAR129) ||
(VAR189 == VAR18) ||
(VAR189 == VAR170) ||
(VAR189 == VAR220)) begin
if (VAR11[1] == 1'b1) begin
VAR78[(1*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
VAR78[(2*VAR212) +: VAR212]
VAR56[(2*VAR212) +: VAR212]
end else begin
VAR78[VAR212-1:0]
VAR56[VAR212-1:0]
VAR78[(2*VAR212) +: VAR212]
VAR56[(2*VAR212) +: VAR212]
end
end else if ((VAR189 == VAR227) ||
(VAR189 == VAR51) ||
(VAR189 == VAR37) ||
(VAR189 == VAR109)) begin
if (VAR11[1] == 1'b1) begin
VAR78[(1*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
end else begin
VAR78[(2*VAR212) +: VAR212]
VAR56[(2*VAR212) +: VAR212]
end
end
end
VAR190[(VAR11*VAR212) +: VAR212]
end
4'b1111: begin
(VAR107 == "120") ? 3'b010 :
(VAR107 == "20") ? 3'b100 :
(VAR107 == "30") ? 3'b101 :
3'b011;
(VAR232 == "120") ? 3'b010 :
(VAR232 == "20") ? 3'b100 :
(VAR232 == "30") ? 3'b101 :
3'b011;
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131 &&
(VAR226==3'd0))) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
2'b10;
end
if(VAR234 == "VAR242")begin
if(VAR11[1] == 1'b1)begin
VAR78[(0*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
end else begin
VAR78[(2*VAR212) +: VAR212]
VAR56[(2*VAR212) +: VAR212]
end
end else begin
if (VAR248 || (VAR189 == VAR129) ||
(VAR189 == VAR18) ||
(VAR189 == VAR170) ||
(VAR189 == VAR220)) begin
if (VAR11[0] == 1'b1) begin
VAR78[(1*VAR212) +: VAR212]
VAR56[(1*VAR212) +: VAR212]
VAR78[(2*VAR212) +: VAR212]
VAR56[(2*VAR212) +: VAR212]
end else begin
VAR78[(0*VAR212) +: VAR212]
VAR56[(0*VAR212) +: VAR212]
VAR78[(3*VAR212) +: VAR212]
VAR56[(3*VAR212) +: VAR212]
end
end else if ((VAR189 == VAR227) ||
(VAR189 == VAR51) ||
(VAR189 == VAR37) ||
(VAR189 == VAR109)) begin
if (VAR11[0] == 1'b1) begin
VAR78[(2*VAR212) +: VAR212]
VAR56[(2*VAR212) +: VAR212]
end else begin
VAR78[(3*VAR212) +: VAR212]
VAR56[(3*VAR212) +: VAR212]
end
end end
VAR190[(VAR11*VAR212) +: VAR212]
end
default: begin
VAR190[(VAR11*VAR212) +: VAR212]
if ((VAR243 == "VAR69") ||
((VAR63=="VAR128") && ~VAR131)) begin
(VAR9 == "60") ? 3'b001 :
3'b010;
(VAR9 == "60") ? 3'b001 :
3'b010;
end else begin
2'b10;
(VAR9 == "120") ? 3'b010 :
(VAR9 == "20") ? 3'b100 :
(VAR9 == "30") ? 3'b101 :
3'b011;
2'b10;
(VAR9 == "120") ? 3'b010 :
(VAR9 == "20") ? 3'b100 :
(VAR9 == "30") ? 3'b101 :
3'b011;
end
end
endcase
end
end
endgenerate
generate
if (VAR82 == 1) begin
always @(posedge clk)
if ((((VAR9 == "VAR115") && (VAR243 == "VAR69")) ||
(VAR131 && !VAR132)) && (VAR234 == "VAR57"))begin
end
else if (((VAR234 == "VAR57")
||((VAR9 != "VAR115") && (VAR234 == "VAR242")))
&& ((VAR248) ||
(VAR189 == VAR18) ||
(VAR189 == VAR198) ||
(VAR189 == VAR170) ||
(VAR189 == VAR4) ||
(VAR189 == VAR220) ||
(VAR189 == VAR173))) begin
end else begin
end
end else if (VAR82 == 2) begin
always @(posedge clk)
if (((VAR9 == "VAR115") && (VAR243 == "VAR69")) ||
VAR22 || VAR90 ||
(VAR131 && !VAR132)) begin
end
else if (((VAR234 == "VAR57")
||((VAR9 != "VAR115") && (VAR234 == "VAR242")))
&& ((VAR31) ||
(VAR189 == VAR18) ||
(VAR189 == VAR198) ||
(VAR189 == VAR51) ||
(VAR189 == VAR220) ||
(VAR189 == VAR173) ||
(VAR189 == VAR109) ||
(VAR189 == VAR170) ||
(VAR189 == VAR4) ||
(VAR189 == VAR37) ||
(VAR189 == VAR105) ||
(VAR189 == VAR46))) begin
end else begin
end
end
endgenerate
always @(VAR10 or VAR195 or VAR11
or VAR32 or VAR189 or VAR244
or VAR116 or VAR150 or VAR58 or VAR40[VAR11][0]
or VAR40[VAR11][1] or VAR40[VAR11][2] or VAR123[VAR11]
or VAR187 or VAR196 or VAR112)begin
VAR188 = 'b0;
VAR136 = 'b0;
if ((VAR189 == VAR133) ||
(VAR189 == VAR86) ||
(VAR189 == VAR194)) begin
VAR188 = 'b0;
VAR188[10] = 1'b1;
VAR136 = 'b0;
end else if (VAR189 == VAR183) begin
VAR136[1:0] = 2'b01;
VAR188 = VAR116[VAR179-1:0];
VAR188[7] = 1'b1;
end else if (VAR189 == VAR98) begin
VAR136[1:0] = 2'b01;
VAR188 = VAR116[VAR179-1:0];
VAR188[2] = VAR40[VAR11][0];
VAR188[6] = VAR40[VAR11][1];
VAR188[9] = VAR40[VAR11][2];
end else if (VAR189 == VAR216) begin
VAR136[1:0] = 2'b10;
VAR188 = VAR150[VAR179-1:0];
VAR188[10:9] = VAR123[VAR11];
end else if ((VAR189 == VAR68)&
(VAR234 == "VAR57"))begin
VAR136 = 'b0;
VAR188 = 'b0;
case (VAR112)
VAR202[2:0]: VAR188[4:0] = VAR202[4:0];
VAR231[2:0]:begin
VAR188[4:0] = VAR231[4:0];
VAR136 = VAR231[7:5];
end
VAR211[2:0]: VAR188[4:0] = VAR211[4:0];
VAR207[2:0]: VAR188[4:0] = VAR207[4:0];
VAR210[2:0]: VAR188[4:0] = VAR210[4:0];
VAR239[2:0]: VAR188[4:0] = VAR239[4:0];
endcase
end else if (VAR189 == VAR8) begin
VAR188 = 'b0;
VAR136 = 'b0;
if(VAR234 == "VAR57")begin
if(&VAR187)begin
VAR136[1:0] = 2'b00;
VAR188 = VAR244[VAR179-1:0];
VAR188[8]= 1'b0; end else begin
case (VAR195)
VAR101: begin
VAR136[1:0] = 2'b10;
VAR188 = VAR150[VAR179-1:0];
VAR188[10:9] = VAR123[VAR11];
end
VAR164: begin
VAR136[1:0] = 2'b11;
VAR188 = VAR58[VAR179-1:0];
end
VAR233: begin
VAR136[1:0] = 2'b01;
VAR188 = VAR116[VAR179-1:0];
VAR188[2] = VAR40[VAR11][0];
VAR188[6] = VAR40[VAR11][1];
VAR188[9] = VAR40[VAR11][2];
end
VAR245: begin
VAR136[1:0] = 2'b00;
VAR188 = VAR244[VAR179-1:0];
VAR188[1:0] = 2'b00;
end
default: begin
VAR136 = {VAR36{1'VAR71}};
VAR188 = {VAR179{1'VAR71}};
end
endcase end end else begin case (VAR195)
VAR101: begin
if(~VAR32)begin
VAR136[1:0] = 2'b10;
VAR188 = VAR150[VAR179-1:0];
end else begin VAR136[1:0] = 2'b00;
VAR188 = VAR244[VAR179-1:0];
VAR188[8]= 1'b0;
end
end
VAR164: begin
if(~VAR32)begin
VAR136[1:0] = 2'b11;
VAR188 = VAR58[VAR179-1:0];
end else begin VAR136[1:0] = 2'b00;
VAR188 = VAR244[VAR179-1:0];
VAR188[8]= 1'b0;
end
end
VAR233: begin
VAR136[1:0] = 2'b01;
if(~VAR32)begin
VAR188 = VAR116[VAR179-1:0];
end else begin VAR188 = VAR116[VAR179-1:0];
VAR188[9:7] = 3'b111;
end
end
VAR245: begin
if(~VAR32)begin
VAR136[1:0] = 2'b00;
VAR188 = VAR244[VAR179-1:0];
end else begin VAR136[1:0] = 2'b01;
VAR188 = VAR116[VAR179-1:0];
if((VAR11 == 2'd1) || (VAR11 == 2'd3))begin
VAR188[2] = 'b0;
VAR188[6] = 'b0;
end
end
end
default: begin
VAR136 = {VAR36{1'VAR71}};
VAR188 = {VAR179{1'VAR71}};
end
endcase end
end else if (VAR196) begin
VAR136 = VAR62[VAR36-1:0];
VAR188[VAR179-1:VAR41] = {VAR179-VAR41{1'b0}};
VAR188[VAR41-1:0] =
{VAR38[VAR41-1:4],VAR10, 2'b00};
VAR188[12] = 1'b1;
end else if ((VAR189 == VAR97) ||
(VAR189 == VAR237)) begin
VAR136 = VAR62[VAR36-1:0];
VAR188 = VAR94[VAR179-1:0];
end else begin
VAR136 = {VAR36{1'VAR71}};
VAR188 = {VAR179{1'VAR71}};
end
end
always @(posedge clk) begin
end
endmodule | lgpl-3.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/iprepo/repo/xilinx_com_hls_get_1_0/hdl/verilog/get.v | 18,460 | module MODULE1 (
VAR20,
VAR214,
VAR36,
VAR246,
VAR16,
VAR187,
VAR178,
VAR163,
VAR2,
VAR8,
VAR110,
VAR31,
VAR44,
VAR204,
VAR170,
VAR67,
VAR183,
VAR26,
VAR211,
VAR25,
VAR244,
VAR138,
VAR238,
VAR83,
VAR155,
VAR109,
VAR64,
VAR21,
VAR102,
VAR254,
VAR40,
VAR59,
VAR69,
VAR253,
VAR229,
VAR115,
VAR50,
VAR72,
VAR53,
VAR92,
VAR173,
VAR255,
VAR142,
VAR248,
VAR243,
VAR241,
VAR257,
VAR247,
VAR181,
VAR245,
VAR62,
VAR74,
VAR60,
VAR176,
VAR260,
VAR184
);
parameter VAR120 = 1'b1;
parameter VAR89 = 1'b0;
parameter VAR139 = 9'b1;
parameter VAR218 = 9'b10;
parameter VAR249 = 9'b100;
parameter VAR151 = 9'b1000;
parameter VAR97 = 9'b10000;
parameter VAR133 = 9'b100000;
parameter VAR213 = 9'b1000000;
parameter VAR233 = 9'b10000000;
parameter VAR45 = 9'b100000000;
parameter VAR158 = 32'b00000000000000000000000000000000;
parameter VAR85 = 1'b1;
parameter VAR182 = 1;
parameter VAR143 = 32;
parameter VAR71 = 32;
parameter VAR49 = 8;
parameter VAR210 = 1;
parameter VAR51 = 1;
parameter VAR153 = 1;
parameter VAR37 = 1;
parameter VAR266 = 1;
parameter VAR136 = 32;
parameter VAR164 = 0;
parameter VAR236 = 0;
parameter VAR174 = 3;
parameter VAR216 = 32'b1;
parameter VAR223 = 1'b0;
parameter VAR202 = 3'b000;
parameter VAR105 = 2'b00;
parameter VAR212 = 4'b0000;
parameter VAR80 = 32'b1000;
parameter VAR3 = 32'b10;
parameter VAR219 = 32'b11111;
parameter VAR57 = 1'b1;
parameter VAR196 = (VAR71 / VAR49);
parameter VAR265 = (VAR136 / VAR49);
input VAR20;
input VAR214;
input VAR36;
output VAR246;
output VAR16;
output VAR187;
output VAR178;
input VAR163;
output [VAR143 - 1 : 0] VAR2;
output [VAR182 - 1 : 0] VAR8;
output [7:0] VAR110;
output [2:0] VAR31;
output [1:0] VAR44;
output [1:0] VAR204;
output [3:0] VAR170;
output [2:0] VAR67;
output [3:0] VAR183;
output [3:0] VAR26;
output [VAR210 - 1 : 0] VAR211;
output VAR25;
input VAR244;
output [VAR71 - 1 : 0] VAR138;
output [VAR196 - 1 : 0] VAR238;
output VAR83;
output [VAR182 - 1 : 0] VAR155;
output [VAR153 - 1 : 0] VAR109;
output VAR64;
input VAR21;
output [VAR143 - 1 : 0] VAR102;
output [VAR182 - 1 : 0] VAR254;
output [7:0] VAR40;
output [2:0] VAR59;
output [1:0] VAR69;
output [1:0] VAR253;
output [3:0] VAR229;
output [2:0] VAR115;
output [3:0] VAR50;
output [3:0] VAR72;
output [VAR51 - 1 : 0] VAR53;
input VAR92;
output VAR173;
input [VAR71 - 1 : 0] VAR255;
input VAR142;
input [VAR182 - 1 : 0] VAR248;
input [VAR37 - 1 : 0] VAR243;
input [1:0] VAR241;
input VAR257;
output VAR247;
input [1:0] VAR181;
input [VAR182 - 1 : 0] VAR245;
input [VAR266 - 1 : 0] VAR62;
input [31:0] VAR74;
input [31:0] VAR60;
output [31:0] VAR176;
output VAR260;
output [31:0] VAR184;
reg VAR246;
reg VAR16;
reg VAR187;
reg VAR260;
reg VAR228;
reg [8:0] VAR38 = 9'b1;
reg VAR128;
reg VAR90;
wire VAR191;
wire VAR107;
wire [31:0] VAR82;
wire [0:0] VAR78;
wire [31:0] VAR119;
wire [2:0] VAR129;
wire [1:0] VAR215;
wire [1:0] VAR179;
wire [3:0] VAR12;
wire [2:0] VAR262;
wire [3:0] VAR28;
wire [3:0] VAR175;
wire [0:0] VAR79;
wire VAR141;
wire VAR206;
wire [31:0] VAR96;
wire [3:0] VAR193;
wire VAR161;
wire [0:0] VAR148;
wire [0:0] VAR106;
reg VAR47;
wire VAR46;
wire [31:0] VAR63;
wire [0:0] VAR146;
wire [31:0] VAR200;
wire [2:0] VAR160;
wire [1:0] VAR232;
wire [1:0] VAR222;
wire [3:0] VAR165;
wire [2:0] VAR203;
wire [3:0] VAR19;
wire [3:0] VAR156;
wire [0:0] VAR199;
wire VAR98;
reg VAR135;
wire [31:0] VAR127;
wire VAR10;
wire [0:0] VAR30;
wire [0:0] VAR154;
wire [1:0] VAR54;
wire VAR22;
wire VAR73;
wire [1:0] VAR9;
wire [0:0] VAR197;
wire [0:0] VAR68;
wire VAR198;
reg [31:0] VAR149;
wire [63:0] VAR84;
reg VAR122 = 1'b0;
reg VAR267;
reg VAR114;
reg VAR201;
reg VAR99;
reg VAR81;
wire [29:0] VAR86;
wire [32:0] VAR112;
wire [32:0] VAR256;
wire [32:0] VAR209;
reg [8:0] VAR43;
VAR242 #(
.VAR77( 32 ),
.VAR166( 32 ),
.VAR227( 5 ),
.VAR108( VAR182 ),
.VAR32( VAR143 ),
.VAR136( VAR71 ),
.VAR13( VAR210 ),
.VAR52( VAR51 ),
.VAR34( VAR153 ),
.VAR93( VAR37 ),
.VAR188( VAR266 ),
.VAR134( VAR164 ),
.VAR235( VAR236 ),
.VAR131( VAR174 ))
VAR177(
.VAR87( VAR178 ),
.VAR101( VAR163 ),
.VAR137( VAR2 ),
.VAR124( VAR8 ),
.VAR58( VAR110 ),
.VAR1( VAR31 ),
.VAR27( VAR44 ),
.VAR258( VAR204 ),
.VAR171( VAR170 ),
.VAR145( VAR67 ),
.VAR118( VAR183 ),
.VAR186( VAR26 ),
.VAR264( VAR211 ),
.VAR192( VAR25 ),
.VAR208( VAR244 ),
.VAR251( VAR138 ),
.VAR180( VAR238 ),
.VAR140( VAR83 ),
.VAR226( VAR155 ),
.VAR195( VAR109 ),
.VAR7( VAR64 ),
.VAR18( VAR21 ),
.VAR94( VAR102 ),
.VAR224( VAR254 ),
.VAR126( VAR40 ),
.VAR234( VAR59 ),
.VAR41( VAR69 ),
.VAR104( VAR253 ),
.VAR190( VAR229 ),
.VAR159( VAR115 ),
.VAR17( VAR50 ),
.VAR35( VAR72 ),
.VAR123( VAR53 ),
.VAR261( VAR92 ),
.VAR205( VAR173 ),
.VAR100( VAR255 ),
.VAR150( VAR142 ),
.VAR263( VAR248 ),
.VAR11( VAR243 ),
.VAR70( VAR241 ),
.VAR207( VAR257 ),
.VAR5( VAR247 ),
.VAR194( VAR181 ),
.VAR23( VAR245 ),
.VAR162( VAR62 ),
.VAR237( VAR20 ),
.VAR14( VAR228 ),
.VAR259( VAR198 ),
.VAR189( VAR47 ),
.VAR230( VAR46 ),
.VAR65( VAR63 ),
.VAR33( VAR146 ),
.VAR220( VAR200 ),
.VAR117( VAR160 ),
.VAR250( VAR222 ),
.VAR113( VAR165 ),
.VAR185( VAR19 ),
.VAR252( VAR203 ),
.VAR39( VAR199 ),
.VAR55( VAR232 ),
.VAR217( VAR156 ),
.VAR157( VAR98 ),
.VAR147( VAR135 ),
.VAR15( VAR127 ),
.VAR231( VAR30 ),
.VAR56( VAR154 ),
.VAR130( VAR54 ),
.VAR121( VAR10 ),
.VAR172( VAR191 ),
.VAR66( VAR107 ),
.VAR6( VAR82 ),
.VAR48( VAR78 ),
.VAR144( VAR119 ),
.VAR95( VAR129 ),
.VAR4( VAR179 ),
.VAR168( VAR12 ),
.VAR225( VAR28 ),
.VAR240( VAR262 ),
.VAR42( VAR79 ),
.VAR111( VAR215 ),
.VAR24( VAR175 ),
.VAR132( VAR141 ),
.VAR29( VAR206 ),
.VAR239( VAR96 ),
.VAR91( VAR148 ),
.VAR116( VAR106 ),
.VAR75( VAR161 ),
.VAR221( VAR193 ),
.VAR103( VAR22 ),
.VAR76( VAR73 ),
.VAR152( VAR9 ),
.VAR125( VAR197 ),
.VAR169( VAR68 )
);
always @ (posedge VAR20) begin : VAR61
if (VAR228 == 1'b1) begin
VAR38 <= VAR139;
end else begin
VAR38 <= VAR43;
end
end
always @ (posedge VAR20) begin : VAR88
if (VAR228 == 1'b1) begin
VAR122 <= VAR89;
end else begin
if ((VAR120 == VAR114)) begin
if (~(VAR89 == VAR267)) begin
VAR122 <= VAR89;
end else if ((VAR120 == VAR46)) begin
VAR122 <= VAR120;
end
end
end
end
always @ (posedge VAR20) begin
if (((VAR120 == VAR128) & ~(VAR36 == VAR89))) begin
VAR149 <= VAR84;
end
end
always @ (VAR98 or VAR99) begin
if (((VAR120 == VAR99) & ~(VAR98 == VAR89))) begin
VAR246 = VAR120;
end else begin
VAR246 = VAR89;
end
end
always @ (VAR36 or VAR128) begin
if ((~(VAR120 == VAR36) & (VAR120 == VAR128))) begin
VAR16 = VAR120;
end else begin
VAR16 = VAR89;
end
end
always @ (VAR98 or VAR99) begin
if (((VAR120 == VAR99) & ~(VAR98 == VAR89))) begin
VAR187 = VAR120;
end else begin
VAR187 = VAR89;
end
end
always @ (VAR90) begin
if (VAR90) begin
VAR128 = VAR120;
end else begin
VAR128 = VAR89;
end
end
always @ (VAR201) begin
if (VAR201) begin
VAR114 = VAR120;
end else begin
VAR114 = VAR89;
end
end
always @ (VAR81) begin
if (VAR81) begin
VAR99 = VAR120;
end else begin
VAR99 = VAR89;
end
end
always @ (VAR46 or VAR122) begin
if ((VAR89 == VAR122)) begin
VAR267 = VAR46;
end else begin
VAR267 = VAR120;
end
end
always @ (VAR122 or VAR114) begin
if (((VAR120 == VAR114) & (VAR89 == VAR122))) begin
VAR47 = VAR120;
end else begin
VAR47 = VAR89;
end
end
always @ (VAR98 or VAR99) begin
if (((VAR120 == VAR99) & ~(VAR98 == VAR89))) begin
VAR135 = VAR120;
end else begin
VAR135 = VAR89;
end
end
always @ (VAR98 or VAR99) begin
if (((VAR120 == VAR99) & ~(VAR98 == VAR89))) begin
VAR260 = VAR120;
end else begin
VAR260 = VAR89;
end
end
always @ (VAR36 or VAR38 or VAR98 or VAR267) begin
case (VAR38)
VAR139 :
begin
if (~(VAR36 == VAR89)) begin
VAR43 = VAR218;
end else begin
VAR43 = VAR139;
end
end
VAR218 :
begin
if (~(VAR89 == VAR267)) begin
VAR43 = VAR249;
end else begin
VAR43 = VAR218;
end
end
VAR249 :
begin
VAR43 = VAR151;
end
VAR151 :
begin
VAR43 = VAR97;
end
VAR97 :
begin
VAR43 = VAR133;
end
VAR133 :
begin
VAR43 = VAR213;
end
VAR213 :
begin
VAR43 = VAR233;
end
VAR233 :
begin
VAR43 = VAR45;
end
VAR45 :
begin
if (~(VAR98 == VAR89)) begin
VAR43 = VAR139;
end else begin
VAR43 = VAR45;
end
end
default :
begin
VAR43 = 'VAR167;
end
endcase
end
assign VAR184 = VAR158;
always @ (VAR214) begin
VAR228 = ~VAR214;
end
always @ (VAR38) begin
VAR201 = (VAR85 == VAR38[VAR216]);
end
always @ (VAR38) begin
VAR81 = (VAR85 == VAR38[VAR80]);
end
always @ (VAR38) begin
VAR90 = (VAR38[VAR158] == VAR85);
end
assign VAR84 = VAR209;
assign VAR209 = (VAR112 + VAR256);
assign VAR198 = VAR120;
assign VAR63 = VAR149;
assign VAR232 = VAR105;
assign VAR165 = VAR212;
assign VAR146 = VAR223;
assign VAR200 = VAR216;
assign VAR222 = VAR105;
assign VAR203 = VAR202;
assign VAR19 = VAR212;
assign VAR156 = VAR212;
assign VAR160 = VAR202;
assign VAR199 = VAR223;
assign VAR82 = VAR158;
assign VAR215 = VAR105;
assign VAR12 = VAR212;
assign VAR78 = VAR223;
assign VAR119 = VAR158;
assign VAR179 = VAR105;
assign VAR262 = VAR202;
assign VAR28 = VAR212;
assign VAR175 = VAR212;
assign VAR129 = VAR202;
assign VAR79 = VAR223;
assign VAR191 = VAR89;
assign VAR73 = VAR89;
assign VAR96 = VAR158;
assign VAR148 = VAR223;
assign VAR161 = VAR89;
assign VAR193 = VAR212;
assign VAR106 = VAR223;
assign VAR141 = VAR89;
assign VAR256 = VAR86;
assign VAR112 = VAR60;
assign VAR86 = {{VAR74[VAR219 : VAR3]}};
assign VAR176 = VAR127;
endmodule | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_clk_gen/bsg_nonsynth_clk_watcher.v | 2,106 | module MODULE1 #(VAR6=0)
(input VAR18);
longint VAR17 = 0;
longint VAR15 = 0;
longint VAR8 = -1;
longint VAR9 = -1;
longint VAR20 = -1;
longint VAR16 = -1;
longint VAR4;
always @(posedge VAR18)
begin
VAR4 =
if ((VAR4-VAR15 > VAR8+VAR6)
|| (VAR4-VAR15 < VAR8-VAR6))
begin
if (VAR20 != -1)
("## VAR5 { VAR12 VAR3 (VAR14 %-8d VAR21) %-7d VAR19 (VAR13/VAR11 VAR1 VAR10=%2.3f)} (%VAR2)\VAR13"
,VAR20, -VAR15, ( real ' (VAR9))/(real ' (-VAR15)));
VAR20 = 0;
VAR8 = -VAR15;
end
else
VAR20 = VAR20+1;
VAR17 =
end
always @(negedge VAR18)
begin
VAR4 =
if ((VAR4-VAR17 > VAR9+VAR6)
|| (VAR4-VAR17 < VAR9-VAR6))
begin
if (VAR16 != -1)
("## VAR5 { VAR7 VAR3 (VAR14 %-7d VAR21) %-7d VAR19 (VAR11/VAR13 VAR1 VAR10=%2.3f)} (%VAR2)\VAR13"
,VAR16, -VAR17, ( real ' (VAR8))/(real ' (-VAR17)));
VAR16 = 0;
VAR9 = -VAR17;
end
else
VAR16 = VAR16+1;
VAR15 =
end
endmodule | bsd-3-clause |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_xbar_2/synth/design_SWandHW_standalone_xbar_2.v | 26,501 | module MODULE1 (
VAR30,
VAR16,
VAR87,
VAR36,
VAR10,
VAR34,
VAR89,
VAR75,
VAR84,
VAR41,
VAR47,
VAR131,
VAR70,
VAR28,
VAR50,
VAR20,
VAR2,
VAR8,
VAR103,
VAR46,
VAR31,
VAR99,
VAR17,
VAR120,
VAR94,
VAR21,
VAR77,
VAR25,
VAR74,
VAR122,
VAR80,
VAR67,
VAR53,
VAR125,
VAR39,
VAR63,
VAR101,
VAR57,
VAR40,
VAR64,
VAR95,
VAR45,
VAR6,
VAR29,
VAR130,
VAR96,
VAR27,
VAR1,
VAR24,
VAR23,
VAR124,
VAR118,
VAR43,
VAR4,
VAR106,
VAR68,
VAR79,
VAR37,
VAR78,
VAR100,
VAR126,
VAR127,
VAR48,
VAR113,
VAR33,
VAR60,
VAR116,
VAR93,
VAR107,
VAR42,
VAR98,
VAR7,
VAR13,
VAR38,
VAR102,
VAR134,
VAR117,
VAR15
);
input wire VAR30;
input wire VAR16;
input wire [14 : 0] VAR87;
input wire [159 : 0] VAR36;
input wire [39 : 0] VAR10;
input wire [14 : 0] VAR34;
input wire [9 : 0] VAR89;
input wire [4 : 0] VAR75;
input wire [19 : 0] VAR84;
input wire [14 : 0] VAR41;
input wire [19 : 0] VAR47;
input wire [4 : 0] VAR131;
output wire [4 : 0] VAR70;
input wire [159 : 0] VAR28;
input wire [19 : 0] VAR50;
input wire [4 : 0] VAR20;
input wire [4 : 0] VAR2;
output wire [4 : 0] VAR8;
output wire [14 : 0] VAR103;
output wire [9 : 0] VAR46;
output wire [4 : 0] VAR31;
input wire [4 : 0] VAR99;
input wire [14 : 0] VAR17;
input wire [159 : 0] VAR120;
input wire [39 : 0] VAR94;
input wire [14 : 0] VAR21;
input wire [9 : 0] VAR77;
input wire [4 : 0] VAR25;
input wire [19 : 0] VAR74;
input wire [14 : 0] VAR122;
input wire [19 : 0] VAR80;
input wire [4 : 0] VAR67;
output wire [4 : 0] VAR53;
output wire [14 : 0] VAR125;
output wire [159 : 0] VAR39;
output wire [9 : 0] VAR63;
output wire [4 : 0] VAR101;
output wire [4 : 0] VAR57;
input wire [4 : 0] VAR40;
output wire [2 : 0] VAR64;
output wire [31 : 0] VAR95;
output wire [7 : 0] VAR45;
output wire [2 : 0] VAR6;
output wire [1 : 0] VAR29;
output wire [0 : 0] VAR130;
output wire [3 : 0] VAR96;
output wire [2 : 0] VAR27;
output wire [3 : 0] VAR1;
output wire [3 : 0] VAR24;
output wire [0 : 0] VAR23;
input wire [0 : 0] VAR124;
output wire [31 : 0] VAR118;
output wire [3 : 0] VAR43;
output wire [0 : 0] VAR4;
output wire [0 : 0] VAR106;
input wire [0 : 0] VAR68;
input wire [2 : 0] VAR79;
input wire [1 : 0] VAR37;
input wire [0 : 0] VAR78;
output wire [0 : 0] VAR100;
output wire [2 : 0] VAR126;
output wire [31 : 0] VAR127;
output wire [7 : 0] VAR48;
output wire [2 : 0] VAR113;
output wire [1 : 0] VAR33;
output wire [0 : 0] VAR60;
output wire [3 : 0] VAR116;
output wire [2 : 0] VAR93;
output wire [3 : 0] VAR107;
output wire [3 : 0] VAR42;
output wire [0 : 0] VAR98;
input wire [0 : 0] VAR7;
input wire [2 : 0] VAR13;
input wire [31 : 0] VAR38;
input wire [1 : 0] VAR102;
input wire [0 : 0] VAR134;
input wire [0 : 0] VAR117;
output wire [0 : 0] VAR15;
VAR112 #(
.VAR69("VAR76"),
.VAR11(5),
.VAR90(1),
.VAR108(3),
.VAR114(32),
.VAR110(32),
.VAR22(0),
.VAR85(1),
.VAR109(64'VAR19),
.VAR49(32'VAR71),
.VAR86(160'VAR18),
.VAR119(160'VAR92),
.VAR56(0),
.VAR52(1),
.VAR81(1),
.VAR72(1),
.VAR51(1),
.VAR59(1),
.VAR115(32'VAR111),
.VAR5(32'VAR3),
.VAR132(0),
.VAR9(160'VAR92),
.VAR104(160'VAR54),
.VAR12(160'VAR54),
.VAR105(32'VAR62),
.VAR83(32'VAR62),
.VAR91(160'VAR92),
.VAR88(32'VAR32),
.VAR44(1)
) VAR133 (
.VAR30(VAR30),
.VAR16(VAR16),
.VAR87(VAR87),
.VAR36(VAR36),
.VAR10(VAR10),
.VAR34(VAR34),
.VAR89(VAR89),
.VAR75(VAR75),
.VAR84(VAR84),
.VAR41(VAR41),
.VAR47(VAR47),
.VAR14(5'VAR129),
.VAR131(VAR131),
.VAR70(VAR70),
.VAR128(15'VAR61),
.VAR28(VAR28),
.VAR50(VAR50),
.VAR20(VAR20),
.VAR73(5'VAR129),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR103(VAR103),
.VAR46(VAR46),
.VAR97(),
.VAR31(VAR31),
.VAR99(VAR99),
.VAR17(VAR17),
.VAR120(VAR120),
.VAR94(VAR94),
.VAR21(VAR21),
.VAR77(VAR77),
.VAR25(VAR25),
.VAR74(VAR74),
.VAR122(VAR122),
.VAR80(VAR80),
.VAR123(5'VAR129),
.VAR67(VAR67),
.VAR53(VAR53),
.VAR125(VAR125),
.VAR39(VAR39),
.VAR63(VAR63),
.VAR101(VAR101),
.VAR35(),
.VAR57(VAR57),
.VAR40(VAR40),
.VAR64(VAR64),
.VAR95(VAR95),
.VAR45(VAR45),
.VAR6(VAR6),
.VAR29(VAR29),
.VAR130(VAR130),
.VAR96(VAR96),
.VAR27(VAR27),
.VAR1(VAR1),
.VAR24(VAR24),
.VAR82(),
.VAR23(VAR23),
.VAR124(VAR124),
.VAR26(),
.VAR118(VAR118),
.VAR43(VAR43),
.VAR4(VAR4),
.VAR58(),
.VAR106(VAR106),
.VAR68(VAR68),
.VAR79(VAR79),
.VAR37(VAR37),
.VAR121(1'VAR65),
.VAR78(VAR78),
.VAR100(VAR100),
.VAR126(VAR126),
.VAR127(VAR127),
.VAR48(VAR48),
.VAR113(VAR113),
.VAR33(VAR33),
.VAR60(VAR60),
.VAR116(VAR116),
.VAR93(VAR93),
.VAR107(VAR107),
.VAR42(VAR42),
.VAR66(),
.VAR98(VAR98),
.VAR7(VAR7),
.VAR13(VAR13),
.VAR38(VAR38),
.VAR102(VAR102),
.VAR134(VAR134),
.VAR55(1'VAR65),
.VAR117(VAR117),
.VAR15(VAR15)
);
endmodule | gpl-3.0 |
tmolteno/TART | hardware/FPGA/fifo/fifo16.v | 3,929 | module MODULE1 (
VAR19,
VAR21,
VAR18,
VAR1, VAR9, VAR17,
VAR20,
VAR5,
VAR15,
VAR4
);
parameter VAR11 = 8'd16;
input VAR19;
input VAR21;
input VAR18;
input VAR1;
input VAR9;
input [VAR11 - 1:0] VAR17;
output [VAR11 - 1:0] VAR20;
output VAR5;
output VAR15;
output VAR4;
reg [3:0] VAR7 = 4'h0;
reg [3:0] VAR2 = 4'h0;
assign VAR5 = (VAR7 - 1) == VAR2;
assign VAR15 = (VAR7 + 1) == VAR2;
assign VAR4 = VAR7 != VAR2;
always @(posedge VAR19)
begin
if (VAR18)
VAR7 <= 4'b0;
end
else
begin
if (VAR1)
VAR7 <= VAR7 + 1;
end
else
VAR7 <= VAR7;
end
end
always @(posedge VAR21)
begin
if (VAR18)
VAR2 <= 4'b0;
end
else
begin
if (VAR9)
VAR2 <= VAR2 + 1;
end
else
VAR2 <= VAR2;
end
end
reg [VAR11 - 1:0] VAR10[0:15];
always @ (posedge VAR21)
begin
if (VAR9)
begin
VAR10 [VAR2] <= VAR17;
end
end
assign VAR20 = VAR10 [VAR7];
VAR14 begin : VAR13
VAR12 (0);
end
task VAR12;
input VAR3;
integer VAR3, VAR8;
begin : VAR16
for (VAR8 = 0; VAR8 < 16; VAR8 = VAR8 + 1)
VAR10[VAR8] = VAR3;
end endtask VAR6
endmodule | lgpl-3.0 |
antmicro/yosys-symbiflow-plugins | ql-qlf-plugin/qlf_k6n10/ffs_map.v | 3,707 | module \VAR2 (VAR18, VAR9, VAR13);
input VAR18;
input VAR9;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR19 VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9));
endmodule
module \VAR31 (VAR18, VAR9, VAR29, VAR13);
input VAR18;
input VAR9;
input VAR29;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR7 VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9), .VAR29(VAR29));
endmodule
module \VAR32 (VAR18, VAR9, VAR29, VAR13);
input VAR18;
input VAR9;
input VAR29;
output VAR13;
VAR5 VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9), .VAR20(VAR29));
endmodule
module \VAR33 (VAR18, VAR9, VAR25, VAR29, VAR13);
input VAR18;
input VAR9;
input VAR25;
input VAR29;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR16 VAR28 (.VAR18(VAR18), .VAR13(VAR13), .VAR9(VAR9), .VAR25(VAR25), .VAR29(VAR29));
endmodule
module \VAR8 (VAR18, VAR9, VAR25, VAR29, VAR13);
input VAR18;
input VAR9;
input VAR25;
input VAR29;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR12 VAR28 (.VAR18(VAR18), .VAR13(VAR13), .VAR9(VAR9), .VAR25(VAR25), .VAR20(VAR20));
endmodule
module \VAR1 (VAR18, VAR9, VAR29, VAR20, VAR13);
input VAR18;
input VAR9;
input VAR29;
input VAR20;
output VAR13;
VAR11 VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9), .VAR29(VAR29), .VAR20(VAR20));
endmodule
module \VAR4 (VAR18, VAR13, VAR9, VAR25, VAR29, VAR20);
input VAR18;
input VAR9;
input VAR25;
input VAR29;
input VAR20;
output VAR13;
VAR26 VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9), .VAR25(VAR25), .VAR29(VAR29), .VAR20(VAR20));
endmodule
module \VAR22 (input VAR25, VAR20, VAR29, VAR18, output VAR13);
parameter VAR23 = 1'VAR10;
VAR14 VAR28 (.VAR18(VAR18), .VAR13(VAR13), .VAR25(1'b1), .VAR27(VAR25), .VAR29(VAR29), .VAR20(VAR20));
endmodule
module \VAR15 (VAR18, VAR9, VAR13);
input VAR18;
input VAR9;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR19 #(.VAR6(1'b1)) VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9));
endmodule
module \VAR17 (VAR18, VAR9, VAR29, VAR13);
input VAR18;
input VAR9;
input VAR29;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR7 #(.VAR6(1'b1)) VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9), .VAR29(VAR29));
endmodule
module \VAR21 (VAR18, VAR9, VAR29, VAR13);
input VAR18;
input VAR9;
input VAR29;
output VAR13;
VAR5 #(.VAR6(1'b1)) VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9), .VAR20(VAR29));
endmodule
module \VAR3 (VAR18, VAR9, VAR25, VAR29, VAR13);
input VAR18;
input VAR9;
input VAR25;
input VAR29;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR16 #(.VAR6(1'b1)) VAR28 (.VAR18(VAR18), .VAR13(VAR13), .VAR9(VAR9), .VAR25(VAR25), .VAR29(VAR29));
endmodule
module \VAR30 (VAR18, VAR9, VAR25, VAR29, VAR13);
input VAR18;
input VAR9;
input VAR25;
input VAR29;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR12 #(.VAR6(1'b1)) VAR28 (.VAR18(VAR18), .VAR13(VAR13), .VAR9(VAR9), .VAR25(VAR25), .VAR20(VAR20));
endmodule
module \VAR24 (VAR18, VAR9, VAR29, VAR20, VAR13);
input VAR18;
input VAR9;
input VAR29;
input VAR20;
output VAR13;
VAR11 #(.VAR6(1'b1)) VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9), .VAR29(VAR29), .VAR20(VAR20));
endmodule
module \VAR4 (VAR18, VAR9, VAR25, VAR29, VAR20, VAR13);
input VAR18;
input VAR9;
input VAR25;
input VAR29;
input VAR20;
output VAR13;
VAR26 #(.VAR6(1'b1)) VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9), .VAR25(VAR25), .VAR29(VAR29), .VAR20(VAR20));
endmodule | isc |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/in_switch.v | 13,104 | module MODULE1(
input clk,
input reset,
output [239:0] VAR44,
input [63:0] VAR73,
input [15:0] VAR78,
input VAR48,
input VAR20,
output reg VAR70,
input [63:0] VAR32,
input [15:0] VAR34,
input VAR88,
input VAR52,
output reg VAR26,
input [63:0] VAR25,
input [15:0] VAR38,
input VAR30,
input VAR66,
output reg VAR1,
input [63:0] VAR23,
input [15:0] VAR54,
input VAR76,
input VAR10,
output reg VAR58,
output [63:0] VAR37,
output [15:0] VAR17,
output VAR22,
output reg VAR29,
input VAR65,
input VAR49,
output [63:0] VAR95,
output [15:0] VAR69,
output VAR89,
output reg VAR3,
input VAR60,
input VAR42,
output [63:0] VAR33,
output [15:0] VAR6,
output VAR56,
output reg VAR31,
input VAR79,
input VAR18,
output [63:0] VAR15,
output [15:0] VAR90,
output VAR63,
output reg VAR46,
input VAR12,
input VAR4
);
reg [3:0] VAR40;
reg [3:0] VAR61;
reg [3:0] VAR50;
reg [3:0] VAR75;
reg [3:0] VAR45;
reg [63:0] VAR93[3:0];
assign VAR37 = VAR93[0];
assign VAR95 = VAR93[1];
assign VAR33 = VAR93[2];
assign VAR15 = VAR93[3];
reg [15:0] VAR8[3:0];
assign VAR17 = VAR8[0];
assign VAR69 = VAR8[1];
assign VAR6 = VAR8[2];
assign VAR90 = VAR8[3];
reg [3:0] VAR14;
assign VAR22 = VAR14[0];
assign VAR89 = VAR14[1];
assign VAR56 = VAR14[2];
assign VAR63 = VAR14[3];
reg [3:0] VAR9;
reg [1:0] VAR62;
reg [1:0] VAR43;
reg [1:0] VAR7;
reg [1:0] VAR64;
reg [1:0] VAR27;
reg [3:0] VAR55;
reg VAR83;
reg VAR16;
reg VAR51;
reg VAR41;
reg [3:0] VAR2;
reg VAR67;
reg VAR57;
reg VAR39;
reg VAR21;
reg [1:0] VAR19;
reg [1:0] VAR91;
reg [1:0] VAR82;
reg [1:0] VAR77;
reg [1:0] VAR94;
reg [1:0] VAR35;
wire [1:0] VAR47;
assign VAR47 = (VAR94 == 2'b11) ? 0 : VAR94 + 1;
parameter VAR5 = 2'b00,
VAR74 = 2'b01,
VAR85 = 2'b10,
VAR53 = 2'b11;
reg [1:0] VAR59;
reg [1:0] VAR13;
always @ begin
VAR83 = 0;
VAR16 = 0;
VAR51 = 0;
VAR41 = 0;
VAR50 = 0;
VAR81 = VAR68;
case(VAR68)
VAR71: begin
VAR61[0] = 0;
VAR9[0] = 0;
if(VAR40[0]) begin
VAR83 = 1;
VAR81 = VAR72;
end
end
VAR72: begin
VAR83 = 1;
if(VAR67) begin
VAR62 = VAR27;
VAR83 = 0;
VAR50[VAR27] = 1;
VAR81 = VAR28;
end
end
VAR28: begin
VAR50[VAR62] = 1;
if(VAR75[VAR62]) begin
VAR61[0] = 1;
VAR9[0] = 1;
VAR81 = VAR87;
end
end
VAR87: begin
VAR50[VAR62] = 1;
VAR61[0] = 1;
VAR9[0] = 1;
if(!VAR40[0]) begin
VAR81 = VAR24;
end
end
VAR24: begin
if(!VAR75[VAR62]) begin
VAR61[0] = 0;
VAR81 = VAR71;
end
end
default: begin
VAR61[0] = 0;
VAR9[0] = 0;
VAR83 = 0;
VAR81 = VAR71;
end
endcase
VAR36 = VAR80;
case(VAR80)
VAR71: begin
VAR61[1] = 0;
VAR9[1] = 0;
if(VAR40[1]) begin
VAR16 = 1;
VAR36 = VAR72;
end
end
VAR72: begin
VAR16 = 1;
if(VAR57) begin
VAR43 = VAR27;
VAR16 = 0;
VAR50[VAR27] = 1;
VAR36 = VAR28;
end
end
VAR28: begin
VAR50[VAR43] = 1;
if(VAR75[VAR43]) begin
VAR61[1] = 1;
VAR9[1] = 1;
VAR36 = VAR87;
end
end
VAR87: begin
VAR50[VAR43] = 1;
VAR61[1] = 1;
VAR9[1] = 1;
if(!VAR40[1]) begin
VAR36 = VAR24;
end
end
VAR24: begin
if(!VAR75[VAR43]) begin
VAR61[1] = 0;
VAR36 = VAR71;
end
end
default: begin
VAR61[1] = 0;
VAR9[1] = 0;
VAR16 = 0;
VAR36 = VAR71;
end
endcase
VAR92 = VAR86;
case(VAR86)
VAR71: begin
VAR61[2] = 0;
VAR9[2] = 0;
if(VAR40[2]) begin
VAR51 = 1;
VAR92 = VAR72;
end
end
VAR72: begin
VAR51 = 1;
if(VAR39) begin
VAR7 = VAR27;
VAR50[VAR27] = 1;
VAR51 = 0;
VAR92 = VAR28;
end
end
VAR28: begin
VAR50[VAR7] = 1;
if(VAR75[VAR7]) begin
VAR61[2] = 1;
VAR9[2] = 1;
VAR92 = VAR87;
end
end
VAR87: begin
VAR50[VAR7] = 1;
VAR61[2] = 1;
VAR9[2] = 1;
if(!VAR40[2]) begin
VAR92 = VAR24;
end
end
VAR24: begin
if(!VAR75[VAR7]) begin
VAR61[2] = 0;
VAR92 = VAR71;
end
end
default: begin
VAR61[2] = 0;
VAR51 = 0;
VAR9[2] = 0;
VAR92 = VAR71;
end
endcase
VAR84 = VAR11;
case(VAR11)
VAR71: begin
VAR61[3] = 0;
VAR9[3] = 0;
if(VAR40[3]) begin
VAR41 = 1;
VAR84 = VAR72;
end
end
VAR72: begin
VAR41 = 1;
if(VAR21) begin
VAR64 = VAR27;
VAR50[VAR27] = 1;
VAR41 = 0;
VAR84 = VAR28;
end
end
VAR28: begin
VAR50[VAR64] = 1;
if(VAR75[VAR64]) begin
VAR61[3] = 1;
VAR9[3] = 1;
VAR84 = VAR87;
end
end
VAR87: begin
VAR50[VAR64] = 1;
VAR61[3] = 1;
VAR9[3] = 1;
if(!VAR40[3]) begin
VAR84 = VAR24;
end
end
VAR24: begin
if(!VAR75[VAR64]) begin
VAR61[3] = 0;
VAR84 = VAR71;
end
end
default: begin
VAR61[3] = 0;
VAR41 = 0;
VAR9[3] = 0;
VAR84 = VAR71;
end
endcase
end
always @(posedge clk)
begin
if(reset) begin
VAR68 <= 0;
VAR80 <= 0;
VAR86 <= 0;
VAR11 <= 0;
VAR59 <= 0;
VAR94 <= 0;
end else begin
VAR68 <= VAR81;
VAR80 <= VAR36;
VAR86 <= VAR92;
VAR11 <= VAR84;
VAR59 <= VAR13;
VAR94 <= VAR35;
VAR67 <= VAR2[0];
VAR57 <= VAR2[1];
VAR39 <= VAR2[2];
VAR21 <= VAR2[3];
VAR55[0] <= VAR83;
VAR55[1] <= VAR16;
VAR55[2] <= VAR51;
VAR55[3] <= VAR41;
VAR40[0] <= VAR20;
VAR40[1] <= VAR52;
VAR40[2] <= VAR66;
VAR40[3] <= VAR10;
VAR70 <= VAR61[0];
VAR26 <= VAR61[1];
VAR1 <= VAR61[2];
VAR58 <= VAR61[3];
VAR29 <= VAR50[0];
VAR3 <= VAR50[1];
VAR31 <= VAR50[2];
VAR46 <= VAR50[3];
VAR75[0] <= VAR65;
VAR75[1] <= VAR60;
VAR75[2] <= VAR79;
VAR75[3] <= VAR12;
VAR45[0] <= VAR49;
VAR45[1] <= VAR42;
VAR45[2] <= VAR18;
VAR45[3] <= VAR4;
if(VAR9[0]) begin
VAR93[VAR62] <= VAR73;
VAR8[VAR62] <= VAR78;
VAR14[VAR62] <= VAR48;
end
if(VAR9[1]) begin
VAR93[VAR43] <= VAR32;
VAR8[VAR43] <= VAR34;
VAR14[VAR43] <= VAR88;
end
if(VAR9[2]) begin
VAR93[VAR7] <= VAR25;
VAR8[VAR7] <= VAR38;
VAR14[VAR7] <= VAR30;
end
if(VAR9[3]) begin
VAR93[VAR64] <= VAR23;
VAR8[VAR64] <= VAR54;
VAR14[VAR64] <= VAR76;
end
end
end
assign VAR44[63:0] = VAR32;
assign VAR44[71:64] = VAR34;
assign VAR44[80] = VAR88;
assign VAR44[81] = VAR52;
assign VAR44[82] = VAR26;
assign VAR44[90] = VAR22;
assign VAR44[91] = VAR29;
assign VAR44[92] = VAR65;
assign VAR44[93] = VAR49;
assign VAR44[100] = VAR89;
assign VAR44[101] = VAR3;
assign VAR44[102] = VAR60;
assign VAR44[103] = VAR42;
assign VAR44[110] = VAR56;
assign VAR44[111] = VAR31;
assign VAR44[112] = VAR79;
assign VAR44[113] = VAR18;
assign VAR44[120] = VAR63;
assign VAR44[121] = VAR46;
assign VAR44[122] = VAR12;
assign VAR44[123] = VAR4;
assign VAR44[131:130] = VAR59;
assign VAR44[133:132] = VAR27;
assign VAR44[135] = VAR55[0];
assign VAR44[136] = VAR55[1];
assign VAR44[137] = VAR55[2];
assign VAR44[138] = VAR55[3];
assign VAR44[145] = VAR2[0];
assign VAR44[146] = VAR2[1];
assign VAR44[147] = VAR2[2];
assign VAR44[148] = VAR2[3];
assign VAR44[151:150] = VAR94;
assign VAR44[163:160] = VAR9;
assign VAR44[171:170] = VAR62;
assign VAR44[173:172] = VAR43;
assign VAR44[175:174] = VAR7;
assign VAR44[177:176] = VAR64;
assign VAR44[182:180] = VAR68;
assign VAR44[185:183] = VAR80;
assign VAR44[188:186] = VAR86;
assign VAR44[191:189] = VAR11;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3_1.v | 2,161 | module MODULE2 (
VAR10 ,
VAR5 ,
VAR4 ,
VAR6 ,
VAR2,
VAR1,
VAR9 ,
VAR3
);
output VAR10 ;
input VAR5 ;
input VAR4 ;
input VAR6 ;
input VAR2;
input VAR1;
input VAR9 ;
input VAR3 ;
VAR8 VAR7 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR10,
VAR5,
VAR4,
VAR6
);
output VAR10;
input VAR5;
input VAR4;
input VAR6;
supply1 VAR2;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR3 ;
VAR8 VAR7 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hs__udp_dlatch_pr_pp_pg_n.symbol.v | 1,505 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR6 ,
input VAR3 ,
input VAR2,
input VAR7 ,
input VAR4
);
endmodule | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/pkt_input_ctrl/pkt_input_ctrl.v | 3,173 | module MODULE1(
clk,
reset,
VAR25,
VAR13,
VAR17,
VAR22,
VAR23,
VAR26,
VAR1,
VAR4
);
input clk;
input reset;
input VAR22;
input [138:0] VAR23;
output [7:0] VAR26;
input VAR1;
input VAR4;
input VAR25;
output VAR13;
output [138:0] VAR17;
reg [138:0] VAR17;
reg VAR13;
reg [2:0] state;
parameter VAR5=3'b000,
VAR21=3'b001,
VAR12=3'b010;
always@(posedge clk or negedge reset)
if(!reset)
begin
VAR13<=1'b0;
state<=VAR5;
end
else
begin
case(state)
VAR5:
begin
if(VAR25)
begin
if((!VAR11)&&(VAR15==1'b1))
begin
VAR24<=1'b1;
VAR10<=1'b1;
state<=VAR21;
end
else
begin
state<=VAR5;
end
end
else
begin
state<=VAR5;
end
end
VAR21:
begin
VAR24<=1'b0;
VAR10<=1'b0;
if(VAR9[138:136]==3'b110) begin
VAR10<=1'b0;
VAR13<=1'b1;
VAR17<=VAR9;
state<=VAR12;
end
else
begin
VAR10<=1'b1;
VAR13<=1'b1;
VAR17<=VAR9;
state<=VAR21;
end
end
VAR12:
begin
VAR10<=1'b0;
VAR13<=1'b0;
state<=VAR5;
end
default:
begin
VAR13<=1'b0;
state<=VAR5;
end
endcase
end
reg VAR10;
wire [138:0]VAR9;
wire [7:0]VAR26;
reg VAR24;
wire VAR15;
wire VAR11;
VAR7 VAR6(
.VAR19(!reset),
.VAR28(clk),
.VAR3(VAR23),
.VAR2(VAR10),
.VAR20(VAR22),
.VAR27(VAR9),
.VAR16(VAR26)
);
VAR8 VAR18(
.VAR19(!reset),
.VAR28(clk),
.VAR3(VAR4),
.VAR2(VAR24),
.VAR20(VAR1),
.VAR14(VAR11),
.VAR27(VAR15)
);
endmodule | apache-2.0 |
MegaShow/college-programming | Homework/Digital Circuits and Logical Design/StudentId/Print.v | 2,731 | module MODULE1(VAR9, VAR3, VAR6, VAR10, VAR12);
input VAR9, VAR3, VAR6;
output reg [3:0] VAR10; output reg [7:0] VAR12; reg [31:0] counter; reg [31:0] VAR2; parameter [31:0] VAR11 = 50000; parameter [31:0] VAR4 = 100000000; parameter [31:0] VAR7 = 32'VAR1; reg [15:0] VAR5; reg [4:0] VAR8; | mit |
mwswartwout/EECS318 | hw1/problem1/problem1.v | 1,239 | module MODULE1(out, VAR34, VAR9);
output [7:0] out;
input [3:0] VAR34, VAR9;
wire VAR29, VAR22, VAR11, VAR17, VAR57, VAR33, VAR49, VAR47, VAR24, VAR55, VAR38, VAR45, VAR2, VAR39, VAR18, VAR27, VAR64, VAR60, VAR37, VAR20;
wire VAR21, VAR28, VAR5, VAR1, VAR12, VAR41, VAR52, VAR3, VAR26, VAR42, VAR15, VAR53, VAR36, VAR59, VAR46, VAR48, VAR30, VAR63, VAR54, VAR10;
VAR23 VAR8(VAR21, VAR29, 1'b0, VAR9[0], VAR34[0], 1'b0);
VAR23 VAR40(VAR28, VAR22, 1'b0, VAR9[1], VAR34[0], 1'b0);
VAR23 VAR58(VAR5, VAR11, 1'b0, VAR9[2], VAR34[0], 1'b0);
VAR23 VAR51(VAR1, VAR17, 1'b0, VAR9[3], VAR34[0], 1'b0);
VAR23 VAR16(VAR12, VAR57, VAR28, VAR9[0], VAR34[1], VAR29);
VAR23 VAR7(VAR41, VAR33, VAR5, VAR9[1], VAR34[1], VAR22);
VAR23 VAR6(VAR52, VAR49, VAR1, VAR9[2], VAR34[1], VAR11);
VAR23 VAR44(VAR3, VAR47, 1'b0, VAR9[3], VAR34[1], VAR17);
VAR23 VAR13(VAR26, VAR24, VAR41, VAR9[0], VAR34[2], VAR57);
VAR23 VAR25(VAR42, VAR55, VAR52, VAR9[1], VAR34[2], VAR33);
VAR23 VAR50(VAR15, VAR38, VAR3, VAR9[2], VAR34[2], VAR49);
VAR23 VAR14(VAR53, VAR45, 1'b0, VAR9[3], VAR34[2], VAR47);
VAR23 VAR35(VAR36, VAR2, VAR42, VAR9[0], VAR34[3], VAR24);
VAR23 VAR31(VAR59, VAR39, VAR15, VAR9[1], VAR34[3], VAR55);
VAR23 VAR61(VAR46, VAR18, VAR53, VAR9[2], VAR34[3], VAR38);
VAR23 VAR62(VAR48, VAR27, 1'b0, VAR9[3], VAR34[3], VAR45);
VAR4 VAR43(VAR30, VAR64, VAR59, VAR2, 1'b0);
VAR4 VAR32(VAR63, VAR60, VAR46, VAR39, VAR64);
VAR4 VAR56(VAR54, VAR37, VAR48, VAR18, VAR60);
VAR4 VAR19(VAR10, VAR20, 1'b0, VAR27, VAR37);
assign out[0] = VAR21;
assign out[1] = VAR12;
assign out[2] = VAR26;
assign out[3] = VAR36;
assign out[4] = VAR30;
assign out[5] = VAR63;
assign out[6] = VAR54;
assign out[7] = VAR10;
endmodule | mit |
cybero/Verilog | src/PicoBlaze (kcpsm6)/Utilities/KCPSM6_Release9_30Sept14/UART_and_PicoTerm/KC705_design/uart6_kc705.v | 15,219 | module MODULE1 ( input VAR3,
output VAR50,
input VAR37,
input VAR16);
wire VAR36;
wire clk;
wire [7:0] VAR46;
wire [11:0] address;
wire [17:0] VAR49;
wire VAR61;
reg [7:0] VAR66;
wire [7:0] VAR18;
wire [7:0] VAR23;
wire VAR27;
wire VAR59;
wire VAR45;
wire interrupt;
wire VAR34;
wire VAR41;
wire VAR57;
wire VAR32;
wire [7:0] VAR39;
wire VAR55;
reg VAR7;
wire VAR58;
wire VAR35;
wire VAR6;
reg VAR19;
wire [7:0] VAR43;
reg VAR28;
wire VAR64;
wire VAR47;
wire VAR5;
reg VAR14;
reg [7:0] VAR22;
reg [7:0] VAR60;
reg VAR63;
assign VAR46 = 8'd200;
VAR2 VAR15(
.VAR44(VAR37),
.VAR24(VAR16),
.VAR25(VAR36));
VAR8 VAR65 (
.VAR44(VAR36),
.VAR25(clk));
VAR13 #(
.VAR54 (12'h7FF),
.VAR17(64),
.VAR4 (8'h41)) VAR21 (
.address (address),
.VAR49 (VAR49),
.VAR61 (VAR61),
.VAR23 (VAR23),
.VAR27 (VAR27),
.VAR59 (VAR59),
.VAR18 (VAR18),
.VAR45 (VAR45),
.VAR66 (VAR66),
.interrupt (interrupt),
.VAR34 (VAR34),
.reset (VAR57),
.VAR12 (VAR41),
.clk (clk));
assign VAR57 = VAR32;
assign VAR41 = VAR27 && VAR59; assign interrupt = VAR34;
VAR30 #(
.VAR1 ("7S"),
.VAR40 (2),
.VAR9 (1))
VAR38 (
.VAR32 (VAR32),
.enable (VAR61),
.address (address),
.VAR49 (VAR49),
.clk (clk));
VAR56 VAR11(
.VAR26(VAR39),
.VAR63(VAR63),
.VAR42(VAR50),
.VAR20(VAR55),
.VAR53(VAR58),
.VAR51(VAR35 ),
.VAR33(VAR6),
.VAR48(VAR19),
.clk(clk));
VAR67 VAR62(
.VAR52(VAR3),
.VAR63(VAR63 ),
.VAR10(VAR43 ),
.VAR29(VAR28 ),
.VAR53(VAR64 ),
.VAR51(VAR47 ),
.VAR33(VAR5 ),
.VAR48(VAR14 ),
.clk(clk ));
always @ (posedge clk )
begin
if (VAR60 == VAR22) begin
VAR60 <= 5'b00000;
VAR63 <= 1'b1; end
else begin
VAR60 <= VAR60 + 5'b00001;
VAR63 <= 1'b0;
end
end
always @ (posedge clk)
begin
case (VAR23[1:0])
2'b00 : VAR66 <= { 2'b00,
VAR5,
VAR47,
VAR64,
VAR6,
VAR35,
VAR58 };
2'b01 : VAR66 <= VAR43;
2'b10 : VAR66 <= VAR46;
default : VAR66 <= 8'VAR31 ;
endcase;
if ((VAR45 == 1'b1) && (VAR23[1:0] == 2'b01)) begin
VAR28 <= 1'b1;
end
else begin
VAR28 <= 1'b0;
end
end
always @ (posedge clk)
begin
if (VAR27 == 1'b1) begin
if (VAR23[1] == 1'b1) begin
VAR22 <= VAR18;
end
end
VAR7 <= VAR23[0];
end
assign VAR39 = VAR18;
assign VAR55 = VAR27 & VAR7;
always @ (posedge clk)
begin
if (VAR59 == 1'b1) begin
if (VAR23[0] == 1'b1) begin
VAR19 <= VAR18[0];
VAR14 <= VAR18[1];
end
end
end
endmodule | mit |
Chapna/TTCache | src/cachek_t.v | 1,196 | module MODULE1;
reg [0:15] VAR5;
reg [0:4] VAR4;
reg enable;
reg write;
reg [0:1] word;
reg VAR7;
reg [0:3] VAR1;
reg VAR8;
reg rst;
wire [0:15] VAR6;
wire [0:4] VAR9;
wire VAR2;
wire VAR3;
wire valid;
wire ack; | gpl-2.0 |
google/bbcpu | pcounter.v | 1,123 | module MODULE1(
input rst,
input clk,
input enable,
input VAR2,
input VAR1,
input [VAR3-1 : 0] VAR5,
output [VAR3-1 : 0] VAR4);
parameter VAR3 = 4;
reg [VAR3-1 : 0] counter;
assign VAR4 = (VAR1) ? counter : 0;
always @(posedge clk) begin
if (rst) begin
counter <= 0;
end else begin
if (enable) begin
counter <= counter + 1;
end else if (VAR2) begin
counter <= VAR5;
end
end
end
endmodule | apache-2.0 |
sigilance/tera-computer | src/control.v | 3,938 | module MODULE1 (VAR6, VAR15, VAR7, VAR16, VAR10, VAR13, VAR17, VAR8, VAR9, VAR2);
output VAR6, VAR15, VAR7, VAR16, VAR10, VAR13;
output [3:0] VAR17;
input VAR9, VAR2;
input [7:0] VAR8;
reg VAR14, VAR12, VAR3, VAR11, VAR5, VAR1;
reg [3:0] VAR4;
assign VAR6 = VAR14;
assign VAR15 = VAR12;
assign VAR7 = VAR3;
assign VAR16 = VAR11;
assign VAR10 = VAR5;
assign VAR13 = VAR1;
assign VAR17[3:0] = VAR4[3:0]; | mit |
manili/Pipelined_6502 | DUT.v | 2,462 | module MODULE1;
wire VAR37;
wire [23:0] VAR14;
wire [15:0] VAR3;
wire [7:0] VAR1;
wire [7:0] VAR33;
wire VAR24;
wire [1:0] VAR17;
wire [1:0] VAR32;
wire [23:0] VAR13;
wire [15:0] VAR31;
wire [15:0] VAR26;
wire [15:0] VAR28;
wire [15:0] VAR23;
wire [15:0] VAR34;
wire [7:0] VAR4;
wire [7:0] VAR11;
wire [7:0] VAR30;
wire [VAR21 - 1:0] VAR10;
wire [VAR22 - 1:0] VAR29;
wire [VAR15 - 1:0] VAR6;
wire [VAR36 - 1:0] VAR9;
wire [VAR20 - 1:0] VAR16;
wire [VAR2 - 1:0] VAR35;
wire [VAR25 - 1:0] VAR8;
reg clk;
reg rst;
VAR7 VAR27
(
.VAR19 (clk),
.VAR18 (rst),
.VAR38 (1'h0),
.VAR12 (1'h0),
.VAR5 (1'h1),
.VAR37 (VAR37),
.VAR14 (VAR14),
.VAR3 (VAR3),
.VAR1 (VAR1),
.VAR33 (VAR33),
.VAR24 (VAR24),
.VAR17 (VAR17),
.VAR32 (VAR32),
.VAR13 (VAR13),
.VAR31 (VAR31),
.VAR26 (VAR26),
.VAR28 (VAR28),
.VAR23 (VAR23),
.VAR34 (VAR34)
,.VAR4 (VAR4),
.VAR11 (VAR11),
.VAR30 (VAR30),
.VAR10 (VAR10),
.VAR29 (VAR29),
.VAR6 (VAR6),
.VAR9 (VAR9),
.VAR16 (VAR16),
.VAR35 (VAR35),
.VAR8 (VAR8)
);
begin
begin
begin
begin | gpl-3.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v | 3,812 | module MODULE1
(
output VAR3,
input VAR2
);
VAR1 VAR4
(
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_clk_wiz_0_0/OpenSSD2_clk_wiz_0_0.v | 3,976 | module MODULE1
(
input VAR1,
output VAR3,
input reset
);
VAR4 VAR2
(
.VAR1(VAR1),
.VAR3(VAR3),
.reset(reset)
);
endmodule | gpl-3.0 |
kevintownsend/inara-hdl-libraries | multistage_interconnect_network/omega_network_ff.v | 1,334 | module MODULE1(clk, VAR3, din, valid, dout, VAR15);
parameter VAR2 = 8;
parameter VAR12 = 8;
parameter VAR14 = VAR12;
parameter VAR11 = VAR6(VAR14-1);
input clk;
input [0:VAR12-1] VAR3;
input [VAR12*VAR2-1:0] din;
output [0:VAR14-1] valid;
output [VAR14*VAR2-1:0] dout;
input [VAR11-1:0] VAR15;
genvar VAR1, VAR10;
wire [VAR2:0] VAR7 [0:VAR11][0:VAR12-1];
generate
for(VAR1 = 0; VAR1 < VAR12; VAR1 = VAR1 + 1) begin: VAR13
assign VAR7[0][VAR1][0] = VAR3[VAR1];
assign VAR7[0][VAR1][VAR2:1] = din[(VAR1+1)*VAR2-1 -:VAR2];
end
for(VAR1 = 0; VAR1 < VAR11; VAR1 = VAR1 + 1) begin: VAR16
for(VAR10 = 0; VAR10 < VAR12/2; VAR10 = VAR10 + 1) begin: VAR8
VAR4 #(VAR2+1) VAR5(clk, VAR7[VAR1][VAR10], VAR7[VAR1][VAR10+VAR12/2], VAR7[VAR1+1][VAR10*2], VAR7[VAR1+1][VAR10*2+1], VAR15[VAR11-1-VAR1]);
end
end
for(VAR1 = 0; VAR1 < VAR12; VAR1 = VAR1 + 1) begin: VAR9
assign valid[VAR1] = VAR7[VAR11][VAR1][0];
assign dout[(VAR1+1)*VAR2-1 -:VAR2] = VAR7[VAR11][VAR1][VAR2:1];
end
endgenerate
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xor2/sky130_fd_sc_hvl__xor2.blackbox.v | 1,268 | module MODULE1 (
VAR6,
VAR3,
VAR7
);
output VAR6;
input VAR3;
input VAR7;
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
LSaldyt/qnp | output/vs/opt_difficult_multi.v | 48,178 | module MODULE1(VAR26, VAR20, VAR8, VAR17, VAR23, VAR13, VAR18, VAR12, VAR15, VAR19, VAR1, VAR11, VAR7, VAR5, VAR21, VAR24, VAR4, VAR3, VAR16, VAR14, VAR10, VAR9, VAR25, VAR22, VAR6, VAR2, valid);
wire 0000;
wire 0001;
wire 0002;
wire 0003;
wire 0004;
wire 0005;
wire 0006;
wire 0007;
wire 0008;
wire 0009;
wire 0010;
wire 0011;
wire 0012;
wire 0013;
wire 0014;
wire 0015;
wire 0016;
wire 0017;
wire 0018;
wire 0019;
wire 0020;
wire 0021;
wire 0022;
wire 0023;
wire 0024;
wire 0025;
wire 0026;
wire 0027;
wire 0028;
wire 0029;
wire 0030;
wire 0031;
wire 0032;
wire 0033;
wire 0034;
wire 0035;
wire 0036;
wire 0037;
wire 0038;
wire 0039;
wire 0040;
wire 0041;
wire 0042;
wire 0043;
wire 0044;
wire 0045;
wire 0046;
wire 0047;
wire 0048;
wire 0049;
wire 0050;
wire 0051;
wire 0052;
wire 0053;
wire 0054;
wire 0055;
wire 0056;
wire 0057;
wire 0058;
wire 0059;
wire 0060;
wire 0061;
wire 0062;
wire 0063;
wire 0064;
wire 0065;
wire 0066;
wire 0067;
wire 0068;
wire 0069;
wire 0070;
wire 0071;
wire 0072;
wire 0073;
wire 0074;
wire 0075;
wire 0076;
wire 0077;
wire 0078;
wire 0079;
wire 0080;
wire 0081;
wire 0082;
wire 0083;
wire 0084;
wire 0085;
wire 0086;
wire 0087;
wire 0088;
wire 0089;
wire 0090;
wire 0091;
wire 0092;
wire 0093;
wire 0094;
wire 0095;
wire 0096;
wire 0097;
wire 0098;
wire 0099;
wire 0100;
wire 0101;
wire 0102;
wire 0103;
wire 0104;
wire 0105;
wire 0106;
wire 0107;
wire 0108;
wire 0109;
wire 0110;
wire 0111;
wire 0112;
wire 0113;
wire 0114;
wire 0115;
wire 0116;
wire 0117;
wire 0118;
wire 0119;
wire 0120;
wire 0121;
wire 0122;
wire 0123;
wire 0124;
wire 0125;
wire 0126;
wire 0127;
wire 0128;
wire 0129;
wire 0130;
wire 0131;
wire 0132;
wire 0133;
wire 0134;
wire 0135;
wire 0136;
wire 0137;
wire 0138;
wire 0139;
wire 0140;
wire 0141;
wire 0142;
wire 0143;
wire 0144;
wire 0145;
wire 0146;
wire 0147;
wire 0148;
wire 0149;
wire 0150;
wire 0151;
wire 0152;
wire 0153;
wire 0154;
wire 0155;
wire 0156;
wire 0157;
wire 0158;
wire 0159;
wire 0160;
wire 0161;
wire 0162;
wire 0163;
wire 0164;
wire 0165;
wire 0166;
wire 0167;
wire 0168;
wire 0169;
wire 0170;
wire 0171;
wire 0172;
wire 0173;
wire 0174;
wire 0175;
wire 0176;
wire 0177;
wire 0178;
wire 0179;
wire 0180;
wire 0181;
wire 0182;
wire 0183;
wire 0184;
wire 0185;
wire 0186;
wire 0187;
wire 0188;
wire 0189;
wire 0190;
wire 0191;
wire 0192;
wire 0193;
wire 0194;
wire 0195;
wire 0196;
wire 0197;
wire 0198;
wire 0199;
wire 0200;
wire 0201;
wire 0202;
wire 0203;
wire 0204;
wire 0205;
wire 0206;
wire 0207;
wire 0208;
wire 0209;
wire 0210;
wire 0211;
wire 0212;
wire 0213;
wire 0214;
wire 0215;
wire 0216;
wire 0217;
wire 0218;
wire 0219;
wire 0220;
wire 0221;
wire 0222;
wire 0223;
wire 0224;
wire 0225;
wire 0226;
wire 0227;
wire 0228;
wire 0229;
wire 0230;
wire 0231;
wire 0232;
wire 0233;
wire 0234;
wire 0235;
wire 0236;
wire 0237;
wire 0238;
wire 0239;
wire 0240;
wire 0241;
wire 0242;
wire 0243;
wire 0244;
wire 0245;
wire 0246;
wire 0247;
wire 0248;
wire 0249;
wire 0250;
wire 0251;
wire 0252;
wire 0253;
wire 0254;
wire 0255;
wire 0256;
wire 0257;
wire 0258;
wire 0259;
wire 0260;
wire 0261;
wire 0262;
wire 0263;
wire 0264;
wire 0265;
wire 0266;
wire 0267;
wire 0268;
wire 0269;
wire 0270;
wire 0271;
wire 0272;
wire 0273;
wire 0274;
wire 0275;
wire 0276;
wire 0277;
wire 0278;
wire 0279;
wire 0280;
wire 0281;
wire 0282;
wire 0283;
wire 0284;
wire 0285;
wire 0286;
wire 0287;
wire 0288;
wire 0289;
wire 0290;
wire 0291;
wire 0292;
wire 0293;
wire 0294;
wire 0295;
wire 0296;
wire 0297;
wire 0298;
wire 0299;
wire 0300;
wire 0301;
wire 0302;
wire 0303;
wire 0304;
wire 0305;
wire 0306;
wire 0307;
wire 0308;
wire 0309;
wire 0310;
wire 0311;
wire 0312;
wire 0313;
wire 0314;
wire 0315;
wire 0316;
wire 0317;
wire 0318;
wire 0319;
wire 0320;
wire 0321;
wire 0322;
wire 0323;
wire 0324;
wire 0325;
wire 0326;
wire 0327;
wire 0328;
wire 0329;
wire 0330;
wire 0331;
wire 0332;
wire 0333;
wire 0334;
wire 0335;
wire 0336;
wire 0337;
wire 0338;
wire 0339;
wire 0340;
wire 0341;
wire 0342;
wire 0343;
wire 0344;
wire 0345;
wire 0346;
wire 0347;
wire 0348;
wire 0349;
wire 0350;
wire 0351;
wire 0352;
wire 0353;
wire 0354;
wire 0355;
wire 0356;
wire 0357;
wire 0358;
wire 0359;
wire 0360;
wire 0361;
wire 0362;
wire 0363;
wire 0364;
wire 0365;
wire 0366;
wire 0367;
wire 0368;
wire 0369;
wire 0370;
wire 0371;
wire 0372;
wire 0373;
wire 0374;
wire 0375;
wire 0376;
wire 0377;
wire 0378;
wire 0379;
wire 0380;
wire 0381;
wire 0382;
wire 0383;
wire 0384;
wire 0385;
wire 0386;
wire 0387;
wire 0388;
wire 0389;
wire 0390;
wire 0391;
wire 0392;
wire 0393;
wire 0394;
wire 0395;
wire 0396;
wire 0397;
wire 0398;
wire 0399;
wire 0400;
wire 0401;
wire 0402;
wire 0403;
wire 0404;
wire 0405;
wire 0406;
wire 0407;
wire 0408;
wire 0409;
wire 0410;
wire 0411;
wire 0412;
wire 0413;
wire 0414;
wire 0415;
wire 0416;
wire 0417;
wire 0418;
wire 0419;
wire 0420;
wire 0421;
wire 0422;
wire 0423;
wire 0424;
wire 0425;
wire 0426;
wire 0427;
wire 0428;
wire 0429;
wire 0430;
wire 0431;
wire 0432;
wire 0433;
wire 0434;
wire 0435;
wire 0436;
wire 0437;
wire 0438;
wire 0439;
wire 0440;
wire 0441;
wire 0442;
wire 0443;
wire 0444;
wire 0445;
wire 0446;
wire 0447;
wire 0448;
wire 0449;
wire 0450;
wire 0451;
wire 0452;
wire 0453;
wire 0454;
wire 0455;
wire 0456;
wire 0457;
wire 0458;
wire 0459;
wire 0460;
wire 0461;
wire 0462;
wire 0463;
wire 0464;
wire 0465;
wire 0466;
wire 0467;
wire 0468;
wire 0469;
wire 0470;
wire 0471;
wire 0472;
wire 0473;
wire 0474;
wire 0475;
wire 0476;
wire 0477;
wire 0478;
wire 0479;
wire 0480;
wire 0481;
wire 0482;
wire 0483;
wire 0484;
wire 0485;
wire 0486;
wire 0487;
wire 0488;
wire 0489;
wire 0490;
wire 0491;
wire 0492;
wire 0493;
wire 0494;
wire 0495;
wire 0496;
wire 0497;
wire 0498;
wire 0499;
wire 0500;
wire 0501;
wire 0502;
wire 0503;
wire 0504;
wire 0505;
wire 0506;
wire 0507;
wire 0508;
wire 0509;
wire 0510;
wire 0511;
wire 0512;
wire 0513;
wire 0514;
wire 0515;
wire 0516;
wire 0517;
wire 0518;
wire 0519;
wire 0520;
wire 0521;
wire 0522;
wire 0523;
wire 0524;
wire 0525;
wire 0526;
wire 0527;
wire 0528;
wire 0529;
wire 0530;
wire 0531;
wire 0532;
wire 0533;
wire 0534;
wire 0535;
wire 0536;
wire 0537;
wire 0538;
wire 0539;
wire 0540;
wire 0541;
wire 0542;
wire 0543;
wire 0544;
wire 0545;
wire 0546;
wire 0547;
wire 0548;
wire 0549;
wire 0550;
wire 0551;
wire 0552;
wire 0553;
wire 0554;
wire 0555;
wire 0556;
wire 0557;
wire 0558;
wire 0559;
wire 0560;
wire 0561;
wire 0562;
wire 0563;
wire 0564;
wire 0565;
wire 0566;
wire 0567;
wire 0568;
wire 0569;
wire 0570;
wire 0571;
wire 0572;
wire 0573;
wire 0574;
wire 0575;
wire 0576;
wire 0577;
wire 0578;
wire 0579;
wire 0580;
wire 0581;
wire 0582;
wire 0583;
wire 0584;
wire 0585;
wire 0586;
wire 0587;
wire 0588;
wire 0589;
wire 0590;
wire 0591;
wire 0592;
wire 0593;
wire 0594;
wire 0595;
wire 0596;
wire 0597;
wire 0598;
wire 0599;
wire 0600;
wire 0601;
wire 0602;
wire 0603;
wire 0604;
wire 0605;
wire 0606;
wire 0607;
wire 0608;
wire 0609;
wire 0610;
wire 0611;
wire 0612;
wire 0613;
wire 0614;
wire 0615;
wire 0616;
wire 0617;
wire 0618;
wire 0619;
wire 0620;
wire 0621;
wire 0622;
wire 0623;
wire 0624;
wire 0625;
wire 0626;
wire 0627;
wire 0628;
wire 0629;
wire 0630;
wire 0631;
wire 0632;
wire 0633;
wire 0634;
wire 0635;
wire 0636;
wire 0637;
wire 0638;
wire 0639;
wire 0640;
wire 0641;
wire 0642;
wire 0643;
wire 0644;
wire 0645;
wire 0646;
wire 0647;
wire 0648;
wire 0649;
wire 0650;
wire 0651;
wire 0652;
wire 0653;
wire 0654;
wire 0655;
wire 0656;
wire 0657;
wire 0658;
wire 0659;
wire 0660;
wire 0661;
wire 0662;
wire 0663;
wire 0664;
wire 0665;
wire 0666;
wire 0667;
wire 0668;
wire 0669;
wire 0670;
wire 0671;
wire 0672;
wire 0673;
wire 0674;
wire 0675;
wire 0676;
wire 0677;
wire 0678;
wire 0679;
wire 0680;
wire 0681;
wire 0682;
wire 0683;
wire 0684;
wire 0685;
wire 0686;
wire 0687;
wire 0688;
wire 0689;
wire 0690;
wire 0691;
wire 0692;
wire 0693;
wire 0694;
wire 0695;
wire 0696;
wire 0697;
wire 0698;
wire 0699;
wire 0700;
wire 0701;
wire 0702;
wire 0703;
wire 0704;
wire 0705;
wire 0706;
wire 0707;
wire 0708;
wire 0709;
wire 0710;
wire 0711;
wire 0712;
wire 0713;
wire 0714;
wire 0715;
wire 0716;
wire 0717;
wire 0718;
wire 0719;
wire 0720;
wire 0721;
wire 0722;
wire 0723;
wire 0724;
wire 0725;
wire 0726;
wire 0727;
wire 0728;
wire 0729;
wire 0730;
wire 0731;
wire 0732;
wire 0733;
wire 0734;
wire 0735;
wire 0736;
wire 0737;
wire 0738;
wire 0739;
wire 0740;
wire 0741;
wire 0742;
wire 0743;
wire 0744;
wire 0745;
wire 0746;
wire 0747;
wire 0748;
wire 0749;
wire 0750;
wire 0751;
wire 0752;
wire 0753;
wire 0754;
wire 0755;
wire 0756;
wire 0757;
wire 0758;
wire 0759;
wire 0760;
wire 0761;
wire 0762;
wire 0763;
wire 0764;
wire 0765;
wire 0766;
wire 0767;
wire 0768;
wire 0769;
wire 0770;
wire 0771;
wire 0772;
wire 0773;
wire 0774;
wire 0775;
wire 0776;
wire 0777;
wire 0778;
wire 0779;
wire 0780;
wire 0781;
wire 0782;
wire 0783;
wire 0784;
wire 0785;
wire 0786;
wire 0787;
wire 0788;
wire 0789;
wire 0790;
wire 0791;
wire 0792;
wire 0793;
wire 0794;
wire 0795;
wire 0796;
wire 0797;
wire 0798;
wire 0799;
wire 0800;
wire 0801;
wire 0802;
wire 0803;
wire 0804;
wire 0805;
wire 0806;
wire 0807;
wire 0808;
wire 0809;
wire 0810;
wire 0811;
wire 0812;
wire 0813;
wire 0814;
wire 0815;
wire 0816;
wire 0817;
wire 0818;
wire 0819;
wire 0820;
wire 0821;
wire 0822;
wire 0823;
wire 0824;
wire 0825;
wire 0826;
wire 0827;
wire 0828;
wire 0829;
wire 0830;
wire 0831;
wire 0832;
wire 0833;
wire 0834;
wire 0835;
wire 0836;
wire 0837;
wire 0838;
wire 0839;
wire 0840;
wire 0841;
wire 0842;
wire 0843;
wire 0844;
wire 0845;
wire 0846;
wire 0847;
wire 0848;
wire 0849;
wire 0850;
wire 0851;
wire 0852;
wire 0853;
wire 0854;
wire 0855;
wire 0856;
wire 0857;
wire 0858;
wire 0859;
wire 0860;
wire 0861;
wire 0862;
wire 0863;
wire 0864;
wire 0865;
wire 0866;
wire 0867;
wire 0868;
wire 0869;
wire 0870;
wire 0871;
wire 0872;
wire 0873;
wire 0874;
wire 0875;
wire 0876;
wire 0877;
wire 0878;
wire 0879;
wire 0880;
wire 0881;
wire 0882;
wire 0883;
wire 0884;
wire 0885;
wire 0886;
wire 0887;
wire 0888;
wire 0889;
wire 0890;
wire 0891;
wire 0892;
wire 0893;
wire 0894;
wire 0895;
wire 0896;
wire 0897;
wire 0898;
wire 0899;
wire 0900;
wire 0901;
wire 0902;
wire 0903;
wire 0904;
wire 0905;
wire 0906;
wire 0907;
wire 0908;
wire 0909;
wire 0910;
wire 0911;
input VAR26;
input VAR20;
input VAR8;
input VAR17;
input VAR23;
input VAR13;
input VAR18;
input VAR12;
input VAR15;
input VAR19;
input VAR1;
input VAR11;
input VAR7;
input VAR5;
input VAR21;
input VAR24;
input VAR4;
input VAR3;
input VAR16;
input VAR14;
input VAR10;
input VAR9;
input VAR25;
input VAR22;
input VAR6;
input VAR2;
output valid;
assign 0180 = ~VAR14;
assign 0191 = ~VAR21;
assign 0202 = ~VAR1;
assign 0213 = ~(VAR20 ^ VAR26);
assign 0224 = 0213 ^ VAR19;
assign 0235 = 0224 ^ 0202;
assign 0246 = 0235 ^ VAR7;
assign 0257 = 0246 ^ 0191;
assign 0268 = ~(0257 | 0180);
assign 0279 = ~VAR24;
assign 0290 = 0246 | 0191;
assign 0301 = 0235 & VAR7;
assign 0312 = 0224 | 0202;
assign 0323 = VAR20 & VAR26;
assign 0344 = ~(VAR20 | VAR26);
assign 0345 = VAR19 ? 0323 : 0344;
assign 0356 = 0345 ^ 0312;
assign 0367 = 0356 ^ VAR11;
assign 0378 = 0367 ^ 0301;
assign 0389 = 0378 ^ 0290;
assign 0400 = 0389 ^ 0279;
assign 0411 = 0400 ^ VAR4;
assign 0422 = 0411 ^ 0268;
assign 0433 = 0422 ^ VAR10;
assign 0444 = 0433 & VAR25;
assign 0455 = ~VAR4;
assign 0466 = 0400 | 0455;
assign 0477 = ~(0389 | 0279);
assign 0488 = ~((0378 | 0246) & VAR21);
assign 0499 = ~VAR5;
assign 0510 = 0367 & 0301;
assign 0521 = ~VAR15;
assign 0532 = ~VAR17;
assign 0553 = ~VAR8;
assign 0554 = 0323 ^ 0553;
assign 0575 = 0554 ^ 0532;
assign 0576 = 0575 ^ VAR18;
assign 0587 = 0576 ^ VAR12;
assign 0598 = 0587 ^ 0521;
assign 0609 = 0344 & VAR19;
assign 0620 = 0609 ^ 0598;
assign 0631 = 0620 ^ 0202;
assign 0642 = ~(0345 | 0312);
assign 0653 = 0356 & VAR11;
assign 0664 = 0653 | 0642;
assign 0675 = 0664 ^ 0631;
assign 0686 = 0675 ^ 0510;
assign 0697 = 0686 ^ 0499;
assign 0708 = 0697 ^ 0488;
assign 0719 = 0708 ^ 0477;
assign 0730 = 0719 ^ 0466;
assign 0741 = 0730 ^ VAR3;
assign 0752 = 0741 ^ VAR16;
assign 0763 = 0752 ^ 0180;
assign 0774 = 0411 & 0268;
assign 0785 = 0422 & VAR10;
assign 0806 = ~(0785 | 0774);
assign 0807 = 0806 ^ 0763;
assign 0818 = ~(0807 ^ 0444);
assign 0829 = 0433 ^ VAR25;
assign 0840 = 0257 ^ 0180;
assign 0851 = 0840 | 0829;
assign 0862 = 0851 & VAR22;
assign 0873 = 0862 & 0818;
assign 0884 = 0763 & 0785;
assign 0895 = ~(0752 | 0180);
assign 0906 = 0763 & 0774;
assign 0907 = 0906 | 0895;
assign 0908 = 0741 & VAR16;
assign 0909 = ~(0730 & VAR3);
assign 0910 = 0719 | 0466;
assign 0911 = 0708 & 0477;
assign 0000 = 0697 | 0488;
assign 0001 = 0686 | 0499;
assign 0002 = 0675 & 0510;
assign 0003 = 0631 & 0653;
assign 0004 = ~0642;
assign 0005 = 0620 | 0202;
assign 0006 = ~(0005 & 0004);
assign 0007 = 0609 & 0598;
assign 0008 = 0587 | 0521;
assign 0009 = ~VAR13;
assign 0010 = ~(0554 | 0532);
assign 0011 = ~((0323 & 0553) | 0344);
assign 0012 = 0011 ^ 0010;
assign 0013 = 0012 ^ 0009;
assign 0014 = 0576 & VAR12;
assign 0015 = ~((0575 & VAR18) | 0014);
assign 0016 = 0015 ^ 0013;
assign 0017 = 0016 ^ 0008;
assign 0018 = 0017 ^ 0007;
assign 0019 = ~(0018 ^ 0006);
assign 0020 = 0019 ^ 0003;
assign 0021 = 0020 ^ VAR7;
assign 0022 = 0021 ^ 0002;
assign 0023 = 0022 ^ 0001;
assign 0024 = 0023 ^ 0000;
assign 0025 = 0024 ^ 0911;
assign 0026 = 0025 ^ 0910;
assign 0027 = 0026 ^ 0909;
assign 0028 = 0027 ^ VAR14;
assign 0029 = 0028 ^ 0908;
assign 0030 = 0029 ^ 0907;
assign 0031 = 0030 ^ 0884;
assign 0032 = ~VAR25;
assign 0033 = ~0444;
assign 0034 = ~(0807 | 0033);
assign 0035 = ~(0034 | 0032);
assign 0036 = 0035 ^ 0031;
assign 0037 = 0036 ^ 0873;
assign 0038 = ~VAR6;
assign 0039 = 0862 ^ 0818;
assign 0040 = ~0829;
assign 0041 = ~VAR22;
assign 0042 = ~(0840 | 0041);
assign 0043 = ~0042;
assign 0044 = ~(0840 & 0041);
assign 0045 = 0044 & 0043;
assign 0046 = ~((0045 & 0040) | 0038);
assign 0047 = 0046 & 0039;
assign 0048 = ~(0047 | 0038);
assign 0049 = 0048 ^ 0037;
assign 0050 = ~VAR2;
assign 0051 = ~(0046 ^ 0039);
assign 0052 = ~((0044 & VAR6) | 0042);
assign 0053 = 0052 ^ 0829;
assign 0054 = 0053 & 0051;
assign 0055 = ~(0054 | 0050);
assign 0056 = 0037 & VAR6;
assign 0057 = 0056 | 0047;
assign 0058 = 0036 & 0873;
assign 0059 = 0031 & VAR25;
assign 0060 = ~(0059 | 0034);
assign 0061 = 0030 & 0884;
assign 0062 = 0029 & 0906;
assign 0063 = 0027 & VAR14;
assign 0064 = 0063 | 0895;
assign 0065 = 0064 | 0062;
assign 0066 = ~(0400 & VAR4);
assign 0067 = ~((0025 | 0719) & VAR4);
assign 0068 = ~((0708 | 0066) & 0067);
assign 0069 = 0024 & 0911;
assign 0070 = ~(0023 | 0000);
assign 0071 = 0022 | 0001;
assign 0072 = ~0002;
assign 0073 = ~(0020 & VAR7);
assign 0074 = ~(0020 | VAR7);
assign 0075 = ~((0074 | 0072) & 0073);
assign 0076 = 0019 & 0003;
assign 0077 = ~((0005 & 0004) | 0018);
assign 0078 = ~0013;
assign 0079 = 0078 & 0014;
assign 0080 = ~(0575 & VAR18);
assign 0081 = 0013 | 0080;
assign 0082 = 0012 | 0009;
assign 0083 = ~0323;
assign 0084 = VAR17 & VAR8;
assign 0085 = ~((0084 & 0083) | 0344);
assign 0086 = 0085 ^ 0082;
assign 0087 = 0086 ^ 0081;
assign 0088 = 0087 ^ VAR12;
assign 0089 = 0088 ^ 0079;
assign 0090 = 0016 | 0587;
assign 0091 = 0090 & VAR15;
assign 0092 = 0091 ^ 0089;
assign 0093 = ~VAR19;
assign 0094 = 0598 & 0344;
assign 0095 = ~0016;
assign 0096 = ~((0095 & 0094) | 0093);
assign 0097 = 0096 ^ 0092;
assign 0098 = 0097 ^ 0077;
assign 0099 = 0098 ^ 0076;
assign 0100 = ~(0099 ^ 0075);
assign 0101 = 0100 ^ 0071;
assign 0102 = 0101 ^ VAR21;
assign 0103 = 0102 ^ 0070;
assign 0104 = 0103 ^ VAR24;
assign 0105 = 0104 ^ 0069;
assign 0106 = 0105 ^ VAR4;
assign 0107 = 0106 ^ 0068;
assign 0108 = ~VAR3;
assign 0109 = ~((0026 & 0730) | 0108);
assign 0110 = ~(0109 ^ 0107);
assign 0111 = ~(0026 & 0908);
assign 0112 = 0111 ^ 0110;
assign 0113 = 0112 ^ 0065;
assign 0114 = 0113 ^ VAR10;
assign 0115 = 0114 ^ 0061;
assign 0116 = 0115 ^ VAR9;
assign 0117 = 0116 ^ 0032;
assign 0118 = 0117 ^ 0060;
assign 0119 = 0118 ^ 0058;
assign 0120 = ~(0119 ^ 0057);
assign 0121 = ~(0120 | 0050);
assign 0122 = ~((0055 & 0049) | 0121);
assign 0123 = 0119 & 0057;
assign 0124 = 0118 & 0058;
assign 0125 = ~(0116 & VAR25);
assign 0126 = ~((0117 | 0060) & 0125);
assign 0127 = 0115 & VAR9;
assign 0128 = ~0061;
assign 0129 = ~(0113 & VAR10);
assign 0130 = ~(0113 | VAR10);
assign 0131 = ~((0130 | 0128) & 0129);
assign 0132 = 0112 & 0065;
assign 0133 = 0109 & 0107;
assign 0134 = 0105 & VAR4;
assign 0135 = 0106 & 0068;
assign 0136 = 0135 | 0134;
assign 0137 = 0103 & VAR24;
assign 0138 = 0104 & 0069;
assign 0139 = 0138 | 0137;
assign 0140 = 0101 & VAR21;
assign 0141 = 0102 & 0070;
assign 0142 = 0141 | 0140;
assign 0143 = 0099 & 0075;
assign 0144 = 0096 & 0092;
assign 0145 = 0091 & 0089;
assign 0146 = 0087 & VAR12;
assign 0147 = 0088 & 0079;
assign 0148 = 0147 | 0146;
assign 0149 = ~(0086 | 0081);
assign 0150 = ~((0085 | 0012) & VAR13);
assign 0151 = ~(0084 | 0323);
assign 0152 = 0151 | 0344;
assign 0153 = 0152 ^ 0150;
assign 0154 = 0153 ^ 0149;
assign 0155 = 0154 ^ 0148;
assign 0156 = 0155 ^ 0145;
assign 0157 = 0156 ^ 0144;
assign 0158 = 0097 & 0077;
assign 0159 = 0098 & 0076;
assign 0160 = 0159 | 0158;
assign 0161 = 0160 ^ 0157;
assign 0162 = 0161 ^ 0143;
assign 0163 = ~(0022 | 0686);
assign 0164 = ~((0100 & 0163) | 0499);
assign 0165 = 0164 ^ 0162;
assign 0166 = 0165 ^ 0142;
assign 0167 = 0166 ^ 0139;
assign 0168 = 0167 ^ 0136;
assign 0169 = 0168 ^ 0133;
assign 0170 = ~VAR16;
assign 0171 = 0026 & 0741;
assign 0172 = ~((0171 & 0110) | 0170);
assign 0173 = 0172 ^ 0169;
assign 0174 = 0173 ^ 0132;
assign 0175 = 0174 ^ 0131;
assign 0176 = 0175 ^ 0127;
assign 0177 = 0176 ^ 0126;
assign 0178 = 0177 ^ 0124;
assign 0179 = ~(0178 ^ 0123);
assign 0181 = 0179 | 0122;
assign 0182 = 0179 & 0122;
assign 0183 = 0049 ? 0055 : 0050;
assign 0184 = ~0054;
assign 0185 = ~(0184 | 0049);
assign 0186 = ~((0185 & 0121) | (0183 & 0120));
assign 0187 = 0053 & VAR2;
assign 0188 = 0053 | VAR2;
assign 0189 = 0045 ^ VAR6;
assign 0190 = ~((0189 & 0188) | 0187);
assign 0192 = 0051 ? 0187 : 0190;
assign 0193 = ~(0192 | 0186);
assign 0194 = ~((0193 | 0182) & 0181);
assign 0195 = 0176 & 0126;
assign 0196 = 0175 & 0127;
assign 0197 = 0174 & 0131;
assign 0198 = 0173 & 0132;
assign 0199 = 0172 & 0169;
assign 0200 = 0168 & 0133;
assign 0201 = ~(0167 & 0136);
assign 0203 = 0161 & 0143;
assign 0204 = 0164 & 0162;
assign 0205 = 0204 | 0203;
assign 0206 = 0160 & 0157;
assign 0207 = ~(0153 & 0149);
assign 0208 = ~((0152 | 0150) & 0207);
assign 0209 = ~((0154 & 0148) | 0208);
assign 0210 = 0155 & 0145;
assign 0211 = ~((0156 & 0144) | 0210);
assign 0212 = 0211 ^ 0209;
assign 0214 = 0212 ^ 0206;
assign 0215 = ~(0214 ^ 0205);
assign 0216 = 0165 & 0142;
assign 0217 = ~((0166 & 0139) | 0216);
assign 0218 = ~(0217 ^ 0215);
assign 0219 = 0218 ^ 0201;
assign 0220 = 0219 ^ 0200;
assign 0221 = 0220 ^ 0199;
assign 0222 = 0221 ^ 0198;
assign 0223 = 0222 ^ 0197;
assign 0225 = 0223 ^ 0196;
assign 0226 = ~(0225 ^ 0195);
assign 0227 = 0177 & 0124;
assign 0228 = ~((0178 & 0123) | 0227);
assign 0229 = 0228 ^ 0226;
assign 0230 = ~(VAR4 ^ VAR19);
assign 0231 = 0230 ^ VAR3;
assign 0232 = ~(0231 | 0170);
assign 0233 = ~(0230 & VAR3);
assign 0234 = ~(VAR18 ^ VAR23);
assign 0236 = 0234 & VAR12;
assign 0237 = ~(0234 | VAR12);
assign 0238 = ~(0237 | 0236);
assign 0239 = 0238 ^ 0521;
assign 0240 = 0239 ^ 0093;
assign 0241 = 0240 ^ VAR1;
assign 0242 = 0241 ^ 0499;
assign 0243 = 0242 ^ VAR21;
assign 0244 = 0243 | 0279;
assign 0245 = ~(0243 & 0279);
assign 0247 = ~(0245 & 0244);
assign 0248 = VAR4 & 0093;
assign 0249 = ~(0247 ^ 0248);
assign 0250 = 0233 ? 0249 : 0247;
assign 0251 = ~(0250 ^ 0232);
assign 0252 = 0231 ^ 0170;
assign 0253 = ~(0252 | 0180);
assign 0254 = ~(0252 & 0180);
assign 0255 = ~((0254 & VAR9) | 0253);
assign 0256 = 0255 ^ 0251;
assign 0258 = ~(0256 | 0032);
assign 0259 = ~VAR9;
assign 0260 = ~0251;
assign 0261 = ~0253;
assign 0262 = 0254 & 0261;
assign 0263 = ~((0262 & 0260) | 0259);
assign 0264 = 0240 & VAR1;
assign 0265 = ~(VAR18 & VAR23);
assign 0266 = VAR17 ^ VAR26;
assign 0267 = 0266 ^ 0009;
assign 0269 = ~(0267 ^ 0265);
assign 0270 = ~0269;
assign 0271 = ~(0236 | VAR15);
assign 0272 = 0271 | 0237;
assign 0273 = 0272 ^ 0270;
assign 0274 = ~0273;
assign 0275 = ~(0239 | 0093);
assign 0276 = 0273 ^ 0275;
assign 0277 = 0264 ? 0274 : 0276;
assign 0278 = ~(0241 | 0499);
assign 0280 = ~((0242 & VAR21) | 0278);
assign 0281 = 0280 ^ 0277;
assign 0282 = ~0244;
assign 0283 = ~((0245 & 0248) | 0282);
assign 0284 = 0283 ^ 0281;
assign 0285 = ~(0247 | 0233);
assign 0286 = ~(0285 ^ 0284);
assign 0287 = ~0232;
assign 0288 = ~(0250 | 0287);
assign 0289 = ~(0288 | 0170);
assign 0291 = 0289 ^ 0286;
assign 0292 = 0261 | 0251;
assign 0293 = 0292 ^ 0291;
assign 0294 = ~(0293 ^ 0263);
assign 0295 = 0294 & 0258;
assign 0296 = ~0263;
assign 0297 = ~(0293 | 0296);
assign 0298 = ~0291;
assign 0299 = ~(0252 | 0251);
assign 0300 = ~((0299 & 0298) | 0180);
assign 0302 = 0281 | VAR19;
assign 0303 = ~((0302 | 0247) & VAR4);
assign 0304 = ~(0281 | 0244);
assign 0305 = ~(0242 & VAR21);
assign 0306 = ~(0277 | 0305);
assign 0307 = ~0277;
assign 0308 = 0307 & 0278;
assign 0309 = ~((0264 | 0275) & 0273);
assign 0310 = 0269 & 0238;
assign 0311 = ~(0310 | 0521);
assign 0313 = ~(0267 | 0265);
assign 0314 = 0266 | 0009;
assign 0315 = ~VAR23;
assign 0316 = ~(VAR17 & VAR26);
assign 0317 = ~(0316 ^ VAR20);
assign 0318 = 0317 ^ 0315;
assign 0319 = 0318 ^ 0314;
assign 0320 = ~(0319 ^ 0313);
assign 0321 = 0269 & 0236;
assign 0322 = 0321 ^ 0320;
assign 0324 = 0322 ^ 0311;
assign 0325 = 0324 ^ 0309;
assign 0326 = 0325 ^ VAR11;
assign 0327 = 0326 ^ 0308;
assign 0328 = ~(0327 ^ 0306);
assign 0329 = 0328 ^ 0304;
assign 0330 = 0329 ^ 0303;
assign 0331 = ~0230;
assign 0332 = ~(0247 | 0331);
assign 0333 = ~((0332 & 0284) | 0108);
assign 0334 = 0333 ^ 0330;
assign 0335 = 0334 ^ VAR16;
assign 0336 = 0286 & VAR16;
assign 0337 = 0336 | 0288;
assign 0338 = 0337 ^ 0335;
assign 0339 = 0338 ^ 0300;
assign 0340 = 0339 ^ VAR10;
assign 0341 = 0340 ^ 0297;
assign 0342 = 0341 ^ 0295;
assign 0343 = 0256 ^ 0032;
assign 0346 = 0262 ^ 0259;
assign 0347 = 0346 & 0343;
assign 0348 = 0294 ^ 0258;
assign 0349 = ~((0348 | 0347) & VAR22);
assign 0350 = ~0349;
assign 0351 = 0350 & 0342;
assign 0352 = ~0351;
assign 0353 = 0340 & 0297;
assign 0354 = ~0339;
assign 0355 = 0338 & 0300;
assign 0357 = ~0286;
assign 0358 = 0357 & 0288;
assign 0359 = 0358 & 0335;
assign 0360 = 0334 & VAR16;
assign 0361 = 0336 | 0360;
assign 0362 = 0361 | 0359;
assign 0363 = 0333 & 0330;
assign 0364 = ~(0329 | 0303);
assign 0365 = 0327 & 0306;
assign 0366 = 0326 & 0308;
assign 0368 = ~(0325 & VAR11);
assign 0369 = ~0311;
assign 0370 = ~(0322 | 0369);
assign 0371 = ~VAR12;
assign 0372 = 0269 & 0234;
assign 0373 = ~((0372 & 0320) | 0371);
assign 0374 = 0319 & 0313;
assign 0375 = ~(0317 & VAR23);
assign 0376 = VAR23 & VAR17;
assign 0377 = ~0376;
assign 0379 = ~(0377 | 0213);
assign 0380 = 0323 | 0532;
assign 0381 = ~((0380 & 0375) | 0379);
assign 0382 = ~0266;
assign 0383 = ~((0318 & 0382) | 0009);
assign 0384 = 0383 ^ 0381;
assign 0385 = 0384 ^ VAR18;
assign 0386 = 0385 ^ 0374;
assign 0387 = 0386 ^ 0373;
assign 0388 = ~(0387 ^ 0370);
assign 0390 = ~0239;
assign 0391 = 0324 & 0273;
assign 0392 = ~((0391 & 0390) | 0093);
assign 0393 = 0392 ^ 0388;
assign 0394 = 0391 & 0264;
assign 0395 = 0394 ^ 0393;
assign 0396 = 0395 ^ 0368;
assign 0397 = 0396 ^ VAR7;
assign 0398 = 0397 ^ VAR5;
assign 0399 = 0398 ^ 0366;
assign 0401 = 0399 ^ VAR21;
assign 0402 = 0401 ^ 0365;
assign 0403 = ~(0281 | 0243);
assign 0404 = ~((0328 & 0403) | 0279);
assign 0405 = 0404 ^ 0402;
assign 0406 = 0405 ^ 0364;
assign 0407 = 0406 ^ 0363;
assign 0408 = 0407 ^ VAR16;
assign 0409 = 0408 ^ 0362;
assign 0410 = 0409 ^ VAR14;
assign 0412 = 0355 ? 0409 : 0410;
assign 0413 = 0412 & VAR10;
assign 0414 = ~(0339 & VAR10);
assign 0415 = ~((0412 | VAR10) & (0410 | 0414));
assign 0416 = ~((0413 & 0354) | 0415);
assign 0417 = 0416 ^ 0353;
assign 0418 = 0417 ^ 0032;
assign 0419 = ~(0418 | 0352);
assign 0420 = 0416 & 0353;
assign 0421 = ~(0410 | 0414);
assign 0423 = 0421 | 0413;
assign 0424 = 0409 & VAR14;
assign 0425 = 0424 | 0355;
assign 0426 = 0407 & VAR16;
assign 0427 = 0408 & 0362;
assign 0428 = 0427 | 0426;
assign 0429 = 0406 & 0363;
assign 0430 = ~(0399 & VAR21);
assign 0431 = ~(0401 & 0365);
assign 0432 = ~(0431 & 0430);
assign 0434 = 0397 & VAR5;
assign 0435 = 0398 & 0366;
assign 0436 = 0435 | 0434;
assign 0437 = 0391 & 0240;
assign 0438 = ~((0437 & 0393) | 0202);
assign 0439 = ~0388;
assign 0440 = 0392 & 0439;
assign 0441 = 0384 & VAR18;
assign 0442 = ~((0385 & 0374) | 0441);
assign 0443 = ~((0377 | 0213) & (0083 | 0532));
assign 0445 = ~((0383 & 0381) | 0443);
assign 0446 = ~(0445 | 0442);
assign 0447 = 0445 & 0442;
assign 0448 = ~(0447 | 0446);
assign 0449 = 0386 & 0373;
assign 0450 = ~((0387 & 0370) | 0449);
assign 0451 = ~(0450 ^ 0448);
assign 0452 = 0451 ^ 0440;
assign 0453 = 0452 ^ 0438;
assign 0454 = ~(0395 | 0368);
assign 0456 = 0396 & VAR7;
assign 0457 = 0456 | 0454;
assign 0458 = 0457 ^ 0453;
assign 0459 = 0458 ^ 0436;
assign 0460 = 0459 ^ 0432;
assign 0461 = 0404 & 0402;
assign 0462 = 0405 & 0364;
assign 0463 = 0462 | 0461;
assign 0464 = 0463 ^ 0460;
assign 0465 = 0464 ^ 0429;
assign 0467 = 0465 ^ 0428;
assign 0468 = 0467 ^ 0425;
assign 0469 = 0468 ^ 0423;
assign 0470 = ~(0469 ^ 0420);
assign 0471 = 0341 & 0295;
assign 0472 = ~((0417 & VAR25) | 0471);
assign 0473 = 0472 ^ 0470;
assign 0474 = ~(0473 & 0419);
assign 0475 = 0465 & 0428;
assign 0476 = 0464 & 0429;
assign 0478 = 0460 & 0462;
assign 0479 = 0460 & 0461;
assign 0480 = 0459 & 0432;
assign 0481 = 0458 & 0436;
assign 0482 = 0453 & 0456;
assign 0483 = ~(0453 & 0454);
assign 0484 = ~(0387 & 0370);
assign 0485 = ~0448;
assign 0486 = ~(0446 | 0449);
assign 0487 = ~((0486 | 0447) & (0485 | 0484));
assign 0489 = 0451 & 0440;
assign 0490 = ~((0452 & 0438) | 0489);
assign 0491 = 0490 ^ 0487;
assign 0492 = 0491 ^ 0483;
assign 0493 = 0492 ^ 0482;
assign 0494 = 0493 ^ 0481;
assign 0495 = 0494 ^ 0480;
assign 0496 = 0495 ^ 0479;
assign 0497 = 0496 ^ 0478;
assign 0498 = 0497 ^ 0476;
assign 0500 = 0498 & 0475;
assign 0501 = ~(0498 | 0475);
assign 0502 = ~(0501 | 0500);
assign 0503 = 0467 & 0425;
assign 0504 = 0468 & 0423;
assign 0505 = 0504 | 0503;
assign 0506 = 0505 ^ 0502;
assign 0507 = ~(0469 & 0420);
assign 0508 = ~((0472 | 0470) & 0507);
assign 0509 = ~(0508 ^ 0506);
assign 0511 = 0509 | 0474;
assign 0512 = ~(0502 & 0504);
assign 0513 = ~(0497 & 0476);
assign 0514 = ~(0495 & 0479);
assign 0515 = ~(0493 & 0481);
assign 0516 = ~0487;
assign 0517 = 0490 | 0516;
assign 0518 = ~((0491 | 0483) & 0517);
assign 0519 = ~((0492 & 0482) | 0518);
assign 0520 = ~(0519 & 0515);
assign 0522 = ~((0494 & 0480) | 0520);
assign 0523 = ~(0522 & 0514);
assign 0524 = ~((0496 & 0478) | 0523);
assign 0525 = 0524 & 0513;
assign 0526 = ~((0502 & 0503) | 0500);
assign 0527 = 0526 ^ 0525;
assign 0528 = ~(0527 ^ 0512);
assign 0529 = 0508 & 0506;
assign 0530 = ~(0529 ^ 0528);
assign 0531 = ~(0347 | 0041);
assign 0533 = 0531 ^ 0348;
assign 0534 = 0346 & VAR22;
assign 0535 = ~((0534 & 0343) | 0050);
assign 0536 = ~((0534 | 0343) & 0535);
assign 0537 = ~0536;
assign 0538 = 0349 ^ 0342;
assign 0539 = ~(0538 | 0050);
assign 0540 = ~((0533 & VAR2) | 0537);
assign 0541 = ~(0540 | 0539);
assign 0542 = ~0541;
assign 0543 = ~(0538 & 0050);
assign 0544 = 0543 | 0533;
assign 0545 = ~((0544 & 0542) | (0537 & 0533));
assign 0546 = 0473 ^ 0419;
assign 0547 = ~(0351 | 0471);
assign 0548 = 0547 ^ 0418;
assign 0549 = 0548 & VAR2;
assign 0550 = 0541 | 0539;
assign 0551 = 0548 ^ VAR2;
assign 0552 = ~((0551 | 0550) & (0549 | 0546));
assign 0555 = 0552 | 0545;
assign 0556 = 0550 | 0549;
assign 0557 = ~(0509 & 0474);
assign 0558 = ~((0557 & 0511) | (0556 & 0546));
assign 0559 = ~((0558 & 0555) | (0530 & 0511));
assign 0560 = 0526 | 0525;
assign 0561 = 0526 & 0525;
assign 0562 = ~((0561 | 0512) & 0560);
assign 0563 = ~((0529 & 0528) | 0562);
assign 0564 = ~((0530 | 0511) & 0563);
assign 0565 = 0228 | 0226;
assign 0566 = ~VAR10;
assign 0567 = VAR23 ^ VAR8;
assign 0568 = 0567 ^ VAR12;
assign 0569 = 0568 ^ VAR1;
assign 0570 = 0569 ^ VAR11;
assign 0571 = 0570 ^ 0455;
assign 0572 = ~(0571 | 0170);
assign 0573 = ~(0570 | 0455);
assign 0574 = 0569 & VAR11;
assign 0577 = 0567 & VAR12;
assign 0578 = 0568 & VAR1;
assign 0579 = 0578 | 0577;
assign 0580 = VAR23 ^ VAR17;
assign 0581 = VAR8 ? 0532 : 0580;
assign 0582 = 0581 ^ VAR18;
assign 0583 = 0582 ^ 0579;
assign 0584 = 0583 ^ 0574;
assign 0585 = 0584 ^ 0499;
assign 0586 = 0585 ^ VAR21;
assign 0588 = 0586 ^ 0573;
assign 0589 = 0588 ^ 0108;
assign 0590 = 0589 ^ 0572;
assign 0591 = 0590 ^ 0180;
assign 0592 = 0591 ^ 0566;
assign 0593 = 0571 ^ 0170;
assign 0594 = ~(0593 | 0259);
assign 0595 = ~(0594 ^ 0592);
assign 0596 = 0593 ^ VAR9;
assign 0597 = 0596 & VAR22;
assign 0599 = ~(0597 ^ 0595);
assign 0600 = 0599 & VAR6;
assign 0601 = ~0592;
assign 0602 = 0594 & 0601;
assign 0603 = ~0602;
assign 0604 = ~(0591 | 0566);
assign 0605 = ~(0590 | 0180);
assign 0606 = 0589 & 0572;
assign 0607 = 0588 | 0108;
assign 0608 = 0586 & 0573;
assign 0610 = 0582 & 0577;
assign 0611 = ~VAR18;
assign 0612 = 0581 | 0611;
assign 0613 = 0084 ^ VAR26;
assign 0614 = ~((0532 & 0553) | 0315);
assign 0615 = 0614 ^ 0613;
assign 0616 = 0615 ^ 0009;
assign 0617 = 0616 ^ 0612;
assign 0618 = 0617 ^ 0610;
assign 0619 = 0618 ^ VAR15;
assign 0621 = ~(0582 & 0578);
assign 0622 = 0621 & VAR1;
assign 0623 = 0622 ^ 0619;
assign 0624 = ~(0583 & 0574);
assign 0625 = 0624 & VAR11;
assign 0626 = 0625 ^ 0623;
assign 0627 = ~(0584 | 0499);
assign 0628 = ~((0585 & VAR21) | 0627);
assign 0629 = 0628 ^ 0626;
assign 0630 = 0629 ^ VAR24;
assign 0632 = 0630 ^ 0608;
assign 0633 = 0632 ^ 0607;
assign 0634 = 0633 ^ 0606;
assign 0635 = 0634 ^ 0605;
assign 0636 = 0635 ^ 0604;
assign 0637 = 0636 ^ 0603;
assign 0638 = ~0595;
assign 0639 = ~(0596 & 0638);
assign 0640 = 0639 & VAR22;
assign 0641 = 0640 ^ 0637;
assign 0643 = ~0641;
assign 0644 = 0643 & 0600;
assign 0645 = ~0644;
assign 0646 = ~((0637 & 0639) | 0041);
assign 0647 = 0636 | 0603;
assign 0648 = 0634 | 0590;
assign 0649 = 0648 & VAR14;
assign 0650 = ~(0630 & 0586);
assign 0651 = 0650 | 0570;
assign 0652 = 0651 & VAR4;
assign 0654 = 0629 & VAR24;
assign 0655 = ~0626;
assign 0656 = ~((0655 & 0585) | 0191);
assign 0657 = ~((0623 & VAR11) | (0583 & 0574));
assign 0658 = ~0621;
assign 0659 = ~((0619 & VAR1) | 0658);
assign 0660 = ~(0615 | 0009);
assign 0661 = ~(0614 & 0613);
assign 0662 = ~0661;
assign 0663 = 0316 & VAR8;
assign 0665 = 0663 ^ 0213;
assign 0666 = 0665 ^ 0315;
assign 0667 = 0666 ^ 0662;
assign 0668 = 0667 ^ 0660;
assign 0669 = ~0581;
assign 0670 = ~((0616 & 0669) | 0611);
assign 0671 = 0670 ^ 0668;
assign 0672 = 0617 & 0610;
assign 0673 = ~((0618 & VAR15) | 0672);
assign 0674 = 0673 ^ 0671;
assign 0676 = 0674 ^ 0659;
assign 0677 = ~(0676 ^ VAR11);
assign 0678 = ~(0677 ^ 0657);
assign 0679 = 0678 ^ VAR7;
assign 0680 = 0655 & 0627;
assign 0681 = ~(0680 ^ 0679);
assign 0682 = 0681 ^ 0656;
assign 0683 = 0682 ^ 0654;
assign 0684 = 0683 ^ 0652;
assign 0685 = 0684 ^ 0108;
assign 0687 = ~(0632 | 0607);
assign 0688 = ~((0633 & 0606) | 0687);
assign 0689 = 0688 ^ 0685;
assign 0690 = ~(0689 ^ 0649);
assign 0691 = 0635 & 0604;
assign 0692 = ~(0691 | 0566);
assign 0693 = 0692 ^ 0690;
assign 0694 = 0693 ^ 0647;
assign 0695 = ~(0694 ^ 0646);
assign 0696 = ~((0695 | 0038) & 0645);
assign 0698 = ~(0690 | 0566);
assign 0699 = ~(0698 | 0691);
assign 0700 = ~(0633 & 0606);
assign 0701 = ~(0685 | 0700);
assign 0702 = 0684 & VAR3;
assign 0703 = 0702 | 0687;
assign 0704 = ~0629;
assign 0705 = 0682 | 0704;
assign 0706 = 0705 & VAR24;
assign 0707 = ~VAR7;
assign 0709 = ~(0678 | 0707);
assign 0710 = 0623 | 0624;
assign 0711 = ~((0676 | 0623) & VAR11);
assign 0712 = ~((0710 | 0677) & 0711);
assign 0713 = ~(0674 | 0659);
assign 0714 = 0671 & 0672;
assign 0715 = 0670 & 0668;
assign 0716 = ~(0666 & 0662);
assign 0717 = ~((0665 | 0315) & 0716);
assign 0718 = ~VAR26;
assign 0720 = VAR20 & 0718;
assign 0721 = VAR20 | 0718;
assign 0722 = ~((0721 & 0553) | 0720);
assign 0723 = ~(0722 | VAR17);
assign 0724 = 0722 & VAR17;
assign 0725 = ~(0323 & VAR8);
assign 0726 = ~((0725 & 0724) | 0723);
assign 0727 = 0726 ^ VAR23;
assign 0728 = 0727 ^ 0717;
assign 0729 = ~(0615 & VAR13);
assign 0731 = ~(0667 & VAR13);
assign 0732 = ~((0666 | 0729) & 0731);
assign 0733 = ~(0732 | 0009);
assign 0734 = 0733 ^ 0728;
assign 0735 = 0734 ^ 0715;
assign 0736 = ~(0735 ^ 0714);
assign 0737 = ~(0671 & 0618);
assign 0738 = ~(0737 & VAR15);
assign 0739 = 0738 ^ 0736;
assign 0740 = 0739 ^ 0713;
assign 0742 = 0740 ^ 0712;
assign 0743 = 0742 ^ 0709;
assign 0744 = ~(0626 | 0584);
assign 0745 = ~((0744 & 0679) | 0499);
assign 0746 = 0745 ^ 0743;
assign 0747 = 0681 & 0656;
assign 0748 = ~(0747 | 0191);
assign 0749 = 0748 ^ 0746;
assign 0750 = ~(0749 ^ 0706);
assign 0751 = ~(0683 & 0652);
assign 0753 = 0751 & VAR4;
assign 0754 = 0753 ^ 0750;
assign 0755 = 0754 ^ 0108;
assign 0756 = 0755 ^ 0703;
assign 0757 = ~(0756 ^ 0701);
assign 0758 = ~(0689 & 0649);
assign 0759 = ~(0758 & VAR14);
assign 0760 = 0759 ^ 0757;
assign 0761 = 0760 ^ 0566;
assign 0762 = 0761 ^ 0699;
assign 0764 = ~(0636 | 0593);
assign 0765 = 0764 & 0601;
assign 0766 = ~((0765 & 0693) | 0259);
assign 0767 = ~(0766 ^ 0762);
assign 0768 = ~(0694 & 0646);
assign 0769 = ~(0768 & VAR22);
assign 0770 = 0769 ^ 0767;
assign 0771 = ~(0770 & 0696);
assign 0772 = ~((0767 | 0041) & 0768);
assign 0773 = 0766 & 0762;
assign 0775 = ~(0760 & VAR10);
assign 0776 = ~((0761 | 0699) & 0775);
assign 0777 = ~((0757 | 0180) & 0758);
assign 0778 = 0756 & 0701;
assign 0779 = ~(0755 & 0703);
assign 0780 = ~((0754 | 0108) & 0779);
assign 0781 = ~((0750 | 0455) & 0751);
assign 0782 = 0749 & 0706;
assign 0783 = ~((0746 & VAR21) | 0747);
assign 0784 = 0740 & 0712;
assign 0786 = 0739 & 0713;
assign 0787 = ~((0737 & 0736) | 0521);
assign 0788 = 0734 & 0715;
assign 0789 = 0728 & VAR13;
assign 0790 = 0789 | 0732;
assign 0791 = 0726 & VAR23;
assign 0792 = ~((0727 & 0717) | 0791);
assign 0793 = 0084 & VAR26;
assign 0794 = ~0793;
assign 0795 = ~((0083 & 0553) | 0344);
assign 0796 = ~((0795 | 0724) & 0794);
assign 0797 = ~((0796 & 0792) | 0662);
assign 0798 = 0797 ^ 0790;
assign 0799 = 0798 | 0788;
assign 0800 = ~((0798 & 0788) | (0735 & 0714));
assign 0801 = 0800 & 0799;
assign 0802 = 0801 ^ 0787;
assign 0803 = 0802 ^ 0786;
assign 0804 = 0803 ^ 0784;
assign 0805 = 0742 & 0709;
assign 0808 = 0745 & 0743;
assign 0809 = ~(0808 | 0805);
assign 0810 = 0809 ^ 0804;
assign 0811 = 0810 ^ 0783;
assign 0812 = 0811 ^ 0782;
assign 0813 = 0812 ^ 0781;
assign 0814 = 0813 ^ 0780;
assign 0815 = 0814 ^ 0778;
assign 0816 = 0815 ^ 0777;
assign 0817 = 0816 ^ 0776;
assign 0819 = 0817 ^ 0773;
assign 0820 = ~(0819 ^ 0772);
assign 0821 = ~(0820 | 0771);
assign 0822 = 0819 & 0772;
assign 0823 = ~(0817 & 0773);
assign 0824 = 0816 & 0776;
assign 0825 = ~(0815 & 0777);
assign 0826 = 0812 & 0781;
assign 0827 = 0811 & 0782;
assign 0828 = ~(0804 & 0808);
assign 0830 = ~((0810 | 0783) & 0828);
assign 0831 = 0797 & 0790;
assign 0832 = 0661 & 0794;
assign 0833 = 0831 ? 0793 : 0832;
assign 0834 = 0833 & 0800;
assign 0835 = 0801 & 0787;
assign 0836 = ~((0802 & 0786) | 0835);
assign 0837 = ~(0836 ^ 0834);
assign 0838 = ~((0804 & 0805) | (0802 & 0784));
assign 0839 = 0838 ^ 0837;
assign 0841 = 0839 ^ 0830;
assign 0842 = 0841 ^ 0827;
assign 0843 = ~(0842 ^ 0826);
assign 0844 = 0813 & 0780;
assign 0845 = ~((0814 & 0778) | 0844);
assign 0846 = ~(0845 ^ 0843);
assign 0847 = 0846 ^ 0825;
assign 0848 = ~(0847 ^ 0824);
assign 0849 = 0848 ^ 0823;
assign 0850 = 0849 ^ 0822;
assign 0852 = ~(0770 ^ 0696);
assign 0853 = ~(0644 | 0038);
assign 0854 = 0853 ^ 0695;
assign 0855 = 0854 | 0050;
assign 0856 = ~(0855 | 0852);
assign 0857 = ~(0596 | VAR22);
assign 0858 = ~(0599 | VAR6);
assign 0859 = ~((0858 | 0600) & (0857 | 0597));
assign 0860 = ~(0641 ^ 0600);
assign 0861 = ~((0860 & 0859) | VAR2);
assign 0863 = 0861 & 0854;
assign 0864 = ~((0863 & 0852) | (0820 & 0771));
assign 0865 = 0821 ? 0849 : 0864;
assign 0866 = ~((0865 | 0856) & (0850 | 0821));
assign 0867 = 0223 & 0196;
assign 0868 = 0221 & 0198;
assign 0869 = ~(0219 & 0200);
assign 0870 = ~(0218 | 0201);
assign 0871 = ~(0212 & 0206);
assign 0872 = ~((0211 | 0209) & 0871);
assign 0874 = ~((0214 & 0205) | 0872);
assign 0875 = ~((0217 | 0215) & 0874);
assign 0876 = ~(0875 | 0870);
assign 0877 = ~(0876 ^ 0869);
assign 0878 = 0220 & 0199;
assign 0879 = 0876 ^ 0869;
assign 0880 = 0878 ? 0876 : 0879;
assign 0881 = 0868 ? 0877 : 0880;
assign 0882 = ~(0222 & 0197);
assign 0883 = 0881 ^ 0882;
assign 0885 = 0867 ? 0881 : 0883;
assign 0886 = 0842 & 0826;
assign 0887 = ~(0836 | 0834);
assign 0888 = ~((0831 & 0793) | 0887);
assign 0889 = ~((0838 | 0837) & 0888);
assign 0890 = ~((0839 & 0830) | 0889);
assign 0891 = ~(0890 & 0886);
assign 0892 = ~((0845 | 0843) & 0891);
assign 0893 = ~(0841 & 0827);
assign 0894 = 0890 & 0893;
assign 0896 = ~((0846 | 0825) & 0894);
assign 0897 = 0896 | 0892;
assign 0898 = ~((0847 & 0824) | 0897);
assign 0899 = ~((0848 | 0823) & 0898);
assign 0900 = ~((0849 & 0822) | 0899);
assign 0901 = 0900 & 0885;
assign 0902 = ~(0901 & 0866);
assign 0903 = ~((0225 & 0195) | 0902);
assign 0904 = 0903 & 0565;
assign 0905 = ~((0564 | 0559) & 0904);
assign valid = ~((0229 & 0194) | 0905);
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.behavioral.v | 1,116 | module MODULE1( VAR2, VAR3 );
input VAR2;
output VAR3;
VAR1 VAR5(.VAR2(VAR2),.VAR3(VAR3));
VAR1 VAR4(.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
liuyenting/CA-Project | src/L1_Cache_rework.v | 4,869 | module MODULE1
parameter VAR7 = 32,
parameter VAR39 = 32,
parameter VAR45 = 256
)
(
input clk,
input rst,
input [VAR7-1:0] VAR14,
input VAR36,
input VAR37,
output VAR13,
input [VAR39-1:0] VAR16,
output [VAR39-1:0] VAR18,
output [VAR7-1:0] VAR27,
output VAR60,
output VAR54,
input VAR35,
input [VAR45-1:0] VAR59,
output [VAR45-1:0] VAR31
);
wire [21:0] VAR26;
wire [4:0] VAR5;
wire [4:0] VAR17;
wire [2:0] VAR9 = VAR17[4:2];
wire VAR1;
wire VAR50;
wire [21:0] VAR41;
wire VAR42;
assign VAR26 = VAR14[31:10];
assign VAR5 = VAR14[9:5];
assign VAR17 = VAR14[4:0];
assign VAR1 = VAR47.VAR8[23];
assign VAR50 = VAR47.VAR8[22];
assign VAR41 = VAR47.VAR8[21:0];
assign VAR42 = ((VAR26 == VAR41) && VAR1) ? 1'b1 : 1'b0;
assign VAR27 = {VAR41, VAR5, 5'b0};
assign VAR31 = VAR25.VAR8;
VAR28 VAR30 (
.clk (clk),
.rst (rst),
.VAR36 (VAR36),
.VAR37 (VAR37),
.VAR13 (VAR13),
.VAR42 (VAR42),
.VAR29 (),
.VAR21 (VAR1),
.VAR4 (VAR50),
.VAR23 (),
.VAR3 (),
.VAR60 (VAR60),
.VAR54 (VAR54),
.VAR35 (VAR35)
);
VAR15 #(.VAR7(5), .VAR12(24), .VAR51(32)) VAR47
(
.clk (clk),
.VAR53 (VAR5),
.VAR2 (1'b1),
.VAR46 (VAR30.VAR29),
.VAR11 ({1'b1, VAR30.VAR23, VAR26}),
.VAR8 ()
);
VAR48 decoder (
.sel (VAR9),
.out ()
);
VAR34 VAR43 (
.VAR40 (VAR25.VAR8[255:224]),
.VAR55 (VAR25.VAR8[255:224]),
.VAR52 (VAR16),
.VAR56 (VAR59[255:224]),
.sel ({decoder.out[0], VAR30.VAR3}),
.VAR8 (VAR25.VAR11[255:224])
);
VAR34 VAR22 (
.VAR40 (VAR25.VAR8[223:192]),
.VAR55 (VAR25.VAR8[223:192]),
.VAR52 (VAR16),
.VAR56 (VAR59[223:192]),
.sel ({decoder.out[1], VAR30.VAR3}),
.VAR8 (VAR25.VAR11[223:192])
);
VAR34 VAR44 (
.VAR40 (VAR25.VAR8[191:160]),
.VAR55 (VAR25.VAR8[191:160]),
.VAR52 (VAR16),
.VAR56 (VAR59[191:160]),
.sel ({decoder.out[2], VAR30.VAR3}),
.VAR8 (VAR25.VAR11[191:160])
);
VAR34 VAR38 (
.VAR40 (VAR25.VAR8[159:128]),
.VAR55 (VAR25.VAR8[159:128]),
.VAR52 (VAR16),
.VAR56 (VAR59[159:128]),
.sel ({decoder.out[3], VAR30.VAR3}),
.VAR8 (VAR25.VAR11[159:128])
);
VAR34 VAR58 (
.VAR40 (VAR25.VAR8[127:96]),
.VAR55 (VAR25.VAR8[127:96]),
.VAR52 (VAR16),
.VAR56 (VAR59[127:96]),
.sel ({decoder.out[4], VAR30.VAR3}),
.VAR8 (VAR25.VAR11[127:96])
);
VAR34 VAR32 (
.VAR40 (VAR25.VAR8[95:64]),
.VAR55 (VAR25.VAR8[95:64]),
.VAR52 (VAR16),
.VAR56 (VAR59[95:64]),
.sel ({decoder.out[5], VAR30.VAR3}),
.VAR8 (VAR25.VAR11[95:64])
);
VAR34 VAR49 (
.VAR40 (VAR25.VAR8[63:32]),
.VAR55 (VAR25.VAR8[63:32]),
.VAR52 (VAR16),
.VAR56 (VAR59[63:32]),
.sel ({decoder.out[6], VAR30.VAR3}),
.VAR8 (VAR25.VAR11[63:32])
);
VAR34 VAR24 (
.VAR40 (VAR25.VAR8[31:0]),
.VAR55 (VAR25.VAR8[31:0]),
.VAR52 (VAR16),
.VAR56 (VAR59[31:0]),
.sel ({decoder.out[7], VAR30.VAR3}),
.VAR8 (VAR25.VAR11[31:0])
);
VAR15 #(.VAR7(5), .VAR12(256), .VAR51(32)) VAR25
(
.clk (clk),
.VAR53 (VAR5),
.VAR2 (1'b1),
.VAR46 (VAR30.VAR29),
.VAR11 (),
.VAR8 ()
);
VAR19 VAR33 (
.VAR40 (VAR25.VAR8[255:224]),
.VAR55 (VAR25.VAR8[223:192]),
.VAR52 (VAR25.VAR8[191:160]),
.VAR56 (VAR25.VAR8[159:128]),
.VAR10 (VAR25.VAR8[127:96]),
.VAR57 (VAR25.VAR8[95:64]),
.VAR6 (VAR25.VAR8[63:32]),
.VAR20 (VAR25.VAR8[31:0]),
.sel (VAR9),
.VAR8 (VAR18)
);
endmodule | gpl-3.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/reg_gpr.v | 3,987 | module MODULE1(
clk, rst,
VAR18, VAR27, VAR32, VAR37,
VAR20, VAR26, VAR10,
VAR4, VAR12, VAR36, VAR2, VAR38, VAR6
);
parameter VAR13 = VAR11;
parameter VAR23 = VAR25;
input clk;
input rst;
input VAR18;
input VAR27;
input [VAR23-1:0] VAR4;
input [VAR23-1:0] VAR12;
input VAR38;
input VAR6;
output [VAR13-1:0] VAR36;
output [VAR13-1:0] VAR2;
input VAR32;
input VAR37;
input [VAR23-1:0] VAR20;
input [VAR13-1:0] VAR26;
input VAR10;
reg [VAR13:0] VAR30;
reg [VAR13:0] VAR17;
wire [VAR13-1:0] VAR19;
wire [VAR13-1:0] VAR9;
wire [VAR23-1:0] VAR28;
wire [VAR23-1:0] VAR29;
wire VAR35;
wire VAR39;
wire [VAR23-1:0] VAR20;
wire [VAR13-1:0] VAR26;
wire VAR10;
wire [VAR23-1:0] VAR7;
wire [VAR13-1:0] VAR8;
wire VAR1;
assign VAR28 = VAR4;
assign VAR29 = VAR12;
assign VAR35 = VAR38 & ~VAR18;
assign VAR39 = VAR6 & ~VAR18;
assign VAR1 = (VAR10 & ~VAR32) & (~VAR37);
assign VAR7 = VAR10 ? VAR20 : 5'd0;
assign VAR8 = VAR10 ? VAR26 : 64'd0;
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR30 <= 65'b0;
end
else if (VAR18 & !VAR30[65]) begin
VAR30 <= {1'b1, VAR19};
end
else if (!VAR18)
VAR30 <= 65'b0;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR17 <= 65'b0;
end
else if (VAR27 & !VAR17[65]) begin
VAR17 <= {1'b1, VAR9};
end
else if (!VAR27)
VAR17 <= 65'b0;
end
assign VAR36 = (VAR30[65]) ? VAR30 : VAR19;
assign VAR2 = (VAR17[65]) ? VAR17 : VAR9;
VAR15 VAR34(
.clk(clk),
.rst(rst),
.VAR24(VAR35),
.VAR16(VAR28),
.VAR21(VAR19),
.VAR3(VAR39),
.VAR22(VAR12),
.VAR5(VAR9),
.VAR14(VAR1),
.VAR33(VAR7),
.VAR31(VAR8)
);
endmodule | gpl-2.0 |
natsutan/NPU | fpga_implement/npu8/src/q_add8.v | 1,762 | module MODULE1
(
input VAR4,
input VAR8,
input VAR11,
input [7:0] VAR3,
input [7:0] VAR2,
output VAR25,
output [7:0] VAR17,
input [31:0] VAR18,
input [31:0] VAR7,
output reg [15:0] VAR12,
output reg [15:0] VAR15
);
wire [15:0] VAR19; reg [16:0] VAR26;
wire [24:0] VAR6;
reg [7:0] VAR21, VAR9, VAR1;
reg [VAR14-1:0] VAR23;
VAR5 VAR20(.VAR4, .VAR16(VAR2), .VAR22(VAR18[15:0]), .VAR10(VAR19));
always @ (posedge VAR4 or negedge VAR8)begin
if (VAR8 == 0) begin
VAR26 <= 25'h000000;
end else begin
VAR26 <= VAR19 + VAR1[7:0];
end
end
VAR13 VAR24(.VAR4(VAR4), .VAR16(VAR26[16:0]), .VAR22(VAR7), .VAR10(VAR6));
assign VAR17 = VAR6[7:0];
always @ (posedge VAR4 or negedge VAR8) begin
if(VAR8)begin
VAR12 <= 16'h7FFF;
VAR15 <= 0;
end else begin
if(VAR25)begin
if (VAR15 > VAR17) begin
VAR15 <= VAR17;
end
if (VAR12 < VAR17) begin
VAR12 <= VAR17;
end
end
end end
always @ (posedge VAR4 or negedge VAR8)begin
if (VAR8 == 0)begin
VAR23 <= 0;
VAR21 <= 0;
VAR9 <= 0;
VAR1 <= 0;
end else begin
VAR23 <= { VAR23[VAR14-2:0], VAR11};
VAR21 <= VAR3;
VAR9 <= VAR21;
VAR1 <= VAR9;
end
end
assign VAR25 = VAR23[VAR14-1];
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill_1.v | 1,848 | module MODULE2 (
VAR2,
VAR3,
VAR4 ,
VAR6
);
input VAR2;
input VAR3;
input VAR4 ;
input VAR6 ;
VAR5 VAR1 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR6 ;
VAR5 VAR1 ();
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.functional.pp.v | 1,168 | module MODULE1( VAR7, VAR6, VAR11, VAR9, VAR2 );
input VAR6, VAR7;
inout VAR9, VAR2;
output VAR11;
wire VAR12;
not VAR8( VAR12, VAR7 );
wire VAR4;
and VAR3( VAR4, VAR12, VAR6 );
wire VAR13;
not VAR14( VAR13, VAR6 );
wire VAR1;
and VAR5( VAR1, VAR13, VAR7 );
or VAR10( VAR11, VAR4, VAR1 );
endmodule | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.