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glennchid/font5-firmware | src/verilog/synthesis/MuxModule.v | 2,023 | module MODULE1(
input VAR16,
input [1:0] sel,
input signed [12:0] VAR12,
input signed [12:0] VAR11,
input signed [12:0] VAR3,
input signed [12:0] VAR19,
input signed [12:0] VAR17,
input signed [12:0] VAR13,
output reg signed [16:0] VAR6,
output reg signed [16:0] VAR7,
output reg signed [16:0] VAR20,
output reg signed [16:0] VAR9,
input clk,
input VAR18
);
wire signed [12:0] VAR14, VAR1, VAR8, VAR4;
reg signed [16:0] VAR10,VAR5,VAR2,VAR15; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcin/sky130_fd_sc_hs__fahcin.functional.v | 2,648 | module MODULE1 (
VAR2,
VAR21 ,
VAR16 ,
VAR13 ,
VAR4 ,
VAR24,
VAR5
);
output VAR2;
output VAR21 ;
input VAR16 ;
input VAR13 ;
input VAR4 ;
input VAR24;
input VAR5;
wire VAR8 ;
wire VAR6 ;
wire VAR12 ;
wire VAR1 ;
wire VAR10 ;
wire VAR26 ;
wire VAR11 ;
wire VAR22;
not VAR17 (VAR8 , VAR4 );
xor VAR3 (VAR6 , VAR16, VAR13, VAR8 );
VAR23 VAR9 (VAR12 , VAR6, VAR24, VAR5);
buf VAR14 (VAR21 , VAR12 );
and VAR18 (VAR1 , VAR16, VAR13 );
and VAR25 (VAR10 , VAR16, VAR8 );
and VAR7 (VAR26 , VAR13, VAR8 );
or VAR20 (VAR11 , VAR1, VAR10, VAR26 );
VAR23 VAR19 (VAR22, VAR11, VAR24, VAR5);
buf VAR15 (VAR2 , VAR22 );
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_ddr_dma_controller.v | 11,857 | module MODULE1(
input VAR9,
input VAR61,
input VAR66,
input VAR36,
output reg VAR30,
input VAR6,
input [31:0] VAR75,
input [31:0] VAR62,
output reg VAR43,
input VAR87,
output reg [11:0] VAR10,
output reg [31:0] VAR99,
output reg [7:0] VAR77,
input [7:0] VAR90,
input VAR52,
input [63:0] VAR92,
input VAR24,
output reg VAR37,
output reg [255:0]VAR76,
input [255:0]VAR15,
input VAR70,
input VAR17,
output reg [63:0] VAR65,
output VAR101,
output [10:0] VAR45,
output VAR47,
input VAR63,
input VAR83
);
parameter VAR22 = 'd0,
VAR88 = 'd1,
VAR26 = 'd2,
VAR7 = 'd3,
VAR56 = 'd4,
VAR25 = 'd5,
VAR91 = 'd6,
VAR1 = 'd7,
VAR71 = 'd8,
VAR58 = 'd9,
VAR3 = 'd10;
reg [3:0] state;
reg VAR12;
reg [31:0] VAR18;
reg [28:0] VAR80;
reg [31:0] VAR19;
reg [9:0] VAR31;
reg [9:0] VAR20;
reg [9:0] VAR28;
reg [9:0] VAR23;
reg [9:0] VAR86;
reg [9:0] VAR100;
reg [9:0] VAR57;
reg [9:0] VAR73;
reg VAR44;
reg VAR48;
wire VAR32;
wire VAR94;
wire [255:0] VAR74;
wire [255:0] VAR16;
wire [255:0] VAR46;
wire [255:0] VAR72;
wire VAR29;
wire VAR5;
wire VAR39;
wire VAR34;
reg VAR4;
reg VAR93;
reg VAR55;
reg VAR13;
reg VAR96;
reg VAR38;
reg VAR35;
reg VAR42;
reg VAR78;
reg VAR59;
reg VAR95;
reg VAR2;
reg [63:0] VAR85;
reg [255:0] VAR98;
reg [255:0] VAR82;
reg [255:0] VAR79;
reg [255:0] VAR67;
wire VAR97;
reg VAR54;
reg VAR49;
reg VAR14;
reg VAR69;
reg [3:0] VAR11;
wire VAR81;
wire[63:0] VAR8;
always @(posedge VAR9)
begin
if(VAR17)
VAR65 <= VAR8;
if(VAR52 & (VAR90 == 8'd0))
VAR54 <= 1'b1;
end
else
VAR54 <= 1'b0;
if(VAR52 & (VAR90 == 8'd1))
VAR49 <= 1'b1;
else
VAR49 <= 1'b0;
VAR85 <= VAR92;
end
assign VAR81 = VAR93 & VAR13;
always @
begin
case(VAR48)
1'b0:begin
VAR76 <= VAR98;
VAR37 <= VAR29;
end
1'b1:begin
VAR76 <= VAR82;
VAR37 <= VAR5;
end
endcase
end
always @(posedge VAR61)
begin
if(VAR11[0])
VAR98 <= VAR74;
if(VAR11[1])
VAR82 <= VAR16;
end
always @(posedge VAR9)
begin
if(!VAR66)
begin
state <= VAR22;
VAR43 <= 1'b0;
VAR30 <= 1'b0;
VAR12 <= 1'b0;
VAR78 <= 1'b1;
VAR59 <= 1'b1;
VAR95 <= 1'b1;
VAR2 <= 1'b1;
end
else
begin
case(state)
VAR22:begin
VAR30 <= 1'b0;
VAR12 <= 1'b0;
VAR44 <= 1'b1;
VAR19 <= VAR62;
VAR99 <= VAR75;
VAR18 <= VAR62;
VAR31 <= 10'd0;
VAR20 <= 10'd0;
VAR28 <= 10'd0;
VAR23 <= 10'd0;
VAR78 <= 1'b0;
VAR59 <= 1'b0;
VAR95 <= 1'b0;
VAR2 <= 1'b0;
if(VAR36) begin
state <= VAR88;
end
end
VAR88:begin
VAR44 <= 1'b0;
if((VAR86 >= VAR31) & VAR93) begin
state <= VAR26;
VAR43 <= 1'b1;
VAR77 <= 8'd0;
VAR78 <= 1'b1; if(VAR18 <= 'd4096)
begin
VAR10 <= VAR18[11:0];
VAR12 <= 1'b1;
end
else
begin
VAR10 <= 0;
VAR31 <= 10'd512;
end
end
end
VAR26:begin
VAR78 <= 1'b0;
if(VAR87)
begin
VAR43 <= 1'b0;
if(VAR12) begin
state <= VAR58;
end
else
begin
state <= VAR7;
VAR18 <= VAR18 - 'd4096;
VAR99 <= VAR99 + 'd4096;
end
end
end
VAR7:begin
if((VAR100 >= VAR20) & VAR13) begin
state <= VAR56;
VAR43 <= 1'b1;
VAR77 <= 8'd1;
VAR59 <= 1'b1; if(VAR18 <= 'd4096)
begin
VAR10 <= VAR18[11:0];
VAR12 <= 1'b1;
end
else
begin
VAR10 <= 0;
VAR20 <= 10'd512;
end
end
end
VAR56:begin
VAR59 <= 1'b0;
if(VAR87)
begin
VAR43 <= 1'b0;
if(VAR12) begin
state <= VAR58;
end
else
begin
state <= VAR88; VAR18 <= VAR18 - 'd4096;
VAR99 <= VAR99 + 'd4096;
end
end
end
VAR58:begin
if(VAR80 >= VAR19[31:3]) begin
VAR30 <= 1'b1;
end
if(~VAR36 & VAR6)
begin
state <= VAR3;
VAR30 <= 1'b0;
end
end
VAR3:begin
if(VAR81)
begin
VAR44 <= 1'b1;
VAR78 <= 1'b1;
VAR59 <= 1'b1;
VAR95 <= 1'b1;
VAR2 <= 1'b1;
state <= VAR22;
end
end
endcase
end
end
always @(posedge VAR9)
begin
if(!VAR66)
VAR80 <= 0;
end
else
begin
if(VAR44)
VAR80 <= 0;
end
else if(VAR54|VAR49)
VAR80 <= VAR80 + 1'd1;
end
end
always @(posedge VAR9)
begin
if(!VAR66)
VAR86 <= 0;
end
else
begin
if(VAR78)
VAR86 <= 0;
end
else if(VAR54)
VAR86 <= VAR86 + 1'd1;
end
end
always @(posedge VAR9)
begin
if(!VAR66)
VAR100 <= 0;
end
else
begin
if(VAR59)
VAR100 <= 0;
end
else if(VAR49)
VAR100 <= VAR100 + 1'd1;
end
end
always @(posedge VAR61)
begin
if(VAR63)
VAR48 <= 1'b0;
end
else if(VAR83)
VAR48 <= VAR48 + 1'b1;;
end
always @(posedge VAR9)
begin
VAR4 <= VAR29;
VAR93 <= VAR4;
VAR55 <= VAR5;
VAR13 <= VAR55;
end
VAR41 VAR40(
.rst(~VAR66),
.VAR84(VAR9),
.VAR33(VAR61),
.din(VAR85),
.VAR51(VAR54),
.VAR68(VAR11[0]),
.dout(VAR74), .VAR64(), .VAR53(VAR29)
);
VAR41 VAR89(
.rst(~VAR66),
.VAR84(VAR9),
.VAR33(VAR61),
.din(VAR85),
.VAR51(VAR49),
.VAR68(VAR11[1]),
.dout(VAR16), .VAR64(), .VAR53(VAR5) );
VAR60 VAR50 (
.rst(~VAR66),
.VAR84(VAR61),
.VAR33(VAR9),
.din(VAR15),
.VAR51(VAR70),
.VAR68(VAR17),
.dout(VAR8),
.VAR64(),
.VAR53(VAR101),
.VAR27(VAR45),
.VAR21(VAR47)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxbp/sky130_fd_sc_ms__dfxbp.symbol.v | 1,338 | module MODULE1 (
input VAR5 ,
output VAR8 ,
output VAR3,
input VAR1
);
supply1 VAR4;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b.behavioral.pp.v | 1,895 | module MODULE1 (
VAR5,
VAR6,
VAR9 ,
VAR4 ,
VAR11 ,
VAR1 ,
VAR10
);
input VAR5;
input VAR6;
output VAR9 ;
input VAR4 ;
input VAR11 ;
input VAR1 ;
input VAR10 ;
wire VAR10 VAR7 ;
wire VAR13 ;
wire VAR3;
not VAR14 (VAR7 , VAR4 );
nand VAR15 (VAR13 , VAR10, VAR1, VAR11, VAR7 );
VAR12 VAR8 (VAR3, VAR13, VAR5, VAR6);
buf VAR2 (VAR9 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a.pp.symbol.v | 1,367 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR2 ,
input VAR5 ,
input VAR8 ,
output VAR6 ,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_rp/bg_rp_stub.v | 1,258 | module MODULE1(VAR5, VAR4, VAR3, VAR2, VAR1)
;
input VAR5;
input [0:0]VAR4;
input [7:0]VAR3;
input [11:0]VAR2;
output [11:0]VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbn/sky130_fd_sc_hd__dlxbn_2.v | 2,312 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR10 ,
VAR9,
VAR5 ,
VAR7 ,
VAR4 ,
VAR2
);
output VAR6 ;
output VAR1 ;
input VAR10 ;
input VAR9;
input VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
VAR8 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6 ,
VAR1 ,
VAR10 ,
VAR9
);
output VAR6 ;
output VAR1 ;
input VAR10 ;
input VAR9;
supply1 VAR5;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR2 ;
VAR8 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_dds_2.v | 5,250 | module MODULE1 #(
parameter VAR16 = 16,
parameter VAR10 = 16,
parameter VAR2 = 1,
parameter VAR28 = 16,
parameter VAR23 = 16) (
input clk,
input VAR14,
input [VAR10-1:0] VAR6,
input [ 15:0] VAR5,
input [VAR10-1:0] VAR9,
input [ 15:0] VAR4,
output [ VAR16-1:0] VAR31);
localparam VAR29 = 1;
localparam VAR18 = 2;
localparam VAR12 = (VAR2 == VAR29) ? VAR28 : 16;
localparam VAR3 = (VAR2 == VAR29) ? VAR23 : 16;
localparam VAR8 = (VAR12 > VAR16) ? (VAR12 - VAR16) : (VAR16 - VAR12);
reg [ VAR16-1:0] VAR26 = 0;
reg [VAR12-1:0] VAR13 = 0;
reg [VAR12-1:0] VAR17 = 0;
reg [ 15:0] VAR22 = 0;
reg [ 15:0] VAR15 = 0;
reg [ VAR16-1:0] VAR21 = 0;
wire [VAR12-1:0] VAR25;
wire [VAR12-1:0] VAR11;
wire [VAR3-1:0] VAR27;
wire [VAR3-1:0] VAR19;
generate
assign VAR31 = VAR21;
always @(posedge clk) begin
VAR21[VAR16-1] <= VAR26[VAR16-1] ^ VAR14;
VAR21[VAR16-2: 0] <= VAR26[VAR16-2: 0];
end
always @(posedge clk) begin
if (VAR16 < VAR12) begin VAR13 <= VAR17 + {(VAR8){VAR17[VAR12-1]}};
VAR26 <= VAR13[VAR12-1:VAR12-VAR16];
end else begin VAR26 <= VAR17 << VAR8;
end
end
always @(posedge clk) begin
VAR17 <= VAR25 + VAR11;
end
always @(posedge clk) begin
VAR22 <= VAR5;
VAR15 <= VAR4;
end
if (VAR3 > VAR10) begin
assign VAR27 = {VAR6,{VAR3-VAR10{1'b0}}};
assign VAR19 = {VAR9,{VAR3-VAR10{1'b0}}};
end else begin
assign VAR27 = VAR6[(VAR10-1):VAR10-VAR3];
assign VAR19 = VAR9[(VAR10-1):VAR10-VAR3];
end
VAR30 #(
.VAR2(VAR2),
.VAR12(VAR12),
.VAR3(VAR3))
VAR7 (
.clk (clk),
.VAR1 (VAR27),
.VAR24 (VAR22),
.VAR31 (VAR25));
VAR30 #(
.VAR2(VAR2),
.VAR12(VAR12),
.VAR3(VAR3))
VAR20 (
.clk (clk),
.VAR1 (VAR19),
.VAR24 (VAR15),
.VAR31 (VAR11));
endgenerate
endmodule | mit |
oceanborn-mx/sirius | src.verilog/Multiplicacion_Matricial_2DMesh/Multiplicacion_Matricial_2DMesh/src/arreglo_2dmesh.v | 1,028 | module MODULE1 (
input VAR16, input VAR1, input[3:0] VAR30,VAR31, input[3:0] VAR10,VAR8, input VAR21, input VAR24, input[3:0] VAR12, input[3:0] VAR18, output[7:0] VAR4,VAR29, output[7:0] VAR25,VAR27
);
wire[3:0] VAR17,VAR19,VAR9;
wire[3:0] VAR3,VAR32,VAR11;
VAR5 VAR6(VAR16,VAR1,VAR12[0],VAR18[0],VAR30,VAR10,VAR4);
VAR7 VAR13(VAR16,VAR1,VAR21,VAR30,VAR17);
VAR7 VAR22(VAR16,VAR1,VAR21,VAR8,VAR3);
VAR5 VAR14(VAR16,VAR1,VAR12[1],VAR18[1],VAR17,VAR3,VAR29);
VAR7 VAR26(VAR16,VAR1,VAR21,VAR31,VAR19);
VAR7 VAR23(VAR16,VAR1,VAR21,VAR10,VAR32);
VAR5 VAR15(VAR16,VAR1,VAR12[2],VAR18[2],VAR19,VAR32,VAR25);
VAR7 VAR28(VAR16,VAR1,VAR24,VAR19,VAR9);
VAR7 VAR20(VAR16,VAR1,VAR24,VAR3,VAR11);
VAR5 VAR2(VAR16,VAR1,VAR12[3],VAR18[3],VAR9,VAR11,VAR27);
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a.pp.symbol.v | 1,368 | module MODULE1 (
input VAR7 ,
input VAR9 ,
input VAR5 ,
input VAR3 ,
output VAR2 ,
input VAR1 ,
input VAR4,
input VAR6,
input VAR8
);
endmodule | apache-2.0 |
em15-10122510310-dongxinyue/Em15_310_dongxinyue_lab1 | lab1/lab1/lab1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/processing_system7_bfm_v2_0_regc.v | 2,173 | module MODULE1(
VAR18,
VAR10,
VAR27,
VAR37,
VAR16,
VAR39,
VAR12,
VAR3,
VAR26,
VAR42,
VAR31,
VAR9,
VAR4,
VAR23
);
input VAR18;
input VAR10;
input VAR27;
output VAR37;
input[31:0] VAR16;
output[1023:0] VAR39;
input[7:0] VAR12;
input [3:0] VAR3;
input VAR26;
output VAR42;
input[31:0] VAR31;
output[1023:0] VAR9;
input[7:0] VAR4;
input[3:0] VAR23;
wire [3:0] VAR5;
reg [1023:0] VAR28;
wire [31:0] VAR22;
wire [7:0] VAR19;
reg VAR33;
wire VAR14;
VAR7 VAR13 (
.VAR18(VAR18),
.VAR10(VAR10),
.VAR24(VAR3),
.VAR15(VAR23),
.VAR30(VAR27),
.VAR8(VAR26),
.VAR2(VAR39),
.VAR34(VAR9),
.VAR36(VAR16),
.VAR17(VAR31),
.VAR43(VAR12),
.VAR38(VAR4),
.VAR41(VAR37),
.VAR20(VAR42),
.VAR1(VAR5),
.VAR6(VAR14),
.VAR32(VAR28),
.VAR11(VAR22),
.VAR35(VAR19),
.VAR25(VAR33)
);
VAR21 VAR40();
reg state;
always@(posedge VAR10 or negedge VAR18)
begin
if(!VAR18) begin
VAR33 <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
VAR33 <= 0;
if(VAR14) begin
VAR40.VAR29(VAR28,VAR22, VAR19);
VAR33 <= 1;
state <= 1;
end
end
1:begin
VAR33 <= 0;
state <= 0;
end
endcase
end end
endmodule | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_lpddr2_addr_cmd.v | 16,892 | module MODULE1
VAR27 = 1,
VAR23 = 1,
VAR16 = 1, VAR40 = 20,
VAR48 = 15, VAR17 = 12, VAR49 = 3, VAR26 = 2
)
(
VAR28,
VAR29,
VAR1,
VAR25,
VAR36,
VAR20,
VAR9,
VAR51,
VAR44,
VAR15,
VAR53,
VAR19,
VAR8,
VAR7,
VAR52,
VAR38, VAR47, VAR55, VAR24,
VAR43, VAR12,
VAR2,
VAR45,
VAR42,
VAR21,
VAR13,
VAR4,
VAR37,
VAR32
);
input VAR28;
input VAR29;
input VAR1;
input [VAR27 -1:0] VAR25;
input VAR36;
input VAR20;
input VAR9;
input VAR51;
input VAR44;
input VAR15;
input [VAR23-1:0] VAR53;
input [VAR23-1:0] VAR19;
input [VAR23-1:0] VAR8;
input [VAR23-1:0] VAR7;
input [VAR23-1:0] VAR24;
input VAR52;
input VAR38;
input VAR47;
input VAR55;
input [VAR23-1:0] VAR43;
input [VAR49-1:0] VAR12;
input [VAR48-1:0] VAR2;
input [VAR17-1:0] VAR45;
input [7:0] VAR42;
input [7:0] VAR21;
output [(VAR16 * (VAR26/2)) - 1:0] VAR13;
output [(VAR23 * (VAR26/2)) - 1:0] VAR4;
output [(VAR40 * (VAR26/2)) - 1:0] VAR37;
output [(VAR26/2) - 1:0] VAR32;
wire VAR20;
wire VAR9;
wire VAR51;
wire VAR44;
wire VAR15;
wire [VAR23-1:0] VAR53;
wire [VAR23-1:0] VAR19;
wire [VAR23-1:0] VAR8;
wire [VAR23-1:0] VAR7;
wire [VAR23-1:0] VAR24;
wire VAR52;
wire VAR38;
wire VAR47;
wire VAR55;
reg [2:0] VAR5;
reg [14:0] VAR30;
reg [11:0] VAR22;
wire [(VAR16 * (VAR26/2)) - 1:0] VAR13;
wire [(VAR23 * (VAR26/2)) - 1:0] VAR4;
wire [(VAR40 * (VAR26/2)) - 1:0] VAR37;
wire [(VAR26/2) - 1:0] VAR32;
reg [(VAR16) - 1:0] VAR56;
reg [(VAR16) - 1:0] VAR31;
reg [(VAR23) - 1:0] VAR41;
reg [(VAR40) - 1:0] VAR54;
reg [(VAR16) - 1:0] VAR6;
reg [(VAR23) - 1:0] VAR14;
reg [(VAR40) - 1:0] VAR34;
reg [(VAR16) - 1:0] VAR10;
reg [(VAR23) - 1:0] VAR50;
reg [(VAR40) - 1:0] VAR46;
reg [VAR23 - 1:0] VAR35;
reg [VAR23 - 1:0] VAR33;
reg [VAR23 - 1:0] VAR11;
reg [VAR23 - 1:0] VAR39;
reg [VAR23 - 1:0] VAR18;
reg [VAR23 - 1:0] VAR3;
assign VAR32 = {(VAR26/2){1'b1}};
generate
if (VAR26 == 2) begin
assign VAR13 = VAR56;
assign VAR4 = VAR41;
assign VAR37 = VAR54;
end
else begin
assign VAR13 = {VAR56,VAR56};
assign VAR4 = (VAR55)? {VAR41,VAR41} :{VAR41,{VAR23{1'b1}}};
assign VAR37 = {VAR54,VAR54};
end
endgenerate
always @(posedge VAR28, negedge VAR29) begin
if (!VAR29)
begin
VAR35 <= {(VAR23){1'b0}};
VAR33 <= {(VAR23){1'b0}};
VAR11 <= {(VAR23){1'b0}};
end
else
begin
VAR35 <= ~VAR7;
VAR33 <= ~VAR8;
VAR11 <= ~VAR24;
end
end
always @
begin
if (VAR25)
begin
VAR56 = VAR10;
VAR41 = VAR50;
VAR54 = VAR46;
end
else
begin
VAR56 = VAR6;
VAR41 = VAR14;
VAR54 = VAR34;
end
end
always @
begin
if (VAR1)
begin
VAR6 = ~(VAR8 | VAR7 | VAR24);
end
else
begin
VAR6 = {(VAR16){1'b1}};
end
end
always @(*)
begin
if (VAR1)
begin
VAR14 = {(VAR23){1'b1}};
VAR34 = {(VAR40){1'b0}};
if (|VAR19)
begin
VAR14 = ~VAR19;
VAR34[3:0] = 4'b1100;
VAR34[(VAR40/2) - 1 : 4] = {(VAR40/2 - 4){1'b0}};
VAR34[VAR40 - 1 : 10] = {(VAR40/2){1'b0}};
end
if (VAR47)
begin
VAR14 = ~VAR43;
VAR34[3:0] = 4'b0100;
VAR34[(VAR40/2) - 1 : 4] = {(VAR40/2 - 4){1'b0}};
VAR34[VAR40 - 1 : 10] = {(VAR40/2){1'b0}};
end
if (|VAR53)
begin
VAR14 = ~VAR53;
VAR34[3:0] = 4'b1011;
VAR34[(VAR40/2) - 1 : 4] = {VAR5,2'b00,(|VAR53)};
VAR34[VAR40 - 1 : 10] = {(VAR40/2){1'b0}};
end
if (VAR44)
begin
VAR14 = ~VAR43;
VAR34[3:0] = {VAR30[9:8],2'b10};
VAR34[(VAR40/2) - 1 : 4] = {VAR5,VAR30[12:10]};
VAR34[VAR40 - 1 : 10] = {VAR30[14:13],VAR30[7:0]};
end
if (VAR15)
begin
VAR14 = ~VAR43;
VAR34[3:0] = 4'b1011;
VAR34[(VAR40/2) - 1 : 4] = {VAR5,3'b000};
VAR34[VAR40 - 1 : 10] = {VAR30[14:13],VAR30[7:0]};
end
if (VAR20)
begin
VAR14 = ~VAR43;
VAR34[3:0] = 4'b0001;
VAR34[(VAR40/2) - 1 : 4] = {VAR5,VAR22[2:1],1'b0};
VAR34[VAR40 - 1 : 10] = {VAR22[11:3],VAR51};
end
if (VAR9)
begin
VAR14 = ~VAR43;
VAR34[3:0] = 4'b0101;
VAR34[(VAR40/2) - 1 : 4] = {VAR5,VAR22[2:1],1'b0};
VAR34[VAR40 - 1 : 10] = {VAR22[11:3],VAR51};
end
if (|VAR39)
begin
VAR14 = {(VAR23){1'b1}};
VAR34[3:0] = 4'b0000;
VAR34[(VAR40/2) - 1 : 4] = {(VAR40/2 - 4){1'b0}};
VAR34[VAR40 - 1 : 10] = {(VAR40/2){1'b0}};
end
if (|VAR3)
begin
if (VAR36)
begin
VAR14 = ~VAR3; end
else
begin
VAR14 = {(VAR23){1'b1}};
end
VAR34[3:0] = 4'b0011;
VAR34[(VAR40/2) - 1 : 4] = {(VAR40/2 - 4){1'b0}};
VAR34[VAR40 - 1 : 10] = {(VAR40/2){1'b0}};
end
if (|VAR18)
begin
if (VAR36)
begin
VAR14 = ~VAR18; end
else
begin
VAR14 = {(VAR23){1'b1}};
end
VAR34[3:0] = 4'b0100;
VAR34[(VAR40/2) - 1 : 4] = {(VAR40/2 - 4){1'b0}};
VAR34[VAR40 - 1 : 10] = {(VAR40/2){1'b0}};
end
if (VAR52)
begin
VAR14 = ~VAR43;
VAR34[3:0] = 4'b0000;
VAR34[(VAR40/2) - 1 : 4] = VAR42[5:0];
VAR34[VAR40 - 1 : 10] = {VAR42[7:6],VAR21};
end
if (VAR38)
begin
VAR14 = ~VAR43;
VAR34[3:0] = 4'b1000;
VAR34[(VAR40/2) - 1 : 4] = VAR42[5:0];
VAR34[VAR40 - 1 : 10] = {VAR42[7:6],{8{1'b0}}};
end
if (VAR55)
begin
VAR14 = ~VAR43;
VAR34[3:0] = 4'b0011;
VAR34[(VAR40/2) - 1 : 4] = {(VAR40/2 - 4){1'b0}};
VAR34[VAR40 - 1 : 10] = {(VAR40/2){1'b0}};
end
end
else
begin
VAR14 = {(VAR23){1'b1}};
VAR34 = {(VAR40){1'b0}};
end
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr.symbol.v | 1,370 | module MODULE1 (
input VAR6,
output VAR1
);
supply1 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_hdmi_tx.v | 12,771 | module MODULE1 (
VAR84,
VAR85,
VAR63,
VAR41,
VAR1,
VAR14,
VAR32,
VAR49,
VAR18,
VAR86,
VAR56,
VAR69,
VAR33,
VAR8,
VAR39,
VAR15,
VAR19,
VAR50,
VAR35,
VAR12,
VAR4,
VAR45,
VAR24,
VAR38,
VAR25,
VAR81,
VAR22,
VAR70,
VAR48,
VAR57,
VAR87,
VAR3,
VAR51,
VAR76,
VAR68);
localparam VAR78 = 32'h00040063;
parameter VAR17 = 0;
input VAR84;
output VAR85;
output VAR63;
output VAR41;
output VAR1;
output [ 1:0] VAR14;
output [23:0] VAR32;
output [15:0] VAR49;
output [15:0] VAR18;
output [15:0] VAR86;
output [15:0] VAR56;
output [15:0] VAR69;
output [15:0] VAR33;
output [15:0] VAR8;
output [15:0] VAR39;
output [15:0] VAR15;
output [15:0] VAR19;
input VAR50;
input VAR35;
input [31:0] VAR12;
input VAR4;
output VAR45;
input VAR24;
input VAR38;
input VAR25;
input VAR81;
input VAR22;
input VAR70;
input [13:0] VAR48;
input [31:0] VAR57;
output VAR87;
input VAR3;
input [13:0] VAR51;
output [31:0] VAR76;
output VAR68;
reg VAR87 = 'd0;
reg [31:0] VAR54 = 'd0;
reg VAR47 = 'd0;
reg VAR62 = 'd0;
reg VAR46 = 'd0;
reg VAR27 = 'd0;
reg [ 1:0] VAR11 = 'd1;
reg [23:0] VAR44 = 'd0;
reg VAR7 = 'd0;
reg VAR2 = 'd0;
reg VAR16 = 'd0;
reg VAR55 = 'd0;
reg [15:0] VAR28 = 'd0;
reg [15:0] VAR82 = 'd0;
reg [15:0] VAR83 = 'd0;
reg [15:0] VAR42 = 'd0;
reg [15:0] VAR13 = 'd0;
reg [15:0] VAR20 = 'd0;
reg [15:0] VAR75 = 'd0;
reg [15:0] VAR66 = 'd0;
reg [15:0] VAR74 = 'd0;
reg [15:0] VAR43 = 'd0;
reg VAR68 = 'd0;
reg [31:0] VAR76 = 'd0;
wire VAR58;
wire VAR80;
wire VAR72;
wire VAR65;
wire VAR53;
wire [31:0] VAR40;
wire VAR5;
wire VAR64;
wire VAR6;
assign VAR58 = (VAR48[13:12] == 2'd0) ? VAR70 : 1'b0;
assign VAR80 = (VAR51[13:12] == 2'd0) ? VAR3 : 1'b0;
assign VAR72 = ~VAR47;
always @(negedge VAR81 or posedge VAR22) begin
if (VAR81 == 0) begin
VAR87 <= 'd0;
VAR54 <= 'd0;
VAR47 <= 'd0;
VAR62 <= 'd0;
VAR46 <= 'd0;
VAR27 <= 'd0;
VAR11 <= 'd1;
VAR44 <= 'd0;
VAR7 <= 'd0;
VAR2 <= 'd0;
VAR16 <= 'd0;
VAR55 <= 'd0;
VAR28 <= 'd0;
VAR82 <= 'd0;
VAR83 <= 'd0;
VAR42 <= 'd0;
VAR13 <= 'd0;
VAR20 <= 'd0;
VAR75 <= 'd0;
VAR66 <= 'd0;
VAR74 <= 'd0;
VAR43 <= 'd0;
end else begin
VAR87 <= VAR58;
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h002)) begin
VAR54 <= VAR57;
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h010)) begin
VAR47 <= VAR57[0];
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h011)) begin
VAR27 <= VAR57[2];
VAR62 <= VAR57[1];
VAR46 <= VAR57[0];
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h012)) begin
VAR11 <= VAR57[1:0];
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h013)) begin
VAR44 <= VAR57[23:0];
end
if (VAR5 == 1'b1) begin
VAR7 <= 1'b1;
end else if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h018)) begin
VAR7 <= VAR7 & ~VAR57[1];
end
if (VAR64 == 1'b1) begin
VAR2 <= 1'b1;
end else if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h018)) begin
VAR2 <= VAR2 & ~VAR57[0];
end
if (VAR53 == 1'b1) begin
VAR16 <= 1'b1;
end else if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h019)) begin
VAR16 <= VAR16 & ~VAR57[1];
end
if (VAR6 == 1'b1) begin
VAR55 <= 1'b1;
end else if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h019)) begin
VAR55 <= VAR55 & ~VAR57[0];
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h100)) begin
VAR28 <= VAR57[31:16];
VAR82 <= VAR57[15:0];
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h101)) begin
VAR83 <= VAR57[15:0];
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h102)) begin
VAR42 <= VAR57[31:16];
VAR13 <= VAR57[15:0];
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h110)) begin
VAR20 <= VAR57[31:16];
VAR75 <= VAR57[15:0];
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h111)) begin
VAR66 <= VAR57[15:0];
end
if ((VAR58 == 1'b1) && (VAR48[11:0] == 12'h112)) begin
VAR74 <= VAR57[31:16];
VAR43 <= VAR57[15:0];
end
end
end
always @(negedge VAR81 or posedge VAR22) begin
if (VAR81 == 0) begin
VAR68 <= 'd0;
VAR76 <= 'd0;
end else begin
VAR68 <= VAR80;
if (VAR80 == 1'b1) begin
case (VAR51[11:0])
12'h000: VAR76 <= VAR78;
12'h001: VAR76 <= VAR17;
12'h002: VAR76 <= VAR54;
12'h010: VAR76 <= {31'd0, VAR47};
12'h011: VAR76 <= {29'd0, VAR27, VAR62, VAR46};
12'h012: VAR76 <= {30'd0, VAR11};
12'h013: VAR76 <= {8'd0, VAR44};
12'h015: VAR76 <= VAR40;
12'h016: VAR76 <= VAR12;
12'h017: VAR76 <= {31'd0, VAR65};
12'h018: VAR76 <= {30'd0, VAR7, VAR2};
12'h019: VAR76 <= {30'd0, VAR16, VAR55};
12'h100: VAR76 <= {VAR28, VAR82};
12'h101: VAR76 <= {16'd0, VAR83};
12'h102: VAR76 <= {VAR42, VAR13};
12'h110: VAR76 <= {VAR20, VAR75};
12'h111: VAR76 <= {16'd0, VAR66};
12'h112: VAR76 <= {VAR74, VAR43};
default: VAR76 <= 0;
endcase
end else begin
VAR76 <= 32'd0;
end
end
end
VAR73 VAR67 (.VAR59(VAR72), .clk(VAR84), .rst(VAR85));
VAR73 VAR71 (.VAR59(VAR72), .clk(VAR4), .rst(VAR45));
VAR77 #(.VAR21(189)) VAR26 (
.VAR81 (VAR81),
.VAR22 (VAR22),
.VAR52 ({ VAR27,
VAR62,
VAR46,
VAR11,
VAR44,
VAR28,
VAR82,
VAR83,
VAR42,
VAR13,
VAR20,
VAR75,
VAR66,
VAR74,
VAR43}),
.VAR9 (),
.VAR23 (VAR85),
.VAR37 (VAR84),
.VAR10 ({ VAR1,
VAR63,
VAR41,
VAR14,
VAR32,
VAR49,
VAR18,
VAR86,
VAR56,
VAR69,
VAR33,
VAR8,
VAR39,
VAR15,
VAR19}));
VAR36 #(.VAR21(2)) VAR79 (
.VAR81 (VAR81),
.VAR22 (VAR22),
.VAR29 ({VAR65,
VAR53}),
.VAR23 (VAR85),
.VAR37 (VAR84),
.VAR31 ({ VAR50,
VAR35}));
VAR34 VAR61 (
.VAR81 (VAR81),
.VAR22 (VAR22),
.VAR60 (VAR40),
.VAR23 (VAR85),
.VAR37 (VAR84));
VAR36 #(.VAR21(3)) VAR30 (
.VAR81 (VAR81),
.VAR22 (VAR22),
.VAR29 ({VAR5,
VAR64,
VAR6}),
.VAR23 (VAR85),
.VAR37 (VAR84),
.VAR31 ({ VAR24,
VAR38,
VAR25}));
endmodule | gpl-3.0 |
joaocarlos/udlx-verilog | rtl/decode/signal_extend.v | 1,816 | module MODULE1
parameter VAR2 = 32,
parameter VAR3 = 16
)(
input [VAR3-1:0] VAR1,
output [VAR2-1:0] VAR4
);
assign VAR4 = {{(VAR2-VAR3){VAR1[VAR3-1]}},VAR1};
endmodule | lgpl-3.0 |
Team-Jared/tera-computer | src/registers.v | 2,368 | module MODULE1 (VAR24, VAR4, VAR3, VAR25, VAR8, VAR2, VAR23, VAR6);
output [7:0] VAR24, VAR4;
input [7:0] VAR3, VAR25;
input [3:0] VAR8;
input VAR2, VAR23, VAR6;
reg [7:0] VAR15 [0:15];
wire [7:0] VAR16, VAR5, VAR21, VAR10, VAR1, VAR9, VAR19, VAR18, VAR7, VAR20, VAR11, VAR17, VAR12, VAR22, VAR13;
assign VAR16 = VAR15[1]; assign VAR5 = VAR15[9]; assign VAR21 = VAR15[11]; assign VAR10 = VAR15[12]; assign VAR1 = VAR15[2]; assign VAR9 = VAR15[3]; assign VAR19 = VAR15[4]; assign VAR18 = VAR15[5]; assign VAR7 = VAR15[6]; assign VAR20 = VAR15[7]; assign VAR11 = VAR15[8]; assign VAR17 = VAR15[10]; assign VAR12 = VAR15[13]; assign VAR22 = VAR15[14]; assign VAR13 = VAR15[15];
integer VAR14;
assign VAR24 = VAR15[VAR3[7:4]];
assign VAR4 = VAR15[VAR3[3:0]]; | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_add_double_ll.v | 1,515 | module MODULE1 (
VAR1,
VAR6,
VAR10,
VAR9,
VAR11,
enable);
input enable;
input VAR1, VAR6;
input [63:0] VAR10;
input [63:0] VAR9;
output [63:0] VAR11;
VAR14 VAR8(
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR13(),
.VAR3(),
.VAR7(),
.VAR15(),
.enable(enable));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi_0.v | 2,332 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR6 ,
VAR7,
VAR9,
VAR2,
VAR5 ,
VAR10
);
output VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR7;
input VAR9;
input VAR2;
input VAR5 ;
input VAR10 ;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR4 ,
VAR8 ,
VAR6 ,
VAR7
);
output VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR7;
supply1 VAR9;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR10 ;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbn/sky130_fd_sc_hs__dlxbn.blackbox.v | 1,303 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR4 ,
VAR2
);
output VAR3 ;
output VAR6 ;
input VAR4 ;
input VAR2;
supply1 VAR1;
supply0 VAR5;
endmodule | apache-2.0 |
hakehuang/pycpld | ips/ip/spi_master/spi_master.v | 5,939 | module MODULE1(
clk,VAR22,
VAR3,VAR17,VAR6,
VAR1,VAR5,VAR15,VAR9,VAR21,VAR4
);
input clk;
input VAR22;
input VAR3;
output VAR17;
output VAR6;
input VAR1;
output VAR15;
output VAR4;
input VAR5;
input VAR9;
input VAR21;
reg[7:0] VAR18;
reg[7:0] VAR19;
reg[7:0] VAR13;
reg[4:0] VAR7;
reg VAR11;
reg VAR10;
reg VAR20;
reg VAR4;
reg[7:0] VAR14;
reg[7:0] VAR2;
wire[7:0] VAR12;
wire[4:0] VAR8;
wire[4:0] VAR16;
assign VAR8 = VAR9 ? 5'd18 : 5'd17;
assign VAR16 = VAR9 ? 5'd1 : 5'd0;
always @(posedge clk or negedge VAR22) begin
if(!VAR22) begin
VAR7 <= 5'd0;
VAR18 <= 8'h0;
VAR13 <= 8'h0;
VAR19 <= 8'h0;
end
else if((VAR1 || VAR5) && ((VAR18 < 8'd64) )) begin
if(VAR7 < VAR8)
VAR7 <= VAR7+1'b1;
end
else begin
if(VAR1 && VAR5 && VAR24 == 1'b1) begin
VAR7 <= 5'd0;
VAR18 <= VAR18 + 1'b1;
VAR13 <= VAR13 + 1'b1;
VAR19 <= (VAR12 == VAR18) ? (VAR19+1'b1) : VAR19;
end
else begin
if(VAR1 && VAR24 == 1'b1) begin
VAR7 <= 5'd0;
VAR18 <= VAR18 + 1'b1;
VAR13 <= VAR13 + 1'b1;
end
else if(VAR24 == 1'b1)begin
VAR7 <= 5'd0;
VAR18 <= VAR18 + 1'b1;
VAR19 <= (VAR12 == VAR18) ? (VAR19+1'b1) : VAR19;
end
end
end
end
else begin
VAR7 <= 5'd0;
VAR18 <= VAR18;
end
end
always @(posedge clk or negedge VAR22) begin
if(!VAR22)
VAR11 <= VAR21 ? 1'b1 : 1'b0;
end
else if(VAR7 > VAR16 && VAR7 < VAR8)
VAR11 <= ~VAR11;
else
VAR11 <= VAR11;
end
assign VAR6 = VAR11;
always @(posedge clk or negedge VAR22) begin
if(!VAR22)
VAR10 <= 1'b1;
end
else if(VAR1) begin
case(VAR7[4:1])
4'd0: VAR10 <= VAR13[7];
4'd1: VAR10 <= VAR13[6];
4'd2: VAR10 <= VAR13[5];
4'd3: VAR10 <= VAR13[4];
4'd4: VAR10 <= VAR13[3];
4'd5: VAR10 <= VAR13[2];
4'd6: VAR10 <= VAR13[1];
4'd7: VAR10 <= VAR13[0];
default: VAR10 <= 1'b1;
endcase
end
else
VAR10 <= 1'b1;
end
always @(posedge clk or negedge VAR22) begin
if(!VAR22)
VAR20 <= 1'b1;
end
else if(VAR1) begin
case(VAR7[4:1])
4'd1: VAR20 <= VAR13[7];
4'd2: VAR20 <= VAR13[6];
4'd3: VAR20 <= VAR13[5];
4'd4: VAR20 <= VAR13[4];
4'd5: VAR20 <= VAR13[3];
4'd6: VAR20 <= VAR13[2];
4'd7: VAR20 <= VAR13[1];
4'd8: VAR20 <= VAR13[0];
default: VAR20 <= 1'b1;
endcase
end
else
VAR20 <= 1'b1;
end
assign VAR17 = VAR9 ? VAR20 : VAR10;
always @(posedge clk or negedge VAR22) begin
if(!VAR22)
VAR14 <= 8'hff;
end
else if(VAR5) begin
case(VAR7)
5'd1: VAR14[7] <= VAR3;
5'd3: VAR14[6] <= VAR3;
5'd5: VAR14[5] <= VAR3;
5'd7: VAR14[4] <= VAR3;
5'd9: VAR14[3] <= VAR3;
5'd11: VAR14[2] <= VAR3;
5'd13: VAR14[1] <= VAR3;
5'd15: VAR14[0] <= VAR3;
default: VAR14 <= VAR14;
endcase
end
end
always @(posedge clk or negedge VAR22) begin
if(!VAR22)
VAR2 <= 8'hff;
end
else if(VAR5) begin
case(VAR7)
5'd3: VAR2[7] <= VAR3;
5'd5: VAR2[6] <= VAR3;
5'd7: VAR2[5] <= VAR3;
5'd9: VAR2[4] <= VAR3;
5'd11: VAR2[3] <= VAR3;
5'd13: VAR2[2] <= VAR3;
5'd15: VAR2[1] <= VAR3;
5'd17: VAR2[0] <= VAR3;
default: VAR2 <= VAR2;
endcase
end
end
assign VAR12 = VAR9 ? VAR2 : VAR14;
assign VAR15 = (VAR18 == 8'd64) ? 1'b1 :1'b0;
always @(posedge clk or negedge VAR22) begin
if(!VAR22)
VAR4 <= 1'b0;
end
else
VAR4 <= (VAR19 == 8'd64) ? 1'b1 : 1'b0;
end
reg VAR24;
reg [31:0] VAR23;
always@(posedge clk or negedge VAR22)begin
if(!VAR22)begin
VAR24 <= 1'b1;
VAR23 <= 'h0;
end
else if(VAR23 == 'hF && VAR7 == VAR8)begin
VAR23 <= 'h0;
VAR24 <= 1'b1;
end
else begin
VAR23 <= (VAR7 == VAR8) ? (VAR23 + 1'b1) : 'h0;
VAR24 <= 1'b0;
end
end
endmodule | mit |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/hps_sdram_p0_altdqdqs.v | 6,964 | module MODULE1 (
VAR26,
VAR29,
VAR12,
VAR73,
VAR67,
VAR79,
VAR71,
VAR32,
VAR51,
VAR21,
VAR92,
VAR49,
VAR37,
VAR36,
VAR63,
VAR60,
VAR6,
VAR19,
VAR39,
VAR15,
VAR34,
VAR53,
VAR24,
VAR48,
VAR11,
VAR16,
VAR20,
VAR70,
VAR42,
VAR50,
VAR38,
VAR66,
VAR90,
VAR91,
VAR1,
VAR89,
VAR93,
VAR25
);
input [7-1:0] VAR25;
input VAR26;
input VAR29;
input VAR12;
input VAR73;
input VAR67;
input [3:0] VAR79;
input VAR71;
output VAR32;
inout [8-1:0] VAR51;
input [2*8-1:0] VAR21;
inout VAR92;
input [2-1:0] VAR49;
inout VAR37;
input [2-1:0] VAR36;
output [2 * 2 * 8-1:0] VAR63;
output VAR60;
input [2 * 2 * 8-1:0] VAR6;
input [2 * 2 * 1-1:0] VAR19;
output [1-1:0] VAR39;
input [16-1:0] VAR15;
input [16-1:0] VAR34;
input VAR53;
input VAR24;
input VAR48;
input [8-1:0] VAR11;
input [1-1:0] VAR16;
input VAR20;
input VAR70;
input [2-1:0] VAR42;
input [2-1:0] VAR50;
input [4:0] VAR38;
input VAR66;
output VAR90;
input [2-1:0] VAR91;
input [2-1:0] VAR1;
input VAR89;
input VAR93;
parameter VAR64 = "";
VAR28 VAR72 (
.VAR26( VAR26),
.VAR29 (VAR29),
.VAR12( VAR12),
.VAR73( VAR73),
.VAR67 (VAR67),
.VAR79(VAR79),
.VAR71( VAR71),
.VAR32 (VAR32),
.VAR51( VAR51),
.VAR21( VAR21),
.VAR92( VAR92),
.VAR49( VAR49),
.VAR37( VAR37),
.VAR36( VAR36),
.VAR63( VAR63),
.VAR60( VAR60),
.VAR6( VAR6),
.VAR19( VAR19),
.VAR39( VAR39),
.VAR15( VAR15),
.VAR34( VAR34),
.VAR53( VAR53),
.VAR24( VAR24),
.VAR48( VAR48),
.VAR11( VAR11),
.VAR16( VAR16),
.VAR20( VAR20),
.VAR70( VAR70),
.VAR42(VAR42),
.VAR50(VAR50),
.VAR38(VAR38),
.VAR66(VAR66),
.VAR90(VAR90),
.VAR91(VAR91),
.VAR1(VAR1),
.VAR89(VAR89),
.VAR93(VAR93),
.VAR25(VAR25)
);
endmodule | epl-1.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/parser.v | 7,494 | module MODULE1(
input clk,
input VAR24,
input VAR11,
input [133:0] VAR21,
input VAR18,
input VAR16,
output VAR20,
output reg VAR23,
output [287:0] VAR22,
output VAR6,
output [133:0] VAR5,
input VAR10
);
reg [7:0] VAR25,VAR19;
reg [7:0] VAR3;
reg [47:0] VAR15;
reg [47:0] VAR13;
reg [15:0] VAR9;
reg [7:0] VAR7;
reg [31:0] VAR2;
reg [31:0] VAR1;
reg [15:0] VAR4;
reg [15:0] VAR8;
wire VAR14;
wire VAR12;
wire VAR17;
assign VAR6 = VAR11;
assign VAR5 = VAR21;
assign VAR20 = VAR10;
always @* begin
if(VAR11 == 1'b1) begin if(VAR21[133:132] == 2'b01) begin VAR19 = 8'b0;
end
else begin
VAR19 = VAR25 + 8'd1;
end
end
else begin
VAR19 = VAR25;
end
end
always @(posedge clk or negedge VAR24) begin
if(VAR24 == 1'b0) begin
VAR25 <= 8'b0;
end
else begin
VAR25 <= VAR19;
end
end
always @(posedge clk) begin
if((VAR11 == 1'b1) && (VAR19 == 8'd0)) begin
VAR3 <= {5'b0,VAR21[110],VAR21[59:58]}; end
else begin
VAR3 <= VAR3;
end
end
always @(posedge clk) begin
if((VAR11 == 1'b1) && (VAR19 == 8'd2)) begin VAR15 <= VAR21[127:80];
VAR13 <= VAR21[79:32];
VAR9 <= VAR21[31:16];
end
else begin
VAR15 <= VAR15;
VAR13 <= VAR13;
VAR9 <= VAR9;
end
end
assign VAR14 = (VAR9 == 16'h0800);
always @(posedge clk) begin
if((VAR11 == 1'b1) && (VAR19 == 8'd3)) begin
VAR7 <= VAR21[71:64];
VAR2 <= VAR21[47:16];
VAR1[31:16] <= VAR21[15:0];
end
else if((VAR11 == 1'b1) && (VAR19 == 8'd4)) begin
VAR1[15:0] <= VAR21[127:112]; end
else begin
VAR7 <= VAR7;
VAR2 <= VAR2;
VAR1 <= VAR1;
end
end
assign VAR12 = (VAR14) && (VAR7 == 16'h6);
assign VAR17 = (VAR14) && (VAR7 == 16'h11);
always @(posedge clk) begin
if((VAR11 == 1'b1) && (VAR19 == 8'd4)) begin
VAR4 <= VAR21[111:96];
VAR8 <= VAR21[95:80];
end
else begin
VAR4 <= VAR4;
VAR8 <= VAR8;
end
end
assign VAR22[287:240] = VAR13;
assign VAR22[239:192] = VAR15;
assign VAR22[191:176] = VAR9;
assign VAR22[175:144] = (VAR14) ? VAR2 : 32'hffffffff;
assign VAR22[143:112] = (VAR14) ? VAR1 : 32'hffffffff;
assign VAR22[111:104] = (VAR14) ? VAR7 : 8'hff;
assign VAR22[103:88] = (VAR12 || VAR17) ? VAR4 : 16'hffff;
assign VAR22[87:72] = (VAR12 || VAR17) ? VAR8 : 16'hffff;
assign VAR22[71:64] = VAR3;
assign VAR22[63:0] = 64'hffffffffffffffff;
always @(posedge clk or negedge VAR24) begin
if(VAR24 == 1'b0) begin
VAR23 <= 1'b0;
end
else begin
if(VAR18 == 1'b1) begin
VAR23 <= 1'b1;
end
else begin
VAR23 <= 1'b0;
end
end
end
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.v | 2,463 | module MODULE2 (
VAR3 ,
VAR10,
VAR9,
VAR7 ,
VAR4 ,
VAR1,
VAR6,
VAR5 ,
VAR2
);
output VAR3 ;
input VAR10;
input VAR9;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR6;
input VAR5 ;
input VAR2 ;
VAR8 VAR11 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR3 ,
VAR10,
VAR9,
VAR7 ,
VAR4
);
output VAR3 ;
input VAR10;
input VAR9;
input VAR7 ;
input VAR4 ;
supply1 VAR1;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR2 ;
VAR8 VAR11 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
qmn/riscv-invicta | hardware/src/regfile.v | 1,829 | module MODULE1 (
input clk,
input reset,
output [31:0] VAR6,
output [31:0] VAR7,
input [4:0] VAR3,
input [4:0] VAR8,
input [4:0] VAR2,
input [31:0] VAR9,
input VAR5,
input VAR4);
reg [31:0] VAR1[31:0];
always @ (posedge clk) begin
if (VAR5 & !VAR4 & VAR2 != 0)
VAR1[VAR2] <= VAR9;
end
assign VAR6 = VAR3 == 0 ? 32'b0 : VAR1[VAR3];
assign VAR7 = VAR8 == 0 ? 32'b0 : VAR1[VAR8];
endmodule | bsd-2-clause |
anderson1008/NOCulator | hring/hw/buffered/src/c_regfile.v | 8,979 | module MODULE1
(clk, VAR43, VAR9, VAR13, VAR8, VAR34);
parameter VAR17 = 8;
parameter VAR30 = 64;
parameter VAR36 = 1;
parameter VAR15 = VAR38;
localparam VAR31 = VAR32(VAR17);
input clk;
input VAR43;
input [0:VAR31-1] VAR9;
input [0:VAR30-1] VAR13;
input [0:VAR36*VAR31-1] VAR8;
output [0:VAR36*VAR30-1] VAR34;
wire [0:VAR36*VAR30-1] VAR34;
genvar VAR35;
genvar VAR25;
generate
case(VAR15)
begin
reg [0:VAR30-1] VAR2 [0:VAR17-1];
case(VAR15)
always @(posedge clk)
if(VAR43)
VAR2[VAR9] <= VAR13;
always @(clk, VAR43, VAR9, VAR13)
if(~clk)
if(VAR43)
VAR2[VAR9] <= VAR13;
endcase
for(VAR25 = 0; VAR25 < VAR36;
VAR25 = VAR25 + 1)
begin:VAR12
wire [0:VAR31-1] VAR24;
assign VAR24
= VAR8[VAR25*VAR31:
(VAR25+1)*VAR31-1];
wire [0:VAR30-1] VAR5;
assign VAR5 = VAR2[VAR24];
assign VAR34[VAR25*VAR30:(VAR25+1)*VAR30-1]
= VAR5;
end
end
begin
wire [0:VAR17*VAR30-1] VAR39;
for(VAR35 = 0; VAR35 < VAR17; VAR35 = VAR35 + 1)
begin:VAR37
wire write;
assign write = VAR43 && (VAR9 == VAR35);
reg [0:VAR30-1] VAR2;
case(VAR15)
always @(posedge clk)
if(write)
VAR2 <= VAR13;
always @(clk, write, VAR13)
if(~clk)
if(write)
VAR2 <= VAR13;
endcase
assign VAR39[VAR35*VAR30:(VAR35+1)*VAR30-1] = VAR2;
end
assign VAR34 = VAR39[VAR8*VAR30 +: VAR30];
end
begin
for(VAR35 = 0; VAR35 < VAR17; VAR35 = VAR35 + 1)
begin:VAR29
wire write;
assign write = VAR43 && (VAR9 == VAR35);
reg [0:VAR30-1] VAR2;
case(VAR15)
always @(posedge clk)
if(write)
VAR2 <= VAR13;
always @(clk, write, VAR13)
if(~clk)
if(write)
VAR2 <= VAR13;
endcase
for(VAR25 = 0; VAR25 < VAR36;
VAR25 = VAR25 + 1)
begin:VAR12
wire [0:VAR31-1] VAR24;
assign VAR24
= VAR8[VAR25*VAR31:
(VAR25+1)*VAR31-1];
wire read;
assign read = (VAR24 == VAR35);
wire [0:VAR30-1] VAR5;
assign VAR5 = read ? VAR2 : {VAR30{1'VAR10}};
assign VAR34[VAR25*VAR30:(VAR25+1)*VAR30-1]
= VAR5;
end
end
end
begin
wire VAR16;
assign VAR16 = ~VAR43;
case(VAR36)
1:
begin
case(VAR15)
begin
VAR18
.VAR17(VAR17),
.VAR6(1))
VAR42
(.clk(clk),
.VAR23(1'b1),
.VAR11(VAR16),
.VAR28(VAR16),
.VAR26(VAR8),
.VAR19(VAR9),
.VAR33(VAR13),
.VAR41(VAR34));
end
begin
VAR21
.VAR17(VAR17))
VAR27
(.clk(clk),
.VAR11(VAR16),
.VAR28(VAR16),
.VAR26(VAR8),
.VAR19(VAR9),
.VAR33(VAR13),
.VAR41(VAR34));
end
endcase
end
2:
begin
wire [0:VAR31-1] VAR40;
assign VAR40
= VAR8[0:VAR31-1];
wire [0:VAR31-1] VAR3;
assign VAR3
= VAR8[VAR31:2*VAR31-1];
wire [0:VAR30-1] VAR14;
wire [0:VAR30-1] VAR4;
case(VAR15)
begin
VAR18
.VAR17(VAR17),
.VAR6(1))
VAR42
(.clk(clk),
.VAR23(1'b1),
.VAR11(VAR16),
.VAR28(VAR16),
.VAR7(VAR40),
.VAR1(VAR3),
.VAR19(VAR9),
.VAR33(VAR13),
.VAR20(VAR14),
.VAR22(VAR4));
end
begin
VAR21
.VAR17(VAR17))
VAR27
(.clk(clk),
.VAR11(VAR16),
.VAR28(VAR16),
.VAR7(VAR40),
.VAR1(VAR3),
.VAR19(VAR9),
.VAR33(VAR13),
.VAR20(VAR14),
.VAR22(VAR4));
end
endcase
assign VAR34 = {VAR14, VAR4};
end
default:
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.pp.blackbox.v | 1,307 | module MODULE1 (
VAR6,
VAR3 ,
VAR5,
VAR7 ,
VAR2,
VAR1,
VAR8 ,
VAR4
);
output VAR6;
input VAR3 ;
input VAR5;
input VAR7 ;
input VAR2;
input VAR1;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
davidjabon/AXI-Peripheral-Library | Eight_Digit_Seven_Segment_Display_2.0/hdl/Eight_Digit_Seven_Segment_Display_v2_0.v | 2,479 | module MODULE1 #
(
parameter integer VAR22 = 32,
parameter integer VAR23 = 4
)
(
output wire [6:0] VAR3,
output wire VAR34,
output wire [7:0] VAR19,
input wire VAR13,
input wire VAR16,
input wire [VAR23-1 : 0] VAR45,
input wire [2 : 0] VAR51,
input wire VAR39,
output wire VAR24,
input wire [VAR22-1 : 0] VAR40,
input wire [(VAR22/8)-1 : 0] VAR12,
input wire VAR32,
output wire VAR44,
output wire [1 : 0] VAR21,
output wire VAR17,
input wire VAR38,
input wire [VAR23-1 : 0] VAR7,
input wire [2 : 0] VAR31,
input wire VAR43,
output wire VAR46,
output wire [VAR22-1 : 0] VAR37,
output wire [1 : 0] VAR48,
output wire VAR4,
input wire VAR26
);
VAR27 # (
.VAR18(VAR22),
.VAR36(VAR23)
) VAR15 (
.VAR3(VAR3),
.VAR34(VAR34),
.VAR19(VAR19),
.VAR9(VAR13),
.VAR28(VAR16),
.VAR42(VAR45),
.VAR35(VAR51),
.VAR49(VAR39),
.VAR1(VAR24),
.VAR41(VAR40),
.VAR20(VAR12),
.VAR6(VAR32),
.VAR14(VAR44),
.VAR29(VAR21),
.VAR47(VAR17),
.VAR2(VAR38),
.VAR25(VAR7),
.VAR50(VAR31),
.VAR33(VAR43),
.VAR8(VAR46),
.VAR11(VAR37),
.VAR30(VAR48),
.VAR5(VAR4),
.VAR10(VAR26)
);
endmodule | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_phy_10g.v | 7,046 | module MODULE1 #
(
parameter VAR16 = 64,
parameter VAR17 = (VAR16/8),
parameter VAR81 = (VAR16/32),
parameter VAR46 = 1,
parameter VAR7 = 1,
parameter VAR79 = 64,
parameter VAR74 = 4'h6,
parameter VAR9 = 16'h6666,
parameter VAR55 = 0,
parameter VAR36 = 96,
parameter VAR66 = VAR55,
parameter VAR63 = 16,
parameter VAR20 = 0,
parameter VAR39 = 96,
parameter VAR22 = (VAR66 ? VAR63 : 0) + 1,
parameter VAR18 = (VAR20 ? VAR39 : 0) + 1,
parameter VAR47 = 0,
parameter VAR21 = 0,
parameter VAR78 = 0,
parameter VAR12 = 0,
parameter VAR77 = 0,
parameter VAR67 = 1,
parameter VAR31 = 8,
parameter VAR26 = 125000/6.4
)
(
input wire VAR82,
input wire VAR62,
input wire VAR76,
input wire VAR5,
input wire [VAR16-1:0] VAR8,
input wire [VAR17-1:0] VAR38,
input wire VAR75,
output wire VAR25,
input wire VAR3,
input wire [VAR22-1:0] VAR73,
output wire [VAR16-1:0] VAR71,
output wire [VAR17-1:0] VAR11,
output wire VAR54,
output wire VAR29,
output wire [VAR18-1:0] VAR44,
output wire [VAR16-1:0] VAR4,
output wire [VAR81-1:0] VAR50,
input wire [VAR16-1:0] VAR52,
input wire [VAR81-1:0] VAR87,
output wire VAR49,
input wire [VAR36-1:0] VAR56,
input wire [VAR39-1:0] VAR61,
output wire [VAR36-1:0] VAR35,
output wire [VAR63-1:0] VAR42,
output wire VAR27,
output wire [1:0] VAR10,
output wire VAR57,
output wire [1:0] VAR70,
output wire [6:0] VAR14,
output wire VAR15,
output wire VAR72,
output wire VAR32,
output wire VAR1,
output wire VAR41,
output wire VAR40,
input wire [7:0] VAR51,
input wire VAR6,
input wire VAR83
);
VAR2 #(
.VAR16(VAR16),
.VAR17(VAR17),
.VAR81(VAR81),
.VAR74(VAR74),
.VAR9(VAR9),
.VAR37(VAR20),
.VAR19(VAR39),
.VAR13(VAR18),
.VAR47(VAR47),
.VAR21(VAR21),
.VAR78(VAR78),
.VAR28(VAR77),
.VAR67(VAR67),
.VAR31(VAR31),
.VAR26(VAR26)
)
VAR23 (
.clk(VAR82),
.rst(VAR62),
.VAR48(VAR71),
.VAR86(VAR11),
.VAR58(VAR54),
.VAR30(VAR29),
.VAR80(VAR44),
.VAR52(VAR52),
.VAR87(VAR87),
.VAR49(VAR49),
.VAR59(VAR61),
.VAR70(VAR70),
.VAR14(VAR14),
.VAR15(VAR15),
.VAR72(VAR72),
.VAR32(VAR32),
.VAR1(VAR1),
.VAR41(VAR41),
.VAR40(VAR40),
.VAR83(VAR83)
);
VAR34 #(
.VAR16(VAR16),
.VAR17(VAR17),
.VAR81(VAR81),
.VAR46(VAR46),
.VAR7(VAR7),
.VAR79(VAR79),
.VAR74(VAR74),
.VAR9(VAR9),
.VAR37(VAR55),
.VAR19(VAR36),
.VAR60(VAR66),
.VAR69(VAR63),
.VAR13(VAR22),
.VAR47(VAR47),
.VAR21(VAR21),
.VAR78(VAR78),
.VAR28(VAR12)
)
VAR65 (
.clk(VAR76),
.rst(VAR5),
.VAR64(VAR8),
.VAR43(VAR38),
.VAR45(VAR75),
.VAR85(VAR25),
.VAR24(VAR3),
.VAR84(VAR73),
.VAR4(VAR4),
.VAR50(VAR50),
.VAR59(VAR56),
.VAR68(VAR35),
.VAR33(VAR42),
.VAR53(VAR27),
.VAR10(VAR10),
.VAR57(VAR57),
.VAR51(VAR51),
.VAR6(VAR6)
);
endmodule | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_ic_ram.v | 7,442 | module MODULE1(
clk, rst,
VAR19, VAR4, VAR2,
addr, en, VAR10, VAR7, VAR15
);
parameter VAR3 = VAR1;
parameter VAR14 = VAR18;
input clk;
input rst;
input [VAR14-1:0] addr;
input en;
input [3:0] VAR10;
input [VAR3-1:0] VAR7;
output [VAR3-1:0] VAR15;
input VAR19;
input [VAR12 - 1:0] VAR2;
output VAR4;
assign VAR15 = {VAR3{1'b0}};
assign VAR4 = VAR19;
VAR8 VAR9(
VAR6 VAR9(
VAR13 VAR9(
.VAR19(VAR19),
.VAR4(VAR4),
.VAR2(VAR2),
.clk(clk),
.rst(rst),
.VAR11(en),
.VAR10(VAR10),
.VAR16(1'b1),
.addr(addr),
.VAR5(VAR7),
.VAR17(VAR15)
);
endmodule | gpl-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/Verilog_Source/Macros/serdes_n_to_1_s16_diff.v | 10,452 | module MODULE1 (VAR44, VAR79, reset, VAR52, VAR9, VAR77, VAR40, VAR64, VAR33, VAR66, VAR3) ;
parameter integer VAR12 = 10 ; parameter integer VAR35 = 16 ;
input VAR44 ; input VAR79 ; input reset ; input VAR52 ; input VAR9 ; input [(VAR35*VAR12)-1:0] VAR77 ; input [VAR12-1:0] VAR40 ; output [VAR35-1:0] VAR64 ; output [VAR35-1:0] VAR33 ; output VAR66 ; output VAR3 ;
wire [VAR35-1:0] VAR29 ; wire [VAR35-1:0] VAR45 ; wire [VAR35-1:0] VAR1 ; wire [VAR35-1:0] VAR48 ; wire [VAR35-1:0] VAR54 ; wire [VAR35*8:0] VAR17 ;
reg VAR6 ; reg VAR56 ; reg [7:0] VAR63 ; reg [(VAR35*VAR12/2)-1:0] VAR20 ;
parameter [VAR35-1:0] VAR32 = 16'h0000 ;
genvar VAR26 ;
genvar VAR24 ;
always @ (posedge VAR9 or posedge reset)
if (reset == 1'b1) begin
VAR6 <= 1'b0 ;
end
else begin
VAR6 <= ~VAR6 ;
end
always @ (posedge VAR52)
begin
VAR56 <= VAR6 ;
if (VAR6 != VAR56) begin
VAR20 <= VAR77[(VAR35*VAR12/2)-1:0] ;
VAR63 <= VAR40[VAR12/2-1:0] ;
end
else begin
VAR20 <= VAR77[(VAR35*VAR12)-1:VAR35*VAR12/2] ;
VAR63 <= VAR40[VAR12-1:VAR12/2] ;
end
end
VAR46 VAR5 (
.VAR38 (VAR66),
.VAR69 (VAR3),
.VAR36 (VAR21));
generate
for (VAR26 = 0 ; VAR26 <= (VAR35-1) ; VAR26 = VAR26+1)
begin : VAR53
VAR46 #(
.VAR51 ("VAR61" ))
VAR5 (
.VAR38 (VAR64[VAR26]),
.VAR69 (VAR33[VAR26]),
.VAR36 (VAR54[VAR26]));
for (VAR24 = 0 ; VAR24 <= (VAR12/2-1) ; VAR24 = VAR24+1)
begin : VAR50
assign VAR17[(8*VAR26)+VAR24] = VAR20[(VAR26)+(VAR35*VAR24)] ^ VAR32[VAR26] ;
end
VAR27 #(
.VAR47 (VAR12/2), .VAR4 ("VAR31"), .VAR65 ("VAR31"), .VAR41 ("VAR59"), .VAR34 ("VAR75"))
VAR23 (
.VAR60 (VAR54[VAR26]),
.VAR11 (1'b1),
.VAR78 (VAR44),
.VAR19 (1'b0),
.VAR28 (VAR79),
.VAR39 (reset),
.VAR18 (VAR52),
.VAR8 (VAR17[(8*VAR26)+7]),
.VAR7 (VAR17[(8*VAR26)+6]),
.VAR73 (VAR17[(8*VAR26)+5]),
.VAR37 (VAR17[(8*VAR26)+4]),
.VAR58 (),
.VAR57 (1'b0),
.VAR68 (1'b0),
.VAR43 (1'b0),
.VAR16 (1'b0),
.VAR49 (1'b0),
.VAR67 (1'b1),
.VAR70 (1'b1), .VAR72 (1'b1), .VAR74 (VAR45[VAR26]), .VAR62 (VAR48[VAR26]), .VAR71 (VAR29[VAR26]), .VAR25 (VAR1[VAR26]), .VAR55 (), .VAR42 ()) ;
VAR27 #(
.VAR47 (VAR12/2), .VAR4 ("VAR31"), .VAR65 ("VAR31"), .VAR41 ("VAR30"), .VAR34 ("VAR75"))
VAR15 (
.VAR60 (),
.VAR11 (1'b1),
.VAR78 (VAR44),
.VAR19 (1'b0),
.VAR28 (VAR79),
.VAR39 (reset),
.VAR18 (VAR52),
.VAR8 (VAR17[(8*VAR26)+3]),
.VAR7 (VAR17[(8*VAR26)+2]),
.VAR73 (VAR17[(8*VAR26)+1]),
.VAR37 (VAR17[(8*VAR26)+0]),
.VAR58 (),
.VAR57 (1'b0),
.VAR68 (1'b0),
.VAR43 (1'b0),
.VAR16 (1'b0),
.VAR49 (1'b0),
.VAR67 (1'b1),
.VAR70 (VAR29[VAR26]), .VAR72 (VAR1[VAR26]), .VAR74 (1'b1), .VAR62 (1'b1), .VAR71 (), .VAR25 (), .VAR55 (VAR45[VAR26]), .VAR42 (VAR48[VAR26])) ; end
endgenerate
VAR27 #(
.VAR47 (VAR12/2), .VAR4 ("VAR31"), .VAR65 ("VAR31"), .VAR41 ("VAR59"), .VAR34 ("VAR75"))
VAR13 (
.VAR60 (VAR21),
.VAR11 (1'b1),
.VAR78 (VAR44),
.VAR19 (1'b0),
.VAR28 (VAR79),
.VAR39 (reset),
.VAR18 (VAR52),
.VAR8 (VAR63[7]),
.VAR7 (VAR63[6]),
.VAR73 (VAR63[5]),
.VAR37 (VAR63[4]),
.VAR58 (),
.VAR57 (1'b0),
.VAR68 (1'b0),
.VAR43 (1'b0),
.VAR16 (1'b0),
.VAR49 (1'b0),
.VAR67 (1'b1),
.VAR70 (1'b1), .VAR72 (1'b1), .VAR74 (VAR14), .VAR62 (VAR22), .VAR71 (VAR76), .VAR25 (VAR2), .VAR55 (), .VAR42 ()) ;
VAR27 #(
.VAR47 (VAR12/2), .VAR4 ("VAR31"), .VAR65 ("VAR31"), .VAR41 ("VAR30"), .VAR34 ("VAR75"))
VAR10 (
.VAR60 (),
.VAR11 (1'b1),
.VAR78 (VAR44),
.VAR19 (1'b0),
.VAR28 (VAR79),
.VAR39 (reset),
.VAR18 (VAR52),
.VAR8 (VAR63[3]),
.VAR7 (VAR63[2]),
.VAR73 (VAR63[1]),
.VAR37 (VAR63[0]),
.VAR58 (),
.VAR57 (1'b0),
.VAR68 (1'b0),
.VAR43 (1'b0),
.VAR16 (1'b0),
.VAR49 (1'b0),
.VAR67 (1'b1),
.VAR70 (VAR76), .VAR72 (VAR2), .VAR74 (1'b1), .VAR62 (1'b1), .VAR71 (), .VAR25 (), .VAR55 (VAR14), .VAR42 (VAR22)) ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2b/sky130_fd_sc_hd__and2b.functional.pp.v | 1,934 | module MODULE1 (
VAR13 ,
VAR14 ,
VAR5 ,
VAR9,
VAR6,
VAR2 ,
VAR7
);
output VAR13 ;
input VAR14 ;
input VAR5 ;
input VAR9;
input VAR6;
input VAR2 ;
input VAR7 ;
wire VAR15 ;
wire VAR4 ;
wire VAR12;
not VAR3 (VAR15 , VAR14 );
and VAR1 (VAR4 , VAR15, VAR5 );
VAR8 VAR11 (VAR12, VAR4, VAR9, VAR6);
buf VAR10 (VAR13 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.pp.blackbox.v | 1,307 | module MODULE1 (
VAR2,
VAR8 ,
VAR5,
VAR4 ,
VAR6,
VAR1,
VAR3 ,
VAR7
);
output VAR2;
input VAR8 ;
input VAR5;
input VAR4 ;
input VAR6;
input VAR1;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
hightoon/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_STATUS_IN.v | 5,843 | module MODULE1(
input VAR2,
input VAR9,
output reg VAR14, output reg VAR4, output reg VAR7, input VAR10,
output reg VAR13 );
reg VAR15;
reg VAR11;
reg VAR12; reg [2:0] VAR5;
reg [7:0] VAR1;
parameter VAR17 = 2'b00;
parameter VAR16 = 2'b01;
parameter VAR3 = 2'b10;
parameter VAR8 = 2'b11;
reg [1:0] VAR6;
always @ ( negedge VAR2 ) begin
if ( VAR9 == 1'b1 ) begin
VAR1 <= 8'h00;
end
else begin
VAR1 <= {VAR1[6:0], VAR10};
end
end
always @ ( negedge VAR2 ) begin
VAR12 <= 1'b0;
if ( VAR1 == 8'h55 | VAR1 == 8'hAA) begin
VAR6 <= VAR17;
end
else if ( VAR1 == 8'hF0 | VAR1 == 8'h87 | VAR1 == 8'hC3 | VAR1 == 8'hE1 | VAR1 == 8'h78 | VAR1 == 8'h3C | VAR1 == 8'h1E | VAR1 == 8'h0F ) begin
VAR6 <= VAR16;
end
else if ( VAR1 == 8'h33 | VAR1 == 8'h66 | VAR1 == 8'hCC | VAR1 == 8'h99 ) begin
VAR6 <= VAR3;
end
else if ( VAR1 == 8'h00) begin
VAR6 <= VAR8;
end
else begin VAR6 <= VAR6;
VAR12 <= 1'b1;
end
end
always@ (negedge VAR2) begin
if (VAR9) begin
VAR5 <= 3'b000;
end else if(VAR12) begin
if (VAR5 != 3'b111)
VAR5 <= VAR5 + 3'b001;
end
else
VAR5 <= VAR5;
end else begin
VAR5 <= 3'b000;
end
end
always@ (negedge VAR2) begin
VAR13 <= (VAR5 == 3'b111) ? 1'b1 : 1'b0;
end
always @ (posedge VAR2) begin
if ( VAR9 == 1'b1 ) begin
VAR14 <= 1'b0;
VAR7 <= 1'b0;
VAR4 <= 1'b0;
VAR15 <= 0;
VAR11 <= 0;
end
else if ( VAR6 == VAR17) begin
VAR14 <= 1'b1;
VAR7 <= 1'b0;
VAR4 <= 1'b0;
VAR15 <= 0;
VAR11 <= 0;
end
else if ( VAR6 == VAR3 ) begin
VAR7 <= 1'b1;
VAR4 <= 1'b0;
VAR14 <= 1'b0;
VAR15 <= 0;
VAR11 <= 0;
end
else if ( VAR6 == VAR16 ) begin
VAR14 <= 1'b0;
VAR4 <= 1'b1;
VAR7 <= 1'b1;
VAR15 <= 0;
VAR11 <= 0;
end
else if ( VAR6 == VAR8 ) begin
if(VAR11 == 0) begin
VAR11 <= 1;
VAR15 <= 1;
end
else
begin
VAR15 <= 0;
end
VAR14 <= 1'b0;
VAR4 <= 1'b0;
VAR7 <= 1'b0;
end
end
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4.functional.pp.v | 1,837 | module MODULE1 (
VAR13 ,
VAR3 ,
VAR8 ,
VAR14 ,
VAR5 ,
VAR6,
VAR2,
VAR9 ,
VAR4
);
output VAR13 ;
input VAR3 ;
input VAR8 ;
input VAR14 ;
input VAR5 ;
input VAR6;
input VAR2;
input VAR9 ;
input VAR4 ;
wire VAR10 ;
wire VAR11;
and VAR15 (VAR10 , VAR3, VAR8, VAR14, VAR5 );
VAR7 VAR1 (VAR11, VAR10, VAR6, VAR2);
buf VAR12 (VAR13 , VAR11 );
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/duc_chain.v | 6,362 | module MODULE1
parameter VAR78 = 0,
parameter VAR42 = 0,
parameter VAR109 = 24
)
(input clk, input rst, input VAR52,
input VAR11, input [7:0] VAR72, input [31:0] VAR65,
input VAR40, input [7:0] VAR95, input [31:0] VAR7,
output [VAR109-1:0] VAR69,
output [VAR109-1:0] VAR26,
input [31:0] VAR67,
input VAR107,
output VAR62,
output [31:0] VAR86
);
wire VAR114;
wire [17:0] VAR50;
wire [31:0] VAR53;
reg [31:0] VAR10;
wire [7:0] VAR68;
wire [3:0] VAR98, VAR84;
wire VAR19, VAR22;
wire VAR25;
VAR75 #(.VAR51(VAR78+0)) VAR112
(.clk(clk),.rst(rst),.VAR62(VAR11),.addr(VAR72),
.in(VAR65),.out(VAR53),.VAR33());
VAR75 #(.VAR51(VAR78+1), .VAR20(18)) VAR63
(.clk(clk),.rst(rst),.VAR62(VAR11),.addr(VAR72),
.in(VAR65),.out(VAR50),.VAR33());
VAR75 #(.VAR51(VAR78+2), .VAR20(10)) VAR64
(.clk(clk),.rst(rst),.VAR62(VAR11),.addr(VAR72),
.in(VAR65),.out({VAR19, VAR22, VAR68}),.VAR33(VAR25));
wire VAR12, VAR89, VAR57;
reg VAR92 = 1;
reg VAR58 = 1;
reg VAR101 = 1;
VAR4 #(.VAR109(8))
VAR4(.VAR115(clk),.reset(rst),.enable(VAR114 & ~VAR25),.VAR29(VAR68),
.VAR17(1),.VAR9(VAR12) );
VAR4 #(.VAR109(2))
VAR104(.VAR115(clk),.reset(rst),.enable(VAR114 & ~VAR25),.VAR29(VAR22 ? 2 : 1),
.VAR17(VAR12),.VAR9(VAR57) );
VAR4 #(.VAR109(2))
VAR2(.VAR115(clk),.reset(rst),.enable(VAR114 & ~VAR25),.VAR29(VAR19 ? 2 : 1),
.VAR17(VAR57),.VAR9(VAR89) );
always @(posedge clk) VAR58 <= VAR89;
always @(posedge clk) VAR101 <= VAR57;
always @(posedge clk) VAR92 <= VAR12;
always @(posedge clk)
if(rst)
VAR10 <= 0;
else if(~VAR114)
VAR10 <= 0;
else
VAR10 <= VAR10 + VAR53;
wire signed [17:0] VAR66, VAR3;
wire signed [35:0] VAR73, VAR56;
wire [15:0] VAR18;
wire [15:0] VAR30;
wire [17:0] VAR87, VAR71;
wire [17:0] VAR96, VAR38, VAR76, VAR70;
wire [7:0] VAR36 = VAR22 ? ({VAR68,1'b0}) : VAR68;
VAR74 #(.VAR97(18),.VAR13(18),.VAR46(VAR109)) VAR113
(.clk(clk),.rst(rst),.VAR35(~VAR19),.VAR36(VAR36),.VAR88(VAR58),.VAR60({VAR18, 2'b0}),.VAR45(VAR101),.VAR100(VAR96));
VAR74 #(.VAR97(18),.VAR13(18),.VAR46(VAR109)) VAR79
(.clk(clk),.rst(rst),.VAR35(~VAR19),.VAR36(VAR36),.VAR88(VAR58),.VAR60({VAR30, 2'b0}),.VAR45(VAR101),.VAR100(VAR38));
VAR81 #(.VAR109(18)) VAR102
(.clk(clk),.rst(rst),.VAR35(~VAR22),.VAR88(VAR101),.VAR60(VAR96),
.VAR47(VAR68),.VAR45(VAR92),.VAR100(VAR76));
VAR81 #(.VAR109(18)) VAR21
(.clk(clk),.rst(rst),.VAR35(~VAR22),.VAR88(VAR101),.VAR60(VAR38),
.VAR47(VAR68),.VAR45(VAR92),.VAR100(VAR70));
VAR103 #(.VAR5(18),.VAR77(4),.VAR110(7))
VAR82(.VAR115(clk),.reset(rst),.enable(VAR114 & ~VAR25),.VAR29(VAR68),
.VAR54(VAR92),.VAR23(1),
.VAR16(VAR76),.VAR34(VAR87));
VAR103 #(.VAR5(18),.VAR77(4),.VAR110(7))
VAR80(.VAR115(clk),.reset(rst),.enable(VAR114 & ~VAR25),.VAR29(VAR68),
.VAR54(VAR92),.VAR23(1),
.VAR16(VAR70),.VAR34(VAR71));
localparam VAR48 = VAR109; localparam VAR105 = 24;
wire [VAR48-1:0] VAR49, VAR111;
VAR83 #(.VAR90(VAR48))
VAR28(.VAR115(clk), .reset(rst), .enable(VAR114),
.VAR108({VAR87,{(VAR48-18){1'b0}}}),.VAR6({VAR71,{(VAR48-18){1'b0}}}),
.VAR43(VAR10[31:32-VAR105]),
.VAR116(VAR49),.VAR14(VAR111),.VAR91() );
VAR93 VAR32
(.VAR37(VAR73), .VAR24(VAR49[VAR48-1:VAR48-18]), .VAR27(VAR50), .VAR41(clk), .VAR94(1), .VAR1(rst) );
VAR93 VAR85
(.VAR37(VAR56), .VAR24(VAR111[VAR48-1:VAR48-18]), .VAR27(VAR50), .VAR41(clk), .VAR94(1), .VAR1(rst) );
VAR31 #(.VAR42(VAR42), .VAR109(VAR109)) VAR31(
.VAR115(clk), .reset(rst), .VAR8(VAR52), .enable(VAR107),
.VAR11(VAR40), .VAR72(VAR95), .VAR65(VAR7),
.VAR59(VAR69), .VAR44(VAR26),
.VAR61(VAR73[33:34-VAR109]), .VAR117(VAR56[33:34-VAR109]),
.VAR106({VAR18, VAR30}), .VAR15(VAR58), .VAR39(VAR114),
.VAR99(VAR67), .VAR55(VAR62));
assign VAR86 = {VAR92, VAR58, VAR101,VAR107};
endmodule | gpl-2.0 |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/pp3/abc9_map.v | 1,409 | module MODULE1 (
output VAR10,
input VAR13,
input VAR11,
input VAR14,
input VAR4,
input VAR5
);
parameter VAR1 = 1'b0;
parameter VAR2 = 1'b0;
parameter VAR8 = 1'b0;
parameter VAR6 = 1'b0;
parameter VAR9 = 1'b0;
if (VAR2 != 1'b0 && VAR8 != 1'b0 && VAR6 == 1'b0 && VAR9 == 1'b0)
VAR12 VAR3 (.VAR10(VAR10), .VAR13(VAR13), .VAR11(VAR11), .VAR14(VAR14));
else
wire VAR7 = 1;
endmodule | apache-2.0 |
migajv/mips_pipeline | verilog/regm.v | 2,281 | module MODULE1(
input wire clk,
input wire rst,
input wire [4:0] VAR3, VAR4,
output wire [31:0] VAR8, VAR2,
input wire VAR7,
input wire [4:0] VAR9,
input wire [31:0] VAR1);
reg [31:0] VAR6 [0:31];
reg [31:0] VAR8, VAR2;
integer VAR5; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbn/sky130_fd_sc_ms__dlxbn.symbol.v | 1,368 | module MODULE1 (
input VAR4 ,
output VAR2 ,
output VAR8 ,
input VAR3
);
supply1 VAR7;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
bluespec/Flute | builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkCSR_MIE.v | 3,367 | module MODULE1(VAR15,
VAR3,
VAR19,
VAR6,
VAR24,
VAR16,
VAR21,
VAR20);
input VAR15;
input VAR3;
input VAR19;
output [31 : 0] VAR6;
input [27 : 0] VAR24;
input [31 : 0] VAR16;
input VAR21;
output [31 : 0] VAR20;
wire [31 : 0] VAR20, VAR6;
reg [11 : 0] VAR17;
wire [11 : 0] VAR12;
wire VAR1;
wire VAR18,
VAR10,
VAR8,
VAR7;
wire [11 : 0] VAR22;
wire VAR9, VAR23, VAR4, VAR2, VAR11, VAR14;
assign VAR10 = 1'd1 ;
assign VAR7 = VAR19 ;
assign VAR6 = { 20'd0, VAR17 } ;
assign VAR20 = { 20'd0, VAR22 } ;
assign VAR18 = 1'd1 ;
assign VAR8 = VAR21 ;
assign VAR12 = VAR21 ? VAR22 : 12'd0 ;
assign VAR1 = VAR21 || VAR19 ;
assign VAR22 =
{ VAR16[11],
1'b0,
VAR9,
VAR2,
VAR16[7],
1'b0,
VAR4,
VAR14,
VAR16[3],
1'b0,
VAR23,
VAR11 } ;
assign VAR9 = VAR24[18] && VAR16[9] ;
assign VAR23 = VAR24[18] && VAR16[1] ;
assign VAR4 = VAR24[18] && VAR16[5] ;
assign VAR2 = VAR24[13] && VAR16[8] ;
assign VAR11 = VAR24[13] && VAR16[0] ;
assign VAR14 = VAR24[13] && VAR16[4] ;
always@(posedge VAR15)
begin
if (VAR3 == VAR5)
begin
VAR17 <= VAR13 12'd0;
end
else
begin
if (VAR1) VAR17 <= VAR13 VAR12;
end
end
begin
VAR17 = 12'hAAA;
end | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_port_lookup/cam_router/src/ip_arp.v | 8,745 | module MODULE1
parameter VAR67 = VAR29,
parameter VAR4 = VAR7(VAR67)
)
( input [31:0] VAR50,
input [VAR61-1:0] VAR41,
input VAR51,
input VAR20,
output [47:0] VAR52,
output [VAR61-1:0] VAR13,
output VAR32,
output VAR6,
output VAR46,
input VAR44,
input [VAR4-1:0] VAR14, input VAR83, output [47:0] VAR77, output [31:0] VAR45, output VAR65,
input [VAR4-1:0] VAR5,
input VAR88,
input [47:0] VAR56,
input [31:0] VAR35, output VAR26,
input reset,
input clk
);
function integer VAR7;
input integer VAR53;
begin
VAR7=0;
while(2**VAR7<VAR53) begin
VAR7=VAR7+1;
end
end
endfunction
wire VAR47;
wire VAR58;
wire [VAR67-1:0] VAR39;
wire [31:0] VAR2, VAR22;
wire [31:0] VAR15, VAR76;
wire VAR63;
wire [VAR4-1:0] VAR80;
wire [47:0] VAR18;
wire VAR11;
reg [VAR61-1:0] VAR68;
reg VAR79;
VAR84 VAR36
(
.reset(reset),
.VAR24(clk),
.VAR31(VAR63),
.VAR42(VAR15),
.VAR87(VAR80),
.VAR28(1'b1),
.VAR55(clk),
.VAR60(VAR51),
.VAR12(VAR2),
.VAR89(VAR39),
.VAR40(),
.VAR19(VAR58),
.VAR54(),
.VAR17(),
.VAR62(),
.VAR37()
);
localparam
VAR78 = 2'b00,
VAR59 = 2'b01,
VAR23 = 2'b10;
reg [1:0] VAR74,VAR33;
reg VAR21,VAR3;
always @(posedge clk) begin
if (reset) begin
VAR74 <= VAR78;
VAR21 <= 1'b0;
end
else begin
VAR74 <= VAR33;
VAR21 <= VAR3;
end end
always @(*) begin
VAR3 = VAR21;
VAR33 = VAR74;
case (VAR74)
VAR78: begin
if (VAR63) begin
VAR3 = 1'b1;
VAR33 = VAR59;
end
else
VAR3 = 1'b0;
end
VAR59: begin
VAR3 = 1'b1;
VAR33 = VAR23;
end
VAR23: begin
VAR3 = 1'b0;
VAR33 = VAR78;
end
endcase
end
assign VAR47 = VAR21;
VAR30
.VAR67(VAR67)
) VAR90
( .VAR66 (VAR51),
.VAR8 (VAR50),
.VAR9 (32'h0),
.VAR72 (VAR72),
.VAR49 (VAR49),
.VAR81 (VAR18),
.VAR43 (VAR14), .VAR64 (VAR83), .VAR71 (VAR77), .VAR25 (VAR45), .VAR38 (), .VAR86 (VAR65),
.VAR34 (VAR5),
.VAR85 (VAR88),
.VAR1 (VAR56), .VAR27 (VAR35), .VAR48 (32'h0), .VAR57 (VAR26),
.VAR47 (VAR47),
.VAR58 (VAR58),
.VAR39 (VAR39),
.VAR2 (VAR2),
.VAR15 (VAR15),
.VAR63 (VAR63),
.VAR80 (VAR80),
.VAR22 (VAR22),
.VAR76 (VAR76),
.reset (reset),
.clk (clk));
VAR82 #(.VAR16(50+VAR61), .VAR75 (2))
VAR69
(.din ({VAR18, VAR68, VAR49, VAR79}), .VAR31 (VAR72), .VAR60 (VAR44), .dout ({VAR52, VAR13, VAR6, VAR46}),
.VAR70 (),
.VAR73 (),
.VAR10 (),
.VAR11 (VAR11),
.reset (reset),
.clk (clk)
);
assign VAR32 = !VAR11;
always @(posedge clk) begin
if(reset) begin
VAR68 <= 0;
VAR79 <= 0;
end
else if(VAR51) begin
VAR68 <= VAR41;
VAR79 <= VAR20;
end
end
endmodule | mit |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/rng.v | 1,925 | module MODULE1(reset, VAR10, VAR5, VAR7, VAR6, VAR3, VAR1, VAR9);
input reset, VAR10, VAR6;
input VAR5, VAR7;
output VAR3, VAR1;
output [15:0] VAR9;
reg [15:0] VAR8;
reg [3:0] VAR4;
assign VAR9[15:0] = VAR8[15:0];
assign VAR3 = VAR8[VAR4];
assign VAR1 = (VAR4 == 0);
reg VAR2;
always @ (posedge VAR6 or posedge reset) begin
if (reset) begin
VAR4 <= 0;
VAR2 <= 0;
end else if (!VAR2) begin
VAR2 <= 1;
VAR4 <= 15;
end else if (!VAR1) begin
VAR4 <= VAR4 - 4'd1;
end else begin
end end
always @ (posedge VAR7 or posedge VAR10) begin
if (VAR10) begin
VAR8 <= 16'h0000;
end else begin
VAR8[0] <= VAR5 ^ VAR8[15];
VAR8[1] <= VAR8[0];
VAR8[2] <= VAR8[1];
VAR8[3] <= VAR8[2];
VAR8[4] <= VAR8[3];
VAR8[5] <= VAR8[4] ^ VAR5 ^ VAR8[15];
VAR8[6] <= VAR8[5];
VAR8[7] <= VAR8[6];
VAR8[8] <= VAR8[7];
VAR8[9] <= VAR8[8];
VAR8[10] <= VAR8[9];
VAR8[11] <= VAR8[10];
VAR8[12] <= VAR8[11] ^ VAR5 ^ VAR8[15];
VAR8[13] <= VAR8[12];
VAR8[14] <= VAR8[13];
VAR8[15] <= VAR8[14];
end end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv_8.v | 1,995 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR1,
VAR3,
VAR5 ,
VAR4
);
output VAR7 ;
input VAR6 ;
input VAR1;
input VAR3;
input VAR5 ;
input VAR4 ;
VAR8 VAR2 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR7,
VAR6
);
output VAR7;
input VAR6;
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
VAR8 VAR2 (
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sa1/cheat.v | 12,539 | module MODULE1(
input clk,
input [7:0] VAR31,
input [23:0] VAR59,
input [7:0] VAR7,
input VAR55,
input VAR4,
input VAR61,
input VAR23,
input VAR41,
input VAR11,
input VAR39,
input VAR44,
input VAR66,
input VAR40,
input VAR50,
input VAR37,
input [2:0] VAR42,
input VAR16,
input [31:0] VAR28,
output [7:0] VAR20,
output VAR17,
output VAR10
);
wire VAR58 = VAR23 & VAR55;
reg VAR22 = 0;
reg VAR54 = 0;
reg VAR12 = 0;
reg VAR13 = 0; reg VAR21 = 0;
reg VAR26 = 0;
wire VAR15 = VAR22 & VAR26;
reg VAR64 = 1;
reg VAR63 = 0;
reg VAR62 = 0;
reg VAR45 = 0;
reg VAR33 = 0;
reg [1:0] VAR29 = 2'b10;
reg [4:0] VAR32 = 5'h00;
reg [4:0] VAR68 = 5'h00;
reg [20:0] VAR38 = 21'h1fffff;
reg [29:0] VAR2 = 0;
reg VAR60 = 0;
reg [1:0] VAR1 = 0;
wire VAR8 = |VAR1;
reg [1:0] VAR65 = 2'b10;
wire VAR47 = |VAR65;
reg [23:0] VAR19[5:0];
reg [7:0] VAR52[5:0];
reg [5:0] VAR24;
reg VAR53 = 0;
assign VAR10 = VAR53;
reg [7:0] VAR6 = 0;
reg [7:0] VAR25 = 8'hea;
reg [7:0] VAR18 = 8'h00;
reg [7:0] VAR67 = 8'h00;
reg [7:0] VAR9 = 8'h04;
reg [15:0] VAR14 = 0;
wire [5:0] VAR30 ={(VAR24[5] & (VAR59 == VAR19[5])),
(VAR24[4] & (VAR59 == VAR19[4])),
(VAR24[3] & (VAR59 == VAR19[3])),
(VAR24[2] & (VAR59 == VAR19[2])),
(VAR24[1] & (VAR59 == VAR19[1])),
(VAR24[0] & (VAR59 == VAR19[0]))};
wire VAR34 = |VAR30;
wire [1:0] VAR3 = {VAR59 == 24'h00FFEA, VAR59 == 24'h00FFEB};
wire [1:0] VAR36 = {VAR59 == 24'h00FFEE, VAR59 == 24'h00FFEF};
wire [1:0] VAR48 = {VAR59 == 24'h00FFFC, VAR59 == 24'h00FFFD};
wire VAR43 = |VAR3;
wire VAR49 = |VAR36;
wire VAR51 = |VAR48;
wire VAR56 = ~|VAR2;
assign VAR20 = VAR30[0] ? VAR52[0]
: VAR30[1] ? VAR52[1]
: VAR30[2] ? VAR52[2]
: VAR30[3] ? VAR52[3]
: VAR30[4] ? VAR52[4]
: VAR30[5] ? VAR52[5]
: VAR3[1] ? 8'h10
: VAR36[1] ? 8'h10
: VAR48[1] ? 8'h7D
: VAR41 ? VAR6
: VAR11 ? VAR25
: VAR39 ? VAR18
: VAR44 ? VAR67
: VAR66 ? VAR9
: 8'h2a;
assign VAR17 = (VAR10 & VAR33 & (VAR41 | VAR11 | VAR39 | VAR44 | VAR66))
| (VAR47 & VAR51)
| (VAR22 & VAR34)
| (VAR33 & (((VAR63 & VAR54) & VAR43 & VAR8)
|((VAR45 & VAR12) & VAR49 & VAR8)
));
reg [7:0] VAR46 = 0;
reg [2:0] VAR35 = 0;
always @(posedge clk) begin
if(VAR61) begin
VAR35 <= 0;
end else if(VAR55) begin
VAR35 <= VAR35 + 1;
if(VAR35 == 3'b0) begin
VAR46 <= VAR31 - 1;
end else begin
if(VAR31 == VAR46) begin
VAR46 <= VAR46 - 1;
end else begin
VAR35 <= 3'b0;
end
end
end else if(VAR4) begin
VAR35 <= 3'b0;
end
end
always @(posedge clk) begin
if(VAR61) begin
VAR1 <= 2'b00;
end else if(VAR4) begin
if(VAR33
& ((VAR63 & VAR54 & VAR3[1])
|(VAR45 & VAR12 & VAR36[1])
)
& VAR35 == 4) begin
VAR1 <= 2'b11;
end else if(|VAR1) begin
VAR1 <= VAR1 - 1;
end
end
end
always @(posedge clk) begin
if(VAR61) begin
VAR65 <= 2'b11;
end else if(VAR37) begin
if(VAR51 & |VAR65) begin
VAR65 <= VAR65 - 1;
end
end
end
reg VAR27 = 1'b0;
reg [6:0] VAR57 = 0;
reg VAR5 = 0;
always @(posedge clk) begin
if(VAR61) begin
VAR53 <= 0;
VAR5 <= 0;
end else begin
if(VAR4) begin
if(VAR33
& ((VAR63 & VAR54 & VAR3[1])
|(VAR45 & VAR12 & VAR36[1])
)
& VAR35 == 4) begin
VAR25 <= VAR59[7:0];
VAR53 <= 1;
end
if(VAR48[1] & |VAR65) begin
VAR53 <= 1;
end
end
if(VAR37) begin
if(VAR5) begin
if(|VAR57) begin
VAR57 <= VAR57 - 1;
end else if(VAR57 == 0) begin
VAR53 <= 0;
VAR5 <= 0;
end
end
end
if(VAR27) begin
VAR57 <= 7'd6;
VAR5 <= 1;
end
end
end
always @(posedge clk) VAR38 <= VAR38 - 1;
always @(posedge clk) begin
if(VAR38 == 21'b0) begin
VAR32 <= VAR37 & VAR3[1];
VAR68 <= VAR37 & VAR36[1];
if(|VAR32 & |VAR68) begin
VAR64 <= 1'b1;
VAR62 <= 1'b0;
end else if(VAR68 == 5'b0) begin
VAR64 <= 1'b1;
VAR62 <= 1'b0;
end else if(VAR32 == 5'b0) begin
VAR64 <= 1'b0;
VAR62 <= 1'b1;
end
VAR64 <= |VAR32;
end else begin
if(VAR37 & VAR3[0]) VAR32 <= VAR32 + 1;
if(VAR37 & VAR36[0]) VAR68 <= VAR68 + 1;
end
end
always @(posedge clk) begin
if(VAR37) begin
if(VAR43
| VAR49
) VAR29 <= 2'b10;
end
else begin
if (|VAR29) VAR29 <= VAR29 - 1;
if (VAR29 == 2'b00) begin
VAR63 <= VAR64;
VAR45 <= VAR62;
VAR33 <= VAR56;
end
end
end
end
always @(posedge clk) begin
if((VAR10 & VAR58 & ~|VAR59[8:0] & (VAR7 == 8'h85))
| (VAR13 & VAR61)) begin
VAR2 <= 30'd960000000;
end else if (|VAR2) begin
VAR2 <= VAR2 - 1;
end
end
always @(posedge clk) begin
if(VAR61) begin
VAR27 <= 1'b0;
end else begin
VAR27 <= 1'b0;
if(VAR10 & VAR58) begin
if(~|VAR59[8:0]) begin
case(VAR7)
8'h82: VAR22 <= 1;
8'h83: VAR22 <= 0;
8'h84: {VAR54, VAR12} <= 2'b00;
endcase
end else if(VAR59[8:0] == 9'h1fd) begin
VAR27 <= 1'b1;
end
end else if(VAR16) begin
if(VAR42 < 6) begin
VAR19[VAR42] <= VAR28[31:8];
VAR52[VAR42] <= VAR28[7:0];
end else if(VAR42 == 6) begin VAR24 <= VAR28[5:0];
end else if(VAR42 == 7) begin {VAR26, VAR21, VAR13, VAR12, VAR54, VAR22}
<= ({VAR26, VAR21, VAR13, VAR12, VAR54, VAR22}
& ~VAR28[13:8])
| VAR28[5:0];
end
end
end
end
always @(posedge clk) begin
if(VAR58) begin
if(VAR59[8:0] == 9'h1f0) begin
VAR14[7:0] <= VAR7;
end else if(VAR59[8:0] == 9'h1f1) begin
VAR14[15:8] <= VAR7;
end
end
end
always @* begin
case(VAR14)
16'h3030: VAR6 = 8'h80;
16'h2070: VAR6 = 8'h81;
16'h10b0: VAR6 = 8'h82;
16'h9030: VAR6 = 8'h83;
16'h5030: VAR6 = 8'h84;
16'h1070: VAR6 = 8'h85;
default: VAR6 = 8'h00;
endcase
end
always @* begin
if(VAR21) begin
if(VAR50) begin
if(VAR6) begin
VAR18 = 8'h30; end else begin
if(VAR15) begin
VAR18 = 8'h3a; end else begin
VAR18 = 8'h43; end
end
end else begin
if(VAR40) begin
if(VAR15) begin
VAR18 = 8'h3a; end else begin
VAR18 = 8'h43; end
end else begin
VAR18 = 8'h00; end
end
end else begin
if(VAR15) begin
VAR18 = 8'h3a; end else begin
VAR18 = 8'h43; end
end
end
always @* begin
if(VAR6 == 8'h81) begin
VAR67 = 8'h14; end else if(VAR15) begin
VAR67 = 8'h00; end else begin
VAR67 = 8'h09; end
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp.pp.symbol.v | 1,474 | module MODULE1 (
input VAR6 ,
output VAR8 ,
output VAR2 ,
input VAR3,
input VAR7 ,
input VAR1 ,
input VAR10 ,
input VAR4 ,
input VAR5 ,
input VAR9
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai.symbol.v | 1,391 | module MODULE1 (
input VAR10,
input VAR8,
input VAR3,
input VAR4,
input VAR1,
output VAR2
);
supply1 VAR9;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_video_camera_decoder.v | 7,480 | module MODULE1 (
clk,
reset,
VAR14,
VAR2,
VAR4,
ready,
VAR1,
VAR10,
VAR15,
valid
);
parameter VAR12 = 9;
input clk;
input reset;
input [VAR12: 0] VAR14;
input VAR2;
input VAR4;
input ready;
output reg [VAR12: 0] VAR1;
output reg VAR10;
output reg VAR15;
output reg valid;
wire VAR9;
reg [VAR12: 0] VAR13;
reg VAR8;
reg VAR6;
reg VAR11;
reg [VAR12: 0] VAR5;
reg VAR3;
reg VAR16;
reg VAR7;
always @ (posedge clk)
begin
VAR13 <= VAR14;
VAR8 <= VAR2;
VAR6 <= VAR4;
end
always @ (posedge clk)
begin
if (reset)
begin
VAR1 <= 'h0;
VAR10 <= 1'b0;
VAR15 <= 1'b0;
valid <= 1'b0;
end
else if (VAR9)
begin
VAR1 <= VAR5;
VAR10 <= VAR3;
VAR15 <= VAR16;
valid <= VAR7;
end
else if (ready)
valid <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
VAR11 <= 1'b0;
end
else if (~VAR6)
VAR11 <= 1'b1;
else if (VAR8 & VAR6)
VAR11 <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
begin
VAR5 <= 'h0;
VAR3 <= 1'b0;
VAR16 <= 1'b0;
VAR7 <= 1'b0;
end
else if (VAR9)
begin
VAR5 <= VAR13;
VAR3 <= VAR11;
VAR16 <= ~VAR6;
VAR7 <= VAR8 & VAR6;
end
else if (~VAR6)
begin
VAR16 <= ~VAR6;
end
end
assign VAR9 = (ready | ~valid) &
((VAR8 & VAR6) |
((VAR3 | VAR16) & VAR7));
endmodule | gpl-2.0 |
jmahler/EECE344-Digital_System_Design | lab02/CPLD/main.v | 2,330 | module MODULE1(
input wire VAR15,
input wire VAR10,
input wire VAR12,
input wire VAR13,
output wire VAR4,
output wire [7:0] VAR6,
input wire [7:0] VAR3
);
VAR7 VAR1(.VAR7(VAR15));
parameter VAR9=7;
wire [VAR9:0] VAR5; assign VAR5 = ~(VAR3);
reg [VAR9:0] VAR8;
wire [VAR9:0] VAR2;
reg [VAR9:0] VAR14;
assign VAR6 = ~(VAR14);
assign VAR2 = {VAR8[VAR9-1:0], VAR11};
assign VAR4 = VAR8[VAR9] & ~(VAR10);
reg VAR11;
always @(posedge VAR12) begin
VAR11 <= VAR13;
end
always @(negedge VAR12 or negedge VAR15) begin
if (~VAR15) begin
VAR8 <= 8'b0;
VAR14 <= 8'b0;
end else begin
if (VAR10) begin
VAR8 <= VAR5; VAR14 <= VAR2; end else begin
VAR8 <= VAR2;
end
end
end
endmodule | gpl-3.0 |
rurume/openrisc_vision_hardware | ISE/or1200_freeze.v | 8,060 | module MODULE1(
clk, rst,
VAR18, VAR15, VAR19, VAR5, VAR20,
VAR16, VAR1, VAR3,
VAR21, VAR10,
VAR7, VAR2, VAR8, VAR17, VAR12,
VAR6, VAR11
);
input clk;
input rst;
input [VAR14-1:0] VAR18;
input VAR15;
input VAR19;
input VAR5;
input VAR20;
input VAR16;
input VAR21;
input VAR10;
input VAR1;
input VAR3;
output VAR7;
output VAR2;
output VAR8;
output VAR17;
output VAR12;
input VAR6;
input VAR11;
wire VAR13;
reg [VAR14-1:0] VAR4;
reg VAR9;
assign VAR7 = VAR1 | VAR9;
assign VAR2 = VAR8 | VAR19;
assign VAR8 = (VAR5 | (~VAR16 & VAR20) | VAR13 | VAR21) | VAR1 | VAR3;
assign VAR17 = VAR12;
assign VAR12 = (VAR5 | (~VAR16 & VAR20) | VAR13) | VAR1 | VAR3 | VAR10;
always @(posedge clk or posedge rst)
if (rst)
VAR9 <= 1'b0;
else if (VAR6 | VAR11)
VAR9 <= VAR15;
else if (!VAR15)
VAR9 <= 1'b0;
assign VAR13 = |VAR4;
always @(posedge clk or posedge rst)
if (rst)
VAR4 <= 2'b00;
else if (|VAR4)
VAR4 <= VAR4 - 2'd1;
else if (|VAR18 & !VAR17)
VAR4 <= VAR18;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn.functional.pp.v | 1,872 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR8,
VAR1,
VAR13,
VAR10 ,
VAR7
);
output VAR5 ;
input VAR3 ;
input VAR8;
input VAR1;
input VAR13;
input VAR10 ;
input VAR7 ;
wire VAR4 ;
wire VAR6;
VAR9 VAR2 (VAR4 , VAR3, VAR1, VAR13 );
VAR9 VAR11 (VAR6, VAR8, VAR1, VAR13 );
notif0 VAR12 (VAR5 , VAR4, VAR6);
endmodule | apache-2.0 |
parallella/oh | parallella/hdl/pi2c.v | 1,410 | module MODULE1 (
VAR4, VAR9,
VAR2, VAR12,
VAR11, VAR18, VAR1, VAR10
);
parameter VAR22 = 0;
input VAR11;
input VAR18;
output VAR4;
input VAR1;
input VAR10;
output VAR9;
inout VAR2;
inout VAR12;
generate
if(VAR22==1) begin
wire VAR2 = VAR18 ? 1'VAR6: VAR11;
wire VAR4 = VAR2;
wire VAR12 = VAR10 ? 1'VAR6 : VAR1;
wire VAR9 = VAR12;
end
else
begin
VAR8 #(
.VAR13(8), .VAR19("VAR5"), .VAR14("VAR3"), .VAR21("VAR24") ) VAR16 (
.VAR7(VAR4), .VAR20(VAR2), .VAR15(VAR11), .VAR23(VAR18) );
VAR8 #(
.VAR13(8),
.VAR19("VAR5"),
.VAR14("VAR3"),
.VAR21("VAR24")
) VAR17 (
.VAR7(VAR9),
.VAR20(VAR12),
.VAR15(VAR1),
.VAR23(VAR10)
);
end
endgenerate
endmodule | mit |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/Raster_Laser_Projector_Video_In_avalon_st_adapter.v | 6,847 | module MODULE1 #(
parameter VAR24 = 8,
parameter VAR6 = 1,
parameter VAR20 = 8,
parameter VAR27 = 1,
parameter VAR2 = 0,
parameter VAR29 = 0,
parameter VAR25 = 1,
parameter VAR21 = 1,
parameter VAR16 = 0,
parameter VAR13 = 8,
parameter VAR11 = 0,
parameter VAR14 = 0,
parameter VAR28 = 0,
parameter VAR23 = 1,
parameter VAR1 = 1,
parameter VAR3 = 0
) (
input wire VAR7, input wire VAR26, input wire [7:0] VAR17, input wire VAR5, output wire VAR10, input wire VAR19, input wire VAR18, input wire VAR22, output wire [7:0] VAR8, output wire VAR12, input wire VAR15, output wire VAR4, output wire VAR9 );
generate
if (VAR24 != 8)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | gpl-3.0 |
BigEd/beeb816 | pcb/bufboard.v | 3,033 | module MODULE1();
supply0 VAR72;
supply1 VAR85;
supply1 VAR74;
wire VAR7, VAR55, VAR82, VAR46, VAR73, VAR64, VAR6, VAR2;
wire VAR36, VAR68, VAR61, VAR21, VAR71, VAR59, VAR15, VAR79;
wire VAR33, VAR93, VAR84, VAR69, VAR5, VAR88, VAR11, VAR98;
wire VAR90, VAR103, VAR75, VAR76, VAR101, VAR4, VAR9 ;
wire VAR99, VAR27, VAR77, VAR24, VAR87, VAR8;
wire VAR83, VAR26, VAR62, VAR13 ;
VAR58 VAR92 ( .VAR41(VAR44),.VAR104(VAR85) );
VAR45 VAR43 (
.VAR31(VAR72),
.VAR78(VAR9),
.VAR48(VAR77),
.VAR30(VAR101),
.VAR63(),
.VAR19(VAR4),
.sync(VAR99),
.VAR51(VAR44),
.VAR100(VAR36),
.VAR40(VAR68),
.VAR38(VAR61),
.VAR25(VAR21),
.VAR23(VAR71),
.VAR10(VAR59),
.VAR1(VAR15),
.VAR94(VAR79),
.VAR86(VAR33),
.VAR95(VAR93),
.VAR34(VAR84),
.VAR81(VAR69),
.VAR56(VAR72),
.VAR14(VAR5),
.VAR32(VAR88),
.VAR42(VAR11),
.VAR16(VAR98),
.VAR80(VAR2),
.VAR65(VAR6),
.VAR47(VAR64),
.VAR67(VAR73),
.VAR102(VAR46),
.VAR22(VAR82),
.VAR29(VAR55),
.VAR35(VAR7),
.VAR54(VAR90),
.VAR18(),
.VAR96(),
.VAR12(VAR27),
.VAR66(),
.VAR53(VAR24),
.VAR89(VAR76)
);
VAR37 VAR70(
.VAR41(VAR72), .VAR104(VAR72),
.VAR3(VAR91), .VAR39(VAR52),
.VAR57(VAR74), .VAR49(VAR74),
.VAR17(VAR74), .VAR97(VAR74),
);
VAR20 VAR50(
.VAR41(VAR72),
.VAR104(VAR72),
.VAR3(VAR72),
.VAR39(VAR72)
);
VAR60 VAR28 (
.VAR41(VAR72), .VAR104(VAR72),
.VAR3(VAR13), .VAR39(VAR26),
.VAR57(VAR83), .VAR49(VAR62),
.VAR17(VAR74), .VAR97(),
);
endmodule | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.symbol.v | 1,493 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR7 ,
input VAR3,
input VAR1,
input VAR10
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_us_1/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v | 4,197 | module MODULE1 (
input wire clk ,
input wire reset ,
output wire VAR13 ,
input wire VAR9 ,
input wire [7:0] VAR6 ,
output wire VAR12 ,
input wire VAR3 ,
output wire VAR17 ,
input wire VAR16 ,
input wire VAR11 ,
output wire VAR1 ,
output wire VAR7
);
localparam VAR10 = 2'b00;
localparam VAR14 = 2'b01;
localparam VAR4 = 2'b10;
localparam VAR8 = 2'b11;
reg [1:0] state;
reg [1:0] VAR15;
reg [1:0] VAR5;
reg [7:0] VAR2;
always @(posedge clk) begin
if (reset) begin
state <= VAR10;
VAR15 <= VAR10;
VAR2 <= 0;
end else begin
state <= VAR5;
VAR15 <= state;
VAR2 <= VAR6;
end
end
always @( * ) begin
VAR5 = state;
case (state)
VAR10:
if (VAR9 & VAR11) begin
VAR5 = VAR14;
end else begin
VAR5 = state;
end
VAR14:
if (~VAR11 & VAR3 & VAR16) begin
VAR5 = VAR4;
end else if (VAR3 & ~VAR16)begin
VAR5 = VAR8;
end else if (VAR3 & VAR16) begin
VAR5 = VAR14;
end else begin
VAR5 = state;
end
VAR4:
if (VAR11) begin
VAR5 = VAR14;
end else begin
VAR5 = state;
end
VAR8:
VAR5 = VAR10;
default:
VAR5 = VAR10;
endcase
end
assign VAR12 = (state == VAR14);
assign VAR17 = VAR3 && (state == VAR14);
assign VAR7 = VAR17;
assign VAR1 = (state == VAR10);
assign VAR13 = ((state == VAR14) || (state == VAR8)) && (VAR5 == VAR10);
endmodule | mit |
perillamint/humbleverilogcalc | sixbitdiv.v | 2,242 | module MODULE1 (VAR14, VAR25, VAR1, VAR20, VAR2);
input[5:0] VAR14;
input[5:0] VAR25;
output[5:0] VAR1;
output[5:0] VAR20;
output VAR2;
wire[5:0] VAR6;
wire[5:0] VAR13;
wire[5:0] VAR5;
wire[5:0] VAR12;
wire[5:0] VAR23;
wire[5:0] VAR21;
wire[5:0] VAR10;
wire[5:0] VAR11;
wire[5:0] VAR3;
wire[5:0] VAR22;
wire[5:0] VAR26;
wire[5:0] VAR8;
wire[5:0] VAR16;
wire[5:0] VAR18;
wire[5:0] VAR28;
wire[5:0] VAR4;
wire VAR9;
nor (VAR9, VAR25[5], VAR25[4], VAR25[3], VAR25[2], VAR25[1], VAR25[0]);
assign VAR6 = VAR14[5] ? ~(VAR14 - 1) : VAR14;
assign VAR13 = VAR25[5] ? ~(VAR25 - 1) : VAR25;
assign VAR26 = VAR6;
assign VAR5[5] = 0;
assign VAR4[0] = 0;
VAR24 VAR15 (VAR26, (VAR13 << 4) & 'h1F, VAR21, VAR4[1]);
nor (VAR5[4], VAR21[5], VAR4[1], VAR13[5], VAR13[4], VAR13[3], VAR13[2], VAR13[1]);
assign VAR8 = VAR5[4] ? VAR21 : VAR26;
VAR24 VAR17 (VAR8, (VAR13 << 3) & 'h1F, VAR10, VAR4[2]);
nor (VAR5[3], VAR10[5], VAR4[2], VAR13[5], VAR13[4], VAR13[3], VAR13[2]);
assign VAR16 = VAR5[3] ? VAR10 : VAR8;
VAR24 VAR19 (VAR16, (VAR13 << 2) & 'h1F, VAR11, VAR4[3]);
nor (VAR5[2], VAR11[5], VAR4[3], VAR13[5], VAR13[4], VAR13[3]);
assign VAR18 = VAR5[2] ? VAR11 : VAR16;
VAR24 VAR27 (VAR18, (VAR13 << 1) & 'h1F, VAR3, VAR4[4]);
nor (VAR5[1], VAR3[5], VAR4[4], VAR13[5], VAR13[4]);
assign VAR28 = VAR5[1] ? VAR3 : VAR18;
VAR24 VAR7 (VAR28, (VAR13) & 'h1F, VAR22, VAR4[5]);
nor (VAR5[0], VAR22[5], VAR4[5], VAR13[5]);
assign VAR12 = VAR5[0] ? VAR22 : VAR28;
assign VAR2 = |VAR4 || VAR9;
assign VAR1 = (VAR14[5] ^ VAR25[5]) ? ~VAR5 + 1 : VAR5;
assign VAR20 = VAR14[5] ? ~VAR12 + 1 : VAR12;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0p/sky130_fd_sc_lp__iso0p.behavioral.pp.v | 2,034 | module MODULE1 (
VAR7 ,
VAR13 ,
VAR15,
VAR12,
VAR2 ,
VAR9 ,
VAR4
);
output VAR7 ;
input VAR13 ;
input VAR15;
input VAR12;
input VAR2 ;
input VAR9 ;
input VAR4 ;
wire VAR6 ;
wire VAR1 ;
wire VAR5;
not VAR11 (VAR6 , VAR15 );
VAR3 VAR14 (VAR1 , VAR13, VAR12, VAR2 );
VAR3 VAR10 (VAR5, VAR6, VAR12, VAR2 );
and VAR8 (VAR7 , VAR1, VAR5);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxtp/sky130_fd_sc_hs__sdfxtp.pp.blackbox.v | 1,310 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR7 ,
VAR6,
VAR1
);
input VAR3 ;
input VAR2 ;
output VAR5 ;
input VAR4 ;
input VAR7 ;
input VAR6;
input VAR1;
endmodule | apache-2.0 |
aabdelfattah/alhaitham-hardware | v/rgb2hsv.v | 15,713 | module MODULE1(
clk,
VAR14,
rst,
VAR4,
VAR7
);
input clk, rst;
input[31:0] VAR4 ;output[31:0] VAR7;
input VAR14 ;
reg[31:0] VAR7 ;
reg[7:0] VAR13[2:0]; reg[19:0] VAR10 ;
wire[7:0] VAR16;
reg[31:0] VAR8 ;
reg signed [9:0] VAR11;reg[15:0] VAR18, VAR1;
reg[15:0] VAR12, VAR5;
wire[15:0] VAR20, VAR17;
reg[2:0] VAR9;
reg[2:0] VAR3;
wire[7:0] VAR19 ;
wire[7:0] VAR2;
wire[7:0] VAR15 ;
wire[7:0] VAR6 ;
assign VAR16 = VAR2 - VAR6;
assign VAR19 = (VAR4[15:8] > VAR4[23:16]) ? VAR4[15:8] : VAR4[23:16];
assign VAR2 = (VAR19 > VAR4[31:24]) ? VAR19 : VAR4[31:24];
assign VAR15 = (VAR4[15:8] < VAR4[23:16]) ? VAR4[15:8] : VAR4[23:16];
assign VAR6 = (VAR15 < VAR4[31:24]) ? VAR15 : VAR4[31:24];
always @ (posedge clk )
begin
if(rst == 1'b1)
begin
VAR7<=0;
end
else if(VAR14 == 1'b1)
begin
VAR7[15:8] = VAR2 ;
case (VAR7[15:8])
8'd0 : VAR10=20'd0;
8'd1 : VAR10=20'd1044480;
8'd2 : VAR10=20'd522240;
8'd3 : VAR10=20'd348160;
8'd4 : VAR10=20'd261120;
8'd5 : VAR10=20'd208896;
8'd6 : VAR10=20'd174080;
8'd7 : VAR10=20'd149211;
8'd8 : VAR10=20'd130560;
8'd9 : VAR10=20'd116053;
8'd10 : VAR10=20'd104448;
8'd11 : VAR10=20'd94953;
8'd12 : VAR10=20'd87040;
8'd13 : VAR10=20'd80345;
8'd14 : VAR10=20'd74606;
8'd15 : VAR10=20'd69632;
8'd16 : VAR10=20'd65280;
8'd17 : VAR10=20'd61440;
8'd18 : VAR10=20'd58027;
8'd19 : VAR10=20'd54973;
8'd20 : VAR10=20'd52224;
8'd21 : VAR10=20'd49737;
8'd22 : VAR10=20'd47476;
8'd23 : VAR10=20'd45412;
8'd24 : VAR10=20'd43520;
8'd25 : VAR10=20'd41779;
8'd26 : VAR10=20'd40172;
8'd27 : VAR10=20'd38684;
8'd28 : VAR10=20'd37303;
8'd29 : VAR10=20'd36017;
8'd30 : VAR10=20'd34816;
8'd31 : VAR10=20'd33693;
8'd32 : VAR10=20'd32640;
8'd33 : VAR10=20'd31651;
8'd34 : VAR10=20'd30720;
8'd35 : VAR10=20'd29842;
8'd36 : VAR10=20'd29013;
8'd37 : VAR10=20'd28229;
8'd38 : VAR10=20'd27486;
8'd39 : VAR10=20'd26782;
8'd40 : VAR10=20'd26112;
8'd41 : VAR10=20'd25475;
8'd42 : VAR10=20'd24869;
8'd43 : VAR10=20'd24290;
8'd44 : VAR10=20'd23738;
8'd45 : VAR10=20'd23211;
8'd46 : VAR10=20'd22706;
8'd47 : VAR10=20'd22223;
8'd48 : VAR10=20'd21760;
8'd49 : VAR10=20'd21316;
8'd50 : VAR10=20'd20890;
8'd51 : VAR10=20'd20480;
8'd52 : VAR10=20'd20086;
8'd53 : VAR10=20'd19707;
8'd54 : VAR10=20'd19342;
8'd55 : VAR10=20'd18991;
8'd56 : VAR10=20'd18651;
8'd57 : VAR10=20'd18324;
8'd58 : VAR10=20'd18008;
8'd59 : VAR10=20'd17703;
8'd60 : VAR10=20'd17408;
8'd61 : VAR10=20'd17123;
8'd62 : VAR10=20'd16846;
8'd63 : VAR10=20'd16579;
8'd64 : VAR10=20'd16320;
8'd65 : VAR10=20'd16069;
8'd66 : VAR10=20'd15825;
8'd67 : VAR10=20'd15589;
8'd68 : VAR10=20'd15360;
8'd69 : VAR10=20'd15137;
8'd70 : VAR10=20'd14921;
8'd71 : VAR10=20'd14711;
8'd72 : VAR10=20'd14507;
8'd73 : VAR10=20'd14308;
8'd74 : VAR10=20'd14115;
8'd75 : VAR10=20'd13926;
8'd76 : VAR10=20'd13743;
8'd77 : VAR10=20'd13565;
8'd78 : VAR10=20'd13391;
8'd79 : VAR10=20'd13221;
8'd80 : VAR10=20'd13056;
8'd81 : VAR10=20'd12895;
8'd82 : VAR10=20'd12738;
8'd83 : VAR10=20'd12584;
8'd84 : VAR10=20'd12434;
8'd85 : VAR10=20'd12288;
8'd86 : VAR10=20'd12145;
8'd87 : VAR10=20'd12006;
8'd88 : VAR10=20'd11869;
8'd89 : VAR10=20'd11736;
8'd90 : VAR10=20'd11605;
8'd91 : VAR10=20'd11478;
8'd92 : VAR10=20'd11353;
8'd93 : VAR10=20'd11231;
8'd94 : VAR10=20'd11111;
8'd95 : VAR10=20'd10995;
8'd96 : VAR10=20'd10880;
8'd97 : VAR10=20'd10768;
8'd98 : VAR10=20'd10658;
8'd99 : VAR10=20'd10550;
8'd100 : VAR10=20'd10445;
8'd101 : VAR10=20'd10341;
8'd102 : VAR10=20'd10240;
8'd103 : VAR10=20'd10141;
8'd104 : VAR10=20'd10043;
8'd105 : VAR10=20'd9947;
8'd106 : VAR10=20'd9854;
8'd107 : VAR10=20'd9761;
8'd108 : VAR10=20'd9671;
8'd109 : VAR10=20'd9582;
8'd110 : VAR10=20'd9495;
8'd111 : VAR10=20'd9410;
8'd112 : VAR10=20'd9326;
8'd113 : VAR10=20'd9243;
8'd114 : VAR10=20'd9162;
8'd115 : VAR10=20'd9082;
8'd116 : VAR10=20'd9004;
8'd117 : VAR10=20'd8927;
8'd118 : VAR10=20'd8852;
8'd119 : VAR10=20'd8777;
8'd120 : VAR10=20'd8704;
8'd121 : VAR10=20'd8632;
8'd122 : VAR10=20'd8561;
8'd123 : VAR10=20'd8492;
8'd124 : VAR10=20'd8423;
8'd125 : VAR10=20'd8356;
8'd126 : VAR10=20'd8290;
8'd127 : VAR10=20'd8224;
8'd128 : VAR10=20'd8160;
8'd129 : VAR10=20'd8097;
8'd130 : VAR10=20'd8034;
8'd131 : VAR10=20'd7973;
8'd132 : VAR10=20'd7913;
8'd133 : VAR10=20'd7853;
8'd134 : VAR10=20'd7795;
8'd135 : VAR10=20'd7737;
8'd136 : VAR10=20'd7680;
8'd137 : VAR10=20'd7624;
8'd138 : VAR10=20'd7569;
8'd139 : VAR10=20'd7514;
8'd140 : VAR10=20'd7461;
8'd141 : VAR10=20'd7408;
8'd142 : VAR10=20'd7355;
8'd143 : VAR10=20'd7304;
8'd144 : VAR10=20'd7253;
8'd145 : VAR10=20'd7203;
8'd146 : VAR10=20'd7154;
8'd147 : VAR10=20'd7105;
8'd148 : VAR10=20'd7057;
8'd149 : VAR10=20'd7010;
8'd150 : VAR10=20'd6963;
8'd151 : VAR10=20'd6917;
8'd152 : VAR10=20'd6872;
8'd153 : VAR10=20'd6827;
8'd154 : VAR10=20'd6782;
8'd155 : VAR10=20'd6739;
8'd156 : VAR10=20'd6695;
8'd157 : VAR10=20'd6653;
8'd158 : VAR10=20'd6611;
8'd159 : VAR10=20'd6569;
8'd160 : VAR10=20'd6528;
8'd161 : VAR10=20'd6487;
8'd162 : VAR10=20'd6447;
8'd163 : VAR10=20'd6408;
8'd164 : VAR10=20'd6369;
8'd165 : VAR10=20'd6330;
8'd166 : VAR10=20'd6292;
8'd167 : VAR10=20'd6254;
8'd168 : VAR10=20'd6217;
8'd169 : VAR10=20'd6180;
8'd170 : VAR10=20'd6144;
8'd171 : VAR10=20'd6108;
8'd172 : VAR10=20'd6073;
8'd173 : VAR10=20'd6037;
8'd174 : VAR10=20'd6003;
8'd175 : VAR10=20'd5968;
8'd176 : VAR10=20'd5935;
8'd177 : VAR10=20'd5901;
8'd178 : VAR10=20'd5868;
8'd179 : VAR10=20'd5835;
8'd180 : VAR10=20'd5803;
8'd181 : VAR10=20'd5771;
8'd182 : VAR10=20'd5739;
8'd183 : VAR10=20'd5708;
8'd184 : VAR10=20'd5677;
8'd185 : VAR10=20'd5646;
8'd186 : VAR10=20'd5615;
8'd187 : VAR10=20'd5585;
8'd188 : VAR10=20'd5556;
8'd189 : VAR10=20'd5526;
8'd190 : VAR10=20'd5497;
8'd191 : VAR10=20'd5468;
8'd192 : VAR10=20'd5440;
8'd193 : VAR10=20'd5412;
8'd194 : VAR10=20'd5384;
8'd195 : VAR10=20'd5356;
8'd196 : VAR10=20'd5329;
8'd197 : VAR10=20'd5302;
8'd198 : VAR10=20'd5275;
8'd199 : VAR10=20'd5249;
8'd200 : VAR10=20'd5222;
8'd201 : VAR10=20'd5196;
8'd202 : VAR10=20'd5171;
8'd203 : VAR10=20'd5145;
8'd204 : VAR10=20'd5120;
8'd205 : VAR10=20'd5095;
8'd206 : VAR10=20'd5070;
8'd207 : VAR10=20'd5046;
8'd208 : VAR10=20'd5022;
8'd209 : VAR10=20'd4998;
8'd210 : VAR10=20'd4974;
8'd211 : VAR10=20'd4950;
8'd212 : VAR10=20'd4927;
8'd213 : VAR10=20'd4904;
8'd214 : VAR10=20'd4881;
8'd215 : VAR10=20'd4858;
8'd216 : VAR10=20'd4836;
8'd217 : VAR10=20'd4813;
8'd218 : VAR10=20'd4791;
8'd219 : VAR10=20'd4769;
8'd220 : VAR10=20'd4748;
8'd221 : VAR10=20'd4726;
8'd222 : VAR10=20'd4705;
8'd223 : VAR10=20'd4684;
8'd224 : VAR10=20'd4663;
8'd225 : VAR10=20'd4642;
8'd226 : VAR10=20'd4622;
8'd227 : VAR10=20'd4601;
8'd228 : VAR10=20'd4581;
8'd229 : VAR10=20'd4561;
8'd230 : VAR10=20'd4541;
8'd231 : VAR10=20'd4522;
8'd232 : VAR10=20'd4502;
8'd233 : VAR10=20'd4483;
8'd234 : VAR10=20'd4464;
8'd235 : VAR10=20'd4445;
8'd236 : VAR10=20'd4426;
8'd237 : VAR10=20'd4407;
8'd238 : VAR10=20'd4389;
8'd239 : VAR10=20'd4370;
8'd240 : VAR10=20'd4352;
8'd241 : VAR10=20'd4334;
8'd242 : VAR10=20'd4316;
8'd243 : VAR10=20'd4298;
8'd244 : VAR10=20'd4281;
8'd245 : VAR10=20'd4263;
8'd246 : VAR10=20'd4246;
8'd247 : VAR10=20'd4229;
8'd248 : VAR10=20'd4212;
8'd249 : VAR10=20'd4195;
8'd250 : VAR10=20'd4178;
8'd251 : VAR10=20'd4161;
8'd252 : VAR10=20'd4145;
8'd253 : VAR10=20'd4128;
8'd254 : VAR10=20'd4112;
8'd255 : VAR10=20'd4096;
endcase
VAR7[23:16] = ((VAR16 * VAR10)>>12) ;
case (VAR16)
8'd0 : VAR8=32'd0;
8'd1 : VAR8=32'd1044480;
8'd2 : VAR8=32'd522240;
8'd3 : VAR8=32'd348160;
8'd4 : VAR8=32'd261120;
8'd5 : VAR8=32'd208896;
8'd6 : VAR8=32'd174080;
8'd7 : VAR8=32'd149211;
8'd8 : VAR8=32'd130560;
8'd9 : VAR8=32'd116053;
8'd10 : VAR8=32'd104448;
8'd11 : VAR8=32'd94953;
8'd12 : VAR8=32'd87040;
8'd13 : VAR8=32'd80345;
8'd14 : VAR8=32'd74606;
8'd15 : VAR8=32'd69632;
8'd16 : VAR8=32'd65280;
8'd17 : VAR8=32'd61440;
8'd18 : VAR8=32'd58027;
8'd19 : VAR8=32'd54973;
8'd20 : VAR8=32'd52224;
8'd21 : VAR8=32'd49737;
8'd22 : VAR8=32'd47476;
8'd23 : VAR8=32'd45412;
8'd24 : VAR8=32'd43520;
8'd25 : VAR8=32'd41779;
8'd26 : VAR8=32'd40172;
8'd27 : VAR8=32'd38684;
8'd28 : VAR8=32'd37303;
8'd29 : VAR8=32'd36017;
8'd30 : VAR8=32'd34816;
8'd31 : VAR8=32'd33693;
8'd32 : VAR8=32'd32640;
8'd33 : VAR8=32'd31651;
8'd34 : VAR8=32'd30720;
8'd35 : VAR8=32'd29842;
8'd36 : VAR8=32'd29013;
8'd37 : VAR8=32'd28229;
8'd38 : VAR8=32'd27486;
8'd39 : VAR8=32'd26782;
8'd40 : VAR8=32'd26112;
8'd41 : VAR8=32'd25475;
8'd42 : VAR8=32'd24869;
8'd43 : VAR8=32'd24290;
8'd44 : VAR8=32'd23738;
8'd45 : VAR8=32'd23211;
8'd46 : VAR8=32'd22706;
8'd47 : VAR8=32'd22223;
8'd48 : VAR8=32'd21760;
8'd49 : VAR8=32'd21316;
8'd50 : VAR8=32'd20890;
8'd51 : VAR8=32'd20480;
8'd52 : VAR8=32'd20086;
8'd53 : VAR8=32'd19707;
8'd54 : VAR8=32'd19342;
8'd55 : VAR8=32'd18991;
8'd56 : VAR8=32'd18651;
8'd57 : VAR8=32'd18324;
8'd58 : VAR8=32'd18008;
8'd59 : VAR8=32'd17703;
8'd60 : VAR8=32'd17408;
8'd61 : VAR8=32'd17123;
8'd62 : VAR8=32'd16846;
8'd63 : VAR8=32'd16579;
8'd64 : VAR8=32'd16320;
8'd65 : VAR8=32'd16069;
8'd66 : VAR8=32'd15825;
8'd67 : VAR8=32'd15589;
8'd68 : VAR8=32'd15360;
8'd69 : VAR8=32'd15137;
8'd70 : VAR8=32'd14921;
8'd71 : VAR8=32'd14711;
8'd72 : VAR8=32'd14507;
8'd73 : VAR8=32'd14308;
8'd74 : VAR8=32'd14115;
8'd75 : VAR8=32'd13926;
8'd76 : VAR8=32'd13743;
8'd77 : VAR8=32'd13565;
8'd78 : VAR8=32'd13391;
8'd79 : VAR8=32'd13221;
8'd80 : VAR8=32'd13056;
8'd81 : VAR8=32'd12895;
8'd82 : VAR8=32'd12738;
8'd83 : VAR8=32'd12584;
8'd84 : VAR8=32'd12434;
8'd85 : VAR8=32'd12288;
8'd86 : VAR8=32'd12145;
8'd87 : VAR8=32'd12006;
8'd88 : VAR8=32'd11869;
8'd89 : VAR8=32'd11736;
8'd90 : VAR8=32'd11605;
8'd91 : VAR8=32'd11478;
8'd92 : VAR8=32'd11353;
8'd93 : VAR8=32'd11231;
8'd94 : VAR8=32'd11111;
8'd95 : VAR8=32'd10995;
8'd96 : VAR8=32'd10880;
8'd97 : VAR8=32'd10768;
8'd98 : VAR8=32'd10658;
8'd99 : VAR8=32'd10550;
8'd100 : VAR8=32'd10445;
8'd101 : VAR8=32'd10341;
8'd102 : VAR8=32'd10240;
8'd103 : VAR8=32'd10141;
8'd104 : VAR8=32'd10043;
8'd105 : VAR8=32'd9947;
8'd106 : VAR8=32'd9854;
8'd107 : VAR8=32'd9761;
8'd108 : VAR8=32'd9671;
8'd109 : VAR8=32'd9582;
8'd110 : VAR8=32'd9495;
8'd111 : VAR8=32'd9410;
8'd112 : VAR8=32'd9326;
8'd113 : VAR8=32'd9243;
8'd114 : VAR8=32'd9162;
8'd115 : VAR8=32'd9082;
8'd116 : VAR8=32'd9004;
8'd117 : VAR8=32'd8927;
8'd118 : VAR8=32'd8852;
8'd119 : VAR8=32'd8777;
8'd120 : VAR8=32'd8704;
8'd121 : VAR8=32'd8632;
8'd122 : VAR8=32'd8561;
8'd123 : VAR8=32'd8492;
8'd124 : VAR8=32'd8423;
8'd125 : VAR8=32'd8356;
8'd126 : VAR8=32'd8290;
8'd127 : VAR8=32'd8224;
8'd128 : VAR8=32'd8160;
8'd129 : VAR8=32'd8097;
8'd130 : VAR8=32'd8034;
8'd131 : VAR8=32'd7973;
8'd132 : VAR8=32'd7913;
8'd133 : VAR8=32'd7853;
8'd134 : VAR8=32'd7795;
8'd135 : VAR8=32'd7737;
8'd136 : VAR8=32'd7680;
8'd137 : VAR8=32'd7624;
8'd138 : VAR8=32'd7569;
8'd139 : VAR8=32'd7514;
8'd140 : VAR8=32'd7461;
8'd141 : VAR8=32'd7408;
8'd142 : VAR8=32'd7355;
8'd143 : VAR8=32'd7304;
8'd144 : VAR8=32'd7253;
8'd145 : VAR8=32'd7203;
8'd146 : VAR8=32'd7154;
8'd147 : VAR8=32'd7105;
8'd148 : VAR8=32'd7057;
8'd149 : VAR8=32'd7010;
8'd150 : VAR8=32'd6963;
8'd151 : VAR8=32'd6917;
8'd152 : VAR8=32'd6872;
8'd153 : VAR8=32'd6827;
8'd154 : VAR8=32'd6782;
8'd155 : VAR8=32'd6739;
8'd156 : VAR8=32'd6695;
8'd157 : VAR8=32'd6653;
8'd158 : VAR8=32'd6611;
8'd159 : VAR8=32'd6569;
8'd160 : VAR8=32'd6528;
8'd161 : VAR8=32'd6487;
8'd162 : VAR8=32'd6447;
8'd163 : VAR8=32'd6408;
8'd164 : VAR8=32'd6369;
8'd165 : VAR8=32'd6330;
8'd166 : VAR8=32'd6292;
8'd167 : VAR8=32'd6254;
8'd168 : VAR8=32'd6217;
8'd169 : VAR8=32'd6180;
8'd170 : VAR8=32'd6144;
8'd171 : VAR8=32'd6108;
8'd172 : VAR8=32'd6073;
8'd173 : VAR8=32'd6037;
8'd174 : VAR8=32'd6003;
8'd175 : VAR8=32'd5968;
8'd176 : VAR8=32'd5935;
8'd177 : VAR8=32'd5901;
8'd178 : VAR8=32'd5868;
8'd179 : VAR8=32'd5835;
8'd180 : VAR8=32'd5803;
8'd181 : VAR8=32'd5771;
8'd182 : VAR8=32'd5739;
8'd183 : VAR8=32'd5708;
8'd184 : VAR8=32'd5677;
8'd185 : VAR8=32'd5646;
8'd186 : VAR8=32'd5615;
8'd187 : VAR8=32'd5585;
8'd188 : VAR8=32'd5556;
8'd189 : VAR8=32'd5526;
8'd190 : VAR8=32'd5497;
8'd191 : VAR8=32'd5468;
8'd192 : VAR8=32'd5440;
8'd193 : VAR8=32'd5412;
8'd194 : VAR8=32'd5384;
8'd195 : VAR8=32'd5356;
8'd196 : VAR8=32'd5329;
8'd197 : VAR8=32'd5302;
8'd198 : VAR8=32'd5275;
8'd199 : VAR8=32'd5249;
8'd200 : VAR8=32'd5222;
8'd201 : VAR8=32'd5196;
8'd202 : VAR8=32'd5171;
8'd203 : VAR8=32'd5145;
8'd204 : VAR8=32'd5120;
8'd205 : VAR8=32'd5095;
8'd206 : VAR8=32'd5070;
8'd207 : VAR8=32'd5046;
8'd208 : VAR8=32'd5022;
8'd209 : VAR8=32'd4998;
8'd210 : VAR8=32'd4974;
8'd211 : VAR8=32'd4950;
8'd212 : VAR8=32'd4927;
8'd213 : VAR8=32'd4904;
8'd214 : VAR8=32'd4881;
8'd215 : VAR8=32'd4858;
8'd216 : VAR8=32'd4836;
8'd217 : VAR8=32'd4813;
8'd218 : VAR8=32'd4791;
8'd219 : VAR8=32'd4769;
8'd220 : VAR8=32'd4748;
8'd221 : VAR8=32'd4726;
8'd222 : VAR8=32'd4705;
8'd223 : VAR8=32'd4684;
8'd224 : VAR8=32'd4663;
8'd225 : VAR8=32'd4642;
8'd226 : VAR8=32'd4622;
8'd227 : VAR8=32'd4601;
8'd228 : VAR8=32'd4581;
8'd229 : VAR8=32'd4561;
8'd230 : VAR8=32'd4541;
8'd231 : VAR8=32'd4522;
8'd232 : VAR8=32'd4502;
8'd233 : VAR8=32'd4483;
8'd234 : VAR8=32'd4464;
8'd235 : VAR8=32'd4445;
8'd236 : VAR8=32'd4426;
8'd237 : VAR8=32'd4407;
8'd238 : VAR8=32'd4389;
8'd239 : VAR8=32'd4370;
8'd240 : VAR8=32'd4352;
8'd241 : VAR8=32'd4334;
8'd242 : VAR8=32'd4316;
8'd243 : VAR8=32'd4298;
8'd244 : VAR8=32'd4281;
8'd245 : VAR8=32'd4263;
8'd246 : VAR8=32'd4246;
8'd247 : VAR8=32'd4229;
8'd248 : VAR8=32'd4212;
8'd249 : VAR8=32'd4195;
8'd250 : VAR8=32'd4178;
8'd251 : VAR8=32'd4161;
8'd252 : VAR8=32'd4145;
8'd253 : VAR8=32'd4128;
8'd254 : VAR8=32'd4112;
8'd255 : VAR8=32'd4096;
endcase
if (VAR4[15:8] == VAR2)
begin
if (VAR4[23:16] >= VAR4[31:24])
begin
VAR12 <= {2'b0,((16'd60*(VAR4[23:16] - VAR4[31:24])*VAR8)>>20)};
end
else
begin
VAR12 <= 0- ((16'd60*(VAR4[31:24] - VAR4[23:16])*VAR8)>>20);
end
end
else if (VAR4[23:16] == VAR2)
begin
if (VAR4[31:24] >= VAR4[15:8])
begin
VAR12 <= (16'd120+((16'd60*(VAR4[31:24] - VAR4[15:8])*VAR8)>>20));
end
else
begin
VAR12 <= (16'd120-((16'd60*(VAR4[15:8] - VAR4[31:24])*VAR8)>>20));
end
end
else
begin
if (VAR4[15:8] >= VAR4[23:16])
begin
VAR12 <= (16'd240+((16'd60*(VAR4[15:8] - VAR4[23:16])*VAR8)>>20));
end
else
begin
VAR12 <= (16'd240-((16'd60*(VAR4[23:16] - VAR4[15:8])*VAR8)>>20));
end
end
VAR11 = VAR12 ;
if (VAR11 < 0)
begin
VAR7[31:24] <= ((VAR11 >>1)+180);
VAR7[7:0]<=0;
end
else
begin
VAR7[31:24]<= (VAR11>>1);
VAR7[7:0]<=0;
end
end
end
endmodule | gpl-3.0 |
fbalakirev/red-pitaya-notes | cores/axis_accumulator_v1_0/axis_accumulator.v | 3,912 | module MODULE1 #
(
parameter integer VAR23 = 16,
parameter integer VAR16 = 32,
parameter integer VAR1 = 16,
parameter VAR32 = "VAR7",
parameter VAR14 = "VAR7"
)
(
input wire VAR21,
input wire VAR28,
input wire [VAR1-1:0] VAR2,
output wire VAR26,
input wire [VAR23-1:0] VAR3,
input wire VAR15,
input wire VAR19,
output wire [VAR16-1:0] VAR4,
output wire VAR6
);
reg [VAR16-1:0] VAR18, VAR22;
reg [VAR16-1:0] VAR13, VAR5;
reg [VAR1-1:0] VAR8, VAR17;
reg VAR20, VAR30;
reg VAR27, VAR25;
wire [VAR16-1:0] VAR9;
wire VAR10, VAR11;
always @(posedge VAR21)
begin
if(~VAR28)
begin
VAR18 <= {(VAR16){1'b0}};
VAR20 <= 1'b0;
VAR27 <= 1'b0;
VAR13 <= {(VAR16){1'b0}};
VAR8 <= {(VAR1){1'b0}};
end
else
begin
VAR18 <= VAR22;
VAR20 <= VAR30;
VAR27 <= VAR25;
VAR13 <= VAR5;
VAR8 <= VAR17;
end
end
assign VAR10 = VAR8 < VAR2;
assign VAR11 = VAR27 & VAR15;
generate
if(VAR32 == "VAR31")
begin : VAR24
assign VAR9 = (VAR13) + (VAR3);
end
else
begin : VAR29
assign VAR9 = VAR13 + VAR3;
end
endgenerate
generate
if(VAR14 == "VAR31")
begin : VAR14
always @*
begin
VAR22 = VAR18;
VAR30 = VAR20;
VAR25 = VAR27;
VAR5 = VAR13;
VAR17 = VAR8;
if(~VAR27 & VAR10)
begin
VAR25 = 1'b1;
end
if(VAR11 & VAR10)
begin
VAR17 = VAR8 + 1'b1;
VAR5 = VAR9;
end
if(VAR11 & ~VAR10)
begin
VAR17 = {(VAR1){1'b0}};
VAR5 = {(VAR16){1'b0}};
VAR22 = VAR9;
VAR30 = 1'b1;
end
if(VAR19 & VAR20)
begin
VAR30 = 1'b0;
end
end
end
else
begin : VAR12
always @*
begin
VAR22 = VAR18;
VAR30 = VAR20;
VAR25 = VAR27;
VAR5 = VAR13;
VAR17 = VAR8;
if(~VAR27 & VAR10)
begin
VAR25 = 1'b1;
end
if(VAR11 & VAR10)
begin
VAR17 = VAR8 + 1'b1;
VAR5 = VAR9;
end
if(VAR11 & ~VAR10)
begin
VAR25 = 1'b0;
VAR22 = VAR9;
VAR30 = 1'b1;
end
if(VAR19 & VAR20)
begin
VAR30 = 1'b0;
end
end
end
endgenerate
assign VAR26 = VAR27;
assign VAR4 = VAR18;
assign VAR6 = VAR20;
endmodule | mit |
Madh93/scpu | modules/vga.v | 1,419 | module MODULE1(
input reset, VAR10,
input wire VAR9,
input wire [7:0] VAR6,
input wire [6:0] VAR8,
input wire [7:0] pos,
input VAR11,
output [3:0] VAR1, VAR16, VAR2,
output VAR14, VAR4, VAR7, VAR5, VAR15);
wire [7:0] VAR6;
wire [6:0] VAR8;
wire [2:0] VAR9;
assign VAR6 = VAR6 + 10 + ((pos%5)*8'b00000101); assign VAR8 = VAR8 + 25; assign VAR9 = (VAR9 == 1) ? 3'b011 : 3'b000;
VAR3 VAR12(
.VAR13(reset),
.VAR10(VAR10),
.VAR9(VAR9), .VAR6(VAR6), .VAR8(VAR8), .VAR11(VAR11),
.VAR1(VAR1),
.VAR16(VAR16),
.VAR2(VAR2),
.VAR14(VAR14),
.VAR4(VAR4));
endmodule | mit |
AnttiLukats/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_sha256/rtl/verilog/wb_sha256_ctrl.v | 5,640 | module MODULE1 (
input VAR25,
input VAR15,
input [6:0] VAR28,
input [31:0] VAR18,
input [3:0] VAR22,
input VAR14,
input [1:0] VAR30,
input [2:0] VAR5,
input VAR6,
input VAR20,
output reg VAR13,
output VAR24,
output VAR8,
output reg [31:0] VAR19,
output reg VAR27,
output reg [255:0] VAR31,
output reg [511:0] VAR7,
input VAR12,
input [255:0] VAR3
);
assign VAR24 = 0;
assign VAR8 = 0;
wire valid = (VAR6 & VAR20);
reg VAR9;
wire VAR32 = valid & ~VAR9;
reg [6:0] VAR10;
wire [6:0] VAR26 = VAR17(VAR10, VAR5, VAR30, 32);
wire [6:0] VAR29 = VAR32 ? VAR28 : VAR26;
always @(posedge VAR25)
begin
VAR10 <= VAR29;
VAR9 <= valid;
VAR13 <= valid & (!((VAR5 == 3'b000) | (VAR5 == 3'b111)) | !VAR13);
if(VAR15)
begin
VAR10 <= 0;
VAR9 <= 0;
VAR13 <= 0;
end
end
reg VAR1, VAR21;
wire rst = (VAR21 | VAR15);
VAR31[256 - (VAR11 * 32) - 23:256 - (VAR11 * 32) - 32] <= (VAR22[0]) \
? VAR18[ 7: 0] : VAR31[256 - (VAR11 * 32) - 23:256 - (VAR11 * 32) - 32]; \
VAR31[256 - (VAR11 * 32) - 17:256 - (VAR11 * 32) - 24] <= (VAR22[1]) \
? VAR18[15: 8] : VAR31[256 - (VAR11 * 32) - 17:256 - (VAR11 * 32) - 24]; \
VAR31[256 - (VAR11 * 32) - 9:256 - (VAR11 * 32) - 16] <= (VAR22[2]) \
? VAR18[23:16] : VAR31[256 - (VAR11 * 32) - 9:256 - (VAR11 * 32) - 16]; \
VAR31[256 - (VAR11 * 32) - 1:256 - (VAR11 * 32) - 8] <= (VAR22[3]) \
? VAR18[31:24] : VAR31[256 - (VAR11 * 32) - 1:256 - (VAR11 * 32) - 8];
VAR19 <= (VAR27 | VAR12) \
? 32'h0 : VAR31[256 - (VAR11 * 32) - 1:256 - (VAR11 * 32) - 32];
VAR7[512 - (VAR11 * 32) - 23:512 - (VAR11 * 32) - 32] <= (VAR22[0]) \
? VAR18[ 7: 0] : VAR7[512 - (VAR11 * 32) - 23:512 - (VAR11 * 32) - 32]; \
VAR7[512 - (VAR11 * 32) - 17:512 - (VAR11 * 32) - 24] <= (VAR22[1]) \
? VAR18[15: 8] : VAR7[512 - (VAR11 * 32) - 17:512 - (VAR11 * 32) - 24]; \
VAR7[512 - (VAR11 * 32) - 9:512 - (VAR11 * 32) - 16] <= (VAR22[2]) \
? VAR18[23:16] : VAR7[512 - (VAR11 * 32) - 9:512 - (VAR11 * 32) - 16]; \
VAR7[512 - (VAR11 * 32) - 1:512 - (VAR11 * 32) - 8] <= (VAR22[3]) \
? VAR18[31:24] : VAR7[512 - (VAR11 * 32) - 1:512 - (VAR11 * 32) - 8];
always @(posedge VAR25)
begin : VAR4
VAR1 <= VAR12;
VAR21 <= 0;
if(rst)
begin
VAR27 <= 0;
VAR31 <= {
32'h6a09e667, 32'hbb67ae85, 32'h3c6ef372, 32'ha54ff53a,
32'h510e527f, 32'h9b05688c, 32'h1f83d9ab, 32'h5be0cd19
};
VAR7 <= 0;
end
else
begin
if(VAR1 & ~VAR12)
begin
VAR31 <= VAR3;
VAR7 <= 0;
end
if(VAR12)
VAR27 <= 0;
if(valid & VAR14 & ~VAR12 & ~VAR27)
begin
case(VAR29[6:5])
2'b00:
begin
case(VAR29[4:2])
0: begin VAR23(0); end
1: begin VAR23(1); end
2: begin VAR23(2); end
3: begin VAR23(3); end
4: begin VAR23(4); end
5: begin VAR23(5); end
6: begin VAR23(6); end
7: begin VAR23(7); end
endcase
end
2'b01:
begin
case(VAR29[4:2])
0: begin VAR16( 0); end
1: begin VAR16( 1); end
2: begin VAR16( 2); end
3: begin VAR16( 3); end
4: begin VAR16( 4); end
5: begin VAR16( 5); end
6: begin VAR16( 6); end
7: begin VAR16( 7); end
endcase
end
2'b10:
begin
case(VAR29[4:2])
0: begin VAR16( 8); end
1: begin VAR16( 9); end
2: begin VAR16(10); end
3: begin VAR16(11); end
4: begin VAR16(12); end
5: begin VAR16(13); end
6: begin VAR16(14); end
7: begin VAR16(15); end
endcase
end
2'b11:
begin
if(VAR29[4:2] == 0)
begin
VAR27 <= VAR22[0] & VAR18[0];
VAR21 <= VAR22[1] & VAR18[8];
end
end
endcase
end
if(valid & ~VAR14)
begin
case(VAR29[6:5])
2'b00:
begin
case(VAR29[4:2])
0: begin VAR2(0); end
1: begin VAR2(1); end
2: begin VAR2(2); end
3: begin VAR2(3); end
4: begin VAR2(4); end
5: begin VAR2(5); end
6: begin VAR2(6); end
7: begin VAR2(7); end
endcase
end
2'b01: VAR19 <= 32'h0;
2'b10: VAR19 <= 32'h0;
2'b11:
begin
if(VAR29[4:2] == 0)
VAR19 <= { 15'h0, VAR27 | VAR12, 16'h0 };
end
else
VAR19 <= 0;
end
endcase
end end
end
endmodule | apache-2.0 |
slongfield/StereoCensus | verilog/census/census.v | 2,493 | module MODULE1#(
parameter VAR12=1,
parameter VAR10=2,
parameter VAR4=2
) (
input wire clk,
input wire rst,
input wire [VAR12*VAR10*VAR4-1:0] VAR11,
output wire [VAR10*VAR4-1:0] VAR3
);
localparam VAR5 = VAR12*VAR10*VAR4;
localparam VAR1 = (VAR10*VAR4-1)/2;
wire [VAR10*VAR4-1:0] VAR9;
wire [VAR12-1:0] word[VAR10*VAR4];
VAR7#(.VAR12(VAR10*VAR4)) VAR8(clk, rst, VAR9, VAR3);
genvar VAR2;
generate
for (VAR2 = 0; VAR2 < VAR10*VAR4; VAR2++) begin
assign word[VAR2] = VAR11[(VAR5-VAR12*VAR2-1):(VAR5-VAR12*(VAR2+1))];
end
endgenerate
genvar VAR6;
generate
for (VAR6 = 0; VAR6 < VAR10*VAR4; VAR6++) begin
if (VAR6 == VAR1) begin
assign VAR9[VAR6] = 0;
end else begin
assign VAR9[VAR6] = word[VAR6] > word[VAR1];
end
end
endgenerate
endmodule | gpl-3.0 |
rfotino/consolite-hardware | proj/ipcore_dir/s6_lpddr_ram/user_design/rtl/infrastructure.v | 10,479 | module MODULE1 #
(
parameter VAR32 = 2500,
parameter VAR116 = 1,
parameter VAR78 = "VAR114",
parameter VAR61 = 1,
parameter VAR69 = 1,
parameter VAR90 = 16,
parameter VAR7 = 8,
parameter VAR18 = 2,
parameter VAR63 = 1
)
(
input VAR104,
input VAR110,
input VAR1,
input VAR72,
output VAR67,
output VAR50,
output VAR2,
output VAR29,
output VAR92,
output VAR93,
output VAR112,
output VAR74,
output VAR57
);
localparam VAR20 = 25;
localparam VAR9 = VAR32 / 1000.0;
localparam VAR77 = VAR32/1000;
wire VAR10;
wire VAR94;
wire VAR48;
wire VAR4;
wire VAR80;
wire VAR101;
wire VAR37;
reg [VAR20-1:0] VAR14 ;
wire VAR22;
reg VAR6;
wire VAR102;
wire VAR25;
wire VAR42;
assign VAR102 = VAR116 ? ~VAR72: VAR72;
assign VAR67 = VAR48;
assign VAR57 = VAR25;
generate
if (VAR78 == "VAR114") begin: VAR28
end else if (VAR78 == "VAR46") begin: VAR97
assign VAR42 = VAR1;
end
endgenerate
VAR39 #
(
.VAR47 ("VAR5"),
.VAR73 ("VAR108"),
.VAR12 (VAR9),
.VAR54 (VAR9),
.VAR16 (VAR61),
.VAR59 (VAR69),
.VAR95 (VAR90),
.VAR111 (VAR7),
.VAR75 (1),
.VAR35 (1),
.VAR34 (0.000),
.VAR85 (180.000),
.VAR40 (0.000),
.VAR27 (0.000),
.VAR65 (0.000),
.VAR33 (0.000),
.VAR3 (0.500),
.VAR49 (0.500),
.VAR68 (0.500),
.VAR17 (0.500),
.VAR55 (0.500),
.VAR88 (0.500),
.VAR31 ("VAR115"),
.VAR30 (VAR63),
.VAR60 (VAR18),
.VAR51 (0.0),
.VAR41 (0.005000)
)
VAR19
(
.VAR38 (VAR101),
.VAR56 (1'b1),
.VAR36 (VAR42),
.VAR113 (1'b0),
.VAR58 (5'b0),
.VAR44 (1'b0),
.VAR62 (1'b0),
.VAR43 (16'b0),
.VAR117 (1'b0),
.VAR15 (1'b0),
.VAR82 (VAR102),
.VAR76 (),
.VAR107 (VAR101),
.VAR79 (),
.VAR98 (),
.VAR84 (),
.VAR91 (),
.VAR81 (),
.VAR24 (),
.VAR87 (VAR10),
.VAR105 (VAR94),
.VAR64 (VAR4),
.VAR100 (VAR80),
.VAR45 (),
.VAR21 (),
.VAR96 (),
.VAR89 (),
.VAR71 (VAR37)
);
VAR109 VAR103
(
.VAR26 (VAR48),
.VAR52 (VAR4)
);
VAR109 VAR11
(
.VAR26 (VAR93),
.VAR52 (VAR80)
);
always @(posedge VAR48 , posedge VAR102)
if(VAR102)
VAR6 <= 1'b0;
end
else if (VAR25)
VAR6 <= 1'b1;
assign VAR22 = VAR102 | ~VAR6;
assign VAR2 = VAR22;
always @(posedge VAR48 or posedge VAR22)
if (VAR22)
VAR14 <= {VAR20{1'b1}};
else
VAR14 <= VAR14 << 1;
assign VAR50 = VAR14[VAR20-1];
VAR70 VAR83
( .VAR8 (VAR29),
.VAR106 (VAR92),
.VAR71 (VAR37),
.VAR66 (VAR93),
.VAR86 (VAR112),
.VAR53 (VAR74),
.VAR13 (VAR10),
.VAR23 (VAR94),
.VAR99 (VAR25)
);
endmodule | mit |
eda-globetrotter/MarcheProcessor | processor/reading/myAddSub.v | 2,319 | module MODULE1(VAR20,VAR25,VAR6,VAR28,VAR40,VAR12,VAR7,VAR1);
input [7:0] VAR20;
input [7:0] VAR25;
input VAR6;
input VAR28;
input VAR40;
output [7:0] VAR12;
output VAR7;
output VAR1;
reg[7:0] VAR42;
wire [7:0] VAR12;
wire VAR43,VAR39,VAR13,VAR46,VAR36,VAR17,VAR15;
wire VAR19;
always @(VAR20 or VAR25 or VAR6 or VAR28 or VAR40)
begin
VAR42[0] = VAR20[0] ^ (VAR25[0] & VAR40) ^ ~VAR28;
VAR42[1] = VAR20[1] ^ (VAR25[1] & VAR40) ^ ~VAR28;
VAR42[2] = VAR20[2] ^ (VAR25[2] & VAR40) ^ ~VAR28;
VAR42[3] = VAR20[3] ^ (VAR25[3] & VAR40) ^ ~VAR28;
VAR42[4] = VAR20[4] ^ (VAR25[4] & VAR40) ^ ~VAR28;
VAR42[5] = VAR20[5] ^ (VAR25[5] & VAR40) ^ ~VAR28;
VAR42[6] = VAR20[6] ^ (VAR25[6] & VAR40) ^ ~VAR28;
VAR42[7] = VAR20[7] ^ (VAR25[7] & VAR40) ^ ~VAR28;
end
VAR23 VAR9 (.VAR38(VAR43),.VAR6(VAR6),.VAR4(VAR20[0]),.VAR21(VAR42[0]) );
VAR23 VAR31 (.VAR38(VAR39),.VAR6(VAR43),.VAR4(VAR20[1]),.VAR21(VAR42[1]) );
VAR23 VAR30 (.VAR38(VAR13),.VAR6(VAR39),.VAR4(VAR20[2]),.VAR21(VAR42[2]) );
VAR23 VAR26 (.VAR38(VAR46),.VAR6(VAR13),.VAR4(VAR20[3]),.VAR21(VAR42[3]) );
VAR23 VAR37 (.VAR38(VAR36),.VAR6(VAR46),.VAR4(VAR20[4]),.VAR21(VAR42[4]) );
VAR23 VAR5 (.VAR38(VAR17),.VAR6(VAR36),.VAR4(VAR20[5]),.VAR21(VAR42[5]) );
VAR29 VAR18 (.VAR38(VAR15),.VAR44(VAR19),.VAR6(VAR17),.VAR4(VAR20[6]),.VAR21(VAR42[6]) );
VAR33 VAR11 (.VAR44(VAR7),.VAR6(VAR15),.VAR4(VAR20[7]),.VAR21(VAR42[7]) );
VAR2 VAR24 (.VAR44(VAR12[0]),.VAR6(VAR6), .VAR41(VAR42[0]));
VAR2 VAR35 (.VAR44(VAR12[1]),.VAR6(VAR43),.VAR41(VAR42[1]));
VAR2 VAR14 (.VAR44(VAR12[2]),.VAR6(VAR39),.VAR41(VAR42[2]));
VAR2 VAR16 (.VAR44(VAR12[3]),.VAR6(VAR13),.VAR41(VAR42[3]));
VAR2 VAR22 (.VAR44(VAR12[4]),.VAR6(VAR46),.VAR41(VAR42[4]));
VAR2 VAR45 (.VAR44(VAR12[5]),.VAR6(VAR36),.VAR41(VAR42[5]));
VAR2 VAR34 (.VAR44(VAR12[6]),.VAR6(VAR17),.VAR41(VAR42[6]));
VAR2 VAR32 (.VAR44(VAR12[7]),.VAR6(VAR15),.VAR41(VAR42[7]));
VAR3 VAR8(.VAR44(VAR1),.VAR10(VAR19),.VAR27(VAR7));
endmodule | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_gt.v | 25,310 | module MODULE1 (
VAR8,
VAR47,
VAR33,
VAR50,
VAR66,
VAR93,
VAR103,
VAR95,
VAR77,
VAR52,
VAR24,
VAR142,
VAR84,
VAR111,
VAR105,
VAR102,
VAR9,
VAR48,
VAR81,
VAR113,
VAR35,
VAR112,
VAR92,
VAR136,
VAR65,
VAR88,
VAR5,
VAR100,
VAR28,
VAR144,
VAR83,
VAR133,
VAR57,
VAR147,
VAR21,
VAR62,
VAR119,
VAR131,
VAR15,
VAR126,
VAR150,
VAR75,
VAR7,
VAR1,
VAR4,
VAR61,
VAR107,
VAR140,
VAR69,
VAR71,
VAR54,
VAR98,
VAR18,
VAR138,
VAR42,
VAR34,
VAR122,
VAR76,
VAR72,
VAR53,
VAR38,
VAR141,
VAR145,
VAR146,
VAR46,
VAR37,
VAR29,
VAR79,
VAR67,
VAR127,
VAR99,
VAR45,
VAR19,
VAR11,
VAR26,
VAR134,
VAR20,
VAR51,
VAR130);
localparam VAR132 = 32'h00060162;
parameter VAR120 = 0;
parameter VAR14 = 0;
output VAR8;
output VAR47;
output VAR33;
output VAR50;
output VAR66;
output [ 1:0] VAR93;
output [ 2:0] VAR103;
output [ 1:0] VAR95;
output [ 2:0] VAR77;
input VAR52;
output VAR24;
output VAR142;
input VAR84;
output VAR111;
input VAR105;
output VAR102;
input [ 7:0] VAR9;
input [ 7:0] VAR48;
input VAR81;
output VAR113;
input VAR35;
output VAR112;
output VAR92;
input VAR136;
output VAR65;
input VAR88;
output VAR5;
input [ 7:0] VAR100;
input [ 7:0] VAR28;
input VAR144;
output VAR83;
output VAR133;
output VAR57;
output [11:0] VAR147;
output [15:0] VAR21;
input [15:0] VAR62;
input VAR119;
output [ 7:0] VAR131;
input [ 7:0] VAR15;
input VAR126;
input VAR150;
input [11:0] VAR75;
input [15:0] VAR7;
output [15:0] VAR1;
output VAR4;
output VAR61;
output VAR107;
output VAR140;
output [ 4:0] VAR69;
output [ 1:0] VAR71;
output [ 7:0] VAR54;
output [ 7:0] VAR98;
output [ 7:0] VAR18;
output [11:0] VAR138;
output [11:0] VAR42;
output [11:0] VAR34;
output [31:0] VAR122;
output [15:0] VAR76;
output [15:0] VAR72;
output [15:0] VAR53;
output [15:0] VAR38;
output [15:0] VAR141;
output [15:0] VAR145;
output [15:0] VAR146;
output [15:0] VAR46;
output [15:0] VAR37;
output [15:0] VAR29;
input VAR79;
input VAR67;
input VAR127;
input VAR99;
input VAR45;
input [13:0] VAR19;
input [31:0] VAR11;
output VAR26;
input VAR134;
input [13:0] VAR20;
output [31:0] VAR51;
output VAR130;
reg VAR55 = 'd1;
reg VAR129 = 'd1;
reg VAR59 = 'd1;
reg VAR68 = 'd1;
reg VAR149 = 'd1;
reg VAR26 = 'd0;
reg [31:0] VAR63 = 'd0;
reg VAR50 = 'd0;
reg VAR66 = 'd0;
reg VAR30 = 'd0;
reg VAR32 = 'd0;
reg VAR115 = 'd0;
reg VAR22 = 'd0;
reg [ 1:0] VAR93 = 'd0;
reg [ 2:0] VAR103 = 'd0;
reg VAR25 = 'd0;
reg VAR56 = 'd0;
reg VAR43 = 'd0;
reg VAR73 = 'd0;
reg VAR106 = 'd0;
reg [ 1:0] VAR95 = 'd0;
reg [ 2:0] VAR77 = 'd0;
reg VAR137 = 'd0;
reg VAR108 = 'd0;
reg VAR12 = 'd0;
reg [ 7:0] VAR131 = 'd0;
reg VAR36 = 'd0;
reg VAR91 = 'd0;
reg VAR27 = 'd0;
reg VAR94 = 'd0;
reg [11:0] VAR3 = 'd0;
reg [15:0] VAR44 = 'd0;
reg [15:0] VAR135 = 'd0;
reg VAR140 = 'd0;
reg VAR107 = 'd0;
reg VAR80 = 'd0;
reg VAR61 = 'd0;
reg VAR109 = 'd0;
reg [ 4:0] VAR69 = 'd0;
reg [ 1:0] VAR71 = 'd0;
reg [ 7:0] VAR54 = 'd0;
reg [ 7:0] VAR98 = 'd0;
reg [ 7:0] VAR18 = 'd0;
reg [11:0] VAR138 = 'd0;
reg [11:0] VAR42 = 'd0;
reg [11:0] VAR34 = 'd0;
reg [31:0] VAR122 = 'd0;
reg [15:0] VAR72 = 'd0;
reg [15:0] VAR76 = 'd0;
reg [15:0] VAR38 = 'd0;
reg [15:0] VAR53 = 'd0;
reg [15:0] VAR141 = 'd0;
reg [15:0] VAR146 = 'd0;
reg [15:0] VAR145 = 'd0;
reg [15:0] VAR37 = 'd0;
reg [15:0] VAR46 = 'd0;
reg [15:0] VAR29 = 'd0;
reg VAR128 = 'd0;
reg VAR130 = 'd0;
reg [31:0] VAR51 = 'd0;
reg [ 7:0] VAR78 = 'd0;
reg [ 7:0] VAR23 = 'd0;
reg [ 7:0] VAR110 = 'd0;
reg [ 7:0] VAR86 = 'd0;
reg [ 7:0] VAR64 = 'd0;
reg [ 7:0] VAR89 = 'd0;
reg [ 7:0] VAR13 = 'd0;
reg [ 7:0] VAR82 = 'd0;
reg VAR2 = 'd0;
reg VAR58 = 'd0;
reg VAR31 = 'd0;
reg VAR111 = 'd0;
reg VAR151 = 'd0;
reg VAR85 = 'd0;
reg VAR102 = 'd0;
reg VAR40 = 'd0;
reg VAR16 = 'd0;
reg VAR139 = 'd0;
reg VAR65 = 'd0;
reg VAR104 = 'd0;
reg VAR121 = 'd0;
reg VAR5 = 'd0;
reg VAR87 = 'd0;
reg VAR114 = 'd0;
reg VAR10 = 'd0;
reg VAR143 = 'd0;
reg VAR133 = 'd0;
reg VAR57 = 'd0;
reg [11:0] VAR147 = 'd0;
reg [15:0] VAR21 = 'd0;
reg [15:0] VAR1 = 'd0;
reg VAR4 = 'd0;
reg [15:0] VAR70 = 'd0;
reg VAR6 = 'd0;
wire VAR117;
wire VAR17;
wire VAR96;
wire VAR123;
wire VAR116;
wire VAR97;
wire VAR39;
wire VAR41;
assign VAR117 = (VAR19[13:8] == 6'h00) ? VAR45 : 1'b0;
assign VAR17 = (VAR20[13:8] == 6'h00) ? VAR134 : 1'b0;
assign VAR96 = & VAR64;
assign VAR123 = & VAR89;
assign VAR116 = & VAR13;
assign VAR97 = & VAR82;
always @(negedge VAR127 or posedge VAR99) begin
if (VAR127 == 0) begin
VAR55 <= 1'b1;
VAR129 <= 1'b1;
VAR59 <= 1'b1;
VAR68 <= 1'b1;
VAR149 <= 1'b1;
end else begin
VAR55 <= ~VAR32;
VAR129 <= ~(VAR32 & VAR115 & VAR123);
VAR59 <= ~(VAR32 & VAR73 & VAR97);
VAR68 <= ~(VAR32 & VAR115 & VAR22 & VAR123 & VAR96);
VAR149 <= ~(VAR32 & VAR73 & VAR106 & VAR97 & VAR116);
end
end
assign VAR113 = VAR96;
assign VAR83 = VAR116;
always @(negedge VAR127 or posedge VAR99) begin
if (VAR127 == 0) begin
VAR26 <= 'd0;
VAR63 <= 'd0;
VAR50 <= 'd0;
VAR66 <= 'd1;
VAR30 <= 'd0;
VAR32 <= 'd0;
VAR115 <= 'd0;
VAR22 <= 'd0;
VAR93 <= 2'b11;
VAR103 <= 3'b010;
VAR25 <= 'd0;
VAR56 <= 'd0;
VAR43 <= 'd0;
VAR73 <= 'd0;
VAR106 <= 'd0;
VAR95 <= 2'b11;
VAR77 <= 3'b010;
VAR137 <= 'd0;
VAR108 <= 'd0;
VAR12 <= 'd0;
VAR131 <= 'd0;
VAR36 <= 'd0;
VAR91 <= 'd0;
VAR27 <= 'd0;
VAR94 <= 'd0;
VAR3 <= 'd0;
VAR44 <= 'd0;
VAR135 <= 'd0;
VAR140 <= 'd0;
VAR107 <= 'd0;
VAR80 <= 'd0;
VAR61 <= 'd0;
VAR109 <= 'd0;
VAR69 <= 'd0;
VAR71 <= 'd0;
VAR54 <= 'd0;
VAR98 <= 'd0;
VAR18 <= 'd0;
VAR138 <= 'd0;
VAR42 <= 'd0;
VAR34 <= 'd0;
VAR122 <= 'd0;
VAR72 <= 'd0;
VAR76 <= 'd0;
VAR38 <= 'd0;
VAR53 <= 'd0;
VAR141 <= 'd0;
VAR146 <= 'd0;
VAR145 <= 'd0;
VAR37 <= 'd0;
VAR46 <= 'd0;
VAR29 <= 'd0;
VAR128 <= 'd0;
end else begin
VAR26 <= VAR117;
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h02)) begin
VAR63 <= VAR11;
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h04)) begin
VAR50 <= VAR11[1];
VAR66 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h05)) begin
VAR30 <= VAR11[1];
VAR32 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h08)) begin
VAR115 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h09)) begin
VAR22 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h0a)) begin
VAR93 <= VAR11[5:4];
VAR103 <= VAR11[2:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h0b)) begin
VAR25 <= VAR11[1];
VAR56 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h0c)) begin
VAR43 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h18)) begin
VAR73 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h19)) begin
VAR106 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h1a)) begin
VAR95 <= VAR11[5:4];
VAR77 <= VAR11[2:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h1b)) begin
VAR137 <= VAR11[1];
VAR108 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h1c)) begin
VAR12 <= VAR11[0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h23)) begin
VAR131 <= VAR11[7:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h24)) begin
VAR36 <= 1'b1;
VAR91 <= ~VAR11[28];
end else begin
VAR36 <= 1'b0;
VAR91 <= 1'b0;
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h24)) begin
VAR27 <= 1'b1;
end else if (VAR119 == 1'b1) begin
VAR27 <= 1'b0;
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h24)) begin
VAR94 <= VAR11[28];
VAR3 <= VAR11[27:16];
VAR44 <= VAR11[15:0];
end
if (VAR6 == 1'b1) begin
VAR135 <= VAR70;
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h28)) begin
VAR140 <= VAR11[2];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h28)) begin
VAR107 <= VAR11[1];
VAR80 <= VAR11[1];
end else begin
VAR107 <= 1'd0;
VAR80 <= VAR80;
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h28)) begin
VAR61 <= VAR11[0];
VAR109 <= VAR11[0];
end else begin
VAR61 <= 1'd0;
VAR109 <= VAR109;
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h29)) begin
VAR69 <= VAR11[4:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h2a)) begin
VAR71 <= VAR11[25:24];
VAR54 <= VAR11[23:16];
VAR98 <= VAR11[15:8];
VAR18 <= VAR11[7:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h2b)) begin
VAR138 <= VAR11[27:16];
VAR42 <= VAR11[11:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h2c)) begin
VAR34 <= VAR11[11:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h2d)) begin
VAR122 <= VAR11;
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h2e)) begin
VAR72 <= VAR11[31:16];
VAR76 <= VAR11[15:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h2f)) begin
VAR38 <= VAR11[31:16];
VAR53 <= VAR11[15:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h30)) begin
VAR141 <= VAR11[15:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h31)) begin
VAR146 <= VAR11[31:16];
VAR145 <= VAR11[15:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h32)) begin
VAR37 <= VAR11[31:16];
VAR46 <= VAR11[15:0];
end
if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h33)) begin
VAR29 <= VAR11[15:0];
end
if (VAR79 == 1'b1) begin
VAR128 <= 1'b1;
end else if ((VAR117 == 1'b1) && (VAR19[7:0] == 8'h38)) begin
VAR128 <= VAR128 & ~VAR11[1];
end
end
end
always @(negedge VAR127 or posedge VAR99) begin
if (VAR127 == 0) begin
VAR130 <= 'd0;
VAR51 <= 'd0;
end else begin
VAR130 <= VAR17;
if (VAR17 == 1'b1) begin
case (VAR20[7:0])
8'h00: VAR51 <= VAR132;
8'h01: VAR51 <= VAR120;
8'h02: VAR51 <= VAR63;
8'h04: VAR51 <= {30'd0, VAR50, VAR66};
8'h05: VAR51 <= {30'd0, VAR30, VAR32};
8'h08: VAR51 <= {31'd0, VAR115};
8'h09: VAR51 <= {31'd0, VAR22};
8'h0a: VAR51 <= {24'd0, 2'd0, VAR93, 1'd0, VAR103};
8'h0b: VAR51 <= {30'd0, VAR25, VAR56};
8'h0c: VAR51 <= {31'd0, VAR43};
8'h0d: VAR51 <= {15'd0, VAR114, VAR64, VAR89};
8'h18: VAR51 <= {31'd0, VAR73};
8'h19: VAR51 <= {31'd0, VAR106};
8'h1a: VAR51 <= {24'd0, 2'd0, VAR95, 1'd0, VAR77};
8'h1b: VAR51 <= {30'd0, VAR137, VAR108};
8'h1c: VAR51 <= {31'd0, VAR12};
8'h1d: VAR51 <= {15'd0, VAR143, VAR13, VAR82};
8'h23: VAR51 <= {24'd0, VAR131};
8'h24: VAR51 <= {3'd0, VAR94, VAR3, VAR44};
8'h25: VAR51 <= {15'd0, VAR27, VAR70};
8'h28: VAR51 <= {29'd0, VAR140, VAR80, VAR109};
8'h29: VAR51 <= {27'd0, VAR69};
8'h2a: VAR51 <= {6'd0, VAR71, VAR54, VAR98, VAR18};
8'h2b: VAR51 <= {4'd0, VAR138, 4'd0, VAR42};
8'h2c: VAR51 <= {20'd0, VAR34};
8'h2d: VAR51 <= VAR122;
8'h2e: VAR51 <= {VAR72, VAR76};
8'h2f: VAR51 <= {VAR38, VAR53};
8'h30: VAR51 <= VAR141;
8'h31: VAR51 <= {VAR146, VAR145};
8'h32: VAR51 <= {VAR37, VAR46};
8'h33: VAR51 <= VAR29;
8'h38: VAR51 <= {30'd0, VAR128, VAR67};
8'h39: VAR51 <= {24'd0, VAR15};
8'h3a: VAR51 <= VAR14;
default: VAR51 <= 0;
endcase
end else begin
VAR51 <= 32'd0;
end
end
end
VAR49 VAR125 (.VAR118(VAR55), .clk(VAR99), .rst(VAR8));
VAR49 VAR60 (.VAR118(VAR129), .clk(VAR99), .rst(VAR47));
VAR49 VAR101 (.VAR118(VAR59), .clk(VAR99), .rst(VAR33));
VAR49 VAR148 (.VAR118(VAR68), .clk(VAR52), .rst(VAR24));
VAR49 VAR90 (.VAR118(VAR68), .clk(VAR99), .rst(VAR142));
VAR49 VAR124 (.VAR118(VAR149), .clk(VAR35), .rst(VAR112));
VAR49 VAR74 (.VAR118(VAR149), .clk(VAR99), .rst(VAR92));
always @(negedge VAR127 or posedge VAR99) begin
if (VAR127 == 0) begin
VAR78 <= 'd0;
VAR23 <= 'd0;
VAR110 <= 'd0;
VAR86 <= 'd0;
VAR64 <= 'd0;
VAR89 <= 'd0;
VAR13 <= 'd0;
VAR82 <= 'd0;
end else begin
VAR78 <= VAR9;
VAR23 <= VAR48;
VAR110 <= VAR100;
VAR86 <= VAR28;
VAR64 <= VAR78;
VAR89 <= VAR23;
VAR13 <= VAR110;
VAR82 <= VAR86;
end
end
assign VAR39 = (VAR25 == 1'b1) ? VAR84 : VAR56;
always @(posedge VAR52) begin
if (VAR24 == 1'b1) begin
VAR2 <= 'd0;
VAR58 <= 'd0;
VAR31 <= 'd0;
VAR111 <= 'd0;
VAR151 <= 'd0;
VAR85 <= 'd0;
VAR102 <= 'd0;
end else begin
VAR2 <= VAR39;
VAR58 <= VAR2;
VAR31 <= VAR58;
VAR111 <= VAR58 & ~VAR31;
VAR151 <= VAR43 & VAR105;
VAR85 <= VAR151;
VAR102 <= VAR85;
end
end
assign VAR41 = (VAR137 == 1'b1) ? VAR136 : VAR108;
always @(posedge VAR35) begin
if (VAR112 == 1'b1) begin
VAR40 <= 'd0;
VAR16 <= 'd0;
VAR139 <= 'd0;
VAR65 <= 'd0;
VAR104 <= 'd0;
VAR121 <= 'd0;
VAR5 <= 'd0;
end else begin
VAR40 <= VAR41;
VAR16 <= VAR40;
VAR139 <= VAR16;
VAR65 <= VAR16 & ~VAR139;
VAR104 <= VAR12 & VAR88;
VAR121 <= VAR104;
VAR5 <= VAR121;
end
end
always @(negedge VAR127 or posedge VAR99) begin
if (VAR127 == 0) begin
VAR87 <= 'd0;
VAR114 <= 'd0;
VAR10 <= 'd0;
VAR143 <= 'd0;
end else begin
VAR87 <= VAR102 & ~VAR81;
VAR114 <= VAR87;
VAR10 <= VAR5 & ~VAR144;
VAR143 <= VAR10;
end
end
always @(negedge VAR127 or posedge VAR99) begin
if (VAR127 == 1'b0) begin
VAR133 <= 'd0;
VAR57 <= 'd0;
VAR147 <= 'd0;
VAR21 <= 'd0;
VAR1 <= 'd0;
VAR4 <= 'd0;
VAR70 <= 'd0;
VAR6 <= 'd0;
end else begin
if (VAR67 == 1'b1) begin
VAR133 <= VAR126;
VAR57 <= VAR150;
VAR147 <= VAR75;
VAR21 <= VAR7;
VAR1 <= VAR62;
VAR4 <= VAR119;
VAR70 <= 16'd0;
VAR6 <= 1'd0;
end else begin
VAR133 <= VAR36;
VAR57 <= VAR91;
VAR147 <= VAR3;
VAR21 <= VAR44;
VAR1 <= 16'd0;
VAR4 <= 1'd0;
VAR70 <= VAR62;
VAR6 <= VAR119;
end
end
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai.functional.v | 1,434 | module MODULE1 (
VAR8 ,
VAR5,
VAR2,
VAR7
);
output VAR8 ;
input VAR5;
input VAR2;
input VAR7;
wire VAR9 ;
wire VAR1;
or VAR4 (VAR9 , VAR2, VAR5 );
nand VAR6 (VAR1, VAR7, VAR9 );
buf VAR3 (VAR8 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp.symbol.v | 1,351 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR5,
input VAR1
);
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b_2.v | 2,173 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR9 ,
VAR8,
VAR7,
VAR2 ,
VAR1
);
output VAR3 ;
input VAR6 ;
input VAR9 ;
input VAR8;
input VAR7;
input VAR2 ;
input VAR1 ;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3 ,
VAR6 ,
VAR9
);
output VAR3 ;
input VAR6 ;
input VAR9;
supply1 VAR8;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR1 ;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v | 32,228 | module MODULE1
parameter VAR48 = 1,
parameter VAR2 = 8,
parameter VAR91 = 16,
parameter VAR44 = 0,
parameter VAR84 = 0,
parameter VAR70 = 0,
parameter VAR96 = 0,
parameter VAR59 = 0,
parameter VAR80 = 0,
parameter VAR78 = 0,
parameter VAR88 = 3,
parameter VAR98 = 1,
parameter VAR37 = VAR48 * VAR2,
parameter VAR23 = VAR28(VAR48)
)
(
input clk,
input reset,
input [VAR37-1: 0] VAR68,
input VAR16,
input VAR24,
input VAR66,
input [((VAR23>0) ? (VAR23-1):0) : 0] VAR83,
input [((VAR84>0) ? (VAR84-1):0) : 0] VAR63,
input [((VAR44>0) ? (VAR44-1):0): 0] VAR60,
output VAR53,
output [VAR37-1 : 0] VAR34,
output reg VAR42,
output VAR11,
output VAR89,
output [((VAR23>0) ? (VAR23-1):0) : 0] VAR38,
output [((VAR84>0) ? (VAR84-1):0) : 0] VAR79,
output [((VAR44>0) ? (VAR44-1):0): 0] VAR82,
input VAR67,
input [(VAR59 ? 2 : 1) : 0] VAR65,
input VAR17,
input VAR26,
input [31 : 0] VAR77,
output reg [31 : 0] VAR51,
output wire VAR30,
output wire VAR43
);
localparam VAR40 = VAR28(VAR91);
localparam VAR8 = VAR91;
localparam VAR20 = 2 + VAR23;
localparam VAR93 = (VAR70 == 1) ?
2 + VAR23 + VAR37 + VAR84 + VAR44:
VAR37 + VAR84 + VAR44;
genvar VAR29;
reg [VAR93-1 : 0] VAR47 [VAR8-1 : 0];
reg [VAR40-1 : 0] VAR5;
reg [VAR40-1 : 0] VAR35;
reg [VAR8-1 : 0] VAR54;
wire [VAR40-1 : 0] VAR76;
wire [VAR40-1 : 0] VAR74;
wire [VAR40-1 : 0] VAR72;
wire [VAR40-1 : 0] VAR15;
wire [VAR40-1 : 0] VAR1;
wire read;
wire write;
reg VAR4;
reg VAR31;
reg VAR86;
reg VAR3;
wire [VAR20-1 : 0] VAR62;
wire [VAR20-1 : 0] VAR10;
wire [VAR93-1 : 0] VAR73;
reg [VAR93-1 : 0] VAR18;
reg [VAR93-1 : 0] VAR25;
reg VAR56;
wire VAR7;
reg [VAR40 : 0] VAR97;
reg [VAR40 : 0] VAR32;
reg [VAR40-1 : 0] VAR64 = 0;
reg [23:0] VAR90;
reg [23:0] VAR87;
reg [23:0] VAR27;
reg [15:0] VAR46;
reg [15:0] VAR50;
reg [15:0] VAR55;
reg [15:0] VAR75;
reg VAR45;
reg VAR57;
reg VAR14;
reg VAR85;
reg VAR49;
reg VAR13;
reg VAR69;
reg VAR36;
wire VAR71;
reg VAR92;
wire VAR95;
wire VAR9;
wire VAR12;
wire VAR81;
wire VAR52;
wire VAR6;
wire VAR33;
wire VAR22;
wire VAR41;
wire [31:0] VAR39;
reg VAR61;
generate
if (VAR23 > 0) begin
assign VAR62 = {VAR24, VAR66, VAR83};
assign {VAR11, VAR89, VAR38} = VAR10;
end
else begin
assign VAR38 = VAR63;
assign VAR62 = {VAR24, VAR66};
assign {VAR11, VAR89} = VAR10;
end
endgenerate
generate
if (VAR70) begin
if (VAR84 > 0) begin
if (VAR44 > 0) begin
assign VAR73 = {VAR62, VAR68, VAR63, VAR60};
assign {VAR10, VAR34, VAR79, VAR82} = VAR25;
end
else begin
assign VAR82 = VAR60;
assign VAR73 = {VAR62, VAR68, VAR63};
assign {VAR10, VAR34, VAR79} = VAR25;
end
end
else begin
assign VAR79 = VAR63;
if (VAR44 > 0) begin
assign VAR73 = {VAR62, VAR68, VAR60};
assign {VAR10, VAR34, VAR82} = VAR25;
end
else begin
assign VAR82 = VAR60;
assign VAR73 = {VAR62, VAR68};
assign {VAR10, VAR34} = VAR25;
end
end
end
else begin
assign VAR10 = 0;
if (VAR84 > 0) begin
if (VAR44 > 0) begin
assign VAR73 = {VAR68, VAR63, VAR60};
assign {VAR34, VAR79, VAR82} = VAR25;
end
else begin
assign VAR82 = VAR60;
assign VAR73 = {VAR68, VAR63};
assign {VAR34, VAR79} = VAR25;
end
end
else begin
assign VAR79 = VAR63;
if (VAR44 > 0) begin
assign VAR73 = {VAR68, VAR60};
assign {VAR34, VAR82} = VAR25;
end
else begin
assign VAR82 = VAR60;
assign VAR73 = VAR68;
assign VAR34 = VAR25;
end
end
end
endgenerate
generate if (VAR98 == 1) begin
if (VAR88 == 1) begin
always @(posedge clk) begin
if (VAR16 && VAR53)
VAR47[VAR5] = VAR73;
VAR18 = VAR47[VAR1];
end
end else begin
always @(posedge clk) begin
if (VAR16 && VAR53)
VAR47[VAR5] <= VAR73;
VAR18 <= VAR47[VAR1];
end
end
assign VAR1 = VAR74;
end else begin
for (VAR29 = 0; VAR29 < VAR8-1; VAR29 = VAR29 + 1) begin : VAR58
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR47[VAR29] <= 0;
end
else if (read || !VAR54[VAR29]) begin
if (!VAR54[VAR29+1])
VAR47[VAR29] <= VAR73;
end
else
VAR47[VAR29] <= VAR47[VAR29+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
VAR47[VAR8-1] <= 0;
end
else begin
if (!VAR54[VAR8-1])
VAR47[VAR8-1] <= VAR73;
if (VAR8 == 1) begin
if (write)
VAR47[VAR8-1] <= VAR73;
end
end
end
end
endgenerate
assign read = VAR7 && VAR56 && VAR9;
assign write = VAR53 && VAR16;
generate if (VAR98 == 1) begin
assign VAR72 = VAR5 + 1'b1;
assign VAR15 = VAR35 + 1'b1;
assign VAR76 = VAR33 ? VAR64 : write ? VAR72 : VAR5;
assign VAR74 = (read) ? VAR15 : VAR35;
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR5 <= 0;
VAR35 <= 0;
end
else begin
VAR5 <= VAR76;
VAR35 <= VAR74;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR54[0] <= 0;
end
else begin
if (write ^ read) begin
if (read) begin
if (VAR8 > 1)
VAR54[0] <= VAR54[1];
end
else
VAR54[0] <= 0;
end
if (write)
VAR54[0] <= 1;
end
end
end
if (VAR8 > 1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR54[VAR8-1] <= 0;
end
else begin
if (write ^ read) begin
VAR54[VAR8-1] <= 0;
if (write)
VAR54[VAR8-1] <= VAR54[VAR8-2];
end
end
end
end
for (VAR29 = 1; VAR29 < VAR8-1; VAR29 = VAR29 + 1) begin : VAR94
always @(posedge clk, posedge reset) begin
if (reset) begin
VAR54[VAR29] <= 0;
end
else begin
if (write ^ read) begin
if (read)
VAR54[VAR29] <= VAR54[VAR29+1];
if (write)
VAR54[VAR29] <= VAR54[VAR29-1];
end
end
end
end
end
endgenerate
generate if (VAR98 == 1) begin
always @* begin
VAR3 = VAR86;
VAR31 = VAR4;
if (read && !write) begin
VAR3 = 1'b0;
if (VAR15 == VAR5)
VAR31 = 1'b1;
end
if (write && !read) begin
if (!VAR33)
VAR31 = 1'b0;
end
else if (VAR64 == VAR35) VAR31 = 1'b1;
if (VAR72 == VAR35 && !VAR33)
VAR3 = 1'b1;
end
if (write && read && VAR33) begin
if (VAR64 == VAR74)
VAR31 = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR4 <= 1;
VAR86 <= 0;
end
else begin
VAR4 <= VAR31;
VAR86 <= VAR3;
end
end
end else begin
always @* begin
VAR86 = VAR54[VAR8-1];
VAR4 = !VAR54[0];
if (VAR8 == 1)
VAR86 = VAR54[0] && !read;
VAR18 = VAR47[0];
if (VAR88 == 0) begin
VAR4 = !VAR54[0] && !VAR16;
if (!VAR54[0] && VAR16)
VAR18 = VAR73;
end
end
end
endgenerate
assign VAR53 = !VAR86;
assign VAR7 = VAR67 || !VAR42;
generate if (VAR88 > 1) begin
always @(posedge clk or posedge reset) begin
if (reset)
VAR56 <= 0;
end
else begin
VAR56 <= !VAR4 & VAR9 & ~VAR33;
if (read) begin
if (VAR15 == VAR5)
VAR56 <= 1'b0;
end
end
end
end else begin
always @* begin
VAR56 = !VAR4 & VAR9;
end
end
endgenerate
generate if (VAR88 == 3) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR42 <= 0;
VAR25 <= 0;
end
else begin
if (VAR7) begin
VAR42 <= VAR56 & VAR9;
VAR25 <= VAR18;
end
end
end
end
else begin
always @* begin
VAR42 = VAR56;
VAR25 = VAR18;
end
end
endgenerate
generate if (VAR96) begin
wire [31:0] VAR21;
assign VAR21 = VAR8;
always @(posedge clk or posedge reset) begin
if (reset)
VAR97 <= 0;
end
else if (VAR3 & !VAR33)
VAR97 <= VAR21[VAR40:0];
end
else begin
VAR97[VAR40] <= 1'b0;
VAR97[VAR40-1 : 0] <= VAR76 - VAR74;
end
end
always @* begin
VAR32 = VAR97;
if (VAR88 == 3)
VAR32 = VAR97 + {{VAR40{1'b0}}, VAR42};
end
end
else begin
always @* begin
VAR32 = 0;
end
end
endgenerate
generate if (VAR80) begin
assign VAR30 = (VAR32 >= VAR90);
end
else
assign VAR30 = 0;
endgenerate
generate if (VAR78) begin
assign VAR43 = (VAR32 <= VAR87);
end
else
assign VAR43 = 0;
endgenerate
generate if (VAR59) begin
assign VAR39 = VAR91 - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR90 <= VAR39[23 : 0];
VAR87 <= 0;
VAR27 <= 0;
VAR45 <= 0;
VAR51 <= 0;
VAR92 <= 1'b1;
end
else begin
if (VAR17) begin
if(VAR65 == 3'b010)
VAR90 <= VAR77[23:0];
if(VAR65 == 3'b011)
VAR87 <= VAR77[23:0];
if(VAR65 == 3'b100) begin
VAR27 <= VAR77[23:0];
VAR92 <= (VAR77[23:0] == 0);
end
if(VAR65 == 3'b101)
VAR45 <= VAR77[0];
end
if (VAR26) begin
VAR51 <= 32'b0;
if (VAR65 == 0)
VAR51 <= {{(31 - VAR40){1'b0}}, VAR32};
if (VAR65 == 2)
VAR51 <= {8'b0, VAR90};
if (VAR65 == 3)
VAR51 <= {8'b0, VAR87};
if (VAR65 == 4)
VAR51 <= {8'b0, VAR27};
if (VAR65 == 5)
VAR51 <= {31'b0, VAR45};
end
end
end
end
else if (VAR80 || VAR78) begin
assign VAR39 = VAR91 - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR90 <= VAR39[23 : 0];
VAR87 <= 0;
VAR51 <= 0;
end
else begin
if (VAR17) begin
if(VAR65 == 3'b010)
VAR90 <= VAR77[23:0];
if(VAR65 == 3'b011)
VAR87 <= VAR77[23:0];
end
if (VAR26) begin
VAR51 <= 32'b0;
if (VAR65 == 0)
VAR51 <= {{(31 - VAR40){1'b0}}, VAR32};
if (VAR65 == 2)
VAR51 <= {8'b0, VAR90};
if (VAR65 == 3)
VAR51 <= {8'b0, VAR87};
end
end
end
end
else begin
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR51 <= 0;
end
else if (VAR26) begin
VAR51 <= 0;
if (VAR65 == 0)
VAR51 <= VAR32;
end
end
end
endgenerate
generate if (VAR59) begin
assign VAR71 = (VAR61) & VAR95 ;
assign VAR95 = VAR13 | (VAR69 & VAR81);
assign VAR9 = (VAR92 ? (~VAR95 | ~VAR14) :
~VAR71) | VAR49;
assign VAR12 = VAR16 & VAR53 & VAR66;
assign VAR52 = VAR16 & VAR53 & VAR24;
assign VAR6 = VAR16 & VAR53 & |VAR63;
assign VAR41 = VAR42 & VAR67 & VAR11;
assign VAR81 = VAR42 & VAR67 & VAR89;
assign VAR22 = (VAR92 ? VAR95 : VAR71) & VAR86 & VAR67;
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR46 <= 0;
VAR50 <= 0;
VAR55 <= 1;
VAR75 <= 0;
VAR36 <= 0;
VAR14 <= 0;
VAR85 <= 0;
VAR49 <= 0;
VAR13 <= 1'b1;
VAR69 <= 1'b0;
VAR61 <= 1'b1;
end
else begin
VAR61 <= VAR97 < VAR27;
VAR49 <= VAR22;
VAR55 <= VAR46 + 1'b1;
VAR75 <= VAR46 - 1'b1;
VAR50 <= VAR46;
VAR36 <= 1'b0;
if( VAR12 )
VAR85 <= 1'b0;
end
else if (VAR41 & VAR13 )
VAR85 <= 1'b1;
if (VAR12 & ~VAR81 & ~VAR33 ) begin
VAR36 <= 1'b1;
VAR46 <= VAR36 ? VAR50 : VAR55;
VAR13 <= 0;
if (VAR46 == 0)
VAR69 <= 1'b1;
end
else
VAR69 <= 1'b0;
end
else if((~VAR12 | VAR33) & VAR81) begin
VAR36 <= 1'b1;
VAR46 <= VAR36 ? VAR50 : VAR75;
if (VAR46 == 1)
VAR13 <= 1'b1;
end
else
VAR13 <= 1'b0;
if (VAR46 == 2)
VAR69 <= 1'b1;
end
else
VAR69 <= 1'b0;
end
if (VAR52)
VAR14 <= 1'b1;
else if (VAR12)
VAR14 <= 1'b0;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
VAR64 <= 0;
VAR57 <= 0;
end
else begin
if ( VAR52 )
VAR64 <= VAR5;
if (VAR12)
VAR57 <= 1'b0;
end
else if ( VAR6 & (VAR14 | VAR52))
VAR57 <= 1'b1;
end
end
assign VAR33 = VAR45 & (VAR57 | VAR6) & VAR12 &
~VAR85 & ~(VAR41 & VAR13);
end
else begin
assign VAR9 = 1'b1;
assign VAR33 = 1'b0;
end
endgenerate
function integer VAR28;
input integer VAR19;
integer VAR29;
begin
VAR29 = 1;
VAR28 = 0;
while (VAR29 < VAR19) begin
VAR28 = VAR28 + 1;
VAR29 = VAR29 << 1;
end
end
endfunction
endmodule | mit |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cmn/block_ram/dual_port_ram_sync.v | 2,515 | module MODULE1
parameter VAR5 = 6,
parameter VAR7 = 8
)
(
input wire clk,
input wire VAR11,
input wire [VAR5-1:0] VAR4,
input wire [VAR5-1:0] VAR8,
input wire [VAR7-1:0] VAR3,
output wire [VAR7-1:0] VAR2,
output wire [VAR7-1:0] VAR10
);
reg [VAR7-1:0] VAR9 [2**VAR5-1:0];
reg [VAR5-1:0] VAR6;
reg [VAR5-1:0] VAR1;
always @(posedge clk)
begin
if (VAR11)
VAR9[VAR4] <= VAR3;
VAR6 <= VAR4;
VAR1 <= VAR8;
end
assign VAR2 = VAR9[VAR6];
assign VAR10 = VAR9[VAR1];
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.behavioral.v | 1,098 | module MODULE1( VAR4, VAR5 );
input VAR4;
output VAR5;
VAR1 VAR3(.VAR4(VAR4),.VAR5(VAR5));
VAR1 VAR2(.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
ace8957/EECE6017C | proc.v | 8,406 | module MODULE1 (VAR56, VAR55, VAR21, VAR50, VAR47, VAR48, VAR12, VAR60);
input [8:0] VAR56;
input VAR55, VAR21, VAR50;
output reg VAR47, VAR60;
output reg [8:0] VAR48, VAR12;
parameter VAR25 = 3'b000, VAR19 = 3'b001, VAR2 = 3'b010, VAR29 = 3'b011, VAR52 = 3'b100;
parameter VAR15 = 3'b000, VAR13 = 3'b001, VAR4 = 3'b010, VAR27 = 3'b011, VAR28 = 3'b100, VAR14 = 3'b101, VAR53 = 3'b110;
parameter VAR35 = 10'b1000000000,
VAR7 = 10'b0100000000,
VAR38 = 10'b0010000000,
VAR70 = 10'b0001000000,
VAR1 = 10'b0000100000,
VAR22 = 10'b0000010000,
VAR66 = 10'b0000001000,
VAR73 = 10'b0000000100,
VAR10 = 10'b0000000010,
VAR63 = 10'b0000000001;
reg [1:0] VAR24;
reg [1:0] VAR33;
wire [2:0] VAR49;
wire [0:7] VAR74, VAR16; wire [8:0] VAR23;
wire [8:0] VAR75, VAR58;
wire [8:0] VAR34;
wire VAR67;
and(VAR67, VAR58[0],
VAR58[1],
VAR58[2],
VAR58[3],
VAR58[4],
VAR58[5],
VAR58[6],
VAR58[7],
VAR58[8]
);
reg [0:7] VAR20;
reg [0:9] VAR9;
reg VAR36, VAR64, VAR3, VAR71, VAR57, VAR43, VAR72, VAR51, VAR76, VAR68,
VAR61, VAR39, VAR30;
assign VAR49 = VAR23[8:6];
VAR42 VAR26 (VAR23[5:3], 1'b1, VAR74);
VAR42 VAR65 (VAR23[2:0], 1'b1, VAR16);
always @(VAR24, VAR50, VAR47)
begin
if(VAR47) begin
VAR33 <= VAR25;
end
else begin
case (VAR24)
VAR25: begin
if(!VAR50)
VAR33 <= VAR25;
end
else
VAR33 <= VAR19;
end
VAR19:
begin
VAR33 <= VAR2;
end
VAR2:
begin
VAR33 <= VAR29;
end
VAR29:
begin
VAR33 <= VAR52;
end
VAR52:
begin
VAR33 <=VAR25;
end
endcase
end
end
always @(VAR24 or VAR49 or VAR74 or VAR16)
begin
VAR36 <= 0;
VAR47 <= 0;
VAR64 <= 0;
VAR3 <= 0;
VAR71 <= 0;
VAR57 <= 0;
VAR43 <= 0;
VAR72 <= 0;
VAR51 <= 0;
VAR76 <= 0;
VAR68 <= 0;
case (VAR24)
VAR25: begin
VAR6 <= 1;
VAR39 <= 1;
end
VAR19:
begin
VAR36 <=1;
VAR61 <=1;
VAR2: case (VAR49)
VAR15:
begin
VAR3 <= 1;
VAR43 <= 1;
VAR47 <= 1;
end
VAR13:
begin
VAR6 <=1;
VAR39 <=1;
end
VAR4:
begin
VAR57 <= 1;
VAR72 <= 1;
end
VAR27:
begin
VAR57 <= 1;
VAR72 <= 1;
end
VAR28:
begin
VAR3 <=1;
VAR39 <=1;
end
VAR14:
begin
VAR3 <=1;
VAR39 <=1;
end
VAR53:
begin
if(VAR67)
begin
VAR3 <=1;
VAR39 <=1;
end
else VAR47 <= 1;
end
default:
begin
VAR36 <= 0;
VAR47 <= 0;
VAR64 <= 0;
VAR3 <= 0;
VAR71 <= 0;
VAR57 <= 0;
VAR43 <= 0;
VAR72 <= 0;
VAR51 <= 0;
VAR76 <= 0;
VAR68 <= 0;
end
endcase
VAR29: case (VAR49)
VAR13:
begin
VAR61 <=1;
VAR64 <=1;
VAR43 <=1;
VAR47 <=1;
VAR4:
begin
VAR3 <= 1;
VAR51 <= 1;
end
VAR27:
begin
VAR3 <= 1;
VAR51 <= 1;
VAR68 <= 1;
end
VAR28:
begin
VAR64 <=1;
VAR43 <=1;
VAR47 <=1;
end
VAR14:
begin
VAR57 <=1;
VAR30 <=1;
VAR8 <=1;
VAR47 <=1; default:
begin
VAR36 <= 0;
VAR47 <= 0;
VAR64 <= 0;
VAR3 <= 0;
VAR71 <= 0;
VAR57 <= 0;
VAR43 <= 0;
VAR72 <= 0;
VAR51 <= 0;
VAR76 <= 0;
VAR68 <= 0;
end
endcase
VAR52: case (VAR49)
VAR4:
begin
VAR47 <= 1;
VAR76 <= 1;
VAR43 <= 1;
end
VAR27:
begin
VAR47 <= 1;
VAR43 <= 1;
VAR76 <= 1;
end
default:
begin
VAR36 <= 0;
VAR47 <= 0;
VAR64 <= 0;
VAR3 <= 0;
VAR71 <= 0;
VAR57 <= 0;
VAR43 <= 0;
VAR72 <= 0;
VAR51 <= 0;
VAR76 <= 0;
VAR68 <= 0;
end
endcase
endcase
end
always @(posedge VAR21, negedge VAR55) begin
if (!VAR55) begin
end
else VAR24 <= VAR33;
end
wire [8:0] VAR31, VAR37, VAR40, VAR17, VAR62, VAR44, VAR5, VAR54;
VAR45 VAR35(VAR46, VAR20[0], VAR21, VAR31);
VAR45 VAR7(VAR46, VAR20[1], VAR21, VAR37);
VAR45 VAR38(VAR46, VAR20[2], VAR21, VAR40);
VAR45 VAR70(VAR46, VAR20[3], VAR21, VAR17);
VAR45 VAR1(VAR46, VAR20[4], VAR21, VAR62);
VAR45 VAR22(VAR46, VAR20[5], VAR21, VAR44);
VAR45 VAR66(VAR46, VAR20[6], VAR21, VAR5);
counter VAR32(VAR21, VAR55, VAR61, VAR20[7], VAR54);
VAR45 VAR41(VAR46, VAR72, VAR21, VAR34);
VAR45 VAR59(VAR75, VAR51, VAR21, VAR58);
VAR45 VAR69(VAR56, VAR36, VAR21, VAR23);
VAR11 VAR18(VAR68, VAR34, VAR46, VAR75);
always @ (VAR57, VAR3, VAR76, VAR64, VAR74, VAR16)
begin if(VAR64 && !(VAR57 || VAR3 || VAR76)) begin
VAR9 = 10'b0000000001;
end
else if(VAR57 && !(VAR64 || VAR3 || VAR76)) begin
VAR9 = {VAR74, 1'b0, 1'b0};
end
else if(VAR3 && !(VAR57 || VAR64 || VAR76)) begin
VAR9 = {VAR16, 1'b0, 1'b0};
end
else if(VAR76 && !(VAR57 || VAR3 || VAR64)) begin
VAR9 = 10'b0000000010;
end
else begin
VAR9 = 10'b0000000001;
end
end
always @ (VAR43, VAR71, VAR74, VAR16)
begin
VAR20 = 8'b00000000;
if(VAR43) begin
VAR20 = VAR20 | VAR74;
end
if(VAR71) begin
VAR20 = VAR20 | VAR16;
end
end
always @ (VAR9, VAR31, VAR37, VAR40, VAR17, VAR62, VAR44, VAR5, VAR54, VAR58, VAR56) begin
case(VAR9)
VAR35: VAR46 <= VAR31;
VAR7: VAR46 <= VAR37;
VAR38: VAR46 <= VAR40;
VAR70: VAR46 <= VAR17;
VAR1: VAR46 <= VAR62;
VAR22: VAR46 <= VAR44;
VAR66: VAR46 <= VAR5;
VAR73: VAR46 <= VAR54;
VAR10: VAR46 <= VAR58;
VAR63: VAR46 <= VAR56;
default:
begin
VAR46 <= VAR56;
end
endcase
end
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.behavioral.v | 1,802 | module MODULE1( VAR4, VAR5, VAR2, VAR7, VAR3 );
input VAR2, VAR4, VAR7, VAR3;
output VAR5;
VAR1 VAR8(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3));
VAR1 VAR6(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3)); | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/ResetToBool.v | 1,552 | module MODULE1( VAR3, VAR1);
input VAR3;
output VAR1;
assign VAR1 = (VAR3 == VAR2);
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxtp/sky130_fd_sc_ms__edfxtp.pp.blackbox.v | 1,363 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR3,
VAR7,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR3;
input VAR7;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter.v | 6,149 | module MODULE1 #(
parameter VAR15 = 18,
parameter VAR14 = 0,
parameter VAR19 = 18,
parameter VAR24 = 0,
parameter VAR17 = 0,
parameter VAR4 = 0,
parameter VAR25 = 1,
parameter VAR20 = 1,
parameter VAR6 = 0,
parameter VAR8 = 18,
parameter VAR9 = 0,
parameter VAR23 = 1,
parameter VAR5 = 0,
parameter VAR1 = 1,
parameter VAR18 = 1,
parameter VAR7 = 0
) (
input wire VAR11, input wire VAR22, input wire [17:0] VAR16, input wire VAR10, output wire VAR21, output wire [17:0] VAR3, output wire VAR2, input wire VAR12, output wire [0:0] VAR13 );
generate
if (VAR15 != 18)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a_2.v | 2,321 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR1 ,
VAR4 ,
VAR2 ,
VAR6 ,
VAR7,
VAR9
);
output VAR3 ;
input VAR10 ;
input VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR7;
input VAR9;
VAR5 VAR8 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR3 ,
VAR10,
VAR1,
VAR4,
VAR2,
VAR6
);
output VAR3 ;
input VAR10;
input VAR1;
input VAR4;
input VAR2;
input VAR6;
supply1 VAR7;
supply0 VAR9;
VAR5 VAR8 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
vadixidav/vga-controller | vga.v | 2,743 | module MODULE1(
clk,
reset,
VAR8,
VAR3,
VAR20,
VAR1,
VAR10
);
parameter VAR12 = 1'b0;
parameter VAR2 = 640;
parameter VAR19 = 16;
parameter VAR7 = 96;
parameter VAR6 = 48;
parameter VAR16 =
VAR2 +
VAR19 +
VAR7 +
VAR6;
parameter VAR21 = 1'b0;
parameter VAR14 = 480;
parameter VAR13 = 10;
parameter VAR9 = 2;
parameter VAR5 = 33;
parameter VAR18 =
VAR14 +
VAR13 +
VAR9 +
VAR5;
parameter VAR17 = 10;
parameter VAR15 = 10;
input clk, reset;
output reg [VAR17-1:0] VAR8;
output VAR3;
output reg [VAR15-1:0] VAR20;
output VAR1;
output VAR10;
reg [VAR17-1:0] VAR4;
reg [VAR15-1:0] VAR11;
assign VAR3 =
((VAR4 >= (VAR2 + VAR19)) &&
(VAR4 < (VAR2 + VAR19 + VAR7))) ?
VAR12 : ~VAR12;
assign VAR1 =
((VAR11 >= (VAR14 + VAR13)) &&
(VAR11 < (VAR14 + VAR13 + VAR9))) ?
VAR21 : ~VAR21;
assign VAR10 = VAR8 < VAR2 && VAR20 < VAR14;
always @* begin
if (reset) begin
VAR8 = 0;
VAR20 = 0;
end else begin
if (VAR4 == VAR16 - 1) begin
VAR8 = 0;
if (VAR11 == VAR18 - 1)
VAR20 = 0;
end
else
VAR20 = VAR11 + 1;
end else
VAR8 = VAR4 + 1;
end
end
always @(posedge clk) begin
VAR4 <= VAR8;
VAR11 <= VAR20;
end
endmodule | mpl-2.0 |
promach/internal_logic_analyzer | rtl/stop.v | 1,034 | module MODULE1 (clk, reset, VAR1, VAR2, VAR6, VAR5);
input clk, reset, VAR1, VAR2;
input [(VAR7-1) : 0] VAR6;
output reg VAR5 = 0;
reg VAR4 = 0;
reg [(VAR7-1) : 0] VAR3 = 0;
always @(posedge clk)
begin
if (reset)
VAR4 <= 1'b0;
end
else if ((VAR2) && (VAR1))
VAR4 <= 1'b1; end
always @(posedge clk)
begin
if (reset)
VAR3 <= 0;
end
else
VAR3 <= (VAR4) ? (VAR3 + 1) : VAR3; end
always @(posedge clk)
begin
if (reset)
VAR5 <= 0;
end
else if (!VAR5)
VAR5 <= (VAR3 >= VAR6) && (VAR4);
end
endmodule | gpl-3.0 |
alankarkotwal/lca-processor | USE THESE FILES PRAVEEN/hazard_detection.v | 7,181 | module MODULE1(VAR2,VAR42,VAR40,clk,VAR32,VAR6,VAR30,VAR14,VAR29,VAR19,VAR13,VAR31,VAR18,VAR39,VAR43);
parameter VAR10 = 6'b000000;
parameter VAR23 = 6'b001000;
parameter VAR26 = 6'b000010;
parameter VAR12 = 6'b000001;
parameter VAR5 = 4'b0001;
parameter VAR4 = 6'b001010;
parameter VAR22 = 6'b001001;
parameter VAR25 = 4'b0011;
parameter VAR38 = 4'b0100;
parameter VAR34 = 4'b0101;
parameter VAR37 = 4'b0110;
parameter VAR28 = 4'b0111;
parameter VAR21 = 4'b1100;
parameter VAR15 = 4'b1000;
parameter VAR11 = 4'b1001;
input clk,VAR43;
input [15:0] VAR14,VAR19,VAR31,VAR18,VAR29,VAR13;
output reg[15:0] VAR42;
output reg VAR6,VAR30,VAR32,VAR39,VAR40,VAR2;
wire [5:0] VAR35,VAR9,VAR17,VAR41;
wire [7:0]VAR20;
assign VAR20=VAR14[7:0];
wire[2:0] VAR1,VAR33,VAR3,VAR36,VAR24,VAR8,VAR7,VAR16,VAR27;
assign VAR35 = {VAR14[15:12],VAR14[1:0]};
assign VAR9 = {VAR19[15:12],VAR19[1:0]};
assign VAR17 = {VAR31[15:12],VAR31[1:0]};
assign VAR41 = {VAR18[15:12],VAR18[1:0]};
assign VAR1 = VAR14[11:9];
assign VAR36 = VAR14[8:6];
assign VAR8 = VAR14[5:3];
assign VAR33 = VAR19[11:9];
assign VAR24 = VAR19[8:6];
assign VAR7 = VAR19[5:3];
assign VAR3 = VAR31[11:9];
assign VAR16 = VAR31[5:3];
assign VAR27 = VAR18[11:9];
always@(negedge clk) begin
if((VAR35[5:2]==VAR37||VAR35[5:2]==VAR28)&&(VAR35!=VAR9))
VAR40=1'b1;
end
else if ((VAR35[5:2]==VAR37||VAR35[5:2]==VAR28)&&(VAR35==VAR9)&&(VAR29!=VAR13))
VAR40=1'b1;
else
VAR40=1'b0;
end always @(negedge clk)
begin
VAR42[15:8]=VAR14[15:8];
if(VAR17[5:2]==VAR21&&VAR43==1'b1)
begin
VAR32=1'b1;
VAR6=1'b1;
VAR39=1'b0; end
else if((VAR35==VAR10||VAR35==VAR23||VAR35==VAR26||VAR35==VAR12||VAR35==VAR4||VAR35==VAR4||VAR35==VAR22)&&(VAR8==3'b111)) begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1; end
else if((VAR9==VAR10||VAR9==VAR23||VAR9==VAR26||VAR9==VAR12||VAR9==VAR4||VAR9==VAR4||VAR9==VAR22)&&(VAR7==3'b111))
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1; end
else if((VAR17==VAR10||VAR17==VAR23||VAR17==VAR26||VAR17==VAR12||VAR17==VAR4||VAR17==VAR4||VAR17==VAR22)&&(VAR16==3'b111))
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30 = 1'b1;
VAR39 = 1'b1;
end
else if(VAR35[5:2]==VAR5&&VAR36==3'b111)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if(VAR9[5:2]==VAR5&&VAR24==3'b111)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if(VAR17[5:2]==VAR5&&VAR24==3'b111)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR35[5:2]==VAR38||VAR35[5:2]==VAR37)&&VAR1==3'b111)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR9[5:2]==VAR38||VAR9[5:2]==VAR37)&&VAR33==3'b111)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR17[5:2]==VAR38||VAR17[5:2]==VAR37)&&VAR3==3'b111)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR41[5:2]==VAR38||VAR41[5:2]==VAR37)&&VAR27==3'b111)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if(VAR35[5:2]==VAR37||VAR35[5:2]==VAR28)
begin
if(VAR20[0]==1)
begin
VAR2=1'b1;
VAR39=1'b1;
VAR42[0]=1'b0;
end
else if(VAR20[1]==1)
begin
VAR2=1'b1;
VAR39=1'b1;
VAR42[1]=1'b0;
end
else if(VAR20[2]==1)
begin
VAR2=1'b1;
VAR39=1'b1;
VAR42[2]=1'b0;
end
else if(VAR20[3]==1)
begin
VAR2=1'b1;
VAR39=1'b1;
VAR42[3]=1'b0;
end
else if(VAR20[4]==1)
begin
VAR2=1'b1;
VAR39=1'b1;
VAR42[4]=1'b0;
end
else if(VAR20[5]==1)
begin
VAR2=1'b1;
VAR39=1'b1;
VAR42[5]=1'b0;
end
else if(VAR20[6]==1)
begin
VAR2=1'b1;
VAR39=1'b1;
VAR42[6]=1'b0;
end
else if(VAR20[7]==1)
begin
VAR2=1'b0;
VAR42[7]=1'b0;
VAR39=1'b0;
end
else begin VAR2=1'b0;
VAR42[7]=1'b0;
VAR39=1'b0;
end
end
else if ((VAR35==VAR10||VAR35==VAR23||VAR35==VAR26||VAR35==VAR12||VAR35==VAR4||VAR35==VAR4||VAR35==VAR22)
&&((VAR1==VAR33)||VAR36==VAR33)&&(VAR9==VAR38||VAR9==VAR37)) begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR35==VAR5)&&(VAR9==VAR38||VAR9==VAR37)&&(VAR1==VAR33))
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR35[5:2]==VAR38)&&(VAR9[5:2]==VAR38||VAR9[5:2]==VAR37)&&(VAR36==VAR33)) begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR35[5:2]==VAR37)&&(VAR9[5:2]==VAR38||VAR9[5:2]==VAR37)&&(VAR1==VAR33)) begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR35[5:2]==VAR34)&&(VAR9[5:2]==VAR38||VAR9[5:2]==VAR37)&&(VAR36==VAR33)) begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if(VAR35[5:2]==VAR15)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if(VAR35[5:2]==VAR11)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if(VAR9[5:2]==VAR11)
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR35[5:2]==VAR28||VAR35[5:2]==VAR37)&&(VAR9==VAR10||VAR9==VAR23||VAR9==VAR26||VAR9==VAR12||VAR9==VAR4||VAR9==VAR4||VAR9==VAR22)&&(VAR1==VAR7))
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR35[5:2]==VAR28||VAR35[5:2]==VAR37)&&(VAR9[5:2]==VAR5)&&(VAR1==VAR24))
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR35[5:2]==VAR28||VAR35[5:2]==VAR37)&&(VAR9[5:2]==VAR25)&&(VAR1==VAR33))
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else if((VAR35[5:2]==VAR28||VAR35[5:2]==VAR37)&&(VAR9[5:2]==VAR38||VAR9[5:2]==VAR37)&&(VAR1==VAR33))
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b1;
VAR39 = 1'b1;
end
else
begin
VAR32=1'b0;
VAR6=1'b0;
VAR30=1'b0;
VAR39=1'b0;
end
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.functional.v | 1,039 | module MODULE1 ();
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/xgmii_interleave.v | 2,161 | module MODULE1
(
input wire [63:0] VAR3,
input wire [7:0] VAR1,
output wire [72:0] VAR2
);
assign VAR2[7:0] = VAR3[7:0];
assign VAR2[8] = VAR1[0];
assign VAR2[16:9] = VAR3[15:8];
assign VAR2[17] = VAR1[1];
assign VAR2[25:18] = VAR3[23:16];
assign VAR2[26] = VAR1[2];
assign VAR2[34:27] = VAR3[31:24];
assign VAR2[35] = VAR1[3];
assign VAR2[43:36] = VAR3[39:32];
assign VAR2[44] = VAR1[4];
assign VAR2[52:45] = VAR3[47:40];
assign VAR2[53] = VAR1[5];
assign VAR2[61:54] = VAR3[55:48];
assign VAR2[62] = VAR1[6];
assign VAR2[70:63] = VAR3[63:56];
assign VAR2[71] = VAR1[7];
endmodule | mit |
cr88192/bgbtech_bjx1core | srvcore/ExUop.v | 19,087 | parameter[7:0] VAR66 = 8'h00; parameter[7:0] VAR17 = 8'h01;
parameter[7:0] VAR20 = 8'h02;
parameter[7:0] VAR59 = 8'h03;
parameter[7:0] VAR137 = 8'h04;
parameter[7:0] VAR46 = 8'h05;
parameter[7:0] VAR107 = 8'h06;
parameter[7:0] VAR86 = 8'h07;
parameter[7:0] VAR85 = 8'h08;
parameter[7:0] VAR172 = 8'h09;
parameter[7:0] VAR9 = 8'h0A;
parameter[7:0] VAR4 = 8'h0B;
parameter[7:0] VAR24 = 8'h0C;
parameter[7:0] VAR67 = 8'h0D;
parameter[7:0] VAR127 = 8'h0E;
parameter[7:0] VAR193 = 8'h0F;
parameter[7:0] VAR52 = 8'h10; parameter[7:0] VAR87 = 8'h11;
parameter[7:0] VAR171 = 8'h12;
parameter[7:0] VAR125 = 8'h13;
parameter[7:0] VAR161 = 8'h14;
parameter[7:0] VAR157 = 8'h15;
parameter[7:0] VAR159 = 8'h16;
parameter[7:0] VAR154 = 8'h17;
parameter[7:0] VAR160 = 8'h18;
parameter[7:0] VAR39 = 8'h19;
parameter[7:0] VAR40 = 8'h1A;
parameter[7:0] VAR83 = 8'h1B;
parameter[7:0] VAR6 = 8'h1C;
parameter[7:0] VAR94 = 8'h1D;
parameter[7:0] VAR197 = 8'h1E;
parameter[7:0] VAR142 = 8'h1F;
parameter[7:0] VAR156 = 8'h20;
parameter[7:0] VAR80 = 8'h21; parameter[7:0] VAR45 = 8'h22;
parameter[7:0] VAR84 = 8'h23;
parameter[7:0] VAR23 = 8'h24;
parameter[7:0] VAR65 = 8'h25;
parameter[7:0] VAR61 = 8'h27;
parameter[7:0] VAR91 = 8'h29; parameter[7:0] VAR19 = 8'h2A;
parameter[7:0] VAR58 = 8'h2B;
parameter[7:0] VAR2 = 8'h2C;
parameter[7:0] VAR48 = 8'h2D;
parameter[7:0] VAR173 = 8'h2F;
parameter[7:0] VAR101 = 8'h30;
parameter[7:0] VAR78 = 8'h31;
parameter[7:0] VAR123 = 8'h32;
parameter[7:0] VAR136 = 8'h33;
parameter[7:0] VAR149 = 8'h34;
parameter[7:0] VAR192 = 8'h36;
parameter[7:0] VAR47 = 8'h37;
parameter[7:0] VAR35 = 8'h39;
parameter[7:0] VAR50 = 8'h3A;
parameter[7:0] VAR97 = 8'h3B;
parameter[7:0] VAR176 = 8'h3C;
parameter[7:0] VAR56 = 8'h40;
parameter[7:0] VAR75 = 8'h41;
parameter[7:0] VAR128 = 8'h42;
parameter[7:0] VAR153 = 8'h43;
parameter[7:0] VAR28 = 8'h44;
parameter[7:0] VAR194 = 8'h45;
parameter[7:0] VAR190 = 8'h46;
parameter[7:0] VAR155 = 8'h47;
parameter[7:0] VAR57 = 8'h48;
parameter[7:0] VAR32 = 8'h4A;
parameter[7:0] VAR131 = 8'h4B;
parameter[7:0] VAR180 = 8'h4E;
parameter[7:0] VAR41 = 8'h4F;
parameter[7:0] VAR33 = 8'h50;
parameter[7:0] VAR76 = 8'h51;
parameter[7:0] VAR110 = 8'h52;
parameter[7:0] VAR27 = 8'h53;
parameter[7:0] VAR10 = 8'h54;
parameter[7:0] VAR126 = 8'h55;
parameter[7:0] VAR115 = 8'h56;
parameter[7:0] VAR31 = 8'h57;
parameter[7:0] VAR77 = 8'h58;
parameter[7:0] VAR199 = 8'h5A;
parameter[7:0] VAR37 = 8'h5B;
parameter[7:0] VAR44 = 8'h5C;
parameter[7:0] VAR21 = 8'h5D;
parameter[7:0] VAR53 = 8'h5E;
parameter[7:0] VAR195 = 8'h5F;
module MODULE1(clk, reset,
VAR134, VAR183,
VAR112, VAR11,
VAR120);
input clk; input reset;
output[47:0] VAR134; inout[31:0] VAR183; output VAR112; output VAR11; input VAR120;
reg[63:0] VAR181;
reg[31:0] VAR69;
reg[31:0] VAR130; reg[6:0] VAR93; reg[6:0] VAR12; reg[6:0] VAR144; reg[31:0] VAR34; reg[11:0] VAR186; reg[31:0] VAR121; reg[63:0] VAR143; reg[63:0] VAR54;
reg[31:0] VAR62; reg[31:0] VAR162; reg[7:0] VAR111;
reg[6:0] VAR191; reg[6:0] VAR18; reg[6:0] VAR99; reg[31:0] VAR22; reg[63:0] VAR71; reg[63:0] VAR55;
reg[6:0] VAR135; reg[6:0] VAR72; reg[6:0] VAR168; reg[31:0] VAR117;
reg[63:0] VAR16;
reg[63:0] VAR122;
reg[63:0] VAR187;
reg[63:0] VAR139;
reg[6:0] VAR138;
reg VAR124;
reg VAR175;
reg[63:0] VAR64;
reg[6:0] VAR102;
reg VAR25;
reg VAR118;
VAR182 VAR164(clk,
VAR25, VAR118, VAR102, VAR64,
VAR135, VAR16, VAR72, VAR122, VAR168, VAR187);
reg[63:0] VAR148;
reg[63:0] VAR90;
reg[63:0] VAR201;
reg[63:0] VAR151;
reg[63:0] VAR96;
reg[63:0] VAR7;
reg[63:0] VAR106;
reg[63:0] VAR81;
reg[63:0] VAR119;
reg[63:0] VAR150;
reg[63:0] VAR140;
reg[3:0] VAR165;
reg[3:0] VAR109;
VAR158 VAR129(clk, VAR165,
VAR148, VAR90, VAR201, VAR151[3:0], VAR109);
reg VAR89;
reg[63:0] VAR30;
reg[2:0] VAR114;
reg[31:0] VAR178;
VAR79 VAR104(clk, VAR114,
VAR122, VAR178, VAR117, VAR30);
assign VAR178 = VAR89 ? VAR187[31:0] : 0;
reg VAR146;
reg[3:0] VAR5;
reg[3:0] VAR108;
reg[63:0] VAR198;
VAR133 VAR8(clk, VAR146, VAR5, VAR122, VAR187, VAR16, VAR198,
VAR151[3:0], VAR108);
reg VAR105;
reg VAR88;
reg[2:0] VAR185;
reg[63:0] VAR167;
reg[63:0] VAR188;
reg[63:0] VAR169;
reg VAR166;
reg[47:0] VAR147;
wire[63:0] VAR184;
wire VAR98;
VAR70 VAR29(clk, reset,
VAR105, VAR88, VAR185,
VAR167, VAR188, VAR169,
VAR166, VAR147, VAR184,
VAR134, VAR183, VAR112, VAR11,
VAR98, VAR120);
reg[1:0] VAR74;
VAR141 VAR92(clk, VAR130, VAR151[31:0],
VAR93, VAR12, VAR144, VAR34, VAR74, VAR186, VAR121);
reg[63:0] VAR36;
reg[11:0] VAR103;
reg[11:0] VAR189;
reg VAR1;
reg VAR51;
reg[15:0] VAR174;
reg VAR177;
reg VAR14;
reg[2:0] VAR15;
reg[2:0] VAR73;
reg VAR145;
reg VAR200;
assign VAR177 = !reset && (VAR174==12345);
assign VAR14 = !VAR177 && !VAR98;
assign VAR7 = VAR164.VAR152;
assign VAR150 = VAR164.VAR26;
assign VAR151 = VAR164.VAR170;
always @ (clk)
begin
if(!VAR177)
begin
end
else if(VAR14)
begin
end
else
if((VAR98==0) && VAR177)
begin
if(!VAR1)
begin
VAR69=VAR184[31:0];
if(VAR184==0)
VAR69=32'hFFFFFFFF;
VAR54=VAR181;
end
else
begin
VAR69=VAR130;
end
VAR36[63:3]=61'h0;
VAR36[2:1]=VAR74[1:0];
VAR36[0]=1'b0;
if(VAR15>1)
begin
VAR106=VAR7;
VAR81=VAR7+4;
VAR189=VAR186;
VAR162=VAR121;
VAR55=VAR143;
end
else
if(!VAR1)
begin
if(VAR130==32'hFFFFFFFF)
VAR189=VAR186;
VAR162=VAR121;
VAR106=VAR181+VAR36;
VAR81=VAR181+VAR36;
VAR55=VAR143;
end
else
begin
if(!VAR98)
begin
end
VAR106=VAR7;
VAR81=VAR7+4;
end
VAR111=VAR62[31:24];
if(VAR15!=0)
begin
VAR73=VAR15-1;
VAR200=VAR145;
end
else
begin
VAR73=0;
VAR200=0;
end
if(VAR62[23]==0)
begin
VAR51=0;
end
else
begin
VAR189=VAR103+1;
VAR162=VAR92.VAR163[VAR189];
VAR51=1;
end
if(VAR15!=0)
VAR51=0;
case(VAR62[22:21])
2'b00:
begin
VAR135 = VAR191;
VAR72 = VAR18;
VAR168 = VAR99;
VAR117 = VAR22;
end
2'b10:
begin
VAR135 = VAR62[20:14];
VAR72 = VAR62[13: 7];
VAR168 = VAR62[ 6: 0];
VAR117 = VAR22;
end
2'b01:
begin
if(VAR62[20])
begin
VAR72 = VAR18;
VAR168 = VAR99;
VAR135[6:4] = 0;
VAR135[3:0] = VAR62[19:16];
VAR117[31:16] = VAR62[15] ? 16'hFFFF : 16'h0000 ;
VAR117[15:0] = VAR62[15:0];
end
else
begin
VAR135 = VAR191;
VAR72 = VAR18;
VAR168 = VAR99;
VAR117[31:20] = VAR62[19] ? 12'hFFF : 12'h000 ;
VAR117[19:0] = VAR62[19:0];
end
end
2'b11:
begin
VAR135[6:4] = 0;
VAR135[3:0] = VAR62[19:16];
VAR72[6:4] = 0;
VAR72[3:0] = VAR62[15:12];
VAR168[6:4] = 0;
VAR168[3:0] = VAR62[11: 8];
VAR117[31:8] = (VAR62[20] && VAR62[7]) ?
24'hFFFFFF : 24'h000000 ;
VAR117[ 7:0] = VAR62[7:0];
end
endcase
VAR148=VAR122;
VAR90=VAR187;
if(VAR72==VAR164.VAR49)
begin
VAR148[63: 0] = 0;
end
if(VAR168==VAR164.VAR3)
begin
VAR90[63:32] = VAR117[31] ? (-1) : 0;
VAR90[31: 0] = VAR117;
end
VAR139=VAR16;
VAR124=1'b0;
VAR175=1'b0;
VAR96=VAR151;
VAR140=VAR150;
VAR138=VAR135;
VAR89 = (VAR168[3:0]!=15);
VAR165=0;
VAR114=0;
VAR185=0;
VAR5=0;
VAR146=0;
case(VAR111[7:4])
4'h0:
begin
if(VAR111[3:0]==4'h0)
begin
VAR51 = 0;
end
else
begin
VAR165=VAR111[3:0];
VAR139=VAR201;
VAR124=VAR165<VAR129.VAR132;
VAR175=1'b0;
if(VAR165>=VAR129.VAR68)
begin
VAR96[31:1]=VAR151[31:1];
VAR96[0]=VAR109[0];
end
VAR60=%VAR113(%VAR113) VAR42=%VAR113(%VAR113) %VAR113",
VAR165,
VAR135, VAR16,
VAR72, VAR148,
VAR168, VAR90,
VAR201);
end
end
4'h1:
begin
if(VAR111[3:0]==4'h0)
begin
end
else
begin
VAR165=VAR111[3:0];
VAR139=VAR201;
VAR124=VAR165<VAR129.VAR132;
VAR175=1'b1;
if(VAR165>=VAR129.VAR68)
begin
VAR96[31:1]=VAR151[31:1];
VAR96[0]=VAR109[1];
end
end
end
4'h2:
begin
if(VAR111[3:0]==4'h0)
begin
VAR106 = VAR119 + (VAR90*2);
VAR73 = 2;
VAR82("3E VAR179 VAR196=%VAR113 %VAR113 (VAR38=%VAR113)",
VAR119, VAR106, VAR90);
end
else
begin
if(VAR168==VAR164.VAR63)
VAR114=VAR104.VAR95;
end
else
VAR114=VAR111[2:0];
if(VAR111[3])
begin
VAR138=VAR72;
VAR89 = 0;
end
VAR139=VAR30;
VAR124=1'b1;
VAR175 = (VAR111!=VAR61);
end
end
4'h3:
begin
if(VAR111[3:0]==4'h0)
begin
VAR140 = VAR81;
VAR106 = VAR81 + (VAR90*2);
VAR73 = 2;
VAR82("3E VAR13 VAR196=%VAR113 %VAR113 (VAR38=%VAR113)",
VAR119, VAR106, VAR90);
end
else
begin
if(VAR168==VAR164.VAR63)
VAR114=VAR104.VAR95;
end
else
VAR114=VAR111[2:0];
VAR185=VAR111[2:0];
VAR167=VAR30[63:0];
VAR124=VAR111[3];
VAR175=VAR111[2];
VAR169=VAR16;
VAR139=VAR188;
if(VAR111[3])
begin
VAR105=1'b0;
VAR88=1'b1;
end
else
begin
VAR105=1'b1;
VAR88=1'b0;
end
end
end
4'h4:
begin
if(VAR111[3:0]==4'h0)
begin
end
else
begin
VAR5=VAR111[3:0];
VAR139=VAR198;
VAR124=1;
VAR175=0;
if((VAR5!=VAR8.VAR100) || (VAR5!=VAR8.VAR43))
begin
VAR124=0;
VAR96[31:1]=VAR151[31:1];
VAR96[0]=VAR108[0];
end
end
end
4'h5:
begin
if(VAR111[3:0]==4'h0)
begin
if((VAR151[0]^VAR62[16])==0)
begin
VAR106 = VAR119 + (VAR90*2);
VAR73 = 2;
VAR200 = VAR62[17];
VAR82("3E VAR116 VAR196=%VAR113 %VAR113 (VAR38=%VAR113)",
VAR119, VAR106, VAR90);
end
end
else
begin
VAR5=VAR111[3:0];
VAR139=VAR198;
VAR124=1;
VAR175=1;
if((VAR5!=VAR8.VAR100) || (VAR5!=VAR8.VAR43))
begin
VAR124=0;
VAR96[31:1]=VAR151[31:1];
VAR96[0]=VAR108[0];
end
end
end
default: begin
end
endcase
if(VAR111==8'h40)
begin
case(VAR62[15:12])
4'h0:
case(VAR62[3:0])
4'h8:
case(VAR62[7:4])
4'h0:
VAR96[0]=0;
4'h1:
VAR96[0]=1;
4'h4:
case(VAR62[11:8])
4'h0: VAR96[1]=0;
4'h1: VAR96[12]=0;
4'h2: VAR96[31]=0;
4'h3: begin VAR96[31]=0; VAR96[12]=0; end
default: VAR96[1]=0;
endcase
4'h5:
case(VAR62[11:8])
4'h0: VAR96[1]=1;
4'h1: VAR96[12]=1;
4'h2: VAR96[31]=1;
4'h3: begin VAR96[31]=1; VAR96[12]=1; end
default: VAR96[1]=1;
endcase
4'h6:
VAR96[0]=!VAR151[0];
default: begin end
endcase
4'h9:
case(VAR62[7:4])
4'h0:
begin end 4'h1:
begin
VAR96[0]=0;
VAR96[8]=0;
VAR96[9]=0;
end
4'h2:
begin
VAR139[63:0]=0;
VAR139[0]=VAR151[0];
end
4'h3:
begin
VAR96[0]=VAR187[0];
end
default: begin end
endcase
4'hB:
case(VAR62[7:4])
4'h0:
VAR106=VAR150;
4'h1:
begin end
4'h2: begin
end
4'h3:
begin end default: begin end
endcase
default: begin end
endcase
default: begin
end
endcase
end
end
end
always @ (negedge clk)
begin
VAR64 <= VAR139;
VAR25 <= VAR124;
VAR118 <= VAR175;
VAR102 <= VAR138;
end
always @ (posedge clk)
begin
if(VAR98 || !VAR177)
begin
if(!reset)
VAR174 <= 12345;
end
else
VAR174 <= 0;
if(!VAR177)
begin
VAR164.VAR170 <= 0;
VAR164.VAR152 <= 0;
VAR164.VAR26 <= 0;
VAR147[47:0] <= 0;
VAR166 <= 1'b1;
end
end
else
begin
VAR164.VAR170 <= VAR96;
VAR164.VAR152 <= VAR106;
VAR164.VAR26 <= VAR140;
VAR15 <= VAR73;
VAR145 <= VAR200;
VAR147[47:0] <= VAR106[47:0];
VAR166 <= 1'b1;
VAR181 <= VAR106;
if((VAR15>1) || (VAR145!=0))
begin
VAR130 <= 32'h0F090F09;
VAR143 <= VAR181;
end
else
if(VAR15!=0)
begin
VAR130 <= VAR184[31:0];
VAR143 <= VAR181;
end
else
begin
VAR130 <= VAR184[31:0];
VAR143 <= VAR54;
end
VAR191 <= VAR93;
VAR18 <= VAR12;
VAR99 <= VAR144;
VAR22 <= VAR34;
VAR71 <= VAR55;
VAR119 <= VAR81;
VAR103 <= VAR189;
VAR62 <= VAR162;
VAR1 <= VAR51;
end
end
endmodule | mit |
combinatorylogic/soc | backends/c2/hw/blackice/vga640x480ice.v | 4,647 | module MODULE1(input clk, input VAR12,
input rst,
input [15:0] VAR26,
output [17:0] VAR32,
output reg VAR36,
input VAR27,
output VAR34,
output VAR13,
output [2:0] VAR10 );
reg VAR28;
reg VAR23;
wire [15:0] VAR30;
wire VAR37;
wire [15:0] VAR18;
wire VAR38;
reg [17:0] VAR31;
assign VAR32 = VAR31[17:0];
assign VAR30 = VAR26;
parameter VAR17 = (640*480/16) - 1;
VAR5 VAR33(.rst(rst),
.VAR1(clk),
.VAR30(VAR30),
.VAR28(VAR28),
.VAR37(VAR37),
.VAR6(VAR12),
.VAR18(VAR18),
.VAR38(VAR38),
.VAR23(VAR23));
always @(posedge clk)
if (!rst) begin
VAR28 <= 0;
VAR36 <= 0;
VAR31 <= 0;
end else begin if (!VAR37 && !VAR28 && !VAR27) begin
VAR36 <= 1;
end if (VAR28 && VAR36) begin
VAR36 <= 0;
VAR28 <= 0;
end else if (!VAR37 && !VAR28 && VAR27) begin
if (VAR31 < VAR17) VAR31 <= VAR31 + 1;
end
else begin
VAR31 <= 0;
end
VAR28 <= 1;
end else begin
VAR28 <= 0;
end
end
reg [9:0] VAR19;
reg [9:0] VAR4;
reg ready;
wire VAR11;
parameter VAR20 = 640;
parameter VAR3 = 96;
parameter VAR8 = 16;
parameter VAR21 = 48;
parameter VAR29 = 480;
parameter VAR14 = 10;
parameter VAR22 = 33;
parameter VAR25 = 2;
parameter VAR35 = VAR20 + VAR3 + VAR8 + VAR21;
parameter VAR16 = VAR29 + VAR25 + VAR14 + VAR22;
assign VAR34 = ~((VAR19 > VAR20+VAR8) & (VAR19 < VAR20+VAR8+VAR3));
assign VAR13 = ~((VAR4 > VAR29+VAR14) & (VAR4 < VAR29+VAR14+VAR25));
assign VAR11 = (VAR19 < VAR20)&&(VAR4 < VAR29);
always @(posedge VAR12)
if (!rst || !ready) begin VAR4 <= 0;
VAR19 <= 0;
end else begin
if (VAR19 >= VAR35-1) begin
VAR19 <= 0;
if (VAR4 >= VAR16-1)
VAR4 <= 0;
end
else
VAR4 <= VAR4 + 1;
end else VAR19 <= VAR19 + 1;
end
reg [15:0] VAR9;
reg [15:0] VAR2;
wire VAR24;
assign VAR24 = VAR9[15];
assign VAR10 = VAR11?{VAR24, VAR24,VAR24}:3'b0;
reg [3:0] VAR7;
reg VAR15;
always @(posedge VAR12)
if (!rst) begin
VAR7 <= 0;
VAR9 <= 0;
VAR2 <= 0;
ready <= 0;
VAR23 <= 0;
VAR15 <= 0;
end else begin
if (!ready) begin
if (VAR23) begin
VAR23 <= 0;
VAR9 <= VAR18;
ready <= 1;
VAR7 <= 15;
end else VAR23 <= 1;
end else
if (VAR11) begin
if (VAR7 < 15) begin
VAR7 <= VAR7 + 1;
VAR9 <= VAR9 << 1;
if (VAR23) begin
VAR2 <= VAR18;
VAR23 <= 0;
VAR15 <= 0;
end else
if ((VAR7 > 8) && VAR15) begin
VAR23 <= 1;
end
end else begin VAR23 <= 0;
VAR7 <= 0;
VAR9 <= VAR2;
VAR15 <= 1;
end
end else begin
VAR23 <= 0; VAR9 <= VAR2;
end
end
endmodule | mit |
zhaishaomin/ring_network-based-multicore- | core/core_if_id.v | 2,354 | module MODULE1( clk,
rst,
VAR15,
VAR10,
VAR1,
VAR13,
VAR6,
VAR16,
VAR4,
VAR12,
VAR14,
VAR2,
VAR17,
VAR3,
VAR8,
VAR11,
VAR7,
VAR9,
VAR5,
VAR18
);
input clk;
input rst;
input [31:0] VAR1;
input [31:0] VAR13;
input [31:0] VAR6;
input [31:0] VAR16;
input [1:0] VAR4;
input [2:0] VAR12;
input [1:0] VAR14;
input VAR2;
input VAR15;
input VAR10;
output [31:0] VAR17;
output [31:0] VAR3;
output [31:0] VAR8;
output [31:0] VAR11;
output [1:0] VAR7;
output [2:0] VAR9;
output [1:0] VAR5;
output VAR18;
reg [31:0] VAR3;
reg [31:0] VAR17;
reg [31:0] VAR8;
reg [31:0] VAR11;
reg [1:0] VAR7;
reg [2:0] VAR9;
reg [1:0] VAR5;
reg VAR18;
always@(posedge clk)
begin
if(rst||VAR10)
begin
VAR17<=32'h0000;
VAR3<=32'h0000;
VAR8<=32'h0000;
VAR11<=32'h0000;
VAR7<=2'b00;
VAR9<=3'b000;
VAR5<=2'b00;
VAR18<=1'b0;
end
else if(VAR15)
begin
VAR17<=VAR1;
VAR3<=VAR13;
VAR8<=VAR6;
VAR11<=VAR16;
VAR7<=VAR4;
VAR9<=VAR12;
VAR5<=VAR14;
VAR18<=VAR2;
end
end
endmodule | apache-2.0 |
mwswartwout/EECS318 | hw1/problem3/problem3.v | 1,941 | module MODULE1(out, VAR50, VAR23);
output [9:0] out;
input [4:0] VAR50, VAR23;
wire [4:0] VAR62, VAR46, VAR13, VAR52, VAR55;
wire VAR33, VAR59, VAR2, VAR39, VAR26, VAR25, VAR66, VAR48, VAR31, VAR51, VAR12, VAR6, VAR57, VAR67, VAR49, VAR7, VAR74, VAR64, VAR38, VAR15, VAR20, VAR43, VAR56, VAR10, VAR30, VAR11;
wire VAR28, VAR1, VAR17, VAR40, VAR4, VAR69, VAR3, VAR5, VAR24, VAR63, VAR71, VAR19, VAR36, VAR53, VAR60, VAR29, VAR70, VAR44;
assign VAR62 = {VAR50[4] && VAR23[0], VAR50[3] && VAR23[0], VAR50[2] && VAR23[0], VAR50[1] && VAR23[0], VAR50[0] && VAR23[0]};
assign VAR46 = {VAR50[4] && VAR23[1], VAR50[3] && VAR23[1], VAR50[2] && VAR23[1], VAR50[1] && VAR23[1], VAR50[0] && VAR23[1]};
assign VAR13 = {VAR50[4] && VAR23[2], VAR50[3] && VAR23[2], VAR50[2] && VAR23[2], VAR50[1] && VAR23[2], VAR50[0] && VAR23[2]};
assign VAR52 = {VAR50[4] && VAR23[3], VAR50[3] && VAR23[3], VAR50[2] && VAR23[3], VAR50[1] && VAR23[3], VAR50[0] && VAR23[3]};
assign VAR55 = {VAR50[4] && VAR23[4], VAR50[3] && VAR23[4], VAR50[2] && VAR23[4], VAR50[1] && VAR23[4], VAR50[0] && VAR23[4]};
assign out[0] = VAR62[0];
VAR73 VAR72(out[1], VAR33, VAR62[1], VAR46[0], 1'b0);
VAR73 VAR54(VAR28, VAR59, VAR62[2], VAR46[1], VAR33);
VAR73 VAR9(out[2], VAR2, VAR28, VAR13[0], VAR59);
VAR73 VAR42(VAR1, VAR39, VAR62[3], VAR46[2], VAR2);
VAR73 VAR78(VAR17, VAR26, VAR1, VAR13[1], VAR39);
VAR73 VAR35(out[3], VAR25, VAR17, VAR52[0], VAR26);
VAR73 VAR68(VAR40, VAR66, VAR62[4], VAR46[3], VAR25);
VAR73 VAR77(VAR4, VAR48, VAR40, VAR13[2], VAR66);
VAR73 VAR16(VAR69, VAR31, VAR4, VAR52[1], VAR48);
VAR73 VAR65(out[4], VAR51, VAR69, VAR55[0], VAR31);
VAR73 VAR21(VAR3, VAR12, VAR62[4], VAR46[4], VAR51);
VAR73 VAR32(VAR5, VAR6, VAR3, VAR13[3], VAR12);
VAR73 VAR61(VAR24, VAR57, VAR5, VAR52[2], VAR6);
VAR73 VAR58(out[5], VAR67, VAR24, VAR55[1], VAR57);
VAR73 VAR75(VAR63, VAR49, VAR62[4], VAR46[4], VAR67);
VAR73 VAR27(VAR71, VAR7, VAR63, VAR13[4], VAR49);
VAR73 VAR45(VAR19, VAR74, VAR71, VAR52[3], VAR7);
VAR73 VAR14(out[6], VAR64, VAR19, VAR55[2], VAR74);
VAR73 VAR18(VAR36, VAR38, VAR62[4], VAR46[4], VAR64);
VAR73 VAR8(VAR53, VAR15, VAR36, VAR13[4], VAR38);
VAR73 VAR41(VAR60, VAR20, VAR53, VAR52[4], VAR15);
VAR73 VAR76(out[7], VAR43, VAR60, VAR55[3], VAR20);
VAR73 VAR37(VAR29, VAR56, VAR62[4], VAR46[4], VAR43);
VAR73 VAR34(VAR70, VAR10, VAR29, VAR13[4], VAR56);
VAR73 VAR22(VAR44, VAR30, VAR70, VAR52[4], VAR10);
VAR73 VAR47(out[8], VAR11, VAR44, VAR55[4], VAR30);
assign out[9] = VAR11;
endmodule | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_ic_filter.v | 1,168 | module MODULE1(
VAR3,
VAR1,
VAR2 );
output VAR3;
input VAR1;
input VAR2;
assign VAR3 = VAR1 ;
endmodule | gpl-2.0 |
MeshSr/onetswitch30 | ons30-app21-ref_switch/vivado/onets_7030_4x_ref_switch/ip/ref_switch_core/src/udp/ethernet_parser_64bit.v | 3,629 | module MODULE1
parameter VAR20=VAR8/8,
parameter VAR6 = 3,
parameter VAR19 = 2
)
( input [VAR8-1:0] VAR7,
input [VAR20-1:0] VAR14,
input VAR16,
output reg [47:0] VAR3,
output reg [47:0] VAR17,
output reg [15:0] VAR13,
output reg VAR10,
output reg [VAR6-1:0] VAR23,
input reset,
input clk
);
parameter VAR21 = 3;
parameter VAR18 = 1;
parameter VAR1 = 2;
parameter VAR22 = 4;
reg [VAR21-1:0] state;
reg [VAR21-1:0] VAR9;
reg [47:0] VAR11;
reg [47:0] VAR24;
reg [15:0] VAR4;
reg VAR12;
reg [VAR6-1:0] VAR5;
always @(*) begin
VAR11 = VAR3;
VAR24 = VAR17;
VAR4 = VAR13;
VAR12 = VAR10;
VAR5 = VAR23;
VAR9 = state;
case(state)
VAR18: begin
if(VAR16 && VAR14==VAR2) begin
VAR5 = VAR7[VAR15 + VAR6 - 1 : VAR15];
end
else if(VAR16 && VAR14==0) begin
VAR11 = VAR7[63:16] ;
VAR24[47:32] = VAR7[15:0];
VAR9 = VAR1;
end
end
VAR1: begin
if(VAR16) begin
VAR24 [31:0] = VAR7[63:32];
VAR4 = VAR7[31:16];
VAR9 = VAR22;
VAR12 = 1;
end
end
VAR22: begin
if(VAR16 && VAR14!=0) begin
VAR12 = 0;
VAR9 = VAR18;
end
end
endcase end
always @(posedge clk) begin
if(reset) begin
VAR17 <= 0;
VAR3 <= 0;
VAR13 <= 0;
VAR10 <= 0;
state <= VAR18;
VAR23 <= 0;
end
else begin
VAR17 <= VAR24;
VAR3 <= VAR11;
VAR13 <= VAR4;
VAR10 <= VAR12;
state <= VAR9;
VAR23 <= VAR5;
end end
endmodule | lgpl-2.1 |
binderclip/BCOpenMIPS | cpu-code/div.v | 3,404 | module MODULE1 (
input wire clk,
input wire rst,
input wire VAR13,
input wire[VAR23] VAR16, input wire[VAR23] VAR12, input wire VAR6,
input wire VAR22,
output reg[VAR11] VAR14,
output reg VAR26
);
wire[32:0] VAR17;
reg[5:0] VAR9;
reg[VAR11] VAR5;
reg[1:0] state; reg[VAR23] VAR4;
wire[VAR23] VAR3;
wire[VAR23] VAR19;
assign VAR17 = VAR5[63:31] - VAR4;
assign VAR3 = (VAR13 == VAR20 && VAR16[31] == 1'b1) ? (~VAR16 + 1) : VAR16;
assign VAR19 = (VAR13 == VAR20 && VAR12[31] == 1'b1) ? (~VAR12 + 1) : VAR12;
always @(posedge clk) begin
if (rst == VAR1) begin
state <= VAR2;
VAR26 <= VAR18;
VAR14 <= {VAR24, VAR24};
end
else begin
case (state)
if (VAR6 == VAR15 && VAR22 == VAR21) begin
if (VAR12 == VAR24) begin
state <= VAR27;
end
else begin
state <= VAR8;
VAR9 <= 0;
VAR5 <= {VAR24, VAR3};
VAR4 <= VAR19;
end
end
else begin
VAR26 <= VAR18;
VAR14 <= {VAR24, VAR24};
end
end
if (VAR22 == VAR21) begin
if (VAR9 != 32) begin if (VAR17[32] == 1'b1) begin
VAR5 <= {VAR5[62:0], 1'b0};
end
else begin
VAR5 <= {VAR17[31:0], VAR5[30:0], 1'b1};
end
VAR9 <= VAR9 + 1;
end
else begin if (VAR13 == VAR20 && (VAR16[31] ^ VAR12[31]) == 1'b1) begin
VAR5[31:0] <= ~VAR5[31:0] + 1;
end
if (VAR13 == VAR20 && VAR16[31] == 1'b1) begin
VAR5[63:32] <= ~VAR5[63:32] + 1;
end
state <= VAR25;
VAR9 <= 0;
end
end
else begin
state <= VAR2;
end
end
VAR5 <= {VAR24, VAR24};
state <= VAR25;
end
VAR14 <= {VAR5[63:32], VAR5[31:0]};
VAR26 <= VAR10;
if (VAR6 == VAR7) begin
state <= VAR2;
VAR26 <= VAR18;
VAR14 <= {VAR24, VAR24};
end
end
endcase
end
end
endmodule | mit |
Beck-Sisyphus/EE471 | Lab4/sourceCode/DE1_SoCPhaseII.v | 6,562 | module MODULE1 (VAR49, VAR1, VAR19, VAR11);
input VAR49; output [9:0] VAR1;
input [9:0] VAR19;
input [3:0] VAR11;
reg [2:0] VAR37, VAR29;
wire [15:0] VAR30;
reg [7:0] VAR34; reg VAR33, VAR7;
reg [10:0] VAR28;
reg [15:0] VAR51;
reg [2:0] VAR38;
wire rst, VAR4;
reg [4:0] VAR20, VAR8, VAR43;
reg [31:0] VAR13;
wire [31:0] VAR45, VAR47;
wire [2:0] VAR9;
wire [4:0] VAR25, VAR41;
reg [31:0] VAR3, VAR14;
wire [31:0] VAR17;
wire VAR48, VAR21, VAR12, VAR27;
assign VAR4 = VAR19[6]; assign rst = VAR19[9];
assign VAR30 = VAR33 ? 16'VAR46 : VAR51; assign VAR1[3:0] = {VAR48, VAR21, VAR12, VAR27};
VAR50 memory(VAR49, VAR28, VAR33, VAR30);
VAR23 VAR26(VAR49, VAR20, VAR8, VAR43, VAR7, VAR13, VAR45, VAR47);
VAR10 VAR32(VAR49, VAR38, VAR3, VAR14, VAR17, VAR48, VAR21, VAR12, VAR27);
VAR42 VAR2(VAR30, VAR9, VAR25, VAR41);
parameter VAR44 = 3'b000, VAR24 = 3'b001, VAR22 = 3'b010,
VAR36 = 3'b011, VAR16 = 3'b100, VAR31 = 3'b101, VAR15 = 3'b110, VAR40 = 3'VAR6;
always @(posedge VAR49)
case (VAR19[6:4])
VAR44 : begin VAR33 = 0;
VAR7 = 1;
VAR43 = 0;
VAR13 = 0;
VAR20 = 0;
VAR8 = 16;
VAR38 = 0;
VAR28 = VAR34[6:0] + 8'h80;
VAR51 = 7'b1111111 - VAR34[6:0];
end
VAR24: begin VAR33 = 0;
VAR7 = 1;
VAR28 = VAR34[6:0];
VAR51 = {VAR34[6:4], {1'b0, VAR34[3:0]}, {1'b1, VAR34[3:0]}, 3'b0};
end
VAR22 : begin VAR33 = 1;
VAR7 = 0;
VAR28 = VAR34[4:0] + 8'h80;
VAR20 = 0;
VAR8 = 16;
VAR38 = 0;
VAR43 = VAR34[4:0];
VAR13= {{16{VAR30[15]}}, VAR30};
end
VAR36 : begin if(VAR34[0]) begin
VAR33 = 1;
VAR7 = 1;
VAR28 = VAR34[7:1];
VAR20 = VAR25;
VAR8 = VAR41;
VAR38 = VAR9;
VAR3 = VAR45;
VAR14 = VAR47;
end else begin
VAR33 = 1;
VAR7 = 0;
VAR43 = VAR25;
VAR13= VAR17;
end
end
default : begin
VAR33 = 1'VAR6;
VAR7 = 1'VAR6;
VAR29 = VAR40;
end
endcase
always @(posedge VAR49) begin
if (rst) begin
VAR34 <= 8'b0;
end
else begin
VAR34 <= VAR34 + 1'b1;
end
end
endmodule
module MODULE2();
reg VAR49; wire [9:0] VAR1;
reg [9:0] VAR19;
reg [3:0] VAR11;
MODULE1 MODULE1 (VAR49, VAR1, VAR19, VAR11);
parameter VAR39 = 100;
VAR18 VAR49 = 1;
always begin
VAR49 = ~VAR49;
end
integer VAR5; | mit |
trander1/Generic-Cache-Block | Verilog Files/multilevel_cache_top.v | 6,890 | module MODULE1(
VAR3, VAR28,
VAR22, clk
);
parameter VAR39 = 4; parameter VAR34 = 4;
parameter VAR4 = 1; parameter VAR19 = 16;
parameter VAR35 = 2;
parameter VAR16 = VAR39+VAR34+VAR35;
parameter VAR37 = VAR8(VAR4); parameter VAR27 = VAR8(VAR19); output reg [VAR34-1:0]VAR3;output reg VAR28; input [VAR16-1:0]VAR22; input clk; wire [VAR16-1:0]VAR14; wire [VAR34-1:0]VAR23; wire [VAR34-1:0]VAR5; wire [VAR39-1:0]VAR25; wire [VAR39-1:0]VAR36; wire [VAR34-1:0]VAR18;wire [VAR34-1:0]VAR38;wire VAR17; wire VAR2; reg [VAR16-1:0]VAR13; reg [VAR16-1:0]VAR31; reg VAR11; reg VAR30; reg [VAR39-1:0]VAR7; reg [VAR34-1:0]VAR33; reg VAR1; reg VAR40; reg [VAR35-1:0]VAR24; reg [VAR39-1:0]VAR20; reg [VAR16-1:0]VAR29; reg [3:0]state; reg [3:0]VAR15; reg [VAR39-1:0]VAR9;
reg [VAR34-1:0]VAR6;
VAR12 #(VAR39,VAR34,VAR4) VAR21 (
.VAR3(VAR23),
.VAR26(VAR18),
.VAR10(VAR25),
.VAR28(VAR17),
.VAR22(VAR13),
.clk(clk),
.enable(VAR1)
);
VAR12 #(VAR39,VAR34,VAR19) VAR32 (
.VAR3(VAR5),
.VAR26(VAR38),
.VAR10(VAR36),
.VAR28(VAR2),
.VAR22(VAR31),
.clk(clk),
.enable(VAR40)
);
begin
begin
begin
begin
end else
begin
begin
end else
begin
begin
begin
begin | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/ram16_2port.v | 1,205 | module MODULE1 (input VAR3, input write,
input [3:0] VAR6, input [15:0] VAR4,
input [3:0] VAR5, output reg [15:0] VAR1,
input [3:0] VAR2, output reg [15:0] VAR7);
reg [15:0] VAR8 [0:31];
always @(posedge VAR3)
VAR1 <= VAR8[VAR5];
always @(posedge VAR3)
VAR7 <= VAR8[VAR2];
always @(posedge VAR3)
if(write)
VAR8[VAR6] <= VAR4;
endmodule | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/shd_fifo_stub.v | 1,365 | module MODULE1(rst, VAR5, VAR3, din, VAR6, VAR1, dout, VAR4, VAR2)
;
input rst;
input VAR5;
input VAR3;
input [255:0]din;
input VAR6;
input VAR1;
output [255:0]dout;
output VAR4;
output VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp.functional.pp.v | 1,840 | module MODULE1 (
VAR4,
VAR3,
VAR16 ,
VAR9,
VAR6,
VAR11 ,
VAR14
);
output VAR4;
input VAR3;
input VAR16 ;
input VAR9;
input VAR6;
input VAR11 ;
input VAR14 ;
wire VAR10 ;
wire VAR2 ;
wire VAR13 ;
wire VAR5;
not VAR8 (VAR2 , VAR16 );
VAR12 VAR15 VAR7 (VAR10 , VAR3, VAR2, , VAR9, VAR6);
and VAR1 (VAR4 , VAR10, VAR16 );
endmodule | apache-2.0 |
Seeed-Studio/DSOQuad_SourceCode | FPGA_V2.5/Signal.v | 8,476 | module MODULE1( VAR31, VAR34, VAR9, VAR39, VAR49, VAR7,
VAR38, VAR23,
VAR45, VAR4, VAR26,
VAR28, VAR42, VAR24, VAR27, VAR30, VAR18,
VAR22, VAR2, VAR10, VAR47, VAR17, VAR29, );
input VAR31; input VAR34; input [ 7:0]VAR9; input [ 7:0]VAR39; input [15:0]VAR49; input [17:0]VAR7; input VAR38;
input [ 7:0]VAR23;
output VAR45; output VAR4; output VAR26;
output [15:0]VAR28; output [15:0]VAR42; output [15:0]VAR24;
output [15:0]VAR27; output [15:0]VAR30; output [15:0]VAR18;
output [15:0]VAR22; output [15:0]VAR2; output [15:0]VAR10;
output [15:0]VAR47; output [15:0]VAR17; output [15:0]VAR29;
reg VAR45;
wire [ 8:0]VAR14;
wire [ 8:0]VAR6;
wire [ 8:0]VAR40;
wire [ 8:0]VAR51;
reg VAR3;
reg VAR36;
reg VAR25;
reg VAR19;
reg VAR1;
reg VAR44;
reg [11:0]VAR12;
reg [15:0]VAR28;
reg [15:0]VAR42;
reg [15:0]VAR24;
reg VAR21;
reg VAR50;
reg VAR41;
reg VAR16;
reg VAR15;
reg VAR20;
reg [11:0]VAR33;
reg [15:0]VAR27;
reg [15:0]VAR30;
reg [15:0]VAR18;
reg VAR5;
reg VAR46;
reg VAR32;
reg VAR48;
reg VAR8;
reg [11:0]VAR52;
reg [15:0]VAR22;
reg [15:0]VAR2;
reg [15:0]VAR10;
reg VAR11;
reg VAR53;
reg VAR43;
reg VAR35;
reg VAR13;
reg [11:0]VAR37;
reg [15:0]VAR47;
reg [15:0]VAR17;
reg [15:0]VAR29;
assign VAR4 = VAR34;
assign VAR26 = VAR23[1] ? ( ~VAR34 ) : ( VAR34 );
assign VAR14 = VAR39 + 12;
assign VAR6 = VAR39 - 12;
assign VAR40 = VAR39 + 1;
assign VAR51 = VAR39 - 1;
always @( posedge VAR34 or posedge VAR31 ) begin
if ( VAR31 ) begin
VAR45 <= 0;
VAR25 <= 0;
VAR19 <= 0;
VAR1 <= 0;
VAR44 <= 0;
VAR28 <= 0;
VAR42 <= 0;
VAR24 <= 0;
VAR41 <= 0;
VAR16 <= 0;
VAR15 <= 0;
VAR20 <= 0;
VAR27 <= 0;
VAR30 <= 0;
VAR18 <= 0;
VAR46 <= 0;
VAR32 <= 0;
VAR48 <= 0;
VAR8 <= 0;
VAR22 <= 0;
VAR2 <= 0;
VAR10 <= 0;
VAR53 <= 0;
VAR43 <= 0;
VAR35 <= 0;
VAR13 <= 0;
VAR47 <= 0;
VAR17 <= 0;
VAR29 <= 0;
end else begin
if ( VAR7[ 7:0] > VAR40 ) VAR36 <= 1;
if ( VAR7[ 7:0] < VAR51 ) VAR36 <= 0;
if (( VAR7[ 7:0] > VAR14 )&&( ~VAR3 )) begin
if ( VAR12 < VAR49 ) VAR25 <= VAR38;
end
else VAR1 <= VAR38;
VAR3 <= 1;
VAR12 <= 0;
VAR28 <= VAR28 + 1;
VAR42 <= VAR42 + VAR12;
end else
if (( VAR7[ 7:0] < VAR6 )&&( VAR3 )) begin
if ( VAR12 < VAR49 ) VAR19 <= VAR38;
end
else VAR44 <= VAR38;
VAR3 <= 0;
VAR12 <= 0;
VAR28 <= VAR28 + 1;
VAR24 <= VAR24 + VAR12;
end else VAR12 <= VAR12 + 1;
if ( VAR7[15:8] > VAR40 ) VAR50 <= 1;
if ( VAR7[15:8] < VAR51 ) VAR50 <= 0;
if (( VAR7[15:8] > VAR14 )&&( ~VAR21 )) begin
if ( VAR33 < VAR49 ) VAR41 <= VAR38;
end
else VAR15 <= VAR38;
VAR21 <= 1;
VAR33 <= 0;
VAR27 <= VAR27 + 1;
VAR30 <= VAR30 + VAR33;
end else
if (( VAR7[15:8] < VAR6 )&&( VAR21 )) begin
if ( VAR33 < VAR49 ) VAR16 <= VAR38;
end
else VAR20 <= VAR38;
VAR21 <= 0;
VAR33 <= 0;
VAR27 <= VAR27 + 1;
VAR18 <= VAR18 + VAR33;
end else VAR33 <= VAR33 + 1;
if ( VAR7[16] != VAR5 ) begin
if ( VAR52 < VAR49 ) begin
if ( VAR7[16] ) VAR46 <= VAR38;
end
else VAR32 <= VAR38;
end else begin
if ( VAR7[16] ) VAR48 <= VAR38;
end
else VAR8 <= VAR38;
end
VAR52 <= 0;
VAR22 <= VAR22 + 1;
if ( ~VAR5 ) VAR2 <= VAR2 + VAR52;
end
else VAR10 <= VAR10 + VAR52;
end else VAR52 <= VAR52 + 1;
VAR5 <= VAR7[16];
if ( VAR7[17] != VAR11 ) begin
if ( VAR37 < VAR49 ) begin
if ( VAR7[17] ) VAR53 <= VAR38;
end
else VAR43 <= VAR38;
end else begin
if ( VAR7[17] ) VAR35 <= VAR38;
end
else VAR13 <= VAR38;
end
VAR37 <= 0;
VAR47 <= VAR47 + 1;
if ( ~VAR11 ) VAR17 <= VAR17 + VAR37;
else VAR29 <= VAR29 + VAR37;
end else VAR37 <= VAR37 + 1;
VAR11 <= VAR7[17];
case( VAR9 )
8'h00: if (( VAR7[ 7:0] < VAR39 )&&( VAR3 )) VAR45 <= VAR38; 8'h01: if (( VAR7[ 7:0] > VAR39 )&&( ~VAR3 )) VAR45 <= VAR38; 8'h02: if (( VAR7[ 7:0] < VAR39 )&&( VAR36 )) VAR45 <= VAR38; 8'h03: if (( VAR7[ 7:0] > VAR39 )&&( ~VAR36 )) VAR45 <= VAR38; 8'h04: VAR45 <= VAR25; 8'h05: VAR45 <= VAR1; 8'h06: VAR45 <= VAR19; 8'h07: VAR45 <= VAR44; 8'h08: if (( VAR7[15:8] < VAR39 )&&( VAR21 )) VAR45 <= VAR38; 8'h09: if (( VAR7[15:8] > VAR39 )&&( ~VAR21 )) VAR45 <= VAR38; 8'h0A: if (( VAR7[15:8] < VAR39 )&&( VAR50 )) VAR45 <= VAR38; 8'h0B: if (( VAR7[15:8] > VAR39 )&&( ~VAR50 )) VAR45 <= VAR38; 8'h0C: VAR45 <= VAR41; 8'h0D: VAR45 <= VAR15; 8'h0E: VAR45 <= VAR16; 8'h0F: VAR45 <= VAR20; 8'h10: if (( ~VAR7[16] )&&( VAR5 )) VAR45 <= VAR38; 8'h11: if (( VAR7[16] )&&( ~VAR5 )) VAR45 <= VAR38; 8'h12: if (( ~VAR7[16] )&&( VAR5 )) VAR45 <= VAR38; 8'h13: if (( VAR7[16] )&&( ~VAR5 )) VAR45 <= VAR38; 8'h14: VAR45 <= VAR46; 8'h15: VAR45 <= VAR48; 8'h16: VAR45 <= VAR32; 8'h17: VAR45 <= VAR8; 8'h18: if (( ~VAR7[17] )&&( VAR11 )) VAR45 <= VAR38; 8'h19: if (( VAR7[17] )&&( ~VAR11 )) VAR45 <= VAR38; 8'h1A: if (( ~VAR7[17] )&&( VAR11 )) VAR45 <= VAR38; 8'h1B: if (( VAR7[17] )&&( ~VAR11 )) VAR45 <= VAR38; 8'h1C: VAR45 <= VAR53; 8'h1D: VAR45 <= VAR35; 8'h1E: VAR45 <= VAR43; 8'h1F: VAR45 <= VAR13; default: VAR45 <= 1;
endcase
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp.behavioral.v | 1,341 | module MODULE1 (
VAR9,
VAR3
);
output VAR9;
input VAR3;
supply1 VAR8;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR2 ;
wire VAR5;
not VAR1 (VAR5, VAR3 );
buf VAR7 (VAR9 , VAR5 );
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.srcs/sources_1/bd/block_design/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_nto1_mux.v | 4,820 | module MODULE1 #
(
parameter integer VAR6 = 1, parameter integer VAR12 = 1, parameter integer VAR8 = 1, parameter integer VAR14 = 0 )
(
input wire [VAR6-1:0] VAR5, input wire [VAR12-1:0] VAR2, input wire [VAR6*VAR8-1:0] VAR1, output wire [VAR8-1:0] VAR4 );
wire [VAR8*VAR6-1:0] VAR9;
genvar VAR3;
generate
if (VAR14 == 0) begin : VAR10
assign VAR9[VAR8-1:0] = {VAR8{(VAR2==0)?1'b1:1'b0}} & VAR1[VAR8-1:0];
for (VAR3=1;VAR3<VAR6;VAR3=VAR3+1) begin : VAR7
assign VAR9[(VAR3+1)*VAR8-1:VAR3*VAR8] =
VAR9[VAR3*VAR8-1:(VAR3-1)*VAR8] |
{VAR8{(VAR2==VAR3)?1'b1:1'b0}} & VAR1[(VAR3+1)*VAR8-1:VAR3*VAR8];
end
end else begin : VAR13
assign VAR9[VAR8-1:0] = {VAR8{VAR5[0]}} & VAR1[VAR8-1:0];
for (VAR3=1;VAR3<VAR6;VAR3=VAR3+1) begin : VAR11
assign VAR9[(VAR3+1)*VAR8-1:VAR3*VAR8] =
VAR9[VAR3*VAR8-1:(VAR3-1)*VAR8] |
{VAR8{VAR5[VAR3]}} & VAR1[(VAR3+1)*VAR8-1:VAR3*VAR8];
end
end
endgenerate
assign VAR4 = VAR9[VAR8*VAR6-1:
VAR8*(VAR6-1)];
endmodule | gpl-3.0 |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_slice_1_0_0/RAT_slice_1_0_0_stub.v | 1,218 | module MODULE1(VAR1, VAR2)
;
input [17:0]VAR1;
output [7:0]VAR2;
endmodule | mit |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/vga.v | 1,403 | module MODULE1
(
input clk,
output wire VAR1,
output wire VAR6,
output reg [VAR3 - 1:0] VAR4,
output reg [VAR3 - 1:0] VAR2,
output wire VAR5
);
begin
end
begin
begin
end | unlicense |
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