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SiLab-Bonn/monopix_daq | firmware/src/pulse_gen640/pulse_gen640_core.v | 8,042 | module MODULE1
parameter VAR30 = 16,
parameter VAR26 = 4, parameter VAR35 =2
)
(
input wire VAR56,
input wire [VAR30-1:0] VAR19,
input wire [7:0] VAR70,
output reg [7:0] VAR57,
input wire VAR80,
input wire VAR45,
input wire VAR23,
input wire VAR58,
input wire VAR61,
input wire VAR10,
input wire VAR81,
output wire [VAR35-1:0] VAR54,
output wire VAR31
);
localparam VAR59 = 1;
wire VAR44;
wire VAR63;
reg VAR65;
reg [31:0] VAR37;
reg [31:0] VAR6;
reg [31:0] VAR12;
reg [15:0] VAR4;
reg VAR75;
always@(posedge VAR56) begin
if(VAR23) begin
if(VAR19 == 0)
VAR57 <= VAR59;
end
else if(VAR19 == 1)
VAR57 <= {7'b0, VAR75};
end
else if(VAR19 == 2)
VAR57 <= {7'b0, VAR65};
else if(VAR19 == 3)
VAR57 <= VAR37[7:0];
else if(VAR19 == 4)
VAR57 <= VAR37[15:8];
else if(VAR19 == 5)
VAR57 <= VAR37[23:16];
else if(VAR19 == 6)
VAR57 <= VAR37[31:24];
else if(VAR19 == 7)
VAR57 <= VAR6[7:0];
else if(VAR19 == 8)
VAR57 <= VAR6[15:8];
else if(VAR19 == 9)
VAR57 <= VAR6[23:16];
else if(VAR19 == 10)
VAR57 <= VAR6[31:24];
else if(VAR19 == 11)
VAR57 <= VAR12[7:0];
else if(VAR19 == 12)
VAR57 <= VAR12[15:8];
else if(VAR19 == 13)
VAR57 <= VAR12[23:16];
else if(VAR19 == 14)
VAR57 <= VAR12[31:24];
else if(VAR19 == 15)
VAR57 <= VAR4[7:0];
else if(VAR19 == 16)
VAR57 <= VAR4[15:8];
else if(VAR19 == 17)
VAR57 <= VAR52[7:0];
else if(VAR19 == 18)
VAR57 <= VAR52[15:8];
else if(VAR19 == 19)
VAR57 <= VAR52[23:16];
else if(VAR19 == 20)
VAR57 <= VAR52[31:24];
else if(VAR19 == 21)
VAR57 <= {6'b0,VAR7, VAR52[32]};
else
VAR57 <= 8'b0;
end
end
assign VAR44 = (VAR19==0 && VAR45);
assign VAR63 = (VAR19==1 && VAR45);
wire VAR33;
assign VAR33 = VAR80 | VAR44;
always @(posedge VAR56) begin
if(VAR33) begin
VAR65 <= 0;
VAR37 <= 0;
VAR6 <= 0;
VAR12 <= 1;
end
else if(VAR45) begin
if(VAR19 == 2)
VAR65 <= VAR70[0];
end
else if(VAR19 == 3)
VAR37[7:0] <= VAR70;
end
else if(VAR19 == 4)
VAR37[15:8] <= VAR70;
else if(VAR19 == 5)
VAR37[23:16] <= VAR70;
else if(VAR19 == 6)
VAR37[31:24] <= VAR70;
else if(VAR19 == 7)
VAR6[7:0] <= VAR70;
else if(VAR19 == 8)
VAR6[15:8] <= VAR70;
else if(VAR19 == 9)
VAR6[23:16] <= VAR70;
else if(VAR19 == 10)
VAR6[31:24] <= VAR70;
else if(VAR19 == 11)
VAR12[7:0] <= VAR70;
else if(VAR19 == 12)
VAR12[15:8] <= VAR70;
else if(VAR19 == 13)
VAR12[23:16] <= VAR70;
else if(VAR19 == 14)
VAR12[31:24] <= VAR70;
else if(VAR19 == 15)
VAR4[7:0] <= VAR70;
else if(VAR19 == 16)
VAR4[15:8] <= VAR70;
end
end
wire VAR2;
wire VAR40;
VAR68 VAR72 (.VAR69(VAR56), .VAR22(VAR33), .VAR55(VAR58), .VAR29(VAR40));
assign VAR2 = VAR40 || VAR80;
wire VAR16;
VAR68 VAR64 (.VAR69(VAR56), .VAR22(VAR63), .VAR55(VAR58), .VAR29(VAR16));
wire VAR28;
reg [2:0] VAR34;
always @(posedge VAR58) begin
VAR34[0] <= VAR81;
VAR34[1] <= VAR34[0];
VAR34[2] <= VAR34[1];
end
assign VAR28 = !VAR34[2] & VAR34[1];
reg [31:0] VAR52;
wire [32:0] VAR48;
assign VAR48 = VAR37 + VAR6;
reg [31:0] VAR53;
always @ (posedge VAR58) begin
if (VAR2)
VAR53 <= 0;
end
else if(VAR16 || (VAR28 && VAR65))
VAR53 <= VAR12;
else if(VAR53 != 0 && VAR52 == 1)
VAR53 <= VAR53 - 1;
end
always @ (posedge VAR58) begin
if (VAR2)
end
VAR52 <= 0; else if(VAR16 || (VAR28 && VAR65))
VAR52 <= 1;
else if(VAR52 == VAR48 && VAR53 != 0)
VAR52 <= 1;
else if(VAR52 == VAR48 && VAR12==0)
VAR52 <= 1;
else if(VAR52 == VAR48 && VAR53 == 0)
VAR52 <= 0;
else if(VAR52 != 0)
VAR52 <= VAR52 + 1;
end
reg [VAR26*4-1:0] VAR62;
reg VAR7;
always @ (posedge VAR58) begin
if(VAR2 || VAR16 || (VAR28 && VAR65)) begin
VAR62 <= 0;
VAR7<=0;
end
else if(VAR52 == VAR37 && VAR52 > 0) begin
VAR7<=1;
VAR62 <= VAR4;
end
else if(VAR52 == VAR37+1) begin
VAR62 <= 16'b1111111111111111;
VAR7<=1;
end
else if(VAR52 == VAR48) begin
VAR62 <= 0;
VAR7<=0;
end
end
assign VAR31 = VAR7;
wire VAR82;
reg [1:0] VAR11;
always @ (posedge VAR61)
VAR11[1:0] <= {VAR11[0],VAR58};
assign VAR82 = VAR58 & ~VAR11[0];
reg [VAR26*4-1:0] VAR15;
always @ (negedge VAR61) begin
if(VAR2 || VAR16 || (VAR28 && VAR65))
VAR15 <= 0;
end
else if (VAR82==1)
VAR15 <= VAR62;
else
VAR15[VAR26*4-2:0] <= {VAR15[VAR26*4-1],VAR15[VAR26*4-1],
VAR15[VAR26*4-1],VAR15[VAR26*4-1:4]};
end
genvar VAR8;
generate
for (VAR8=0; VAR8<2; VAR8=VAR8+1) begin
VAR21 # (
.VAR14("VAR39"),
.VAR49(4),
.VAR17("VAR83")
) VAR42 (
.VAR9(VAR54[VAR8]),
.VAR20(),
.VAR32(),
.VAR78(),
.VAR50(),
.VAR67(),
.VAR18(VAR10),
.VAR71(VAR61),
.VAR1(VAR15[0]),
.VAR74(VAR15[1]),
.VAR41(VAR15[2]),
.VAR85(VAR15[3]),
.VAR51(),
.VAR38(),
.VAR76(),
.VAR46(),
.VAR24(0),
.VAR25(1),
.VAR84(),
.VAR43(),
.VAR33(VAR2),
.VAR73(),
.VAR13(),
.VAR66(0),
.VAR27(0),
.VAR60(0),
.VAR79(0)
);
end
endgenerate
wire VAR77;
assign VAR77 = (VAR52 == 0);
wire VAR5;
VAR68 VAR3 (.VAR69(VAR58), .VAR22(VAR77), .VAR55(VAR56), .VAR29(VAR5));
wire VAR36;
VAR68 VAR47 (.VAR69(VAR58), .VAR22(VAR81 && VAR65), .VAR55(VAR56), .VAR29(VAR36));
always @(posedge VAR56)
if(VAR33)
VAR75 <= 1;
else if(VAR63 || VAR36)
VAR75 <= 0;
else if(VAR5)
VAR75 <= 1;
endmodule | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_gt_common.v | 7,333 | module MODULE1 #(
parameter VAR7 = "VAR32", parameter VAR19 = "VAR14", parameter VAR38 = "2.1", parameter VAR31 = "VAR30", parameter VAR10 = 0 )
(
input VAR26,
input VAR20,
input VAR52,
input VAR18,
input VAR41,
input VAR46,
input VAR56,
input VAR11,
input VAR59,
output [5:0] VAR15,
output [8:0] VAR55,
output VAR44,
output VAR5,
output VAR8,
output VAR13,
output VAR29
);
wire [7:0] VAR16;
wire VAR21;
wire [15:0] VAR34;
wire VAR2;
wire [15:0] VAR23;
wire VAR28;
VAR37 #
(
.VAR19 (VAR19), .VAR38 (VAR38), .VAR31 (VAR31), .VAR10 (VAR10)
)
VAR45
(
.VAR54 (VAR41),
.VAR53 (!VAR46),
.VAR25 (VAR56),
.VAR35 (&VAR11),
.VAR47 (VAR8),
.VAR24 (VAR59),
.VAR50 (VAR23),
.VAR43 (VAR28),
.VAR51 (VAR16),
.VAR49 (VAR21),
.VAR36 (VAR34),
.VAR9 (VAR2),
.VAR42 (VAR44),
.VAR12 (VAR5),
.VAR27 (VAR15),
.VAR17 (VAR55)
);
VAR3 #
(
.VAR7 (VAR7), .VAR19 (VAR19), .VAR38 (VAR38), .VAR31 (VAR31), .VAR10 (VAR10) )
VAR39
(
.VAR40 (VAR26),
.VAR1 (VAR20),
.VAR48 (1'd0),
.VAR13 (VAR13),
.VAR29 (VAR29),
.VAR8 (VAR8),
.VAR52 (VAR52),
.VAR18 (VAR18),
.VAR41 (VAR41),
.VAR22 (VAR16),
.VAR4 (VAR21),
.VAR57 (VAR34),
.VAR33 (VAR2),
.VAR6 (VAR23),
.VAR58 (VAR28)
);
endmodule | gpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_SRAM_TT_201020.v | 210,959 | module MODULE1 (VAR11, VAR1, VAR2, VAR5, VAR9);
output VAR11;
input VAR1, VAR2, VAR5, VAR9;
wire VAR10, VAR4, VAR8;
wire VAR7, VAR3, VAR6;
not (VAR7, VAR9);
not (VAR8, VAR5);
not (VAR4, VAR2);
and (VAR3, VAR4, VAR8);
not (VAR10, VAR1);
and (VAR6, VAR10, VAR8);
or (VAR11, VAR6, VAR3, VAR7); | bsd-3-clause |
vvk/sysrek | uart_echo/UART_memory.v | 3,562 | module MODULE1(
input VAR12,
output VAR25,
input VAR13,
output [7:0]VAR7,
output [7:0]VAR17,
output [7:0]VAR33,
output [7:0]VAR34,
output [7:0]VAR24,
output [7:0]VAR14,
output [7:0]VAR16,
output [7:0]VAR8,
output [7:0] VAR2
);
parameter VAR11 = 8;
reg [15:0]memory[VAR11-1:0];
VAR38 begin: VAR9
integer VAR1;
for (VAR1 = 0; VAR1 < VAR11; VAR1 = VAR1+1)
begin
memory[VAR1] = 16'd0;
end
end
assign VAR7 = memory[0];
assign VAR17 = memory[1];
assign VAR33 = memory[2];
assign VAR34 = memory[3];
assign VAR24 = memory[4];
assign VAR14 = memory[5];
assign VAR16 = memory[6];
assign VAR8 = memory[7];
wire [7:0]VAR3;
reg [7:0]VAR15;
reg VAR40 = 1'b0;
reg VAR36 = 1'b0;
reg VAR32 = 1'b0;
wire VAR30;
wire VAR4;
VAR23 # (
.VAR35(100000000),
.VAR31(115200)
)VAR5 (
.VAR22(VAR13),
.VAR39(VAR3),
.VAR36(VAR36),
.VAR32(VAR32),
.VAR19(VAR12),
.VAR30(VAR30)
);
VAR28 # (
.VAR35(100000000),
.VAR31(115200)
) VAR10 (
.VAR22(VAR13),
.VAR39(VAR15),
.VAR40(VAR40),
.VAR32(VAR32),
.VAR29(VAR25),
.VAR4(VAR4)
);
reg VAR18 = 1'b0;
reg VAR27 = 1'b1;
reg [7:0]VAR37 = 8'h0; reg [7:0]VAR6 = 8'h0; reg [1:0]VAR26 = 0; reg [1:0]VAR20 = 0; reg [7:0]VAR21[2:1];
always @(posedge VAR13) begin
VAR40 <= 1'b0;
if (VAR18 == 1'b0 && VAR30 == 1'b1) begin
VAR36 <= 1'b1;
end else if (VAR36 == 1'b1) begin
VAR36 <= 1'b0;
case (VAR26)
0: begin VAR37 <= VAR3;
VAR26 <= VAR26+1;
end
1: begin VAR6 <= VAR3;
VAR26 <= VAR26+1;
end
2: begin case (VAR37[7:6]) 2'b00: begin
VAR21[1] <= memory[VAR37[5:0]][7:0];
VAR21[2] <= memory[VAR37[5:0]][15:8];
VAR15 <= {2'b00, VAR37[5:0]};
VAR20 <= 2;
VAR40 <= 1'b1;
end
2'b01: memory[VAR37[5:0]] <= {VAR6, VAR3};
endcase
VAR26 <= 0;
end
endcase
end else if (VAR20 && VAR4 && !VAR27) begin
VAR15 <= VAR21[VAR20];
VAR20 <= VAR20-1;
VAR40 <= 1'b1;
end
VAR27 <= VAR4;
VAR18 <= VAR30;
end
assign VAR2 = VAR7;
endmodule | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_22.v | 16,359 | module MODULE3 (
clk,
reset,
VAR77,
VAR43,
VAR34,
VAR119,
VAR112
);
parameter VAR56 = 18;
parameter VAR86 = 22;
parameter VAR48 = 11;
localparam VAR102 = 23;
input clk;
input reset;
input VAR77;
input VAR43;
input [VAR56-1:0] VAR34; output VAR119;
output [VAR56-1:0] VAR112;
localparam VAR59 = 18; localparam VAR115 = 36; localparam VAR37 = 17;
localparam VAR39 = 22;
reg [VAR56-1:0] VAR99;
reg [VAR56-1:0] VAR26;
reg [VAR56-1:0] VAR108;
reg [VAR56-1:0] VAR18;
reg [VAR56-1:0] VAR131;
reg [VAR56-1:0] VAR73;
reg [VAR56-1:0] VAR6;
reg [VAR56-1:0] VAR127;
reg [VAR56-1:0] VAR80;
reg [VAR56-1:0] VAR9;
reg [VAR56-1:0] VAR94;
always@(posedge clk) begin
VAR99 <= 18'd88;
VAR26 <= 18'd0;
VAR108 <= -18'd97;
VAR18 <= -18'd197;
VAR131 <= -18'd294;
VAR73 <= -18'd380;
VAR6 <= -18'd447;
VAR127 <= -18'd490;
VAR80 <= -18'd504;
VAR9 <= -18'd481;
VAR94 <= -18'd420;
end
reg [VAR102-1:0] VAR90;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR90 <= 0;
end else begin
if(VAR77) begin
VAR90 <= {VAR90[VAR102-2:0], VAR43};
end else begin
VAR90 <= VAR90;
end
end
end
wire [VAR56-1:0] VAR51;
wire [VAR56-1:0] VAR134;
wire [VAR56-1:0] VAR15;
wire [VAR56-1:0] VAR2;
wire [VAR56-1:0] VAR24;
wire [VAR56-1:0] VAR120;
wire [VAR56-1:0] VAR40;
wire [VAR56-1:0] VAR11;
wire [VAR56-1:0] VAR113;
wire [VAR56-1:0] VAR128;
wire [VAR56-1:0] VAR125;
wire [VAR56-1:0] VAR133;
wire [VAR56-1:0] VAR92;
wire [VAR56-1:0] VAR13;
wire [VAR56-1:0] VAR140;
wire [VAR56-1:0] VAR38;
wire [VAR56-1:0] VAR29;
wire [VAR56-1:0] VAR95;
wire [VAR56-1:0] VAR106;
wire [VAR56-1:0] VAR78;
wire [VAR56-1:0] VAR103;
wire [VAR56-1:0] VAR42;
MODULE4 MODULE21(
.clk(clk), .VAR77(VAR77),
.VAR136(VAR34),
.VAR129(VAR51),
.VAR84(VAR134),
.VAR93(VAR15),
.VAR44(VAR2),
.VAR100(VAR24),
.VAR35(VAR120),
.VAR46(VAR40),
.VAR67(VAR11),
.VAR141(VAR113),
.VAR14(VAR128),
.VAR36(VAR125),
.VAR16(VAR133),
.VAR74(VAR92),
.VAR138(VAR13),
.VAR10(VAR140),
.VAR50(VAR38),
.VAR85(VAR29),
.VAR111(VAR95),
.VAR76(VAR106),
.VAR41(VAR78),
.VAR104(VAR103),
.VAR66(VAR42),
.reset(reset) );
wire [VAR56-1:0] VAR17;
wire [VAR56-1:0] VAR7;
wire [VAR56-1:0] VAR58;
wire [VAR56-1:0] VAR21;
wire [VAR56-1:0] VAR22;
wire [VAR56-1:0] VAR62;
wire [VAR56-1:0] VAR19;
wire [VAR56-1:0] VAR45;
wire [VAR56-1:0] VAR81;
wire [VAR56-1:0] VAR52;
wire [VAR56-1:0] VAR83;
MODULE1 VAR109(
.VAR126 (VAR51),
.VAR12 (VAR42),
.VAR107(VAR17)
);
MODULE1 VAR96(
.VAR126 (VAR134),
.VAR12 (VAR103),
.VAR107(VAR7)
);
MODULE1 VAR49(
.VAR126 (VAR15),
.VAR12 (VAR78),
.VAR107(VAR58)
);
MODULE1 VAR97(
.VAR126 (VAR2),
.VAR12 (VAR106),
.VAR107(VAR21)
);
MODULE1 VAR114(
.VAR126 (VAR24),
.VAR12 (VAR95),
.VAR107(VAR22)
);
MODULE1 VAR69(
.VAR126 (VAR120),
.VAR12 (VAR29),
.VAR107(VAR62)
);
MODULE1 VAR121(
.VAR126 (VAR40),
.VAR12 (VAR38),
.VAR107(VAR19)
);
MODULE1 VAR122(
.VAR126 (VAR11),
.VAR12 (VAR140),
.VAR107(VAR45)
);
MODULE1 VAR57(
.VAR126 (VAR113),
.VAR12 (VAR13),
.VAR107(VAR81)
);
MODULE1 VAR98(
.VAR126 (VAR128),
.VAR12 (VAR92),
.VAR107(VAR52)
);
MODULE1 VAR53(
.VAR126 (VAR125),
.VAR12 (VAR133),
.VAR107(VAR83)
);
wire [VAR56-1:0] VAR123;
wire [VAR56-1:0] VAR23;
wire [VAR56-1:0] VAR5;
wire [VAR56-1:0] VAR71;
wire [VAR56-1:0] VAR135;
wire [VAR56-1:0] VAR60;
wire [VAR56-1:0] VAR64;
wire [VAR56-1:0] VAR117;
wire [VAR56-1:0] VAR130;
wire [VAR56-1:0] VAR28;
wire [VAR56-1:0] VAR79;
MODULE2 VAR68(
.VAR126 (VAR17),
.VAR12 (VAR99),
.VAR107(VAR123)
);
MODULE2 VAR88(
.VAR126 (VAR7),
.VAR12 (VAR26),
.VAR107(VAR23)
);
MODULE2 VAR20(
.VAR126 (VAR58),
.VAR12 (VAR108),
.VAR107(VAR5)
);
MODULE2 VAR75(
.VAR126 (VAR21),
.VAR12 (VAR18),
.VAR107(VAR71)
);
MODULE2 VAR116(
.VAR126 (VAR22),
.VAR12 (VAR131),
.VAR107(VAR135)
);
MODULE2 VAR65(
.VAR126 (VAR62),
.VAR12 (VAR73),
.VAR107(VAR60)
);
MODULE2 VAR47(
.VAR126 (VAR19),
.VAR12 (VAR6),
.VAR107(VAR64)
);
MODULE2 VAR139(
.VAR126 (VAR45),
.VAR12 (VAR127),
.VAR107(VAR117)
);
MODULE2 VAR61(
.VAR126 (VAR81),
.VAR12 (VAR80),
.VAR107(VAR130)
);
MODULE2 VAR30(
.VAR126 (VAR52),
.VAR12 (VAR9),
.VAR107(VAR28)
);
MODULE2 VAR27(
.VAR126 (VAR83),
.VAR12 (VAR94),
.VAR107(VAR79)
);
wire [VAR56-1:0] VAR4;
wire [VAR56-1:0] VAR110;
wire [VAR56-1:0] VAR82;
wire [VAR56-1:0] VAR142;
wire [VAR56-1:0] VAR89;
wire [VAR56-1:0] VAR55;
MODULE1 VAR3(
.VAR126 (VAR123),
.VAR12 (VAR23),
.VAR107(VAR4)
);
MODULE1 VAR132(
.VAR126 (VAR5),
.VAR12 (VAR71),
.VAR107(VAR110)
);
MODULE1 VAR72(
.VAR126 (VAR135),
.VAR12 (VAR60),
.VAR107(VAR82)
);
MODULE1 VAR143(
.VAR126 (VAR64),
.VAR12 (VAR117),
.VAR107(VAR142)
);
MODULE1 VAR137(
.VAR126 (VAR130),
.VAR12 (VAR28),
.VAR107(VAR89)
);
MODULE5 VAR105(
.VAR126 (VAR79),
.VAR107(VAR55)
);
wire [VAR56-1:0] VAR33;
wire [VAR56-1:0] VAR63;
wire [VAR56-1:0] VAR25;
MODULE1 VAR32(
.VAR126 (VAR4),
.VAR12 (VAR110),
.VAR107(VAR33)
);
MODULE1 VAR101(
.VAR126 (VAR82),
.VAR12 (VAR142),
.VAR107(VAR63)
);
MODULE1 VAR70(
.VAR126 (VAR89),
.VAR12 (VAR55),
.VAR107(VAR25)
);
wire [VAR56-1:0] VAR124;
wire [VAR56-1:0] VAR1;
MODULE1 VAR118(
.VAR126 (VAR33),
.VAR12 (VAR63),
.VAR107(VAR124)
);
MODULE5 VAR31(
.VAR126 (VAR25),
.VAR107(VAR1)
);
wire [VAR56-1:0] VAR87;
MODULE1 VAR54(
.VAR126 (VAR124),
.VAR12 (VAR1),
.VAR107(VAR87)
);
reg [17:0] VAR112;
always @(posedge clk) begin
if(VAR77) begin
VAR112 <= VAR87;
end
end
assign VAR119 = VAR90[VAR102-1];
endmodule
module MODULE4 (
clk,
VAR77,
VAR136,
VAR129,
VAR84,
VAR93,
VAR44,
VAR100,
VAR35,
VAR46,
VAR67,
VAR141,
VAR14,
VAR36,
VAR16,
VAR74,
VAR138,
VAR10,
VAR50,
VAR85,
VAR111,
VAR76,
VAR41,
VAR104,
VAR66,
reset);
parameter VAR91 = 1;
input clk;
input VAR77;
input [VAR91-1:0] VAR136;
output [VAR91-1:0] VAR129;
output [VAR91-1:0] VAR84;
output [VAR91-1:0] VAR93;
output [VAR91-1:0] VAR44;
output [VAR91-1:0] VAR100;
output [VAR91-1:0] VAR35;
output [VAR91-1:0] VAR46;
output [VAR91-1:0] VAR67;
output [VAR91-1:0] VAR141;
output [VAR91-1:0] VAR14;
output [VAR91-1:0] VAR36;
output [VAR91-1:0] VAR16;
output [VAR91-1:0] VAR74;
output [VAR91-1:0] VAR138;
output [VAR91-1:0] VAR10;
output [VAR91-1:0] VAR50;
output [VAR91-1:0] VAR85;
output [VAR91-1:0] VAR111;
output [VAR91-1:0] VAR76;
output [VAR91-1:0] VAR41;
output [VAR91-1:0] VAR104;
output [VAR91-1:0] VAR66;
reg [VAR91-1:0] VAR129;
reg [VAR91-1:0] VAR84;
reg [VAR91-1:0] VAR93;
reg [VAR91-1:0] VAR44;
reg [VAR91-1:0] VAR100;
reg [VAR91-1:0] VAR35;
reg [VAR91-1:0] VAR46;
reg [VAR91-1:0] VAR67;
reg [VAR91-1:0] VAR141;
reg [VAR91-1:0] VAR14;
reg [VAR91-1:0] VAR36;
reg [VAR91-1:0] VAR16;
reg [VAR91-1:0] VAR74;
reg [VAR91-1:0] VAR138;
reg [VAR91-1:0] VAR10;
reg [VAR91-1:0] VAR50;
reg [VAR91-1:0] VAR85;
reg [VAR91-1:0] VAR111;
reg [VAR91-1:0] VAR76;
reg [VAR91-1:0] VAR41;
reg [VAR91-1:0] VAR104;
reg [VAR91-1:0] VAR66;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR129 <= 0;
VAR84 <= 0;
VAR93 <= 0;
VAR44 <= 0;
VAR100 <= 0;
VAR35 <= 0;
VAR46 <= 0;
VAR67 <= 0;
VAR141 <= 0;
VAR14 <= 0;
VAR36 <= 0;
VAR16 <= 0;
VAR74 <= 0;
VAR138 <= 0;
VAR10 <= 0;
VAR50 <= 0;
VAR85 <= 0;
VAR111 <= 0;
VAR76 <= 0;
VAR41 <= 0;
VAR104 <= 0;
VAR66 <= 0;
end else begin
if(VAR77) begin
VAR129 <= VAR136;
VAR84 <= VAR129;
VAR93 <= VAR84;
VAR44 <= VAR93;
VAR100 <= VAR44;
VAR35 <= VAR100;
VAR46 <= VAR35;
VAR67 <= VAR46;
VAR141 <= VAR67;
VAR14 <= VAR141;
VAR36 <= VAR14;
VAR16 <= VAR36;
VAR74 <= VAR16;
VAR138 <= VAR74;
VAR10 <= VAR138;
VAR50 <= VAR10;
VAR85 <= VAR50;
VAR111 <= VAR85;
VAR76 <= VAR111;
VAR41 <= VAR76;
VAR104 <= VAR41;
VAR66 <= VAR104;
end end
end
endmodule
module MODULE1 (
VAR126,
VAR12,
VAR107);
input clk;
input VAR77;
input [17:0] VAR126;
input [17:0] VAR12;
output [17:0] VAR107;
assign VAR107 = VAR126 + VAR12;
endmodule
module MODULE2 (
VAR126,
VAR12,
VAR107);
input clk;
input VAR77;
input [17:0] VAR126;
input [17:0] VAR12;
output [17:0] VAR107;
assign VAR107 = VAR126 * VAR12;
endmodule
module MODULE5 (
VAR126,
VAR107);
input clk;
input VAR77;
input [17:0] VAR126;
output [17:0] VAR107;
assign VAR107 = VAR126;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b.functional.v | 1,356 | module MODULE1 (
VAR7 ,
VAR2,
VAR3
);
output VAR7 ;
input VAR2;
input VAR3 ;
wire VAR1 ;
wire VAR5;
not VAR8 (VAR1 , VAR3 );
or VAR4 (VAR5, VAR1, VAR2 );
buf VAR6 (VAR7 , VAR5 );
endmodule | apache-2.0 |
skarpenko/ultiparc | rtl/src/interval_timer.v | 5,127 | module MODULE1(
clk,
VAR18,
VAR26,
VAR27,
VAR7,
VAR23,
VAR5,
VAR25,
VAR11,
VAR24
);
localparam [2:0] VAR17 = 3'b001;
localparam [2:0] VAR4 = 3'b010;
localparam [2:0] VAR14 = 3'b100;
localparam [VAR1-1:0] VAR2 = 32'h000;
localparam [VAR1-1:0] VAR19 = 32'h004;
localparam [VAR1-1:0] VAR9 = 32'h008;
input wire clk;
input wire VAR18;
output reg VAR26;
input wire [VAR1-1:0] VAR27;
input wire [2:0] VAR7;
input wire [VAR21-1:0] VAR23;
input wire [VAR10-1:0] VAR5;
output wire VAR25;
output reg [VAR21-1:0] VAR11;
output reg [1:0] VAR24;
reg [VAR21-1:0] VAR20;
reg [VAR21-1:0] VAR6;
reg enable;
reg VAR22;
reg VAR12;
reg [2:0] VAR16;
reg VAR13;
assign VAR25 = 1'b1;
always @(*)
begin
case(VAR7)
VAR11 = {(VAR21){1'b0}};
VAR24 = VAR8;
end
if(VAR27 == VAR2)
begin
VAR11 = { {(VAR21-3){1'b0}},
VAR12, VAR22, enable };
end
else if(VAR27 == VAR19)
begin
VAR11 = { {(VAR21-32){1'b0}}, VAR20 };
end
else if(VAR27 == VAR9)
begin
VAR11 = { {(VAR21-32){1'b0}}, VAR6 };
end
else
VAR11 = 32'hDEADDEAD;
VAR24 = VAR8;
end
default: begin
VAR11 = {(VAR21){1'b0}};
VAR24 = VAR3;
end
endcase
end
always @(posedge clk or negedge VAR18)
begin
if(!VAR18)
begin
enable <= 1'b0;
VAR22 <= 1'b0;
VAR20 <= {(VAR21){1'b0}};
VAR12 <= 1'b0;
VAR13 <= 1'b0;
end
else if(VAR7 == VAR15)
begin
VAR13 <= VAR27 == VAR19 ? 1'b1 : 1'b0;
if(VAR27 == VAR2)
begin
enable <= VAR23[0];
VAR22 <= VAR23[1];
VAR12 <= VAR23[2];
end
else if(VAR27 == VAR19)
begin
VAR20 <= VAR23[31:0];
end
end
else
VAR13 <= 1'b0;
end
always @(posedge clk or negedge VAR18)
begin
if(!VAR18)
begin
VAR6 <= 0;
VAR26 <= 1'b0;
VAR16 <= VAR17;
end
else if(VAR13)
begin
VAR6 <= VAR20;
VAR16 <= VAR17;
end
else
begin
case(VAR16)
VAR17: begin
VAR26 <= 1'b0;
if(enable)
VAR16 <= VAR14;
end
VAR14: begin
if(VAR6 == 0)
VAR26 <= 1'b1 & VAR22;
end
else
VAR6 <= VAR6 - 1;
VAR16 <= enable ?
(VAR6 == 0 ?
(VAR12 ? VAR4 : VAR17) : VAR14) : VAR17;
end
VAR4: begin
VAR26 <= 1'b0;
VAR6 <= VAR20 - 1;
VAR16 <= enable ? VAR14 : VAR17;
end
default: VAR16 <= VAR17;
endcase
end
end
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn_8.v | 2,164 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR2,
VAR7,
VAR5,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR4 ;
input VAR2;
input VAR7;
input VAR5;
input VAR3 ;
input VAR1 ;
VAR9 VAR8 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR6 ,
VAR4 ,
VAR2
);
output VAR6 ;
input VAR4 ;
input VAR2;
supply1 VAR7;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR1 ;
VAR9 VAR8 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ebufn/sky130_fd_sc_ms__ebufn.pp.blackbox.v | 1,287 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR4,
VAR7,
VAR2,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR6 ;
input VAR4;
input VAR7;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
merckhung/zet | cores/zet/rtl/zet_fulladd16.v | 1,028 | module MODULE1 (
input [15:0] VAR5,
input [15:0] VAR6,
input VAR1,
output VAR4,
output [15:0] VAR3,
input VAR2
);
assign {VAR4,VAR3} = {1'b0, VAR5} + {VAR2, VAR6} + VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o.pp.symbol.v | 1,388 | module MODULE1 (
input VAR1 ,
input VAR5 ,
input VAR3 ,
input VAR4 ,
input VAR8 ,
output VAR10 ,
input VAR9 ,
input VAR7,
input VAR2,
input VAR6
);
endmodule | apache-2.0 |
Marcoslz22/Tercer_Proyecto | VGAInterface.v | 4,443 | module MODULE1(
input VAR20, output VAR1, input [7:0] VAR26, output reg [7:0] VAR27, output [9:0] VAR10, output [8:0] VAR36, output reg VAR5, output reg VAR22, input VAR3
);
wire [9:0] VAR37; wire [9:0] VAR21; wire VAR18;
VAR30 begin VAR5 = 0;
VAR22 = 0;
VAR27 = 8'b0;
end
parameter VAR23 = 10'd96;
parameter VAR17 = 10'd144;
parameter VAR9 = 10'd784;
parameter VAR16 = 10'd800;
parameter VAR7 = 10'd2; parameter VAR28 = 10'd31; parameter VAR12 = 10'd511; parameter VAR2 = 10'd521;
VAR15 # (
.VAR14(VAR16-1), .VAR13(10) )
VAR35(
.VAR20(VAR20), .VAR25(VAR3), .VAR34(VAR18), .VAR4(VAR21) );
VAR15 # (
.VAR14(VAR2-1), .VAR13(10) )
VAR33(
.VAR20(VAR20), .VAR25(VAR18), .VAR34(VAR1), .VAR4(VAR37) );
always @(posedge VAR20) begin if ((VAR21 < VAR23-1) || (VAR21 == VAR16-1)) VAR5 <= 1'b0;
end
else
VAR5 <= 1'b1;
end
always @(posedge VAR20) begin if (VAR18)begin
if ((VAR37 < VAR7-1) || (VAR37 == VAR2-1))
VAR22 <= 1'b0;
end
else
VAR22 <= 1'b1;
end
end
always @(posedge VAR20) begin
if (VAR3) begin
if ( (VAR21 > VAR17-2) && (VAR21 <= VAR9-2)
&& (VAR37 > VAR28-1)
&& (VAR37 <= VAR12-1) )
VAR27 <= VAR26;
end
else
VAR27 <= 8'b0;
end
end
VAR19 # (
.VAR6(10), .VAR32 (VAR17-1), .VAR31 (VAR9-1) )
VAR29(
.VAR20(VAR20), .VAR11(VAR21), .VAR25(VAR3), .VAR24(VAR10) );
VAR19 # (
.VAR6(9),
.VAR32 (VAR28-1),
.VAR31 (VAR12-1)
)
VAR8(
.VAR20(VAR20),
.VAR11(VAR37),
.VAR25(VAR18), .VAR24(VAR36)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b.behavioral.pp.v | 1,995 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR12 ,
VAR4 ,
VAR10,
VAR3,
VAR5 ,
VAR7
);
output VAR6 ;
input VAR1 ;
input VAR12 ;
input VAR4 ;
input VAR10;
input VAR3;
input VAR5 ;
input VAR7 ;
wire VAR9 ;
wire VAR13 ;
wire VAR8;
nor VAR16 (VAR9 , VAR1, VAR12 );
and VAR11 (VAR13 , VAR4, VAR9 );
VAR15 VAR14 (VAR8, VAR13, VAR10, VAR3);
buf VAR2 (VAR6 , VAR8 );
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_016.v | 1,533 | module MODULE2 (
VAR4,
VAR2
);
input [31:0] VAR4;
output [31:0]
VAR2;
wire [31:0]
VAR7,
VAR3,
VAR12,
VAR8,
VAR13,
VAR1,
VAR11,
VAR10,
VAR14;
assign VAR7 = VAR4;
assign VAR10 = VAR11 << 2;
assign VAR3 = VAR7 << 8;
assign VAR12 = VAR7 + VAR3;
assign VAR11 = VAR1 - VAR12;
assign VAR1 = VAR7 << 12;
assign VAR14 = VAR10 - VAR13;
assign VAR8 = VAR12 << 5;
assign VAR13 = VAR12 + VAR8;
assign VAR2 = VAR14;
endmodule
module MODULE1(
VAR4,
VAR2,
clk
);
input [31:0] VAR4;
output [31:0] VAR2;
reg [31:0] VAR2;
input clk;
reg [31:0] VAR6;
wire [30:0] VAR9;
always @(posedge clk) begin
VAR6 <= VAR4;
VAR2 <= VAR9;
end
MODULE2 MODULE1(
.VAR4(VAR6),
.VAR2(VAR9)
);
endmodule | mit |
rkrajnc/minimig-mist | rtl/or1200/or1200_pm.v | 6,711 | module MODULE1(
clk, rst, VAR11, VAR18, VAR23, VAR27, VAR8,
VAR15, VAR19, VAR28, VAR12, VAR2,
VAR10, VAR5, VAR13, VAR24, VAR26
);
input clk; input rst; input VAR11; input VAR18; input [31:0] VAR23; input [31:0] VAR27; output [31:0] VAR8;
input VAR19; output [3:0] VAR15; output VAR28; output VAR12; output VAR2; output VAR10; output VAR5; output VAR13; output VAR24; output VAR26;
reg [3:0] VAR7; reg VAR25; reg VAR4; reg VAR20;
wire VAR6;
assign VAR6 = (VAR23[VAR22] == VAR21) ? 1'b1 : 1'b0;
assign VAR6 = ((VAR23[VAR22] == VAR21) &&
(VAR23[VAR9] == VAR1)) ? 1'b1 : 1'b0;
always @(posedge clk or posedge rst)
if (rst)
{VAR20, VAR4, VAR25, VAR7} <= 7'b0;
else if (VAR6 && VAR18) begin
VAR7 <= VAR27[VAR3];
VAR25 <= VAR27[VAR17];
VAR4 <= VAR27[VAR14];
VAR20 <= VAR27[VAR16];
end
else if (VAR11) begin
VAR25 <= 1'b0;
VAR4 <= 1'b0;
end
assign VAR8[VAR3] = VAR7;
assign VAR8[VAR17] = VAR25;
assign VAR8[VAR14] = VAR4;
assign VAR8[VAR16] = VAR20;
assign VAR8[VAR29] = 25'b0;
assign VAR15 = VAR7;
assign VAR13 = (VAR25 | VAR4) & ~VAR11;
assign VAR28 = VAR13;
assign VAR12 = VAR13;
assign VAR2 = VAR13;
assign VAR10 = VAR13;
assign VAR5 = VAR4 & ~VAR11;
assign VAR24 = VAR11;
assign VAR26 = VAR13 | VAR19;
assign VAR15 = 4'b0;
assign VAR13 = 1'b0;
assign VAR28 = 1'b0;
assign VAR12 = 1'b0;
assign VAR2 = 1'b0;
assign VAR10 = 1'b0;
assign VAR5 = 1'b0;
assign VAR24 = 1'b1;
assign VAR26 = 1'b0;
assign VAR8[VAR3] = 4'b0;
assign VAR8[VAR17] = 1'b0;
assign VAR8[VAR14] = 1'b0;
assign VAR8[VAR16] = 1'b0;
assign VAR8[VAR29] = 25'b0;
endmodule | gpl-3.0 |
esonghori/TinyGarble | circuit_synthesis/lib/stdcells_S.v | 23,550 | module \not ;
endmodule
module MODULE45 ;
endmodule
module \VAR67 ;
endmodule
module MODULE23 (VAR77, VAR86);
parameter VAR30 = 0;
parameter VAR97 = 1;
parameter VAR1 = 1;
input [VAR97-1:0] VAR77;
output [VAR1-1:0] VAR86;
\VAR95 #(
.VAR30(VAR30),
.VAR36(VAR30),
.VAR97(1),
.VAR10(VAR97),
.VAR1(VAR1)
) VAR95 (
.VAR77(1'b0),
.VAR35(VAR77),
.VAR86(VAR86)
);
endmodule
module \and ;
endmodule
module \or ;
endmodule
module \xor ;
endmodule
module \xnor ;
endmodule
module \VAR13 ;
endmodule
module \VAR80 ;
endmodule
module \VAR34 ;
endmodule
module \VAR42 ;
endmodule
module \VAR39 ;
endmodule
module \VAR25 (VAR65, VAR77, VAR86);
parameter VAR51 = 1;
parameter VAR115 = 0;
input VAR65;
input [VAR51-1:0] VAR77;
output [VAR51-1:0] VAR86;
genvar VAR54;
generate
for (VAR54 = 0; VAR54 < VAR51; VAR54 = VAR54 + 1) begin:VAR108
if (VAR54+VAR115 < 0) begin
assign VAR86[VAR54] = 0;
end else
if (VAR54+VAR115 < VAR51) begin
assign VAR86[VAR54] = VAR77[VAR54+VAR115];
end else begin
assign VAR86[VAR54] = VAR65;
end
end
endgenerate
endmodule
module \VAR38 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
parameter VAR51 = VAR1;
localparam VAR5 = VAR93(VAR51) + 2 < VAR10 ? VAR93(VAR51) + 2 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
genvar VAR54;
generate
wire [VAR51*(VAR5+1)-1:0] VAR92;
\VAR67 #(
.VAR30(VAR30),
.VAR97(VAR97),
.VAR1(VAR51)
) VAR82 (
.VAR77(VAR77),
.VAR86(VAR92[VAR51-1:0])
);
assign VAR86 = VAR92[VAR51*(VAR5+1)-1 : VAR51*VAR5];
for (VAR54 = 0; VAR54 < VAR5; VAR54 = VAR54 + 1) begin:VAR108
wire [VAR51-1:0] VAR3, VAR56, VAR2;
assign VAR3 = VAR92[VAR51*VAR54 + VAR51-1 : VAR51*VAR54];
assign VAR92[VAR51*(VAR54+1) + VAR51-1 : VAR51*(VAR54+1)] = VAR2;
wire VAR46;
if (VAR54 == VAR5-1 && VAR5 < VAR10)
assign VAR46 = |VAR35[VAR10-1:VAR5-1];
end
else
assign VAR46 = VAR35[VAR54];
\VAR25 #(
.VAR51(VAR51),
.VAR115(0 - (2 ** (VAR54 > 30 ? 30 : VAR54)))
) VAR103 (
.VAR65(0),
.VAR77(VAR3),
.VAR86(VAR56)
);
MODULE16 #(
.VAR51(VAR51)
) MODULE16 (
.VAR77(VAR3),
.VAR35(VAR56),
.VAR86(VAR2),
.VAR26(VAR46)
);
end
endgenerate
endmodule
module \VAR90 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 = VAR97 > VAR1 ? VAR97 : VAR1;
localparam VAR5 = VAR93(VAR51) + 2 < VAR10 ? VAR93(VAR51) + 2 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
genvar VAR54;
generate
wire [VAR51*(VAR5+1)-1:0] VAR92;
\VAR67 #(
.VAR30(VAR30),
.VAR97(VAR97),
.VAR1(VAR51)
) VAR82 (
.VAR77(VAR77),
.VAR86(VAR92[VAR51-1:0])
);
assign VAR86 = VAR92[VAR51*(VAR5+1)-1 : VAR51*VAR5];
for (VAR54 = 0; VAR54 < VAR5; VAR54 = VAR54 + 1) begin:VAR108
wire [VAR51-1:0] VAR3, VAR56, VAR2;
assign VAR3 = VAR92[VAR51*VAR54 + VAR51-1 : VAR51*VAR54];
assign VAR92[VAR51*(VAR54+1) + VAR51-1 : VAR51*(VAR54+1)] = VAR2;
wire VAR46;
if (VAR54 == VAR5-1 && VAR5 < VAR10)
assign VAR46 = |VAR35[VAR10-1:VAR5-1];
end
else
assign VAR46 = VAR35[VAR54];
\VAR25 #(
.VAR51(VAR51),
.VAR115(2 ** (VAR54 > 30 ? 30 : VAR54))
) VAR103 (
.VAR65(0),
.VAR77(VAR3),
.VAR86(VAR56)
);
MODULE16 #(
.VAR51(VAR51)
) MODULE16 (
.VAR77(VAR3),
.VAR35(VAR56),
.VAR86(VAR2),
.VAR26(VAR46)
);
end
endgenerate
endmodule
module \VAR112 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 = VAR1;
localparam VAR5 = VAR93(VAR51) + 2 < VAR10 ? VAR93(VAR51) + 2 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
genvar VAR54;
generate
wire [VAR51*(VAR5+1)-1:0] VAR92;
\VAR67 #(
.VAR30(VAR30),
.VAR97(VAR97),
.VAR1(VAR51)
) VAR82 (
.VAR77(VAR77),
.VAR86(VAR92[VAR51-1:0])
);
assign VAR86 = VAR92[VAR51*(VAR5+1)-1 : VAR51*VAR5];
for (VAR54 = 0; VAR54 < VAR5; VAR54 = VAR54 + 1) begin:VAR108
wire [VAR51-1:0] VAR3, VAR56, VAR2;
assign VAR3 = VAR92[VAR51*VAR54 + VAR51-1 : VAR51*VAR54];
assign VAR92[VAR51*(VAR54+1) + VAR51-1 : VAR51*(VAR54+1)] = VAR2;
wire VAR46;
if (VAR54 == VAR5-1 && VAR5 < VAR10)
assign VAR46 = |VAR35[VAR10-1:VAR5-1];
end
else
assign VAR46 = VAR35[VAR54];
\VAR25 #(
.VAR51(VAR51),
.VAR115(0 - (2 ** (VAR54 > 30 ? 30 : VAR54)))
) VAR103 (
.VAR65(0),
.VAR77(VAR3),
.VAR86(VAR56)
);
MODULE16 #(
.VAR51(VAR51)
) MODULE16 (
.VAR77(VAR3),
.VAR35(VAR56),
.VAR86(VAR2),
.VAR26(VAR46)
);
end
endgenerate
endmodule
module \VAR22 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 = VAR97 > VAR1 ? VAR97 : VAR1;
localparam VAR5 = VAR93(VAR51) + 2 < VAR10 ? VAR93(VAR51) + 2 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
genvar VAR54;
generate
wire [VAR51*(VAR5+1)-1:0] VAR92;
\VAR67 #(
.VAR30(VAR30),
.VAR97(VAR97),
.VAR1(VAR51)
) VAR82 (
.VAR77(VAR77),
.VAR86(VAR92[VAR51-1:0])
);
for (VAR54 = 0; VAR54 < VAR1; VAR54 = VAR54 + 1) begin:VAR86
if (VAR54 < VAR51) begin
assign VAR86[VAR54] = VAR92[VAR51*VAR5 + VAR54];
end else
if (VAR30) begin
assign VAR86[VAR54] = VAR92[VAR51*VAR5 + VAR51-1];
end else begin
assign VAR86[VAR54] = 0;
end
end
for (VAR54 = 0; VAR54 < VAR5; VAR54 = VAR54 + 1) begin:VAR108
wire [VAR51-1:0] VAR3, VAR56, VAR2;
assign VAR3 = VAR92[VAR51*VAR54 + VAR51-1 : VAR51*VAR54];
assign VAR92[VAR51*(VAR54+1) + VAR51-1 : VAR51*(VAR54+1)] = VAR2;
wire VAR46;
if (VAR54 == VAR5-1 && VAR5 < VAR10)
assign VAR46 = |VAR35[VAR10-1:VAR5-1];
end
else
assign VAR46 = VAR35[VAR54];
\VAR25 #(
.VAR51(VAR51),
.VAR115(2 ** (VAR54 > 30 ? 30 : VAR54))
) VAR103 (
.VAR65(VAR30 && VAR77[VAR97-1]),
.VAR77(VAR3),
.VAR86(VAR56)
);
MODULE16 #(
.VAR51(VAR51)
) MODULE16 (
.VAR77(VAR3),
.VAR35(VAR56),
.VAR86(VAR2),
.VAR26(VAR46)
);
end
endgenerate
endmodule
module \VAR107 (VAR77, VAR35, VAR84, VAR65, VAR86);
input VAR77, VAR35, VAR84;
output VAR65, VAR86;
wire VAR24, VAR6, VAR78;
\VAR8 VAR50 ( .VAR77(VAR77), .VAR35(VAR84), .VAR86(VAR24) );
\VAR8 VAR27 ( .VAR77(VAR35), .VAR35(VAR84), .VAR86(VAR6) );
\VAR66 VAR100 ( .VAR77(VAR24), .VAR35(VAR6), .VAR86(VAR78) );
\VAR8 VAR4 ( .VAR77(VAR24), .VAR35(VAR35), .VAR86(VAR86) );
\VAR8 VAR111 ( .VAR77(VAR78), .VAR35(VAR84), .VAR86(VAR65) );
endmodule
module MODULE30 (VAR77, VAR35, VAR23, VAR86, VAR85, VAR48);
parameter VAR51 = 1;
input [VAR51-1:0] VAR77, VAR35;
input VAR23;
output [VAR51-1:0] VAR86;
output VAR85, VAR48;
wire [VAR51:0] VAR55;
assign VAR55[0] = VAR23;
assign VAR85 = VAR55[VAR51];
assign VAR48 = VAR55[VAR51-1];
genvar VAR54;
generate
for (VAR54 = 0; VAR54 < VAR51; VAR54 = VAR54 + 1) begin:VAR108
\VAR107 VAR118 (
.VAR77(VAR77[VAR54]),
.VAR35(VAR35[VAR54]),
.VAR84(VAR55[VAR54]),
.VAR65(VAR55[VAR54+1]),
.VAR86(VAR86[VAR54])
);
end
endgenerate
endmodule
module \VAR96 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 = VAR97 > VAR10 ? VAR97 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
wire VAR55, VAR81;
wire [VAR51-1:0] VAR53, VAR63, VAR21;
MODULE45 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR51)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
MODULE45 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR51)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
MODULE30 #(
.VAR51(VAR51)
) MODULE30 (
.VAR77(VAR53),
.VAR35(~VAR63),
.VAR23(1'b1),
.VAR86(VAR21),
.VAR85(VAR55),
.VAR48(VAR81)
);
wire VAR116, VAR69, VAR89, VAR58;
assign VAR116 = !VAR55;
assign VAR69 = VAR55 ^ VAR81;
assign VAR89 = ~|VAR21;
assign VAR58 = VAR21[VAR51-1];
generate
if (VAR30 && VAR36) begin
assign VAR86 = VAR69 != VAR58;
end else begin
assign VAR86 = VAR116;
end
endgenerate
endmodule
module \VAR33 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 = VAR97 > VAR10 ? VAR97 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
wire VAR55, VAR81;
wire [VAR51-1:0] VAR53, VAR63, VAR21;
MODULE45 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR51)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
MODULE45 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR51)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
MODULE30 #(
.VAR51(VAR51)
) MODULE30 (
.VAR77(VAR53),
.VAR35(~VAR63),
.VAR23(1'b1),
.VAR86(VAR21),
.VAR85(VAR55),
.VAR48(VAR81)
);
wire VAR116, VAR69, VAR89, VAR58;
assign VAR116 = !VAR55;
assign VAR69 = VAR55 ^ VAR81;
assign VAR89 = ~|VAR21;
assign VAR58 = VAR21[VAR51-1];
generate
if (VAR30 && VAR36) begin
assign VAR86 = VAR89 || (VAR69 != VAR58);
end else begin
assign VAR86 = VAR89 || VAR116;
end
endgenerate
endmodule
module \VAR47 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 = VAR97 > VAR10 ? VAR97 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
wire VAR55, VAR81;
wire [VAR51-1:0] VAR53, VAR63;
\VAR67 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR51)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
\VAR67 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR51)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
assign VAR86 = ~|(VAR53 ^ VAR63);
endmodule
module \VAR20 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 = VAR97 > VAR10 ? VAR97 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
wire VAR55, VAR81;
wire [VAR51-1:0] VAR53, VAR63;
\VAR67 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR51)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
\VAR67 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR51)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
assign VAR86 = |(VAR53 ^ VAR63);
endmodule
module \VAR74 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 = VAR97 > VAR10 ? VAR97 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
wire VAR55, VAR81;
wire [VAR51-1:0] VAR53, VAR63;
MODULE45 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR51)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
MODULE45 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR51)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
assign VAR86 = ~|(VAR53 ^ VAR63);
endmodule
module \VAR61 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 = VAR97 > VAR10 ? VAR97 : VAR10;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
wire VAR55, VAR81;
wire [VAR51-1:0] VAR53, VAR63;
MODULE45 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR51)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
MODULE45 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR51)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
assign VAR86 = |(VAR53 ^ VAR63);
endmodule
module \VAR7 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
\VAR33 #(
.VAR30(VAR36),
.VAR36(VAR30),
.VAR97(VAR10),
.VAR10(VAR97),
.VAR1(VAR1)
) VAR59 (
.VAR77(VAR35),
.VAR35(VAR77),
.VAR86(VAR86)
);
endmodule
module \VAR110 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
\VAR96 #(
.VAR30(VAR36),
.VAR36(VAR30),
.VAR97(VAR10),
.VAR10(VAR97),
.VAR1(VAR1)
) VAR9 (
.VAR77(VAR35),
.VAR35(VAR77),
.VAR86(VAR86)
);
endmodule
module \VAR37 (VAR77, VAR35, VAR84, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR87 = 1;
parameter VAR1 = 1;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
input [VAR87-1:0] VAR84;
output [VAR1-1:0] VAR86;
wire [VAR1-1:0] VAR53, VAR63;
MODULE45 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR1)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
MODULE45 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR1)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
MODULE30 #(
.VAR51(VAR1)
) MODULE30 (
.VAR77(VAR53),
.VAR35(VAR63),
.VAR23(VAR84),
.VAR86(VAR86)
);
endmodule
module \VAR95 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
wire [VAR1-1:0] VAR53, VAR63;
MODULE45 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR1)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
MODULE45 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR1)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
MODULE30 #(
.VAR51(VAR1)
) MODULE30 (
.VAR77(VAR53),
.VAR35(~VAR63),
.VAR23(1'b1),
.VAR86(VAR86)
);
endmodule
module \VAR14 (VAR77, VAR35, VAR86);
parameter VAR51 = 8;
input [VAR51-1:0] VAR77, VAR35;
output [VAR51-1:0] VAR86;
wire [VAR51*VAR51-1:0] VAR102;
genvar VAR54;
assign VAR102[VAR51-1 : 0] = VAR77[0] ? VAR35 : 0;
generate for (VAR54 = 1; VAR54 < VAR51; VAR54 = VAR54+1) begin:VAR45
assign VAR102[VAR51*(VAR54+1)-1 : VAR51*VAR54] = (VAR77[VAR54] ? VAR35 << VAR54 : 0) + VAR102[VAR51*VAR54-1 : VAR51*(VAR54-1)];
end endgenerate
assign VAR86 = VAR102[VAR51*VAR51-1 : VAR51*(VAR51-1)];
endmodule
module \VAR117 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
wire [VAR1-1:0] VAR53, VAR63;
MODULE45 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR1)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
MODULE45 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR1)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
\VAR14 #(
.VAR51(VAR1)
) VAR14 (
.VAR77(VAR53),
.VAR35(VAR63),
.VAR86(VAR86)
);
endmodule
module \VAR106 (VAR77, VAR35, VAR86, VAR16);
parameter VAR51 = 1;
input [VAR51-1:0] VAR77, VAR35;
output [VAR51-1:0] VAR86, VAR16;
wire [VAR51*VAR51-1:0] VAR60;
assign VAR16 = VAR60[VAR51*VAR51-1:VAR51*(VAR51-1)];
genvar VAR54;
generate begin
for (VAR54 = 0; VAR54 < VAR51; VAR54=VAR54+1) begin:VAR31
wire [VAR51-1:0] VAR57;
if (VAR54 == 0) begin:VAR52
assign VAR57 = VAR77;
end else begin:VAR52
assign VAR57 = VAR60[VAR54*VAR51-1:(VAR54-1)*VAR51];
end
assign VAR86[VAR51-(VAR54+1)] = VAR57 >= {VAR35, {VAR51-(VAR54+1){1'b0}}};
assign VAR60[(VAR54+1)*VAR51-1:VAR54*VAR51] = VAR86[VAR51-(VAR54+1)] ? VAR57 - {VAR35, {VAR51-(VAR54+1){1'b0}}} : VAR57;
end
end endgenerate
endmodule
module \VAR75 (VAR77, VAR35, VAR86, VAR16);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
localparam VAR51 =
VAR97 >= VAR10 && VAR97 >= VAR1 ? VAR97 :
VAR10 >= VAR97 && VAR10 >= VAR1 ? VAR10 : VAR1;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86, VAR16;
wire [VAR51-1:0] VAR53, VAR63;
MODULE45 #(.VAR30(VAR30), .VAR97(VAR97), .VAR1(VAR51)) VAR94 (.VAR77(VAR77), .VAR86(VAR53));
MODULE45 #(.VAR30(VAR36), .VAR97(VAR10), .VAR1(VAR51)) VAR64 (.VAR77(VAR35), .VAR86(VAR63));
wire [VAR51-1:0] VAR109, VAR41, VAR105, VAR101;
assign VAR109 = VAR30 && VAR53[VAR51-1] ? -VAR53 : VAR53;
assign VAR41 = VAR36 && VAR63[VAR51-1] ? -VAR63 : VAR63;
\VAR106 #(
.VAR51(VAR51)
) VAR106 (
.VAR77(VAR109),
.VAR35(VAR41),
.VAR86(VAR105),
.VAR16(VAR101)
);
assign VAR86 = VAR30 && VAR36 && (VAR53[VAR51-1] != VAR63[VAR51-1]) ? -VAR105 : VAR105;
assign VAR16 = VAR30 && VAR36 && VAR53[VAR51-1] ? -VAR101 : VAR101;
endmodule
module \VAR15 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
\VAR75 #(
.VAR30(VAR30),
.VAR36(VAR36),
.VAR97(VAR97),
.VAR10(VAR10),
.VAR1(VAR1)
) VAR75 (
.VAR77(VAR77),
.VAR35(VAR35),
.VAR86(VAR86)
);
endmodule
module \VAR71 (VAR77, VAR35, VAR86);
parameter VAR30 = 0;
parameter VAR36 = 0;
parameter VAR97 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
input [VAR97-1:0] VAR77;
input [VAR10-1:0] VAR35;
output [VAR1-1:0] VAR86;
\VAR75 #(
.VAR30(VAR30),
.VAR36(VAR36),
.VAR97(VAR97),
.VAR10(VAR10),
.VAR1(VAR1)
) VAR75 (
.VAR77(VAR77),
.VAR35(VAR35),
.VAR16(VAR86)
);
endmodule
module \VAR83 ;
endmodule
module \VAR18 ;
endmodule
module \VAR99 ;
endmodule
module \VAR11 ;
endmodule
module \VAR88 ;
endmodule
module MODULE16 ;
endmodule
module \VAR32 (VAR77, VAR35, VAR26, VAR86);
parameter VAR51 = 1;
parameter VAR49 = 1;
input [VAR51-1:0] VAR77;
input [VAR51*VAR49-1:0] VAR35;
input [VAR49-1:0] VAR26;
output [VAR51-1:0] VAR86;
wire [VAR51-1:0] VAR76;
genvar VAR54, VAR72;
generate
wire [VAR51*VAR49-1:0] VAR104;
for (VAR54 = 0; VAR54 < VAR49; VAR54 = VAR54 + 1) begin:VAR73
assign VAR104[VAR51*(VAR54+1)-1:VAR51*VAR54] = VAR35[VAR51*(VAR54+1)-1:VAR51*VAR54] & {VAR51{VAR26[VAR54]}};
end:VAR73
for (VAR54 = 0; VAR54 < VAR51; VAR54 = VAR54 + 1) begin:VAR113
wire [VAR49-1:0] VAR62;
for (VAR72 = 0; VAR72 < VAR49; VAR72 = VAR72 + 1) begin:VAR43
assign VAR62[VAR72] = VAR104[VAR51*VAR72+VAR54];
end:VAR43
assign VAR76[VAR54] = |VAR62;
end:VAR113
endgenerate
assign VAR86 = |VAR26 ? VAR76 : VAR77;
endmodule
module \VAR98 (VAR77, VAR35, VAR26, VAR86);
parameter VAR51 = 1;
parameter VAR49 = 1;
input [VAR51-1:0] VAR77;
input [VAR51*VAR49-1:0] VAR35;
input [VAR49-1:0] VAR26;
output [VAR51-1:0] VAR86;
wire [VAR49-1:0] VAR12;
wire [VAR49-1:0] VAR91;
genvar VAR54;
generate
for (VAR54 = 0; VAR54 < VAR49; VAR54 = VAR54 + 1) begin:VAR44
wire VAR114;
if (VAR54 > 0) begin:VAR29
assign VAR114 = VAR12[VAR54-1];
end
end:VAR29 else begin:VAR68
assign VAR114 = 0;
end:VAR68
assign VAR12[VAR54] = VAR114 | VAR26[VAR54];
assign VAR91[VAR54] = VAR114 & VAR26[VAR54];
end:VAR44
endgenerate
\VAR32 #(
.VAR51(VAR51),
.VAR49(VAR49)
) VAR79 (
.VAR77(VAR77),
.VAR35(VAR35),
.VAR26(VAR26 & {VAR49{~|VAR91}}),
.VAR86(VAR86)
);
endmodule
module \VAR40 ;
endmodule
module \VAR28 ;
endmodule
module \VAR19 ;
endmodule
module \VAR17 ;
endmodule
module \VAR70 ;
endmodule | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/earb/hdl/earb.v | 4,459 | module MODULE1 (
VAR11, VAR17, VAR8, VAR2, VAR21,
VAR14, VAR7, VAR20, VAR22,
VAR6,
VAR24, reset, VAR10, VAR15, VAR4, VAR16,
VAR3, VAR18, VAR5, VAR19, VAR23
);
input VAR24;
input reset;
input [102:0] VAR10;
output VAR11;
input VAR15;
input [102:0] VAR4;
output VAR17;
input VAR16;
input [102:0] VAR3;
output VAR8;
input VAR18;
output VAR2;
output VAR21;
output [1:0] VAR14;
output [3:0] VAR7;
output [31:0] VAR20;
output [31:0] VAR22;
output [31:0] VAR6;
input VAR5;
input VAR19;
input VAR23;
wire VAR2;
wire VAR21;
wire [1:0] VAR14;
wire [3:0] VAR7;
wire [31:0] VAR20;
wire [31:0] VAR22;
wire [31:0] VAR6;
reg ready;
reg [102:0] VAR9;
wire VAR13 = ~VAR18 & ~VAR19;
wire VAR12 = ~VAR16 & ~VAR5 & ~VAR13;
wire VAR1 = ~VAR15 & ~VAR19 & ~VAR13 & ~VAR12;
wire VAR8 = VAR13 & (~ready | VAR23);
wire VAR17 = VAR12 & (~ready | VAR23);
wire VAR11 = VAR1 & (~ready | VAR23);
always @ (posedge VAR24) begin
if( reset ) begin
ready <= 1'b0;
VAR9 <= 'd0;
end else begin
if( VAR8 ) begin
ready <= 1'b1;
VAR9 <= VAR3;
end else if( VAR17 ) begin
ready <= 1'b1;
VAR9 <= VAR4;
end else if( VAR11 ) begin
ready <= 1'b1;
VAR9 <= VAR10;
end else if( VAR23 ) begin
ready <= 1'b0;
end
end end
assign VAR2 = ready;
assign VAR21 = VAR9[102];
assign VAR14 = VAR9[101:100];
assign VAR7 = VAR9[99:96];
assign VAR20 = VAR9[95:64];
assign VAR22 = VAR9[63:32];
assign VAR6 = VAR9[31:0];
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_phy_write.v | 16,797 | module MODULE1 #
(
parameter VAR28 = 72,
parameter VAR53 = 1,
parameter VAR13 = 0,
parameter VAR50 = 5,
parameter VAR6 = 0,
parameter VAR51 = 1,
parameter VAR61 = 1,
parameter VAR31 = 1
)
(
input VAR18,
input VAR56,
input VAR9,
input [(2*VAR28)-1:0] VAR23,
input [(2*VAR28/8)-1:0] VAR41,
input VAR44,
input VAR58,
input VAR29,
output reg VAR30,
output reg [1:0] VAR42,
output reg VAR19 ,
output reg VAR69 ,
output VAR55,
output reg [VAR53-1:0] VAR25 ,
output [VAR28-1:0] VAR12,
output [VAR28-1:0] VAR11,
output [(VAR28/8)-1:0] VAR22,
output [(VAR28/8)-1:0] VAR71
);
localparam VAR43 = VAR28/8;
localparam VAR68 = 0;
localparam VAR39 = 1;
localparam VAR17 = 2;
localparam VAR46 = (VAR31 == VAR17) ?
(VAR13 + (VAR50) + VAR61 ) :
(VAR31 == VAR39) ?
(VAR13 + (VAR50-1) + VAR61 ) :
(1 + VAR61 );
localparam VAR8 = VAR46 - VAR61;
wire VAR62;
reg VAR59;
wire [1:0] VAR10;
reg [1:0] VAR14;
reg [1:0] VAR5;
wire VAR2;
reg VAR45;
reg VAR37;
wire VAR33;
reg VAR52;
reg VAR4;
reg VAR21;
reg VAR7;
reg [(VAR28-1):0] VAR1;
reg [(VAR28-1):0] VAR27;
reg [3:0] VAR24;
wire VAR54;
reg VAR60 ;
reg [10:0] VAR36 ;
reg [(2*VAR28)-1:0] VAR47;
reg [(2*VAR28/8)-1:0] VAR16;
wire [(2*VAR28/8)-1:0] VAR20;
reg [(2*VAR28/8)-1:0] VAR65;
wire VAR26;
reg VAR64;
reg VAR35;
reg VAR38;
reg VAR34;
always @(posedge VAR56)
VAR60 <= VAR9;
assign VAR2 = VAR36[VAR46-1] | VAR36[VAR46-2];
generate
if ((VAR31 != VAR68) && (VAR51 > 0))begin: VAR57
if(VAR8 > 3)
assign VAR54 =
VAR36[VAR8-2] |
VAR36[VAR8-3] |
VAR36[VAR8-4] ;
end
else if ( VAR8 == 3)
assign VAR54 =
VAR36[VAR8-1] |
VAR36[VAR8-2] |
VAR36[VAR8-3] ;
else
assign VAR54 =
VAR36[VAR8] |
VAR36[VAR8-1] |
VAR36[VAR8-2] ;
end else
assign VAR54 = 1'b0;
endgenerate
assign VAR10[0] = VAR36[VAR46-1] | VAR36[VAR46];
assign VAR10[1] = VAR36[VAR46-1] | VAR36[VAR46-2];
assign VAR33 = ~VAR36[VAR46-2];
assign VAR62 = VAR36[VAR46] | VAR36[VAR46-1]
| VAR36[VAR46-2];
generate
if (VAR31 != VAR68) begin: VAR15
if (VAR46 > 2)
assign VAR26 = VAR36[VAR46-3];
end
else
assign VAR26 = VAR36[VAR46-2];
end else begin: VAR63
assign VAR26 = VAR36[VAR46-2];
end
endgenerate
always @ begin
VAR38 = VAR35
& VAR29;
VAR64 = VAR35;
end
end endgenerate
always @(negedge VAR56)begin
VAR59 <= VAR62;
VAR30 <= VAR59;
end
genvar VAR67;
generate
if(VAR6) begin
for (VAR67 = 0; VAR67 < (2*VAR28)/72;
VAR67 = VAR67+1) begin: VAR48
assign VAR20[((VAR67*9)+9)-1:(VAR67*9)] =
{&VAR41[(VAR67*8)+(7+VAR67):VAR67*9],
VAR41[(VAR67*8)+(7+VAR67):VAR67*9]};
end
end
endgenerate
generate
if (VAR6) begin:VAR32
always @(posedge VAR56)begin
if(VAR29)
VAR16 <= VAR20;
end
else
VAR16 <= {(2*VAR28/8){1'b0}};
end
end else begin
always@(posedge VAR56) begin
if (VAR29)
VAR16 <= VAR41;
end
else
VAR16 <= {(2*VAR28/8){1'b0}};
end
end
endgenerate
always @(posedge VAR56) begin
if(VAR29)
VAR47 <= VAR23;
end
else
VAR47 <={VAR1,VAR27};
end
generate
if (VAR6) begin: VAR3
always @(posedge VAR56) begin
VAR65 <= VAR16;
if(VAR28 > 72)
VAR21
<= (
(~VAR65[35] && (|VAR65[34:27])) ||
(~VAR65[26] && (|VAR65[25:18])) ||
(~VAR65[17] && (|VAR65[16:9])) ||
(~VAR65[8] && (|VAR65[7:0]))) && VAR29;
end
else
VAR21
<= ((~VAR65[17] && (|VAR65[16:9])) ||
(~VAR65[8] && (|VAR65[7:0]))) && VAR29;
VAR7 <= VAR21 ;
if (VAR21 && ~VAR7)
end
end
endgenerate
always @(posedge VAR56) begin
if (VAR60) begin
VAR24 <= 4'd0;
VAR27 <= {64{1'VAR40}};
VAR1 <= {64{1'VAR40}};
end else begin
VAR24 <= VAR24 + VAR64;
casex (VAR24)
4'VAR70: begin
VAR27 <= {VAR28{1'b1}};
VAR1 <= {VAR28{1'b0}};
end
4'VAR49: begin
VAR27 <= {VAR28{1'b1}};
VAR1 <= {VAR28{1'b1}};
end
4'VAR66: begin
VAR27 <= {VAR28{1'b0}};
VAR1 <= {VAR28{1'b0}};
end
4'b1000: begin
VAR27 <= {VAR28/4{4'h1}};
VAR1 <= {VAR28/4{4'hE}};
end
4'b1001: begin
VAR27 <= {VAR28/4{4'hE}};
VAR1 <= {VAR28/4{4'h1}};
end
4'b1010: begin
VAR27 <= {(VAR28/4){4'hE}};
VAR1 <= {(VAR28/4){4'h1}};
end
4'b1011: begin
VAR27 <= {(VAR28/4){4'hE}};
VAR1 <= {(VAR28/4){4'h1}};
end
4'b1100: begin
VAR27 <= {VAR28/4{4'h1}};
VAR1 <= {VAR28/4{4'hE}};
end
4'b1101: begin
VAR27 <= {VAR28/4{4'hE}};
VAR1 <= {VAR28/4{4'h1}};
end
4'b1110: begin
VAR27 <= {(VAR28/4){4'h1}};
VAR1 <= {(VAR28/4){4'hE}};
end
4'b1111: begin
VAR27 <= {(VAR28/4){4'h1}};
VAR1 <= {(VAR28/4){4'hE}};
end
endcase
end
end
always @(posedge VAR56)
VAR42 <= VAR14;
always @(negedge VAR18)
VAR19 <= VAR37;
always @(negedge VAR18)
VAR69 <= VAR52;
generate
if (VAR8 > 3) begin
always @(posedge VAR18) begin
VAR25 <= 'b0;
VAR25[0] <= VAR54;
end
end else begin
always @ (*) begin
VAR25 = 'b0;
VAR25[0] = VAR54;
end
end
endgenerate
assign VAR55 = VAR38;
assign VAR12 = VAR47[VAR28-1:0];
assign VAR11 = VAR47[(2*VAR28)-1:VAR28];
assign VAR22 = VAR16[VAR43-1:0];
assign VAR71 = VAR16[(2*VAR43)-1:VAR43];
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_pwrgood_pp_g/sky130_fd_sc_ms__udp_pwrgood_pp_g.symbol.v | 1,285 | module MODULE1 (
input VAR1 ,
output VAR2,
input VAR3
);
endmodule | apache-2.0 |
PeterMagnusson/modexp | src/rtl/shr32.v | 2,264 | module MODULE1(
input wire [31 : 0] VAR3,
input wire VAR4,
output wire [31 : 0] VAR2,
output wire VAR1
);
assign VAR2 = {VAR4, VAR3[31 : 1]};
assign VAR1 = VAR3[0];
endmodule | bsd-2-clause |
zhangly/azpr_cpu | rtl/cpu/rtl/id_stage.v | 7,148 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR9] VAR49, input wire [VAR9] VAR8, output wire [VAR21] VAR36, output wire [VAR21] VAR29,
input wire VAR28, input wire [VAR9] VAR12, input wire [VAR21] VAR13, input wire VAR2, input wire [VAR9] VAR43,
input wire [VAR30] VAR48, input wire [VAR9] VAR11, output wire [VAR21] VAR45,
input wire VAR4, input wire VAR47, output wire [VAR37] VAR19, output wire VAR39, output wire VAR16,
input wire [VAR37] VAR23, input wire [VAR9] VAR25, input wire VAR31,
output wire [VAR37] VAR26, output wire VAR44, output wire [VAR51] VAR22, output wire [VAR9] VAR42, output wire [VAR9] VAR40, output wire VAR5, output wire [VAR3] VAR24, output wire [VAR9] VAR32, output wire [VAR7] VAR6, output wire [VAR21] VAR50, output wire VAR17, output wire [VAR10] VAR46 );
wire [VAR51] VAR35; wire [VAR9] VAR1; wire [VAR9] VAR33; wire VAR34; wire [VAR3] VAR14; wire [VAR9] VAR27; wire [VAR7] VAR38; wire [VAR21] VAR18; wire VAR20; wire [VAR10] VAR41;
decoder decoder (
.VAR23 (VAR23), .VAR25 (VAR25), .VAR31 (VAR31),
.VAR49 (VAR49), .VAR8 (VAR8), .VAR36 (VAR36), .VAR29 (VAR29),
.VAR44 (VAR44), .VAR50 (VAR50), .VAR17 (VAR17), .VAR24 (VAR24), .VAR28 (VAR28), .VAR12 (VAR12), .VAR13 (VAR13), .VAR2 (VAR2), .VAR43 (VAR43),
.VAR48 (VAR48), .VAR11 (VAR11), .VAR45 (VAR45),
.VAR35 (VAR35), .VAR1 (VAR1), .VAR33 (VAR33), .VAR19 (VAR19), .VAR39 (VAR39), .VAR34 (VAR34), .VAR14 (VAR14), .VAR27 (VAR27), .VAR38 (VAR38), .VAR18 (VAR18), .VAR20 (VAR20), .VAR41 (VAR41), .VAR16 (VAR16) );
VAR15 VAR15 (
.clk (clk), .reset (reset),
.VAR35 (VAR35), .VAR1 (VAR1), .VAR33 (VAR33), .VAR34 (VAR34), .VAR14 (VAR14), .VAR27 (VAR27), .VAR38 (VAR38), .VAR18 (VAR18), .VAR20 (VAR20), .VAR41 (VAR41),
.VAR4 (VAR4), .VAR47 (VAR47),
.VAR23 (VAR23), .VAR31 (VAR31),
.VAR26 (VAR26), .VAR44 (VAR44), .VAR22 (VAR22), .VAR42 (VAR42), .VAR40 (VAR40), .VAR5 (VAR5), .VAR24 (VAR24), .VAR32 (VAR32), .VAR6 (VAR6), .VAR50 (VAR50), .VAR17 (VAR17), .VAR46 (VAR46) );
endmodule | mit |
ptracton/Picoblaze | PicoBlaze_GPIO_Example/PicoBlaze_GPIO_Example.srcs/sources_1/imports/PicoBlaze_GPIO_Example/gpio.v | 3,720 | module MODULE1 (
VAR1,
MODULE1,
clk, VAR8, VAR11
) ;
input clk;
input [7:0] VAR8;
output [7:0] VAR1; input [7:0] VAR11;
inout [7:0] MODULE1;
VAR12 VAR2(
.VAR1 (VAR1[0]),
.MODULE1 (MODULE1[0]),
.clk (clk),
.VAR8 (VAR8[0]),
.VAR11 (VAR11[0]));
VAR12 VAR6(
.VAR1 (VAR1[1]),
.MODULE1 (MODULE1[1]),
.clk (clk),
.VAR8 (VAR8[1]),
.VAR11 (VAR11[1]));
VAR12 VAR7(
.VAR1 (VAR1[2]),
.MODULE1 (MODULE1[2]),
.clk (clk),
.VAR8 (VAR8[2]),
.VAR11 (VAR11[2]));
VAR12 VAR3(
.VAR1 (VAR1[3]),
.MODULE1 (MODULE1[3]),
.clk (clk),
.VAR8 (VAR8[3]),
.VAR11 (VAR11[3]));
VAR12 VAR4(
.VAR1 (VAR1[4]),
.MODULE1 (MODULE1[4]),
.clk (clk),
.VAR8 (VAR8[4]),
.VAR11 (VAR11[4]));
VAR12 VAR10(
.VAR1 (VAR1[5]),
.MODULE1 (MODULE1[5]),
.clk (clk),
.VAR8 (VAR8[5]),
.VAR11 (VAR11[5]));
VAR12 VAR5(
.VAR1 (VAR1[6]),
.MODULE1 (MODULE1[6]),
.clk (clk),
.VAR8 (VAR8[6]),
.VAR11 (VAR11[6]));
VAR12 VAR9(
.VAR1 (VAR1[7]),
.MODULE1 (MODULE1[7]),
.clk (clk),
.VAR8 (VAR8[7]),
.VAR11 (VAR11[7]));
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_4.behavioral.v | 2,924 | module MODULE1( VAR26, VAR9, VAR23, VAR21 );
input VAR9, VAR26, VAR23;
output VAR21;
reg VAR22;
VAR7 VAR18(.VAR26(VAR26),.VAR9(VAR9),.VAR23(VAR23),.VAR21(VAR21),.VAR22(VAR22));
VAR7 VAR6(.VAR26(VAR26),.VAR9(VAR9),.VAR23(VAR23),.VAR21(VAR21),.VAR22(VAR22));
buf VAR10(VAR1,VAR23);
not VAR12(VAR15,VAR9);
and VAR5(VAR19,VAR23,VAR15);
and VAR2(VAR14,VAR23,VAR9);
not VAR8(VAR3,VAR9);
not VAR16(VAR20,VAR26);
and VAR4(VAR11,VAR20,VAR3);
not VAR25(VAR17,VAR26);
and VAR24(VAR13,VAR17,VAR9); | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_obc1/obc_lower.v | 7,045 | module MODULE1 (
address,
VAR2,
VAR15,
VAR27,
VAR24);
input [8:0] address;
input VAR2;
input [7:0] VAR15;
input VAR27;
output [7:0] VAR24;
tri1 VAR2;
wire [7:0] VAR20;
wire [7:0] VAR24 = VAR20[7:0];
VAR46 VAR18 (
.VAR44 (address),
.VAR13 (VAR2),
.VAR30 (VAR15),
.VAR7 (VAR27),
.VAR16 (VAR20),
.VAR37 (1'b0),
.VAR17 (1'b0),
.VAR1 (1'b1),
.VAR39 (1'b0),
.VAR4 (1'b0),
.VAR11 (1'b1),
.VAR42 (1'b1),
.VAR47 (1'b1),
.VAR8 (1'b1),
.VAR50 (1'b1),
.VAR25 (1'b1),
.VAR38 (1'b1),
.VAR35 (1'b1),
.VAR33 (),
.VAR40 (),
.VAR34 (1'b1),
.VAR48 (1'b1),
.VAR55 (1'b0));
VAR18.VAR3 = "VAR10",
VAR18.VAR26 = "VAR10",
VAR18.VAR45 = "VAR43 VAR5 VAR49",
VAR18.VAR32 = "VAR6=VAR29",
VAR18.VAR22 = "VAR46",
VAR18.VAR54 = 512,
VAR18.VAR41 = "VAR12",
VAR18.VAR19 = "VAR23",
VAR18.VAR53 = "VAR14",
VAR18.VAR36 = "VAR28",
VAR18.VAR52 = "VAR9",
VAR18.VAR51 = 9,
VAR18.VAR21 = 8,
VAR18.VAR31 = 1;
endmodule | gpl-2.0 |
natsutan/NPU | fpga_implement/npu8/npu8.ip_user_files/ip/mul8_16/mul8_16_stub.v | 1,252 | module MODULE1(VAR3, VAR1, VAR4, VAR2)
;
input VAR3;
input [7:0]VAR1;
input [15:0]VAR4;
output [15:0]VAR2;
endmodule | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_axi_basic_tx.v | 10,039 | module MODULE1 #(
parameter VAR34 = 128, parameter VAR22 = "VAR10", parameter VAR32 = "VAR2", parameter VAR20 = "VAR2", parameter VAR42 = 1,
parameter VAR26 = (VAR34 == 128) ? 2 : 1, parameter VAR8 = VAR34 / 8 ) (
input [VAR34-1:0] VAR41, input VAR15, output VAR29, input [VAR8-1:0] VAR17, input VAR6, input [3:0] VAR43,
input VAR37, input VAR16,
output [VAR34-1:0] VAR45, output VAR7, output VAR3, output VAR27, input VAR9, output VAR13, output [VAR26-1:0] VAR36, output VAR33, output VAR12, input [5:0] VAR24, output VAR25,
input VAR19, output VAR4, input VAR21,
input [2:0] VAR5,
input VAR23, input [1:0] VAR11, input [31:0] VAR28, input VAR46,
input VAR31, output VAR18,
input VAR38, input VAR40 );
wire VAR14;
VAR39 #(
.VAR34( VAR34 ),
.VAR20( VAR20 ),
.VAR42( VAR42 ),
.VAR26( VAR26 ),
.VAR8( VAR8 )
) VAR1 (
.VAR41( VAR41 ),
.VAR29( VAR29 ),
.VAR15( VAR15 ),
.VAR17( VAR17 ),
.VAR6( VAR6 ),
.VAR43( VAR43 ),
.VAR45( VAR45 ),
.VAR7( VAR7 ),
.VAR3( VAR3 ),
.VAR27( VAR27 ),
.VAR9( VAR9 ),
.VAR13( VAR13 ),
.VAR36( VAR36 ),
.VAR33( VAR33 ),
.VAR12( VAR12 ),
.VAR25( VAR25 ),
.VAR21( VAR21 ),
.VAR14( VAR14 ),
.VAR38( VAR38 ),
.VAR40( VAR40 )
);
generate
if(VAR20 == "VAR2") begin : VAR30
VAR35 #(
.VAR34( VAR34 ),
.VAR22( VAR22 ),
.VAR32( VAR32 ),
.VAR42( VAR42 )
) VAR44 (
.VAR41( VAR41 ),
.VAR15( VAR15 ),
.VAR43( VAR43 ),
.VAR6( VAR6 ),
.VAR37( VAR37 ),
.VAR16( VAR16 ),
.VAR24( VAR24 ),
.VAR9( VAR9 ),
.VAR19( VAR19 ),
.VAR4( VAR4 ),
.VAR21( VAR21 ),
.VAR5( VAR5 ),
.VAR23( VAR23 ),
.VAR11( VAR11 ),
.VAR28( VAR28 ),
.VAR46( VAR46 ),
.VAR31( VAR31 ),
.VAR18( VAR18 ),
.VAR14( VAR14 ),
.VAR38( VAR38 ),
.VAR40( VAR40 )
);
end
else begin : VAR47
assign VAR14 = 1'b0;
assign VAR18 = VAR37;
assign VAR4 = VAR16;
end
endgenerate
endmodule | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_nios2_gen2_0.v | 5,764 | module MODULE1 (
input wire clk, input wire VAR17, input wire VAR25, output wire [28:0] VAR13, output wire [3:0] VAR15, output wire VAR24, input wire [31:0] VAR22, input wire VAR5, output wire VAR16, output wire [31:0] VAR2, output wire VAR20, output wire [28:0] VAR8, output wire VAR19, input wire [31:0] VAR21, input wire VAR9, input wire [31:0] irq, output wire VAR14, input wire [8:0] VAR1, input wire [3:0] VAR3, input wire VAR4, input wire VAR6, output wire [31:0] VAR10, output wire VAR11, input wire VAR23, input wire [31:0] VAR26, output wire VAR12 );
VAR18 VAR7 (
.clk (clk), .VAR17 (VAR17), .VAR25 (VAR25), .VAR13 (VAR13), .VAR15 (VAR15), .VAR24 (VAR24), .VAR22 (VAR22), .VAR5 (VAR5), .VAR16 (VAR16), .VAR2 (VAR2), .VAR20 (VAR20), .VAR8 (VAR8), .VAR19 (VAR19), .VAR21 (VAR21), .VAR9 (VAR9), .irq (irq), .VAR14 (VAR14), .VAR1 (VAR1), .VAR3 (VAR3), .VAR4 (VAR4), .VAR6 (VAR6), .VAR10 (VAR10), .VAR11 (VAR11), .VAR23 (VAR23), .VAR26 (VAR26), .VAR12 (VAR12) );
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.behavioral.pp.v | 1,159 | module MODULE1( VAR4, VAR3, VAR7, VAR1 );
input VAR4;
inout VAR7, VAR1;
output VAR3;
VAR2 VAR5(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR1(VAR1));
VAR2 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3b/sky130_fd_sc_ms__nand3b.behavioral.v | 1,497 | module MODULE1 (
VAR2 ,
VAR9,
VAR3 ,
VAR10
);
output VAR2 ;
input VAR9;
input VAR3 ;
input VAR10 ;
supply1 VAR6;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR13 ;
wire VAR4 ;
wire VAR11;
not VAR1 (VAR4 , VAR9 );
nand VAR5 (VAR11, VAR3, VAR4, VAR10 );
buf VAR12 (VAR2 , VAR11 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp_dramgif.v | 8,240 | module MODULE1(
VAR37, VAR35, VAR49, VAR31,
VAR57, VAR14, VAR10,
VAR50, VAR22, VAR59,
VAR39, VAR27, VAR26, VAR63,
VAR33, VAR9, VAR54,
VAR6, VAR13, VAR30,
VAR25, VAR23,
VAR5, VAR61, VAR58,
VAR51, VAR4
);
input VAR39;
input VAR27;
input VAR26;
input VAR63;
input VAR33;
input [9:0] VAR9;
input VAR54;
input VAR6;
input VAR13;
input VAR30;
input VAR25;
input VAR23;
input VAR5;
input VAR61;
input VAR58;
input VAR51;
input VAR4;
output VAR37;
output VAR35;
output VAR49;
output VAR31;
output VAR57;
output VAR14;
output VAR10;
output VAR50;
output VAR22;
output VAR59;
wire VAR16;
wire VAR41;
wire VAR47;
wire VAR24;
wire VAR42;
wire VAR2;
wire VAR38;
wire [9:0] VAR28;
wire [9:0] VAR56;
wire [9:0] VAR53;
wire VAR52;
wire VAR62;
wire VAR32;
wire VAR29;
wire VAR17;
wire VAR12;
wire VAR46;
wire VAR36;
assign VAR35 = VAR39 ;
assign VAR31 = VAR39 ;
assign VAR38 = VAR4 | ~VAR26;
assign VAR16 = VAR38 ? 1'b1: VAR25 & VAR33;
assign VAR41 = VAR38 ? 1'b1: VAR23 & VAR33;
assign VAR47 = VAR38 ? 1'b1: VAR5 & VAR33;
assign VAR24 = VAR38 ? 1'b1: VAR61 & VAR33;
assign VAR42 = VAR38 ? 1'b1: VAR58 & VAR33;
assign VAR2 = VAR38 ? 1'b1: VAR51 & VAR33;
VAR20 VAR3(
.din (VAR16),
.clk (VAR63),
.VAR21(VAR39),
.VAR15 (VAR57));
VAR20 VAR7(
.din (VAR41),
.clk (VAR63),
.VAR21(VAR39),
.VAR15 (VAR14));
VAR20 VAR55(
.din (VAR47),
.clk (VAR63),
.VAR21(VAR39),
.VAR15 (VAR10));
VAR20 VAR43(
.din (VAR24),
.clk (VAR63),
.VAR21(VAR39),
.VAR15 (VAR50));
VAR20 VAR40(
.din (VAR42),
.clk (VAR63),
.VAR21(VAR39),
.VAR15 (VAR22));
VAR20 VAR8(
.din (VAR2),
.clk (VAR63),
.VAR21(VAR39),
.VAR15 (VAR59));
VAR44 VAR19(
.din (1'b0),
.clk (VAR63),
.VAR18 (VAR27),
.VAR15(VAR62));
assign VAR28 = VAR53 - 10'h001;
assign VAR56 = VAR62? VAR9[9:0]:
(|(VAR53[9:1])) ? VAR28 : VAR9[9:0];
VAR20 #(10) VAR60 (
.din (VAR56),
.clk (VAR63),
.VAR21 (VAR27),
.VAR15(VAR53));
assign VAR52 = ~(|(VAR53[9:1]));
assign VAR32 = (VAR53 == VAR45) & VAR36? 1'b1:
VAR13? 1'b0:
VAR37;
VAR20 VAR48(
.din (VAR32 & VAR33),
.clk (VAR63),
.VAR21(VAR39),
.VAR15(VAR37));
assign VAR29 =
(VAR30|VAR13) ? 1'b0:
(VAR53 == VAR45) & VAR12? 1'b1:
VAR49;
VAR20 VAR34(
.din (VAR29 & VAR33),
.clk (VAR63),
.VAR21(VAR39),
.VAR15(VAR49));
assign VAR46 = VAR54 & VAR52 ? 1'b1:
VAR52 & VAR36 ? 1'b0:
VAR36;
VAR20 VAR1( .din (VAR46 & VAR33),
.clk (VAR63),
.VAR21(VAR39),
.VAR15(VAR36));
assign VAR17 = VAR6 & VAR52 ? 1'b1:
VAR52 & VAR12 ? 1'b0:
VAR12;
VAR20 VAR11( .din (VAR17 & VAR33 ),
.clk (VAR63),
.VAR21(VAR39),
.VAR15(VAR12));
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai.behavioral.pp.v | 2,059 | module MODULE1 (
VAR5 ,
VAR11 ,
VAR16 ,
VAR4 ,
VAR7 ,
VAR1 ,
VAR6,
VAR9,
VAR14 ,
VAR15
);
output VAR5 ;
input VAR11 ;
input VAR16 ;
input VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR6;
input VAR9;
input VAR14 ;
input VAR15 ;
wire VAR3 ;
wire VAR12 ;
wire VAR10;
or VAR17 (VAR3 , VAR7, VAR4, VAR16, VAR11 );
nand VAR2 (VAR12 , VAR1, VAR3 );
VAR18 VAR13 (VAR10, VAR12, VAR6, VAR9);
buf VAR8 (VAR5 , VAR10 );
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v | 3,933 | module MODULE1 #
(
parameter integer VAR18 = 4,
parameter integer VAR6 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR18-1:0] VAR20 ,
input wire [VAR6-1:0] VAR7 ,
input wire [7:0] VAR10 ,
input wire [2:0] VAR25 ,
input wire [1:0] VAR12 ,
input wire VAR27 ,
output wire VAR4 ,
output wire VAR8 ,
output wire [VAR6-1:0] VAR29 ,
input wire VAR28 ,
output wire [VAR18-1:0] VAR23 ,
output wire VAR9 ,
output wire VAR19 ,
input wire VAR26
);
wire VAR32 ;
wire VAR17 ;
wire VAR5;
wire VAR15;
reg [VAR18-1:0] VAR31;
VAR2 #
(
.VAR6 ( VAR6 )
)
VAR21
(
.clk ( clk ) ,
.reset ( reset ) ,
.VAR11 ( VAR7 ) ,
.VAR22 ( VAR10 ) ,
.VAR24 ( VAR25 ) ,
.VAR16 ( VAR12 ) ,
.VAR30 ( VAR27 & VAR5 ) ,
.VAR15 ( VAR15 ) ,
.VAR13 ( VAR29 ) ,
.VAR32 ( VAR32 ) ,
.VAR17 ( VAR17 )
);
VAR3 VAR1
(
.clk ( clk ) ,
.reset ( reset ) ,
.VAR4 ( VAR4 ) ,
.VAR27 ( VAR27 ) ,
.VAR10 ( VAR10 ) ,
.VAR8 ( VAR8 ) ,
.VAR28 ( VAR28 ) ,
.VAR32 ( VAR32 ) ,
.VAR17 ( VAR17 ) ,
.VAR14 ( ~VAR26 ) ,
.VAR5 ( VAR5 ) ,
.VAR9 ( VAR9 )
);
assign VAR23 = VAR31;
assign VAR19 = ~VAR17;
always @(posedge clk) begin
VAR31 <= VAR20 ;
end
endmodule | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_AsyncResetRegVec.v | 1,798 | module MODULE1(
input VAR3,
input reset,
input VAR2,
output VAR5,
input VAR4
);
wire VAR12;
wire VAR10;
wire VAR11;
wire VAR6;
wire VAR7;
VAR1 VAR13 (
.rst(VAR12),
.clk(VAR10),
.en(VAR11),
.VAR9(VAR6),
.VAR8(VAR7)
);
assign VAR5 = VAR6;
assign VAR12 = reset;
assign VAR10 = VAR3;
assign VAR11 = VAR4;
assign VAR7 = VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb_lp.v | 2,322 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR11 ,
VAR7 ,
VAR9 ,
VAR3,
VAR5,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR6 ;
input VAR11 ;
input VAR7 ;
input VAR9 ;
input VAR3;
input VAR5;
input VAR2 ;
input VAR1 ;
VAR8 VAR10 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR4 ,
VAR6 ,
VAR11 ,
VAR7,
VAR9
);
output VAR4 ;
input VAR6 ;
input VAR11 ;
input VAR7;
input VAR9;
supply1 VAR3;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR1 ;
VAR8 VAR10 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi.pp.symbol.v | 1,380 | module MODULE1 (
input VAR1 ,
input VAR7 ,
input VAR9 ,
input VAR4 ,
output VAR8 ,
input VAR2 ,
input VAR6,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/cache/CacheBlockRAM_bb.v | 8,598 | module MODULE1 (
VAR5,
VAR8,
VAR6,
VAR9,
VAR3,
VAR1,
VAR7,
VAR4,
VAR2);
input [8:0] VAR5;
input [8:0] VAR8;
input VAR6;
input [17:0] VAR9;
input [17:0] VAR3;
input VAR1;
input VAR7;
output [17:0] VAR4;
output [17:0] VAR2;
tri1 VAR6;
tri0 VAR1;
tri0 VAR7;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn_8.v | 2,150 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR8,
VAR6,
VAR7,
VAR1 ,
VAR9
);
output VAR3 ;
input VAR5 ;
input VAR8;
input VAR6;
input VAR7;
input VAR1 ;
input VAR9 ;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR3 ,
VAR5 ,
VAR8
);
output VAR3 ;
input VAR5 ;
input VAR8;
supply1 VAR6;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR9 ;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule | apache-2.0 |
nyaxt/dmix | mpemu_scale_t.v | 1,591 | module MODULE1;
reg [31:0] VAR4 [VAR1-1:0];
reg [31:0] VAR10 [VAR1-1:0];
reg [31:0] VAR7 [VAR1-1:0];
reg clk;
reg [23:0] VAR9;
reg [31:0] VAR6;
wire [31:0] VAR2;
VAR11 VAR8(
.clk(clk),
.VAR9(VAR9), .VAR6(VAR6),
.VAR2(VAR2));
parameter VAR3 = 41.0;
integer VAR5; | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_uitofp.v | 2,407 | module MODULE1(VAR2, VAR10,
VAR21, VAR14, VAR29,
VAR24, VAR7, VAR23);
parameter VAR12 = 32;
parameter VAR5 = 6;
parameter VAR19 = 64;
input VAR2, VAR10;
input [VAR12-1:0] VAR21;
input VAR14;
output VAR29;
output [VAR12-1:0] VAR24;
input VAR7;
output VAR23;
reg [VAR5-1:0] VAR20;
wire [VAR12-1:0] VAR15;
wire VAR17;
wire VAR22;
wire VAR8;
VAR16 VAR6 ( .VAR2(VAR2), .VAR10(VAR10),
.VAR3(VAR21), .VAR1(VAR15), .VAR18(VAR14),
.VAR4( VAR17 ), .VAR26(VAR8), .VAR27(VAR29) );
VAR11 VAR25( .VAR2(VAR2), .enable(~VAR22),
.VAR13(VAR15), .VAR28(VAR24));
always @(posedge VAR2 or negedge VAR10)
begin
if (~VAR10)
begin
VAR20 <= {VAR5{1'b0}};
end
else
begin
if(~VAR22)
VAR20 <= { VAR17, VAR20[VAR5-1:1] };
end
end
assign VAR22 = (VAR20[0] & VAR7);
assign VAR8 = (VAR20[0] & VAR7) | ~VAR17;
assign VAR23 = VAR20[0];
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp.behavioral.v | 2,290 | module MODULE1 (
VAR8 ,
VAR1,
VAR12 ,
VAR13
);
output VAR8 ;
input VAR1;
input VAR12 ;
input VAR13 ;
supply1 VAR11;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR7 ;
wire VAR15 ;
reg VAR18 ;
wire VAR14 ;
wire VAR16 ;
wire VAR9 ;
wire VAR3;
wire VAR17 ;
wire VAR19 ;
wire VAR5 ;
wire VAR4 ;
not VAR10 (VAR15 , VAR3 );
VAR21 VAR22 (VAR17 , VAR14, VAR16, VAR15, VAR18, VAR11, VAR2);
assign VAR19 = ( VAR11 === 1'b1 );
assign VAR5 = ( VAR19 && ( VAR3 === 1'b1 ) );
assign VAR4 = ( VAR19 && ( VAR1 === 1'b1 ) );
buf VAR20 (VAR8 , VAR17 );
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/user_logic_if/user_dma_req_arbitrator.v | 4,758 | module MODULE1 #(
parameter VAR18 = 'd4,
parameter VAR5 = 'd32,
parameter VAR29 = 'd12,
parameter VAR4 = 'd8,
parameter VAR39 = 'd64,
parameter VAR26 = 'd5
)
(
input VAR2,
input VAR30,
input [VAR18-1:0] VAR9,
input [VAR5*VAR18-1:0] VAR25,
input [VAR29*VAR18-1:0] VAR35,
input [VAR4*VAR18-1 :0] VAR15,
output reg [VAR18-1:0] VAR32,
input [VAR18-1:0] VAR7,
input [VAR5*VAR18-1:0] VAR31,
output reg [VAR18-1:0] VAR8,
input [VAR18*VAR39-1:0] VAR33,
input [VAR18*VAR26-1:0] VAR36,
output reg [VAR18-1:0] VAR24,
output reg VAR37,
input VAR14,
output reg [VAR5-1:0] VAR6,
output reg [VAR29-1:0] VAR3,
output reg [VAR4-1:0] VAR38,
output reg VAR28,
output reg [VAR5-1:0] VAR13,
input VAR11,
output reg [VAR39-1:0] VAR10,
output reg [VAR26-1:0] VAR20,
input VAR21
);
reg [VAR16(VAR18)-1:0] VAR19;
reg [VAR16(VAR18)-1:0] VAR22;
localparam VAR17 = 'd0,
VAR23 = 'd1;
reg VAR34;
reg VAR12;
wire VAR27;
wire VAR1;
assign VAR27 = |VAR7[VAR18-1:0];
assign VAR1 = |VAR9[VAR18-1:0];
always@(*)
begin
VAR8 <= {VAR18{1'b0}};
VAR8[VAR22] <= VAR11;
VAR10 <= VAR33[VAR22*VAR39+:VAR39];
VAR6 <= VAR25[VAR19*VAR5+:VAR5];
VAR3 <= VAR35[VAR19*VAR29+:VAR29];
VAR38 <= VAR15[VAR19*VAR4+:VAR4];
VAR13 <= VAR31[VAR22*VAR5+:VAR5];
VAR20 <= VAR36[VAR22*VAR26+:VAR26];
VAR24 <= {VAR18{1'b0}};
VAR24[VAR22] <= VAR21;
VAR37 <= VAR9[VAR19];
VAR32 <= {VAR18{1'b0}};
VAR32[VAR19] <= VAR14;
VAR28 <= VAR7[VAR22];
end
always @(posedge VAR2)
begin
if(!VAR30)
begin
VAR34 <= VAR17;
VAR19 <= 0;
end
else
begin
case(VAR34)
VAR17:begin
if(VAR9[VAR19])
begin
VAR34 <= VAR23;
end
else if(VAR1)
VAR19 <= VAR19 + 1'b1;
end
VAR23:begin
if(VAR14)
begin
VAR34 <= VAR17;
end
end
endcase
end
end
always @(posedge VAR2)
begin
if(!VAR30)
begin
VAR12 <= VAR17;
VAR22 <= 0;
end
else
begin
case(VAR12)
VAR17:begin
if(VAR7[VAR22])
begin
VAR12 <= VAR23;
end
else if(VAR27)
VAR22 <= VAR22 + 1'b1;
end
VAR23:begin
if(VAR21)
begin
VAR12 <= VAR17;
end
end
endcase
end
end
endmodule | mit |
walkthetalk/fsref | ip/s2mm/src/s2mm.v | 4,686 | module MODULE1 #
(
parameter integer VAR2 = 8,
parameter integer VAR6 = 12,
parameter integer VAR55 = 12,
parameter integer VAR5 = 12,
parameter integer VAR59 = 8,
parameter integer VAR66 = 16,
parameter integer VAR68 = 32,
parameter integer VAR20 = 32
)
(
input wire [VAR6-1:0] VAR51,
input wire [VAR55-1:0] VAR70,
input wire clk,
input wire VAR28,
input wire VAR26,
output wire VAR80,
input wire VAR37,
input wire [VAR2-1:0] VAR8,
input wire VAR73,
input wire VAR79,
output wire VAR9,
input wire VAR30,
input wire VAR47,
output wire [VAR2+1 : 0] VAR11,
output wire VAR42,
output wire VAR7,
input wire [VAR68-1:0] VAR39,
input wire [VAR20/VAR59*(VAR2+2)-1 : 0] VAR36,
input wire VAR31,
output wire VAR61,
input wire [VAR5-1:0] VAR48,
output wire [VAR68-1 : 0] VAR82,
output wire [7 : 0] VAR45,
output wire [2 : 0] VAR67,
output wire [1 : 0] VAR74,
output wire VAR83,
output wire [3 : 0] VAR63,
output wire [2 : 0] VAR24,
output wire [3 : 0] VAR3,
output wire VAR27,
input wire VAR21,
output wire [VAR20-1 : 0] VAR15,
output wire [VAR20/8-1 : 0] VAR49,
output wire VAR72,
output wire VAR38,
input wire VAR64,
input wire [1 : 0] VAR17,
input wire VAR18,
output wire VAR22
);
localparam VAR76 = VAR2 - 1;
localparam VAR1 = VAR2 + 1;
localparam VAR84 = VAR2 + 2;
localparam VAR62 = VAR20/VAR59;
function integer VAR16(input integer VAR50);
begin
VAR16 = VAR62-1-VAR50;
end
endfunction
function integer VAR81(input integer VAR50);
begin
VAR81 = VAR50 * VAR84 + VAR2;
end
endfunction
function integer VAR75(input integer VAR50);
begin
VAR75 = VAR50 * VAR84 + VAR1;
end
endfunction
wire VAR77;
assign VAR77 = (VAR28 && VAR26);
assign VAR80 = ~VAR77;
assign VAR11 = {VAR79, VAR73, VAR8};
assign VAR42 = VAR37 && VAR9;
reg VAR56;
assign VAR9 = VAR56;
always @ (posedge clk) begin
if (VAR80)
VAR56 <= 0;
end
else if (VAR42 && VAR47)
VAR56 <= 0;
else
VAR56 <= 1;
end
wire [VAR20-1 : 0] VAR44;
generate
genvar VAR50;
for (VAR50 = 0; VAR50 < VAR20/VAR2; VAR50 = VAR50+1) begin: VAR57
assign VAR44[VAR50*VAR59 + VAR76 : VAR50*VAR59]
= VAR36[VAR16(VAR50)*VAR84 + VAR76 : VAR16(VAR50)*VAR84];
end
endgenerate
VAR23 # (
.VAR5(VAR5),
.VAR66(VAR66),
.VAR68(VAR68),
.VAR20(VAR20),
.VAR6(VAR6),
.VAR55(VAR55),
.VAR62(VAR62)
) VAR33 (
.VAR51(VAR51),
.VAR70(VAR70),
.VAR26(VAR26),
.din(VAR44),
.VAR46(VAR61),
.VAR4(VAR48),
.VAR53(VAR7),
.VAR60(VAR39),
.VAR40(clk),
.VAR19(VAR28),
.VAR58(VAR82),
.VAR41(VAR45),
.VAR69(VAR67),
.VAR78(VAR74),
.VAR32(VAR83),
.VAR43(VAR63),
.VAR14(VAR24),
.VAR10(VAR3),
.VAR29(VAR27),
.VAR65(VAR21),
.VAR35(VAR15),
.VAR13(VAR49),
.VAR71(VAR72),
.VAR12(VAR38),
.VAR52(VAR64),
.VAR25(VAR17),
.VAR54(VAR18),
.VAR34(VAR22)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4/sky130_fd_sc_ms__nor4_2.v | 2,275 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR11 ,
VAR1 ,
VAR4 ,
VAR10,
VAR7,
VAR3 ,
VAR8
);
output VAR5 ;
input VAR2 ;
input VAR11 ;
input VAR1 ;
input VAR4 ;
input VAR10;
input VAR7;
input VAR3 ;
input VAR8 ;
VAR9 VAR6 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR5,
VAR2,
VAR11,
VAR1,
VAR4
);
output VAR5;
input VAR2;
input VAR11;
input VAR1;
input VAR4;
supply1 VAR10;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR8 ;
VAR9 VAR6 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v | 8,787 | module MODULE1 #
(
parameter VAR3 = "none",
parameter integer VAR16 = 1,
parameter integer VAR30 = 32,
parameter integer VAR34 = 32,
parameter integer VAR21 = 0,
parameter integer VAR33 = 1,
parameter integer VAR20 = 1,
parameter integer VAR5 = 1
)
(
input wire VAR6,
input wire VAR27,
input wire VAR38,
input wire VAR10,
output wire VAR32,
output wire [VAR16-1:0] VAR35,
output wire [VAR34-1:0] VAR39,
output wire [2-1:0] VAR12,
output wire VAR7,
output wire [VAR33-1:0] VAR31,
output wire VAR40,
input wire VAR42,
input wire [VAR16-1:0] VAR1,
input wire [VAR34-1:0] VAR22,
input wire [2-1:0] VAR8,
input wire VAR28,
input wire [VAR33-1:0] VAR41,
input wire VAR37,
output wire VAR25
);
localparam [2-1:0] VAR23 = 2'b00;
localparam [2-1:0] VAR26 = 2'b01;
localparam [2-1:0] VAR36 = 2'b10;
localparam [2-1:0] VAR24 = 2'b11;
wire VAR15;
wire VAR2;
wire VAR29;
wire VAR9;
wire [VAR16-1:0] VAR13;
wire [VAR34-1:0] VAR4;
wire [2-1:0] VAR19;
wire VAR14;
wire [VAR33-1:0] VAR17;
wire VAR11;
wire VAR18;
assign VAR9 = ~VAR29 & VAR38;
assign VAR25 = VAR9;
assign VAR11 = VAR37 & VAR38;
assign VAR2 = VAR11 & VAR18;
assign VAR15 = VAR38 & VAR2 & VAR28;
assign VAR32 = VAR15;
assign VAR29 = VAR11 & ~VAR18;
assign VAR14 = VAR28 &
( ~VAR10 | ( VAR20 == 0 ) );
assign VAR13 = VAR1;
assign VAR17 = VAR41;
assign VAR4 = VAR22;
assign VAR19 = VAR8;
assign VAR18 = VAR42;
assign VAR40 = VAR11;
assign VAR35 = VAR13;
assign VAR39 = VAR4;
assign VAR12 = VAR19;
assign VAR7 = VAR14;
assign VAR31 = VAR17;
endmodule | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/26bit/ReCodeRKOA/RKOA_OPCHANGE.v | 4,100 | module MODULE1
(
input wire [VAR16-1:0] VAR22,
input wire [VAR16-1:0] VAR15,
output reg [2*VAR16-1:0] VAR11
);
wire [1:0] VAR24;
wire [3:0] VAR14;
assign VAR24 = 2'b00;
assign VAR14 = 4'b0000;
wire [VAR16/2-1:0] VAR2;
wire [VAR16/2:0] VAR9;
wire [VAR16/2-3:0] VAR3;
wire [VAR16/2-4:0] VAR17;
reg [4*(VAR16/2)-1:0] VAR7 = 0;
assign VAR2 = (VAR16/2) *1'b0;
assign VAR9 = (VAR16/2+1)*1'b0;
assign VAR3 = (VAR16/2-2) *1'b0; assign VAR17 = (VAR16/2-1)*1'b0;
localparam VAR4 = VAR16/2;
generate
if (VAR16 <=VAR19 || VAR16 <=VAR18) begin
always @* begin
VAR11 <= VAR22 * VAR15;
end
end else begin
case (VAR16%2)
0:begin : VAR12
reg [VAR16/2:0] VAR1 = 0;
reg [VAR16/2:0] VAR20 = 0;
reg [VAR16-1:0] VAR23 = 0;
reg [VAR16-1:0] VAR13 = 0;
reg [VAR16+1:0] VAR5 = 0;
reg [2*(VAR16/2+2)-1:0] VAR25 = 0;
reg [2*(VAR16/2+2)-1:0] VAR8 = 0;
always @* begin : VAR6
VAR23 [VAR16-1:0] <= VAR22[(VAR16-1) -: VAR16/2] * VAR15[(VAR16-1) -: VAR16/2];
VAR13[VAR16-1:0] <= VAR22[((VAR16/2)-1):0] * VAR15[((VAR16/2)-1):0];
VAR1 <= (VAR22[((VAR16/2)-1):0] + VAR22[(VAR16-1) -: VAR16/2]);
VAR20 <= (VAR15[((VAR16/2)-1):0] + VAR15[(VAR16-1) -: VAR16/2]);
VAR5 <= VAR1 * VAR20;
VAR8 <= (VAR5 - (VAR23 + {VAR24,VAR13}));
VAR11[2*VAR16-1:0] <= {VAR8[2*(VAR16/2)+1:0],VAR2} + {VAR23,VAR13[2*(VAR16/2)-1:0]};
end
end
1:begin : VAR21
always @* begin : VAR10
reg [VAR16/2+1:0] VAR1;
reg [VAR16/2+1:0] VAR20;
reg [2*(VAR16/2)-1:0] VAR23;
reg [2*(VAR16/2+1)-1:0] VAR13;
reg [2*(VAR16/2+2)-1:0] VAR5;
reg [2*(VAR16/2+2)-1:0] VAR25;
reg [2*(VAR16/2+2)-1:0] VAR8;
VAR23 <= VAR22[VAR16-1:VAR16/2+1] * VAR15[VAR16-1:VAR16/2+1];
VAR13 <= VAR22[VAR16/2:0] * VAR15[VAR16/2:0];
VAR1 <= (VAR22[VAR16-VAR16/2-1:0] + VAR22[VAR16-1:VAR16-VAR16/2]);
VAR20 <= VAR15[VAR16-VAR16/2-1:0] + VAR15[VAR16-1:VAR16-VAR16/2];
VAR5 <= VAR1 * VAR20;
VAR8 <= (VAR5 - (VAR23 + VAR13));
VAR11<= {VAR8,VAR9} + {VAR23,VAR13};
end
end
endcase
end
endgenerate
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai_1.v | 2,424 | module MODULE1 (
VAR12 ,
VAR6 ,
VAR9 ,
VAR8 ,
VAR7 ,
VAR10 ,
VAR1,
VAR5,
VAR2 ,
VAR4
);
output VAR12 ;
input VAR6 ;
input VAR9 ;
input VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR1;
input VAR5;
input VAR2 ;
input VAR4 ;
VAR3 VAR11 (
.VAR12(VAR12),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR12 ,
VAR6,
VAR9,
VAR8,
VAR7,
VAR10
);
output VAR12 ;
input VAR6;
input VAR9;
input VAR8;
input VAR7;
input VAR10;
supply1 VAR1;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR4 ;
VAR3 VAR11 (
.VAR12(VAR12),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v | 56,935 | module MODULE1 (
input wire VAR145, input wire VAR232, input wire VAR6, input wire [31:0] VAR202, output wire VAR12, input wire [4:0] VAR9, input wire [31:0] VAR42, input wire VAR41, output wire [255:0] VAR55, output wire VAR86, input wire VAR225, input wire [255:0] VAR166, output wire [26:0] VAR248, output wire VAR14, output wire VAR167, input wire [255:0] VAR323, output wire [255:0] VAR127, output wire [7:0] VAR115, output wire [31:0] VAR179, input wire VAR314, input wire VAR278 );
wire VAR339; wire [9:0] VAR76; wire [255:0] VAR48; wire [31:0] VAR88; wire VAR104; wire VAR117; wire VAR334; wire [255:0] VAR274; wire VAR249; wire [31:0] VAR306; wire VAR155; wire VAR337; wire VAR285; wire VAR72; wire [363:0] VAR85; wire [0:0] VAR148; wire VAR341; wire VAR114; wire [12:0] VAR322; wire [255:0] VAR4; wire [31:0] VAR188; wire VAR140; wire VAR191; wire VAR302; wire [255:0] VAR271; wire VAR196; wire VAR87; wire [31:0] VAR263; wire VAR33; wire VAR10; wire VAR135; wire [364:0] VAR45; wire VAR132; wire VAR80; wire VAR273; wire VAR92; wire [364:0] VAR160; wire VAR214; wire VAR63; wire [257:0] VAR253; wire VAR129; wire VAR49; wire VAR252; wire VAR242; wire [363:0] VAR194; wire [0:0] VAR197; wire VAR20; wire VAR343; wire VAR270; wire VAR3; wire [363:0] VAR297; wire VAR234; wire VAR311; wire VAR126; wire VAR295; wire [363:0] VAR31; wire [0:0] VAR209; wire VAR67; wire VAR23; wire VAR37; wire VAR178; wire [363:0] VAR222; wire VAR313; wire VAR57; wire VAR331; wire VAR327; wire [363:0] VAR161; wire [0:0] VAR305; wire VAR96; wire VAR320; wire VAR105; wire VAR254; wire [363:0] VAR187; wire [0:0] VAR25; wire VAR79; wire VAR203; wire VAR340; wire VAR151; wire [363:0] VAR264; wire [0:0] VAR268; wire VAR318;
VAR130 #(
.VAR288 (32),
.VAR336 (256),
.VAR156 (5),
.VAR246 (32),
.VAR199 (32),
.VAR190 (10),
.VAR173 (1),
.VAR212 (1),
.VAR200 (0),
.VAR183 (0),
.VAR287 (0),
.VAR15 (1),
.VAR83 (1),
.VAR219 (1),
.VAR7 (0),
.VAR259 (0),
.VAR215 (32),
.VAR324 (1),
.VAR304 (0),
.VAR84 (1),
.VAR280 (0),
.VAR277 (0),
.VAR1 (0)
) VAR11 (
.clk (VAR145), .reset (VAR232), .VAR256 (VAR88), .VAR38 (VAR76), .VAR150 (VAR334), .VAR144 (VAR117), .VAR330 (VAR339), .VAR75 (VAR155), .VAR158 (VAR306), .VAR44 (VAR274), .VAR103 (VAR48), .VAR315 (VAR104), .VAR89 (VAR249), .VAR286 (VAR202), .VAR171 (VAR12), .VAR99 (VAR9), .VAR230 (VAR42), .VAR119 (VAR41), .VAR2 (VAR55), .VAR284 (VAR86), .VAR272 (VAR225), .VAR224 (VAR166), .VAR228 (1'b0), .VAR238 (1'b0), .VAR198 (1'b0), .VAR28 (1'b0), .VAR261 (1'b0), .VAR112 (), .VAR213 (1'b1), .VAR107 (2'b00), .VAR64 (), .VAR134 (), .VAR124 (1'b0), .VAR207 (1'b0), .VAR73 () );
VAR176 #(
.VAR288 (27),
.VAR336 (256),
.VAR90 (256),
.VAR156 (8),
.VAR246 (32),
.VAR139 (32),
.VAR199 (32),
.VAR190 (13),
.VAR289 (0),
.VAR83 (1),
.VAR219 (1),
.VAR244 (0),
.VAR7 (0),
.VAR259 (0),
.VAR215 (32),
.VAR324 (0),
.VAR304 (0),
.VAR84 (0),
.VAR280 (0),
.VAR82 (0),
.VAR78 (0),
.VAR113 (1),
.VAR66 (0),
.VAR309 (0),
.VAR172 (0)
) VAR276 (
.clk (VAR145), .reset (VAR6), .VAR256 (VAR188), .VAR38 (VAR322), .VAR150 (VAR302), .VAR144 (VAR140), .VAR330 (VAR114), .VAR75 (VAR196), .VAR158 (VAR263), .VAR44 (VAR271), .VAR103 (VAR4), .VAR315 (VAR191), .VAR89 (VAR87), .VAR286 (VAR248), .VAR272 (VAR14), .VAR119 (VAR167), .VAR2 (VAR323), .VAR224 (VAR127), .VAR99 (VAR115), .VAR230 (VAR179), .VAR284 (VAR314), .VAR171 (VAR278), .VAR238 (), .VAR228 (), .VAR236 (), .VAR28 (), .VAR198 (), .VAR213 (), .VAR112 (1'b0), .VAR261 (), .VAR58 (), .VAR107 (), .VAR64 (2'b00), .VAR134 (1'b0), .VAR124 (), .VAR207 (), .VAR73 (1'b0) );
VAR111 #(
.VAR193 (354),
.VAR159 (352),
.VAR65 (347),
.VAR77 (339),
.VAR342 (339),
.VAR147 (342),
.VAR282 (340),
.VAR229 (344),
.VAR299 (343),
.VAR128 (338),
.VAR32 (326),
.VAR181 (319),
.VAR262 (288),
.VAR13 (320),
.VAR157 (321),
.VAR335 (322),
.VAR39 (323),
.VAR265 (324),
.VAR164 (325),
.VAR154 (255),
.VAR59 (0),
.VAR21 (287),
.VAR29 (256),
.VAR250 (349),
.VAR319 (349),
.VAR56 (350),
.VAR177 (350),
.VAR170 (351),
.VAR241 (351),
.VAR303 (358),
.VAR125 (355),
.VAR201 (346),
.VAR36 (346),
.VAR153 (348),
.VAR251 (348),
.VAR152 (345),
.VAR81 (345),
.VAR312 (360),
.VAR116 (359),
.VAR121 (361),
.VAR71 (363),
.VAR70 (364),
.VAR47 (1),
.VAR156 (10),
.VAR35 (0),
.VAR204 (0),
.VAR52 (1),
.VAR328 (0),
.VAR46 (1),
.VAR7 (0),
.VAR259 (0)
) VAR294 (
.clk (VAR145), .reset (VAR232), .VAR286 (VAR88), .VAR272 (VAR117), .VAR119 (VAR334), .VAR224 (VAR48), .VAR2 (VAR274), .VAR171 (VAR339), .VAR284 (VAR155), .VAR230 (VAR306), .VAR99 (VAR76), .VAR261 (VAR249), .VAR28 (VAR104), .VAR120 (VAR270), .VAR185 (VAR297), .VAR237 (VAR3), .VAR316 (VAR343), .VAR195 (VAR234), .VAR205 (VAR285), .VAR292 (VAR85), .VAR333 (VAR148), .VAR296 (VAR72), .VAR53 (VAR337), .VAR108 (VAR341), .VAR64 (), .VAR207 (1'b0), .VAR73 () );
VAR137 #(
.VAR154 (255),
.VAR59 (0),
.VAR65 (347),
.VAR221 (8),
.VAR21 (287),
.VAR29 (256),
.VAR181 (319),
.VAR262 (288),
.VAR13 (320),
.VAR157 (321),
.VAR335 (322),
.VAR39 (323),
.VAR265 (324),
.VAR250 (349),
.VAR319 (349),
.VAR56 (350),
.VAR177 (350),
.VAR77 (339),
.VAR342 (339),
.VAR128 (338),
.VAR32 (326),
.VAR193 (354),
.VAR159 (352),
.VAR312 (360),
.VAR116 (359),
.VAR147 (342),
.VAR282 (340),
.VAR121 (361),
.VAR71 (363),
.VAR47 (1),
.VAR70 (364),
.VAR192 (13),
.VAR102 (0),
.VAR233 (1),
.VAR7 (0),
.VAR259 (0)
) VAR210 (
.clk (VAR145), .reset (VAR6), .VAR101 (VAR188), .VAR258 (VAR322), .VAR300 (VAR263), .VAR17 (VAR87), .VAR68 (VAR191), .VAR40 (VAR271), .VAR122 (VAR196), .VAR133 (VAR302), .VAR189 (VAR114), .VAR325 (VAR4), .VAR19 (VAR140), .VAR53 (VAR23), .VAR108 (VAR313), .VAR205 (VAR37), .VAR292 (VAR222), .VAR296 (VAR178), .VAR195 (VAR20), .VAR120 (VAR252), .VAR185 (VAR194), .VAR237 (VAR242), .VAR316 (VAR49), .VAR91 (VAR197), .VAR18 (VAR214), .VAR240 (VAR273), .VAR184 (VAR92), .VAR8 (VAR80), .VAR24 (VAR160), .VAR34 (VAR132), .VAR109 (VAR10), .VAR290 (VAR135), .VAR267 (VAR33), .VAR180 (VAR45), .VAR100 (VAR129), .VAR110 (VAR63), .VAR141 (VAR253), .VAR146 (VAR129), .VAR326 (VAR63), .VAR95 (VAR253), .VAR118 (2'b00), .VAR22 (), .VAR293 (1'b0) );
VAR97 #(
.VAR165 (1),
.VAR317 (365),
.VAR60 (15),
.VAR174 (0),
.VAR16 (0),
.VAR186 (1),
.VAR291 (0),
.VAR93 (1),
.VAR142 (0),
.VAR43 (0),
.VAR257 (0),
.VAR74 (0)
) VAR266 (
.clk (VAR145), .reset (VAR6), .VAR231 (VAR45), .VAR175 (VAR10), .VAR138 (VAR132), .VAR208 (VAR135), .VAR255 (VAR33), .VAR5 (VAR160), .VAR51 (VAR273), .VAR54 (VAR214), .VAR269 (VAR92), .VAR223 (VAR80), .VAR106 (2'b00), .VAR247 (1'b0), .VAR283 (1'b0), .VAR218 (), .VAR338 (32'b00000000000000000000000000000000), .VAR243 (), .VAR62 (), .VAR332 (1'b0), .VAR168 (), .VAR260 (1'b0), .VAR211 (), .VAR149 (1'b0), .VAR123 () );
VAR216 VAR279 (
.VAR98 (VAR234), .VAR220 (VAR270), .VAR281 (VAR297), .VAR298 (VAR3), .VAR226 (VAR343), .clk (VAR145), .reset (VAR232), .VAR344 (VAR67), .VAR27 (VAR126), .VAR26 (VAR31), .VAR61 (VAR209), .VAR310 (VAR295), .VAR239 (VAR311) );
VAR182 VAR169 (
.VAR98 (VAR313), .VAR220 (VAR37), .VAR281 (VAR222), .VAR298 (VAR178), .VAR226 (VAR23), .clk (VAR145), .reset (VAR6), .VAR344 (VAR96), .VAR27 (VAR331), .VAR26 (VAR161), .VAR61 (VAR305), .VAR310 (VAR327), .VAR239 (VAR57) );
VAR307 VAR308 (
.clk (VAR145), .reset (VAR232), .VAR98 (VAR67), .VAR30 (VAR209), .VAR281 (VAR31), .VAR298 (VAR295), .VAR226 (VAR311), .VAR220 (VAR126), .VAR94 (VAR79), .VAR50 (VAR105), .VAR162 (VAR187), .VAR275 (VAR25), .VAR245 (VAR254), .VAR217 (VAR320) );
VAR321 VAR329 (
.clk (VAR145), .reset (VAR6), .VAR344 (VAR20), .VAR27 (VAR252), .VAR26 (VAR194), .VAR61 (VAR197), .VAR310 (VAR242), .VAR239 (VAR49), .VAR136 (VAR79), .VAR69 (VAR105), .VAR143 (VAR25), .VAR206 (VAR187), .VAR235 (VAR254), .VAR163 (VAR320) );
VAR307 VAR131 (
.clk (VAR145), .reset (VAR6), .VAR98 (VAR96), .VAR30 (VAR305), .VAR281 (VAR161), .VAR298 (VAR327), .VAR226 (VAR57), .VAR220 (VAR331), .VAR94 (VAR318), .VAR50 (VAR340), .VAR162 (VAR264), .VAR275 (VAR268), .VAR245 (VAR151), .VAR217 (VAR203) );
VAR227 VAR301 (
.clk (VAR145), .reset (VAR232), .VAR344 (VAR341), .VAR27 (VAR285), .VAR26 (VAR85), .VAR61 (VAR148), .VAR310 (VAR72), .VAR239 (VAR337), .VAR136 (VAR318), .VAR69 (VAR340), .VAR143 (VAR268), .VAR206 (VAR264), .VAR235 (VAR151), .VAR163 (VAR203) );
endmodule | mit |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_texcache.v | 10,795 | module MODULE1 #(
parameter VAR45 = 13,
parameter VAR102 = 26
) (
input VAR95,
input VAR84,
output [VAR102-1:0] VAR20,
output reg VAR36,
input VAR38,
input [63:0] VAR76,
input VAR30,
output VAR3,
input VAR17,
output VAR13,
input [VAR102-1-1:0] VAR11,
input [VAR102-1-1:0] VAR105,
input [VAR102-1-1:0] VAR48,
input [VAR102-1-1:0] VAR4,
input [VAR102-1-1:0] VAR103,
input [5:0] VAR19,
input [5:0] VAR49,
output VAR22,
input VAR108,
output reg [VAR102-1-1:0] VAR27,
output [15:0] VAR16,
output [15:0] VAR81,
output [15:0] VAR9,
output [15:0] VAR73,
output reg [5:0] VAR106,
output reg [5:0] VAR78,
output reg [21:0] VAR75,
output reg [21:0] VAR42,
output reg [21:0] VAR82,
output reg [21:0] VAR32,
output reg [21:0] VAR62,
output reg [21:0] VAR58,
output reg [21:0] VAR69,
output reg [21:0] VAR85
);
wire [VAR102-1:0] VAR18 = {VAR105, 1'b0};
wire [VAR102-1:0] VAR14 = {VAR48, 1'b0};
wire [VAR102-1:0] VAR60 = {VAR4, 1'b0};
wire [VAR102-1:0] VAR71 = {VAR103, 1'b0};
reg [VAR102-1:0] VAR51;
reg [VAR102-1:0] VAR7;
reg [VAR102-1:0] VAR35;
reg [VAR102-1:0] VAR55;
always @(posedge VAR95) begin
if(VAR13) begin
VAR51 <= VAR18;
VAR7 <= VAR14;
VAR35 <= VAR60;
VAR55 <= VAR71;
end
end
wire VAR59;
wire [31:0] VAR97;
wire [31:0] VAR47;
wire [31:0] VAR61;
wire [31:0] VAR99;
reg VAR2;
wire [VAR45-3-1:0] VAR50;
VAR94 #(
.VAR87(VAR45-2)
) VAR5 (
.VAR95(VAR95),
.VAR46(VAR59 ? VAR51[VAR45-1:2] : VAR18[VAR45-1:2]),
.d1(VAR97),
.VAR66(VAR59 ? VAR7[VAR45-1:2] : VAR14[VAR45-1:2]),
.d2(VAR47),
.VAR101(VAR59 ? VAR35[VAR45-1:2] : VAR60[VAR45-1:2]),
.d3(VAR61),
.VAR57(VAR59 ? VAR55[VAR45-1:2] : VAR71[VAR45-1:2]),
.d4(VAR99),
.VAR110(VAR2),
.VAR72(VAR50),
.VAR65(VAR76)
);
assign VAR16 = VAR51[1] ? VAR97[15:0] : VAR97[31:16];
assign VAR81 = VAR7[1] ? VAR47[15:0] : VAR47[31:16];
assign VAR9 = VAR35[1] ? VAR61[15:0] : VAR61[31:16];
assign VAR73 = VAR55[1] ? VAR99[15:0] : VAR99[31:16];
wire [1+VAR102-VAR45-1:0] VAR37;
wire [1+VAR102-VAR45-1:0] VAR8;
wire [1+VAR102-VAR45-1:0] VAR70;
wire [1+VAR102-VAR45-1:0] VAR44;
reg VAR107;
wire [VAR45-1-5:0] VAR111;
wire [1+VAR102-VAR45-1:0] VAR25;
VAR63 #(
.VAR87(VAR45-5),
.VAR23(1+VAR102-VAR45)
) VAR79 (
.VAR95(VAR95),
.VAR46(VAR59 ? VAR51[VAR45-1:5] : VAR18[VAR45-1:5]),
.d1(VAR37),
.VAR66(VAR59 ? VAR7[VAR45-1:5] : VAR14[VAR45-1:5]),
.d2(VAR8),
.VAR101(VAR59 ? VAR35[VAR45-1:5] : VAR60[VAR45-1:5]),
.d3(VAR70),
.VAR57(VAR59 ? VAR55[VAR45-1:5] : VAR71[VAR45-1:5]),
.d4(VAR44),
.VAR110(VAR107),
.VAR72(VAR111),
.VAR65(VAR25)
);
reg VAR109;
reg VAR1;
always @(posedge VAR95) begin
if(VAR84)
VAR1 <= 1'b0;
end
else if(VAR13)
VAR1 <= VAR17;
end
reg VAR67;
always @(posedge VAR95) VAR67 <= VAR107;
reg VAR40;
reg VAR80;
reg VAR28;
always @(posedge VAR95) begin
if(VAR13) begin
VAR40 <= VAR19 == 6'd0;
VAR80 <= VAR49 == 6'd0;
VAR28 <= (VAR19 == 6'd0) | (VAR49 == 6'd0);
end
end
wire VAR53 = VAR37[1+VAR102-VAR45-1];
wire [VAR102-1-VAR45:0] VAR83 = VAR37[VAR102-VAR45-1:0];
wire VAR86 = VAR8[1+VAR102-VAR45-1];
wire [VAR102-1-VAR45:0] VAR88 = VAR8[VAR102-VAR45-1:0];
wire VAR6 = VAR70[1+VAR102-VAR45-1];
wire [VAR102-1-VAR45:0] VAR100 = VAR70[VAR102-VAR45-1:0];
wire VAR74 = VAR44[1+VAR102-VAR45-1];
wire [VAR102-1-VAR45:0] VAR33 = VAR44[VAR102-VAR45-1:0];
wire VAR68 = ~VAR67 & VAR53 & (VAR83 == VAR51[VAR102-1:VAR45]);
wire VAR21 = VAR40 | (~VAR67 & VAR86 & (VAR88 == VAR7[VAR102-1:VAR45]));
wire VAR31 = VAR80 | (~VAR67 & VAR6 & (VAR100 == VAR35[VAR102-1:VAR45]));
wire VAR41 = VAR28 | (~VAR67 & VAR74 & (VAR33 == VAR55[VAR102-1:VAR45]));
assign VAR22 = VAR1 & VAR68 & VAR21 & VAR31 & VAR41;
assign VAR13 = ~VAR109 & ((VAR108 & VAR22) | ~VAR1);
assign VAR59 = ~VAR13;
reg VAR98;
always @(posedge VAR95) begin
if(VAR84)
VAR98 <= 1'b0;
end
else
VAR98 <= VAR13;
end
always @(posedge VAR95) begin
if(VAR84|VAR30) begin
VAR75 <= 22'd0;
VAR42 <= 22'd0;
VAR82 <= 22'd0;
VAR32 <= 22'd0;
VAR62 <= 22'd0;
VAR58 <= 22'd0;
VAR69 <= 22'd0;
VAR85 <= 22'd0;
end else begin
if(VAR98 & VAR1) begin
VAR75 <= VAR75 + 22'd1;
if(VAR68)
VAR42 <= VAR42 + 22'd1;
if(~VAR40) begin
VAR82 <= VAR82 + 22'd1;
if(VAR21)
VAR32 <= VAR32 + 22'd1;
end
if(~VAR80) begin
VAR62 <= VAR62 + 22'd1;
if(VAR31)
VAR58 <= VAR58 + 22'd1;
end
if(~VAR28) begin
VAR69 <= VAR69 + 22'd1;
if(VAR41)
VAR85 <= VAR85 + 22'd1;
end
end
end
end
integer VAR112, VAR24;
reg [15:0] VAR104;
always @(posedge VAR95) begin
if(VAR22 & VAR108) begin
VAR112 = (VAR51/2) % 512;
VAR24 = (VAR51/2) / 512;
VAR56(VAR112, VAR24, VAR104);
if(VAR16 != VAR104) begin
: VAR104 %VAR112, VAR10 %VAR112", VAR112, VAR24, VAR104, VAR16);
end
if(~VAR40) begin
VAR112 = (VAR7/2) % 512;
VAR24 = (VAR7/2) / 512;
VAR56(VAR112, VAR24, VAR104);
if(VAR81 != VAR104) begin
: VAR104 %VAR112, VAR10 %VAR112", VAR112, VAR24, VAR104, VAR81);
end
end
if(~VAR80) begin
VAR112 = (VAR35/2) % 512;
VAR24 = (VAR35/2) / 512;
VAR56(VAR112, VAR24, VAR104);
if(VAR9 != VAR104) begin
: VAR104 %VAR112, VAR10 %VAR112", VAR112, VAR24, VAR104, VAR9);
end
end
if(~VAR28) begin
VAR112 = (VAR55/2) % 512;
VAR24 = (VAR55/2) / 512;
VAR56(VAR112, VAR24, VAR104);
if(VAR73 != VAR104) begin
: VAR104 %VAR112, VAR10 %VAR112", VAR112, VAR24, VAR104, VAR73);
end
end
end
end
always @(posedge VAR95) begin
if(VAR13 & VAR17) begin
VAR27 <= VAR11;
VAR106 <= VAR19;
VAR78 <= VAR49;
end
end
reg VAR34;
reg [VAR102-1:0] VAR92;
always @(posedge VAR95) begin
if(VAR84)
VAR34 <= 1'b0;
end
else begin
if(VAR1) begin
VAR34 <= ~(VAR68 & VAR21 & VAR31 & VAR41);
if(~VAR68)
VAR92 <= VAR51;
end
else if(~VAR21)
VAR92 <= VAR7;
end
else if(~VAR31)
VAR92 <= VAR35;
end
else if(~VAR41)
VAR92 <= VAR55;
end
end
end
wire VAR93;
reg [VAR45-1-5:0] VAR96;
always @(posedge VAR95) begin
if(VAR109)
VAR96 <= VAR96 + 1'd1;
end
else
VAR96 <= {VAR45-5{1'b0}};
end
assign VAR93 = &VAR96;
reg VAR90;
assign VAR111 = VAR109 ? VAR96 : VAR92[VAR45-1:5];
assign VAR25 = {VAR90, VAR92[VAR102-1:VAR45]};
reg VAR64;
reg [1:0] VAR91;
always @(posedge VAR95) begin
if(VAR64)
VAR91 <= VAR91 + 2'd1;
end
else
VAR91 <= 2'd0;
end
assign VAR50 = {VAR92[VAR45-1:5], VAR91};
assign VAR20 = {VAR92[VAR102-1:5], 5'd0};
reg [2:0] state;
reg [2:0] VAR29;
parameter VAR43 = 3'd0;
parameter VAR89 = 3'd1;
parameter VAR12 = 3'd2;
parameter VAR15 = 3'd3;
parameter VAR52 = 3'd4;
parameter VAR39 = 3'd5;
parameter VAR54 = 3'd6;
parameter VAR26 = 3'd7;
always @(posedge VAR95) begin
if(VAR84)
state <= VAR43;
end
else
state <= VAR29;
end
reg VAR77;
always @(*) begin
VAR29 = state;
VAR107 = 1'b0;
VAR90 = 1'b1;
VAR2 = 1'b0;
VAR64 = 1'b0;
VAR109 = 1'b0;
VAR36 = 1'b0;
VAR77 = 1'b1;
case(state)
VAR43: begin
VAR77 = 1'b0;
if(VAR34)
VAR29 = VAR89;
if(VAR30)
VAR29 = VAR26;
end
VAR89: begin
VAR36 = 1'b1;
VAR2 = 1'b1;
if(VAR38) begin
VAR64 = 1'b1;
VAR29 = VAR12;
end
end
VAR12: begin
VAR2 = 1'b1;
VAR64 = 1'b1;
VAR29 = VAR15;
end
VAR15: begin
VAR2 = 1'b1;
VAR64 = 1'b1;
VAR29 = VAR52;
end
VAR52: begin
VAR2 = 1'b1;
VAR107 = 1'b1;
VAR29 = VAR39;
end
VAR39: VAR29 = VAR54;
VAR54: VAR29 = VAR43;
VAR26: begin
VAR107 = 1'b1;
VAR90 = 1'b0;
VAR109 = 1'b1;
if(VAR93)
VAR29 = VAR43;
end
endcase
end
assign VAR3 = VAR77 | VAR1;
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha.behavioral.v | 1,511 | module MODULE1 (
VAR9,
VAR14 ,
VAR7 ,
VAR12
);
output VAR9;
output VAR14 ;
input VAR7 ;
input VAR12 ;
supply1 VAR5;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR3 ;
wire VAR1;
wire VAR4 ;
and VAR13 (VAR1, VAR7, VAR12 );
buf VAR2 (VAR9 , VAR1 );
xor VAR10 (VAR4 , VAR12, VAR7 );
buf VAR11 (VAR14 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3.pp.symbol.v | 1,295 | module MODULE1 (
input VAR1 ,
input VAR3 ,
input VAR4 ,
output VAR5 ,
input VAR8 ,
input VAR2,
input VAR7,
input VAR6
);
endmodule | apache-2.0 |
Chapna/TTCache | src/cache_ctl.v | 1,801 | module MODULE1 (enable, clk, VAR26, word, VAR10,
write, VAR17, VAR8, VAR20,
rst, VAR2, VAR13, VAR6,
VAR5, valid);
input clk;
input enable;
input [0:3] VAR26;
input [0:1] word;
input VAR10;
input write;
input [0:4] VAR17;
input [0:15] VAR8;
input VAR20;
input rst;
output reg VAR2;
output reg VAR13;
output reg [0:4] VAR6;
output reg [0:15] VAR5;
output reg valid;
reg VAR25;
reg VAR16;
reg [0:3] VAR7;
reg [0:1] VAR23;
reg VAR18;
reg VAR12;
reg [0:4] VAR11;
reg [0:15] VAR14;
reg VAR15;
wire VAR9;
wire VAR3;
wire [0:4] VAR4;
wire [0:15] VAR1;
wire VAR22;
wire VAR19;
VAR24 VAR21(VAR25, VAR7, VAR23, VAR18, VAR12, VAR11,
VAR14, VAR15, VAR16, VAR9, VAR3,
VAR4, VAR1, VAR22, VAR19);
always @ (posedge clk) begin
if (enable) begin
VAR16 = rst;
VAR23 = word;
VAR7 = VAR26;
VAR18 = VAR10;
VAR12 = write;
VAR11 = VAR17;
VAR14 = VAR8;
VAR15 = VAR20;
VAR25 = 1'b1;
wait (VAR19) begin
VAR2 = VAR9;
VAR13 = VAR3;
VAR6 = VAR4;
valid = VAR22;
VAR5 = VAR1;
end
end else begin
VAR25 = 1'b0;
end
end
always @ (negedge clk) begin
VAR25 = 1'b0;
end
endmodule | gpl-2.0 |
ptracton/pmodacl2 | behavioral/adxl362/adxl362_spi.v | 13,798 | module MODULE1 (
VAR62, address, VAR63, VAR16, write, VAR48,
VAR37, VAR64, VAR21, VAR12, VAR51, VAR10, rst
) ;
input wire VAR37;
input wire VAR64;
input wire VAR21;
output reg VAR62;
input wire VAR12;
output reg [5:0] address;
output reg [7:0] VAR63;
input wire [7:0] VAR51;
input wire [15:0] VAR10;
output reg VAR16;
output reg write;
input wire rst;
output reg VAR48;
reg [7:0] VAR27 = 0;
reg [7:0] VAR56 =0 ;
reg [2:0] VAR50 =0;
reg [2:0] VAR53 =0;
reg [7:0] VAR26 =0;
reg VAR33 = 0;
wire [7:0] VAR6;
reg VAR41 = 0;
wire VAR7 = VAR41 ; reg VAR40 =0;
wire VAR18; wire VAR1;
reg [7:0] VAR25 =0;
always @(posedge VAR37 or posedge VAR21)
if (VAR21) begin
VAR50 <= 0;
VAR53 <= 0;
VAR27 <= 0;
VAR62 <= 1'VAR57;
end else begin
VAR53 <= VAR50;
VAR50 <= VAR50 + 1;
VAR25 <= VAR25 + 1;
VAR27 <= {VAR27[6:0], VAR64};
VAR62 <= VAR56[7-VAR50];
end
wire VAR13 = (VAR50 == 0) && (VAR53 == 7);
wire VAR69 = (VAR50 == 1) && (VAR53 == 0);
reg [2:0] VAR43;
reg [2:0] VAR45;
parameter VAR28 = 3'h0;
parameter VAR8 = 3'h1;
parameter VAR22 = 3'h2;
always @(posedge VAR12) begin
VAR43 <= VAR45;
end
always @ begin
case (state)
VAR17: begin
if (VAR21) begin
VAR26 = 0;
address = 0;
VAR56 = 0;
VAR63 = 0;
write = 0;
VAR58 = 0;
VAR48 = 0;
end
if (! VAR21) begin
if (VAR13) begin
VAR26 = VAR27;
if (VAR39 == VAR26) begin
VAR56 = VAR6;
VAR46 = VAR11;
end else if ((VAR71 == VAR26) || (VAR30==VAR26)) begin
VAR46 = VAR59;
end
end
end
end
VAR59: begin
if (VAR21) begin
VAR46 = VAR17;
end else if (VAR69) begin
VAR46 = VAR4;
end else begin
VAR46 = VAR59;
end
end
VAR4: begin
if (VAR21) begin
VAR46 = VAR17;
end else if (VAR13) begin
address = VAR27;
VAR56 = VAR51;
if (VAR71 == VAR26) VAR46 = VAR49;
if (VAR30 == VAR26) VAR46 = VAR68;
end else begin
VAR46 = VAR4;
end
end
VAR49: begin
if (!VAR21) begin
if (VAR69) begin
VAR46 = VAR54;
end else begin
VAR46 = VAR49;
end
end else begin
VAR46 = VAR17;
end
end
VAR54:begin
if (VAR21) begin
VAR46 = VAR17;
end else if (VAR13) begin
VAR63 = VAR27;
VAR46 = VAR20;
end else begin
VAR46 = VAR54;
end
end
VAR20:begin
write = 1;
VAR46 = VAR14;
end
VAR14:begin
if (VAR21) begin
VAR46 = VAR17;
end else begin
write = 0;
VAR58 = 1;
VAR46 = VAR36;
end
end
VAR36: begin
if (VAR21) begin
VAR46 = VAR17;
end else begin
if (VAR58) begin
address = address + 1;
VAR58 = 0;
end
VAR46 = VAR49;
end
end
VAR68:begin
if (! VAR21) begin
VAR56 = VAR51; if (VAR69) begin
VAR46 = VAR31;
end else begin
VAR46 = VAR68;
end
end else begin
VAR46 = VAR17;
end
end
VAR31: begin
if (!VAR21) begin
if (VAR13) begin
VAR58 = 1;
VAR46 = VAR9;
end else begin
VAR46 = VAR31;
end
end else begin
VAR46 = VAR17;
end
end
VAR9: begin
if (VAR21) begin
VAR46 = VAR17;
end else begin
if (VAR58) begin
address = address + 1;
VAR58 = 0;
end
VAR46 = VAR68;
end
end
VAR11: begin
if (VAR21) begin
VAR46 = VAR17;
end else begin
VAR48 = 0;
VAR56 = VAR10[7:0];
VAR46 = VAR5;
end
end
VAR5: begin
if (VAR21) begin
VAR46 = VAR17;
end else begin
if (VAR69) begin
VAR46 = VAR32;
end else begin
VAR46 = VAR5;
end
end
end
VAR32:begin
if (VAR21) begin
VAR46 = VAR17;
end else if (VAR13) begin
VAR46 = VAR70;
end else begin
VAR46 = VAR32;
end
end
VAR70:begin
if (VAR21) begin
VAR46 = VAR17;
end else begin
VAR48 = 0;
VAR56 = VAR10[15:08];
VAR46 = VAR47;
end
end
VAR47: begin
if (VAR21) begin
VAR46 = VAR17;
end else if (VAR69) begin
VAR46 = VAR44;
end else begin
VAR46 = VAR47;
end
end
VAR44:begin
if (VAR21) begin
VAR46 = VAR17;
end else if (VAR13) begin
VAR46 = VAR35;
end else begin
VAR46 = VAR44;
end
end
VAR35:begin
if (VAR21) begin
VAR46 = VAR17;
end else begin
VAR48 = 1;
VAR46 = VAR11;
end
end
default: begin
VAR46 = VAR17;
end
endcase
end
reg [(40*8)-1:0] VAR34 =0;
always @(*)
case (state)
VAR17: VAR34 = "VAR23";
VAR11: VAR34 = "VAR2 VAR60 VAR38 VAR52";
VAR59 : VAR34 = "VAR55 VAR2 VAR61";
VAR4 : VAR34 = "VAR38 VAR61";
VAR49: VAR34 = "VAR55 VAR2 VAR3";
VAR68 : VAR34 = "VAR55 VAR2 VAR38";
VAR54 : VAR34 = "VAR38 VAR3";
VAR20 : VAR34 = "VAR42 VAR24";
VAR14 : VAR34 = "VAR42 VAR24 VAR67";
VAR36 : VAR34 = "VAR42 VAR19 VAR61";
VAR31: VAR34 = "VAR67 VAR38 VAR66";
VAR9: VAR34 = "VAR38 VAR19 VAR61";
VAR5: VAR34 = "VAR2 VAR60 VAR66 VAR52";
VAR32 : VAR34 = "VAR55 VAR67 VAR60 VAR66 VAR52";
VAR47: VAR34 = "VAR2 VAR60 VAR66 VAR29";
VAR44 : VAR34 = "VAR55 VAR67 VAR60 VAR66 VAR29";
VAR35: VAR34 = "VAR65 VAR60";
default: VAR34 = "VAR15!";
endcase
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.v | 2,444 | module MODULE2 (
VAR2,
VAR4 ,
VAR8 ,
VAR10 ,
VAR6 ,
VAR7 ,
VAR5 ,
VAR1
);
input VAR2;
input VAR4 ;
input VAR8 ;
output VAR10 ;
input VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR1 ;
VAR9 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR2,
VAR4 ,
VAR8 ,
VAR10 ,
VAR6 ,
VAR7
);
input VAR2;
input VAR4 ;
input VAR8 ;
output VAR10 ;
input VAR6 ;
input VAR7 ;
supply1 VAR5;
supply0 VAR1;
VAR9 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule | apache-2.0 |
bunnie/novena-sd-fpga | novena-sd.srcs/sources_1/imports/romulator_ddr3.v | 36,309 | module MODULE1(
input wire clk,
input wire VAR61,
input wire VAR4,
input wire VAR64,
input wire VAR134,
output wire VAR46,
input wire VAR127,
input wire VAR87,
input wire [7:0] VAR122,
output wire [7:0] VAR103,
output wire VAR73,
input wire VAR114,
output wire VAR93,
output wire VAR31,
output reg VAR31,
output wire [2:0] VAR5,
output wire [5:0] VAR28,
output reg [29:0] VAR2,
input wire VAR27,
input wire VAR38,
output reg VAR124,
output wire [31:0] VAR107,
input wire VAR67,
input wire VAR26,
output reg [3:0] VAR7,
output wire VAR132,
output reg VAR106,
output wire [2:0] VAR77,
output wire [5:0] VAR84,
output wire [29:0] VAR29,
input wire VAR1,
output reg VAR63,
input wire [31:0] VAR68,
input wire VAR79,
input wire [6:0] VAR23,
input wire VAR112,
input wire VAR25,
output reg VAR97,
output reg VAR137,
output wire [7:0] VAR30,
output reg VAR60,
output wire [7:0] VAR129,
output reg VAR130,
output wire [29:0] VAR142,
output wire VAR34,
output wire [3:0] VAR16,
input wire reset
);
wire VAR85;
VAR141 VAR22( .VAR135(reset), .clk(clk), .reset(VAR85) );
wire VAR48;
VAR141 VAR56( .VAR135(VAR114), .clk(clk), .reset(VAR48) );
assign VAR93 = clk;
assign VAR132 = clk;
reg VAR71;
reg VAR105;
reg [11:0] VAR6;
reg [17:0] VAR113;
assign VAR142 = {VAR113, VAR6};
wire VAR115;
wire [29:0] VAR65;
assign VAR65[29:0] = (VAR113[17:0] * 12'd2112) + VAR6;
assign VAR115 = VAR113[17:0] >= 18'h1D174;
parameter VAR14 = 13'b1 << 0;
parameter VAR18 = 13'b1 << 1;
parameter VAR19 = 13'b1 << 2;
parameter VAR140 = 13'b1 << 3;
parameter VAR70 = 13'b1 << 4;
parameter VAR69 = 13'b1 << 5;
parameter VAR116 = 13'b1 << 6;
parameter VAR121 = 13'b1 << 7;
parameter VAR80 = 13'b1 << 8;
parameter VAR45 = 13'b1 << 9;
parameter VAR17 = 13'b1 << 10;
parameter VAR62 = 13'b1 << 11;
parameter VAR53 = 13'b1 << 12;
parameter VAR100 = 13;
reg [(VAR100 - 1):0] VAR94;
reg [(VAR100 - 1):0] VAR41;
parameter VAR102 = 8'h90;
parameter VAR37 = 8'h00;
parameter VAR21 = 8'h30;
parameter VAR108 = 8'h35;
parameter VAR89 = 8'hFF;
parameter VAR81 = 8'h05;
parameter VAR125 = 8'hE0;
parameter VAR20 = 8'h70;
parameter VAR138 = 8'h80;
parameter VAR9 = 8'h10;
parameter VAR82 = 8'h60;
parameter VAR76= 8'hD0;
reg VAR104; reg VAR109;
reg VAR66;
reg [7:0] VAR33;
reg [7:0] VAR126;
assign VAR30 = VAR33;
assign VAR129 = VAR126;
always @(posedge clk) begin
VAR130 <= !(VAR134 & !VAR61);
end
always @(posedge VAR61 or posedge VAR85) begin
if(VAR85) begin
VAR94 <= VAR14;
end else begin
VAR94 <= VAR41;
end
end
always @ reg VAR43, VAR36, VAR120;
reg VAR12, VAR8;
reg VAR72, VAR75;
reg VAR11, VAR39;
reg [12:0] VAR55;
reg VAR86;
always @(posedge clk) begin
VAR43 <= VAR104;
VAR12 <= VAR43;
VAR36 <= VAR109;
VAR72 <= VAR36;
VAR120 <= VAR66;
VAR11 <= VAR120;
if( !VAR12 && VAR43 ) begin
VAR8 <= 1'b1;
end else begin
VAR8 <= 1'b0;
end
if( !VAR72 && VAR36 ) begin
VAR75 <= 1'b1;
end else begin
VAR75 <= 1'b0;
end
if( !VAR11 && VAR120 ) begin
VAR39 <= 1'b1;
end else begin
VAR39 <= 1'b0;
end
if( VAR85 ) begin
VAR55 <= 12'b0;
VAR86 <= 1'b0;
end else begin
if( (VAR75 || VAR8) && (VAR55 == 12'b0) ) begin
VAR55 <= VAR55 + 12'b1;
VAR86 <= 1'b1;
end else if( VAR55 == 12'h200 ) begin VAR55 <= 12'h0;
VAR86 <= 1'b0;
end else if( VAR86 == 1'b1 ) begin
VAR55 <= VAR55 + 12'b1;
VAR86 <= 1'b1;
end else begin
VAR55 <= 12'h0;
VAR86 <= 1'b0;
end
end end
parameter VAR78 = 4'b1 << 0;
parameter VAR32 = 4'b1 << 1;
parameter VAR95 = 4'b1 << 2;
parameter VAR59 = 4'b1 << 3;
parameter VAR88 = 4;
reg [(VAR88 - 1):0] VAR47;
reg [(VAR88 - 1):0] VAR15;
reg [(VAR88 - 1):0] VAR92;
reg [11:0] VAR99;
reg [11:0] VAR40; reg [6:0] VAR52; reg [4:0] VAR74;
reg [11:0] VAR133;
reg [19:0] VAR131;
assign VAR16 = VAR47;
assign VAR46 = !(VAR47 != VAR78);
always @(posedge clk) begin
VAR92 <= VAR47;
if(VAR48) begin
VAR47 <= VAR78;
end else begin
VAR47 <= VAR15;
end
end
always @(*) begin
case(VAR47)
VAR78: begin
if( VAR75 ) begin
VAR15 <= VAR32;
end else if( VAR8 ) begin
VAR15 <= VAR95;
end else if( VAR39 ) begin
VAR15 <= VAR59;
end else begin
VAR15 <= VAR78;
end
end
VAR32: begin
if( ((VAR40 >= 12'd511) && (VAR40 < 12'hFF0))
&& (VAR52 == 7'd0) ) begin
VAR15 <= VAR78;
end else begin
VAR15 <= VAR32;
end
end
VAR95: begin
if( (VAR52 >= 7'd33) && VAR26 ) begin
VAR15 <= VAR78;
end else begin
VAR15 <= VAR95;
end
if( VAR133[11:0] == VAR44[11:0] ) begin
VAR15 <= VAR78;
end else begin
VAR15 <= VAR95;
end
if( (VAR131[19:0] >= 20'h107FF) && (VAR131[19:0] != 20'hFFFFF) ) begin
VAR15 <= VAR78;
end else begin
VAR15 <= VAR59;
end
end
endcase end
assign VAR29[29:0] = (VAR113[17:0] * 30'd2112) + (VAR40[11:0] * 30'd4);
assign VAR77 = 3'b001;
assign VAR84 = 6'd15;
assign VAR31 = VAR105;
reg [17:0] VAR49; reg [17:0] VAR54;
always @(posedge clk) begin
VAR49 <= VAR3[17:0] * 30'd2112; VAR54 <= VAR90[17:0] * 30'd2112;
VAR2[29:0] <= (VAR47 == VAR59) ?
(VAR49) +
(VAR131[19:0] * 12'd4)
:
(VAR54) +
(VAR52[6:0] * 12'd16 + (VAR74[4:0] - 5'b1)) * 30'd4 ;
VAR124 <= VAR71;
end
reg [17:0] VAR49; reg [17:0] VAR54;
always @(posedge clk) begin
VAR49 <= VAR3[17:0] * 30'd2112; VAR54 <= VAR90[17:0] * 30'd2112;
VAR124 <= VAR71;
VAR31 <= VAR105;
VAR2[29:0] <= (VAR47 == VAR59) ?
(VAR49[17:0]) +
(VAR131[19:0] * 12'd4)
:
(VAR54[17:0]) +
{VAR133[11:2], 2'b0};
if( VAR47 == VAR59 ) begin
VAR7[3:0] <= 4'b0;
end else begin
case(VAR133[1:0])
2'b00: begin
VAR7[3:0] <= 4'b1110;
end
2'b01: begin
VAR7[3:0] <= 4'b1101;
end
2'b10: begin
VAR7[3:0] <= 4'b1011;
end
2'b11: begin
VAR7[3:0] <= 4'b0111;
end
endcase end end
assign VAR5 = 3'b000;
end
assign VAR28 = 6'd15; else
assign VAR28 = (VAR47 == VAR59) ? 6'd0 : 6'd0;
always @(posedge clk) begin
case(VAR47)
VAR78: begin
VAR71 <= 1'b0;
VAR74 <= 5'h0;
VAR99 <= 12'hFFF;
VAR40 <= 12'hFF0; VAR52 <= 7'b0;
if( !VAR79 ) begin
VAR63 <= 1'b1; end else begin
VAR63 <= 1'b0;
end
VAR97 <= 1'b0;
VAR137 <= 1'b0;
VAR105 <= 1'b0;
VAR133 <= VAR50;
VAR131 <= 20'hFFFFF; end
VAR32: begin
VAR131 <= 20'hFFFFF;
VAR133 <= VAR50;
VAR71 <= 1'b0;
VAR105 <= 1'b0;
VAR74 <= 5'h0;
if( ((VAR40 < 12'd511) || (VAR40 >= 12'hFF0)) && !VAR1 &&
(VAR52 < 7'd47) && VAR79) begin
VAR106 <= 1'b1;
VAR40 <= VAR40 + 12'd16; VAR52 <= VAR52 + 7'd16;
VAR63 <= 1'b0;
VAR99 <= VAR99;
VAR97 <= 1'b0;
VAR137 <= 1'b0;
end else if (((VAR40 < 12'd511) || (VAR40 >= 12'hFF0)) &&
!VAR1 &&
(VAR52 < 7'd47) && !VAR79) begin
VAR106 <= 1'b1;
VAR40 <= VAR40 + 12'd16;
VAR52 <= VAR52 + 7'd15; VAR63 <= 1'b1;
if( (VAR99 < 12'd2112) || (VAR99 == 12'hFFF) ) begin
VAR99 <= VAR99 + 12'b1;
VAR97 <= 1'b0;
end else begin
VAR99 <= VAR99;
VAR97 <= 1'b1;
end
VAR137 <= 1'b0;
end else if( !VAR79 ) begin
VAR106 <= 1'b0;
VAR40 <= VAR40;
if( VAR52 > 7'b0 ) begin
VAR52 <= VAR52 - 7'b1;
VAR137 <= 1'b0;
end else begin
VAR52 <= 12'b0; VAR137 <= 1'b1;
end
VAR63 <= 1'b1;
if( (VAR99 < 12'd2112) || (VAR99 == 12'hFFF) ) begin
VAR99 <= VAR99 + 12'b1;
VAR97 <= 1'b0;
end else begin
VAR99 <= VAR99;
VAR97 <= 1'b1;
end
end else begin
VAR106 <= 1'b0;
VAR40 <= VAR40;
VAR52 <= VAR52;
VAR63 <= 1'b0;
VAR99 <= VAR99;
VAR97 <= 1'b0;
VAR137 <= 1'b0;
end
end
VAR95: begin
if( VAR52 < 7'd33 ) begin
if( ((VAR74 == 5'h0) && !VAR26) || VAR27 ) begin
VAR71 <= 1'b0;
VAR52 <= VAR52;
VAR74 <= VAR74;
VAR105 <= 1'b0;
end else if( (VAR74 == 5'h0) && VAR26 ) begin
VAR71 <= 1'b1;
VAR74 <= VAR74 + 5'h1;
VAR52 <= VAR52;
VAR105 <= 1'b0;
end else if(VAR74 < 5'd16) begin
VAR71 <= 1'b1;
VAR74 <= VAR74 + 5'h1;
VAR52 <= VAR52;
VAR105 <= 1'b0;
end else begin
VAR74 <= 5'h0;
VAR71 <= 1'b0;
VAR52 <= VAR52 + 7'b1;
VAR105 <= 1'b1;
end end else begin VAR71 <= 1'b0;
VAR52 <= VAR52;
VAR74 <= VAR74;
VAR105 <= 1'b0;
end
end else VAR52 <= VAR52;
if( ((VAR133 < VAR44) || (VAR133 == 12'hFFF)) && VAR38 ) begin
VAR71 <= 1'b1;
VAR105 <= 1'b1;
VAR133 <= VAR133 + 12'b1;
end else begin
VAR105 <= 1'b0;
VAR71 <= 1'b0;
VAR133 <= VAR133;
end
VAR40 <= 12'b0;
VAR63 <= 1'b0;
VAR97 <= 1'b0;
VAR137 <= 1'b0;
VAR131 <= 20'hFFFFF;
end VAR59: begin
if( VAR38 &&
((VAR131 < 20'h107FF) || (VAR131 == 20'hFFFFF)) ) begin
VAR131 <= VAR131 + 20'd1;
VAR71 <= 1'b1;
VAR105 <= 1'b1;
end else begin
VAR105 <= 1'b0;
VAR71 <= 1'b0;
VAR131 <= VAR131;
end
VAR52 <= VAR52;
VAR74 <= 5'h0;
VAR99 <= 12'hFFF;
VAR40 <= 12'hFF0;
VAR63 <= 1'b0;
VAR97 <= 1'b0;
VAR137 <= 1'b0;
VAR133 <= VAR50;
end endcase end
reg VAR83;
reg VAR98;
reg VAR110;
always @(posedge clk) begin
VAR83 <= VAR24 & VAR61;
VAR98 <= VAR83;
VAR110 <= !VAR98 & VAR83;
end
wire [31:0] VAR123;
assign VAR107[31:0] = ( VAR92 == VAR59 ) ?
32'hFFFFFFFF
:
VAR123[31:0];
VAR118 VAR13(
.VAR10(clk),
.VAR42(1'b1),
.VAR139(VAR63 && (VAR47 == VAR32)),
.VAR119(( VAR47 == VAR32) ? VAR99[9:0] :
VAR52[6:0] * 10'd16 + (VAR74[4:0] - 5'b1) ),
.VAR119(( VAR47 == VAR32) ? VAR99[9:0] :
VAR133[11:2] ),
.VAR136(VAR68[31:0]),
.VAR57(VAR123[31:0]),
.VAR35(clk),
.VAR117(1'b1),
.VAR96(VAR110 && (VAR47 == VAR78)),
.VAR51(VAR24 ? VAR101[11:0] : VAR6[11:0]),
.VAR128(VAR58[7:0]),
.VAR111(VAR91[7:0])
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_16/bsg_async/bsg_sync_sync.v | 3,615 | \
module MODULE2 \
(input VAR11 \
,input [VAR2-1:0] VAR19 \
,output [VAR2-1:0] VAR5 ); \
\
genvar VAR17; \
\
logic [VAR2-1:0] VAR12; \
\
assign VAR5 = VAR12; \
\
for (VAR17 = 0; VAR17 < VAR2; VAR17 = VAR17 + 1) \
begin : VAR4 \
VAR8 VAR6 \
(.VAR1 (VAR19[VAR17]) \
,.VAR15 (VAR11) \
,.VAR22 (1'b0) \
,.VAR14 (1'b0) \
,.VAR13 (VAR12[VAR17]) \
); \
end \
\
endmodule
VAR16 VAR18 \
(.VAR11 \
,.VAR19(VAR19[VAR2-1-:VAR3]) \
,.VAR5(VAR5[VAR2-1-:VAR3]) \
); end
module MODULE1 #(parameter VAR9(VAR2 ))
(
input VAR11
, input [VAR2-1:0] VAR19
, output [VAR2-1:0] VAR5 );
genvar VAR17;
for (VAR17 = 0; VAR17 < (VAR2/VAR20); VAR17 = VAR17 + 1)
begin : VAR7
VAR10 VAR21
(.VAR11
,.VAR19(VAR19[VAR17*VAR20+:VAR20])
,.VAR5(VAR5[VAR17*VAR20+:VAR20])
);
end
endmodule | bsd-3-clause |
marmolejo/zet | cores/ps2/rtl/ps2_mouse_datain.v | 5,048 | module MODULE1 (
input clk,
input reset,
input VAR14,
input VAR13,
input VAR10,
input VAR2,
input VAR9,
output reg [7:0] VAR12,
output reg VAR11 );
localparam VAR1 = 3'h0,
VAR15 = 3'h1,
VAR4 = 3'h2,
VAR16 = 3'h3,
VAR7 = 3'h4;
reg [3:0] VAR5;
reg [7:0] VAR6;
reg [2:0] VAR8;
reg [2:0] VAR3;
always @(posedge clk) begin
if (reset == 1'b1) VAR3 <= VAR1;
end
else VAR3 <= VAR8;
end
always @(*) begin VAR8 = VAR1;
case (VAR3)
VAR1:
begin
if((VAR14 == 1'b1) && (VAR11 == 1'b0))
VAR8 = VAR15;
end
else if ((VAR13 == 1'b1) && (VAR11 == 1'b0))
VAR8 = VAR4;
end
else VAR8 = VAR1;
end
VAR15:
begin
if((VAR9 == 1'b0) && (VAR10 == 1'b1))
VAR8 = VAR4;
end
else if (VAR14 == 1'b0)
VAR8 = VAR1;
else
VAR8 = VAR15;
end
VAR4:
begin
if((VAR5 == 3'h7) && (VAR10 == 1'b1))
VAR8 = VAR16;
end
else
VAR8 = VAR4;
end
VAR16:
begin
if (VAR10 == 1'b1)
VAR8 = VAR7;
end
else
VAR8 = VAR16;
end
VAR7:
begin
if (VAR10 == 1'b1)
VAR8 = VAR1;
end
else
VAR8 = VAR7;
end
default:
begin
VAR8 = VAR1;
end
endcase
end
always @(posedge clk) begin
if (reset == 1'b1) VAR5 <= 3'h0;
end
else if((VAR3 == VAR4) && (VAR10 == 1'b1))
VAR5 <= VAR5 + 3'h1;
else if(VAR3 != VAR4)
VAR5 <= 3'h0;
end
always @(posedge clk) begin
if(reset == 1'b1) VAR6 <= 8'h00;
end
else if((VAR3 == VAR4) && (VAR10 == 1'b1))
VAR6 <= {VAR9, VAR6[7:1]};
end
always @(posedge clk) begin
if(reset == 1'b1) VAR12 <= 8'h00;
end
else if(VAR3 == VAR7)
VAR12 <= VAR6;
end
always @(posedge clk) begin
if(reset == 1'b1) VAR11 <= 1'b0;
end
else if((VAR3 == VAR7) && (VAR10 == 1'b1))
VAR11 <= 1'b1;
else
VAR11 <= 1'b0;
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fah/sky130_fd_sc_ls__fah.blackbox.v | 1,297 | module MODULE1 (
VAR4,
VAR5 ,
VAR7 ,
VAR1 ,
VAR2
);
output VAR4;
output VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR2 ;
supply1 VAR8;
supply0 VAR9;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/verilog/ANN_dadd_64ns_64ns_64_5_full_dsp.v | 1,912 | module MODULE1
VAR6 = 7,
VAR18 = 5,
VAR25 = 64,
VAR2 = 64,
VAR1 = 64
)(
input wire clk,
input wire reset,
input wire VAR24,
input wire [VAR25-1:0] VAR10,
input wire [VAR2-1:0] VAR4,
output wire [VAR1-1:0] dout
);
wire VAR27;
wire VAR21;
wire VAR20;
wire [63:0] VAR5;
wire VAR7;
wire [63:0] VAR13;
wire VAR12;
wire [63:0] VAR17;
reg [VAR25-1:0] VAR26;
reg [VAR2-1:0] VAR23;
VAR3 VAR11 (
.VAR27 ( VAR27 ),
.VAR21 ( VAR21 ),
.VAR8 ( VAR20 ),
.VAR9 ( VAR5 ),
.VAR22 ( VAR7 ),
.VAR15 ( VAR13 ),
.VAR14 ( VAR12 ),
.VAR16 ( VAR17 )
);
assign VAR27 = clk;
assign VAR21 = VAR24;
assign VAR20 = 1'b1;
assign VAR5 = VAR26==='VAR19 ? 'b0 : VAR26;
assign VAR7 = 1'b1;
assign VAR13 = VAR23==='VAR19 ? 'b0 : VAR23;
assign dout = VAR17;
always @(posedge clk) begin
if (VAR24) begin
VAR26 <= VAR10;
VAR23 <= VAR4;
end
end
endmodule | gpl-3.0 |
disaderp/automatic-chainsaw | GPU/Font_ROM.v | 132,545 | module MODULE1(
input clk,
input [11:0] address,
output reg [7:0] out);
reg [7:0] MODULE1 [4095:0];
VAR1 begin : VAR2
MODULE1[0] <= 8'b00000000;
MODULE1[1] <= 8'b00000000;
MODULE1[2] <= 8'b00000000;
MODULE1[3] <= 8'b00000000;
MODULE1[4] <= 8'b00000000;
MODULE1[5] <= 8'b00000000;
MODULE1[6] <= 8'b00000000;
MODULE1[7] <= 8'b00000000;
MODULE1[8] <= 8'b00000000;
MODULE1[9] <= 8'b00000000;
MODULE1[10] <= 8'b00000000;
MODULE1[11] <= 8'b00000000;
MODULE1[12] <= 8'b00000000;
MODULE1[13] <= 8'b00000000;
MODULE1[14] <= 8'b00000000;
MODULE1[15] <= 8'b00000000;
MODULE1[16] <= 8'b00000000;
MODULE1[17] <= 8'b00000000;
MODULE1[18] <= 8'b00000000;
MODULE1[19] <= 8'b00000000;
MODULE1[20] <= 8'b00000000;
MODULE1[21] <= 8'b00000000;
MODULE1[22] <= 8'b00000000;
MODULE1[23] <= 8'b00000000;
MODULE1[24] <= 8'b00000000;
MODULE1[25] <= 8'b00000000;
MODULE1[26] <= 8'b00000000;
MODULE1[27] <= 8'b00000000;
MODULE1[28] <= 8'b00000000;
MODULE1[29] <= 8'b00000000;
MODULE1[30] <= 8'b00000000;
MODULE1[31] <= 8'b00000000;
MODULE1[32] <= 8'b00000000;
MODULE1[33] <= 8'b00000000;
MODULE1[34] <= 8'b00000000;
MODULE1[35] <= 8'b00000000;
MODULE1[36] <= 8'b00000000;
MODULE1[37] <= 8'b00000000;
MODULE1[38] <= 8'b00000000;
MODULE1[39] <= 8'b00000000;
MODULE1[40] <= 8'b00000000;
MODULE1[41] <= 8'b00000000;
MODULE1[42] <= 8'b00000000;
MODULE1[43] <= 8'b00000000;
MODULE1[44] <= 8'b00000000;
MODULE1[45] <= 8'b00000000;
MODULE1[46] <= 8'b00000000;
MODULE1[47] <= 8'b00000000;
MODULE1[48] <= 8'b00000000;
MODULE1[49] <= 8'b00000000;
MODULE1[50] <= 8'b00000000;
MODULE1[51] <= 8'b00000000;
MODULE1[52] <= 8'b00000000;
MODULE1[53] <= 8'b00000000;
MODULE1[54] <= 8'b00000000;
MODULE1[55] <= 8'b00000000;
MODULE1[56] <= 8'b00000000;
MODULE1[57] <= 8'b00000000;
MODULE1[58] <= 8'b00000000;
MODULE1[59] <= 8'b00000000;
MODULE1[60] <= 8'b00000000;
MODULE1[61] <= 8'b00000000;
MODULE1[62] <= 8'b00000000;
MODULE1[63] <= 8'b00000000;
MODULE1[64] <= 8'b00000000;
MODULE1[65] <= 8'b00000000;
MODULE1[66] <= 8'b00000000;
MODULE1[67] <= 8'b00000000;
MODULE1[68] <= 8'b00000000;
MODULE1[69] <= 8'b00000000;
MODULE1[70] <= 8'b00000000;
MODULE1[71] <= 8'b00000000;
MODULE1[72] <= 8'b00000000;
MODULE1[73] <= 8'b00000000;
MODULE1[74] <= 8'b00000000;
MODULE1[75] <= 8'b00000000;
MODULE1[76] <= 8'b00000000;
MODULE1[77] <= 8'b00000000;
MODULE1[78] <= 8'b00000000;
MODULE1[79] <= 8'b00000000;
MODULE1[80] <= 8'b00000000;
MODULE1[81] <= 8'b00000000;
MODULE1[82] <= 8'b00000000;
MODULE1[83] <= 8'b00000000;
MODULE1[84] <= 8'b00000111;
MODULE1[85] <= 8'b10000000;
MODULE1[86] <= 8'b00000000;
MODULE1[87] <= 8'b10000000;
MODULE1[88] <= 8'b00000000;
MODULE1[89] <= 8'b10000000;
MODULE1[90] <= 8'b00000000;
MODULE1[91] <= 8'b10000000;
MODULE1[92] <= 8'b00000000;
MODULE1[93] <= 8'b10000000;
MODULE1[94] <= 8'b00000000;
MODULE1[95] <= 8'b10000000;
MODULE1[96] <= 8'b00000000;
MODULE1[97] <= 8'b00000000;
MODULE1[98] <= 8'b00000000;
MODULE1[99] <= 8'b00000000;
MODULE1[100] <= 8'b00000000;
MODULE1[101] <= 8'b00000000;
MODULE1[102] <= 8'b00000000;
MODULE1[103] <= 8'b00000000;
MODULE1[104] <= 8'b00000000;
MODULE1[105] <= 8'b10000000;
MODULE1[106] <= 8'b00000000;
MODULE1[107] <= 8'b10000000;
MODULE1[108] <= 8'b00000000;
MODULE1[109] <= 8'b10000000;
MODULE1[110] <= 8'b00000000;
MODULE1[111] <= 8'b10000000;
MODULE1[112] <= 8'b00000000;
MODULE1[113] <= 8'b10000000;
MODULE1[114] <= 8'b00000000;
MODULE1[115] <= 8'b10000000;
MODULE1[116] <= 8'b00000000;
MODULE1[117] <= 8'b11100000;
MODULE1[118] <= 8'b00000000;
MODULE1[119] <= 8'b00000000;
MODULE1[120] <= 8'b00000000;
MODULE1[121] <= 8'b00000000;
MODULE1[122] <= 8'b00000000;
MODULE1[123] <= 8'b00000000;
MODULE1[124] <= 8'b00000000;
MODULE1[125] <= 8'b00000000;
MODULE1[126] <= 8'b00000000;
MODULE1[127] <= 8'b00000000;
MODULE1[128] <= 8'b00000000;
MODULE1[129] <= 8'b00000000;
MODULE1[130] <= 8'b00000000;
MODULE1[131] <= 8'b00000000;
MODULE1[132] <= 8'b00000000;
MODULE1[133] <= 8'b00000000;
MODULE1[134] <= 8'b00000000;
MODULE1[135] <= 8'b00000000;
MODULE1[136] <= 8'b00000000;
MODULE1[137] <= 8'b10000000;
MODULE1[138] <= 8'b00000000;
MODULE1[139] <= 8'b10000000;
MODULE1[140] <= 8'b00000000;
MODULE1[141] <= 8'b10000000;
MODULE1[142] <= 8'b00000000;
MODULE1[143] <= 8'b10000000;
MODULE1[144] <= 8'b00000000;
MODULE1[145] <= 8'b10000000;
MODULE1[146] <= 8'b00000000;
MODULE1[147] <= 8'b10000000;
MODULE1[148] <= 8'b00000111;
MODULE1[149] <= 8'b10000000;
MODULE1[150] <= 8'b00000000;
MODULE1[151] <= 8'b00000000;
MODULE1[152] <= 8'b00000000;
MODULE1[153] <= 8'b00000000;
MODULE1[154] <= 8'b00000000;
MODULE1[155] <= 8'b00000000;
MODULE1[156] <= 8'b00000000;
MODULE1[157] <= 8'b00000000;
MODULE1[158] <= 8'b00000000;
MODULE1[159] <= 8'b00000000;
MODULE1[160] <= 8'b00000000;
MODULE1[161] <= 8'b00000000;
MODULE1[162] <= 8'b00000000;
MODULE1[163] <= 8'b00000000;
MODULE1[164] <= 8'b00000000;
MODULE1[165] <= 8'b00000000;
MODULE1[166] <= 8'b00000000;
MODULE1[167] <= 8'b00000000;
MODULE1[168] <= 8'b00000000;
MODULE1[169] <= 8'b10000000;
MODULE1[170] <= 8'b00000000;
MODULE1[171] <= 8'b10000000;
MODULE1[172] <= 8'b00000000;
MODULE1[173] <= 8'b10000000;
MODULE1[174] <= 8'b00000000;
MODULE1[175] <= 8'b10000000;
MODULE1[176] <= 8'b00000000;
MODULE1[177] <= 8'b10000000;
MODULE1[178] <= 8'b00000000;
MODULE1[179] <= 8'b10000000;
MODULE1[180] <= 8'b00000000;
MODULE1[181] <= 8'b10000000;
MODULE1[182] <= 8'b00000000;
MODULE1[183] <= 8'b10000000;
MODULE1[184] <= 8'b00000000;
MODULE1[185] <= 8'b10000000;
MODULE1[186] <= 8'b00000000;
MODULE1[187] <= 8'b10000000;
MODULE1[188] <= 8'b00000000;
MODULE1[189] <= 8'b10000000;
MODULE1[190] <= 8'b00000000;
MODULE1[191] <= 8'b10000000;
MODULE1[192] <= 8'b00000000;
MODULE1[193] <= 8'b00000000;
MODULE1[194] <= 8'b00000000;
MODULE1[195] <= 8'b00000000;
MODULE1[196] <= 8'b00000000;
MODULE1[197] <= 8'b00000000;
MODULE1[198] <= 8'b00000000;
MODULE1[199] <= 8'b00000000;
MODULE1[200] <= 8'b00000000;
MODULE1[201] <= 8'b00000000;
MODULE1[202] <= 8'b00000000;
MODULE1[203] <= 8'b00000000;
MODULE1[204] <= 8'b00000000;
MODULE1[205] <= 8'b00000000;
MODULE1[206] <= 8'b00000000;
MODULE1[207] <= 8'b00000000;
MODULE1[208] <= 8'b00000000;
MODULE1[209] <= 8'b00000000;
MODULE1[210] <= 8'b00000000;
MODULE1[211] <= 8'b00000000;
MODULE1[212] <= 8'b00000111;
MODULE1[213] <= 8'b11100000;
MODULE1[214] <= 8'b00000000;
MODULE1[215] <= 8'b00000000;
MODULE1[216] <= 8'b00000000;
MODULE1[217] <= 8'b00000000;
MODULE1[218] <= 8'b00000000;
MODULE1[219] <= 8'b00000000;
MODULE1[220] <= 8'b00000000;
MODULE1[221] <= 8'b00000000;
MODULE1[222] <= 8'b00000000;
MODULE1[223] <= 8'b00000000;
MODULE1[224] <= 8'b00000000;
MODULE1[225] <= 8'b00000000;
MODULE1[226] <= 8'b00000000;
MODULE1[227] <= 8'b00000000;
MODULE1[228] <= 8'b00000000;
MODULE1[229] <= 8'b00000000;
MODULE1[230] <= 8'b00000000;
MODULE1[231] <= 8'b00000000;
MODULE1[232] <= 8'b00000000;
MODULE1[233] <= 8'b00000000;
MODULE1[234] <= 8'b00000000;
MODULE1[235] <= 8'b00000000;
MODULE1[236] <= 8'b00000000;
MODULE1[237] <= 8'b00000000;
MODULE1[238] <= 8'b00000001;
MODULE1[239] <= 8'b10000000;
MODULE1[240] <= 8'b00000011;
MODULE1[241] <= 8'b11000000;
MODULE1[242] <= 8'b00000011;
MODULE1[243] <= 8'b11000000;
MODULE1[244] <= 8'b00000011;
MODULE1[245] <= 8'b11000000;
MODULE1[246] <= 8'b00000001;
MODULE1[247] <= 8'b10000000;
MODULE1[248] <= 8'b00000000;
MODULE1[249] <= 8'b00000000;
MODULE1[250] <= 8'b00000000;
MODULE1[251] <= 8'b00000000;
MODULE1[252] <= 8'b00000000;
MODULE1[253] <= 8'b00000000;
MODULE1[254] <= 8'b00000000;
MODULE1[255] <= 8'b00000000;
MODULE1[256] <= 8'b00000000;
MODULE1[257] <= 8'b00000000;
MODULE1[258] <= 8'b00000000;
MODULE1[259] <= 8'b00000000;
MODULE1[260] <= 8'b00000000;
MODULE1[261] <= 8'b00000000;
MODULE1[262] <= 8'b00000000;
MODULE1[263] <= 8'b00000000;
MODULE1[264] <= 8'b00000111;
MODULE1[265] <= 8'b11100000;
MODULE1[266] <= 8'b00000111;
MODULE1[267] <= 8'b11100000;
MODULE1[268] <= 8'b00000111;
MODULE1[269] <= 8'b11100000;
MODULE1[270] <= 8'b00000110;
MODULE1[271] <= 8'b01100000;
MODULE1[272] <= 8'b00000100;
MODULE1[273] <= 8'b00100000;
MODULE1[274] <= 8'b00000100;
MODULE1[275] <= 8'b00100000;
MODULE1[276] <= 8'b00000100;
MODULE1[277] <= 8'b00100000;
MODULE1[278] <= 8'b00000110;
MODULE1[279] <= 8'b01100000;
MODULE1[280] <= 8'b00000111;
MODULE1[281] <= 8'b11100000;
MODULE1[282] <= 8'b00000111;
MODULE1[283] <= 8'b11100000;
MODULE1[284] <= 8'b00000111;
MODULE1[285] <= 8'b11100000;
MODULE1[286] <= 8'b00000111;
MODULE1[287] <= 8'b11100000;
MODULE1[288] <= 8'b00000000;
MODULE1[289] <= 8'b00000000;
MODULE1[290] <= 8'b00000000;
MODULE1[291] <= 8'b00000000;
MODULE1[292] <= 8'b00000000;
MODULE1[293] <= 8'b00000000;
MODULE1[294] <= 8'b00000000;
MODULE1[295] <= 8'b00000000;
MODULE1[296] <= 8'b00000000;
MODULE1[297] <= 8'b00000000;
MODULE1[298] <= 8'b00000000;
MODULE1[299] <= 8'b00000000;
MODULE1[300] <= 8'b00000000;
MODULE1[301] <= 8'b00000000;
MODULE1[302] <= 8'b00000000;
MODULE1[303] <= 8'b00000000;
MODULE1[304] <= 8'b00000000;
MODULE1[305] <= 8'b00000000;
MODULE1[306] <= 8'b00000000;
MODULE1[307] <= 8'b00000000;
MODULE1[308] <= 8'b00000000;
MODULE1[309] <= 8'b00000000;
MODULE1[310] <= 8'b00000000;
MODULE1[311] <= 8'b00000000;
MODULE1[312] <= 8'b00000000;
MODULE1[313] <= 8'b00000000;
MODULE1[314] <= 8'b00000000;
MODULE1[315] <= 8'b00000000;
MODULE1[316] <= 8'b00000000;
MODULE1[317] <= 8'b00000000;
MODULE1[318] <= 8'b00000000;
MODULE1[319] <= 8'b00000000;
MODULE1[320] <= 8'b00000000;
MODULE1[321] <= 8'b00000000;
MODULE1[322] <= 8'b00000000;
MODULE1[323] <= 8'b00000000;
MODULE1[324] <= 8'b00000000;
MODULE1[325] <= 8'b00000000;
MODULE1[326] <= 8'b00000000;
MODULE1[327] <= 8'b00000000;
MODULE1[328] <= 8'b00000000;
MODULE1[329] <= 8'b00000000;
MODULE1[330] <= 8'b00000000;
MODULE1[331] <= 8'b00000000;
MODULE1[332] <= 8'b00000000;
MODULE1[333] <= 8'b00000000;
MODULE1[334] <= 8'b00000000;
MODULE1[335] <= 8'b00000000;
MODULE1[336] <= 8'b00000000;
MODULE1[337] <= 8'b00000000;
MODULE1[338] <= 8'b00000000;
MODULE1[339] <= 8'b00000000;
MODULE1[340] <= 8'b00000000;
MODULE1[341] <= 8'b00000000;
MODULE1[342] <= 8'b00000000;
MODULE1[343] <= 8'b00000000;
MODULE1[344] <= 8'b00000000;
MODULE1[345] <= 8'b00000000;
MODULE1[346] <= 8'b00000000;
MODULE1[347] <= 8'b00000000;
MODULE1[348] <= 8'b00000000;
MODULE1[349] <= 8'b00000000;
MODULE1[350] <= 8'b00000000;
MODULE1[351] <= 8'b00000000;
MODULE1[352] <= 8'b00000000;
MODULE1[353] <= 8'b00000000;
MODULE1[354] <= 8'b00000000;
MODULE1[355] <= 8'b00000000;
MODULE1[356] <= 8'b00000000;
MODULE1[357] <= 8'b00000000;
MODULE1[358] <= 8'b00000000;
MODULE1[359] <= 8'b00000000;
MODULE1[360] <= 8'b00000000;
MODULE1[361] <= 8'b00000000;
MODULE1[362] <= 8'b00000000;
MODULE1[363] <= 8'b11100000;
MODULE1[364] <= 8'b00000000;
MODULE1[365] <= 8'b01100000;
MODULE1[366] <= 8'b00000000;
MODULE1[367] <= 8'b01100000;
MODULE1[368] <= 8'b00000000;
MODULE1[369] <= 8'b10100000;
MODULE1[370] <= 8'b00000000;
MODULE1[371] <= 8'b10000000;
MODULE1[372] <= 8'b00000001;
MODULE1[373] <= 8'b10000000;
MODULE1[374] <= 8'b00000010;
MODULE1[375] <= 8'b01000000;
MODULE1[376] <= 8'b00000010;
MODULE1[377] <= 8'b01000000;
MODULE1[378] <= 8'b00000001;
MODULE1[379] <= 8'b10000000;
MODULE1[380] <= 8'b00000000;
MODULE1[381] <= 8'b00000000;
MODULE1[382] <= 8'b00000000;
MODULE1[383] <= 8'b00000000;
MODULE1[384] <= 8'b00000000;
MODULE1[385] <= 8'b00000000;
MODULE1[386] <= 8'b00000000;
MODULE1[387] <= 8'b00000000;
MODULE1[388] <= 8'b00000000;
MODULE1[389] <= 8'b00000000;
MODULE1[390] <= 8'b00000000;
MODULE1[391] <= 8'b00000000;
MODULE1[392] <= 8'b00000000;
MODULE1[393] <= 8'b00000000;
MODULE1[394] <= 8'b00000001;
MODULE1[395] <= 8'b11000000;
MODULE1[396] <= 8'b00000010;
MODULE1[397] <= 8'b00100000;
MODULE1[398] <= 8'b00000010;
MODULE1[399] <= 8'b00100000;
MODULE1[400] <= 8'b00000001;
MODULE1[401] <= 8'b11000000;
MODULE1[402] <= 8'b00000000;
MODULE1[403] <= 8'b10000000;
MODULE1[404] <= 8'b00000011;
MODULE1[405] <= 8'b11100000;
MODULE1[406] <= 8'b00000000;
MODULE1[407] <= 8'b10000000;
MODULE1[408] <= 8'b00000000;
MODULE1[409] <= 8'b10000000;
MODULE1[410] <= 8'b00000000;
MODULE1[411] <= 8'b10000000;
MODULE1[412] <= 8'b00000000;
MODULE1[413] <= 8'b00000000;
MODULE1[414] <= 8'b00000000;
MODULE1[415] <= 8'b00000000;
MODULE1[416] <= 8'b00000000;
MODULE1[417] <= 8'b00000000;
MODULE1[418] <= 8'b00000000;
MODULE1[419] <= 8'b00000000;
MODULE1[420] <= 8'b00000000;
MODULE1[421] <= 8'b00000000;
MODULE1[422] <= 8'b00000000;
MODULE1[423] <= 8'b00000000;
MODULE1[424] <= 8'b00000000;
MODULE1[425] <= 8'b00000000;
MODULE1[426] <= 8'b00000000;
MODULE1[427] <= 8'b00000000;
MODULE1[428] <= 8'b00000000;
MODULE1[429] <= 8'b00000000;
MODULE1[430] <= 8'b00000000;
MODULE1[431] <= 8'b00000000;
MODULE1[432] <= 8'b00000000;
MODULE1[433] <= 8'b00000000;
MODULE1[434] <= 8'b00000000;
MODULE1[435] <= 8'b00000000;
MODULE1[436] <= 8'b00000000;
MODULE1[437] <= 8'b00000000;
MODULE1[438] <= 8'b00000000;
MODULE1[439] <= 8'b00000000;
MODULE1[440] <= 8'b00000000;
MODULE1[441] <= 8'b00000000;
MODULE1[442] <= 8'b00000000;
MODULE1[443] <= 8'b00000000;
MODULE1[444] <= 8'b00000000;
MODULE1[445] <= 8'b00000000;
MODULE1[446] <= 8'b00000000;
MODULE1[447] <= 8'b00000000;
MODULE1[448] <= 8'b00000000;
MODULE1[449] <= 8'b00000000;
MODULE1[450] <= 8'b00000000;
MODULE1[451] <= 8'b00000000;
MODULE1[452] <= 8'b00000000;
MODULE1[453] <= 8'b00000000;
MODULE1[454] <= 8'b00000000;
MODULE1[455] <= 8'b00000000;
MODULE1[456] <= 8'b00000000;
MODULE1[457] <= 8'b00000000;
MODULE1[458] <= 8'b00000000;
MODULE1[459] <= 8'b01100000;
MODULE1[460] <= 8'b00000001;
MODULE1[461] <= 8'b10100000;
MODULE1[462] <= 8'b00000001;
MODULE1[463] <= 8'b01100000;
MODULE1[464] <= 8'b00000001;
MODULE1[465] <= 8'b10100000;
MODULE1[466] <= 8'b00000001;
MODULE1[467] <= 8'b00100000;
MODULE1[468] <= 8'b00000001;
MODULE1[469] <= 8'b00100000;
MODULE1[470] <= 8'b00000001;
MODULE1[471] <= 8'b01100000;
MODULE1[472] <= 8'b00000011;
MODULE1[473] <= 8'b01100000;
MODULE1[474] <= 8'b00000011;
MODULE1[475] <= 8'b00000000;
MODULE1[476] <= 8'b00000000;
MODULE1[477] <= 8'b00000000;
MODULE1[478] <= 8'b00000000;
MODULE1[479] <= 8'b00000000;
MODULE1[480] <= 8'b00000000;
MODULE1[481] <= 8'b00000000;
MODULE1[482] <= 8'b00000000;
MODULE1[483] <= 8'b00000000;
MODULE1[484] <= 8'b00000000;
MODULE1[485] <= 8'b00000000;
MODULE1[486] <= 8'b00000000;
MODULE1[487] <= 8'b00000000;
MODULE1[488] <= 8'b00000000;
MODULE1[489] <= 8'b00000000;
MODULE1[490] <= 8'b00000010;
MODULE1[491] <= 8'b10100000;
MODULE1[492] <= 8'b00000010;
MODULE1[493] <= 8'b10100000;
MODULE1[494] <= 8'b00000001;
MODULE1[495] <= 8'b01000000;
MODULE1[496] <= 8'b00000001;
MODULE1[497] <= 8'b01000000;
MODULE1[498] <= 8'b00000011;
MODULE1[499] <= 8'b01100000;
MODULE1[500] <= 8'b00000001;
MODULE1[501] <= 8'b01000000;
MODULE1[502] <= 8'b00000001;
MODULE1[503] <= 8'b01000000;
MODULE1[504] <= 8'b00000010;
MODULE1[505] <= 8'b10100000;
MODULE1[506] <= 8'b00000010;
MODULE1[507] <= 8'b10100000;
MODULE1[508] <= 8'b00000000;
MODULE1[509] <= 8'b00000000;
MODULE1[510] <= 8'b00000000;
MODULE1[511] <= 8'b00000000;
MODULE1[512] <= 8'b00000000;
MODULE1[513] <= 8'b00000000;
MODULE1[514] <= 8'b00000000;
MODULE1[515] <= 8'b00000000;
MODULE1[516] <= 8'b00000000;
MODULE1[517] <= 8'b00000000;
MODULE1[518] <= 8'b00000000;
MODULE1[519] <= 8'b00000000;
MODULE1[520] <= 8'b00000000;
MODULE1[521] <= 8'b10000000;
MODULE1[522] <= 8'b00000000;
MODULE1[523] <= 8'b10000000;
MODULE1[524] <= 8'b00000000;
MODULE1[525] <= 8'b10000000;
MODULE1[526] <= 8'b00000000;
MODULE1[527] <= 8'b10000000;
MODULE1[528] <= 8'b00000000;
MODULE1[529] <= 8'b10000000;
MODULE1[530] <= 8'b00000000;
MODULE1[531] <= 8'b10000000;
MODULE1[532] <= 8'b00000111;
MODULE1[533] <= 8'b11100000;
MODULE1[534] <= 8'b00000000;
MODULE1[535] <= 8'b10000000;
MODULE1[536] <= 8'b00000000;
MODULE1[537] <= 8'b10000000;
MODULE1[538] <= 8'b00000000;
MODULE1[539] <= 8'b10000000;
MODULE1[540] <= 8'b00000000;
MODULE1[541] <= 8'b10000000;
MODULE1[542] <= 8'b00000000;
MODULE1[543] <= 8'b10000000;
MODULE1[544] <= 8'b00000000;
MODULE1[545] <= 8'b00000000;
MODULE1[546] <= 8'b00000000;
MODULE1[547] <= 8'b00000000;
MODULE1[548] <= 8'b00000000;
MODULE1[549] <= 8'b00000000;
MODULE1[550] <= 8'b00000000;
MODULE1[551] <= 8'b00000000;
MODULE1[552] <= 8'b00000000;
MODULE1[553] <= 8'b00000000;
MODULE1[554] <= 8'b00000000;
MODULE1[555] <= 8'b00100000;
MODULE1[556] <= 8'b00000000;
MODULE1[557] <= 8'b01100000;
MODULE1[558] <= 8'b00000000;
MODULE1[559] <= 8'b11100000;
MODULE1[560] <= 8'b00000001;
MODULE1[561] <= 8'b11100000;
MODULE1[562] <= 8'b00000011;
MODULE1[563] <= 8'b11100000;
MODULE1[564] <= 8'b00000001;
MODULE1[565] <= 8'b11100000;
MODULE1[566] <= 8'b00000000;
MODULE1[567] <= 8'b11100000;
MODULE1[568] <= 8'b00000000;
MODULE1[569] <= 8'b01100000;
MODULE1[570] <= 8'b00000000;
MODULE1[571] <= 8'b00100000;
MODULE1[572] <= 8'b00000000;
MODULE1[573] <= 8'b00000000;
MODULE1[574] <= 8'b00000000;
MODULE1[575] <= 8'b00000000;
MODULE1[576] <= 8'b00000000;
MODULE1[577] <= 8'b00000000;
MODULE1[578] <= 8'b00000000;
MODULE1[579] <= 8'b00000000;
MODULE1[580] <= 8'b00000000;
MODULE1[581] <= 8'b00000000;
MODULE1[582] <= 8'b00000000;
MODULE1[583] <= 8'b00000000;
MODULE1[584] <= 8'b00000000;
MODULE1[585] <= 8'b10000000;
MODULE1[586] <= 8'b00000001;
MODULE1[587] <= 8'b11000000;
MODULE1[588] <= 8'b00000000;
MODULE1[589] <= 8'b10000000;
MODULE1[590] <= 8'b00000000;
MODULE1[591] <= 8'b10000000;
MODULE1[592] <= 8'b00000000;
MODULE1[593] <= 8'b10000000;
MODULE1[594] <= 8'b00000000;
MODULE1[595] <= 8'b10000000;
MODULE1[596] <= 8'b00000000;
MODULE1[597] <= 8'b10000000;
MODULE1[598] <= 8'b00000000;
MODULE1[599] <= 8'b10000000;
MODULE1[600] <= 8'b00000001;
MODULE1[601] <= 8'b11000000;
MODULE1[602] <= 8'b00000000;
MODULE1[603] <= 8'b10000000;
MODULE1[604] <= 8'b00000000;
MODULE1[605] <= 8'b00000000;
MODULE1[606] <= 8'b00000000;
MODULE1[607] <= 8'b00000000;
MODULE1[608] <= 8'b00000000;
MODULE1[609] <= 8'b00000000;
MODULE1[610] <= 8'b00000000;
MODULE1[611] <= 8'b00000000;
MODULE1[612] <= 8'b00000000;
MODULE1[613] <= 8'b00000000;
MODULE1[614] <= 8'b00000000;
MODULE1[615] <= 8'b00000000;
MODULE1[616] <= 8'b00000001;
MODULE1[617] <= 8'b01000000;
MODULE1[618] <= 8'b00000001;
MODULE1[619] <= 8'b01000000;
MODULE1[620] <= 8'b00000001;
MODULE1[621] <= 8'b01000000;
MODULE1[622] <= 8'b00000001;
MODULE1[623] <= 8'b01000000;
MODULE1[624] <= 8'b00000001;
MODULE1[625] <= 8'b01000000;
MODULE1[626] <= 8'b00000001;
MODULE1[627] <= 8'b01000000;
MODULE1[628] <= 8'b00000001;
MODULE1[629] <= 8'b01000000;
MODULE1[630] <= 8'b00000000;
MODULE1[631] <= 8'b00000000;
MODULE1[632] <= 8'b00000001;
MODULE1[633] <= 8'b01000000;
MODULE1[634] <= 8'b00000001;
MODULE1[635] <= 8'b01000000;
MODULE1[636] <= 8'b00000000;
MODULE1[637] <= 8'b00000000;
MODULE1[638] <= 8'b00000000;
MODULE1[639] <= 8'b00000000;
MODULE1[640] <= 8'b00000000;
MODULE1[641] <= 8'b00000000;
MODULE1[642] <= 8'b00000000;
MODULE1[643] <= 8'b00000000;
MODULE1[644] <= 8'b00000000;
MODULE1[645] <= 8'b00000000;
MODULE1[646] <= 8'b00000000;
MODULE1[647] <= 8'b00000000;
MODULE1[648] <= 8'b00000001;
MODULE1[649] <= 8'b11100000;
MODULE1[650] <= 8'b00000010;
MODULE1[651] <= 8'b10100000;
MODULE1[652] <= 8'b00000010;
MODULE1[653] <= 8'b10100000;
MODULE1[654] <= 8'b00000010;
MODULE1[655] <= 8'b10100000;
MODULE1[656] <= 8'b00000001;
MODULE1[657] <= 8'b10100000;
MODULE1[658] <= 8'b00000000;
MODULE1[659] <= 8'b10100000;
MODULE1[660] <= 8'b00000000;
MODULE1[661] <= 8'b10100000;
MODULE1[662] <= 8'b00000000;
MODULE1[663] <= 8'b10100000;
MODULE1[664] <= 8'b00000000;
MODULE1[665] <= 8'b10100000;
MODULE1[666] <= 8'b00000000;
MODULE1[667] <= 8'b10100000;
MODULE1[668] <= 8'b00000000;
MODULE1[669] <= 8'b00000000;
MODULE1[670] <= 8'b00000000;
MODULE1[671] <= 8'b00000000;
MODULE1[672] <= 8'b00000000;
MODULE1[673] <= 8'b00000000;
MODULE1[674] <= 8'b00000000;
MODULE1[675] <= 8'b00000000;
MODULE1[676] <= 8'b00000000;
MODULE1[677] <= 8'b00000000;
MODULE1[678] <= 8'b00000000;
MODULE1[679] <= 8'b00000000;
MODULE1[680] <= 8'b00000000;
MODULE1[681] <= 8'b10000000;
MODULE1[682] <= 8'b00000000;
MODULE1[683] <= 8'b10000000;
MODULE1[684] <= 8'b00000000;
MODULE1[685] <= 8'b10000000;
MODULE1[686] <= 8'b00000000;
MODULE1[687] <= 8'b10000000;
MODULE1[688] <= 8'b00000000;
MODULE1[689] <= 8'b10000000;
MODULE1[690] <= 8'b00000000;
MODULE1[691] <= 8'b10000000;
MODULE1[692] <= 8'b00000111;
MODULE1[693] <= 8'b11100000;
MODULE1[694] <= 8'b00000000;
MODULE1[695] <= 8'b00000000;
MODULE1[696] <= 8'b00000000;
MODULE1[697] <= 8'b00000000;
MODULE1[698] <= 8'b00000000;
MODULE1[699] <= 8'b00000000;
MODULE1[700] <= 8'b00000000;
MODULE1[701] <= 8'b00000000;
MODULE1[702] <= 8'b00000000;
MODULE1[703] <= 8'b00000000;
MODULE1[704] <= 8'b00000000;
MODULE1[705] <= 8'b00000000;
MODULE1[706] <= 8'b00000000;
MODULE1[707] <= 8'b00000000;
MODULE1[708] <= 8'b00000000;
MODULE1[709] <= 8'b00000000;
MODULE1[710] <= 8'b00000000;
MODULE1[711] <= 8'b00000000;
MODULE1[712] <= 8'b00000000;
MODULE1[713] <= 8'b00000000;
MODULE1[714] <= 8'b00000000;
MODULE1[715] <= 8'b00000000;
MODULE1[716] <= 8'b00000000;
MODULE1[717] <= 8'b00000000;
MODULE1[718] <= 8'b00000000;
MODULE1[719] <= 8'b00000000;
MODULE1[720] <= 8'b00000000;
MODULE1[721] <= 8'b00000000;
MODULE1[722] <= 8'b00000000;
MODULE1[723] <= 8'b00000000;
MODULE1[724] <= 8'b00000111;
MODULE1[725] <= 8'b11100000;
MODULE1[726] <= 8'b00000000;
MODULE1[727] <= 8'b10000000;
MODULE1[728] <= 8'b00000000;
MODULE1[729] <= 8'b10000000;
MODULE1[730] <= 8'b00000000;
MODULE1[731] <= 8'b10000000;
MODULE1[732] <= 8'b00000000;
MODULE1[733] <= 8'b10000000;
MODULE1[734] <= 8'b00000000;
MODULE1[735] <= 8'b10000000;
MODULE1[736] <= 8'b00000000;
MODULE1[737] <= 8'b00000000;
MODULE1[738] <= 8'b00000000;
MODULE1[739] <= 8'b00000000;
MODULE1[740] <= 8'b00000000;
MODULE1[741] <= 8'b00000000;
MODULE1[742] <= 8'b00000000;
MODULE1[743] <= 8'b00000000;
MODULE1[744] <= 8'b00000000;
MODULE1[745] <= 8'b10000000;
MODULE1[746] <= 8'b00000000;
MODULE1[747] <= 8'b10000000;
MODULE1[748] <= 8'b00000000;
MODULE1[749] <= 8'b10000000;
MODULE1[750] <= 8'b00000000;
MODULE1[751] <= 8'b10000000;
MODULE1[752] <= 8'b00000000;
MODULE1[753] <= 8'b10000000;
MODULE1[754] <= 8'b00000000;
MODULE1[755] <= 8'b10000000;
MODULE1[756] <= 8'b00000111;
MODULE1[757] <= 8'b10000000;
MODULE1[758] <= 8'b00000000;
MODULE1[759] <= 8'b10000000;
MODULE1[760] <= 8'b00000000;
MODULE1[761] <= 8'b10000000;
MODULE1[762] <= 8'b00000000;
MODULE1[763] <= 8'b10000000;
MODULE1[764] <= 8'b00000000;
MODULE1[765] <= 8'b10000000;
MODULE1[766] <= 8'b00000000;
MODULE1[767] <= 8'b10000000;
MODULE1[768] <= 8'b00000000;
MODULE1[769] <= 8'b00000000;
MODULE1[770] <= 8'b00000000;
MODULE1[771] <= 8'b00000000;
MODULE1[772] <= 8'b00000000;
MODULE1[773] <= 8'b00000000;
MODULE1[774] <= 8'b00000000;
MODULE1[775] <= 8'b00000000;
MODULE1[776] <= 8'b00000000;
MODULE1[777] <= 8'b10000000;
MODULE1[778] <= 8'b00000001;
MODULE1[779] <= 8'b11000000;
MODULE1[780] <= 8'b00000000;
MODULE1[781] <= 8'b10000000;
MODULE1[782] <= 8'b00000000;
MODULE1[783] <= 8'b10000000;
MODULE1[784] <= 8'b00000000;
MODULE1[785] <= 8'b10000000;
MODULE1[786] <= 8'b00000000;
MODULE1[787] <= 8'b10000000;
MODULE1[788] <= 8'b00000000;
MODULE1[789] <= 8'b10000000;
MODULE1[790] <= 8'b00000000;
MODULE1[791] <= 8'b10000000;
MODULE1[792] <= 8'b00000000;
MODULE1[793] <= 8'b10000000;
MODULE1[794] <= 8'b00000000;
MODULE1[795] <= 8'b10000000;
MODULE1[796] <= 8'b00000000;
MODULE1[797] <= 8'b00000000;
MODULE1[798] <= 8'b00000000;
MODULE1[799] <= 8'b00000000;
MODULE1[800] <= 8'b00000000;
MODULE1[801] <= 8'b00000000;
MODULE1[802] <= 8'b00000000;
MODULE1[803] <= 8'b00000000;
MODULE1[804] <= 8'b00000000;
MODULE1[805] <= 8'b00000000;
MODULE1[806] <= 8'b00000000;
MODULE1[807] <= 8'b00000000;
MODULE1[808] <= 8'b00000000;
MODULE1[809] <= 8'b10000000;
MODULE1[810] <= 8'b00000000;
MODULE1[811] <= 8'b10000000;
MODULE1[812] <= 8'b00000000;
MODULE1[813] <= 8'b10000000;
MODULE1[814] <= 8'b00000000;
MODULE1[815] <= 8'b10000000;
MODULE1[816] <= 8'b00000000;
MODULE1[817] <= 8'b10000000;
MODULE1[818] <= 8'b00000000;
MODULE1[819] <= 8'b10000000;
MODULE1[820] <= 8'b00000000;
MODULE1[821] <= 8'b11100000;
MODULE1[822] <= 8'b00000000;
MODULE1[823] <= 8'b10000000;
MODULE1[824] <= 8'b00000000;
MODULE1[825] <= 8'b10000000;
MODULE1[826] <= 8'b00000000;
MODULE1[827] <= 8'b10000000;
MODULE1[828] <= 8'b00000000;
MODULE1[829] <= 8'b10000000;
MODULE1[830] <= 8'b00000000;
MODULE1[831] <= 8'b10000000;
MODULE1[832] <= 8'b00000000;
MODULE1[833] <= 8'b00000000;
MODULE1[834] <= 8'b00000000;
MODULE1[835] <= 8'b00000000;
MODULE1[836] <= 8'b00000000;
MODULE1[837] <= 8'b00000000;
MODULE1[838] <= 8'b00000000;
MODULE1[839] <= 8'b00000000;
MODULE1[840] <= 8'b00000000;
MODULE1[841] <= 8'b00000000;
MODULE1[842] <= 8'b00000000;
MODULE1[843] <= 8'b00000000;
MODULE1[844] <= 8'b00000000;
MODULE1[845] <= 8'b00000000;
MODULE1[846] <= 8'b00000000;
MODULE1[847] <= 8'b00000000;
MODULE1[848] <= 8'b00000000;
MODULE1[849] <= 8'b01000000;
MODULE1[850] <= 8'b00000011;
MODULE1[851] <= 8'b11100000;
MODULE1[852] <= 8'b00000000;
MODULE1[853] <= 8'b01000000;
MODULE1[854] <= 8'b00000000;
MODULE1[855] <= 8'b00000000;
MODULE1[856] <= 8'b00000000;
MODULE1[857] <= 8'b00000000;
MODULE1[858] <= 8'b00000000;
MODULE1[859] <= 8'b00000000;
MODULE1[860] <= 8'b00000000;
MODULE1[861] <= 8'b00000000;
MODULE1[862] <= 8'b00000000;
MODULE1[863] <= 8'b00000000;
MODULE1[864] <= 8'b00000000;
MODULE1[865] <= 8'b00000000;
MODULE1[866] <= 8'b00000000;
MODULE1[867] <= 8'b00000000;
MODULE1[868] <= 8'b00000000;
MODULE1[869] <= 8'b00000000;
MODULE1[870] <= 8'b00000000;
MODULE1[871] <= 8'b00000000;
MODULE1[872] <= 8'b00000000;
MODULE1[873] <= 8'b00000000;
MODULE1[874] <= 8'b00000000;
MODULE1[875] <= 8'b00000000;
MODULE1[876] <= 8'b00000000;
MODULE1[877] <= 8'b00000000;
MODULE1[878] <= 8'b00000000;
MODULE1[879] <= 8'b00000000;
MODULE1[880] <= 8'b00000001;
MODULE1[881] <= 8'b00000000;
MODULE1[882] <= 8'b00000011;
MODULE1[883] <= 8'b11100000;
MODULE1[884] <= 8'b00000001;
MODULE1[885] <= 8'b00000000;
MODULE1[886] <= 8'b00000000;
MODULE1[887] <= 8'b00000000;
MODULE1[888] <= 8'b00000000;
MODULE1[889] <= 8'b00000000;
MODULE1[890] <= 8'b00000000;
MODULE1[891] <= 8'b00000000;
MODULE1[892] <= 8'b00000000;
MODULE1[893] <= 8'b00000000;
MODULE1[894] <= 8'b00000000;
MODULE1[895] <= 8'b00000000;
MODULE1[896] <= 8'b00000000;
MODULE1[897] <= 8'b00000000;
MODULE1[898] <= 8'b00000000;
MODULE1[899] <= 8'b00000000;
MODULE1[900] <= 8'b00000000;
MODULE1[901] <= 8'b00000000;
MODULE1[902] <= 8'b00000000;
MODULE1[903] <= 8'b00000000;
MODULE1[904] <= 8'b00000000;
MODULE1[905] <= 8'b00000000;
MODULE1[906] <= 8'b00000000;
MODULE1[907] <= 8'b00000000;
MODULE1[908] <= 8'b00000000;
MODULE1[909] <= 8'b00000000;
MODULE1[910] <= 8'b00000000;
MODULE1[911] <= 8'b00000000;
MODULE1[912] <= 8'b00000000;
MODULE1[913] <= 8'b00000000;
MODULE1[914] <= 8'b00000000;
MODULE1[915] <= 8'b00000000;
MODULE1[916] <= 8'b00000000;
MODULE1[917] <= 8'b00000000;
MODULE1[918] <= 8'b00000000;
MODULE1[919] <= 8'b00000000;
MODULE1[920] <= 8'b00000000;
MODULE1[921] <= 8'b00000000;
MODULE1[922] <= 8'b00000000;
MODULE1[923] <= 8'b00000000;
MODULE1[924] <= 8'b00000000;
MODULE1[925] <= 8'b00000000;
MODULE1[926] <= 8'b00000000;
MODULE1[927] <= 8'b00000000;
MODULE1[928] <= 8'b00000000;
MODULE1[929] <= 8'b00000000;
MODULE1[930] <= 8'b00000000;
MODULE1[931] <= 8'b00000000;
MODULE1[932] <= 8'b00000000;
MODULE1[933] <= 8'b00000000;
MODULE1[934] <= 8'b00000000;
MODULE1[935] <= 8'b00000000;
MODULE1[936] <= 8'b00000000;
MODULE1[937] <= 8'b00000000;
MODULE1[938] <= 8'b00000000;
MODULE1[939] <= 8'b00000000;
MODULE1[940] <= 8'b00000000;
MODULE1[941] <= 8'b00000000;
MODULE1[942] <= 8'b00000000;
MODULE1[943] <= 8'b00000000;
MODULE1[944] <= 8'b00000000;
MODULE1[945] <= 8'b00000000;
MODULE1[946] <= 8'b00000000;
MODULE1[947] <= 8'b00000000;
MODULE1[948] <= 8'b00000000;
MODULE1[949] <= 8'b00000000;
MODULE1[950] <= 8'b00000000;
MODULE1[951] <= 8'b00000000;
MODULE1[952] <= 8'b00000000;
MODULE1[953] <= 8'b00000000;
MODULE1[954] <= 8'b00000000;
MODULE1[955] <= 8'b00000000;
MODULE1[956] <= 8'b00000000;
MODULE1[957] <= 8'b00000000;
MODULE1[958] <= 8'b00000000;
MODULE1[959] <= 8'b00000000;
MODULE1[960] <= 8'b00000000;
MODULE1[961] <= 8'b00000000;
MODULE1[962] <= 8'b00000000;
MODULE1[963] <= 8'b00000000;
MODULE1[964] <= 8'b00000000;
MODULE1[965] <= 8'b00000000;
MODULE1[966] <= 8'b00000000;
MODULE1[967] <= 8'b00000000;
MODULE1[968] <= 8'b00000000;
MODULE1[969] <= 8'b00000000;
MODULE1[970] <= 8'b00000000;
MODULE1[971] <= 8'b00000000;
MODULE1[972] <= 8'b00000000;
MODULE1[973] <= 8'b00000000;
MODULE1[974] <= 8'b00000000;
MODULE1[975] <= 8'b00000000;
MODULE1[976] <= 8'b00000000;
MODULE1[977] <= 8'b00000000;
MODULE1[978] <= 8'b00000000;
MODULE1[979] <= 8'b00000000;
MODULE1[980] <= 8'b00000000;
MODULE1[981] <= 8'b00000000;
MODULE1[982] <= 8'b00000000;
MODULE1[983] <= 8'b00000000;
MODULE1[984] <= 8'b00000000;
MODULE1[985] <= 8'b00000000;
MODULE1[986] <= 8'b00000000;
MODULE1[987] <= 8'b00000000;
MODULE1[988] <= 8'b00000000;
MODULE1[989] <= 8'b00000000;
MODULE1[990] <= 8'b00000000;
MODULE1[991] <= 8'b00000000;
MODULE1[992] <= 8'b00000000;
MODULE1[993] <= 8'b00000000;
MODULE1[994] <= 8'b00000000;
MODULE1[995] <= 8'b00000000;
MODULE1[996] <= 8'b00000000;
MODULE1[997] <= 8'b00000000;
MODULE1[998] <= 8'b00000000;
MODULE1[999] <= 8'b00000000;
MODULE1[1000] <= 8'b00000000;
MODULE1[1001] <= 8'b00000000;
MODULE1[1002] <= 8'b00000000;
MODULE1[1003] <= 8'b00000000;
MODULE1[1004] <= 8'b00000000;
MODULE1[1005] <= 8'b00000000;
MODULE1[1006] <= 8'b00000000;
MODULE1[1007] <= 8'b00000000;
MODULE1[1008] <= 8'b00000000;
MODULE1[1009] <= 8'b00000000;
MODULE1[1010] <= 8'b00000000;
MODULE1[1011] <= 8'b00000000;
MODULE1[1012] <= 8'b00000000;
MODULE1[1013] <= 8'b00000000;
MODULE1[1014] <= 8'b00000000;
MODULE1[1015] <= 8'b00000000;
MODULE1[1016] <= 8'b00000000;
MODULE1[1017] <= 8'b00000000;
MODULE1[1018] <= 8'b00000000;
MODULE1[1019] <= 8'b00000000;
MODULE1[1020] <= 8'b00000000;
MODULE1[1021] <= 8'b00000000;
MODULE1[1022] <= 8'b00000000;
MODULE1[1023] <= 8'b00000000;
MODULE1[1024] <= 8'b00000000;
MODULE1[1025] <= 8'b00000000;
MODULE1[1026] <= 8'b00000000;
MODULE1[1027] <= 8'b00000000;
MODULE1[1028] <= 8'b00000000;
MODULE1[1029] <= 8'b00000000;
MODULE1[1030] <= 8'b00000000;
MODULE1[1031] <= 8'b00000000;
MODULE1[1032] <= 8'b00000000;
MODULE1[1033] <= 8'b00000000;
MODULE1[1034] <= 8'b00000000;
MODULE1[1035] <= 8'b00000000;
MODULE1[1036] <= 8'b00000000;
MODULE1[1037] <= 8'b00000000;
MODULE1[1038] <= 8'b00000000;
MODULE1[1039] <= 8'b00000000;
MODULE1[1040] <= 8'b00000000;
MODULE1[1041] <= 8'b00000000;
MODULE1[1042] <= 8'b00000000;
MODULE1[1043] <= 8'b00000000;
MODULE1[1044] <= 8'b00000000;
MODULE1[1045] <= 8'b00000000;
MODULE1[1046] <= 8'b00000000;
MODULE1[1047] <= 8'b00000000;
MODULE1[1048] <= 8'b00000000;
MODULE1[1049] <= 8'b00000000;
MODULE1[1050] <= 8'b00000000;
MODULE1[1051] <= 8'b00000000;
MODULE1[1052] <= 8'b00000000;
MODULE1[1053] <= 8'b00000000;
MODULE1[1054] <= 8'b00000000;
MODULE1[1055] <= 8'b00000000;
MODULE1[1056] <= 8'b00000000;
MODULE1[1057] <= 8'b00000000;
MODULE1[1058] <= 8'b00000000;
MODULE1[1059] <= 8'b00000000;
MODULE1[1060] <= 8'b00000000;
MODULE1[1061] <= 8'b00000000;
MODULE1[1062] <= 8'b00000000;
MODULE1[1063] <= 8'b00000000;
MODULE1[1064] <= 8'b00000011;
MODULE1[1065] <= 8'b00000000;
MODULE1[1066] <= 8'b00000011;
MODULE1[1067] <= 8'b00000000;
MODULE1[1068] <= 8'b00000011;
MODULE1[1069] <= 8'b00000000;
MODULE1[1070] <= 8'b00000011;
MODULE1[1071] <= 8'b00000000;
MODULE1[1072] <= 8'b00000011;
MODULE1[1073] <= 8'b00000000;
MODULE1[1074] <= 8'b00000011;
MODULE1[1075] <= 8'b00000000;
MODULE1[1076] <= 8'b00000011;
MODULE1[1077] <= 8'b00000000;
MODULE1[1078] <= 8'b00000000;
MODULE1[1079] <= 8'b00000000;
MODULE1[1080] <= 8'b00000011;
MODULE1[1081] <= 8'b00000000;
MODULE1[1082] <= 8'b00000000;
MODULE1[1083] <= 8'b00000000;
MODULE1[1084] <= 8'b00000000;
MODULE1[1085] <= 8'b00000000;
MODULE1[1086] <= 8'b00000000;
MODULE1[1087] <= 8'b00000000;
MODULE1[1088] <= 8'b00000000;
MODULE1[1089] <= 8'b00000000;
MODULE1[1090] <= 8'b00000000;
MODULE1[1091] <= 8'b00000000;
MODULE1[1092] <= 8'b00000000;
MODULE1[1093] <= 8'b00000000;
MODULE1[1094] <= 8'b00000000;
MODULE1[1095] <= 8'b00000000;
MODULE1[1096] <= 8'b00000000;
MODULE1[1097] <= 8'b00000000;
MODULE1[1098] <= 8'b00000011;
MODULE1[1099] <= 8'b11000000;
MODULE1[1100] <= 8'b00000011;
MODULE1[1101] <= 8'b11000000;
MODULE1[1102] <= 8'b00000011;
MODULE1[1103] <= 8'b11000000;
MODULE1[1104] <= 8'b00000000;
MODULE1[1105] <= 8'b00000000;
MODULE1[1106] <= 8'b00000000;
MODULE1[1107] <= 8'b00000000;
MODULE1[1108] <= 8'b00000000;
MODULE1[1109] <= 8'b00000000;
MODULE1[1110] <= 8'b00000000;
MODULE1[1111] <= 8'b00000000;
MODULE1[1112] <= 8'b00000000;
MODULE1[1113] <= 8'b00000000;
MODULE1[1114] <= 8'b00000000;
MODULE1[1115] <= 8'b00000000;
MODULE1[1116] <= 8'b00000000;
MODULE1[1117] <= 8'b00000000;
MODULE1[1118] <= 8'b00000000;
MODULE1[1119] <= 8'b00000000;
MODULE1[1120] <= 8'b00000000;
MODULE1[1121] <= 8'b00000000;
MODULE1[1122] <= 8'b00000000;
MODULE1[1123] <= 8'b00000000;
MODULE1[1124] <= 8'b00000000;
MODULE1[1125] <= 8'b00000000;
MODULE1[1126] <= 8'b00000000;
MODULE1[1127] <= 8'b00000000;
MODULE1[1128] <= 8'b00000000;
MODULE1[1129] <= 8'b00000000;
MODULE1[1130] <= 8'b00000001;
MODULE1[1131] <= 8'b00110000;
MODULE1[1132] <= 8'b00000011;
MODULE1[1133] <= 8'b00110000;
MODULE1[1134] <= 8'b00001111;
MODULE1[1135] <= 8'b11111000;
MODULE1[1136] <= 8'b00000011;
MODULE1[1137] <= 8'b01100000;
MODULE1[1138] <= 8'b00000110;
MODULE1[1139] <= 8'b01100000;
MODULE1[1140] <= 8'b00011111;
MODULE1[1141] <= 8'b11111000;
MODULE1[1142] <= 8'b00000110;
MODULE1[1143] <= 8'b11000000;
MODULE1[1144] <= 8'b00001100;
MODULE1[1145] <= 8'b11000000;
MODULE1[1146] <= 8'b00000000;
MODULE1[1147] <= 8'b00000000;
MODULE1[1148] <= 8'b00000000;
MODULE1[1149] <= 8'b00000000;
MODULE1[1150] <= 8'b00000000;
MODULE1[1151] <= 8'b00000000;
MODULE1[1152] <= 8'b00000000;
MODULE1[1153] <= 8'b00000000;
MODULE1[1154] <= 8'b00000000;
MODULE1[1155] <= 8'b00000000;
MODULE1[1156] <= 8'b00000000;
MODULE1[1157] <= 8'b00000000;
MODULE1[1158] <= 8'b00000000;
MODULE1[1159] <= 8'b00000000;
MODULE1[1160] <= 8'b00000011;
MODULE1[1161] <= 8'b00000000;
MODULE1[1162] <= 8'b00000111;
MODULE1[1163] <= 8'b11100000;
MODULE1[1164] <= 8'b00001111;
MODULE1[1165] <= 8'b00000000;
MODULE1[1166] <= 8'b00001111;
MODULE1[1167] <= 8'b00000000;
MODULE1[1168] <= 8'b00000111;
MODULE1[1169] <= 8'b11000000;
MODULE1[1170] <= 8'b00000011;
MODULE1[1171] <= 8'b01100000;
MODULE1[1172] <= 8'b00000011;
MODULE1[1173] <= 8'b01100000;
MODULE1[1174] <= 8'b00000011;
MODULE1[1175] <= 8'b11100000;
MODULE1[1176] <= 8'b00001111;
MODULE1[1177] <= 8'b11000000;
MODULE1[1178] <= 8'b00000011;
MODULE1[1179] <= 8'b00000000;
MODULE1[1180] <= 8'b00000011;
MODULE1[1181] <= 8'b00000000;
MODULE1[1182] <= 8'b00000000;
MODULE1[1183] <= 8'b00000000;
MODULE1[1184] <= 8'b00000000;
MODULE1[1185] <= 8'b00000000;
MODULE1[1186] <= 8'b00000000;
MODULE1[1187] <= 8'b00000000;
MODULE1[1188] <= 8'b00000000;
MODULE1[1189] <= 8'b00000000;
MODULE1[1190] <= 8'b00000000;
MODULE1[1191] <= 8'b00000000;
MODULE1[1192] <= 8'b00000000;
MODULE1[1193] <= 8'b01100000;
MODULE1[1194] <= 8'b00000111;
MODULE1[1195] <= 8'b01000000;
MODULE1[1196] <= 8'b00001111;
MODULE1[1197] <= 8'b11000000;
MODULE1[1198] <= 8'b00001111;
MODULE1[1199] <= 8'b11000000;
MODULE1[1200] <= 8'b00000111;
MODULE1[1201] <= 8'b10000000;
MODULE1[1202] <= 8'b00000001;
MODULE1[1203] <= 8'b11110000;
MODULE1[1204] <= 8'b00000011;
MODULE1[1205] <= 8'b11011000;
MODULE1[1206] <= 8'b00000011;
MODULE1[1207] <= 8'b11011000;
MODULE1[1208] <= 8'b00000110;
MODULE1[1209] <= 8'b01110000;
MODULE1[1210] <= 8'b00000000;
MODULE1[1211] <= 8'b00000000;
MODULE1[1212] <= 8'b00000000;
MODULE1[1213] <= 8'b00000000;
MODULE1[1214] <= 8'b00000000;
MODULE1[1215] <= 8'b00000000;
MODULE1[1216] <= 8'b00000000;
MODULE1[1217] <= 8'b00000000;
MODULE1[1218] <= 8'b00000000;
MODULE1[1219] <= 8'b00000000;
MODULE1[1220] <= 8'b00000000;
MODULE1[1221] <= 8'b00000000;
MODULE1[1222] <= 8'b00000000;
MODULE1[1223] <= 8'b00000000;
MODULE1[1224] <= 8'b00000000;
MODULE1[1225] <= 8'b00000000;
MODULE1[1226] <= 8'b00000011;
MODULE1[1227] <= 8'b10000000;
MODULE1[1228] <= 8'b00000011;
MODULE1[1229] <= 8'b10000000;
MODULE1[1230] <= 8'b00000011;
MODULE1[1231] <= 8'b10000000;
MODULE1[1232] <= 8'b00000111;
MODULE1[1233] <= 8'b01100000;
MODULE1[1234] <= 8'b00001101;
MODULE1[1235] <= 8'b11100000;
MODULE1[1236] <= 8'b00001100;
MODULE1[1237] <= 8'b11000000;
MODULE1[1238] <= 8'b00001100;
MODULE1[1239] <= 8'b11000000;
MODULE1[1240] <= 8'b00000111;
MODULE1[1241] <= 8'b11100000;
MODULE1[1242] <= 8'b00000000;
MODULE1[1243] <= 8'b00000000;
MODULE1[1244] <= 8'b00000000;
MODULE1[1245] <= 8'b00000000;
MODULE1[1246] <= 8'b00000000;
MODULE1[1247] <= 8'b00000000;
MODULE1[1248] <= 8'b00000000;
MODULE1[1249] <= 8'b00000000;
MODULE1[1250] <= 8'b00000000;
MODULE1[1251] <= 8'b00000000;
MODULE1[1252] <= 8'b00000000;
MODULE1[1253] <= 8'b00000000;
MODULE1[1254] <= 8'b00000000;
MODULE1[1255] <= 8'b00000000;
MODULE1[1256] <= 8'b00000000;
MODULE1[1257] <= 8'b00000000;
MODULE1[1258] <= 8'b00000001;
MODULE1[1259] <= 8'b10000000;
MODULE1[1260] <= 8'b00000001;
MODULE1[1261] <= 8'b10000000;
MODULE1[1262] <= 8'b00000001;
MODULE1[1263] <= 8'b10000000;
MODULE1[1264] <= 8'b00000000;
MODULE1[1265] <= 8'b00000000;
MODULE1[1266] <= 8'b00000000;
MODULE1[1267] <= 8'b00000000;
MODULE1[1268] <= 8'b00000000;
MODULE1[1269] <= 8'b00000000;
MODULE1[1270] <= 8'b00000000;
MODULE1[1271] <= 8'b00000000;
MODULE1[1272] <= 8'b00000000;
MODULE1[1273] <= 8'b00000000;
MODULE1[1274] <= 8'b00000000;
MODULE1[1275] <= 8'b00000000;
MODULE1[1276] <= 8'b00000000;
MODULE1[1277] <= 8'b00000000;
MODULE1[1278] <= 8'b00000000;
MODULE1[1279] <= 8'b00000000;
MODULE1[1280] <= 8'b00000000;
MODULE1[1281] <= 8'b00000000;
MODULE1[1282] <= 8'b00000000;
MODULE1[1283] <= 8'b00000000;
MODULE1[1284] <= 8'b00000000;
MODULE1[1285] <= 8'b00000000;
MODULE1[1286] <= 8'b00000000;
MODULE1[1287] <= 8'b00000000;
MODULE1[1288] <= 8'b00000000;
MODULE1[1289] <= 8'b11000000;
MODULE1[1290] <= 8'b00000001;
MODULE1[1291] <= 8'b10000000;
MODULE1[1292] <= 8'b00000011;
MODULE1[1293] <= 8'b00000000;
MODULE1[1294] <= 8'b00000011;
MODULE1[1295] <= 8'b00000000;
MODULE1[1296] <= 8'b00000011;
MODULE1[1297] <= 8'b00000000;
MODULE1[1298] <= 8'b00000011;
MODULE1[1299] <= 8'b00000000;
MODULE1[1300] <= 8'b00000011;
MODULE1[1301] <= 8'b00000000;
MODULE1[1302] <= 8'b00000011;
MODULE1[1303] <= 8'b00000000;
MODULE1[1304] <= 8'b00000011;
MODULE1[1305] <= 8'b00000000;
MODULE1[1306] <= 8'b00000001;
MODULE1[1307] <= 8'b10000000;
MODULE1[1308] <= 8'b00000000;
MODULE1[1309] <= 8'b11000000;
MODULE1[1310] <= 8'b00000000;
MODULE1[1311] <= 8'b00000000;
MODULE1[1312] <= 8'b00000000;
MODULE1[1313] <= 8'b00000000;
MODULE1[1314] <= 8'b00000000;
MODULE1[1315] <= 8'b00000000;
MODULE1[1316] <= 8'b00000000;
MODULE1[1317] <= 8'b00000000;
MODULE1[1318] <= 8'b00000000;
MODULE1[1319] <= 8'b00000000;
MODULE1[1320] <= 8'b00000011;
MODULE1[1321] <= 8'b00000000;
MODULE1[1322] <= 8'b00000011;
MODULE1[1323] <= 8'b10000000;
MODULE1[1324] <= 8'b00000001;
MODULE1[1325] <= 8'b10000000;
MODULE1[1326] <= 8'b00000001;
MODULE1[1327] <= 8'b10000000;
MODULE1[1328] <= 8'b00000000;
MODULE1[1329] <= 8'b11000000;
MODULE1[1330] <= 8'b00000000;
MODULE1[1331] <= 8'b11000000;
MODULE1[1332] <= 8'b00000000;
MODULE1[1333] <= 8'b11000000;
MODULE1[1334] <= 8'b00000000;
MODULE1[1335] <= 8'b10000000;
MODULE1[1336] <= 8'b00000001;
MODULE1[1337] <= 8'b10000000;
MODULE1[1338] <= 8'b00000001;
MODULE1[1339] <= 8'b10000000;
MODULE1[1340] <= 8'b00000011;
MODULE1[1341] <= 8'b00000000;
MODULE1[1342] <= 8'b00000000;
MODULE1[1343] <= 8'b00000000;
MODULE1[1344] <= 8'b00000000;
MODULE1[1345] <= 8'b00000000;
MODULE1[1346] <= 8'b00000000;
MODULE1[1347] <= 8'b00000000;
MODULE1[1348] <= 8'b00000000;
MODULE1[1349] <= 8'b00000000;
MODULE1[1350] <= 8'b00000000;
MODULE1[1351] <= 8'b00000000;
MODULE1[1352] <= 8'b00000000;
MODULE1[1353] <= 8'b00000000;
MODULE1[1354] <= 8'b00000011;
MODULE1[1355] <= 8'b00000000;
MODULE1[1356] <= 8'b00000111;
MODULE1[1357] <= 8'b11000000;
MODULE1[1358] <= 8'b00000011;
MODULE1[1359] <= 8'b10000000;
MODULE1[1360] <= 8'b00000110;
MODULE1[1361] <= 8'b11000000;
MODULE1[1362] <= 8'b00000000;
MODULE1[1363] <= 8'b00000000;
MODULE1[1364] <= 8'b00000000;
MODULE1[1365] <= 8'b00000000;
MODULE1[1366] <= 8'b00000000;
MODULE1[1367] <= 8'b00000000;
MODULE1[1368] <= 8'b00000000;
MODULE1[1369] <= 8'b00000000;
MODULE1[1370] <= 8'b00000000;
MODULE1[1371] <= 8'b00000000;
MODULE1[1372] <= 8'b00000000;
MODULE1[1373] <= 8'b00000000;
MODULE1[1374] <= 8'b00000000;
MODULE1[1375] <= 8'b00000000;
MODULE1[1376] <= 8'b00000000;
MODULE1[1377] <= 8'b00000000;
MODULE1[1378] <= 8'b00000000;
MODULE1[1379] <= 8'b00000000;
MODULE1[1380] <= 8'b00000000;
MODULE1[1381] <= 8'b00000000;
MODULE1[1382] <= 8'b00000000;
MODULE1[1383] <= 8'b00000000;
MODULE1[1384] <= 8'b00000000;
MODULE1[1385] <= 8'b00000000;
MODULE1[1386] <= 8'b00000000;
MODULE1[1387] <= 8'b00000000;
MODULE1[1388] <= 8'b00000000;
MODULE1[1389] <= 8'b00000000;
MODULE1[1390] <= 8'b00000001;
MODULE1[1391] <= 8'b10000000;
MODULE1[1392] <= 8'b00000001;
MODULE1[1393] <= 8'b10000000;
MODULE1[1394] <= 8'b00000111;
MODULE1[1395] <= 8'b11100000;
MODULE1[1396] <= 8'b00000001;
MODULE1[1397] <= 8'b10000000;
MODULE1[1398] <= 8'b00000001;
MODULE1[1399] <= 8'b10000000;
MODULE1[1400] <= 8'b00000000;
MODULE1[1401] <= 8'b00000000;
MODULE1[1402] <= 8'b00000000;
MODULE1[1403] <= 8'b00000000;
MODULE1[1404] <= 8'b00000000;
MODULE1[1405] <= 8'b00000000;
MODULE1[1406] <= 8'b00000000;
MODULE1[1407] <= 8'b00000000;
MODULE1[1408] <= 8'b00000000;
MODULE1[1409] <= 8'b00000000;
MODULE1[1410] <= 8'b00000000;
MODULE1[1411] <= 8'b00000000;
MODULE1[1412] <= 8'b00000000;
MODULE1[1413] <= 8'b00000000;
MODULE1[1414] <= 8'b00000000;
MODULE1[1415] <= 8'b00000000;
MODULE1[1416] <= 8'b00000000;
MODULE1[1417] <= 8'b00000000;
MODULE1[1418] <= 8'b00000000;
MODULE1[1419] <= 8'b00000000;
MODULE1[1420] <= 8'b00000000;
MODULE1[1421] <= 8'b00000000;
MODULE1[1422] <= 8'b00000000;
MODULE1[1423] <= 8'b00000000;
MODULE1[1424] <= 8'b00000000;
MODULE1[1425] <= 8'b00000000;
MODULE1[1426] <= 8'b00000000;
MODULE1[1427] <= 8'b00000000;
MODULE1[1428] <= 8'b00000000;
MODULE1[1429] <= 8'b00000000;
MODULE1[1430] <= 8'b00000000;
MODULE1[1431] <= 8'b00000000;
MODULE1[1432] <= 8'b00000001;
MODULE1[1433] <= 8'b10000000;
MODULE1[1434] <= 8'b00000011;
MODULE1[1435] <= 8'b00000000;
MODULE1[1436] <= 8'b00000000;
MODULE1[1437] <= 8'b00000000;
MODULE1[1438] <= 8'b00000000;
MODULE1[1439] <= 8'b00000000;
MODULE1[1440] <= 8'b00000000;
MODULE1[1441] <= 8'b00000000;
MODULE1[1442] <= 8'b00000000;
MODULE1[1443] <= 8'b00000000;
MODULE1[1444] <= 8'b00000000;
MODULE1[1445] <= 8'b00000000;
MODULE1[1446] <= 8'b00000000;
MODULE1[1447] <= 8'b00000000;
MODULE1[1448] <= 8'b00000000;
MODULE1[1449] <= 8'b00000000;
MODULE1[1450] <= 8'b00000000;
MODULE1[1451] <= 8'b00000000;
MODULE1[1452] <= 8'b00000000;
MODULE1[1453] <= 8'b00000000;
MODULE1[1454] <= 8'b00000000;
MODULE1[1455] <= 8'b00000000;
MODULE1[1456] <= 8'b00000000;
MODULE1[1457] <= 8'b00000000;
MODULE1[1458] <= 8'b00000000;
MODULE1[1459] <= 8'b00000000;
MODULE1[1460] <= 8'b00000011;
MODULE1[1461] <= 8'b11000000;
MODULE1[1462] <= 8'b00000000;
MODULE1[1463] <= 8'b00000000;
MODULE1[1464] <= 8'b00000000;
MODULE1[1465] <= 8'b00000000;
MODULE1[1466] <= 8'b00000000;
MODULE1[1467] <= 8'b00000000;
MODULE1[1468] <= 8'b00000000;
MODULE1[1469] <= 8'b00000000;
MODULE1[1470] <= 8'b00000000;
MODULE1[1471] <= 8'b00000000;
MODULE1[1472] <= 8'b00000000;
MODULE1[1473] <= 8'b00000000;
MODULE1[1474] <= 8'b00000000;
MODULE1[1475] <= 8'b00000000;
MODULE1[1476] <= 8'b00000000;
MODULE1[1477] <= 8'b00000000;
MODULE1[1478] <= 8'b00000000;
MODULE1[1479] <= 8'b00000000;
MODULE1[1480] <= 8'b00000000;
MODULE1[1481] <= 8'b00000000;
MODULE1[1482] <= 8'b00000000;
MODULE1[1483] <= 8'b00000000;
MODULE1[1484] <= 8'b00000000;
MODULE1[1485] <= 8'b00000000;
MODULE1[1486] <= 8'b00000000;
MODULE1[1487] <= 8'b00000000;
MODULE1[1488] <= 8'b00000000;
MODULE1[1489] <= 8'b00000000;
MODULE1[1490] <= 8'b00000000;
MODULE1[1491] <= 8'b00000000;
MODULE1[1492] <= 8'b00000000;
MODULE1[1493] <= 8'b00000000;
MODULE1[1494] <= 8'b00000000;
MODULE1[1495] <= 8'b00000000;
MODULE1[1496] <= 8'b00000011;
MODULE1[1497] <= 8'b00000000;
MODULE1[1498] <= 8'b00000000;
MODULE1[1499] <= 8'b00000000;
MODULE1[1500] <= 8'b00000000;
MODULE1[1501] <= 8'b00000000;
MODULE1[1502] <= 8'b00000000;
MODULE1[1503] <= 8'b00000000;
MODULE1[1504] <= 8'b00000000;
MODULE1[1505] <= 8'b00000000;
MODULE1[1506] <= 8'b00000000;
MODULE1[1507] <= 8'b00000000;
MODULE1[1508] <= 8'b00000000;
MODULE1[1509] <= 8'b00000000;
MODULE1[1510] <= 8'b00000000;
MODULE1[1511] <= 8'b00000000;
MODULE1[1512] <= 8'b00000000;
MODULE1[1513] <= 8'b11000000;
MODULE1[1514] <= 8'b00000000;
MODULE1[1515] <= 8'b11000000;
MODULE1[1516] <= 8'b00000000;
MODULE1[1517] <= 8'b10000000;
MODULE1[1518] <= 8'b00000001;
MODULE1[1519] <= 8'b10000000;
MODULE1[1520] <= 8'b00000001;
MODULE1[1521] <= 8'b00000000;
MODULE1[1522] <= 8'b00000011;
MODULE1[1523] <= 8'b00000000;
MODULE1[1524] <= 8'b00000010;
MODULE1[1525] <= 8'b00000000;
MODULE1[1526] <= 8'b00000110;
MODULE1[1527] <= 8'b00000000;
MODULE1[1528] <= 8'b00000110;
MODULE1[1529] <= 8'b00000000;
MODULE1[1530] <= 8'b00000000;
MODULE1[1531] <= 8'b00000000;
MODULE1[1532] <= 8'b00000000;
MODULE1[1533] <= 8'b00000000;
MODULE1[1534] <= 8'b00000000;
MODULE1[1535] <= 8'b00000000;
MODULE1[1536] <= 8'b00000000;
MODULE1[1537] <= 8'b00000000;
MODULE1[1538] <= 8'b00000000;
MODULE1[1539] <= 8'b00000000;
MODULE1[1540] <= 8'b00000000;
MODULE1[1541] <= 8'b00000000;
MODULE1[1542] <= 8'b00000000;
MODULE1[1543] <= 8'b00000000;
MODULE1[1544] <= 8'b00000000;
MODULE1[1545] <= 8'b00000000;
MODULE1[1546] <= 8'b00000111;
MODULE1[1547] <= 8'b11000000;
MODULE1[1548] <= 8'b00001100;
MODULE1[1549] <= 8'b11000000;
MODULE1[1550] <= 8'b00001100;
MODULE1[1551] <= 8'b01000000;
MODULE1[1552] <= 8'b00001000;
MODULE1[1553] <= 8'b01100000;
MODULE1[1554] <= 8'b00001000;
MODULE1[1555] <= 8'b01100000;
MODULE1[1556] <= 8'b00001100;
MODULE1[1557] <= 8'b11000000;
MODULE1[1558] <= 8'b00001100;
MODULE1[1559] <= 8'b11000000;
MODULE1[1560] <= 8'b00000111;
MODULE1[1561] <= 8'b11000000;
MODULE1[1562] <= 8'b00000000;
MODULE1[1563] <= 8'b00000000;
MODULE1[1564] <= 8'b00000000;
MODULE1[1565] <= 8'b00000000;
MODULE1[1566] <= 8'b00000000;
MODULE1[1567] <= 8'b00000000;
MODULE1[1568] <= 8'b00000000;
MODULE1[1569] <= 8'b00000000;
MODULE1[1570] <= 8'b00000000;
MODULE1[1571] <= 8'b00000000;
MODULE1[1572] <= 8'b00000000;
MODULE1[1573] <= 8'b00000000;
MODULE1[1574] <= 8'b00000000;
MODULE1[1575] <= 8'b00000000;
MODULE1[1576] <= 8'b00000000;
MODULE1[1577] <= 8'b00000000;
MODULE1[1578] <= 8'b00000001;
MODULE1[1579] <= 8'b10000000;
MODULE1[1580] <= 8'b00000011;
MODULE1[1581] <= 8'b10000000;
MODULE1[1582] <= 8'b00000000;
MODULE1[1583] <= 8'b10000000;
MODULE1[1584] <= 8'b00000001;
MODULE1[1585] <= 8'b10000000;
MODULE1[1586] <= 8'b00000001;
MODULE1[1587] <= 8'b10000000;
MODULE1[1588] <= 8'b00000001;
MODULE1[1589] <= 8'b10000000;
MODULE1[1590] <= 8'b00000001;
MODULE1[1591] <= 8'b10000000;
MODULE1[1592] <= 8'b00000011;
MODULE1[1593] <= 8'b11000000;
MODULE1[1594] <= 8'b00000000;
MODULE1[1595] <= 8'b00000000;
MODULE1[1596] <= 8'b00000000;
MODULE1[1597] <= 8'b00000000;
MODULE1[1598] <= 8'b00000000;
MODULE1[1599] <= 8'b00000000;
MODULE1[1600] <= 8'b00000000;
MODULE1[1601] <= 8'b00000000;
MODULE1[1602] <= 8'b00000000;
MODULE1[1603] <= 8'b00000000;
MODULE1[1604] <= 8'b00000000;
MODULE1[1605] <= 8'b00000000;
MODULE1[1606] <= 8'b00000000;
MODULE1[1607] <= 8'b00000000;
MODULE1[1608] <= 8'b00000000;
MODULE1[1609] <= 8'b00000000;
MODULE1[1610] <= 8'b00000111;
MODULE1[1611] <= 8'b10000000;
MODULE1[1612] <= 8'b00001100;
MODULE1[1613] <= 8'b11000000;
MODULE1[1614] <= 8'b00000000;
MODULE1[1615] <= 8'b11000000;
MODULE1[1616] <= 8'b00000001;
MODULE1[1617] <= 8'b11000000;
MODULE1[1618] <= 8'b00000011;
MODULE1[1619] <= 8'b00000000;
MODULE1[1620] <= 8'b00000110;
MODULE1[1621] <= 8'b00000000;
MODULE1[1622] <= 8'b00001100;
MODULE1[1623] <= 8'b00000000;
MODULE1[1624] <= 8'b00001111;
MODULE1[1625] <= 8'b11000000;
MODULE1[1626] <= 8'b00000000;
MODULE1[1627] <= 8'b00000000;
MODULE1[1628] <= 8'b00000000;
MODULE1[1629] <= 8'b00000000;
MODULE1[1630] <= 8'b00000000;
MODULE1[1631] <= 8'b00000000;
MODULE1[1632] <= 8'b00000000;
MODULE1[1633] <= 8'b00000000;
MODULE1[1634] <= 8'b00000000;
MODULE1[1635] <= 8'b00000000;
MODULE1[1636] <= 8'b00000000;
MODULE1[1637] <= 8'b00000000;
MODULE1[1638] <= 8'b00000000;
MODULE1[1639] <= 8'b00000000;
MODULE1[1640] <= 8'b00000000;
MODULE1[1641] <= 8'b00000000;
MODULE1[1642] <= 8'b00000111;
MODULE1[1643] <= 8'b10000000;
MODULE1[1644] <= 8'b00001100;
MODULE1[1645] <= 8'b11000000;
MODULE1[1646] <= 8'b00000000;
MODULE1[1647] <= 8'b11000000;
MODULE1[1648] <= 8'b00000011;
MODULE1[1649] <= 8'b10000000;
MODULE1[1650] <= 8'b00000000;
MODULE1[1651] <= 8'b11000000;
MODULE1[1652] <= 8'b00000000;
MODULE1[1653] <= 8'b11000000;
MODULE1[1654] <= 8'b00001100;
MODULE1[1655] <= 8'b11000000;
MODULE1[1656] <= 8'b00000111;
MODULE1[1657] <= 8'b10000000;
MODULE1[1658] <= 8'b00000000;
MODULE1[1659] <= 8'b00000000;
MODULE1[1660] <= 8'b00000000;
MODULE1[1661] <= 8'b00000000;
MODULE1[1662] <= 8'b00000000;
MODULE1[1663] <= 8'b00000000;
MODULE1[1664] <= 8'b00000000;
MODULE1[1665] <= 8'b00000000;
MODULE1[1666] <= 8'b00000000;
MODULE1[1667] <= 8'b00000000;
MODULE1[1668] <= 8'b00000000;
MODULE1[1669] <= 8'b00000000;
MODULE1[1670] <= 8'b00000000;
MODULE1[1671] <= 8'b00000000;
MODULE1[1672] <= 8'b00000000;
MODULE1[1673] <= 8'b00000000;
MODULE1[1674] <= 8'b00000001;
MODULE1[1675] <= 8'b10000000;
MODULE1[1676] <= 8'b00000011;
MODULE1[1677] <= 8'b10000000;
MODULE1[1678] <= 8'b00000011;
MODULE1[1679] <= 8'b10000000;
MODULE1[1680] <= 8'b00000110;
MODULE1[1681] <= 8'b10000000;
MODULE1[1682] <= 8'b00001100;
MODULE1[1683] <= 8'b10000000;
MODULE1[1684] <= 8'b00001111;
MODULE1[1685] <= 8'b11100000;
MODULE1[1686] <= 8'b00000000;
MODULE1[1687] <= 8'b10000000;
MODULE1[1688] <= 8'b00000000;
MODULE1[1689] <= 8'b10000000;
MODULE1[1690] <= 8'b00000000;
MODULE1[1691] <= 8'b00000000;
MODULE1[1692] <= 8'b00000000;
MODULE1[1693] <= 8'b00000000;
MODULE1[1694] <= 8'b00000000;
MODULE1[1695] <= 8'b00000000;
MODULE1[1696] <= 8'b00000000;
MODULE1[1697] <= 8'b00000000;
MODULE1[1698] <= 8'b00000000;
MODULE1[1699] <= 8'b00000000;
MODULE1[1700] <= 8'b00000000;
MODULE1[1701] <= 8'b00000000;
MODULE1[1702] <= 8'b00000000;
MODULE1[1703] <= 8'b00000000;
MODULE1[1704] <= 8'b00000000;
MODULE1[1705] <= 8'b00000000;
MODULE1[1706] <= 8'b00001111;
MODULE1[1707] <= 8'b11000000;
MODULE1[1708] <= 8'b00001100;
MODULE1[1709] <= 8'b00000000;
MODULE1[1710] <= 8'b00001111;
MODULE1[1711] <= 8'b11000000;
MODULE1[1712] <= 8'b00001100;
MODULE1[1713] <= 8'b11000000;
MODULE1[1714] <= 8'b00000000;
MODULE1[1715] <= 8'b01100000;
MODULE1[1716] <= 8'b00000000;
MODULE1[1717] <= 8'b01100000;
MODULE1[1718] <= 8'b00001100;
MODULE1[1719] <= 8'b11000000;
MODULE1[1720] <= 8'b00000111;
MODULE1[1721] <= 8'b10000000;
MODULE1[1722] <= 8'b00000000;
MODULE1[1723] <= 8'b00000000;
MODULE1[1724] <= 8'b00000000;
MODULE1[1725] <= 8'b00000000;
MODULE1[1726] <= 8'b00000000;
MODULE1[1727] <= 8'b00000000;
MODULE1[1728] <= 8'b00000000;
MODULE1[1729] <= 8'b00000000;
MODULE1[1730] <= 8'b00000000;
MODULE1[1731] <= 8'b00000000;
MODULE1[1732] <= 8'b00000000;
MODULE1[1733] <= 8'b00000000;
MODULE1[1734] <= 8'b00000000;
MODULE1[1735] <= 8'b00000000;
MODULE1[1736] <= 8'b00000000;
MODULE1[1737] <= 8'b00000000;
MODULE1[1738] <= 8'b00000011;
MODULE1[1739] <= 8'b10000000;
MODULE1[1740] <= 8'b00000111;
MODULE1[1741] <= 8'b00000000;
MODULE1[1742] <= 8'b00000110;
MODULE1[1743] <= 8'b00000000;
MODULE1[1744] <= 8'b00001111;
MODULE1[1745] <= 8'b10000000;
MODULE1[1746] <= 8'b00001100;
MODULE1[1747] <= 8'b11000000;
MODULE1[1748] <= 8'b00001100;
MODULE1[1749] <= 8'b11000000;
MODULE1[1750] <= 8'b00001100;
MODULE1[1751] <= 8'b11000000;
MODULE1[1752] <= 8'b00000111;
MODULE1[1753] <= 8'b10000000;
MODULE1[1754] <= 8'b00000000;
MODULE1[1755] <= 8'b00000000;
MODULE1[1756] <= 8'b00000000;
MODULE1[1757] <= 8'b00000000;
MODULE1[1758] <= 8'b00000000;
MODULE1[1759] <= 8'b00000000;
MODULE1[1760] <= 8'b00000000;
MODULE1[1761] <= 8'b00000000;
MODULE1[1762] <= 8'b00000000;
MODULE1[1763] <= 8'b00000000;
MODULE1[1764] <= 8'b00000000;
MODULE1[1765] <= 8'b00000000;
MODULE1[1766] <= 8'b00000000;
MODULE1[1767] <= 8'b00000000;
MODULE1[1768] <= 8'b00000000;
MODULE1[1769] <= 8'b00000000;
MODULE1[1770] <= 8'b00001111;
MODULE1[1771] <= 8'b11100000;
MODULE1[1772] <= 8'b00000000;
MODULE1[1773] <= 8'b11000000;
MODULE1[1774] <= 8'b00000001;
MODULE1[1775] <= 8'b10000000;
MODULE1[1776] <= 8'b00000011;
MODULE1[1777] <= 8'b00000000;
MODULE1[1778] <= 8'b00000011;
MODULE1[1779] <= 8'b00000000;
MODULE1[1780] <= 8'b00000011;
MODULE1[1781] <= 8'b00000000;
MODULE1[1782] <= 8'b00000110;
MODULE1[1783] <= 8'b00000000;
MODULE1[1784] <= 8'b00000110;
MODULE1[1785] <= 8'b00000000;
MODULE1[1786] <= 8'b00000000;
MODULE1[1787] <= 8'b00000000;
MODULE1[1788] <= 8'b00000000;
MODULE1[1789] <= 8'b00000000;
MODULE1[1790] <= 8'b00000000;
MODULE1[1791] <= 8'b00000000;
MODULE1[1792] <= 8'b00000000;
MODULE1[1793] <= 8'b00000000;
MODULE1[1794] <= 8'b00000000;
MODULE1[1795] <= 8'b00000000;
MODULE1[1796] <= 8'b00000000;
MODULE1[1797] <= 8'b00000000;
MODULE1[1798] <= 8'b00000000;
MODULE1[1799] <= 8'b00000000;
MODULE1[1800] <= 8'b00000000;
MODULE1[1801] <= 8'b00000000;
MODULE1[1802] <= 8'b00000111;
MODULE1[1803] <= 8'b10000000;
MODULE1[1804] <= 8'b00001100;
MODULE1[1805] <= 8'b11000000;
MODULE1[1806] <= 8'b00001100;
MODULE1[1807] <= 8'b11000000;
MODULE1[1808] <= 8'b00000111;
MODULE1[1809] <= 8'b10000000;
MODULE1[1810] <= 8'b00001100;
MODULE1[1811] <= 8'b11000000;
MODULE1[1812] <= 8'b00001100;
MODULE1[1813] <= 8'b11000000;
MODULE1[1814] <= 8'b00001100;
MODULE1[1815] <= 8'b11000000;
MODULE1[1816] <= 8'b00000111;
MODULE1[1817] <= 8'b10000000;
MODULE1[1818] <= 8'b00000000;
MODULE1[1819] <= 8'b00000000;
MODULE1[1820] <= 8'b00000000;
MODULE1[1821] <= 8'b00000000;
MODULE1[1822] <= 8'b00000000;
MODULE1[1823] <= 8'b00000000;
MODULE1[1824] <= 8'b00000000;
MODULE1[1825] <= 8'b00000000;
MODULE1[1826] <= 8'b00000000;
MODULE1[1827] <= 8'b00000000;
MODULE1[1828] <= 8'b00000000;
MODULE1[1829] <= 8'b00000000;
MODULE1[1830] <= 8'b00000000;
MODULE1[1831] <= 8'b00000000;
MODULE1[1832] <= 8'b00000000;
MODULE1[1833] <= 8'b00000000;
MODULE1[1834] <= 8'b00000111;
MODULE1[1835] <= 8'b10000000;
MODULE1[1836] <= 8'b00001100;
MODULE1[1837] <= 8'b11000000;
MODULE1[1838] <= 8'b00001100;
MODULE1[1839] <= 8'b01100000;
MODULE1[1840] <= 8'b00001100;
MODULE1[1841] <= 8'b01100000;
MODULE1[1842] <= 8'b00000111;
MODULE1[1843] <= 8'b11000000;
MODULE1[1844] <= 8'b00000000;
MODULE1[1845] <= 8'b11000000;
MODULE1[1846] <= 8'b00000011;
MODULE1[1847] <= 8'b10000000;
MODULE1[1848] <= 8'b00001110;
MODULE1[1849] <= 8'b00000000;
MODULE1[1850] <= 8'b00000000;
MODULE1[1851] <= 8'b00000000;
MODULE1[1852] <= 8'b00000000;
MODULE1[1853] <= 8'b00000000;
MODULE1[1854] <= 8'b00000000;
MODULE1[1855] <= 8'b00000000;
MODULE1[1856] <= 8'b00000000;
MODULE1[1857] <= 8'b00000000;
MODULE1[1858] <= 8'b00000000;
MODULE1[1859] <= 8'b00000000;
MODULE1[1860] <= 8'b00000000;
MODULE1[1861] <= 8'b00000000;
MODULE1[1862] <= 8'b00000000;
MODULE1[1863] <= 8'b00000000;
MODULE1[1864] <= 8'b00000000;
MODULE1[1865] <= 8'b00000000;
MODULE1[1866] <= 8'b00000000;
MODULE1[1867] <= 8'b00000000;
MODULE1[1868] <= 8'b00000000;
MODULE1[1869] <= 8'b00000000;
MODULE1[1870] <= 8'b00000011;
MODULE1[1871] <= 8'b00000000;
MODULE1[1872] <= 8'b00000000;
MODULE1[1873] <= 8'b00000000;
MODULE1[1874] <= 8'b00000000;
MODULE1[1875] <= 8'b00000000;
MODULE1[1876] <= 8'b00000000;
MODULE1[1877] <= 8'b00000000;
MODULE1[1878] <= 8'b00000011;
MODULE1[1879] <= 8'b00000000;
MODULE1[1880] <= 8'b00000000;
MODULE1[1881] <= 8'b00000000;
MODULE1[1882] <= 8'b00000000;
MODULE1[1883] <= 8'b00000000;
MODULE1[1884] <= 8'b00000000;
MODULE1[1885] <= 8'b00000000;
MODULE1[1886] <= 8'b00000000;
MODULE1[1887] <= 8'b00000000;
MODULE1[1888] <= 8'b00000000;
MODULE1[1889] <= 8'b00000000;
MODULE1[1890] <= 8'b00000000;
MODULE1[1891] <= 8'b00000000;
MODULE1[1892] <= 8'b00000000;
MODULE1[1893] <= 8'b00000000;
MODULE1[1894] <= 8'b00000000;
MODULE1[1895] <= 8'b00000000;
MODULE1[1896] <= 8'b00000000;
MODULE1[1897] <= 8'b00000000;
MODULE1[1898] <= 8'b00000000;
MODULE1[1899] <= 8'b00000000;
MODULE1[1900] <= 8'b00000000;
MODULE1[1901] <= 8'b00000000;
MODULE1[1902] <= 8'b00000011;
MODULE1[1903] <= 8'b00000000;
MODULE1[1904] <= 8'b00000000;
MODULE1[1905] <= 8'b00000000;
MODULE1[1906] <= 8'b00000000;
MODULE1[1907] <= 8'b00000000;
MODULE1[1908] <= 8'b00000000;
MODULE1[1909] <= 8'b00000000;
MODULE1[1910] <= 8'b00000000;
MODULE1[1911] <= 8'b00000000;
MODULE1[1912] <= 8'b00000011;
MODULE1[1913] <= 8'b00000000;
MODULE1[1914] <= 8'b00000010;
MODULE1[1915] <= 8'b00000000;
MODULE1[1916] <= 8'b00000000;
MODULE1[1917] <= 8'b00000000;
MODULE1[1918] <= 8'b00000000;
MODULE1[1919] <= 8'b00000000;
MODULE1[1920] <= 8'b00000000;
MODULE1[1921] <= 8'b00000000;
MODULE1[1922] <= 8'b00000000;
MODULE1[1923] <= 8'b00000000;
MODULE1[1924] <= 8'b00000000;
MODULE1[1925] <= 8'b00000000;
MODULE1[1926] <= 8'b00000000;
MODULE1[1927] <= 8'b00000000;
MODULE1[1928] <= 8'b00000000;
MODULE1[1929] <= 8'b00000000;
MODULE1[1930] <= 8'b00000000;
MODULE1[1931] <= 8'b00000000;
MODULE1[1932] <= 8'b00000000;
MODULE1[1933] <= 8'b00000000;
MODULE1[1934] <= 8'b00000001;
MODULE1[1935] <= 8'b10000000;
MODULE1[1936] <= 8'b00000011;
MODULE1[1937] <= 8'b10000000;
MODULE1[1938] <= 8'b00000111;
MODULE1[1939] <= 8'b00000000;
MODULE1[1940] <= 8'b00000011;
MODULE1[1941] <= 8'b00000000;
MODULE1[1942] <= 8'b00000001;
MODULE1[1943] <= 8'b10000000;
MODULE1[1944] <= 8'b00000000;
MODULE1[1945] <= 8'b00000000;
MODULE1[1946] <= 8'b00000000;
MODULE1[1947] <= 8'b00000000;
MODULE1[1948] <= 8'b00000000;
MODULE1[1949] <= 8'b00000000;
MODULE1[1950] <= 8'b00000000;
MODULE1[1951] <= 8'b00000000;
MODULE1[1952] <= 8'b00000000;
MODULE1[1953] <= 8'b00000000;
MODULE1[1954] <= 8'b00000000;
MODULE1[1955] <= 8'b00000000;
MODULE1[1956] <= 8'b00000000;
MODULE1[1957] <= 8'b00000000;
MODULE1[1958] <= 8'b00000000;
MODULE1[1959] <= 8'b00000000;
MODULE1[1960] <= 8'b00000000;
MODULE1[1961] <= 8'b00000000;
MODULE1[1962] <= 8'b00000000;
MODULE1[1963] <= 8'b00000000;
MODULE1[1964] <= 8'b00000000;
MODULE1[1965] <= 8'b00000000;
MODULE1[1966] <= 8'b00000111;
MODULE1[1967] <= 8'b11000000;
MODULE1[1968] <= 8'b00000000;
MODULE1[1969] <= 8'b00000000;
MODULE1[1970] <= 8'b00000000;
MODULE1[1971] <= 8'b00000000;
MODULE1[1972] <= 8'b00000111;
MODULE1[1973] <= 8'b11000000;
MODULE1[1974] <= 8'b00000000;
MODULE1[1975] <= 8'b00000000;
MODULE1[1976] <= 8'b00000000;
MODULE1[1977] <= 8'b00000000;
MODULE1[1978] <= 8'b00000000;
MODULE1[1979] <= 8'b00000000;
MODULE1[1980] <= 8'b00000000;
MODULE1[1981] <= 8'b00000000;
MODULE1[1982] <= 8'b00000000;
MODULE1[1983] <= 8'b00000000;
MODULE1[1984] <= 8'b00000000;
MODULE1[1985] <= 8'b00000000;
MODULE1[1986] <= 8'b00000000;
MODULE1[1987] <= 8'b00000000;
MODULE1[1988] <= 8'b00000000;
MODULE1[1989] <= 8'b00000000;
MODULE1[1990] <= 8'b00000000;
MODULE1[1991] <= 8'b00000000;
MODULE1[1992] <= 8'b00000000;
MODULE1[1993] <= 8'b00000000;
MODULE1[1994] <= 8'b00000000;
MODULE1[1995] <= 8'b00000000;
MODULE1[1996] <= 8'b00000000;
MODULE1[1997] <= 8'b00000000;
MODULE1[1998] <= 8'b00000011;
MODULE1[1999] <= 8'b00000000;
MODULE1[2000] <= 8'b00000001;
MODULE1[2001] <= 8'b10000000;
MODULE1[2002] <= 8'b00000000;
MODULE1[2003] <= 8'b11000000;
MODULE1[2004] <= 8'b00000001;
MODULE1[2005] <= 8'b10000000;
MODULE1[2006] <= 8'b00000011;
MODULE1[2007] <= 8'b00000000;
MODULE1[2008] <= 8'b00000000;
MODULE1[2009] <= 8'b00000000;
MODULE1[2010] <= 8'b00000000;
MODULE1[2011] <= 8'b00000000;
MODULE1[2012] <= 8'b00000000;
MODULE1[2013] <= 8'b00000000;
MODULE1[2014] <= 8'b00000000;
MODULE1[2015] <= 8'b00000000;
MODULE1[2016] <= 8'b00000000;
MODULE1[2017] <= 8'b00000000;
MODULE1[2018] <= 8'b00000000;
MODULE1[2019] <= 8'b00000000;
MODULE1[2020] <= 8'b00000000;
MODULE1[2021] <= 8'b00000000;
MODULE1[2022] <= 8'b00000000;
MODULE1[2023] <= 8'b00000000;
MODULE1[2024] <= 8'b00000000;
MODULE1[2025] <= 8'b00000000;
MODULE1[2026] <= 8'b00000111;
MODULE1[2027] <= 8'b10000000;
MODULE1[2028] <= 8'b00000000;
MODULE1[2029] <= 8'b11000000;
MODULE1[2030] <= 8'b00000000;
MODULE1[2031] <= 8'b01000000;
MODULE1[2032] <= 8'b00000000;
MODULE1[2033] <= 8'b11000000;
MODULE1[2034] <= 8'b00000011;
MODULE1[2035] <= 8'b10000000;
MODULE1[2036] <= 8'b00000011;
MODULE1[2037] <= 8'b00000000;
MODULE1[2038] <= 8'b00000000;
MODULE1[2039] <= 8'b00000000;
MODULE1[2040] <= 8'b00000110;
MODULE1[2041] <= 8'b00000000;
MODULE1[2042] <= 8'b00000000;
MODULE1[2043] <= 8'b00000000;
MODULE1[2044] <= 8'b00000000;
MODULE1[2045] <= 8'b00000000;
MODULE1[2046] <= 8'b00000000;
MODULE1[2047] <= 8'b00000000;
MODULE1[2048] <= 8'b00000000;
MODULE1[2049] <= 8'b00000000;
MODULE1[2050] <= 8'b00000000;
MODULE1[2051] <= 8'b00000000;
MODULE1[2052] <= 8'b00000000;
MODULE1[2053] <= 8'b00000000;
MODULE1[2054] <= 8'b00000000;
MODULE1[2055] <= 8'b00000000;
MODULE1[2056] <= 8'b00000111;
MODULE1[2057] <= 8'b11000000;
MODULE1[2058] <= 8'b00001100;
MODULE1[2059] <= 8'b01100000;
MODULE1[2060] <= 8'b00011011;
MODULE1[2061] <= 8'b10110000;
MODULE1[2062] <= 8'b00011111;
MODULE1[2063] <= 8'b10110000;
MODULE1[2064] <= 8'b00011111;
MODULE1[2065] <= 8'b10110000;
MODULE1[2066] <= 8'b00011111;
MODULE1[2067] <= 8'b11110000;
MODULE1[2068] <= 8'b00011000;
MODULE1[2069] <= 8'b00000000;
MODULE1[2070] <= 8'b00001100;
MODULE1[2071] <= 8'b01100000;
MODULE1[2072] <= 8'b00000111;
MODULE1[2073] <= 8'b11000000;
MODULE1[2074] <= 8'b00000000;
MODULE1[2075] <= 8'b00000000;
MODULE1[2076] <= 8'b00000000;
MODULE1[2077] <= 8'b00000000;
MODULE1[2078] <= 8'b00000000;
MODULE1[2079] <= 8'b00000000;
MODULE1[2080] <= 8'b00000000;
MODULE1[2081] <= 8'b00000000;
MODULE1[2082] <= 8'b00000000;
MODULE1[2083] <= 8'b00000000;
MODULE1[2084] <= 8'b00000000;
MODULE1[2085] <= 8'b00000000;
MODULE1[2086] <= 8'b00000000;
MODULE1[2087] <= 8'b00000000;
MODULE1[2088] <= 8'b00000000;
MODULE1[2089] <= 8'b00000000;
MODULE1[2090] <= 8'b00000000;
MODULE1[2091] <= 8'b11000000;
MODULE1[2092] <= 8'b00000001;
MODULE1[2093] <= 8'b11000000;
MODULE1[2094] <= 8'b00000011;
MODULE1[2095] <= 8'b11000000;
MODULE1[2096] <= 8'b00000011;
MODULE1[2097] <= 8'b11000000;
MODULE1[2098] <= 8'b00000111;
MODULE1[2099] <= 8'b11100000;
MODULE1[2100] <= 8'b00000110;
MODULE1[2101] <= 8'b01100000;
MODULE1[2102] <= 8'b00001100;
MODULE1[2103] <= 8'b01100000;
MODULE1[2104] <= 8'b00001100;
MODULE1[2105] <= 8'b01100000;
MODULE1[2106] <= 8'b00000000;
MODULE1[2107] <= 8'b00000000;
MODULE1[2108] <= 8'b00000000;
MODULE1[2109] <= 8'b00000000;
MODULE1[2110] <= 8'b00000000;
MODULE1[2111] <= 8'b00000000;
MODULE1[2112] <= 8'b00000000;
MODULE1[2113] <= 8'b00000000;
MODULE1[2114] <= 8'b00000000;
MODULE1[2115] <= 8'b00000000;
MODULE1[2116] <= 8'b00000000;
MODULE1[2117] <= 8'b00000000;
MODULE1[2118] <= 8'b00000000;
MODULE1[2119] <= 8'b00000000;
MODULE1[2120] <= 8'b00000000;
MODULE1[2121] <= 8'b00000000;
MODULE1[2122] <= 8'b00000111;
MODULE1[2123] <= 8'b10000000;
MODULE1[2124] <= 8'b00001100;
MODULE1[2125] <= 8'b11000000;
MODULE1[2126] <= 8'b00001100;
MODULE1[2127] <= 8'b11000000;
MODULE1[2128] <= 8'b00001100;
MODULE1[2129] <= 8'b11000000;
MODULE1[2130] <= 8'b00001111;
MODULE1[2131] <= 8'b10000000;
MODULE1[2132] <= 8'b00001100;
MODULE1[2133] <= 8'b11100000;
MODULE1[2134] <= 8'b00001100;
MODULE1[2135] <= 8'b11000000;
MODULE1[2136] <= 8'b00001111;
MODULE1[2137] <= 8'b10000000;
MODULE1[2138] <= 8'b00000000;
MODULE1[2139] <= 8'b00000000;
MODULE1[2140] <= 8'b00000000;
MODULE1[2141] <= 8'b00000000;
MODULE1[2142] <= 8'b00000000;
MODULE1[2143] <= 8'b00000000;
MODULE1[2144] <= 8'b00000000;
MODULE1[2145] <= 8'b00000000;
MODULE1[2146] <= 8'b00000000;
MODULE1[2147] <= 8'b00000000;
MODULE1[2148] <= 8'b00000000;
MODULE1[2149] <= 8'b00000000;
MODULE1[2150] <= 8'b00000000;
MODULE1[2151] <= 8'b00000000;
MODULE1[2152] <= 8'b00000000;
MODULE1[2153] <= 8'b00000000;
MODULE1[2154] <= 8'b00000011;
MODULE1[2155] <= 8'b11100000;
MODULE1[2156] <= 8'b00000111;
MODULE1[2157] <= 8'b01100000;
MODULE1[2158] <= 8'b00000110;
MODULE1[2159] <= 8'b00000000;
MODULE1[2160] <= 8'b00001100;
MODULE1[2161] <= 8'b00000000;
MODULE1[2162] <= 8'b00001100;
MODULE1[2163] <= 8'b00000000;
MODULE1[2164] <= 8'b00001100;
MODULE1[2165] <= 8'b00000000;
MODULE1[2166] <= 8'b00001100;
MODULE1[2167] <= 8'b11000000;
MODULE1[2168] <= 8'b00000111;
MODULE1[2169] <= 8'b10000000;
MODULE1[2170] <= 8'b00000000;
MODULE1[2171] <= 8'b00000000;
MODULE1[2172] <= 8'b00000000;
MODULE1[2173] <= 8'b00000000;
MODULE1[2174] <= 8'b00000000;
MODULE1[2175] <= 8'b00000000;
MODULE1[2176] <= 8'b00000000;
MODULE1[2177] <= 8'b00000000;
MODULE1[2178] <= 8'b00000000;
MODULE1[2179] <= 8'b00000000;
MODULE1[2180] <= 8'b00000000;
MODULE1[2181] <= 8'b00000000;
MODULE1[2182] <= 8'b00000000;
MODULE1[2183] <= 8'b00000000;
MODULE1[2184] <= 8'b00000000;
MODULE1[2185] <= 8'b00000000;
MODULE1[2186] <= 8'b00001110;
MODULE1[2187] <= 8'b00000000;
MODULE1[2188] <= 8'b00001111;
MODULE1[2189] <= 8'b10000000;
MODULE1[2190] <= 8'b00001100;
MODULE1[2191] <= 8'b11100000;
MODULE1[2192] <= 8'b00001100;
MODULE1[2193] <= 8'b01100000;
MODULE1[2194] <= 8'b00001100;
MODULE1[2195] <= 8'b00100000;
MODULE1[2196] <= 8'b00001100;
MODULE1[2197] <= 8'b01100000;
MODULE1[2198] <= 8'b00001100;
MODULE1[2199] <= 8'b01100000;
MODULE1[2200] <= 8'b00000111;
MODULE1[2201] <= 8'b11000000;
MODULE1[2202] <= 8'b00000000;
MODULE1[2203] <= 8'b00000000;
MODULE1[2204] <= 8'b00000000;
MODULE1[2205] <= 8'b00000000;
MODULE1[2206] <= 8'b00000000;
MODULE1[2207] <= 8'b00000000;
MODULE1[2208] <= 8'b00000000;
MODULE1[2209] <= 8'b00000000;
MODULE1[2210] <= 8'b00000000;
MODULE1[2211] <= 8'b00000000;
MODULE1[2212] <= 8'b00000000;
MODULE1[2213] <= 8'b00000000;
MODULE1[2214] <= 8'b00000000;
MODULE1[2215] <= 8'b00000000;
MODULE1[2216] <= 8'b00000000;
MODULE1[2217] <= 8'b00000000;
MODULE1[2218] <= 8'b00001111;
MODULE1[2219] <= 8'b11100000;
MODULE1[2220] <= 8'b00001100;
MODULE1[2221] <= 8'b00000000;
MODULE1[2222] <= 8'b00001100;
MODULE1[2223] <= 8'b00000000;
MODULE1[2224] <= 8'b00001111;
MODULE1[2225] <= 8'b11000000;
MODULE1[2226] <= 8'b00001100;
MODULE1[2227] <= 8'b00000000;
MODULE1[2228] <= 8'b00001100;
MODULE1[2229] <= 8'b00000000;
MODULE1[2230] <= 8'b00001100;
MODULE1[2231] <= 8'b00000000;
MODULE1[2232] <= 8'b00001111;
MODULE1[2233] <= 8'b11000000;
MODULE1[2234] <= 8'b00000000;
MODULE1[2235] <= 8'b00000000;
MODULE1[2236] <= 8'b00000000;
MODULE1[2237] <= 8'b00000000;
MODULE1[2238] <= 8'b00000000;
MODULE1[2239] <= 8'b00000000;
MODULE1[2240] <= 8'b00000000;
MODULE1[2241] <= 8'b00000000;
MODULE1[2242] <= 8'b00000000;
MODULE1[2243] <= 8'b00000000;
MODULE1[2244] <= 8'b00000000;
MODULE1[2245] <= 8'b00000000;
MODULE1[2246] <= 8'b00000000;
MODULE1[2247] <= 8'b00000000;
MODULE1[2248] <= 8'b00000000;
MODULE1[2249] <= 8'b00000000;
MODULE1[2250] <= 8'b00000111;
MODULE1[2251] <= 8'b11100000;
MODULE1[2252] <= 8'b00000110;
MODULE1[2253] <= 8'b00000000;
MODULE1[2254] <= 8'b00000110;
MODULE1[2255] <= 8'b00000000;
MODULE1[2256] <= 8'b00000111;
MODULE1[2257] <= 8'b11100000;
MODULE1[2258] <= 8'b00000110;
MODULE1[2259] <= 8'b00000000;
MODULE1[2260] <= 8'b00000110;
MODULE1[2261] <= 8'b00000000;
MODULE1[2262] <= 8'b00000110;
MODULE1[2263] <= 8'b00000000;
MODULE1[2264] <= 8'b00000110;
MODULE1[2265] <= 8'b00000000;
MODULE1[2266] <= 8'b00000000;
MODULE1[2267] <= 8'b00000000;
MODULE1[2268] <= 8'b00000000;
MODULE1[2269] <= 8'b00000000;
MODULE1[2270] <= 8'b00000000;
MODULE1[2271] <= 8'b00000000;
MODULE1[2272] <= 8'b00000000;
MODULE1[2273] <= 8'b00000000;
MODULE1[2274] <= 8'b00000000;
MODULE1[2275] <= 8'b00000000;
MODULE1[2276] <= 8'b00000000;
MODULE1[2277] <= 8'b00000000;
MODULE1[2278] <= 8'b00000000;
MODULE1[2279] <= 8'b00000000;
MODULE1[2280] <= 8'b00000000;
MODULE1[2281] <= 8'b00000000;
MODULE1[2282] <= 8'b00000011;
MODULE1[2283] <= 8'b11000000;
MODULE1[2284] <= 8'b00000110;
MODULE1[2285] <= 8'b01100000;
MODULE1[2286] <= 8'b00000110;
MODULE1[2287] <= 8'b00000000;
MODULE1[2288] <= 8'b00001100;
MODULE1[2289] <= 8'b00000000;
MODULE1[2290] <= 8'b00001111;
MODULE1[2291] <= 8'b11100000;
MODULE1[2292] <= 8'b00001100;
MODULE1[2293] <= 8'b01100000;
MODULE1[2294] <= 8'b00001100;
MODULE1[2295] <= 8'b01100000;
MODULE1[2296] <= 8'b00000111;
MODULE1[2297] <= 8'b11000000;
MODULE1[2298] <= 8'b00000000;
MODULE1[2299] <= 8'b00000000;
MODULE1[2300] <= 8'b00000000;
MODULE1[2301] <= 8'b00000000;
MODULE1[2302] <= 8'b00000000;
MODULE1[2303] <= 8'b00000000;
MODULE1[2304] <= 8'b00000000;
MODULE1[2305] <= 8'b00000000;
MODULE1[2306] <= 8'b00000000;
MODULE1[2307] <= 8'b00000000;
MODULE1[2308] <= 8'b00000000;
MODULE1[2309] <= 8'b00000000;
MODULE1[2310] <= 8'b00000000;
MODULE1[2311] <= 8'b00000000;
MODULE1[2312] <= 8'b00000000;
MODULE1[2313] <= 8'b00000000;
MODULE1[2314] <= 8'b00001100;
MODULE1[2315] <= 8'b00110000;
MODULE1[2316] <= 8'b00001100;
MODULE1[2317] <= 8'b00100000;
MODULE1[2318] <= 8'b00001100;
MODULE1[2319] <= 8'b00100000;
MODULE1[2320] <= 8'b00001111;
MODULE1[2321] <= 8'b11100000;
MODULE1[2322] <= 8'b00001110;
MODULE1[2323] <= 8'b01100000;
MODULE1[2324] <= 8'b00001100;
MODULE1[2325] <= 8'b01100000;
MODULE1[2326] <= 8'b00001100;
MODULE1[2327] <= 8'b01100000;
MODULE1[2328] <= 8'b00001100;
MODULE1[2329] <= 8'b01100000;
MODULE1[2330] <= 8'b00000000;
MODULE1[2331] <= 8'b00000000;
MODULE1[2332] <= 8'b00000000;
MODULE1[2333] <= 8'b00000000;
MODULE1[2334] <= 8'b00000000;
MODULE1[2335] <= 8'b00000000;
MODULE1[2336] <= 8'b00000000;
MODULE1[2337] <= 8'b00000000;
MODULE1[2338] <= 8'b00000000;
MODULE1[2339] <= 8'b00000000;
MODULE1[2340] <= 8'b00000000;
MODULE1[2341] <= 8'b00000000;
MODULE1[2342] <= 8'b00000000;
MODULE1[2343] <= 8'b00000000;
MODULE1[2344] <= 8'b00000000;
MODULE1[2345] <= 8'b00000000;
MODULE1[2346] <= 8'b00000111;
MODULE1[2347] <= 8'b11100000;
MODULE1[2348] <= 8'b00000001;
MODULE1[2349] <= 8'b00000000;
MODULE1[2350] <= 8'b00000011;
MODULE1[2351] <= 8'b00000000;
MODULE1[2352] <= 8'b00000011;
MODULE1[2353] <= 8'b00000000;
MODULE1[2354] <= 8'b00000011;
MODULE1[2355] <= 8'b00000000;
MODULE1[2356] <= 8'b00000001;
MODULE1[2357] <= 8'b00000000;
MODULE1[2358] <= 8'b00000001;
MODULE1[2359] <= 8'b00000000;
MODULE1[2360] <= 8'b00000111;
MODULE1[2361] <= 8'b11000000;
MODULE1[2362] <= 8'b00000000;
MODULE1[2363] <= 8'b00000000;
MODULE1[2364] <= 8'b00000000;
MODULE1[2365] <= 8'b00000000;
MODULE1[2366] <= 8'b00000000;
MODULE1[2367] <= 8'b00000000;
MODULE1[2368] <= 8'b00000000;
MODULE1[2369] <= 8'b00000000;
MODULE1[2370] <= 8'b00000000;
MODULE1[2371] <= 8'b00000000;
MODULE1[2372] <= 8'b00000000;
MODULE1[2373] <= 8'b00000000;
MODULE1[2374] <= 8'b00000000;
MODULE1[2375] <= 8'b00000000;
MODULE1[2376] <= 8'b00000000;
MODULE1[2377] <= 8'b00000000;
MODULE1[2378] <= 8'b00000111;
MODULE1[2379] <= 8'b11100000;
MODULE1[2380] <= 8'b00000001;
MODULE1[2381] <= 8'b10000000;
MODULE1[2382] <= 8'b00000001;
MODULE1[2383] <= 8'b10000000;
MODULE1[2384] <= 8'b00000001;
MODULE1[2385] <= 8'b10000000;
MODULE1[2386] <= 8'b00000001;
MODULE1[2387] <= 8'b10000000;
MODULE1[2388] <= 8'b00001101;
MODULE1[2389] <= 8'b10000000;
MODULE1[2390] <= 8'b00001101;
MODULE1[2391] <= 8'b10000000;
MODULE1[2392] <= 8'b00000111;
MODULE1[2393] <= 8'b00000000;
MODULE1[2394] <= 8'b00000000;
MODULE1[2395] <= 8'b00000000;
MODULE1[2396] <= 8'b00000000;
MODULE1[2397] <= 8'b00000000;
MODULE1[2398] <= 8'b00000000;
MODULE1[2399] <= 8'b00000000;
MODULE1[2400] <= 8'b00000000;
MODULE1[2401] <= 8'b00000000;
MODULE1[2402] <= 8'b00000000;
MODULE1[2403] <= 8'b00000000;
MODULE1[2404] <= 8'b00000000;
MODULE1[2405] <= 8'b00000000;
MODULE1[2406] <= 8'b00000000;
MODULE1[2407] <= 8'b00000000;
MODULE1[2408] <= 8'b00000000;
MODULE1[2409] <= 8'b00000000;
MODULE1[2410] <= 8'b00000100;
MODULE1[2411] <= 8'b11100000;
MODULE1[2412] <= 8'b00000100;
MODULE1[2413] <= 8'b11000000;
MODULE1[2414] <= 8'b00000101;
MODULE1[2415] <= 8'b10000000;
MODULE1[2416] <= 8'b00000111;
MODULE1[2417] <= 8'b00000000;
MODULE1[2418] <= 8'b00000111;
MODULE1[2419] <= 8'b00000000;
MODULE1[2420] <= 8'b00000111;
MODULE1[2421] <= 8'b10000000;
MODULE1[2422] <= 8'b00000101;
MODULE1[2423] <= 8'b11000000;
MODULE1[2424] <= 8'b00000100;
MODULE1[2425] <= 8'b11100000;
MODULE1[2426] <= 8'b00000000;
MODULE1[2427] <= 8'b00000000;
MODULE1[2428] <= 8'b00000000;
MODULE1[2429] <= 8'b00000000;
MODULE1[2430] <= 8'b00000000;
MODULE1[2431] <= 8'b00000000;
MODULE1[2432] <= 8'b00000000;
MODULE1[2433] <= 8'b00000000;
MODULE1[2434] <= 8'b00000000;
MODULE1[2435] <= 8'b00000000;
MODULE1[2436] <= 8'b00000000;
MODULE1[2437] <= 8'b00000000;
MODULE1[2438] <= 8'b00000000;
MODULE1[2439] <= 8'b00000000;
MODULE1[2440] <= 8'b00000000;
MODULE1[2441] <= 8'b00000000;
MODULE1[2442] <= 8'b00000110;
MODULE1[2443] <= 8'b00000000;
MODULE1[2444] <= 8'b00000110;
MODULE1[2445] <= 8'b00000000;
MODULE1[2446] <= 8'b00000110;
MODULE1[2447] <= 8'b00000000;
MODULE1[2448] <= 8'b00000110;
MODULE1[2449] <= 8'b00000000;
MODULE1[2450] <= 8'b00000110;
MODULE1[2451] <= 8'b00000000;
MODULE1[2452] <= 8'b00000110;
MODULE1[2453] <= 8'b00000000;
MODULE1[2454] <= 8'b00000110;
MODULE1[2455] <= 8'b00000000;
MODULE1[2456] <= 8'b00000111;
MODULE1[2457] <= 8'b11100000;
MODULE1[2458] <= 8'b00000000;
MODULE1[2459] <= 8'b00000000;
MODULE1[2460] <= 8'b00000000;
MODULE1[2461] <= 8'b00000000;
MODULE1[2462] <= 8'b00000000;
MODULE1[2463] <= 8'b00000000;
MODULE1[2464] <= 8'b00000000;
MODULE1[2465] <= 8'b00000000;
MODULE1[2466] <= 8'b00000000;
MODULE1[2467] <= 8'b00000000;
MODULE1[2468] <= 8'b00000000;
MODULE1[2469] <= 8'b00000000;
MODULE1[2470] <= 8'b00000000;
MODULE1[2471] <= 8'b00000000;
MODULE1[2472] <= 8'b00000000;
MODULE1[2473] <= 8'b00000000;
MODULE1[2474] <= 8'b00000110;
MODULE1[2475] <= 8'b01100000;
MODULE1[2476] <= 8'b00001110;
MODULE1[2477] <= 8'b01100000;
MODULE1[2478] <= 8'b00001110;
MODULE1[2479] <= 8'b11100000;
MODULE1[2480] <= 8'b00001110;
MODULE1[2481] <= 8'b11100000;
MODULE1[2482] <= 8'b00001110;
MODULE1[2483] <= 8'b11110000;
MODULE1[2484] <= 8'b00011011;
MODULE1[2485] <= 8'b10110000;
MODULE1[2486] <= 8'b00011011;
MODULE1[2487] <= 8'b10110000;
MODULE1[2488] <= 8'b00011011;
MODULE1[2489] <= 8'b10110000;
MODULE1[2490] <= 8'b00000000;
MODULE1[2491] <= 8'b00000000;
MODULE1[2492] <= 8'b00000000;
MODULE1[2493] <= 8'b00000000;
MODULE1[2494] <= 8'b00000000;
MODULE1[2495] <= 8'b00000000;
MODULE1[2496] <= 8'b00000000;
MODULE1[2497] <= 8'b00000000;
MODULE1[2498] <= 8'b00000000;
MODULE1[2499] <= 8'b00000000;
MODULE1[2500] <= 8'b00000000;
MODULE1[2501] <= 8'b00000000;
MODULE1[2502] <= 8'b00000000;
MODULE1[2503] <= 8'b00000000;
MODULE1[2504] <= 8'b00000000;
MODULE1[2505] <= 8'b00000000;
MODULE1[2506] <= 8'b00001100;
MODULE1[2507] <= 8'b00110000;
MODULE1[2508] <= 8'b00001110;
MODULE1[2509] <= 8'b00110000;
MODULE1[2510] <= 8'b00001111;
MODULE1[2511] <= 8'b00011000;
MODULE1[2512] <= 8'b00001111;
MODULE1[2513] <= 8'b00011000;
MODULE1[2514] <= 8'b00001101;
MODULE1[2515] <= 8'b10011000;
MODULE1[2516] <= 8'b00001100;
MODULE1[2517] <= 8'b11011000;
MODULE1[2518] <= 8'b00001100;
MODULE1[2519] <= 8'b01111000;
MODULE1[2520] <= 8'b00001100;
MODULE1[2521] <= 8'b00110000;
MODULE1[2522] <= 8'b00000000;
MODULE1[2523] <= 8'b00000000;
MODULE1[2524] <= 8'b00000000;
MODULE1[2525] <= 8'b00000000;
MODULE1[2526] <= 8'b00000000;
MODULE1[2527] <= 8'b00000000;
MODULE1[2528] <= 8'b00000000;
MODULE1[2529] <= 8'b00000000;
MODULE1[2530] <= 8'b00000000;
MODULE1[2531] <= 8'b00000000;
MODULE1[2532] <= 8'b00000000;
MODULE1[2533] <= 8'b00000000;
MODULE1[2534] <= 8'b00000000;
MODULE1[2535] <= 8'b00000000;
MODULE1[2536] <= 8'b00000000;
MODULE1[2537] <= 8'b00000000;
MODULE1[2538] <= 8'b00000011;
MODULE1[2539] <= 8'b11100000;
MODULE1[2540] <= 8'b00000110;
MODULE1[2541] <= 8'b00110000;
MODULE1[2542] <= 8'b00001100;
MODULE1[2543] <= 8'b00011000;
MODULE1[2544] <= 8'b00001100;
MODULE1[2545] <= 8'b00011000;
MODULE1[2546] <= 8'b00001100;
MODULE1[2547] <= 8'b00010000;
MODULE1[2548] <= 8'b00001100;
MODULE1[2549] <= 8'b00110000;
MODULE1[2550] <= 8'b00001110;
MODULE1[2551] <= 8'b01100000;
MODULE1[2552] <= 8'b00000011;
MODULE1[2553] <= 8'b11000000;
MODULE1[2554] <= 8'b00000000;
MODULE1[2555] <= 8'b00000000;
MODULE1[2556] <= 8'b00000000;
MODULE1[2557] <= 8'b00000000;
MODULE1[2558] <= 8'b00000000;
MODULE1[2559] <= 8'b00000000;
MODULE1[2560] <= 8'b00000000;
MODULE1[2561] <= 8'b00000000;
MODULE1[2562] <= 8'b00000000;
MODULE1[2563] <= 8'b00000000;
MODULE1[2564] <= 8'b00000000;
MODULE1[2565] <= 8'b00000000;
MODULE1[2566] <= 8'b00000000;
MODULE1[2567] <= 8'b00000000;
MODULE1[2568] <= 8'b00000000;
MODULE1[2569] <= 8'b00000000;
MODULE1[2570] <= 8'b00000111;
MODULE1[2571] <= 8'b10000000;
MODULE1[2572] <= 8'b00000110;
MODULE1[2573] <= 8'b11000000;
MODULE1[2574] <= 8'b00000110;
MODULE1[2575] <= 8'b01100000;
MODULE1[2576] <= 8'b00000110;
MODULE1[2577] <= 8'b01100000;
MODULE1[2578] <= 8'b00000110;
MODULE1[2579] <= 8'b11000000;
MODULE1[2580] <= 8'b00000111;
MODULE1[2581] <= 8'b10000000;
MODULE1[2582] <= 8'b00000110;
MODULE1[2583] <= 8'b00000000;
MODULE1[2584] <= 8'b00000110;
MODULE1[2585] <= 8'b00000000;
MODULE1[2586] <= 8'b00000000;
MODULE1[2587] <= 8'b00000000;
MODULE1[2588] <= 8'b00000000;
MODULE1[2589] <= 8'b00000000;
MODULE1[2590] <= 8'b00000000;
MODULE1[2591] <= 8'b00000000;
MODULE1[2592] <= 8'b00000000;
MODULE1[2593] <= 8'b00000000;
MODULE1[2594] <= 8'b00000000;
MODULE1[2595] <= 8'b00000000;
MODULE1[2596] <= 8'b00000000;
MODULE1[2597] <= 8'b00000000;
MODULE1[2598] <= 8'b00000000;
MODULE1[2599] <= 8'b00000000;
MODULE1[2600] <= 8'b00000000;
MODULE1[2601] <= 8'b00000000;
MODULE1[2602] <= 8'b00000111;
MODULE1[2603] <= 8'b11100000;
MODULE1[2604] <= 8'b00001100;
MODULE1[2605] <= 8'b01110000;
MODULE1[2606] <= 8'b00011000;
MODULE1[2607] <= 8'b00110000;
MODULE1[2608] <= 8'b00011000;
MODULE1[2609] <= 8'b00010000;
MODULE1[2610] <= 8'b00011000;
MODULE1[2611] <= 8'b00011000;
MODULE1[2612] <= 8'b00011001;
MODULE1[2613] <= 8'b10110000;
MODULE1[2614] <= 8'b00001101;
MODULE1[2615] <= 8'b11110000;
MODULE1[2616] <= 8'b00000111;
MODULE1[2617] <= 8'b11100000;
MODULE1[2618] <= 8'b00000000;
MODULE1[2619] <= 8'b00110000;
MODULE1[2620] <= 8'b00000000;
MODULE1[2621] <= 8'b00011000;
MODULE1[2622] <= 8'b00000000;
MODULE1[2623] <= 8'b00000000;
MODULE1[2624] <= 8'b00000000;
MODULE1[2625] <= 8'b00000000;
MODULE1[2626] <= 8'b00000000;
MODULE1[2627] <= 8'b00000000;
MODULE1[2628] <= 8'b00000000;
MODULE1[2629] <= 8'b00000000;
MODULE1[2630] <= 8'b00000000;
MODULE1[2631] <= 8'b00000000;
MODULE1[2632] <= 8'b00000000;
MODULE1[2633] <= 8'b00000000;
MODULE1[2634] <= 8'b00001111;
MODULE1[2635] <= 8'b00000000;
MODULE1[2636] <= 8'b00001101;
MODULE1[2637] <= 8'b11000000;
MODULE1[2638] <= 8'b00001100;
MODULE1[2639] <= 8'b11000000;
MODULE1[2640] <= 8'b00001100;
MODULE1[2641] <= 8'b11000000;
MODULE1[2642] <= 8'b00001111;
MODULE1[2643] <= 8'b10000000;
MODULE1[2644] <= 8'b00001111;
MODULE1[2645] <= 8'b10000000;
MODULE1[2646] <= 8'b00001100;
MODULE1[2647] <= 8'b11000000;
MODULE1[2648] <= 8'b00001100;
MODULE1[2649] <= 8'b01100000;
MODULE1[2650] <= 8'b00000000;
MODULE1[2651] <= 8'b00000000;
MODULE1[2652] <= 8'b00000000;
MODULE1[2653] <= 8'b00000000;
MODULE1[2654] <= 8'b00000000;
MODULE1[2655] <= 8'b00000000;
MODULE1[2656] <= 8'b00000000;
MODULE1[2657] <= 8'b00000000;
MODULE1[2658] <= 8'b00000000;
MODULE1[2659] <= 8'b00000000;
MODULE1[2660] <= 8'b00000000;
MODULE1[2661] <= 8'b00000000;
MODULE1[2662] <= 8'b00000000;
MODULE1[2663] <= 8'b00000000;
MODULE1[2664] <= 8'b00000000;
MODULE1[2665] <= 8'b00000000;
MODULE1[2666] <= 8'b00000011;
MODULE1[2667] <= 8'b11100000;
MODULE1[2668] <= 8'b00000110;
MODULE1[2669] <= 8'b00000000;
MODULE1[2670] <= 8'b00000110;
MODULE1[2671] <= 8'b00000000;
MODULE1[2672] <= 8'b00000111;
MODULE1[2673] <= 8'b11000000;
MODULE1[2674] <= 8'b00000000;
MODULE1[2675] <= 8'b01100000;
MODULE1[2676] <= 8'b00000000;
MODULE1[2677] <= 8'b00100000;
MODULE1[2678] <= 8'b00001100;
MODULE1[2679] <= 8'b01100000;
MODULE1[2680] <= 8'b00000111;
MODULE1[2681] <= 8'b11000000;
MODULE1[2682] <= 8'b00000000;
MODULE1[2683] <= 8'b00000000;
MODULE1[2684] <= 8'b00000000;
MODULE1[2685] <= 8'b00000000;
MODULE1[2686] <= 8'b00000000;
MODULE1[2687] <= 8'b00000000;
MODULE1[2688] <= 8'b00000000;
MODULE1[2689] <= 8'b00000000;
MODULE1[2690] <= 8'b00000000;
MODULE1[2691] <= 8'b00000000;
MODULE1[2692] <= 8'b00000000;
MODULE1[2693] <= 8'b00000000;
MODULE1[2694] <= 8'b00000000;
MODULE1[2695] <= 8'b00000000;
MODULE1[2696] <= 8'b00000000;
MODULE1[2697] <= 8'b00000000;
MODULE1[2698] <= 8'b00001111;
MODULE1[2699] <= 8'b11110000;
MODULE1[2700] <= 8'b00000011;
MODULE1[2701] <= 8'b00000000;
MODULE1[2702] <= 8'b00000011;
MODULE1[2703] <= 8'b00000000;
MODULE1[2704] <= 8'b00000001;
MODULE1[2705] <= 8'b00000000;
MODULE1[2706] <= 8'b00000001;
MODULE1[2707] <= 8'b00000000;
MODULE1[2708] <= 8'b00000001;
MODULE1[2709] <= 8'b00000000;
MODULE1[2710] <= 8'b00000001;
MODULE1[2711] <= 8'b00000000;
MODULE1[2712] <= 8'b00000001;
MODULE1[2713] <= 8'b00000000;
MODULE1[2714] <= 8'b00000000;
MODULE1[2715] <= 8'b00000000;
MODULE1[2716] <= 8'b00000000;
MODULE1[2717] <= 8'b00000000;
MODULE1[2718] <= 8'b00000000;
MODULE1[2719] <= 8'b00000000;
MODULE1[2720] <= 8'b00000000;
MODULE1[2721] <= 8'b00000000;
MODULE1[2722] <= 8'b00000000;
MODULE1[2723] <= 8'b00000000;
MODULE1[2724] <= 8'b00000000;
MODULE1[2725] <= 8'b00000000;
MODULE1[2726] <= 8'b00000000;
MODULE1[2727] <= 8'b00000000;
MODULE1[2728] <= 8'b00000000;
MODULE1[2729] <= 8'b00000000;
MODULE1[2730] <= 8'b00001100;
MODULE1[2731] <= 8'b00100000;
MODULE1[2732] <= 8'b00001100;
MODULE1[2733] <= 8'b00100000;
MODULE1[2734] <= 8'b00001100;
MODULE1[2735] <= 8'b00100000;
MODULE1[2736] <= 8'b00001100;
MODULE1[2737] <= 8'b01100000;
MODULE1[2738] <= 8'b00001100;
MODULE1[2739] <= 8'b01100000;
MODULE1[2740] <= 8'b00001100;
MODULE1[2741] <= 8'b01100000;
MODULE1[2742] <= 8'b00000100;
MODULE1[2743] <= 8'b01100000;
MODULE1[2744] <= 8'b00000111;
MODULE1[2745] <= 8'b11000000;
MODULE1[2746] <= 8'b00000000;
MODULE1[2747] <= 8'b00000000;
MODULE1[2748] <= 8'b00000000;
MODULE1[2749] <= 8'b00000000;
MODULE1[2750] <= 8'b00000000;
MODULE1[2751] <= 8'b00000000;
MODULE1[2752] <= 8'b00000000;
MODULE1[2753] <= 8'b00000000;
MODULE1[2754] <= 8'b00000000;
MODULE1[2755] <= 8'b00000000;
MODULE1[2756] <= 8'b00000000;
MODULE1[2757] <= 8'b00000000;
MODULE1[2758] <= 8'b00000000;
MODULE1[2759] <= 8'b00000000;
MODULE1[2760] <= 8'b00000000;
MODULE1[2761] <= 8'b00000000;
MODULE1[2762] <= 8'b00001100;
MODULE1[2763] <= 8'b01100000;
MODULE1[2764] <= 8'b00001100;
MODULE1[2765] <= 8'b01100000;
MODULE1[2766] <= 8'b00000100;
MODULE1[2767] <= 8'b11000000;
MODULE1[2768] <= 8'b00000110;
MODULE1[2769] <= 8'b11000000;
MODULE1[2770] <= 8'b00000110;
MODULE1[2771] <= 8'b11000000;
MODULE1[2772] <= 8'b00000111;
MODULE1[2773] <= 8'b10000000;
MODULE1[2774] <= 8'b00000011;
MODULE1[2775] <= 8'b10000000;
MODULE1[2776] <= 8'b00000011;
MODULE1[2777] <= 8'b00000000;
MODULE1[2778] <= 8'b00000000;
MODULE1[2779] <= 8'b00000000;
MODULE1[2780] <= 8'b00000000;
MODULE1[2781] <= 8'b00000000;
MODULE1[2782] <= 8'b00000000;
MODULE1[2783] <= 8'b00000000;
MODULE1[2784] <= 8'b00000000;
MODULE1[2785] <= 8'b00000000;
MODULE1[2786] <= 8'b00000000;
MODULE1[2787] <= 8'b00000000;
MODULE1[2788] <= 8'b00000000;
MODULE1[2789] <= 8'b00000000;
MODULE1[2790] <= 8'b00000000;
MODULE1[2791] <= 8'b00000000;
MODULE1[2792] <= 8'b00000000;
MODULE1[2793] <= 8'b00000000;
MODULE1[2794] <= 8'b00110001;
MODULE1[2795] <= 8'b10011000;
MODULE1[2796] <= 8'b00110011;
MODULE1[2797] <= 8'b10011000;
MODULE1[2798] <= 8'b00011011;
MODULE1[2799] <= 8'b10011000;
MODULE1[2800] <= 8'b00011011;
MODULE1[2801] <= 8'b10110000;
MODULE1[2802] <= 8'b00011110;
MODULE1[2803] <= 8'b10110000;
MODULE1[2804] <= 8'b00011110;
MODULE1[2805] <= 8'b11100000;
MODULE1[2806] <= 8'b00001100;
MODULE1[2807] <= 8'b11100000;
MODULE1[2808] <= 8'b00001100;
MODULE1[2809] <= 8'b11100000;
MODULE1[2810] <= 8'b00000000;
MODULE1[2811] <= 8'b00000000;
MODULE1[2812] <= 8'b00000000;
MODULE1[2813] <= 8'b00000000;
MODULE1[2814] <= 8'b00000000;
MODULE1[2815] <= 8'b00000000;
MODULE1[2816] <= 8'b00000000;
MODULE1[2817] <= 8'b00000000;
MODULE1[2818] <= 8'b00000000;
MODULE1[2819] <= 8'b00000000;
MODULE1[2820] <= 8'b00000000;
MODULE1[2821] <= 8'b00000000;
MODULE1[2822] <= 8'b00000000;
MODULE1[2823] <= 8'b00000000;
MODULE1[2824] <= 8'b00000000;
MODULE1[2825] <= 8'b00000000;
MODULE1[2826] <= 8'b00001100;
MODULE1[2827] <= 8'b00110000;
MODULE1[2828] <= 8'b00000110;
MODULE1[2829] <= 8'b01100000;
MODULE1[2830] <= 8'b00000011;
MODULE1[2831] <= 8'b11000000;
MODULE1[2832] <= 8'b00000011;
MODULE1[2833] <= 8'b10000000;
MODULE1[2834] <= 8'b00000011;
MODULE1[2835] <= 8'b10000000;
MODULE1[2836] <= 8'b00000111;
MODULE1[2837] <= 8'b11000000;
MODULE1[2838] <= 8'b00001110;
MODULE1[2839] <= 8'b01100000;
MODULE1[2840] <= 8'b00001100;
MODULE1[2841] <= 8'b01110000;
MODULE1[2842] <= 8'b00000000;
MODULE1[2843] <= 8'b00000000;
MODULE1[2844] <= 8'b00000000;
MODULE1[2845] <= 8'b00000000;
MODULE1[2846] <= 8'b00000000;
MODULE1[2847] <= 8'b00000000;
MODULE1[2848] <= 8'b00000000;
MODULE1[2849] <= 8'b00000000;
MODULE1[2850] <= 8'b00000000;
MODULE1[2851] <= 8'b00000000;
MODULE1[2852] <= 8'b00000000;
MODULE1[2853] <= 8'b00000000;
MODULE1[2854] <= 8'b00000000;
MODULE1[2855] <= 8'b00000000;
MODULE1[2856] <= 8'b00000000;
MODULE1[2857] <= 8'b00000000;
MODULE1[2858] <= 8'b00011000;
MODULE1[2859] <= 8'b01100000;
MODULE1[2860] <= 8'b00001100;
MODULE1[2861] <= 8'b11000000;
MODULE1[2862] <= 8'b00000110;
MODULE1[2863] <= 8'b11000000;
MODULE1[2864] <= 8'b00000111;
MODULE1[2865] <= 8'b10000000;
MODULE1[2866] <= 8'b00000011;
MODULE1[2867] <= 8'b10000000;
MODULE1[2868] <= 8'b00000011;
MODULE1[2869] <= 8'b10000000;
MODULE1[2870] <= 8'b00000011;
MODULE1[2871] <= 8'b00000000;
MODULE1[2872] <= 8'b00000110;
MODULE1[2873] <= 8'b00000000;
MODULE1[2874] <= 8'b00000000;
MODULE1[2875] <= 8'b00000000;
MODULE1[2876] <= 8'b00000000;
MODULE1[2877] <= 8'b00000000;
MODULE1[2878] <= 8'b00000000;
MODULE1[2879] <= 8'b00000000;
MODULE1[2880] <= 8'b00000000;
MODULE1[2881] <= 8'b00000000;
MODULE1[2882] <= 8'b00000000;
MODULE1[2883] <= 8'b00000000;
MODULE1[2884] <= 8'b00000000;
MODULE1[2885] <= 8'b00000000;
MODULE1[2886] <= 8'b00000000;
MODULE1[2887] <= 8'b00000000;
MODULE1[2888] <= 8'b00000000;
MODULE1[2889] <= 8'b00000000;
MODULE1[2890] <= 8'b00001111;
MODULE1[2891] <= 8'b11110000;
MODULE1[2892] <= 8'b00000000;
MODULE1[2893] <= 8'b11100000;
MODULE1[2894] <= 8'b00000001;
MODULE1[2895] <= 8'b10000000;
MODULE1[2896] <= 8'b00000011;
MODULE1[2897] <= 8'b00000000;
MODULE1[2898] <= 8'b00000011;
MODULE1[2899] <= 8'b00000000;
MODULE1[2900] <= 8'b00000110;
MODULE1[2901] <= 8'b00000000;
MODULE1[2902] <= 8'b00001100;
MODULE1[2903] <= 8'b00000000;
MODULE1[2904] <= 8'b00001111;
MODULE1[2905] <= 8'b11110000;
MODULE1[2906] <= 8'b00000000;
MODULE1[2907] <= 8'b00000000;
MODULE1[2908] <= 8'b00000000;
MODULE1[2909] <= 8'b00000000;
MODULE1[2910] <= 8'b00000000;
MODULE1[2911] <= 8'b00000000;
MODULE1[2912] <= 8'b00000000;
MODULE1[2913] <= 8'b00000000;
MODULE1[2914] <= 8'b00000000;
MODULE1[2915] <= 8'b00000000;
MODULE1[2916] <= 8'b00000000;
MODULE1[2917] <= 8'b00000000;
MODULE1[2918] <= 8'b00000000;
MODULE1[2919] <= 8'b00000000;
MODULE1[2920] <= 8'b00000011;
MODULE1[2921] <= 8'b11000000;
MODULE1[2922] <= 8'b00000011;
MODULE1[2923] <= 8'b00000000;
MODULE1[2924] <= 8'b00000011;
MODULE1[2925] <= 8'b00000000;
MODULE1[2926] <= 8'b00000011;
MODULE1[2927] <= 8'b00000000;
MODULE1[2928] <= 8'b00000011;
MODULE1[2929] <= 8'b00000000;
MODULE1[2930] <= 8'b00000011;
MODULE1[2931] <= 8'b00000000;
MODULE1[2932] <= 8'b00000011;
MODULE1[2933] <= 8'b00000000;
MODULE1[2934] <= 8'b00000011;
MODULE1[2935] <= 8'b00000000;
MODULE1[2936] <= 8'b00000011;
MODULE1[2937] <= 8'b00000000;
MODULE1[2938] <= 8'b00000011;
MODULE1[2939] <= 8'b00000000;
MODULE1[2940] <= 8'b00000011;
MODULE1[2941] <= 8'b11000000;
MODULE1[2942] <= 8'b00000000;
MODULE1[2943] <= 8'b00000000;
MODULE1[2944] <= 8'b00000000;
MODULE1[2945] <= 8'b00000000;
MODULE1[2946] <= 8'b00000000;
MODULE1[2947] <= 8'b00000000;
MODULE1[2948] <= 8'b00000000;
MODULE1[2949] <= 8'b00000000;
MODULE1[2950] <= 8'b00000000;
MODULE1[2951] <= 8'b00000000;
MODULE1[2952] <= 8'b00000000;
MODULE1[2953] <= 8'b00000000;
MODULE1[2954] <= 8'b00000011;
MODULE1[2955] <= 8'b00000000;
MODULE1[2956] <= 8'b00000001;
MODULE1[2957] <= 8'b10000000;
MODULE1[2958] <= 8'b00000001;
MODULE1[2959] <= 8'b10000000;
MODULE1[2960] <= 8'b00000000;
MODULE1[2961] <= 8'b11000000;
MODULE1[2962] <= 8'b00000000;
MODULE1[2963] <= 8'b11000000;
MODULE1[2964] <= 8'b00000000;
MODULE1[2965] <= 8'b11000000;
MODULE1[2966] <= 8'b00000000;
MODULE1[2967] <= 8'b01100000;
MODULE1[2968] <= 8'b00000000;
MODULE1[2969] <= 8'b01100000;
MODULE1[2970] <= 8'b00000000;
MODULE1[2971] <= 8'b00110000;
MODULE1[2972] <= 8'b00000000;
MODULE1[2973] <= 8'b00000000;
MODULE1[2974] <= 8'b00000000;
MODULE1[2975] <= 8'b00000000;
MODULE1[2976] <= 8'b00000000;
MODULE1[2977] <= 8'b00000000;
MODULE1[2978] <= 8'b00000000;
MODULE1[2979] <= 8'b00000000;
MODULE1[2980] <= 8'b00000000;
MODULE1[2981] <= 8'b00000000;
MODULE1[2982] <= 8'b00000000;
MODULE1[2983] <= 8'b00000000;
MODULE1[2984] <= 8'b00000011;
MODULE1[2985] <= 8'b11000000;
MODULE1[2986] <= 8'b00000000;
MODULE1[2987] <= 8'b11000000;
MODULE1[2988] <= 8'b00000000;
MODULE1[2989] <= 8'b11000000;
MODULE1[2990] <= 8'b00000000;
MODULE1[2991] <= 8'b11000000;
MODULE1[2992] <= 8'b00000000;
MODULE1[2993] <= 8'b11000000;
MODULE1[2994] <= 8'b00000000;
MODULE1[2995] <= 8'b11000000;
MODULE1[2996] <= 8'b00000000;
MODULE1[2997] <= 8'b11000000;
MODULE1[2998] <= 8'b00000000;
MODULE1[2999] <= 8'b11000000;
MODULE1[3000] <= 8'b00000000;
MODULE1[3001] <= 8'b11000000;
MODULE1[3002] <= 8'b00000000;
MODULE1[3003] <= 8'b11000000;
MODULE1[3004] <= 8'b00000011;
MODULE1[3005] <= 8'b11000000;
MODULE1[3006] <= 8'b00000000;
MODULE1[3007] <= 8'b00000000;
MODULE1[3008] <= 8'b00000000;
MODULE1[3009] <= 8'b00000000;
MODULE1[3010] <= 8'b00000000;
MODULE1[3011] <= 8'b00000000;
MODULE1[3012] <= 8'b00000000;
MODULE1[3013] <= 8'b00000000;
MODULE1[3014] <= 8'b00000000;
MODULE1[3015] <= 8'b00000000;
MODULE1[3016] <= 8'b00000000;
MODULE1[3017] <= 8'b11000000;
MODULE1[3018] <= 8'b00000001;
MODULE1[3019] <= 8'b11100000;
MODULE1[3020] <= 8'b00000011;
MODULE1[3021] <= 8'b00110000;
MODULE1[3022] <= 8'b00000000;
MODULE1[3023] <= 8'b00000000;
MODULE1[3024] <= 8'b00000000;
MODULE1[3025] <= 8'b00000000;
MODULE1[3026] <= 8'b00000000;
MODULE1[3027] <= 8'b00000000;
MODULE1[3028] <= 8'b00000000;
MODULE1[3029] <= 8'b00000000;
MODULE1[3030] <= 8'b00000000;
MODULE1[3031] <= 8'b00000000;
MODULE1[3032] <= 8'b00000000;
MODULE1[3033] <= 8'b00000000;
MODULE1[3034] <= 8'b00000000;
MODULE1[3035] <= 8'b00000000;
MODULE1[3036] <= 8'b00000000;
MODULE1[3037] <= 8'b00000000;
MODULE1[3038] <= 8'b00000000;
MODULE1[3039] <= 8'b00000000;
MODULE1[3040] <= 8'b00000000;
MODULE1[3041] <= 8'b00000000;
MODULE1[3042] <= 8'b00000000;
MODULE1[3043] <= 8'b00000000;
MODULE1[3044] <= 8'b00000000;
MODULE1[3045] <= 8'b00000000;
MODULE1[3046] <= 8'b00000000;
MODULE1[3047] <= 8'b00000000;
MODULE1[3048] <= 8'b00000000;
MODULE1[3049] <= 8'b00000000;
MODULE1[3050] <= 8'b00000000;
MODULE1[3051] <= 8'b00000000;
MODULE1[3052] <= 8'b00000000;
MODULE1[3053] <= 8'b00000000;
MODULE1[3054] <= 8'b00000000;
MODULE1[3055] <= 8'b00000000;
MODULE1[3056] <= 8'b00000000;
MODULE1[3057] <= 8'b00000000;
MODULE1[3058] <= 8'b00000000;
MODULE1[3059] <= 8'b00000000;
MODULE1[3060] <= 8'b00000000;
MODULE1[3061] <= 8'b00000000;
MODULE1[3062] <= 8'b00000000;
MODULE1[3063] <= 8'b00000000;
MODULE1[3064] <= 8'b00000000;
MODULE1[3065] <= 8'b00000000;
MODULE1[3066] <= 8'b00000000;
MODULE1[3067] <= 8'b00000000;
MODULE1[3068] <= 8'b00011111;
MODULE1[3069] <= 8'b11100000;
MODULE1[3070] <= 8'b00000000;
MODULE1[3071] <= 8'b00000000;
MODULE1[3072] <= 8'b00000000;
MODULE1[3073] <= 8'b00000000;
MODULE1[3074] <= 8'b00000000;
MODULE1[3075] <= 8'b00000000;
MODULE1[3076] <= 8'b00000000;
MODULE1[3077] <= 8'b00000000;
MODULE1[3078] <= 8'b00000000;
MODULE1[3079] <= 8'b00000000;
MODULE1[3080] <= 8'b00000110;
MODULE1[3081] <= 8'b00000000;
MODULE1[3082] <= 8'b00000011;
MODULE1[3083] <= 8'b00000000;
MODULE1[3084] <= 8'b00000000;
MODULE1[3085] <= 8'b00000000;
MODULE1[3086] <= 8'b00000000;
MODULE1[3087] <= 8'b00000000;
MODULE1[3088] <= 8'b00000000;
MODULE1[3089] <= 8'b00000000;
MODULE1[3090] <= 8'b00000000;
MODULE1[3091] <= 8'b00000000;
MODULE1[3092] <= 8'b00000000;
MODULE1[3093] <= 8'b00000000;
MODULE1[3094] <= 8'b00000000;
MODULE1[3095] <= 8'b00000000;
MODULE1[3096] <= 8'b00000000;
MODULE1[3097] <= 8'b00000000;
MODULE1[3098] <= 8'b00000000;
MODULE1[3099] <= 8'b00000000;
MODULE1[3100] <= 8'b00000000;
MODULE1[3101] <= 8'b00000000;
MODULE1[3102] <= 8'b00000000;
MODULE1[3103] <= 8'b00000000;
MODULE1[3104] <= 8'b00000000;
MODULE1[3105] <= 8'b00000000;
MODULE1[3106] <= 8'b00000000;
MODULE1[3107] <= 8'b00000000;
MODULE1[3108] <= 8'b00000000;
MODULE1[3109] <= 8'b00000000;
MODULE1[3110] <= 8'b00000000;
MODULE1[3111] <= 8'b00000000;
MODULE1[3112] <= 8'b00000000;
MODULE1[3113] <= 8'b00000000;
MODULE1[3114] <= 8'b00000000;
MODULE1[3115] <= 8'b00000000;
MODULE1[3116] <= 8'b00000000;
MODULE1[3117] <= 8'b00000000;
MODULE1[3118] <= 8'b00000011;
MODULE1[3119] <= 8'b11000000;
MODULE1[3120] <= 8'b00000110;
MODULE1[3121] <= 8'b11000000;
MODULE1[3122] <= 8'b00000110;
MODULE1[3123] <= 8'b11000000;
MODULE1[3124] <= 8'b00000100;
MODULE1[3125] <= 8'b11000000;
MODULE1[3126] <= 8'b00000110;
MODULE1[3127] <= 8'b11000000;
MODULE1[3128] <= 8'b00000111;
MODULE1[3129] <= 8'b11100000;
MODULE1[3130] <= 8'b00000000;
MODULE1[3131] <= 8'b00000000;
MODULE1[3132] <= 8'b00000000;
MODULE1[3133] <= 8'b00000000;
MODULE1[3134] <= 8'b00000000;
MODULE1[3135] <= 8'b00000000;
MODULE1[3136] <= 8'b00000000;
MODULE1[3137] <= 8'b00000000;
MODULE1[3138] <= 8'b00000000;
MODULE1[3139] <= 8'b00000000;
MODULE1[3140] <= 8'b00000000;
MODULE1[3141] <= 8'b00000000;
MODULE1[3142] <= 8'b00000000;
MODULE1[3143] <= 8'b00000000;
MODULE1[3144] <= 8'b00000110;
MODULE1[3145] <= 8'b00000000;
MODULE1[3146] <= 8'b00000110;
MODULE1[3147] <= 8'b00000000;
MODULE1[3148] <= 8'b00000110;
MODULE1[3149] <= 8'b00000000;
MODULE1[3150] <= 8'b00000111;
MODULE1[3151] <= 8'b11000000;
MODULE1[3152] <= 8'b00000110;
MODULE1[3153] <= 8'b01000000;
MODULE1[3154] <= 8'b00000110;
MODULE1[3155] <= 8'b01100000;
MODULE1[3156] <= 8'b00000110;
MODULE1[3157] <= 8'b01100000;
MODULE1[3158] <= 8'b00000110;
MODULE1[3159] <= 8'b11000000;
MODULE1[3160] <= 8'b00000111;
MODULE1[3161] <= 8'b11000000;
MODULE1[3162] <= 8'b00000000;
MODULE1[3163] <= 8'b00000000;
MODULE1[3164] <= 8'b00000000;
MODULE1[3165] <= 8'b00000000;
MODULE1[3166] <= 8'b00000000;
MODULE1[3167] <= 8'b00000000;
MODULE1[3168] <= 8'b00000000;
MODULE1[3169] <= 8'b00000000;
MODULE1[3170] <= 8'b00000000;
MODULE1[3171] <= 8'b00000000;
MODULE1[3172] <= 8'b00000000;
MODULE1[3173] <= 8'b00000000;
MODULE1[3174] <= 8'b00000000;
MODULE1[3175] <= 8'b00000000;
MODULE1[3176] <= 8'b00000000;
MODULE1[3177] <= 8'b00000000;
MODULE1[3178] <= 8'b00000000;
MODULE1[3179] <= 8'b00000000;
MODULE1[3180] <= 8'b00000000;
MODULE1[3181] <= 8'b00000000;
MODULE1[3182] <= 8'b00000001;
MODULE1[3183] <= 8'b11000000;
MODULE1[3184] <= 8'b00000011;
MODULE1[3185] <= 8'b01100000;
MODULE1[3186] <= 8'b00000110;
MODULE1[3187] <= 8'b00000000;
MODULE1[3188] <= 8'b00000110;
MODULE1[3189] <= 8'b00000000;
MODULE1[3190] <= 8'b00000110;
MODULE1[3191] <= 8'b01100000;
MODULE1[3192] <= 8'b00000011;
MODULE1[3193] <= 8'b11000000;
MODULE1[3194] <= 8'b00000000;
MODULE1[3195] <= 8'b00000000;
MODULE1[3196] <= 8'b00000000;
MODULE1[3197] <= 8'b00000000;
MODULE1[3198] <= 8'b00000000;
MODULE1[3199] <= 8'b00000000;
MODULE1[3200] <= 8'b00000000;
MODULE1[3201] <= 8'b00000000;
MODULE1[3202] <= 8'b00000000;
MODULE1[3203] <= 8'b00000000;
MODULE1[3204] <= 8'b00000000;
MODULE1[3205] <= 8'b00000000;
MODULE1[3206] <= 8'b00000000;
MODULE1[3207] <= 8'b00000000;
MODULE1[3208] <= 8'b00000000;
MODULE1[3209] <= 8'b01100000;
MODULE1[3210] <= 8'b00000000;
MODULE1[3211] <= 8'b01100000;
MODULE1[3212] <= 8'b00000000;
MODULE1[3213] <= 8'b01000000;
MODULE1[3214] <= 8'b00000011;
MODULE1[3215] <= 8'b11000000;
MODULE1[3216] <= 8'b00000110;
MODULE1[3217] <= 8'b11000000;
MODULE1[3218] <= 8'b00000110;
MODULE1[3219] <= 8'b01000000;
MODULE1[3220] <= 8'b00000110;
MODULE1[3221] <= 8'b01000000;
MODULE1[3222] <= 8'b00000110;
MODULE1[3223] <= 8'b11000000;
MODULE1[3224] <= 8'b00000011;
MODULE1[3225] <= 8'b11100000;
MODULE1[3226] <= 8'b00000000;
MODULE1[3227] <= 8'b00000000;
MODULE1[3228] <= 8'b00000000;
MODULE1[3229] <= 8'b00000000;
MODULE1[3230] <= 8'b00000000;
MODULE1[3231] <= 8'b00000000;
MODULE1[3232] <= 8'b00000000;
MODULE1[3233] <= 8'b00000000;
MODULE1[3234] <= 8'b00000000;
MODULE1[3235] <= 8'b00000000;
MODULE1[3236] <= 8'b00000000;
MODULE1[3237] <= 8'b00000000;
MODULE1[3238] <= 8'b00000000;
MODULE1[3239] <= 8'b00000000;
MODULE1[3240] <= 8'b00000000;
MODULE1[3241] <= 8'b00000000;
MODULE1[3242] <= 8'b00000000;
MODULE1[3243] <= 8'b00000000;
MODULE1[3244] <= 8'b00000000;
MODULE1[3245] <= 8'b00000000;
MODULE1[3246] <= 8'b00000011;
MODULE1[3247] <= 8'b11000000;
MODULE1[3248] <= 8'b00000110;
MODULE1[3249] <= 8'b01000000;
MODULE1[3250] <= 8'b00000111;
MODULE1[3251] <= 8'b11000000;
MODULE1[3252] <= 8'b00000111;
MODULE1[3253] <= 8'b00000000;
MODULE1[3254] <= 8'b00000110;
MODULE1[3255] <= 8'b01100000;
MODULE1[3256] <= 8'b00000011;
MODULE1[3257] <= 8'b11000000;
MODULE1[3258] <= 8'b00000000;
MODULE1[3259] <= 8'b00000000;
MODULE1[3260] <= 8'b00000000;
MODULE1[3261] <= 8'b00000000;
MODULE1[3262] <= 8'b00000000;
MODULE1[3263] <= 8'b00000000;
MODULE1[3264] <= 8'b00000000;
MODULE1[3265] <= 8'b00000000;
MODULE1[3266] <= 8'b00000000;
MODULE1[3267] <= 8'b00000000;
MODULE1[3268] <= 8'b00000000;
MODULE1[3269] <= 8'b00000000;
MODULE1[3270] <= 8'b00000000;
MODULE1[3271] <= 8'b00000000;
MODULE1[3272] <= 8'b00000001;
MODULE1[3273] <= 8'b11000000;
MODULE1[3274] <= 8'b00000001;
MODULE1[3275] <= 8'b00000000;
MODULE1[3276] <= 8'b00000011;
MODULE1[3277] <= 8'b00000000;
MODULE1[3278] <= 8'b00000111;
MODULE1[3279] <= 8'b11000000;
MODULE1[3280] <= 8'b00000011;
MODULE1[3281] <= 8'b00000000;
MODULE1[3282] <= 8'b00000011;
MODULE1[3283] <= 8'b00000000;
MODULE1[3284] <= 8'b00000011;
MODULE1[3285] <= 8'b00000000;
MODULE1[3286] <= 8'b00000011;
MODULE1[3287] <= 8'b00000000;
MODULE1[3288] <= 8'b00000011;
MODULE1[3289] <= 8'b00000000;
MODULE1[3290] <= 8'b00000000;
MODULE1[3291] <= 8'b00000000;
MODULE1[3292] <= 8'b00000000;
MODULE1[3293] <= 8'b00000000;
MODULE1[3294] <= 8'b00000000;
MODULE1[3295] <= 8'b00000000;
MODULE1[3296] <= 8'b00000000;
MODULE1[3297] <= 8'b00000000;
MODULE1[3298] <= 8'b00000000;
MODULE1[3299] <= 8'b00000000;
MODULE1[3300] <= 8'b00000000;
MODULE1[3301] <= 8'b00000000;
MODULE1[3302] <= 8'b00000000;
MODULE1[3303] <= 8'b00000000;
MODULE1[3304] <= 8'b00000000;
MODULE1[3305] <= 8'b00000000;
MODULE1[3306] <= 8'b00000000;
MODULE1[3307] <= 8'b00000000;
MODULE1[3308] <= 8'b00000000;
MODULE1[3309] <= 8'b00000000;
MODULE1[3310] <= 8'b00000011;
MODULE1[3311] <= 8'b11000000;
MODULE1[3312] <= 8'b00000110;
MODULE1[3313] <= 8'b01100000;
MODULE1[3314] <= 8'b00000110;
MODULE1[3315] <= 8'b01100000;
MODULE1[3316] <= 8'b00000100;
MODULE1[3317] <= 8'b11000000;
MODULE1[3318] <= 8'b00000110;
MODULE1[3319] <= 8'b11000000;
MODULE1[3320] <= 8'b00000111;
MODULE1[3321] <= 8'b11000000;
MODULE1[3322] <= 8'b00000000;
MODULE1[3323] <= 8'b11000000;
MODULE1[3324] <= 8'b00000000;
MODULE1[3325] <= 8'b11000000;
MODULE1[3326] <= 8'b00000111;
MODULE1[3327] <= 8'b10000000;
MODULE1[3328] <= 8'b00000000;
MODULE1[3329] <= 8'b00000000;
MODULE1[3330] <= 8'b00000000;
MODULE1[3331] <= 8'b00000000;
MODULE1[3332] <= 8'b00000000;
MODULE1[3333] <= 8'b00000000;
MODULE1[3334] <= 8'b00000000;
MODULE1[3335] <= 8'b00000000;
MODULE1[3336] <= 8'b00000110;
MODULE1[3337] <= 8'b00000000;
MODULE1[3338] <= 8'b00000110;
MODULE1[3339] <= 8'b00000000;
MODULE1[3340] <= 8'b00000110;
MODULE1[3341] <= 8'b00000000;
MODULE1[3342] <= 8'b00000111;
MODULE1[3343] <= 8'b11000000;
MODULE1[3344] <= 8'b00000111;
MODULE1[3345] <= 8'b11000000;
MODULE1[3346] <= 8'b00000110;
MODULE1[3347] <= 8'b11000000;
MODULE1[3348] <= 8'b00000110;
MODULE1[3349] <= 8'b11000000;
MODULE1[3350] <= 8'b00000110;
MODULE1[3351] <= 8'b11000000;
MODULE1[3352] <= 8'b00000110;
MODULE1[3353] <= 8'b01100000;
MODULE1[3354] <= 8'b00000000;
MODULE1[3355] <= 8'b00000000;
MODULE1[3356] <= 8'b00000000;
MODULE1[3357] <= 8'b00000000;
MODULE1[3358] <= 8'b00000000;
MODULE1[3359] <= 8'b00000000;
MODULE1[3360] <= 8'b00000000;
MODULE1[3361] <= 8'b00000000;
MODULE1[3362] <= 8'b00000000;
MODULE1[3363] <= 8'b00000000;
MODULE1[3364] <= 8'b00000000;
MODULE1[3365] <= 8'b00000000;
MODULE1[3366] <= 8'b00000000;
MODULE1[3367] <= 8'b00000000;
MODULE1[3368] <= 8'b00000000;
MODULE1[3369] <= 8'b00000000;
MODULE1[3370] <= 8'b00000001;
MODULE1[3371] <= 8'b10000000;
MODULE1[3372] <= 8'b00000000;
MODULE1[3373] <= 8'b00000000;
MODULE1[3374] <= 8'b00000001;
MODULE1[3375] <= 8'b10000000;
MODULE1[3376] <= 8'b00000001;
MODULE1[3377] <= 8'b10000000;
MODULE1[3378] <= 8'b00000001;
MODULE1[3379] <= 8'b10000000;
MODULE1[3380] <= 8'b00000001;
MODULE1[3381] <= 8'b10000000;
MODULE1[3382] <= 8'b00000001;
MODULE1[3383] <= 8'b10000000;
MODULE1[3384] <= 8'b00000001;
MODULE1[3385] <= 8'b10000000;
MODULE1[3386] <= 8'b00000000;
MODULE1[3387] <= 8'b00000000;
MODULE1[3388] <= 8'b00000000;
MODULE1[3389] <= 8'b00000000;
MODULE1[3390] <= 8'b00000000;
MODULE1[3391] <= 8'b00000000;
MODULE1[3392] <= 8'b00000000;
MODULE1[3393] <= 8'b00000000;
MODULE1[3394] <= 8'b00000000;
MODULE1[3395] <= 8'b00000000;
MODULE1[3396] <= 8'b00000000;
MODULE1[3397] <= 8'b00000000;
MODULE1[3398] <= 8'b00000000;
MODULE1[3399] <= 8'b00000000;
MODULE1[3400] <= 8'b00000000;
MODULE1[3401] <= 8'b00000000;
MODULE1[3402] <= 8'b00000001;
MODULE1[3403] <= 8'b10000000;
MODULE1[3404] <= 8'b00000000;
MODULE1[3405] <= 8'b00000000;
MODULE1[3406] <= 8'b00000001;
MODULE1[3407] <= 8'b10000000;
MODULE1[3408] <= 8'b00000001;
MODULE1[3409] <= 8'b10000000;
MODULE1[3410] <= 8'b00000001;
MODULE1[3411] <= 8'b10000000;
MODULE1[3412] <= 8'b00000001;
MODULE1[3413] <= 8'b10000000;
MODULE1[3414] <= 8'b00000001;
MODULE1[3415] <= 8'b10000000;
MODULE1[3416] <= 8'b00000001;
MODULE1[3417] <= 8'b10000000;
MODULE1[3418] <= 8'b00000001;
MODULE1[3419] <= 8'b10000000;
MODULE1[3420] <= 8'b00000111;
MODULE1[3421] <= 8'b10000000;
MODULE1[3422] <= 8'b00000011;
MODULE1[3423] <= 8'b10000000;
MODULE1[3424] <= 8'b00000000;
MODULE1[3425] <= 8'b00000000;
MODULE1[3426] <= 8'b00000000;
MODULE1[3427] <= 8'b00000000;
MODULE1[3428] <= 8'b00000000;
MODULE1[3429] <= 8'b00000000;
MODULE1[3430] <= 8'b00000000;
MODULE1[3431] <= 8'b00000000;
MODULE1[3432] <= 8'b00000110;
MODULE1[3433] <= 8'b00000000;
MODULE1[3434] <= 8'b00000110;
MODULE1[3435] <= 8'b00000000;
MODULE1[3436] <= 8'b00000110;
MODULE1[3437] <= 8'b00000000;
MODULE1[3438] <= 8'b00000110;
MODULE1[3439] <= 8'b11100000;
MODULE1[3440] <= 8'b00000110;
MODULE1[3441] <= 8'b11000000;
MODULE1[3442] <= 8'b00000111;
MODULE1[3443] <= 8'b10000000;
MODULE1[3444] <= 8'b00000111;
MODULE1[3445] <= 8'b11000000;
MODULE1[3446] <= 8'b00000110;
MODULE1[3447] <= 8'b11000000;
MODULE1[3448] <= 8'b00000110;
MODULE1[3449] <= 8'b01100000;
MODULE1[3450] <= 8'b00000000;
MODULE1[3451] <= 8'b00000000;
MODULE1[3452] <= 8'b00000000;
MODULE1[3453] <= 8'b00000000;
MODULE1[3454] <= 8'b00000000;
MODULE1[3455] <= 8'b00000000;
MODULE1[3456] <= 8'b00000000;
MODULE1[3457] <= 8'b00000000;
MODULE1[3458] <= 8'b00000000;
MODULE1[3459] <= 8'b00000000;
MODULE1[3460] <= 8'b00000000;
MODULE1[3461] <= 8'b00000000;
MODULE1[3462] <= 8'b00000000;
MODULE1[3463] <= 8'b00000000;
MODULE1[3464] <= 8'b00000011;
MODULE1[3465] <= 8'b00000000;
MODULE1[3466] <= 8'b00000011;
MODULE1[3467] <= 8'b00000000;
MODULE1[3468] <= 8'b00000011;
MODULE1[3469] <= 8'b00000000;
MODULE1[3470] <= 8'b00000011;
MODULE1[3471] <= 8'b00000000;
MODULE1[3472] <= 8'b00000011;
MODULE1[3473] <= 8'b00000000;
MODULE1[3474] <= 8'b00000011;
MODULE1[3475] <= 8'b00000000;
MODULE1[3476] <= 8'b00000011;
MODULE1[3477] <= 8'b00000000;
MODULE1[3478] <= 8'b00000011;
MODULE1[3479] <= 8'b00000000;
MODULE1[3480] <= 8'b00000011;
MODULE1[3481] <= 8'b00000000;
MODULE1[3482] <= 8'b00000000;
MODULE1[3483] <= 8'b00000000;
MODULE1[3484] <= 8'b00000000;
MODULE1[3485] <= 8'b00000000;
MODULE1[3486] <= 8'b00000000;
MODULE1[3487] <= 8'b00000000;
MODULE1[3488] <= 8'b00000000;
MODULE1[3489] <= 8'b00000000;
MODULE1[3490] <= 8'b00000000;
MODULE1[3491] <= 8'b00000000;
MODULE1[3492] <= 8'b00000000;
MODULE1[3493] <= 8'b00000000;
MODULE1[3494] <= 8'b00000000;
MODULE1[3495] <= 8'b00000000;
MODULE1[3496] <= 8'b00000000;
MODULE1[3497] <= 8'b00000000;
MODULE1[3498] <= 8'b00000000;
MODULE1[3499] <= 8'b00000000;
MODULE1[3500] <= 8'b00000000;
MODULE1[3501] <= 8'b00000000;
MODULE1[3502] <= 8'b00001111;
MODULE1[3503] <= 8'b11100000;
MODULE1[3504] <= 8'b00001111;
MODULE1[3505] <= 8'b11100000;
MODULE1[3506] <= 8'b00001101;
MODULE1[3507] <= 8'b11100000;
MODULE1[3508] <= 8'b00001101;
MODULE1[3509] <= 8'b10100000;
MODULE1[3510] <= 8'b00001101;
MODULE1[3511] <= 8'b10110000;
MODULE1[3512] <= 8'b00001101;
MODULE1[3513] <= 8'b10110000;
MODULE1[3514] <= 8'b00000000;
MODULE1[3515] <= 8'b00000000;
MODULE1[3516] <= 8'b00000000;
MODULE1[3517] <= 8'b00000000;
MODULE1[3518] <= 8'b00000000;
MODULE1[3519] <= 8'b00000000;
MODULE1[3520] <= 8'b00000000;
MODULE1[3521] <= 8'b00000000;
MODULE1[3522] <= 8'b00000000;
MODULE1[3523] <= 8'b00000000;
MODULE1[3524] <= 8'b00000000;
MODULE1[3525] <= 8'b00000000;
MODULE1[3526] <= 8'b00000000;
MODULE1[3527] <= 8'b00000000;
MODULE1[3528] <= 8'b00000000;
MODULE1[3529] <= 8'b00000000;
MODULE1[3530] <= 8'b00000000;
MODULE1[3531] <= 8'b00000000;
MODULE1[3532] <= 8'b00000000;
MODULE1[3533] <= 8'b00000000;
MODULE1[3534] <= 8'b00000111;
MODULE1[3535] <= 8'b11000000;
MODULE1[3536] <= 8'b00000111;
MODULE1[3537] <= 8'b11000000;
MODULE1[3538] <= 8'b00000110;
MODULE1[3539] <= 8'b01100000;
MODULE1[3540] <= 8'b00000110;
MODULE1[3541] <= 8'b01100000;
MODULE1[3542] <= 8'b00000110;
MODULE1[3543] <= 8'b01100000;
MODULE1[3544] <= 8'b00000110;
MODULE1[3545] <= 8'b01100000;
MODULE1[3546] <= 8'b00000000;
MODULE1[3547] <= 8'b00000000;
MODULE1[3548] <= 8'b00000000;
MODULE1[3549] <= 8'b00000000;
MODULE1[3550] <= 8'b00000000;
MODULE1[3551] <= 8'b00000000;
MODULE1[3552] <= 8'b00000000;
MODULE1[3553] <= 8'b00000000;
MODULE1[3554] <= 8'b00000000;
MODULE1[3555] <= 8'b00000000;
MODULE1[3556] <= 8'b00000000;
MODULE1[3557] <= 8'b00000000;
MODULE1[3558] <= 8'b00000000;
MODULE1[3559] <= 8'b00000000;
MODULE1[3560] <= 8'b00000000;
MODULE1[3561] <= 8'b00000000;
MODULE1[3562] <= 8'b00000000;
MODULE1[3563] <= 8'b00000000;
MODULE1[3564] <= 8'b00000000;
MODULE1[3565] <= 8'b00000000;
MODULE1[3566] <= 8'b00000011;
MODULE1[3567] <= 8'b11000000;
MODULE1[3568] <= 8'b00000110;
MODULE1[3569] <= 8'b11000000;
MODULE1[3570] <= 8'b00000110;
MODULE1[3571] <= 8'b01000000;
MODULE1[3572] <= 8'b00000110;
MODULE1[3573] <= 8'b01000000;
MODULE1[3574] <= 8'b00000110;
MODULE1[3575] <= 8'b11000000;
MODULE1[3576] <= 8'b00000011;
MODULE1[3577] <= 8'b10000000;
MODULE1[3578] <= 8'b00000000;
MODULE1[3579] <= 8'b00000000;
MODULE1[3580] <= 8'b00000000;
MODULE1[3581] <= 8'b00000000;
MODULE1[3582] <= 8'b00000000;
MODULE1[3583] <= 8'b00000000;
MODULE1[3584] <= 8'b00000000;
MODULE1[3585] <= 8'b00000000;
MODULE1[3586] <= 8'b00000000;
MODULE1[3587] <= 8'b00000000;
MODULE1[3588] <= 8'b00000000;
MODULE1[3589] <= 8'b00000000;
MODULE1[3590] <= 8'b00000000;
MODULE1[3591] <= 8'b00000000;
MODULE1[3592] <= 8'b00000000;
MODULE1[3593] <= 8'b00000000;
MODULE1[3594] <= 8'b00000000;
MODULE1[3595] <= 8'b00000000;
MODULE1[3596] <= 8'b00000000;
MODULE1[3597] <= 8'b00000000;
MODULE1[3598] <= 8'b00000111;
MODULE1[3599] <= 8'b11000000;
MODULE1[3600] <= 8'b00000110;
MODULE1[3601] <= 8'b11000000;
MODULE1[3602] <= 8'b00000110;
MODULE1[3603] <= 8'b01100000;
MODULE1[3604] <= 8'b00000110;
MODULE1[3605] <= 8'b01100000;
MODULE1[3606] <= 8'b00000110;
MODULE1[3607] <= 8'b11000000;
MODULE1[3608] <= 8'b00000111;
MODULE1[3609] <= 8'b11000000;
MODULE1[3610] <= 8'b00000110;
MODULE1[3611] <= 8'b00000000;
MODULE1[3612] <= 8'b00000110;
MODULE1[3613] <= 8'b00000000;
MODULE1[3614] <= 8'b00000110;
MODULE1[3615] <= 8'b00000000;
MODULE1[3616] <= 8'b00000000;
MODULE1[3617] <= 8'b00000000;
MODULE1[3618] <= 8'b00000000;
MODULE1[3619] <= 8'b00000000;
MODULE1[3620] <= 8'b00000000;
MODULE1[3621] <= 8'b00000000;
MODULE1[3622] <= 8'b00000000;
MODULE1[3623] <= 8'b00000000;
MODULE1[3624] <= 8'b00000000;
MODULE1[3625] <= 8'b00000000;
MODULE1[3626] <= 8'b00000000;
MODULE1[3627] <= 8'b00000000;
MODULE1[3628] <= 8'b00000000;
MODULE1[3629] <= 8'b00000000;
MODULE1[3630] <= 8'b00000011;
MODULE1[3631] <= 8'b11000000;
MODULE1[3632] <= 8'b00000110;
MODULE1[3633] <= 8'b11000000;
MODULE1[3634] <= 8'b00000110;
MODULE1[3635] <= 8'b11000000;
MODULE1[3636] <= 8'b00000110;
MODULE1[3637] <= 8'b11000000;
MODULE1[3638] <= 8'b00000110;
MODULE1[3639] <= 8'b11000000;
MODULE1[3640] <= 8'b00000011;
MODULE1[3641] <= 8'b11000000;
MODULE1[3642] <= 8'b00000000;
MODULE1[3643] <= 8'b11000000;
MODULE1[3644] <= 8'b00000000;
MODULE1[3645] <= 8'b11000000;
MODULE1[3646] <= 8'b00000000;
MODULE1[3647] <= 8'b11000000;
MODULE1[3648] <= 8'b00000000;
MODULE1[3649] <= 8'b00000000;
MODULE1[3650] <= 8'b00000000;
MODULE1[3651] <= 8'b00000000;
MODULE1[3652] <= 8'b00000000;
MODULE1[3653] <= 8'b00000000;
MODULE1[3654] <= 8'b00000000;
MODULE1[3655] <= 8'b00000000;
MODULE1[3656] <= 8'b00000000;
MODULE1[3657] <= 8'b00000000;
MODULE1[3658] <= 8'b00000000;
MODULE1[3659] <= 8'b00000000;
MODULE1[3660] <= 8'b00000000;
MODULE1[3661] <= 8'b00000000;
MODULE1[3662] <= 8'b00000011;
MODULE1[3663] <= 8'b11100000;
MODULE1[3664] <= 8'b00000011;
MODULE1[3665] <= 8'b01100000;
MODULE1[3666] <= 8'b00000011;
MODULE1[3667] <= 8'b00000000;
MODULE1[3668] <= 8'b00000011;
MODULE1[3669] <= 8'b00000000;
MODULE1[3670] <= 8'b00000011;
MODULE1[3671] <= 8'b00000000;
MODULE1[3672] <= 8'b00000011;
MODULE1[3673] <= 8'b00000000;
MODULE1[3674] <= 8'b00000000;
MODULE1[3675] <= 8'b00000000;
MODULE1[3676] <= 8'b00000000;
MODULE1[3677] <= 8'b00000000;
MODULE1[3678] <= 8'b00000000;
MODULE1[3679] <= 8'b00000000;
MODULE1[3680] <= 8'b00000000;
MODULE1[3681] <= 8'b00000000;
MODULE1[3682] <= 8'b00000000;
MODULE1[3683] <= 8'b00000000;
MODULE1[3684] <= 8'b00000000;
MODULE1[3685] <= 8'b00000000;
MODULE1[3686] <= 8'b00000000;
MODULE1[3687] <= 8'b00000000;
MODULE1[3688] <= 8'b00000000;
MODULE1[3689] <= 8'b00000000;
MODULE1[3690] <= 8'b00000000;
MODULE1[3691] <= 8'b00000000;
MODULE1[3692] <= 8'b00000000;
MODULE1[3693] <= 8'b00000000;
MODULE1[3694] <= 8'b00000000;
MODULE1[3695] <= 8'b11100000;
MODULE1[3696] <= 8'b00000011;
MODULE1[3697] <= 8'b00000000;
MODULE1[3698] <= 8'b00000011;
MODULE1[3699] <= 8'b10000000;
MODULE1[3700] <= 8'b00000000;
MODULE1[3701] <= 8'b11000000;
MODULE1[3702] <= 8'b00000000;
MODULE1[3703] <= 8'b01100000;
MODULE1[3704] <= 8'b00000111;
MODULE1[3705] <= 8'b11000000;
MODULE1[3706] <= 8'b00000000;
MODULE1[3707] <= 8'b00000000;
MODULE1[3708] <= 8'b00000000;
MODULE1[3709] <= 8'b00000000;
MODULE1[3710] <= 8'b00000000;
MODULE1[3711] <= 8'b00000000;
MODULE1[3712] <= 8'b00000000;
MODULE1[3713] <= 8'b00000000;
MODULE1[3714] <= 8'b00000000;
MODULE1[3715] <= 8'b00000000;
MODULE1[3716] <= 8'b00000000;
MODULE1[3717] <= 8'b00000000;
MODULE1[3718] <= 8'b00000000;
MODULE1[3719] <= 8'b00000000;
MODULE1[3720] <= 8'b00000000;
MODULE1[3721] <= 8'b00000000;
MODULE1[3722] <= 8'b00000001;
MODULE1[3723] <= 8'b10000000;
MODULE1[3724] <= 8'b00000001;
MODULE1[3725] <= 8'b10000000;
MODULE1[3726] <= 8'b00000111;
MODULE1[3727] <= 8'b11000000;
MODULE1[3728] <= 8'b00000001;
MODULE1[3729] <= 8'b10000000;
MODULE1[3730] <= 8'b00000001;
MODULE1[3731] <= 8'b10000000;
MODULE1[3732] <= 8'b00000001;
MODULE1[3733] <= 8'b10000000;
MODULE1[3734] <= 8'b00000001;
MODULE1[3735] <= 8'b10000000;
MODULE1[3736] <= 8'b00000001;
MODULE1[3737] <= 8'b10000000;
MODULE1[3738] <= 8'b00000000;
MODULE1[3739] <= 8'b00000000;
MODULE1[3740] <= 8'b00000000;
MODULE1[3741] <= 8'b00000000;
MODULE1[3742] <= 8'b00000000;
MODULE1[3743] <= 8'b00000000;
MODULE1[3744] <= 8'b00000000;
MODULE1[3745] <= 8'b00000000;
MODULE1[3746] <= 8'b00000000;
MODULE1[3747] <= 8'b00000000;
MODULE1[3748] <= 8'b00000000;
MODULE1[3749] <= 8'b00000000;
MODULE1[3750] <= 8'b00000000;
MODULE1[3751] <= 8'b00000000;
MODULE1[3752] <= 8'b00000000;
MODULE1[3753] <= 8'b00000000;
MODULE1[3754] <= 8'b00000000;
MODULE1[3755] <= 8'b00000000;
MODULE1[3756] <= 8'b00000000;
MODULE1[3757] <= 8'b00000000;
MODULE1[3758] <= 8'b00000110;
MODULE1[3759] <= 8'b01000000;
MODULE1[3760] <= 8'b00000110;
MODULE1[3761] <= 8'b01000000;
MODULE1[3762] <= 8'b00000110;
MODULE1[3763] <= 8'b01000000;
MODULE1[3764] <= 8'b00000110;
MODULE1[3765] <= 8'b01000000;
MODULE1[3766] <= 8'b00000110;
MODULE1[3767] <= 8'b01000000;
MODULE1[3768] <= 8'b00000111;
MODULE1[3769] <= 8'b11000000;
MODULE1[3770] <= 8'b00000000;
MODULE1[3771] <= 8'b00000000;
MODULE1[3772] <= 8'b00000000;
MODULE1[3773] <= 8'b00000000;
MODULE1[3774] <= 8'b00000000;
MODULE1[3775] <= 8'b00000000;
MODULE1[3776] <= 8'b00000000;
MODULE1[3777] <= 8'b00000000;
MODULE1[3778] <= 8'b00000000;
MODULE1[3779] <= 8'b00000000;
MODULE1[3780] <= 8'b00000000;
MODULE1[3781] <= 8'b00000000;
MODULE1[3782] <= 8'b00000000;
MODULE1[3783] <= 8'b00000000;
MODULE1[3784] <= 8'b00000000;
MODULE1[3785] <= 8'b00000000;
MODULE1[3786] <= 8'b00000000;
MODULE1[3787] <= 8'b00000000;
MODULE1[3788] <= 8'b00000000;
MODULE1[3789] <= 8'b00000000;
MODULE1[3790] <= 8'b00000100;
MODULE1[3791] <= 8'b11000000;
MODULE1[3792] <= 8'b00000110;
MODULE1[3793] <= 8'b11000000;
MODULE1[3794] <= 8'b00000110;
MODULE1[3795] <= 8'b11000000;
MODULE1[3796] <= 8'b00000011;
MODULE1[3797] <= 8'b10000000;
MODULE1[3798] <= 8'b00000011;
MODULE1[3799] <= 8'b10000000;
MODULE1[3800] <= 8'b00000011;
MODULE1[3801] <= 8'b00000000;
MODULE1[3802] <= 8'b00000000;
MODULE1[3803] <= 8'b00000000;
MODULE1[3804] <= 8'b00000000;
MODULE1[3805] <= 8'b00000000;
MODULE1[3806] <= 8'b00000000;
MODULE1[3807] <= 8'b00000000;
MODULE1[3808] <= 8'b00000000;
MODULE1[3809] <= 8'b00000000;
MODULE1[3810] <= 8'b00000000;
MODULE1[3811] <= 8'b00000000;
MODULE1[3812] <= 8'b00000000;
MODULE1[3813] <= 8'b00000000;
MODULE1[3814] <= 8'b00000000;
MODULE1[3815] <= 8'b00000000;
MODULE1[3816] <= 8'b00000000;
MODULE1[3817] <= 8'b00000000;
MODULE1[3818] <= 8'b00000000;
MODULE1[3819] <= 8'b00000000;
MODULE1[3820] <= 8'b00000000;
MODULE1[3821] <= 8'b00000000;
MODULE1[3822] <= 8'b00001101;
MODULE1[3823] <= 8'b11100000;
MODULE1[3824] <= 8'b00001111;
MODULE1[3825] <= 8'b11100000;
MODULE1[3826] <= 8'b00001111;
MODULE1[3827] <= 8'b11100000;
MODULE1[3828] <= 8'b00001111;
MODULE1[3829] <= 8'b11100000;
MODULE1[3830] <= 8'b00001111;
MODULE1[3831] <= 8'b11000000;
MODULE1[3832] <= 8'b00000110;
MODULE1[3833] <= 8'b11000000;
MODULE1[3834] <= 8'b00000000;
MODULE1[3835] <= 8'b00000000;
MODULE1[3836] <= 8'b00000000;
MODULE1[3837] <= 8'b00000000;
MODULE1[3838] <= 8'b00000000;
MODULE1[3839] <= 8'b00000000;
MODULE1[3840] <= 8'b00000000;
MODULE1[3841] <= 8'b00000000;
MODULE1[3842] <= 8'b00000000;
MODULE1[3843] <= 8'b00000000;
MODULE1[3844] <= 8'b00000000;
MODULE1[3845] <= 8'b00000000;
MODULE1[3846] <= 8'b00000000;
MODULE1[3847] <= 8'b00000000;
MODULE1[3848] <= 8'b00000000;
MODULE1[3849] <= 8'b00000000;
MODULE1[3850] <= 8'b00000000;
MODULE1[3851] <= 8'b00000000;
MODULE1[3852] <= 8'b00000000;
MODULE1[3853] <= 8'b00000000;
MODULE1[3854] <= 8'b00001100;
MODULE1[3855] <= 8'b11000000;
MODULE1[3856] <= 8'b00000111;
MODULE1[3857] <= 8'b11000000;
MODULE1[3858] <= 8'b00000011;
MODULE1[3859] <= 8'b10000000;
MODULE1[3860] <= 8'b00000111;
MODULE1[3861] <= 8'b00000000;
MODULE1[3862] <= 8'b00001111;
MODULE1[3863] <= 8'b10000000;
MODULE1[3864] <= 8'b00001100;
MODULE1[3865] <= 8'b11000000;
MODULE1[3866] <= 8'b00000000;
MODULE1[3867] <= 8'b00000000;
MODULE1[3868] <= 8'b00000000;
MODULE1[3869] <= 8'b00000000;
MODULE1[3870] <= 8'b00000000;
MODULE1[3871] <= 8'b00000000;
MODULE1[3872] <= 8'b00000000;
MODULE1[3873] <= 8'b00000000;
MODULE1[3874] <= 8'b00000000;
MODULE1[3875] <= 8'b00000000;
MODULE1[3876] <= 8'b00000000;
MODULE1[3877] <= 8'b00000000;
MODULE1[3878] <= 8'b00000000;
MODULE1[3879] <= 8'b00000000;
MODULE1[3880] <= 8'b00000000;
MODULE1[3881] <= 8'b00000000;
MODULE1[3882] <= 8'b00000000;
MODULE1[3883] <= 8'b00000000;
MODULE1[3884] <= 8'b00000000;
MODULE1[3885] <= 8'b00000000;
MODULE1[3886] <= 8'b00001100;
MODULE1[3887] <= 8'b01100000;
MODULE1[3888] <= 8'b00001100;
MODULE1[3889] <= 8'b11000000;
MODULE1[3890] <= 8'b00000110;
MODULE1[3891] <= 8'b11000000;
MODULE1[3892] <= 8'b00000011;
MODULE1[3893] <= 8'b10000000;
MODULE1[3894] <= 8'b00000011;
MODULE1[3895] <= 8'b10000000;
MODULE1[3896] <= 8'b00000001;
MODULE1[3897] <= 8'b10000000;
MODULE1[3898] <= 8'b00000011;
MODULE1[3899] <= 8'b00000000;
MODULE1[3900] <= 8'b00000011;
MODULE1[3901] <= 8'b00000000;
MODULE1[3902] <= 8'b00000110;
MODULE1[3903] <= 8'b00000000;
MODULE1[3904] <= 8'b00000000;
MODULE1[3905] <= 8'b00000000;
MODULE1[3906] <= 8'b00000000;
MODULE1[3907] <= 8'b00000000;
MODULE1[3908] <= 8'b00000000;
MODULE1[3909] <= 8'b00000000;
MODULE1[3910] <= 8'b00000000;
MODULE1[3911] <= 8'b00000000;
MODULE1[3912] <= 8'b00000000;
MODULE1[3913] <= 8'b00000000;
MODULE1[3914] <= 8'b00000000;
MODULE1[3915] <= 8'b00000000;
MODULE1[3916] <= 8'b00000000;
MODULE1[3917] <= 8'b00000000;
MODULE1[3918] <= 8'b00000111;
MODULE1[3919] <= 8'b11100000;
MODULE1[3920] <= 8'b00000000;
MODULE1[3921] <= 8'b11000000;
MODULE1[3922] <= 8'b00000001;
MODULE1[3923] <= 8'b10000000;
MODULE1[3924] <= 8'b00000001;
MODULE1[3925] <= 8'b10000000;
MODULE1[3926] <= 8'b00000011;
MODULE1[3927] <= 8'b00000000;
MODULE1[3928] <= 8'b00000111;
MODULE1[3929] <= 8'b11100000;
MODULE1[3930] <= 8'b00000000;
MODULE1[3931] <= 8'b00000000;
MODULE1[3932] <= 8'b00000000;
MODULE1[3933] <= 8'b00000000;
MODULE1[3934] <= 8'b00000000;
MODULE1[3935] <= 8'b00000000;
MODULE1[3936] <= 8'b00000000;
MODULE1[3937] <= 8'b00000000;
MODULE1[3938] <= 8'b00000000;
MODULE1[3939] <= 8'b00000000;
MODULE1[3940] <= 8'b00000000;
MODULE1[3941] <= 8'b00000000;
MODULE1[3942] <= 8'b00000000;
MODULE1[3943] <= 8'b00000000;
MODULE1[3944] <= 8'b00000001;
MODULE1[3945] <= 8'b11000000;
MODULE1[3946] <= 8'b00000011;
MODULE1[3947] <= 8'b00000000;
MODULE1[3948] <= 8'b00000011;
MODULE1[3949] <= 8'b00000000;
MODULE1[3950] <= 8'b00000011;
MODULE1[3951] <= 8'b00000000;
MODULE1[3952] <= 8'b00000011;
MODULE1[3953] <= 8'b00000000;
MODULE1[3954] <= 8'b00000111;
MODULE1[3955] <= 8'b00000000;
MODULE1[3956] <= 8'b00000011;
MODULE1[3957] <= 8'b00000000;
MODULE1[3958] <= 8'b00000011;
MODULE1[3959] <= 8'b00000000;
MODULE1[3960] <= 8'b00000011;
MODULE1[3961] <= 8'b00000000;
MODULE1[3962] <= 8'b00000011;
MODULE1[3963] <= 8'b00000000;
MODULE1[3964] <= 8'b00000001;
MODULE1[3965] <= 8'b11000000;
MODULE1[3966] <= 8'b00000000;
MODULE1[3967] <= 8'b00000000;
MODULE1[3968] <= 8'b00000000;
MODULE1[3969] <= 8'b00000000;
MODULE1[3970] <= 8'b00000000;
MODULE1[3971] <= 8'b00000000;
MODULE1[3972] <= 8'b00000000;
MODULE1[3973] <= 8'b00000000;
MODULE1[3974] <= 8'b00000000;
MODULE1[3975] <= 8'b00000000;
MODULE1[3976] <= 8'b00000001;
MODULE1[3977] <= 8'b10000000;
MODULE1[3978] <= 8'b00000001;
MODULE1[3979] <= 8'b10000000;
MODULE1[3980] <= 8'b00000001;
MODULE1[3981] <= 8'b10000000;
MODULE1[3982] <= 8'b00000001;
MODULE1[3983] <= 8'b10000000;
MODULE1[3984] <= 8'b00000001;
MODULE1[3985] <= 8'b10000000;
MODULE1[3986] <= 8'b00000001;
MODULE1[3987] <= 8'b10000000;
MODULE1[3988] <= 8'b00000001;
MODULE1[3989] <= 8'b10000000;
MODULE1[3990] <= 8'b00000001;
MODULE1[3991] <= 8'b10000000;
MODULE1[3992] <= 8'b00000001;
MODULE1[3993] <= 8'b10000000;
MODULE1[3994] <= 8'b00000001;
MODULE1[3995] <= 8'b10000000;
MODULE1[3996] <= 8'b00000001;
MODULE1[3997] <= 8'b10000000;
MODULE1[3998] <= 8'b00000000;
MODULE1[3999] <= 8'b00000000;
MODULE1[4000] <= 8'b00000000;
MODULE1[4001] <= 8'b00000000;
MODULE1[4002] <= 8'b00000000;
MODULE1[4003] <= 8'b00000000;
MODULE1[4004] <= 8'b00000000;
MODULE1[4005] <= 8'b00000000;
MODULE1[4006] <= 8'b00000000;
MODULE1[4007] <= 8'b00000000;
MODULE1[4008] <= 8'b00000111;
MODULE1[4009] <= 8'b00000000;
MODULE1[4010] <= 8'b00000001;
MODULE1[4011] <= 8'b10000000;
MODULE1[4012] <= 8'b00000001;
MODULE1[4013] <= 8'b10000000;
MODULE1[4014] <= 8'b00000001;
MODULE1[4015] <= 8'b10000000;
MODULE1[4016] <= 8'b00000001;
MODULE1[4017] <= 8'b10000000;
MODULE1[4018] <= 8'b00000001;
MODULE1[4019] <= 8'b11000000;
MODULE1[4020] <= 8'b00000001;
MODULE1[4021] <= 8'b10000000;
MODULE1[4022] <= 8'b00000001;
MODULE1[4023] <= 8'b10000000;
MODULE1[4024] <= 8'b00000001;
MODULE1[4025] <= 8'b10000000;
MODULE1[4026] <= 8'b00000001;
MODULE1[4027] <= 8'b10000000;
MODULE1[4028] <= 8'b00000111;
MODULE1[4029] <= 8'b00000000;
MODULE1[4030] <= 8'b00000000;
MODULE1[4031] <= 8'b00000000;
MODULE1[4032] <= 8'b00000000;
MODULE1[4033] <= 8'b00000000;
MODULE1[4034] <= 8'b00000000;
MODULE1[4035] <= 8'b00000000;
MODULE1[4036] <= 8'b00000000;
MODULE1[4037] <= 8'b00000000;
MODULE1[4038] <= 8'b00000000;
MODULE1[4039] <= 8'b00000000;
MODULE1[4040] <= 8'b00000000;
MODULE1[4041] <= 8'b00000000;
MODULE1[4042] <= 8'b00000000;
MODULE1[4043] <= 8'b00000000;
MODULE1[4044] <= 8'b00000000;
MODULE1[4045] <= 8'b00000000;
MODULE1[4046] <= 8'b00000111;
MODULE1[4047] <= 8'b01000000;
MODULE1[4048] <= 8'b00001111;
MODULE1[4049] <= 8'b11000000;
MODULE1[4050] <= 8'b00001101;
MODULE1[4051] <= 8'b11000000;
MODULE1[4052] <= 8'b00000000;
MODULE1[4053] <= 8'b00000000;
MODULE1[4054] <= 8'b00000000;
MODULE1[4055] <= 8'b00000000;
MODULE1[4056] <= 8'b00000000;
MODULE1[4057] <= 8'b00000000;
MODULE1[4058] <= 8'b00000000;
MODULE1[4059] <= 8'b00000000;
MODULE1[4060] <= 8'b00000000;
MODULE1[4061] <= 8'b00000000;
MODULE1[4062] <= 8'b00000000;
MODULE1[4063] <= 8'b00000000;
MODULE1[4064] <= 8'b00000000;
MODULE1[4065] <= 8'b00000000;
MODULE1[4066] <= 8'b00000000;
MODULE1[4067] <= 8'b00000000;
MODULE1[4068] <= 8'b00000000;
MODULE1[4069] <= 8'b00000000;
MODULE1[4070] <= 8'b00000000;
MODULE1[4071] <= 8'b00000000;
MODULE1[4072] <= 8'b00000011;
MODULE1[4073] <= 8'b10000000;
MODULE1[4074] <= 8'b00000010;
MODULE1[4075] <= 8'b10000000;
MODULE1[4076] <= 8'b00000010;
MODULE1[4077] <= 8'b10000000;
MODULE1[4078] <= 8'b00000010;
MODULE1[4079] <= 8'b10000000;
MODULE1[4080] <= 8'b00000010;
MODULE1[4081] <= 8'b10000000;
MODULE1[4082] <= 8'b00000010;
MODULE1[4083] <= 8'b10000000;
MODULE1[4084] <= 8'b00000010;
MODULE1[4085] <= 8'b10000000;
MODULE1[4086] <= 8'b00000011;
MODULE1[4087] <= 8'b10000000;
MODULE1[4088] <= 8'b00000000;
MODULE1[4089] <= 8'b00000000;
MODULE1[4090] <= 8'b00000000;
MODULE1[4091] <= 8'b00000000;
MODULE1[4092] <= 8'b00000000;
MODULE1[4093] <= 8'b00000000;
MODULE1[4094] <= 8'b00000000;
MODULE1[4095] <= 8'b00000000;
end
always @(posedge clk) begin
out <= MODULE1[address];
end
endmodule | gpl-3.0 |
jameshegarty/rigel | generators/hardfloat/source/iNToRecFN.v | 5,334 | module
MODULE1#(parameter VAR19 = 1) (VAR1, in, VAR17, VAR15, VAR7, VAR8);
localparam VAR13 = VAR9(VAR19) + 1;
input VAR1;
input [(VAR19 - 1):0] in;
output VAR17;
output VAR15;
output signed [(VAR13 + 1):0] VAR7;
output [VAR19:0] VAR8;
localparam VAR10 = 1<<(VAR13 - 1);
assign VAR15 = VAR1 && in[VAR19 - 1];
wire [(VAR19 - 1):0] VAR6 = VAR15 ? -in : in;
wire [(VAR10 - 1):0] VAR2 = VAR6;
wire [(VAR13 - 2):0] VAR3;
VAR16#(VAR10, VAR13 - 1)
VAR16(VAR2, VAR3);
assign VAR8 = (VAR2<<VAR3)>>(VAR10 - VAR19);
assign VAR17 = !VAR8[VAR19 - 1];
assign VAR7 = {2'b10, ~VAR3};
endmodule
module
MODULE2#(
parameter VAR19 = 1, parameter VAR13 = 3, parameter VAR14 = 3
) (
input [(VAR11 - 1):0] VAR4,
input VAR1,
input [(VAR19 - 1):0] in,
input [2:0] VAR21,
output [(VAR13 + VAR14):0] out,
output [4:0] VAR5
);
localparam VAR12 = VAR9(VAR19) + 1;
wire VAR17, VAR15;
wire signed [(VAR12 + 1):0] VAR7;
wire [VAR19:0] VAR8;
MODULE1#(VAR19) MODULE1(VAR1, in, VAR17, VAR15, VAR7, VAR8);
VAR18#(
VAR12,
VAR19,
VAR13,
VAR14,
) VAR20(
VAR4,
1'b0,
1'b0,
1'b0,
1'b0,
VAR17,
VAR15,
VAR7,
VAR8,
VAR21,
out,
VAR5
);
endmodule | mit |
benreynwar/fpga-sdrlib | verilog/fft/qa_stage.v | 5,098 | module MODULE1
parameter VAR60 = 32,
parameter VAR27 = 1
)
(
input wire clk,
input wire VAR63,
input wire [VAR60-1:0] VAR15,
input wire VAR1,
input wire [VAR27-1:0] VAR80,
input wire [VAR29-1:0] VAR21,
input wire VAR39,
output wire [VAR60-1:0] VAR19,
output wire VAR12,
output wire [VAR27-1:0] VAR54,
output wire [VAR29-1:0] VAR69,
output wire VAR45,
output wire VAR81
);
function integer VAR30;
input integer VAR10;
begin
VAR10 = VAR10-1;
for (VAR30=0; VAR10>0; VAR30=VAR30+1)
VAR10 = VAR10>>1;
end
endfunction
localparam integer VAR34 = VAR30(VAR65);
localparam integer VAR49 = 2'd0;
localparam integer VAR17 = 2'd1;
localparam integer VAR62 = 2'd2;
localparam integer VAR58 = 2'd3;
wire VAR38;
wire VAR70;
wire [VAR60+VAR27-1:0] VAR3;
wire VAR68;
VAR35 #(VAR60+VAR27, VAR65) VAR8
(
.clk(clk),
.VAR63(VAR63),
.VAR47(VAR1),
.VAR44({VAR15, VAR80}),
.VAR5(VAR38),
.VAR46(VAR70),
.VAR48(VAR3),
.VAR81(VAR68)
);
reg VAR20;
wire VAR57;
wire [VAR34-1:0] VAR52;
wire [VAR34-1:0] VAR76;
wire VAR37;
wire [VAR60-1:0] VAR67;
wire [VAR60-1:0] VAR14;
wire VAR22;
wire [VAR27-1:0] VAR4;
wire VAR32;
VAR40 #(VAR65, VAR34, VAR60, VAR27) VAR11
(
.clk(clk),
.VAR63(VAR63),
.VAR41(VAR20),
.VAR46(VAR70),
.VAR48(VAR3),
.VAR5(VAR38),
.VAR6(VAR52),
.VAR64(VAR76),
.VAR12(VAR37),
.VAR59(VAR67),
.VAR50(VAR14),
.VAR25(VAR22),
.VAR54(VAR4),
.VAR26(VAR57),
.VAR81(VAR32)
);
wire VAR28;
wire VAR33;
wire VAR55;
wire [VAR27-1:0] VAR79;
VAR35 #(VAR27, VAR65*2) VAR7
(
.clk(clk),
.VAR63(VAR63),
.VAR47(VAR22),
.VAR44(VAR4),
.VAR5(VAR28),
.VAR46(VAR55),
.VAR48(VAR79),
.VAR81(VAR33)
);
wire [VAR34-1:0] VAR18;
wire [VAR34-1:0] VAR24; wire [VAR60-1:0] VAR23;
wire [VAR60-1:0] VAR77;
wire VAR42;
wire [1:0] VAR66;
wire VAR56;
VAR31 #(VAR65, VAR34, VAR60) VAR2
(
.clk(clk),
.VAR63(VAR63),
.VAR75(VAR52),
.VAR9(VAR76),
.VAR1(VAR37),
.VAR16(VAR67),
.VAR61(VAR14),
.VAR78(VAR57),
.VAR6(VAR18),
.VAR64(VAR24),
.VAR59(VAR23),
.VAR50(VAR77),
.VAR51(VAR56),
.state(VAR66),
.VAR81(VAR42)
);
reg VAR43;
wire VAR72;
VAR73 #(VAR65, VAR34, VAR60, VAR27) VAR13
(
.clk(clk),
.VAR63(VAR63),
.VAR41(VAR43),
.addr(VAR18),
.VAR15(VAR23),
.VAR36(VAR28),
.VAR80(VAR79),
.VAR12(VAR12),
.VAR19(VAR19),
.VAR54(VAR54),
.VAR26(VAR56),
.VAR81(VAR72)
);
reg VAR71;
assign VAR74 = (VAR71)?VAR52:VAR18;
assign VAR53 = VAR76;
always @ (posedge clk)
if (~VAR63)
begin
VAR71 <= 1'b1;
VAR20 <= 1'b1;
VAR43 <= 1'b0;
end
else
begin
VAR20 <= 1'b0;
VAR43 <= 1'b0;
if (VAR66 == VAR49)
VAR20 <= 1'b1;
end
else if (VAR66 == VAR62)
VAR43 <= 1'b1;
end
assign VAR81 = VAR68 | VAR32 | VAR33 | VAR42 | VAR72;
endmodule | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_19.v | 16,187 | module MODULE1 (
clk,
reset,
VAR112,
VAR125,
VAR68,
VAR44,
VAR67
);
parameter VAR88 = 18;
parameter VAR69 = 19;
parameter VAR41 = 10;
localparam VAR129 = 25;
input clk;
input reset;
input VAR112;
input VAR125;
input [VAR88-1:0] VAR68; output VAR44;
output [VAR88-1:0] VAR67;
localparam VAR2 = 18; localparam VAR75 = 36; localparam VAR34 = 17;
localparam VAR126 = 19;
reg [VAR88-1:0] VAR94;
reg [VAR88-1:0] VAR40;
reg [VAR88-1:0] VAR27;
reg [VAR88-1:0] VAR20;
reg [VAR88-1:0] VAR16;
reg [VAR88-1:0] VAR39;
reg [VAR88-1:0] VAR120;
reg [VAR88-1:0] VAR45;
reg [VAR88-1:0] VAR18;
reg [VAR88-1:0] VAR19;
always@(posedge clk) begin
VAR94 <= 18'd88;
VAR40 <= 18'd0;
VAR27 <= -18'd97;
VAR20 <= -18'd197;
VAR16 <= -18'd294;
VAR39 <= -18'd380;
VAR120 <= -18'd447;
VAR45 <= -18'd490;
VAR18 <= -18'd504;
VAR19 <= -18'd481;
end
reg [VAR129-1:0] VAR115;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR115 <= 0;
end else begin
if(VAR112) begin
VAR115 <= {VAR115[VAR129-2:0], VAR125};
end else begin
VAR115 <= VAR115;
end
end
end
wire [VAR88-1:0] VAR63;
wire [VAR88-1:0] VAR72;
wire [VAR88-1:0] VAR102;
wire [VAR88-1:0] VAR92;
wire [VAR88-1:0] VAR7;
wire [VAR88-1:0] VAR104;
wire [VAR88-1:0] VAR76;
wire [VAR88-1:0] VAR5;
wire [VAR88-1:0] VAR12;
wire [VAR88-1:0] VAR26;
wire [VAR88-1:0] VAR35;
wire [VAR88-1:0] VAR21;
wire [VAR88-1:0] VAR113;
wire [VAR88-1:0] VAR103;
wire [VAR88-1:0] VAR17;
wire [VAR88-1:0] VAR28;
wire [VAR88-1:0] VAR48;
wire [VAR88-1:0] VAR86;
wire [VAR88-1:0] VAR91;
MODULE5 MODULE10(
.clk(clk), .VAR112(VAR112),
.VAR50(VAR68),
.VAR82(VAR63),
.VAR83(VAR72),
.VAR108(VAR102),
.VAR4(VAR92),
.VAR95(VAR7),
.VAR84(VAR104),
.VAR64(VAR76),
.VAR109(VAR5),
.VAR121(VAR12),
.VAR54(VAR26),
.VAR11(VAR35),
.VAR47(VAR21),
.VAR51(VAR113),
.VAR25(VAR103),
.VAR93(VAR17),
.VAR37(VAR28),
.VAR15(VAR48),
.VAR70(VAR86),
.VAR14(VAR91),
.reset(reset) );
wire [VAR88-1:0] VAR53;
wire [VAR88-1:0] VAR81;
wire [VAR88-1:0] VAR42;
wire [VAR88-1:0] VAR66;
wire [VAR88-1:0] VAR110;
wire [VAR88-1:0] VAR96;
wire [VAR88-1:0] VAR24;
wire [VAR88-1:0] VAR13;
wire [VAR88-1:0] VAR85;
wire [VAR88-1:0] VAR79;
MODULE3 VAR77(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR63),
.VAR30 (VAR91),
.VAR38(VAR53)
);
MODULE3 VAR10(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR72),
.VAR30 (VAR86),
.VAR38(VAR81)
);
MODULE3 VAR36(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR102),
.VAR30 (VAR48),
.VAR38(VAR42)
);
MODULE3 VAR124(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR92),
.VAR30 (VAR28),
.VAR38(VAR66)
);
MODULE3 VAR105(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR7),
.VAR30 (VAR17),
.VAR38(VAR110)
);
MODULE3 VAR78(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR104),
.VAR30 (VAR103),
.VAR38(VAR96)
);
MODULE3 VAR6(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR76),
.VAR30 (VAR113),
.VAR38(VAR24)
);
MODULE3 VAR127(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR5),
.VAR30 (VAR21),
.VAR38(VAR13)
);
MODULE3 VAR1(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR12),
.VAR30 (VAR35),
.VAR38(VAR85)
);
MODULE4 VAR60(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR26),
.VAR38(VAR79)
);
wire [VAR88-1:0] VAR116;
wire [VAR88-1:0] VAR9;
wire [VAR88-1:0] VAR117;
wire [VAR88-1:0] VAR122;
wire [VAR88-1:0] VAR99;
wire [VAR88-1:0] VAR57;
wire [VAR88-1:0] VAR22;
wire [VAR88-1:0] VAR123;
wire [VAR88-1:0] VAR43;
wire [VAR88-1:0] VAR46;
MODULE2 VAR29(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR53),
.VAR30 (VAR94),
.VAR38(VAR116)
);
MODULE2 VAR59(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR81),
.VAR30 (VAR40),
.VAR38(VAR9)
);
MODULE2 VAR65(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR42),
.VAR30 (VAR27),
.VAR38(VAR117)
);
MODULE2 VAR73(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR66),
.VAR30 (VAR20),
.VAR38(VAR122)
);
MODULE2 VAR114(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR110),
.VAR30 (VAR16),
.VAR38(VAR99)
);
MODULE2 VAR101(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR96),
.VAR30 (VAR39),
.VAR38(VAR57)
);
MODULE2 VAR87(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR24),
.VAR30 (VAR120),
.VAR38(VAR22)
);
MODULE2 VAR106(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR13),
.VAR30 (VAR45),
.VAR38(VAR123)
);
MODULE2 VAR118(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR85),
.VAR30 (VAR18),
.VAR38(VAR43)
);
MODULE2 VAR97(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR79),
.VAR30 (VAR19),
.VAR38(VAR46)
);
wire [VAR88-1:0] VAR56;
wire [VAR88-1:0] VAR80;
wire [VAR88-1:0] VAR119;
wire [VAR88-1:0] VAR107;
wire [VAR88-1:0] VAR130;
MODULE3 VAR31(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR116),
.VAR30 (VAR9),
.VAR38(VAR56)
);
MODULE3 VAR74(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR117),
.VAR30 (VAR122),
.VAR38(VAR80)
);
MODULE3 VAR55(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR99),
.VAR30 (VAR57),
.VAR38(VAR119)
);
MODULE3 VAR23(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR22),
.VAR30 (VAR123),
.VAR38(VAR107)
);
MODULE3 VAR100(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR43),
.VAR30 (VAR46),
.VAR38(VAR130)
);
wire [VAR88-1:0] VAR98;
wire [VAR88-1:0] VAR32;
wire [VAR88-1:0] VAR90;
MODULE3 VAR89(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR56),
.VAR30 (VAR80),
.VAR38(VAR98)
);
MODULE3 VAR33(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR119),
.VAR30 (VAR107),
.VAR38(VAR32)
);
MODULE4 VAR62(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR130),
.VAR38(VAR90)
);
wire [VAR88-1:0] VAR3;
wire [VAR88-1:0] VAR61;
MODULE3 VAR8(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR98),
.VAR30 (VAR32),
.VAR38(VAR3)
);
MODULE4 VAR111(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR90),
.VAR38(VAR61)
);
wire [VAR88-1:0] VAR58;
MODULE3 VAR128(
.clk(clk), .VAR112(VAR112),
.VAR52 (VAR3),
.VAR30 (VAR61),
.VAR38(VAR58)
);
assign VAR67 = VAR58;
assign VAR44 = VAR115[VAR129-1];
endmodule
module MODULE5 (
clk,
VAR112,
VAR50,
VAR82,
VAR83,
VAR108,
VAR4,
VAR95,
VAR84,
VAR64,
VAR109,
VAR121,
VAR54,
VAR11,
VAR47,
VAR51,
VAR25,
VAR93,
VAR37,
VAR15,
VAR70,
VAR14,
reset);
parameter VAR71 = 1;
input clk;
input VAR112;
input [VAR71-1:0] VAR50;
output [VAR71-1:0] VAR82;
output [VAR71-1:0] VAR83;
output [VAR71-1:0] VAR108;
output [VAR71-1:0] VAR4;
output [VAR71-1:0] VAR95;
output [VAR71-1:0] VAR84;
output [VAR71-1:0] VAR64;
output [VAR71-1:0] VAR109;
output [VAR71-1:0] VAR121;
output [VAR71-1:0] VAR54;
output [VAR71-1:0] VAR11;
output [VAR71-1:0] VAR47;
output [VAR71-1:0] VAR51;
output [VAR71-1:0] VAR25;
output [VAR71-1:0] VAR93;
output [VAR71-1:0] VAR37;
output [VAR71-1:0] VAR15;
output [VAR71-1:0] VAR70;
output [VAR71-1:0] VAR14;
reg [VAR71-1:0] VAR82;
reg [VAR71-1:0] VAR83;
reg [VAR71-1:0] VAR108;
reg [VAR71-1:0] VAR4;
reg [VAR71-1:0] VAR95;
reg [VAR71-1:0] VAR84;
reg [VAR71-1:0] VAR64;
reg [VAR71-1:0] VAR109;
reg [VAR71-1:0] VAR121;
reg [VAR71-1:0] VAR54;
reg [VAR71-1:0] VAR11;
reg [VAR71-1:0] VAR47;
reg [VAR71-1:0] VAR51;
reg [VAR71-1:0] VAR25;
reg [VAR71-1:0] VAR93;
reg [VAR71-1:0] VAR37;
reg [VAR71-1:0] VAR15;
reg [VAR71-1:0] VAR70;
reg [VAR71-1:0] VAR14;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
VAR82 <= 0;
VAR83 <= 0;
VAR108 <= 0;
VAR4 <= 0;
VAR95 <= 0;
VAR84 <= 0;
VAR64 <= 0;
VAR109 <= 0;
VAR121 <= 0;
VAR54 <= 0;
VAR11 <= 0;
VAR47 <= 0;
VAR51 <= 0;
VAR25 <= 0;
VAR93 <= 0;
VAR37 <= 0;
VAR15 <= 0;
VAR70 <= 0;
VAR14 <= 0;
end else begin
if(VAR112) begin
VAR82 <= VAR50;
VAR83 <= VAR82;
VAR108 <= VAR83;
VAR4 <= VAR108;
VAR95 <= VAR4;
VAR84 <= VAR95;
VAR64 <= VAR84;
VAR109 <= VAR64;
VAR121 <= VAR109;
VAR54 <= VAR121;
VAR11 <= VAR54;
VAR47 <= VAR11;
VAR51 <= VAR47;
VAR25 <= VAR51;
VAR93 <= VAR25;
VAR37 <= VAR93;
VAR15 <= VAR37;
VAR70 <= VAR15;
VAR14 <= VAR70;
end end
end
endmodule
module MODULE3 (
clk,
VAR112,
VAR52,
VAR30,
VAR38);
input clk;
input VAR112;
input [17:0] VAR52;
input [17:0] VAR30;
output [17:0] VAR38;
reg [17:0] VAR38;
always @(posedge clk) begin
if(VAR112) begin
VAR38 <= VAR52 + VAR30;
end
end
endmodule
module MODULE2 (
clk,
VAR112,
VAR52,
VAR30,
VAR38);
input clk;
input VAR112;
input [17:0] VAR52;
input [17:0] VAR30;
output [17:0] VAR38;
reg [17:0] VAR38;
always @(posedge clk) begin
if(VAR112) begin
VAR38 <= VAR52 * VAR30;
end
end
endmodule
module MODULE4 (
clk,
VAR112,
VAR52,
VAR38);
input clk;
input VAR112;
input [17:0] VAR52;
output [17:0] VAR38;
reg [17:0] VAR38;
always @(posedge clk) begin
if(VAR112) begin
VAR38 <= VAR52;
end
end
endmodule | mit |
orbancedric/DeepGate | other/convPrototype/DeepGATE_top.v | 6,059 | module MODULE1(
input clk,
input VAR1,
input VAR57,
output wire [7:0]VAR46,
input VAR60,
input VAR39,
input VAR14,
output reg VAR82,
output VAR20,
input VAR79,
input VAR75,
input VAR71,
output [3:0] VAR44,
input VAR3, output VAR54, input VAR77,
output VAR33,
output VAR66,
output VAR7,
output VAR69,
output VAR65,
output VAR78,
output VAR24,
output [1:0] VAR40,
output [12:0] VAR34,
inout [7:0] VAR31
);
wire rst = ~VAR1; wire [7:0] VAR2;
wire VAR43;
wire [7:0] VAR22;
wire VAR9;
reg [7:0] VAR76 = 0;
reg [7:0] VAR81 = 0;
reg VAR48 = 0;
VAR18 VAR74 (
.clk (clk),
.rst (rst),
.VAR57 (VAR57),
.VAR20 (VAR20),
.VAR75 (VAR75),
.VAR71 (VAR71),
.VAR79 (VAR79),
.VAR44 (VAR44),
.VAR25 (VAR54),
.VAR13 (VAR3),
.VAR8 (4'd15),
.VAR2 (VAR2),
.VAR48 (VAR48),
.VAR43 (VAR43),
.VAR17 (VAR77),
.VAR22 (VAR22),
.VAR9 (VAR9)
);
wire [31:0] VAR58;
wire [22:0] VAR28;
wire VAR12;
wire VAR27;
reg [31:0] VAR50;
reg VAR63;
reg VAR10 = 0;
VAR4 VAR15 (
.clk (clk),
.rst (rst),
.VAR33 (VAR33),
.VAR66 (VAR66),
.VAR69 (VAR69),
.VAR78 (VAR78),
.VAR24 (VAR24),
.VAR65 (VAR65),
.VAR7 (VAR7),
.VAR40 (VAR40),
.VAR34 (VAR34),
.VAR31 (VAR31),
.addr (VAR28), .VAR49 (VAR10), .VAR21 (VAR50), .VAR52 (VAR58), .VAR19 (VAR12), .VAR53 (VAR63), .VAR73 (VAR27)
);
wire [7:0] VAR42;
wire VAR37;
wire VAR47;
wire [7:0] VAR64;
reg [31:0] VAR6 = 0;
reg [7:0] VAR36 = 0;
reg [7:0] VAR61 = 0;
reg VAR80 = 0;
reg VAR16 = 0;
reg VAR62 = 0;
reg [7:0] VAR70 = 0;
VAR32 VAR26(
.clk (clk),
.VAR80 (VAR80),
.VAR55 (VAR70),
.wr (VAR62),
.VAR51 (VAR61),
.VAR29 (48'hBABEFACEBABE),
.VAR37 (VAR37),
.VAR42 (VAR42),
.VAR23 (VAR47)
);
reg VAR59 = 0;
reg VAR5 = 0;
reg VAR38 = 0;
reg VAR30 = 0;
reg [22:0] VAR35 = 0;
reg [22:0] VAR45 = 0;
reg [22:0] VAR68 = 0;
reg [23:0] VAR41 = 0;
reg [79:0] VAR56 = 0;
reg [31:0] VAR67 = 0;
reg [7:0] VAR11 [783 : 0];
reg [7:0] VAR72 = 0;
assign VAR2 = !VAR59 ? VAR76 : VAR56[7:0];
assign VAR46 = VAR81;
assign VAR28 = !VAR5 ? VAR45 : VAR35;
always@(posedge clk) begin
VAR10 <= 0;
VAR63 <= 0;
VAR80 <= 0;
VAR48 <= 0;
if(VAR9 && !VAR5) begin
VAR45 <= VAR45 + 1'b1;
VAR81 <= VAR22;
VAR11[VAR45] <= VAR22;
VAR41 <= {VAR41[15:0], VAR22};
end
else if(!VAR43 && !VAR48 && (VAR5 || VAR59)) begin
VAR48 <= 1'b1;
VAR35 <= VAR35 + 1'b1;
VAR76 <= VAR11[VAR35];
end
if(VAR45 == 784) begin
VAR45 <= 0;
VAR5 <= 1;
end
if(VAR35 == 784) begin
VAR5 <= 0;
VAR35 <= 0;
end
if(VAR5)
VAR67 <= VAR67 + 1'b1;
if(!VAR12 && !VAR63) begin
if(!VAR5) begin
VAR50 <= VAR81;
VAR10 <= 1;
end
VAR63 <= 1;
end
if(VAR41 == 24'h262626) VAR59 <= 1;
if(VAR47)
VAR56 <= {VAR56[71:0], VAR42};
end
else if(!VAR47 && !VAR43 && !VAR48)
VAR56 <= {VAR56[71:0], VAR56[79:72]} ;
if(VAR59 && VAR37 && !VAR16) begin
VAR80 <= 1;
VAR16 <= 1;
end
if(((VAR16 && !VAR80 && VAR6 == 0) || (VAR6 > 0 && VAR6 < 784)) && !VAR72) begin
VAR6 <= VAR6 + 1'b1;
VAR70 <= VAR11[VAR6];
end
if(VAR6 == 784) begin
VAR72 <= VAR72 + 1'b1;
if(VAR72 == 10) begin
VAR6 <= 0;
VAR72 <= 0;
end
end
end
endmodule | gpl-3.0 |
alexforencich/xfcp | lib/eth/rtl/arp.v | 17,469 | module MODULE1 #
(
parameter VAR123 = 8,
parameter VAR48 = (VAR123>8),
parameter VAR20 = (VAR123/8),
parameter VAR9 = 9,
parameter VAR31 = 4,
parameter VAR119 = 125000000*2,
parameter VAR101 = 125000000*30
)
(
input wire clk,
input wire rst,
input wire VAR24,
output wire VAR38,
input wire [47:0] VAR84,
input wire [47:0] VAR7,
input wire [15:0] VAR91,
input wire [VAR123-1:0] VAR3,
input wire [VAR20-1:0] VAR76,
input wire VAR53,
output wire VAR106,
input wire VAR69,
input wire VAR60,
output wire VAR27,
input wire VAR133,
output wire [47:0] VAR136,
output wire [47:0] VAR113,
output wire [15:0] VAR26,
output wire [VAR123-1:0] VAR86,
output wire [VAR20-1:0] VAR55,
output wire VAR14,
input wire VAR112,
output wire VAR40,
output wire VAR118,
input wire VAR12,
output wire VAR52,
input wire [31:0] VAR130,
output wire VAR71,
input wire VAR109,
output wire VAR51,
output wire [47:0] VAR103,
input wire [47:0] VAR18,
input wire [31:0] VAR28,
input wire [31:0] VAR96,
input wire [31:0] VAR10,
input wire VAR33
);
localparam [15:0]
VAR23 = 16'h0001,
VAR115 = 16'h0002,
VAR139 = 16'h0008,
VAR43 = 16'h0009;
wire VAR116;
reg VAR94;
wire [47:0] VAR104;
wire [47:0] VAR80;
wire [15:0] VAR2;
wire [15:0] VAR59;
wire [15:0] VAR5;
wire [7:0] VAR114;
wire [7:0] VAR121;
wire [15:0] VAR49;
wire [47:0] VAR46;
wire [31:0] VAR81;
wire [47:0] VAR8;
wire [31:0] VAR15;
VAR17 #(
.VAR123(VAR123),
.VAR48(VAR48),
.VAR20(VAR20)
)
VAR99 (
.clk(clk),
.rst(rst),
.VAR24(VAR24),
.VAR38(VAR38),
.VAR84(VAR84),
.VAR7(VAR7),
.VAR91(VAR91),
.VAR3(VAR3),
.VAR76(VAR76),
.VAR53(VAR53),
.VAR106(VAR106),
.VAR69(VAR69),
.VAR60(VAR60),
.VAR25(VAR116),
.VAR127(VAR94),
.VAR136(VAR104),
.VAR113(VAR80),
.VAR26(VAR2),
.VAR32(VAR59),
.VAR21(VAR5),
.VAR72(VAR114),
.VAR70(VAR121),
.VAR57(VAR49),
.VAR117(VAR46),
.VAR90(VAR81),
.VAR44(VAR8),
.VAR50(VAR15),
.VAR137(),
.VAR131(),
.VAR102()
);
reg VAR35 = 1'b0, VAR97;
wire VAR126;
reg [47:0] VAR122 = 48'd0, VAR65;
reg [15:0] VAR107 = 16'd0, VAR67;
reg [47:0] VAR120 = 48'd0, VAR34;
reg [31:0] VAR16 = 32'd0, VAR47;
VAR92 #(
.VAR123(VAR123),
.VAR48(VAR48),
.VAR20(VAR20)
)
VAR58 (
.clk(clk),
.rst(rst),
.VAR61(VAR35),
.VAR54(VAR126),
.VAR84(VAR122),
.VAR7(VAR18),
.VAR91(16'h0806),
.VAR22(16'h0001),
.VAR39(16'h0800),
.VAR73(VAR107),
.VAR1(VAR18),
.VAR42(VAR28),
.VAR110(VAR120),
.VAR132(VAR16),
.VAR27(VAR27),
.VAR133(VAR133),
.VAR136(VAR136),
.VAR113(VAR113),
.VAR26(VAR26),
.VAR86(VAR86),
.VAR55(VAR55),
.VAR14(VAR14),
.VAR112(VAR112),
.VAR40(VAR40),
.VAR118(VAR118),
.VAR137()
);
reg VAR64 = 1'b0, VAR68;
reg [31:0] VAR135 = 32'd0, VAR108;
wire VAR134;
wire VAR138;
wire [47:0] VAR83;
reg VAR87 = 1'b0, VAR74;
reg [31:0] VAR56 = 32'd0, VAR30;
reg [47:0] VAR62 = 48'd0, VAR11;
VAR66 #(
.VAR9(VAR9)
)
VAR111 (
.clk(clk),
.rst(rst),
.VAR41(VAR64),
.VAR93(),
.VAR4(VAR135),
.VAR82(VAR134),
.VAR129(1'b1),
.VAR100(VAR138),
.VAR36(VAR83),
.VAR77(VAR87),
.VAR85(),
.VAR88(VAR56),
.VAR63(VAR62),
.VAR33(VAR33)
);
reg VAR95 = 1'b0, VAR29;
reg VAR13 = 1'b0, VAR128;
reg [31:0] VAR79 = 32'd0, VAR37;
reg VAR98 = 1'b0, VAR6;
reg VAR75 = 1'b0, VAR78;
reg [47:0] VAR124 = 48'd0, VAR89;
reg [5:0] VAR19 = 6'd0, VAR105;
reg [35:0] VAR125 = 36'd0, VAR45;
assign VAR52 = VAR13;
assign VAR71 = VAR98;
assign VAR51 = VAR75;
assign VAR103 = VAR124;
always @* begin
VAR94 = 1'b0;
VAR97 = VAR35 && !VAR126;
VAR65 = VAR122;
VAR67 = VAR107;
VAR34 = VAR120;
VAR47 = VAR16;
VAR68 = 1'b0;
VAR108 = VAR135;
VAR74 = 1'b0;
VAR11 = VAR62;
VAR30 = VAR56;
VAR128 = 1'b0;
VAR37 = VAR79;
VAR29 = VAR95;
VAR105 = VAR19;
VAR45 = VAR125;
VAR6 = VAR98 && !VAR109;
VAR78 = 1'b0;
VAR89 = 48'd0;
VAR94 = VAR126;
if (VAR116 && VAR94) begin
if (VAR2 == 16'h0806 && VAR59 == 16'h0001 && VAR5 == 16'h0800) begin
VAR74 = 1'b1;
VAR30 = VAR81;
VAR11 = VAR46;
if (VAR49 == VAR23) begin
if (VAR15 == VAR28) begin
VAR97 = 1'b1;
VAR65 = VAR80;
VAR67 = VAR115;
VAR34 = VAR46;
VAR47 = VAR81;
end
end else if (VAR49 == VAR139) begin
if (VAR8 == VAR18) begin
VAR97 = 1'b1;
VAR65 = VAR80;
VAR67 = VAR43;
VAR34 = VAR46;
VAR47 = VAR81;
end
end
end
end
if (VAR95) begin
VAR128 = 1'b0;
VAR68 = 1'b1;
VAR45 = VAR125 - 1;
if (VAR134 && !VAR138) begin
VAR29 = 1'b0;
VAR68 = 1'b0;
VAR6 = 1'b1;
VAR78 = 1'b0;
VAR89 = VAR83;
end
if (VAR125 == 0) begin
if (VAR19 > 0) begin
VAR97 = 1'b1;
VAR65 = 48'hffffffffffff;
VAR67 = VAR23;
VAR34 = 48'h000000000000;
VAR47 = VAR79;
VAR105 = VAR19 - 1;
if (VAR19 > 1) begin
VAR45 = VAR119;
end else begin
VAR45 = VAR101;
end
end else begin
VAR29 = 1'b0;
VAR6 = 1'b1;
VAR78 = 1'b1;
VAR68 = 1'b0;
end
end
end else begin
VAR128 = !VAR6;
if (VAR64) begin
VAR68 = 1'b1;
if (VAR134) begin
if (VAR138) begin
VAR29 = 1'b1;
VAR97 = 1'b1;
VAR65 = 48'hffffffffffff;
VAR67 = VAR23;
VAR34 = 48'h000000000000;
VAR47 = VAR79;
VAR105 = VAR31-1;
VAR45 = VAR119;
end else begin
VAR68 = 1'b0;
VAR6 = 1'b1;
VAR78 = 1'b0;
VAR89 = VAR83;
end
end
end else if (VAR12 && VAR52) begin
if (~(VAR130 | VAR10) == 0) begin
VAR6 = 1'b1;
VAR78 = 1'b0;
VAR89 = 48'hffffffffffff;
end else if (((VAR130 ^ VAR96) & VAR10) == 0) begin
VAR68 = 1'b1;
VAR108 = VAR130;
VAR37 = VAR130;
end else begin
VAR68 = 1'b1;
VAR108 = VAR96;
VAR37 = VAR96;
end
end
end
end
always @(posedge clk) begin
if (rst) begin
VAR35 <= 1'b0;
VAR64 <= 1'b0;
VAR87 <= 1'b0;
VAR13 <= 1'b0;
VAR95 <= 1'b0;
VAR19 <= 6'd0;
VAR125 <= 36'd0;
VAR98 <= 1'b0;
end else begin
VAR35 <= VAR97;
VAR64 <= VAR68;
VAR87 <= VAR74;
VAR13 <= VAR128;
VAR95 <= VAR29;
VAR19 <= VAR105;
VAR125 <= VAR45;
VAR98 <= VAR6;
end
VAR135 <= VAR108;
VAR122 <= VAR65;
VAR107 <= VAR67;
VAR120 <= VAR34;
VAR16 <= VAR47;
VAR62 <= VAR11;
VAR56 <= VAR30;
VAR79 <= VAR37;
VAR75 <= VAR78;
VAR124 <= VAR89;
end
endmodule | mit |
jotego/jt12 | hdl/jt03.v | 3,542 | module MODULE1(
input rst, input clk, input VAR36, input [7:0] din,
input addr,
input VAR37,
input VAR8,
output [7:0] dout,
output VAR7,
input [7:0] VAR9,
input [7:0] VAR1,
output [ 7:0] VAR10,
output [ 7:0] VAR13,
output [ 7:0] VAR5,
output signed [15:0] VAR19,
output [ 9:0] VAR4,
output signed [15:0] VAR32,
output VAR23,
output [ 7:0] VAR38
);
VAR25 #(
.VAR15(0),.VAR39(1), .VAR17(3), .VAR31(0), .VAR33(0), .VAR35(0) )
VAR16(
.rst ( rst ), .clk ( clk ), .VAR36 ( VAR36 ), .din ( din ),
.addr ( {1'b0, addr} ),
.VAR37 ( VAR37 ),
.VAR8 ( VAR8 ),
.dout ( dout ),
.VAR7 ( VAR7 ),
.VAR9 ( VAR9 ),
.VAR1 ( VAR1 ),
.VAR18 ( 1'b0 ), .VAR24 ( ), .VAR26 ( ),
.VAR27 ( ), .VAR3 ( 8'd0 ), .VAR6 ( 8'd0 ),
.VAR29 ( ), .VAR12 ( ), .VAR10 ( VAR10 ),
.VAR13 ( VAR13 ),
.VAR5 ( VAR5 ),
.VAR4 ( VAR4 ),
.VAR11 ( VAR19 ),
.VAR2 (),
.VAR34 (),
.VAR14 (),
.VAR20 (),
.VAR28 (),
.VAR22 ( VAR32 ),
.VAR30 (),
.VAR23 ( VAR23 ),
.VAR21 ( 8'd0 ),
.VAR38 ( VAR38 )
);
endmodule | gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemTextures/MemTextures_stub.v | 1,252 | module MODULE1(VAR2, clk, VAR1)
;
input [7:0]VAR2;
input clk;
output [91:0]VAR1;
endmodule | gpl-3.0 |
hakehuang/pycpld | ips/ip/spi_master/spi_ctrl.v | 1,515 | module MODULE1(
clk,VAR5,VAR18,VAR7,VAR2,VAR11,VAR19,VAR13,VAR3,VAR17,VAR16
);
input clk,VAR5,VAR2;
input VAR3;
input VAR17;
output VAR18,VAR7,VAR11;
output VAR16;
input VAR19;
input VAR13;
wire VAR12;
wire VAR16;
reg VAR4;
reg VAR11;
reg[7:0] VAR8;
reg[7:0] VAR9;
reg VAR15;
always @(posedge clk or negedge VAR5) begin
if(!VAR5) begin
VAR8 <= 8'h0;
VAR4 <= 1'b0;
end
else begin
if(VAR8 < 8'd100)
VAR8 <= VAR8 + 1'b1;
end
else begin
VAR8 <= 8'h0;
VAR4 <= ~VAR4;
end
end
end
always @(posedge clk or negedge VAR5) begin
if(!VAR5)
VAR11 <= 1'b1;
end
else begin
if(VAR12 || ((VAR19 == 1'b0) && (VAR13 == 1'b0)))
VAR11 <= 1'b1;
end
else
VAR11 <= 1'b0;
end
end
always @(posedge clk or negedge VAR5) begin
if(!VAR5)begin
VAR15 <= 1'b0;
VAR9 <= 'h0;
end
else begin
if(VAR9<8'd20)
VAR9 <= VAR9 + 1'b1;
end
else
VAR15 <= 1'b1;
end
end
VAR6 VAR1(
.clk(VAR4),
.VAR5(VAR15),
.VAR10(VAR2),
.VAR14(VAR7),
.VAR4(VAR18),
.VAR19(VAR19),
.VAR12(VAR12),
.VAR13(VAR13),
.VAR3(VAR3),
.VAR17(VAR17),
.VAR16(VAR16)
);
endmodule | mit |
Digilent/vivado-library | ip/Pmods/Pmod_Bridge_v1_1/src/pmod_concat.v | 7,190 | module MODULE1
(
VAR34,
VAR18,
VAR50,
VAR25,
VAR57,
VAR17,
VAR26,
VAR68,
VAR71,
VAR48,
VAR9,
VAR51,
VAR45,
VAR54,
VAR13,
VAR61,
VAR6,
VAR59,
VAR67,
VAR64,
VAR1,
VAR62,
VAR30,
VAR23,
VAR3,
VAR66,
VAR24,
VAR40,
VAR10,
VAR52,
VAR2,
VAR55,
VAR43,
VAR63,
VAR8,
VAR42,
VAR29,
VAR27,
VAR65,
VAR56,
VAR39,
VAR46,
VAR32,
VAR22,
VAR21,
VAR53,
VAR47,
VAR38,
VAR49,
VAR19,
VAR14,
VAR7,
VAR12,
VAR33,
VAR41,
VAR36,
VAR58,
VAR69,
VAR37,
VAR31,
VAR11,
VAR5,
VAR60,
VAR16,
VAR70,
VAR28);
parameter VAR72 = "VAR20";
parameter VAR35 = "VAR20";
output [3:0] VAR34;
input [3:0] VAR18;
input [3:0] VAR50;
output [1:0] VAR25;
input [1:0] VAR57;
input [1:0] VAR17;
output [1:0] VAR26;
input [1:0] VAR68;
input [1:0] VAR71;
output [3:0] VAR48;
input [3:0] VAR9;
input [3:0] VAR51;
output [1:0] VAR45;
input [1:0] VAR54;
input [1:0] VAR13;
output [1:0] VAR61;
input [1:0] VAR6;
input [1:0] VAR59;
output VAR67;
output VAR64;
output VAR1;
output VAR62;
output VAR30;
output VAR23;
output VAR3;
output VAR66;
input VAR24;
input VAR40;
input VAR10;
input VAR52;
input VAR2;
input VAR55;
input VAR43;
input VAR63;
input VAR8;
input VAR42;
input VAR29;
input VAR27;
input VAR65;
input VAR56;
input VAR39;
input VAR46;
input VAR32;
input VAR22;
input VAR21;
input VAR53;
input VAR47;
input VAR38;
input VAR49;
input VAR19;
output VAR14;
output VAR7;
output VAR12;
output VAR33;
output VAR41;
output VAR36;
output VAR58;
output VAR69;
output VAR37;
output VAR31;
output VAR11;
output VAR5;
output VAR60;
output VAR16;
output VAR70;
output VAR28;
generate
case (VAR72)
"VAR4": begin
assign VAR34={VAR53,VAR21,VAR22,VAR32};
assign {VAR33,VAR12,VAR7,VAR14}=VAR18;
assign {VAR5,VAR11,VAR31,VAR37}=VAR50;
end
"VAR44": begin
assign VAR25={VAR53,VAR32};
assign {VAR33,VAR14}=VAR57;
assign {VAR5,VAR37}=VAR17;
assign VAR1=VAR21;
assign VAR7 = VAR40;
assign VAR31 = 0;
assign VAR11 = 1;
end
"VAR15": begin
assign VAR26={VAR22,VAR32}; assign {VAR7,VAR14}=VAR68;
assign {VAR31,VAR37}=VAR71;
assign VAR12 = VAR10;
assign VAR33 = VAR52;
assign VAR11 = VAR29;
assign VAR5 = VAR27;
assign VAR1 = VAR21;
assign VAR62 = VAR53;
end
default: begin
assign VAR14 = VAR24;
assign VAR7 = VAR40;
assign VAR12 = VAR10;
assign VAR33 = VAR52;
assign VAR37 = VAR8;
assign VAR31 = VAR42;
assign VAR11 = VAR29;
assign VAR5 = VAR27;
assign VAR67 = VAR32;
assign VAR64 = VAR22;
assign VAR1 = VAR21;
assign VAR62 = VAR53;
end
endcase
endgenerate
generate
case (VAR35)
"VAR4":begin
assign VAR48={VAR19,VAR49,VAR38,VAR47};
assign {VAR69,VAR58,VAR36,VAR41}=VAR9;
assign {VAR28,VAR70,VAR16,VAR60}=VAR51;
end
"VAR44": begin
assign VAR45={VAR19,VAR47};
assign {VAR69,VAR41}=VAR54;
assign {VAR28,VAR60}=VAR13;
assign VAR36 = VAR55;
assign VAR58 = VAR43;
assign VAR16 = VAR56;
assign VAR70 = VAR39;
assign VAR23 = VAR38;
assign VAR3 = VAR49;
end
"VAR15": begin
assign VAR61={VAR38,VAR47};
assign {VAR36,VAR41}=VAR6;
assign {VAR16,VAR60}=VAR59;
assign VAR58 = VAR43;
assign VAR69 = VAR43;
assign VAR70 = VAR39;
assign VAR28 = VAR46;
assign VAR3 = VAR49;
assign VAR66 = VAR19;
end
default: begin
assign VAR41 = VAR2;
assign VAR36 = VAR55;
assign VAR58 = VAR43;
assign VAR69 = VAR63;
assign VAR60 = VAR65;
assign VAR16 = VAR56;
assign VAR70 = VAR39;
assign VAR28 = VAR46;
assign VAR30 = VAR47;
assign VAR23 = VAR38;
assign VAR3 = VAR49;
assign VAR66 = VAR19;
end
endcase
endgenerate
endmodule | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab3/array_io_prj/solution3/syn/verilog/array_io.v | 47,456 | module MODULE1 (
VAR236,
VAR13,
VAR61,
VAR54,
VAR64,
VAR171,
VAR233,
VAR162,
VAR111,
VAR222,
VAR113,
VAR9,
VAR79,
VAR51,
VAR144,
VAR133,
VAR183,
VAR52,
VAR204,
VAR169,
VAR174,
VAR119,
VAR116,
VAR63,
VAR197,
VAR188,
VAR24,
VAR47,
VAR143,
VAR91
);
parameter VAR115 = 12'd1;
parameter VAR165 = 12'd2;
parameter VAR201 = 12'd4;
parameter VAR215 = 12'd8;
parameter VAR234 = 12'd16;
parameter VAR164 = 12'd32;
parameter VAR86 = 12'd64;
parameter VAR90 = 12'd128;
parameter VAR187 = 12'd256;
parameter VAR156 = 12'd512;
parameter VAR205 = 12'd1024;
parameter VAR19 = 12'd2048;
input VAR236;
input VAR13;
input VAR61;
output VAR54;
output VAR64;
output VAR171;
output [15:0] VAR233;
input VAR162;
output VAR111;
output [15:0] VAR222;
input VAR113;
output VAR9;
output [15:0] VAR79;
input VAR51;
output VAR144;
output [15:0] VAR133;
input VAR183;
output VAR52;
output [3:0] VAR204;
output VAR169;
input [15:0] VAR174;
output [3:0] VAR119;
output VAR116;
input [15:0] VAR63;
output [3:0] VAR197;
output VAR188;
input [15:0] VAR24;
output [3:0] VAR47;
output VAR143;
input [15:0] VAR91;
reg VAR54;
reg VAR64;
reg VAR171;
reg[15:0] VAR233;
reg VAR111;
reg[15:0] VAR222;
reg VAR9;
reg[15:0] VAR79;
reg VAR144;
reg[15:0] VAR133;
reg VAR52;
reg[3:0] VAR204;
reg VAR169;
reg[3:0] VAR119;
reg VAR116;
reg[3:0] VAR197;
reg VAR188;
reg[3:0] VAR47;
reg VAR143;
reg [11:0] VAR56;
wire VAR7;
reg [31:0] VAR68;
reg [31:0] VAR231;
reg [31:0] VAR38;
reg [31:0] VAR152;
reg [31:0] VAR29;
reg [31:0] VAR209;
reg [31:0] VAR158;
reg [31:0] VAR74;
reg VAR105;
wire VAR83;
wire VAR235;
wire VAR11;
wire VAR172;
wire VAR81;
wire VAR230;
wire VAR4;
wire VAR214;
reg VAR71;
reg VAR20;
reg VAR28;
reg [15:0] VAR176;
wire VAR220;
wire VAR112;
reg VAR118;
reg VAR42;
reg VAR142;
reg [15:0] VAR1;
reg [15:0] VAR161;
reg VAR77;
reg VAR59;
reg VAR57;
reg [15:0] VAR189;
wire VAR73;
reg [15:0] VAR30;
reg [15:0] VAR190;
reg [15:0] VAR50;
reg [15:0] VAR147;
wire [15:0] VAR76;
reg [15:0] VAR163;
wire [16:0] VAR228;
reg [16:0] VAR92;
wire [15:0] VAR157;
reg [15:0] VAR200;
wire [15:0] VAR43;
reg [15:0] VAR148;
wire [15:0] VAR104;
reg [15:0] VAR97;
wire [16:0] VAR12;
reg [16:0] VAR110;
wire [15:0] VAR229;
reg [15:0] VAR89;
wire [15:0] VAR184;
reg [15:0] VAR109;
wire [15:0] VAR32;
reg [15:0] VAR225;
wire [16:0] VAR87;
reg [16:0] VAR138;
wire [15:0] VAR129;
reg [15:0] VAR180;
wire [15:0] VAR219;
reg [15:0] VAR103;
wire [15:0] VAR167;
reg [15:0] VAR137;
wire [16:0] VAR85;
reg [16:0] VAR15;
wire [15:0] VAR134;
reg [15:0] VAR139;
wire [15:0] VAR198;
reg [15:0] VAR186;
wire [15:0] VAR107;
reg [15:0] VAR70;
wire [16:0] VAR46;
reg [16:0] VAR14;
wire [15:0] VAR39;
reg [15:0] VAR78;
wire [15:0] VAR232;
reg [15:0] VAR216;
wire [15:0] VAR62;
reg [15:0] VAR98;
wire [16:0] VAR202;
reg [16:0] VAR168;
wire [15:0] VAR211;
reg [15:0] VAR96;
wire [15:0] VAR3;
reg [15:0] VAR40;
wire [15:0] VAR123;
reg [15:0] VAR166;
wire [16:0] VAR48;
reg [16:0] VAR75;
wire [15:0] VAR101;
reg [15:0] VAR208;
wire [15:0] VAR35;
reg [15:0] VAR206;
wire [15:0] VAR226;
reg [15:0] VAR66;
wire [16:0] VAR80;
reg [16:0] VAR151;
wire [15:0] VAR31;
reg [15:0] VAR99;
reg VAR69;
wire [15:0] VAR221;
reg [15:0] VAR126;
reg VAR122;
wire [15:0] VAR179;
wire [15:0] VAR141;
wire [15:0] VAR100;
wire [15:0] VAR132;
wire [15:0] VAR194;
wire [15:0] VAR218;
wire [15:0] VAR178;
wire [15:0] VAR155;
wire [31:0] VAR149;
wire [31:0] VAR128;
wire [31:0] VAR17;
wire [31:0] VAR173;
wire [31:0] VAR82;
wire [31:0] VAR25;
wire [31:0] VAR124;
wire [31:0] VAR181;
wire [15:0] VAR170;
wire signed [16:0] VAR150;
wire signed [16:0] VAR175;
wire [15:0] VAR93;
wire signed [31:0] VAR65;
wire signed [17:0] VAR18;
wire signed [17:0] VAR36;
wire [17:0] VAR146;
wire signed [31:0] VAR207;
wire [31:0] VAR117;
wire signed [16:0] VAR153;
wire signed [16:0] VAR16;
wire [15:0] VAR2;
wire signed [31:0] VAR102;
wire signed [17:0] VAR195;
wire signed [17:0] VAR192;
wire [17:0] VAR95;
wire signed [31:0] VAR213;
wire [31:0] VAR45;
wire signed [16:0] VAR94;
wire signed [16:0] VAR227;
wire [15:0] VAR237;
wire signed [31:0] VAR121;
wire signed [17:0] VAR41;
wire signed [17:0] VAR6;
wire [17:0] VAR114;
wire signed [31:0] VAR8;
wire [31:0] VAR140;
wire signed [16:0] VAR193;
wire signed [16:0] VAR130;
wire [15:0] VAR53;
wire signed [31:0] VAR58;
wire signed [17:0] VAR212;
wire signed [17:0] VAR185;
wire [17:0] VAR21;
wire signed [31:0] VAR191;
wire [31:0] VAR72;
wire signed [16:0] VAR182;
wire signed [16:0] VAR136;
wire [15:0] VAR88;
wire signed [31:0] VAR34;
wire signed [17:0] VAR217;
wire signed [17:0] VAR84;
wire [17:0] VAR44;
wire signed [31:0] VAR5;
wire [31:0] VAR60;
wire signed [16:0] VAR49;
wire signed [16:0] VAR199;
wire [15:0] VAR120;
wire signed [31:0] VAR210;
wire signed [17:0] VAR203;
wire signed [17:0] VAR177;
wire [17:0] VAR23;
wire signed [31:0] VAR223;
wire [31:0] VAR154;
wire signed [16:0] VAR159;
wire signed [16:0] VAR106;
wire [15:0] VAR145;
wire signed [31:0] VAR127;
wire signed [17:0] VAR131;
wire signed [17:0] VAR125;
wire [17:0] VAR135;
wire signed [31:0] VAR160;
wire [31:0] VAR22;
wire signed [16:0] VAR37;
wire signed [16:0] VAR27;
wire signed [31:0] VAR55;
wire signed [17:0] VAR67;
wire signed [17:0] VAR26;
wire [17:0] VAR196;
wire signed [31:0] VAR10;
wire [31:0] VAR224;
reg [11:0] VAR33;
reg VAR108; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi_1.v | 2,450 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR12 ,
VAR6 ,
VAR5 ,
VAR10 ,
VAR11,
VAR4,
VAR1 ,
VAR2
);
output VAR8 ;
input VAR3 ;
input VAR12 ;
input VAR6 ;
input VAR5 ;
input VAR10 ;
input VAR11;
input VAR4;
input VAR1 ;
input VAR2 ;
VAR7 VAR9 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR8 ,
VAR3,
VAR12,
VAR6,
VAR5,
VAR10
);
output VAR8 ;
input VAR3;
input VAR12;
input VAR6;
input VAR5;
input VAR10;
supply1 VAR11;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR2 ;
VAR7 VAR9 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10)
);
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/RAM16_s36_s36_altera.v | 11,211 | module MODULE1 (
VAR62,
VAR33,
VAR41,
VAR37,
VAR46,
VAR13,
VAR24,
VAR51,
VAR28,
VAR27,
VAR5,
VAR60);
input VAR62;
input VAR33;
input [8:0] VAR41;
input [8:0] VAR37;
input VAR46;
input VAR13;
input [31:0] VAR24;
input [31:0] VAR51;
input VAR28;
input VAR27;
output [31:0] VAR5;
output [31:0] VAR60;
tri0 VAR62;
tri0 VAR33;
tri1 VAR28;
tri1 VAR27;
wire [31:0] VAR61;
wire [31:0] VAR48;
wire [31:0] VAR5 = VAR61[31:0];
wire [31:0] VAR60 = VAR48[31:0];
VAR2 VAR38 (
.VAR28 (VAR28),
.VAR10 (VAR62),
.VAR39 (VAR46),
.VAR27 (VAR27),
.VAR34 (VAR33),
.VAR12 (VAR13),
.VAR41 (VAR41),
.VAR37 (VAR37),
.VAR24 (VAR24),
.VAR51 (VAR51),
.VAR5 (VAR61),
.VAR60 (VAR48),
.VAR1 (1'b0),
.VAR63 (1'b0),
.VAR52 (1'b1),
.VAR56 (1'b1),
.VAR54 (1'b1),
.VAR16 (1'b1),
.VAR9 (1'b1),
.VAR53 (1'b1),
.VAR18 (),
.VAR26 (1'b1),
.VAR23 (1'b1));
VAR38.VAR3 = "VAR42",
VAR38.VAR30 = "VAR45",
VAR38.VAR15 = "VAR45",
VAR38.VAR29 = "VAR45",
VAR38.VAR49 = "VAR45",
VAR38.VAR31 = "VAR42",
VAR38.VAR40 = "VAR7 VAR14",
VAR38.VAR25 = "VAR2",
VAR38.VAR19 = 512,
VAR38.VAR6 = 512,
VAR38.VAR58 = "VAR55",
VAR38.VAR59 = "VAR57",
VAR38.VAR21 = "VAR17",
VAR38.VAR20 = "VAR36",
VAR38.VAR22 = "VAR42",
VAR38.VAR8 = "VAR35",
VAR38.VAR44 = 9,
VAR38.VAR47 = 9,
VAR38.VAR43 = 32,
VAR38.VAR4 = 32,
VAR38.VAR32 = 1,
VAR38.VAR11 = 1,
VAR38.VAR50 = "VAR42";
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o.symbol.v | 1,375 | module MODULE1 (
input VAR6,
input VAR4,
input VAR9,
input VAR1,
output VAR2
);
supply1 VAR7;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
oblivioncth/DE0-Verilog-Processor | src/reg_8x16bit.v | 4,771 | module MODULE1(
VAR43,
VAR22,
reset,
VAR4,
VAR32,
VAR30,
VAR13,
VAR55,
VAR72,
VAR29,
VAR1,
VAR71,
VAR40,
VAR12,
VAR26,
VAR31,
VAR7
);
input wire VAR43;
input wire VAR22;
input wire reset;
input wire [2:0] VAR4;
input wire [2:0] VAR32;
input wire [15:0] VAR30;
input wire [2:0] VAR13;
output wire [15:0] VAR55;
output wire [15:0] VAR72;
output wire [15:0] VAR29;
output wire [15:0] VAR1;
output wire [15:0] VAR71;
output wire [15:0] VAR40;
output wire [15:0] VAR12;
output wire [15:0] VAR26;
output wire [15:0] VAR31;
output wire [15:0] VAR7;
wire VAR57;
wire VAR50;
wire VAR9;
wire VAR23;
wire VAR53;
wire VAR19;
wire VAR3;
wire [15:0] VAR28;
wire [15:0] VAR68;
wire [15:0] VAR11;
wire [15:0] VAR54;
wire [15:0] VAR41;
wire [15:0] VAR18;
wire [15:0] VAR36;
wire [15:0] VAR49;
wire VAR45;
wire VAR46;
wire VAR63;
wire VAR8;
wire VAR64;
wire VAR37;
wire VAR47;
wire VAR20;
wire VAR59;
assign VAR29 = VAR28;
assign VAR1 = VAR68;
assign VAR71 = VAR11;
assign VAR40 = VAR54;
assign VAR12 = VAR41;
assign VAR26 = VAR18;
assign VAR31 = VAR36;
assign VAR7 = VAR49;
VAR51 VAR16(
.clk(VAR43),
.VAR10(VAR57),
.VAR60(reset),
.VAR30(VAR30),
.VAR44(VAR28));
assign VAR46 = VAR22 & VAR50;
VAR51 VAR67(
.clk(VAR43),
.VAR10(VAR9),
.VAR60(reset),
.VAR30(VAR30),
.VAR44(VAR54));
VAR51 VAR62(
.clk(VAR43),
.VAR10(VAR23),
.VAR60(reset),
.VAR30(VAR30),
.VAR44(VAR41));
VAR51 VAR14(
.clk(VAR43),
.VAR10(VAR53),
.VAR60(reset),
.VAR30(VAR30),
.VAR44(VAR18));
VAR51 VAR39(
.clk(VAR43),
.VAR10(VAR19),
.VAR60(reset),
.VAR30(VAR30),
.VAR44(VAR36));
VAR51 VAR21(
.clk(VAR43),
.VAR10(VAR3),
.VAR60(reset),
.VAR30(VAR30),
.VAR44(VAR49));
VAR42 VAR70(
.VAR38(VAR28),
.VAR6(VAR68),
.VAR35(VAR11),
.VAR17(VAR54),
.VAR65(VAR41),
.VAR24(VAR18),
.VAR73(VAR36),
.VAR33(VAR49),
.VAR2(VAR4),
.VAR44(VAR55));
VAR69 VAR66(
.VAR2(VAR13),
.VAR52(VAR45),
.VAR56(VAR50),
.VAR48(VAR63),
.VAR74(VAR8),
.VAR58(VAR64),
.VAR34(VAR37),
.VAR61(VAR20),
.VAR25(VAR59));
assign VAR57 = VAR22 & VAR45;
VAR42 VAR27(
.VAR38(VAR28),
.VAR6(VAR68),
.VAR35(VAR11),
.VAR17(VAR54),
.VAR65(VAR41),
.VAR24(VAR18),
.VAR73(VAR36),
.VAR33(VAR49),
.VAR2(VAR32),
.VAR44(VAR72));
VAR51 VAR15(
.clk(VAR43),
.VAR10(VAR46),
.VAR60(reset),
.VAR30(VAR30),
.VAR44(VAR68));
assign VAR47 = VAR22 & VAR63;
assign VAR9 = VAR22 & VAR8;
assign VAR23 = VAR22 & VAR64;
assign VAR53 = VAR22 & VAR37;
VAR51 VAR5(
.clk(VAR43),
.VAR10(VAR47),
.VAR60(reset),
.VAR30(VAR30),
.VAR44(VAR11));
assign VAR19 = VAR22 & VAR20;
assign VAR3 = VAR22 & VAR59;
endmodule | mit |
csail-csg/recycle-bsv-lib | src/v/EHRU_2.v | 2,003 | module MODULE1 (
VAR11,
VAR10,
VAR6,
VAR12,
VAR9,
VAR4,
VAR3
);
parameter VAR8 = 1;
parameter VAR1 = 0;
input VAR11;
output [VAR8-1:0] VAR10;
input [VAR8-1:0] VAR6;
input VAR12;
output [VAR8-1:0] VAR9;
input [VAR8-1:0] VAR4;
input VAR3;
reg [VAR8-1:0] VAR7;
wire [VAR8-1:0] VAR13;
wire [VAR8-1:0] VAR5;
wire [VAR8-1:0] VAR2;
assign VAR13 = VAR7;
assign VAR5 = VAR12 ? VAR6 : VAR13;
assign VAR2 = VAR3 ? VAR4 : VAR5;
assign VAR10 = VAR13;
assign VAR9 = VAR5;
always @(posedge VAR11) begin
VAR7 <= VAR2;
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_pg/sky130_fd_sc_hs__udp_dff_pr_pp_pg.symbol.v | 1,430 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR6,
input VAR2 ,
input VAR4 ,
input VAR1
);
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/standard_cc_module.v | 9,894 | module MODULE1
(
VAR10,
VAR18,
VAR5,
VAR9,
VAR8
);
output VAR10;
output VAR18;
input VAR5;
input VAR9;
input VAR8;
reg VAR10;
reg VAR18;
reg [0:7] VAR2;
reg [0:5] VAR15;
reg VAR11;
reg [0:11] VAR7;
reg VAR1;
reg [0:14] VAR3;
reg VAR17;
reg [0:10] VAR16;
reg VAR19;
wire VAR14;
wire VAR4;
wire VAR6;
wire VAR13;
always @(posedge VAR9)
VAR7 <= VAR12 {VAR1, VAR7[0:10]};
assign VAR4 = VAR7[11];
always @(posedge VAR9)
if(~VAR8)
VAR1 <= VAR12 1'b0;
else if(VAR8 && VAR11)
VAR1 <= VAR12 1'b1;
else
VAR1 <= VAR12 VAR4;
always @(posedge VAR9)
if(VAR4|| !VAR8)
VAR3 <= VAR12 {VAR17, VAR3[0:13]};
assign VAR6 = VAR4 && VAR3[14];
always @(posedge VAR9)
if(~VAR8)
VAR17 <= VAR12 1'b0;
else if(VAR8 && VAR11)
VAR17 <= VAR12 1'b1;
else if(VAR4)
VAR17 <= VAR12 VAR6;
always @(posedge VAR9)
if(VAR6 || !VAR8)
VAR16 <= VAR12 {VAR19, VAR16[0:9]};
assign VAR13 = VAR6 & VAR16[10];
always @(posedge VAR9)
if(~VAR8)
VAR19 <= VAR12 1'b0;
else if(VAR8 && VAR11)
VAR19 <= VAR12 1'b1;
else if(VAR6)
VAR19 <= VAR12 VAR13; | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill_2.v | 1,840 | module MODULE1 (
VAR6,
VAR5,
VAR4 ,
VAR2
);
input VAR6;
input VAR5;
input VAR4 ;
input VAR2 ;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 ();
supply1 VAR6;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR2 ;
VAR1 VAR3 ();
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9361/axi_ad9361_dev_if_alt.v | 9,684 | module MODULE1 (
VAR24,
VAR50,
VAR21,
VAR51,
VAR52,
VAR64,
VAR33,
VAR62,
VAR59,
VAR19,
VAR56,
VAR15,
rst,
clk,
VAR35,
VAR5,
VAR45,
VAR7,
VAR41,
VAR9,
VAR17,
VAR53,
VAR42,
VAR65,
VAR13,
VAR67,
VAR61,
VAR39,
VAR3,
VAR55,
VAR54,
VAR12,
VAR18);
parameter VAR37 = 0;
parameter VAR40 = 0;
parameter VAR27 = "VAR30";
localparam VAR11 = 0;
localparam VAR32 = 1;
input VAR24;
input VAR50;
input VAR21;
input VAR51;
input [ 5:0] VAR52;
input [ 5:0] VAR64;
output VAR33;
output VAR62;
output VAR59;
output VAR19;
output [ 5:0] VAR56;
output [ 5:0] VAR15;
input rst;
input clk;
output VAR35;
output VAR5;
output [47:0] VAR45;
output VAR7;
input VAR41;
input VAR9;
input VAR17;
input [47:0] VAR53;
input VAR42;
input VAR65;
input [ 6:0] VAR13;
input [34:0] VAR67;
output [34:0] VAR61;
input [ 7:0] VAR39;
input [39:0] VAR3;
output [39:0] VAR55;
input VAR54;
input VAR12;
output VAR18;
reg [ 3:0] VAR20 = 'd0;
reg [ 5:0] VAR36 = 'd0;
reg [ 5:0] VAR22 = 'd0;
reg [ 5:0] VAR25 = 'd0;
reg [ 5:0] VAR6 = 'd0;
reg VAR31 = 'd0;
reg VAR2 = 'd0;
reg [23:0] VAR49 = 'd0;
reg VAR5 = 'd0;
reg [47:0] VAR45 = 'd0;
reg VAR7 = 'd0;
reg VAR47 = 'd0;
reg [47:0] VAR63 = 'd0;
reg [ 3:0] VAR66 = 'd0;
reg [ 5:0] VAR28 = 'd0;
reg [ 5:0] VAR38 = 'd0;
reg [ 5:0] VAR4 = 'd0;
reg [ 5:0] VAR14 = 'd0;
wire [ 3:0] VAR1;
wire VAR58;
wire [ 3:0] VAR16;
wire [ 5:0] VAR57;
wire [ 5:0] VAR8;
wire [ 5:0] VAR26;
wire [ 5:0] VAR44;
wire VAR48;
assign VAR18 = 1'd1;
assign VAR1 = ~VAR20;
always @(posedge VAR35) begin
VAR20 <= VAR16;
VAR36 <= VAR44;
VAR22 <= VAR26;
VAR25 <= VAR8;
VAR6 <= VAR57;
if (VAR1 == VAR16) begin
VAR31 <= 1'b0;
end else begin
VAR31 <= 1'b1;
end
case (VAR20)
4'b1111: begin
VAR2 <= 1'b1;
VAR49[23:12] <= {VAR25, VAR36};
VAR49[11: 0] <= {VAR6, VAR22};
end
4'b1110: begin
VAR2 <= 1'b1;
VAR49[23:12] <= {VAR22, VAR57};
VAR49[11: 0] <= {VAR25, VAR36};
end
4'b1100: begin
VAR2 <= 1'b1;
VAR49[23:12] <= {VAR36, VAR8};
VAR49[11: 0] <= {VAR22, VAR57};
end
4'b1000: begin
VAR2 <= 1'b1;
VAR49[23:12] <= {VAR57, VAR26};
VAR49[11: 0] <= {VAR36, VAR8};
end
4'b0000: begin
VAR2 <= 1'b0;
VAR49[23:12] <= {VAR25, VAR36};
VAR49[11: 0] <= {VAR6, VAR22};
end
4'b0001: begin
VAR2 <= 1'b0;
VAR49[23:12] <= {VAR22, VAR57};
VAR49[11: 0] <= {VAR25, VAR36};
end
4'b0011: begin
VAR2 <= 1'b0;
VAR49[23:12] <= {VAR36, VAR8};
VAR49[11: 0] <= {VAR22, VAR57};
end
4'b0111: begin
VAR2 <= 1'b0;
VAR49[23:12] <= {VAR57, VAR26};
VAR49[11: 0] <= {VAR36, VAR8};
end
default: begin
VAR2 <= 1'b0;
VAR49[23:12] <= 12'd0;
VAR49[11: 0] <= 12'd0;
end
endcase
if (VAR2 == 1'b1) begin
VAR5 <= 1'b0;
VAR45 <= {24'd0, VAR49};
end else begin
VAR5 <= 1'b1;
VAR45 <= {VAR49, VAR45[23:0]};
end
VAR7 <= ~VAR31 & VAR48 & VAR58;
end
always @(posedge VAR35) begin
VAR47 <= VAR17;
VAR63 <= VAR53;
if (VAR47 == 1'b1) begin
VAR66 <= 4'b1111;
VAR28 <= VAR63[11: 6];
VAR38 <= VAR63[23:18];
VAR4 <= VAR63[ 5: 0];
VAR14 <= VAR63[17:12];
end else begin
VAR66 <= 4'b0000;
VAR28 <= VAR63[35:30];
VAR38 <= VAR63[47:42];
VAR4 <= VAR63[29:24];
VAR14 <= VAR63[41:36];
end
end
VAR34 VAR23 (
.VAR33 (VAR33),
.VAR62 (VAR62),
.VAR59 (VAR59),
.VAR19 (VAR19),
.VAR56 (VAR56),
.VAR15 (VAR15),
.VAR46 (VAR24),
.clk (VAR35),
.VAR66 (VAR66),
.VAR28 (VAR28),
.VAR38 (VAR38),
.VAR4 (VAR4),
.VAR14 (VAR14),
.VAR10 (VAR58));
VAR43 VAR29 (
.VAR24 (VAR24),
.VAR50 (VAR50),
.VAR21 (VAR21),
.VAR51 (VAR51),
.VAR52 (VAR52),
.VAR64 (VAR64),
.clk (VAR35),
.VAR20 (VAR16),
.VAR6 (VAR57),
.VAR25 (VAR8),
.VAR22 (VAR26),
.VAR36 (VAR44),
.VAR60 (VAR48));
endmodule | gpl-3.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CORESPI/4.2.116/rtl/vlog/core/spi.v | 15,748 | module MODULE1( VAR13, VAR22, VAR36, VAR69, VAR76, VAR52, VAR80, VAR108, VAR84, VAR31,
VAR53, VAR38, VAR62, VAR29, VAR109, VAR94, VAR87, VAR104, VAR56 );
parameter VAR51 = 8;
parameter VAR2 = 4;
parameter VAR4 = 4;
parameter VAR30 = 7;
parameter VAR49 = 0;
parameter VAR54 = 0;
parameter VAR27 = 0;
parameter VAR105 = 0;
input VAR13;
input VAR22;
input [6:0] VAR36;
input VAR69;
input VAR76;
input VAR52;
input [VAR51-1:0] VAR80;
input VAR108;
input VAR84;
input VAR31;
output [VAR51-1:0] VAR53;
output VAR38;
output [7:0] VAR62;
output VAR29;
output VAR109;
output VAR94;
output VAR87;
output VAR56;
output VAR104;
wire [VAR51-1:0] VAR95;
wire [7:0] VAR73;
wire VAR9;
wire VAR19;
wire [2:0] VAR113;
wire [VAR2-1:0] VAR117;
wire [VAR2-1:0] VAR85;
wire [VAR2-1:0] VAR65;
wire [VAR2-1:0] VAR75;
wire VAR115;
wire VAR102;
wire VAR88;
wire [5:0] VAR57;
wire [5:0] VAR44;
wire [6:0] VAR39 = { VAR36[6:2], 2'b00 };
assign VAR53 = ~(VAR39[6:0]==7'h08) ? VAR95 : VAR75;
assign VAR56 = VAR9;
assign VAR109 = ~VAR115;
assign VAR94 = ~VAR102;
reg [7:0] VAR114;
assign VAR62 = VAR114;
integer VAR50;
always @(*)
begin
if (VAR19 && VAR9)
begin
for (VAR50=0; VAR50<8; VAR50=VAR50+1)
begin
if (VAR73[VAR50])
VAR114[VAR50] = VAR88;
end
else
VAR114[VAR50] = (VAR105 != 1); end
end
else
begin
for (VAR50 =0; VAR50<8; VAR50=VAR50+1)
VAR114[VAR50] = (VAR105 != 1); end
end
wire VAR55 = ( VAR9 ? VAR88 : VAR108 );
VAR99 # (
.VAR51(VAR51)
)
VAR103 ( .VAR8 (VAR13),
.VAR91 (VAR22),
.VAR107 (VAR39[6:0]),
.VAR120 (VAR69),
.VAR110 (VAR76),
.VAR98 (VAR52),
.VAR14 (VAR80),
.VAR86 (VAR95),
.interrupt (VAR38),
.VAR111 (VAR111),
.VAR93 (VAR93),
.VAR15 (VAR15),
.VAR79 (VAR79),
.VAR63 (VAR63),
.VAR72 (VAR72),
.VAR82 (VAR82),
.VAR37 (VAR37),
.VAR101 (VAR101),
.VAR115 (VAR115),
.VAR112 (VAR112),
.VAR102 (VAR102),
.VAR46 (VAR46),
.VAR12 (VAR12),
.VAR3 (VAR3),
.VAR83 (VAR1),
.VAR78 (VAR55),
.VAR26 (VAR26),
.VAR23 (VAR23),
.VAR118 (VAR118),
.VAR19 (VAR19),
.VAR9 (VAR9),
.VAR73 (VAR73),
.VAR113 (VAR113),
.VAR10 (VAR68),
.VAR25 (VAR33),
.VAR5 (VAR5),
.VAR6 (VAR6)
);
VAR16 # (
.VAR2 (VAR2)
) VAR89 ( .VAR8 (VAR13),
.VAR91 (VAR22),
.VAR120 (VAR69),
.VAR110 (VAR76),
.VAR98 (VAR52),
.VAR107 (VAR39[6:0]),
.VAR28 (VAR80[VAR2-1:0]), .VAR9 (VAR9),
.VAR7 (VAR117),
.VAR72 (VAR72),
.VAR116 (VAR41),
.VAR12 (VAR12),
.VAR63 (VAR63),
.VAR115 (VAR115)
);
VAR43 # (
.VAR2 (VAR2),
.VAR4 (VAR4)
) VAR47 ( .VAR8 (VAR13),
.VAR91 (VAR22),
.VAR70 (VAR68),
.VAR119 (VAR117),
.VAR106 (VAR41),
.VAR58 (VAR85),
.VAR24 (VAR45),
.VAR92 (VAR82),
.VAR61 (VAR72),
.VAR35 (VAR102),
.VAR48 (VAR12),
.VAR21 (VAR46),
.VAR32 (VAR3),
.VAR74 (VAR121),
.VAR81 (VAR44)
);
VAR43 # (
.VAR2(VAR2),
.VAR4(VAR4)
) VAR96 ( .VAR8 (VAR13),
.VAR91 (VAR22),
.VAR70 (VAR33),
.VAR119 (VAR65),
.VAR61 (VAR64),
.VAR106 (VAR90),
.VAR58 (VAR75),
.VAR92 (VAR63),
.VAR24 (VAR1),
.VAR35 (VAR37),
.VAR48 (VAR115),
.VAR32 (VAR112),
.VAR21 (VAR101),
.VAR74 (VAR93),
.VAR81 (VAR57)
);
VAR67 # (
.VAR54 (VAR54),
.VAR49 (VAR49),
.VAR27 (VAR27),
.VAR105 (VAR105),
.VAR18 (VAR30),
.VAR2 (VAR2)
)VAR17 ( .VAR8 (VAR13),
.VAR91 (VAR22),
.VAR97 (VAR31),
.VAR40 (VAR29),
.VAR100 (VAR108),
.VAR60 (VAR88),
.VAR11 (VAR84),
.VAR20 (VAR104),
.VAR71 (VAR87),
.VAR44 (VAR44),
.VAR12 (VAR12),
.VAR82 (VAR82),
.VAR7 (VAR85),
.VAR116 (VAR45),
.VAR57 (VAR57),
.VAR64 (VAR64),
.VAR34 (VAR65),
.VAR42 (VAR90),
.VAR19 (VAR19),
.VAR9 (VAR9),
.VAR5 (VAR5),
.VAR113 (VAR113),
.VAR6 (VAR6),
.VAR66 (VAR15),
.VAR77 (VAR79),
.VAR26 (VAR26),
.VAR23 (VAR23),
.VAR59 (VAR111),
.VAR118 (VAR118)
);
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.functional.pp.v | 1,520 | module MODULE1( VAR5, VAR7, VAR1, VAR10, VAR6, VAR19, VAR13 );
input VAR10, VAR6, VAR7, VAR5;
inout VAR19, VAR13;
output VAR1;
wire VAR15;
not VAR17( VAR15, VAR10 );
wire VAR11;
not VAR4( VAR11, VAR6 );
wire VAR16;
and VAR3( VAR16, VAR15, VAR11 );
wire VAR9;
not VAR20( VAR9, VAR7 );
wire VAR2;
not VAR8( VAR2, VAR5 );
wire VAR14;
and VAR18( VAR14, VAR9, VAR2 );
or VAR12( VAR1, VAR16, VAR14 );
endmodule | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/EXMEM_Stage.v | 6,014 | module MODULE1(
input VAR28,
input reset,
input VAR36,
input VAR48,
input VAR40,
input VAR67,
input VAR10,
input VAR38,
input VAR16, input VAR3, input VAR64,
input VAR41,
input VAR31,
input VAR44,
input VAR2,
input VAR50,
input VAR52,
input VAR51,
input VAR56,
input VAR9,
input [31:0] VAR61,
input VAR68,
input VAR43,
input VAR46,
input VAR30,
input [31:0] VAR22,
input [31:0] VAR25,
input [4:0] VAR59,
input VAR53,
input VAR32,
input VAR37,
input VAR15,
input VAR24,
input VAR55,
input VAR42,
input VAR35,
input VAR26,
input VAR20,
input VAR23,
input VAR18,
input [31:0] VAR47,
input VAR17,
input VAR8,
input VAR13,
input VAR54,
input [31:0] VAR65,
input [31:0] VAR45,
input [4:0] VAR29,
output reg VAR58,
output reg VAR11,
output reg VAR62,
output reg VAR66,
output reg VAR21,
output reg VAR7,
output reg VAR49,
output reg VAR1,
output reg VAR57,
output reg VAR6,
output reg VAR63,
output reg VAR14,
output reg [31:0] VAR5,
output reg VAR4,
output reg VAR33,
output reg VAR27,
output reg VAR60,
output reg [31:0] VAR39,
output reg [31:0] VAR34,
output reg [4:0] VAR12
);
wire VAR19 = (VAR67 & ~VAR38) | (VAR10 & VAR38);
always @(posedge VAR28) begin
VAR58 <= (reset) ? 1'b0 : ((VAR40) ? VAR53 : ((VAR48 | VAR36) ? 1'b0 : ((VAR67 | VAR10) ? VAR19 : VAR16)));
VAR11 <= (reset) ? 1'b0 : ((VAR40) ? VAR32 : VAR3);
VAR62 <= (reset) ? 1'b0 : ((VAR40) ? VAR37 : VAR64);
VAR66 <= (reset) ? 1'b0 : ((VAR40) ? VAR15 : VAR41);
VAR21 <= (reset) ? 1'b0 : ((VAR40) ? VAR24 : ((VAR48 | VAR36) ? 1'b0 : VAR31));
VAR7 <= (reset) ? 1'b0 : ((VAR40) ? VAR55 : ((VAR48 | VAR36) ? 1'b0 : VAR44));
VAR49 <= (reset) ? 1'b0 : ((VAR40) ? VAR42 : VAR2);
VAR1 <= (reset) ? 1'b0 : ((VAR40) ? VAR35 : VAR50);
VAR57 <= (reset) ? 1'b0 : ((VAR40) ? VAR26 : VAR52);
VAR6 <= (reset) ? 1'b0 : ((VAR40) ? VAR20 : VAR51);
VAR63 <= (reset) ? 1'b0 : ((VAR40) ? VAR23 : VAR56);
VAR14 <= (reset) ? 1'b0 : ((VAR40) ? VAR18 : VAR9);
VAR5 <= (reset) ? 32'b0 : ((VAR40) ? VAR47 : VAR61);
VAR4 <= (reset) ? 1'b0 : ((VAR40) ? VAR17 : VAR68);
VAR33 <= (reset) ? 1'b0 : ((VAR40) ? VAR8 : ((VAR48 | VAR36) ? 1'b0 : VAR43));
VAR27 <= (reset) ? 1'b0 : ((VAR40) ? VAR13 : VAR46);
VAR60 <= (reset) ? 1'b0 : ((VAR40) ? VAR54 : ((VAR48 | VAR36) ? 1'b0 : VAR30));
VAR39 <= (reset) ? 32'b0 : ((VAR40) ? VAR65 : VAR22);
VAR34 <= (reset) ? 32'b0 : ((VAR40) ? VAR45 : VAR25);
VAR12 <= (reset) ? 5'b0 : ((VAR40) ? VAR29 : VAR59);
end
endmodule | lgpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/uart16550/uart_wb.v | 11,593 | module MODULE1 (clk, VAR5,
VAR15, VAR22, VAR3, VAR26, VAR16,
VAR17, VAR21, VAR14, VAR2, VAR13, VAR4, VAR8,
VAR1, VAR9 );
input clk;
input VAR5;
input VAR15;
input VAR22;
input VAR3;
input [3:0] VAR8;
input [VAR6-1:0] VAR16;
input [7:0] VAR21; output [7:0] VAR14;
reg [7:0] VAR14;
wire [7:0] VAR21;
reg [7:0] VAR12;
reg [31:0] VAR14;
wire [31:0] VAR21;
reg [31:0] VAR12;
output [VAR6-1:0] VAR17; input [7:0] VAR13; output [7:0] VAR2;
input [31:0] VAR4; output VAR26;
output VAR1;
output VAR9;
wire VAR1;
reg VAR26;
reg [7:0] VAR2;
wire [7:0] VAR13;
wire [VAR6-1:0] VAR17; reg [VAR6-1:0] VAR23;
reg VAR25;
reg VAR11;
reg VAR24;
reg [3:0] VAR20;
wire [3:0] VAR8;
reg VAR7 ;
reg [1:0] VAR18;
always @(posedge clk or posedge VAR5)
if (VAR5) begin
VAR26 <= 1'b0;
VAR18 <= 0;
VAR7 <= 1'b1;
end else
case (VAR18)
0: begin
if (VAR24 & VAR11) begin
VAR7 <= 0;
VAR18 <= 1;
VAR26 <= 1;
end else begin
VAR7 <= 1;
VAR26 <= 0;
end
end
1: begin
VAR26 <= 0;
VAR18 <= 2;
VAR7 <= 0;
end
2,3: begin
VAR26 <= 0;
VAR18 <= 0;
VAR7 <= 0;
end
endcase
assign VAR1 = VAR25 & VAR24 & VAR11 & VAR7 ; assign VAR9 = ~VAR25 & VAR24 & VAR11 & VAR7 ;
always @(posedge clk or posedge VAR5)
if (VAR5) begin
VAR23 <= 0;
VAR25 <= 0;
VAR11 <= 0;
VAR24 <= 0;
VAR12 <= 0;
VAR20 <= 0;
end else begin
VAR23 <= VAR16;
VAR25 <= VAR15;
VAR11 <= VAR3;
VAR24 <= VAR22;
VAR12 <= VAR21;
VAR20 <= VAR8;
end
if (VAR5)
VAR14 <= 0;
end
else
VAR14 <= VAR13;
always @(VAR12)
VAR2 = VAR12;
assign VAR17 = VAR23;
if (VAR5)
VAR14 <= 0;
end
else if (VAR9)
case (VAR20)
4'b0001: VAR14 <= {24'b0, VAR13};
4'b0010: VAR14 <= {16'b0, VAR13, 8'b0};
4'b0100: VAR14 <= {8'b0, VAR13, 16'b0};
4'b1000: VAR14 <= {VAR13, 24'b0};
4'b1111: VAR14 <= VAR4; default: VAR14 <= 0;
endcase
reg [1:0] VAR19;
always @(VAR20 or VAR12)
begin
case (VAR20)
4'b0001 : VAR2 = VAR12[7:0];
4'b0010 : VAR2 = VAR12[15:8];
4'b0100 : VAR2 = VAR12[23:16];
4'b1000 : VAR2 = VAR12[31:24];
default : VAR2 = VAR12[7:0];
endcase
case (VAR20)
4'b0001 : VAR19 = 2'h0;
4'b0010 : VAR19 = 2'h1;
4'b0100 : VAR19 = 2'h2;
4'b1000 : VAR19 = 2'h3;
default : VAR19 = 2'h0;
end
endcase else
case (VAR20)
4'b0001 : VAR19 = 2'h3;
4'b0010 : VAR19 = 2'h2;
4'b0100 : VAR19 = 2'h1;
4'b1000 : VAR19 = 2'h0;
default : VAR19 = 2'h0;
endcase VAR10
end
assign VAR17 = {VAR23[VAR6-1:2], VAR19};
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.functional.v | 1,344 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
wire VAR1;
not VAR4 (VAR1, VAR5 );
buf VAR2 (VAR3 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a.behavioral.v | 1,930 | module MODULE1 (
VAR15 ,
VAR2 ,
VAR5 ,
VAR6 ,
VAR9 ,
VAR14,
VAR3
);
output VAR15 ;
input VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR9 ;
input VAR14;
input VAR3;
wire VAR9 VAR7 ;
wire VAR4 ;
wire VAR1;
or VAR13 (VAR7 , VAR5, VAR2 );
and VAR11 (VAR4 , VAR7, VAR6, VAR9 );
VAR12 VAR10 (VAR1, VAR4, VAR14, VAR3);
buf VAR8 (VAR15 , VAR1 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_async/bsg_async_fifo.v | 4,442 | module MODULE1 #(parameter VAR44( VAR25 )
, parameter VAR44( VAR11 )
, parameter VAR45 = 0)
(
input VAR42
, input VAR3
, input VAR41
, input [VAR11-1:0] VAR17
, output VAR38
, input VAR20
, input VAR23
, input VAR43
, output [VAR11-1:0] VAR29
, output VAR37
);
localparam VAR22 = 1 << VAR25;
logic [VAR25:0] VAR10;
logic [VAR25:0] VAR7;
logic [VAR25:0] VAR18, VAR1, VAR40, VAR2;
wire VAR28; assign VAR37 = VAR28;
VAR39 #(.VAR11(VAR11-VAR45)
,.VAR21(VAR22)
,.VAR5(0)
) VAR33
(.VAR42 (VAR42 )
,.VAR3 (VAR3)
,.VAR34 (VAR41 )
,.VAR32(VAR2[0+:VAR25] )
,.VAR17(VAR17[0+:(VAR11 - VAR45)] )
,.VAR24 (VAR28 )
,.VAR26(VAR40[0+:VAR25] )
,.VAR29(VAR29[0+:(VAR11 - VAR45)] )
);
if (VAR45 > 0)
begin : VAR16
VAR39 #(.VAR11(VAR45)
,.VAR21(VAR22)
,.VAR5(0)
) VAR33
(.VAR42 (VAR42 )
,.VAR3(VAR3)
,.VAR34 (VAR41 )
,.VAR32 (VAR2[0+:VAR25] )
,.VAR17 (VAR17[(VAR11-1)-:VAR45])
,.VAR24 (VAR28 )
,.VAR26 (VAR40[0+:VAR25] )
,.VAR29 (VAR29[(VAR11-1)-:VAR45])
);
end
VAR6 #(.VAR25(VAR25+1)) VAR13
(.VAR42(VAR42)
,.VAR3(VAR3)
,.VAR30(VAR41)
,.VAR20(VAR20)
,.VAR14(VAR2)
,.VAR36(VAR7)
,.VAR31(VAR18)
);
VAR6 #(.VAR25(VAR25+1)) VAR4
(.VAR42(VAR20)
,.VAR3(VAR23)
,.VAR30(VAR43)
,.VAR20(VAR42)
,.VAR14(VAR40)
,.VAR36(VAR10) ,.VAR31(VAR1) );
assign VAR28 = (VAR10 != VAR18);
assign VAR38 = (VAR7 == { ~VAR1[VAR25-:2]
, VAR1[0+:VAR25-1] });
always @(negedge VAR42)
assert(!(VAR38===1 && VAR41===1)) else ("VAR9 VAR12 VAR15 MODULE1 MODULE1 VAR19");
always @(negedge VAR20)
assert(!(VAR28===0 && VAR43===1)) else ("VAR35 VAR12 VAR15 MODULE1 MODULE1 VAR8");
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3.behavioral.v | 1,396 | module MODULE1 (
VAR8,
VAR3,
VAR1,
VAR11
);
output VAR8;
input VAR3;
input VAR1;
input VAR11;
supply1 VAR2;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR5 ;
wire VAR9;
xnor VAR4 (VAR9, VAR3, VAR1, VAR11 );
buf VAR10 (VAR8 , VAR9 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_j_pack_out_gen.v | 8,543 | module MODULE1 (
VAR47, VAR43,
VAR24, VAR15,
VAR34, VAR39, VAR37, VAR68, VAR67,
VAR29, VAR23, VAR54,
clk, VAR36, VAR14, VAR17, VAR5
);
input VAR34;
input VAR39;
input VAR37;
input VAR68;
input VAR67;
input VAR29; input [3:0] VAR23; input VAR54;
output [2:0] VAR47;
output VAR43;
output [2:0] VAR24;
output VAR15;
input clk;
input VAR36;
input VAR14;
input VAR17;
input VAR5;
wire VAR51, VAR53;
wire [1:0] state;
reg VAR16;
reg [1:0] VAR6;
reg [2:0] VAR62;
VAR27 VAR28 (.din(VAR5), .VAR41(VAR58), .clk(VAR14));
parameter VAR50 = 2'h0,
VAR19 = 2'h1,
VAR66 = 2'h2,
VAR25 = 2'h3,
VAR65 = 2'VAR1;
parameter VAR32 = 3'VAR31;
VAR13 #(2) VAR21 (.din(VAR6), .VAR41(state), .VAR36(VAR36), .clk(clk));
always @(VAR16 or VAR51
or VAR62 or VAR6 or VAR39 or VAR37
or VAR53 or VAR68 or VAR67
or state) begin
casex ({ state, VAR53, VAR39, VAR68, VAR37, VAR67, VAR51 })
{ VAR50, VAR9, VAR9, VAR9, VAR9, VAR9, VAR9 }: out = { VAR50, VAR9, VAR33 };
{ VAR50, VAR4, VAR8, VAR8, VAR8, VAR8, VAR8 }: out = { VAR19, VAR9, VAR56 };
{ VAR50, VAR9, VAR4, VAR8, VAR8, VAR8, VAR8 }: out = { VAR50, VAR9, VAR10 };
{ VAR50, VAR9, VAR9, VAR4, VAR8, VAR8, VAR8 }: out = { VAR50, VAR9, VAR48 };
{ VAR50, VAR9, VAR9, VAR9, VAR4, VAR8, VAR8 }: out = { VAR50, VAR9, VAR52 };
{ VAR50, VAR9, VAR9, VAR9, VAR9, VAR4, VAR8 }: out = { VAR50, VAR9, VAR56 };
{ VAR50, VAR9, VAR9, VAR9, VAR9, VAR9, VAR4 }: out = { VAR50, VAR4, VAR61 };
{ VAR19, VAR8, VAR8, VAR8, VAR8, VAR8, VAR8 }: out = { VAR66, VAR9, VAR56 };
{ VAR66, VAR8, VAR8, VAR8, VAR8, VAR8, VAR8 }: out = { VAR25, VAR9, VAR56 };
{ VAR25, VAR8, VAR8, VAR8, VAR8, VAR8, VAR8 }: out = { VAR50, VAR9, VAR56 };
default: out = { VAR65, VAR8, VAR32 };
endcase
end
assign VAR47 = VAR62;
assign VAR43 = 1'b1;
assign VAR24 = VAR62;
assign VAR15 = 1'b1;
VAR57 VAR20 (
.VAR2 (VAR34),
.valid (VAR51),
.VAR49 (VAR16),
.clk (clk),
.VAR36 (VAR36)
);
wire VAR42 = (|VAR23[3:0]);
VAR27 VAR26 (.din(VAR42), .VAR41(VAR12), .clk(VAR14));
wire VAR22 = VAR12;
wire VAR44 = VAR58; VAR55 VAR59 (.VAR45(VAR22), .VAR18(VAR44), .VAR36(VAR17), .clk(VAR14), .VAR41(VAR60));
wire VAR11 = VAR60;
wire VAR30 = VAR58;
VAR35 VAR46 (.din(VAR11), .en(VAR30), .VAR41(VAR38), .clk(VAR14));
wire VAR40 = VAR38;
VAR27 VAR63 (.din(VAR40), .VAR41(VAR64), .clk(clk));
assign VAR53 = VAR29 || (VAR64 && VAR54);
reg VAR3;
reg VAR7; | gpl-2.0 |
theapi/de0-nano | memory/memory_init.v | 1,442 | module MODULE1(
input clk,
input reset,
output [7:0] out
);
reg [12:0] address;
reg VAR6, VAR15, VAR3;
wire [15:0] VAR14, VAR4, VAR9;
reg [15:0] VAR18;
reg [7:0] VAR13;
always @(posedge clk or posedge reset) begin
if (reset) begin
address <= 0;
VAR18 <= 16'b1111111111111111;
end else begin
address <= address + 13'd1;
VAR18 <= 16'b1111111111111111;
end
end
always @* begin
VAR6 = 0; VAR15 = 0; VAR3 = 0; VAR13 = 0;
if (address < 13'd2048) begin
VAR6 = 1;
VAR13 = VAR14[7:0];
end else if (address < (13'd2048 + 13'd1024)) begin
VAR15 = 1;
VAR13 = VAR4[7:0];
end else if (address < (13'd2048 + 13'd1024 + 13'd512)) begin
VAR3 = 1;
VAR13 <= VAR9[7:0];
end
end
VAR10 VAR5 (.VAR11(VAR14), .VAR18(VAR18), .VAR7(address), .VAR2(address - 1), .VAR12(VAR6), .clk(clk));
VAR16 VAR17 (.VAR11(VAR4), .VAR18(VAR18), .VAR7(address), .VAR2(address - 1), .VAR12(VAR15), .clk(clk));
VAR8 VAR1 (.VAR11(VAR9), .VAR18(VAR18), .VAR7(address), .VAR2(address - 1), .VAR12(VAR3), .clk(clk));
assign out = VAR13;
endmodule | mit |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/ppu/ppu_vga.v | 9,365 | module MODULE1
(
input VAR9, input VAR19,
output VAR18, output VAR28, output [2:0] VAR1, output [2:0] VAR3, output [1:0] VAR10,
input [5:0] VAR33,
output [9:0] VAR27, output [9:0] VAR36, output [9:0] VAR32, output VAR8, output VAR26 );
localparam [9:0] VAR16 = 10'h280,
VAR14 = 10'h1E0;
localparam [9:0] VAR34 = 10'h100,
VAR25 = 10'h0F0;
localparam [7:0] VAR20 = 8'h49;
wire VAR6; wire [9:0] VAR24; wire [9:0] VAR30; wire [9:0] VAR4; wire [9:0] VAR37;
VAR7 VAR2(
.clk (VAR9 ),
.rst (VAR19 ),
.VAR23 (VAR18 ),
.VAR17 (VAR28 ),
.en (VAR6 ),
.VAR29 (VAR24 ),
.VAR15 (VAR30 ),
.VAR31 (VAR4 ),
.VAR12 (VAR37 )
);
reg [7:0] VAR35; reg [7:0] VAR22;
reg VAR11; wire VAR21;
always @(posedge VAR9) begin
if (VAR19)
begin
VAR35 <= 8'h00;
VAR11 <= 1'h0;
end
else
begin
VAR35 <= VAR22;
VAR11 <= VAR21;
end
end
wire [9:0] VAR13; wire VAR5;
assign VAR27 = (VAR24 - 10'h040) >> 1;
assign VAR36 = VAR30 >> 1;
assign VAR13 = (VAR4 - 10'h040) >> 1;
assign VAR32 = VAR37 >> 1;
assign VAR5 = (VAR27 >= VAR34) || (VAR36 < 8) || (VAR36 >= (VAR25 - 8));
always @*
begin
if (!VAR6)
begin
VAR22 = 8'h00;
end
else if (VAR5)
begin
VAR22 = VAR20;
end
else
begin
case (VAR33)
6'h00: VAR22 = { 3'h3, 3'h3, 2'h1 };
6'h01: VAR22 = { 3'h1, 3'h0, 2'h2 };
6'h02: VAR22 = { 3'h0, 3'h0, 2'h2 };
6'h03: VAR22 = { 3'h2, 3'h0, 2'h2 };
6'h04: VAR22 = { 3'h4, 3'h0, 2'h1 };
6'h05: VAR22 = { 3'h5, 3'h0, 2'h0 };
6'h06: VAR22 = { 3'h5, 3'h0, 2'h0 };
6'h07: VAR22 = { 3'h3, 3'h0, 2'h0 };
6'h08: VAR22 = { 3'h2, 3'h1, 2'h0 };
6'h09: VAR22 = { 3'h0, 3'h2, 2'h0 };
6'h0a: VAR22 = { 3'h0, 3'h2, 2'h0 };
6'h0b: VAR22 = { 3'h0, 3'h1, 2'h0 };
6'h0c: VAR22 = { 3'h0, 3'h1, 2'h1 };
6'h0d: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h0e: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h0f: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h10: VAR22 = { 3'h5, 3'h5, 2'h2 };
6'h11: VAR22 = { 3'h0, 3'h3, 2'h3 };
6'h12: VAR22 = { 3'h1, 3'h1, 2'h3 };
6'h13: VAR22 = { 3'h4, 3'h0, 2'h3 };
6'h14: VAR22 = { 3'h5, 3'h0, 2'h2 };
6'h15: VAR22 = { 3'h7, 3'h0, 2'h1 };
6'h16: VAR22 = { 3'h6, 3'h1, 2'h0 };
6'h17: VAR22 = { 3'h6, 3'h2, 2'h0 };
6'h18: VAR22 = { 3'h4, 3'h3, 2'h0 };
6'h19: VAR22 = { 3'h0, 3'h4, 2'h0 };
6'h1a: VAR22 = { 3'h0, 3'h5, 2'h0 };
6'h1b: VAR22 = { 3'h0, 3'h4, 2'h0 };
6'h1c: VAR22 = { 3'h0, 3'h4, 2'h2 };
6'h1d: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h1e: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h1f: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h20: VAR22 = { 3'h7, 3'h7, 2'h3 };
6'h21: VAR22 = { 3'h1, 3'h5, 2'h3 };
6'h22: VAR22 = { 3'h2, 3'h4, 2'h3 };
6'h23: VAR22 = { 3'h5, 3'h4, 2'h3 };
6'h24: VAR22 = { 3'h7, 3'h3, 2'h3 };
6'h25: VAR22 = { 3'h7, 3'h3, 2'h2 };
6'h26: VAR22 = { 3'h7, 3'h3, 2'h1 };
6'h27: VAR22 = { 3'h7, 3'h4, 2'h0 };
6'h28: VAR22 = { 3'h7, 3'h5, 2'h0 };
6'h29: VAR22 = { 3'h4, 3'h6, 2'h0 };
6'h2a: VAR22 = { 3'h2, 3'h6, 2'h1 };
6'h2b: VAR22 = { 3'h2, 3'h7, 2'h2 };
6'h2c: VAR22 = { 3'h0, 3'h7, 2'h3 };
6'h2d: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h2e: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h2f: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h30: VAR22 = { 3'h7, 3'h7, 2'h3 };
6'h31: VAR22 = { 3'h5, 3'h7, 2'h3 };
6'h32: VAR22 = { 3'h6, 3'h6, 2'h3 };
6'h33: VAR22 = { 3'h6, 3'h6, 2'h3 };
6'h34: VAR22 = { 3'h7, 3'h6, 2'h3 };
6'h35: VAR22 = { 3'h7, 3'h6, 2'h3 };
6'h36: VAR22 = { 3'h7, 3'h5, 2'h2 };
6'h37: VAR22 = { 3'h7, 3'h6, 2'h2 };
6'h38: VAR22 = { 3'h7, 3'h7, 2'h2 };
6'h39: VAR22 = { 3'h7, 3'h7, 2'h2 };
6'h3a: VAR22 = { 3'h5, 3'h7, 2'h2 };
6'h3b: VAR22 = { 3'h5, 3'h7, 2'h3 };
6'h3c: VAR22 = { 3'h4, 3'h7, 2'h3 };
6'h3d: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h3e: VAR22 = { 3'h0, 3'h0, 2'h0 };
6'h3f: VAR22 = { 3'h0, 3'h0, 2'h0 };
endcase
end
end
assign { VAR1, VAR3, VAR10 } = VAR35;
assign VAR8 = VAR13 != VAR27;
assign VAR21 = ((VAR24 == 730) && (VAR30 == 477)) ? 1'b1 :
((VAR24 == 64) && (VAR30 == 519)) ? 1'b0 : VAR11;
assign VAR26 = VAR11;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b.functional.pp.v | 1,998 | module MODULE1 (
VAR1 ,
VAR16 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR6,
VAR14,
VAR5 ,
VAR8
);
output VAR1 ;
input VAR16 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR6;
input VAR14;
input VAR5 ;
input VAR8 ;
wire VAR2 ;
wire VAR11 ;
wire VAR13;
not VAR10 (VAR2 , VAR16 );
nand VAR9 (VAR11 , VAR4, VAR3, VAR7, VAR2 );
VAR12 VAR15 (VAR13, VAR11, VAR6, VAR14);
buf VAR17 (VAR1 , VAR13 );
endmodule | apache-2.0 |
jakubfi/mera400f | src/platform.v | 1,398 | module MODULE1(
input VAR16,
output VAR33,
input VAR22,
output VAR4,
output [7:0] VAR21,
output [7:0] VAR15,
output VAR24, VAR11, VAR17, VAR26, VAR29,
output [17:0] VAR30,
inout [15:0] VAR1,
output VAR28, VAR14, VAR25
);
localparam VAR23 = 50000000;
wire VAR8, VAR35, VAR18;
wire [0:15] VAR10;
wire [10:0] VAR32;
wire [0:9] VAR27;
VAR5 #(
.VAR23(VAR23)
) VAR7 (
.VAR36(VAR16),
.VAR3(VAR22),
.VAR2(VAR4),
.VAR20(VAR8),
.VAR13(VAR35),
.VAR38(VAR18),
.VAR31(VAR30),
.VAR6(VAR1),
.VAR10(VAR10),
.VAR32(VAR32),
.VAR27(VAR27)
);
assign VAR33 = 1'b1;
assign VAR28 = 1'b1;
assign VAR14 = 1'b1;
assign VAR25 = 1'b1;
assign VAR29 = 1'b0;
assign VAR26 = 1'b0;
assign VAR24 = ~VAR8;
assign VAR11 = ~VAR35;
assign VAR17 = ~VAR18;
VAR12 VAR34(
.VAR37(VAR16),
.VAR10(VAR10),
.VAR32(VAR32),
.VAR27(VAR27),
.VAR9(VAR15),
.VAR19(VAR21)
);
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai_1.v | 2,352 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR4 ,
VAR2 ,
VAR3 ,
VAR5,
VAR11,
VAR7 ,
VAR1
);
output VAR9 ;
input VAR10 ;
input VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR5;
input VAR11;
input VAR7 ;
input VAR1 ;
VAR8 VAR6 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR9 ,
VAR10,
VAR4,
VAR2,
VAR3
);
output VAR9 ;
input VAR10;
input VAR4;
input VAR2;
input VAR3;
supply1 VAR5;
supply0 VAR11;
supply1 VAR7 ;
supply0 VAR1 ;
VAR8 VAR6 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/jasons_v/QM_FIR.v | 6,536 | module MODULE1(
VAR11, VAR27, VAR12, VAR2, VAR16, VAR13,
VAR20,
VAR25, VAR18, VAR29, VAR8, VAR31, VAR1, VAR14, VAR32,
VAR23
);
parameter VAR9 = 16;
parameter VAR28 = 8;
parameter VAR39 = 32;
output signed [(VAR9-1):0] VAR11, VAR27, VAR12;
output signed [(VAR9-1):0] VAR2, VAR16, VAR13;
output VAR20;
input VAR25;
input VAR18;
input VAR29;
input signed [(VAR28-1):0] VAR8;
input signed [(VAR28-1):0] VAR31;
input signed [(VAR28-1):0] VAR1;
input signed [(VAR28-1):0] VAR14;
input [6:0] VAR32;
input VAR23;
wire VAR15;
wire signed [(VAR9-1):0] VAR38, VAR22, VAR19;
wire signed [(VAR9-1):0] VAR17, VAR24, VAR36;
wire [6:0] VAR4;
wire [6:0] VAR5;
wire [6:0] VAR3;
assign VAR5[6:0] = (VAR32[6:0] * 2 > 119 ) ?
VAR32[6:0] * 2 - 120 :
VAR32[6:0] * 2 ;
assign VAR4[6:0] = VAR5[6:0] - 5 ;
assign VAR3[6:0] = VAR5[6:0] + 5 ;
VAR40 VAR40
( .clk(VAR25),
.rst(VAR18),
.VAR32(VAR32),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR23(VAR23),
.VAR29(VAR29),
.VAR8(VAR8),
.VAR31(VAR31),
.VAR1(VAR1),
.VAR14(VAR14),
.VAR38(VAR38),
.VAR22(VAR22),
.VAR19(VAR19),
.VAR17(VAR17),
.VAR24(VAR24),
.VAR36(VAR36),
.VAR30(VAR15)
);
VAR37 VAR10
( .VAR25 (VAR25),
.VAR18 (VAR18),
.VAR29 (VAR15),
.VAR21 (VAR38),
.VAR35 (VAR11),
.VAR20 (VAR20)
);
VAR37 VAR7
( .VAR25 (VAR25),
.VAR18 (VAR18),
.VAR29 (VAR15),
.VAR21 (VAR17),
.VAR35 (VAR2)
);
VAR37 VAR6
( .VAR25 (VAR25),
.VAR18 (VAR18),
.VAR29 (VAR15),
.VAR21 (VAR22),
.VAR35 (VAR27)
);
VAR37 VAR34
( .VAR25 (VAR25),
.VAR18 (VAR18),
.VAR29 (VAR15),
.VAR21 (VAR24),
.VAR35 (VAR16)
);
VAR37 VAR26
( .VAR25 (VAR25),
.VAR18 (VAR18),
.VAR29 (VAR15),
.VAR21 (VAR19),
.VAR35 (VAR12)
);
VAR37 VAR33
( .VAR25 (VAR25),
.VAR18 (VAR18),
.VAR29 (VAR15),
.VAR21 (VAR36),
.VAR35 (VAR13)
);
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15.pp.symbol.v | 1,322 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR6 ,
input VAR2,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4/sky130_fd_sc_hs__nor4.functional.v | 1,759 | module MODULE1 (
VAR6,
VAR11,
VAR1 ,
VAR13 ,
VAR10 ,
VAR8 ,
VAR7
);
input VAR6;
input VAR11;
output VAR1 ;
input VAR13 ;
input VAR10 ;
input VAR8 ;
input VAR7 ;
wire VAR9 ;
wire VAR5;
nor VAR4 (VAR9 , VAR13, VAR10, VAR8, VAR7 );
VAR12 VAR3 (VAR5, VAR9, VAR6, VAR11);
buf VAR2 (VAR1 , VAR5 );
endmodule | apache-2.0 |
argonnexraydetector/RoachFirmPy | ANLYellowBlocks/mkid_dacadc_4x/ise/mkiddac/mkid_dac_4x.v | 26,818 | module MODULE1(
input VAR124, input VAR139,
output VAR102, output VAR150,
output VAR155,
output VAR142,
output VAR103,
output VAR84,
output VAR37,
output VAR169,
output [15:0] VAR44, output [15:0] VAR77,
output [15:0] VAR157,
output [15:0] VAR83,
output VAR19,
output VAR162,
output VAR152,
output VAR45,
output VAR50,
input VAR3,
output VAR95, output VAR2, output VAR34, output VAR105, output VAR63,
input [15:0] VAR14, input [15:0] VAR120,
input [15:0] VAR49,
input [15:0] VAR66,
input [15:0] VAR111,
input [15:0] VAR161,
input [15:0] VAR53,
input [15:0] VAR104,
input VAR138, input VAR55,
input VAR100, input VAR122,
input VAR182,
input VAR125,
input VAR175 );
parameter VAR118 =0;
wire VAR95;
wire VAR2;
wire VAR34;
wire VAR105;
wire VAR52[15:0];
wire VAR46[15:0];
VAR168 #(
.VAR13("VAR89"))
VAR113 (
.VAR163(VAR19),
.VAR183(VAR100)
);
VAR168 #(.VAR13("VAR89")) VAR27 (
.VAR163(VAR162),
.VAR183(VAR122)
);
VAR168 #(.VAR13("VAR89")) VAR22 (
.VAR163(VAR152),
.VAR183(VAR182)
);
VAR168 #(.VAR13("VAR89")) VAR101 (
.VAR163(VAR45),
.VAR183(VAR125)
);
VAR168 #(.VAR13("VAR89")) VAR137 (
.VAR163(VAR50),
.VAR183(VAR175)
);
VAR64 #(.VAR13("VAR23"))
VAR160
(
.VAR163(VAR103),
.VAR6(VAR84),
.VAR183(VAR138)
);
VAR64 #(.VAR13("VAR23"))
VAR65
(
.VAR163(VAR37),
.VAR6(VAR169),
.VAR183(VAR55)
);
genvar VAR31;
generate
for (VAR31 =0; VAR31<16; VAR31 = VAR31 + 1)
begin: VAR12
VAR178 #(
.VAR181("VAR135"),
.VAR133("VAR62"),
.VAR30(4),
.VAR79(1),
.VAR40(1'b0),
.VAR108(1'b0),
.VAR117("VAR89"), .VAR148(0),
.VAR99("VAR156"),
.VAR170(1'b0),
.VAR147(1'b0),
.VAR132(1)
)
VAR70 (
.VAR115(), .VAR59(VAR52[VAR31]), .VAR48(), .VAR4(), .VAR109(), .VAR112(), .VAR94(clk), .VAR54(VAR51), .VAR18(1'b1), .VAR129(1'b0), .VAR98(1'b1), .VAR32(VAR14[VAR31]),
.VAR171(VAR120[VAR31]),
.VAR127(VAR49[VAR31]),
.VAR158(VAR66[VAR31]),
.VAR17(1'b0),
.VAR43(1'b0),
.VAR71(1'b0), .VAR57(1'b0), .VAR33(1'b0),
.VAR78(1'b1),
.VAR114(1'b1),
.VAR165(1'b1)
);
VAR64 #(.VAR13("VAR23"))
VAR21 (
.VAR163(VAR44[VAR31]),
.VAR6(VAR77[VAR31]),
.VAR183(VAR52[VAR31])
);
end
endgenerate
generate
for (VAR31 =0; VAR31<16; VAR31 = VAR31 + 1)
begin: VAR107
VAR178 #(
.VAR181("VAR135"),
.VAR133("VAR62"),
.VAR30(4),
.VAR79(1),
.VAR40(1'b0),
.VAR108(1'b0),
.VAR117("VAR89"), .VAR148(0),
.VAR99("VAR156"),
.VAR170(1'b0),
.VAR147(1'b0),
.VAR132(1)
)
VAR96 (
.VAR115(), .VAR59(VAR46[VAR31]), .VAR48(), .VAR4(), .VAR109(), .VAR112(), .VAR94(clk), .VAR54(VAR51), .VAR18(1'b1), .VAR129(1'b0), .VAR98(1'b1), .VAR32(VAR111[VAR31]), .VAR171(VAR161[VAR31]),
.VAR127(VAR53[VAR31]),
.VAR158(VAR104[VAR31]),
.VAR17(1'b0),
.VAR43(1'b0),
.VAR71(1'b0), .VAR57(1'b0), .VAR33(1'b0),
.VAR78(1'b1),
.VAR114(1'b1),
.VAR165(1'b1)
);
VAR64 #(.VAR13("VAR23"))
VAR134 (
.VAR163(VAR157[VAR31]),
.VAR6(VAR83[VAR31]),
.VAR183(VAR52[VAR31])
);
end
endgenerate
VAR178 #(
.VAR181("VAR135"),
.VAR133("VAR62"),
.VAR30(4),
.VAR79(1),
.VAR40(1'b0),
.VAR108(1'b0),
.VAR117("VAR89"), .VAR148(0),
.VAR99("VAR156"),
.VAR170(1'b0),
.VAR147(1'b0),
.VAR132(1)
)
VAR141 (
.VAR115(), .VAR59(VAR36), .VAR48(), .VAR4(), .VAR109(), .VAR112(), .VAR94(clk), .VAR54(VAR51), .VAR18(1'b1), .VAR129(1'b0), .VAR98(1'b1), .VAR32(1'b0), .VAR171(1'b1),
.VAR127(1'b0),
.VAR158(1'b1),
.VAR17(1'b0),
.VAR43(1'b0),
.VAR71(1'b0), .VAR57(1'b0), .VAR33(1'b0),
.VAR78(1'b1),
.VAR114(1'b1),
.VAR165(1'b1)
);
VAR178 #(
.VAR181("VAR135"),
.VAR133("VAR62"),
.VAR30(4),
.VAR79(1),
.VAR40(1'b0),
.VAR108(1'b0),
.VAR117("VAR89"), .VAR148(0),
.VAR99("VAR156"),
.VAR170(1'b0),
.VAR147(1'b0),
.VAR132(1)
)
VAR5 (
.VAR115(), .VAR59(VAR176), .VAR48(), .VAR4(), .VAR109(), .VAR112(), .VAR94(clk), .VAR54(VAR51), .VAR18(1'b1), .VAR129(1'b0), .VAR98(1'b1), .VAR32(1'b0),
.VAR171(1'b1),
.VAR127(1'b0),
.VAR158(1'b1),
.VAR17(1'b0),
.VAR43(1'b0),
.VAR71(1'b0), .VAR57(1'b0), .VAR33(1'b0),
.VAR78(1'b1),
.VAR114(1'b1),
.VAR165(1'b1)
);
VAR64 #(.VAR13("VAR23"))
VAR130 (
.VAR163(VAR102),
.VAR6(VAR150),
.VAR183(VAR36)
);
VAR64 #(.VAR13("VAR23"))
VAR123 (
.VAR163(VAR155),
.VAR6(VAR142),
.VAR183(VAR176)
);
generate
if(VAR118==1)
begin
VAR153 #(
.VAR13("VAR23")
)
VAR7 (
.VAR163(VAR173), .VAR183(VAR124), .VAR81(VAR139) );
VAR61 VAR110 (
.VAR163(VAR28), .VAR183(VAR173) );
VAR61 VAR29 (
.VAR163(VAR51), .VAR183(VAR24) );
VAR61 VAR42 (
.VAR163(clk), .VAR183(VAR69) );
VAR61 VAR39 (
.VAR163(VAR76), .VAR183(VAR38) );
VAR61 VAR167 (
.VAR163(VAR72), .VAR183(VAR159) );
VAR61 VAR8 (
.VAR163(VAR116), .VAR183(VAR87) );
assign VAR95 = VAR51; assign VAR2 = VAR76; assign VAR34 = VAR72; assign VAR105 = VAR116;
VAR126 #(
.VAR20("VAR121"), .VAR143(4.0), .VAR67(0.0), .VAR106(3.906), .VAR180(8.0), .VAR154(0.5),
.VAR68(0.5),
.VAR60(0.5),
.VAR145(0.5),
.VAR16(0.5),
.VAR80(0.5),
.VAR136(0.5),
.VAR119(0.0),
.VAR86(90.0),
.VAR58(180.0),
.VAR144(270.0),
.VAR41(0.0),
.VAR151(0.0),
.VAR11(0.0),
.VAR179(8), .VAR140(8),
.VAR73(8),
.VAR166(4), .VAR93(1),
.VAR15(1),
.VAR92("VAR174"), .VAR88("VAR174"), .VAR146(1), .VAR26(0.0), .VAR177("VAR174") )
VAR128 (
.VAR85(VAR24), .VAR74(), .VAR10(VAR38), .VAR25(), .VAR9(VAR159), .VAR82(), .VAR172(VAR87), .VAR1(), .VAR91(VAR69), .VAR97(), .VAR131(), .VAR90(), .VAR47(), .VAR75(VAR63), .VAR56(VAR28), .VAR35(1'b0), .VAR129(1'b0), .VAR164(VAR51) );
end
endgenerate
generate
if(VAR118==0)
begin
VAR61 VAR149 (
.VAR163(VAR28), .VAR183(VAR3) );
VAR61 VAR42 (
.VAR163(clk), .VAR183(VAR69) );
VAR61 VAR29 (
.VAR163(VAR51), .VAR183(VAR24) );
VAR61 VAR39 (
.VAR163(VAR76), .VAR183(VAR38) );
VAR61 VAR167 (
.VAR163(VAR72), .VAR183(VAR159) );
VAR61 VAR8 (
.VAR163(VAR116), .VAR183(VAR87) );
assign VAR95 = VAR51; assign VAR2 = VAR76; assign VAR34 = VAR72; assign VAR105 = VAR116;
VAR126 #(
.VAR20("VAR121"), .VAR143(8.0), .VAR67(0.0), .VAR106(7.812), .VAR180(8.0), .VAR154(0.5),
.VAR68(0.5),
.VAR60(0.5),
.VAR145(0.5),
.VAR16(0.5),
.VAR80(0.5),
.VAR136(0.5),
.VAR119(0.0),
.VAR86(90.0),
.VAR58(180.0),
.VAR144(270.0),
.VAR41(0.0),
.VAR151(0.0),
.VAR11(0.0),
.VAR179(8), .VAR140(8),
.VAR73(8),
.VAR166(4), .VAR93(1),
.VAR15(1),
.VAR92("VAR174"), .VAR88("VAR174"), .VAR146(1), .VAR26(0.0), .VAR177("VAR174") )
VAR128 (
.VAR85(VAR24), .VAR74(), .VAR10(VAR38), .VAR25(), .VAR9(VAR159), .VAR82(), .VAR172(VAR87), .VAR1(), .VAR91(VAR69), .VAR97(), .VAR131(), .VAR90(), .VAR47(), .VAR75(VAR63), .VAR56(VAR28), .VAR35(1'b0), .VAR129(1'b0), .VAR164(VAR51) );
end
endgenerate
endmodule | gpl-2.0 |
AquarHEAD/stopwatch | src/calc.v | 1,314 | module MODULE1(
input wire clk,
input wire VAR5, VAR13,
input wire VAR9, VAR12,
input wire VAR4, input wire[3:0] VAR6,
output wire[3:0] VAR11,
output wire[7:0] VAR8,
output wire VAR2,
output wire VAR3,
output wire VAR1,
output wire VAR10);
reg[15:0] VAR7; | mit |
jefg89/proyecto_final_prototipado | ProyectoFinal/SOC/synthesis/submodules/SoC_onchip_memory2_0.v | 2,916 | module MODULE1 (
address,
VAR27,
VAR29,
clk,
VAR19,
reset,
VAR17,
write,
VAR1,
VAR11
)
;
parameter VAR3 = "MODULE1.VAR4";
output [ 31: 0] VAR11;
input [ 14: 0] address;
input [ 3: 0] VAR27;
input VAR29;
input clk;
input VAR19;
input reset;
input VAR17;
input write;
input [ 31: 0] VAR1;
wire VAR14;
wire [ 31: 0] VAR11;
wire VAR5;
assign VAR5 = VAR29 & write;
assign VAR14 = VAR19 & ~VAR17;
VAR10 VAR30
(
.VAR32 (address),
.VAR26 (VAR27),
.VAR7 (clk),
.VAR14 (VAR14),
.VAR20 (VAR1),
.VAR6 (VAR11),
.VAR8 (VAR5)
);
VAR30.VAR24 = VAR3,
VAR30.VAR25 = "VAR10",
VAR30.VAR18 = 32768,
VAR30.VAR31 = 32768,
VAR30.VAR21 = "VAR23",
VAR30.VAR28 = "VAR9",
VAR30.VAR34 = "VAR2",
VAR30.VAR12 = "VAR15",
VAR30.VAR16 = 32,
VAR30.VAR33 = 4,
VAR30.VAR22 = 15;
endmodule | gpl-2.0 |
rakeshkadamati/MIPS-32-Bit-Verilog | alu.v | 1,838 | module MODULE1(VAR15,VAR19,VAR12,VAR11,VAR13,VAR2,clk);
input clk;
input [5:0] VAR15, VAR19;
input [31:0] VAR12, VAR11;
output [31:0] VAR13; reg [31:0] VAR13;
output VAR2;
reg VAR2;
wire [31:0] sum, VAR16, VAR3, VAR6;
VAR9 VAR1(VAR12,VAR11,VAR17,sum,1'b0);
VAR4 VAR10(VAR12,VAR11,VAR18,VAR16,1'b0);
VAR14 VAR5(VAR12,VAR11,VAR3);
VAR8 VAR7(VAR12,VAR11,VAR6);
always @(*)
begin
if(VAR15==6'b000000)
begin
if(VAR19==6'b100000) begin
VAR2=1'b0;
VAR13=sum;
VAR2=1'b1;
end
if(VAR19==6'b100010) begin
VAR2=1'b0;
VAR13=VAR16;
VAR2=1'b1;
end
if(VAR19==6'b100100) begin
VAR2=1'b0;
VAR13=VAR3;
VAR2=1'b1;
end
if(VAR19==6'b100101)
begin
VAR2=1'b0;
VAR13=VAR6;
VAR2=1'b1;
end
end
if(VAR15==6'b100011)
begin
VAR2=1'b0;
VAR13=sum;
VAR2=1'b1;
end
if(VAR15==6'b101011)
begin
VAR2=1'b0;
VAR13=sum;
end
if(VAR15==6'b000100)
begin
VAR2=1'b0;
if(VAR16==32'b00000000000000000000000000000000)
begin
VAR13=VAR16;
end
end
end
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.functional.pp.v | 1,386 | module MODULE1( VAR15, VAR14, VAR17, VAR13, VAR6, VAR12 );
input VAR13, VAR17, VAR15;
inout VAR6, VAR12;
output VAR14;
wire VAR16;
not VAR4( VAR16, VAR13 );
wire VAR2;
not VAR11( VAR2, VAR15 );
wire VAR10;
and VAR8( VAR10, VAR16, VAR2 );
wire VAR9;
not VAR1( VAR9, VAR17 );
wire VAR7;
and VAR3( VAR7, VAR9, VAR2 );
or VAR5( VAR14, VAR10, VAR7 );
endmodule | apache-2.0 |
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